1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s
3
4---
5name: umed3_s32_vvv
6legalized: true
7regBankSelected: true
8
9body: |
10  bb.0:
11    liveins: $vgpr0, $vgpr1, $vgpr2
12
13    ; GFX6-LABEL: name: umed3_s32_vvv
14    ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
15    ; GFX6-NEXT: {{  $}}
16    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
17    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
18    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
19    ; GFX6-NEXT: [[V_MED3_U32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_U32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
20    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MED3_U32_e64_]]
21    %0:vgpr(s32) = COPY $vgpr0
22    %1:vgpr(s32) = COPY $vgpr1
23    %2:vgpr(s32) = COPY $vgpr2
24    %3:vgpr(s32) = G_UMAX %0, %1
25    %4:vgpr(s32) = G_UMIN %0, %1
26    %5:vgpr(s32) = G_UMAX %4, %2
27    %6:vgpr(s32) = G_UMIN %3, %5
28    S_ENDPGM 0, implicit %6
29...
30
31---
32
33name: umed3_s32_sss
34legalized: true
35regBankSelected: true
36
37body: |
38  bb.0:
39    liveins: $sgpr0, $sgpr1, $sgpr2
40
41    ; GFX6-LABEL: name: umed3_s32_sss
42    ; GFX6: liveins: $sgpr0, $sgpr1, $sgpr2
43    ; GFX6-NEXT: {{  $}}
44    ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
45    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
46    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
47    ; GFX6-NEXT: [[S_MAX_U32_:%[0-9]+]]:sreg_32 = S_MAX_U32 [[COPY]], [[COPY1]], implicit-def $scc
48    ; GFX6-NEXT: [[S_MIN_U32_:%[0-9]+]]:sreg_32 = S_MIN_U32 [[COPY]], [[COPY1]], implicit-def $scc
49    ; GFX6-NEXT: [[S_MAX_U32_1:%[0-9]+]]:sreg_32 = S_MAX_U32 [[S_MIN_U32_]], [[COPY2]], implicit-def $scc
50    ; GFX6-NEXT: [[S_MIN_U32_1:%[0-9]+]]:sreg_32 = S_MIN_U32 [[S_MAX_U32_]], [[S_MAX_U32_1]], implicit-def $scc
51    ; GFX6-NEXT: S_ENDPGM 0, implicit [[S_MIN_U32_1]]
52    %0:sgpr(s32) = COPY $sgpr0
53    %1:sgpr(s32) = COPY $sgpr1
54    %2:sgpr(s32) = COPY $sgpr2
55    %3:sgpr(s32) = G_UMAX %0, %1
56    %4:sgpr(s32) = G_UMIN %0, %1
57    %5:sgpr(s32) = G_UMAX %4, %2
58    %6:sgpr(s32) = G_UMIN %3, %5
59    S_ENDPGM 0, implicit %6
60...
61
62---
63name: umed3_s32_vvv_multiuse0
64legalized: true
65regBankSelected: true
66
67body: |
68  bb.0:
69    liveins: $vgpr0, $vgpr1, $vgpr2
70
71    ; GFX6-LABEL: name: umed3_s32_vvv_multiuse0
72    ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
73    ; GFX6-NEXT: {{  $}}
74    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
75    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
76    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
77    ; GFX6-NEXT: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec
78    ; GFX6-NEXT: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec
79    ; GFX6-NEXT: [[V_MAX_U32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[V_MIN_U32_e64_]], [[COPY2]], implicit $exec
80    ; GFX6-NEXT: [[V_MIN_U32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[V_MAX_U32_e64_]], [[V_MAX_U32_e64_1]], implicit $exec
81    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MIN_U32_e64_1]], implicit [[V_MAX_U32_e64_]]
82    %0:vgpr(s32) = COPY $vgpr0
83    %1:vgpr(s32) = COPY $vgpr1
84    %2:vgpr(s32) = COPY $vgpr2
85    %3:vgpr(s32) = G_UMAX %0, %1
86    %4:vgpr(s32) = G_UMIN %0, %1
87    %5:vgpr(s32) = G_UMAX %4, %2
88    %6:vgpr(s32) = G_UMIN %3, %5
89    S_ENDPGM 0, implicit %6, implicit %3
90...
91
92---
93name: umed3_s32_vvv_multiuse1
94legalized: true
95regBankSelected: true
96
97body: |
98  bb.0:
99    liveins: $vgpr0, $vgpr1, $vgpr2
100
101    ; GFX6-LABEL: name: umed3_s32_vvv_multiuse1
102    ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
103    ; GFX6-NEXT: {{  $}}
104    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
105    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
106    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
107    ; GFX6-NEXT: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec
108    ; GFX6-NEXT: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec
109    ; GFX6-NEXT: [[V_MAX_U32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[V_MIN_U32_e64_]], [[COPY2]], implicit $exec
110    ; GFX6-NEXT: [[V_MIN_U32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[V_MAX_U32_e64_]], [[V_MAX_U32_e64_1]], implicit $exec
111    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MIN_U32_e64_1]], implicit [[V_MIN_U32_e64_]]
112    %0:vgpr(s32) = COPY $vgpr0
113    %1:vgpr(s32) = COPY $vgpr1
114    %2:vgpr(s32) = COPY $vgpr2
115    %3:vgpr(s32) = G_UMAX %0, %1
116    %4:vgpr(s32) = G_UMIN %0, %1
117    %5:vgpr(s32) = G_UMAX %4, %2
118    %6:vgpr(s32) = G_UMIN %3, %5
119    S_ENDPGM 0, implicit %6, implicit %4
120...
121
122---
123name: umed3_s32_vvv_multiuse2
124legalized: true
125regBankSelected: true
126
127body: |
128  bb.0:
129    liveins: $vgpr0, $vgpr1, $vgpr2
130
131    ; GFX6-LABEL: name: umed3_s32_vvv_multiuse2
132    ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
133    ; GFX6-NEXT: {{  $}}
134    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
135    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
136    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
137    ; GFX6-NEXT: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec
138    ; GFX6-NEXT: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec
139    ; GFX6-NEXT: [[V_MAX_U32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[V_MIN_U32_e64_]], [[COPY2]], implicit $exec
140    ; GFX6-NEXT: [[V_MIN_U32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[V_MAX_U32_e64_]], [[V_MAX_U32_e64_1]], implicit $exec
141    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MIN_U32_e64_1]], implicit [[V_MAX_U32_e64_1]]
142    %0:vgpr(s32) = COPY $vgpr0
143    %1:vgpr(s32) = COPY $vgpr1
144    %2:vgpr(s32) = COPY $vgpr2
145    %3:vgpr(s32) = G_UMAX %0, %1
146    %4:vgpr(s32) = G_UMIN %0, %1
147    %5:vgpr(s32) = G_UMAX %4, %2
148    %6:vgpr(s32) = G_UMIN %3, %5
149    S_ENDPGM 0, implicit %6, implicit %5
150...
151