1; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck %s
2
3@lds0 = addrspace(3) global [512 x float] undef
4@lds1 = addrspace(3) global [256 x float] undef
5@lds2 = addrspace(3) global [4096 x float] undef
6@lds3 = addrspace(3) global [67 x i8] undef
7
8@dynamic_shared0 = external addrspace(3) global [0 x float]
9@dynamic_shared1 = external addrspace(3) global [0 x double]
10@dynamic_shared2 = external addrspace(3) global [0 x double], align 4
11@dynamic_shared3 = external addrspace(3) global [0 x double], align 16
12
13; CHECK-LABEL: {{^}}dynamic_shared_array_0:
14; CHECK: v_add_u32_e32 v{{[0-9]+}}, 0x800, v{{[0-9]+}}
15define amdgpu_kernel void @dynamic_shared_array_0(float addrspace(1)* %out) {
16  %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
17  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %tid.x
18  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
19  %arrayidx1 = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
20  store float %val0, float addrspace(3)* %arrayidx1, align 4
21  ret void
22}
23
24; CHECK-LABEL: {{^}}dynamic_shared_array_1:
25; CHECK: v_lshlrev_b32_e32 {{v[0-9]+}}, 2, {{v[0-9]+}}
26; CHECK: v_lshlrev_b32_e32 {{v[0-9]+}}, 2, {{v[0-9]+}}
27; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
28; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0xc00, [[IDX]]
29define amdgpu_kernel void @dynamic_shared_array_1(float addrspace(1)* %out, i32 %cond) {
30entry:
31  %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
32  %idx.0 = add nsw i32 %tid.x, 64
33  %tmp = icmp eq i32 %cond, 0
34  br i1 %tmp, label %if, label %else
35
36if:                                               ; preds = %entry
37  %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0
38  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
39  br label %endif
40
41else:                                             ; preds = %entry
42  %arrayidx1 = getelementptr inbounds [256 x float], [256 x float] addrspace(3)* @lds1, i32 0, i32 %idx.0
43  %val1 = load float, float addrspace(3)* %arrayidx1, align 4
44  br label %endif
45
46endif:                                            ; preds = %else, %if
47  %val = phi float [ %val0, %if ], [ %val1, %else ]
48  %arrayidx = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
49  store float %val, float addrspace(3)* %arrayidx, align 4
50  ret void
51}
52
53; CHECK-LABEL: {{^}}dynamic_shared_array_2:
54; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
55; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x4000, [[IDX]]
56define amdgpu_kernel void @dynamic_shared_array_2(i32 %idx) {
57  %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
58  %vidx = add i32 %tid.x, %idx
59  %arrayidx0 = getelementptr inbounds [4096 x float], [4096 x float] addrspace(3)* @lds2, i32 0, i32 %vidx
60  %val0 = load float, float addrspace(3)* %arrayidx0, align 4
61  %arrayidx1 = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
62  store float %val0, float addrspace(3)* %arrayidx1, align 4
63  ret void
64}
65
66; The offset to the dynamic shared memory array should be aligned on the type
67; specified.
68; CHECK-LABEL: {{^}}dynamic_shared_array_3:
69; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
70; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x44, [[IDX]]
71define amdgpu_kernel void @dynamic_shared_array_3(i32 %idx) {
72  %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
73  %vidx = add i32 %tid.x, %idx
74  %arrayidx0 = getelementptr inbounds [67 x i8], [67 x i8] addrspace(3)* @lds3, i32 0, i32 %vidx
75  %val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
76  %val1 = uitofp i8 %val0 to float
77  %arrayidx1 = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
78  store float %val1, float addrspace(3)* %arrayidx1, align 4
79  ret void
80}
81
82; The offset to the dynamic shared memory array should be aligned on the
83; maximal one.
84; CHECK-LABEL: {{^}}dynamic_shared_array_4:
85; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
86; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x48, [[IDX]]
87define amdgpu_kernel void @dynamic_shared_array_4(i32 %idx) {
88  %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
89  %vidx = add i32 %tid.x, %idx
90  %arrayidx0 = getelementptr inbounds [67 x i8], [67 x i8] addrspace(3)* @lds3, i32 0, i32 %vidx
91  %val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
92  %val1 = uitofp i8 %val0 to float
93  %val2 = uitofp i8 %val0 to double
94  %arrayidx1 = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
95  store float %val1, float addrspace(3)* %arrayidx1, align 4
96  %arrayidx2 = getelementptr inbounds [0 x double], [0 x double] addrspace(3)* @dynamic_shared1, i32 0, i32 %tid.x
97  store double %val2, double addrspace(3)* %arrayidx2, align 4
98  ret void
99}
100
101; Honor the explicit alignment from the specified variable.
102; CHECK-LABEL: {{^}}dynamic_shared_array_5:
103; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
104; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x44, [[IDX]]
105define amdgpu_kernel void @dynamic_shared_array_5(i32 %idx) {
106  %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
107  %vidx = add i32 %tid.x, %idx
108  %arrayidx0 = getelementptr inbounds [67 x i8], [67 x i8] addrspace(3)* @lds3, i32 0, i32 %vidx
109  %val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
110  %val1 = uitofp i8 %val0 to float
111  %val2 = uitofp i8 %val0 to double
112  %arrayidx1 = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
113  store float %val1, float addrspace(3)* %arrayidx1, align 4
114  %arrayidx2 = getelementptr inbounds [0 x double], [0 x double] addrspace(3)* @dynamic_shared2, i32 0, i32 %tid.x
115  store double %val2, double addrspace(3)* %arrayidx2, align 4
116  ret void
117}
118
119; Honor the explicit alignment from the specified variable.
120; CHECK-LABEL: {{^}}dynamic_shared_array_6:
121; CHECK: v_lshlrev_b32_e32 [[IDX:v[0-9]+]], 2, {{v[0-9]+}}
122; CHECK: v_add_u32_e32 {{v[0-9]+}}, 0x50, [[IDX]]
123define amdgpu_kernel void @dynamic_shared_array_6(i32 %idx) {
124  %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x()
125  %vidx = add i32 %tid.x, %idx
126  %arrayidx0 = getelementptr inbounds [67 x i8], [67 x i8] addrspace(3)* @lds3, i32 0, i32 %vidx
127  %val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
128  %val1 = uitofp i8 %val0 to float
129  %val2 = uitofp i8 %val0 to double
130  %arrayidx1 = getelementptr inbounds [0 x float], [0 x float] addrspace(3)* @dynamic_shared0, i32 0, i32 %tid.x
131  store float %val1, float addrspace(3)* %arrayidx1, align 4
132  %arrayidx2 = getelementptr inbounds [0 x double], [0 x double] addrspace(3)* @dynamic_shared3, i32 0, i32 %tid.x
133  store double %val2, double addrspace(3)* %arrayidx2, align 4
134  ret void
135}
136
137declare i32 @llvm.amdgcn.workitem.id.x()
138