1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s
3
4declare { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>)
5
6define <vscale x 2 x i8> @smulo_nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y) {
7; CHECK-LABEL: smulo_nxv2i8:
8; CHECK:       // %bb.0:
9; CHECK-NEXT:    ptrue p0.d
10; CHECK-NEXT:    sxtb z1.d, p0/m, z1.d
11; CHECK-NEXT:    sxtb z0.d, p0/m, z0.d
12; CHECK-NEXT:    movprfx z2, z0
13; CHECK-NEXT:    smulh z2.d, p0/m, z2.d, z1.d
14; CHECK-NEXT:    mul z0.d, p0/m, z0.d, z1.d
15; CHECK-NEXT:    asr z1.d, z0.d, #63
16; CHECK-NEXT:    movprfx z3, z0
17; CHECK-NEXT:    sxtb z3.d, p0/m, z0.d
18; CHECK-NEXT:    cmpne p1.d, p0/z, z2.d, z1.d
19; CHECK-NEXT:    cmpne p0.d, p0/z, z3.d, z0.d
20; CHECK-NEXT:    sel p0.b, p0, p0.b, p1.b
21; CHECK-NEXT:    mov z0.d, p0/m, #0 // =0x0
22; CHECK-NEXT:    ret
23  %a = call { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y)
24  %b = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i1> } %a, 0
25  %c = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i1> } %a, 1
26  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i8> zeroinitializer, <vscale x 2 x i8> %b
27  ret <vscale x 2 x i8> %d
28}
29
30declare { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>)
31
32define <vscale x 4 x i8> @smulo_nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y) {
33; CHECK-LABEL: smulo_nxv4i8:
34; CHECK:       // %bb.0:
35; CHECK-NEXT:    ptrue p0.s
36; CHECK-NEXT:    sxtb z1.s, p0/m, z1.s
37; CHECK-NEXT:    sxtb z0.s, p0/m, z0.s
38; CHECK-NEXT:    movprfx z2, z0
39; CHECK-NEXT:    smulh z2.s, p0/m, z2.s, z1.s
40; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z1.s
41; CHECK-NEXT:    asr z1.s, z0.s, #31
42; CHECK-NEXT:    movprfx z3, z0
43; CHECK-NEXT:    sxtb z3.s, p0/m, z0.s
44; CHECK-NEXT:    cmpne p1.s, p0/z, z2.s, z1.s
45; CHECK-NEXT:    cmpne p0.s, p0/z, z3.s, z0.s
46; CHECK-NEXT:    sel p0.b, p0, p0.b, p1.b
47; CHECK-NEXT:    mov z0.s, p0/m, #0 // =0x0
48; CHECK-NEXT:    ret
49  %a = call { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y)
50  %b = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i1> } %a, 0
51  %c = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i1> } %a, 1
52  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i8> zeroinitializer, <vscale x 4 x i8> %b
53  ret <vscale x 4 x i8> %d
54}
55
56declare { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>)
57
58define <vscale x 8 x i8> @smulo_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
59; CHECK-LABEL: smulo_nxv8i8:
60; CHECK:       // %bb.0:
61; CHECK-NEXT:    ptrue p0.h
62; CHECK-NEXT:    sxtb z1.h, p0/m, z1.h
63; CHECK-NEXT:    sxtb z0.h, p0/m, z0.h
64; CHECK-NEXT:    movprfx z2, z0
65; CHECK-NEXT:    smulh z2.h, p0/m, z2.h, z1.h
66; CHECK-NEXT:    mul z0.h, p0/m, z0.h, z1.h
67; CHECK-NEXT:    asr z1.h, z0.h, #15
68; CHECK-NEXT:    movprfx z3, z0
69; CHECK-NEXT:    sxtb z3.h, p0/m, z0.h
70; CHECK-NEXT:    cmpne p1.h, p0/z, z2.h, z1.h
71; CHECK-NEXT:    cmpne p0.h, p0/z, z3.h, z0.h
72; CHECK-NEXT:    sel p0.b, p0, p0.b, p1.b
73; CHECK-NEXT:    mov z0.h, p0/m, #0 // =0x0
74; CHECK-NEXT:    ret
75  %a = call { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y)
76  %b = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i1> } %a, 0
77  %c = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i1> } %a, 1
78  %d = select <vscale x 8 x i1> %c, <vscale x 8 x i8> zeroinitializer, <vscale x 8 x i8> %b
79  ret <vscale x 8 x i8> %d
80}
81
82declare { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
83
84define <vscale x 16 x i8> @smulo_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) {
85; CHECK-LABEL: smulo_nxv16i8:
86; CHECK:       // %bb.0:
87; CHECK-NEXT:    ptrue p0.b
88; CHECK-NEXT:    movprfx z2, z0
89; CHECK-NEXT:    mul z2.b, p0/m, z2.b, z1.b
90; CHECK-NEXT:    smulh z0.b, p0/m, z0.b, z1.b
91; CHECK-NEXT:    asr z1.b, z2.b, #7
92; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, z1.b
93; CHECK-NEXT:    mov z2.b, p0/m, #0 // =0x0
94; CHECK-NEXT:    mov z0.d, z2.d
95; CHECK-NEXT:    ret
96  %a = call { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
97  %b = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i1> } %a, 0
98  %c = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i1> } %a, 1
99  %d = select <vscale x 16 x i1> %c, <vscale x 16 x i8> zeroinitializer, <vscale x 16 x i8> %b
100  ret <vscale x 16 x i8> %d
101}
102
103declare { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>)
104
105define <vscale x 32 x i8> @smulo_nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y) {
106; CHECK-LABEL: smulo_nxv32i8:
107; CHECK:       // %bb.0:
108; CHECK-NEXT:    ptrue p0.b
109; CHECK-NEXT:    movprfx z4, z1
110; CHECK-NEXT:    smulh z4.b, p0/m, z4.b, z3.b
111; CHECK-NEXT:    mul z1.b, p0/m, z1.b, z3.b
112; CHECK-NEXT:    movprfx z3, z0
113; CHECK-NEXT:    mul z3.b, p0/m, z3.b, z2.b
114; CHECK-NEXT:    asr z5.b, z1.b, #7
115; CHECK-NEXT:    smulh z0.b, p0/m, z0.b, z2.b
116; CHECK-NEXT:    asr z2.b, z3.b, #7
117; CHECK-NEXT:    cmpne p1.b, p0/z, z4.b, z5.b
118; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, z2.b
119; CHECK-NEXT:    mov z1.b, p1/m, #0 // =0x0
120; CHECK-NEXT:    mov z3.b, p0/m, #0 // =0x0
121; CHECK-NEXT:    mov z0.d, z3.d
122; CHECK-NEXT:    ret
123  %a = call { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y)
124  %b = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i1> } %a, 0
125  %c = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i1> } %a, 1
126  %d = select <vscale x 32 x i1> %c, <vscale x 32 x i8> zeroinitializer, <vscale x 32 x i8> %b
127  ret <vscale x 32 x i8> %d
128}
129
130declare { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.smul.with.overflow.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>)
131
132define <vscale x 64 x i8> @smulo_nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y) {
133; CHECK-LABEL: smulo_nxv64i8:
134; CHECK:       // %bb.0:
135; CHECK-NEXT:    ptrue p0.b
136; CHECK-NEXT:    movprfx z24, z3
137; CHECK-NEXT:    smulh z24.b, p0/m, z24.b, z7.b
138; CHECK-NEXT:    mul z3.b, p0/m, z3.b, z7.b
139; CHECK-NEXT:    movprfx z7, z2
140; CHECK-NEXT:    mul z7.b, p0/m, z7.b, z6.b
141; CHECK-NEXT:    smulh z2.b, p0/m, z2.b, z6.b
142; CHECK-NEXT:    asr z6.b, z7.b, #7
143; CHECK-NEXT:    cmpne p2.b, p0/z, z2.b, z6.b
144; CHECK-NEXT:    movprfx z6, z1
145; CHECK-NEXT:    smulh z6.b, p0/m, z6.b, z5.b
146; CHECK-NEXT:    mul z1.b, p0/m, z1.b, z5.b
147; CHECK-NEXT:    asr z25.b, z3.b, #7
148; CHECK-NEXT:    asr z5.b, z1.b, #7
149; CHECK-NEXT:    movprfx z2, z0
150; CHECK-NEXT:    mul z2.b, p0/m, z2.b, z4.b
151; CHECK-NEXT:    smulh z0.b, p0/m, z0.b, z4.b
152; CHECK-NEXT:    asr z4.b, z2.b, #7
153; CHECK-NEXT:    cmpne p1.b, p0/z, z24.b, z25.b
154; CHECK-NEXT:    cmpne p3.b, p0/z, z6.b, z5.b
155; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, z4.b
156; CHECK-NEXT:    mov z7.b, p2/m, #0 // =0x0
157; CHECK-NEXT:    mov z2.b, p0/m, #0 // =0x0
158; CHECK-NEXT:    mov z1.b, p3/m, #0 // =0x0
159; CHECK-NEXT:    mov z3.b, p1/m, #0 // =0x0
160; CHECK-NEXT:    mov z0.d, z2.d
161; CHECK-NEXT:    mov z2.d, z7.d
162; CHECK-NEXT:    ret
163  %a = call { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.smul.with.overflow.nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y)
164  %b = extractvalue { <vscale x 64 x i8>, <vscale x 64 x i1> } %a, 0
165  %c = extractvalue { <vscale x 64 x i8>, <vscale x 64 x i1> } %a, 1
166  %d = select <vscale x 64 x i1> %c, <vscale x 64 x i8> zeroinitializer, <vscale x 64 x i8> %b
167  ret <vscale x 64 x i8> %d
168}
169
170declare { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>)
171
172define <vscale x 2 x i16> @smulo_nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y) {
173; CHECK-LABEL: smulo_nxv2i16:
174; CHECK:       // %bb.0:
175; CHECK-NEXT:    ptrue p0.d
176; CHECK-NEXT:    sxth z1.d, p0/m, z1.d
177; CHECK-NEXT:    sxth z0.d, p0/m, z0.d
178; CHECK-NEXT:    movprfx z2, z0
179; CHECK-NEXT:    smulh z2.d, p0/m, z2.d, z1.d
180; CHECK-NEXT:    mul z0.d, p0/m, z0.d, z1.d
181; CHECK-NEXT:    asr z1.d, z0.d, #63
182; CHECK-NEXT:    movprfx z3, z0
183; CHECK-NEXT:    sxth z3.d, p0/m, z0.d
184; CHECK-NEXT:    cmpne p1.d, p0/z, z2.d, z1.d
185; CHECK-NEXT:    cmpne p0.d, p0/z, z3.d, z0.d
186; CHECK-NEXT:    sel p0.b, p0, p0.b, p1.b
187; CHECK-NEXT:    mov z0.d, p0/m, #0 // =0x0
188; CHECK-NEXT:    ret
189  %a = call { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y)
190  %b = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i1> } %a, 0
191  %c = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i1> } %a, 1
192  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i16> zeroinitializer, <vscale x 2 x i16> %b
193  ret <vscale x 2 x i16> %d
194}
195
196declare { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>)
197
198define <vscale x 4 x i16> @smulo_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y) {
199; CHECK-LABEL: smulo_nxv4i16:
200; CHECK:       // %bb.0:
201; CHECK-NEXT:    ptrue p0.s
202; CHECK-NEXT:    sxth z1.s, p0/m, z1.s
203; CHECK-NEXT:    sxth z0.s, p0/m, z0.s
204; CHECK-NEXT:    movprfx z2, z0
205; CHECK-NEXT:    smulh z2.s, p0/m, z2.s, z1.s
206; CHECK-NEXT:    mul z0.s, p0/m, z0.s, z1.s
207; CHECK-NEXT:    asr z1.s, z0.s, #31
208; CHECK-NEXT:    movprfx z3, z0
209; CHECK-NEXT:    sxth z3.s, p0/m, z0.s
210; CHECK-NEXT:    cmpne p1.s, p0/z, z2.s, z1.s
211; CHECK-NEXT:    cmpne p0.s, p0/z, z3.s, z0.s
212; CHECK-NEXT:    sel p0.b, p0, p0.b, p1.b
213; CHECK-NEXT:    mov z0.s, p0/m, #0 // =0x0
214; CHECK-NEXT:    ret
215  %a = call { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y)
216  %b = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i1> } %a, 0
217  %c = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i1> } %a, 1
218  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i16> zeroinitializer, <vscale x 4 x i16> %b
219  ret <vscale x 4 x i16> %d
220}
221
222declare { <vscale x 8 x i16>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
223
224define <vscale x 8 x i16> @smulo_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
225; CHECK-LABEL: smulo_nxv8i16:
226; CHECK:       // %bb.0:
227; CHECK-NEXT:    ptrue p0.h
228; CHECK-NEXT:    movprfx z2, z0
229; CHECK-NEXT:    mul z2.h, p0/m, z2.h, z1.h
230; CHECK-NEXT:    smulh z0.h, p0/m, z0.h, z1.h
231; CHECK-NEXT:    asr z1.h, z2.h, #15
232; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, z1.h
233; CHECK-NEXT:    mov z2.h, p0/m, #0 // =0x0
234; CHECK-NEXT:    mov z0.d, z2.d
235; CHECK-NEXT:    ret
236  %a = call { <vscale x 8 x i16>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)
237  %b = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i1> } %a, 0
238  %c = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i1> } %a, 1
239  %d = select <vscale x 8 x i1> %c, <vscale x 8 x i16> zeroinitializer, <vscale x 8 x i16> %b
240  ret <vscale x 8 x i16> %d
241}
242
243declare { <vscale x 16 x i16>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>)
244
245define <vscale x 16 x i16> @smulo_nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y) {
246; CHECK-LABEL: smulo_nxv16i16:
247; CHECK:       // %bb.0:
248; CHECK-NEXT:    ptrue p0.h
249; CHECK-NEXT:    movprfx z4, z1
250; CHECK-NEXT:    smulh z4.h, p0/m, z4.h, z3.h
251; CHECK-NEXT:    mul z1.h, p0/m, z1.h, z3.h
252; CHECK-NEXT:    movprfx z3, z0
253; CHECK-NEXT:    mul z3.h, p0/m, z3.h, z2.h
254; CHECK-NEXT:    asr z5.h, z1.h, #15
255; CHECK-NEXT:    smulh z0.h, p0/m, z0.h, z2.h
256; CHECK-NEXT:    asr z2.h, z3.h, #15
257; CHECK-NEXT:    cmpne p1.h, p0/z, z4.h, z5.h
258; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, z2.h
259; CHECK-NEXT:    mov z1.h, p1/m, #0 // =0x0
260; CHECK-NEXT:    mov z3.h, p0/m, #0 // =0x0
261; CHECK-NEXT:    mov z0.d, z3.d
262; CHECK-NEXT:    ret
263  %a = call { <vscale x 16 x i16>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y)
264  %b = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i1> } %a, 0
265  %c = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i1> } %a, 1
266  %d = select <vscale x 16 x i1> %c, <vscale x 16 x i16> zeroinitializer, <vscale x 16 x i16> %b
267  ret <vscale x 16 x i16> %d
268}
269
270declare { <vscale x 32 x i16>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>)
271
272define <vscale x 32 x i16> @smulo_nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y) {
273; CHECK-LABEL: smulo_nxv32i16:
274; CHECK:       // %bb.0:
275; CHECK-NEXT:    ptrue p0.h
276; CHECK-NEXT:    movprfx z24, z3
277; CHECK-NEXT:    smulh z24.h, p0/m, z24.h, z7.h
278; CHECK-NEXT:    mul z3.h, p0/m, z3.h, z7.h
279; CHECK-NEXT:    movprfx z7, z2
280; CHECK-NEXT:    mul z7.h, p0/m, z7.h, z6.h
281; CHECK-NEXT:    smulh z2.h, p0/m, z2.h, z6.h
282; CHECK-NEXT:    asr z6.h, z7.h, #15
283; CHECK-NEXT:    cmpne p2.h, p0/z, z2.h, z6.h
284; CHECK-NEXT:    movprfx z6, z1
285; CHECK-NEXT:    smulh z6.h, p0/m, z6.h, z5.h
286; CHECK-NEXT:    mul z1.h, p0/m, z1.h, z5.h
287; CHECK-NEXT:    asr z25.h, z3.h, #15
288; CHECK-NEXT:    asr z5.h, z1.h, #15
289; CHECK-NEXT:    movprfx z2, z0
290; CHECK-NEXT:    mul z2.h, p0/m, z2.h, z4.h
291; CHECK-NEXT:    smulh z0.h, p0/m, z0.h, z4.h
292; CHECK-NEXT:    asr z4.h, z2.h, #15
293; CHECK-NEXT:    cmpne p1.h, p0/z, z24.h, z25.h
294; CHECK-NEXT:    cmpne p3.h, p0/z, z6.h, z5.h
295; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, z4.h
296; CHECK-NEXT:    mov z7.h, p2/m, #0 // =0x0
297; CHECK-NEXT:    mov z2.h, p0/m, #0 // =0x0
298; CHECK-NEXT:    mov z1.h, p3/m, #0 // =0x0
299; CHECK-NEXT:    mov z3.h, p1/m, #0 // =0x0
300; CHECK-NEXT:    mov z0.d, z2.d
301; CHECK-NEXT:    mov z2.d, z7.d
302; CHECK-NEXT:    ret
303  %a = call { <vscale x 32 x i16>, <vscale x 32 x i1> } @llvm.smul.with.overflow.nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y)
304  %b = extractvalue { <vscale x 32 x i16>, <vscale x 32 x i1> } %a, 0
305  %c = extractvalue { <vscale x 32 x i16>, <vscale x 32 x i1> } %a, 1
306  %d = select <vscale x 32 x i1> %c, <vscale x 32 x i16> zeroinitializer, <vscale x 32 x i16> %b
307  ret <vscale x 32 x i16> %d
308}
309
310declare { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
311
312define <vscale x 2 x i32> @smulo_nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {
313; CHECK-LABEL: smulo_nxv2i32:
314; CHECK:       // %bb.0:
315; CHECK-NEXT:    ptrue p0.d
316; CHECK-NEXT:    sxtw z1.d, p0/m, z1.d
317; CHECK-NEXT:    sxtw z0.d, p0/m, z0.d
318; CHECK-NEXT:    movprfx z2, z0
319; CHECK-NEXT:    smulh z2.d, p0/m, z2.d, z1.d
320; CHECK-NEXT:    mul z0.d, p0/m, z0.d, z1.d
321; CHECK-NEXT:    asr z1.d, z0.d, #63
322; CHECK-NEXT:    movprfx z3, z0
323; CHECK-NEXT:    sxtw z3.d, p0/m, z0.d
324; CHECK-NEXT:    cmpne p1.d, p0/z, z2.d, z1.d
325; CHECK-NEXT:    cmpne p0.d, p0/z, z3.d, z0.d
326; CHECK-NEXT:    sel p0.b, p0, p0.b, p1.b
327; CHECK-NEXT:    mov z0.d, p0/m, #0 // =0x0
328; CHECK-NEXT:    ret
329  %a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y)
330  %b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0
331  %c = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 1
332  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %b
333  ret <vscale x 2 x i32> %d
334}
335
336declare { <vscale x 4 x i32>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
337
338define <vscale x 4 x i32> @smulo_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
339; CHECK-LABEL: smulo_nxv4i32:
340; CHECK:       // %bb.0:
341; CHECK-NEXT:    ptrue p0.s
342; CHECK-NEXT:    movprfx z2, z0
343; CHECK-NEXT:    mul z2.s, p0/m, z2.s, z1.s
344; CHECK-NEXT:    smulh z0.s, p0/m, z0.s, z1.s
345; CHECK-NEXT:    asr z1.s, z2.s, #31
346; CHECK-NEXT:    cmpne p0.s, p0/z, z0.s, z1.s
347; CHECK-NEXT:    mov z2.s, p0/m, #0 // =0x0
348; CHECK-NEXT:    mov z0.d, z2.d
349; CHECK-NEXT:    ret
350  %a = call { <vscale x 4 x i32>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)
351  %b = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i1> } %a, 0
352  %c = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i1> } %a, 1
353  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> %b
354  ret <vscale x 4 x i32> %d
355}
356
357declare { <vscale x 8 x i32>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
358
359define <vscale x 8 x i32> @smulo_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {
360; CHECK-LABEL: smulo_nxv8i32:
361; CHECK:       // %bb.0:
362; CHECK-NEXT:    ptrue p0.s
363; CHECK-NEXT:    movprfx z4, z1
364; CHECK-NEXT:    smulh z4.s, p0/m, z4.s, z3.s
365; CHECK-NEXT:    mul z1.s, p0/m, z1.s, z3.s
366; CHECK-NEXT:    movprfx z3, z0
367; CHECK-NEXT:    mul z3.s, p0/m, z3.s, z2.s
368; CHECK-NEXT:    asr z5.s, z1.s, #31
369; CHECK-NEXT:    smulh z0.s, p0/m, z0.s, z2.s
370; CHECK-NEXT:    asr z2.s, z3.s, #31
371; CHECK-NEXT:    cmpne p1.s, p0/z, z4.s, z5.s
372; CHECK-NEXT:    cmpne p0.s, p0/z, z0.s, z2.s
373; CHECK-NEXT:    mov z1.s, p1/m, #0 // =0x0
374; CHECK-NEXT:    mov z3.s, p0/m, #0 // =0x0
375; CHECK-NEXT:    mov z0.d, z3.d
376; CHECK-NEXT:    ret
377  %a = call { <vscale x 8 x i32>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y)
378  %b = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i1> } %a, 0
379  %c = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i1> } %a, 1
380  %d = select <vscale x 8 x i1> %c, <vscale x 8 x i32> zeroinitializer, <vscale x 8 x i32> %b
381  ret <vscale x 8 x i32> %d
382}
383
384declare { <vscale x 16 x i32>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
385
386define <vscale x 16 x i32> @smulo_nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y) {
387; CHECK-LABEL: smulo_nxv16i32:
388; CHECK:       // %bb.0:
389; CHECK-NEXT:    ptrue p0.s
390; CHECK-NEXT:    movprfx z24, z3
391; CHECK-NEXT:    smulh z24.s, p0/m, z24.s, z7.s
392; CHECK-NEXT:    mul z3.s, p0/m, z3.s, z7.s
393; CHECK-NEXT:    movprfx z7, z2
394; CHECK-NEXT:    mul z7.s, p0/m, z7.s, z6.s
395; CHECK-NEXT:    smulh z2.s, p0/m, z2.s, z6.s
396; CHECK-NEXT:    asr z6.s, z7.s, #31
397; CHECK-NEXT:    cmpne p2.s, p0/z, z2.s, z6.s
398; CHECK-NEXT:    movprfx z6, z1
399; CHECK-NEXT:    smulh z6.s, p0/m, z6.s, z5.s
400; CHECK-NEXT:    mul z1.s, p0/m, z1.s, z5.s
401; CHECK-NEXT:    asr z25.s, z3.s, #31
402; CHECK-NEXT:    asr z5.s, z1.s, #31
403; CHECK-NEXT:    movprfx z2, z0
404; CHECK-NEXT:    mul z2.s, p0/m, z2.s, z4.s
405; CHECK-NEXT:    smulh z0.s, p0/m, z0.s, z4.s
406; CHECK-NEXT:    asr z4.s, z2.s, #31
407; CHECK-NEXT:    cmpne p1.s, p0/z, z24.s, z25.s
408; CHECK-NEXT:    cmpne p3.s, p0/z, z6.s, z5.s
409; CHECK-NEXT:    cmpne p0.s, p0/z, z0.s, z4.s
410; CHECK-NEXT:    mov z7.s, p2/m, #0 // =0x0
411; CHECK-NEXT:    mov z2.s, p0/m, #0 // =0x0
412; CHECK-NEXT:    mov z1.s, p3/m, #0 // =0x0
413; CHECK-NEXT:    mov z3.s, p1/m, #0 // =0x0
414; CHECK-NEXT:    mov z0.d, z2.d
415; CHECK-NEXT:    mov z2.d, z7.d
416; CHECK-NEXT:    ret
417  %a = call { <vscale x 16 x i32>, <vscale x 16 x i1> } @llvm.smul.with.overflow.nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y)
418  %b = extractvalue { <vscale x 16 x i32>, <vscale x 16 x i1> } %a, 0
419  %c = extractvalue { <vscale x 16 x i32>, <vscale x 16 x i1> } %a, 1
420  %d = select <vscale x 16 x i1> %c, <vscale x 16 x i32> zeroinitializer, <vscale x 16 x i32> %b
421  ret <vscale x 16 x i32> %d
422}
423
424declare { <vscale x 2 x i64>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
425
426define <vscale x 2 x i64> @smulo_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {
427; CHECK-LABEL: smulo_nxv2i64:
428; CHECK:       // %bb.0:
429; CHECK-NEXT:    ptrue p0.d
430; CHECK-NEXT:    movprfx z2, z0
431; CHECK-NEXT:    mul z2.d, p0/m, z2.d, z1.d
432; CHECK-NEXT:    smulh z0.d, p0/m, z0.d, z1.d
433; CHECK-NEXT:    asr z1.d, z2.d, #63
434; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, z1.d
435; CHECK-NEXT:    mov z2.d, p0/m, #0 // =0x0
436; CHECK-NEXT:    mov z0.d, z2.d
437; CHECK-NEXT:    ret
438  %a = call { <vscale x 2 x i64>, <vscale x 2 x i1> } @llvm.smul.with.overflow.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y)
439  %b = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i1> } %a, 0
440  %c = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i1> } %a, 1
441  %d = select <vscale x 2 x i1> %c, <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i64> %b
442  ret <vscale x 2 x i64> %d
443}
444
445declare { <vscale x 4 x i64>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
446
447define <vscale x 4 x i64> @smulo_nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y) {
448; CHECK-LABEL: smulo_nxv4i64:
449; CHECK:       // %bb.0:
450; CHECK-NEXT:    ptrue p0.d
451; CHECK-NEXT:    movprfx z4, z1
452; CHECK-NEXT:    smulh z4.d, p0/m, z4.d, z3.d
453; CHECK-NEXT:    mul z1.d, p0/m, z1.d, z3.d
454; CHECK-NEXT:    movprfx z3, z0
455; CHECK-NEXT:    mul z3.d, p0/m, z3.d, z2.d
456; CHECK-NEXT:    asr z5.d, z1.d, #63
457; CHECK-NEXT:    smulh z0.d, p0/m, z0.d, z2.d
458; CHECK-NEXT:    asr z2.d, z3.d, #63
459; CHECK-NEXT:    cmpne p1.d, p0/z, z4.d, z5.d
460; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, z2.d
461; CHECK-NEXT:    mov z1.d, p1/m, #0 // =0x0
462; CHECK-NEXT:    mov z3.d, p0/m, #0 // =0x0
463; CHECK-NEXT:    mov z0.d, z3.d
464; CHECK-NEXT:    ret
465  %a = call { <vscale x 4 x i64>, <vscale x 4 x i1> } @llvm.smul.with.overflow.nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y)
466  %b = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i1> } %a, 0
467  %c = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i1> } %a, 1
468  %d = select <vscale x 4 x i1> %c, <vscale x 4 x i64> zeroinitializer, <vscale x 4 x i64> %b
469  ret <vscale x 4 x i64> %d
470}
471
472declare { <vscale x 8 x i64>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
473
474define <vscale x 8 x i64> @smulo_nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y) {
475; CHECK-LABEL: smulo_nxv8i64:
476; CHECK:       // %bb.0:
477; CHECK-NEXT:    ptrue p0.d
478; CHECK-NEXT:    movprfx z24, z3
479; CHECK-NEXT:    smulh z24.d, p0/m, z24.d, z7.d
480; CHECK-NEXT:    mul z3.d, p0/m, z3.d, z7.d
481; CHECK-NEXT:    movprfx z7, z2
482; CHECK-NEXT:    mul z7.d, p0/m, z7.d, z6.d
483; CHECK-NEXT:    smulh z2.d, p0/m, z2.d, z6.d
484; CHECK-NEXT:    asr z6.d, z7.d, #63
485; CHECK-NEXT:    cmpne p2.d, p0/z, z2.d, z6.d
486; CHECK-NEXT:    movprfx z6, z1
487; CHECK-NEXT:    smulh z6.d, p0/m, z6.d, z5.d
488; CHECK-NEXT:    mul z1.d, p0/m, z1.d, z5.d
489; CHECK-NEXT:    asr z25.d, z3.d, #63
490; CHECK-NEXT:    asr z5.d, z1.d, #63
491; CHECK-NEXT:    movprfx z2, z0
492; CHECK-NEXT:    mul z2.d, p0/m, z2.d, z4.d
493; CHECK-NEXT:    smulh z0.d, p0/m, z0.d, z4.d
494; CHECK-NEXT:    asr z4.d, z2.d, #63
495; CHECK-NEXT:    cmpne p1.d, p0/z, z24.d, z25.d
496; CHECK-NEXT:    cmpne p3.d, p0/z, z6.d, z5.d
497; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, z4.d
498; CHECK-NEXT:    mov z7.d, p2/m, #0 // =0x0
499; CHECK-NEXT:    mov z2.d, p0/m, #0 // =0x0
500; CHECK-NEXT:    mov z1.d, p3/m, #0 // =0x0
501; CHECK-NEXT:    mov z3.d, p1/m, #0 // =0x0
502; CHECK-NEXT:    mov z0.d, z2.d
503; CHECK-NEXT:    mov z2.d, z7.d
504; CHECK-NEXT:    ret
505  %a = call { <vscale x 8 x i64>, <vscale x 8 x i1> } @llvm.smul.with.overflow.nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y)
506  %b = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i1> } %a, 0
507  %c = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i1> } %a, 1
508  %d = select <vscale x 8 x i1> %c, <vscale x 8 x i64> zeroinitializer, <vscale x 8 x i64> %b
509  ret <vscale x 8 x i64> %d
510}
511