1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64 -mattr=+v8.5a,+rand %s -o - | FileCheck %s
3
4define  i32 @rndr(i64* %__addr) {
5; CHECK-LABEL: rndr:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    mrs x10, RNDR
8; CHECK-NEXT:    mov x9, x0
9; CHECK-NEXT:    cset w8, eq
10; CHECK-NEXT:    and w8, w8, #0x1
11; CHECK-NEXT:    mov w0, w8
12; CHECK-NEXT:    str x10, [x9]
13; CHECK-NEXT:    ret
14  %1 = tail call { i64, i1 } @llvm.aarch64.rndr()
15  %2 = extractvalue { i64, i1 } %1, 0
16  %3 = extractvalue { i64, i1 } %1, 1
17  store i64 %2, i64* %__addr, align 8
18  %4 = zext i1 %3 to i32
19  ret i32 %4
20}
21
22
23define  i32 @rndrrs(i64*  %__addr) {
24; CHECK-LABEL: rndrrs:
25; CHECK:       // %bb.0:
26; CHECK-NEXT:    mrs x10, RNDRRS
27; CHECK-NEXT:    mov x9, x0
28; CHECK-NEXT:    cset w8, eq
29; CHECK-NEXT:    and w8, w8, #0x1
30; CHECK-NEXT:    mov w0, w8
31; CHECK-NEXT:    str x10, [x9]
32; CHECK-NEXT:    ret
33  %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
34  %2 = extractvalue { i64, i1 } %1, 0
35  %3 = extractvalue { i64, i1 } %1, 1
36  store i64 %2, i64* %__addr, align 8
37  %4 = zext i1 %3 to i32
38  ret i32 %4
39}
40
41declare { i64, i1 } @llvm.aarch64.rndr()
42declare { i64, i1 } @llvm.aarch64.rndrrs()
43