1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefixes=CHECK
3
4; LEGAL INTEGER TYPES
5
6define <2 x i64> @stepvector_v2i64() {
7; CHECK-LABEL: .LCPI0_0:
8; CHECK-NEXT:    .xword 0
9; CHECK-NEXT:    .xword 1
10; CHECK-LABEL: stepvector_v2i64:
11; CHECK:       // %bb.0: // %entry
12; CHECK-NEXT:    adrp x8, .LCPI0_0
13; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI0_0]
14; CHECK-NEXT:    ret
15entry:
16  %0 = call <2 x i64> @llvm.experimental.stepvector.v2i64()
17  ret <2 x i64> %0
18}
19
20define <4 x i32> @stepvector_v4i32() {
21; CHECK-LABEL: .LCPI1_0:
22; CHECK-NEXT:    .word 0
23; CHECK-NEXT:    .word 1
24; CHECK-NEXT:    .word 2
25; CHECK-NEXT:    .word 3
26; CHECK-LABEL: stepvector_v4i32:
27; CHECK:       // %bb.0: // %entry
28; CHECK-NEXT:    adrp x8, .LCPI1_0
29; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI1_0]
30; CHECK-NEXT:    ret
31entry:
32  %0 = call <4 x i32> @llvm.experimental.stepvector.v4i32()
33  ret <4 x i32> %0
34}
35
36define <8 x i16> @stepvector_v8i16() {
37; CHECK-LABEL: .LCPI2_0:
38; CHECK-NEXT:    .hword 0
39; CHECK-NEXT:    .hword 1
40; CHECK-NEXT:    .hword 2
41; CHECK-NEXT:    .hword 3
42; CHECK-NEXT:    .hword 4
43; CHECK-NEXT:    .hword 5
44; CHECK-NEXT:    .hword 6
45; CHECK-NEXT:    .hword 7
46; CHECK-LABEL: stepvector_v8i16:
47; CHECK:       // %bb.0: // %entry
48; CHECK-NEXT:    adrp x8, .LCPI2_0
49; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI2_0]
50; CHECK-NEXT:    ret
51entry:
52  %0 = call <8 x i16> @llvm.experimental.stepvector.v8i16()
53  ret <8 x i16> %0
54}
55
56define <16 x i8> @stepvector_v16i8() {
57; CHECK-LABEL: .LCPI3_0:
58; CHECK-NEXT:    .byte 0
59; CHECK-NEXT:    .byte 1
60; CHECK-NEXT:    .byte 2
61; CHECK-NEXT:    .byte 3
62; CHECK-NEXT:    .byte 4
63; CHECK-NEXT:    .byte 5
64; CHECK-NEXT:    .byte 6
65; CHECK-NEXT:    .byte 7
66; CHECK-NEXT:    .byte 8
67; CHECK-NEXT:    .byte 9
68; CHECK-NEXT:    .byte 10
69; CHECK-NEXT:    .byte 11
70; CHECK-NEXT:    .byte 12
71; CHECK-NEXT:    .byte 13
72; CHECK-NEXT:    .byte 14
73; CHECK-NEXT:    .byte 15
74; CHECK-LABEL: stepvector_v16i8:
75; CHECK:       // %bb.0: // %entry
76; CHECK-NEXT:    adrp x8, .LCPI3_0
77; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI3_0]
78; CHECK-NEXT:    ret
79entry:
80  %0 = call <16 x i8> @llvm.experimental.stepvector.v16i8()
81  ret <16 x i8> %0
82}
83
84; ILLEGAL INTEGER TYPES
85
86define <4 x i64> @stepvector_v4i64() {
87; CHECK-LABEL: .LCPI4_0:
88; CHECK-NEXT:    .xword 0
89; CHECK-NEXT:    .xword 1
90; CHECK-LABEL: .LCPI4_1:
91; CHECK-NEXT:    .xword 2
92; CHECK-NEXT:    .xword 3
93; CHECK-LABEL: stepvector_v4i64:
94; CHECK:       // %bb.0: // %entry
95; CHECK-NEXT:    adrp x8, .LCPI4_0
96; CHECK-NEXT:    adrp x9, .LCPI4_1
97; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI4_0]
98; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI4_1]
99; CHECK-NEXT:    ret
100entry:
101  %0 = call <4 x i64> @llvm.experimental.stepvector.v4i64()
102  ret <4 x i64> %0
103}
104
105define <16 x i32> @stepvector_v16i32() {
106; CHECK-LABEL: .LCPI5_0:
107; CHECK-NEXT:    .word 0
108; CHECK-NEXT:    .word 1
109; CHECK-NEXT:    .word 2
110; CHECK-NEXT:    .word 3
111; CHECK-LABEL: .LCPI5_1:
112; CHECK-NEXT:    .word 4
113; CHECK-NEXT:    .word 5
114; CHECK-NEXT:    .word 6
115; CHECK-NEXT:    .word 7
116; CHECK-LABEL: .LCPI5_2:
117; CHECK-NEXT:    .word 8
118; CHECK-NEXT:    .word 9
119; CHECK-NEXT:    .word 10
120; CHECK-NEXT:    .word 11
121; CHECK-LABEL: .LCPI5_3:
122; CHECK-NEXT:    .word 12
123; CHECK-NEXT:    .word 13
124; CHECK-NEXT:    .word 14
125; CHECK-NEXT:    .word 15
126; CHECK-LABEL: stepvector_v16i32:
127; CHECK:       // %bb.0: // %entry
128; CHECK-NEXT:    adrp x8, .LCPI5_0
129; CHECK-NEXT:    adrp x9, .LCPI5_1
130; CHECK-NEXT:    adrp x10, .LCPI5_2
131; CHECK-NEXT:    adrp x11, .LCPI5_3
132; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI5_0]
133; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI5_1]
134; CHECK-NEXT:    ldr q2, [x10, :lo12:.LCPI5_2]
135; CHECK-NEXT:    ldr q3, [x11, :lo12:.LCPI5_3]
136; CHECK-NEXT:    ret
137entry:
138  %0 = call <16 x i32> @llvm.experimental.stepvector.v16i32()
139  ret <16 x i32> %0
140}
141
142define <2 x i32> @stepvector_v2i32() {
143; CHECK-LABEL: .LCPI6_0:
144; CHECK-NEXT:    .word 0
145; CHECK-NEXT:    .word 1
146; CHECK-LABEL: stepvector_v2i32:
147; CHECK:       // %bb.0: // %entry
148; CHECK-NEXT:    adrp x8, .LCPI6_0
149; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI6_0]
150; CHECK-NEXT:    ret
151entry:
152  %0 = call <2 x i32> @llvm.experimental.stepvector.v2i32()
153  ret <2 x i32> %0
154}
155
156define <4 x i16> @stepvector_v4i16() {
157; CHECK-LABEL: .LCPI7_0:
158; CHECK-NEXT:    .hword 0
159; CHECK-NEXT:    .hword 1
160; CHECK-NEXT:    .hword 2
161; CHECK-NEXT:    .hword 3
162; CHECK-LABEL: stepvector_v4i16:
163; CHECK:       // %bb.0: // %entry
164; CHECK-NEXT:    adrp x8, .LCPI7_0
165; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI7_0]
166; CHECK-NEXT:    ret
167entry:
168  %0 = call <4 x i16> @llvm.experimental.stepvector.v4i16()
169  ret <4 x i16> %0
170}
171
172
173declare <2 x i64> @llvm.experimental.stepvector.v2i64()
174declare <4 x i32> @llvm.experimental.stepvector.v4i32()
175declare <8 x i16> @llvm.experimental.stepvector.v8i16()
176declare <16 x i8> @llvm.experimental.stepvector.v16i8()
177
178declare <4 x i64> @llvm.experimental.stepvector.v4i64()
179declare <16 x i32> @llvm.experimental.stepvector.v16i32()
180declare <2 x i32> @llvm.experimental.stepvector.v2i32()
181declare <4 x i16> @llvm.experimental.stepvector.v4i16()
182