1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefixes=CHECK
2
3; LEGAL INTEGER TYPES
4
5define <2 x i64> @stepvector_v2i64() {
6; CHECK-LABEL: .LCPI0_0:
7; CHECK-NEXT:    .xword 0
8; CHECK-NEXT:    .xword 1
9; CHECK-LABEL: stepvector_v2i64:
10; CHECK:       // %bb.0: // %entry
11; CHECK-NEXT:    adrp x8, .LCPI0_0
12; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI0_0]
13; CHECK-NEXT:    ret
14entry:
15  %0 = call <2 x i64> @llvm.experimental.stepvector.v2i64()
16  ret <2 x i64> %0
17}
18
19define <4 x i32> @stepvector_v4i32() {
20; CHECK-LABEL: .LCPI1_0:
21; CHECK-NEXT:    .word 0
22; CHECK-NEXT:    .word 1
23; CHECK-NEXT:    .word 2
24; CHECK-NEXT:    .word 3
25; CHECK-LABEL: stepvector_v4i32:
26; CHECK:       // %bb.0: // %entry
27; CHECK-NEXT:    adrp x8, .LCPI1_0
28; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI1_0]
29; CHECK-NEXT:    ret
30entry:
31  %0 = call <4 x i32> @llvm.experimental.stepvector.v4i32()
32  ret <4 x i32> %0
33}
34
35define <8 x i16> @stepvector_v8i16() {
36; CHECK-LABEL: .LCPI2_0:
37; CHECK-NEXT:    .hword 0
38; CHECK-NEXT:    .hword 1
39; CHECK-NEXT:    .hword 2
40; CHECK-NEXT:    .hword 3
41; CHECK-NEXT:    .hword 4
42; CHECK-NEXT:    .hword 5
43; CHECK-NEXT:    .hword 6
44; CHECK-NEXT:    .hword 7
45; CHECK-LABEL: stepvector_v8i16:
46; CHECK:       // %bb.0: // %entry
47; CHECK-NEXT:    adrp x8, .LCPI2_0
48; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI2_0]
49; CHECK-NEXT:    ret
50entry:
51  %0 = call <8 x i16> @llvm.experimental.stepvector.v8i16()
52  ret <8 x i16> %0
53}
54
55define <16 x i8> @stepvector_v16i8() {
56; CHECK-LABEL: .LCPI3_0:
57; CHECK-NEXT:    .byte 0
58; CHECK-NEXT:    .byte 1
59; CHECK-NEXT:    .byte 2
60; CHECK-NEXT:    .byte 3
61; CHECK-NEXT:    .byte 4
62; CHECK-NEXT:    .byte 5
63; CHECK-NEXT:    .byte 6
64; CHECK-NEXT:    .byte 7
65; CHECK-NEXT:    .byte 8
66; CHECK-NEXT:    .byte 9
67; CHECK-NEXT:    .byte 10
68; CHECK-NEXT:    .byte 11
69; CHECK-NEXT:    .byte 12
70; CHECK-NEXT:    .byte 13
71; CHECK-NEXT:    .byte 14
72; CHECK-NEXT:    .byte 15
73; CHECK-LABEL: stepvector_v16i8:
74; CHECK:       // %bb.0: // %entry
75; CHECK-NEXT:    adrp x8, .LCPI3_0
76; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI3_0]
77; CHECK-NEXT:    ret
78entry:
79  %0 = call <16 x i8> @llvm.experimental.stepvector.v16i8()
80  ret <16 x i8> %0
81}
82
83; ILLEGAL INTEGER TYPES
84
85define <4 x i64> @stepvector_v4i64() {
86; CHECK-LABEL: .LCPI4_0:
87; CHECK-NEXT:    .xword 0
88; CHECK-NEXT:    .xword 1
89; CHECK-LABEL: .LCPI4_1:
90; CHECK-NEXT:    .xword 2
91; CHECK-NEXT:    .xword 3
92; CHECK-LABEL: stepvector_v4i64:
93; CHECK:       // %bb.0: // %entry
94; CHECK-NEXT:    adrp x8, .LCPI4_0
95; CHECK-NEXT:    adrp x9, .LCPI4_1
96; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI4_0]
97; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI4_1]
98; CHECK-NEXT:    ret
99entry:
100  %0 = call <4 x i64> @llvm.experimental.stepvector.v4i64()
101  ret <4 x i64> %0
102}
103
104define <16 x i32> @stepvector_v16i32() {
105; CHECK-LABEL: .LCPI5_0:
106; CHECK-NEXT:    .word 0
107; CHECK-NEXT:    .word 1
108; CHECK-NEXT:    .word 2
109; CHECK-NEXT:    .word 3
110; CHECK-LABEL: .LCPI5_1:
111; CHECK-NEXT:    .word 4
112; CHECK-NEXT:    .word 5
113; CHECK-NEXT:    .word 6
114; CHECK-NEXT:    .word 7
115; CHECK-LABEL: .LCPI5_2:
116; CHECK-NEXT:    .word 8
117; CHECK-NEXT:    .word 9
118; CHECK-NEXT:    .word 10
119; CHECK-NEXT:    .word 11
120; CHECK-LABEL: .LCPI5_3:
121; CHECK-NEXT:    .word 12
122; CHECK-NEXT:    .word 13
123; CHECK-NEXT:    .word 14
124; CHECK-NEXT:    .word 15
125; CHECK-LABEL: stepvector_v16i32:
126; CHECK:       // %bb.0: // %entry
127; CHECK-NEXT:    adrp x8, .LCPI5_0
128; CHECK-NEXT:    adrp x9, .LCPI5_1
129; CHECK-NEXT:    adrp x10, .LCPI5_2
130; CHECK-NEXT:    adrp x11, .LCPI5_3
131; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI5_0]
132; CHECK-NEXT:    ldr q1, [x9, :lo12:.LCPI5_1]
133; CHECK-NEXT:    ldr q2, [x10, :lo12:.LCPI5_2]
134; CHECK-NEXT:    ldr q3, [x11, :lo12:.LCPI5_3]
135; CHECK-NEXT:    ret
136entry:
137  %0 = call <16 x i32> @llvm.experimental.stepvector.v16i32()
138  ret <16 x i32> %0
139}
140
141define <2 x i32> @stepvector_v2i32() {
142; CHECK-LABEL: .LCPI6_0:
143; CHECK-NEXT:    .word 0
144; CHECK-NEXT:    .word 1
145; CHECK-LABEL: stepvector_v2i32:
146; CHECK:       // %bb.0: // %entry
147; CHECK-NEXT:    adrp x8, .LCPI6_0
148; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI6_0]
149; CHECK-NEXT:    ret
150entry:
151  %0 = call <2 x i32> @llvm.experimental.stepvector.v2i32()
152  ret <2 x i32> %0
153}
154
155define <4 x i16> @stepvector_v4i16() {
156; CHECK-LABEL: .LCPI7_0:
157; CHECK-NEXT:    .hword 0
158; CHECK-NEXT:    .hword 1
159; CHECK-NEXT:    .hword 2
160; CHECK-NEXT:    .hword 3
161; CHECK-LABEL: stepvector_v4i16:
162; CHECK:       // %bb.0: // %entry
163; CHECK-NEXT:    adrp x8, .LCPI7_0
164; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI7_0]
165; CHECK-NEXT:    ret
166entry:
167  %0 = call <4 x i16> @llvm.experimental.stepvector.v4i16()
168  ret <4 x i16> %0
169}
170
171
172declare <2 x i64> @llvm.experimental.stepvector.v2i64()
173declare <4 x i32> @llvm.experimental.stepvector.v4i32()
174declare <8 x i16> @llvm.experimental.stepvector.v8i16()
175declare <16 x i8> @llvm.experimental.stepvector.v16i8()
176
177declare <4 x i64> @llvm.experimental.stepvector.v4i64()
178declare <16 x i32> @llvm.experimental.stepvector.v16i32()
179declare <2 x i32> @llvm.experimental.stepvector.v2i32()
180declare <4 x i16> @llvm.experimental.stepvector.v4i16()
181