1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64 -mattr=+ls64 -verify-machineinstrs -o - %s | FileCheck %s
3
4%struct.foo = type { [8 x i64] }
5
6define void @load(%struct.foo* %output, i8* %addr) {
7; CHECK-LABEL: load:
8; CHECK:       // %bb.0: // %entry
9; CHECK-NEXT:    //APP
10; CHECK-NEXT:    ld64b x2, [x1]
11; CHECK-NEXT:    //NO_APP
12; CHECK-NEXT:    stp x8, x9, [x0, #48]
13; CHECK-NEXT:    stp x6, x7, [x0, #32]
14; CHECK-NEXT:    stp x4, x5, [x0, #16]
15; CHECK-NEXT:    stp x2, x3, [x0]
16; CHECK-NEXT:    ret
17entry:
18  %val = call i512 asm sideeffect "ld64b $0,[$1]", "=r,r,~{memory}"(i8* %addr)
19  %outcast = bitcast %struct.foo* %output to i512*
20  store i512 %val, i512* %outcast, align 8
21  ret void
22}
23
24define void @store(%struct.foo* %input, i8* %addr) {
25; CHECK-LABEL: store:
26; CHECK:       // %bb.0: // %entry
27; CHECK-NEXT:    ldp x8, x9, [x0, #48]
28; CHECK-NEXT:    ldp x6, x7, [x0, #32]
29; CHECK-NEXT:    ldp x4, x5, [x0, #16]
30; CHECK-NEXT:    ldp x2, x3, [x0]
31; CHECK-NEXT:    //APP
32; CHECK-NEXT:    st64b x2, [x1]
33; CHECK-NEXT:    //NO_APP
34; CHECK-NEXT:    ret
35entry:
36  %incast = bitcast %struct.foo* %input to i512*
37  %val = load i512, i512* %incast, align 8
38  call void asm sideeffect "st64b $0,[$1]", "r,r,~{memory}"(i512 %val, i8* %addr)
39  ret void
40}
41
42define void @store2(i32* %in, i8* %addr) {
43; CHECK-LABEL: store2:
44; CHECK:       // %bb.0: // %entry
45; CHECK-NEXT:    sub sp, sp, #64
46; CHECK-NEXT:    .cfi_def_cfa_offset 64
47; CHECK-NEXT:    ldpsw x2, x3, [x0]
48; CHECK-NEXT:    ldrsw x4, [x0, #16]
49; CHECK-NEXT:    ldrsw x5, [x0, #64]
50; CHECK-NEXT:    ldrsw x6, [x0, #100]
51; CHECK-NEXT:    ldrsw x7, [x0, #144]
52; CHECK-NEXT:    ldrsw x8, [x0, #196]
53; CHECK-NEXT:    ldrsw x9, [x0, #256]
54; CHECK-NEXT:    //APP
55; CHECK-NEXT:    st64b x2, [x1]
56; CHECK-NEXT:    //NO_APP
57; CHECK-NEXT:    add sp, sp, #64
58; CHECK-NEXT:    ret
59entry:
60  %0 = load i32, i32* %in, align 4
61  %conv = sext i32 %0 to i64
62  %arrayidx1 = getelementptr inbounds i32, i32* %in, i64 1
63  %1 = load i32, i32* %arrayidx1, align 4
64  %conv2 = sext i32 %1 to i64
65  %arrayidx4 = getelementptr inbounds i32, i32* %in, i64 4
66  %2 = load i32, i32* %arrayidx4, align 4
67  %conv5 = sext i32 %2 to i64
68  %arrayidx7 = getelementptr inbounds i32, i32* %in, i64 16
69  %3 = load i32, i32* %arrayidx7, align 4
70  %conv8 = sext i32 %3 to i64
71  %arrayidx10 = getelementptr inbounds i32, i32* %in, i64 25
72  %4 = load i32, i32* %arrayidx10, align 4
73  %conv11 = sext i32 %4 to i64
74  %arrayidx13 = getelementptr inbounds i32, i32* %in, i64 36
75  %5 = load i32, i32* %arrayidx13, align 4
76  %conv14 = sext i32 %5 to i64
77  %arrayidx16 = getelementptr inbounds i32, i32* %in, i64 49
78  %6 = load i32, i32* %arrayidx16, align 4
79  %conv17 = sext i32 %6 to i64
80  %arrayidx19 = getelementptr inbounds i32, i32* %in, i64 64
81  %7 = load i32, i32* %arrayidx19, align 4
82  %conv20 = sext i32 %7 to i64
83  %s.sroa.10.0.insert.ext = zext i64 %conv20 to i512
84  %s.sroa.10.0.insert.shift = shl nuw i512 %s.sroa.10.0.insert.ext, 448
85  %s.sroa.9.0.insert.ext = zext i64 %conv17 to i512
86  %s.sroa.9.0.insert.shift = shl nuw nsw i512 %s.sroa.9.0.insert.ext, 384
87  %s.sroa.9.0.insert.insert = or i512 %s.sroa.10.0.insert.shift, %s.sroa.9.0.insert.shift
88  %s.sroa.8.0.insert.ext = zext i64 %conv14 to i512
89  %s.sroa.8.0.insert.shift = shl nuw nsw i512 %s.sroa.8.0.insert.ext, 320
90  %s.sroa.8.0.insert.insert = or i512 %s.sroa.9.0.insert.insert, %s.sroa.8.0.insert.shift
91  %s.sroa.7.0.insert.ext = zext i64 %conv11 to i512
92  %s.sroa.7.0.insert.shift = shl nuw nsw i512 %s.sroa.7.0.insert.ext, 256
93  %s.sroa.7.0.insert.insert = or i512 %s.sroa.8.0.insert.insert, %s.sroa.7.0.insert.shift
94  %s.sroa.6.0.insert.ext = zext i64 %conv8 to i512
95  %s.sroa.6.0.insert.shift = shl nuw nsw i512 %s.sroa.6.0.insert.ext, 192
96  %s.sroa.6.0.insert.insert = or i512 %s.sroa.7.0.insert.insert, %s.sroa.6.0.insert.shift
97  %s.sroa.5.0.insert.ext = zext i64 %conv5 to i512
98  %s.sroa.5.0.insert.shift = shl nuw nsw i512 %s.sroa.5.0.insert.ext, 128
99  %s.sroa.4.0.insert.ext = zext i64 %conv2 to i512
100  %s.sroa.4.0.insert.shift = shl nuw nsw i512 %s.sroa.4.0.insert.ext, 64
101  %s.sroa.4.0.insert.mask = or i512 %s.sroa.6.0.insert.insert, %s.sroa.5.0.insert.shift
102  %s.sroa.0.0.insert.ext = zext i64 %conv to i512
103  %s.sroa.0.0.insert.mask = or i512 %s.sroa.4.0.insert.mask, %s.sroa.4.0.insert.shift
104  %s.sroa.0.0.insert.insert = or i512 %s.sroa.0.0.insert.mask, %s.sroa.0.0.insert.ext
105  call void asm sideeffect "st64b $0,[$1]", "r,r,~{memory}"(i512 %s.sroa.0.0.insert.insert, i8* %addr)
106  ret void
107}
108