1; RUN: llc -O0 -fast-isel -verify-machineinstrs -mtriple=arm64-eabi < %s | FileCheck --enable-var-scope %s
2
3; Test fptosi
4define i32 @fptosi_wh(half %a) nounwind ssp {
5entry:
6; CHECK-LABEL: fptosi_wh
7; CHECK: fcvt [[REG:s[0-9]+]], h0
8; CHECK: fcvtzs w0, [[REG]]
9  %conv = fptosi half %a to i32
10  ret i32 %conv
11}
12
13; Test fptoui
14define i32 @fptoui_swh(half %a) nounwind ssp {
15entry:
16; CHECK-LABEL: fptoui_swh
17; CHECK: fcvt [[REG:s[0-9]+]], h0
18; CHECK: fcvtzu w0, [[REG]]
19  %conv = fptoui half %a to i32
20  ret i32 %conv
21}
22
23; Test sitofp
24define half @sitofp_hw_i1(i1 %a) nounwind ssp {
25entry:
26; CHECK-LABEL: sitofp_hw_i1
27; CHECK: sbfx [[REG:w[0-9]+]], w0, #0, #1
28; CHECK: scvtf s0, [[REG]]
29; CHECK: fcvt  h0, s0
30  %conv = sitofp i1 %a to half
31  ret half %conv
32}
33
34; Test sitofp
35define half @sitofp_hw_i8(i8 %a) nounwind ssp {
36entry:
37; CHECK-LABEL: sitofp_hw_i8
38; CHECK: sxtb [[REG:w[0-9]+]], w0
39; CHECK: scvtf s0, [[REG]]
40; CHECK: fcvt  h0, s0
41  %conv = sitofp i8 %a to half
42  ret half %conv
43}
44
45; Test sitofp
46define half @sitofp_hw_i16(i16 %a) nounwind ssp {
47entry:
48; CHECK-LABEL: sitofp_hw_i16
49; CHECK: sxth [[REG:w[0-9]+]], w0
50; CHECK: scvtf s0, [[REG]]
51; CHECK: fcvt  h0, s0
52  %conv = sitofp i16 %a to half
53  ret half %conv
54}
55
56; Test sitofp
57define half @sitofp_hw_i32(i32 %a) nounwind ssp {
58entry:
59; CHECK-LABEL: sitofp_hw_i32
60; CHECK: scvtf s0, w0
61; CHECK: fcvt  h0, s0
62  %conv = sitofp i32 %a to half
63  ret half %conv
64}
65
66; Test sitofp
67define half @sitofp_hx(i64 %a) nounwind ssp {
68entry:
69; CHECK-LABEL: sitofp_hx
70; CHECK: scvtf s0, x0
71; CHECK: fcvt  h0, s0
72  %conv = sitofp i64 %a to half
73  ret half %conv
74}
75
76; Test uitofp
77define half @uitofp_hw_i1(i1 %a) nounwind ssp {
78entry:
79; CHECK-LABEL: uitofp_hw_i1
80; CHECK: and [[REG:w[0-9]+]], w0, #0x1
81; CHECK: ucvtf s0, [[REG]]
82; CHECK: fcvt  h0, s0
83  %conv = uitofp i1 %a to half
84  ret half %conv
85}
86
87; Test uitofp
88define half @uitofp_hw_i8(i8 %a) nounwind ssp {
89entry:
90; CHECK-LABEL: uitofp_hw_i8
91; CHECK: and [[REG:w[0-9]+]], w0, #0xff
92; CHECK: ucvtf s0, [[REG]]
93; CHECK: fcvt  h0, s0
94  %conv = uitofp i8 %a to half
95  ret half %conv
96}
97
98; Test uitofp
99define half @uitofp_hw_i16(i16 %a) nounwind ssp {
100entry:
101; CHECK-LABEL: uitofp_hw_i16
102; CHECK: and [[REG:w[0-9]+]], w0, #0xffff
103; CHECK: ucvtf s0, [[REG]]
104; CHECK: fcvt  h0, s0
105  %conv = uitofp i16 %a to half
106  ret half %conv
107}
108
109; Test uitofp
110define half @uitofp_hw_i32(i32 %a) nounwind ssp {
111entry:
112; CHECK-LABEL: uitofp_hw_i32
113; CHECK: ucvtf s0, w0
114; CHECK: fcvt  h0, s0
115  %conv = uitofp i32 %a to half
116  ret half %conv
117}
118
119; Test uitofp
120define half @uitofp_hx(i64 %a) nounwind ssp {
121entry:
122; CHECK-LABEL: uitofp_hx
123; CHECK: ucvtf s0, x0
124; CHECK: fcvt  h0, s0
125  %conv = uitofp i64 %a to half
126  ret half %conv
127}
128
129
130