1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3--- 4name: shl_v2i32 5alignment: 4 6legalized: true 7regBankSelected: true 8tracksRegLiveness: true 9registers: 10 - { id: 0, class: fpr } 11 - { id: 1, class: fpr } 12 - { id: 2, class: fpr } 13machineFunctionInfo: {} 14body: | 15 bb.1: 16 liveins: $d0, $d1 17 18 ; CHECK-LABEL: name: shl_v2i32 19 ; CHECK: liveins: $d0, $d1 20 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 21 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 22 ; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[COPY1]] 23 ; CHECK: $d0 = COPY [[USHLv2i32_]] 24 ; CHECK: RET_ReallyLR implicit $d0 25 %0:fpr(<2 x s32>) = COPY $d0 26 %1:fpr(<2 x s32>) = COPY $d1 27 %2:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>) 28 $d0 = COPY %2(<2 x s32>) 29 RET_ReallyLR implicit $d0 30 31... 32--- 33name: shl_v2i32_imm 34alignment: 4 35legalized: true 36regBankSelected: true 37tracksRegLiveness: true 38registers: 39 - { id: 0, class: fpr } 40 - { id: 1, class: fpr } 41 - { id: 2, class: gpr } 42 - { id: 3, class: fpr } 43liveins: 44 - { reg: '$d0' } 45frameInfo: 46 maxAlignment: 1 47machineFunctionInfo: {} 48body: | 49 bb.1: 50 liveins: $d0 51 52 ; CHECK-LABEL: name: shl_v2i32_imm 53 ; CHECK: liveins: $d0 54 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 55 ; CHECK: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 24 56 ; CHECK: $d0 = COPY [[SHLv2i32_shift]] 57 ; CHECK: RET_ReallyLR implicit $d0 58 %0:fpr(<2 x s32>) = COPY $d0 59 %2:gpr(s32) = G_CONSTANT i32 24 60 %1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32) 61 %3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>) 62 $d0 = COPY %3(<2 x s32>) 63 RET_ReallyLR implicit $d0 64 65... 66--- 67name: shl_v2i32_imm_out_of_range 68alignment: 4 69legalized: true 70regBankSelected: true 71tracksRegLiveness: true 72registers: 73 - { id: 0, class: fpr } 74 - { id: 1, class: fpr } 75 - { id: 2, class: gpr } 76 - { id: 3, class: fpr } 77liveins: 78 - { reg: '$d0' } 79frameInfo: 80 maxAlignment: 1 81machineFunctionInfo: {} 82body: | 83 bb.1: 84 liveins: $d0 85 86 ; CHECK-LABEL: name: shl_v2i32_imm_out_of_range 87 ; CHECK: liveins: $d0 88 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 89 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 90 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 91 ; CHECK: [[USHLv2i32_:%[0-9]+]]:fpr64 = USHLv2i32 [[COPY]], [[LDRDui]] 92 ; CHECK: $d0 = COPY [[USHLv2i32_]] 93 ; CHECK: RET_ReallyLR implicit $d0 94 %0:fpr(<2 x s32>) = COPY $d0 95 %2:gpr(s32) = G_CONSTANT i32 40 96 %1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32) 97 %3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>) 98 $d0 = COPY %3(<2 x s32>) 99 RET_ReallyLR implicit $d0 100 101... 102--- 103name: shl_v4i32 104alignment: 4 105legalized: true 106regBankSelected: true 107tracksRegLiveness: true 108registers: 109 - { id: 0, class: fpr } 110 - { id: 1, class: fpr } 111 - { id: 2, class: fpr } 112machineFunctionInfo: {} 113body: | 114 bb.1: 115 liveins: $q0, $q1 116 117 ; CHECK-LABEL: name: shl_v4i32 118 ; CHECK: liveins: $q0, $q1 119 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 120 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 121 ; CHECK: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[COPY1]] 122 ; CHECK: $q0 = COPY [[USHLv4i32_]] 123 ; CHECK: RET_ReallyLR implicit $q0 124 %0:fpr(<4 x s32>) = COPY $q0 125 %1:fpr(<4 x s32>) = COPY $q1 126 %2:fpr(<4 x s32>) = G_SHL %0, %1(<4 x s32>) 127 $q0 = COPY %2(<4 x s32>) 128 RET_ReallyLR implicit $q0 129 130... 131--- 132name: shl_v4i32_imm 133alignment: 4 134legalized: true 135regBankSelected: true 136tracksRegLiveness: true 137registers: 138 - { id: 0, class: fpr } 139 - { id: 1, class: fpr } 140 - { id: 2, class: gpr } 141 - { id: 3, class: fpr } 142liveins: 143 - { reg: '$q0' } 144frameInfo: 145 maxAlignment: 1 146machineFunctionInfo: {} 147body: | 148 bb.1: 149 liveins: $q0 150 151 ; CHECK-LABEL: name: shl_v4i32_imm 152 ; CHECK: liveins: $q0 153 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 154 ; CHECK: [[SHLv4i32_shift:%[0-9]+]]:fpr128 = SHLv4i32_shift [[COPY]], 24 155 ; CHECK: $q0 = COPY [[SHLv4i32_shift]] 156 ; CHECK: RET_ReallyLR implicit $q0 157 %0:fpr(<4 x s32>) = COPY $q0 158 %2:gpr(s32) = G_CONSTANT i32 24 159 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %2(s32), %2(s32), %2(s32) 160 %3:fpr(<4 x s32>) = G_SHL %0, %1(<4 x s32>) 161 $q0 = COPY %3(<4 x s32>) 162 RET_ReallyLR implicit $q0 163 164... 165--- 166name: shl_v2i64 167alignment: 4 168legalized: true 169regBankSelected: true 170tracksRegLiveness: true 171registers: 172 - { id: 0, class: fpr } 173 - { id: 1, class: fpr } 174 - { id: 2, class: fpr } 175machineFunctionInfo: {} 176body: | 177 bb.1: 178 liveins: $q0, $q1 179 180 ; CHECK-LABEL: name: shl_v2i64 181 ; CHECK: liveins: $q0, $q1 182 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 183 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 184 ; CHECK: [[USHLv2i64_:%[0-9]+]]:fpr128 = USHLv2i64 [[COPY]], [[COPY1]] 185 ; CHECK: $q0 = COPY [[USHLv2i64_]] 186 ; CHECK: RET_ReallyLR implicit $q0 187 %0:fpr(<2 x s64>) = COPY $q0 188 %1:fpr(<2 x s64>) = COPY $q1 189 %2:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>) 190 $q0 = COPY %2(<2 x s64>) 191 RET_ReallyLR implicit $q0 192 193... 194--- 195name: shl_v2i64_imm 196alignment: 4 197legalized: true 198regBankSelected: true 199tracksRegLiveness: true 200registers: 201 - { id: 0, class: fpr } 202 - { id: 1, class: fpr } 203 - { id: 2, class: gpr } 204 - { id: 3, class: fpr } 205liveins: 206 - { reg: '$q0' } 207frameInfo: 208 maxAlignment: 1 209machineFunctionInfo: {} 210body: | 211 bb.1: 212 liveins: $q0 213 214 ; CHECK-LABEL: name: shl_v2i64_imm 215 ; CHECK: liveins: $q0 216 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 217 ; CHECK: [[SHLv2i64_shift:%[0-9]+]]:fpr128 = SHLv2i64_shift [[COPY]], 24 218 ; CHECK: $q0 = COPY [[SHLv2i64_shift]] 219 ; CHECK: RET_ReallyLR implicit $q0 220 %0:fpr(<2 x s64>) = COPY $q0 221 %2:gpr(s64) = G_CONSTANT i64 24 222 %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %2(s64) 223 %3:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>) 224 $q0 = COPY %3(<2 x s64>) 225 RET_ReallyLR implicit $q0 226 227... 228--- 229name: shl_v2i64_imm_out_of_range 230alignment: 4 231legalized: true 232regBankSelected: true 233tracksRegLiveness: true 234registers: 235 - { id: 0, class: fpr } 236 - { id: 1, class: fpr } 237 - { id: 2, class: gpr } 238 - { id: 3, class: fpr } 239liveins: 240 - { reg: '$q0' } 241frameInfo: 242 maxAlignment: 1 243machineFunctionInfo: {} 244body: | 245 bb.1: 246 liveins: $q0 247 248 ; CHECK-LABEL: name: shl_v2i64_imm_out_of_range 249 ; CHECK: liveins: $q0 250 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 251 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 252 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 253 ; CHECK: [[USHLv2i64_:%[0-9]+]]:fpr128 = USHLv2i64 [[COPY]], [[LDRQui]] 254 ; CHECK: $q0 = COPY [[USHLv2i64_]] 255 ; CHECK: RET_ReallyLR implicit $q0 256 %0:fpr(<2 x s64>) = COPY $q0 257 %2:gpr(s64) = G_CONSTANT i64 70 258 %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %2(s64) 259 %3:fpr(<2 x s64>) = G_SHL %0, %1(<2 x s64>) 260 $q0 = COPY %3(<2 x s64>) 261 RET_ReallyLR implicit $q0 262 263... 264--- 265name: ashr_v2i32 266alignment: 4 267legalized: true 268regBankSelected: true 269tracksRegLiveness: true 270registers: 271 - { id: 0, class: fpr } 272 - { id: 1, class: fpr } 273 - { id: 2, class: fpr } 274machineFunctionInfo: {} 275body: | 276 bb.1: 277 liveins: $d0, $d1 278 279 ; CHECK-LABEL: name: ashr_v2i32 280 ; CHECK: liveins: $d0, $d1 281 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 282 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 283 ; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[COPY1]] 284 ; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[COPY]], [[NEGv2i32_]] 285 ; CHECK: $d0 = COPY [[SSHLv2i32_]] 286 ; CHECK: RET_ReallyLR implicit $d0 287 %0:fpr(<2 x s32>) = COPY $d0 288 %1:fpr(<2 x s32>) = COPY $d1 289 %2:fpr(<2 x s32>) = G_ASHR %0, %1(<2 x s32>) 290 $d0 = COPY %2(<2 x s32>) 291 RET_ReallyLR implicit $d0 292 293... 294--- 295name: ashr_v4i32 296alignment: 4 297legalized: true 298regBankSelected: true 299tracksRegLiveness: true 300registers: 301 - { id: 0, class: fpr } 302 - { id: 1, class: fpr } 303 - { id: 2, class: fpr } 304machineFunctionInfo: {} 305body: | 306 bb.1: 307 liveins: $q0, $q1 308 309 ; CHECK-LABEL: name: ashr_v4i32 310 ; CHECK: liveins: $q0, $q1 311 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 312 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 313 ; CHECK: [[NEGv4i32_:%[0-9]+]]:fpr128 = NEGv4i32 [[COPY1]] 314 ; CHECK: [[SSHLv4i32_:%[0-9]+]]:fpr128 = SSHLv4i32 [[COPY]], [[NEGv4i32_]] 315 ; CHECK: $q0 = COPY [[SSHLv4i32_]] 316 ; CHECK: RET_ReallyLR implicit $q0 317 %0:fpr(<4 x s32>) = COPY $q0 318 %1:fpr(<4 x s32>) = COPY $q1 319 %2:fpr(<4 x s32>) = G_ASHR %0, %1(<4 x s32>) 320 $q0 = COPY %2(<4 x s32>) 321 RET_ReallyLR implicit $q0 322 323... 324--- 325name: ashr_v2i64 326alignment: 4 327legalized: true 328regBankSelected: true 329tracksRegLiveness: true 330registers: 331 - { id: 0, class: fpr } 332 - { id: 1, class: fpr } 333 - { id: 2, class: fpr } 334machineFunctionInfo: {} 335body: | 336 bb.1: 337 liveins: $q0, $q1 338 339 ; CHECK-LABEL: name: ashr_v2i64 340 ; CHECK: liveins: $q0, $q1 341 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 342 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 343 ; CHECK: [[NEGv2i64_:%[0-9]+]]:fpr128 = NEGv2i64 [[COPY1]] 344 ; CHECK: [[SSHLv2i64_:%[0-9]+]]:fpr128 = SSHLv2i64 [[COPY]], [[NEGv2i64_]] 345 ; CHECK: $q0 = COPY [[SSHLv2i64_]] 346 ; CHECK: RET_ReallyLR implicit $q0 347 %0:fpr(<2 x s64>) = COPY $q0 348 %1:fpr(<2 x s64>) = COPY $q1 349 %2:fpr(<2 x s64>) = G_ASHR %0, %1(<2 x s64>) 350 $q0 = COPY %2(<2 x s64>) 351 RET_ReallyLR implicit $q0 352 353... 354--- 355name: shl_v4i16 356legalized: true 357regBankSelected: true 358tracksRegLiveness: true 359body: | 360 bb.1: 361 liveins: $d0, $d1 362 ; CHECK-LABEL: name: shl_v4i16 363 ; CHECK: liveins: $d0, $d1 364 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 365 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 366 ; CHECK: [[USHLv4i16_:%[0-9]+]]:fpr64 = USHLv4i16 [[COPY]], [[COPY1]] 367 ; CHECK: $d0 = COPY [[USHLv4i16_]] 368 ; CHECK: RET_ReallyLR implicit $d0 369 %0:fpr(<4 x s16>) = COPY $d0 370 %1:fpr(<4 x s16>) = COPY $d1 371 %2:fpr(<4 x s16>) = G_SHL %0, %1(<4 x s16>) 372 $d0 = COPY %2(<4 x s16>) 373 RET_ReallyLR implicit $d0 374... 375--- 376name: lshr_v4i16 377legalized: true 378regBankSelected: true 379tracksRegLiveness: true 380body: | 381 bb.1: 382 liveins: $d0, $d1 383 ; CHECK-LABEL: name: lshr_v4i16 384 ; CHECK: liveins: $d0, $d1 385 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 386 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 387 ; CHECK: [[NEGv4i16_:%[0-9]+]]:fpr64 = NEGv4i16 [[COPY1]] 388 ; CHECK: [[USHLv4i16_:%[0-9]+]]:fpr64 = USHLv4i16 [[COPY]], [[NEGv4i16_]] 389 ; CHECK: $d0 = COPY [[USHLv4i16_]] 390 ; CHECK: RET_ReallyLR implicit $d0 391 %0:fpr(<4 x s16>) = COPY $d0 392 %1:fpr(<4 x s16>) = COPY $d1 393 %2:fpr(<4 x s16>) = G_LSHR %0, %1(<4 x s16>) 394 $d0 = COPY %2(<4 x s16>) 395 RET_ReallyLR implicit $d0 396... 397--- 398name: lshr_v4i32 399alignment: 4 400legalized: true 401regBankSelected: true 402tracksRegLiveness: true 403registers: 404 - { id: 0, class: fpr } 405 - { id: 1, class: fpr } 406 - { id: 2, class: fpr } 407machineFunctionInfo: {} 408body: | 409 bb.1: 410 liveins: $q0, $q1 411 412 ; CHECK-LABEL: name: lshr_v4i32 413 ; CHECK: liveins: $q0, $q1 414 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 415 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 416 ; CHECK: [[NEGv4i32_:%[0-9]+]]:fpr128 = NEGv4i32 [[COPY1]] 417 ; CHECK: [[USHLv4i32_:%[0-9]+]]:fpr128 = USHLv4i32 [[COPY]], [[NEGv4i32_]] 418 ; CHECK: $q0 = COPY [[USHLv4i32_]] 419 ; CHECK: RET_ReallyLR implicit $q0 420 %0:fpr(<4 x s32>) = COPY $q0 421 %1:fpr(<4 x s32>) = COPY $q1 422 %2:fpr(<4 x s32>) = G_LSHR %0, %1(<4 x s32>) 423 $q0 = COPY %2(<4 x s32>) 424 RET_ReallyLR implicit $q0 425 426... 427--- 428name: lshr_v8i16 429legalized: true 430regBankSelected: true 431tracksRegLiveness: true 432body: | 433 bb.1: 434 liveins: $q0, $q1 435 ; CHECK-LABEL: name: lshr_v8i16 436 ; CHECK: liveins: $q0, $q1 437 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 438 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 439 ; CHECK: [[NEGv8i16_:%[0-9]+]]:fpr128 = NEGv8i16 [[COPY1]] 440 ; CHECK: [[USHLv8i16_:%[0-9]+]]:fpr128 = USHLv8i16 [[COPY]], [[NEGv8i16_]] 441 ; CHECK: $q0 = COPY [[USHLv8i16_]] 442 ; CHECK: RET_ReallyLR implicit $q0 443 %0:fpr(<8 x s16>) = COPY $q0 444 %1:fpr(<8 x s16>) = COPY $q1 445 %2:fpr(<8 x s16>) = G_LSHR %0, %1(<8 x s16>) 446 $q0 = COPY %2(<8 x s16>) 447 RET_ReallyLR implicit $q0 448... 449--- 450name: ashr_v4i16 451legalized: true 452regBankSelected: true 453tracksRegLiveness: true 454body: | 455 bb.1: 456 liveins: $d0, $d1 457 ; CHECK-LABEL: name: ashr_v4i16 458 ; CHECK: liveins: $d0, $d1 459 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 460 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 461 ; CHECK: [[NEGv4i16_:%[0-9]+]]:fpr64 = NEGv4i16 [[COPY1]] 462 ; CHECK: [[SSHLv4i16_:%[0-9]+]]:fpr64 = SSHLv4i16 [[COPY]], [[NEGv4i16_]] 463 ; CHECK: $d0 = COPY [[SSHLv4i16_]] 464 ; CHECK: RET_ReallyLR implicit $d0 465 %0:fpr(<4 x s16>) = COPY $d0 466 %1:fpr(<4 x s16>) = COPY $d1 467 %2:fpr(<4 x s16>) = G_ASHR %0, %1(<4 x s16>) 468 $d0 = COPY %2(<4 x s16>) 469 RET_ReallyLR implicit $d0 470... 471--- 472name: vashr_v4i16_imm 473legalized: true 474regBankSelected: true 475tracksRegLiveness: true 476body: | 477 bb.1: 478 liveins: $d0, $d1 479 ; CHECK-LABEL: name: vashr_v4i16_imm 480 ; CHECK: liveins: $d0, $d1 481 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 482 ; CHECK: [[SSHRv4i16_shift:%[0-9]+]]:fpr64 = SSHRv4i16_shift [[COPY]], 5 483 ; CHECK: $d0 = COPY [[SSHRv4i16_shift]] 484 ; CHECK: RET_ReallyLR implicit $d0 485 %0:fpr(<4 x s16>) = COPY $d0 486 %1:gpr(s32) = G_CONSTANT i32 5 487 %2:fpr(<4 x s16>) = G_VASHR %0, %1 488 $d0 = COPY %2(<4 x s16>) 489 RET_ReallyLR implicit $d0 490... 491--- 492name: vlshr_v4i16_imm 493legalized: true 494regBankSelected: true 495tracksRegLiveness: true 496body: | 497 bb.1: 498 liveins: $d0, $d1 499 ; CHECK-LABEL: name: vlshr_v4i16_imm 500 ; CHECK: liveins: $d0, $d1 501 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 502 ; CHECK: [[USHRv4i16_shift:%[0-9]+]]:fpr64 = USHRv4i16_shift [[COPY]], 5 503 ; CHECK: $d0 = COPY [[USHRv4i16_shift]] 504 ; CHECK: RET_ReallyLR implicit $d0 505 %0:fpr(<4 x s16>) = COPY $d0 506 %1:gpr(s32) = G_CONSTANT i32 5 507 %2:fpr(<4 x s16>) = G_VLSHR %0, %1 508 $d0 = COPY %2(<4 x s16>) 509 RET_ReallyLR implicit $d0 510... 511--- 512name: shl_v8i16 513legalized: true 514regBankSelected: true 515tracksRegLiveness: true 516body: | 517 bb.1: 518 liveins: $q0, $q1 519 ; CHECK-LABEL: name: shl_v8i16 520 ; CHECK: liveins: $q0, $q1 521 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 522 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 523 ; CHECK: [[USHLv8i16_:%[0-9]+]]:fpr128 = USHLv8i16 [[COPY]], [[COPY1]] 524 ; CHECK: $q0 = COPY [[USHLv8i16_]] 525 ; CHECK: RET_ReallyLR implicit $q0 526 %0:fpr(<8 x s16>) = COPY $q0 527 %1:fpr(<8 x s16>) = COPY $q1 528 %2:fpr(<8 x s16>) = G_SHL %0, %1(<8 x s16>) 529 $q0 = COPY %2(<8 x s16>) 530 RET_ReallyLR implicit $q0 531... 532--- 533name: shl_v16i8 534legalized: true 535regBankSelected: true 536tracksRegLiveness: true 537body: | 538 bb.1: 539 liveins: $q0, $q1 540 ; CHECK-LABEL: name: shl_v16i8 541 ; CHECK: liveins: $q0, $q1 542 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 543 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 544 ; CHECK: [[USHLv16i8_:%[0-9]+]]:fpr128 = USHLv16i8 [[COPY]], [[COPY1]] 545 ; CHECK: $q0 = COPY [[USHLv16i8_]] 546 ; CHECK: RET_ReallyLR implicit $q0 547 %0:fpr(<16 x s8>) = COPY $q0 548 %1:fpr(<16 x s8>) = COPY $q1 549 %2:fpr(<16 x s8>) = G_SHL %0, %1(<16 x s8>) 550 $q0 = COPY %2(<16 x s8>) 551 RET_ReallyLR implicit $q0 552... 553--- 554name: lshr_v16i8 555legalized: true 556regBankSelected: true 557tracksRegLiveness: true 558body: | 559 bb.1: 560 liveins: $q0, $q1 561 ; CHECK-LABEL: name: lshr_v16i8 562 ; CHECK: liveins: $q0, $q1 563 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 564 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 565 ; CHECK: [[NEGv16i8_:%[0-9]+]]:fpr128 = NEGv16i8 [[COPY1]] 566 ; CHECK: [[USHLv16i8_:%[0-9]+]]:fpr128 = USHLv16i8 [[COPY]], [[NEGv16i8_]] 567 ; CHECK: $q0 = COPY [[USHLv16i8_]] 568 ; CHECK: RET_ReallyLR implicit $q0 569 %0:fpr(<16 x s8>) = COPY $q0 570 %1:fpr(<16 x s8>) = COPY $q1 571 %2:fpr(<16 x s8>) = G_LSHR %0, %1(<16 x s8>) 572 $q0 = COPY %2(<16 x s8>) 573 RET_ReallyLR implicit $q0 574... 575--- 576name: shl_v2i32_imm_dup 577alignment: 4 578legalized: true 579regBankSelected: true 580tracksRegLiveness: true 581registers: 582 - { id: 0, class: fpr } 583 - { id: 1, class: fpr } 584 - { id: 2, class: gpr } 585 - { id: 3, class: fpr } 586liveins: 587 - { reg: '$d0' } 588frameInfo: 589 maxAlignment: 1 590machineFunctionInfo: {} 591body: | 592 bb.1: 593 liveins: $d0 594 595 ; Should still be able to select immediate forms using a G_DUP from a 596 ; constant. 597 598 ; CHECK-LABEL: name: shl_v2i32_imm_dup 599 ; CHECK: liveins: $d0 600 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 601 ; CHECK: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 24 602 ; CHECK: $d0 = COPY [[SHLv2i32_shift]] 603 ; CHECK: RET_ReallyLR implicit $d0 604 %0:fpr(<2 x s32>) = COPY $d0 605 %2:gpr(s32) = G_CONSTANT i32 24 606 %1:fpr(<2 x s32>) = G_DUP %2(s32) 607 %3:fpr(<2 x s32>) = G_SHL %0, %1(<2 x s32>) 608 $d0 = COPY %3(<2 x s32>) 609 RET_ReallyLR implicit $d0 610