1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 ; ModuleID = 'icmp-autogen-tests-with-ne.ll' 6 source_filename = "icmp-autogen-tests-with-ne.ll" 7 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 8 target triple = "aarch64" 9 10 define <2 x i1> @test_v2i64_eq(<2 x i64> %v1, <2 x i64> %v2) { 11 %cmp = icmp eq <2 x i64> %v1, %v2 12 ret <2 x i1> %cmp 13 } 14 15 define <4 x i1> @test_v4i32_eq(<4 x i32> %v1, <4 x i32> %v2) { 16 %cmp = icmp eq <4 x i32> %v1, %v2 17 ret <4 x i1> %cmp 18 } 19 20 define <2 x i1> @test_v2i32_eq(<2 x i32> %v1, <2 x i32> %v2) { 21 %cmp = icmp eq <2 x i32> %v1, %v2 22 ret <2 x i1> %cmp 23 } 24 25 define <2 x i1> @test_v2i16_eq(<2 x i16> %v1, <2 x i16> %v2) { 26 %cmp = icmp eq <2 x i16> %v1, %v2 27 ret <2 x i1> %cmp 28 } 29 30 define <8 x i1> @test_v8i16_eq(<8 x i16> %v1, <8 x i16> %v2) { 31 %cmp = icmp eq <8 x i16> %v1, %v2 32 ret <8 x i1> %cmp 33 } 34 35 define <4 x i1> @test_v4i16_eq(<4 x i16> %v1, <4 x i16> %v2) { 36 %cmp = icmp eq <4 x i16> %v1, %v2 37 ret <4 x i1> %cmp 38 } 39 40 define <16 x i1> @test_v16i8_eq(<16 x i8> %v1, <16 x i8> %v2) { 41 %cmp = icmp eq <16 x i8> %v1, %v2 42 ret <16 x i1> %cmp 43 } 44 45 define <8 x i1> @test_v8i8_eq(<8 x i8> %v1, <8 x i8> %v2) { 46 %cmp = icmp eq <8 x i8> %v1, %v2 47 ret <8 x i1> %cmp 48 } 49 50 define <2 x i1> @test_v2i64_ne(<2 x i64> %v1, <2 x i64> %v2) { 51 %cmp = icmp ne <2 x i64> %v1, %v2 52 ret <2 x i1> %cmp 53 } 54 55 define <4 x i1> @test_v4i32_ne(<4 x i32> %v1, <4 x i32> %v2) { 56 %cmp = icmp ne <4 x i32> %v1, %v2 57 ret <4 x i1> %cmp 58 } 59 60 define <2 x i1> @test_v2i32_ne(<2 x i32> %v1, <2 x i32> %v2) { 61 %cmp = icmp ne <2 x i32> %v1, %v2 62 ret <2 x i1> %cmp 63 } 64 65 define <2 x i1> @test_v2i16_ne(<2 x i16> %v1, <2 x i16> %v2) { 66 %cmp = icmp ne <2 x i16> %v1, %v2 67 ret <2 x i1> %cmp 68 } 69 70 define <8 x i1> @test_v8i16_ne(<8 x i16> %v1, <8 x i16> %v2) { 71 %cmp = icmp ne <8 x i16> %v1, %v2 72 ret <8 x i1> %cmp 73 } 74 75 define <4 x i1> @test_v4i16_ne(<4 x i16> %v1, <4 x i16> %v2) { 76 %cmp = icmp ne <4 x i16> %v1, %v2 77 ret <4 x i1> %cmp 78 } 79 80 define <16 x i1> @test_v16i8_ne(<16 x i8> %v1, <16 x i8> %v2) { 81 %cmp = icmp ne <16 x i8> %v1, %v2 82 ret <16 x i1> %cmp 83 } 84 85 define <8 x i1> @test_v8i8_ne(<8 x i8> %v1, <8 x i8> %v2) { 86 %cmp = icmp ne <8 x i8> %v1, %v2 87 ret <8 x i1> %cmp 88 } 89 90 define <2 x i1> @test_v2i64_ugt(<2 x i64> %v1, <2 x i64> %v2) { 91 %cmp = icmp ugt <2 x i64> %v1, %v2 92 ret <2 x i1> %cmp 93 } 94 95 define <4 x i1> @test_v4i32_ugt(<4 x i32> %v1, <4 x i32> %v2) { 96 %cmp = icmp ugt <4 x i32> %v1, %v2 97 ret <4 x i1> %cmp 98 } 99 100 define <2 x i1> @test_v2i32_ugt(<2 x i32> %v1, <2 x i32> %v2) { 101 %cmp = icmp ugt <2 x i32> %v1, %v2 102 ret <2 x i1> %cmp 103 } 104 105 define <2 x i1> @test_v2i16_ugt(<2 x i16> %v1, <2 x i16> %v2) { 106 %cmp = icmp ugt <2 x i16> %v1, %v2 107 ret <2 x i1> %cmp 108 } 109 110 define <8 x i1> @test_v8i16_ugt(<8 x i16> %v1, <8 x i16> %v2) { 111 %cmp = icmp ugt <8 x i16> %v1, %v2 112 ret <8 x i1> %cmp 113 } 114 115 define <4 x i1> @test_v4i16_ugt(<4 x i16> %v1, <4 x i16> %v2) { 116 %cmp = icmp ugt <4 x i16> %v1, %v2 117 ret <4 x i1> %cmp 118 } 119 120 define <16 x i1> @test_v16i8_ugt(<16 x i8> %v1, <16 x i8> %v2) { 121 %cmp = icmp ugt <16 x i8> %v1, %v2 122 ret <16 x i1> %cmp 123 } 124 125 define <8 x i1> @test_v8i8_ugt(<8 x i8> %v1, <8 x i8> %v2) { 126 %cmp = icmp ugt <8 x i8> %v1, %v2 127 ret <8 x i1> %cmp 128 } 129 130 define <2 x i1> @test_v2i64_uge(<2 x i64> %v1, <2 x i64> %v2) { 131 %cmp = icmp uge <2 x i64> %v1, %v2 132 ret <2 x i1> %cmp 133 } 134 135 define <4 x i1> @test_v4i32_uge(<4 x i32> %v1, <4 x i32> %v2) { 136 %cmp = icmp uge <4 x i32> %v1, %v2 137 ret <4 x i1> %cmp 138 } 139 140 define <2 x i1> @test_v2i32_uge(<2 x i32> %v1, <2 x i32> %v2) { 141 %cmp = icmp uge <2 x i32> %v1, %v2 142 ret <2 x i1> %cmp 143 } 144 145 define <2 x i1> @test_v2i16_uge(<2 x i16> %v1, <2 x i16> %v2) { 146 %cmp = icmp uge <2 x i16> %v1, %v2 147 ret <2 x i1> %cmp 148 } 149 150 define <8 x i1> @test_v8i16_uge(<8 x i16> %v1, <8 x i16> %v2) { 151 %cmp = icmp uge <8 x i16> %v1, %v2 152 ret <8 x i1> %cmp 153 } 154 155 define <4 x i1> @test_v4i16_uge(<4 x i16> %v1, <4 x i16> %v2) { 156 %cmp = icmp uge <4 x i16> %v1, %v2 157 ret <4 x i1> %cmp 158 } 159 160 define <16 x i1> @test_v16i8_uge(<16 x i8> %v1, <16 x i8> %v2) { 161 %cmp = icmp uge <16 x i8> %v1, %v2 162 ret <16 x i1> %cmp 163 } 164 165 define <8 x i1> @test_v8i8_uge(<8 x i8> %v1, <8 x i8> %v2) { 166 %cmp = icmp uge <8 x i8> %v1, %v2 167 ret <8 x i1> %cmp 168 } 169 170 define <2 x i1> @test_v2i64_ult(<2 x i64> %v1, <2 x i64> %v2) { 171 %cmp = icmp ult <2 x i64> %v1, %v2 172 ret <2 x i1> %cmp 173 } 174 175 define <4 x i1> @test_v4i32_ult(<4 x i32> %v1, <4 x i32> %v2) { 176 %cmp = icmp ult <4 x i32> %v1, %v2 177 ret <4 x i1> %cmp 178 } 179 180 define <2 x i1> @test_v2i32_ult(<2 x i32> %v1, <2 x i32> %v2) { 181 %cmp = icmp ult <2 x i32> %v1, %v2 182 ret <2 x i1> %cmp 183 } 184 185 define <2 x i1> @test_v2i16_ult(<2 x i16> %v1, <2 x i16> %v2) { 186 %cmp = icmp ult <2 x i16> %v1, %v2 187 ret <2 x i1> %cmp 188 } 189 190 define <8 x i1> @test_v8i16_ult(<8 x i16> %v1, <8 x i16> %v2) { 191 %cmp = icmp ult <8 x i16> %v1, %v2 192 ret <8 x i1> %cmp 193 } 194 195 define <4 x i1> @test_v4i16_ult(<4 x i16> %v1, <4 x i16> %v2) { 196 %cmp = icmp ult <4 x i16> %v1, %v2 197 ret <4 x i1> %cmp 198 } 199 200 define <16 x i1> @test_v16i8_ult(<16 x i8> %v1, <16 x i8> %v2) { 201 %cmp = icmp ult <16 x i8> %v1, %v2 202 ret <16 x i1> %cmp 203 } 204 205 define <8 x i1> @test_v8i8_ult(<8 x i8> %v1, <8 x i8> %v2) { 206 %cmp = icmp ult <8 x i8> %v1, %v2 207 ret <8 x i1> %cmp 208 } 209 210 define <2 x i1> @test_v2i64_ule(<2 x i64> %v1, <2 x i64> %v2) { 211 %cmp = icmp ule <2 x i64> %v1, %v2 212 ret <2 x i1> %cmp 213 } 214 215 define <4 x i1> @test_v4i32_ule(<4 x i32> %v1, <4 x i32> %v2) { 216 %cmp = icmp ule <4 x i32> %v1, %v2 217 ret <4 x i1> %cmp 218 } 219 220 define <2 x i1> @test_v2i32_ule(<2 x i32> %v1, <2 x i32> %v2) { 221 %cmp = icmp ule <2 x i32> %v1, %v2 222 ret <2 x i1> %cmp 223 } 224 225 define <2 x i1> @test_v2i16_ule(<2 x i16> %v1, <2 x i16> %v2) { 226 %cmp = icmp ule <2 x i16> %v1, %v2 227 ret <2 x i1> %cmp 228 } 229 230 define <8 x i1> @test_v8i16_ule(<8 x i16> %v1, <8 x i16> %v2) { 231 %cmp = icmp ule <8 x i16> %v1, %v2 232 ret <8 x i1> %cmp 233 } 234 235 define <4 x i1> @test_v4i16_ule(<4 x i16> %v1, <4 x i16> %v2) { 236 %cmp = icmp ule <4 x i16> %v1, %v2 237 ret <4 x i1> %cmp 238 } 239 240 define <16 x i1> @test_v16i8_ule(<16 x i8> %v1, <16 x i8> %v2) { 241 %cmp = icmp ule <16 x i8> %v1, %v2 242 ret <16 x i1> %cmp 243 } 244 245 define <8 x i1> @test_v8i8_ule(<8 x i8> %v1, <8 x i8> %v2) { 246 %cmp = icmp ule <8 x i8> %v1, %v2 247 ret <8 x i1> %cmp 248 } 249 250 define <2 x i1> @test_v2i64_sgt(<2 x i64> %v1, <2 x i64> %v2) { 251 %cmp = icmp sgt <2 x i64> %v1, %v2 252 ret <2 x i1> %cmp 253 } 254 255 define <4 x i1> @test_v4i32_sgt(<4 x i32> %v1, <4 x i32> %v2) { 256 %cmp = icmp sgt <4 x i32> %v1, %v2 257 ret <4 x i1> %cmp 258 } 259 260 define <2 x i1> @test_v2i32_sgt(<2 x i32> %v1, <2 x i32> %v2) { 261 %cmp = icmp sgt <2 x i32> %v1, %v2 262 ret <2 x i1> %cmp 263 } 264 265 define <2 x i1> @test_v2i16_sgt(<2 x i16> %v1, <2 x i16> %v2) { 266 %cmp = icmp sgt <2 x i16> %v1, %v2 267 ret <2 x i1> %cmp 268 } 269 270 define <8 x i1> @test_v8i16_sgt(<8 x i16> %v1, <8 x i16> %v2) { 271 %cmp = icmp sgt <8 x i16> %v1, %v2 272 ret <8 x i1> %cmp 273 } 274 275 define <4 x i1> @test_v4i16_sgt(<4 x i16> %v1, <4 x i16> %v2) { 276 %cmp = icmp sgt <4 x i16> %v1, %v2 277 ret <4 x i1> %cmp 278 } 279 280 define <16 x i1> @test_v16i8_sgt(<16 x i8> %v1, <16 x i8> %v2) { 281 %cmp = icmp sgt <16 x i8> %v1, %v2 282 ret <16 x i1> %cmp 283 } 284 285 define <8 x i1> @test_v8i8_sgt(<8 x i8> %v1, <8 x i8> %v2) { 286 %cmp = icmp sgt <8 x i8> %v1, %v2 287 ret <8 x i1> %cmp 288 } 289 290 define <2 x i1> @test_v2i64_sge(<2 x i64> %v1, <2 x i64> %v2) { 291 %cmp = icmp sge <2 x i64> %v1, %v2 292 ret <2 x i1> %cmp 293 } 294 295 define <4 x i1> @test_v4i32_sge(<4 x i32> %v1, <4 x i32> %v2) { 296 %cmp = icmp sge <4 x i32> %v1, %v2 297 ret <4 x i1> %cmp 298 } 299 300 define <2 x i1> @test_v2i32_sge(<2 x i32> %v1, <2 x i32> %v2) { 301 %cmp = icmp sge <2 x i32> %v1, %v2 302 ret <2 x i1> %cmp 303 } 304 305 define <2 x i1> @test_v2i16_sge(<2 x i16> %v1, <2 x i16> %v2) { 306 %cmp = icmp sge <2 x i16> %v1, %v2 307 ret <2 x i1> %cmp 308 } 309 310 define <8 x i1> @test_v8i16_sge(<8 x i16> %v1, <8 x i16> %v2) { 311 %cmp = icmp sge <8 x i16> %v1, %v2 312 ret <8 x i1> %cmp 313 } 314 315 define <4 x i1> @test_v4i16_sge(<4 x i16> %v1, <4 x i16> %v2) { 316 %cmp = icmp sge <4 x i16> %v1, %v2 317 ret <4 x i1> %cmp 318 } 319 320 define <16 x i1> @test_v16i8_sge(<16 x i8> %v1, <16 x i8> %v2) { 321 %cmp = icmp sge <16 x i8> %v1, %v2 322 ret <16 x i1> %cmp 323 } 324 325 define <8 x i1> @test_v8i8_sge(<8 x i8> %v1, <8 x i8> %v2) { 326 %cmp = icmp sge <8 x i8> %v1, %v2 327 ret <8 x i1> %cmp 328 } 329 330 define <2 x i1> @test_v2i64_slt(<2 x i64> %v1, <2 x i64> %v2) { 331 %cmp = icmp slt <2 x i64> %v1, %v2 332 ret <2 x i1> %cmp 333 } 334 335 define <4 x i1> @test_v4i32_slt(<4 x i32> %v1, <4 x i32> %v2) { 336 %cmp = icmp slt <4 x i32> %v1, %v2 337 ret <4 x i1> %cmp 338 } 339 340 define <2 x i1> @test_v2i32_slt(<2 x i32> %v1, <2 x i32> %v2) { 341 %cmp = icmp slt <2 x i32> %v1, %v2 342 ret <2 x i1> %cmp 343 } 344 345 define <2 x i1> @test_v2i16_slt(<2 x i16> %v1, <2 x i16> %v2) { 346 %cmp = icmp slt <2 x i16> %v1, %v2 347 ret <2 x i1> %cmp 348 } 349 350 define <8 x i1> @test_v8i16_slt(<8 x i16> %v1, <8 x i16> %v2) { 351 %cmp = icmp slt <8 x i16> %v1, %v2 352 ret <8 x i1> %cmp 353 } 354 355 define <4 x i1> @test_v4i16_slt(<4 x i16> %v1, <4 x i16> %v2) { 356 %cmp = icmp slt <4 x i16> %v1, %v2 357 ret <4 x i1> %cmp 358 } 359 360 define <16 x i1> @test_v16i8_slt(<16 x i8> %v1, <16 x i8> %v2) { 361 %cmp = icmp slt <16 x i8> %v1, %v2 362 ret <16 x i1> %cmp 363 } 364 365 define <8 x i1> @test_v8i8_slt(<8 x i8> %v1, <8 x i8> %v2) { 366 %cmp = icmp slt <8 x i8> %v1, %v2 367 ret <8 x i1> %cmp 368 } 369 370 define <2 x i1> @test_v2i64_sle(<2 x i64> %v1, <2 x i64> %v2) { 371 %cmp = icmp sle <2 x i64> %v1, %v2 372 ret <2 x i1> %cmp 373 } 374 375 define <4 x i1> @test_v4i32_sle(<4 x i32> %v1, <4 x i32> %v2) { 376 %cmp = icmp sle <4 x i32> %v1, %v2 377 ret <4 x i1> %cmp 378 } 379 380 define <2 x i1> @test_v2i32_sle(<2 x i32> %v1, <2 x i32> %v2) { 381 %cmp = icmp sle <2 x i32> %v1, %v2 382 ret <2 x i1> %cmp 383 } 384 385 define <2 x i1> @test_v2i16_sle(<2 x i16> %v1, <2 x i16> %v2) { 386 %cmp = icmp sle <2 x i16> %v1, %v2 387 ret <2 x i1> %cmp 388 } 389 390 define <8 x i1> @test_v8i16_sle(<8 x i16> %v1, <8 x i16> %v2) { 391 %cmp = icmp sle <8 x i16> %v1, %v2 392 ret <8 x i1> %cmp 393 } 394 395 define <4 x i1> @test_v4i16_sle(<4 x i16> %v1, <4 x i16> %v2) { 396 %cmp = icmp sle <4 x i16> %v1, %v2 397 ret <4 x i1> %cmp 398 } 399 400 define <16 x i1> @test_v16i8_sle(<16 x i8> %v1, <16 x i8> %v2) { 401 %cmp = icmp sle <16 x i8> %v1, %v2 402 ret <16 x i1> %cmp 403 } 404 405 define <8 x i1> @test_v8i8_sle(<8 x i8> %v1, <8 x i8> %v2) { 406 %cmp = icmp sle <8 x i8> %v1, %v2 407 ret <8 x i1> %cmp 408 } 409 410... 411--- 412name: test_v2i64_eq 413alignment: 4 414legalized: true 415regBankSelected: true 416tracksRegLiveness: true 417registers: 418 - { id: 0, class: fpr } 419 - { id: 1, class: fpr } 420 - { id: 2, class: _ } 421 - { id: 3, class: fpr } 422 - { id: 4, class: fpr } 423machineFunctionInfo: {} 424body: | 425 bb.1 (%ir-block.0): 426 liveins: $q0, $q1 427 428 ; CHECK-LABEL: name: test_v2i64_eq 429 ; CHECK: liveins: $q0, $q1 430 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 431 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 432 ; CHECK: [[CMEQv2i64_:%[0-9]+]]:fpr128 = CMEQv2i64 [[COPY]], [[COPY1]] 433 ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMEQv2i64_]] 434 ; CHECK: $d0 = COPY [[XTNv2i32_]] 435 ; CHECK: RET_ReallyLR implicit $d0 436 %0:fpr(<2 x s64>) = COPY $q0 437 %1:fpr(<2 x s64>) = COPY $q1 438 %4:fpr(<2 x s64>) = G_ICMP intpred(eq), %0(<2 x s64>), %1 439 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 440 $d0 = COPY %3(<2 x s32>) 441 RET_ReallyLR implicit $d0 442 443... 444--- 445name: test_v4i32_eq 446alignment: 4 447legalized: true 448regBankSelected: true 449tracksRegLiveness: true 450registers: 451 - { id: 0, class: fpr } 452 - { id: 1, class: fpr } 453 - { id: 2, class: _ } 454 - { id: 3, class: fpr } 455 - { id: 4, class: fpr } 456machineFunctionInfo: {} 457body: | 458 bb.1 (%ir-block.0): 459 liveins: $q0, $q1 460 461 ; CHECK-LABEL: name: test_v4i32_eq 462 ; CHECK: liveins: $q0, $q1 463 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 464 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 465 ; CHECK: [[CMEQv4i32_:%[0-9]+]]:fpr128 = CMEQv4i32 [[COPY]], [[COPY1]] 466 ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMEQv4i32_]] 467 ; CHECK: $d0 = COPY [[XTNv4i16_]] 468 ; CHECK: RET_ReallyLR implicit $d0 469 %0:fpr(<4 x s32>) = COPY $q0 470 %1:fpr(<4 x s32>) = COPY $q1 471 %4:fpr(<4 x s32>) = G_ICMP intpred(eq), %0(<4 x s32>), %1 472 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 473 $d0 = COPY %3(<4 x s16>) 474 RET_ReallyLR implicit $d0 475 476... 477--- 478name: test_v2i32_eq 479alignment: 4 480legalized: true 481regBankSelected: true 482tracksRegLiveness: true 483registers: 484 - { id: 0, class: fpr } 485 - { id: 1, class: fpr } 486 - { id: 2, class: _ } 487 - { id: 3, class: fpr } 488 - { id: 4, class: fpr } 489machineFunctionInfo: {} 490body: | 491 bb.1 (%ir-block.0): 492 liveins: $d0, $d1 493 494 ; CHECK-LABEL: name: test_v2i32_eq 495 ; CHECK: liveins: $d0, $d1 496 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 497 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 498 ; CHECK: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[COPY]], [[COPY1]] 499 ; CHECK: $d0 = COPY [[CMEQv2i32_]] 500 ; CHECK: RET_ReallyLR implicit $d0 501 %0:fpr(<2 x s32>) = COPY $d0 502 %1:fpr(<2 x s32>) = COPY $d1 503 %4:fpr(<2 x s32>) = G_ICMP intpred(eq), %0(<2 x s32>), %1 504 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 505 $d0 = COPY %3(<2 x s32>) 506 RET_ReallyLR implicit $d0 507 508... 509--- 510name: test_v2i16_eq 511alignment: 4 512legalized: true 513regBankSelected: true 514tracksRegLiveness: true 515registers: 516 - { id: 0, class: _ } 517 - { id: 1, class: _ } 518 - { id: 2, class: fpr } 519 - { id: 3, class: fpr } 520 - { id: 4, class: _ } 521 - { id: 5, class: fpr } 522 - { id: 6, class: _ } 523 - { id: 7, class: fpr } 524 - { id: 8, class: fpr } 525 - { id: 9, class: fpr } 526 - { id: 10, class: gpr } 527 - { id: 11, class: fpr } 528 - { id: 12, class: fpr } 529 - { id: 13, class: gpr } 530 - { id: 14, class: fpr } 531 - { id: 15, class: fpr } 532machineFunctionInfo: {} 533body: | 534 bb.1 (%ir-block.0): 535 liveins: $d0, $d1 536 537 ; CHECK-LABEL: name: test_v2i16_eq 538 ; CHECK: liveins: $d0, $d1 539 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 540 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 541 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 542 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 543 ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[LDRDui]] 544 ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 545 ; CHECK: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 546 ; CHECK: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[LDRDui1]] 547 ; CHECK: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[ANDv8i8_]], [[ANDv8i8_1]] 548 ; CHECK: $d0 = COPY [[CMEQv2i32_]] 549 ; CHECK: RET_ReallyLR implicit $d0 550 %2:fpr(<2 x s32>) = COPY $d0 551 %3:fpr(<2 x s32>) = COPY $d1 552 %13:gpr(s32) = G_CONSTANT i32 65535 553 %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32) 554 %15:fpr(<2 x s32>) = COPY %2(<2 x s32>) 555 %7:fpr(<2 x s32>) = G_AND %15, %14 556 %10:gpr(s32) = G_CONSTANT i32 65535 557 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 558 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 559 %8:fpr(<2 x s32>) = G_AND %12, %11 560 %9:fpr(<2 x s32>) = G_ICMP intpred(eq), %7(<2 x s32>), %8 561 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 562 $d0 = COPY %5(<2 x s32>) 563 RET_ReallyLR implicit $d0 564 565... 566--- 567name: test_v8i16_eq 568alignment: 4 569legalized: true 570regBankSelected: true 571tracksRegLiveness: true 572registers: 573 - { id: 0, class: fpr } 574 - { id: 1, class: fpr } 575 - { id: 2, class: _ } 576 - { id: 3, class: fpr } 577 - { id: 4, class: fpr } 578machineFunctionInfo: {} 579body: | 580 bb.1 (%ir-block.0): 581 liveins: $q0, $q1 582 583 ; CHECK-LABEL: name: test_v8i16_eq 584 ; CHECK: liveins: $q0, $q1 585 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 586 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 587 ; CHECK: [[CMEQv8i16_:%[0-9]+]]:fpr128 = CMEQv8i16 [[COPY]], [[COPY1]] 588 ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMEQv8i16_]] 589 ; CHECK: $d0 = COPY [[XTNv8i8_]] 590 ; CHECK: RET_ReallyLR implicit $d0 591 %0:fpr(<8 x s16>) = COPY $q0 592 %1:fpr(<8 x s16>) = COPY $q1 593 %4:fpr(<8 x s16>) = G_ICMP intpred(eq), %0(<8 x s16>), %1 594 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 595 $d0 = COPY %3(<8 x s8>) 596 RET_ReallyLR implicit $d0 597 598... 599--- 600name: test_v4i16_eq 601alignment: 4 602legalized: true 603regBankSelected: true 604tracksRegLiveness: true 605registers: 606 - { id: 0, class: fpr } 607 - { id: 1, class: fpr } 608 - { id: 2, class: _ } 609 - { id: 3, class: fpr } 610 - { id: 4, class: fpr } 611machineFunctionInfo: {} 612body: | 613 bb.1 (%ir-block.0): 614 liveins: $d0, $d1 615 616 ; CHECK-LABEL: name: test_v4i16_eq 617 ; CHECK: liveins: $d0, $d1 618 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 619 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 620 ; CHECK: [[CMEQv4i16_:%[0-9]+]]:fpr64 = CMEQv4i16 [[COPY]], [[COPY1]] 621 ; CHECK: $d0 = COPY [[CMEQv4i16_]] 622 ; CHECK: RET_ReallyLR implicit $d0 623 %0:fpr(<4 x s16>) = COPY $d0 624 %1:fpr(<4 x s16>) = COPY $d1 625 %4:fpr(<4 x s16>) = G_ICMP intpred(eq), %0(<4 x s16>), %1 626 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 627 $d0 = COPY %3(<4 x s16>) 628 RET_ReallyLR implicit $d0 629 630... 631--- 632name: test_v16i8_eq 633alignment: 4 634legalized: true 635regBankSelected: true 636tracksRegLiveness: true 637registers: 638 - { id: 0, class: fpr } 639 - { id: 1, class: fpr } 640 - { id: 2, class: _ } 641 - { id: 3, class: fpr } 642 - { id: 4, class: fpr } 643machineFunctionInfo: {} 644body: | 645 bb.1 (%ir-block.0): 646 liveins: $q0, $q1 647 648 ; CHECK-LABEL: name: test_v16i8_eq 649 ; CHECK: liveins: $q0, $q1 650 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 651 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 652 ; CHECK: [[CMEQv16i8_:%[0-9]+]]:fpr128 = CMEQv16i8 [[COPY]], [[COPY1]] 653 ; CHECK: $q0 = COPY [[CMEQv16i8_]] 654 ; CHECK: RET_ReallyLR implicit $q0 655 %0:fpr(<16 x s8>) = COPY $q0 656 %1:fpr(<16 x s8>) = COPY $q1 657 %4:fpr(<16 x s8>) = G_ICMP intpred(eq), %0(<16 x s8>), %1 658 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 659 $q0 = COPY %3(<16 x s8>) 660 RET_ReallyLR implicit $q0 661 662... 663--- 664name: test_v8i8_eq 665alignment: 4 666legalized: true 667regBankSelected: true 668tracksRegLiveness: true 669registers: 670 - { id: 0, class: fpr } 671 - { id: 1, class: fpr } 672 - { id: 2, class: _ } 673 - { id: 3, class: fpr } 674 - { id: 4, class: fpr } 675machineFunctionInfo: {} 676body: | 677 bb.1 (%ir-block.0): 678 liveins: $d0, $d1 679 680 ; CHECK-LABEL: name: test_v8i8_eq 681 ; CHECK: liveins: $d0, $d1 682 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 683 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 684 ; CHECK: [[CMEQv8i8_:%[0-9]+]]:fpr64 = CMEQv8i8 [[COPY]], [[COPY1]] 685 ; CHECK: $d0 = COPY [[CMEQv8i8_]] 686 ; CHECK: RET_ReallyLR implicit $d0 687 %0:fpr(<8 x s8>) = COPY $d0 688 %1:fpr(<8 x s8>) = COPY $d1 689 %4:fpr(<8 x s8>) = G_ICMP intpred(eq), %0(<8 x s8>), %1 690 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 691 $d0 = COPY %3(<8 x s8>) 692 RET_ReallyLR implicit $d0 693 694... 695--- 696name: test_v2i64_ne 697alignment: 4 698legalized: true 699regBankSelected: true 700tracksRegLiveness: true 701registers: 702 - { id: 0, class: fpr } 703 - { id: 1, class: fpr } 704 - { id: 2, class: _ } 705 - { id: 3, class: fpr } 706 - { id: 4, class: fpr } 707machineFunctionInfo: {} 708body: | 709 bb.1 (%ir-block.0): 710 liveins: $q0, $q1 711 712 ; CHECK-LABEL: name: test_v2i64_ne 713 ; CHECK: liveins: $q0, $q1 714 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 715 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 716 ; CHECK: [[CMEQv2i64_:%[0-9]+]]:fpr128 = CMEQv2i64 [[COPY]], [[COPY1]] 717 ; CHECK: [[NOTv16i8_:%[0-9]+]]:fpr128 = NOTv16i8 [[CMEQv2i64_]] 718 ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[NOTv16i8_]] 719 ; CHECK: $d0 = COPY [[XTNv2i32_]] 720 ; CHECK: RET_ReallyLR implicit $d0 721 %0:fpr(<2 x s64>) = COPY $q0 722 %1:fpr(<2 x s64>) = COPY $q1 723 %4:fpr(<2 x s64>) = G_ICMP intpred(ne), %0(<2 x s64>), %1 724 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 725 $d0 = COPY %3(<2 x s32>) 726 RET_ReallyLR implicit $d0 727 728... 729--- 730name: test_v4i32_ne 731alignment: 4 732legalized: true 733regBankSelected: true 734tracksRegLiveness: true 735registers: 736 - { id: 0, class: fpr } 737 - { id: 1, class: fpr } 738 - { id: 2, class: _ } 739 - { id: 3, class: fpr } 740 - { id: 4, class: fpr } 741machineFunctionInfo: {} 742body: | 743 bb.1 (%ir-block.0): 744 liveins: $q0, $q1 745 746 ; CHECK-LABEL: name: test_v4i32_ne 747 ; CHECK: liveins: $q0, $q1 748 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 749 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 750 ; CHECK: [[CMEQv4i32_:%[0-9]+]]:fpr128 = CMEQv4i32 [[COPY]], [[COPY1]] 751 ; CHECK: [[NOTv16i8_:%[0-9]+]]:fpr128 = NOTv16i8 [[CMEQv4i32_]] 752 ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[NOTv16i8_]] 753 ; CHECK: $d0 = COPY [[XTNv4i16_]] 754 ; CHECK: RET_ReallyLR implicit $d0 755 %0:fpr(<4 x s32>) = COPY $q0 756 %1:fpr(<4 x s32>) = COPY $q1 757 %4:fpr(<4 x s32>) = G_ICMP intpred(ne), %0(<4 x s32>), %1 758 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 759 $d0 = COPY %3(<4 x s16>) 760 RET_ReallyLR implicit $d0 761 762... 763--- 764name: test_v2i32_ne 765alignment: 4 766legalized: true 767regBankSelected: true 768tracksRegLiveness: true 769registers: 770 - { id: 0, class: fpr } 771 - { id: 1, class: fpr } 772 - { id: 2, class: _ } 773 - { id: 3, class: fpr } 774 - { id: 4, class: fpr } 775machineFunctionInfo: {} 776body: | 777 bb.1 (%ir-block.0): 778 liveins: $d0, $d1 779 780 ; CHECK-LABEL: name: test_v2i32_ne 781 ; CHECK: liveins: $d0, $d1 782 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 783 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 784 ; CHECK: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[COPY]], [[COPY1]] 785 ; CHECK: [[NOTv8i8_:%[0-9]+]]:fpr64 = NOTv8i8 [[CMEQv2i32_]] 786 ; CHECK: $d0 = COPY [[NOTv8i8_]] 787 ; CHECK: RET_ReallyLR implicit $d0 788 %0:fpr(<2 x s32>) = COPY $d0 789 %1:fpr(<2 x s32>) = COPY $d1 790 %4:fpr(<2 x s32>) = G_ICMP intpred(ne), %0(<2 x s32>), %1 791 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 792 $d0 = COPY %3(<2 x s32>) 793 RET_ReallyLR implicit $d0 794 795... 796--- 797name: test_v2i16_ne 798alignment: 4 799legalized: true 800regBankSelected: true 801tracksRegLiveness: true 802registers: 803 - { id: 0, class: _ } 804 - { id: 1, class: _ } 805 - { id: 2, class: fpr } 806 - { id: 3, class: fpr } 807 - { id: 4, class: _ } 808 - { id: 5, class: fpr } 809 - { id: 6, class: _ } 810 - { id: 7, class: fpr } 811 - { id: 8, class: fpr } 812 - { id: 9, class: fpr } 813 - { id: 10, class: gpr } 814 - { id: 11, class: fpr } 815 - { id: 12, class: fpr } 816 - { id: 13, class: gpr } 817 - { id: 14, class: fpr } 818 - { id: 15, class: fpr } 819machineFunctionInfo: {} 820body: | 821 bb.1 (%ir-block.0): 822 liveins: $d0, $d1 823 824 ; CHECK-LABEL: name: test_v2i16_ne 825 ; CHECK: liveins: $d0, $d1 826 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 827 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 828 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 829 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 830 ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[LDRDui]] 831 ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 832 ; CHECK: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 833 ; CHECK: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[LDRDui1]] 834 ; CHECK: [[CMEQv2i32_:%[0-9]+]]:fpr64 = CMEQv2i32 [[ANDv8i8_]], [[ANDv8i8_1]] 835 ; CHECK: [[NOTv8i8_:%[0-9]+]]:fpr64 = NOTv8i8 [[CMEQv2i32_]] 836 ; CHECK: $d0 = COPY [[NOTv8i8_]] 837 ; CHECK: RET_ReallyLR implicit $d0 838 %2:fpr(<2 x s32>) = COPY $d0 839 %3:fpr(<2 x s32>) = COPY $d1 840 %13:gpr(s32) = G_CONSTANT i32 65535 841 %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32) 842 %15:fpr(<2 x s32>) = COPY %2(<2 x s32>) 843 %7:fpr(<2 x s32>) = G_AND %15, %14 844 %10:gpr(s32) = G_CONSTANT i32 65535 845 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 846 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 847 %8:fpr(<2 x s32>) = G_AND %12, %11 848 %9:fpr(<2 x s32>) = G_ICMP intpred(ne), %7(<2 x s32>), %8 849 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 850 $d0 = COPY %5(<2 x s32>) 851 RET_ReallyLR implicit $d0 852 853... 854--- 855name: test_v8i16_ne 856alignment: 4 857legalized: true 858regBankSelected: true 859tracksRegLiveness: true 860registers: 861 - { id: 0, class: fpr } 862 - { id: 1, class: fpr } 863 - { id: 2, class: _ } 864 - { id: 3, class: fpr } 865 - { id: 4, class: fpr } 866machineFunctionInfo: {} 867body: | 868 bb.1 (%ir-block.0): 869 liveins: $q0, $q1 870 871 ; CHECK-LABEL: name: test_v8i16_ne 872 ; CHECK: liveins: $q0, $q1 873 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 874 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 875 ; CHECK: [[CMEQv8i16_:%[0-9]+]]:fpr128 = CMEQv8i16 [[COPY]], [[COPY1]] 876 ; CHECK: [[NOTv16i8_:%[0-9]+]]:fpr128 = NOTv16i8 [[CMEQv8i16_]] 877 ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[NOTv16i8_]] 878 ; CHECK: $d0 = COPY [[XTNv8i8_]] 879 ; CHECK: RET_ReallyLR implicit $d0 880 %0:fpr(<8 x s16>) = COPY $q0 881 %1:fpr(<8 x s16>) = COPY $q1 882 %4:fpr(<8 x s16>) = G_ICMP intpred(ne), %0(<8 x s16>), %1 883 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 884 $d0 = COPY %3(<8 x s8>) 885 RET_ReallyLR implicit $d0 886 887... 888--- 889name: test_v4i16_ne 890alignment: 4 891legalized: true 892regBankSelected: true 893tracksRegLiveness: true 894registers: 895 - { id: 0, class: fpr } 896 - { id: 1, class: fpr } 897 - { id: 2, class: _ } 898 - { id: 3, class: fpr } 899 - { id: 4, class: fpr } 900machineFunctionInfo: {} 901body: | 902 bb.1 (%ir-block.0): 903 liveins: $d0, $d1 904 905 ; CHECK-LABEL: name: test_v4i16_ne 906 ; CHECK: liveins: $d0, $d1 907 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 908 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 909 ; CHECK: [[CMEQv4i16_:%[0-9]+]]:fpr64 = CMEQv4i16 [[COPY]], [[COPY1]] 910 ; CHECK: [[NOTv8i8_:%[0-9]+]]:fpr64 = NOTv8i8 [[CMEQv4i16_]] 911 ; CHECK: $d0 = COPY [[NOTv8i8_]] 912 ; CHECK: RET_ReallyLR implicit $d0 913 %0:fpr(<4 x s16>) = COPY $d0 914 %1:fpr(<4 x s16>) = COPY $d1 915 %4:fpr(<4 x s16>) = G_ICMP intpred(ne), %0(<4 x s16>), %1 916 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 917 $d0 = COPY %3(<4 x s16>) 918 RET_ReallyLR implicit $d0 919 920... 921--- 922name: test_v16i8_ne 923alignment: 4 924legalized: true 925regBankSelected: true 926tracksRegLiveness: true 927registers: 928 - { id: 0, class: fpr } 929 - { id: 1, class: fpr } 930 - { id: 2, class: _ } 931 - { id: 3, class: fpr } 932 - { id: 4, class: fpr } 933machineFunctionInfo: {} 934body: | 935 bb.1 (%ir-block.0): 936 liveins: $q0, $q1 937 938 ; CHECK-LABEL: name: test_v16i8_ne 939 ; CHECK: liveins: $q0, $q1 940 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 941 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 942 ; CHECK: [[CMEQv16i8_:%[0-9]+]]:fpr128 = CMEQv16i8 [[COPY]], [[COPY1]] 943 ; CHECK: [[NOTv16i8_:%[0-9]+]]:fpr128 = NOTv16i8 [[CMEQv16i8_]] 944 ; CHECK: $q0 = COPY [[NOTv16i8_]] 945 ; CHECK: RET_ReallyLR implicit $q0 946 %0:fpr(<16 x s8>) = COPY $q0 947 %1:fpr(<16 x s8>) = COPY $q1 948 %4:fpr(<16 x s8>) = G_ICMP intpred(ne), %0(<16 x s8>), %1 949 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 950 $q0 = COPY %3(<16 x s8>) 951 RET_ReallyLR implicit $q0 952 953... 954--- 955name: test_v8i8_ne 956alignment: 4 957legalized: true 958regBankSelected: true 959tracksRegLiveness: true 960registers: 961 - { id: 0, class: fpr } 962 - { id: 1, class: fpr } 963 - { id: 2, class: _ } 964 - { id: 3, class: fpr } 965 - { id: 4, class: fpr } 966machineFunctionInfo: {} 967body: | 968 bb.1 (%ir-block.0): 969 liveins: $d0, $d1 970 971 ; CHECK-LABEL: name: test_v8i8_ne 972 ; CHECK: liveins: $d0, $d1 973 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 974 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 975 ; CHECK: [[CMEQv8i8_:%[0-9]+]]:fpr64 = CMEQv8i8 [[COPY]], [[COPY1]] 976 ; CHECK: [[NOTv8i8_:%[0-9]+]]:fpr64 = NOTv8i8 [[CMEQv8i8_]] 977 ; CHECK: $d0 = COPY [[NOTv8i8_]] 978 ; CHECK: RET_ReallyLR implicit $d0 979 %0:fpr(<8 x s8>) = COPY $d0 980 %1:fpr(<8 x s8>) = COPY $d1 981 %4:fpr(<8 x s8>) = G_ICMP intpred(ne), %0(<8 x s8>), %1 982 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 983 $d0 = COPY %3(<8 x s8>) 984 RET_ReallyLR implicit $d0 985 986... 987--- 988name: test_v2i64_ugt 989alignment: 4 990legalized: true 991regBankSelected: true 992tracksRegLiveness: true 993registers: 994 - { id: 0, class: fpr } 995 - { id: 1, class: fpr } 996 - { id: 2, class: _ } 997 - { id: 3, class: fpr } 998 - { id: 4, class: fpr } 999machineFunctionInfo: {} 1000body: | 1001 bb.1 (%ir-block.0): 1002 liveins: $q0, $q1 1003 1004 ; CHECK-LABEL: name: test_v2i64_ugt 1005 ; CHECK: liveins: $q0, $q1 1006 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1007 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1008 ; CHECK: [[CMHIv2i64_:%[0-9]+]]:fpr128 = CMHIv2i64 [[COPY]], [[COPY1]] 1009 ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHIv2i64_]] 1010 ; CHECK: $d0 = COPY [[XTNv2i32_]] 1011 ; CHECK: RET_ReallyLR implicit $d0 1012 %0:fpr(<2 x s64>) = COPY $q0 1013 %1:fpr(<2 x s64>) = COPY $q1 1014 %4:fpr(<2 x s64>) = G_ICMP intpred(ugt), %0(<2 x s64>), %1 1015 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 1016 $d0 = COPY %3(<2 x s32>) 1017 RET_ReallyLR implicit $d0 1018 1019... 1020--- 1021name: test_v4i32_ugt 1022alignment: 4 1023legalized: true 1024regBankSelected: true 1025tracksRegLiveness: true 1026registers: 1027 - { id: 0, class: fpr } 1028 - { id: 1, class: fpr } 1029 - { id: 2, class: _ } 1030 - { id: 3, class: fpr } 1031 - { id: 4, class: fpr } 1032machineFunctionInfo: {} 1033body: | 1034 bb.1 (%ir-block.0): 1035 liveins: $q0, $q1 1036 1037 ; CHECK-LABEL: name: test_v4i32_ugt 1038 ; CHECK: liveins: $q0, $q1 1039 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1040 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1041 ; CHECK: [[CMHIv4i32_:%[0-9]+]]:fpr128 = CMHIv4i32 [[COPY]], [[COPY1]] 1042 ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHIv4i32_]] 1043 ; CHECK: $d0 = COPY [[XTNv4i16_]] 1044 ; CHECK: RET_ReallyLR implicit $d0 1045 %0:fpr(<4 x s32>) = COPY $q0 1046 %1:fpr(<4 x s32>) = COPY $q1 1047 %4:fpr(<4 x s32>) = G_ICMP intpred(ugt), %0(<4 x s32>), %1 1048 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 1049 $d0 = COPY %3(<4 x s16>) 1050 RET_ReallyLR implicit $d0 1051 1052... 1053--- 1054name: test_v2i32_ugt 1055alignment: 4 1056legalized: true 1057regBankSelected: true 1058tracksRegLiveness: true 1059registers: 1060 - { id: 0, class: fpr } 1061 - { id: 1, class: fpr } 1062 - { id: 2, class: _ } 1063 - { id: 3, class: fpr } 1064 - { id: 4, class: fpr } 1065machineFunctionInfo: {} 1066body: | 1067 bb.1 (%ir-block.0): 1068 liveins: $d0, $d1 1069 1070 ; CHECK-LABEL: name: test_v2i32_ugt 1071 ; CHECK: liveins: $d0, $d1 1072 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1073 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1074 ; CHECK: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[COPY]], [[COPY1]] 1075 ; CHECK: $d0 = COPY [[CMHIv2i32_]] 1076 ; CHECK: RET_ReallyLR implicit $d0 1077 %0:fpr(<2 x s32>) = COPY $d0 1078 %1:fpr(<2 x s32>) = COPY $d1 1079 %4:fpr(<2 x s32>) = G_ICMP intpred(ugt), %0(<2 x s32>), %1 1080 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 1081 $d0 = COPY %3(<2 x s32>) 1082 RET_ReallyLR implicit $d0 1083 1084... 1085--- 1086name: test_v2i16_ugt 1087alignment: 4 1088legalized: true 1089regBankSelected: true 1090tracksRegLiveness: true 1091registers: 1092 - { id: 0, class: _ } 1093 - { id: 1, class: _ } 1094 - { id: 2, class: fpr } 1095 - { id: 3, class: fpr } 1096 - { id: 4, class: _ } 1097 - { id: 5, class: fpr } 1098 - { id: 6, class: _ } 1099 - { id: 7, class: fpr } 1100 - { id: 8, class: fpr } 1101 - { id: 9, class: fpr } 1102 - { id: 10, class: gpr } 1103 - { id: 11, class: fpr } 1104 - { id: 12, class: fpr } 1105 - { id: 13, class: gpr } 1106 - { id: 14, class: fpr } 1107 - { id: 15, class: fpr } 1108machineFunctionInfo: {} 1109body: | 1110 bb.1 (%ir-block.0): 1111 liveins: $d0, $d1 1112 1113 ; CHECK-LABEL: name: test_v2i16_ugt 1114 ; CHECK: liveins: $d0, $d1 1115 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1116 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1117 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 1118 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 1119 ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[LDRDui]] 1120 ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 1121 ; CHECK: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 1122 ; CHECK: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[LDRDui1]] 1123 ; CHECK: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[ANDv8i8_]], [[ANDv8i8_1]] 1124 ; CHECK: $d0 = COPY [[CMHIv2i32_]] 1125 ; CHECK: RET_ReallyLR implicit $d0 1126 %2:fpr(<2 x s32>) = COPY $d0 1127 %3:fpr(<2 x s32>) = COPY $d1 1128 %13:gpr(s32) = G_CONSTANT i32 65535 1129 %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32) 1130 %15:fpr(<2 x s32>) = COPY %2(<2 x s32>) 1131 %7:fpr(<2 x s32>) = G_AND %15, %14 1132 %10:gpr(s32) = G_CONSTANT i32 65535 1133 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 1134 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 1135 %8:fpr(<2 x s32>) = G_AND %12, %11 1136 %9:fpr(<2 x s32>) = G_ICMP intpred(ugt), %7(<2 x s32>), %8 1137 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 1138 $d0 = COPY %5(<2 x s32>) 1139 RET_ReallyLR implicit $d0 1140 1141... 1142--- 1143name: test_v8i16_ugt 1144alignment: 4 1145legalized: true 1146regBankSelected: true 1147tracksRegLiveness: true 1148registers: 1149 - { id: 0, class: fpr } 1150 - { id: 1, class: fpr } 1151 - { id: 2, class: _ } 1152 - { id: 3, class: fpr } 1153 - { id: 4, class: fpr } 1154machineFunctionInfo: {} 1155body: | 1156 bb.1 (%ir-block.0): 1157 liveins: $q0, $q1 1158 1159 ; CHECK-LABEL: name: test_v8i16_ugt 1160 ; CHECK: liveins: $q0, $q1 1161 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1162 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1163 ; CHECK: [[CMHIv8i16_:%[0-9]+]]:fpr128 = CMHIv8i16 [[COPY]], [[COPY1]] 1164 ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHIv8i16_]] 1165 ; CHECK: $d0 = COPY [[XTNv8i8_]] 1166 ; CHECK: RET_ReallyLR implicit $d0 1167 %0:fpr(<8 x s16>) = COPY $q0 1168 %1:fpr(<8 x s16>) = COPY $q1 1169 %4:fpr(<8 x s16>) = G_ICMP intpred(ugt), %0(<8 x s16>), %1 1170 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 1171 $d0 = COPY %3(<8 x s8>) 1172 RET_ReallyLR implicit $d0 1173 1174... 1175--- 1176name: test_v4i16_ugt 1177alignment: 4 1178legalized: true 1179regBankSelected: true 1180tracksRegLiveness: true 1181registers: 1182 - { id: 0, class: fpr } 1183 - { id: 1, class: fpr } 1184 - { id: 2, class: _ } 1185 - { id: 3, class: fpr } 1186 - { id: 4, class: fpr } 1187machineFunctionInfo: {} 1188body: | 1189 bb.1 (%ir-block.0): 1190 liveins: $d0, $d1 1191 1192 ; CHECK-LABEL: name: test_v4i16_ugt 1193 ; CHECK: liveins: $d0, $d1 1194 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1195 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1196 ; CHECK: [[CMHIv4i16_:%[0-9]+]]:fpr64 = CMHIv4i16 [[COPY]], [[COPY1]] 1197 ; CHECK: $d0 = COPY [[CMHIv4i16_]] 1198 ; CHECK: RET_ReallyLR implicit $d0 1199 %0:fpr(<4 x s16>) = COPY $d0 1200 %1:fpr(<4 x s16>) = COPY $d1 1201 %4:fpr(<4 x s16>) = G_ICMP intpred(ugt), %0(<4 x s16>), %1 1202 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 1203 $d0 = COPY %3(<4 x s16>) 1204 RET_ReallyLR implicit $d0 1205 1206... 1207--- 1208name: test_v16i8_ugt 1209alignment: 4 1210legalized: true 1211regBankSelected: true 1212tracksRegLiveness: true 1213registers: 1214 - { id: 0, class: fpr } 1215 - { id: 1, class: fpr } 1216 - { id: 2, class: _ } 1217 - { id: 3, class: fpr } 1218 - { id: 4, class: fpr } 1219machineFunctionInfo: {} 1220body: | 1221 bb.1 (%ir-block.0): 1222 liveins: $q0, $q1 1223 1224 ; CHECK-LABEL: name: test_v16i8_ugt 1225 ; CHECK: liveins: $q0, $q1 1226 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1227 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1228 ; CHECK: [[CMHIv16i8_:%[0-9]+]]:fpr128 = CMHIv16i8 [[COPY]], [[COPY1]] 1229 ; CHECK: $q0 = COPY [[CMHIv16i8_]] 1230 ; CHECK: RET_ReallyLR implicit $q0 1231 %0:fpr(<16 x s8>) = COPY $q0 1232 %1:fpr(<16 x s8>) = COPY $q1 1233 %4:fpr(<16 x s8>) = G_ICMP intpred(ugt), %0(<16 x s8>), %1 1234 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 1235 $q0 = COPY %3(<16 x s8>) 1236 RET_ReallyLR implicit $q0 1237 1238... 1239--- 1240name: test_v8i8_ugt 1241alignment: 4 1242legalized: true 1243regBankSelected: true 1244tracksRegLiveness: true 1245registers: 1246 - { id: 0, class: fpr } 1247 - { id: 1, class: fpr } 1248 - { id: 2, class: _ } 1249 - { id: 3, class: fpr } 1250 - { id: 4, class: fpr } 1251machineFunctionInfo: {} 1252body: | 1253 bb.1 (%ir-block.0): 1254 liveins: $d0, $d1 1255 1256 ; CHECK-LABEL: name: test_v8i8_ugt 1257 ; CHECK: liveins: $d0, $d1 1258 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1259 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1260 ; CHECK: [[CMHIv8i8_:%[0-9]+]]:fpr64 = CMHIv8i8 [[COPY]], [[COPY1]] 1261 ; CHECK: $d0 = COPY [[CMHIv8i8_]] 1262 ; CHECK: RET_ReallyLR implicit $d0 1263 %0:fpr(<8 x s8>) = COPY $d0 1264 %1:fpr(<8 x s8>) = COPY $d1 1265 %4:fpr(<8 x s8>) = G_ICMP intpred(ugt), %0(<8 x s8>), %1 1266 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 1267 $d0 = COPY %3(<8 x s8>) 1268 RET_ReallyLR implicit $d0 1269 1270... 1271--- 1272name: test_v2i64_uge 1273alignment: 4 1274legalized: true 1275regBankSelected: true 1276tracksRegLiveness: true 1277registers: 1278 - { id: 0, class: fpr } 1279 - { id: 1, class: fpr } 1280 - { id: 2, class: _ } 1281 - { id: 3, class: fpr } 1282 - { id: 4, class: fpr } 1283machineFunctionInfo: {} 1284body: | 1285 bb.1 (%ir-block.0): 1286 liveins: $q0, $q1 1287 1288 ; CHECK-LABEL: name: test_v2i64_uge 1289 ; CHECK: liveins: $q0, $q1 1290 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1291 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1292 ; CHECK: [[CMHSv2i64_:%[0-9]+]]:fpr128 = CMHSv2i64 [[COPY]], [[COPY1]] 1293 ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHSv2i64_]] 1294 ; CHECK: $d0 = COPY [[XTNv2i32_]] 1295 ; CHECK: RET_ReallyLR implicit $d0 1296 %0:fpr(<2 x s64>) = COPY $q0 1297 %1:fpr(<2 x s64>) = COPY $q1 1298 %4:fpr(<2 x s64>) = G_ICMP intpred(uge), %0(<2 x s64>), %1 1299 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 1300 $d0 = COPY %3(<2 x s32>) 1301 RET_ReallyLR implicit $d0 1302 1303... 1304--- 1305name: test_v4i32_uge 1306alignment: 4 1307legalized: true 1308regBankSelected: true 1309tracksRegLiveness: true 1310registers: 1311 - { id: 0, class: fpr } 1312 - { id: 1, class: fpr } 1313 - { id: 2, class: _ } 1314 - { id: 3, class: fpr } 1315 - { id: 4, class: fpr } 1316machineFunctionInfo: {} 1317body: | 1318 bb.1 (%ir-block.0): 1319 liveins: $q0, $q1 1320 1321 ; CHECK-LABEL: name: test_v4i32_uge 1322 ; CHECK: liveins: $q0, $q1 1323 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1324 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1325 ; CHECK: [[CMHSv4i32_:%[0-9]+]]:fpr128 = CMHSv4i32 [[COPY]], [[COPY1]] 1326 ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHSv4i32_]] 1327 ; CHECK: $d0 = COPY [[XTNv4i16_]] 1328 ; CHECK: RET_ReallyLR implicit $d0 1329 %0:fpr(<4 x s32>) = COPY $q0 1330 %1:fpr(<4 x s32>) = COPY $q1 1331 %4:fpr(<4 x s32>) = G_ICMP intpred(uge), %0(<4 x s32>), %1 1332 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 1333 $d0 = COPY %3(<4 x s16>) 1334 RET_ReallyLR implicit $d0 1335 1336... 1337--- 1338name: test_v2i32_uge 1339alignment: 4 1340legalized: true 1341regBankSelected: true 1342tracksRegLiveness: true 1343registers: 1344 - { id: 0, class: fpr } 1345 - { id: 1, class: fpr } 1346 - { id: 2, class: _ } 1347 - { id: 3, class: fpr } 1348 - { id: 4, class: fpr } 1349machineFunctionInfo: {} 1350body: | 1351 bb.1 (%ir-block.0): 1352 liveins: $d0, $d1 1353 1354 ; CHECK-LABEL: name: test_v2i32_uge 1355 ; CHECK: liveins: $d0, $d1 1356 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1357 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1358 ; CHECK: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[COPY]], [[COPY1]] 1359 ; CHECK: $d0 = COPY [[CMHSv2i32_]] 1360 ; CHECK: RET_ReallyLR implicit $d0 1361 %0:fpr(<2 x s32>) = COPY $d0 1362 %1:fpr(<2 x s32>) = COPY $d1 1363 %4:fpr(<2 x s32>) = G_ICMP intpred(uge), %0(<2 x s32>), %1 1364 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 1365 $d0 = COPY %3(<2 x s32>) 1366 RET_ReallyLR implicit $d0 1367 1368... 1369--- 1370name: test_v2i16_uge 1371alignment: 4 1372legalized: true 1373regBankSelected: true 1374tracksRegLiveness: true 1375registers: 1376 - { id: 0, class: _ } 1377 - { id: 1, class: _ } 1378 - { id: 2, class: fpr } 1379 - { id: 3, class: fpr } 1380 - { id: 4, class: _ } 1381 - { id: 5, class: fpr } 1382 - { id: 6, class: _ } 1383 - { id: 7, class: fpr } 1384 - { id: 8, class: fpr } 1385 - { id: 9, class: fpr } 1386 - { id: 10, class: gpr } 1387 - { id: 11, class: fpr } 1388 - { id: 12, class: fpr } 1389 - { id: 13, class: gpr } 1390 - { id: 14, class: fpr } 1391 - { id: 15, class: fpr } 1392machineFunctionInfo: {} 1393body: | 1394 bb.1 (%ir-block.0): 1395 liveins: $d0, $d1 1396 1397 ; CHECK-LABEL: name: test_v2i16_uge 1398 ; CHECK: liveins: $d0, $d1 1399 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1400 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1401 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 1402 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 1403 ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[LDRDui]] 1404 ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 1405 ; CHECK: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 1406 ; CHECK: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[LDRDui1]] 1407 ; CHECK: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[ANDv8i8_]], [[ANDv8i8_1]] 1408 ; CHECK: $d0 = COPY [[CMHSv2i32_]] 1409 ; CHECK: RET_ReallyLR implicit $d0 1410 %2:fpr(<2 x s32>) = COPY $d0 1411 %3:fpr(<2 x s32>) = COPY $d1 1412 %13:gpr(s32) = G_CONSTANT i32 65535 1413 %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32) 1414 %15:fpr(<2 x s32>) = COPY %2(<2 x s32>) 1415 %7:fpr(<2 x s32>) = G_AND %15, %14 1416 %10:gpr(s32) = G_CONSTANT i32 65535 1417 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 1418 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 1419 %8:fpr(<2 x s32>) = G_AND %12, %11 1420 %9:fpr(<2 x s32>) = G_ICMP intpred(uge), %7(<2 x s32>), %8 1421 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 1422 $d0 = COPY %5(<2 x s32>) 1423 RET_ReallyLR implicit $d0 1424 1425... 1426--- 1427name: test_v8i16_uge 1428alignment: 4 1429legalized: true 1430regBankSelected: true 1431tracksRegLiveness: true 1432registers: 1433 - { id: 0, class: fpr } 1434 - { id: 1, class: fpr } 1435 - { id: 2, class: _ } 1436 - { id: 3, class: fpr } 1437 - { id: 4, class: fpr } 1438machineFunctionInfo: {} 1439body: | 1440 bb.1 (%ir-block.0): 1441 liveins: $q0, $q1 1442 1443 ; CHECK-LABEL: name: test_v8i16_uge 1444 ; CHECK: liveins: $q0, $q1 1445 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1446 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1447 ; CHECK: [[CMHSv8i16_:%[0-9]+]]:fpr128 = CMHSv8i16 [[COPY]], [[COPY1]] 1448 ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHSv8i16_]] 1449 ; CHECK: $d0 = COPY [[XTNv8i8_]] 1450 ; CHECK: RET_ReallyLR implicit $d0 1451 %0:fpr(<8 x s16>) = COPY $q0 1452 %1:fpr(<8 x s16>) = COPY $q1 1453 %4:fpr(<8 x s16>) = G_ICMP intpred(uge), %0(<8 x s16>), %1 1454 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 1455 $d0 = COPY %3(<8 x s8>) 1456 RET_ReallyLR implicit $d0 1457 1458... 1459--- 1460name: test_v4i16_uge 1461alignment: 4 1462legalized: true 1463regBankSelected: true 1464tracksRegLiveness: true 1465registers: 1466 - { id: 0, class: fpr } 1467 - { id: 1, class: fpr } 1468 - { id: 2, class: _ } 1469 - { id: 3, class: fpr } 1470 - { id: 4, class: fpr } 1471machineFunctionInfo: {} 1472body: | 1473 bb.1 (%ir-block.0): 1474 liveins: $d0, $d1 1475 1476 ; CHECK-LABEL: name: test_v4i16_uge 1477 ; CHECK: liveins: $d0, $d1 1478 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1479 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1480 ; CHECK: [[CMHSv4i16_:%[0-9]+]]:fpr64 = CMHSv4i16 [[COPY]], [[COPY1]] 1481 ; CHECK: $d0 = COPY [[CMHSv4i16_]] 1482 ; CHECK: RET_ReallyLR implicit $d0 1483 %0:fpr(<4 x s16>) = COPY $d0 1484 %1:fpr(<4 x s16>) = COPY $d1 1485 %4:fpr(<4 x s16>) = G_ICMP intpred(uge), %0(<4 x s16>), %1 1486 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 1487 $d0 = COPY %3(<4 x s16>) 1488 RET_ReallyLR implicit $d0 1489 1490... 1491--- 1492name: test_v16i8_uge 1493alignment: 4 1494legalized: true 1495regBankSelected: true 1496tracksRegLiveness: true 1497registers: 1498 - { id: 0, class: fpr } 1499 - { id: 1, class: fpr } 1500 - { id: 2, class: _ } 1501 - { id: 3, class: fpr } 1502 - { id: 4, class: fpr } 1503machineFunctionInfo: {} 1504body: | 1505 bb.1 (%ir-block.0): 1506 liveins: $q0, $q1 1507 1508 ; CHECK-LABEL: name: test_v16i8_uge 1509 ; CHECK: liveins: $q0, $q1 1510 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1511 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1512 ; CHECK: [[CMHSv16i8_:%[0-9]+]]:fpr128 = CMHSv16i8 [[COPY]], [[COPY1]] 1513 ; CHECK: $q0 = COPY [[CMHSv16i8_]] 1514 ; CHECK: RET_ReallyLR implicit $q0 1515 %0:fpr(<16 x s8>) = COPY $q0 1516 %1:fpr(<16 x s8>) = COPY $q1 1517 %4:fpr(<16 x s8>) = G_ICMP intpred(uge), %0(<16 x s8>), %1 1518 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 1519 $q0 = COPY %3(<16 x s8>) 1520 RET_ReallyLR implicit $q0 1521 1522... 1523--- 1524name: test_v8i8_uge 1525alignment: 4 1526legalized: true 1527regBankSelected: true 1528tracksRegLiveness: true 1529registers: 1530 - { id: 0, class: fpr } 1531 - { id: 1, class: fpr } 1532 - { id: 2, class: _ } 1533 - { id: 3, class: fpr } 1534 - { id: 4, class: fpr } 1535machineFunctionInfo: {} 1536body: | 1537 bb.1 (%ir-block.0): 1538 liveins: $d0, $d1 1539 1540 ; CHECK-LABEL: name: test_v8i8_uge 1541 ; CHECK: liveins: $d0, $d1 1542 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1543 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1544 ; CHECK: [[CMHSv8i8_:%[0-9]+]]:fpr64 = CMHSv8i8 [[COPY]], [[COPY1]] 1545 ; CHECK: $d0 = COPY [[CMHSv8i8_]] 1546 ; CHECK: RET_ReallyLR implicit $d0 1547 %0:fpr(<8 x s8>) = COPY $d0 1548 %1:fpr(<8 x s8>) = COPY $d1 1549 %4:fpr(<8 x s8>) = G_ICMP intpred(uge), %0(<8 x s8>), %1 1550 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 1551 $d0 = COPY %3(<8 x s8>) 1552 RET_ReallyLR implicit $d0 1553 1554... 1555--- 1556name: test_v2i64_ult 1557alignment: 4 1558legalized: true 1559regBankSelected: true 1560tracksRegLiveness: true 1561registers: 1562 - { id: 0, class: fpr } 1563 - { id: 1, class: fpr } 1564 - { id: 2, class: _ } 1565 - { id: 3, class: fpr } 1566 - { id: 4, class: fpr } 1567machineFunctionInfo: {} 1568body: | 1569 bb.1 (%ir-block.0): 1570 liveins: $q0, $q1 1571 1572 ; CHECK-LABEL: name: test_v2i64_ult 1573 ; CHECK: liveins: $q0, $q1 1574 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1575 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1576 ; CHECK: [[CMHIv2i64_:%[0-9]+]]:fpr128 = CMHIv2i64 [[COPY1]], [[COPY]] 1577 ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHIv2i64_]] 1578 ; CHECK: $d0 = COPY [[XTNv2i32_]] 1579 ; CHECK: RET_ReallyLR implicit $d0 1580 %0:fpr(<2 x s64>) = COPY $q0 1581 %1:fpr(<2 x s64>) = COPY $q1 1582 %4:fpr(<2 x s64>) = G_ICMP intpred(ult), %0(<2 x s64>), %1 1583 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 1584 $d0 = COPY %3(<2 x s32>) 1585 RET_ReallyLR implicit $d0 1586 1587... 1588--- 1589name: test_v4i32_ult 1590alignment: 4 1591legalized: true 1592regBankSelected: true 1593tracksRegLiveness: true 1594registers: 1595 - { id: 0, class: fpr } 1596 - { id: 1, class: fpr } 1597 - { id: 2, class: _ } 1598 - { id: 3, class: fpr } 1599 - { id: 4, class: fpr } 1600machineFunctionInfo: {} 1601body: | 1602 bb.1 (%ir-block.0): 1603 liveins: $q0, $q1 1604 1605 ; CHECK-LABEL: name: test_v4i32_ult 1606 ; CHECK: liveins: $q0, $q1 1607 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1608 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1609 ; CHECK: [[CMHIv4i32_:%[0-9]+]]:fpr128 = CMHIv4i32 [[COPY1]], [[COPY]] 1610 ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHIv4i32_]] 1611 ; CHECK: $d0 = COPY [[XTNv4i16_]] 1612 ; CHECK: RET_ReallyLR implicit $d0 1613 %0:fpr(<4 x s32>) = COPY $q0 1614 %1:fpr(<4 x s32>) = COPY $q1 1615 %4:fpr(<4 x s32>) = G_ICMP intpred(ult), %0(<4 x s32>), %1 1616 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 1617 $d0 = COPY %3(<4 x s16>) 1618 RET_ReallyLR implicit $d0 1619 1620... 1621--- 1622name: test_v2i32_ult 1623alignment: 4 1624legalized: true 1625regBankSelected: true 1626tracksRegLiveness: true 1627registers: 1628 - { id: 0, class: fpr } 1629 - { id: 1, class: fpr } 1630 - { id: 2, class: _ } 1631 - { id: 3, class: fpr } 1632 - { id: 4, class: fpr } 1633machineFunctionInfo: {} 1634body: | 1635 bb.1 (%ir-block.0): 1636 liveins: $d0, $d1 1637 1638 ; CHECK-LABEL: name: test_v2i32_ult 1639 ; CHECK: liveins: $d0, $d1 1640 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1641 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1642 ; CHECK: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[COPY1]], [[COPY]] 1643 ; CHECK: $d0 = COPY [[CMHIv2i32_]] 1644 ; CHECK: RET_ReallyLR implicit $d0 1645 %0:fpr(<2 x s32>) = COPY $d0 1646 %1:fpr(<2 x s32>) = COPY $d1 1647 %4:fpr(<2 x s32>) = G_ICMP intpred(ult), %0(<2 x s32>), %1 1648 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 1649 $d0 = COPY %3(<2 x s32>) 1650 RET_ReallyLR implicit $d0 1651 1652... 1653--- 1654name: test_v2i16_ult 1655alignment: 4 1656legalized: true 1657regBankSelected: true 1658tracksRegLiveness: true 1659registers: 1660 - { id: 0, class: _ } 1661 - { id: 1, class: _ } 1662 - { id: 2, class: fpr } 1663 - { id: 3, class: fpr } 1664 - { id: 4, class: _ } 1665 - { id: 5, class: fpr } 1666 - { id: 6, class: _ } 1667 - { id: 7, class: fpr } 1668 - { id: 8, class: fpr } 1669 - { id: 9, class: fpr } 1670 - { id: 10, class: gpr } 1671 - { id: 11, class: fpr } 1672 - { id: 12, class: fpr } 1673 - { id: 13, class: gpr } 1674 - { id: 14, class: fpr } 1675 - { id: 15, class: fpr } 1676machineFunctionInfo: {} 1677body: | 1678 bb.1 (%ir-block.0): 1679 liveins: $d0, $d1 1680 1681 ; CHECK-LABEL: name: test_v2i16_ult 1682 ; CHECK: liveins: $d0, $d1 1683 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1684 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1685 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 1686 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 1687 ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[LDRDui]] 1688 ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 1689 ; CHECK: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 1690 ; CHECK: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[LDRDui1]] 1691 ; CHECK: [[CMHIv2i32_:%[0-9]+]]:fpr64 = CMHIv2i32 [[ANDv8i8_1]], [[ANDv8i8_]] 1692 ; CHECK: $d0 = COPY [[CMHIv2i32_]] 1693 ; CHECK: RET_ReallyLR implicit $d0 1694 %2:fpr(<2 x s32>) = COPY $d0 1695 %3:fpr(<2 x s32>) = COPY $d1 1696 %13:gpr(s32) = G_CONSTANT i32 65535 1697 %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32) 1698 %15:fpr(<2 x s32>) = COPY %2(<2 x s32>) 1699 %7:fpr(<2 x s32>) = G_AND %15, %14 1700 %10:gpr(s32) = G_CONSTANT i32 65535 1701 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 1702 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 1703 %8:fpr(<2 x s32>) = G_AND %12, %11 1704 %9:fpr(<2 x s32>) = G_ICMP intpred(ult), %7(<2 x s32>), %8 1705 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 1706 $d0 = COPY %5(<2 x s32>) 1707 RET_ReallyLR implicit $d0 1708 1709... 1710--- 1711name: test_v8i16_ult 1712alignment: 4 1713legalized: true 1714regBankSelected: true 1715tracksRegLiveness: true 1716registers: 1717 - { id: 0, class: fpr } 1718 - { id: 1, class: fpr } 1719 - { id: 2, class: _ } 1720 - { id: 3, class: fpr } 1721 - { id: 4, class: fpr } 1722machineFunctionInfo: {} 1723body: | 1724 bb.1 (%ir-block.0): 1725 liveins: $q0, $q1 1726 1727 ; CHECK-LABEL: name: test_v8i16_ult 1728 ; CHECK: liveins: $q0, $q1 1729 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1730 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1731 ; CHECK: [[CMHIv8i16_:%[0-9]+]]:fpr128 = CMHIv8i16 [[COPY1]], [[COPY]] 1732 ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHIv8i16_]] 1733 ; CHECK: $d0 = COPY [[XTNv8i8_]] 1734 ; CHECK: RET_ReallyLR implicit $d0 1735 %0:fpr(<8 x s16>) = COPY $q0 1736 %1:fpr(<8 x s16>) = COPY $q1 1737 %4:fpr(<8 x s16>) = G_ICMP intpred(ult), %0(<8 x s16>), %1 1738 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 1739 $d0 = COPY %3(<8 x s8>) 1740 RET_ReallyLR implicit $d0 1741 1742... 1743--- 1744name: test_v4i16_ult 1745alignment: 4 1746legalized: true 1747regBankSelected: true 1748tracksRegLiveness: true 1749registers: 1750 - { id: 0, class: fpr } 1751 - { id: 1, class: fpr } 1752 - { id: 2, class: _ } 1753 - { id: 3, class: fpr } 1754 - { id: 4, class: fpr } 1755machineFunctionInfo: {} 1756body: | 1757 bb.1 (%ir-block.0): 1758 liveins: $d0, $d1 1759 1760 ; CHECK-LABEL: name: test_v4i16_ult 1761 ; CHECK: liveins: $d0, $d1 1762 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1763 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1764 ; CHECK: [[CMHIv4i16_:%[0-9]+]]:fpr64 = CMHIv4i16 [[COPY1]], [[COPY]] 1765 ; CHECK: $d0 = COPY [[CMHIv4i16_]] 1766 ; CHECK: RET_ReallyLR implicit $d0 1767 %0:fpr(<4 x s16>) = COPY $d0 1768 %1:fpr(<4 x s16>) = COPY $d1 1769 %4:fpr(<4 x s16>) = G_ICMP intpred(ult), %0(<4 x s16>), %1 1770 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 1771 $d0 = COPY %3(<4 x s16>) 1772 RET_ReallyLR implicit $d0 1773 1774... 1775--- 1776name: test_v16i8_ult 1777alignment: 4 1778legalized: true 1779regBankSelected: true 1780tracksRegLiveness: true 1781registers: 1782 - { id: 0, class: fpr } 1783 - { id: 1, class: fpr } 1784 - { id: 2, class: _ } 1785 - { id: 3, class: fpr } 1786 - { id: 4, class: fpr } 1787machineFunctionInfo: {} 1788body: | 1789 bb.1 (%ir-block.0): 1790 liveins: $q0, $q1 1791 1792 ; CHECK-LABEL: name: test_v16i8_ult 1793 ; CHECK: liveins: $q0, $q1 1794 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1795 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1796 ; CHECK: [[CMHIv16i8_:%[0-9]+]]:fpr128 = CMHIv16i8 [[COPY1]], [[COPY]] 1797 ; CHECK: $q0 = COPY [[CMHIv16i8_]] 1798 ; CHECK: RET_ReallyLR implicit $q0 1799 %0:fpr(<16 x s8>) = COPY $q0 1800 %1:fpr(<16 x s8>) = COPY $q1 1801 %4:fpr(<16 x s8>) = G_ICMP intpred(ult), %0(<16 x s8>), %1 1802 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 1803 $q0 = COPY %3(<16 x s8>) 1804 RET_ReallyLR implicit $q0 1805 1806... 1807--- 1808name: test_v8i8_ult 1809alignment: 4 1810legalized: true 1811regBankSelected: true 1812tracksRegLiveness: true 1813registers: 1814 - { id: 0, class: fpr } 1815 - { id: 1, class: fpr } 1816 - { id: 2, class: _ } 1817 - { id: 3, class: fpr } 1818 - { id: 4, class: fpr } 1819machineFunctionInfo: {} 1820body: | 1821 bb.1 (%ir-block.0): 1822 liveins: $d0, $d1 1823 1824 ; CHECK-LABEL: name: test_v8i8_ult 1825 ; CHECK: liveins: $d0, $d1 1826 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1827 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1828 ; CHECK: [[CMHIv8i8_:%[0-9]+]]:fpr64 = CMHIv8i8 [[COPY1]], [[COPY]] 1829 ; CHECK: $d0 = COPY [[CMHIv8i8_]] 1830 ; CHECK: RET_ReallyLR implicit $d0 1831 %0:fpr(<8 x s8>) = COPY $d0 1832 %1:fpr(<8 x s8>) = COPY $d1 1833 %4:fpr(<8 x s8>) = G_ICMP intpred(ult), %0(<8 x s8>), %1 1834 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 1835 $d0 = COPY %3(<8 x s8>) 1836 RET_ReallyLR implicit $d0 1837 1838... 1839--- 1840name: test_v2i64_ule 1841alignment: 4 1842legalized: true 1843regBankSelected: true 1844tracksRegLiveness: true 1845registers: 1846 - { id: 0, class: fpr } 1847 - { id: 1, class: fpr } 1848 - { id: 2, class: _ } 1849 - { id: 3, class: fpr } 1850 - { id: 4, class: fpr } 1851machineFunctionInfo: {} 1852body: | 1853 bb.1 (%ir-block.0): 1854 liveins: $q0, $q1 1855 1856 ; CHECK-LABEL: name: test_v2i64_ule 1857 ; CHECK: liveins: $q0, $q1 1858 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1859 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1860 ; CHECK: [[CMHSv2i64_:%[0-9]+]]:fpr128 = CMHSv2i64 [[COPY1]], [[COPY]] 1861 ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMHSv2i64_]] 1862 ; CHECK: $d0 = COPY [[XTNv2i32_]] 1863 ; CHECK: RET_ReallyLR implicit $d0 1864 %0:fpr(<2 x s64>) = COPY $q0 1865 %1:fpr(<2 x s64>) = COPY $q1 1866 %4:fpr(<2 x s64>) = G_ICMP intpred(ule), %0(<2 x s64>), %1 1867 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 1868 $d0 = COPY %3(<2 x s32>) 1869 RET_ReallyLR implicit $d0 1870 1871... 1872--- 1873name: test_v4i32_ule 1874alignment: 4 1875legalized: true 1876regBankSelected: true 1877tracksRegLiveness: true 1878registers: 1879 - { id: 0, class: fpr } 1880 - { id: 1, class: fpr } 1881 - { id: 2, class: _ } 1882 - { id: 3, class: fpr } 1883 - { id: 4, class: fpr } 1884machineFunctionInfo: {} 1885body: | 1886 bb.1 (%ir-block.0): 1887 liveins: $q0, $q1 1888 1889 ; CHECK-LABEL: name: test_v4i32_ule 1890 ; CHECK: liveins: $q0, $q1 1891 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1892 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1893 ; CHECK: [[CMHSv4i32_:%[0-9]+]]:fpr128 = CMHSv4i32 [[COPY1]], [[COPY]] 1894 ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMHSv4i32_]] 1895 ; CHECK: $d0 = COPY [[XTNv4i16_]] 1896 ; CHECK: RET_ReallyLR implicit $d0 1897 %0:fpr(<4 x s32>) = COPY $q0 1898 %1:fpr(<4 x s32>) = COPY $q1 1899 %4:fpr(<4 x s32>) = G_ICMP intpred(ule), %0(<4 x s32>), %1 1900 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 1901 $d0 = COPY %3(<4 x s16>) 1902 RET_ReallyLR implicit $d0 1903 1904... 1905--- 1906name: test_v2i32_ule 1907alignment: 4 1908legalized: true 1909regBankSelected: true 1910tracksRegLiveness: true 1911registers: 1912 - { id: 0, class: fpr } 1913 - { id: 1, class: fpr } 1914 - { id: 2, class: _ } 1915 - { id: 3, class: fpr } 1916 - { id: 4, class: fpr } 1917machineFunctionInfo: {} 1918body: | 1919 bb.1 (%ir-block.0): 1920 liveins: $d0, $d1 1921 1922 ; CHECK-LABEL: name: test_v2i32_ule 1923 ; CHECK: liveins: $d0, $d1 1924 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1925 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1926 ; CHECK: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[COPY1]], [[COPY]] 1927 ; CHECK: $d0 = COPY [[CMHSv2i32_]] 1928 ; CHECK: RET_ReallyLR implicit $d0 1929 %0:fpr(<2 x s32>) = COPY $d0 1930 %1:fpr(<2 x s32>) = COPY $d1 1931 %4:fpr(<2 x s32>) = G_ICMP intpred(ule), %0(<2 x s32>), %1 1932 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 1933 $d0 = COPY %3(<2 x s32>) 1934 RET_ReallyLR implicit $d0 1935 1936... 1937--- 1938name: test_v2i16_ule 1939alignment: 4 1940legalized: true 1941regBankSelected: true 1942tracksRegLiveness: true 1943registers: 1944 - { id: 0, class: _ } 1945 - { id: 1, class: _ } 1946 - { id: 2, class: fpr } 1947 - { id: 3, class: fpr } 1948 - { id: 4, class: _ } 1949 - { id: 5, class: fpr } 1950 - { id: 6, class: _ } 1951 - { id: 7, class: fpr } 1952 - { id: 8, class: fpr } 1953 - { id: 9, class: fpr } 1954 - { id: 10, class: gpr } 1955 - { id: 11, class: fpr } 1956 - { id: 12, class: fpr } 1957 - { id: 13, class: gpr } 1958 - { id: 14, class: fpr } 1959 - { id: 15, class: fpr } 1960machineFunctionInfo: {} 1961body: | 1962 bb.1 (%ir-block.0): 1963 liveins: $d0, $d1 1964 1965 ; CHECK-LABEL: name: test_v2i16_ule 1966 ; CHECK: liveins: $d0, $d1 1967 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1968 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1969 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 1970 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 1971 ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY]], [[LDRDui]] 1972 ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 1973 ; CHECK: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 1974 ; CHECK: [[ANDv8i8_1:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[LDRDui1]] 1975 ; CHECK: [[CMHSv2i32_:%[0-9]+]]:fpr64 = CMHSv2i32 [[ANDv8i8_1]], [[ANDv8i8_]] 1976 ; CHECK: $d0 = COPY [[CMHSv2i32_]] 1977 ; CHECK: RET_ReallyLR implicit $d0 1978 %2:fpr(<2 x s32>) = COPY $d0 1979 %3:fpr(<2 x s32>) = COPY $d1 1980 %13:gpr(s32) = G_CONSTANT i32 65535 1981 %14:fpr(<2 x s32>) = G_BUILD_VECTOR %13(s32), %13(s32) 1982 %15:fpr(<2 x s32>) = COPY %2(<2 x s32>) 1983 %7:fpr(<2 x s32>) = G_AND %15, %14 1984 %10:gpr(s32) = G_CONSTANT i32 65535 1985 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 1986 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 1987 %8:fpr(<2 x s32>) = G_AND %12, %11 1988 %9:fpr(<2 x s32>) = G_ICMP intpred(ule), %7(<2 x s32>), %8 1989 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 1990 $d0 = COPY %5(<2 x s32>) 1991 RET_ReallyLR implicit $d0 1992 1993... 1994--- 1995name: test_v8i16_ule 1996alignment: 4 1997legalized: true 1998regBankSelected: true 1999tracksRegLiveness: true 2000registers: 2001 - { id: 0, class: fpr } 2002 - { id: 1, class: fpr } 2003 - { id: 2, class: _ } 2004 - { id: 3, class: fpr } 2005 - { id: 4, class: fpr } 2006machineFunctionInfo: {} 2007body: | 2008 bb.1 (%ir-block.0): 2009 liveins: $q0, $q1 2010 2011 ; CHECK-LABEL: name: test_v8i16_ule 2012 ; CHECK: liveins: $q0, $q1 2013 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2014 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2015 ; CHECK: [[CMHSv8i16_:%[0-9]+]]:fpr128 = CMHSv8i16 [[COPY1]], [[COPY]] 2016 ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMHSv8i16_]] 2017 ; CHECK: $d0 = COPY [[XTNv8i8_]] 2018 ; CHECK: RET_ReallyLR implicit $d0 2019 %0:fpr(<8 x s16>) = COPY $q0 2020 %1:fpr(<8 x s16>) = COPY $q1 2021 %4:fpr(<8 x s16>) = G_ICMP intpred(ule), %0(<8 x s16>), %1 2022 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 2023 $d0 = COPY %3(<8 x s8>) 2024 RET_ReallyLR implicit $d0 2025 2026... 2027--- 2028name: test_v4i16_ule 2029alignment: 4 2030legalized: true 2031regBankSelected: true 2032tracksRegLiveness: true 2033registers: 2034 - { id: 0, class: fpr } 2035 - { id: 1, class: fpr } 2036 - { id: 2, class: _ } 2037 - { id: 3, class: fpr } 2038 - { id: 4, class: fpr } 2039machineFunctionInfo: {} 2040body: | 2041 bb.1 (%ir-block.0): 2042 liveins: $d0, $d1 2043 2044 ; CHECK-LABEL: name: test_v4i16_ule 2045 ; CHECK: liveins: $d0, $d1 2046 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2047 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2048 ; CHECK: [[CMHSv4i16_:%[0-9]+]]:fpr64 = CMHSv4i16 [[COPY1]], [[COPY]] 2049 ; CHECK: $d0 = COPY [[CMHSv4i16_]] 2050 ; CHECK: RET_ReallyLR implicit $d0 2051 %0:fpr(<4 x s16>) = COPY $d0 2052 %1:fpr(<4 x s16>) = COPY $d1 2053 %4:fpr(<4 x s16>) = G_ICMP intpred(ule), %0(<4 x s16>), %1 2054 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 2055 $d0 = COPY %3(<4 x s16>) 2056 RET_ReallyLR implicit $d0 2057 2058... 2059--- 2060name: test_v16i8_ule 2061alignment: 4 2062legalized: true 2063regBankSelected: true 2064tracksRegLiveness: true 2065registers: 2066 - { id: 0, class: fpr } 2067 - { id: 1, class: fpr } 2068 - { id: 2, class: _ } 2069 - { id: 3, class: fpr } 2070 - { id: 4, class: fpr } 2071machineFunctionInfo: {} 2072body: | 2073 bb.1 (%ir-block.0): 2074 liveins: $q0, $q1 2075 2076 ; CHECK-LABEL: name: test_v16i8_ule 2077 ; CHECK: liveins: $q0, $q1 2078 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2079 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2080 ; CHECK: [[CMHSv16i8_:%[0-9]+]]:fpr128 = CMHSv16i8 [[COPY1]], [[COPY]] 2081 ; CHECK: $q0 = COPY [[CMHSv16i8_]] 2082 ; CHECK: RET_ReallyLR implicit $q0 2083 %0:fpr(<16 x s8>) = COPY $q0 2084 %1:fpr(<16 x s8>) = COPY $q1 2085 %4:fpr(<16 x s8>) = G_ICMP intpred(ule), %0(<16 x s8>), %1 2086 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 2087 $q0 = COPY %3(<16 x s8>) 2088 RET_ReallyLR implicit $q0 2089 2090... 2091--- 2092name: test_v8i8_ule 2093alignment: 4 2094legalized: true 2095regBankSelected: true 2096tracksRegLiveness: true 2097registers: 2098 - { id: 0, class: fpr } 2099 - { id: 1, class: fpr } 2100 - { id: 2, class: _ } 2101 - { id: 3, class: fpr } 2102 - { id: 4, class: fpr } 2103machineFunctionInfo: {} 2104body: | 2105 bb.1 (%ir-block.0): 2106 liveins: $d0, $d1 2107 2108 ; CHECK-LABEL: name: test_v8i8_ule 2109 ; CHECK: liveins: $d0, $d1 2110 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2111 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2112 ; CHECK: [[CMHSv8i8_:%[0-9]+]]:fpr64 = CMHSv8i8 [[COPY1]], [[COPY]] 2113 ; CHECK: $d0 = COPY [[CMHSv8i8_]] 2114 ; CHECK: RET_ReallyLR implicit $d0 2115 %0:fpr(<8 x s8>) = COPY $d0 2116 %1:fpr(<8 x s8>) = COPY $d1 2117 %4:fpr(<8 x s8>) = G_ICMP intpred(ule), %0(<8 x s8>), %1 2118 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 2119 $d0 = COPY %3(<8 x s8>) 2120 RET_ReallyLR implicit $d0 2121 2122... 2123--- 2124name: test_v2i64_sgt 2125alignment: 4 2126legalized: true 2127regBankSelected: true 2128tracksRegLiveness: true 2129registers: 2130 - { id: 0, class: fpr } 2131 - { id: 1, class: fpr } 2132 - { id: 2, class: _ } 2133 - { id: 3, class: fpr } 2134 - { id: 4, class: fpr } 2135machineFunctionInfo: {} 2136body: | 2137 bb.1 (%ir-block.0): 2138 liveins: $q0, $q1 2139 2140 ; CHECK-LABEL: name: test_v2i64_sgt 2141 ; CHECK: liveins: $q0, $q1 2142 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2143 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2144 ; CHECK: [[CMGTv2i64_:%[0-9]+]]:fpr128 = CMGTv2i64 [[COPY]], [[COPY1]] 2145 ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGTv2i64_]] 2146 ; CHECK: $d0 = COPY [[XTNv2i32_]] 2147 ; CHECK: RET_ReallyLR implicit $d0 2148 %0:fpr(<2 x s64>) = COPY $q0 2149 %1:fpr(<2 x s64>) = COPY $q1 2150 %4:fpr(<2 x s64>) = G_ICMP intpred(sgt), %0(<2 x s64>), %1 2151 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 2152 $d0 = COPY %3(<2 x s32>) 2153 RET_ReallyLR implicit $d0 2154 2155... 2156--- 2157name: test_v4i32_sgt 2158alignment: 4 2159legalized: true 2160regBankSelected: true 2161tracksRegLiveness: true 2162registers: 2163 - { id: 0, class: fpr } 2164 - { id: 1, class: fpr } 2165 - { id: 2, class: _ } 2166 - { id: 3, class: fpr } 2167 - { id: 4, class: fpr } 2168machineFunctionInfo: {} 2169body: | 2170 bb.1 (%ir-block.0): 2171 liveins: $q0, $q1 2172 2173 ; CHECK-LABEL: name: test_v4i32_sgt 2174 ; CHECK: liveins: $q0, $q1 2175 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2176 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2177 ; CHECK: [[CMGTv4i32_:%[0-9]+]]:fpr128 = CMGTv4i32 [[COPY]], [[COPY1]] 2178 ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGTv4i32_]] 2179 ; CHECK: $d0 = COPY [[XTNv4i16_]] 2180 ; CHECK: RET_ReallyLR implicit $d0 2181 %0:fpr(<4 x s32>) = COPY $q0 2182 %1:fpr(<4 x s32>) = COPY $q1 2183 %4:fpr(<4 x s32>) = G_ICMP intpred(sgt), %0(<4 x s32>), %1 2184 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 2185 $d0 = COPY %3(<4 x s16>) 2186 RET_ReallyLR implicit $d0 2187 2188... 2189--- 2190name: test_v2i32_sgt 2191alignment: 4 2192legalized: true 2193regBankSelected: true 2194tracksRegLiveness: true 2195registers: 2196 - { id: 0, class: fpr } 2197 - { id: 1, class: fpr } 2198 - { id: 2, class: _ } 2199 - { id: 3, class: fpr } 2200 - { id: 4, class: fpr } 2201machineFunctionInfo: {} 2202body: | 2203 bb.1 (%ir-block.0): 2204 liveins: $d0, $d1 2205 2206 ; CHECK-LABEL: name: test_v2i32_sgt 2207 ; CHECK: liveins: $d0, $d1 2208 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2209 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2210 ; CHECK: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[COPY]], [[COPY1]] 2211 ; CHECK: $d0 = COPY [[CMGTv2i32_]] 2212 ; CHECK: RET_ReallyLR implicit $d0 2213 %0:fpr(<2 x s32>) = COPY $d0 2214 %1:fpr(<2 x s32>) = COPY $d1 2215 %4:fpr(<2 x s32>) = G_ICMP intpred(sgt), %0(<2 x s32>), %1 2216 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 2217 $d0 = COPY %3(<2 x s32>) 2218 RET_ReallyLR implicit $d0 2219 2220... 2221--- 2222name: test_v2i16_sgt 2223alignment: 4 2224legalized: true 2225regBankSelected: true 2226tracksRegLiveness: true 2227registers: 2228 - { id: 0, class: _ } 2229 - { id: 1, class: _ } 2230 - { id: 2, class: fpr } 2231 - { id: 3, class: fpr } 2232 - { id: 4, class: _ } 2233 - { id: 5, class: fpr } 2234 - { id: 6, class: _ } 2235 - { id: 7, class: fpr } 2236 - { id: 8, class: fpr } 2237 - { id: 9, class: fpr } 2238 - { id: 10, class: gpr } 2239 - { id: 11, class: fpr } 2240 - { id: 12, class: fpr } 2241 - { id: 13, class: fpr } 2242 - { id: 14, class: gpr } 2243 - { id: 15, class: fpr } 2244 - { id: 16, class: fpr } 2245 - { id: 17, class: fpr } 2246machineFunctionInfo: {} 2247body: | 2248 bb.1 (%ir-block.0): 2249 liveins: $d0, $d1 2250 2251 ; CHECK-LABEL: name: test_v2i16_sgt 2252 ; CHECK: liveins: $d0, $d1 2253 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2254 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2255 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 2256 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 2257 ; CHECK: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 16 2258 ; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[LDRDui]] 2259 ; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]] 2260 ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 2261 ; CHECK: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 2262 ; CHECK: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 16 2263 ; CHECK: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[LDRDui1]] 2264 ; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]] 2265 ; CHECK: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[SSHLv2i32_]], [[SSHLv2i32_1]] 2266 ; CHECK: $d0 = COPY [[CMGTv2i32_]] 2267 ; CHECK: RET_ReallyLR implicit $d0 2268 %2:fpr(<2 x s32>) = COPY $d0 2269 %3:fpr(<2 x s32>) = COPY $d1 2270 %14:gpr(s32) = G_CONSTANT i32 16 2271 %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32) 2272 %16:fpr(<2 x s32>) = COPY %2(<2 x s32>) 2273 %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>) 2274 %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>) 2275 %10:gpr(s32) = G_CONSTANT i32 16 2276 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 2277 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 2278 %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>) 2279 %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>) 2280 %9:fpr(<2 x s32>) = G_ICMP intpred(sgt), %7(<2 x s32>), %8 2281 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 2282 $d0 = COPY %5(<2 x s32>) 2283 RET_ReallyLR implicit $d0 2284 2285... 2286--- 2287name: test_v8i16_sgt 2288alignment: 4 2289legalized: true 2290regBankSelected: true 2291tracksRegLiveness: true 2292registers: 2293 - { id: 0, class: fpr } 2294 - { id: 1, class: fpr } 2295 - { id: 2, class: _ } 2296 - { id: 3, class: fpr } 2297 - { id: 4, class: fpr } 2298machineFunctionInfo: {} 2299body: | 2300 bb.1 (%ir-block.0): 2301 liveins: $q0, $q1 2302 2303 ; CHECK-LABEL: name: test_v8i16_sgt 2304 ; CHECK: liveins: $q0, $q1 2305 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2306 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2307 ; CHECK: [[CMGTv8i16_:%[0-9]+]]:fpr128 = CMGTv8i16 [[COPY]], [[COPY1]] 2308 ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGTv8i16_]] 2309 ; CHECK: $d0 = COPY [[XTNv8i8_]] 2310 ; CHECK: RET_ReallyLR implicit $d0 2311 %0:fpr(<8 x s16>) = COPY $q0 2312 %1:fpr(<8 x s16>) = COPY $q1 2313 %4:fpr(<8 x s16>) = G_ICMP intpred(sgt), %0(<8 x s16>), %1 2314 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 2315 $d0 = COPY %3(<8 x s8>) 2316 RET_ReallyLR implicit $d0 2317 2318... 2319--- 2320name: test_v4i16_sgt 2321alignment: 4 2322legalized: true 2323regBankSelected: true 2324tracksRegLiveness: true 2325registers: 2326 - { id: 0, class: fpr } 2327 - { id: 1, class: fpr } 2328 - { id: 2, class: _ } 2329 - { id: 3, class: fpr } 2330 - { id: 4, class: fpr } 2331machineFunctionInfo: {} 2332body: | 2333 bb.1 (%ir-block.0): 2334 liveins: $d0, $d1 2335 2336 ; CHECK-LABEL: name: test_v4i16_sgt 2337 ; CHECK: liveins: $d0, $d1 2338 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2339 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2340 ; CHECK: [[CMGTv4i16_:%[0-9]+]]:fpr64 = CMGTv4i16 [[COPY]], [[COPY1]] 2341 ; CHECK: $d0 = COPY [[CMGTv4i16_]] 2342 ; CHECK: RET_ReallyLR implicit $d0 2343 %0:fpr(<4 x s16>) = COPY $d0 2344 %1:fpr(<4 x s16>) = COPY $d1 2345 %4:fpr(<4 x s16>) = G_ICMP intpred(sgt), %0(<4 x s16>), %1 2346 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 2347 $d0 = COPY %3(<4 x s16>) 2348 RET_ReallyLR implicit $d0 2349 2350... 2351--- 2352name: test_v16i8_sgt 2353alignment: 4 2354legalized: true 2355regBankSelected: true 2356tracksRegLiveness: true 2357registers: 2358 - { id: 0, class: fpr } 2359 - { id: 1, class: fpr } 2360 - { id: 2, class: _ } 2361 - { id: 3, class: fpr } 2362 - { id: 4, class: fpr } 2363machineFunctionInfo: {} 2364body: | 2365 bb.1 (%ir-block.0): 2366 liveins: $q0, $q1 2367 2368 ; CHECK-LABEL: name: test_v16i8_sgt 2369 ; CHECK: liveins: $q0, $q1 2370 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2371 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2372 ; CHECK: [[CMGTv16i8_:%[0-9]+]]:fpr128 = CMGTv16i8 [[COPY]], [[COPY1]] 2373 ; CHECK: $q0 = COPY [[CMGTv16i8_]] 2374 ; CHECK: RET_ReallyLR implicit $q0 2375 %0:fpr(<16 x s8>) = COPY $q0 2376 %1:fpr(<16 x s8>) = COPY $q1 2377 %4:fpr(<16 x s8>) = G_ICMP intpred(sgt), %0(<16 x s8>), %1 2378 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 2379 $q0 = COPY %3(<16 x s8>) 2380 RET_ReallyLR implicit $q0 2381 2382... 2383--- 2384name: test_v8i8_sgt 2385alignment: 4 2386legalized: true 2387regBankSelected: true 2388tracksRegLiveness: true 2389registers: 2390 - { id: 0, class: fpr } 2391 - { id: 1, class: fpr } 2392 - { id: 2, class: _ } 2393 - { id: 3, class: fpr } 2394 - { id: 4, class: fpr } 2395machineFunctionInfo: {} 2396body: | 2397 bb.1 (%ir-block.0): 2398 liveins: $d0, $d1 2399 2400 ; CHECK-LABEL: name: test_v8i8_sgt 2401 ; CHECK: liveins: $d0, $d1 2402 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2403 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2404 ; CHECK: [[CMGTv8i8_:%[0-9]+]]:fpr64 = CMGTv8i8 [[COPY]], [[COPY1]] 2405 ; CHECK: $d0 = COPY [[CMGTv8i8_]] 2406 ; CHECK: RET_ReallyLR implicit $d0 2407 %0:fpr(<8 x s8>) = COPY $d0 2408 %1:fpr(<8 x s8>) = COPY $d1 2409 %4:fpr(<8 x s8>) = G_ICMP intpred(sgt), %0(<8 x s8>), %1 2410 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 2411 $d0 = COPY %3(<8 x s8>) 2412 RET_ReallyLR implicit $d0 2413 2414... 2415--- 2416name: test_v2i64_sge 2417alignment: 4 2418legalized: true 2419regBankSelected: true 2420tracksRegLiveness: true 2421registers: 2422 - { id: 0, class: fpr } 2423 - { id: 1, class: fpr } 2424 - { id: 2, class: _ } 2425 - { id: 3, class: fpr } 2426 - { id: 4, class: fpr } 2427machineFunctionInfo: {} 2428body: | 2429 bb.1 (%ir-block.0): 2430 liveins: $q0, $q1 2431 2432 ; CHECK-LABEL: name: test_v2i64_sge 2433 ; CHECK: liveins: $q0, $q1 2434 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2435 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2436 ; CHECK: [[CMGEv2i64_:%[0-9]+]]:fpr128 = CMGEv2i64 [[COPY]], [[COPY1]] 2437 ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGEv2i64_]] 2438 ; CHECK: $d0 = COPY [[XTNv2i32_]] 2439 ; CHECK: RET_ReallyLR implicit $d0 2440 %0:fpr(<2 x s64>) = COPY $q0 2441 %1:fpr(<2 x s64>) = COPY $q1 2442 %4:fpr(<2 x s64>) = G_ICMP intpred(sge), %0(<2 x s64>), %1 2443 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 2444 $d0 = COPY %3(<2 x s32>) 2445 RET_ReallyLR implicit $d0 2446 2447... 2448--- 2449name: test_v4i32_sge 2450alignment: 4 2451legalized: true 2452regBankSelected: true 2453tracksRegLiveness: true 2454registers: 2455 - { id: 0, class: fpr } 2456 - { id: 1, class: fpr } 2457 - { id: 2, class: _ } 2458 - { id: 3, class: fpr } 2459 - { id: 4, class: fpr } 2460machineFunctionInfo: {} 2461body: | 2462 bb.1 (%ir-block.0): 2463 liveins: $q0, $q1 2464 2465 ; CHECK-LABEL: name: test_v4i32_sge 2466 ; CHECK: liveins: $q0, $q1 2467 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2468 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2469 ; CHECK: [[CMGEv4i32_:%[0-9]+]]:fpr128 = CMGEv4i32 [[COPY]], [[COPY1]] 2470 ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGEv4i32_]] 2471 ; CHECK: $d0 = COPY [[XTNv4i16_]] 2472 ; CHECK: RET_ReallyLR implicit $d0 2473 %0:fpr(<4 x s32>) = COPY $q0 2474 %1:fpr(<4 x s32>) = COPY $q1 2475 %4:fpr(<4 x s32>) = G_ICMP intpred(sge), %0(<4 x s32>), %1 2476 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 2477 $d0 = COPY %3(<4 x s16>) 2478 RET_ReallyLR implicit $d0 2479 2480... 2481--- 2482name: test_v2i32_sge 2483alignment: 4 2484legalized: true 2485regBankSelected: true 2486tracksRegLiveness: true 2487registers: 2488 - { id: 0, class: fpr } 2489 - { id: 1, class: fpr } 2490 - { id: 2, class: _ } 2491 - { id: 3, class: fpr } 2492 - { id: 4, class: fpr } 2493machineFunctionInfo: {} 2494body: | 2495 bb.1 (%ir-block.0): 2496 liveins: $d0, $d1 2497 2498 ; CHECK-LABEL: name: test_v2i32_sge 2499 ; CHECK: liveins: $d0, $d1 2500 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2501 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2502 ; CHECK: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[COPY]], [[COPY1]] 2503 ; CHECK: $d0 = COPY [[CMGEv2i32_]] 2504 ; CHECK: RET_ReallyLR implicit $d0 2505 %0:fpr(<2 x s32>) = COPY $d0 2506 %1:fpr(<2 x s32>) = COPY $d1 2507 %4:fpr(<2 x s32>) = G_ICMP intpred(sge), %0(<2 x s32>), %1 2508 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 2509 $d0 = COPY %3(<2 x s32>) 2510 RET_ReallyLR implicit $d0 2511 2512... 2513--- 2514name: test_v2i16_sge 2515alignment: 4 2516legalized: true 2517regBankSelected: true 2518tracksRegLiveness: true 2519registers: 2520 - { id: 0, class: _ } 2521 - { id: 1, class: _ } 2522 - { id: 2, class: fpr } 2523 - { id: 3, class: fpr } 2524 - { id: 4, class: _ } 2525 - { id: 5, class: fpr } 2526 - { id: 6, class: _ } 2527 - { id: 7, class: fpr } 2528 - { id: 8, class: fpr } 2529 - { id: 9, class: fpr } 2530 - { id: 10, class: gpr } 2531 - { id: 11, class: fpr } 2532 - { id: 12, class: fpr } 2533 - { id: 13, class: fpr } 2534 - { id: 14, class: gpr } 2535 - { id: 15, class: fpr } 2536 - { id: 16, class: fpr } 2537 - { id: 17, class: fpr } 2538machineFunctionInfo: {} 2539body: | 2540 bb.1 (%ir-block.0): 2541 liveins: $d0, $d1 2542 2543 ; CHECK-LABEL: name: test_v2i16_sge 2544 ; CHECK: liveins: $d0, $d1 2545 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2546 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2547 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 2548 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 2549 ; CHECK: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 16 2550 ; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[LDRDui]] 2551 ; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]] 2552 ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 2553 ; CHECK: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 2554 ; CHECK: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 16 2555 ; CHECK: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[LDRDui1]] 2556 ; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]] 2557 ; CHECK: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[SSHLv2i32_]], [[SSHLv2i32_1]] 2558 ; CHECK: $d0 = COPY [[CMGEv2i32_]] 2559 ; CHECK: RET_ReallyLR implicit $d0 2560 %2:fpr(<2 x s32>) = COPY $d0 2561 %3:fpr(<2 x s32>) = COPY $d1 2562 %14:gpr(s32) = G_CONSTANT i32 16 2563 %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32) 2564 %16:fpr(<2 x s32>) = COPY %2(<2 x s32>) 2565 %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>) 2566 %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>) 2567 %10:gpr(s32) = G_CONSTANT i32 16 2568 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 2569 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 2570 %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>) 2571 %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>) 2572 %9:fpr(<2 x s32>) = G_ICMP intpred(sge), %7(<2 x s32>), %8 2573 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 2574 $d0 = COPY %5(<2 x s32>) 2575 RET_ReallyLR implicit $d0 2576 2577... 2578--- 2579name: test_v8i16_sge 2580alignment: 4 2581legalized: true 2582regBankSelected: true 2583tracksRegLiveness: true 2584registers: 2585 - { id: 0, class: fpr } 2586 - { id: 1, class: fpr } 2587 - { id: 2, class: _ } 2588 - { id: 3, class: fpr } 2589 - { id: 4, class: fpr } 2590machineFunctionInfo: {} 2591body: | 2592 bb.1 (%ir-block.0): 2593 liveins: $q0, $q1 2594 2595 ; CHECK-LABEL: name: test_v8i16_sge 2596 ; CHECK: liveins: $q0, $q1 2597 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2598 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2599 ; CHECK: [[CMGEv8i16_:%[0-9]+]]:fpr128 = CMGEv8i16 [[COPY]], [[COPY1]] 2600 ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGEv8i16_]] 2601 ; CHECK: $d0 = COPY [[XTNv8i8_]] 2602 ; CHECK: RET_ReallyLR implicit $d0 2603 %0:fpr(<8 x s16>) = COPY $q0 2604 %1:fpr(<8 x s16>) = COPY $q1 2605 %4:fpr(<8 x s16>) = G_ICMP intpred(sge), %0(<8 x s16>), %1 2606 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 2607 $d0 = COPY %3(<8 x s8>) 2608 RET_ReallyLR implicit $d0 2609 2610... 2611--- 2612name: test_v4i16_sge 2613alignment: 4 2614legalized: true 2615regBankSelected: true 2616tracksRegLiveness: true 2617registers: 2618 - { id: 0, class: fpr } 2619 - { id: 1, class: fpr } 2620 - { id: 2, class: _ } 2621 - { id: 3, class: fpr } 2622 - { id: 4, class: fpr } 2623machineFunctionInfo: {} 2624body: | 2625 bb.1 (%ir-block.0): 2626 liveins: $d0, $d1 2627 2628 ; CHECK-LABEL: name: test_v4i16_sge 2629 ; CHECK: liveins: $d0, $d1 2630 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2631 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2632 ; CHECK: [[CMGEv4i16_:%[0-9]+]]:fpr64 = CMGEv4i16 [[COPY]], [[COPY1]] 2633 ; CHECK: $d0 = COPY [[CMGEv4i16_]] 2634 ; CHECK: RET_ReallyLR implicit $d0 2635 %0:fpr(<4 x s16>) = COPY $d0 2636 %1:fpr(<4 x s16>) = COPY $d1 2637 %4:fpr(<4 x s16>) = G_ICMP intpred(sge), %0(<4 x s16>), %1 2638 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 2639 $d0 = COPY %3(<4 x s16>) 2640 RET_ReallyLR implicit $d0 2641 2642... 2643--- 2644name: test_v16i8_sge 2645alignment: 4 2646legalized: true 2647regBankSelected: true 2648tracksRegLiveness: true 2649registers: 2650 - { id: 0, class: fpr } 2651 - { id: 1, class: fpr } 2652 - { id: 2, class: _ } 2653 - { id: 3, class: fpr } 2654 - { id: 4, class: fpr } 2655machineFunctionInfo: {} 2656body: | 2657 bb.1 (%ir-block.0): 2658 liveins: $q0, $q1 2659 2660 ; CHECK-LABEL: name: test_v16i8_sge 2661 ; CHECK: liveins: $q0, $q1 2662 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2663 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2664 ; CHECK: [[CMGEv16i8_:%[0-9]+]]:fpr128 = CMGEv16i8 [[COPY]], [[COPY1]] 2665 ; CHECK: $q0 = COPY [[CMGEv16i8_]] 2666 ; CHECK: RET_ReallyLR implicit $q0 2667 %0:fpr(<16 x s8>) = COPY $q0 2668 %1:fpr(<16 x s8>) = COPY $q1 2669 %4:fpr(<16 x s8>) = G_ICMP intpred(sge), %0(<16 x s8>), %1 2670 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 2671 $q0 = COPY %3(<16 x s8>) 2672 RET_ReallyLR implicit $q0 2673 2674... 2675--- 2676name: test_v8i8_sge 2677alignment: 4 2678legalized: true 2679regBankSelected: true 2680tracksRegLiveness: true 2681registers: 2682 - { id: 0, class: fpr } 2683 - { id: 1, class: fpr } 2684 - { id: 2, class: _ } 2685 - { id: 3, class: fpr } 2686 - { id: 4, class: fpr } 2687machineFunctionInfo: {} 2688body: | 2689 bb.1 (%ir-block.0): 2690 liveins: $d0, $d1 2691 2692 ; CHECK-LABEL: name: test_v8i8_sge 2693 ; CHECK: liveins: $d0, $d1 2694 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2695 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2696 ; CHECK: [[CMGEv8i8_:%[0-9]+]]:fpr64 = CMGEv8i8 [[COPY]], [[COPY1]] 2697 ; CHECK: $d0 = COPY [[CMGEv8i8_]] 2698 ; CHECK: RET_ReallyLR implicit $d0 2699 %0:fpr(<8 x s8>) = COPY $d0 2700 %1:fpr(<8 x s8>) = COPY $d1 2701 %4:fpr(<8 x s8>) = G_ICMP intpred(sge), %0(<8 x s8>), %1 2702 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 2703 $d0 = COPY %3(<8 x s8>) 2704 RET_ReallyLR implicit $d0 2705 2706... 2707--- 2708name: test_v2i64_slt 2709alignment: 4 2710legalized: true 2711regBankSelected: true 2712tracksRegLiveness: true 2713registers: 2714 - { id: 0, class: fpr } 2715 - { id: 1, class: fpr } 2716 - { id: 2, class: _ } 2717 - { id: 3, class: fpr } 2718 - { id: 4, class: fpr } 2719machineFunctionInfo: {} 2720body: | 2721 bb.1 (%ir-block.0): 2722 liveins: $q0, $q1 2723 2724 ; CHECK-LABEL: name: test_v2i64_slt 2725 ; CHECK: liveins: $q0, $q1 2726 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2727 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2728 ; CHECK: [[CMGTv2i64_:%[0-9]+]]:fpr128 = CMGTv2i64 [[COPY1]], [[COPY]] 2729 ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGTv2i64_]] 2730 ; CHECK: $d0 = COPY [[XTNv2i32_]] 2731 ; CHECK: RET_ReallyLR implicit $d0 2732 %0:fpr(<2 x s64>) = COPY $q0 2733 %1:fpr(<2 x s64>) = COPY $q1 2734 %4:fpr(<2 x s64>) = G_ICMP intpred(slt), %0(<2 x s64>), %1 2735 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 2736 $d0 = COPY %3(<2 x s32>) 2737 RET_ReallyLR implicit $d0 2738 2739... 2740--- 2741name: test_v4i32_slt 2742alignment: 4 2743legalized: true 2744regBankSelected: true 2745tracksRegLiveness: true 2746registers: 2747 - { id: 0, class: fpr } 2748 - { id: 1, class: fpr } 2749 - { id: 2, class: _ } 2750 - { id: 3, class: fpr } 2751 - { id: 4, class: fpr } 2752machineFunctionInfo: {} 2753body: | 2754 bb.1 (%ir-block.0): 2755 liveins: $q0, $q1 2756 2757 ; CHECK-LABEL: name: test_v4i32_slt 2758 ; CHECK: liveins: $q0, $q1 2759 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2760 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2761 ; CHECK: [[CMGTv4i32_:%[0-9]+]]:fpr128 = CMGTv4i32 [[COPY1]], [[COPY]] 2762 ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGTv4i32_]] 2763 ; CHECK: $d0 = COPY [[XTNv4i16_]] 2764 ; CHECK: RET_ReallyLR implicit $d0 2765 %0:fpr(<4 x s32>) = COPY $q0 2766 %1:fpr(<4 x s32>) = COPY $q1 2767 %4:fpr(<4 x s32>) = G_ICMP intpred(slt), %0(<4 x s32>), %1 2768 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 2769 $d0 = COPY %3(<4 x s16>) 2770 RET_ReallyLR implicit $d0 2771 2772... 2773--- 2774name: test_v2i32_slt 2775alignment: 4 2776legalized: true 2777regBankSelected: true 2778tracksRegLiveness: true 2779registers: 2780 - { id: 0, class: fpr } 2781 - { id: 1, class: fpr } 2782 - { id: 2, class: _ } 2783 - { id: 3, class: fpr } 2784 - { id: 4, class: fpr } 2785machineFunctionInfo: {} 2786body: | 2787 bb.1 (%ir-block.0): 2788 liveins: $d0, $d1 2789 2790 ; CHECK-LABEL: name: test_v2i32_slt 2791 ; CHECK: liveins: $d0, $d1 2792 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2793 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2794 ; CHECK: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[COPY1]], [[COPY]] 2795 ; CHECK: $d0 = COPY [[CMGTv2i32_]] 2796 ; CHECK: RET_ReallyLR implicit $d0 2797 %0:fpr(<2 x s32>) = COPY $d0 2798 %1:fpr(<2 x s32>) = COPY $d1 2799 %4:fpr(<2 x s32>) = G_ICMP intpred(slt), %0(<2 x s32>), %1 2800 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 2801 $d0 = COPY %3(<2 x s32>) 2802 RET_ReallyLR implicit $d0 2803 2804... 2805--- 2806name: test_v2i16_slt 2807alignment: 4 2808legalized: true 2809regBankSelected: true 2810tracksRegLiveness: true 2811registers: 2812 - { id: 0, class: _ } 2813 - { id: 1, class: _ } 2814 - { id: 2, class: fpr } 2815 - { id: 3, class: fpr } 2816 - { id: 4, class: _ } 2817 - { id: 5, class: fpr } 2818 - { id: 6, class: _ } 2819 - { id: 7, class: fpr } 2820 - { id: 8, class: fpr } 2821 - { id: 9, class: fpr } 2822 - { id: 10, class: gpr } 2823 - { id: 11, class: fpr } 2824 - { id: 12, class: fpr } 2825 - { id: 13, class: fpr } 2826 - { id: 14, class: gpr } 2827 - { id: 15, class: fpr } 2828 - { id: 16, class: fpr } 2829 - { id: 17, class: fpr } 2830machineFunctionInfo: {} 2831body: | 2832 bb.1 (%ir-block.0): 2833 liveins: $d0, $d1 2834 2835 ; CHECK-LABEL: name: test_v2i16_slt 2836 ; CHECK: liveins: $d0, $d1 2837 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2838 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2839 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 2840 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 2841 ; CHECK: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 16 2842 ; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[LDRDui]] 2843 ; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]] 2844 ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 2845 ; CHECK: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 2846 ; CHECK: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 16 2847 ; CHECK: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[LDRDui1]] 2848 ; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]] 2849 ; CHECK: [[CMGTv2i32_:%[0-9]+]]:fpr64 = CMGTv2i32 [[SSHLv2i32_1]], [[SSHLv2i32_]] 2850 ; CHECK: $d0 = COPY [[CMGTv2i32_]] 2851 ; CHECK: RET_ReallyLR implicit $d0 2852 %2:fpr(<2 x s32>) = COPY $d0 2853 %3:fpr(<2 x s32>) = COPY $d1 2854 %14:gpr(s32) = G_CONSTANT i32 16 2855 %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32) 2856 %16:fpr(<2 x s32>) = COPY %2(<2 x s32>) 2857 %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>) 2858 %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>) 2859 %10:gpr(s32) = G_CONSTANT i32 16 2860 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 2861 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 2862 %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>) 2863 %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>) 2864 %9:fpr(<2 x s32>) = G_ICMP intpred(slt), %7(<2 x s32>), %8 2865 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 2866 $d0 = COPY %5(<2 x s32>) 2867 RET_ReallyLR implicit $d0 2868 2869... 2870--- 2871name: test_v8i16_slt 2872alignment: 4 2873legalized: true 2874regBankSelected: true 2875tracksRegLiveness: true 2876registers: 2877 - { id: 0, class: fpr } 2878 - { id: 1, class: fpr } 2879 - { id: 2, class: _ } 2880 - { id: 3, class: fpr } 2881 - { id: 4, class: fpr } 2882machineFunctionInfo: {} 2883body: | 2884 bb.1 (%ir-block.0): 2885 liveins: $q0, $q1 2886 2887 ; CHECK-LABEL: name: test_v8i16_slt 2888 ; CHECK: liveins: $q0, $q1 2889 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2890 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2891 ; CHECK: [[CMGTv8i16_:%[0-9]+]]:fpr128 = CMGTv8i16 [[COPY1]], [[COPY]] 2892 ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGTv8i16_]] 2893 ; CHECK: $d0 = COPY [[XTNv8i8_]] 2894 ; CHECK: RET_ReallyLR implicit $d0 2895 %0:fpr(<8 x s16>) = COPY $q0 2896 %1:fpr(<8 x s16>) = COPY $q1 2897 %4:fpr(<8 x s16>) = G_ICMP intpred(slt), %0(<8 x s16>), %1 2898 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 2899 $d0 = COPY %3(<8 x s8>) 2900 RET_ReallyLR implicit $d0 2901 2902... 2903--- 2904name: test_v4i16_slt 2905alignment: 4 2906legalized: true 2907regBankSelected: true 2908tracksRegLiveness: true 2909registers: 2910 - { id: 0, class: fpr } 2911 - { id: 1, class: fpr } 2912 - { id: 2, class: _ } 2913 - { id: 3, class: fpr } 2914 - { id: 4, class: fpr } 2915machineFunctionInfo: {} 2916body: | 2917 bb.1 (%ir-block.0): 2918 liveins: $d0, $d1 2919 2920 ; CHECK-LABEL: name: test_v4i16_slt 2921 ; CHECK: liveins: $d0, $d1 2922 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2923 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2924 ; CHECK: [[CMGTv4i16_:%[0-9]+]]:fpr64 = CMGTv4i16 [[COPY1]], [[COPY]] 2925 ; CHECK: $d0 = COPY [[CMGTv4i16_]] 2926 ; CHECK: RET_ReallyLR implicit $d0 2927 %0:fpr(<4 x s16>) = COPY $d0 2928 %1:fpr(<4 x s16>) = COPY $d1 2929 %4:fpr(<4 x s16>) = G_ICMP intpred(slt), %0(<4 x s16>), %1 2930 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 2931 $d0 = COPY %3(<4 x s16>) 2932 RET_ReallyLR implicit $d0 2933 2934... 2935--- 2936name: test_v16i8_slt 2937alignment: 4 2938legalized: true 2939regBankSelected: true 2940tracksRegLiveness: true 2941registers: 2942 - { id: 0, class: fpr } 2943 - { id: 1, class: fpr } 2944 - { id: 2, class: _ } 2945 - { id: 3, class: fpr } 2946 - { id: 4, class: fpr } 2947machineFunctionInfo: {} 2948body: | 2949 bb.1 (%ir-block.0): 2950 liveins: $q0, $q1 2951 2952 ; CHECK-LABEL: name: test_v16i8_slt 2953 ; CHECK: liveins: $q0, $q1 2954 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 2955 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2956 ; CHECK: [[CMGTv16i8_:%[0-9]+]]:fpr128 = CMGTv16i8 [[COPY1]], [[COPY]] 2957 ; CHECK: $q0 = COPY [[CMGTv16i8_]] 2958 ; CHECK: RET_ReallyLR implicit $q0 2959 %0:fpr(<16 x s8>) = COPY $q0 2960 %1:fpr(<16 x s8>) = COPY $q1 2961 %4:fpr(<16 x s8>) = G_ICMP intpred(slt), %0(<16 x s8>), %1 2962 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 2963 $q0 = COPY %3(<16 x s8>) 2964 RET_ReallyLR implicit $q0 2965 2966... 2967--- 2968name: test_v8i8_slt 2969alignment: 4 2970legalized: true 2971regBankSelected: true 2972tracksRegLiveness: true 2973registers: 2974 - { id: 0, class: fpr } 2975 - { id: 1, class: fpr } 2976 - { id: 2, class: _ } 2977 - { id: 3, class: fpr } 2978 - { id: 4, class: fpr } 2979machineFunctionInfo: {} 2980body: | 2981 bb.1 (%ir-block.0): 2982 liveins: $d0, $d1 2983 2984 ; CHECK-LABEL: name: test_v8i8_slt 2985 ; CHECK: liveins: $d0, $d1 2986 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2987 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2988 ; CHECK: [[CMGTv8i8_:%[0-9]+]]:fpr64 = CMGTv8i8 [[COPY1]], [[COPY]] 2989 ; CHECK: $d0 = COPY [[CMGTv8i8_]] 2990 ; CHECK: RET_ReallyLR implicit $d0 2991 %0:fpr(<8 x s8>) = COPY $d0 2992 %1:fpr(<8 x s8>) = COPY $d1 2993 %4:fpr(<8 x s8>) = G_ICMP intpred(slt), %0(<8 x s8>), %1 2994 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 2995 $d0 = COPY %3(<8 x s8>) 2996 RET_ReallyLR implicit $d0 2997 2998... 2999--- 3000name: test_v2i64_sle 3001alignment: 4 3002legalized: true 3003regBankSelected: true 3004tracksRegLiveness: true 3005registers: 3006 - { id: 0, class: fpr } 3007 - { id: 1, class: fpr } 3008 - { id: 2, class: _ } 3009 - { id: 3, class: fpr } 3010 - { id: 4, class: fpr } 3011machineFunctionInfo: {} 3012body: | 3013 bb.1 (%ir-block.0): 3014 liveins: $q0, $q1 3015 3016 ; CHECK-LABEL: name: test_v2i64_sle 3017 ; CHECK: liveins: $q0, $q1 3018 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 3019 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 3020 ; CHECK: [[CMGEv2i64_:%[0-9]+]]:fpr128 = CMGEv2i64 [[COPY1]], [[COPY]] 3021 ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[CMGEv2i64_]] 3022 ; CHECK: $d0 = COPY [[XTNv2i32_]] 3023 ; CHECK: RET_ReallyLR implicit $d0 3024 %0:fpr(<2 x s64>) = COPY $q0 3025 %1:fpr(<2 x s64>) = COPY $q1 3026 %4:fpr(<2 x s64>) = G_ICMP intpred(sle), %0(<2 x s64>), %1 3027 %3:fpr(<2 x s32>) = G_TRUNC %4(<2 x s64>) 3028 $d0 = COPY %3(<2 x s32>) 3029 RET_ReallyLR implicit $d0 3030 3031... 3032--- 3033name: test_v4i32_sle 3034alignment: 4 3035legalized: true 3036regBankSelected: true 3037tracksRegLiveness: true 3038registers: 3039 - { id: 0, class: fpr } 3040 - { id: 1, class: fpr } 3041 - { id: 2, class: _ } 3042 - { id: 3, class: fpr } 3043 - { id: 4, class: fpr } 3044machineFunctionInfo: {} 3045body: | 3046 bb.1 (%ir-block.0): 3047 liveins: $q0, $q1 3048 3049 ; CHECK-LABEL: name: test_v4i32_sle 3050 ; CHECK: liveins: $q0, $q1 3051 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 3052 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 3053 ; CHECK: [[CMGEv4i32_:%[0-9]+]]:fpr128 = CMGEv4i32 [[COPY1]], [[COPY]] 3054 ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[CMGEv4i32_]] 3055 ; CHECK: $d0 = COPY [[XTNv4i16_]] 3056 ; CHECK: RET_ReallyLR implicit $d0 3057 %0:fpr(<4 x s32>) = COPY $q0 3058 %1:fpr(<4 x s32>) = COPY $q1 3059 %4:fpr(<4 x s32>) = G_ICMP intpred(sle), %0(<4 x s32>), %1 3060 %3:fpr(<4 x s16>) = G_TRUNC %4(<4 x s32>) 3061 $d0 = COPY %3(<4 x s16>) 3062 RET_ReallyLR implicit $d0 3063 3064... 3065--- 3066name: test_v2i32_sle 3067alignment: 4 3068legalized: true 3069regBankSelected: true 3070tracksRegLiveness: true 3071registers: 3072 - { id: 0, class: fpr } 3073 - { id: 1, class: fpr } 3074 - { id: 2, class: _ } 3075 - { id: 3, class: fpr } 3076 - { id: 4, class: fpr } 3077machineFunctionInfo: {} 3078body: | 3079 bb.1 (%ir-block.0): 3080 liveins: $d0, $d1 3081 3082 ; CHECK-LABEL: name: test_v2i32_sle 3083 ; CHECK: liveins: $d0, $d1 3084 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3085 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 3086 ; CHECK: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[COPY1]], [[COPY]] 3087 ; CHECK: $d0 = COPY [[CMGEv2i32_]] 3088 ; CHECK: RET_ReallyLR implicit $d0 3089 %0:fpr(<2 x s32>) = COPY $d0 3090 %1:fpr(<2 x s32>) = COPY $d1 3091 %4:fpr(<2 x s32>) = G_ICMP intpred(sle), %0(<2 x s32>), %1 3092 %3:fpr(<2 x s32>) = COPY %4(<2 x s32>) 3093 $d0 = COPY %3(<2 x s32>) 3094 RET_ReallyLR implicit $d0 3095 3096... 3097--- 3098name: test_v2i16_sle 3099alignment: 4 3100legalized: true 3101regBankSelected: true 3102tracksRegLiveness: true 3103registers: 3104 - { id: 0, class: _ } 3105 - { id: 1, class: _ } 3106 - { id: 2, class: fpr } 3107 - { id: 3, class: fpr } 3108 - { id: 4, class: _ } 3109 - { id: 5, class: fpr } 3110 - { id: 6, class: _ } 3111 - { id: 7, class: fpr } 3112 - { id: 8, class: fpr } 3113 - { id: 9, class: fpr } 3114 - { id: 10, class: gpr } 3115 - { id: 11, class: fpr } 3116 - { id: 12, class: fpr } 3117 - { id: 13, class: fpr } 3118 - { id: 14, class: gpr } 3119 - { id: 15, class: fpr } 3120 - { id: 16, class: fpr } 3121 - { id: 17, class: fpr } 3122machineFunctionInfo: {} 3123body: | 3124 bb.1 (%ir-block.0): 3125 liveins: $d0, $d1 3126 3127 ; CHECK-LABEL: name: test_v2i16_sle 3128 ; CHECK: liveins: $d0, $d1 3129 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3130 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 3131 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 3132 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 3133 ; CHECK: [[SHLv2i32_shift:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY]], 16 3134 ; CHECK: [[NEGv2i32_:%[0-9]+]]:fpr64 = NEGv2i32 [[LDRDui]] 3135 ; CHECK: [[SSHLv2i32_:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift]], [[NEGv2i32_]] 3136 ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 3137 ; CHECK: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 3138 ; CHECK: [[SHLv2i32_shift1:%[0-9]+]]:fpr64 = SHLv2i32_shift [[COPY1]], 16 3139 ; CHECK: [[NEGv2i32_1:%[0-9]+]]:fpr64 = NEGv2i32 [[LDRDui1]] 3140 ; CHECK: [[SSHLv2i32_1:%[0-9]+]]:fpr64 = SSHLv2i32 [[SHLv2i32_shift1]], [[NEGv2i32_1]] 3141 ; CHECK: [[CMGEv2i32_:%[0-9]+]]:fpr64 = CMGEv2i32 [[SSHLv2i32_1]], [[SSHLv2i32_]] 3142 ; CHECK: $d0 = COPY [[CMGEv2i32_]] 3143 ; CHECK: RET_ReallyLR implicit $d0 3144 %2:fpr(<2 x s32>) = COPY $d0 3145 %3:fpr(<2 x s32>) = COPY $d1 3146 %14:gpr(s32) = G_CONSTANT i32 16 3147 %15:fpr(<2 x s32>) = G_BUILD_VECTOR %14(s32), %14(s32) 3148 %16:fpr(<2 x s32>) = COPY %2(<2 x s32>) 3149 %17:fpr(<2 x s32>) = G_SHL %16, %15(<2 x s32>) 3150 %7:fpr(<2 x s32>) = G_ASHR %17, %15(<2 x s32>) 3151 %10:gpr(s32) = G_CONSTANT i32 16 3152 %11:fpr(<2 x s32>) = G_BUILD_VECTOR %10(s32), %10(s32) 3153 %12:fpr(<2 x s32>) = COPY %3(<2 x s32>) 3154 %13:fpr(<2 x s32>) = G_SHL %12, %11(<2 x s32>) 3155 %8:fpr(<2 x s32>) = G_ASHR %13, %11(<2 x s32>) 3156 %9:fpr(<2 x s32>) = G_ICMP intpred(sle), %7(<2 x s32>), %8 3157 %5:fpr(<2 x s32>) = COPY %9(<2 x s32>) 3158 $d0 = COPY %5(<2 x s32>) 3159 RET_ReallyLR implicit $d0 3160 3161... 3162--- 3163name: test_v8i16_sle 3164alignment: 4 3165legalized: true 3166regBankSelected: true 3167tracksRegLiveness: true 3168registers: 3169 - { id: 0, class: fpr } 3170 - { id: 1, class: fpr } 3171 - { id: 2, class: _ } 3172 - { id: 3, class: fpr } 3173 - { id: 4, class: fpr } 3174machineFunctionInfo: {} 3175body: | 3176 bb.1 (%ir-block.0): 3177 liveins: $q0, $q1 3178 3179 ; CHECK-LABEL: name: test_v8i16_sle 3180 ; CHECK: liveins: $q0, $q1 3181 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 3182 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 3183 ; CHECK: [[CMGEv8i16_:%[0-9]+]]:fpr128 = CMGEv8i16 [[COPY1]], [[COPY]] 3184 ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[CMGEv8i16_]] 3185 ; CHECK: $d0 = COPY [[XTNv8i8_]] 3186 ; CHECK: RET_ReallyLR implicit $d0 3187 %0:fpr(<8 x s16>) = COPY $q0 3188 %1:fpr(<8 x s16>) = COPY $q1 3189 %4:fpr(<8 x s16>) = G_ICMP intpred(sle), %0(<8 x s16>), %1 3190 %3:fpr(<8 x s8>) = G_TRUNC %4(<8 x s16>) 3191 $d0 = COPY %3(<8 x s8>) 3192 RET_ReallyLR implicit $d0 3193 3194... 3195--- 3196name: test_v4i16_sle 3197alignment: 4 3198legalized: true 3199regBankSelected: true 3200tracksRegLiveness: true 3201registers: 3202 - { id: 0, class: fpr } 3203 - { id: 1, class: fpr } 3204 - { id: 2, class: _ } 3205 - { id: 3, class: fpr } 3206 - { id: 4, class: fpr } 3207machineFunctionInfo: {} 3208body: | 3209 bb.1 (%ir-block.0): 3210 liveins: $d0, $d1 3211 3212 ; CHECK-LABEL: name: test_v4i16_sle 3213 ; CHECK: liveins: $d0, $d1 3214 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3215 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 3216 ; CHECK: [[CMGEv4i16_:%[0-9]+]]:fpr64 = CMGEv4i16 [[COPY1]], [[COPY]] 3217 ; CHECK: $d0 = COPY [[CMGEv4i16_]] 3218 ; CHECK: RET_ReallyLR implicit $d0 3219 %0:fpr(<4 x s16>) = COPY $d0 3220 %1:fpr(<4 x s16>) = COPY $d1 3221 %4:fpr(<4 x s16>) = G_ICMP intpred(sle), %0(<4 x s16>), %1 3222 %3:fpr(<4 x s16>) = COPY %4(<4 x s16>) 3223 $d0 = COPY %3(<4 x s16>) 3224 RET_ReallyLR implicit $d0 3225 3226... 3227--- 3228name: test_v16i8_sle 3229alignment: 4 3230legalized: true 3231regBankSelected: true 3232tracksRegLiveness: true 3233registers: 3234 - { id: 0, class: fpr } 3235 - { id: 1, class: fpr } 3236 - { id: 2, class: _ } 3237 - { id: 3, class: fpr } 3238 - { id: 4, class: fpr } 3239machineFunctionInfo: {} 3240body: | 3241 bb.1 (%ir-block.0): 3242 liveins: $q0, $q1 3243 3244 ; CHECK-LABEL: name: test_v16i8_sle 3245 ; CHECK: liveins: $q0, $q1 3246 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 3247 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 3248 ; CHECK: [[CMGEv16i8_:%[0-9]+]]:fpr128 = CMGEv16i8 [[COPY1]], [[COPY]] 3249 ; CHECK: $q0 = COPY [[CMGEv16i8_]] 3250 ; CHECK: RET_ReallyLR implicit $q0 3251 %0:fpr(<16 x s8>) = COPY $q0 3252 %1:fpr(<16 x s8>) = COPY $q1 3253 %4:fpr(<16 x s8>) = G_ICMP intpred(sle), %0(<16 x s8>), %1 3254 %3:fpr(<16 x s8>) = COPY %4(<16 x s8>) 3255 $q0 = COPY %3(<16 x s8>) 3256 RET_ReallyLR implicit $q0 3257 3258... 3259--- 3260name: test_v8i8_sle 3261alignment: 4 3262legalized: true 3263regBankSelected: true 3264tracksRegLiveness: true 3265registers: 3266 - { id: 0, class: fpr } 3267 - { id: 1, class: fpr } 3268 - { id: 2, class: _ } 3269 - { id: 3, class: fpr } 3270 - { id: 4, class: fpr } 3271machineFunctionInfo: {} 3272body: | 3273 bb.1 (%ir-block.0): 3274 liveins: $d0, $d1 3275 3276 ; CHECK-LABEL: name: test_v8i8_sle 3277 ; CHECK: liveins: $d0, $d1 3278 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3279 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 3280 ; CHECK: [[CMGEv8i8_:%[0-9]+]]:fpr64 = CMGEv8i8 [[COPY1]], [[COPY]] 3281 ; CHECK: $d0 = COPY [[CMGEv8i8_]] 3282 ; CHECK: RET_ReallyLR implicit $d0 3283 %0:fpr(<8 x s8>) = COPY $d0 3284 %1:fpr(<8 x s8>) = COPY $d1 3285 %4:fpr(<8 x s8>) = G_ICMP intpred(sle), %0(<8 x s8>), %1 3286 %3:fpr(<8 x s8>) = COPY %4(<8 x s8>) 3287 $d0 = COPY %3(<8 x s8>) 3288 RET_ReallyLR implicit $d0 3289 3290... 3291