1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3#
4# Test that we can select G_TRN1 and G_TRN2.
5#
6# Each testcase is named based off of the instruction which should be selected.
7
8...
9---
10name:            TRN1v2i32
11alignment:       4
12legalized:       true
13regBankSelected: true
14tracksRegLiveness: true
15body:             |
16  bb.0:
17    liveins: $d0, $d1
18    ; CHECK-LABEL: name: TRN1v2i32
19    ; CHECK: liveins: $d0, $d1
20    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
21    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
22    ; CHECK: [[TRN1v2i32_:%[0-9]+]]:fpr64 = TRN1v2i32 [[COPY]], [[COPY1]]
23    ; CHECK: $d0 = COPY [[TRN1v2i32_]]
24    ; CHECK: RET_ReallyLR implicit $d0
25    %0:fpr(<2 x s32>) = COPY $d0
26    %1:fpr(<2 x s32>) = COPY $d1
27    %2:fpr(<2 x s32>) = G_TRN1 %0, %1
28    $d0 = COPY %2(<2 x s32>)
29    RET_ReallyLR implicit $d0
30
31...
32---
33name:            TRN1v2i64
34alignment:       4
35legalized:       true
36regBankSelected: true
37tracksRegLiveness: true
38body:             |
39  bb.0:
40    liveins: $q0, $q1
41    ; CHECK-LABEL: name: TRN1v2i64
42    ; CHECK: liveins: $q0, $q1
43    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
44    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
45    ; CHECK: [[TRN1v2i64_:%[0-9]+]]:fpr128 = TRN1v2i64 [[COPY]], [[COPY1]]
46    ; CHECK: $q0 = COPY [[TRN1v2i64_]]
47    ; CHECK: RET_ReallyLR implicit $q0
48    %0:fpr(<2 x s64>) = COPY $q0
49    %1:fpr(<2 x s64>) = COPY $q1
50    %2:fpr(<2 x s64>) = G_TRN1 %0, %1
51    $q0 = COPY %2(<2 x s64>)
52    RET_ReallyLR implicit $q0
53
54...
55---
56name:            TRN1v4i16
57alignment:       4
58legalized:       true
59regBankSelected: true
60tracksRegLiveness: true
61body:             |
62  bb.0:
63    liveins: $d0, $d1
64    ; CHECK-LABEL: name: TRN1v4i16
65    ; CHECK: liveins: $d0, $d1
66    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
67    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
68    ; CHECK: [[TRN1v4i16_:%[0-9]+]]:fpr64 = TRN1v4i16 [[COPY]], [[COPY1]]
69    ; CHECK: $d0 = COPY [[TRN1v4i16_]]
70    ; CHECK: RET_ReallyLR implicit $d0
71    %0:fpr(<4 x s16>) = COPY $d0
72    %1:fpr(<4 x s16>) = COPY $d1
73    %2:fpr(<4 x s16>) = G_TRN1 %0, %1
74    $d0 = COPY %2(<4 x s16>)
75    RET_ReallyLR implicit $d0
76
77...
78---
79name:            TRN1v4i32
80alignment:       4
81legalized:       true
82regBankSelected: true
83tracksRegLiveness: true
84body:             |
85  bb.0:
86    liveins: $q0, $q1
87    ; CHECK-LABEL: name: TRN1v4i32
88    ; CHECK: liveins: $q0, $q1
89    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
90    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
91    ; CHECK: [[TRN1v4i32_:%[0-9]+]]:fpr128 = TRN1v4i32 [[COPY]], [[COPY1]]
92    ; CHECK: $q0 = COPY [[TRN1v4i32_]]
93    ; CHECK: RET_ReallyLR implicit $q0
94    %0:fpr(<4 x s32>) = COPY $q0
95    %1:fpr(<4 x s32>) = COPY $q1
96    %2:fpr(<4 x s32>) = G_TRN1 %0, %1
97    $q0 = COPY %2(<4 x s32>)
98    RET_ReallyLR implicit $q0
99
100...
101---
102name:            TRN1v8i8
103alignment:       4
104legalized:       true
105regBankSelected: true
106tracksRegLiveness: true
107body:             |
108  bb.0:
109    liveins: $d0, $d1
110    ; CHECK-LABEL: name: TRN1v8i8
111    ; CHECK: liveins: $d0, $d1
112    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
113    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
114    ; CHECK: [[TRN1v8i8_:%[0-9]+]]:fpr64 = TRN1v8i8 [[COPY]], [[COPY1]]
115    ; CHECK: $d0 = COPY [[TRN1v8i8_]]
116    ; CHECK: RET_ReallyLR implicit $d0
117    %0:fpr(<8 x s8>) = COPY $d0
118    %1:fpr(<8 x s8>) = COPY $d1
119    %2:fpr(<8 x s8>) = G_TRN1 %0, %1
120    $d0 = COPY %2(<8 x s8>)
121    RET_ReallyLR implicit $d0
122
123...
124---
125name:            TRN1v8i16
126alignment:       4
127legalized:       true
128regBankSelected: true
129tracksRegLiveness: true
130body:             |
131  bb.0:
132    liveins: $q0, $q1
133    ; CHECK-LABEL: name: TRN1v8i16
134    ; CHECK: liveins: $q0, $q1
135    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
136    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
137    ; CHECK: [[TRN1v8i16_:%[0-9]+]]:fpr128 = TRN1v8i16 [[COPY]], [[COPY1]]
138    ; CHECK: $q0 = COPY [[TRN1v8i16_]]
139    ; CHECK: RET_ReallyLR implicit $q0
140    %0:fpr(<8 x s16>) = COPY $q0
141    %1:fpr(<8 x s16>) = COPY $q1
142    %2:fpr(<8 x s16>) = G_TRN1 %0, %1
143    $q0 = COPY %2(<8 x s16>)
144    RET_ReallyLR implicit $q0
145
146...
147---
148name:            TRN1v16i8
149alignment:       4
150legalized:       true
151regBankSelected: true
152tracksRegLiveness: true
153body:             |
154  bb.0:
155    liveins: $q0, $q1
156    ; CHECK-LABEL: name: TRN1v16i8
157    ; CHECK: liveins: $q0, $q1
158    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
159    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
160    ; CHECK: [[TRN1v16i8_:%[0-9]+]]:fpr128 = TRN1v16i8 [[COPY]], [[COPY1]]
161    ; CHECK: $q0 = COPY [[TRN1v16i8_]]
162    ; CHECK: RET_ReallyLR implicit $q0
163    %0:fpr(<16 x s8>) = COPY $q0
164    %1:fpr(<16 x s8>) = COPY $q1
165    %2:fpr(<16 x s8>) = G_TRN1 %0, %1
166    $q0 = COPY %2(<16 x s8>)
167    RET_ReallyLR implicit $q0
168
169...
170---
171name:            TRN2v2i32
172alignment:       4
173legalized:       true
174regBankSelected: true
175tracksRegLiveness: true
176body:             |
177  bb.0:
178    liveins: $d0, $d1
179    ; CHECK-LABEL: name: TRN2v2i32
180    ; CHECK: liveins: $d0, $d1
181    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
182    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
183    ; CHECK: [[TRN2v2i32_:%[0-9]+]]:fpr64 = TRN2v2i32 [[COPY]], [[COPY1]]
184    ; CHECK: $d0 = COPY [[TRN2v2i32_]]
185    ; CHECK: RET_ReallyLR implicit $d0
186    %0:fpr(<2 x s32>) = COPY $d0
187    %1:fpr(<2 x s32>) = COPY $d1
188    %2:fpr(<2 x s32>) = G_TRN2 %0, %1
189    $d0 = COPY %2(<2 x s32>)
190    RET_ReallyLR implicit $d0
191
192...
193---
194name:            TRN2v2i64
195alignment:       4
196legalized:       true
197regBankSelected: true
198tracksRegLiveness: true
199body:             |
200  bb.0:
201    liveins: $q0, $q1
202    ; CHECK-LABEL: name: TRN2v2i64
203    ; CHECK: liveins: $q0, $q1
204    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
205    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
206    ; CHECK: [[TRN2v2i64_:%[0-9]+]]:fpr128 = TRN2v2i64 [[COPY]], [[COPY1]]
207    ; CHECK: $q0 = COPY [[TRN2v2i64_]]
208    ; CHECK: RET_ReallyLR implicit $q0
209    %0:fpr(<2 x s64>) = COPY $q0
210    %1:fpr(<2 x s64>) = COPY $q1
211    %2:fpr(<2 x s64>) = G_TRN2 %0, %1
212    $q0 = COPY %2(<2 x s64>)
213    RET_ReallyLR implicit $q0
214
215...
216---
217name:            TRN2v4i16
218alignment:       4
219legalized:       true
220regBankSelected: true
221tracksRegLiveness: true
222body:             |
223  bb.0:
224    liveins: $d0, $d1
225    ; CHECK-LABEL: name: TRN2v4i16
226    ; CHECK: liveins: $d0, $d1
227    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
228    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
229    ; CHECK: [[TRN2v4i16_:%[0-9]+]]:fpr64 = TRN2v4i16 [[COPY]], [[COPY1]]
230    ; CHECK: $d0 = COPY [[TRN2v4i16_]]
231    ; CHECK: RET_ReallyLR implicit $d0
232    %0:fpr(<4 x s16>) = COPY $d0
233    %1:fpr(<4 x s16>) = COPY $d1
234    %2:fpr(<4 x s16>) = G_TRN2 %0, %1
235    $d0 = COPY %2(<4 x s16>)
236    RET_ReallyLR implicit $d0
237
238...
239---
240name:            TRN2v4i32
241alignment:       4
242legalized:       true
243regBankSelected: true
244tracksRegLiveness: true
245body:             |
246  bb.0:
247    liveins: $q0, $q1
248    ; CHECK-LABEL: name: TRN2v4i32
249    ; CHECK: liveins: $q0, $q1
250    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
251    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
252    ; CHECK: [[TRN2v4i32_:%[0-9]+]]:fpr128 = TRN2v4i32 [[COPY]], [[COPY1]]
253    ; CHECK: $q0 = COPY [[TRN2v4i32_]]
254    ; CHECK: RET_ReallyLR implicit $q0
255    %0:fpr(<4 x s32>) = COPY $q0
256    %1:fpr(<4 x s32>) = COPY $q1
257    %2:fpr(<4 x s32>) = G_TRN2 %0, %1
258    $q0 = COPY %2(<4 x s32>)
259    RET_ReallyLR implicit $q0
260
261...
262---
263name:            TRN2v8i8
264alignment:       4
265legalized:       true
266regBankSelected: true
267tracksRegLiveness: true
268body:             |
269  bb.0:
270    liveins: $d0, $d1
271    ; CHECK-LABEL: name: TRN2v8i8
272    ; CHECK: liveins: $d0, $d1
273    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
274    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
275    ; CHECK: [[TRN2v8i8_:%[0-9]+]]:fpr64 = TRN2v8i8 [[COPY]], [[COPY1]]
276    ; CHECK: $d0 = COPY [[TRN2v8i8_]]
277    ; CHECK: RET_ReallyLR implicit $d0
278    %0:fpr(<8 x s8>) = COPY $d0
279    %1:fpr(<8 x s8>) = COPY $d1
280    %2:fpr(<8 x s8>) = G_TRN2 %0, %1
281    $d0 = COPY %2(<8 x s8>)
282    RET_ReallyLR implicit $d0
283
284...
285---
286name:            TRN2v8i16
287alignment:       4
288legalized:       true
289regBankSelected: true
290tracksRegLiveness: true
291body:             |
292  bb.0:
293    liveins: $q0, $q1
294    ; CHECK-LABEL: name: TRN2v8i16
295    ; CHECK: liveins: $q0, $q1
296    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
297    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
298    ; CHECK: [[TRN2v8i16_:%[0-9]+]]:fpr128 = TRN2v8i16 [[COPY]], [[COPY1]]
299    ; CHECK: $q0 = COPY [[TRN2v8i16_]]
300    ; CHECK: RET_ReallyLR implicit $q0
301    %0:fpr(<8 x s16>) = COPY $q0
302    %1:fpr(<8 x s16>) = COPY $q1
303    %2:fpr(<8 x s16>) = G_TRN2 %0, %1
304    $q0 = COPY %2(<8 x s16>)
305    RET_ReallyLR implicit $q0
306
307...
308---
309name:            TRN2v16i8
310alignment:       4
311legalized:       true
312regBankSelected: true
313tracksRegLiveness: true
314body:             |
315  bb.0:
316    liveins: $q0, $q1
317    ; CHECK-LABEL: name: TRN2v16i8
318    ; CHECK: liveins: $q0, $q1
319    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
320    ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
321    ; CHECK: [[TRN2v16i8_:%[0-9]+]]:fpr128 = TRN2v16i8 [[COPY]], [[COPY1]]
322    ; CHECK: $q0 = COPY [[TRN2v16i8_]]
323    ; CHECK: RET_ReallyLR implicit $q0
324    %0:fpr(<16 x s8>) = COPY $q0
325    %1:fpr(<16 x s8>) = COPY $q1
326    %2:fpr(<16 x s8>) = G_TRN2 %0, %1
327    $q0 = COPY %2(<16 x s8>)
328    RET_ReallyLR implicit $q0
329