1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s
3...
4---
5name:            v2s32_fpr
6alignment:       4
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10registers:
11  - { id: 0, class: fpr }
12  - { id: 1, class: fpr }
13  - { id: 2, class: gpr }
14  - { id: 3, class: fpr }
15body:             |
16  bb.0:
17    liveins: $d0
18
19    ; CHECK-LABEL: name: v2s32_fpr
20    ; CHECK: liveins: $d0
21    ; CHECK-NEXT: {{  $}}
22    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
23    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
24    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
25    ; CHECK-NEXT: [[DUPi32_:%[0-9]+]]:fpr32 = DUPi32 [[INSERT_SUBREG]], 1
26    ; CHECK-NEXT: $s0 = COPY [[DUPi32_]]
27    ; CHECK-NEXT: RET_ReallyLR implicit $s0
28    %0:fpr(<2 x s32>) = COPY $d0
29    %2:gpr(s64) = G_CONSTANT i64 1
30    %3:fpr(s64) = COPY %2(s64)
31    %1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
32    $s0 = COPY %1(s32)
33    RET_ReallyLR implicit $s0
34
35...
36---
37name:            v2s32_fpr_idx0
38alignment:       4
39legalized:       true
40regBankSelected: true
41tracksRegLiveness: true
42body:             |
43  bb.0:
44    liveins: $d0
45    ; CHECK-LABEL: name: v2s32_fpr_idx0
46    ; CHECK: liveins: $d0
47    ; CHECK-NEXT: {{  $}}
48    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
49    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
50    ; CHECK-NEXT: $s0 = COPY [[COPY1]]
51    ; CHECK-NEXT: RET_ReallyLR implicit $s0
52    %0:fpr(<2 x s32>) = COPY $d0
53    %2:gpr(s64) = G_CONSTANT i64 0
54    %3:fpr(s64) = COPY %2(s64)
55    %1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
56    $s0 = COPY %1(s32)
57    RET_ReallyLR implicit $s0
58
59...
60---
61name:            v2s64_fpr
62alignment:       4
63legalized:       true
64regBankSelected: true
65tracksRegLiveness: true
66registers:
67  - { id: 0, class: fpr }
68  - { id: 1, class: fpr }
69  - { id: 2, class: gpr }
70  - { id: 3, class: fpr }
71body:             |
72  bb.0:
73    liveins: $q0
74
75    ; CHECK-LABEL: name: v2s64_fpr
76    ; CHECK: liveins: $q0
77    ; CHECK-NEXT: {{  $}}
78    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
79    ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 2
80    ; CHECK-NEXT: $d0 = COPY [[DUPi64_]]
81    ; CHECK-NEXT: RET_ReallyLR implicit $d0
82    %0:fpr(<2 x s64>) = COPY $q0
83    %2:gpr(s64) = G_CONSTANT i64 2
84    %3:fpr(s64) = COPY %2(s64)
85    %1:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %3(s64)
86    $d0 = COPY %1(s64)
87    RET_ReallyLR implicit $d0
88
89...
90---
91name:            v4s16_fpr
92alignment:       4
93legalized:       true
94regBankSelected: true
95tracksRegLiveness: true
96registers:
97  - { id: 0, class: fpr }
98  - { id: 1, class: fpr }
99  - { id: 2, class: gpr }
100  - { id: 3, class: fpr }
101body:             |
102  bb.0:
103    liveins: $d0
104
105    ; CHECK-LABEL: name: v4s16_fpr
106    ; CHECK: liveins: $d0
107    ; CHECK-NEXT: {{  $}}
108    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
109    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
110    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
111    ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
112    ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
113    ; CHECK-NEXT: RET_ReallyLR implicit $h0
114    %0:fpr(<4 x s16>) = COPY $d0
115    %2:gpr(s64) = G_CONSTANT i64 1
116    %3:fpr(s64) = COPY %2(s64)
117    %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %3(s64)
118    $h0 = COPY %1(s16)
119    RET_ReallyLR implicit $h0
120
121...
122---
123name:            v8s16_fpr
124alignment:       4
125legalized:       true
126regBankSelected: true
127tracksRegLiveness: true
128body:             |
129  bb.0:
130    liveins: $q0
131    ; CHECK-LABEL: name: v8s16_fpr
132    ; CHECK: liveins: $q0
133    ; CHECK-NEXT: {{  $}}
134    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
135    ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
136    ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
137    ; CHECK-NEXT: RET_ReallyLR implicit $h0
138    %0:fpr(<8 x s16>) = COPY $q0
139    %2:gpr(s64) = G_CONSTANT i64 1
140    %3:fpr(s64) = COPY %2(s64)
141    %1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
142    $h0 = COPY %1(s16)
143    RET_ReallyLR implicit $h0
144
145...
146---
147name:            v8s16_fpr_zext
148alignment:       4
149legalized:       true
150regBankSelected: true
151tracksRegLiveness: true
152body:             |
153  bb.0:
154    liveins: $q0
155    ; CHECK-LABEL: name: v8s16_fpr_zext
156    ; CHECK: liveins: $q0
157    ; CHECK-NEXT: {{  $}}
158    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
159    ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
160    ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
161    ; CHECK-NEXT: RET_ReallyLR implicit $h0
162    %0:fpr(<8 x s16>) = COPY $q0
163    %1:gpr(s32) = G_CONSTANT i32 1
164    %2:gpr(s64) = G_ZEXT %1
165    %3:fpr(s64) = COPY %2(s64)
166    %4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
167    $h0 = COPY %4(s16)
168    RET_ReallyLR implicit $h0
169
170...
171---
172name:            v8s16_fpr_sext
173alignment:       4
174legalized:       true
175regBankSelected: true
176tracksRegLiveness: true
177body:             |
178  bb.0:
179    liveins: $q0
180    ; CHECK-LABEL: name: v8s16_fpr_sext
181    ; CHECK: liveins: $q0
182    ; CHECK-NEXT: {{  $}}
183    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
184    ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
185    ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
186    ; CHECK-NEXT: RET_ReallyLR implicit $h0
187    %0:fpr(<8 x s16>) = COPY $q0
188    %1:gpr(s32) = G_CONSTANT i32 1
189    %2:gpr(s64) = G_SEXT %1
190    %3:fpr(s64) = COPY %2(s64)
191    %4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
192    $h0 = COPY %4(s16)
193    RET_ReallyLR implicit $h0
194
195...
196---
197name:            v8s16_fpr_trunc
198alignment:       4
199legalized:       true
200regBankSelected: true
201tracksRegLiveness: true
202body:             |
203  bb.0:
204    liveins: $q0
205    ; CHECK-LABEL: name: v8s16_fpr_trunc
206    ; CHECK: liveins: $q0
207    ; CHECK-NEXT: {{  $}}
208    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
209    ; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
210    ; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
211    ; CHECK-NEXT: RET_ReallyLR implicit $h0
212    %0:fpr(<8 x s16>) = COPY $q0
213    %1:gpr(s64) = G_CONSTANT i64 1
214    %2:gpr(s32) = G_TRUNC %1
215    %3:gpr(s64) = G_SEXT %2
216    %4:fpr(s64) = COPY %3(s64)
217    %5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
218    $h0 = COPY %5(s16)
219    RET_ReallyLR implicit $h0
220...
221---
222name:            v16s8
223alignment:       4
224legalized:       true
225regBankSelected: true
226tracksRegLiveness: true
227liveins:
228  - { reg: '$q0' }
229body:             |
230  bb.1:
231    liveins: $q0
232
233    ; CHECK-LABEL: name: v16s8
234    ; CHECK: liveins: $q0
235    ; CHECK-NEXT: {{  $}}
236    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
237    ; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[COPY]], 0
238    ; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]
239    ; CHECK-NEXT: RET_ReallyLR implicit $w0
240    %0:fpr(<16 x s8>) = COPY $q0
241    %2:gpr(s64) = G_CONSTANT i64 0
242    %1:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %2(s64)
243    %4:gpr(s8) = COPY %1(s8)
244    %3:gpr(s32) = G_ANYEXT %4(s8)
245    $w0 = COPY %3(s32)
246    RET_ReallyLR implicit $w0
247
248...
249---
250name:            v8s8
251alignment:       4
252legalized:       true
253regBankSelected: true
254tracksRegLiveness: true
255liveins:
256  - { reg: '$q0' }
257body:             |
258  bb.1:
259    liveins: $d0
260
261    ; CHECK-LABEL: name: v8s8
262    ; CHECK: liveins: $d0
263    ; CHECK-NEXT: {{  $}}
264    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
265    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
266    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
267    ; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[INSERT_SUBREG]], 0
268    ; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]
269    ; CHECK-NEXT: RET_ReallyLR implicit $w0
270    %0:fpr(<8 x s8>) = COPY $d0
271    %2:gpr(s64) = G_CONSTANT i64 0
272    %1:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %2(s64)
273    %4:gpr(s8) = COPY %1(s8)
274    %3:gpr(s32) = G_ANYEXT %4(s8)
275    $w0 = COPY %3(s32)
276    RET_ReallyLR implicit $w0
277
278...
279---
280name:            v2p0
281alignment:       4
282legalized:       true
283regBankSelected: true
284tracksRegLiveness: true
285body:             |
286  bb.0:
287    liveins: $q0
288
289    ; CHECK-LABEL: name: v2p0
290    ; CHECK: liveins: $q0
291    ; CHECK-NEXT: {{  $}}
292    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
293    ; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 1
294    ; CHECK-NEXT: $d0 = COPY [[DUPi64_]]
295    ; CHECK-NEXT: RET_ReallyLR implicit $d0
296    %0:fpr(<2 x p0>) = COPY $q0
297    %2:gpr(s64) = G_CONSTANT i64 1
298    %1:fpr(p0) = G_EXTRACT_VECTOR_ELT %0(<2 x p0>), %2(s64)
299    $d0 = COPY %1(p0)
300    RET_ReallyLR implicit $d0
301
302...
303