1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s
3
4name:            test_v8s8
5alignment:       4
6legalized:       true
7regBankSelected: true
8tracksRegLiveness: true
9body:             |
10  bb.0:
11    liveins: $d0
12
13    ; CHECK-LABEL: name:            test_v8s8
14    ; CHECK: liveins: $d0
15    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
16    ; CHECK: [[CLZv8i8_:%[0-9]+]]:fpr64 = CLZv8i8 [[COPY]]
17    ; CHECK: $d0 = COPY [[CLZv8i8_]]
18    ; CHECK: RET_ReallyLR implicit $d0
19    %0:fpr(<8 x s8>) = COPY $d0
20    %1:fpr(<8 x s8>) = G_CTLZ %0(<8 x s8>)
21    $d0 = COPY %1(<8 x s8>)
22    RET_ReallyLR implicit $d0
23
24...
25---
26name:            test_v4s16
27alignment:       4
28legalized:       true
29regBankSelected: true
30tracksRegLiveness: true
31body:             |
32  bb.0:
33    liveins: $d0
34
35    ; CHECK-LABEL: name: test_v4s16
36    ; CHECK: liveins: $d0
37    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
38    ; CHECK: [[CLZv4i16_:%[0-9]+]]:fpr64 = CLZv4i16 [[COPY]]
39    ; CHECK: $d0 = COPY [[CLZv4i16_]]
40    ; CHECK: RET_ReallyLR implicit $d0
41    %0:fpr(<4 x s16>) = COPY $d0
42    %1:fpr(<4 x s16>) = G_CTLZ %0(<4 x s16>)
43    $d0 = COPY %1(<4 x s16>)
44    RET_ReallyLR implicit $d0
45
46...
47---
48name:            test_v2s32
49alignment:       4
50legalized:       true
51regBankSelected: true
52tracksRegLiveness: true
53body:             |
54  bb.0:
55    liveins: $d0
56
57    ; CHECK-LABEL: name: test_v2s32
58    ; CHECK: liveins: $d0
59    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
60    ; CHECK: [[CLZv2i32_:%[0-9]+]]:fpr64 = CLZv2i32 [[COPY]]
61    ; CHECK: $d0 = COPY [[CLZv2i32_]]
62    ; CHECK: RET_ReallyLR implicit $d0
63    %0:fpr(<2 x s32>) = COPY $d0
64    %1:fpr(<2 x s32>) = G_CTLZ %0(<2 x s32>)
65    $d0 = COPY %1(<2 x s32>)
66    RET_ReallyLR implicit $d0
67
68...
69---
70name:            test_s64
71alignment:       4
72legalized:       true
73regBankSelected: true
74tracksRegLiveness: true
75body:             |
76  bb.0:
77    liveins: $d0
78
79    ; CHECK-LABEL: name: test_s64
80    ; CHECK: liveins: $d0
81    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
82    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
83    ; CHECK: [[CLZXr:%[0-9]+]]:gpr64 = CLZXr [[COPY1]]
84    ; CHECK: $d0 = COPY [[CLZXr]]
85    ; CHECK: RET_ReallyLR implicit $d0
86    %0:fpr(s64) = COPY $d0
87    %2:gpr(s64) = COPY %0(s64)
88    %1:gpr(s64) = G_CTLZ %2(s64)
89    $d0 = COPY %1(s64)
90    RET_ReallyLR implicit $d0
91
92...
93---
94name:            test_s32
95alignment:       4
96legalized:       true
97regBankSelected: true
98tracksRegLiveness: true
99body:             |
100  bb.0:
101    liveins: $s0
102    ; CHECK-LABEL: name: test_s32
103    ; CHECK: liveins: $s0
104    ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
105    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
106    ; CHECK: [[CLZWr:%[0-9]+]]:gpr32 = CLZWr [[COPY1]]
107    ; CHECK: $s0 = COPY [[CLZWr]]
108    ; CHECK: RET_ReallyLR implicit $s0
109    %0:fpr(s32) = COPY $s0
110    %2:gpr(s32) = COPY %0(s32)
111    %1:gpr(s32) = G_CTLZ %2(s32)
112    $s0 = COPY %1(s32)
113    RET_ReallyLR implicit $s0
114
115...
116---
117name:            test_v16s8
118alignment:       4
119legalized:       true
120regBankSelected: true
121tracksRegLiveness: true
122body:             |
123  bb.0:
124    liveins: $q0
125
126    ; CHECK-LABEL: name: test_v16s8
127    ; CHECK: liveins: $q0
128    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
129    ; CHECK: [[CLZv16i8_:%[0-9]+]]:fpr128 = CLZv16i8 [[COPY]]
130    ; CHECK: $q0 = COPY [[CLZv16i8_]]
131    ; CHECK: RET_ReallyLR implicit $q0
132    %0:fpr(<16 x s8>) = COPY $q0
133    %1:fpr(<16 x s8>) = G_CTLZ %0(<16 x s8>)
134    $q0 = COPY %1(<16 x s8>)
135    RET_ReallyLR implicit $q0
136
137...
138---
139name:            test_v8s16
140alignment:       4
141legalized:       true
142regBankSelected: true
143tracksRegLiveness: true
144body:             |
145  bb.0:
146    liveins: $q0
147
148    ; CHECK-LABEL: name: test_v8s16
149    ; CHECK: liveins: $q0
150    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
151    ; CHECK: [[CLZv8i16_:%[0-9]+]]:fpr128 = CLZv8i16 [[COPY]]
152    ; CHECK: $q0 = COPY [[CLZv8i16_]]
153    ; CHECK: RET_ReallyLR implicit $q0
154    %0:fpr(<8 x s16>) = COPY $q0
155    %1:fpr(<8 x s16>) = G_CTLZ %0(<8 x s16>)
156    $q0 = COPY %1(<8 x s16>)
157    RET_ReallyLR implicit $q0
158
159...
160---
161name:            test_v4s32
162alignment:       4
163legalized:       true
164regBankSelected: true
165tracksRegLiveness: true
166body:             |
167  bb.0:
168    liveins: $q0
169
170    ; CHECK-LABEL: name: test_v4s32
171    ; CHECK: liveins: $q0
172    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
173    ; CHECK: [[CLZv4i32_:%[0-9]+]]:fpr128 = CLZv4i32 [[COPY]]
174    ; CHECK: $q0 = COPY [[CLZv4i32_]]
175    ; CHECK: RET_ReallyLR implicit $q0
176    %0:fpr(<4 x s32>) = COPY $q0
177    %1:fpr(<4 x s32>) = G_CTLZ %0(<4 x s32>)
178    $q0 = COPY %1(<4 x s32>)
179    RET_ReallyLR implicit $q0
180
181...
182