1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
3--- |
4  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
5  target triple = "aarch64"
6
7  define void @test_memmove1(i32* nocapture %dst, i32* nocapture readonly %src, i64 %len) local_unnamed_addr #0 {
8  entry:
9    %0 = bitcast i32* %dst to i8*
10    %1 = bitcast i32* %src to i8*
11    tail call void @llvm.memmove.p0i8.p0i8.i64(i8* align 4 %0, i8* align 4 %1, i64 %len, i1 false)
12    ret void
13  }
14
15  declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1 immarg) #1
16  declare void @llvm.memmove.p1i8.p2i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(2)* nocapture readonly, i64, i1 immarg) #1
17
18  define void @test_memmove2_const(i32* nocapture %dst, i32* nocapture readonly %src) local_unnamed_addr #0 {
19  entry:
20    %0 = bitcast i32* %dst to i8*
21    %1 = bitcast i32* %src to i8*
22    tail call void @llvm.memmove.p0i8.p0i8.i64(i8* align 4 %0, i8* align 4 %1, i64 48, i1 false)
23    ret void
24  }
25
26  define void @test_memmove3_const_toolarge(i32* nocapture %dst, i32* nocapture readonly %src) local_unnamed_addr #0 {
27  entry:
28    %0 = bitcast i32* %dst to i8*
29    %1 = bitcast i32* %src to i8*
30    tail call void @llvm.memmove.p0i8.p0i8.i64(i8* align 4 %0, i8* align 4 %1, i64 96, i1 false)
31    ret void
32  }
33
34  define void @test_memmove4_const_unaligned(i32* nocapture %dst, i32* nocapture readonly %src) local_unnamed_addr #0 {
35  entry:
36    %0 = bitcast i32* %dst to i8*
37    %1 = bitcast i32* %src to i8*
38    tail call void @llvm.memmove.p0i8.p0i8.i64(i8* align 4 %0, i8* align 4 %1, i64 52, i1 false)
39    ret void
40  }
41
42  define void @test_memmove_addrspace(i32 addrspace(1)* nocapture %dst, i32 addrspace(2)* nocapture readonly %src) local_unnamed_addr #0 {
43  entry:
44    %0 = bitcast i32 addrspace(1)* %dst to i8 addrspace(1)*
45    %1 = bitcast i32 addrspace(2)* %src to i8 addrspace(2)*
46    tail call void @llvm.memmove.p1i8.p2i8.i64(i8 addrspace(1)* align 4 %0, i8 addrspace(2)* align 4 %1, i64 8, i1 false)
47    ret void
48  }
49
50  attributes #0 = { nounwind ssp uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cyclone" "target-features"="+aes,+crypto,+fp-armv8,+neon,+sha2,+zcm,+zcz" "unsafe-fp-math"="false" "use-soft-float"="false" }
51  attributes #1 = { argmemonly nounwind }
52
53...
54---
55name:            test_memmove1
56alignment:       4
57tracksRegLiveness: true
58body:             |
59  bb.1.entry:
60    liveins: $x0, $x1, $x2
61
62    ; CHECK-LABEL: name: test_memmove1
63    ; CHECK: liveins: $x0, $x1, $x2
64    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
65    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
66    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
67    ; CHECK: G_MEMMOVE [[COPY]](p0), [[COPY1]](p0), [[COPY2]](s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
68    ; CHECK: RET_ReallyLR
69    %0:_(p0) = COPY $x0
70    %1:_(p0) = COPY $x1
71    %2:_(s64) = COPY $x2
72    G_MEMMOVE %0(p0), %1(p0), %2(s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
73    RET_ReallyLR
74
75...
76---
77name:            test_memmove2_const
78alignment:       4
79tracksRegLiveness: true
80body:             |
81  bb.1.entry:
82    liveins: $x0, $x1
83
84    ; CHECK-LABEL: name: test_memmove2_const
85    ; CHECK: liveins: $x0, $x1
86    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
87    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
88    ; CHECK: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
89    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
90    ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C]](s64)
91    ; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
92    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
93    ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64)
94    ; CHECK: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
95    ; CHECK: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
96    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
97    ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
98    ; CHECK: G_STORE [[LOAD1]](s128), [[PTR_ADD2]](p0) :: (store (s128) into %ir.0 + 16, align 4)
99    ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
100    ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
101    ; CHECK: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 32, align 4)
102    ; CHECK: RET_ReallyLR
103    %0:_(p0) = COPY $x0
104    %1:_(p0) = COPY $x1
105    %2:_(s64) = G_CONSTANT i64 48
106    G_MEMMOVE %0(p0), %1(p0), %2(s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
107    RET_ReallyLR
108
109...
110---
111name:            test_memmove3_const_toolarge
112alignment:       4
113tracksRegLiveness: true
114body:             |
115  bb.1.entry:
116    liveins: $x0, $x1
117
118    ; CHECK-LABEL: name: test_memmove3_const_toolarge
119    ; CHECK: liveins: $x0, $x1
120    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
121    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
122    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 96
123    ; CHECK: G_MEMMOVE [[COPY]](p0), [[COPY1]](p0), [[C]](s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
124    ; CHECK: RET_ReallyLR
125    %0:_(p0) = COPY $x0
126    %1:_(p0) = COPY $x1
127    %2:_(s64) = G_CONSTANT i64 96
128    G_MEMMOVE %0(p0), %1(p0), %2(s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
129    RET_ReallyLR
130
131...
132---
133name:            test_memmove4_const_unaligned
134alignment:       4
135tracksRegLiveness: true
136body:             |
137  bb.1.entry:
138    liveins: $x0, $x1
139
140    ; CHECK-LABEL: name: test_memmove4_const_unaligned
141    ; CHECK: liveins: $x0, $x1
142    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
143    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
144    ; CHECK: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p0) :: (load (s128) from %ir.1, align 4)
145    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
146    ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C]](s64)
147    ; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p0) :: (load (s128) from %ir.1 + 16, align 4)
148    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
149    ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64)
150    ; CHECK: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD1]](p0) :: (load (s128) from %ir.1 + 32, align 4)
151    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
152    ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s64)
153    ; CHECK: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s32) from %ir.1 + 48)
154    ; CHECK: G_STORE [[LOAD]](s128), [[COPY]](p0) :: (store (s128) into %ir.0, align 4)
155    ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
156    ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
157    ; CHECK: G_STORE [[LOAD1]](s128), [[PTR_ADD3]](p0) :: (store (s128) into %ir.0 + 16, align 4)
158    ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
159    ; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)
160    ; CHECK: G_STORE [[LOAD2]](s128), [[PTR_ADD4]](p0) :: (store (s128) into %ir.0 + 32, align 4)
161    ; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
162    ; CHECK: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64)
163    ; CHECK: G_STORE [[LOAD3]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %ir.0 + 48)
164    ; CHECK: RET_ReallyLR
165    %0:_(p0) = COPY $x0
166    %1:_(p0) = COPY $x1
167    %2:_(s64) = G_CONSTANT i64 52
168    G_MEMMOVE %0(p0), %1(p0), %2(s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
169    RET_ReallyLR
170
171...
172---
173name:            test_memmove_addrspace
174alignment:       4
175tracksRegLiveness: true
176body:             |
177  bb.1.entry:
178    liveins: $x0, $x1
179
180    ; CHECK-LABEL: name: test_memmove_addrspace
181    ; CHECK: liveins: $x0, $x1
182    ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $x0
183    ; CHECK: [[COPY1:%[0-9]+]]:_(p2) = COPY $x1
184    ; CHECK: [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY1]](p2) :: (load (s128) from %ir.1, align 4, addrspace 2)
185    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
186    ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p2) = G_PTR_ADD [[COPY1]], [[C]](s64)
187    ; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD]](p2) :: (load (s128) from %ir.1 + 16, align 4, addrspace 2)
188    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
189    ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p2) = G_PTR_ADD [[COPY1]], [[C1]](s64)
190    ; CHECK: [[LOAD2:%[0-9]+]]:_(s128) = G_LOAD [[PTR_ADD1]](p2) :: (load (s128) from %ir.1 + 32, align 4, addrspace 2)
191    ; CHECK: G_STORE [[LOAD]](s128), [[COPY]](p1) :: (store (s128) into %ir.0, align 4, addrspace 1)
192    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
193    ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
194    ; CHECK: G_STORE [[LOAD1]](s128), [[PTR_ADD2]](p1) :: (store (s128) into %ir.0 + 16, align 4, addrspace 1)
195    ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
196    ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
197    ; CHECK: G_STORE [[LOAD2]](s128), [[PTR_ADD3]](p1) :: (store (s128) into %ir.0 + 32, align 4, addrspace 1)
198    ; CHECK: RET_ReallyLR
199    %0:_(p1) = COPY $x0
200    %1:_(p2) = COPY $x1
201    %2:_(s64) = G_CONSTANT i64 48
202    G_MEMMOVE %0(p1), %1(p2), %2(s64), 1 :: (store (s8) into %ir.0, align 4), (load (s8) from %ir.1, align 4)
203    RET_ReallyLR
204
205
206...
207