1; RUN: llc -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err
2; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out
3; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err
4; RUN: not --crash llc -global-isel -mtriple aarch64_be %s -o - 2>&1 | FileCheck %s --check-prefix=BIG-ENDIAN
5; This file checks that the fallback path to selection dag works.
6; The test is fragile in the sense that it must be updated to expose
7; something that fails with global-isel.
8; When we cannot produce a test case anymore, that means we can remove
9; the fallback path.
10
11target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
12target triple = "aarch64--"
13
14; BIG-ENDIAN: unable to translate in big endian mode
15
16; Make sure we don't mess up metadata arguments.
17declare void @llvm.write_register.i64(metadata, i64)
18
19; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_WRITE_REGISTER !0, %0:_(s64) (in function: test_write_register_intrin)
20; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_write_register_intrin
21; FALLBACK-WITH-REPORT-LABEL: test_write_register_intrin:
22define void @test_write_register_intrin() {
23  call void @llvm.write_register.i64(metadata !{!"sp"}, i64 0)
24  ret void
25}
26
27@_ZTIi = external global i8*
28declare i32 @__gxx_personality_v0(...)
29
30; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(<2 x p0>) = G_INSERT_VECTOR_ELT %0:_, %{{[0-9]+}}:_(p0), %{{[0-9]+}}:_(s32) (in function: vector_of_pointers_insertelement)
31; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement
32; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement:
33define void @vector_of_pointers_insertelement() {
34  br label %end
35
36block:
37  %dummy = insertelement <2 x i16*> %vec, i16* null, i32 0
38  store <2 x i16*> %dummy, <2 x i16*>* undef
39  ret void
40
41end:
42  %vec = load <2 x i16*>, <2 x i16*>* undef
43  br label %block
44}
45
46; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: RET_ReallyLR implicit $x0 (in function: strict_align_feature)
47; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for strict_align_feature
48; FALLBACK-WITH-REPORT-OUT-LABEL: strict_align_feature
49define i64 @strict_align_feature(i64* %p) #0 {
50  %x = load i64, i64* %p, align 1
51  ret i64 %x
52}
53
54attributes #0 = { "target-features"="+strict-align" }
55
56; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: call
57; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for direct_mem
58; FALLBACK-WITH-REPORT-OUT-LABEL: direct_mem
59define void @direct_mem(i32 %x, i32 %y) {
60entry:
61  tail call void asm sideeffect "", "imr,imr,~{memory}"(i32 %x, i32 %y)
62  ret void
63}
64
65; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to lower function{{.*}}scalable_arg
66; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_arg
67define <vscale x 16 x i8> @scalable_arg(<vscale x 16 x i1> %pred, i8* %addr) #1 {
68  %res = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pred, i8* %addr)
69  ret <vscale x 16 x i8> %res
70}
71
72; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to lower function{{.*}}scalable_ret
73; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_ret
74define <vscale x 16 x i8> @scalable_ret(i8* %addr) #1 {
75  %pred = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
76  %res = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pred, i8* %addr)
77  ret <vscale x 16 x i8> %res
78}
79
80; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction{{.*}}scalable_call
81; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_call
82define i8 @scalable_call(i8* %addr) #1 {
83  %pred = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 0)
84  %vec = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pred, i8* %addr)
85  %res = extractelement <vscale x 16 x i8> %vec, i32 0
86  ret i8 %res
87}
88
89; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction{{.*}}scalable_alloca
90; FALLBACK-WITH-REPORT-OUT-LABEL: scalable_alloca
91define void @scalable_alloca() #1 {
92  %local0 = alloca <vscale x 16 x i8>
93  load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local0
94  ret void
95}
96
97; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction{{.*}}asm_indirect_output
98; FALLBACK-WITH-REPORT-OUT-LABEL: asm_indirect_output
99define void @asm_indirect_output() {
100entry:
101  %ap = alloca i8*, align 8
102  %0 = load i8*, i8** %ap, align 8
103  call void asm sideeffect "", "=*r|m,0,~{memory}"(i8** elementtype(i8*) %ap, i8* %0)
104  ret void
105}
106
107%struct.foo = type { [8 x i64] }
108
109; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction:{{.*}}ld64b{{.*}}asm_output_ls64
110; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for asm_output_ls64
111; FALLBACK-WITH-REPORT-OUT-LABEL: asm_output_ls64
112define void @asm_output_ls64(%struct.foo* %output, i8* %addr) #2 {
113entry:
114  %val = call i512 asm sideeffect "ld64b $0,[$1]", "=r,r,~{memory}"(i8* %addr)
115  %outcast = bitcast %struct.foo* %output to i512*
116  store i512 %val, i512* %outcast, align 8
117  ret void
118}
119
120; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction:{{.*}}st64b{{.*}}asm_input_ls64
121; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for asm_input_ls64
122; FALLBACK-WITH-REPORT-OUT-LABEL: asm_input_ls64
123define void @asm_input_ls64(%struct.foo* %input, i8* %addr) #2 {
124entry:
125  %incast = bitcast %struct.foo* %input to i512*
126  %val = load i512, i512* %incast, align 8
127  call void asm sideeffect "st64b $0,[$1]", "r,r,~{memory}"(i512 %val, i8* %addr)
128  ret void
129}
130
131; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %4:_(s128), %5:_(s1) = G_UMULO %0:_, %6:_ (in function: umul_s128)
132; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for umul_s128
133; FALLBACK-WITH-REPORT-OUT-LABEL: umul_s128
134declare {i128, i1} @llvm.umul.with.overflow.i128(i128, i128) nounwind readnone
135define zeroext i1 @umul_s128(i128 %v1, i128* %res) {
136entry:
137  %t = call {i128, i1} @llvm.umul.with.overflow.i128(i128 %v1, i128 2)
138  %val = extractvalue {i128, i1} %t, 0
139  %obit = extractvalue {i128, i1} %t, 1
140  store i128 %val, i128* %res
141  ret i1 %obit
142}
143
144attributes #1 = { "target-features"="+sve" }
145attributes #2 = { "target-features"="+ls64" }
146
147declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 %pattern)
148declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1>, i8*)
149