1; RUN: opt %s -passes='print<divergence>' -disable-output 2>&1 | FileCheck %s
2
3target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
4target triple = "nvptx64-nvidia-cuda"
5
6define i32 @daorder(i32 %n) {
7; CHECK-LABEL: Divergence Analysis' for function 'daorder'
8entry:
9  %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
10  %cond = icmp slt i32 %tid, 0
11  br i1 %cond, label %A, label %B ; divergent
12; CHECK: DIVERGENT: br i1 %cond,
13A:
14  %defAtA = add i32 %n, 1 ; uniform
15; CHECK-NOT: DIVERGENT: %defAtA =
16  br label %C
17B:
18  %defAtB = add i32 %n, 2 ; uniform
19; CHECK-NOT: DIVERGENT: %defAtB =
20  br label %C
21C:
22  %defAtC = phi i32 [ %defAtA, %A ], [ %defAtB, %B ] ; divergent
23; CHECK: DIVERGENT: %defAtC =
24  br label %D
25
26D:
27  %i = phi i32 [0, %C], [ %i.inc, %E ] ; uniform
28; CHECK-NOT: DIVERGENT: %i = phi
29  br label %E
30
31E:
32  %i.inc = add i32 %i, 1
33  %loopCnt = icmp slt i32 %i.inc, %n
34; CHECK-NOT: DIVERGENT: %loopCnt =
35  br i1 %loopCnt, label %D, label %exit
36
37exit:
38  ret i32 %n
39}
40
41declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
42declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
43declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
44declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
45
46!nvvm.annotations = !{!0}
47!0 = !{i32 (i32)* @daorder, !"kernel", i32 1}
48