1*f1f57a31SAmjad Aboud //===- TruncInstCombine.cpp -----------------------------------------------===//
2*f1f57a31SAmjad Aboud //
3*f1f57a31SAmjad Aboud //                     The LLVM Compiler Infrastructure
4*f1f57a31SAmjad Aboud //
5*f1f57a31SAmjad Aboud // This file is distributed under the University of Illinois Open Source
6*f1f57a31SAmjad Aboud // License. See LICENSE.TXT for details.
7*f1f57a31SAmjad Aboud //
8*f1f57a31SAmjad Aboud //===----------------------------------------------------------------------===//
9*f1f57a31SAmjad Aboud //
10*f1f57a31SAmjad Aboud // TruncInstCombine - looks for expression dags post-dominated by TruncInst and
11*f1f57a31SAmjad Aboud // for each eligible dag, it will create a reduced bit-width expression, replace
12*f1f57a31SAmjad Aboud // the old expression with this new one and remove the old expression.
13*f1f57a31SAmjad Aboud // Eligible expression dag is such that:
14*f1f57a31SAmjad Aboud //   1. Contains only supported instructions.
15*f1f57a31SAmjad Aboud //   2. Supported leaves: ZExtInst, SExtInst, TruncInst and Constant value.
16*f1f57a31SAmjad Aboud //   3. Can be evaluated into type with reduced legal bit-width.
17*f1f57a31SAmjad Aboud //   4. All instructions in the dag must not have users outside the dag.
18*f1f57a31SAmjad Aboud //      The only exception is for {ZExt, SExt}Inst with operand type equal to
19*f1f57a31SAmjad Aboud //      the new reduced type evaluated in (3).
20*f1f57a31SAmjad Aboud //
21*f1f57a31SAmjad Aboud // The motivation for this optimization is that evaluating and expression using
22*f1f57a31SAmjad Aboud // smaller bit-width is preferable, especially for vectorization where we can
23*f1f57a31SAmjad Aboud // fit more values in one vectorized instruction. In addition, this optimization
24*f1f57a31SAmjad Aboud // may decrease the number of cast instructions, but will not increase it.
25*f1f57a31SAmjad Aboud //
26*f1f57a31SAmjad Aboud //===----------------------------------------------------------------------===//
27*f1f57a31SAmjad Aboud 
28*f1f57a31SAmjad Aboud #include "AggressiveInstCombineInternal.h"
29*f1f57a31SAmjad Aboud #include "llvm/ADT/MapVector.h"
30*f1f57a31SAmjad Aboud #include "llvm/ADT/STLExtras.h"
31*f1f57a31SAmjad Aboud #include "llvm/Analysis/ConstantFolding.h"
32*f1f57a31SAmjad Aboud #include "llvm/Analysis/TargetLibraryInfo.h"
33*f1f57a31SAmjad Aboud #include "llvm/IR/DataLayout.h"
34*f1f57a31SAmjad Aboud #include "llvm/IR/IRBuilder.h"
35*f1f57a31SAmjad Aboud using namespace llvm;
36*f1f57a31SAmjad Aboud 
37*f1f57a31SAmjad Aboud #define DEBUG_TYPE "aggressive-instcombine"
38*f1f57a31SAmjad Aboud 
39*f1f57a31SAmjad Aboud /// Given an instruction and a container, it fills all the relevant operands of
40*f1f57a31SAmjad Aboud /// that instruction, with respect to the Trunc expression dag optimizaton.
41*f1f57a31SAmjad Aboud static void getRelevantOperands(Instruction *I, SmallVectorImpl<Value *> &Ops) {
42*f1f57a31SAmjad Aboud   unsigned Opc = I->getOpcode();
43*f1f57a31SAmjad Aboud   switch (Opc) {
44*f1f57a31SAmjad Aboud   case Instruction::Trunc:
45*f1f57a31SAmjad Aboud   case Instruction::ZExt:
46*f1f57a31SAmjad Aboud   case Instruction::SExt:
47*f1f57a31SAmjad Aboud     // These CastInst are considered leaves of the evaluated expression, thus,
48*f1f57a31SAmjad Aboud     // their operands are not relevent.
49*f1f57a31SAmjad Aboud     break;
50*f1f57a31SAmjad Aboud   case Instruction::Add:
51*f1f57a31SAmjad Aboud   case Instruction::Sub:
52*f1f57a31SAmjad Aboud   case Instruction::Mul:
53*f1f57a31SAmjad Aboud   case Instruction::And:
54*f1f57a31SAmjad Aboud   case Instruction::Or:
55*f1f57a31SAmjad Aboud   case Instruction::Xor:
56*f1f57a31SAmjad Aboud     Ops.push_back(I->getOperand(0));
57*f1f57a31SAmjad Aboud     Ops.push_back(I->getOperand(1));
58*f1f57a31SAmjad Aboud     break;
59*f1f57a31SAmjad Aboud   default:
60*f1f57a31SAmjad Aboud     llvm_unreachable("Unreachable!");
61*f1f57a31SAmjad Aboud   }
62*f1f57a31SAmjad Aboud }
63*f1f57a31SAmjad Aboud 
64*f1f57a31SAmjad Aboud bool TruncInstCombine::buildTruncExpressionDag() {
65*f1f57a31SAmjad Aboud   SmallVector<Value *, 8> Worklist;
66*f1f57a31SAmjad Aboud   SmallVector<Instruction *, 8> Stack;
67*f1f57a31SAmjad Aboud   // Clear old expression dag.
68*f1f57a31SAmjad Aboud   InstInfoMap.clear();
69*f1f57a31SAmjad Aboud 
70*f1f57a31SAmjad Aboud   Worklist.push_back(CurrentTruncInst->getOperand(0));
71*f1f57a31SAmjad Aboud 
72*f1f57a31SAmjad Aboud   while (!Worklist.empty()) {
73*f1f57a31SAmjad Aboud     Value *Curr = Worklist.back();
74*f1f57a31SAmjad Aboud 
75*f1f57a31SAmjad Aboud     if (isa<Constant>(Curr)) {
76*f1f57a31SAmjad Aboud       Worklist.pop_back();
77*f1f57a31SAmjad Aboud       continue;
78*f1f57a31SAmjad Aboud     }
79*f1f57a31SAmjad Aboud 
80*f1f57a31SAmjad Aboud     auto *I = dyn_cast<Instruction>(Curr);
81*f1f57a31SAmjad Aboud     if (!I)
82*f1f57a31SAmjad Aboud       return false;
83*f1f57a31SAmjad Aboud 
84*f1f57a31SAmjad Aboud     if (!Stack.empty() && Stack.back() == I) {
85*f1f57a31SAmjad Aboud       // Already handled all instruction operands, can remove it from both the
86*f1f57a31SAmjad Aboud       // Worklist and the Stack, and add it to the instruction info map.
87*f1f57a31SAmjad Aboud       Worklist.pop_back();
88*f1f57a31SAmjad Aboud       Stack.pop_back();
89*f1f57a31SAmjad Aboud       // Insert I to the Info map.
90*f1f57a31SAmjad Aboud       InstInfoMap.insert(std::make_pair(I, Info()));
91*f1f57a31SAmjad Aboud       continue;
92*f1f57a31SAmjad Aboud     }
93*f1f57a31SAmjad Aboud 
94*f1f57a31SAmjad Aboud     if (InstInfoMap.count(I)) {
95*f1f57a31SAmjad Aboud       Worklist.pop_back();
96*f1f57a31SAmjad Aboud       continue;
97*f1f57a31SAmjad Aboud     }
98*f1f57a31SAmjad Aboud 
99*f1f57a31SAmjad Aboud     // Add the instruction to the stack before start handling its operands.
100*f1f57a31SAmjad Aboud     Stack.push_back(I);
101*f1f57a31SAmjad Aboud 
102*f1f57a31SAmjad Aboud     unsigned Opc = I->getOpcode();
103*f1f57a31SAmjad Aboud     switch (Opc) {
104*f1f57a31SAmjad Aboud     case Instruction::Trunc:
105*f1f57a31SAmjad Aboud     case Instruction::ZExt:
106*f1f57a31SAmjad Aboud     case Instruction::SExt:
107*f1f57a31SAmjad Aboud       // trunc(trunc(x)) -> trunc(x)
108*f1f57a31SAmjad Aboud       // trunc(ext(x)) -> ext(x) if the source type is smaller than the new dest
109*f1f57a31SAmjad Aboud       // trunc(ext(x)) -> trunc(x) if the source type is larger than the new
110*f1f57a31SAmjad Aboud       // dest
111*f1f57a31SAmjad Aboud       break;
112*f1f57a31SAmjad Aboud     case Instruction::Add:
113*f1f57a31SAmjad Aboud     case Instruction::Sub:
114*f1f57a31SAmjad Aboud     case Instruction::Mul:
115*f1f57a31SAmjad Aboud     case Instruction::And:
116*f1f57a31SAmjad Aboud     case Instruction::Or:
117*f1f57a31SAmjad Aboud     case Instruction::Xor: {
118*f1f57a31SAmjad Aboud       SmallVector<Value *, 2> Operands;
119*f1f57a31SAmjad Aboud       getRelevantOperands(I, Operands);
120*f1f57a31SAmjad Aboud       for (Value *Operand : Operands)
121*f1f57a31SAmjad Aboud         Worklist.push_back(Operand);
122*f1f57a31SAmjad Aboud       break;
123*f1f57a31SAmjad Aboud     }
124*f1f57a31SAmjad Aboud     default:
125*f1f57a31SAmjad Aboud       // TODO: Can handle more cases here:
126*f1f57a31SAmjad Aboud       // 1. select, shufflevector, extractelement, insertelement
127*f1f57a31SAmjad Aboud       // 2. udiv, urem
128*f1f57a31SAmjad Aboud       // 3. shl, lshr, ashr
129*f1f57a31SAmjad Aboud       // 4. phi node(and loop handling)
130*f1f57a31SAmjad Aboud       // ...
131*f1f57a31SAmjad Aboud       return false;
132*f1f57a31SAmjad Aboud     }
133*f1f57a31SAmjad Aboud   }
134*f1f57a31SAmjad Aboud   return true;
135*f1f57a31SAmjad Aboud }
136*f1f57a31SAmjad Aboud 
137*f1f57a31SAmjad Aboud unsigned TruncInstCombine::getMinBitWidth() {
138*f1f57a31SAmjad Aboud   SmallVector<Value *, 8> Worklist;
139*f1f57a31SAmjad Aboud   SmallVector<Instruction *, 8> Stack;
140*f1f57a31SAmjad Aboud 
141*f1f57a31SAmjad Aboud   Value *Src = CurrentTruncInst->getOperand(0);
142*f1f57a31SAmjad Aboud   Type *DstTy = CurrentTruncInst->getType();
143*f1f57a31SAmjad Aboud   unsigned TruncBitWidth = DstTy->getScalarSizeInBits();
144*f1f57a31SAmjad Aboud   unsigned OrigBitWidth =
145*f1f57a31SAmjad Aboud       CurrentTruncInst->getOperand(0)->getType()->getScalarSizeInBits();
146*f1f57a31SAmjad Aboud 
147*f1f57a31SAmjad Aboud   if (isa<Constant>(Src))
148*f1f57a31SAmjad Aboud     return TruncBitWidth;
149*f1f57a31SAmjad Aboud 
150*f1f57a31SAmjad Aboud   Worklist.push_back(Src);
151*f1f57a31SAmjad Aboud   InstInfoMap[cast<Instruction>(Src)].ValidBitWidth = TruncBitWidth;
152*f1f57a31SAmjad Aboud 
153*f1f57a31SAmjad Aboud   while (!Worklist.empty()) {
154*f1f57a31SAmjad Aboud     Value *Curr = Worklist.back();
155*f1f57a31SAmjad Aboud 
156*f1f57a31SAmjad Aboud     if (isa<Constant>(Curr)) {
157*f1f57a31SAmjad Aboud       Worklist.pop_back();
158*f1f57a31SAmjad Aboud       continue;
159*f1f57a31SAmjad Aboud     }
160*f1f57a31SAmjad Aboud 
161*f1f57a31SAmjad Aboud     // Otherwise, it must be an instruction.
162*f1f57a31SAmjad Aboud     auto *I = cast<Instruction>(Curr);
163*f1f57a31SAmjad Aboud 
164*f1f57a31SAmjad Aboud     auto &Info = InstInfoMap[I];
165*f1f57a31SAmjad Aboud 
166*f1f57a31SAmjad Aboud     SmallVector<Value *, 2> Operands;
167*f1f57a31SAmjad Aboud     getRelevantOperands(I, Operands);
168*f1f57a31SAmjad Aboud 
169*f1f57a31SAmjad Aboud     if (!Stack.empty() && Stack.back() == I) {
170*f1f57a31SAmjad Aboud       // Already handled all instruction operands, can remove it from both, the
171*f1f57a31SAmjad Aboud       // Worklist and the Stack, and update MinBitWidth.
172*f1f57a31SAmjad Aboud       Worklist.pop_back();
173*f1f57a31SAmjad Aboud       Stack.pop_back();
174*f1f57a31SAmjad Aboud       for (auto *Operand : Operands)
175*f1f57a31SAmjad Aboud         if (auto *IOp = dyn_cast<Instruction>(Operand))
176*f1f57a31SAmjad Aboud           Info.MinBitWidth =
177*f1f57a31SAmjad Aboud               std::max(Info.MinBitWidth, InstInfoMap[IOp].MinBitWidth);
178*f1f57a31SAmjad Aboud       continue;
179*f1f57a31SAmjad Aboud     }
180*f1f57a31SAmjad Aboud 
181*f1f57a31SAmjad Aboud     // Add the instruction to the stack before start handling its operands.
182*f1f57a31SAmjad Aboud     Stack.push_back(I);
183*f1f57a31SAmjad Aboud     unsigned ValidBitWidth = Info.ValidBitWidth;
184*f1f57a31SAmjad Aboud 
185*f1f57a31SAmjad Aboud     // Update minimum bit-width before handling its operands. This is required
186*f1f57a31SAmjad Aboud     // when the instruction is part of a loop.
187*f1f57a31SAmjad Aboud     Info.MinBitWidth = std::max(Info.MinBitWidth, Info.ValidBitWidth);
188*f1f57a31SAmjad Aboud 
189*f1f57a31SAmjad Aboud     for (auto *Operand : Operands)
190*f1f57a31SAmjad Aboud       if (auto *IOp = dyn_cast<Instruction>(Operand)) {
191*f1f57a31SAmjad Aboud         // If we already calculated the minimum bit-width for this valid
192*f1f57a31SAmjad Aboud         // bit-width, or for a smaller valid bit-width, then just keep the
193*f1f57a31SAmjad Aboud         // answer we already calculated.
194*f1f57a31SAmjad Aboud         unsigned IOpBitwidth = InstInfoMap.lookup(IOp).ValidBitWidth;
195*f1f57a31SAmjad Aboud         if (IOpBitwidth >= ValidBitWidth)
196*f1f57a31SAmjad Aboud           continue;
197*f1f57a31SAmjad Aboud         InstInfoMap[IOp].ValidBitWidth = std::max(ValidBitWidth, IOpBitwidth);
198*f1f57a31SAmjad Aboud         Worklist.push_back(IOp);
199*f1f57a31SAmjad Aboud       }
200*f1f57a31SAmjad Aboud   }
201*f1f57a31SAmjad Aboud   unsigned MinBitWidth = InstInfoMap.lookup(cast<Instruction>(Src)).MinBitWidth;
202*f1f57a31SAmjad Aboud   assert(MinBitWidth >= TruncBitWidth);
203*f1f57a31SAmjad Aboud 
204*f1f57a31SAmjad Aboud   if (MinBitWidth > TruncBitWidth) {
205*f1f57a31SAmjad Aboud     // In this case reducing expression with vector type might generate a new
206*f1f57a31SAmjad Aboud     // vector type, which is not preferable as it might result in generating
207*f1f57a31SAmjad Aboud     // sub-optimal code.
208*f1f57a31SAmjad Aboud     if (DstTy->isVectorTy())
209*f1f57a31SAmjad Aboud       return OrigBitWidth;
210*f1f57a31SAmjad Aboud     // Use the smallest integer type in the range [MinBitWidth, OrigBitWidth).
211*f1f57a31SAmjad Aboud     Type *Ty = DL.getSmallestLegalIntType(DstTy->getContext(), MinBitWidth);
212*f1f57a31SAmjad Aboud     // Update minimum bit-width with the new destination type bit-width if
213*f1f57a31SAmjad Aboud     // succeeded to find such, otherwise, with original bit-width.
214*f1f57a31SAmjad Aboud     MinBitWidth = Ty ? Ty->getScalarSizeInBits() : OrigBitWidth;
215*f1f57a31SAmjad Aboud   } else { // MinBitWidth == TruncBitWidth
216*f1f57a31SAmjad Aboud     // In this case the expression can be evaluated with the trunc instruction
217*f1f57a31SAmjad Aboud     // destination type, and trunc instruction can be omitted. However, we
218*f1f57a31SAmjad Aboud     // should not perform the evaluation if the original type is a legal scalar
219*f1f57a31SAmjad Aboud     // type and the target type is illegal.
220*f1f57a31SAmjad Aboud     bool FromLegal = MinBitWidth == 1 || DL.isLegalInteger(OrigBitWidth);
221*f1f57a31SAmjad Aboud     bool ToLegal = MinBitWidth == 1 || DL.isLegalInteger(MinBitWidth);
222*f1f57a31SAmjad Aboud     if (!DstTy->isVectorTy() && FromLegal && !ToLegal)
223*f1f57a31SAmjad Aboud       return OrigBitWidth;
224*f1f57a31SAmjad Aboud   }
225*f1f57a31SAmjad Aboud   return MinBitWidth;
226*f1f57a31SAmjad Aboud }
227*f1f57a31SAmjad Aboud 
228*f1f57a31SAmjad Aboud Type *TruncInstCombine::getBestTruncatedType() {
229*f1f57a31SAmjad Aboud   if (!buildTruncExpressionDag())
230*f1f57a31SAmjad Aboud     return nullptr;
231*f1f57a31SAmjad Aboud 
232*f1f57a31SAmjad Aboud   // We don't want to duplicate instructions, which isn't profitable. Thus, we
233*f1f57a31SAmjad Aboud   // can't shrink something that has multiple users, unless all users are
234*f1f57a31SAmjad Aboud   // post-dominated by the trunc instruction, i.e., were visited during the
235*f1f57a31SAmjad Aboud   // expression evaluation.
236*f1f57a31SAmjad Aboud   unsigned DesiredBitWidth = 0;
237*f1f57a31SAmjad Aboud   for (auto Itr : InstInfoMap) {
238*f1f57a31SAmjad Aboud     Instruction *I = Itr.first;
239*f1f57a31SAmjad Aboud     if (I->hasOneUse())
240*f1f57a31SAmjad Aboud       continue;
241*f1f57a31SAmjad Aboud     bool IsExtInst = (isa<ZExtInst>(I) || isa<SExtInst>(I));
242*f1f57a31SAmjad Aboud     for (auto *U : I->users())
243*f1f57a31SAmjad Aboud       if (auto *UI = dyn_cast<Instruction>(U))
244*f1f57a31SAmjad Aboud         if (UI != CurrentTruncInst && !InstInfoMap.count(UI)) {
245*f1f57a31SAmjad Aboud           if (!IsExtInst)
246*f1f57a31SAmjad Aboud             return nullptr;
247*f1f57a31SAmjad Aboud           // If this is an extension from the dest type, we can eliminate it,
248*f1f57a31SAmjad Aboud           // even if it has multiple users. Thus, update the DesiredBitWidth and
249*f1f57a31SAmjad Aboud           // validate all extension instructions agrees on same DesiredBitWidth.
250*f1f57a31SAmjad Aboud           unsigned ExtInstBitWidth =
251*f1f57a31SAmjad Aboud               I->getOperand(0)->getType()->getScalarSizeInBits();
252*f1f57a31SAmjad Aboud           if (DesiredBitWidth && DesiredBitWidth != ExtInstBitWidth)
253*f1f57a31SAmjad Aboud             return nullptr;
254*f1f57a31SAmjad Aboud           DesiredBitWidth = ExtInstBitWidth;
255*f1f57a31SAmjad Aboud         }
256*f1f57a31SAmjad Aboud   }
257*f1f57a31SAmjad Aboud 
258*f1f57a31SAmjad Aboud   unsigned OrigBitWidth =
259*f1f57a31SAmjad Aboud       CurrentTruncInst->getOperand(0)->getType()->getScalarSizeInBits();
260*f1f57a31SAmjad Aboud 
261*f1f57a31SAmjad Aboud   // Calculate minimum allowed bit-width allowed for shrinking the currently
262*f1f57a31SAmjad Aboud   // visited truncate's operand.
263*f1f57a31SAmjad Aboud   unsigned MinBitWidth = getMinBitWidth();
264*f1f57a31SAmjad Aboud 
265*f1f57a31SAmjad Aboud   // Check that we can shrink to smaller bit-width than original one and that
266*f1f57a31SAmjad Aboud   // it is similar to the DesiredBitWidth is such exists.
267*f1f57a31SAmjad Aboud   if (MinBitWidth >= OrigBitWidth ||
268*f1f57a31SAmjad Aboud       (DesiredBitWidth && DesiredBitWidth != MinBitWidth))
269*f1f57a31SAmjad Aboud     return nullptr;
270*f1f57a31SAmjad Aboud 
271*f1f57a31SAmjad Aboud   return IntegerType::get(CurrentTruncInst->getContext(), MinBitWidth);
272*f1f57a31SAmjad Aboud }
273*f1f57a31SAmjad Aboud 
274*f1f57a31SAmjad Aboud /// Given a reduced scalar type \p Ty and a \p V value, return a reduced type
275*f1f57a31SAmjad Aboud /// for \p V, according to its type, if it vector type, return the vector
276*f1f57a31SAmjad Aboud /// version of \p Ty, otherwise return \p Ty.
277*f1f57a31SAmjad Aboud static Type *getReducedType(Value *V, Type *Ty) {
278*f1f57a31SAmjad Aboud   assert(Ty && !Ty->isVectorTy() && "Expect Scalar Type");
279*f1f57a31SAmjad Aboud   if (auto *VTy = dyn_cast<VectorType>(V->getType()))
280*f1f57a31SAmjad Aboud     return VectorType::get(Ty, VTy->getNumElements());
281*f1f57a31SAmjad Aboud   return Ty;
282*f1f57a31SAmjad Aboud }
283*f1f57a31SAmjad Aboud 
284*f1f57a31SAmjad Aboud Value *TruncInstCombine::getReducedOperand(Value *V, Type *SclTy) {
285*f1f57a31SAmjad Aboud   Type *Ty = getReducedType(V, SclTy);
286*f1f57a31SAmjad Aboud   if (auto *C = dyn_cast<Constant>(V)) {
287*f1f57a31SAmjad Aboud     C = ConstantExpr::getIntegerCast(C, Ty, false);
288*f1f57a31SAmjad Aboud     // If we got a constantexpr back, try to simplify it with DL info.
289*f1f57a31SAmjad Aboud     if (Constant *FoldedC = ConstantFoldConstant(C, DL, &TLI))
290*f1f57a31SAmjad Aboud       C = FoldedC;
291*f1f57a31SAmjad Aboud     return C;
292*f1f57a31SAmjad Aboud   }
293*f1f57a31SAmjad Aboud 
294*f1f57a31SAmjad Aboud   auto *I = cast<Instruction>(V);
295*f1f57a31SAmjad Aboud   Info Entry = InstInfoMap.lookup(I);
296*f1f57a31SAmjad Aboud   assert(Entry.NewValue);
297*f1f57a31SAmjad Aboud   return Entry.NewValue;
298*f1f57a31SAmjad Aboud }
299*f1f57a31SAmjad Aboud 
300*f1f57a31SAmjad Aboud void TruncInstCombine::ReduceExpressionDag(Type *SclTy) {
301*f1f57a31SAmjad Aboud   for (auto &Itr : InstInfoMap) { // Forward
302*f1f57a31SAmjad Aboud     Instruction *I = Itr.first;
303*f1f57a31SAmjad Aboud     TruncInstCombine::Info &NodeInfo = Itr.second;
304*f1f57a31SAmjad Aboud 
305*f1f57a31SAmjad Aboud     assert(!NodeInfo.NewValue && "Instruction has been evaluated");
306*f1f57a31SAmjad Aboud 
307*f1f57a31SAmjad Aboud     IRBuilder<> Builder(I);
308*f1f57a31SAmjad Aboud     Value *Res = nullptr;
309*f1f57a31SAmjad Aboud     unsigned Opc = I->getOpcode();
310*f1f57a31SAmjad Aboud     switch (Opc) {
311*f1f57a31SAmjad Aboud     case Instruction::Trunc:
312*f1f57a31SAmjad Aboud     case Instruction::ZExt:
313*f1f57a31SAmjad Aboud     case Instruction::SExt: {
314*f1f57a31SAmjad Aboud       Type *Ty = getReducedType(I, SclTy);
315*f1f57a31SAmjad Aboud       // If the source type of the cast is the type we're trying for then we can
316*f1f57a31SAmjad Aboud       // just return the source.  There's no need to insert it because it is not
317*f1f57a31SAmjad Aboud       // new.
318*f1f57a31SAmjad Aboud       if (I->getOperand(0)->getType() == Ty) {
319*f1f57a31SAmjad Aboud         NodeInfo.NewValue = I->getOperand(0);
320*f1f57a31SAmjad Aboud         continue;
321*f1f57a31SAmjad Aboud       }
322*f1f57a31SAmjad Aboud       // Otherwise, must be the same type of cast, so just reinsert a new one.
323*f1f57a31SAmjad Aboud       // This also handles the case of zext(trunc(x)) -> zext(x).
324*f1f57a31SAmjad Aboud       Res = Builder.CreateIntCast(I->getOperand(0), Ty,
325*f1f57a31SAmjad Aboud                                   Opc == Instruction::SExt);
326*f1f57a31SAmjad Aboud 
327*f1f57a31SAmjad Aboud       // Update Worklist entries with new value if needed.
328*f1f57a31SAmjad Aboud       if (auto *NewCI = dyn_cast<TruncInst>(Res)) {
329*f1f57a31SAmjad Aboud         auto Entry = find(Worklist, I);
330*f1f57a31SAmjad Aboud         if (Entry != Worklist.end())
331*f1f57a31SAmjad Aboud           *Entry = NewCI;
332*f1f57a31SAmjad Aboud       }
333*f1f57a31SAmjad Aboud       break;
334*f1f57a31SAmjad Aboud     }
335*f1f57a31SAmjad Aboud     case Instruction::Add:
336*f1f57a31SAmjad Aboud     case Instruction::Sub:
337*f1f57a31SAmjad Aboud     case Instruction::Mul:
338*f1f57a31SAmjad Aboud     case Instruction::And:
339*f1f57a31SAmjad Aboud     case Instruction::Or:
340*f1f57a31SAmjad Aboud     case Instruction::Xor: {
341*f1f57a31SAmjad Aboud       Value *LHS = getReducedOperand(I->getOperand(0), SclTy);
342*f1f57a31SAmjad Aboud       Value *RHS = getReducedOperand(I->getOperand(1), SclTy);
343*f1f57a31SAmjad Aboud       Res = Builder.CreateBinOp((Instruction::BinaryOps)Opc, LHS, RHS);
344*f1f57a31SAmjad Aboud       break;
345*f1f57a31SAmjad Aboud     }
346*f1f57a31SAmjad Aboud     default:
347*f1f57a31SAmjad Aboud       llvm_unreachable("Unhandled instruction");
348*f1f57a31SAmjad Aboud     }
349*f1f57a31SAmjad Aboud 
350*f1f57a31SAmjad Aboud     NodeInfo.NewValue = Res;
351*f1f57a31SAmjad Aboud     if (auto *ResI = dyn_cast<Instruction>(Res))
352*f1f57a31SAmjad Aboud       ResI->takeName(I);
353*f1f57a31SAmjad Aboud   }
354*f1f57a31SAmjad Aboud 
355*f1f57a31SAmjad Aboud   Value *Res = getReducedOperand(CurrentTruncInst->getOperand(0), SclTy);
356*f1f57a31SAmjad Aboud   Type *DstTy = CurrentTruncInst->getType();
357*f1f57a31SAmjad Aboud   if (Res->getType() != DstTy) {
358*f1f57a31SAmjad Aboud     IRBuilder<> Builder(CurrentTruncInst);
359*f1f57a31SAmjad Aboud     Res = Builder.CreateIntCast(Res, DstTy, false);
360*f1f57a31SAmjad Aboud     if (auto *ResI = dyn_cast<Instruction>(Res))
361*f1f57a31SAmjad Aboud       ResI->takeName(CurrentTruncInst);
362*f1f57a31SAmjad Aboud   }
363*f1f57a31SAmjad Aboud   CurrentTruncInst->replaceAllUsesWith(Res);
364*f1f57a31SAmjad Aboud 
365*f1f57a31SAmjad Aboud   // Erase old expression dag, which was replaced by the reduced expression dag.
366*f1f57a31SAmjad Aboud   // We iterate backward, which means we visit the instruction before we visit
367*f1f57a31SAmjad Aboud   // any of its operands, this way, when we get to the operand, we already
368*f1f57a31SAmjad Aboud   // removed the instructions (from the expression dag) that uses it.
369*f1f57a31SAmjad Aboud   CurrentTruncInst->eraseFromParent();
370*f1f57a31SAmjad Aboud   for (auto I = InstInfoMap.rbegin(), E = InstInfoMap.rend(); I != E; ++I) {
371*f1f57a31SAmjad Aboud     // We still need to check that the instruction has no users before we erase
372*f1f57a31SAmjad Aboud     // it, because {SExt, ZExt}Inst Instruction might have other users that was
373*f1f57a31SAmjad Aboud     // not reduced, in such case, we need to keep that instruction.
374*f1f57a31SAmjad Aboud     if (!I->first->getNumUses())
375*f1f57a31SAmjad Aboud       I->first->eraseFromParent();
376*f1f57a31SAmjad Aboud   }
377*f1f57a31SAmjad Aboud }
378*f1f57a31SAmjad Aboud 
379*f1f57a31SAmjad Aboud bool TruncInstCombine::run(Function &F) {
380*f1f57a31SAmjad Aboud   bool MadeIRChange = false;
381*f1f57a31SAmjad Aboud 
382*f1f57a31SAmjad Aboud   // Collect all TruncInst in the function into the Worklist for evaluating.
383*f1f57a31SAmjad Aboud   for (auto &BB : F)
384*f1f57a31SAmjad Aboud     for (auto &I : BB)
385*f1f57a31SAmjad Aboud       if (auto *CI = dyn_cast<TruncInst>(&I))
386*f1f57a31SAmjad Aboud         Worklist.push_back(CI);
387*f1f57a31SAmjad Aboud 
388*f1f57a31SAmjad Aboud   // Process all TruncInst in the Worklist, for each instruction:
389*f1f57a31SAmjad Aboud   //   1. Check if it dominates an eligible expression dag to be reduced.
390*f1f57a31SAmjad Aboud   //   2. Create a reduced expression dag and replace the old one with it.
391*f1f57a31SAmjad Aboud   while (!Worklist.empty()) {
392*f1f57a31SAmjad Aboud     CurrentTruncInst = Worklist.pop_back_val();
393*f1f57a31SAmjad Aboud 
394*f1f57a31SAmjad Aboud     if (Type *NewDstSclTy = getBestTruncatedType()) {
395*f1f57a31SAmjad Aboud       DEBUG(dbgs() << "ICE: TruncInstCombine reducing type of expression dag "
396*f1f57a31SAmjad Aboud                       "dominated by: "
397*f1f57a31SAmjad Aboud                    << CurrentTruncInst << '\n');
398*f1f57a31SAmjad Aboud       ReduceExpressionDag(NewDstSclTy);
399*f1f57a31SAmjad Aboud       MadeIRChange = true;
400*f1f57a31SAmjad Aboud     }
401*f1f57a31SAmjad Aboud   }
402*f1f57a31SAmjad Aboud 
403*f1f57a31SAmjad Aboud   return MadeIRChange;
404*f1f57a31SAmjad Aboud }
405