1f1f57a31SAmjad Aboud //===- TruncInstCombine.cpp -----------------------------------------------===// 2f1f57a31SAmjad Aboud // 32946cd70SChandler Carruth // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 42946cd70SChandler Carruth // See https://llvm.org/LICENSE.txt for license information. 52946cd70SChandler Carruth // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6f1f57a31SAmjad Aboud // 7f1f57a31SAmjad Aboud //===----------------------------------------------------------------------===// 8f1f57a31SAmjad Aboud // 9f1f57a31SAmjad Aboud // TruncInstCombine - looks for expression dags post-dominated by TruncInst and 10f1f57a31SAmjad Aboud // for each eligible dag, it will create a reduced bit-width expression, replace 11f1f57a31SAmjad Aboud // the old expression with this new one and remove the old expression. 12f1f57a31SAmjad Aboud // Eligible expression dag is such that: 13f1f57a31SAmjad Aboud // 1. Contains only supported instructions. 14f1f57a31SAmjad Aboud // 2. Supported leaves: ZExtInst, SExtInst, TruncInst and Constant value. 15f1f57a31SAmjad Aboud // 3. Can be evaluated into type with reduced legal bit-width. 16f1f57a31SAmjad Aboud // 4. All instructions in the dag must not have users outside the dag. 17f1f57a31SAmjad Aboud // The only exception is for {ZExt, SExt}Inst with operand type equal to 18f1f57a31SAmjad Aboud // the new reduced type evaluated in (3). 19f1f57a31SAmjad Aboud // 20f1f57a31SAmjad Aboud // The motivation for this optimization is that evaluating and expression using 21f1f57a31SAmjad Aboud // smaller bit-width is preferable, especially for vectorization where we can 22f1f57a31SAmjad Aboud // fit more values in one vectorized instruction. In addition, this optimization 23f1f57a31SAmjad Aboud // may decrease the number of cast instructions, but will not increase it. 24f1f57a31SAmjad Aboud // 25f1f57a31SAmjad Aboud //===----------------------------------------------------------------------===// 26f1f57a31SAmjad Aboud 27f1f57a31SAmjad Aboud #include "AggressiveInstCombineInternal.h" 28f1f57a31SAmjad Aboud #include "llvm/ADT/MapVector.h" 29f1f57a31SAmjad Aboud #include "llvm/ADT/STLExtras.h" 30f1f57a31SAmjad Aboud #include "llvm/Analysis/ConstantFolding.h" 31f1f57a31SAmjad Aboud #include "llvm/Analysis/TargetLibraryInfo.h" 32f1f57a31SAmjad Aboud #include "llvm/IR/DataLayout.h" 33d895bff5SAmjad Aboud #include "llvm/IR/Dominators.h" 34f1f57a31SAmjad Aboud #include "llvm/IR/IRBuilder.h" 35f1f57a31SAmjad Aboud using namespace llvm; 36f1f57a31SAmjad Aboud 37f1f57a31SAmjad Aboud #define DEBUG_TYPE "aggressive-instcombine" 38f1f57a31SAmjad Aboud 39f1f57a31SAmjad Aboud /// Given an instruction and a container, it fills all the relevant operands of 40f1f57a31SAmjad Aboud /// that instruction, with respect to the Trunc expression dag optimizaton. 41f1f57a31SAmjad Aboud static void getRelevantOperands(Instruction *I, SmallVectorImpl<Value *> &Ops) { 42f1f57a31SAmjad Aboud unsigned Opc = I->getOpcode(); 43f1f57a31SAmjad Aboud switch (Opc) { 44f1f57a31SAmjad Aboud case Instruction::Trunc: 45f1f57a31SAmjad Aboud case Instruction::ZExt: 46f1f57a31SAmjad Aboud case Instruction::SExt: 47f1f57a31SAmjad Aboud // These CastInst are considered leaves of the evaluated expression, thus, 48f1f57a31SAmjad Aboud // their operands are not relevent. 49f1f57a31SAmjad Aboud break; 50f1f57a31SAmjad Aboud case Instruction::Add: 51f1f57a31SAmjad Aboud case Instruction::Sub: 52f1f57a31SAmjad Aboud case Instruction::Mul: 53f1f57a31SAmjad Aboud case Instruction::And: 54f1f57a31SAmjad Aboud case Instruction::Or: 55f1f57a31SAmjad Aboud case Instruction::Xor: 56f1f57a31SAmjad Aboud Ops.push_back(I->getOperand(0)); 57f1f57a31SAmjad Aboud Ops.push_back(I->getOperand(1)); 58f1f57a31SAmjad Aboud break; 593bda9059SAyman Musa case Instruction::Select: 603bda9059SAyman Musa Ops.push_back(I->getOperand(1)); 613bda9059SAyman Musa Ops.push_back(I->getOperand(2)); 623bda9059SAyman Musa break; 63f1f57a31SAmjad Aboud default: 64f1f57a31SAmjad Aboud llvm_unreachable("Unreachable!"); 65f1f57a31SAmjad Aboud } 66f1f57a31SAmjad Aboud } 67f1f57a31SAmjad Aboud 68f1f57a31SAmjad Aboud bool TruncInstCombine::buildTruncExpressionDag() { 69f1f57a31SAmjad Aboud SmallVector<Value *, 8> Worklist; 70f1f57a31SAmjad Aboud SmallVector<Instruction *, 8> Stack; 71f1f57a31SAmjad Aboud // Clear old expression dag. 72f1f57a31SAmjad Aboud InstInfoMap.clear(); 73f1f57a31SAmjad Aboud 74f1f57a31SAmjad Aboud Worklist.push_back(CurrentTruncInst->getOperand(0)); 75f1f57a31SAmjad Aboud 76f1f57a31SAmjad Aboud while (!Worklist.empty()) { 77f1f57a31SAmjad Aboud Value *Curr = Worklist.back(); 78f1f57a31SAmjad Aboud 79f1f57a31SAmjad Aboud if (isa<Constant>(Curr)) { 80f1f57a31SAmjad Aboud Worklist.pop_back(); 81f1f57a31SAmjad Aboud continue; 82f1f57a31SAmjad Aboud } 83f1f57a31SAmjad Aboud 84f1f57a31SAmjad Aboud auto *I = dyn_cast<Instruction>(Curr); 85f1f57a31SAmjad Aboud if (!I) 86f1f57a31SAmjad Aboud return false; 87f1f57a31SAmjad Aboud 88f1f57a31SAmjad Aboud if (!Stack.empty() && Stack.back() == I) { 89f1f57a31SAmjad Aboud // Already handled all instruction operands, can remove it from both the 90f1f57a31SAmjad Aboud // Worklist and the Stack, and add it to the instruction info map. 91f1f57a31SAmjad Aboud Worklist.pop_back(); 92f1f57a31SAmjad Aboud Stack.pop_back(); 93f1f57a31SAmjad Aboud // Insert I to the Info map. 94f1f57a31SAmjad Aboud InstInfoMap.insert(std::make_pair(I, Info())); 95f1f57a31SAmjad Aboud continue; 96f1f57a31SAmjad Aboud } 97f1f57a31SAmjad Aboud 98f1f57a31SAmjad Aboud if (InstInfoMap.count(I)) { 99f1f57a31SAmjad Aboud Worklist.pop_back(); 100f1f57a31SAmjad Aboud continue; 101f1f57a31SAmjad Aboud } 102f1f57a31SAmjad Aboud 103f1f57a31SAmjad Aboud // Add the instruction to the stack before start handling its operands. 104f1f57a31SAmjad Aboud Stack.push_back(I); 105f1f57a31SAmjad Aboud 106f1f57a31SAmjad Aboud unsigned Opc = I->getOpcode(); 107f1f57a31SAmjad Aboud switch (Opc) { 108f1f57a31SAmjad Aboud case Instruction::Trunc: 109f1f57a31SAmjad Aboud case Instruction::ZExt: 110f1f57a31SAmjad Aboud case Instruction::SExt: 111f1f57a31SAmjad Aboud // trunc(trunc(x)) -> trunc(x) 112f1f57a31SAmjad Aboud // trunc(ext(x)) -> ext(x) if the source type is smaller than the new dest 113f1f57a31SAmjad Aboud // trunc(ext(x)) -> trunc(x) if the source type is larger than the new 114f1f57a31SAmjad Aboud // dest 115f1f57a31SAmjad Aboud break; 116f1f57a31SAmjad Aboud case Instruction::Add: 117f1f57a31SAmjad Aboud case Instruction::Sub: 118f1f57a31SAmjad Aboud case Instruction::Mul: 119f1f57a31SAmjad Aboud case Instruction::And: 120f1f57a31SAmjad Aboud case Instruction::Or: 1213bda9059SAyman Musa case Instruction::Xor: 12235f02aa0SAyman Musa case Instruction::Select: { 123f1f57a31SAmjad Aboud SmallVector<Value *, 2> Operands; 124f1f57a31SAmjad Aboud getRelevantOperands(I, Operands); 125f1f57a31SAmjad Aboud for (Value *Operand : Operands) 126f1f57a31SAmjad Aboud Worklist.push_back(Operand); 127f1f57a31SAmjad Aboud break; 128f1f57a31SAmjad Aboud } 129f1f57a31SAmjad Aboud default: 130f1f57a31SAmjad Aboud // TODO: Can handle more cases here: 1313bda9059SAyman Musa // 1. shufflevector, extractelement, insertelement 132f1f57a31SAmjad Aboud // 2. udiv, urem 133f1f57a31SAmjad Aboud // 3. shl, lshr, ashr 134f1f57a31SAmjad Aboud // 4. phi node(and loop handling) 135f1f57a31SAmjad Aboud // ... 136f1f57a31SAmjad Aboud return false; 137f1f57a31SAmjad Aboud } 138f1f57a31SAmjad Aboud } 139f1f57a31SAmjad Aboud return true; 140f1f57a31SAmjad Aboud } 141f1f57a31SAmjad Aboud 142f1f57a31SAmjad Aboud unsigned TruncInstCombine::getMinBitWidth() { 143f1f57a31SAmjad Aboud SmallVector<Value *, 8> Worklist; 144f1f57a31SAmjad Aboud SmallVector<Instruction *, 8> Stack; 145f1f57a31SAmjad Aboud 146f1f57a31SAmjad Aboud Value *Src = CurrentTruncInst->getOperand(0); 147f1f57a31SAmjad Aboud Type *DstTy = CurrentTruncInst->getType(); 148f1f57a31SAmjad Aboud unsigned TruncBitWidth = DstTy->getScalarSizeInBits(); 149f1f57a31SAmjad Aboud unsigned OrigBitWidth = 150f1f57a31SAmjad Aboud CurrentTruncInst->getOperand(0)->getType()->getScalarSizeInBits(); 151f1f57a31SAmjad Aboud 152f1f57a31SAmjad Aboud if (isa<Constant>(Src)) 153f1f57a31SAmjad Aboud return TruncBitWidth; 154f1f57a31SAmjad Aboud 155f1f57a31SAmjad Aboud Worklist.push_back(Src); 156f1f57a31SAmjad Aboud InstInfoMap[cast<Instruction>(Src)].ValidBitWidth = TruncBitWidth; 157f1f57a31SAmjad Aboud 158f1f57a31SAmjad Aboud while (!Worklist.empty()) { 159f1f57a31SAmjad Aboud Value *Curr = Worklist.back(); 160f1f57a31SAmjad Aboud 161f1f57a31SAmjad Aboud if (isa<Constant>(Curr)) { 162f1f57a31SAmjad Aboud Worklist.pop_back(); 163f1f57a31SAmjad Aboud continue; 164f1f57a31SAmjad Aboud } 165f1f57a31SAmjad Aboud 166f1f57a31SAmjad Aboud // Otherwise, it must be an instruction. 167f1f57a31SAmjad Aboud auto *I = cast<Instruction>(Curr); 168f1f57a31SAmjad Aboud 169f1f57a31SAmjad Aboud auto &Info = InstInfoMap[I]; 170f1f57a31SAmjad Aboud 171f1f57a31SAmjad Aboud SmallVector<Value *, 2> Operands; 172f1f57a31SAmjad Aboud getRelevantOperands(I, Operands); 173f1f57a31SAmjad Aboud 174f1f57a31SAmjad Aboud if (!Stack.empty() && Stack.back() == I) { 175f1f57a31SAmjad Aboud // Already handled all instruction operands, can remove it from both, the 176f1f57a31SAmjad Aboud // Worklist and the Stack, and update MinBitWidth. 177f1f57a31SAmjad Aboud Worklist.pop_back(); 178f1f57a31SAmjad Aboud Stack.pop_back(); 179f1f57a31SAmjad Aboud for (auto *Operand : Operands) 180f1f57a31SAmjad Aboud if (auto *IOp = dyn_cast<Instruction>(Operand)) 181f1f57a31SAmjad Aboud Info.MinBitWidth = 182f1f57a31SAmjad Aboud std::max(Info.MinBitWidth, InstInfoMap[IOp].MinBitWidth); 183f1f57a31SAmjad Aboud continue; 184f1f57a31SAmjad Aboud } 185f1f57a31SAmjad Aboud 186f1f57a31SAmjad Aboud // Add the instruction to the stack before start handling its operands. 187f1f57a31SAmjad Aboud Stack.push_back(I); 188f1f57a31SAmjad Aboud unsigned ValidBitWidth = Info.ValidBitWidth; 189f1f57a31SAmjad Aboud 190f1f57a31SAmjad Aboud // Update minimum bit-width before handling its operands. This is required 191f1f57a31SAmjad Aboud // when the instruction is part of a loop. 192f1f57a31SAmjad Aboud Info.MinBitWidth = std::max(Info.MinBitWidth, Info.ValidBitWidth); 193f1f57a31SAmjad Aboud 194f1f57a31SAmjad Aboud for (auto *Operand : Operands) 195f1f57a31SAmjad Aboud if (auto *IOp = dyn_cast<Instruction>(Operand)) { 196f1f57a31SAmjad Aboud // If we already calculated the minimum bit-width for this valid 197f1f57a31SAmjad Aboud // bit-width, or for a smaller valid bit-width, then just keep the 198f1f57a31SAmjad Aboud // answer we already calculated. 199f1f57a31SAmjad Aboud unsigned IOpBitwidth = InstInfoMap.lookup(IOp).ValidBitWidth; 200f1f57a31SAmjad Aboud if (IOpBitwidth >= ValidBitWidth) 201f1f57a31SAmjad Aboud continue; 20249a4d85fSAyman Musa InstInfoMap[IOp].ValidBitWidth = ValidBitWidth; 203f1f57a31SAmjad Aboud Worklist.push_back(IOp); 204f1f57a31SAmjad Aboud } 205f1f57a31SAmjad Aboud } 206f1f57a31SAmjad Aboud unsigned MinBitWidth = InstInfoMap.lookup(cast<Instruction>(Src)).MinBitWidth; 207f1f57a31SAmjad Aboud assert(MinBitWidth >= TruncBitWidth); 208f1f57a31SAmjad Aboud 209f1f57a31SAmjad Aboud if (MinBitWidth > TruncBitWidth) { 210f1f57a31SAmjad Aboud // In this case reducing expression with vector type might generate a new 211f1f57a31SAmjad Aboud // vector type, which is not preferable as it might result in generating 212f1f57a31SAmjad Aboud // sub-optimal code. 213f1f57a31SAmjad Aboud if (DstTy->isVectorTy()) 214f1f57a31SAmjad Aboud return OrigBitWidth; 215f1f57a31SAmjad Aboud // Use the smallest integer type in the range [MinBitWidth, OrigBitWidth). 216f1f57a31SAmjad Aboud Type *Ty = DL.getSmallestLegalIntType(DstTy->getContext(), MinBitWidth); 217f1f57a31SAmjad Aboud // Update minimum bit-width with the new destination type bit-width if 218f1f57a31SAmjad Aboud // succeeded to find such, otherwise, with original bit-width. 219f1f57a31SAmjad Aboud MinBitWidth = Ty ? Ty->getScalarSizeInBits() : OrigBitWidth; 220f1f57a31SAmjad Aboud } else { // MinBitWidth == TruncBitWidth 221f1f57a31SAmjad Aboud // In this case the expression can be evaluated with the trunc instruction 222f1f57a31SAmjad Aboud // destination type, and trunc instruction can be omitted. However, we 223f1f57a31SAmjad Aboud // should not perform the evaluation if the original type is a legal scalar 224f1f57a31SAmjad Aboud // type and the target type is illegal. 225f1f57a31SAmjad Aboud bool FromLegal = MinBitWidth == 1 || DL.isLegalInteger(OrigBitWidth); 226f1f57a31SAmjad Aboud bool ToLegal = MinBitWidth == 1 || DL.isLegalInteger(MinBitWidth); 227f1f57a31SAmjad Aboud if (!DstTy->isVectorTy() && FromLegal && !ToLegal) 228f1f57a31SAmjad Aboud return OrigBitWidth; 229f1f57a31SAmjad Aboud } 230f1f57a31SAmjad Aboud return MinBitWidth; 231f1f57a31SAmjad Aboud } 232f1f57a31SAmjad Aboud 233f1f57a31SAmjad Aboud Type *TruncInstCombine::getBestTruncatedType() { 234f1f57a31SAmjad Aboud if (!buildTruncExpressionDag()) 235f1f57a31SAmjad Aboud return nullptr; 236f1f57a31SAmjad Aboud 237f1f57a31SAmjad Aboud // We don't want to duplicate instructions, which isn't profitable. Thus, we 238f1f57a31SAmjad Aboud // can't shrink something that has multiple users, unless all users are 239f1f57a31SAmjad Aboud // post-dominated by the trunc instruction, i.e., were visited during the 240f1f57a31SAmjad Aboud // expression evaluation. 241f1f57a31SAmjad Aboud unsigned DesiredBitWidth = 0; 242f1f57a31SAmjad Aboud for (auto Itr : InstInfoMap) { 243f1f57a31SAmjad Aboud Instruction *I = Itr.first; 244f1f57a31SAmjad Aboud if (I->hasOneUse()) 245f1f57a31SAmjad Aboud continue; 246f1f57a31SAmjad Aboud bool IsExtInst = (isa<ZExtInst>(I) || isa<SExtInst>(I)); 247f1f57a31SAmjad Aboud for (auto *U : I->users()) 248f1f57a31SAmjad Aboud if (auto *UI = dyn_cast<Instruction>(U)) 249f1f57a31SAmjad Aboud if (UI != CurrentTruncInst && !InstInfoMap.count(UI)) { 250f1f57a31SAmjad Aboud if (!IsExtInst) 251f1f57a31SAmjad Aboud return nullptr; 252f1f57a31SAmjad Aboud // If this is an extension from the dest type, we can eliminate it, 253f1f57a31SAmjad Aboud // even if it has multiple users. Thus, update the DesiredBitWidth and 254f1f57a31SAmjad Aboud // validate all extension instructions agrees on same DesiredBitWidth. 255f1f57a31SAmjad Aboud unsigned ExtInstBitWidth = 256f1f57a31SAmjad Aboud I->getOperand(0)->getType()->getScalarSizeInBits(); 257f1f57a31SAmjad Aboud if (DesiredBitWidth && DesiredBitWidth != ExtInstBitWidth) 258f1f57a31SAmjad Aboud return nullptr; 259f1f57a31SAmjad Aboud DesiredBitWidth = ExtInstBitWidth; 260f1f57a31SAmjad Aboud } 261f1f57a31SAmjad Aboud } 262f1f57a31SAmjad Aboud 263f1f57a31SAmjad Aboud unsigned OrigBitWidth = 264f1f57a31SAmjad Aboud CurrentTruncInst->getOperand(0)->getType()->getScalarSizeInBits(); 265f1f57a31SAmjad Aboud 266f1f57a31SAmjad Aboud // Calculate minimum allowed bit-width allowed for shrinking the currently 267f1f57a31SAmjad Aboud // visited truncate's operand. 268f1f57a31SAmjad Aboud unsigned MinBitWidth = getMinBitWidth(); 269f1f57a31SAmjad Aboud 270f1f57a31SAmjad Aboud // Check that we can shrink to smaller bit-width than original one and that 271f1f57a31SAmjad Aboud // it is similar to the DesiredBitWidth is such exists. 272f1f57a31SAmjad Aboud if (MinBitWidth >= OrigBitWidth || 273f1f57a31SAmjad Aboud (DesiredBitWidth && DesiredBitWidth != MinBitWidth)) 274f1f57a31SAmjad Aboud return nullptr; 275f1f57a31SAmjad Aboud 276f1f57a31SAmjad Aboud return IntegerType::get(CurrentTruncInst->getContext(), MinBitWidth); 277f1f57a31SAmjad Aboud } 278f1f57a31SAmjad Aboud 279f1f57a31SAmjad Aboud /// Given a reduced scalar type \p Ty and a \p V value, return a reduced type 280f1f57a31SAmjad Aboud /// for \p V, according to its type, if it vector type, return the vector 281f1f57a31SAmjad Aboud /// version of \p Ty, otherwise return \p Ty. 282f1f57a31SAmjad Aboud static Type *getReducedType(Value *V, Type *Ty) { 283f1f57a31SAmjad Aboud assert(Ty && !Ty->isVectorTy() && "Expect Scalar Type"); 284f1f57a31SAmjad Aboud if (auto *VTy = dyn_cast<VectorType>(V->getType())) 285f1f57a31SAmjad Aboud return VectorType::get(Ty, VTy->getNumElements()); 286f1f57a31SAmjad Aboud return Ty; 287f1f57a31SAmjad Aboud } 288f1f57a31SAmjad Aboud 289f1f57a31SAmjad Aboud Value *TruncInstCombine::getReducedOperand(Value *V, Type *SclTy) { 290f1f57a31SAmjad Aboud Type *Ty = getReducedType(V, SclTy); 291f1f57a31SAmjad Aboud if (auto *C = dyn_cast<Constant>(V)) { 292f1f57a31SAmjad Aboud C = ConstantExpr::getIntegerCast(C, Ty, false); 293f1f57a31SAmjad Aboud // If we got a constantexpr back, try to simplify it with DL info. 294*0e890cd4SNikita Popov return ConstantFoldConstant(C, DL, &TLI); 295f1f57a31SAmjad Aboud } 296f1f57a31SAmjad Aboud 297f1f57a31SAmjad Aboud auto *I = cast<Instruction>(V); 298f1f57a31SAmjad Aboud Info Entry = InstInfoMap.lookup(I); 299f1f57a31SAmjad Aboud assert(Entry.NewValue); 300f1f57a31SAmjad Aboud return Entry.NewValue; 301f1f57a31SAmjad Aboud } 302f1f57a31SAmjad Aboud 303f1f57a31SAmjad Aboud void TruncInstCombine::ReduceExpressionDag(Type *SclTy) { 304f1f57a31SAmjad Aboud for (auto &Itr : InstInfoMap) { // Forward 305f1f57a31SAmjad Aboud Instruction *I = Itr.first; 306f1f57a31SAmjad Aboud TruncInstCombine::Info &NodeInfo = Itr.second; 307f1f57a31SAmjad Aboud 308f1f57a31SAmjad Aboud assert(!NodeInfo.NewValue && "Instruction has been evaluated"); 309f1f57a31SAmjad Aboud 310f1f57a31SAmjad Aboud IRBuilder<> Builder(I); 311f1f57a31SAmjad Aboud Value *Res = nullptr; 312f1f57a31SAmjad Aboud unsigned Opc = I->getOpcode(); 313f1f57a31SAmjad Aboud switch (Opc) { 314f1f57a31SAmjad Aboud case Instruction::Trunc: 315f1f57a31SAmjad Aboud case Instruction::ZExt: 316f1f57a31SAmjad Aboud case Instruction::SExt: { 317f1f57a31SAmjad Aboud Type *Ty = getReducedType(I, SclTy); 318f1f57a31SAmjad Aboud // If the source type of the cast is the type we're trying for then we can 319f1f57a31SAmjad Aboud // just return the source. There's no need to insert it because it is not 320f1f57a31SAmjad Aboud // new. 321f1f57a31SAmjad Aboud if (I->getOperand(0)->getType() == Ty) { 322b86b771cSAmjad Aboud assert(!isa<TruncInst>(I) && "Cannot reach here with TruncInst"); 323f1f57a31SAmjad Aboud NodeInfo.NewValue = I->getOperand(0); 324f1f57a31SAmjad Aboud continue; 325f1f57a31SAmjad Aboud } 326f1f57a31SAmjad Aboud // Otherwise, must be the same type of cast, so just reinsert a new one. 327f1f57a31SAmjad Aboud // This also handles the case of zext(trunc(x)) -> zext(x). 328f1f57a31SAmjad Aboud Res = Builder.CreateIntCast(I->getOperand(0), Ty, 329f1f57a31SAmjad Aboud Opc == Instruction::SExt); 330f1f57a31SAmjad Aboud 331f1f57a31SAmjad Aboud // Update Worklist entries with new value if needed. 332b86b771cSAmjad Aboud // There are three possible changes to the Worklist: 333b86b771cSAmjad Aboud // 1. Update Old-TruncInst -> New-TruncInst. 334b86b771cSAmjad Aboud // 2. Remove Old-TruncInst (if New node is not TruncInst). 335b86b771cSAmjad Aboud // 3. Add New-TruncInst (if Old node was not TruncInst). 336f1f57a31SAmjad Aboud auto Entry = find(Worklist, I); 337b86b771cSAmjad Aboud if (Entry != Worklist.end()) { 338b86b771cSAmjad Aboud if (auto *NewCI = dyn_cast<TruncInst>(Res)) 339f1f57a31SAmjad Aboud *Entry = NewCI; 340b86b771cSAmjad Aboud else 341b86b771cSAmjad Aboud Worklist.erase(Entry); 342b86b771cSAmjad Aboud } else if (auto *NewCI = dyn_cast<TruncInst>(Res)) 343b86b771cSAmjad Aboud Worklist.push_back(NewCI); 344f1f57a31SAmjad Aboud break; 345f1f57a31SAmjad Aboud } 346f1f57a31SAmjad Aboud case Instruction::Add: 347f1f57a31SAmjad Aboud case Instruction::Sub: 348f1f57a31SAmjad Aboud case Instruction::Mul: 349f1f57a31SAmjad Aboud case Instruction::And: 350f1f57a31SAmjad Aboud case Instruction::Or: 351f1f57a31SAmjad Aboud case Instruction::Xor: { 352f1f57a31SAmjad Aboud Value *LHS = getReducedOperand(I->getOperand(0), SclTy); 353f1f57a31SAmjad Aboud Value *RHS = getReducedOperand(I->getOperand(1), SclTy); 354f1f57a31SAmjad Aboud Res = Builder.CreateBinOp((Instruction::BinaryOps)Opc, LHS, RHS); 355f1f57a31SAmjad Aboud break; 356f1f57a31SAmjad Aboud } 3573bda9059SAyman Musa case Instruction::Select: { 3583bda9059SAyman Musa Value *Op0 = I->getOperand(0); 3593bda9059SAyman Musa Value *LHS = getReducedOperand(I->getOperand(1), SclTy); 3603bda9059SAyman Musa Value *RHS = getReducedOperand(I->getOperand(2), SclTy); 3613bda9059SAyman Musa Res = Builder.CreateSelect(Op0, LHS, RHS); 3623bda9059SAyman Musa break; 3633bda9059SAyman Musa } 364f1f57a31SAmjad Aboud default: 365f1f57a31SAmjad Aboud llvm_unreachable("Unhandled instruction"); 366f1f57a31SAmjad Aboud } 367f1f57a31SAmjad Aboud 368f1f57a31SAmjad Aboud NodeInfo.NewValue = Res; 369f1f57a31SAmjad Aboud if (auto *ResI = dyn_cast<Instruction>(Res)) 370f1f57a31SAmjad Aboud ResI->takeName(I); 371f1f57a31SAmjad Aboud } 372f1f57a31SAmjad Aboud 373f1f57a31SAmjad Aboud Value *Res = getReducedOperand(CurrentTruncInst->getOperand(0), SclTy); 374f1f57a31SAmjad Aboud Type *DstTy = CurrentTruncInst->getType(); 375f1f57a31SAmjad Aboud if (Res->getType() != DstTy) { 376f1f57a31SAmjad Aboud IRBuilder<> Builder(CurrentTruncInst); 377f1f57a31SAmjad Aboud Res = Builder.CreateIntCast(Res, DstTy, false); 378f1f57a31SAmjad Aboud if (auto *ResI = dyn_cast<Instruction>(Res)) 379f1f57a31SAmjad Aboud ResI->takeName(CurrentTruncInst); 380f1f57a31SAmjad Aboud } 381f1f57a31SAmjad Aboud CurrentTruncInst->replaceAllUsesWith(Res); 382f1f57a31SAmjad Aboud 383f1f57a31SAmjad Aboud // Erase old expression dag, which was replaced by the reduced expression dag. 384f1f57a31SAmjad Aboud // We iterate backward, which means we visit the instruction before we visit 385f1f57a31SAmjad Aboud // any of its operands, this way, when we get to the operand, we already 386f1f57a31SAmjad Aboud // removed the instructions (from the expression dag) that uses it. 387f1f57a31SAmjad Aboud CurrentTruncInst->eraseFromParent(); 388f1f57a31SAmjad Aboud for (auto I = InstInfoMap.rbegin(), E = InstInfoMap.rend(); I != E; ++I) { 389f1f57a31SAmjad Aboud // We still need to check that the instruction has no users before we erase 390f1f57a31SAmjad Aboud // it, because {SExt, ZExt}Inst Instruction might have other users that was 391f1f57a31SAmjad Aboud // not reduced, in such case, we need to keep that instruction. 3927fc591f8SVedant Kumar if (I->first->use_empty()) 393f1f57a31SAmjad Aboud I->first->eraseFromParent(); 394f1f57a31SAmjad Aboud } 395f1f57a31SAmjad Aboud } 396f1f57a31SAmjad Aboud 397f1f57a31SAmjad Aboud bool TruncInstCombine::run(Function &F) { 398f1f57a31SAmjad Aboud bool MadeIRChange = false; 399f1f57a31SAmjad Aboud 400f1f57a31SAmjad Aboud // Collect all TruncInst in the function into the Worklist for evaluating. 401d895bff5SAmjad Aboud for (auto &BB : F) { 402d895bff5SAmjad Aboud // Ignore unreachable basic block. 403d895bff5SAmjad Aboud if (!DT.isReachableFromEntry(&BB)) 404d895bff5SAmjad Aboud continue; 405f1f57a31SAmjad Aboud for (auto &I : BB) 406f1f57a31SAmjad Aboud if (auto *CI = dyn_cast<TruncInst>(&I)) 407f1f57a31SAmjad Aboud Worklist.push_back(CI); 408d895bff5SAmjad Aboud } 409f1f57a31SAmjad Aboud 410f1f57a31SAmjad Aboud // Process all TruncInst in the Worklist, for each instruction: 411f1f57a31SAmjad Aboud // 1. Check if it dominates an eligible expression dag to be reduced. 412f1f57a31SAmjad Aboud // 2. Create a reduced expression dag and replace the old one with it. 413f1f57a31SAmjad Aboud while (!Worklist.empty()) { 414f1f57a31SAmjad Aboud CurrentTruncInst = Worklist.pop_back_val(); 415f1f57a31SAmjad Aboud 416f1f57a31SAmjad Aboud if (Type *NewDstSclTy = getBestTruncatedType()) { 417d34e60caSNicola Zaghen LLVM_DEBUG( 418d34e60caSNicola Zaghen dbgs() << "ICE: TruncInstCombine reducing type of expression dag " 419f1f57a31SAmjad Aboud "dominated by: " 420f1f57a31SAmjad Aboud << CurrentTruncInst << '\n'); 421f1f57a31SAmjad Aboud ReduceExpressionDag(NewDstSclTy); 422f1f57a31SAmjad Aboud MadeIRChange = true; 423f1f57a31SAmjad Aboud } 424f1f57a31SAmjad Aboud } 425f1f57a31SAmjad Aboud 426f1f57a31SAmjad Aboud return MadeIRChange; 427f1f57a31SAmjad Aboud } 428