1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation   ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the XCoreTargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "xcore-lower"
15 
16 #include "XCoreISelLowering.h"
17 #include "XCoreMachineFunctionInfo.h"
18 #include "XCore.h"
19 #include "XCoreTargetObjectFile.h"
20 #include "XCoreTargetMachine.h"
21 #include "XCoreSubtarget.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/GlobalAlias.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAGISel.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/VectorExtras.h"
40 using namespace llvm;
41 
42 const char *XCoreTargetLowering::
43 getTargetNodeName(unsigned Opcode) const
44 {
45   switch (Opcode)
46   {
47     case XCoreISD::BL                : return "XCoreISD::BL";
48     case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
49     case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
50     case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
51     case XCoreISD::STWSP             : return "XCoreISD::STWSP";
52     case XCoreISD::RETSP             : return "XCoreISD::RETSP";
53     case XCoreISD::LADD              : return "XCoreISD::LADD";
54     case XCoreISD::LSUB              : return "XCoreISD::LSUB";
55     case XCoreISD::LMUL              : return "XCoreISD::LMUL";
56     case XCoreISD::MACCU             : return "XCoreISD::MACCU";
57     case XCoreISD::MACCS             : return "XCoreISD::MACCS";
58     case XCoreISD::BR_JT             : return "XCoreISD::BR_JT";
59     case XCoreISD::BR_JT32           : return "XCoreISD::BR_JT32";
60     default                          : return NULL;
61   }
62 }
63 
64 XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
65   : TargetLowering(XTM, new XCoreTargetObjectFile()),
66     TM(XTM),
67     Subtarget(*XTM.getSubtargetImpl()) {
68 
69   // Set up the register classes.
70   addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass);
71 
72   // Compute derived properties from the register classes
73   computeRegisterProperties();
74 
75   // Division is expensive
76   setIntDivIsCheap(false);
77 
78   setStackPointerRegisterToSaveRestore(XCore::SP);
79 
80   setSchedulingPreference(Sched::RegPressure);
81 
82   // Use i32 for setcc operations results (slt, sgt, ...).
83   setBooleanContents(ZeroOrOneBooleanContent);
84   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
85 
86   // XCore does not have the NodeTypes below.
87   setOperationAction(ISD::BR_CC,     MVT::Other, Expand);
88   setOperationAction(ISD::SELECT_CC, MVT::i32,   Custom);
89   setOperationAction(ISD::ADDC, MVT::i32, Expand);
90   setOperationAction(ISD::ADDE, MVT::i32, Expand);
91   setOperationAction(ISD::SUBC, MVT::i32, Expand);
92   setOperationAction(ISD::SUBE, MVT::i32, Expand);
93 
94   // Stop the combiner recombining select and set_cc
95   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
96 
97   // 64bit
98   setOperationAction(ISD::ADD, MVT::i64, Custom);
99   setOperationAction(ISD::SUB, MVT::i64, Custom);
100   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
101   setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
102   setOperationAction(ISD::MULHS, MVT::i32, Expand);
103   setOperationAction(ISD::MULHU, MVT::i32, Expand);
104   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
105   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
106   setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
107 
108   // Bit Manipulation
109   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
110   setOperationAction(ISD::ROTL , MVT::i32, Expand);
111   setOperationAction(ISD::ROTR , MVT::i32, Expand);
112 
113   setOperationAction(ISD::TRAP, MVT::Other, Legal);
114 
115   // Jump tables.
116   setOperationAction(ISD::BR_JT, MVT::Other, Custom);
117 
118   setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
119   setOperationAction(ISD::BlockAddress, MVT::i32 , Custom);
120 
121   // Thread Local Storage
122   setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
123 
124   // Conversion of i64 -> double produces constantpool nodes
125   setOperationAction(ISD::ConstantPool, MVT::i32,   Custom);
126 
127   // Loads
128   setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
129   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
130   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
131 
132   setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
133   setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
134 
135   // Custom expand misaligned loads / stores.
136   setOperationAction(ISD::LOAD, MVT::i32, Custom);
137   setOperationAction(ISD::STORE, MVT::i32, Custom);
138 
139   // Varargs
140   setOperationAction(ISD::VAEND, MVT::Other, Expand);
141   setOperationAction(ISD::VACOPY, MVT::Other, Expand);
142   setOperationAction(ISD::VAARG, MVT::Other, Custom);
143   setOperationAction(ISD::VASTART, MVT::Other, Custom);
144 
145   // Dynamic stack
146   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
147   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
148   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
149 
150   // TRAMPOLINE is custom lowered.
151   setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
152   setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
153 
154   maxStoresPerMemset = maxStoresPerMemsetOptSize = 4;
155   maxStoresPerMemmove = maxStoresPerMemmoveOptSize
156     = maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 2;
157 
158   // We have target-specific dag combine patterns for the following nodes:
159   setTargetDAGCombine(ISD::STORE);
160   setTargetDAGCombine(ISD::ADD);
161 
162   setMinFunctionAlignment(1);
163 }
164 
165 SDValue XCoreTargetLowering::
166 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
167   switch (Op.getOpcode())
168   {
169   case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
170   case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
171   case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
172   case ISD::ConstantPool:     return LowerConstantPool(Op, DAG);
173   case ISD::BR_JT:            return LowerBR_JT(Op, DAG);
174   case ISD::LOAD:             return LowerLOAD(Op, DAG);
175   case ISD::STORE:            return LowerSTORE(Op, DAG);
176   case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
177   case ISD::VAARG:            return LowerVAARG(Op, DAG);
178   case ISD::VASTART:          return LowerVASTART(Op, DAG);
179   case ISD::SMUL_LOHI:        return LowerSMUL_LOHI(Op, DAG);
180   case ISD::UMUL_LOHI:        return LowerUMUL_LOHI(Op, DAG);
181   // FIXME: Remove these when LegalizeDAGTypes lands.
182   case ISD::ADD:
183   case ISD::SUB:              return ExpandADDSUB(Op.getNode(), DAG);
184   case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
185   case ISD::INIT_TRAMPOLINE:  return LowerINIT_TRAMPOLINE(Op, DAG);
186   case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
187   default:
188     llvm_unreachable("unimplemented operand");
189     return SDValue();
190   }
191 }
192 
193 /// ReplaceNodeResults - Replace the results of node with an illegal result
194 /// type with new values built out of custom code.
195 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
196                                              SmallVectorImpl<SDValue>&Results,
197                                              SelectionDAG &DAG) const {
198   switch (N->getOpcode()) {
199   default:
200     llvm_unreachable("Don't know how to custom expand this!");
201     return;
202   case ISD::ADD:
203   case ISD::SUB:
204     Results.push_back(ExpandADDSUB(N, DAG));
205     return;
206   }
207 }
208 
209 //===----------------------------------------------------------------------===//
210 //  Misc Lower Operation implementation
211 //===----------------------------------------------------------------------===//
212 
213 SDValue XCoreTargetLowering::
214 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
215 {
216   DebugLoc dl = Op.getDebugLoc();
217   SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
218                              Op.getOperand(3), Op.getOperand(4));
219   return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),
220                      Op.getOperand(1));
221 }
222 
223 SDValue XCoreTargetLowering::
224 getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
225                         SelectionDAG &DAG) const
226 {
227   // FIXME there is no actual debug info here
228   DebugLoc dl = GA.getDebugLoc();
229   if (isa<Function>(GV)) {
230     return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
231   }
232   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
233   if (!GVar) {
234     // If GV is an alias then use the aliasee to determine constness
235     if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
236       GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
237   }
238   bool isConst = GVar && GVar->isConstant();
239   if (isConst) {
240     return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
241   }
242   return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
243 }
244 
245 SDValue XCoreTargetLowering::
246 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
247 {
248   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
249   SDValue GA = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), MVT::i32);
250   return getGlobalAddressWrapper(GA, GV, DAG);
251 }
252 
253 static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) {
254   return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
255                      DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
256 }
257 
258 static inline bool isZeroLengthArray(Type *Ty) {
259   ArrayType *AT = dyn_cast_or_null<ArrayType>(Ty);
260   return AT && (AT->getNumElements() == 0);
261 }
262 
263 SDValue XCoreTargetLowering::
264 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
265 {
266   // FIXME there isn't really debug info here
267   DebugLoc dl = Op.getDebugLoc();
268   // transform to label + getid() * size
269   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
270   SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
271   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
272   if (!GVar) {
273     // If GV is an alias then use the aliasee to determine size
274     if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
275       GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
276   }
277   if (! GVar) {
278     llvm_unreachable("Thread local object not a GlobalVariable?");
279     return SDValue();
280   }
281   Type *Ty = cast<PointerType>(GV->getType())->getElementType();
282   if (!Ty->isSized() || isZeroLengthArray(Ty)) {
283 #ifndef NDEBUG
284     errs() << "Size of thread local object " << GVar->getName()
285            << " is unknown\n";
286 #endif
287     llvm_unreachable(0);
288   }
289   SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
290   const TargetData *TD = TM.getTargetData();
291   unsigned Size = TD->getTypeAllocSize(Ty);
292   SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl),
293                        DAG.getConstant(Size, MVT::i32));
294   return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset);
295 }
296 
297 SDValue XCoreTargetLowering::
298 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
299 {
300   DebugLoc DL = Op.getDebugLoc();
301 
302   const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
303   SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
304 
305   return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result);
306 }
307 
308 SDValue XCoreTargetLowering::
309 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
310 {
311   ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
312   // FIXME there isn't really debug info here
313   DebugLoc dl = CP->getDebugLoc();
314   EVT PtrVT = Op.getValueType();
315   SDValue Res;
316   if (CP->isMachineConstantPoolEntry()) {
317     Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
318                                     CP->getAlignment());
319   } else {
320     Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
321                                     CP->getAlignment());
322   }
323   return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
324 }
325 
326 unsigned XCoreTargetLowering::getJumpTableEncoding() const {
327   return MachineJumpTableInfo::EK_Inline;
328 }
329 
330 SDValue XCoreTargetLowering::
331 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
332 {
333   SDValue Chain = Op.getOperand(0);
334   SDValue Table = Op.getOperand(1);
335   SDValue Index = Op.getOperand(2);
336   DebugLoc dl = Op.getDebugLoc();
337   JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
338   unsigned JTI = JT->getIndex();
339   MachineFunction &MF = DAG.getMachineFunction();
340   const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
341   SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
342 
343   unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size();
344   if (NumEntries <= 32) {
345     return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index);
346   }
347   assert((NumEntries >> 31) == 0);
348   SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
349                                     DAG.getConstant(1, MVT::i32));
350   return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
351                      ScaledIndex);
352 }
353 
354 static bool
355 IsWordAlignedBasePlusConstantOffset(SDValue Addr, SDValue &AlignedBase,
356                                     int64_t &Offset)
357 {
358   if (Addr.getOpcode() != ISD::ADD) {
359     return false;
360   }
361   ConstantSDNode *CN = 0;
362   if (!(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
363     return false;
364   }
365   int64_t off = CN->getSExtValue();
366   const SDValue &Base = Addr.getOperand(0);
367   const SDValue *Root = &Base;
368   if (Base.getOpcode() == ISD::ADD &&
369       Base.getOperand(1).getOpcode() == ISD::SHL) {
370     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Base.getOperand(1)
371                                                       .getOperand(1));
372     if (CN && (CN->getSExtValue() >= 2)) {
373       Root = &Base.getOperand(0);
374     }
375   }
376   if (isa<FrameIndexSDNode>(*Root)) {
377     // All frame indicies are word aligned
378     AlignedBase = Base;
379     Offset = off;
380     return true;
381   }
382   if (Root->getOpcode() == XCoreISD::DPRelativeWrapper ||
383       Root->getOpcode() == XCoreISD::CPRelativeWrapper) {
384     // All dp / cp relative addresses are word aligned
385     AlignedBase = Base;
386     Offset = off;
387     return true;
388   }
389   // Check for an aligned global variable.
390   if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(*Root)) {
391     const GlobalValue *GV = GA->getGlobal();
392     if (GA->getOffset() == 0 && GV->getAlignment() >= 4) {
393       AlignedBase = Base;
394       Offset = off;
395       return true;
396     }
397   }
398   return false;
399 }
400 
401 SDValue XCoreTargetLowering::
402 LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
403   LoadSDNode *LD = cast<LoadSDNode>(Op);
404   assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
405          "Unexpected extension type");
406   assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
407   if (allowsUnalignedMemoryAccesses(LD->getMemoryVT()))
408     return SDValue();
409 
410   unsigned ABIAlignment = getTargetData()->
411     getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
412   // Leave aligned load alone.
413   if (LD->getAlignment() >= ABIAlignment)
414     return SDValue();
415 
416   SDValue Chain = LD->getChain();
417   SDValue BasePtr = LD->getBasePtr();
418   DebugLoc DL = Op.getDebugLoc();
419 
420   SDValue Base;
421   int64_t Offset;
422   if (!LD->isVolatile() &&
423       IsWordAlignedBasePlusConstantOffset(BasePtr, Base, Offset)) {
424     if (Offset % 4 == 0) {
425       // We've managed to infer better alignment information than the load
426       // already has. Use an aligned load.
427       //
428       return DAG.getLoad(getPointerTy(), DL, Chain, BasePtr,
429                          MachinePointerInfo(),
430                          false, false, false, 0);
431     }
432     // Lower to
433     // ldw low, base[offset >> 2]
434     // ldw high, base[(offset >> 2) + 1]
435     // shr low_shifted, low, (offset & 0x3) * 8
436     // shl high_shifted, high, 32 - (offset & 0x3) * 8
437     // or result, low_shifted, high_shifted
438     SDValue LowOffset = DAG.getConstant(Offset & ~0x3, MVT::i32);
439     SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, MVT::i32);
440     SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, MVT::i32);
441     SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, MVT::i32);
442 
443     SDValue LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, LowOffset);
444     SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, HighOffset);
445 
446     SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain,
447                               LowAddr, MachinePointerInfo(),
448                               false, false, false, 0);
449     SDValue High = DAG.getLoad(getPointerTy(), DL, Chain,
450                                HighAddr, MachinePointerInfo(),
451                                false, false, false, 0);
452     SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
453     SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
454     SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted);
455     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
456                              High.getValue(1));
457     SDValue Ops[] = { Result, Chain };
458     return DAG.getMergeValues(Ops, 2, DL);
459   }
460 
461   if (LD->getAlignment() == 2) {
462     SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain,
463                                  BasePtr, LD->getPointerInfo(), MVT::i16,
464                                  LD->isVolatile(), LD->isNonTemporal(), 2);
465     SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
466                                    DAG.getConstant(2, MVT::i32));
467     SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
468                                   HighAddr,
469                                   LD->getPointerInfo().getWithOffset(2),
470                                   MVT::i16, LD->isVolatile(),
471                                   LD->isNonTemporal(), 2);
472     SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
473                                       DAG.getConstant(16, MVT::i32));
474     SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
475     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
476                              High.getValue(1));
477     SDValue Ops[] = { Result, Chain };
478     return DAG.getMergeValues(Ops, 2, DL);
479   }
480 
481   // Lower to a call to __misaligned_load(BasePtr).
482   Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
483   TargetLowering::ArgListTy Args;
484   TargetLowering::ArgListEntry Entry;
485 
486   Entry.Ty = IntPtrTy;
487   Entry.Node = BasePtr;
488   Args.push_back(Entry);
489 
490   std::pair<SDValue, SDValue> CallResult =
491         LowerCallTo(Chain, IntPtrTy, false, false,
492                     false, false, 0, CallingConv::C, false,
493                     /*isReturnValueUsed=*/true,
494                     DAG.getExternalSymbol("__misaligned_load", getPointerTy()),
495                     Args, DAG, DL);
496 
497   SDValue Ops[] =
498     { CallResult.first, CallResult.second };
499 
500   return DAG.getMergeValues(Ops, 2, DL);
501 }
502 
503 SDValue XCoreTargetLowering::
504 LowerSTORE(SDValue Op, SelectionDAG &DAG) const
505 {
506   StoreSDNode *ST = cast<StoreSDNode>(Op);
507   assert(!ST->isTruncatingStore() && "Unexpected store type");
508   assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
509   if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
510     return SDValue();
511   }
512   unsigned ABIAlignment = getTargetData()->
513     getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
514   // Leave aligned store alone.
515   if (ST->getAlignment() >= ABIAlignment) {
516     return SDValue();
517   }
518   SDValue Chain = ST->getChain();
519   SDValue BasePtr = ST->getBasePtr();
520   SDValue Value = ST->getValue();
521   DebugLoc dl = Op.getDebugLoc();
522 
523   if (ST->getAlignment() == 2) {
524     SDValue Low = Value;
525     SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
526                                       DAG.getConstant(16, MVT::i32));
527     SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
528                                          ST->getPointerInfo(), MVT::i16,
529                                          ST->isVolatile(), ST->isNonTemporal(),
530                                          2);
531     SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
532                                    DAG.getConstant(2, MVT::i32));
533     SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
534                                           ST->getPointerInfo().getWithOffset(2),
535                                           MVT::i16, ST->isVolatile(),
536                                           ST->isNonTemporal(), 2);
537     return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
538   }
539 
540   // Lower to a call to __misaligned_store(BasePtr, Value).
541   Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
542   TargetLowering::ArgListTy Args;
543   TargetLowering::ArgListEntry Entry;
544 
545   Entry.Ty = IntPtrTy;
546   Entry.Node = BasePtr;
547   Args.push_back(Entry);
548 
549   Entry.Node = Value;
550   Args.push_back(Entry);
551 
552   std::pair<SDValue, SDValue> CallResult =
553         LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), false, false,
554                     false, false, 0, CallingConv::C, false,
555                     /*isReturnValueUsed=*/true,
556                     DAG.getExternalSymbol("__misaligned_store", getPointerTy()),
557                     Args, DAG, dl);
558 
559   return CallResult.second;
560 }
561 
562 SDValue XCoreTargetLowering::
563 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
564 {
565   assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
566          "Unexpected operand to lower!");
567   DebugLoc dl = Op.getDebugLoc();
568   SDValue LHS = Op.getOperand(0);
569   SDValue RHS = Op.getOperand(1);
570   SDValue Zero = DAG.getConstant(0, MVT::i32);
571   SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
572                            DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
573                            LHS, RHS);
574   SDValue Lo(Hi.getNode(), 1);
575   SDValue Ops[] = { Lo, Hi };
576   return DAG.getMergeValues(Ops, 2, dl);
577 }
578 
579 SDValue XCoreTargetLowering::
580 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
581 {
582   assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
583          "Unexpected operand to lower!");
584   DebugLoc dl = Op.getDebugLoc();
585   SDValue LHS = Op.getOperand(0);
586   SDValue RHS = Op.getOperand(1);
587   SDValue Zero = DAG.getConstant(0, MVT::i32);
588   SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
589                            DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
590                            Zero, Zero);
591   SDValue Lo(Hi.getNode(), 1);
592   SDValue Ops[] = { Lo, Hi };
593   return DAG.getMergeValues(Ops, 2, dl);
594 }
595 
596 /// isADDADDMUL - Return whether Op is in a form that is equivalent to
597 /// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then
598 /// each intermediate result in the calculation must also have a single use.
599 /// If the Op is in the correct form the constituent parts are written to Mul0,
600 /// Mul1, Addend0 and Addend1.
601 static bool
602 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0,
603             SDValue &Addend1, bool requireIntermediatesHaveOneUse)
604 {
605   if (Op.getOpcode() != ISD::ADD)
606     return false;
607   SDValue N0 = Op.getOperand(0);
608   SDValue N1 = Op.getOperand(1);
609   SDValue AddOp;
610   SDValue OtherOp;
611   if (N0.getOpcode() == ISD::ADD) {
612     AddOp = N0;
613     OtherOp = N1;
614   } else if (N1.getOpcode() == ISD::ADD) {
615     AddOp = N1;
616     OtherOp = N0;
617   } else {
618     return false;
619   }
620   if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse())
621     return false;
622   if (OtherOp.getOpcode() == ISD::MUL) {
623     // add(add(a,b),mul(x,y))
624     if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse())
625       return false;
626     Mul0 = OtherOp.getOperand(0);
627     Mul1 = OtherOp.getOperand(1);
628     Addend0 = AddOp.getOperand(0);
629     Addend1 = AddOp.getOperand(1);
630     return true;
631   }
632   if (AddOp.getOperand(0).getOpcode() == ISD::MUL) {
633     // add(add(mul(x,y),a),b)
634     if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse())
635       return false;
636     Mul0 = AddOp.getOperand(0).getOperand(0);
637     Mul1 = AddOp.getOperand(0).getOperand(1);
638     Addend0 = AddOp.getOperand(1);
639     Addend1 = OtherOp;
640     return true;
641   }
642   if (AddOp.getOperand(1).getOpcode() == ISD::MUL) {
643     // add(add(a,mul(x,y)),b)
644     if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse())
645       return false;
646     Mul0 = AddOp.getOperand(1).getOperand(0);
647     Mul1 = AddOp.getOperand(1).getOperand(1);
648     Addend0 = AddOp.getOperand(0);
649     Addend1 = OtherOp;
650     return true;
651   }
652   return false;
653 }
654 
655 SDValue XCoreTargetLowering::
656 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
657 {
658   SDValue Mul;
659   SDValue Other;
660   if (N->getOperand(0).getOpcode() == ISD::MUL) {
661     Mul = N->getOperand(0);
662     Other = N->getOperand(1);
663   } else if (N->getOperand(1).getOpcode() == ISD::MUL) {
664     Mul = N->getOperand(1);
665     Other = N->getOperand(0);
666   } else {
667     return SDValue();
668   }
669   DebugLoc dl = N->getDebugLoc();
670   SDValue LL, RL, AddendL, AddendH;
671   LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
672                    Mul.getOperand(0),  DAG.getConstant(0, MVT::i32));
673   RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
674                    Mul.getOperand(1),  DAG.getConstant(0, MVT::i32));
675   AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
676                         Other,  DAG.getConstant(0, MVT::i32));
677   AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
678                         Other,  DAG.getConstant(1, MVT::i32));
679   APInt HighMask = APInt::getHighBitsSet(64, 32);
680   unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
681   unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
682   if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) &&
683       DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) {
684     // The inputs are both zero-extended.
685     SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
686                              DAG.getVTList(MVT::i32, MVT::i32), AddendH,
687                              AddendL, LL, RL);
688     SDValue Lo(Hi.getNode(), 1);
689     return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
690   }
691   if (LHSSB > 32 && RHSSB > 32) {
692     // The inputs are both sign-extended.
693     SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
694                              DAG.getVTList(MVT::i32, MVT::i32), AddendH,
695                              AddendL, LL, RL);
696     SDValue Lo(Hi.getNode(), 1);
697     return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
698   }
699   SDValue LH, RH;
700   LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
701                    Mul.getOperand(0),  DAG.getConstant(1, MVT::i32));
702   RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
703                    Mul.getOperand(1),  DAG.getConstant(1, MVT::i32));
704   SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
705                            DAG.getVTList(MVT::i32, MVT::i32), AddendH,
706                            AddendL, LL, RL);
707   SDValue Lo(Hi.getNode(), 1);
708   RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
709   LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
710   Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
711   Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH);
712   return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
713 }
714 
715 SDValue XCoreTargetLowering::
716 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
717 {
718   assert(N->getValueType(0) == MVT::i64 &&
719          (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
720         "Unknown operand to lower!");
721 
722   if (N->getOpcode() == ISD::ADD) {
723     SDValue Result = TryExpandADDWithMul(N, DAG);
724     if (Result.getNode() != 0)
725       return Result;
726   }
727 
728   DebugLoc dl = N->getDebugLoc();
729 
730   // Extract components
731   SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
732                             N->getOperand(0),  DAG.getConstant(0, MVT::i32));
733   SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
734                             N->getOperand(0),  DAG.getConstant(1, MVT::i32));
735   SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
736                              N->getOperand(1), DAG.getConstant(0, MVT::i32));
737   SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
738                              N->getOperand(1), DAG.getConstant(1, MVT::i32));
739 
740   // Expand
741   unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
742                                                    XCoreISD::LSUB;
743   SDValue Zero = DAG.getConstant(0, MVT::i32);
744   SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
745                                   LHSL, RHSL, Zero);
746   SDValue Lo(Carry.getNode(), 1);
747 
748   SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
749                                   LHSH, RHSH, Carry);
750   SDValue Hi(Ignored.getNode(), 1);
751   // Merge the pieces
752   return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
753 }
754 
755 SDValue XCoreTargetLowering::
756 LowerVAARG(SDValue Op, SelectionDAG &DAG) const
757 {
758   llvm_unreachable("unimplemented");
759   // FIX Arguments passed by reference need a extra dereference.
760   SDNode *Node = Op.getNode();
761   DebugLoc dl = Node->getDebugLoc();
762   const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
763   EVT VT = Node->getValueType(0);
764   SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0),
765                                Node->getOperand(1), MachinePointerInfo(V),
766                                false, false, false, 0);
767   // Increment the pointer, VAList, to the next vararg
768   SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList,
769                      DAG.getConstant(VT.getSizeInBits(),
770                                      getPointerTy()));
771   // Store the incremented VAList to the legalized pointer
772   Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1),
773                       MachinePointerInfo(V), false, false, 0);
774   // Load the actual argument out of the pointer VAList
775   return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
776                      false, false, false, 0);
777 }
778 
779 SDValue XCoreTargetLowering::
780 LowerVASTART(SDValue Op, SelectionDAG &DAG) const
781 {
782   DebugLoc dl = Op.getDebugLoc();
783   // vastart stores the address of the VarArgsFrameIndex slot into the
784   // memory location argument
785   MachineFunction &MF = DAG.getMachineFunction();
786   XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
787   SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
788   return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1),
789                       MachinePointerInfo(), false, false, 0);
790 }
791 
792 SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
793                                             SelectionDAG &DAG) const {
794   DebugLoc dl = Op.getDebugLoc();
795   // Depths > 0 not supported yet!
796   if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
797     return SDValue();
798 
799   MachineFunction &MF = DAG.getMachineFunction();
800   const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo();
801   return DAG.getCopyFromReg(DAG.getEntryNode(), dl,
802                             RegInfo->getFrameRegister(MF), MVT::i32);
803 }
804 
805 SDValue XCoreTargetLowering::
806 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
807   return Op.getOperand(0);
808 }
809 
810 SDValue XCoreTargetLowering::
811 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
812   SDValue Chain = Op.getOperand(0);
813   SDValue Trmp = Op.getOperand(1); // trampoline
814   SDValue FPtr = Op.getOperand(2); // nested function
815   SDValue Nest = Op.getOperand(3); // 'nest' parameter value
816 
817   const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
818 
819   // .align 4
820   // LDAPF_u10 r11, nest
821   // LDW_2rus r11, r11[0]
822   // STWSP_ru6 r11, sp[0]
823   // LDAPF_u10 r11, fptr
824   // LDW_2rus r11, r11[0]
825   // BAU_1r r11
826   // nest:
827   // .word nest
828   // fptr:
829   // .word fptr
830   SDValue OutChains[5];
831 
832   SDValue Addr = Trmp;
833 
834   DebugLoc dl = Op.getDebugLoc();
835   OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32),
836                               Addr, MachinePointerInfo(TrmpAddr), false, false,
837                               0);
838 
839   Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
840                      DAG.getConstant(4, MVT::i32));
841   OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32),
842                               Addr, MachinePointerInfo(TrmpAddr, 4), false,
843                               false, 0);
844 
845   Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
846                      DAG.getConstant(8, MVT::i32));
847   OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32),
848                               Addr, MachinePointerInfo(TrmpAddr, 8), false,
849                               false, 0);
850 
851   Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
852                      DAG.getConstant(12, MVT::i32));
853   OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,
854                               MachinePointerInfo(TrmpAddr, 12), false, false,
855                               0);
856 
857   Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
858                      DAG.getConstant(16, MVT::i32));
859   OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,
860                               MachinePointerInfo(TrmpAddr, 16), false, false,
861                               0);
862 
863   return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5);
864 }
865 
866 //===----------------------------------------------------------------------===//
867 //                      Calling Convention Implementation
868 //===----------------------------------------------------------------------===//
869 
870 #include "XCoreGenCallingConv.inc"
871 
872 //===----------------------------------------------------------------------===//
873 //                  Call Calling Convention Implementation
874 //===----------------------------------------------------------------------===//
875 
876 /// XCore call implementation
877 SDValue
878 XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
879                                CallingConv::ID CallConv, bool isVarArg,
880                                bool &isTailCall,
881                                const SmallVectorImpl<ISD::OutputArg> &Outs,
882                                const SmallVectorImpl<SDValue> &OutVals,
883                                const SmallVectorImpl<ISD::InputArg> &Ins,
884                                DebugLoc dl, SelectionDAG &DAG,
885                                SmallVectorImpl<SDValue> &InVals) const {
886   // XCore target does not yet support tail call optimization.
887   isTailCall = false;
888 
889   // For now, only CallingConv::C implemented
890   switch (CallConv)
891   {
892     default:
893       llvm_unreachable("Unsupported calling convention");
894     case CallingConv::Fast:
895     case CallingConv::C:
896       return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
897                             Outs, OutVals, Ins, dl, DAG, InVals);
898   }
899 }
900 
901 /// LowerCCCCallTo - functions arguments are copied from virtual
902 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
903 /// CALLSEQ_END are emitted.
904 /// TODO: isTailCall, sret.
905 SDValue
906 XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
907                                     CallingConv::ID CallConv, bool isVarArg,
908                                     bool isTailCall,
909                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
910                                     const SmallVectorImpl<SDValue> &OutVals,
911                                     const SmallVectorImpl<ISD::InputArg> &Ins,
912                                     DebugLoc dl, SelectionDAG &DAG,
913                                     SmallVectorImpl<SDValue> &InVals) const {
914 
915   // Analyze operands of the call, assigning locations to each operand.
916   SmallVector<CCValAssign, 16> ArgLocs;
917   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
918 		 getTargetMachine(), ArgLocs, *DAG.getContext());
919 
920   // The ABI dictates there should be one stack slot available to the callee
921   // on function entry (for saving lr).
922   CCInfo.AllocateStack(4, 4);
923 
924   CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
925 
926   // Get a count of how many bytes are to be pushed on the stack.
927   unsigned NumBytes = CCInfo.getNextStackOffset();
928 
929   Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
930                                  getPointerTy(), true));
931 
932   SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
933   SmallVector<SDValue, 12> MemOpChains;
934 
935   // Walk the register/memloc assignments, inserting copies/loads.
936   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
937     CCValAssign &VA = ArgLocs[i];
938     SDValue Arg = OutVals[i];
939 
940     // Promote the value if needed.
941     switch (VA.getLocInfo()) {
942       default: llvm_unreachable("Unknown loc info!");
943       case CCValAssign::Full: break;
944       case CCValAssign::SExt:
945         Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
946         break;
947       case CCValAssign::ZExt:
948         Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
949         break;
950       case CCValAssign::AExt:
951         Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
952         break;
953     }
954 
955     // Arguments that can be passed on register must be kept at
956     // RegsToPass vector
957     if (VA.isRegLoc()) {
958       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
959     } else {
960       assert(VA.isMemLoc());
961 
962       int Offset = VA.getLocMemOffset();
963 
964       MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
965                                         Chain, Arg,
966                                         DAG.getConstant(Offset/4, MVT::i32)));
967     }
968   }
969 
970   // Transform all store nodes into one single node because
971   // all store nodes are independent of each other.
972   if (!MemOpChains.empty())
973     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
974                         &MemOpChains[0], MemOpChains.size());
975 
976   // Build a sequence of copy-to-reg nodes chained together with token
977   // chain and flag operands which copy the outgoing args into registers.
978   // The InFlag in necessary since all emitted instructions must be
979   // stuck together.
980   SDValue InFlag;
981   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
982     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
983                              RegsToPass[i].second, InFlag);
984     InFlag = Chain.getValue(1);
985   }
986 
987   // If the callee is a GlobalAddress node (quite common, every direct call is)
988   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
989   // Likewise ExternalSymbol -> TargetExternalSymbol.
990   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
991     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
992   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
993     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
994 
995   // XCoreBranchLink = #chain, #target_address, #opt_in_flags...
996   //             = Chain, Callee, Reg#1, Reg#2, ...
997   //
998   // Returns a chain & a flag for retval copy to use.
999   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1000   SmallVector<SDValue, 8> Ops;
1001   Ops.push_back(Chain);
1002   Ops.push_back(Callee);
1003 
1004   // Add argument registers to the end of the list so that they are
1005   // known live into the call.
1006   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1007     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1008                                   RegsToPass[i].second.getValueType()));
1009 
1010   if (InFlag.getNode())
1011     Ops.push_back(InFlag);
1012 
1013   Chain  = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size());
1014   InFlag = Chain.getValue(1);
1015 
1016   // Create the CALLSEQ_END node.
1017   Chain = DAG.getCALLSEQ_END(Chain,
1018                              DAG.getConstant(NumBytes, getPointerTy(), true),
1019                              DAG.getConstant(0, getPointerTy(), true),
1020                              InFlag);
1021   InFlag = Chain.getValue(1);
1022 
1023   // Handle result values, copying them out of physregs into vregs that we
1024   // return.
1025   return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1026                          Ins, dl, DAG, InVals);
1027 }
1028 
1029 /// LowerCallResult - Lower the result values of a call into the
1030 /// appropriate copies out of appropriate physical registers.
1031 SDValue
1032 XCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1033                                      CallingConv::ID CallConv, bool isVarArg,
1034                                      const SmallVectorImpl<ISD::InputArg> &Ins,
1035                                      DebugLoc dl, SelectionDAG &DAG,
1036                                      SmallVectorImpl<SDValue> &InVals) const {
1037 
1038   // Assign locations to each value returned by this call.
1039   SmallVector<CCValAssign, 16> RVLocs;
1040   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1041 		 getTargetMachine(), RVLocs, *DAG.getContext());
1042 
1043   CCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1044 
1045   // Copy all of the result registers out of their specified physreg.
1046   for (unsigned i = 0; i != RVLocs.size(); ++i) {
1047     Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1048                                  RVLocs[i].getValVT(), InFlag).getValue(1);
1049     InFlag = Chain.getValue(2);
1050     InVals.push_back(Chain.getValue(0));
1051   }
1052 
1053   return Chain;
1054 }
1055 
1056 //===----------------------------------------------------------------------===//
1057 //             Formal Arguments Calling Convention Implementation
1058 //===----------------------------------------------------------------------===//
1059 
1060 /// XCore formal arguments implementation
1061 SDValue
1062 XCoreTargetLowering::LowerFormalArguments(SDValue Chain,
1063                                           CallingConv::ID CallConv,
1064                                           bool isVarArg,
1065                                       const SmallVectorImpl<ISD::InputArg> &Ins,
1066                                           DebugLoc dl,
1067                                           SelectionDAG &DAG,
1068                                           SmallVectorImpl<SDValue> &InVals)
1069                                             const {
1070   switch (CallConv)
1071   {
1072     default:
1073       llvm_unreachable("Unsupported calling convention");
1074     case CallingConv::C:
1075     case CallingConv::Fast:
1076       return LowerCCCArguments(Chain, CallConv, isVarArg,
1077                                Ins, dl, DAG, InVals);
1078   }
1079 }
1080 
1081 /// LowerCCCArguments - transform physical registers into
1082 /// virtual registers and generate load operations for
1083 /// arguments places on the stack.
1084 /// TODO: sret
1085 SDValue
1086 XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
1087                                        CallingConv::ID CallConv,
1088                                        bool isVarArg,
1089                                        const SmallVectorImpl<ISD::InputArg>
1090                                          &Ins,
1091                                        DebugLoc dl,
1092                                        SelectionDAG &DAG,
1093                                        SmallVectorImpl<SDValue> &InVals) const {
1094   MachineFunction &MF = DAG.getMachineFunction();
1095   MachineFrameInfo *MFI = MF.getFrameInfo();
1096   MachineRegisterInfo &RegInfo = MF.getRegInfo();
1097 
1098   // Assign locations to all of the incoming arguments.
1099   SmallVector<CCValAssign, 16> ArgLocs;
1100   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1101 		 getTargetMachine(), ArgLocs, *DAG.getContext());
1102 
1103   CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1104 
1105   unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize();
1106 
1107   unsigned LRSaveSize = StackSlotSize;
1108 
1109   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1110 
1111     CCValAssign &VA = ArgLocs[i];
1112 
1113     if (VA.isRegLoc()) {
1114       // Arguments passed in registers
1115       EVT RegVT = VA.getLocVT();
1116       switch (RegVT.getSimpleVT().SimpleTy) {
1117       default:
1118         {
1119 #ifndef NDEBUG
1120           errs() << "LowerFormalArguments Unhandled argument type: "
1121                  << RegVT.getSimpleVT().SimpleTy << "\n";
1122 #endif
1123           llvm_unreachable(0);
1124         }
1125       case MVT::i32:
1126         unsigned VReg = RegInfo.createVirtualRegister(
1127                           XCore::GRRegsRegisterClass);
1128         RegInfo.addLiveIn(VA.getLocReg(), VReg);
1129         InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1130       }
1131     } else {
1132       // sanity check
1133       assert(VA.isMemLoc());
1134       // Load the argument to a virtual register
1135       unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
1136       if (ObjSize > StackSlotSize) {
1137         errs() << "LowerFormalArguments Unhandled argument type: "
1138                << EVT(VA.getLocVT()).getEVTString()
1139                << "\n";
1140       }
1141       // Create the frame index object for this incoming parameter...
1142       int FI = MFI->CreateFixedObject(ObjSize,
1143                                       LRSaveSize + VA.getLocMemOffset(),
1144                                       true);
1145 
1146       // Create the SelectionDAG nodes corresponding to a load
1147       //from this parameter
1148       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1149       InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1150                                    MachinePointerInfo::getFixedStack(FI),
1151                                    false, false, false, 0));
1152     }
1153   }
1154 
1155   if (isVarArg) {
1156     /* Argument registers */
1157     static const unsigned ArgRegs[] = {
1158       XCore::R0, XCore::R1, XCore::R2, XCore::R3
1159     };
1160     XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1161     unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs,
1162                                                      array_lengthof(ArgRegs));
1163     if (FirstVAReg < array_lengthof(ArgRegs)) {
1164       SmallVector<SDValue, 4> MemOps;
1165       int offset = 0;
1166       // Save remaining registers, storing higher register numbers at a higher
1167       // address
1168       for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
1169         // Create a stack slot
1170         int FI = MFI->CreateFixedObject(4, offset, true);
1171         if (i == (int)FirstVAReg) {
1172           XFI->setVarArgsFrameIndex(FI);
1173         }
1174         offset -= StackSlotSize;
1175         SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1176         // Move argument from phys reg -> virt reg
1177         unsigned VReg = RegInfo.createVirtualRegister(
1178                           XCore::GRRegsRegisterClass);
1179         RegInfo.addLiveIn(ArgRegs[i], VReg);
1180         SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1181         // Move argument from virt reg -> stack
1182         SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1183                                      MachinePointerInfo(), false, false, 0);
1184         MemOps.push_back(Store);
1185       }
1186       if (!MemOps.empty())
1187         Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1188                             &MemOps[0], MemOps.size());
1189     } else {
1190       // This will point to the next argument passed via stack.
1191       XFI->setVarArgsFrameIndex(
1192         MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(),
1193                                true));
1194     }
1195   }
1196 
1197   return Chain;
1198 }
1199 
1200 //===----------------------------------------------------------------------===//
1201 //               Return Value Calling Convention Implementation
1202 //===----------------------------------------------------------------------===//
1203 
1204 bool XCoreTargetLowering::
1205 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1206 	       bool isVarArg,
1207                const SmallVectorImpl<ISD::OutputArg> &Outs,
1208                LLVMContext &Context) const {
1209   SmallVector<CCValAssign, 16> RVLocs;
1210   CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
1211   return CCInfo.CheckReturn(Outs, RetCC_XCore);
1212 }
1213 
1214 SDValue
1215 XCoreTargetLowering::LowerReturn(SDValue Chain,
1216                                  CallingConv::ID CallConv, bool isVarArg,
1217                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
1218                                  const SmallVectorImpl<SDValue> &OutVals,
1219                                  DebugLoc dl, SelectionDAG &DAG) const {
1220 
1221   // CCValAssign - represent the assignment of
1222   // the return value to a location
1223   SmallVector<CCValAssign, 16> RVLocs;
1224 
1225   // CCState - Info about the registers and stack slot.
1226   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1227 		 getTargetMachine(), RVLocs, *DAG.getContext());
1228 
1229   // Analyze return values.
1230   CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
1231 
1232   // If this is the first return lowered for this function, add
1233   // the regs to the liveout set for the function.
1234   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1235     for (unsigned i = 0; i != RVLocs.size(); ++i)
1236       if (RVLocs[i].isRegLoc())
1237         DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1238   }
1239 
1240   SDValue Flag;
1241 
1242   // Copy the result values into the output registers.
1243   for (unsigned i = 0; i != RVLocs.size(); ++i) {
1244     CCValAssign &VA = RVLocs[i];
1245     assert(VA.isRegLoc() && "Can only return in registers!");
1246 
1247     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1248                              OutVals[i], Flag);
1249 
1250     // guarantee that all emitted copies are
1251     // stuck together, avoiding something bad
1252     Flag = Chain.getValue(1);
1253   }
1254 
1255   // Return on XCore is always a "retsp 0"
1256   if (Flag.getNode())
1257     return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
1258                        Chain, DAG.getConstant(0, MVT::i32), Flag);
1259   else // Return Void
1260     return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
1261                        Chain, DAG.getConstant(0, MVT::i32));
1262 }
1263 
1264 //===----------------------------------------------------------------------===//
1265 //  Other Lowering Code
1266 //===----------------------------------------------------------------------===//
1267 
1268 MachineBasicBlock *
1269 XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1270                                                  MachineBasicBlock *BB) const {
1271   const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1272   DebugLoc dl = MI->getDebugLoc();
1273   assert((MI->getOpcode() == XCore::SELECT_CC) &&
1274          "Unexpected instr type to insert");
1275 
1276   // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1277   // control-flow pattern.  The incoming instruction knows the destination vreg
1278   // to set, the condition code register to branch on, the true/false values to
1279   // select between, and a branch opcode to use.
1280   const BasicBlock *LLVM_BB = BB->getBasicBlock();
1281   MachineFunction::iterator It = BB;
1282   ++It;
1283 
1284   //  thisMBB:
1285   //  ...
1286   //   TrueVal = ...
1287   //   cmpTY ccX, r1, r2
1288   //   bCC copy1MBB
1289   //   fallthrough --> copy0MBB
1290   MachineBasicBlock *thisMBB = BB;
1291   MachineFunction *F = BB->getParent();
1292   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1293   MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1294   F->insert(It, copy0MBB);
1295   F->insert(It, sinkMBB);
1296 
1297   // Transfer the remainder of BB and its successor edges to sinkMBB.
1298   sinkMBB->splice(sinkMBB->begin(), BB,
1299                   llvm::next(MachineBasicBlock::iterator(MI)),
1300                   BB->end());
1301   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1302 
1303   // Next, add the true and fallthrough blocks as its successors.
1304   BB->addSuccessor(copy0MBB);
1305   BB->addSuccessor(sinkMBB);
1306 
1307   BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
1308     .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
1309 
1310   //  copy0MBB:
1311   //   %FalseValue = ...
1312   //   # fallthrough to sinkMBB
1313   BB = copy0MBB;
1314 
1315   // Update machine-CFG edges
1316   BB->addSuccessor(sinkMBB);
1317 
1318   //  sinkMBB:
1319   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1320   //  ...
1321   BB = sinkMBB;
1322   BuildMI(*BB, BB->begin(), dl,
1323           TII.get(XCore::PHI), MI->getOperand(0).getReg())
1324     .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
1325     .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1326 
1327   MI->eraseFromParent();   // The pseudo instruction is gone now.
1328   return BB;
1329 }
1330 
1331 //===----------------------------------------------------------------------===//
1332 // Target Optimization Hooks
1333 //===----------------------------------------------------------------------===//
1334 
1335 SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
1336                                              DAGCombinerInfo &DCI) const {
1337   SelectionDAG &DAG = DCI.DAG;
1338   DebugLoc dl = N->getDebugLoc();
1339   switch (N->getOpcode()) {
1340   default: break;
1341   case XCoreISD::LADD: {
1342     SDValue N0 = N->getOperand(0);
1343     SDValue N1 = N->getOperand(1);
1344     SDValue N2 = N->getOperand(2);
1345     ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1346     ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1347     EVT VT = N0.getValueType();
1348 
1349     // canonicalize constant to RHS
1350     if (N0C && !N1C)
1351       return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1352 
1353     // fold (ladd 0, 0, x) -> 0, x & 1
1354     if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1355       SDValue Carry = DAG.getConstant(0, VT);
1356       SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
1357                                    DAG.getConstant(1, VT));
1358       SDValue Ops [] = { Carry, Result };
1359       return DAG.getMergeValues(Ops, 2, dl);
1360     }
1361 
1362     // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the
1363     // low bit set
1364     if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) {
1365       APInt KnownZero, KnownOne;
1366       APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1367                                          VT.getSizeInBits() - 1);
1368       DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne);
1369       if (KnownZero == Mask) {
1370         SDValue Carry = DAG.getConstant(0, VT);
1371         SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1372         SDValue Ops [] = { Carry, Result };
1373         return DAG.getMergeValues(Ops, 2, dl);
1374       }
1375     }
1376   }
1377   break;
1378   case XCoreISD::LSUB: {
1379     SDValue N0 = N->getOperand(0);
1380     SDValue N1 = N->getOperand(1);
1381     SDValue N2 = N->getOperand(2);
1382     ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1383     ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1384     EVT VT = N0.getValueType();
1385 
1386     // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set
1387     if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1388       APInt KnownZero, KnownOne;
1389       APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1390                                          VT.getSizeInBits() - 1);
1391       DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne);
1392       if (KnownZero == Mask) {
1393         SDValue Borrow = N2;
1394         SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
1395                                      DAG.getConstant(0, VT), N2);
1396         SDValue Ops [] = { Borrow, Result };
1397         return DAG.getMergeValues(Ops, 2, dl);
1398       }
1399     }
1400 
1401     // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the
1402     // low bit set
1403     if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) {
1404       APInt KnownZero, KnownOne;
1405       APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1406                                          VT.getSizeInBits() - 1);
1407       DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne);
1408       if (KnownZero == Mask) {
1409         SDValue Borrow = DAG.getConstant(0, VT);
1410         SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
1411         SDValue Ops [] = { Borrow, Result };
1412         return DAG.getMergeValues(Ops, 2, dl);
1413       }
1414     }
1415   }
1416   break;
1417   case XCoreISD::LMUL: {
1418     SDValue N0 = N->getOperand(0);
1419     SDValue N1 = N->getOperand(1);
1420     SDValue N2 = N->getOperand(2);
1421     SDValue N3 = N->getOperand(3);
1422     ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1423     ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1424     EVT VT = N0.getValueType();
1425     // Canonicalize multiplicative constant to RHS. If both multiplicative
1426     // operands are constant canonicalize smallest to RHS.
1427     if ((N0C && !N1C) ||
1428         (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue()))
1429       return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT),
1430                          N1, N0, N2, N3);
1431 
1432     // lmul(x, 0, a, b)
1433     if (N1C && N1C->isNullValue()) {
1434       // If the high result is unused fold to add(a, b)
1435       if (N->hasNUsesOfValue(0, 0)) {
1436         SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
1437         SDValue Ops [] = { Lo, Lo };
1438         return DAG.getMergeValues(Ops, 2, dl);
1439       }
1440       // Otherwise fold to ladd(a, b, 0)
1441       return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
1442     }
1443   }
1444   break;
1445   case ISD::ADD: {
1446     // Fold 32 bit expressions such as add(add(mul(x,y),a),b) ->
1447     // lmul(x, y, a, b). The high result of lmul will be ignored.
1448     // This is only profitable if the intermediate results are unused
1449     // elsewhere.
1450     SDValue Mul0, Mul1, Addend0, Addend1;
1451     if (N->getValueType(0) == MVT::i32 &&
1452         isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) {
1453       SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
1454                                     DAG.getVTList(MVT::i32, MVT::i32), Mul0,
1455                                     Mul1, Addend0, Addend1);
1456       SDValue Result(Ignored.getNode(), 1);
1457       return Result;
1458     }
1459     APInt HighMask = APInt::getHighBitsSet(64, 32);
1460     // Fold 64 bit expression such as add(add(mul(x,y),a),b) ->
1461     // lmul(x, y, a, b) if all operands are zero-extended. We do this
1462     // before type legalization as it is messy to match the operands after
1463     // that.
1464     if (N->getValueType(0) == MVT::i64 &&
1465         isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) &&
1466         DAG.MaskedValueIsZero(Mul0, HighMask) &&
1467         DAG.MaskedValueIsZero(Mul1, HighMask) &&
1468         DAG.MaskedValueIsZero(Addend0, HighMask) &&
1469         DAG.MaskedValueIsZero(Addend1, HighMask)) {
1470       SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1471                                   Mul0, DAG.getConstant(0, MVT::i32));
1472       SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1473                                   Mul1, DAG.getConstant(0, MVT::i32));
1474       SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1475                                      Addend0, DAG.getConstant(0, MVT::i32));
1476       SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1477                                      Addend1, DAG.getConstant(0, MVT::i32));
1478       SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
1479                                DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
1480                                Addend0L, Addend1L);
1481       SDValue Lo(Hi.getNode(), 1);
1482       return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1483     }
1484   }
1485   break;
1486   case ISD::STORE: {
1487     // Replace unaligned store of unaligned load with memmove.
1488     StoreSDNode *ST  = cast<StoreSDNode>(N);
1489     if (!DCI.isBeforeLegalize() ||
1490         allowsUnalignedMemoryAccesses(ST->getMemoryVT()) ||
1491         ST->isVolatile() || ST->isIndexed()) {
1492       break;
1493     }
1494     SDValue Chain = ST->getChain();
1495 
1496     unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits();
1497     if (StoreBits % 8) {
1498       break;
1499     }
1500     unsigned ABIAlignment = getTargetData()->getABITypeAlignment(
1501         ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
1502     unsigned Alignment = ST->getAlignment();
1503     if (Alignment >= ABIAlignment) {
1504       break;
1505     }
1506 
1507     if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) {
1508       if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() &&
1509         LD->getAlignment() == Alignment &&
1510         !LD->isVolatile() && !LD->isIndexed() &&
1511         Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
1512         return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
1513                               LD->getBasePtr(),
1514                               DAG.getConstant(StoreBits/8, MVT::i32),
1515                               Alignment, false, ST->getPointerInfo(),
1516                               LD->getPointerInfo());
1517       }
1518     }
1519     break;
1520   }
1521   }
1522   return SDValue();
1523 }
1524 
1525 void XCoreTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1526                                                          const APInt &Mask,
1527                                                          APInt &KnownZero,
1528                                                          APInt &KnownOne,
1529                                                          const SelectionDAG &DAG,
1530                                                          unsigned Depth) const {
1531   KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1532   switch (Op.getOpcode()) {
1533   default: break;
1534   case XCoreISD::LADD:
1535   case XCoreISD::LSUB:
1536     if (Op.getResNo() == 0) {
1537       // Top bits of carry / borrow are clear.
1538       KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
1539                                         Mask.getBitWidth() - 1);
1540       KnownZero &= Mask;
1541     }
1542     break;
1543   }
1544 }
1545 
1546 //===----------------------------------------------------------------------===//
1547 //  Addressing mode description hooks
1548 //===----------------------------------------------------------------------===//
1549 
1550 static inline bool isImmUs(int64_t val)
1551 {
1552   return (val >= 0 && val <= 11);
1553 }
1554 
1555 static inline bool isImmUs2(int64_t val)
1556 {
1557   return (val%2 == 0 && isImmUs(val/2));
1558 }
1559 
1560 static inline bool isImmUs4(int64_t val)
1561 {
1562   return (val%4 == 0 && isImmUs(val/4));
1563 }
1564 
1565 /// isLegalAddressingMode - Return true if the addressing mode represented
1566 /// by AM is legal for this target, for a load/store of the specified type.
1567 bool
1568 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1569                                               Type *Ty) const {
1570   if (Ty->getTypeID() == Type::VoidTyID)
1571     return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1572 
1573   const TargetData *TD = TM.getTargetData();
1574   unsigned Size = TD->getTypeAllocSize(Ty);
1575   if (AM.BaseGV) {
1576     return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
1577                  AM.BaseOffs%4 == 0;
1578   }
1579 
1580   switch (Size) {
1581   case 1:
1582     // reg + imm
1583     if (AM.Scale == 0) {
1584       return isImmUs(AM.BaseOffs);
1585     }
1586     // reg + reg
1587     return AM.Scale == 1 && AM.BaseOffs == 0;
1588   case 2:
1589   case 3:
1590     // reg + imm
1591     if (AM.Scale == 0) {
1592       return isImmUs2(AM.BaseOffs);
1593     }
1594     // reg + reg<<1
1595     return AM.Scale == 2 && AM.BaseOffs == 0;
1596   default:
1597     // reg + imm
1598     if (AM.Scale == 0) {
1599       return isImmUs4(AM.BaseOffs);
1600     }
1601     // reg + reg<<2
1602     return AM.Scale == 4 && AM.BaseOffs == 0;
1603   }
1604 
1605   return false;
1606 }
1607 
1608 //===----------------------------------------------------------------------===//
1609 //                           XCore Inline Assembly Support
1610 //===----------------------------------------------------------------------===//
1611 
1612 std::pair<unsigned, const TargetRegisterClass*>
1613 XCoreTargetLowering::
1614 getRegForInlineAsmConstraint(const std::string &Constraint,
1615 			     EVT VT) const {
1616   if (Constraint.size() == 1) {
1617     switch (Constraint[0]) {
1618     default : break;
1619     case 'r':
1620       return std::make_pair(0U, XCore::GRRegsRegisterClass);
1621     }
1622   }
1623   // Use the default implementation in TargetLowering to convert the register
1624   // constraint into a member of a register class.
1625   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1626 }
1627