1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "x86-instr-info"
45 
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
48 
49 static cl::opt<bool>
50 NoFusing("disable-spill-fusing",
51          cl::desc("Disable fusing of spill code into instructions"));
52 static cl::opt<bool>
53 PrintFailedFusing("print-failed-fuse-candidates",
54                   cl::desc("Print instructions that the allocator wants to"
55                            " fuse, but the X86 backend currently can't"),
56                   cl::Hidden);
57 static cl::opt<bool>
58 ReMatPICStubLoad("remat-pic-stub-load",
59                  cl::desc("Re-materialize load from stub in PIC mode"),
60                  cl::init(false), cl::Hidden);
61 static cl::opt<unsigned>
62 PartialRegUpdateClearance("partial-reg-update-clearance",
63                           cl::desc("Clearance between two register writes "
64                                    "for inserting XOR to avoid partial "
65                                    "register update"),
66                           cl::init(64), cl::Hidden);
67 static cl::opt<unsigned>
68 UndefRegClearance("undef-reg-clearance",
69                   cl::desc("How many idle instructions we would like before "
70                            "certain undef register reads"),
71                   cl::init(64), cl::Hidden);
72 
73 enum {
74   // Select which memory operand is being unfolded.
75   // (stored in bits 0 - 3)
76   TB_INDEX_0    = 0,
77   TB_INDEX_1    = 1,
78   TB_INDEX_2    = 2,
79   TB_INDEX_3    = 3,
80   TB_INDEX_4    = 4,
81   TB_INDEX_MASK = 0xf,
82 
83   // Do not insert the reverse map (MemOp -> RegOp) into the table.
84   // This may be needed because there is a many -> one mapping.
85   TB_NO_REVERSE   = 1 << 4,
86 
87   // Do not insert the forward map (RegOp -> MemOp) into the table.
88   // This is needed for Native Client, which prohibits branch
89   // instructions from using a memory operand.
90   TB_NO_FORWARD   = 1 << 5,
91 
92   TB_FOLDED_LOAD  = 1 << 6,
93   TB_FOLDED_STORE = 1 << 7,
94 
95   // Minimum alignment required for load/store.
96   // Used for RegOp->MemOp conversion.
97   // (stored in bits 8 - 15)
98   TB_ALIGN_SHIFT = 8,
99   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
100   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
101   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
102   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
103   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
104 };
105 
106 struct X86MemoryFoldTableEntry {
107   uint16_t RegOp;
108   uint16_t MemOp;
109   uint16_t Flags;
110 };
111 
112 // Pin the vtable to this file.
113 void X86InstrInfo::anchor() {}
114 
115 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
116     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117                                                : X86::ADJCALLSTACKDOWN32),
118                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119                                                : X86::ADJCALLSTACKUP32),
120                       X86::CATCHRET),
121       Subtarget(STI), RI(STI.getTargetTriple()) {
122 
123   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
124     { X86::ADC32ri,     X86::ADC32mi,    0 },
125     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
126     { X86::ADC32rr,     X86::ADC32mr,    0 },
127     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
128     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
129     { X86::ADC64rr,     X86::ADC64mr,    0 },
130     { X86::ADD16ri,     X86::ADD16mi,    0 },
131     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
132     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
133     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
134     { X86::ADD16rr,     X86::ADD16mr,    0 },
135     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
136     { X86::ADD32ri,     X86::ADD32mi,    0 },
137     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
138     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
139     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
140     { X86::ADD32rr,     X86::ADD32mr,    0 },
141     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
142     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
143     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
144     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
145     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
146     { X86::ADD64rr,     X86::ADD64mr,    0 },
147     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
148     { X86::ADD8ri,      X86::ADD8mi,     0 },
149     { X86::ADD8rr,      X86::ADD8mr,     0 },
150     { X86::AND16ri,     X86::AND16mi,    0 },
151     { X86::AND16ri8,    X86::AND16mi8,   0 },
152     { X86::AND16rr,     X86::AND16mr,    0 },
153     { X86::AND32ri,     X86::AND32mi,    0 },
154     { X86::AND32ri8,    X86::AND32mi8,   0 },
155     { X86::AND32rr,     X86::AND32mr,    0 },
156     { X86::AND64ri32,   X86::AND64mi32,  0 },
157     { X86::AND64ri8,    X86::AND64mi8,   0 },
158     { X86::AND64rr,     X86::AND64mr,    0 },
159     { X86::AND8ri,      X86::AND8mi,     0 },
160     { X86::AND8rr,      X86::AND8mr,     0 },
161     { X86::DEC16r,      X86::DEC16m,     0 },
162     { X86::DEC32r,      X86::DEC32m,     0 },
163     { X86::DEC64r,      X86::DEC64m,     0 },
164     { X86::DEC8r,       X86::DEC8m,      0 },
165     { X86::INC16r,      X86::INC16m,     0 },
166     { X86::INC32r,      X86::INC32m,     0 },
167     { X86::INC64r,      X86::INC64m,     0 },
168     { X86::INC8r,       X86::INC8m,      0 },
169     { X86::NEG16r,      X86::NEG16m,     0 },
170     { X86::NEG32r,      X86::NEG32m,     0 },
171     { X86::NEG64r,      X86::NEG64m,     0 },
172     { X86::NEG8r,       X86::NEG8m,      0 },
173     { X86::NOT16r,      X86::NOT16m,     0 },
174     { X86::NOT32r,      X86::NOT32m,     0 },
175     { X86::NOT64r,      X86::NOT64m,     0 },
176     { X86::NOT8r,       X86::NOT8m,      0 },
177     { X86::OR16ri,      X86::OR16mi,     0 },
178     { X86::OR16ri8,     X86::OR16mi8,    0 },
179     { X86::OR16rr,      X86::OR16mr,     0 },
180     { X86::OR32ri,      X86::OR32mi,     0 },
181     { X86::OR32ri8,     X86::OR32mi8,    0 },
182     { X86::OR32rr,      X86::OR32mr,     0 },
183     { X86::OR64ri32,    X86::OR64mi32,   0 },
184     { X86::OR64ri8,     X86::OR64mi8,    0 },
185     { X86::OR64rr,      X86::OR64mr,     0 },
186     { X86::OR8ri,       X86::OR8mi,      0 },
187     { X86::OR8rr,       X86::OR8mr,      0 },
188     { X86::ROL16r1,     X86::ROL16m1,    0 },
189     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
190     { X86::ROL16ri,     X86::ROL16mi,    0 },
191     { X86::ROL32r1,     X86::ROL32m1,    0 },
192     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
193     { X86::ROL32ri,     X86::ROL32mi,    0 },
194     { X86::ROL64r1,     X86::ROL64m1,    0 },
195     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
196     { X86::ROL64ri,     X86::ROL64mi,    0 },
197     { X86::ROL8r1,      X86::ROL8m1,     0 },
198     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
199     { X86::ROL8ri,      X86::ROL8mi,     0 },
200     { X86::ROR16r1,     X86::ROR16m1,    0 },
201     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
202     { X86::ROR16ri,     X86::ROR16mi,    0 },
203     { X86::ROR32r1,     X86::ROR32m1,    0 },
204     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
205     { X86::ROR32ri,     X86::ROR32mi,    0 },
206     { X86::ROR64r1,     X86::ROR64m1,    0 },
207     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
208     { X86::ROR64ri,     X86::ROR64mi,    0 },
209     { X86::ROR8r1,      X86::ROR8m1,     0 },
210     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
211     { X86::ROR8ri,      X86::ROR8mi,     0 },
212     { X86::SAR16r1,     X86::SAR16m1,    0 },
213     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
214     { X86::SAR16ri,     X86::SAR16mi,    0 },
215     { X86::SAR32r1,     X86::SAR32m1,    0 },
216     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
217     { X86::SAR32ri,     X86::SAR32mi,    0 },
218     { X86::SAR64r1,     X86::SAR64m1,    0 },
219     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
220     { X86::SAR64ri,     X86::SAR64mi,    0 },
221     { X86::SAR8r1,      X86::SAR8m1,     0 },
222     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
223     { X86::SAR8ri,      X86::SAR8mi,     0 },
224     { X86::SBB32ri,     X86::SBB32mi,    0 },
225     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
226     { X86::SBB32rr,     X86::SBB32mr,    0 },
227     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
228     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
229     { X86::SBB64rr,     X86::SBB64mr,    0 },
230     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
231     { X86::SHL16ri,     X86::SHL16mi,    0 },
232     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
233     { X86::SHL32ri,     X86::SHL32mi,    0 },
234     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
235     { X86::SHL64ri,     X86::SHL64mi,    0 },
236     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
237     { X86::SHL8ri,      X86::SHL8mi,     0 },
238     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
239     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
240     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
241     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
242     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
243     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
244     { X86::SHR16r1,     X86::SHR16m1,    0 },
245     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
246     { X86::SHR16ri,     X86::SHR16mi,    0 },
247     { X86::SHR32r1,     X86::SHR32m1,    0 },
248     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
249     { X86::SHR32ri,     X86::SHR32mi,    0 },
250     { X86::SHR64r1,     X86::SHR64m1,    0 },
251     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
252     { X86::SHR64ri,     X86::SHR64mi,    0 },
253     { X86::SHR8r1,      X86::SHR8m1,     0 },
254     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
255     { X86::SHR8ri,      X86::SHR8mi,     0 },
256     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
257     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
258     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
259     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
260     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
261     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
262     { X86::SUB16ri,     X86::SUB16mi,    0 },
263     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
264     { X86::SUB16rr,     X86::SUB16mr,    0 },
265     { X86::SUB32ri,     X86::SUB32mi,    0 },
266     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
267     { X86::SUB32rr,     X86::SUB32mr,    0 },
268     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
269     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
270     { X86::SUB64rr,     X86::SUB64mr,    0 },
271     { X86::SUB8ri,      X86::SUB8mi,     0 },
272     { X86::SUB8rr,      X86::SUB8mr,     0 },
273     { X86::XOR16ri,     X86::XOR16mi,    0 },
274     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
275     { X86::XOR16rr,     X86::XOR16mr,    0 },
276     { X86::XOR32ri,     X86::XOR32mi,    0 },
277     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
278     { X86::XOR32rr,     X86::XOR32mr,    0 },
279     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
280     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
281     { X86::XOR64rr,     X86::XOR64mr,    0 },
282     { X86::XOR8ri,      X86::XOR8mi,     0 },
283     { X86::XOR8rr,      X86::XOR8mr,     0 }
284   };
285 
286   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
287     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
288                   Entry.RegOp, Entry.MemOp,
289                   // Index 0, folded load and store, no alignment requirement.
290                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
291   }
292 
293   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
294     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
295     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
296     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
297     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
298     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
299     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
300     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
301     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
302     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
303     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
304     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
305     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
306     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
307     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
308     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
309     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
310     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
311     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
312     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
313     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
314     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
315     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
316     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
317     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
318     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
319     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
320     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
321     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
322     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
323     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
324     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
325     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
326     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
327     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
328     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
329     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
330     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
331     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
332     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
333     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
334     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
335     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
336     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
337     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
338     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
339     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
340     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
341     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
342     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
343     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
344     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
345     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
346     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
347     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
348     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
349     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
350     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
351     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
352     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
353     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
354     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
355     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
356     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
357     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
358     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
359     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
360     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
361     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
362     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
363     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
364     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
365     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
366     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
367     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
368     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
369     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
370     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
371     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
372     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
373     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
374     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
375 
376     // AVX 128-bit versions of foldable instructions
377     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
378     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
379     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
380     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
381     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
382     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
383     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
384     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
385     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
386     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
387     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
388     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
389     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
390 
391     // AVX 256-bit foldable instructions
392     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
393     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
394     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
395     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
396     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
397     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
398 
399     // AVX-512 foldable instructions
400     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
401     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
402     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
403     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
404     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
405     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
406     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
407     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
408     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
409     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
410     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
411 
412     // AVX-512 foldable instructions (256-bit versions)
413     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
414     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
415     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
416     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
417     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
418     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
419     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
420     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
421     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
422     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
423 
424     // AVX-512 foldable instructions (128-bit versions)
425     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
426     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
427     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
428     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
429     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
430     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
431     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
432     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
433     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
434     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
435 
436     // F16C foldable instructions
437     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
438     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
439   };
440 
441   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
442     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
443                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
444   }
445 
446   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
447     { X86::BSF16rr,         X86::BSF16rm,             0 },
448     { X86::BSF32rr,         X86::BSF32rm,             0 },
449     { X86::BSF64rr,         X86::BSF64rm,             0 },
450     { X86::BSR16rr,         X86::BSR16rm,             0 },
451     { X86::BSR32rr,         X86::BSR32rm,             0 },
452     { X86::BSR64rr,         X86::BSR64rm,             0 },
453     { X86::CMP16rr,         X86::CMP16rm,             0 },
454     { X86::CMP32rr,         X86::CMP32rm,             0 },
455     { X86::CMP64rr,         X86::CMP64rm,             0 },
456     { X86::CMP8rr,          X86::CMP8rm,              0 },
457     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
458     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
459     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
460     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
461     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
462     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
463     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
464     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
465     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
466     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
467     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
468     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
469     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
470     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
471     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
472     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
473     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
474     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
475     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
476     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
477     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
478     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
479     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
480     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
481     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
482     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
483     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
484     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
485     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
486     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
487     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
488     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
489     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
490     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
491     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
492     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
493     { X86::MOV16rr,         X86::MOV16rm,             0 },
494     { X86::MOV32rr,         X86::MOV32rm,             0 },
495     { X86::MOV64rr,         X86::MOV64rm,             0 },
496     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
497     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
498     { X86::MOV8rr,          X86::MOV8rm,              0 },
499     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
500     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
501     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
502     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
503     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
504     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
505     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
506     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
507     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
508     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
509     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
510     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
511     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
512     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
513     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
514     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
515     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
516     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
517     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
518     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
519     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
520     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
521     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
522     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
523     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
524     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
525     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
526     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
527     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
528     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
529     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
530     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
531     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
532     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
533     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
534     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
535     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
536     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
537     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
538     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
539     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
540     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
541     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
542     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
543     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
544     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
545     { X86::RCPSSr,          X86::RCPSSm,              0 },
546     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          0 },
547     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
548     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
549     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
550     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
551     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
552     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
553     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
554     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
555     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
556     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
557     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
558     { X86::TEST16rr,        X86::TEST16rm,            0 },
559     { X86::TEST32rr,        X86::TEST32rm,            0 },
560     { X86::TEST64rr,        X86::TEST64rm,            0 },
561     { X86::TEST8rr,         X86::TEST8rm,             0 },
562     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
563     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
564     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
565 
566     // MMX version of foldable instructions
567     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
568     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
569     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
570     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
571     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
572     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
573     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
574     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
575     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
576     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
577 
578     // 3DNow! version of foldable instructions
579     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
580     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
581     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
582     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
583     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
584     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
585     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
586 
587     // AVX 128-bit versions of foldable instructions
588     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
589     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
590     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
591     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
592     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
593     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
594     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
595     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
596     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
597     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
598     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
599     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
600     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
601     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
602     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
603     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
604     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
605     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
606     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
607     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
608     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
609     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
610     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
611     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
612     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
613     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
614     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
615     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
616     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
617     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
618     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
619     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
620     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
621     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
622     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
623     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
624     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
625     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
626     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
627     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
628     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
629     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
630     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
631     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
632     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
633     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
634     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
635     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
636     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
637     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
638     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
639     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
640     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
641     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
642     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
643     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
644     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
645     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
646     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
647     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
648     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
649     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
650     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
651     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
652     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
653     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
654     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
655     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
656     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
657     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
658     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
659     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
660     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
661 
662     // AVX 256-bit foldable instructions
663     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
664     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
665     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
666     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
667     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
668     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
669     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
670     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
671     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
672     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
673     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
674     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
675     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
676     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
677     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
678     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
679     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
680     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
681     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
682     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
683     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
684     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
685     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
686     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
687     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
688     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
689     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
690 
691     // AVX2 foldable instructions
692 
693     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
694     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
695     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
696     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
697     // so they don't need an equivalent limitation.
698     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
699     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
700     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
701     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
702     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
703     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
704     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      0 },
705     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     0 },
706     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      0 },
707     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     0 },
708     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      0 },
709     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     0 },
710     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      0 },
711     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     0 },
712     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
713     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
714     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        0 },
715     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        0 },
716     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
717     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
718     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
719     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        0 },
720     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        0 },
721     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        0 },
722     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
723     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
724     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
725     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        0 },
726     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
727     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
728     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
729 
730     // XOP foldable instructions
731     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
732     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
733     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
734     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
735     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
736     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
737     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
738     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
739     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
740     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
741     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
742     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
743     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
744     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
745     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
746     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
747     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
748     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
749     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
750     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
751     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
752     { X86::VPROTBri,           X86::VPROTBmi,         0 },
753     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
754     { X86::VPROTDri,           X86::VPROTDmi,         0 },
755     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
756     { X86::VPROTQri,           X86::VPROTQmi,         0 },
757     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
758     { X86::VPROTWri,           X86::VPROTWmi,         0 },
759     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
760     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
761     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
762     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
763     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
764     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
765     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
766     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
767     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
768 
769     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
770     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
771     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
772     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
773     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
774     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
775     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
776     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
777     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
778     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
779     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
780     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
781     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
782     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
783     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
784     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
785     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
786     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
787     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
788     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
789     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
790     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
791     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
792     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
793     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
794     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
795     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
796     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
797     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
798     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
799     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
800     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
801     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
802     { X86::RORX32ri,        X86::RORX32mi,            0 },
803     { X86::RORX64ri,        X86::RORX64mi,            0 },
804     { X86::SARX32rr,        X86::SARX32rm,            0 },
805     { X86::SARX64rr,        X86::SARX64rm,            0 },
806     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
807     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
808     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
809     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
810     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
811     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
812     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
813     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
814     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
815     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
816     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
817 
818     // AVX-512 foldable instructions
819     { X86::VMOV64toPQIZrr,   X86::VMOVQI2PQIZrm,      0 },
820     { X86::VMOVDI2SSZrr,     X86::VMOVDI2SSZrm,       0 },
821     { X86::VMOVAPDZrr,       X86::VMOVAPDZrm,         TB_ALIGN_64 },
822     { X86::VMOVAPSZrr,       X86::VMOVAPSZrm,         TB_ALIGN_64 },
823     { X86::VMOVDQA32Zrr,     X86::VMOVDQA32Zrm,       TB_ALIGN_64 },
824     { X86::VMOVDQA64Zrr,     X86::VMOVDQA64Zrm,       TB_ALIGN_64 },
825     { X86::VMOVDQU8Zrr,      X86::VMOVDQU8Zrm,        0 },
826     { X86::VMOVDQU16Zrr,     X86::VMOVDQU16Zrm,       0 },
827     { X86::VMOVDQU32Zrr,     X86::VMOVDQU32Zrm,       0 },
828     { X86::VMOVDQU64Zrr,     X86::VMOVDQU64Zrm,       0 },
829     { X86::VMOVUPDZrr,       X86::VMOVUPDZrm,         0 },
830     { X86::VMOVUPSZrr,       X86::VMOVUPSZrm,         0 },
831     { X86::VPABSDZrr,        X86::VPABSDZrm,          0 },
832     { X86::VPABSQZrr,        X86::VPABSQZrm,          0 },
833     { X86::VBROADCASTSSZr,   X86::VBROADCASTSSZm,     TB_NO_REVERSE },
834     { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm,     TB_NO_REVERSE },
835     { X86::VBROADCASTSDZr,   X86::VBROADCASTSDZm,     TB_NO_REVERSE },
836     { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm,     TB_NO_REVERSE },
837 
838     // AVX-512 foldable instructions (256-bit versions)
839     { X86::VMOVAPDZ256rr,        X86::VMOVAPDZ256rm,        TB_ALIGN_32 },
840     { X86::VMOVAPSZ256rr,        X86::VMOVAPSZ256rm,        TB_ALIGN_32 },
841     { X86::VMOVDQA32Z256rr,      X86::VMOVDQA32Z256rm,      TB_ALIGN_32 },
842     { X86::VMOVDQA64Z256rr,      X86::VMOVDQA64Z256rm,      TB_ALIGN_32 },
843     { X86::VMOVDQU8Z256rr,       X86::VMOVDQU8Z256rm,       0 },
844     { X86::VMOVDQU16Z256rr,      X86::VMOVDQU16Z256rm,      0 },
845     { X86::VMOVDQU32Z256rr,      X86::VMOVDQU32Z256rm,      0 },
846     { X86::VMOVDQU64Z256rr,      X86::VMOVDQU64Z256rm,      0 },
847     { X86::VMOVUPDZ256rr,        X86::VMOVUPDZ256rm,        0 },
848     { X86::VMOVUPSZ256rr,        X86::VMOVUPSZ256rm,        0 },
849     { X86::VBROADCASTSSZ256r,    X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
850     { X86::VBROADCASTSSZ256r_s,  X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
851     { X86::VBROADCASTSDZ256r,    X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
852     { X86::VBROADCASTSDZ256r_s,  X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
853 
854     // AVX-512 foldable instructions (128-bit versions)
855     { X86::VMOVAPDZ128rr,        X86::VMOVAPDZ128rm,        TB_ALIGN_16 },
856     { X86::VMOVAPSZ128rr,        X86::VMOVAPSZ128rm,        TB_ALIGN_16 },
857     { X86::VMOVDQA32Z128rr,      X86::VMOVDQA32Z128rm,      TB_ALIGN_16 },
858     { X86::VMOVDQA64Z128rr,      X86::VMOVDQA64Z128rm,      TB_ALIGN_16 },
859     { X86::VMOVDQU8Z128rr,       X86::VMOVDQU8Z128rm,       0 },
860     { X86::VMOVDQU16Z128rr,      X86::VMOVDQU16Z128rm,      0 },
861     { X86::VMOVDQU32Z128rr,      X86::VMOVDQU32Z128rm,      0 },
862     { X86::VMOVDQU64Z128rr,      X86::VMOVDQU64Z128rm,      0 },
863     { X86::VMOVUPDZ128rr,        X86::VMOVUPDZ128rm,        0 },
864     { X86::VMOVUPSZ128rr,        X86::VMOVUPSZ128rm,        0 },
865     { X86::VBROADCASTSSZ128r,    X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
866     { X86::VBROADCASTSSZ128r_s,  X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
867     // F16C foldable instructions
868     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
869     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
870 
871     // AES foldable instructions
872     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
873     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
874     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
875     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
876   };
877 
878   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
879     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
880                   Entry.RegOp, Entry.MemOp,
881                   // Index 1, folded load
882                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
883   }
884 
885   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
886     { X86::ADC32rr,         X86::ADC32rm,       0 },
887     { X86::ADC64rr,         X86::ADC64rm,       0 },
888     { X86::ADD16rr,         X86::ADD16rm,       0 },
889     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
890     { X86::ADD32rr,         X86::ADD32rm,       0 },
891     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
892     { X86::ADD64rr,         X86::ADD64rm,       0 },
893     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
894     { X86::ADD8rr,          X86::ADD8rm,        0 },
895     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
896     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
897     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
898     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
899     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
900     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
901     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
902     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
903     { X86::AND16rr,         X86::AND16rm,       0 },
904     { X86::AND32rr,         X86::AND32rm,       0 },
905     { X86::AND64rr,         X86::AND64rm,       0 },
906     { X86::AND8rr,          X86::AND8rm,        0 },
907     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
908     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
909     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
910     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
911     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
912     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
913     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
914     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
915     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
916     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
917     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
918     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
919     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
920     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
921     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
922     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
923     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
924     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
925     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
926     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
927     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
928     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
929     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
930     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
931     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
932     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
933     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
934     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
935     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
936     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
937     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
938     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
939     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
940     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
941     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
942     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
943     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
944     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
945     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
946     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
947     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
948     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
949     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
950     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
951     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
952     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
953     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
954     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
955     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
956     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
957     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
958     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
959     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
960     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
961     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
962     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
963     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
964     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
965     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
966     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
967     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
968     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
969     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
970     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
971     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
972     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
973     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
974     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
975     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
976     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
977 
978     // Do not fold Fs* scalar logical op loads because there are no scalar
979     // load variants for these instructions. When folded, the load is required
980     // to be 128-bits, so the load size would not match.
981 
982     { X86::FvANDNPDrr,      X86::FvANDNPDrm,    TB_ALIGN_16 },
983     { X86::FvANDNPSrr,      X86::FvANDNPSrm,    TB_ALIGN_16 },
984     { X86::FvANDPDrr,       X86::FvANDPDrm,     TB_ALIGN_16 },
985     { X86::FvANDPSrr,       X86::FvANDPSrm,     TB_ALIGN_16 },
986     { X86::FvORPDrr,        X86::FvORPDrm,      TB_ALIGN_16 },
987     { X86::FvORPSrr,        X86::FvORPSrm,      TB_ALIGN_16 },
988     { X86::FvXORPDrr,       X86::FvXORPDrm,     TB_ALIGN_16 },
989     { X86::FvXORPSrr,       X86::FvXORPSrm,     TB_ALIGN_16 },
990     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
991     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
992     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
993     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
994     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
995     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
996     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
997     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
998     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
999     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
1000     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
1001     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
1002     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
1003     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
1004     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
1005     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
1006     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
1007     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
1008     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
1009     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
1010     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
1011     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
1012     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
1013     { X86::MINSDrr,         X86::MINSDrm,       0 },
1014     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
1015     { X86::MINSSrr,         X86::MINSSrm,       0 },
1016     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
1017     { X86::MOVLHPSrr,       X86::MOVHPSrm,      TB_NO_REVERSE },
1018     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1019     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1020     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1021     { X86::MULSDrr,         X86::MULSDrm,       0 },
1022     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
1023     { X86::MULSSrr,         X86::MULSSrm,       0 },
1024     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
1025     { X86::OR16rr,          X86::OR16rm,        0 },
1026     { X86::OR32rr,          X86::OR32rm,        0 },
1027     { X86::OR64rr,          X86::OR64rm,        0 },
1028     { X86::OR8rr,           X86::OR8rm,         0 },
1029     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1030     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1031     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1032     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1033     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1034     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1035     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1036     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1037     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1038     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1039     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1040     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1041     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1042     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1043     { X86::PALIGNRrri,      X86::PALIGNRrmi,    TB_ALIGN_16 },
1044     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1045     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1046     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1047     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1048     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1049     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1050     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1051     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1052     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1053     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1054     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1055     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1056     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1057     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1058     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1059     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1060     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1061     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1062     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1063     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1064     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1065     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1066     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1067     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1068     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1069     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
1070     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1071     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1072     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1073     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1074     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1075     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1076     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1077     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1078     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1079     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1080     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1081     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1082     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1083     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1084     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
1085     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1086     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1087     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1088     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1089     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1090     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1091     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1092     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1093     { X86::PSIGNBrr128,     X86::PSIGNBrm128,   TB_ALIGN_16 },
1094     { X86::PSIGNWrr128,     X86::PSIGNWrm128,   TB_ALIGN_16 },
1095     { X86::PSIGNDrr128,     X86::PSIGNDrm128,   TB_ALIGN_16 },
1096     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1097     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1098     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1099     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1100     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1101     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1102     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1103     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1104     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1105     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1106     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1107     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1108     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1109     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1110     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1111     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1112     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1113     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1114     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1115     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1116     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1117     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1118     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1119     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1120     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1121     { X86::ROUNDSDr,        X86::ROUNDSDm,      0 },
1122     { X86::ROUNDSSr,        X86::ROUNDSSm,      0 },
1123     { X86::SBB32rr,         X86::SBB32rm,       0 },
1124     { X86::SBB64rr,         X86::SBB64rm,       0 },
1125     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1126     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1127     { X86::SUB16rr,         X86::SUB16rm,       0 },
1128     { X86::SUB32rr,         X86::SUB32rm,       0 },
1129     { X86::SUB64rr,         X86::SUB64rm,       0 },
1130     { X86::SUB8rr,          X86::SUB8rm,        0 },
1131     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1132     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1133     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1134     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1135     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1136     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1137     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1138     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1139     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1140     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1141     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1142     { X86::XOR16rr,         X86::XOR16rm,       0 },
1143     { X86::XOR32rr,         X86::XOR32rm,       0 },
1144     { X86::XOR64rr,         X86::XOR64rm,       0 },
1145     { X86::XOR8rr,          X86::XOR8rm,        0 },
1146     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1147     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1148 
1149     // MMX version of foldable instructions
1150     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1151     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1152     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1153     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1154     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1155     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1156     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1157     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1158     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1159     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1160     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1161     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1162     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1163     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1164     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1165     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1166     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1167     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1168     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1169     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1170     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1171     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1172     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1173     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1174     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1175     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1176     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1177     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1178     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1179     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1180     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1181     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1182     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1183     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1184     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1185     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1186     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1187     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1188     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1189     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1190     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1191     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1192     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1193     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1194     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1195     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1196     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1197     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1198     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1199     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1200     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1201     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1202     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1203     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1204     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1205     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1206     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1207     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1208     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1209     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1210     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1211     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1212     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1213     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1214     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1215     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1216     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1217     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1218     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1219     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1220 
1221     // 3DNow! version of foldable instructions
1222     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1223     { X86::PFACCrr,           X86::PFACCrm,           0 },
1224     { X86::PFADDrr,           X86::PFADDrm,           0 },
1225     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1226     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1227     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1228     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1229     { X86::PFMINrr,           X86::PFMINrm,           0 },
1230     { X86::PFMULrr,           X86::PFMULrm,           0 },
1231     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1232     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1233     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1234     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1235     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1236     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1237     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1238     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1239 
1240     // AVX 128-bit versions of foldable instructions
1241     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1242     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1243     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1244     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1245     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1246     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1247     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1248     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1249     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1250     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1251     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1252     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1253     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1254     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        0 },
1255     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1256     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      0 },
1257     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1258     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       0 },
1259     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1260     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       0 },
1261     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1262     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1263     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1264     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1265     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1266     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1267     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1268     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1269     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1270     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1271     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1272     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1273     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1274     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1275     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1276     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1277     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1278     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1279     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1280     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1281     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1282     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1283     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1284     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1285     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1286     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1287     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1288     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1289     // Do not fold VFs* loads because there are no scalar load variants for
1290     // these instructions. When folded, the load is required to be 128-bits, so
1291     // the load size would not match.
1292     { X86::VFvANDNPDrr,       X86::VFvANDNPDrm,        0 },
1293     { X86::VFvANDNPSrr,       X86::VFvANDNPSrm,        0 },
1294     { X86::VFvANDPDrr,        X86::VFvANDPDrm,         0 },
1295     { X86::VFvANDPSrr,        X86::VFvANDPSrm,         0 },
1296     { X86::VFvORPDrr,         X86::VFvORPDrm,          0 },
1297     { X86::VFvORPSrr,         X86::VFvORPSrm,          0 },
1298     { X86::VFvXORPDrr,        X86::VFvXORPDrm,         0 },
1299     { X86::VFvXORPSrr,        X86::VFvXORPSrm,         0 },
1300     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1301     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1302     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1303     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1304     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1305     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1306     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1307     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1308     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1309     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1310     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1311     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1312     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1313     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1314     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1315     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1316     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1317     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1318     { X86::VMOVLHPSrr,        X86::VMOVHPSrm,          TB_NO_REVERSE },
1319     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1320     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1321     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1322     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1323     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1324     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1325     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1326     { X86::VORPDrr,           X86::VORPDrm,            0 },
1327     { X86::VORPSrr,           X86::VORPSrm,            0 },
1328     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1329     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1330     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1331     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1332     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1333     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1334     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1335     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1336     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1337     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1338     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1339     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1340     { X86::VPALIGNRrri,       X86::VPALIGNRrmi,        0 },
1341     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1342     { X86::VPANDrr,           X86::VPANDrm,            0 },
1343     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1344     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1345     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1346     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1347     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1348     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1349     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1350     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1351     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1352     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1353     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1354     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1355     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1356     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1357     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1358     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1359     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1360     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1361     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1362     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1363     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1364     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1365     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1366     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1367     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1368     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1369     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1370     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1371     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1372     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1373     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1374     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1375     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1376     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1377     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1378     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1379     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1380     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1381     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1382     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1383     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1384     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1385     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1386     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1387     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1388     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1389     { X86::VPORrr,            X86::VPORrm,             0 },
1390     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1391     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1392     { X86::VPSIGNBrr128,      X86::VPSIGNBrm128,       0 },
1393     { X86::VPSIGNWrr128,      X86::VPSIGNWrm128,       0 },
1394     { X86::VPSIGNDrr128,      X86::VPSIGNDrm128,       0 },
1395     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1396     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1397     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1398     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1399     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1400     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1401     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1402     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1403     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1404     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1405     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1406     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1407     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1408     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1409     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1410     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1411     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1412     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1413     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1414     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1415     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1416     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1417     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1418     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1419     { X86::VPXORrr,           X86::VPXORrm,            0 },
1420     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1421     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1422     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1423     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1424     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1425     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1426     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1427     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1428     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1429     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1430     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1431     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1432     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1433     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1434     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1435     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1436 
1437     // AVX 256-bit foldable instructions
1438     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1439     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1440     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1441     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1442     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1443     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1444     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1445     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1446     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1447     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1448     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1449     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1450     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1451     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1452     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1453     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1454     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1455     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1456     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1457     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1458     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1459     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1460     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1461     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1462     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1463     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1464     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1465     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1466     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1467     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1468     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1469     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1470     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1471     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1472     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1473     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1474     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1475     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1476     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1477     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1478     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1479     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1480     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1481 
1482     // AVX2 foldable instructions
1483     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1484     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1485     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1486     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1487     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1488     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1489     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1490     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1491     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1492     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1493     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1494     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1495     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1496     { X86::VPALIGNRYrri,      X86::VPALIGNRYrmi,       0 },
1497     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1498     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1499     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1500     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1501     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1502     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1503     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1504     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1505     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1506     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1507     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1508     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1509     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1510     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1511     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1512     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1513     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1514     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1515     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1516     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1517     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1518     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1519     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1520     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1521     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1522     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1523     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1524     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1525     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1526     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1527     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1528     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1529     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1530     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1531     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1532     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1533     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1534     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1535     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1536     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1537     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1538     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1539     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1540     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1541     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1542     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1543     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1544     { X86::VPORYrr,           X86::VPORYrm,            0 },
1545     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1546     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1547     { X86::VPSIGNBYrr256,     X86::VPSIGNBYrm256,      0 },
1548     { X86::VPSIGNWYrr256,     X86::VPSIGNWYrm256,      0 },
1549     { X86::VPSIGNDYrr256,     X86::VPSIGNDYrm256,      0 },
1550     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1551     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1552     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1553     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1554     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1555     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1556     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1557     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1558     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1559     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1560     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1561     { X86::VPSRAVD_Intrr,     X86::VPSRAVD_Intrm,      0 },
1562     { X86::VPSRAVD_IntYrr,    X86::VPSRAVD_IntYrm,     0 },
1563     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1564     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1565     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1566     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1567     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1568     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1569     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1570     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1571     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1572     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1573     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1574     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1575     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1576     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1577     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1578     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1579     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1580     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1581     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1582     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1583     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1584     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1585     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1586     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1587 
1588     // FMA4 foldable patterns
1589     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1590     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1591     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1592     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1593     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_NONE },
1594     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_NONE },
1595     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1596     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1597     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1598     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1599     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_NONE },
1600     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_NONE },
1601     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1602     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1603     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1604     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1605     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_NONE },
1606     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_NONE },
1607     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1608     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1609     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1610     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1611     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_NONE },
1612     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_NONE },
1613     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1614     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1615     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_NONE },
1616     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_NONE },
1617     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1618     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1619     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_NONE },
1620     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_NONE },
1621 
1622     // XOP foldable instructions
1623     { X86::VPCMOVrrr,         X86::VPCMOVrmr,           0 },
1624     { X86::VPCMOVrrrY,        X86::VPCMOVrmrY,          0 },
1625     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1626     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1627     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1628     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1629     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1630     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1631     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1632     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1633     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1634     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1635     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1636     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1637     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1638     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1639     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1640     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1641     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1642     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1643     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1644     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1645     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1646     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1647     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1648     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1649     { X86::VPPERMrrr,         X86::VPPERMrmr,           0 },
1650     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1651     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1652     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1653     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1654     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1655     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1656     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1657     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1658     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1659     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1660     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1661     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1662 
1663     // BMI/BMI2 foldable instructions
1664     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1665     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1666     { X86::MULX32rr,          X86::MULX32rm,            0 },
1667     { X86::MULX64rr,          X86::MULX64rm,            0 },
1668     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1669     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1670     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1671     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1672 
1673     // ADX foldable instructions
1674     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1675     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1676     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1677     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1678 
1679     // AVX-512 foldable instructions
1680     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1681     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1682     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1683     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1684     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1685     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1686     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1687     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1688     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1689     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1690     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1691     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1692     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1693     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1694     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1695     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1696     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1697     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1698     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1699     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1700     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1701     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1702     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1703     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1704     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1705     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1706     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1707     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1708     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1709     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1710     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1711     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1712     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1713     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1714     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1715     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1716     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1717     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1718     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1719 
1720     // AVX-512{F,VL} foldable instructions
1721     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1722     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1723     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1724 
1725     // AVX-512{F,VL} foldable instructions
1726     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1727     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1728     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1729     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1730 
1731     // AES foldable instructions
1732     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1733     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1734     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1735     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1736     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
1737     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
1738     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
1739     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
1740 
1741     // SHA foldable instructions
1742     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1743     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1744     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1745     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1746     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1747     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1748     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
1749   };
1750 
1751   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
1752     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1753                   Entry.RegOp, Entry.MemOp,
1754                   // Index 2, folded load
1755                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1756   }
1757 
1758   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1759     // FMA foldable instructions
1760     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1761     { X86::VFMADDSSr231r_Int,     X86::VFMADDSSr231m_Int,     TB_ALIGN_NONE },
1762     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1763     { X86::VFMADDSDr231r_Int,     X86::VFMADDSDr231m_Int,     TB_ALIGN_NONE },
1764     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1765     { X86::VFMADDSSr132r_Int,     X86::VFMADDSSr132m_Int,     TB_ALIGN_NONE },
1766     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1767     { X86::VFMADDSDr132r_Int,     X86::VFMADDSDr132m_Int,     TB_ALIGN_NONE },
1768     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1769     { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     TB_ALIGN_NONE },
1770     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1771     { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     TB_ALIGN_NONE },
1772 
1773     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1774     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1775     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1776     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1777     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1778     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1779     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1780     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1781     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1782     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1783     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1784     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1785 
1786     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1787     { X86::VFNMADDSSr231r_Int,    X86::VFNMADDSSr231m_Int,    TB_ALIGN_NONE },
1788     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1789     { X86::VFNMADDSDr231r_Int,    X86::VFNMADDSDr231m_Int,    TB_ALIGN_NONE },
1790     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1791     { X86::VFNMADDSSr132r_Int,    X86::VFNMADDSSr132m_Int,    TB_ALIGN_NONE },
1792     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1793     { X86::VFNMADDSDr132r_Int,    X86::VFNMADDSDr132m_Int,    TB_ALIGN_NONE },
1794     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1795     { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    TB_ALIGN_NONE },
1796     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1797     { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    TB_ALIGN_NONE },
1798 
1799     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1800     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1801     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1802     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1803     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1804     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1805     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1806     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1807     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1808     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1809     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1810     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1811 
1812     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1813     { X86::VFMSUBSSr231r_Int,     X86::VFMSUBSSr231m_Int,     TB_ALIGN_NONE },
1814     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1815     { X86::VFMSUBSDr231r_Int,     X86::VFMSUBSDr231m_Int,     TB_ALIGN_NONE },
1816     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1817     { X86::VFMSUBSSr132r_Int,     X86::VFMSUBSSr132m_Int,     TB_ALIGN_NONE },
1818     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1819     { X86::VFMSUBSDr132r_Int,     X86::VFMSUBSDr132m_Int,     TB_ALIGN_NONE },
1820     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1821     { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     TB_ALIGN_NONE },
1822     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1823     { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     TB_ALIGN_NONE },
1824 
1825     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1826     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1827     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1828     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1829     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1830     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1831     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1832     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1833     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1834     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1835     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1836     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1837 
1838     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1839     { X86::VFNMSUBSSr231r_Int,    X86::VFNMSUBSSr231m_Int,    TB_ALIGN_NONE },
1840     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1841     { X86::VFNMSUBSDr231r_Int,    X86::VFNMSUBSDr231m_Int,    TB_ALIGN_NONE },
1842     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1843     { X86::VFNMSUBSSr132r_Int,    X86::VFNMSUBSSr132m_Int,    TB_ALIGN_NONE },
1844     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1845     { X86::VFNMSUBSDr132r_Int,    X86::VFNMSUBSDr132m_Int,    TB_ALIGN_NONE },
1846     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1847     { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    TB_ALIGN_NONE },
1848     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1849     { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    TB_ALIGN_NONE },
1850 
1851     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1852     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1853     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1854     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1855     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1856     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1857     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1858     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1859     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1860     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1861     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1862     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1863 
1864     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1865     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1866     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1867     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1868     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1869     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1870     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1871     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1872     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1873     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1874     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1875     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1876 
1877     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1878     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1879     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1880     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1881     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1882     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1883     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1884     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1885     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1886     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1887     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1888     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1889 
1890     // FMA4 foldable patterns
1891     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
1892     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
1893     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
1894     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
1895     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_NONE },
1896     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_NONE },
1897     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
1898     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
1899     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
1900     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
1901     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_NONE },
1902     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_NONE },
1903     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
1904     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
1905     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
1906     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
1907     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_NONE },
1908     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_NONE },
1909     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
1910     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
1911     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
1912     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
1913     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_NONE },
1914     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_NONE },
1915     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
1916     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
1917     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_NONE },
1918     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_NONE },
1919     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
1920     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
1921     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_NONE },
1922     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_NONE },
1923 
1924     // XOP foldable instructions
1925     { X86::VPCMOVrrr,             X86::VPCMOVrrm,             0 },
1926     { X86::VPCMOVrrrY,            X86::VPCMOVrrmY,            0 },
1927     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
1928     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
1929     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
1930     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
1931     { X86::VPPERMrrr,             X86::VPPERMrrm,             0 },
1932 
1933     // AVX-512 VPERMI instructions with 3 source operands.
1934     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1935     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1936     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1937     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1938     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1939     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1940     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1941     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1942     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1943     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1944     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1945     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1946     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
1947      // AVX-512 arithmetic instructions
1948     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
1949     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
1950     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
1951     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
1952     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
1953     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
1954     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
1955     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
1956     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
1957     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
1958     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
1959     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
1960     // AVX-512{F,VL} arithmetic instructions 256-bit
1961     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
1962     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
1963     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
1964     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
1965     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
1966     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
1967     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
1968     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
1969     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
1970     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
1971     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
1972     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
1973     // AVX-512{F,VL} arithmetic instructions 128-bit
1974     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
1975     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
1976     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
1977     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
1978     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
1979     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
1980     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
1981     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
1982     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
1983     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
1984     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
1985     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
1986   };
1987 
1988   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
1989     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1990                   Entry.RegOp, Entry.MemOp,
1991                   // Index 3, folded load
1992                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1993   }
1994 
1995   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
1996      // AVX-512 foldable instructions
1997     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
1998     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
1999     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
2000     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
2001     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
2002     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
2003     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
2004     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
2005     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
2006     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
2007     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
2008     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
2009     // AVX-512{F,VL} foldable instructions 256-bit
2010     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
2011     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
2012     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
2013     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
2014     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
2015     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
2016     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
2017     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
2018     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
2019     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
2020     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
2021     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
2022     // AVX-512{F,VL} foldable instructions 128-bit
2023     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
2024     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
2025     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
2026     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
2027     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
2028     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
2029     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
2030     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
2031     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
2032     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
2033     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
2034     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
2035   };
2036 
2037   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
2038     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2039                   Entry.RegOp, Entry.MemOp,
2040                   // Index 4, folded load
2041                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
2042   }
2043 }
2044 
2045 void
2046 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2047                             MemOp2RegOpTableType &M2RTable,
2048                             uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
2049     if ((Flags & TB_NO_FORWARD) == 0) {
2050       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2051       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2052     }
2053     if ((Flags & TB_NO_REVERSE) == 0) {
2054       assert(!M2RTable.count(MemOp) &&
2055            "Duplicated entries in unfolding maps?");
2056       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2057     }
2058 }
2059 
2060 bool
2061 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2062                                     unsigned &SrcReg, unsigned &DstReg,
2063                                     unsigned &SubIdx) const {
2064   switch (MI.getOpcode()) {
2065   default: break;
2066   case X86::MOVSX16rr8:
2067   case X86::MOVZX16rr8:
2068   case X86::MOVSX32rr8:
2069   case X86::MOVZX32rr8:
2070   case X86::MOVSX64rr8:
2071     if (!Subtarget.is64Bit())
2072       // It's not always legal to reference the low 8-bit of the larger
2073       // register in 32-bit mode.
2074       return false;
2075   case X86::MOVSX32rr16:
2076   case X86::MOVZX32rr16:
2077   case X86::MOVSX64rr16:
2078   case X86::MOVSX64rr32: {
2079     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2080       // Be conservative.
2081       return false;
2082     SrcReg = MI.getOperand(1).getReg();
2083     DstReg = MI.getOperand(0).getReg();
2084     switch (MI.getOpcode()) {
2085     default: llvm_unreachable("Unreachable!");
2086     case X86::MOVSX16rr8:
2087     case X86::MOVZX16rr8:
2088     case X86::MOVSX32rr8:
2089     case X86::MOVZX32rr8:
2090     case X86::MOVSX64rr8:
2091       SubIdx = X86::sub_8bit;
2092       break;
2093     case X86::MOVSX32rr16:
2094     case X86::MOVZX32rr16:
2095     case X86::MOVSX64rr16:
2096       SubIdx = X86::sub_16bit;
2097       break;
2098     case X86::MOVSX64rr32:
2099       SubIdx = X86::sub_32bit;
2100       break;
2101     }
2102     return true;
2103   }
2104   }
2105   return false;
2106 }
2107 
2108 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
2109   const MachineFunction *MF = MI->getParent()->getParent();
2110   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2111 
2112   if (MI->getOpcode() == getCallFrameSetupOpcode() ||
2113       MI->getOpcode() == getCallFrameDestroyOpcode()) {
2114     unsigned StackAlign = TFI->getStackAlignment();
2115     int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
2116                  StackAlign;
2117 
2118     SPAdj -= MI->getOperand(1).getImm();
2119 
2120     if (MI->getOpcode() == getCallFrameSetupOpcode())
2121       return SPAdj;
2122     else
2123       return -SPAdj;
2124   }
2125 
2126   // To know whether a call adjusts the stack, we need information
2127   // that is bound to the following ADJCALLSTACKUP pseudo.
2128   // Look for the next ADJCALLSTACKUP that follows the call.
2129   if (MI->isCall()) {
2130     const MachineBasicBlock* MBB = MI->getParent();
2131     auto I = ++MachineBasicBlock::const_iterator(MI);
2132     for (auto E = MBB->end(); I != E; ++I) {
2133       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2134           I->isCall())
2135         break;
2136     }
2137 
2138     // If we could not find a frame destroy opcode, then it has already
2139     // been simplified, so we don't care.
2140     if (I->getOpcode() != getCallFrameDestroyOpcode())
2141       return 0;
2142 
2143     return -(I->getOperand(1).getImm());
2144   }
2145 
2146   // Currently handle only PUSHes we can reasonably expect to see
2147   // in call sequences
2148   switch (MI->getOpcode()) {
2149   default:
2150     return 0;
2151   case X86::PUSH32i8:
2152   case X86::PUSH32r:
2153   case X86::PUSH32rmm:
2154   case X86::PUSH32rmr:
2155   case X86::PUSHi32:
2156     return 4;
2157   case X86::PUSH64i8:
2158   case X86::PUSH64r:
2159   case X86::PUSH64rmm:
2160   case X86::PUSH64rmr:
2161   case X86::PUSH64i32:
2162     return 8;
2163   }
2164 }
2165 
2166 /// Return true and the FrameIndex if the specified
2167 /// operand and follow operands form a reference to the stack frame.
2168 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2169                                   int &FrameIndex) const {
2170   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2171       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2172       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2173       MI->getOperand(Op+X86::AddrDisp).isImm() &&
2174       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2175       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2176       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2177     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
2178     return true;
2179   }
2180   return false;
2181 }
2182 
2183 static bool isFrameLoadOpcode(int Opcode) {
2184   switch (Opcode) {
2185   default:
2186     return false;
2187   case X86::MOV8rm:
2188   case X86::MOV16rm:
2189   case X86::MOV32rm:
2190   case X86::MOV64rm:
2191   case X86::LD_Fp64m:
2192   case X86::MOVSSrm:
2193   case X86::MOVSDrm:
2194   case X86::MOVAPSrm:
2195   case X86::MOVAPDrm:
2196   case X86::MOVDQArm:
2197   case X86::VMOVSSrm:
2198   case X86::VMOVSDrm:
2199   case X86::VMOVAPSrm:
2200   case X86::VMOVAPDrm:
2201   case X86::VMOVDQArm:
2202   case X86::VMOVUPSYrm:
2203   case X86::VMOVAPSYrm:
2204   case X86::VMOVUPDYrm:
2205   case X86::VMOVAPDYrm:
2206   case X86::VMOVDQUYrm:
2207   case X86::VMOVDQAYrm:
2208   case X86::MMX_MOVD64rm:
2209   case X86::MMX_MOVQ64rm:
2210   case X86::VMOVAPSZrm:
2211   case X86::VMOVUPSZrm:
2212     return true;
2213   }
2214 }
2215 
2216 static bool isFrameStoreOpcode(int Opcode) {
2217   switch (Opcode) {
2218   default: break;
2219   case X86::MOV8mr:
2220   case X86::MOV16mr:
2221   case X86::MOV32mr:
2222   case X86::MOV64mr:
2223   case X86::ST_FpP64m:
2224   case X86::MOVSSmr:
2225   case X86::MOVSDmr:
2226   case X86::MOVAPSmr:
2227   case X86::MOVAPDmr:
2228   case X86::MOVDQAmr:
2229   case X86::VMOVSSmr:
2230   case X86::VMOVSDmr:
2231   case X86::VMOVAPSmr:
2232   case X86::VMOVAPDmr:
2233   case X86::VMOVDQAmr:
2234   case X86::VMOVUPSYmr:
2235   case X86::VMOVAPSYmr:
2236   case X86::VMOVUPDYmr:
2237   case X86::VMOVAPDYmr:
2238   case X86::VMOVDQUYmr:
2239   case X86::VMOVDQAYmr:
2240   case X86::VMOVUPSZmr:
2241   case X86::VMOVAPSZmr:
2242   case X86::MMX_MOVD64mr:
2243   case X86::MMX_MOVQ64mr:
2244   case X86::MMX_MOVNTQmr:
2245     return true;
2246   }
2247   return false;
2248 }
2249 
2250 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
2251                                            int &FrameIndex) const {
2252   if (isFrameLoadOpcode(MI->getOpcode()))
2253     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2254       return MI->getOperand(0).getReg();
2255   return 0;
2256 }
2257 
2258 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
2259                                                  int &FrameIndex) const {
2260   if (isFrameLoadOpcode(MI->getOpcode())) {
2261     unsigned Reg;
2262     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2263       return Reg;
2264     // Check for post-frame index elimination operations
2265     const MachineMemOperand *Dummy;
2266     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2267   }
2268   return 0;
2269 }
2270 
2271 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
2272                                           int &FrameIndex) const {
2273   if (isFrameStoreOpcode(MI->getOpcode()))
2274     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2275         isFrameOperand(MI, 0, FrameIndex))
2276       return MI->getOperand(X86::AddrNumOperands).getReg();
2277   return 0;
2278 }
2279 
2280 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2281                                                 int &FrameIndex) const {
2282   if (isFrameStoreOpcode(MI->getOpcode())) {
2283     unsigned Reg;
2284     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2285       return Reg;
2286     // Check for post-frame index elimination operations
2287     const MachineMemOperand *Dummy;
2288     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2289   }
2290   return 0;
2291 }
2292 
2293 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2294 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2295   // Don't waste compile time scanning use-def chains of physregs.
2296   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2297     return false;
2298   bool isPICBase = false;
2299   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2300          E = MRI.def_instr_end(); I != E; ++I) {
2301     MachineInstr *DefMI = &*I;
2302     if (DefMI->getOpcode() != X86::MOVPC32r)
2303       return false;
2304     assert(!isPICBase && "More than one PIC base?");
2305     isPICBase = true;
2306   }
2307   return isPICBase;
2308 }
2309 
2310 bool
2311 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2312                                                 AliasAnalysis *AA) const {
2313   switch (MI->getOpcode()) {
2314   default: break;
2315   case X86::MOV8rm:
2316   case X86::MOV16rm:
2317   case X86::MOV32rm:
2318   case X86::MOV64rm:
2319   case X86::LD_Fp64m:
2320   case X86::MOVSSrm:
2321   case X86::MOVSDrm:
2322   case X86::MOVAPSrm:
2323   case X86::MOVUPSrm:
2324   case X86::MOVAPDrm:
2325   case X86::MOVDQArm:
2326   case X86::MOVDQUrm:
2327   case X86::VMOVSSrm:
2328   case X86::VMOVSDrm:
2329   case X86::VMOVAPSrm:
2330   case X86::VMOVUPSrm:
2331   case X86::VMOVAPDrm:
2332   case X86::VMOVDQArm:
2333   case X86::VMOVDQUrm:
2334   case X86::VMOVAPSYrm:
2335   case X86::VMOVUPSYrm:
2336   case X86::VMOVAPDYrm:
2337   case X86::VMOVDQAYrm:
2338   case X86::VMOVDQUYrm:
2339   case X86::MMX_MOVD64rm:
2340   case X86::MMX_MOVQ64rm:
2341   case X86::FsVMOVAPSrm:
2342   case X86::FsVMOVAPDrm:
2343   case X86::FsMOVAPSrm:
2344   case X86::FsMOVAPDrm:
2345   // AVX-512
2346   case X86::VMOVAPDZ128rm:
2347   case X86::VMOVAPDZ256rm:
2348   case X86::VMOVAPDZrm:
2349   case X86::VMOVAPSZ128rm:
2350   case X86::VMOVAPSZ256rm:
2351   case X86::VMOVAPSZrm:
2352   case X86::VMOVDQA32Z128rm:
2353   case X86::VMOVDQA32Z256rm:
2354   case X86::VMOVDQA32Zrm:
2355   case X86::VMOVDQA64Z128rm:
2356   case X86::VMOVDQA64Z256rm:
2357   case X86::VMOVDQA64Zrm:
2358   case X86::VMOVDQU16Z128rm:
2359   case X86::VMOVDQU16Z256rm:
2360   case X86::VMOVDQU16Zrm:
2361   case X86::VMOVDQU32Z128rm:
2362   case X86::VMOVDQU32Z256rm:
2363   case X86::VMOVDQU32Zrm:
2364   case X86::VMOVDQU64Z128rm:
2365   case X86::VMOVDQU64Z256rm:
2366   case X86::VMOVDQU64Zrm:
2367   case X86::VMOVDQU8Z128rm:
2368   case X86::VMOVDQU8Z256rm:
2369   case X86::VMOVDQU8Zrm:
2370   case X86::VMOVUPSZ128rm:
2371   case X86::VMOVUPSZ256rm:
2372   case X86::VMOVUPSZrm: {
2373     // Loads from constant pools are trivially rematerializable.
2374     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2375         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2376         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2377         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2378         MI->isInvariantLoad(AA)) {
2379       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2380       if (BaseReg == 0 || BaseReg == X86::RIP)
2381         return true;
2382       // Allow re-materialization of PIC load.
2383       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
2384         return false;
2385       const MachineFunction &MF = *MI->getParent()->getParent();
2386       const MachineRegisterInfo &MRI = MF.getRegInfo();
2387       return regIsPICBase(BaseReg, MRI);
2388     }
2389     return false;
2390   }
2391 
2392   case X86::LEA32r:
2393   case X86::LEA64r: {
2394     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2395         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2396         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2397         !MI->getOperand(1+X86::AddrDisp).isReg()) {
2398       // lea fi#, lea GV, etc. are all rematerializable.
2399       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
2400         return true;
2401       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2402       if (BaseReg == 0)
2403         return true;
2404       // Allow re-materialization of lea PICBase + x.
2405       const MachineFunction &MF = *MI->getParent()->getParent();
2406       const MachineRegisterInfo &MRI = MF.getRegInfo();
2407       return regIsPICBase(BaseReg, MRI);
2408     }
2409     return false;
2410   }
2411   }
2412 
2413   // All other instructions marked M_REMATERIALIZABLE are always trivially
2414   // rematerializable.
2415   return true;
2416 }
2417 
2418 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2419                                          MachineBasicBlock::iterator I) const {
2420   MachineBasicBlock::iterator E = MBB.end();
2421 
2422   // For compile time consideration, if we are not able to determine the
2423   // safety after visiting 4 instructions in each direction, we will assume
2424   // it's not safe.
2425   MachineBasicBlock::iterator Iter = I;
2426   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2427     bool SeenDef = false;
2428     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2429       MachineOperand &MO = Iter->getOperand(j);
2430       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2431         SeenDef = true;
2432       if (!MO.isReg())
2433         continue;
2434       if (MO.getReg() == X86::EFLAGS) {
2435         if (MO.isUse())
2436           return false;
2437         SeenDef = true;
2438       }
2439     }
2440 
2441     if (SeenDef)
2442       // This instruction defines EFLAGS, no need to look any further.
2443       return true;
2444     ++Iter;
2445     // Skip over DBG_VALUE.
2446     while (Iter != E && Iter->isDebugValue())
2447       ++Iter;
2448   }
2449 
2450   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2451   // live in.
2452   if (Iter == E) {
2453     for (MachineBasicBlock *S : MBB.successors())
2454       if (S->isLiveIn(X86::EFLAGS))
2455         return false;
2456     return true;
2457   }
2458 
2459   MachineBasicBlock::iterator B = MBB.begin();
2460   Iter = I;
2461   for (unsigned i = 0; i < 4; ++i) {
2462     // If we make it to the beginning of the block, it's safe to clobber
2463     // EFLAGS iff EFLAGS is not live-in.
2464     if (Iter == B)
2465       return !MBB.isLiveIn(X86::EFLAGS);
2466 
2467     --Iter;
2468     // Skip over DBG_VALUE.
2469     while (Iter != B && Iter->isDebugValue())
2470       --Iter;
2471 
2472     bool SawKill = false;
2473     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2474       MachineOperand &MO = Iter->getOperand(j);
2475       // A register mask may clobber EFLAGS, but we should still look for a
2476       // live EFLAGS def.
2477       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2478         SawKill = true;
2479       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2480         if (MO.isDef()) return MO.isDead();
2481         if (MO.isKill()) SawKill = true;
2482       }
2483     }
2484 
2485     if (SawKill)
2486       // This instruction kills EFLAGS and doesn't redefine it, so
2487       // there's no need to look further.
2488       return true;
2489   }
2490 
2491   // Conservative answer.
2492   return false;
2493 }
2494 
2495 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2496                                  MachineBasicBlock::iterator I,
2497                                  unsigned DestReg, unsigned SubIdx,
2498                                  const MachineInstr *Orig,
2499                                  const TargetRegisterInfo &TRI) const {
2500   bool ClobbersEFLAGS = false;
2501   for (const MachineOperand &MO : Orig->operands()) {
2502     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2503       ClobbersEFLAGS = true;
2504       break;
2505     }
2506   }
2507 
2508   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2509     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2510     // effects.
2511     int Value;
2512     switch (Orig->getOpcode()) {
2513     case X86::MOV32r0:  Value = 0; break;
2514     case X86::MOV32r1:  Value = 1; break;
2515     case X86::MOV32r_1: Value = -1; break;
2516     default:
2517       llvm_unreachable("Unexpected instruction!");
2518     }
2519 
2520     const DebugLoc &DL = Orig->getDebugLoc();
2521     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2522       .addImm(Value);
2523   } else {
2524     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2525     MBB.insert(I, MI);
2526   }
2527 
2528   MachineInstr *NewMI = std::prev(I);
2529   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2530 }
2531 
2532 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2533 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr *MI) const {
2534   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2535     MachineOperand &MO = MI->getOperand(i);
2536     if (MO.isReg() && MO.isDef() &&
2537         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2538       return true;
2539     }
2540   }
2541   return false;
2542 }
2543 
2544 /// Check whether the shift count for a machine operand is non-zero.
2545 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2546                                               unsigned ShiftAmtOperandIdx) {
2547   // The shift count is six bits with the REX.W prefix and five bits without.
2548   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2549   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2550   return Imm & ShiftCountMask;
2551 }
2552 
2553 /// Check whether the given shift count is appropriate
2554 /// can be represented by a LEA instruction.
2555 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2556   // Left shift instructions can be transformed into load-effective-address
2557   // instructions if we can encode them appropriately.
2558   // A LEA instruction utilizes a SIB byte to encode its scale factor.
2559   // The SIB.scale field is two bits wide which means that we can encode any
2560   // shift amount less than 4.
2561   return ShAmt < 4 && ShAmt > 0;
2562 }
2563 
2564 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2565                                   unsigned Opc, bool AllowSP,
2566                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
2567                                   MachineOperand &ImplicitOp) const {
2568   MachineFunction &MF = *MI->getParent()->getParent();
2569   const TargetRegisterClass *RC;
2570   if (AllowSP) {
2571     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2572   } else {
2573     RC = Opc != X86::LEA32r ?
2574       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2575   }
2576   unsigned SrcReg = Src.getReg();
2577 
2578   // For both LEA64 and LEA32 the register already has essentially the right
2579   // type (32-bit or 64-bit) we may just need to forbid SP.
2580   if (Opc != X86::LEA64_32r) {
2581     NewSrc = SrcReg;
2582     isKill = Src.isKill();
2583     isUndef = Src.isUndef();
2584 
2585     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2586         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2587       return false;
2588 
2589     return true;
2590   }
2591 
2592   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2593   // another we need to add 64-bit registers to the final MI.
2594   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2595     ImplicitOp = Src;
2596     ImplicitOp.setImplicit();
2597 
2598     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
2599     MachineBasicBlock::LivenessQueryResult LQR =
2600       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2601 
2602     switch (LQR) {
2603     case MachineBasicBlock::LQR_Unknown:
2604       // We can't give sane liveness flags to the instruction, abandon LEA
2605       // formation.
2606       return false;
2607     case MachineBasicBlock::LQR_Live:
2608       isKill = MI->killsRegister(SrcReg);
2609       isUndef = false;
2610       break;
2611     default:
2612       // The physreg itself is dead, so we have to use it as an <undef>.
2613       isKill = false;
2614       isUndef = true;
2615       break;
2616     }
2617   } else {
2618     // Virtual register of the wrong class, we have to create a temporary 64-bit
2619     // vreg to feed into the LEA.
2620     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2621     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2622             get(TargetOpcode::COPY))
2623       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2624         .addOperand(Src);
2625 
2626     // Which is obviously going to be dead after we're done with it.
2627     isKill = true;
2628     isUndef = false;
2629   }
2630 
2631   // We've set all the parameters without issue.
2632   return true;
2633 }
2634 
2635 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2636 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2637 /// truncating back down to a 16-bit subregister.
2638 MachineInstr *
2639 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2640                                            MachineFunction::iterator &MFI,
2641                                            MachineBasicBlock::iterator &MBBI,
2642                                            LiveVariables *LV) const {
2643   MachineInstr *MI = MBBI;
2644   unsigned Dest = MI->getOperand(0).getReg();
2645   unsigned Src = MI->getOperand(1).getReg();
2646   bool isDead = MI->getOperand(0).isDead();
2647   bool isKill = MI->getOperand(1).isKill();
2648 
2649   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2650   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2651   unsigned Opc, leaInReg;
2652   if (Subtarget.is64Bit()) {
2653     Opc = X86::LEA64_32r;
2654     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2655   } else {
2656     Opc = X86::LEA32r;
2657     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2658   }
2659 
2660   // Build and insert into an implicit UNDEF value. This is OK because
2661   // well be shifting and then extracting the lower 16-bits.
2662   // This has the potential to cause partial register stall. e.g.
2663   //   movw    (%rbp,%rcx,2), %dx
2664   //   leal    -65(%rdx), %esi
2665   // But testing has shown this *does* help performance in 64-bit mode (at
2666   // least on modern x86 machines).
2667   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2668   MachineInstr *InsMI =
2669     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2670     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2671     .addReg(Src, getKillRegState(isKill));
2672 
2673   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2674                                     get(Opc), leaOutReg);
2675   switch (MIOpc) {
2676   default: llvm_unreachable("Unreachable!");
2677   case X86::SHL16ri: {
2678     unsigned ShAmt = MI->getOperand(2).getImm();
2679     MIB.addReg(0).addImm(1ULL << ShAmt)
2680        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2681     break;
2682   }
2683   case X86::INC16r:
2684     addRegOffset(MIB, leaInReg, true, 1);
2685     break;
2686   case X86::DEC16r:
2687     addRegOffset(MIB, leaInReg, true, -1);
2688     break;
2689   case X86::ADD16ri:
2690   case X86::ADD16ri8:
2691   case X86::ADD16ri_DB:
2692   case X86::ADD16ri8_DB:
2693     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2694     break;
2695   case X86::ADD16rr:
2696   case X86::ADD16rr_DB: {
2697     unsigned Src2 = MI->getOperand(2).getReg();
2698     bool isKill2 = MI->getOperand(2).isKill();
2699     unsigned leaInReg2 = 0;
2700     MachineInstr *InsMI2 = nullptr;
2701     if (Src == Src2) {
2702       // ADD16rr %reg1028<kill>, %reg1028
2703       // just a single insert_subreg.
2704       addRegReg(MIB, leaInReg, true, leaInReg, false);
2705     } else {
2706       if (Subtarget.is64Bit())
2707         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2708       else
2709         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2710       // Build and insert into an implicit UNDEF value. This is OK because
2711       // well be shifting and then extracting the lower 16-bits.
2712       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2713       InsMI2 =
2714         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2715         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2716         .addReg(Src2, getKillRegState(isKill2));
2717       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2718     }
2719     if (LV && isKill2 && InsMI2)
2720       LV->replaceKillInstruction(Src2, MI, InsMI2);
2721     break;
2722   }
2723   }
2724 
2725   MachineInstr *NewMI = MIB;
2726   MachineInstr *ExtMI =
2727     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2728     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2729     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2730 
2731   if (LV) {
2732     // Update live variables
2733     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2734     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2735     if (isKill)
2736       LV->replaceKillInstruction(Src, MI, InsMI);
2737     if (isDead)
2738       LV->replaceKillInstruction(Dest, MI, ExtMI);
2739   }
2740 
2741   return ExtMI;
2742 }
2743 
2744 /// This method must be implemented by targets that
2745 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2746 /// may be able to convert a two-address instruction into a true
2747 /// three-address instruction on demand.  This allows the X86 target (for
2748 /// example) to convert ADD and SHL instructions into LEA instructions if they
2749 /// would require register copies due to two-addressness.
2750 ///
2751 /// This method returns a null pointer if the transformation cannot be
2752 /// performed, otherwise it returns the new instruction.
2753 ///
2754 MachineInstr *
2755 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2756                                     MachineBasicBlock::iterator &MBBI,
2757                                     LiveVariables *LV) const {
2758   MachineInstr *MI = MBBI;
2759 
2760   // The following opcodes also sets the condition code register(s). Only
2761   // convert them to equivalent lea if the condition code register def's
2762   // are dead!
2763   if (hasLiveCondCodeDef(MI))
2764     return nullptr;
2765 
2766   MachineFunction &MF = *MI->getParent()->getParent();
2767   // All instructions input are two-addr instructions.  Get the known operands.
2768   const MachineOperand &Dest = MI->getOperand(0);
2769   const MachineOperand &Src = MI->getOperand(1);
2770 
2771   MachineInstr *NewMI = nullptr;
2772   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2773   // we have better subtarget support, enable the 16-bit LEA generation here.
2774   // 16-bit LEA is also slow on Core2.
2775   bool DisableLEA16 = true;
2776   bool is64Bit = Subtarget.is64Bit();
2777 
2778   unsigned MIOpc = MI->getOpcode();
2779   switch (MIOpc) {
2780   default: return nullptr;
2781   case X86::SHL64ri: {
2782     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2783     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2784     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2785 
2786     // LEA can't handle RSP.
2787     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2788         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2789                                            &X86::GR64_NOSPRegClass))
2790       return nullptr;
2791 
2792     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2793       .addOperand(Dest)
2794       .addReg(0).addImm(1ULL << ShAmt).addOperand(Src).addImm(0).addReg(0);
2795     break;
2796   }
2797   case X86::SHL32ri: {
2798     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2799     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2800     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2801 
2802     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2803 
2804     // LEA can't handle ESP.
2805     bool isKill, isUndef;
2806     unsigned SrcReg;
2807     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2808     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2809                         SrcReg, isKill, isUndef, ImplicitOp))
2810       return nullptr;
2811 
2812     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2813       .addOperand(Dest)
2814       .addReg(0).addImm(1ULL << ShAmt)
2815       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2816       .addImm(0).addReg(0);
2817     if (ImplicitOp.getReg() != 0)
2818       MIB.addOperand(ImplicitOp);
2819     NewMI = MIB;
2820 
2821     break;
2822   }
2823   case X86::SHL16ri: {
2824     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2825     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2826     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2827 
2828     if (DisableLEA16)
2829       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2830     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2831       .addOperand(Dest)
2832       .addReg(0).addImm(1ULL << ShAmt).addOperand(Src).addImm(0).addReg(0);
2833     break;
2834   }
2835   case X86::INC64r:
2836   case X86::INC32r: {
2837     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2838     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2839       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2840     bool isKill, isUndef;
2841     unsigned SrcReg;
2842     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2843     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2844                         SrcReg, isKill, isUndef, ImplicitOp))
2845       return nullptr;
2846 
2847     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2848         .addOperand(Dest)
2849         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2850     if (ImplicitOp.getReg() != 0)
2851       MIB.addOperand(ImplicitOp);
2852 
2853     NewMI = addOffset(MIB, 1);
2854     break;
2855   }
2856   case X86::INC16r:
2857     if (DisableLEA16)
2858       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2859                      : nullptr;
2860     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2861     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2862                       .addOperand(Dest).addOperand(Src), 1);
2863     break;
2864   case X86::DEC64r:
2865   case X86::DEC32r: {
2866     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2867     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2868       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2869 
2870     bool isKill, isUndef;
2871     unsigned SrcReg;
2872     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2873     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2874                         SrcReg, isKill, isUndef, ImplicitOp))
2875       return nullptr;
2876 
2877     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2878         .addOperand(Dest)
2879         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2880     if (ImplicitOp.getReg() != 0)
2881       MIB.addOperand(ImplicitOp);
2882 
2883     NewMI = addOffset(MIB, -1);
2884 
2885     break;
2886   }
2887   case X86::DEC16r:
2888     if (DisableLEA16)
2889       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2890                      : nullptr;
2891     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2892     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2893                       .addOperand(Dest).addOperand(Src), -1);
2894     break;
2895   case X86::ADD64rr:
2896   case X86::ADD64rr_DB:
2897   case X86::ADD32rr:
2898   case X86::ADD32rr_DB: {
2899     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2900     unsigned Opc;
2901     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2902       Opc = X86::LEA64r;
2903     else
2904       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2905 
2906     bool isKill, isUndef;
2907     unsigned SrcReg;
2908     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2909     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2910                         SrcReg, isKill, isUndef, ImplicitOp))
2911       return nullptr;
2912 
2913     const MachineOperand &Src2 = MI->getOperand(2);
2914     bool isKill2, isUndef2;
2915     unsigned SrcReg2;
2916     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2917     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2918                         SrcReg2, isKill2, isUndef2, ImplicitOp2))
2919       return nullptr;
2920 
2921     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2922       .addOperand(Dest);
2923     if (ImplicitOp.getReg() != 0)
2924       MIB.addOperand(ImplicitOp);
2925     if (ImplicitOp2.getReg() != 0)
2926       MIB.addOperand(ImplicitOp2);
2927 
2928     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2929 
2930     // Preserve undefness of the operands.
2931     NewMI->getOperand(1).setIsUndef(isUndef);
2932     NewMI->getOperand(3).setIsUndef(isUndef2);
2933 
2934     if (LV && Src2.isKill())
2935       LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2936     break;
2937   }
2938   case X86::ADD16rr:
2939   case X86::ADD16rr_DB: {
2940     if (DisableLEA16)
2941       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2942                      : nullptr;
2943     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2944     unsigned Src2 = MI->getOperand(2).getReg();
2945     bool isKill2 = MI->getOperand(2).isKill();
2946     NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2947                       .addOperand(Dest),
2948                       Src.getReg(), Src.isKill(), Src2, isKill2);
2949 
2950     // Preserve undefness of the operands.
2951     bool isUndef = MI->getOperand(1).isUndef();
2952     bool isUndef2 = MI->getOperand(2).isUndef();
2953     NewMI->getOperand(1).setIsUndef(isUndef);
2954     NewMI->getOperand(3).setIsUndef(isUndef2);
2955 
2956     if (LV && isKill2)
2957       LV->replaceKillInstruction(Src2, MI, NewMI);
2958     break;
2959   }
2960   case X86::ADD64ri32:
2961   case X86::ADD64ri8:
2962   case X86::ADD64ri32_DB:
2963   case X86::ADD64ri8_DB:
2964     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2965     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2966                       .addOperand(Dest).addOperand(Src),
2967                       MI->getOperand(2).getImm());
2968     break;
2969   case X86::ADD32ri:
2970   case X86::ADD32ri8:
2971   case X86::ADD32ri_DB:
2972   case X86::ADD32ri8_DB: {
2973     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2974     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2975 
2976     bool isKill, isUndef;
2977     unsigned SrcReg;
2978     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2979     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2980                         SrcReg, isKill, isUndef, ImplicitOp))
2981       return nullptr;
2982 
2983     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2984         .addOperand(Dest)
2985         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2986     if (ImplicitOp.getReg() != 0)
2987       MIB.addOperand(ImplicitOp);
2988 
2989     NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2990     break;
2991   }
2992   case X86::ADD16ri:
2993   case X86::ADD16ri8:
2994   case X86::ADD16ri_DB:
2995   case X86::ADD16ri8_DB:
2996     if (DisableLEA16)
2997       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2998                      : nullptr;
2999     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
3000     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
3001                       .addOperand(Dest).addOperand(Src),
3002                       MI->getOperand(2).getImm());
3003     break;
3004   }
3005 
3006   if (!NewMI) return nullptr;
3007 
3008   if (LV) {  // Update live variables
3009     if (Src.isKill())
3010       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
3011     if (Dest.isDead())
3012       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
3013   }
3014 
3015   MFI->insert(MBBI, NewMI);          // Insert the new inst
3016   return NewMI;
3017 }
3018 
3019 /// Returns true if the given instruction opcode is FMA3.
3020 /// Otherwise, returns false.
3021 /// The second parameter is optional and is used as the second return from
3022 /// the function. It is set to true if the given instruction has FMA3 opcode
3023 /// that is used for lowering of scalar FMA intrinsics, and it is set to false
3024 /// otherwise.
3025 static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
3026   if (IsIntrinsic)
3027     *IsIntrinsic = false;
3028 
3029   switch (Opcode) {
3030     case X86::VFMADDSDr132r:      case X86::VFMADDSDr132m:
3031     case X86::VFMADDSSr132r:      case X86::VFMADDSSr132m:
3032     case X86::VFMSUBSDr132r:      case X86::VFMSUBSDr132m:
3033     case X86::VFMSUBSSr132r:      case X86::VFMSUBSSr132m:
3034     case X86::VFNMADDSDr132r:     case X86::VFNMADDSDr132m:
3035     case X86::VFNMADDSSr132r:     case X86::VFNMADDSSr132m:
3036     case X86::VFNMSUBSDr132r:     case X86::VFNMSUBSDr132m:
3037     case X86::VFNMSUBSSr132r:     case X86::VFNMSUBSSr132m:
3038 
3039     case X86::VFMADDSDr213r:      case X86::VFMADDSDr213m:
3040     case X86::VFMADDSSr213r:      case X86::VFMADDSSr213m:
3041     case X86::VFMSUBSDr213r:      case X86::VFMSUBSDr213m:
3042     case X86::VFMSUBSSr213r:      case X86::VFMSUBSSr213m:
3043     case X86::VFNMADDSDr213r:     case X86::VFNMADDSDr213m:
3044     case X86::VFNMADDSSr213r:     case X86::VFNMADDSSr213m:
3045     case X86::VFNMSUBSDr213r:     case X86::VFNMSUBSDr213m:
3046     case X86::VFNMSUBSSr213r:     case X86::VFNMSUBSSr213m:
3047 
3048     case X86::VFMADDSDr231r:      case X86::VFMADDSDr231m:
3049     case X86::VFMADDSSr231r:      case X86::VFMADDSSr231m:
3050     case X86::VFMSUBSDr231r:      case X86::VFMSUBSDr231m:
3051     case X86::VFMSUBSSr231r:      case X86::VFMSUBSSr231m:
3052     case X86::VFNMADDSDr231r:     case X86::VFNMADDSDr231m:
3053     case X86::VFNMADDSSr231r:     case X86::VFNMADDSSr231m:
3054     case X86::VFNMSUBSDr231r:     case X86::VFNMSUBSDr231m:
3055     case X86::VFNMSUBSSr231r:     case X86::VFNMSUBSSr231m:
3056 
3057     case X86::VFMADDSUBPDr132r:   case X86::VFMADDSUBPDr132m:
3058     case X86::VFMADDSUBPSr132r:   case X86::VFMADDSUBPSr132m:
3059     case X86::VFMSUBADDPDr132r:   case X86::VFMSUBADDPDr132m:
3060     case X86::VFMSUBADDPSr132r:   case X86::VFMSUBADDPSr132m:
3061     case X86::VFMADDSUBPDr132rY:  case X86::VFMADDSUBPDr132mY:
3062     case X86::VFMADDSUBPSr132rY:  case X86::VFMADDSUBPSr132mY:
3063     case X86::VFMSUBADDPDr132rY:  case X86::VFMSUBADDPDr132mY:
3064     case X86::VFMSUBADDPSr132rY:  case X86::VFMSUBADDPSr132mY:
3065 
3066     case X86::VFMADDPDr132r:      case X86::VFMADDPDr132m:
3067     case X86::VFMADDPSr132r:      case X86::VFMADDPSr132m:
3068     case X86::VFMSUBPDr132r:      case X86::VFMSUBPDr132m:
3069     case X86::VFMSUBPSr132r:      case X86::VFMSUBPSr132m:
3070     case X86::VFNMADDPDr132r:     case X86::VFNMADDPDr132m:
3071     case X86::VFNMADDPSr132r:     case X86::VFNMADDPSr132m:
3072     case X86::VFNMSUBPDr132r:     case X86::VFNMSUBPDr132m:
3073     case X86::VFNMSUBPSr132r:     case X86::VFNMSUBPSr132m:
3074     case X86::VFMADDPDr132rY:     case X86::VFMADDPDr132mY:
3075     case X86::VFMADDPSr132rY:     case X86::VFMADDPSr132mY:
3076     case X86::VFMSUBPDr132rY:     case X86::VFMSUBPDr132mY:
3077     case X86::VFMSUBPSr132rY:     case X86::VFMSUBPSr132mY:
3078     case X86::VFNMADDPDr132rY:    case X86::VFNMADDPDr132mY:
3079     case X86::VFNMADDPSr132rY:    case X86::VFNMADDPSr132mY:
3080     case X86::VFNMSUBPDr132rY:    case X86::VFNMSUBPDr132mY:
3081     case X86::VFNMSUBPSr132rY:    case X86::VFNMSUBPSr132mY:
3082 
3083     case X86::VFMADDSUBPDr213r:   case X86::VFMADDSUBPDr213m:
3084     case X86::VFMADDSUBPSr213r:   case X86::VFMADDSUBPSr213m:
3085     case X86::VFMSUBADDPDr213r:   case X86::VFMSUBADDPDr213m:
3086     case X86::VFMSUBADDPSr213r:   case X86::VFMSUBADDPSr213m:
3087     case X86::VFMADDSUBPDr213rY:  case X86::VFMADDSUBPDr213mY:
3088     case X86::VFMADDSUBPSr213rY:  case X86::VFMADDSUBPSr213mY:
3089     case X86::VFMSUBADDPDr213rY:  case X86::VFMSUBADDPDr213mY:
3090     case X86::VFMSUBADDPSr213rY:  case X86::VFMSUBADDPSr213mY:
3091 
3092     case X86::VFMADDPDr213r:      case X86::VFMADDPDr213m:
3093     case X86::VFMADDPSr213r:      case X86::VFMADDPSr213m:
3094     case X86::VFMSUBPDr213r:      case X86::VFMSUBPDr213m:
3095     case X86::VFMSUBPSr213r:      case X86::VFMSUBPSr213m:
3096     case X86::VFNMADDPDr213r:     case X86::VFNMADDPDr213m:
3097     case X86::VFNMADDPSr213r:     case X86::VFNMADDPSr213m:
3098     case X86::VFNMSUBPDr213r:     case X86::VFNMSUBPDr213m:
3099     case X86::VFNMSUBPSr213r:     case X86::VFNMSUBPSr213m:
3100     case X86::VFMADDPDr213rY:     case X86::VFMADDPDr213mY:
3101     case X86::VFMADDPSr213rY:     case X86::VFMADDPSr213mY:
3102     case X86::VFMSUBPDr213rY:     case X86::VFMSUBPDr213mY:
3103     case X86::VFMSUBPSr213rY:     case X86::VFMSUBPSr213mY:
3104     case X86::VFNMADDPDr213rY:    case X86::VFNMADDPDr213mY:
3105     case X86::VFNMADDPSr213rY:    case X86::VFNMADDPSr213mY:
3106     case X86::VFNMSUBPDr213rY:    case X86::VFNMSUBPDr213mY:
3107     case X86::VFNMSUBPSr213rY:    case X86::VFNMSUBPSr213mY:
3108 
3109     case X86::VFMADDSUBPDr231r:   case X86::VFMADDSUBPDr231m:
3110     case X86::VFMADDSUBPSr231r:   case X86::VFMADDSUBPSr231m:
3111     case X86::VFMSUBADDPDr231r:   case X86::VFMSUBADDPDr231m:
3112     case X86::VFMSUBADDPSr231r:   case X86::VFMSUBADDPSr231m:
3113     case X86::VFMADDSUBPDr231rY:  case X86::VFMADDSUBPDr231mY:
3114     case X86::VFMADDSUBPSr231rY:  case X86::VFMADDSUBPSr231mY:
3115     case X86::VFMSUBADDPDr231rY:  case X86::VFMSUBADDPDr231mY:
3116     case X86::VFMSUBADDPSr231rY:  case X86::VFMSUBADDPSr231mY:
3117 
3118     case X86::VFMADDPDr231r:      case X86::VFMADDPDr231m:
3119     case X86::VFMADDPSr231r:      case X86::VFMADDPSr231m:
3120     case X86::VFMSUBPDr231r:      case X86::VFMSUBPDr231m:
3121     case X86::VFMSUBPSr231r:      case X86::VFMSUBPSr231m:
3122     case X86::VFNMADDPDr231r:     case X86::VFNMADDPDr231m:
3123     case X86::VFNMADDPSr231r:     case X86::VFNMADDPSr231m:
3124     case X86::VFNMSUBPDr231r:     case X86::VFNMSUBPDr231m:
3125     case X86::VFNMSUBPSr231r:     case X86::VFNMSUBPSr231m:
3126     case X86::VFMADDPDr231rY:     case X86::VFMADDPDr231mY:
3127     case X86::VFMADDPSr231rY:     case X86::VFMADDPSr231mY:
3128     case X86::VFMSUBPDr231rY:     case X86::VFMSUBPDr231mY:
3129     case X86::VFMSUBPSr231rY:     case X86::VFMSUBPSr231mY:
3130     case X86::VFNMADDPDr231rY:    case X86::VFNMADDPDr231mY:
3131     case X86::VFNMADDPSr231rY:    case X86::VFNMADDPSr231mY:
3132     case X86::VFNMSUBPDr231rY:    case X86::VFNMSUBPDr231mY:
3133     case X86::VFNMSUBPSr231rY:    case X86::VFNMSUBPSr231mY:
3134       return true;
3135 
3136     case X86::VFMADDSDr132r_Int:  case X86::VFMADDSDr132m_Int:
3137     case X86::VFMADDSSr132r_Int:  case X86::VFMADDSSr132m_Int:
3138     case X86::VFMSUBSDr132r_Int:  case X86::VFMSUBSDr132m_Int:
3139     case X86::VFMSUBSSr132r_Int:  case X86::VFMSUBSSr132m_Int:
3140     case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int:
3141     case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int:
3142     case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int:
3143     case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int:
3144 
3145     case X86::VFMADDSDr213r_Int:  case X86::VFMADDSDr213m_Int:
3146     case X86::VFMADDSSr213r_Int:  case X86::VFMADDSSr213m_Int:
3147     case X86::VFMSUBSDr213r_Int:  case X86::VFMSUBSDr213m_Int:
3148     case X86::VFMSUBSSr213r_Int:  case X86::VFMSUBSSr213m_Int:
3149     case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int:
3150     case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int:
3151     case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int:
3152     case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int:
3153 
3154     case X86::VFMADDSDr231r_Int:  case X86::VFMADDSDr231m_Int:
3155     case X86::VFMADDSSr231r_Int:  case X86::VFMADDSSr231m_Int:
3156     case X86::VFMSUBSDr231r_Int:  case X86::VFMSUBSDr231m_Int:
3157     case X86::VFMSUBSSr231r_Int:  case X86::VFMSUBSSr231m_Int:
3158     case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int:
3159     case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
3160     case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
3161     case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
3162       if (IsIntrinsic)
3163         *IsIntrinsic = true;
3164       return true;
3165     default:
3166       return false;
3167   }
3168   llvm_unreachable("Opcode not handled by the switch");
3169 }
3170 
3171 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr *MI,
3172                                                    bool NewMI,
3173                                                    unsigned OpIdx1,
3174                                                    unsigned OpIdx2) const {
3175   switch (MI->getOpcode()) {
3176   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3177   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
3178   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
3179   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3180   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3181   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
3182     unsigned Opc;
3183     unsigned Size;
3184     switch (MI->getOpcode()) {
3185     default: llvm_unreachable("Unreachable!");
3186     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3187     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3188     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3189     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
3190     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3191     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
3192     }
3193     unsigned Amt = MI->getOperand(3).getImm();
3194     if (NewMI) {
3195       MachineFunction &MF = *MI->getParent()->getParent();
3196       MI = MF.CloneMachineInstr(MI);
3197       NewMI = false;
3198     }
3199     MI->setDesc(get(Opc));
3200     MI->getOperand(3).setImm(Size-Amt);
3201     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3202   }
3203   case X86::BLENDPDrri:
3204   case X86::BLENDPSrri:
3205   case X86::PBLENDWrri:
3206   case X86::VBLENDPDrri:
3207   case X86::VBLENDPSrri:
3208   case X86::VBLENDPDYrri:
3209   case X86::VBLENDPSYrri:
3210   case X86::VPBLENDDrri:
3211   case X86::VPBLENDWrri:
3212   case X86::VPBLENDDYrri:
3213   case X86::VPBLENDWYrri:{
3214     unsigned Mask;
3215     switch (MI->getOpcode()) {
3216     default: llvm_unreachable("Unreachable!");
3217     case X86::BLENDPDrri:    Mask = 0x03; break;
3218     case X86::BLENDPSrri:    Mask = 0x0F; break;
3219     case X86::PBLENDWrri:    Mask = 0xFF; break;
3220     case X86::VBLENDPDrri:   Mask = 0x03; break;
3221     case X86::VBLENDPSrri:   Mask = 0x0F; break;
3222     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
3223     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
3224     case X86::VPBLENDDrri:   Mask = 0x0F; break;
3225     case X86::VPBLENDWrri:   Mask = 0xFF; break;
3226     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
3227     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
3228     }
3229     // Only the least significant bits of Imm are used.
3230     unsigned Imm = MI->getOperand(3).getImm() & Mask;
3231     if (NewMI) {
3232       MachineFunction &MF = *MI->getParent()->getParent();
3233       MI = MF.CloneMachineInstr(MI);
3234       NewMI = false;
3235     }
3236     MI->getOperand(3).setImm(Mask ^ Imm);
3237     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3238   }
3239   case X86::PCLMULQDQrr:
3240   case X86::VPCLMULQDQrr:{
3241     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3242     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3243     unsigned Imm = MI->getOperand(3).getImm();
3244     unsigned Src1Hi = Imm & 0x01;
3245     unsigned Src2Hi = Imm & 0x10;
3246     if (NewMI) {
3247       MachineFunction &MF = *MI->getParent()->getParent();
3248       MI = MF.CloneMachineInstr(MI);
3249       NewMI = false;
3250     }
3251     MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3252     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3253   }
3254   case X86::CMPPDrri:
3255   case X86::CMPPSrri:
3256   case X86::VCMPPDrri:
3257   case X86::VCMPPSrri:
3258   case X86::VCMPPDYrri:
3259   case X86::VCMPPSYrri: {
3260     // Float comparison can be safely commuted for
3261     // Ordered/Unordered/Equal/NotEqual tests
3262     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3263     switch (Imm) {
3264     case 0x00: // EQUAL
3265     case 0x03: // UNORDERED
3266     case 0x04: // NOT EQUAL
3267     case 0x07: // ORDERED
3268       if (NewMI) {
3269         MachineFunction &MF = *MI->getParent()->getParent();
3270         MI = MF.CloneMachineInstr(MI);
3271         NewMI = false;
3272       }
3273       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3274     default:
3275       return nullptr;
3276     }
3277   }
3278   case X86::VPCOMBri: case X86::VPCOMUBri:
3279   case X86::VPCOMDri: case X86::VPCOMUDri:
3280   case X86::VPCOMQri: case X86::VPCOMUQri:
3281   case X86::VPCOMWri: case X86::VPCOMUWri: {
3282     // Flip comparison mode immediate (if necessary).
3283     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3284     switch (Imm) {
3285     case 0x00: Imm = 0x02; break; // LT -> GT
3286     case 0x01: Imm = 0x03; break; // LE -> GE
3287     case 0x02: Imm = 0x00; break; // GT -> LT
3288     case 0x03: Imm = 0x01; break; // GE -> LE
3289     case 0x04: // EQ
3290     case 0x05: // NE
3291     case 0x06: // FALSE
3292     case 0x07: // TRUE
3293     default:
3294       break;
3295     }
3296     if (NewMI) {
3297       MachineFunction &MF = *MI->getParent()->getParent();
3298       MI = MF.CloneMachineInstr(MI);
3299       NewMI = false;
3300     }
3301     MI->getOperand(3).setImm(Imm);
3302     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3303   }
3304   case X86::VPERM2F128rr:
3305   case X86::VPERM2I128rr: {
3306     // Flip permute source immediate.
3307     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3308     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
3309     unsigned Imm = MI->getOperand(3).getImm() & 0xFF;
3310     if (NewMI) {
3311       MachineFunction &MF = *MI->getParent()->getParent();
3312       MI = MF.CloneMachineInstr(MI);
3313       NewMI = false;
3314     }
3315     MI->getOperand(3).setImm(Imm ^ 0x22);
3316     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3317   }
3318   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
3319   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3320   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
3321   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3322   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3323   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
3324   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
3325   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3326   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3327   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
3328   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
3329   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3330   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
3331   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3332   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
3333   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3334     unsigned Opc;
3335     switch (MI->getOpcode()) {
3336     default: llvm_unreachable("Unreachable!");
3337     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
3338     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
3339     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
3340     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3341     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3342     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3343     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
3344     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
3345     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
3346     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3347     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3348     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
3349     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3350     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3351     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3352     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
3353     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
3354     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
3355     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
3356     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
3357     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
3358     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3359     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3360     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3361     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3362     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3363     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3364     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
3365     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
3366     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
3367     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
3368     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
3369     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
3370     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3371     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3372     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3373     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
3374     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
3375     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
3376     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3377     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3378     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3379     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
3380     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
3381     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
3382     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3383     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3384     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3385     }
3386     if (NewMI) {
3387       MachineFunction &MF = *MI->getParent()->getParent();
3388       MI = MF.CloneMachineInstr(MI);
3389       NewMI = false;
3390     }
3391     MI->setDesc(get(Opc));
3392     // Fallthrough intended.
3393   }
3394   default:
3395     if (isFMA3(MI->getOpcode())) {
3396       unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
3397       if (Opc == 0)
3398         return nullptr;
3399       if (NewMI) {
3400         MachineFunction &MF = *MI->getParent()->getParent();
3401         MI = MF.CloneMachineInstr(MI);
3402         NewMI = false;
3403       }
3404       MI->setDesc(get(Opc));
3405     }
3406     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3407   }
3408 }
3409 
3410 bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr *MI,
3411                                              unsigned &SrcOpIdx1,
3412                                              unsigned &SrcOpIdx2) const {
3413 
3414   unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3415 
3416   // Only the first RegOpsNum operands are commutable.
3417   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3418   // that the operand is not specified/fixed.
3419   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3420       (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3421     return false;
3422   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3423       (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3424     return false;
3425 
3426   // Look for two different register operands assumed to be commutable
3427   // regardless of the FMA opcode. The FMA opcode is adjusted later.
3428   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3429       SrcOpIdx2 == CommuteAnyOperandIndex) {
3430     unsigned CommutableOpIdx1 = SrcOpIdx1;
3431     unsigned CommutableOpIdx2 = SrcOpIdx2;
3432 
3433     // At least one of operands to be commuted is not specified and
3434     // this method is free to choose appropriate commutable operands.
3435     if (SrcOpIdx1 == SrcOpIdx2)
3436       // Both of operands are not fixed. By default set one of commutable
3437       // operands to the last register operand of the instruction.
3438       CommutableOpIdx2 = RegOpsNum;
3439     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3440       // Only one of operands is not fixed.
3441       CommutableOpIdx2 = SrcOpIdx1;
3442 
3443     // CommutableOpIdx2 is well defined now. Let's choose another commutable
3444     // operand and assign its index to CommutableOpIdx1.
3445     unsigned Op2Reg = MI->getOperand(CommutableOpIdx2).getReg();
3446     for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3447       // The commuted operands must have different registers.
3448       // Otherwise, the commute transformation does not change anything and
3449       // is useless then.
3450       if (Op2Reg != MI->getOperand(CommutableOpIdx1).getReg())
3451         break;
3452     }
3453 
3454     // No appropriate commutable operands were found.
3455     if (CommutableOpIdx1 == 0)
3456       return false;
3457 
3458     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3459     // to return those values.
3460     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3461                               CommutableOpIdx1, CommutableOpIdx2))
3462       return false;
3463   }
3464 
3465   // Check if we can adjust the opcode to preserve the semantics when
3466   // commute the register operands.
3467   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
3468 }
3469 
3470 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(MachineInstr *MI,
3471                                                       unsigned SrcOpIdx1,
3472                                                       unsigned SrcOpIdx2) const {
3473   unsigned Opc = MI->getOpcode();
3474 
3475   // Define the array that holds FMA opcodes in groups
3476   // of 3 opcodes(132, 213, 231) in each group.
3477   static const uint16_t RegularOpcodeGroups[][3] = {
3478     { X86::VFMADDSSr132r,   X86::VFMADDSSr213r,   X86::VFMADDSSr231r  },
3479     { X86::VFMADDSDr132r,   X86::VFMADDSDr213r,   X86::VFMADDSDr231r  },
3480     { X86::VFMADDPSr132r,   X86::VFMADDPSr213r,   X86::VFMADDPSr231r  },
3481     { X86::VFMADDPDr132r,   X86::VFMADDPDr213r,   X86::VFMADDPDr231r  },
3482     { X86::VFMADDPSr132rY,  X86::VFMADDPSr213rY,  X86::VFMADDPSr231rY },
3483     { X86::VFMADDPDr132rY,  X86::VFMADDPDr213rY,  X86::VFMADDPDr231rY },
3484     { X86::VFMADDSSr132m,   X86::VFMADDSSr213m,   X86::VFMADDSSr231m  },
3485     { X86::VFMADDSDr132m,   X86::VFMADDSDr213m,   X86::VFMADDSDr231m  },
3486     { X86::VFMADDPSr132m,   X86::VFMADDPSr213m,   X86::VFMADDPSr231m  },
3487     { X86::VFMADDPDr132m,   X86::VFMADDPDr213m,   X86::VFMADDPDr231m  },
3488     { X86::VFMADDPSr132mY,  X86::VFMADDPSr213mY,  X86::VFMADDPSr231mY },
3489     { X86::VFMADDPDr132mY,  X86::VFMADDPDr213mY,  X86::VFMADDPDr231mY },
3490 
3491     { X86::VFMSUBSSr132r,   X86::VFMSUBSSr213r,   X86::VFMSUBSSr231r  },
3492     { X86::VFMSUBSDr132r,   X86::VFMSUBSDr213r,   X86::VFMSUBSDr231r  },
3493     { X86::VFMSUBPSr132r,   X86::VFMSUBPSr213r,   X86::VFMSUBPSr231r  },
3494     { X86::VFMSUBPDr132r,   X86::VFMSUBPDr213r,   X86::VFMSUBPDr231r  },
3495     { X86::VFMSUBPSr132rY,  X86::VFMSUBPSr213rY,  X86::VFMSUBPSr231rY },
3496     { X86::VFMSUBPDr132rY,  X86::VFMSUBPDr213rY,  X86::VFMSUBPDr231rY },
3497     { X86::VFMSUBSSr132m,   X86::VFMSUBSSr213m,   X86::VFMSUBSSr231m  },
3498     { X86::VFMSUBSDr132m,   X86::VFMSUBSDr213m,   X86::VFMSUBSDr231m  },
3499     { X86::VFMSUBPSr132m,   X86::VFMSUBPSr213m,   X86::VFMSUBPSr231m  },
3500     { X86::VFMSUBPDr132m,   X86::VFMSUBPDr213m,   X86::VFMSUBPDr231m  },
3501     { X86::VFMSUBPSr132mY,  X86::VFMSUBPSr213mY,  X86::VFMSUBPSr231mY },
3502     { X86::VFMSUBPDr132mY,  X86::VFMSUBPDr213mY,  X86::VFMSUBPDr231mY },
3503 
3504     { X86::VFNMADDSSr132r,  X86::VFNMADDSSr213r,  X86::VFNMADDSSr231r  },
3505     { X86::VFNMADDSDr132r,  X86::VFNMADDSDr213r,  X86::VFNMADDSDr231r  },
3506     { X86::VFNMADDPSr132r,  X86::VFNMADDPSr213r,  X86::VFNMADDPSr231r  },
3507     { X86::VFNMADDPDr132r,  X86::VFNMADDPDr213r,  X86::VFNMADDPDr231r  },
3508     { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
3509     { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
3510     { X86::VFNMADDSSr132m,  X86::VFNMADDSSr213m,  X86::VFNMADDSSr231m  },
3511     { X86::VFNMADDSDr132m,  X86::VFNMADDSDr213m,  X86::VFNMADDSDr231m  },
3512     { X86::VFNMADDPSr132m,  X86::VFNMADDPSr213m,  X86::VFNMADDPSr231m  },
3513     { X86::VFNMADDPDr132m,  X86::VFNMADDPDr213m,  X86::VFNMADDPDr231m  },
3514     { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
3515     { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
3516 
3517     { X86::VFNMSUBSSr132r,  X86::VFNMSUBSSr213r,  X86::VFNMSUBSSr231r  },
3518     { X86::VFNMSUBSDr132r,  X86::VFNMSUBSDr213r,  X86::VFNMSUBSDr231r  },
3519     { X86::VFNMSUBPSr132r,  X86::VFNMSUBPSr213r,  X86::VFNMSUBPSr231r  },
3520     { X86::VFNMSUBPDr132r,  X86::VFNMSUBPDr213r,  X86::VFNMSUBPDr231r  },
3521     { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
3522     { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
3523     { X86::VFNMSUBSSr132m,  X86::VFNMSUBSSr213m,  X86::VFNMSUBSSr231m  },
3524     { X86::VFNMSUBSDr132m,  X86::VFNMSUBSDr213m,  X86::VFNMSUBSDr231m  },
3525     { X86::VFNMSUBPSr132m,  X86::VFNMSUBPSr213m,  X86::VFNMSUBPSr231m  },
3526     { X86::VFNMSUBPDr132m,  X86::VFNMSUBPDr213m,  X86::VFNMSUBPDr231m  },
3527     { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
3528     { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
3529 
3530     { X86::VFMADDSUBPSr132r,  X86::VFMADDSUBPSr213r,  X86::VFMADDSUBPSr231r  },
3531     { X86::VFMADDSUBPDr132r,  X86::VFMADDSUBPDr213r,  X86::VFMADDSUBPDr231r  },
3532     { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
3533     { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
3534     { X86::VFMADDSUBPSr132m,  X86::VFMADDSUBPSr213m,  X86::VFMADDSUBPSr231m  },
3535     { X86::VFMADDSUBPDr132m,  X86::VFMADDSUBPDr213m,  X86::VFMADDSUBPDr231m  },
3536     { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
3537     { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
3538 
3539     { X86::VFMSUBADDPSr132r,  X86::VFMSUBADDPSr213r,  X86::VFMSUBADDPSr231r  },
3540     { X86::VFMSUBADDPDr132r,  X86::VFMSUBADDPDr213r,  X86::VFMSUBADDPDr231r  },
3541     { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
3542     { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
3543     { X86::VFMSUBADDPSr132m,  X86::VFMSUBADDPSr213m,  X86::VFMSUBADDPSr231m  },
3544     { X86::VFMSUBADDPDr132m,  X86::VFMSUBADDPDr213m,  X86::VFMSUBADDPDr231m  },
3545     { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
3546     { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
3547   };
3548 
3549   // Define the array that holds FMA*_Int opcodes in groups
3550   // of 3 opcodes(132, 213, 231) in each group.
3551   static const uint16_t IntrinOpcodeGroups[][3] = {
3552     { X86::VFMADDSSr132r_Int,  X86::VFMADDSSr213r_Int,  X86::VFMADDSSr231r_Int },
3553     { X86::VFMADDSDr132r_Int,  X86::VFMADDSDr213r_Int,  X86::VFMADDSDr231r_Int },
3554     { X86::VFMADDSSr132m_Int,  X86::VFMADDSSr213m_Int,  X86::VFMADDSSr231m_Int },
3555     { X86::VFMADDSDr132m_Int,  X86::VFMADDSDr213m_Int,  X86::VFMADDSDr231m_Int },
3556 
3557     { X86::VFMSUBSSr132r_Int,  X86::VFMSUBSSr213r_Int,  X86::VFMSUBSSr231r_Int },
3558     { X86::VFMSUBSDr132r_Int,  X86::VFMSUBSDr213r_Int,  X86::VFMSUBSDr231r_Int },
3559     { X86::VFMSUBSSr132m_Int,  X86::VFMSUBSSr213m_Int,  X86::VFMSUBSSr231m_Int },
3560     { X86::VFMSUBSDr132m_Int,  X86::VFMSUBSDr213m_Int,  X86::VFMSUBSDr231m_Int },
3561 
3562     { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
3563     { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
3564     { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
3565     { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
3566 
3567     { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
3568     { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
3569     { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
3570     { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
3571   };
3572 
3573   const unsigned Form132Index = 0;
3574   const unsigned Form213Index = 1;
3575   const unsigned Form231Index = 2;
3576   const unsigned FormsNum = 3;
3577 
3578   bool IsIntrinOpcode;
3579   isFMA3(Opc, &IsIntrinOpcode);
3580 
3581   size_t GroupsNum;
3582   const uint16_t (*OpcodeGroups)[3];
3583   if (IsIntrinOpcode) {
3584     GroupsNum = array_lengthof(IntrinOpcodeGroups);
3585     OpcodeGroups = IntrinOpcodeGroups;
3586   } else {
3587     GroupsNum = array_lengthof(RegularOpcodeGroups);
3588     OpcodeGroups = RegularOpcodeGroups;
3589   }
3590 
3591   const uint16_t *FoundOpcodesGroup = nullptr;
3592   size_t FormIndex;
3593 
3594   // Look for the input opcode in the corresponding opcodes table.
3595   for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
3596          ++GroupIndex) {
3597     for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
3598       if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
3599         FoundOpcodesGroup = OpcodeGroups[GroupIndex];
3600         break;
3601       }
3602     }
3603   }
3604 
3605   // The input opcode does not match with any of the opcodes from the tables.
3606   // The unsupported FMA opcode must be added to one of the two opcode groups
3607   // defined above.
3608   assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
3609 
3610   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3611   if (SrcOpIdx1 > SrcOpIdx2)
3612     std::swap(SrcOpIdx1, SrcOpIdx2);
3613 
3614   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3615   // analysis. The commute optimization is legal only if all users of FMA*_Int
3616   // use only the lowest element of the FMA*_Int instruction. Such analysis are
3617   // not implemented yet. So, just return 0 in that case.
3618   // When such analysis are available this place will be the right place for
3619   // calling it.
3620   if (IsIntrinOpcode && SrcOpIdx1 == 1)
3621     return 0;
3622 
3623   unsigned Case;
3624   if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
3625     Case = 0;
3626   else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3627     Case = 1;
3628   else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3629     Case = 2;
3630   else
3631     return 0;
3632 
3633   // Define the FMA forms mapping array that helps to map input FMA form
3634   // to output FMA form to preserve the operation semantics after
3635   // commuting the operands.
3636   static const unsigned FormMapping[][3] = {
3637     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3638     // FMA132 A, C, b; ==> FMA231 C, A, b;
3639     // FMA213 B, A, c; ==> FMA213 A, B, c;
3640     // FMA231 C, A, b; ==> FMA132 A, C, b;
3641     { Form231Index, Form213Index, Form132Index },
3642     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3643     // FMA132 A, c, B; ==> FMA132 B, c, A;
3644     // FMA213 B, a, C; ==> FMA231 C, a, B;
3645     // FMA231 C, a, B; ==> FMA213 B, a, C;
3646     { Form132Index, Form231Index, Form213Index },
3647     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3648     // FMA132 a, C, B; ==> FMA213 a, B, C;
3649     // FMA213 b, A, C; ==> FMA132 b, C, A;
3650     // FMA231 c, A, B; ==> FMA231 c, B, A;
3651     { Form213Index, Form132Index, Form231Index }
3652   };
3653 
3654   // Everything is ready, just adjust the FMA opcode and return it.
3655   FormIndex = FormMapping[Case][FormIndex];
3656   return FoundOpcodesGroup[FormIndex];
3657 }
3658 
3659 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI,
3660                                          unsigned &SrcOpIdx1,
3661                                          unsigned &SrcOpIdx2) const {
3662   switch (MI->getOpcode()) {
3663     case X86::CMPPDrri:
3664     case X86::CMPPSrri:
3665     case X86::VCMPPDrri:
3666     case X86::VCMPPSrri:
3667     case X86::VCMPPDYrri:
3668     case X86::VCMPPSYrri: {
3669       // Float comparison can be safely commuted for
3670       // Ordered/Unordered/Equal/NotEqual tests
3671       unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3672       switch (Imm) {
3673         case 0x00: // EQUAL
3674         case 0x03: // UNORDERED
3675         case 0x04: // NOT EQUAL
3676         case 0x07: // ORDERED
3677           // The indices of the commutable operands are 1 and 2.
3678           // Assign them to the returned operand indices here.
3679           return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
3680       }
3681       return false;
3682     }
3683     default:
3684       if (isFMA3(MI->getOpcode()))
3685         return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3686       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3687   }
3688   return false;
3689 }
3690 
3691 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
3692   switch (BrOpc) {
3693   default: return X86::COND_INVALID;
3694   case X86::JE_1:  return X86::COND_E;
3695   case X86::JNE_1: return X86::COND_NE;
3696   case X86::JL_1:  return X86::COND_L;
3697   case X86::JLE_1: return X86::COND_LE;
3698   case X86::JG_1:  return X86::COND_G;
3699   case X86::JGE_1: return X86::COND_GE;
3700   case X86::JB_1:  return X86::COND_B;
3701   case X86::JBE_1: return X86::COND_BE;
3702   case X86::JA_1:  return X86::COND_A;
3703   case X86::JAE_1: return X86::COND_AE;
3704   case X86::JS_1:  return X86::COND_S;
3705   case X86::JNS_1: return X86::COND_NS;
3706   case X86::JP_1:  return X86::COND_P;
3707   case X86::JNP_1: return X86::COND_NP;
3708   case X86::JO_1:  return X86::COND_O;
3709   case X86::JNO_1: return X86::COND_NO;
3710   }
3711 }
3712 
3713 /// Return condition code of a SET opcode.
3714 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3715   switch (Opc) {
3716   default: return X86::COND_INVALID;
3717   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
3718   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3719   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
3720   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3721   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
3722   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
3723   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3724   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
3725   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3726   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3727   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3728   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3729   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3730   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
3731   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
3732   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
3733   }
3734 }
3735 
3736 /// Return condition code of a CMov opcode.
3737 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
3738   switch (Opc) {
3739   default: return X86::COND_INVALID;
3740   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
3741   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
3742     return X86::COND_A;
3743   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3744   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3745     return X86::COND_AE;
3746   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
3747   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
3748     return X86::COND_B;
3749   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3750   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3751     return X86::COND_BE;
3752   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
3753   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
3754     return X86::COND_E;
3755   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
3756   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
3757     return X86::COND_G;
3758   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3759   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3760     return X86::COND_GE;
3761   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
3762   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
3763     return X86::COND_L;
3764   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3765   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3766     return X86::COND_LE;
3767   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3768   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3769     return X86::COND_NE;
3770   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3771   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3772     return X86::COND_NO;
3773   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3774   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3775     return X86::COND_NP;
3776   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3777   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3778     return X86::COND_NS;
3779   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
3780   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
3781     return X86::COND_O;
3782   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
3783   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
3784     return X86::COND_P;
3785   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
3786   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
3787     return X86::COND_S;
3788   }
3789 }
3790 
3791 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3792   switch (CC) {
3793   default: llvm_unreachable("Illegal condition code!");
3794   case X86::COND_E:  return X86::JE_1;
3795   case X86::COND_NE: return X86::JNE_1;
3796   case X86::COND_L:  return X86::JL_1;
3797   case X86::COND_LE: return X86::JLE_1;
3798   case X86::COND_G:  return X86::JG_1;
3799   case X86::COND_GE: return X86::JGE_1;
3800   case X86::COND_B:  return X86::JB_1;
3801   case X86::COND_BE: return X86::JBE_1;
3802   case X86::COND_A:  return X86::JA_1;
3803   case X86::COND_AE: return X86::JAE_1;
3804   case X86::COND_S:  return X86::JS_1;
3805   case X86::COND_NS: return X86::JNS_1;
3806   case X86::COND_P:  return X86::JP_1;
3807   case X86::COND_NP: return X86::JNP_1;
3808   case X86::COND_O:  return X86::JO_1;
3809   case X86::COND_NO: return X86::JNO_1;
3810   }
3811 }
3812 
3813 /// Return the inverse of the specified condition,
3814 /// e.g. turning COND_E to COND_NE.
3815 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3816   switch (CC) {
3817   default: llvm_unreachable("Illegal condition code!");
3818   case X86::COND_E:  return X86::COND_NE;
3819   case X86::COND_NE: return X86::COND_E;
3820   case X86::COND_L:  return X86::COND_GE;
3821   case X86::COND_LE: return X86::COND_G;
3822   case X86::COND_G:  return X86::COND_LE;
3823   case X86::COND_GE: return X86::COND_L;
3824   case X86::COND_B:  return X86::COND_AE;
3825   case X86::COND_BE: return X86::COND_A;
3826   case X86::COND_A:  return X86::COND_BE;
3827   case X86::COND_AE: return X86::COND_B;
3828   case X86::COND_S:  return X86::COND_NS;
3829   case X86::COND_NS: return X86::COND_S;
3830   case X86::COND_P:  return X86::COND_NP;
3831   case X86::COND_NP: return X86::COND_P;
3832   case X86::COND_O:  return X86::COND_NO;
3833   case X86::COND_NO: return X86::COND_O;
3834   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
3835   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
3836   }
3837 }
3838 
3839 /// Assuming the flags are set by MI(a,b), return the condition code if we
3840 /// modify the instructions such that flags are set by MI(b,a).
3841 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3842   switch (CC) {
3843   default: return X86::COND_INVALID;
3844   case X86::COND_E:  return X86::COND_E;
3845   case X86::COND_NE: return X86::COND_NE;
3846   case X86::COND_L:  return X86::COND_G;
3847   case X86::COND_LE: return X86::COND_GE;
3848   case X86::COND_G:  return X86::COND_L;
3849   case X86::COND_GE: return X86::COND_LE;
3850   case X86::COND_B:  return X86::COND_A;
3851   case X86::COND_BE: return X86::COND_AE;
3852   case X86::COND_A:  return X86::COND_B;
3853   case X86::COND_AE: return X86::COND_BE;
3854   }
3855 }
3856 
3857 /// Return a set opcode for the given condition and
3858 /// whether it has memory operand.
3859 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
3860   static const uint16_t Opc[16][2] = {
3861     { X86::SETAr,  X86::SETAm  },
3862     { X86::SETAEr, X86::SETAEm },
3863     { X86::SETBr,  X86::SETBm  },
3864     { X86::SETBEr, X86::SETBEm },
3865     { X86::SETEr,  X86::SETEm  },
3866     { X86::SETGr,  X86::SETGm  },
3867     { X86::SETGEr, X86::SETGEm },
3868     { X86::SETLr,  X86::SETLm  },
3869     { X86::SETLEr, X86::SETLEm },
3870     { X86::SETNEr, X86::SETNEm },
3871     { X86::SETNOr, X86::SETNOm },
3872     { X86::SETNPr, X86::SETNPm },
3873     { X86::SETNSr, X86::SETNSm },
3874     { X86::SETOr,  X86::SETOm  },
3875     { X86::SETPr,  X86::SETPm  },
3876     { X86::SETSr,  X86::SETSm  }
3877   };
3878 
3879   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
3880   return Opc[CC][HasMemoryOperand ? 1 : 0];
3881 }
3882 
3883 /// Return a cmov opcode for the given condition,
3884 /// register size in bytes, and operand type.
3885 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3886                               bool HasMemoryOperand) {
3887   static const uint16_t Opc[32][3] = {
3888     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
3889     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3890     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
3891     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3892     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
3893     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
3894     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3895     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
3896     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3897     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3898     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3899     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3900     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3901     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
3902     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
3903     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
3904     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
3905     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3906     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
3907     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3908     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
3909     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
3910     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3911     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
3912     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3913     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3914     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3915     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3916     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3917     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
3918     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
3919     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
3920   };
3921 
3922   assert(CC < 16 && "Can only handle standard cond codes");
3923   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
3924   switch(RegBytes) {
3925   default: llvm_unreachable("Illegal register size!");
3926   case 2: return Opc[Idx][0];
3927   case 4: return Opc[Idx][1];
3928   case 8: return Opc[Idx][2];
3929   }
3930 }
3931 
3932 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
3933   if (!MI.isTerminator()) return false;
3934 
3935   // Conditional branch is a special case.
3936   if (MI.isBranch() && !MI.isBarrier())
3937     return true;
3938   if (!MI.isPredicable())
3939     return true;
3940   return !isPredicated(MI);
3941 }
3942 
3943 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
3944 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
3945 // fallthrough MBB cannot be identified.
3946 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3947                                             MachineBasicBlock *TBB) {
3948   // Look for non-EHPad successors other than TBB. If we find exactly one, it
3949   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
3950   // and fallthrough MBB. If we find more than one, we cannot identify the
3951   // fallthrough MBB and should return nullptr.
3952   MachineBasicBlock *FallthroughBB = nullptr;
3953   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
3954     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
3955       continue;
3956     // Return a nullptr if we found more than one fallthrough successor.
3957     if (FallthroughBB && FallthroughBB != TBB)
3958       return nullptr;
3959     FallthroughBB = *SI;
3960   }
3961   return FallthroughBB;
3962 }
3963 
3964 bool X86InstrInfo::AnalyzeBranchImpl(
3965     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3966     SmallVectorImpl<MachineOperand> &Cond,
3967     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3968 
3969   // Start from the bottom of the block and work up, examining the
3970   // terminator instructions.
3971   MachineBasicBlock::iterator I = MBB.end();
3972   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3973   while (I != MBB.begin()) {
3974     --I;
3975     if (I->isDebugValue())
3976       continue;
3977 
3978     // Working from the bottom, when we see a non-terminator instruction, we're
3979     // done.
3980     if (!isUnpredicatedTerminator(*I))
3981       break;
3982 
3983     // A terminator that isn't a branch can't easily be handled by this
3984     // analysis.
3985     if (!I->isBranch())
3986       return true;
3987 
3988     // Handle unconditional branches.
3989     if (I->getOpcode() == X86::JMP_1) {
3990       UnCondBrIter = I;
3991 
3992       if (!AllowModify) {
3993         TBB = I->getOperand(0).getMBB();
3994         continue;
3995       }
3996 
3997       // If the block has any instructions after a JMP, delete them.
3998       while (std::next(I) != MBB.end())
3999         std::next(I)->eraseFromParent();
4000 
4001       Cond.clear();
4002       FBB = nullptr;
4003 
4004       // Delete the JMP if it's equivalent to a fall-through.
4005       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
4006         TBB = nullptr;
4007         I->eraseFromParent();
4008         I = MBB.end();
4009         UnCondBrIter = MBB.end();
4010         continue;
4011       }
4012 
4013       // TBB is used to indicate the unconditional destination.
4014       TBB = I->getOperand(0).getMBB();
4015       continue;
4016     }
4017 
4018     // Handle conditional branches.
4019     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
4020     if (BranchCode == X86::COND_INVALID)
4021       return true;  // Can't handle indirect branch.
4022 
4023     // Working from the bottom, handle the first conditional branch.
4024     if (Cond.empty()) {
4025       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4026       if (AllowModify && UnCondBrIter != MBB.end() &&
4027           MBB.isLayoutSuccessor(TargetBB)) {
4028         // If we can modify the code and it ends in something like:
4029         //
4030         //     jCC L1
4031         //     jmp L2
4032         //   L1:
4033         //     ...
4034         //   L2:
4035         //
4036         // Then we can change this to:
4037         //
4038         //     jnCC L2
4039         //   L1:
4040         //     ...
4041         //   L2:
4042         //
4043         // Which is a bit more efficient.
4044         // We conditionally jump to the fall-through block.
4045         BranchCode = GetOppositeBranchCondition(BranchCode);
4046         unsigned JNCC = GetCondBranchFromCond(BranchCode);
4047         MachineBasicBlock::iterator OldInst = I;
4048 
4049         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
4050           .addMBB(UnCondBrIter->getOperand(0).getMBB());
4051         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
4052           .addMBB(TargetBB);
4053 
4054         OldInst->eraseFromParent();
4055         UnCondBrIter->eraseFromParent();
4056 
4057         // Restart the analysis.
4058         UnCondBrIter = MBB.end();
4059         I = MBB.end();
4060         continue;
4061       }
4062 
4063       FBB = TBB;
4064       TBB = I->getOperand(0).getMBB();
4065       Cond.push_back(MachineOperand::CreateImm(BranchCode));
4066       CondBranches.push_back(I);
4067       continue;
4068     }
4069 
4070     // Handle subsequent conditional branches. Only handle the case where all
4071     // conditional branches branch to the same destination and their condition
4072     // opcodes fit one of the special multi-branch idioms.
4073     assert(Cond.size() == 1);
4074     assert(TBB);
4075 
4076     // If the conditions are the same, we can leave them alone.
4077     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
4078     auto NewTBB = I->getOperand(0).getMBB();
4079     if (OldBranchCode == BranchCode && TBB == NewTBB)
4080       continue;
4081 
4082     // If they differ, see if they fit one of the known patterns. Theoretically,
4083     // we could handle more patterns here, but we shouldn't expect to see them
4084     // if instruction selection has done a reasonable job.
4085     if (TBB == NewTBB &&
4086                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4087                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
4088       BranchCode = X86::COND_NE_OR_P;
4089     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4090                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4091       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4092         return true;
4093 
4094       // X86::COND_E_AND_NP usually has two different branch destinations.
4095       //
4096       // JP B1
4097       // JE B2
4098       // JMP B1
4099       // B1:
4100       // B2:
4101       //
4102       // Here this condition branches to B2 only if NP && E. It has another
4103       // equivalent form:
4104       //
4105       // JNE B1
4106       // JNP B2
4107       // JMP B1
4108       // B1:
4109       // B2:
4110       //
4111       // Similarly it branches to B2 only if E && NP. That is why this condition
4112       // is named with COND_E_AND_NP.
4113       BranchCode = X86::COND_E_AND_NP;
4114     } else
4115       return true;
4116 
4117     // Update the MachineOperand.
4118     Cond[0].setImm(BranchCode);
4119     CondBranches.push_back(I);
4120   }
4121 
4122   return false;
4123 }
4124 
4125 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
4126                                  MachineBasicBlock *&TBB,
4127                                  MachineBasicBlock *&FBB,
4128                                  SmallVectorImpl<MachineOperand> &Cond,
4129                                  bool AllowModify) const {
4130   SmallVector<MachineInstr *, 4> CondBranches;
4131   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4132 }
4133 
4134 bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB,
4135                                           MachineBranchPredicate &MBP,
4136                                           bool AllowModify) const {
4137   using namespace std::placeholders;
4138 
4139   SmallVector<MachineOperand, 4> Cond;
4140   SmallVector<MachineInstr *, 4> CondBranches;
4141   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4142                         AllowModify))
4143     return true;
4144 
4145   if (Cond.size() != 1)
4146     return true;
4147 
4148   assert(MBP.TrueDest && "expected!");
4149 
4150   if (!MBP.FalseDest)
4151     MBP.FalseDest = MBB.getNextNode();
4152 
4153   const TargetRegisterInfo *TRI = &getRegisterInfo();
4154 
4155   MachineInstr *ConditionDef = nullptr;
4156   bool SingleUseCondition = true;
4157 
4158   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4159     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4160       ConditionDef = &*I;
4161       break;
4162     }
4163 
4164     if (I->readsRegister(X86::EFLAGS, TRI))
4165       SingleUseCondition = false;
4166   }
4167 
4168   if (!ConditionDef)
4169     return true;
4170 
4171   if (SingleUseCondition) {
4172     for (auto *Succ : MBB.successors())
4173       if (Succ->isLiveIn(X86::EFLAGS))
4174         SingleUseCondition = false;
4175   }
4176 
4177   MBP.ConditionDef = ConditionDef;
4178   MBP.SingleUseCondition = SingleUseCondition;
4179 
4180   // Currently we only recognize the simple pattern:
4181   //
4182   //   test %reg, %reg
4183   //   je %label
4184   //
4185   const unsigned TestOpcode =
4186       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4187 
4188   if (ConditionDef->getOpcode() == TestOpcode &&
4189       ConditionDef->getNumOperands() == 3 &&
4190       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4191       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4192     MBP.LHS = ConditionDef->getOperand(0);
4193     MBP.RHS = MachineOperand::CreateImm(0);
4194     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4195                         ? MachineBranchPredicate::PRED_NE
4196                         : MachineBranchPredicate::PRED_EQ;
4197     return false;
4198   }
4199 
4200   return true;
4201 }
4202 
4203 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
4204   MachineBasicBlock::iterator I = MBB.end();
4205   unsigned Count = 0;
4206 
4207   while (I != MBB.begin()) {
4208     --I;
4209     if (I->isDebugValue())
4210       continue;
4211     if (I->getOpcode() != X86::JMP_1 &&
4212         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
4213       break;
4214     // Remove the branch.
4215     I->eraseFromParent();
4216     I = MBB.end();
4217     ++Count;
4218   }
4219 
4220   return Count;
4221 }
4222 
4223 unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB,
4224                                     MachineBasicBlock *TBB,
4225                                     MachineBasicBlock *FBB,
4226                                     ArrayRef<MachineOperand> Cond,
4227                                     const DebugLoc &DL) const {
4228   // Shouldn't be a fall through.
4229   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
4230   assert((Cond.size() == 1 || Cond.size() == 0) &&
4231          "X86 branch conditions have one component!");
4232 
4233   if (Cond.empty()) {
4234     // Unconditional branch?
4235     assert(!FBB && "Unconditional branch with multiple successors!");
4236     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
4237     return 1;
4238   }
4239 
4240   // If FBB is null, it is implied to be a fall-through block.
4241   bool FallThru = FBB == nullptr;
4242 
4243   // Conditional branch.
4244   unsigned Count = 0;
4245   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4246   switch (CC) {
4247   case X86::COND_NE_OR_P:
4248     // Synthesize NE_OR_P with two branches.
4249     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
4250     ++Count;
4251     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
4252     ++Count;
4253     break;
4254   case X86::COND_E_AND_NP:
4255     // Use the next block of MBB as FBB if it is null.
4256     if (FBB == nullptr) {
4257       FBB = getFallThroughMBB(&MBB, TBB);
4258       assert(FBB && "MBB cannot be the last block in function when the false "
4259                     "body is a fall-through.");
4260     }
4261     // Synthesize COND_E_AND_NP with two branches.
4262     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4263     ++Count;
4264     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4265     ++Count;
4266     break;
4267   default: {
4268     unsigned Opc = GetCondBranchFromCond(CC);
4269     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
4270     ++Count;
4271   }
4272   }
4273   if (!FallThru) {
4274     // Two-way Conditional branch. Insert the second branch.
4275     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
4276     ++Count;
4277   }
4278   return Count;
4279 }
4280 
4281 bool X86InstrInfo::
4282 canInsertSelect(const MachineBasicBlock &MBB,
4283                 ArrayRef<MachineOperand> Cond,
4284                 unsigned TrueReg, unsigned FalseReg,
4285                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4286   // Not all subtargets have cmov instructions.
4287   if (!Subtarget.hasCMov())
4288     return false;
4289   if (Cond.size() != 1)
4290     return false;
4291   // We cannot do the composite conditions, at least not in SSA form.
4292   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4293     return false;
4294 
4295   // Check register classes.
4296   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4297   const TargetRegisterClass *RC =
4298     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4299   if (!RC)
4300     return false;
4301 
4302   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4303   if (X86::GR16RegClass.hasSubClassEq(RC) ||
4304       X86::GR32RegClass.hasSubClassEq(RC) ||
4305       X86::GR64RegClass.hasSubClassEq(RC)) {
4306     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4307     // Bridge. Probably Ivy Bridge as well.
4308     CondCycles = 2;
4309     TrueCycles = 2;
4310     FalseCycles = 2;
4311     return true;
4312   }
4313 
4314   // Can't do vectors.
4315   return false;
4316 }
4317 
4318 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4319                                 MachineBasicBlock::iterator I,
4320                                 const DebugLoc &DL, unsigned DstReg,
4321                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
4322                                 unsigned FalseReg) const {
4323   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4324   assert(Cond.size() == 1 && "Invalid Cond array");
4325   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4326                                  MRI.getRegClass(DstReg)->getSize(),
4327                                  false /*HasMemoryOperand*/);
4328   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
4329 }
4330 
4331 /// Test if the given register is a physical h register.
4332 static bool isHReg(unsigned Reg) {
4333   return X86::GR8_ABCD_HRegClass.contains(Reg);
4334 }
4335 
4336 // Try and copy between VR128/VR64 and GR64 registers.
4337 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
4338                                         const X86Subtarget &Subtarget) {
4339 
4340   // SrcReg(VR128) -> DestReg(GR64)
4341   // SrcReg(VR64)  -> DestReg(GR64)
4342   // SrcReg(GR64)  -> DestReg(VR128)
4343   // SrcReg(GR64)  -> DestReg(VR64)
4344 
4345   bool HasAVX = Subtarget.hasAVX();
4346   bool HasAVX512 = Subtarget.hasAVX512();
4347   if (X86::GR64RegClass.contains(DestReg)) {
4348     if (X86::VR128XRegClass.contains(SrcReg))
4349       // Copy from a VR128 register to a GR64 register.
4350       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
4351                                                X86::MOVPQIto64rr);
4352     if (X86::VR64RegClass.contains(SrcReg))
4353       // Copy from a VR64 register to a GR64 register.
4354       return X86::MMX_MOVD64from64rr;
4355   } else if (X86::GR64RegClass.contains(SrcReg)) {
4356     // Copy from a GR64 register to a VR128 register.
4357     if (X86::VR128XRegClass.contains(DestReg))
4358       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
4359                                                X86::MOV64toPQIrr);
4360     // Copy from a GR64 register to a VR64 register.
4361     if (X86::VR64RegClass.contains(DestReg))
4362       return X86::MMX_MOVD64to64rr;
4363   }
4364 
4365   // SrcReg(FR32) -> DestReg(GR32)
4366   // SrcReg(GR32) -> DestReg(FR32)
4367 
4368   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
4369     // Copy from a FR32 register to a GR32 register.
4370     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
4371 
4372   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4373     // Copy from a GR32 register to a FR32 register.
4374     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
4375   return 0;
4376 }
4377 
4378 static bool isMaskRegClass(const TargetRegisterClass *RC) {
4379   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4380   return X86::VK16RegClass.hasSubClassEq(RC);
4381 }
4382 
4383 static bool MaskRegClassContains(unsigned Reg) {
4384   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4385   return X86::VK16RegClass.contains(Reg);
4386 }
4387 
4388 static bool GRRegClassContains(unsigned Reg) {
4389   return X86::GR64RegClass.contains(Reg) ||
4390          X86::GR32RegClass.contains(Reg) ||
4391          X86::GR16RegClass.contains(Reg) ||
4392          X86::GR8RegClass.contains(Reg);
4393 }
4394 static
4395 unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4396   if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
4397     DestReg = getX86SubSuperRegister(DestReg, 32);
4398     return X86::KMOVBrk;
4399   }
4400   if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
4401     SrcReg = getX86SubSuperRegister(SrcReg, 32);
4402     return X86::KMOVBkr;
4403   }
4404   return 0;
4405 }
4406 
4407 static
4408 unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4409   if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4410     return X86::KMOVQkk;
4411   if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4412     return X86::KMOVDrk;
4413   if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4414     return X86::KMOVQrk;
4415   if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4416     return X86::KMOVDkr;
4417   if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4418     return X86::KMOVQkr;
4419   return 0;
4420 }
4421 
4422 static
4423 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4424                                   const X86Subtarget &Subtarget)
4425 {
4426   if (Subtarget.hasDQI())
4427     if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4428       return Opc;
4429   if (Subtarget.hasBWI())
4430     if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4431       return Opc;
4432   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
4433       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
4434       X86::VR512RegClass.contains(DestReg, SrcReg)) {
4435      DestReg = get512BitSuperRegister(DestReg);
4436      SrcReg = get512BitSuperRegister(SrcReg);
4437      return X86::VMOVAPSZrr;
4438   }
4439   if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
4440     return X86::KMOVWkk;
4441   if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
4442     SrcReg = getX86SubSuperRegister(SrcReg, 32);
4443     return X86::KMOVWkr;
4444   }
4445   if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
4446     DestReg = getX86SubSuperRegister(DestReg, 32);
4447     return X86::KMOVWrk;
4448   }
4449   return 0;
4450 }
4451 
4452 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4453                                MachineBasicBlock::iterator MI,
4454                                const DebugLoc &DL, unsigned DestReg,
4455                                unsigned SrcReg, bool KillSrc) const {
4456   // First deal with the normal symmetric copies.
4457   bool HasAVX = Subtarget.hasAVX();
4458   bool HasAVX512 = Subtarget.hasAVX512();
4459   unsigned Opc = 0;
4460   if (X86::GR64RegClass.contains(DestReg, SrcReg))
4461     Opc = X86::MOV64rr;
4462   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4463     Opc = X86::MOV32rr;
4464   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4465     Opc = X86::MOV16rr;
4466   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4467     // Copying to or from a physical H register on x86-64 requires a NOREX
4468     // move.  Otherwise use a normal move.
4469     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
4470         Subtarget.is64Bit()) {
4471       Opc = X86::MOV8rr_NOREX;
4472       // Both operands must be encodable without an REX prefix.
4473       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4474              "8-bit H register can not be copied outside GR8_NOREX");
4475     } else
4476       Opc = X86::MOV8rr;
4477   }
4478   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4479     Opc = X86::MMX_MOVQ64rr;
4480   else if (HasAVX512)
4481     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
4482   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
4483     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4484   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4485     Opc = X86::VMOVAPSYrr;
4486   if (!Opc)
4487     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4488 
4489   if (Opc) {
4490     BuildMI(MBB, MI, DL, get(Opc), DestReg)
4491       .addReg(SrcReg, getKillRegState(KillSrc));
4492     return;
4493   }
4494 
4495   bool FromEFLAGS = SrcReg == X86::EFLAGS;
4496   bool ToEFLAGS = DestReg == X86::EFLAGS;
4497   int Reg = FromEFLAGS ? DestReg : SrcReg;
4498   bool is32 = X86::GR32RegClass.contains(Reg);
4499   bool is64 = X86::GR64RegClass.contains(Reg);
4500 
4501   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
4502     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4503     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4504     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4505     int Pop = is64 ? X86::POP64r : X86::POP32r;
4506     int PopF = is64 ? X86::POPF64 : X86::POPF32;
4507     int AX = is64 ? X86::RAX : X86::EAX;
4508 
4509     if (!Subtarget.hasLAHFSAHF()) {
4510       assert(Subtarget.is64Bit() &&
4511              "Not having LAHF/SAHF only happens on 64-bit.");
4512       // Moving EFLAGS to / from another register requires a push and a pop.
4513       // Notice that we have to adjust the stack if we don't want to clobber the
4514       // first frame index. See X86FrameLowering.cpp - usesTheStack.
4515       if (FromEFLAGS) {
4516         BuildMI(MBB, MI, DL, get(PushF));
4517         BuildMI(MBB, MI, DL, get(Pop), DestReg);
4518       }
4519       if (ToEFLAGS) {
4520         BuildMI(MBB, MI, DL, get(Push))
4521             .addReg(SrcReg, getKillRegState(KillSrc));
4522         BuildMI(MBB, MI, DL, get(PopF));
4523       }
4524       return;
4525     }
4526 
4527     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4528     // inefficient. Instead:
4529     //   - Save the overflow flag OF into AL using SETO, and restore it using a
4530     //     signed 8-bit addition of AL and INT8_MAX.
4531     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4532     //     using LAHF/SAHF.
4533     //   - When RAX/EAX is live and isn't the destination register, make sure it
4534     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4535     //     the flags.
4536     // This approach is ~2.25x faster than using PUSHF/POPF.
4537     //
4538     // This is still somewhat inefficient because we don't know which flags are
4539     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4540     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4541     //
4542     // PUSHF/POPF is also potentially incorrect because it affects other flags
4543     // such as TF/IF/DF, which LLVM doesn't model.
4544     //
4545     // Notice that we have to adjust the stack if we don't want to clobber the
4546     // first frame index.
4547     // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
4548 
4549     const TargetRegisterInfo *TRI = &getRegisterInfo();
4550     MachineBasicBlock::LivenessQueryResult LQR =
4551         MBB.computeRegisterLiveness(TRI, AX, MI);
4552     // We do not want to save and restore AX if we do not have to.
4553     // Moreover, if we do so whereas AX is dead, we would need to set
4554     // an undef flag on the use of AX, otherwise the verifier will
4555     // complain that we read an undef value.
4556     // We do not want to change the behavior of the machine verifier
4557     // as this is usually wrong to read an undef value.
4558     if (MachineBasicBlock::LQR_Unknown == LQR) {
4559       LivePhysRegs LPR(TRI);
4560       LPR.addLiveOuts(MBB);
4561       MachineBasicBlock::iterator I = MBB.end();
4562       while (I != MI) {
4563         --I;
4564         LPR.stepBackward(*I);
4565       }
4566       // AX contains the top most register in the aliasing hierarchy.
4567       // It may not be live, but one of its aliases may be.
4568       for (MCRegAliasIterator AI(AX, TRI, true);
4569            AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
4570         LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
4571                                 : MachineBasicBlock::LQR_Dead;
4572     }
4573     bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4574     if (!AXDead)
4575       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
4576     if (FromEFLAGS) {
4577       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4578       BuildMI(MBB, MI, DL, get(X86::LAHF));
4579       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
4580     }
4581     if (ToEFLAGS) {
4582       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4583       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4584           .addReg(X86::AL)
4585           .addImm(INT8_MAX);
4586       BuildMI(MBB, MI, DL, get(X86::SAHF));
4587     }
4588     if (!AXDead)
4589       BuildMI(MBB, MI, DL, get(Pop), AX);
4590     return;
4591   }
4592 
4593   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4594                << " to " << RI.getName(DestReg) << '\n');
4595   llvm_unreachable("Cannot emit physreg copy instruction");
4596 }
4597 
4598 static unsigned getLoadStoreMaskRegOpcode(const TargetRegisterClass *RC,
4599                                           bool load) {
4600   switch (RC->getSize()) {
4601   default:
4602     llvm_unreachable("Unknown spill size");
4603   case 2:
4604     return load ? X86::KMOVWkm : X86::KMOVWmk;
4605   case 4:
4606     return load ? X86::KMOVDkm : X86::KMOVDmk;
4607   case 8:
4608     return load ? X86::KMOVQkm : X86::KMOVQmk;
4609   }
4610 }
4611 
4612 static unsigned getLoadStoreRegOpcode(unsigned Reg,
4613                                       const TargetRegisterClass *RC,
4614                                       bool isStackAligned,
4615                                       const X86Subtarget &STI,
4616                                       bool load) {
4617   if (STI.hasAVX512()) {
4618     if (isMaskRegClass(RC))
4619       return getLoadStoreMaskRegOpcode(RC, load);
4620     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
4621       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
4622     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
4623       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
4624     if (X86::VR512RegClass.hasSubClassEq(RC))
4625       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4626   }
4627 
4628   bool HasAVX = STI.hasAVX();
4629   switch (RC->getSize()) {
4630   default:
4631     llvm_unreachable("Unknown spill size");
4632   case 1:
4633     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
4634     if (STI.is64Bit())
4635       // Copying to or from a physical H register on x86-64 requires a NOREX
4636       // move.  Otherwise use a normal move.
4637       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4638         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4639     return load ? X86::MOV8rm : X86::MOV8mr;
4640   case 2:
4641     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4642     return load ? X86::MOV16rm : X86::MOV16mr;
4643   case 4:
4644     if (X86::GR32RegClass.hasSubClassEq(RC))
4645       return load ? X86::MOV32rm : X86::MOV32mr;
4646     if (X86::FR32RegClass.hasSubClassEq(RC))
4647       return load ?
4648         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4649         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
4650     if (X86::RFP32RegClass.hasSubClassEq(RC))
4651       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4652     llvm_unreachable("Unknown 4-byte regclass");
4653   case 8:
4654     if (X86::GR64RegClass.hasSubClassEq(RC))
4655       return load ? X86::MOV64rm : X86::MOV64mr;
4656     if (X86::FR64RegClass.hasSubClassEq(RC))
4657       return load ?
4658         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4659         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
4660     if (X86::VR64RegClass.hasSubClassEq(RC))
4661       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4662     if (X86::RFP64RegClass.hasSubClassEq(RC))
4663       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4664     llvm_unreachable("Unknown 8-byte regclass");
4665   case 10:
4666     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
4667     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
4668   case 16: {
4669     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4670             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
4671     // If stack is realigned we can use aligned stores.
4672     if (X86::VR128RegClass.hasSubClassEq(RC)) {
4673       if (isStackAligned)
4674         return load ? (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm)
4675                     : (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4676       else
4677         return load ? (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm)
4678                     : (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4679     }
4680     assert(STI.hasVLX() && "Using extended register requires VLX");
4681     if (isStackAligned)
4682       return load ? X86::VMOVAPSZ128rm : X86::VMOVAPSZ128mr;
4683     else
4684       return load ? X86::VMOVUPSZ128rm : X86::VMOVUPSZ128mr;
4685   }
4686   case 32:
4687     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4688             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
4689     // If stack is realigned we can use aligned stores.
4690     if (X86::VR256RegClass.hasSubClassEq(RC)) {
4691       if (isStackAligned)
4692         return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4693       else
4694         return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
4695     }
4696     assert(STI.hasVLX() && "Using extended register requires VLX");
4697     if (isStackAligned)
4698       return load ? X86::VMOVAPSZ256rm : X86::VMOVAPSZ256mr;
4699     else
4700       return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr;
4701   case 64:
4702     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4703     assert(STI.hasVLX() && "Using 512-bit register requires AVX512");
4704     if (isStackAligned)
4705       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4706     else
4707       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4708   }
4709 }
4710 
4711 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
4712                                          int64_t &Offset,
4713                                          const TargetRegisterInfo *TRI) const {
4714   const MCInstrDesc &Desc = MemOp->getDesc();
4715   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
4716   if (MemRefBegin < 0)
4717     return false;
4718 
4719   MemRefBegin += X86II::getOperandBias(Desc);
4720 
4721   MachineOperand &BaseMO = MemOp->getOperand(MemRefBegin + X86::AddrBaseReg);
4722   if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4723     return false;
4724 
4725   BaseReg = BaseMO.getReg();
4726   if (MemOp->getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4727     return false;
4728 
4729   if (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
4730       X86::NoRegister)
4731     return false;
4732 
4733   const MachineOperand &DispMO = MemOp->getOperand(MemRefBegin + X86::AddrDisp);
4734 
4735   // Displacement can be symbolic
4736   if (!DispMO.isImm())
4737     return false;
4738 
4739   Offset = DispMO.getImm();
4740 
4741   return (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4742           X86::NoRegister);
4743 }
4744 
4745 static unsigned getStoreRegOpcode(unsigned SrcReg,
4746                                   const TargetRegisterClass *RC,
4747                                   bool isStackAligned,
4748                                   const X86Subtarget &STI) {
4749   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
4750 }
4751 
4752 
4753 static unsigned getLoadRegOpcode(unsigned DestReg,
4754                                  const TargetRegisterClass *RC,
4755                                  bool isStackAligned,
4756                                  const X86Subtarget &STI) {
4757   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
4758 }
4759 
4760 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4761                                        MachineBasicBlock::iterator MI,
4762                                        unsigned SrcReg, bool isKill, int FrameIdx,
4763                                        const TargetRegisterClass *RC,
4764                                        const TargetRegisterInfo *TRI) const {
4765   const MachineFunction &MF = *MBB.getParent();
4766   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4767          "Stack slot too small for store");
4768   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4769   bool isAligned =
4770       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4771       RI.canRealignStack(MF);
4772   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4773   DebugLoc DL = MBB.findDebugLoc(MI);
4774   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
4775     .addReg(SrcReg, getKillRegState(isKill));
4776 }
4777 
4778 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4779                                   bool isKill,
4780                                   SmallVectorImpl<MachineOperand> &Addr,
4781                                   const TargetRegisterClass *RC,
4782                                   MachineInstr::mmo_iterator MMOBegin,
4783                                   MachineInstr::mmo_iterator MMOEnd,
4784                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
4785   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4786   bool isAligned = MMOBegin != MMOEnd &&
4787                    (*MMOBegin)->getAlignment() >= Alignment;
4788   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4789   DebugLoc DL;
4790   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
4791   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4792     MIB.addOperand(Addr[i]);
4793   MIB.addReg(SrcReg, getKillRegState(isKill));
4794   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4795   NewMIs.push_back(MIB);
4796 }
4797 
4798 
4799 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4800                                         MachineBasicBlock::iterator MI,
4801                                         unsigned DestReg, int FrameIdx,
4802                                         const TargetRegisterClass *RC,
4803                                         const TargetRegisterInfo *TRI) const {
4804   const MachineFunction &MF = *MBB.getParent();
4805   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4806   bool isAligned =
4807       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4808       RI.canRealignStack(MF);
4809   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4810   DebugLoc DL = MBB.findDebugLoc(MI);
4811   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
4812 }
4813 
4814 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
4815                                  SmallVectorImpl<MachineOperand> &Addr,
4816                                  const TargetRegisterClass *RC,
4817                                  MachineInstr::mmo_iterator MMOBegin,
4818                                  MachineInstr::mmo_iterator MMOEnd,
4819                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
4820   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4821   bool isAligned = MMOBegin != MMOEnd &&
4822                    (*MMOBegin)->getAlignment() >= Alignment;
4823   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4824   DebugLoc DL;
4825   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
4826   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4827     MIB.addOperand(Addr[i]);
4828   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4829   NewMIs.push_back(MIB);
4830 }
4831 
4832 bool X86InstrInfo::
4833 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
4834                int &CmpMask, int &CmpValue) const {
4835   switch (MI->getOpcode()) {
4836   default: break;
4837   case X86::CMP64ri32:
4838   case X86::CMP64ri8:
4839   case X86::CMP32ri:
4840   case X86::CMP32ri8:
4841   case X86::CMP16ri:
4842   case X86::CMP16ri8:
4843   case X86::CMP8ri:
4844     SrcReg = MI->getOperand(0).getReg();
4845     SrcReg2 = 0;
4846     CmpMask = ~0;
4847     CmpValue = MI->getOperand(1).getImm();
4848     return true;
4849   // A SUB can be used to perform comparison.
4850   case X86::SUB64rm:
4851   case X86::SUB32rm:
4852   case X86::SUB16rm:
4853   case X86::SUB8rm:
4854     SrcReg = MI->getOperand(1).getReg();
4855     SrcReg2 = 0;
4856     CmpMask = ~0;
4857     CmpValue = 0;
4858     return true;
4859   case X86::SUB64rr:
4860   case X86::SUB32rr:
4861   case X86::SUB16rr:
4862   case X86::SUB8rr:
4863     SrcReg = MI->getOperand(1).getReg();
4864     SrcReg2 = MI->getOperand(2).getReg();
4865     CmpMask = ~0;
4866     CmpValue = 0;
4867     return true;
4868   case X86::SUB64ri32:
4869   case X86::SUB64ri8:
4870   case X86::SUB32ri:
4871   case X86::SUB32ri8:
4872   case X86::SUB16ri:
4873   case X86::SUB16ri8:
4874   case X86::SUB8ri:
4875     SrcReg = MI->getOperand(1).getReg();
4876     SrcReg2 = 0;
4877     CmpMask = ~0;
4878     CmpValue = MI->getOperand(2).getImm();
4879     return true;
4880   case X86::CMP64rr:
4881   case X86::CMP32rr:
4882   case X86::CMP16rr:
4883   case X86::CMP8rr:
4884     SrcReg = MI->getOperand(0).getReg();
4885     SrcReg2 = MI->getOperand(1).getReg();
4886     CmpMask = ~0;
4887     CmpValue = 0;
4888     return true;
4889   case X86::TEST8rr:
4890   case X86::TEST16rr:
4891   case X86::TEST32rr:
4892   case X86::TEST64rr:
4893     SrcReg = MI->getOperand(0).getReg();
4894     if (MI->getOperand(1).getReg() != SrcReg) return false;
4895     // Compare against zero.
4896     SrcReg2 = 0;
4897     CmpMask = ~0;
4898     CmpValue = 0;
4899     return true;
4900   }
4901   return false;
4902 }
4903 
4904 /// Check whether the first instruction, whose only
4905 /// purpose is to update flags, can be made redundant.
4906 /// CMPrr can be made redundant by SUBrr if the operands are the same.
4907 /// This function can be extended later on.
4908 /// SrcReg, SrcRegs: register operands for FlagI.
4909 /// ImmValue: immediate for FlagI if it takes an immediate.
4910 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4911                                         unsigned SrcReg2, int ImmValue,
4912                                         MachineInstr *OI) {
4913   if (((FlagI->getOpcode() == X86::CMP64rr &&
4914         OI->getOpcode() == X86::SUB64rr) ||
4915        (FlagI->getOpcode() == X86::CMP32rr &&
4916         OI->getOpcode() == X86::SUB32rr)||
4917        (FlagI->getOpcode() == X86::CMP16rr &&
4918         OI->getOpcode() == X86::SUB16rr)||
4919        (FlagI->getOpcode() == X86::CMP8rr &&
4920         OI->getOpcode() == X86::SUB8rr)) &&
4921       ((OI->getOperand(1).getReg() == SrcReg &&
4922         OI->getOperand(2).getReg() == SrcReg2) ||
4923        (OI->getOperand(1).getReg() == SrcReg2 &&
4924         OI->getOperand(2).getReg() == SrcReg)))
4925     return true;
4926 
4927   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4928         OI->getOpcode() == X86::SUB64ri32) ||
4929        (FlagI->getOpcode() == X86::CMP64ri8 &&
4930         OI->getOpcode() == X86::SUB64ri8) ||
4931        (FlagI->getOpcode() == X86::CMP32ri &&
4932         OI->getOpcode() == X86::SUB32ri) ||
4933        (FlagI->getOpcode() == X86::CMP32ri8 &&
4934         OI->getOpcode() == X86::SUB32ri8) ||
4935        (FlagI->getOpcode() == X86::CMP16ri &&
4936         OI->getOpcode() == X86::SUB16ri) ||
4937        (FlagI->getOpcode() == X86::CMP16ri8 &&
4938         OI->getOpcode() == X86::SUB16ri8) ||
4939        (FlagI->getOpcode() == X86::CMP8ri &&
4940         OI->getOpcode() == X86::SUB8ri)) &&
4941       OI->getOperand(1).getReg() == SrcReg &&
4942       OI->getOperand(2).getImm() == ImmValue)
4943     return true;
4944   return false;
4945 }
4946 
4947 /// Check whether the definition can be converted
4948 /// to remove a comparison against zero.
4949 inline static bool isDefConvertible(MachineInstr *MI) {
4950   switch (MI->getOpcode()) {
4951   default: return false;
4952 
4953   // The shift instructions only modify ZF if their shift count is non-zero.
4954   // N.B.: The processor truncates the shift count depending on the encoding.
4955   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
4956   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
4957      return getTruncatedShiftCount(MI, 2) != 0;
4958 
4959   // Some left shift instructions can be turned into LEA instructions but only
4960   // if their flags aren't used. Avoid transforming such instructions.
4961   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
4962     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4963     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4964     return ShAmt != 0;
4965   }
4966 
4967   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4968   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4969      return getTruncatedShiftCount(MI, 3) != 0;
4970 
4971   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4972   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
4973   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
4974   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
4975   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
4976   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
4977   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4978   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
4979   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
4980   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
4981   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
4982   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
4983   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4984   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
4985   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
4986   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
4987   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
4988   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4989   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
4990   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
4991   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
4992   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
4993   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
4994   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
4995   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
4996   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
4997   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
4998   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4999   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
5000   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
5001   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
5002   case X86::ADC32ri:   case X86::ADC32ri8:
5003   case X86::ADC32rr:   case X86::ADC64ri32:
5004   case X86::ADC64ri8:  case X86::ADC64rr:
5005   case X86::SBB32ri:   case X86::SBB32ri8:
5006   case X86::SBB32rr:   case X86::SBB64ri32:
5007   case X86::SBB64ri8:  case X86::SBB64rr:
5008   case X86::ANDN32rr:  case X86::ANDN32rm:
5009   case X86::ANDN64rr:  case X86::ANDN64rm:
5010   case X86::BEXTR32rr: case X86::BEXTR64rr:
5011   case X86::BEXTR32rm: case X86::BEXTR64rm:
5012   case X86::BLSI32rr:  case X86::BLSI32rm:
5013   case X86::BLSI64rr:  case X86::BLSI64rm:
5014   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
5015   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
5016   case X86::BLSR32rr:  case X86::BLSR32rm:
5017   case X86::BLSR64rr:  case X86::BLSR64rm:
5018   case X86::BZHI32rr:  case X86::BZHI32rm:
5019   case X86::BZHI64rr:  case X86::BZHI64rm:
5020   case X86::LZCNT16rr: case X86::LZCNT16rm:
5021   case X86::LZCNT32rr: case X86::LZCNT32rm:
5022   case X86::LZCNT64rr: case X86::LZCNT64rm:
5023   case X86::POPCNT16rr:case X86::POPCNT16rm:
5024   case X86::POPCNT32rr:case X86::POPCNT32rm:
5025   case X86::POPCNT64rr:case X86::POPCNT64rm:
5026   case X86::TZCNT16rr: case X86::TZCNT16rm:
5027   case X86::TZCNT32rr: case X86::TZCNT32rm:
5028   case X86::TZCNT64rr: case X86::TZCNT64rm:
5029     return true;
5030   }
5031 }
5032 
5033 /// Check whether the use can be converted to remove a comparison against zero.
5034 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
5035   switch (MI->getOpcode()) {
5036   default: return X86::COND_INVALID;
5037   case X86::LZCNT16rr: case X86::LZCNT16rm:
5038   case X86::LZCNT32rr: case X86::LZCNT32rm:
5039   case X86::LZCNT64rr: case X86::LZCNT64rm:
5040     return X86::COND_B;
5041   case X86::POPCNT16rr:case X86::POPCNT16rm:
5042   case X86::POPCNT32rr:case X86::POPCNT32rm:
5043   case X86::POPCNT64rr:case X86::POPCNT64rm:
5044     return X86::COND_E;
5045   case X86::TZCNT16rr: case X86::TZCNT16rm:
5046   case X86::TZCNT32rr: case X86::TZCNT32rm:
5047   case X86::TZCNT64rr: case X86::TZCNT64rm:
5048     return X86::COND_B;
5049   }
5050 }
5051 
5052 /// Check if there exists an earlier instruction that
5053 /// operates on the same source operands and sets flags in the same way as
5054 /// Compare; remove Compare if possible.
5055 bool X86InstrInfo::
5056 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
5057                      int CmpMask, int CmpValue,
5058                      const MachineRegisterInfo *MRI) const {
5059   // Check whether we can replace SUB with CMP.
5060   unsigned NewOpcode = 0;
5061   switch (CmpInstr->getOpcode()) {
5062   default: break;
5063   case X86::SUB64ri32:
5064   case X86::SUB64ri8:
5065   case X86::SUB32ri:
5066   case X86::SUB32ri8:
5067   case X86::SUB16ri:
5068   case X86::SUB16ri8:
5069   case X86::SUB8ri:
5070   case X86::SUB64rm:
5071   case X86::SUB32rm:
5072   case X86::SUB16rm:
5073   case X86::SUB8rm:
5074   case X86::SUB64rr:
5075   case X86::SUB32rr:
5076   case X86::SUB16rr:
5077   case X86::SUB8rr: {
5078     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
5079       return false;
5080     // There is no use of the destination register, we can replace SUB with CMP.
5081     switch (CmpInstr->getOpcode()) {
5082     default: llvm_unreachable("Unreachable!");
5083     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
5084     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
5085     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
5086     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
5087     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
5088     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
5089     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
5090     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
5091     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5092     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
5093     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
5094     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
5095     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
5096     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
5097     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
5098     }
5099     CmpInstr->setDesc(get(NewOpcode));
5100     CmpInstr->RemoveOperand(0);
5101     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5102     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5103         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5104       return false;
5105   }
5106   }
5107 
5108   // Get the unique definition of SrcReg.
5109   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5110   if (!MI) return false;
5111 
5112   // CmpInstr is the first instruction of the BB.
5113   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5114 
5115   // If we are comparing against zero, check whether we can use MI to update
5116   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5117   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
5118   if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
5119     return false;
5120 
5121   // If we have a use of the source register between the def and our compare
5122   // instruction we can eliminate the compare iff the use sets EFLAGS in the
5123   // right way.
5124   bool ShouldUpdateCC = false;
5125   X86::CondCode NewCC = X86::COND_INVALID;
5126   if (IsCmpZero && !isDefConvertible(MI)) {
5127     // Scan forward from the use until we hit the use we're looking for or the
5128     // compare instruction.
5129     for (MachineBasicBlock::iterator J = MI;; ++J) {
5130       // Do we have a convertible instruction?
5131       NewCC = isUseDefConvertible(J);
5132       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5133           J->getOperand(1).getReg() == SrcReg) {
5134         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5135         ShouldUpdateCC = true; // Update CC later on.
5136         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5137         // with the new def.
5138         MI = Def = J;
5139         break;
5140       }
5141 
5142       if (J == I)
5143         return false;
5144     }
5145   }
5146 
5147   // We are searching for an earlier instruction that can make CmpInstr
5148   // redundant and that instruction will be saved in Sub.
5149   MachineInstr *Sub = nullptr;
5150   const TargetRegisterInfo *TRI = &getRegisterInfo();
5151 
5152   // We iterate backward, starting from the instruction before CmpInstr and
5153   // stop when reaching the definition of a source register or done with the BB.
5154   // RI points to the instruction before CmpInstr.
5155   // If the definition is in this basic block, RE points to the definition;
5156   // otherwise, RE is the rend of the basic block.
5157   MachineBasicBlock::reverse_iterator
5158       RI = MachineBasicBlock::reverse_iterator(I),
5159       RE = CmpInstr->getParent() == MI->getParent() ?
5160            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
5161            CmpInstr->getParent()->rend();
5162   MachineInstr *Movr0Inst = nullptr;
5163   for (; RI != RE; ++RI) {
5164     MachineInstr *Instr = &*RI;
5165     // Check whether CmpInstr can be made redundant by the current instruction.
5166     if (!IsCmpZero &&
5167         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
5168       Sub = Instr;
5169       break;
5170     }
5171 
5172     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
5173         Instr->readsRegister(X86::EFLAGS, TRI)) {
5174       // This instruction modifies or uses EFLAGS.
5175 
5176       // MOV32r0 etc. are implemented with xor which clobbers condition code.
5177       // They are safe to move up, if the definition to EFLAGS is dead and
5178       // earlier instructions do not read or write EFLAGS.
5179       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
5180           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
5181         Movr0Inst = Instr;
5182         continue;
5183       }
5184 
5185       // We can't remove CmpInstr.
5186       return false;
5187     }
5188   }
5189 
5190   // Return false if no candidates exist.
5191   if (!IsCmpZero && !Sub)
5192     return false;
5193 
5194   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5195                     Sub->getOperand(2).getReg() == SrcReg);
5196 
5197   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
5198   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5199   // If we are done with the basic block, we need to check whether EFLAGS is
5200   // live-out.
5201   bool IsSafe = false;
5202   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
5203   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
5204   for (++I; I != E; ++I) {
5205     const MachineInstr &Instr = *I;
5206     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5207     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5208     // We should check the usage if this instruction uses and updates EFLAGS.
5209     if (!UseEFLAGS && ModifyEFLAGS) {
5210       // It is safe to remove CmpInstr if EFLAGS is updated again.
5211       IsSafe = true;
5212       break;
5213     }
5214     if (!UseEFLAGS && !ModifyEFLAGS)
5215       continue;
5216 
5217     // EFLAGS is used by this instruction.
5218     X86::CondCode OldCC = X86::COND_INVALID;
5219     bool OpcIsSET = false;
5220     if (IsCmpZero || IsSwapped) {
5221       // We decode the condition code from opcode.
5222       if (Instr.isBranch())
5223         OldCC = getCondFromBranchOpc(Instr.getOpcode());
5224       else {
5225         OldCC = getCondFromSETOpc(Instr.getOpcode());
5226         if (OldCC != X86::COND_INVALID)
5227           OpcIsSET = true;
5228         else
5229           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
5230       }
5231       if (OldCC == X86::COND_INVALID) return false;
5232     }
5233     if (IsCmpZero) {
5234       switch (OldCC) {
5235       default: break;
5236       case X86::COND_A: case X86::COND_AE:
5237       case X86::COND_B: case X86::COND_BE:
5238       case X86::COND_G: case X86::COND_GE:
5239       case X86::COND_L: case X86::COND_LE:
5240       case X86::COND_O: case X86::COND_NO:
5241         // CF and OF are used, we can't perform this optimization.
5242         return false;
5243       }
5244 
5245       // If we're updating the condition code check if we have to reverse the
5246       // condition.
5247       if (ShouldUpdateCC)
5248         switch (OldCC) {
5249         default:
5250           return false;
5251         case X86::COND_E:
5252           break;
5253         case X86::COND_NE:
5254           NewCC = GetOppositeBranchCondition(NewCC);
5255           break;
5256         }
5257     } else if (IsSwapped) {
5258       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5259       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5260       // We swap the condition code and synthesize the new opcode.
5261       NewCC = getSwappedCondition(OldCC);
5262       if (NewCC == X86::COND_INVALID) return false;
5263     }
5264 
5265     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
5266       // Synthesize the new opcode.
5267       bool HasMemoryOperand = Instr.hasOneMemOperand();
5268       unsigned NewOpc;
5269       if (Instr.isBranch())
5270         NewOpc = GetCondBranchFromCond(NewCC);
5271       else if(OpcIsSET)
5272         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5273       else {
5274         unsigned DstReg = Instr.getOperand(0).getReg();
5275         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5276                                  HasMemoryOperand);
5277       }
5278 
5279       // Push the MachineInstr to OpsToUpdate.
5280       // If it is safe to remove CmpInstr, the condition code of these
5281       // instructions will be modified.
5282       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5283     }
5284     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5285       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
5286       IsSafe = true;
5287       break;
5288     }
5289   }
5290 
5291   // If EFLAGS is not killed nor re-defined, we should check whether it is
5292   // live-out. If it is live-out, do not optimize.
5293   if ((IsCmpZero || IsSwapped) && !IsSafe) {
5294     MachineBasicBlock *MBB = CmpInstr->getParent();
5295     for (MachineBasicBlock *Successor : MBB->successors())
5296       if (Successor->isLiveIn(X86::EFLAGS))
5297         return false;
5298   }
5299 
5300   // The instruction to be updated is either Sub or MI.
5301   Sub = IsCmpZero ? MI : Sub;
5302   // Move Movr0Inst to the appropriate place before Sub.
5303   if (Movr0Inst) {
5304     // Look backwards until we find a def that doesn't use the current EFLAGS.
5305     Def = Sub;
5306     MachineBasicBlock::reverse_iterator
5307       InsertI = MachineBasicBlock::reverse_iterator(++Def),
5308                 InsertE = Sub->getParent()->rend();
5309     for (; InsertI != InsertE; ++InsertI) {
5310       MachineInstr *Instr = &*InsertI;
5311       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5312           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5313         Sub->getParent()->remove(Movr0Inst);
5314         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5315                                    Movr0Inst);
5316         break;
5317       }
5318     }
5319     if (InsertI == InsertE)
5320       return false;
5321   }
5322 
5323   // Make sure Sub instruction defines EFLAGS and mark the def live.
5324   unsigned i = 0, e = Sub->getNumOperands();
5325   for (; i != e; ++i) {
5326     MachineOperand &MO = Sub->getOperand(i);
5327     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5328       MO.setIsDead(false);
5329       break;
5330     }
5331   }
5332   assert(i != e && "Unable to locate a def EFLAGS operand");
5333 
5334   CmpInstr->eraseFromParent();
5335 
5336   // Modify the condition code of instructions in OpsToUpdate.
5337   for (auto &Op : OpsToUpdate)
5338     Op.first->setDesc(get(Op.second));
5339   return true;
5340 }
5341 
5342 /// Try to remove the load by folding it to a register
5343 /// operand at the use. We fold the load instructions if load defines a virtual
5344 /// register, the virtual register is used once in the same BB, and the
5345 /// instructions in-between do not load or store, and have no side effects.
5346 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
5347                                               const MachineRegisterInfo *MRI,
5348                                               unsigned &FoldAsLoadDefReg,
5349                                               MachineInstr *&DefMI) const {
5350   if (FoldAsLoadDefReg == 0)
5351     return nullptr;
5352   // To be conservative, if there exists another load, clear the load candidate.
5353   if (MI->mayLoad()) {
5354     FoldAsLoadDefReg = 0;
5355     return nullptr;
5356   }
5357 
5358   // Check whether we can move DefMI here.
5359   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5360   assert(DefMI);
5361   bool SawStore = false;
5362   if (!DefMI->isSafeToMove(nullptr, SawStore))
5363     return nullptr;
5364 
5365   // Collect information about virtual register operands of MI.
5366   unsigned SrcOperandId = 0;
5367   bool FoundSrcOperand = false;
5368   for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
5369     MachineOperand &MO = MI->getOperand(i);
5370     if (!MO.isReg())
5371       continue;
5372     unsigned Reg = MO.getReg();
5373     if (Reg != FoldAsLoadDefReg)
5374       continue;
5375     // Do not fold if we have a subreg use or a def or multiple uses.
5376     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
5377       return nullptr;
5378 
5379     SrcOperandId = i;
5380     FoundSrcOperand = true;
5381   }
5382   if (!FoundSrcOperand)
5383     return nullptr;
5384 
5385   // Check whether we can fold the def into SrcOperandId.
5386   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI)) {
5387     FoldAsLoadDefReg = 0;
5388     return FoldMI;
5389   }
5390 
5391   return nullptr;
5392 }
5393 
5394 /// Expand a single-def pseudo instruction to a two-addr
5395 /// instruction with two undef reads of the register being defined.
5396 /// This is used for mapping:
5397 ///   %xmm4 = V_SET0
5398 /// to:
5399 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5400 ///
5401 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5402                              const MCInstrDesc &Desc) {
5403   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5404   unsigned Reg = MIB->getOperand(0).getReg();
5405   MIB->setDesc(Desc);
5406 
5407   // MachineInstr::addOperand() will insert explicit operands before any
5408   // implicit operands.
5409   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5410   // But we don't trust that.
5411   assert(MIB->getOperand(1).getReg() == Reg &&
5412          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
5413   return true;
5414 }
5415 
5416 /// Expand a single-def pseudo instruction to a two-addr
5417 /// instruction with two %k0 reads.
5418 /// This is used for mapping:
5419 ///   %k4 = K_SET1
5420 /// to:
5421 ///   %k4 = KXNORrr %k0, %k0
5422 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5423                             const MCInstrDesc &Desc, unsigned Reg) {
5424   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5425   MIB->setDesc(Desc);
5426   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5427   return true;
5428 }
5429 
5430 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5431                           bool MinusOne) {
5432   MachineBasicBlock &MBB = *MIB->getParent();
5433   DebugLoc DL = MIB->getDebugLoc();
5434   unsigned Reg = MIB->getOperand(0).getReg();
5435 
5436   // Insert the XOR.
5437   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5438       .addReg(Reg, RegState::Undef)
5439       .addReg(Reg, RegState::Undef);
5440 
5441   // Turn the pseudo into an INC or DEC.
5442   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5443   MIB.addReg(Reg);
5444 
5445   return true;
5446 }
5447 
5448 bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5449   MachineBasicBlock &MBB = *MIB->getParent();
5450   DebugLoc DL = MIB->getDebugLoc();
5451   int64_t Imm = MIB->getOperand(1).getImm();
5452   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5453   MachineBasicBlock::iterator I = MIB.getInstr();
5454 
5455   int StackAdjustment;
5456 
5457   if (Subtarget.is64Bit()) {
5458     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5459            MIB->getOpcode() == X86::MOV32ImmSExti8);
5460 
5461     // Can't use push/pop lowering if the function might write to the red zone.
5462     X86MachineFunctionInfo *X86FI =
5463         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5464     if (X86FI->getUsesRedZone()) {
5465       MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5466                                                                : X86::MOV64ri));
5467       return true;
5468     }
5469 
5470     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5471     // widen the register if necessary.
5472     StackAdjustment = 8;
5473     BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5474     MIB->setDesc(get(X86::POP64r));
5475     MIB->getOperand(0)
5476         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5477   } else {
5478     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5479     StackAdjustment = 4;
5480     BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5481     MIB->setDesc(get(X86::POP32r));
5482   }
5483 
5484   // Build CFI if necessary.
5485   MachineFunction &MF = *MBB.getParent();
5486   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5487   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5488   bool NeedsDwarfCFI =
5489       !IsWin64Prologue &&
5490       (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5491   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5492   if (EmitCFI) {
5493     TFL->BuildCFI(MBB, I, DL,
5494         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5495     TFL->BuildCFI(MBB, std::next(I), DL,
5496         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5497   }
5498 
5499   return true;
5500 }
5501 
5502 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5503 // code sequence is needed for other targets.
5504 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5505                                  const TargetInstrInfo &TII) {
5506   MachineBasicBlock &MBB = *MIB->getParent();
5507   DebugLoc DL = MIB->getDebugLoc();
5508   unsigned Reg = MIB->getOperand(0).getReg();
5509   const GlobalValue *GV =
5510       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
5511   unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
5512   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
5513       MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8);
5514   MachineBasicBlock::iterator I = MIB.getInstr();
5515 
5516   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5517       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5518       .addMemOperand(MMO);
5519   MIB->setDebugLoc(DL);
5520   MIB->setDesc(TII.get(X86::MOV64rm));
5521   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5522 }
5523 
5524 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
5525   bool HasAVX = Subtarget.hasAVX();
5526   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
5527   switch (MI->getOpcode()) {
5528   case X86::MOV32r0:
5529     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
5530   case X86::MOV32r1:
5531     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5532   case X86::MOV32r_1:
5533     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
5534   case X86::MOV32ImmSExti8:
5535   case X86::MOV64ImmSExti8:
5536     return ExpandMOVImmSExti8(MIB);
5537   case X86::SETB_C8r:
5538     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
5539   case X86::SETB_C16r:
5540     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
5541   case X86::SETB_C32r:
5542     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
5543   case X86::SETB_C64r:
5544     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
5545   case X86::V_SET0:
5546   case X86::FsFLD0SS:
5547   case X86::FsFLD0SD:
5548     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
5549   case X86::AVX_SET0:
5550     assert(HasAVX && "AVX not supported");
5551     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
5552   case X86::AVX512_128_SET0:
5553     return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
5554   case X86::AVX512_256_SET0:
5555     return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
5556   case X86::AVX512_512_SET0:
5557     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
5558   case X86::V_SETALLONES:
5559     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
5560   case X86::AVX2_SETALLONES:
5561     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
5562   case X86::TEST8ri_NOREX:
5563     MI->setDesc(get(X86::TEST8ri));
5564     return true;
5565   case X86::MOV32ri64:
5566     MI->setDesc(get(X86::MOV32ri));
5567     return true;
5568 
5569   // KNL does not recognize dependency-breaking idioms for mask registers,
5570   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5571   // Using %k0 as the undef input register is a performance heuristic based
5572   // on the assumption that %k0 is used less frequently than the other mask
5573   // registers, since it is not usable as a write mask.
5574   // FIXME: A more advanced approach would be to choose the best input mask
5575   // register based on context.
5576   case X86::KSET0B:
5577   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5578   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5579   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
5580   case X86::KSET1B:
5581   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5582   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5583   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
5584   case TargetOpcode::LOAD_STACK_GUARD:
5585     expandLoadStackGuard(MIB, *this);
5586     return true;
5587   }
5588   return false;
5589 }
5590 
5591 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5592                         int PtrOffset = 0) {
5593   unsigned NumAddrOps = MOs.size();
5594 
5595   if (NumAddrOps < 4) {
5596     // FrameIndex only - add an immediate offset (whether its zero or not).
5597     for (unsigned i = 0; i != NumAddrOps; ++i)
5598       MIB.addOperand(MOs[i]);
5599     addOffset(MIB, PtrOffset);
5600   } else {
5601     // General Memory Addressing - we need to add any offset to an existing
5602     // offset.
5603     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5604     for (unsigned i = 0; i != NumAddrOps; ++i) {
5605       const MachineOperand &MO = MOs[i];
5606       if (i == 3 && PtrOffset != 0) {
5607         MIB.addDisp(MO, PtrOffset);
5608       } else {
5609         MIB.addOperand(MO);
5610       }
5611     }
5612   }
5613 }
5614 
5615 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5616                                      ArrayRef<MachineOperand> MOs,
5617                                      MachineBasicBlock::iterator InsertPt,
5618                                      MachineInstr *MI,
5619                                      const TargetInstrInfo &TII) {
5620   // Create the base instruction with the memory operand as the first part.
5621   // Omit the implicit operands, something BuildMI can't do.
5622   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5623                                               MI->getDebugLoc(), true);
5624   MachineInstrBuilder MIB(MF, NewMI);
5625   addOperands(MIB, MOs);
5626 
5627   // Loop over the rest of the ri operands, converting them over.
5628   unsigned NumOps = MI->getDesc().getNumOperands()-2;
5629   for (unsigned i = 0; i != NumOps; ++i) {
5630     MachineOperand &MO = MI->getOperand(i+2);
5631     MIB.addOperand(MO);
5632   }
5633   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
5634     MachineOperand &MO = MI->getOperand(i);
5635     MIB.addOperand(MO);
5636   }
5637 
5638   MachineBasicBlock *MBB = InsertPt->getParent();
5639   MBB->insert(InsertPt, NewMI);
5640 
5641   return MIB;
5642 }
5643 
5644 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5645                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5646                               MachineBasicBlock::iterator InsertPt,
5647                               MachineInstr *MI, const TargetInstrInfo &TII,
5648                               int PtrOffset = 0) {
5649   // Omit the implicit operands, something BuildMI can't do.
5650   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5651                                               MI->getDebugLoc(), true);
5652   MachineInstrBuilder MIB(MF, NewMI);
5653 
5654   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5655     MachineOperand &MO = MI->getOperand(i);
5656     if (i == OpNo) {
5657       assert(MO.isReg() && "Expected to fold into reg operand!");
5658       addOperands(MIB, MOs, PtrOffset);
5659     } else {
5660       MIB.addOperand(MO);
5661     }
5662   }
5663 
5664   MachineBasicBlock *MBB = InsertPt->getParent();
5665   MBB->insert(InsertPt, NewMI);
5666 
5667   return MIB;
5668 }
5669 
5670 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5671                                 ArrayRef<MachineOperand> MOs,
5672                                 MachineBasicBlock::iterator InsertPt,
5673                                 MachineInstr *MI) {
5674   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5675                                     MI->getDebugLoc(), TII.get(Opcode));
5676   addOperands(MIB, MOs);
5677   return MIB.addImm(0);
5678 }
5679 
5680 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5681     MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5682     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5683     unsigned Size, unsigned Align) const {
5684   switch (MI->getOpcode()) {
5685   case X86::INSERTPSrr:
5686   case X86::VINSERTPSrr:
5687     // Attempt to convert the load of inserted vector into a fold load
5688     // of a single float.
5689     if (OpNum == 2) {
5690       unsigned Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
5691       unsigned ZMask = Imm & 15;
5692       unsigned DstIdx = (Imm >> 4) & 3;
5693       unsigned SrcIdx = (Imm >> 6) & 3;
5694 
5695       unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5696       if (Size <= RCSize && 4 <= Align) {
5697         int PtrOffset = SrcIdx * 4;
5698         unsigned NewImm = (DstIdx << 4) | ZMask;
5699         unsigned NewOpCode =
5700             (MI->getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
5701                                                  : X86::INSERTPSrm);
5702         MachineInstr *NewMI =
5703             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5704         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5705         return NewMI;
5706       }
5707     }
5708     break;
5709   case X86::MOVHLPSrr:
5710   case X86::VMOVHLPSrr:
5711     // Move the upper 64-bits of the second operand to the lower 64-bits.
5712     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5713     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5714     if (OpNum == 2) {
5715       unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5716       if (Size <= RCSize && 8 <= Align) {
5717         unsigned NewOpCode =
5718             (MI->getOpcode() == X86::VMOVHLPSrr ? X86::VMOVLPSrm
5719                                                 : X86::MOVLPSrm);
5720         MachineInstr *NewMI =
5721             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5722         return NewMI;
5723       }
5724     }
5725     break;
5726   };
5727 
5728   return nullptr;
5729 }
5730 
5731 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5732     MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5733     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5734     unsigned Size, unsigned Align, bool AllowCommute) const {
5735   const DenseMap<unsigned,
5736                  std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
5737   bool isCallRegIndirect = Subtarget.callRegIndirect();
5738   bool isTwoAddrFold = false;
5739 
5740   // For CPUs that favor the register form of a call or push,
5741   // do not fold loads into calls or pushes, unless optimizing for size
5742   // aggressively.
5743   if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
5744       (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r ||
5745        MI->getOpcode() == X86::PUSH16r || MI->getOpcode() == X86::PUSH32r ||
5746        MI->getOpcode() == X86::PUSH64r))
5747     return nullptr;
5748 
5749   unsigned NumOps = MI->getDesc().getNumOperands();
5750   bool isTwoAddr = NumOps > 1 &&
5751     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5752 
5753   // FIXME: AsmPrinter doesn't know how to handle
5754   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5755   if (MI->getOpcode() == X86::ADD32ri &&
5756       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5757     return nullptr;
5758 
5759   MachineInstr *NewMI = nullptr;
5760 
5761   // Attempt to fold any custom cases we have.
5762   if (MachineInstr *CustomMI =
5763           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
5764     return CustomMI;
5765 
5766   // Folding a memory location into the two-address part of a two-address
5767   // instruction is different than folding it other places.  It requires
5768   // replacing the *two* registers with the memory location.
5769   if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
5770       MI->getOperand(0).isReg() &&
5771       MI->getOperand(1).isReg() &&
5772       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
5773     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5774     isTwoAddrFold = true;
5775   } else if (OpNum == 0) {
5776     if (MI->getOpcode() == X86::MOV32r0) {
5777       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5778       if (NewMI)
5779         return NewMI;
5780     }
5781 
5782     OpcodeTablePtr = &RegOp2MemOpTable0;
5783   } else if (OpNum == 1) {
5784     OpcodeTablePtr = &RegOp2MemOpTable1;
5785   } else if (OpNum == 2) {
5786     OpcodeTablePtr = &RegOp2MemOpTable2;
5787   } else if (OpNum == 3) {
5788     OpcodeTablePtr = &RegOp2MemOpTable3;
5789   } else if (OpNum == 4) {
5790     OpcodeTablePtr = &RegOp2MemOpTable4;
5791   }
5792 
5793   // If table selected...
5794   if (OpcodeTablePtr) {
5795     // Find the Opcode to fuse
5796     auto I = OpcodeTablePtr->find(MI->getOpcode());
5797     if (I != OpcodeTablePtr->end()) {
5798       unsigned Opcode = I->second.first;
5799       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
5800       if (Align < MinAlign)
5801         return nullptr;
5802       bool NarrowToMOV32rm = false;
5803       if (Size) {
5804         unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5805         if (Size < RCSize) {
5806           // Check if it's safe to fold the load. If the size of the object is
5807           // narrower than the load width, then it's not.
5808           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5809             return nullptr;
5810           // If this is a 64-bit load, but the spill slot is 32, then we can do
5811           // a 32-bit load which is implicitly zero-extended. This likely is
5812           // due to live interval analysis remat'ing a load from stack slot.
5813           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
5814             return nullptr;
5815           Opcode = X86::MOV32rm;
5816           NarrowToMOV32rm = true;
5817         }
5818       }
5819 
5820       if (isTwoAddrFold)
5821         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5822       else
5823         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5824 
5825       if (NarrowToMOV32rm) {
5826         // If this is the special case where we use a MOV32rm to load a 32-bit
5827         // value and zero-extend the top bits. Change the destination register
5828         // to a 32-bit one.
5829         unsigned DstReg = NewMI->getOperand(0).getReg();
5830         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
5831           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5832         else
5833           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5834       }
5835       return NewMI;
5836     }
5837   }
5838 
5839   // If the instruction and target operand are commutable, commute the
5840   // instruction and try again.
5841   if (AllowCommute) {
5842     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5843     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5844       bool HasDef = MI->getDesc().getNumDefs();
5845       unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
5846       unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
5847       unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
5848       bool Tied1 =
5849           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5850       bool Tied2 =
5851           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5852 
5853       // If either of the commutable operands are tied to the destination
5854       // then we can not commute + fold.
5855       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5856           (HasDef && Reg0 == Reg2 && Tied2))
5857         return nullptr;
5858 
5859       MachineInstr *CommutedMI =
5860           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5861       if (!CommutedMI) {
5862         // Unable to commute.
5863         return nullptr;
5864       }
5865       if (CommutedMI != MI) {
5866         // New instruction. We can't fold from this.
5867         CommutedMI->eraseFromParent();
5868         return nullptr;
5869       }
5870 
5871       // Attempt to fold with the commuted version of the instruction.
5872       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5873                                     Size, Align, /*AllowCommute=*/false);
5874       if (NewMI)
5875         return NewMI;
5876 
5877       // Folding failed again - undo the commute before returning.
5878       MachineInstr *UncommutedMI =
5879           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5880       if (!UncommutedMI) {
5881         // Unable to commute.
5882         return nullptr;
5883       }
5884       if (UncommutedMI != MI) {
5885         // New instruction. It doesn't need to be kept.
5886         UncommutedMI->eraseFromParent();
5887         return nullptr;
5888       }
5889 
5890       // Return here to prevent duplicate fuse failure report.
5891       return nullptr;
5892     }
5893   }
5894 
5895   // No fusion
5896   if (PrintFailedFusing && !MI->isCopy())
5897     dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
5898   return nullptr;
5899 }
5900 
5901 /// Return true for all instructions that only update
5902 /// the first 32 or 64-bits of the destination register and leave the rest
5903 /// unmodified. This can be used to avoid folding loads if the instructions
5904 /// only update part of the destination register, and the non-updated part is
5905 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5906 /// instructions breaks the partial register dependency and it can improve
5907 /// performance. e.g.:
5908 ///
5909 ///   movss (%rdi), %xmm0
5910 ///   cvtss2sd %xmm0, %xmm0
5911 ///
5912 /// Instead of
5913 ///   cvtss2sd (%rdi), %xmm0
5914 ///
5915 /// FIXME: This should be turned into a TSFlags.
5916 ///
5917 static bool hasPartialRegUpdate(unsigned Opcode) {
5918   switch (Opcode) {
5919   case X86::CVTSI2SSrr:
5920   case X86::CVTSI2SSrm:
5921   case X86::CVTSI2SS64rr:
5922   case X86::CVTSI2SS64rm:
5923   case X86::CVTSI2SDrr:
5924   case X86::CVTSI2SDrm:
5925   case X86::CVTSI2SD64rr:
5926   case X86::CVTSI2SD64rm:
5927   case X86::CVTSD2SSrr:
5928   case X86::CVTSD2SSrm:
5929   case X86::Int_CVTSD2SSrr:
5930   case X86::Int_CVTSD2SSrm:
5931   case X86::CVTSS2SDrr:
5932   case X86::CVTSS2SDrm:
5933   case X86::Int_CVTSS2SDrr:
5934   case X86::Int_CVTSS2SDrm:
5935   case X86::MOVHPDrm:
5936   case X86::MOVHPSrm:
5937   case X86::MOVLPDrm:
5938   case X86::MOVLPSrm:
5939   case X86::RCPSSr:
5940   case X86::RCPSSm:
5941   case X86::RCPSSr_Int:
5942   case X86::RCPSSm_Int:
5943   case X86::ROUNDSDr:
5944   case X86::ROUNDSDm:
5945   case X86::ROUNDSDr_Int:
5946   case X86::ROUNDSSr:
5947   case X86::ROUNDSSm:
5948   case X86::ROUNDSSr_Int:
5949   case X86::RSQRTSSr:
5950   case X86::RSQRTSSm:
5951   case X86::RSQRTSSr_Int:
5952   case X86::RSQRTSSm_Int:
5953   case X86::SQRTSSr:
5954   case X86::SQRTSSm:
5955   case X86::SQRTSSr_Int:
5956   case X86::SQRTSSm_Int:
5957   case X86::SQRTSDr:
5958   case X86::SQRTSDm:
5959   case X86::SQRTSDr_Int:
5960   case X86::SQRTSDm_Int:
5961     return true;
5962   }
5963 
5964   return false;
5965 }
5966 
5967 /// Inform the ExeDepsFix pass how many idle
5968 /// instructions we would like before a partial register update.
5969 unsigned X86InstrInfo::
5970 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
5971                              const TargetRegisterInfo *TRI) const {
5972   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
5973     return 0;
5974 
5975   // If MI is marked as reading Reg, the partial register update is wanted.
5976   const MachineOperand &MO = MI->getOperand(0);
5977   unsigned Reg = MO.getReg();
5978   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
5979     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
5980       return 0;
5981   } else {
5982     if (MI->readsRegister(Reg, TRI))
5983       return 0;
5984   }
5985 
5986   // If any instructions in the clearance range are reading Reg, insert a
5987   // dependency breaking instruction, which is inexpensive and is likely to
5988   // be hidden in other instruction's cycles.
5989   return PartialRegUpdateClearance;
5990 }
5991 
5992 // Return true for any instruction the copies the high bits of the first source
5993 // operand into the unused high bits of the destination operand.
5994 static bool hasUndefRegUpdate(unsigned Opcode) {
5995   switch (Opcode) {
5996   case X86::VCVTSI2SSrr:
5997   case X86::VCVTSI2SSrm:
5998   case X86::Int_VCVTSI2SSrr:
5999   case X86::Int_VCVTSI2SSrm:
6000   case X86::VCVTSI2SS64rr:
6001   case X86::VCVTSI2SS64rm:
6002   case X86::Int_VCVTSI2SS64rr:
6003   case X86::Int_VCVTSI2SS64rm:
6004   case X86::VCVTSI2SDrr:
6005   case X86::VCVTSI2SDrm:
6006   case X86::Int_VCVTSI2SDrr:
6007   case X86::Int_VCVTSI2SDrm:
6008   case X86::VCVTSI2SD64rr:
6009   case X86::VCVTSI2SD64rm:
6010   case X86::Int_VCVTSI2SD64rr:
6011   case X86::Int_VCVTSI2SD64rm:
6012   case X86::VCVTSD2SSrr:
6013   case X86::VCVTSD2SSrm:
6014   case X86::Int_VCVTSD2SSrr:
6015   case X86::Int_VCVTSD2SSrm:
6016   case X86::VCVTSS2SDrr:
6017   case X86::VCVTSS2SDrm:
6018   case X86::Int_VCVTSS2SDrr:
6019   case X86::Int_VCVTSS2SDrm:
6020   case X86::VRCPSSr:
6021   case X86::VRCPSSm:
6022   case X86::VRCPSSm_Int:
6023   case X86::VROUNDSDr:
6024   case X86::VROUNDSDm:
6025   case X86::VROUNDSDr_Int:
6026   case X86::VROUNDSSr:
6027   case X86::VROUNDSSm:
6028   case X86::VROUNDSSr_Int:
6029   case X86::VRSQRTSSr:
6030   case X86::VRSQRTSSm:
6031   case X86::VRSQRTSSm_Int:
6032   case X86::VSQRTSSr:
6033   case X86::VSQRTSSm:
6034   case X86::VSQRTSSm_Int:
6035   case X86::VSQRTSDr:
6036   case X86::VSQRTSDm:
6037   case X86::VSQRTSDm_Int:
6038     // AVX-512
6039   case X86::VCVTSD2SSZrr:
6040   case X86::VCVTSD2SSZrm:
6041   case X86::VCVTSS2SDZrr:
6042   case X86::VCVTSS2SDZrm:
6043     return true;
6044   }
6045 
6046   return false;
6047 }
6048 
6049 /// Inform the ExeDepsFix pass how many idle instructions we would like before
6050 /// certain undef register reads.
6051 ///
6052 /// This catches the VCVTSI2SD family of instructions:
6053 ///
6054 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6055 ///
6056 /// We should to be careful *not* to catch VXOR idioms which are presumably
6057 /// handled specially in the pipeline:
6058 ///
6059 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6060 ///
6061 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6062 /// high bits that are passed-through are not live.
6063 unsigned X86InstrInfo::
6064 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
6065                      const TargetRegisterInfo *TRI) const {
6066   if (!hasUndefRegUpdate(MI->getOpcode()))
6067     return 0;
6068 
6069   // Set the OpNum parameter to the first source operand.
6070   OpNum = 1;
6071 
6072   const MachineOperand &MO = MI->getOperand(OpNum);
6073   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
6074     return UndefRegClearance;
6075   }
6076   return 0;
6077 }
6078 
6079 void X86InstrInfo::
6080 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
6081                           const TargetRegisterInfo *TRI) const {
6082   unsigned Reg = MI->getOperand(OpNum).getReg();
6083   // If MI kills this register, the false dependence is already broken.
6084   if (MI->killsRegister(Reg, TRI))
6085     return;
6086 
6087   if (X86::VR128RegClass.contains(Reg)) {
6088     // These instructions are all floating point domain, so xorps is the best
6089     // choice.
6090     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
6091     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
6092       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
6093     MI->addRegisterKilled(Reg, TRI, true);
6094   } else if (X86::VR256RegClass.contains(Reg)) {
6095     // Use vxorps to clear the full ymm register.
6096     // It wants to read and write the xmm sub-register.
6097     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
6098     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
6099       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
6100       .addReg(Reg, RegState::ImplicitDefine);
6101     MI->addRegisterKilled(Reg, TRI, true);
6102   }
6103 }
6104 
6105 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6106     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
6107     MachineBasicBlock::iterator InsertPt, int FrameIndex,
6108     LiveIntervals *LIS) const {
6109   // Check switch flag
6110   if (NoFusing)
6111     return nullptr;
6112 
6113   // Unless optimizing for size, don't fold to avoid partial
6114   // register update stalls
6115   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
6116     return nullptr;
6117 
6118   const MachineFrameInfo *MFI = MF.getFrameInfo();
6119   unsigned Size = MFI->getObjectSize(FrameIndex);
6120   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
6121   // If the function stack isn't realigned we don't want to fold instructions
6122   // that need increased alignment.
6123   if (!RI.needsStackRealignment(MF))
6124     Alignment =
6125         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
6126   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6127     unsigned NewOpc = 0;
6128     unsigned RCSize = 0;
6129     switch (MI->getOpcode()) {
6130     default: return nullptr;
6131     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
6132     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6133     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6134     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
6135     }
6136     // Check if it's safe to fold the load. If the size of the object is
6137     // narrower than the load width, then it's not.
6138     if (Size < RCSize)
6139       return nullptr;
6140     // Change to CMPXXri r, 0 first.
6141     MI->setDesc(get(NewOpc));
6142     MI->getOperand(1).ChangeToImmediate(0);
6143   } else if (Ops.size() != 1)
6144     return nullptr;
6145 
6146   return foldMemoryOperandImpl(MF, MI, Ops[0],
6147                                MachineOperand::CreateFI(FrameIndex), InsertPt,
6148                                Size, Alignment, /*AllowCommute=*/true);
6149 }
6150 
6151 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6152 /// because the latter uses contents that wouldn't be defined in the folded
6153 /// version.  For instance, this transformation isn't legal:
6154 ///   movss (%rdi), %xmm0
6155 ///   addps %xmm0, %xmm0
6156 /// ->
6157 ///   addps (%rdi), %xmm0
6158 ///
6159 /// But this one is:
6160 ///   movss (%rdi), %xmm0
6161 ///   addss %xmm0, %xmm0
6162 /// ->
6163 ///   addss (%rdi), %xmm0
6164 ///
6165 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6166                                              const MachineInstr &UserMI,
6167                                              const MachineFunction &MF) {
6168   unsigned Opc = LoadMI.getOpcode();
6169   unsigned UserOpc = UserMI.getOpcode();
6170   unsigned RegSize =
6171       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6172 
6173   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
6174     // These instructions only load 32 bits, we can't fold them if the
6175     // destination register is wider than 32 bits (4 bytes), and its user
6176     // instruction isn't scalar (SS).
6177     switch (UserOpc) {
6178     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
6179     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
6180     case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
6181     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
6182     case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int:
6183     case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int:
6184     case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int:
6185     case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int:
6186     case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int:
6187     case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int:
6188       return false;
6189     default:
6190       return true;
6191     }
6192   }
6193 
6194   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
6195     // These instructions only load 64 bits, we can't fold them if the
6196     // destination register is wider than 64 bits (8 bytes), and its user
6197     // instruction isn't scalar (SD).
6198     switch (UserOpc) {
6199     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
6200     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
6201     case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
6202     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
6203     case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int:
6204     case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int:
6205     case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int:
6206     case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int:
6207     case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int:
6208     case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int:
6209       return false;
6210     default:
6211       return true;
6212     }
6213   }
6214 
6215   return false;
6216 }
6217 
6218 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6219     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
6220     MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI,
6221     LiveIntervals *LIS) const {
6222   // If loading from a FrameIndex, fold directly from the FrameIndex.
6223   unsigned NumOps = LoadMI->getDesc().getNumOperands();
6224   int FrameIndex;
6225   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6226     if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
6227       return nullptr;
6228     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
6229   }
6230 
6231   // Check switch flag
6232   if (NoFusing) return nullptr;
6233 
6234   // Avoid partial register update stalls unless optimizing for size.
6235   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
6236     return nullptr;
6237 
6238   // Determine the alignment of the load.
6239   unsigned Alignment = 0;
6240   if (LoadMI->hasOneMemOperand())
6241     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
6242   else
6243     switch (LoadMI->getOpcode()) {
6244     case X86::AVX2_SETALLONES:
6245     case X86::AVX_SET0:
6246       Alignment = 32;
6247       break;
6248     case X86::V_SET0:
6249     case X86::V_SETALLONES:
6250       Alignment = 16;
6251       break;
6252     case X86::FsFLD0SD:
6253       Alignment = 8;
6254       break;
6255     case X86::FsFLD0SS:
6256       Alignment = 4;
6257       break;
6258     default:
6259       return nullptr;
6260     }
6261   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6262     unsigned NewOpc = 0;
6263     switch (MI->getOpcode()) {
6264     default: return nullptr;
6265     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6266     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6267     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6268     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6269     }
6270     // Change to CMPXXri r, 0 first.
6271     MI->setDesc(get(NewOpc));
6272     MI->getOperand(1).ChangeToImmediate(0);
6273   } else if (Ops.size() != 1)
6274     return nullptr;
6275 
6276   // Make sure the subregisters match.
6277   // Otherwise we risk changing the size of the load.
6278   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
6279     return nullptr;
6280 
6281   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6282   switch (LoadMI->getOpcode()) {
6283   case X86::V_SET0:
6284   case X86::V_SETALLONES:
6285   case X86::AVX2_SETALLONES:
6286   case X86::AVX_SET0:
6287   case X86::FsFLD0SD:
6288   case X86::FsFLD0SS: {
6289     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6290     // Create a constant-pool entry and operands to load from it.
6291 
6292     // Medium and large mode can't fold loads this way.
6293     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6294         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6295       return nullptr;
6296 
6297     // x86-32 PIC requires a PIC base register for constant pools.
6298     unsigned PICBase = 0;
6299     if (MF.getTarget().isPositionIndependent()) {
6300       if (Subtarget.is64Bit())
6301         PICBase = X86::RIP;
6302       else
6303         // FIXME: PICBase = getGlobalBaseReg(&MF);
6304         // This doesn't work for several reasons.
6305         // 1. GlobalBaseReg may have been spilled.
6306         // 2. It may not be live at MI.
6307         return nullptr;
6308     }
6309 
6310     // Create a constant-pool entry.
6311     MachineConstantPool &MCP = *MF.getConstantPool();
6312     Type *Ty;
6313     unsigned Opc = LoadMI->getOpcode();
6314     if (Opc == X86::FsFLD0SS)
6315       Ty = Type::getFloatTy(MF.getFunction()->getContext());
6316     else if (Opc == X86::FsFLD0SD)
6317       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
6318     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
6319       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
6320     else
6321       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
6322 
6323     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
6324     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6325                                     Constant::getNullValue(Ty);
6326     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6327 
6328     // Create operands to load from the constant pool entry.
6329     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6330     MOs.push_back(MachineOperand::CreateImm(1));
6331     MOs.push_back(MachineOperand::CreateReg(0, false));
6332     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6333     MOs.push_back(MachineOperand::CreateReg(0, false));
6334     break;
6335   }
6336   default: {
6337     if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
6338       return nullptr;
6339 
6340     // Folding a normal load. Just copy the load's address operands.
6341     MOs.append(LoadMI->operands_begin() + NumOps - X86::AddrNumOperands,
6342                LoadMI->operands_begin() + NumOps);
6343     break;
6344   }
6345   }
6346   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6347                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6348 }
6349 
6350 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
6351                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
6352                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
6353   auto I = MemOp2RegOpTable.find(MI->getOpcode());
6354   if (I == MemOp2RegOpTable.end())
6355     return false;
6356   unsigned Opc = I->second.first;
6357   unsigned Index = I->second.second & TB_INDEX_MASK;
6358   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6359   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6360   if (UnfoldLoad && !FoldedLoad)
6361     return false;
6362   UnfoldLoad &= FoldedLoad;
6363   if (UnfoldStore && !FoldedStore)
6364     return false;
6365   UnfoldStore &= FoldedStore;
6366 
6367   const MCInstrDesc &MCID = get(Opc);
6368   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6369   // TODO: Check if 32-byte or greater accesses are slow too?
6370   if (!MI->hasOneMemOperand() &&
6371       RC == &X86::VR128RegClass &&
6372       Subtarget.isUnalignedMem16Slow())
6373     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6374     // conservatively assume the address is unaligned. That's bad for
6375     // performance.
6376     return false;
6377   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6378   SmallVector<MachineOperand,2> BeforeOps;
6379   SmallVector<MachineOperand,2> AfterOps;
6380   SmallVector<MachineOperand,4> ImpOps;
6381   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
6382     MachineOperand &Op = MI->getOperand(i);
6383     if (i >= Index && i < Index + X86::AddrNumOperands)
6384       AddrOps.push_back(Op);
6385     else if (Op.isReg() && Op.isImplicit())
6386       ImpOps.push_back(Op);
6387     else if (i < Index)
6388       BeforeOps.push_back(Op);
6389     else if (i > Index)
6390       AfterOps.push_back(Op);
6391   }
6392 
6393   // Emit the load instruction.
6394   if (UnfoldLoad) {
6395     std::pair<MachineInstr::mmo_iterator,
6396               MachineInstr::mmo_iterator> MMOs =
6397       MF.extractLoadMemRefs(MI->memoperands_begin(),
6398                             MI->memoperands_end());
6399     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
6400     if (UnfoldStore) {
6401       // Address operands cannot be marked isKill.
6402       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6403         MachineOperand &MO = NewMIs[0]->getOperand(i);
6404         if (MO.isReg())
6405           MO.setIsKill(false);
6406       }
6407     }
6408   }
6409 
6410   // Emit the data processing instruction.
6411   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
6412   MachineInstrBuilder MIB(MF, DataMI);
6413 
6414   if (FoldedStore)
6415     MIB.addReg(Reg, RegState::Define);
6416   for (MachineOperand &BeforeOp : BeforeOps)
6417     MIB.addOperand(BeforeOp);
6418   if (FoldedLoad)
6419     MIB.addReg(Reg);
6420   for (MachineOperand &AfterOp : AfterOps)
6421     MIB.addOperand(AfterOp);
6422   for (MachineOperand &ImpOp : ImpOps) {
6423     MIB.addReg(ImpOp.getReg(),
6424                getDefRegState(ImpOp.isDef()) |
6425                RegState::Implicit |
6426                getKillRegState(ImpOp.isKill()) |
6427                getDeadRegState(ImpOp.isDead()) |
6428                getUndefRegState(ImpOp.isUndef()));
6429   }
6430   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6431   switch (DataMI->getOpcode()) {
6432   default: break;
6433   case X86::CMP64ri32:
6434   case X86::CMP64ri8:
6435   case X86::CMP32ri:
6436   case X86::CMP32ri8:
6437   case X86::CMP16ri:
6438   case X86::CMP16ri8:
6439   case X86::CMP8ri: {
6440     MachineOperand &MO0 = DataMI->getOperand(0);
6441     MachineOperand &MO1 = DataMI->getOperand(1);
6442     if (MO1.getImm() == 0) {
6443       unsigned NewOpc;
6444       switch (DataMI->getOpcode()) {
6445       default: llvm_unreachable("Unreachable!");
6446       case X86::CMP64ri8:
6447       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6448       case X86::CMP32ri8:
6449       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6450       case X86::CMP16ri8:
6451       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6452       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6453       }
6454       DataMI->setDesc(get(NewOpc));
6455       MO1.ChangeToRegister(MO0.getReg(), false);
6456     }
6457   }
6458   }
6459   NewMIs.push_back(DataMI);
6460 
6461   // Emit the store instruction.
6462   if (UnfoldStore) {
6463     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6464     std::pair<MachineInstr::mmo_iterator,
6465               MachineInstr::mmo_iterator> MMOs =
6466       MF.extractStoreMemRefs(MI->memoperands_begin(),
6467                              MI->memoperands_end());
6468     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
6469   }
6470 
6471   return true;
6472 }
6473 
6474 bool
6475 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6476                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6477   if (!N->isMachineOpcode())
6478     return false;
6479 
6480   auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
6481   if (I == MemOp2RegOpTable.end())
6482     return false;
6483   unsigned Opc = I->second.first;
6484   unsigned Index = I->second.second & TB_INDEX_MASK;
6485   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6486   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6487   const MCInstrDesc &MCID = get(Opc);
6488   MachineFunction &MF = DAG.getMachineFunction();
6489   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6490   unsigned NumDefs = MCID.NumDefs;
6491   std::vector<SDValue> AddrOps;
6492   std::vector<SDValue> BeforeOps;
6493   std::vector<SDValue> AfterOps;
6494   SDLoc dl(N);
6495   unsigned NumOps = N->getNumOperands();
6496   for (unsigned i = 0; i != NumOps-1; ++i) {
6497     SDValue Op = N->getOperand(i);
6498     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6499       AddrOps.push_back(Op);
6500     else if (i < Index-NumDefs)
6501       BeforeOps.push_back(Op);
6502     else if (i > Index-NumDefs)
6503       AfterOps.push_back(Op);
6504   }
6505   SDValue Chain = N->getOperand(NumOps-1);
6506   AddrOps.push_back(Chain);
6507 
6508   // Emit the load instruction.
6509   SDNode *Load = nullptr;
6510   if (FoldedLoad) {
6511     EVT VT = *RC->vt_begin();
6512     std::pair<MachineInstr::mmo_iterator,
6513               MachineInstr::mmo_iterator> MMOs =
6514       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6515                             cast<MachineSDNode>(N)->memoperands_end());
6516     if (!(*MMOs.first) &&
6517         RC == &X86::VR128RegClass &&
6518         Subtarget.isUnalignedMem16Slow())
6519       // Do not introduce a slow unaligned load.
6520       return false;
6521     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6522     // memory access is slow above.
6523     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6524     bool isAligned = (*MMOs.first) &&
6525                      (*MMOs.first)->getAlignment() >= Alignment;
6526     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
6527                               VT, MVT::Other, AddrOps);
6528     NewNodes.push_back(Load);
6529 
6530     // Preserve memory reference information.
6531     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
6532   }
6533 
6534   // Emit the data processing instruction.
6535   std::vector<EVT> VTs;
6536   const TargetRegisterClass *DstRC = nullptr;
6537   if (MCID.getNumDefs() > 0) {
6538     DstRC = getRegClass(MCID, 0, &RI, MF);
6539     VTs.push_back(*DstRC->vt_begin());
6540   }
6541   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6542     EVT VT = N->getValueType(i);
6543     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6544       VTs.push_back(VT);
6545   }
6546   if (Load)
6547     BeforeOps.push_back(SDValue(Load, 0));
6548   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
6549   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6550   NewNodes.push_back(NewNode);
6551 
6552   // Emit the store instruction.
6553   if (FoldedStore) {
6554     AddrOps.pop_back();
6555     AddrOps.push_back(SDValue(NewNode, 0));
6556     AddrOps.push_back(Chain);
6557     std::pair<MachineInstr::mmo_iterator,
6558               MachineInstr::mmo_iterator> MMOs =
6559       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6560                              cast<MachineSDNode>(N)->memoperands_end());
6561     if (!(*MMOs.first) &&
6562         RC == &X86::VR128RegClass &&
6563         Subtarget.isUnalignedMem16Slow())
6564       // Do not introduce a slow unaligned store.
6565       return false;
6566     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6567     // memory access is slow above.
6568     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6569     bool isAligned = (*MMOs.first) &&
6570                      (*MMOs.first)->getAlignment() >= Alignment;
6571     SDNode *Store =
6572         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6573                            dl, MVT::Other, AddrOps);
6574     NewNodes.push_back(Store);
6575 
6576     // Preserve memory reference information.
6577     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
6578   }
6579 
6580   return true;
6581 }
6582 
6583 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6584                                       bool UnfoldLoad, bool UnfoldStore,
6585                                       unsigned *LoadRegIndex) const {
6586   auto I = MemOp2RegOpTable.find(Opc);
6587   if (I == MemOp2RegOpTable.end())
6588     return 0;
6589   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6590   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6591   if (UnfoldLoad && !FoldedLoad)
6592     return 0;
6593   if (UnfoldStore && !FoldedStore)
6594     return 0;
6595   if (LoadRegIndex)
6596     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
6597   return I->second.first;
6598 }
6599 
6600 bool
6601 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6602                                      int64_t &Offset1, int64_t &Offset2) const {
6603   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6604     return false;
6605   unsigned Opc1 = Load1->getMachineOpcode();
6606   unsigned Opc2 = Load2->getMachineOpcode();
6607   switch (Opc1) {
6608   default: return false;
6609   case X86::MOV8rm:
6610   case X86::MOV16rm:
6611   case X86::MOV32rm:
6612   case X86::MOV64rm:
6613   case X86::LD_Fp32m:
6614   case X86::LD_Fp64m:
6615   case X86::LD_Fp80m:
6616   case X86::MOVSSrm:
6617   case X86::MOVSDrm:
6618   case X86::MMX_MOVD64rm:
6619   case X86::MMX_MOVQ64rm:
6620   case X86::FsMOVAPSrm:
6621   case X86::FsMOVAPDrm:
6622   case X86::MOVAPSrm:
6623   case X86::MOVUPSrm:
6624   case X86::MOVAPDrm:
6625   case X86::MOVDQArm:
6626   case X86::MOVDQUrm:
6627   // AVX load instructions
6628   case X86::VMOVSSrm:
6629   case X86::VMOVSDrm:
6630   case X86::FsVMOVAPSrm:
6631   case X86::FsVMOVAPDrm:
6632   case X86::VMOVAPSrm:
6633   case X86::VMOVUPSrm:
6634   case X86::VMOVAPDrm:
6635   case X86::VMOVDQArm:
6636   case X86::VMOVDQUrm:
6637   case X86::VMOVAPSYrm:
6638   case X86::VMOVUPSYrm:
6639   case X86::VMOVAPDYrm:
6640   case X86::VMOVDQAYrm:
6641   case X86::VMOVDQUYrm:
6642     break;
6643   }
6644   switch (Opc2) {
6645   default: return false;
6646   case X86::MOV8rm:
6647   case X86::MOV16rm:
6648   case X86::MOV32rm:
6649   case X86::MOV64rm:
6650   case X86::LD_Fp32m:
6651   case X86::LD_Fp64m:
6652   case X86::LD_Fp80m:
6653   case X86::MOVSSrm:
6654   case X86::MOVSDrm:
6655   case X86::MMX_MOVD64rm:
6656   case X86::MMX_MOVQ64rm:
6657   case X86::FsMOVAPSrm:
6658   case X86::FsMOVAPDrm:
6659   case X86::MOVAPSrm:
6660   case X86::MOVUPSrm:
6661   case X86::MOVAPDrm:
6662   case X86::MOVDQArm:
6663   case X86::MOVDQUrm:
6664   // AVX load instructions
6665   case X86::VMOVSSrm:
6666   case X86::VMOVSDrm:
6667   case X86::FsVMOVAPSrm:
6668   case X86::FsVMOVAPDrm:
6669   case X86::VMOVAPSrm:
6670   case X86::VMOVUPSrm:
6671   case X86::VMOVAPDrm:
6672   case X86::VMOVDQArm:
6673   case X86::VMOVDQUrm:
6674   case X86::VMOVAPSYrm:
6675   case X86::VMOVUPSYrm:
6676   case X86::VMOVAPDYrm:
6677   case X86::VMOVDQAYrm:
6678   case X86::VMOVDQUYrm:
6679     break;
6680   }
6681 
6682   // Check if chain operands and base addresses match.
6683   if (Load1->getOperand(0) != Load2->getOperand(0) ||
6684       Load1->getOperand(5) != Load2->getOperand(5))
6685     return false;
6686   // Segment operands should match as well.
6687   if (Load1->getOperand(4) != Load2->getOperand(4))
6688     return false;
6689   // Scale should be 1, Index should be Reg0.
6690   if (Load1->getOperand(1) == Load2->getOperand(1) &&
6691       Load1->getOperand(2) == Load2->getOperand(2)) {
6692     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6693       return false;
6694 
6695     // Now let's examine the displacements.
6696     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6697         isa<ConstantSDNode>(Load2->getOperand(3))) {
6698       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6699       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6700       return true;
6701     }
6702   }
6703   return false;
6704 }
6705 
6706 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6707                                            int64_t Offset1, int64_t Offset2,
6708                                            unsigned NumLoads) const {
6709   assert(Offset2 > Offset1);
6710   if ((Offset2 - Offset1) / 8 > 64)
6711     return false;
6712 
6713   unsigned Opc1 = Load1->getMachineOpcode();
6714   unsigned Opc2 = Load2->getMachineOpcode();
6715   if (Opc1 != Opc2)
6716     return false;  // FIXME: overly conservative?
6717 
6718   switch (Opc1) {
6719   default: break;
6720   case X86::LD_Fp32m:
6721   case X86::LD_Fp64m:
6722   case X86::LD_Fp80m:
6723   case X86::MMX_MOVD64rm:
6724   case X86::MMX_MOVQ64rm:
6725     return false;
6726   }
6727 
6728   EVT VT = Load1->getValueType(0);
6729   switch (VT.getSimpleVT().SimpleTy) {
6730   default:
6731     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6732     // have 16 of them to play with.
6733     if (Subtarget.is64Bit()) {
6734       if (NumLoads >= 3)
6735         return false;
6736     } else if (NumLoads) {
6737       return false;
6738     }
6739     break;
6740   case MVT::i8:
6741   case MVT::i16:
6742   case MVT::i32:
6743   case MVT::i64:
6744   case MVT::f32:
6745   case MVT::f64:
6746     if (NumLoads)
6747       return false;
6748     break;
6749   }
6750 
6751   return true;
6752 }
6753 
6754 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
6755                                           MachineInstr *Second) const {
6756   // Check if this processor supports macro-fusion. Since this is a minor
6757   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6758   // proxy for SandyBridge+.
6759   if (!Subtarget.hasAVX())
6760     return false;
6761 
6762   enum {
6763     FuseTest,
6764     FuseCmp,
6765     FuseInc
6766   } FuseKind;
6767 
6768   switch(Second->getOpcode()) {
6769   default:
6770     return false;
6771   case X86::JE_1:
6772   case X86::JNE_1:
6773   case X86::JL_1:
6774   case X86::JLE_1:
6775   case X86::JG_1:
6776   case X86::JGE_1:
6777     FuseKind = FuseInc;
6778     break;
6779   case X86::JB_1:
6780   case X86::JBE_1:
6781   case X86::JA_1:
6782   case X86::JAE_1:
6783     FuseKind = FuseCmp;
6784     break;
6785   case X86::JS_1:
6786   case X86::JNS_1:
6787   case X86::JP_1:
6788   case X86::JNP_1:
6789   case X86::JO_1:
6790   case X86::JNO_1:
6791     FuseKind = FuseTest;
6792     break;
6793   }
6794   switch (First->getOpcode()) {
6795   default:
6796     return false;
6797   case X86::TEST8rr:
6798   case X86::TEST16rr:
6799   case X86::TEST32rr:
6800   case X86::TEST64rr:
6801   case X86::TEST8ri:
6802   case X86::TEST16ri:
6803   case X86::TEST32ri:
6804   case X86::TEST32i32:
6805   case X86::TEST64i32:
6806   case X86::TEST64ri32:
6807   case X86::TEST8rm:
6808   case X86::TEST16rm:
6809   case X86::TEST32rm:
6810   case X86::TEST64rm:
6811   case X86::TEST8ri_NOREX:
6812   case X86::AND16i16:
6813   case X86::AND16ri:
6814   case X86::AND16ri8:
6815   case X86::AND16rm:
6816   case X86::AND16rr:
6817   case X86::AND32i32:
6818   case X86::AND32ri:
6819   case X86::AND32ri8:
6820   case X86::AND32rm:
6821   case X86::AND32rr:
6822   case X86::AND64i32:
6823   case X86::AND64ri32:
6824   case X86::AND64ri8:
6825   case X86::AND64rm:
6826   case X86::AND64rr:
6827   case X86::AND8i8:
6828   case X86::AND8ri:
6829   case X86::AND8rm:
6830   case X86::AND8rr:
6831     return true;
6832   case X86::CMP16i16:
6833   case X86::CMP16ri:
6834   case X86::CMP16ri8:
6835   case X86::CMP16rm:
6836   case X86::CMP16rr:
6837   case X86::CMP32i32:
6838   case X86::CMP32ri:
6839   case X86::CMP32ri8:
6840   case X86::CMP32rm:
6841   case X86::CMP32rr:
6842   case X86::CMP64i32:
6843   case X86::CMP64ri32:
6844   case X86::CMP64ri8:
6845   case X86::CMP64rm:
6846   case X86::CMP64rr:
6847   case X86::CMP8i8:
6848   case X86::CMP8ri:
6849   case X86::CMP8rm:
6850   case X86::CMP8rr:
6851   case X86::ADD16i16:
6852   case X86::ADD16ri:
6853   case X86::ADD16ri8:
6854   case X86::ADD16ri8_DB:
6855   case X86::ADD16ri_DB:
6856   case X86::ADD16rm:
6857   case X86::ADD16rr:
6858   case X86::ADD16rr_DB:
6859   case X86::ADD32i32:
6860   case X86::ADD32ri:
6861   case X86::ADD32ri8:
6862   case X86::ADD32ri8_DB:
6863   case X86::ADD32ri_DB:
6864   case X86::ADD32rm:
6865   case X86::ADD32rr:
6866   case X86::ADD32rr_DB:
6867   case X86::ADD64i32:
6868   case X86::ADD64ri32:
6869   case X86::ADD64ri32_DB:
6870   case X86::ADD64ri8:
6871   case X86::ADD64ri8_DB:
6872   case X86::ADD64rm:
6873   case X86::ADD64rr:
6874   case X86::ADD64rr_DB:
6875   case X86::ADD8i8:
6876   case X86::ADD8mi:
6877   case X86::ADD8mr:
6878   case X86::ADD8ri:
6879   case X86::ADD8rm:
6880   case X86::ADD8rr:
6881   case X86::SUB16i16:
6882   case X86::SUB16ri:
6883   case X86::SUB16ri8:
6884   case X86::SUB16rm:
6885   case X86::SUB16rr:
6886   case X86::SUB32i32:
6887   case X86::SUB32ri:
6888   case X86::SUB32ri8:
6889   case X86::SUB32rm:
6890   case X86::SUB32rr:
6891   case X86::SUB64i32:
6892   case X86::SUB64ri32:
6893   case X86::SUB64ri8:
6894   case X86::SUB64rm:
6895   case X86::SUB64rr:
6896   case X86::SUB8i8:
6897   case X86::SUB8ri:
6898   case X86::SUB8rm:
6899   case X86::SUB8rr:
6900     return FuseKind == FuseCmp || FuseKind == FuseInc;
6901   case X86::INC16r:
6902   case X86::INC32r:
6903   case X86::INC64r:
6904   case X86::INC8r:
6905   case X86::DEC16r:
6906   case X86::DEC32r:
6907   case X86::DEC64r:
6908   case X86::DEC8r:
6909     return FuseKind == FuseInc;
6910   }
6911 }
6912 
6913 bool X86InstrInfo::
6914 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6915   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6916   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6917   Cond[0].setImm(GetOppositeBranchCondition(CC));
6918   return false;
6919 }
6920 
6921 bool X86InstrInfo::
6922 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6923   // FIXME: Return false for x87 stack register classes for now. We can't
6924   // allow any loads of these registers before FpGet_ST0_80.
6925   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6926            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
6927 }
6928 
6929 /// Return a virtual register initialized with the
6930 /// the global base register value. Output instructions required to
6931 /// initialize the register in the function entry block, if necessary.
6932 ///
6933 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6934 ///
6935 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6936   assert(!Subtarget.is64Bit() &&
6937          "X86-64 PIC uses RIP relative addressing");
6938 
6939   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6940   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6941   if (GlobalBaseReg != 0)
6942     return GlobalBaseReg;
6943 
6944   // Create the register. The code to initialize it is inserted
6945   // later, by the CGBR pass (below).
6946   MachineRegisterInfo &RegInfo = MF->getRegInfo();
6947   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
6948   X86FI->setGlobalBaseReg(GlobalBaseReg);
6949   return GlobalBaseReg;
6950 }
6951 
6952 // These are the replaceable SSE instructions. Some of these have Int variants
6953 // that we don't include here. We don't want to replace instructions selected
6954 // by intrinsics.
6955 static const uint16_t ReplaceableInstrs[][3] = {
6956   //PackedSingle     PackedDouble    PackedInt
6957   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
6958   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
6959   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
6960   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
6961   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
6962   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr  },
6963   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
6964   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
6965   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
6966   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
6967   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
6968   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
6969   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
6970   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
6971   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
6972   // AVX 128-bit support
6973   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
6974   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
6975   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
6976   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
6977   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
6978   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr  },
6979   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6980   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
6981   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
6982   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
6983   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
6984   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
6985   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
6986   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
6987   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
6988   // AVX 256-bit support
6989   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
6990   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
6991   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
6992   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
6993   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
6994   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
6995 };
6996 
6997 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6998   //PackedSingle       PackedDouble       PackedInt
6999   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
7000   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
7001   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
7002   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
7003   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
7004   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
7005   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
7006   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
7007   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7008   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7009   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
7010   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
7011   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
7012   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
7013   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7014   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7015   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7016   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7017   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7018   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
7019 };
7020 
7021 // FIXME: Some shuffle and unpack instructions have equivalents in different
7022 // domains, but they require a bit more work than just switching opcodes.
7023 
7024 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
7025   for (const uint16_t (&Row)[3] : ReplaceableInstrs)
7026     if (Row[domain-1] == opcode)
7027       return Row;
7028   return nullptr;
7029 }
7030 
7031 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
7032   for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
7033     if (Row[domain-1] == opcode)
7034       return Row;
7035   return nullptr;
7036 }
7037 
7038 std::pair<uint16_t, uint16_t>
7039 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
7040   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7041   bool hasAVX2 = Subtarget.hasAVX2();
7042   uint16_t validDomains = 0;
7043   if (domain && lookup(MI->getOpcode(), domain))
7044     validDomains = 0xe;
7045   else if (domain && lookupAVX2(MI->getOpcode(), domain))
7046     validDomains = hasAVX2 ? 0xe : 0x6;
7047   return std::make_pair(domain, validDomains);
7048 }
7049 
7050 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
7051   assert(Domain>0 && Domain<4 && "Invalid execution domain");
7052   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7053   assert(dom && "Not an SSE instruction");
7054   const uint16_t *table = lookup(MI->getOpcode(), dom);
7055   if (!table) { // try the other table
7056     assert((Subtarget.hasAVX2() || Domain < 3) &&
7057            "256-bit vector operations only available in AVX2");
7058     table = lookupAVX2(MI->getOpcode(), dom);
7059   }
7060   assert(table && "Cannot change domain");
7061   MI->setDesc(get(table[Domain-1]));
7062 }
7063 
7064 /// Return the noop instruction to use for a noop.
7065 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7066   NopInst.setOpcode(X86::NOOP);
7067 }
7068 
7069 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
7070 // In particular, getJumpInstrTableEntryBound must always return an upper bound
7071 // on the encoding lengths of the instructions generated by
7072 // getUnconditionalBranch and getTrap.
7073 void X86InstrInfo::getUnconditionalBranch(
7074     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
7075   Branch.setOpcode(X86::JMP_1);
7076   Branch.addOperand(MCOperand::createExpr(BranchTarget));
7077 }
7078 
7079 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
7080 // In particular, getJumpInstrTableEntryBound must always return an upper bound
7081 // on the encoding lengths of the instructions generated by
7082 // getUnconditionalBranch and getTrap.
7083 void X86InstrInfo::getTrap(MCInst &MI) const {
7084   MI.setOpcode(X86::TRAP);
7085 }
7086 
7087 // See getTrap and getUnconditionalBranch for conditions on the value returned
7088 // by this function.
7089 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7090   // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7091   // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7092   return 5;
7093 }
7094 
7095 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7096   switch (opc) {
7097   default: return false;
7098   case X86::DIVSDrm:
7099   case X86::DIVSDrm_Int:
7100   case X86::DIVSDrr:
7101   case X86::DIVSDrr_Int:
7102   case X86::DIVSSrm:
7103   case X86::DIVSSrm_Int:
7104   case X86::DIVSSrr:
7105   case X86::DIVSSrr_Int:
7106   case X86::SQRTPDm:
7107   case X86::SQRTPDr:
7108   case X86::SQRTPSm:
7109   case X86::SQRTPSr:
7110   case X86::SQRTSDm:
7111   case X86::SQRTSDm_Int:
7112   case X86::SQRTSDr:
7113   case X86::SQRTSDr_Int:
7114   case X86::SQRTSSm:
7115   case X86::SQRTSSm_Int:
7116   case X86::SQRTSSr:
7117   case X86::SQRTSSr_Int:
7118   // AVX instructions with high latency
7119   case X86::VDIVSDrm:
7120   case X86::VDIVSDrm_Int:
7121   case X86::VDIVSDrr:
7122   case X86::VDIVSDrr_Int:
7123   case X86::VDIVSSrm:
7124   case X86::VDIVSSrm_Int:
7125   case X86::VDIVSSrr:
7126   case X86::VDIVSSrr_Int:
7127   case X86::VSQRTPDm:
7128   case X86::VSQRTPDr:
7129   case X86::VSQRTPSm:
7130   case X86::VSQRTPSr:
7131   case X86::VSQRTSDm:
7132   case X86::VSQRTSDm_Int:
7133   case X86::VSQRTSDr:
7134   case X86::VSQRTSSm:
7135   case X86::VSQRTSSm_Int:
7136   case X86::VSQRTSSr:
7137   case X86::VSQRTPDZm:
7138   case X86::VSQRTPDZr:
7139   case X86::VSQRTPSZm:
7140   case X86::VSQRTPSZr:
7141   case X86::VSQRTSDZm:
7142   case X86::VSQRTSDZm_Int:
7143   case X86::VSQRTSDZr:
7144   case X86::VSQRTSSZm_Int:
7145   case X86::VSQRTSSZr:
7146   case X86::VSQRTSSZm:
7147   case X86::VDIVSDZrm:
7148   case X86::VDIVSDZrr:
7149   case X86::VDIVSSZrm:
7150   case X86::VDIVSSZrr:
7151 
7152   case X86::VGATHERQPSZrm:
7153   case X86::VGATHERQPDZrm:
7154   case X86::VGATHERDPDZrm:
7155   case X86::VGATHERDPSZrm:
7156   case X86::VPGATHERQDZrm:
7157   case X86::VPGATHERQQZrm:
7158   case X86::VPGATHERDDZrm:
7159   case X86::VPGATHERDQZrm:
7160   case X86::VSCATTERQPDZmr:
7161   case X86::VSCATTERQPSZmr:
7162   case X86::VSCATTERDPDZmr:
7163   case X86::VSCATTERDPSZmr:
7164   case X86::VPSCATTERQDZmr:
7165   case X86::VPSCATTERQQZmr:
7166   case X86::VPSCATTERDDZmr:
7167   case X86::VPSCATTERDQZmr:
7168     return true;
7169   }
7170 }
7171 
7172 bool X86InstrInfo::
7173 hasHighOperandLatency(const TargetSchedModel &SchedModel,
7174                       const MachineRegisterInfo *MRI,
7175                       const MachineInstr *DefMI, unsigned DefIdx,
7176                       const MachineInstr *UseMI, unsigned UseIdx) const {
7177   return isHighLatencyDef(DefMI->getOpcode());
7178 }
7179 
7180 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7181                                            const MachineBasicBlock *MBB) const {
7182   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7183          "Reassociation needs binary operators");
7184 
7185   // Integer binary math/logic instructions have a third source operand:
7186   // the EFLAGS register. That operand must be both defined here and never
7187   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7188   // not change anything because rearranging the operands could affect other
7189   // instructions that depend on the exact status flags (zero, sign, etc.)
7190   // that are set by using these particular operands with this operation.
7191   if (Inst.getNumOperands() == 4) {
7192     assert(Inst.getOperand(3).isReg() &&
7193            Inst.getOperand(3).getReg() == X86::EFLAGS &&
7194            "Unexpected operand in reassociable instruction");
7195     if (!Inst.getOperand(3).isDead())
7196       return false;
7197   }
7198 
7199   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7200 }
7201 
7202 // TODO: There are many more machine instruction opcodes to match:
7203 //       1. Other data types (integer, vectors)
7204 //       2. Other math / logic operations (xor, or)
7205 //       3. Other forms of the same operation (intrinsics and other variants)
7206 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7207   switch (Inst.getOpcode()) {
7208   case X86::AND8rr:
7209   case X86::AND16rr:
7210   case X86::AND32rr:
7211   case X86::AND64rr:
7212   case X86::OR8rr:
7213   case X86::OR16rr:
7214   case X86::OR32rr:
7215   case X86::OR64rr:
7216   case X86::XOR8rr:
7217   case X86::XOR16rr:
7218   case X86::XOR32rr:
7219   case X86::XOR64rr:
7220   case X86::IMUL16rr:
7221   case X86::IMUL32rr:
7222   case X86::IMUL64rr:
7223   case X86::PANDrr:
7224   case X86::PORrr:
7225   case X86::PXORrr:
7226   case X86::VPANDrr:
7227   case X86::VPANDYrr:
7228   case X86::VPORrr:
7229   case X86::VPORYrr:
7230   case X86::VPXORrr:
7231   case X86::VPXORYrr:
7232   // Normal min/max instructions are not commutative because of NaN and signed
7233   // zero semantics, but these are. Thus, there's no need to check for global
7234   // relaxed math; the instructions themselves have the properties we need.
7235   case X86::MAXCPDrr:
7236   case X86::MAXCPSrr:
7237   case X86::MAXCSDrr:
7238   case X86::MAXCSSrr:
7239   case X86::MINCPDrr:
7240   case X86::MINCPSrr:
7241   case X86::MINCSDrr:
7242   case X86::MINCSSrr:
7243   case X86::VMAXCPDrr:
7244   case X86::VMAXCPSrr:
7245   case X86::VMAXCPDYrr:
7246   case X86::VMAXCPSYrr:
7247   case X86::VMAXCSDrr:
7248   case X86::VMAXCSSrr:
7249   case X86::VMINCPDrr:
7250   case X86::VMINCPSrr:
7251   case X86::VMINCPDYrr:
7252   case X86::VMINCPSYrr:
7253   case X86::VMINCSDrr:
7254   case X86::VMINCSSrr:
7255     return true;
7256   case X86::ADDPDrr:
7257   case X86::ADDPSrr:
7258   case X86::ADDSDrr:
7259   case X86::ADDSSrr:
7260   case X86::MULPDrr:
7261   case X86::MULPSrr:
7262   case X86::MULSDrr:
7263   case X86::MULSSrr:
7264   case X86::VADDPDrr:
7265   case X86::VADDPSrr:
7266   case X86::VADDPDYrr:
7267   case X86::VADDPSYrr:
7268   case X86::VADDSDrr:
7269   case X86::VADDSSrr:
7270   case X86::VMULPDrr:
7271   case X86::VMULPSrr:
7272   case X86::VMULPDYrr:
7273   case X86::VMULPSYrr:
7274   case X86::VMULSDrr:
7275   case X86::VMULSSrr:
7276     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7277   default:
7278     return false;
7279   }
7280 }
7281 
7282 /// This is an architecture-specific helper function of reassociateOps.
7283 /// Set special operand attributes for new instructions after reassociation.
7284 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7285                                          MachineInstr &OldMI2,
7286                                          MachineInstr &NewMI1,
7287                                          MachineInstr &NewMI2) const {
7288   // Integer instructions define an implicit EFLAGS source register operand as
7289   // the third source (fourth total) operand.
7290   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7291     return;
7292 
7293   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7294          "Unexpected instruction type for reassociation");
7295 
7296   MachineOperand &OldOp1 = OldMI1.getOperand(3);
7297   MachineOperand &OldOp2 = OldMI2.getOperand(3);
7298   MachineOperand &NewOp1 = NewMI1.getOperand(3);
7299   MachineOperand &NewOp2 = NewMI2.getOperand(3);
7300 
7301   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7302          "Must have dead EFLAGS operand in reassociable instruction");
7303   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7304          "Must have dead EFLAGS operand in reassociable instruction");
7305 
7306   (void)OldOp1;
7307   (void)OldOp2;
7308 
7309   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7310          "Unexpected operand in reassociable instruction");
7311   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7312          "Unexpected operand in reassociable instruction");
7313 
7314   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7315   // of this pass or other passes. The EFLAGS operands must be dead in these new
7316   // instructions because the EFLAGS operands in the original instructions must
7317   // be dead in order for reassociation to occur.
7318   NewOp1.setIsDead();
7319   NewOp2.setIsDead();
7320 }
7321 
7322 std::pair<unsigned, unsigned>
7323 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7324   return std::make_pair(TF, 0u);
7325 }
7326 
7327 ArrayRef<std::pair<unsigned, const char *>>
7328 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7329   using namespace X86II;
7330   static const std::pair<unsigned, const char *> TargetFlags[] = {
7331       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7332       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7333       {MO_GOT, "x86-got"},
7334       {MO_GOTOFF, "x86-gotoff"},
7335       {MO_GOTPCREL, "x86-gotpcrel"},
7336       {MO_PLT, "x86-plt"},
7337       {MO_TLSGD, "x86-tlsgd"},
7338       {MO_TLSLD, "x86-tlsld"},
7339       {MO_TLSLDM, "x86-tlsldm"},
7340       {MO_GOTTPOFF, "x86-gottpoff"},
7341       {MO_INDNTPOFF, "x86-indntpoff"},
7342       {MO_TPOFF, "x86-tpoff"},
7343       {MO_DTPOFF, "x86-dtpoff"},
7344       {MO_NTPOFF, "x86-ntpoff"},
7345       {MO_GOTNTPOFF, "x86-gotntpoff"},
7346       {MO_DLLIMPORT, "x86-dllimport"},
7347       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7348       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7349       {MO_TLVP, "x86-tlvp"},
7350       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7351       {MO_SECREL, "x86-secrel"}};
7352   return makeArrayRef(TargetFlags);
7353 }
7354 
7355 namespace {
7356   /// Create Global Base Reg pass. This initializes the PIC
7357   /// global base register for x86-32.
7358   struct CGBR : public MachineFunctionPass {
7359     static char ID;
7360     CGBR() : MachineFunctionPass(ID) {}
7361 
7362     bool runOnMachineFunction(MachineFunction &MF) override {
7363       const X86TargetMachine *TM =
7364         static_cast<const X86TargetMachine *>(&MF.getTarget());
7365       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7366 
7367       // Don't do anything if this is 64-bit as 64-bit PIC
7368       // uses RIP relative addressing.
7369       if (STI.is64Bit())
7370         return false;
7371 
7372       // Only emit a global base reg in PIC mode.
7373       if (!TM->isPositionIndependent())
7374         return false;
7375 
7376       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7377       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7378 
7379       // If we didn't need a GlobalBaseReg, don't insert code.
7380       if (GlobalBaseReg == 0)
7381         return false;
7382 
7383       // Insert the set of GlobalBaseReg into the first MBB of the function
7384       MachineBasicBlock &FirstMBB = MF.front();
7385       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7386       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7387       MachineRegisterInfo &RegInfo = MF.getRegInfo();
7388       const X86InstrInfo *TII = STI.getInstrInfo();
7389 
7390       unsigned PC;
7391       if (STI.isPICStyleGOT())
7392         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7393       else
7394         PC = GlobalBaseReg;
7395 
7396       // Operand of MovePCtoStack is completely ignored by asm printer. It's
7397       // only used in JIT code emission as displacement to pc.
7398       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7399 
7400       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
7401       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7402       if (STI.isPICStyleGOT()) {
7403         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
7404         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7405           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7406                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
7407       }
7408 
7409       return true;
7410     }
7411 
7412     const char *getPassName() const override {
7413       return "X86 PIC Global Base Reg Initialization";
7414     }
7415 
7416     void getAnalysisUsage(AnalysisUsage &AU) const override {
7417       AU.setPreservesCFG();
7418       MachineFunctionPass::getAnalysisUsage(AU);
7419     }
7420   };
7421 }
7422 
7423 char CGBR::ID = 0;
7424 FunctionPass*
7425 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
7426 
7427 namespace {
7428   struct LDTLSCleanup : public MachineFunctionPass {
7429     static char ID;
7430     LDTLSCleanup() : MachineFunctionPass(ID) {}
7431 
7432     bool runOnMachineFunction(MachineFunction &MF) override {
7433       if (skipFunction(*MF.getFunction()))
7434         return false;
7435 
7436       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
7437       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7438         // No point folding accesses if there isn't at least two.
7439         return false;
7440       }
7441 
7442       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7443       return VisitNode(DT->getRootNode(), 0);
7444     }
7445 
7446     // Visit the dominator subtree rooted at Node in pre-order.
7447     // If TLSBaseAddrReg is non-null, then use that to replace any
7448     // TLS_base_addr instructions. Otherwise, create the register
7449     // when the first such instruction is seen, and then use it
7450     // as we encounter more instructions.
7451     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7452       MachineBasicBlock *BB = Node->getBlock();
7453       bool Changed = false;
7454 
7455       // Traverse the current block.
7456       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7457            ++I) {
7458         switch (I->getOpcode()) {
7459           case X86::TLS_base_addr32:
7460           case X86::TLS_base_addr64:
7461             if (TLSBaseAddrReg)
7462               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
7463             else
7464               I = SetRegister(I, &TLSBaseAddrReg);
7465             Changed = true;
7466             break;
7467           default:
7468             break;
7469         }
7470       }
7471 
7472       // Visit the children of this block in the dominator tree.
7473       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7474            I != E; ++I) {
7475         Changed |= VisitNode(*I, TLSBaseAddrReg);
7476       }
7477 
7478       return Changed;
7479     }
7480 
7481     // Replace the TLS_base_addr instruction I with a copy from
7482     // TLSBaseAddrReg, returning the new instruction.
7483     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
7484                                          unsigned TLSBaseAddrReg) {
7485       MachineFunction *MF = I->getParent()->getParent();
7486       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7487       const bool is64Bit = STI.is64Bit();
7488       const X86InstrInfo *TII = STI.getInstrInfo();
7489 
7490       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7491       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
7492                                    TII->get(TargetOpcode::COPY),
7493                                    is64Bit ? X86::RAX : X86::EAX)
7494                                    .addReg(TLSBaseAddrReg);
7495 
7496       // Erase the TLS_base_addr instruction.
7497       I->eraseFromParent();
7498 
7499       return Copy;
7500     }
7501 
7502     // Create a virtal register in *TLSBaseAddrReg, and populate it by
7503     // inserting a copy instruction after I. Returns the new instruction.
7504     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
7505       MachineFunction *MF = I->getParent()->getParent();
7506       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7507       const bool is64Bit = STI.is64Bit();
7508       const X86InstrInfo *TII = STI.getInstrInfo();
7509 
7510       // Create a virtual register for the TLS base address.
7511       MachineRegisterInfo &RegInfo = MF->getRegInfo();
7512       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7513                                                       ? &X86::GR64RegClass
7514                                                       : &X86::GR32RegClass);
7515 
7516       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7517       MachineInstr *Next = I->getNextNode();
7518       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
7519                                    TII->get(TargetOpcode::COPY),
7520                                    *TLSBaseAddrReg)
7521                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
7522 
7523       return Copy;
7524     }
7525 
7526     const char *getPassName() const override {
7527       return "Local Dynamic TLS Access Clean-up";
7528     }
7529 
7530     void getAnalysisUsage(AnalysisUsage &AU) const override {
7531       AU.setPreservesCFG();
7532       AU.addRequired<MachineDominatorTree>();
7533       MachineFunctionPass::getAnalysisUsage(AU);
7534     }
7535   };
7536 }
7537 
7538 char LDTLSCleanup::ID = 0;
7539 FunctionPass*
7540 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
7541