1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LivePhysRegs.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/DebugInfoMetadata.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "x86-instr-info"
46 
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "X86GenInstrInfo.inc"
49 
50 static cl::opt<bool>
51     NoFusing("disable-spill-fusing",
52              cl::desc("Disable fusing of spill code into instructions"),
53              cl::Hidden);
54 static cl::opt<bool>
55 PrintFailedFusing("print-failed-fuse-candidates",
56                   cl::desc("Print instructions that the allocator wants to"
57                            " fuse, but the X86 backend currently can't"),
58                   cl::Hidden);
59 static cl::opt<bool>
60 ReMatPICStubLoad("remat-pic-stub-load",
61                  cl::desc("Re-materialize load from stub in PIC mode"),
62                  cl::init(false), cl::Hidden);
63 static cl::opt<unsigned>
64 PartialRegUpdateClearance("partial-reg-update-clearance",
65                           cl::desc("Clearance between two register writes "
66                                    "for inserting XOR to avoid partial "
67                                    "register update"),
68                           cl::init(64), cl::Hidden);
69 static cl::opt<unsigned>
70 UndefRegClearance("undef-reg-clearance",
71                   cl::desc("How many idle instructions we would like before "
72                            "certain undef register reads"),
73                   cl::init(128), cl::Hidden);
74 
75 
76 // Pin the vtable to this file.
77 void X86InstrInfo::anchor() {}
78 
79 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81                                                : X86::ADJCALLSTACKDOWN32),
82                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83                                                : X86::ADJCALLSTACKUP32),
84                       X86::CATCHRET,
85                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86       Subtarget(STI), RI(STI.getTargetTriple()) {
87 }
88 
89 bool
90 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91                                     unsigned &SrcReg, unsigned &DstReg,
92                                     unsigned &SubIdx) const {
93   switch (MI.getOpcode()) {
94   default: break;
95   case X86::MOVSX16rr8:
96   case X86::MOVZX16rr8:
97   case X86::MOVSX32rr8:
98   case X86::MOVZX32rr8:
99   case X86::MOVSX64rr8:
100     if (!Subtarget.is64Bit())
101       // It's not always legal to reference the low 8-bit of the larger
102       // register in 32-bit mode.
103       return false;
104     LLVM_FALLTHROUGH;
105   case X86::MOVSX32rr16:
106   case X86::MOVZX32rr16:
107   case X86::MOVSX64rr16:
108   case X86::MOVSX64rr32: {
109     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110       // Be conservative.
111       return false;
112     SrcReg = MI.getOperand(1).getReg();
113     DstReg = MI.getOperand(0).getReg();
114     switch (MI.getOpcode()) {
115     default: llvm_unreachable("Unreachable!");
116     case X86::MOVSX16rr8:
117     case X86::MOVZX16rr8:
118     case X86::MOVSX32rr8:
119     case X86::MOVZX32rr8:
120     case X86::MOVSX64rr8:
121       SubIdx = X86::sub_8bit;
122       break;
123     case X86::MOVSX32rr16:
124     case X86::MOVZX32rr16:
125     case X86::MOVSX64rr16:
126       SubIdx = X86::sub_16bit;
127       break;
128     case X86::MOVSX64rr32:
129       SubIdx = X86::sub_32bit;
130       break;
131     }
132     return true;
133   }
134   }
135   return false;
136 }
137 
138 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
139   const MachineFunction *MF = MI.getParent()->getParent();
140   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
141 
142   if (isFrameInstr(MI)) {
143     unsigned StackAlign = TFI->getStackAlignment();
144     int SPAdj = alignTo(getFrameSize(MI), StackAlign);
145     SPAdj -= getFrameAdjustment(MI);
146     if (!isFrameSetup(MI))
147       SPAdj = -SPAdj;
148     return SPAdj;
149   }
150 
151   // To know whether a call adjusts the stack, we need information
152   // that is bound to the following ADJCALLSTACKUP pseudo.
153   // Look for the next ADJCALLSTACKUP that follows the call.
154   if (MI.isCall()) {
155     const MachineBasicBlock *MBB = MI.getParent();
156     auto I = ++MachineBasicBlock::const_iterator(MI);
157     for (auto E = MBB->end(); I != E; ++I) {
158       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
159           I->isCall())
160         break;
161     }
162 
163     // If we could not find a frame destroy opcode, then it has already
164     // been simplified, so we don't care.
165     if (I->getOpcode() != getCallFrameDestroyOpcode())
166       return 0;
167 
168     return -(I->getOperand(1).getImm());
169   }
170 
171   // Currently handle only PUSHes we can reasonably expect to see
172   // in call sequences
173   switch (MI.getOpcode()) {
174   default:
175     return 0;
176   case X86::PUSH32i8:
177   case X86::PUSH32r:
178   case X86::PUSH32rmm:
179   case X86::PUSH32rmr:
180   case X86::PUSHi32:
181     return 4;
182   case X86::PUSH64i8:
183   case X86::PUSH64r:
184   case X86::PUSH64rmm:
185   case X86::PUSH64rmr:
186   case X86::PUSH64i32:
187     return 8;
188   }
189 }
190 
191 /// Return true and the FrameIndex if the specified
192 /// operand and follow operands form a reference to the stack frame.
193 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
194                                   int &FrameIndex) const {
195   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
196       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
197       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
198       MI.getOperand(Op + X86::AddrDisp).isImm() &&
199       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
200       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
201       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
202     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
203     return true;
204   }
205   return false;
206 }
207 
208 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
209   switch (Opcode) {
210   default:
211     return false;
212   case X86::MOV8rm:
213   case X86::KMOVBkm:
214     MemBytes = 1;
215     return true;
216   case X86::MOV16rm:
217   case X86::KMOVWkm:
218     MemBytes = 2;
219     return true;
220   case X86::MOV32rm:
221   case X86::MOVSSrm:
222   case X86::MOVSSrm_alt:
223   case X86::VMOVSSrm:
224   case X86::VMOVSSrm_alt:
225   case X86::VMOVSSZrm:
226   case X86::VMOVSSZrm_alt:
227   case X86::KMOVDkm:
228     MemBytes = 4;
229     return true;
230   case X86::MOV64rm:
231   case X86::LD_Fp64m:
232   case X86::MOVSDrm:
233   case X86::MOVSDrm_alt:
234   case X86::VMOVSDrm:
235   case X86::VMOVSDrm_alt:
236   case X86::VMOVSDZrm:
237   case X86::VMOVSDZrm_alt:
238   case X86::MMX_MOVD64rm:
239   case X86::MMX_MOVQ64rm:
240   case X86::KMOVQkm:
241     MemBytes = 8;
242     return true;
243   case X86::MOVAPSrm:
244   case X86::MOVUPSrm:
245   case X86::MOVAPDrm:
246   case X86::MOVUPDrm:
247   case X86::MOVDQArm:
248   case X86::MOVDQUrm:
249   case X86::VMOVAPSrm:
250   case X86::VMOVUPSrm:
251   case X86::VMOVAPDrm:
252   case X86::VMOVUPDrm:
253   case X86::VMOVDQArm:
254   case X86::VMOVDQUrm:
255   case X86::VMOVAPSZ128rm:
256   case X86::VMOVUPSZ128rm:
257   case X86::VMOVAPSZ128rm_NOVLX:
258   case X86::VMOVUPSZ128rm_NOVLX:
259   case X86::VMOVAPDZ128rm:
260   case X86::VMOVUPDZ128rm:
261   case X86::VMOVDQU8Z128rm:
262   case X86::VMOVDQU16Z128rm:
263   case X86::VMOVDQA32Z128rm:
264   case X86::VMOVDQU32Z128rm:
265   case X86::VMOVDQA64Z128rm:
266   case X86::VMOVDQU64Z128rm:
267     MemBytes = 16;
268     return true;
269   case X86::VMOVAPSYrm:
270   case X86::VMOVUPSYrm:
271   case X86::VMOVAPDYrm:
272   case X86::VMOVUPDYrm:
273   case X86::VMOVDQAYrm:
274   case X86::VMOVDQUYrm:
275   case X86::VMOVAPSZ256rm:
276   case X86::VMOVUPSZ256rm:
277   case X86::VMOVAPSZ256rm_NOVLX:
278   case X86::VMOVUPSZ256rm_NOVLX:
279   case X86::VMOVAPDZ256rm:
280   case X86::VMOVUPDZ256rm:
281   case X86::VMOVDQU8Z256rm:
282   case X86::VMOVDQU16Z256rm:
283   case X86::VMOVDQA32Z256rm:
284   case X86::VMOVDQU32Z256rm:
285   case X86::VMOVDQA64Z256rm:
286   case X86::VMOVDQU64Z256rm:
287     MemBytes = 32;
288     return true;
289   case X86::VMOVAPSZrm:
290   case X86::VMOVUPSZrm:
291   case X86::VMOVAPDZrm:
292   case X86::VMOVUPDZrm:
293   case X86::VMOVDQU8Zrm:
294   case X86::VMOVDQU16Zrm:
295   case X86::VMOVDQA32Zrm:
296   case X86::VMOVDQU32Zrm:
297   case X86::VMOVDQA64Zrm:
298   case X86::VMOVDQU64Zrm:
299     MemBytes = 64;
300     return true;
301   }
302 }
303 
304 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
305   switch (Opcode) {
306   default:
307     return false;
308   case X86::MOV8mr:
309   case X86::KMOVBmk:
310     MemBytes = 1;
311     return true;
312   case X86::MOV16mr:
313   case X86::KMOVWmk:
314     MemBytes = 2;
315     return true;
316   case X86::MOV32mr:
317   case X86::MOVSSmr:
318   case X86::VMOVSSmr:
319   case X86::VMOVSSZmr:
320   case X86::KMOVDmk:
321     MemBytes = 4;
322     return true;
323   case X86::MOV64mr:
324   case X86::ST_FpP64m:
325   case X86::MOVSDmr:
326   case X86::VMOVSDmr:
327   case X86::VMOVSDZmr:
328   case X86::MMX_MOVD64mr:
329   case X86::MMX_MOVQ64mr:
330   case X86::MMX_MOVNTQmr:
331   case X86::KMOVQmk:
332     MemBytes = 8;
333     return true;
334   case X86::MOVAPSmr:
335   case X86::MOVUPSmr:
336   case X86::MOVAPDmr:
337   case X86::MOVUPDmr:
338   case X86::MOVDQAmr:
339   case X86::MOVDQUmr:
340   case X86::VMOVAPSmr:
341   case X86::VMOVUPSmr:
342   case X86::VMOVAPDmr:
343   case X86::VMOVUPDmr:
344   case X86::VMOVDQAmr:
345   case X86::VMOVDQUmr:
346   case X86::VMOVUPSZ128mr:
347   case X86::VMOVAPSZ128mr:
348   case X86::VMOVUPSZ128mr_NOVLX:
349   case X86::VMOVAPSZ128mr_NOVLX:
350   case X86::VMOVUPDZ128mr:
351   case X86::VMOVAPDZ128mr:
352   case X86::VMOVDQA32Z128mr:
353   case X86::VMOVDQU32Z128mr:
354   case X86::VMOVDQA64Z128mr:
355   case X86::VMOVDQU64Z128mr:
356   case X86::VMOVDQU8Z128mr:
357   case X86::VMOVDQU16Z128mr:
358     MemBytes = 16;
359     return true;
360   case X86::VMOVUPSYmr:
361   case X86::VMOVAPSYmr:
362   case X86::VMOVUPDYmr:
363   case X86::VMOVAPDYmr:
364   case X86::VMOVDQUYmr:
365   case X86::VMOVDQAYmr:
366   case X86::VMOVUPSZ256mr:
367   case X86::VMOVAPSZ256mr:
368   case X86::VMOVUPSZ256mr_NOVLX:
369   case X86::VMOVAPSZ256mr_NOVLX:
370   case X86::VMOVUPDZ256mr:
371   case X86::VMOVAPDZ256mr:
372   case X86::VMOVDQU8Z256mr:
373   case X86::VMOVDQU16Z256mr:
374   case X86::VMOVDQA32Z256mr:
375   case X86::VMOVDQU32Z256mr:
376   case X86::VMOVDQA64Z256mr:
377   case X86::VMOVDQU64Z256mr:
378     MemBytes = 32;
379     return true;
380   case X86::VMOVUPSZmr:
381   case X86::VMOVAPSZmr:
382   case X86::VMOVUPDZmr:
383   case X86::VMOVAPDZmr:
384   case X86::VMOVDQU8Zmr:
385   case X86::VMOVDQU16Zmr:
386   case X86::VMOVDQA32Zmr:
387   case X86::VMOVDQU32Zmr:
388   case X86::VMOVDQA64Zmr:
389   case X86::VMOVDQU64Zmr:
390     MemBytes = 64;
391     return true;
392   }
393   return false;
394 }
395 
396 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
397                                            int &FrameIndex) const {
398   unsigned Dummy;
399   return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
400 }
401 
402 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
403                                            int &FrameIndex,
404                                            unsigned &MemBytes) const {
405   if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
406     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
407       return MI.getOperand(0).getReg();
408   return 0;
409 }
410 
411 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
412                                                  int &FrameIndex) const {
413   unsigned Dummy;
414   if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
415     unsigned Reg;
416     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
417       return Reg;
418     // Check for post-frame index elimination operations
419     SmallVector<const MachineMemOperand *, 1> Accesses;
420     if (hasLoadFromStackSlot(MI, Accesses)) {
421       FrameIndex =
422           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
423               ->getFrameIndex();
424       return 1;
425     }
426   }
427   return 0;
428 }
429 
430 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
431                                           int &FrameIndex) const {
432   unsigned Dummy;
433   return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
434 }
435 
436 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
437                                           int &FrameIndex,
438                                           unsigned &MemBytes) const {
439   if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
440     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
441         isFrameOperand(MI, 0, FrameIndex))
442       return MI.getOperand(X86::AddrNumOperands).getReg();
443   return 0;
444 }
445 
446 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
447                                                 int &FrameIndex) const {
448   unsigned Dummy;
449   if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
450     unsigned Reg;
451     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
452       return Reg;
453     // Check for post-frame index elimination operations
454     SmallVector<const MachineMemOperand *, 1> Accesses;
455     if (hasStoreToStackSlot(MI, Accesses)) {
456       FrameIndex =
457           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
458               ->getFrameIndex();
459       return 1;
460     }
461   }
462   return 0;
463 }
464 
465 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
466 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
467   // Don't waste compile time scanning use-def chains of physregs.
468   if (!Register::isVirtualRegister(BaseReg))
469     return false;
470   bool isPICBase = false;
471   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
472          E = MRI.def_instr_end(); I != E; ++I) {
473     MachineInstr *DefMI = &*I;
474     if (DefMI->getOpcode() != X86::MOVPC32r)
475       return false;
476     assert(!isPICBase && "More than one PIC base?");
477     isPICBase = true;
478   }
479   return isPICBase;
480 }
481 
482 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
483                                                      AAResults *AA) const {
484   switch (MI.getOpcode()) {
485   default:
486     // This function should only be called for opcodes with the ReMaterializable
487     // flag set.
488     llvm_unreachable("Unknown rematerializable operation!");
489     break;
490 
491   case X86::LOAD_STACK_GUARD:
492   case X86::AVX1_SETALLONES:
493   case X86::AVX2_SETALLONES:
494   case X86::AVX512_128_SET0:
495   case X86::AVX512_256_SET0:
496   case X86::AVX512_512_SET0:
497   case X86::AVX512_512_SETALLONES:
498   case X86::AVX512_FsFLD0SD:
499   case X86::AVX512_FsFLD0SS:
500   case X86::AVX512_FsFLD0F128:
501   case X86::AVX_SET0:
502   case X86::FsFLD0SD:
503   case X86::FsFLD0SS:
504   case X86::FsFLD0F128:
505   case X86::KSET0D:
506   case X86::KSET0Q:
507   case X86::KSET0W:
508   case X86::KSET1D:
509   case X86::KSET1Q:
510   case X86::KSET1W:
511   case X86::MMX_SET0:
512   case X86::MOV32ImmSExti8:
513   case X86::MOV32r0:
514   case X86::MOV32r1:
515   case X86::MOV32r_1:
516   case X86::MOV32ri64:
517   case X86::MOV64ImmSExti8:
518   case X86::V_SET0:
519   case X86::V_SETALLONES:
520   case X86::MOV16ri:
521   case X86::MOV32ri:
522   case X86::MOV64ri:
523   case X86::MOV64ri32:
524   case X86::MOV8ri:
525     return true;
526 
527   case X86::MOV8rm:
528   case X86::MOV8rm_NOREX:
529   case X86::MOV16rm:
530   case X86::MOV32rm:
531   case X86::MOV64rm:
532   case X86::MOVSSrm:
533   case X86::MOVSSrm_alt:
534   case X86::MOVSDrm:
535   case X86::MOVSDrm_alt:
536   case X86::MOVAPSrm:
537   case X86::MOVUPSrm:
538   case X86::MOVAPDrm:
539   case X86::MOVUPDrm:
540   case X86::MOVDQArm:
541   case X86::MOVDQUrm:
542   case X86::VMOVSSrm:
543   case X86::VMOVSSrm_alt:
544   case X86::VMOVSDrm:
545   case X86::VMOVSDrm_alt:
546   case X86::VMOVAPSrm:
547   case X86::VMOVUPSrm:
548   case X86::VMOVAPDrm:
549   case X86::VMOVUPDrm:
550   case X86::VMOVDQArm:
551   case X86::VMOVDQUrm:
552   case X86::VMOVAPSYrm:
553   case X86::VMOVUPSYrm:
554   case X86::VMOVAPDYrm:
555   case X86::VMOVUPDYrm:
556   case X86::VMOVDQAYrm:
557   case X86::VMOVDQUYrm:
558   case X86::MMX_MOVD64rm:
559   case X86::MMX_MOVQ64rm:
560   // AVX-512
561   case X86::VMOVSSZrm:
562   case X86::VMOVSSZrm_alt:
563   case X86::VMOVSDZrm:
564   case X86::VMOVSDZrm_alt:
565   case X86::VMOVAPDZ128rm:
566   case X86::VMOVAPDZ256rm:
567   case X86::VMOVAPDZrm:
568   case X86::VMOVAPSZ128rm:
569   case X86::VMOVAPSZ256rm:
570   case X86::VMOVAPSZ128rm_NOVLX:
571   case X86::VMOVAPSZ256rm_NOVLX:
572   case X86::VMOVAPSZrm:
573   case X86::VMOVDQA32Z128rm:
574   case X86::VMOVDQA32Z256rm:
575   case X86::VMOVDQA32Zrm:
576   case X86::VMOVDQA64Z128rm:
577   case X86::VMOVDQA64Z256rm:
578   case X86::VMOVDQA64Zrm:
579   case X86::VMOVDQU16Z128rm:
580   case X86::VMOVDQU16Z256rm:
581   case X86::VMOVDQU16Zrm:
582   case X86::VMOVDQU32Z128rm:
583   case X86::VMOVDQU32Z256rm:
584   case X86::VMOVDQU32Zrm:
585   case X86::VMOVDQU64Z128rm:
586   case X86::VMOVDQU64Z256rm:
587   case X86::VMOVDQU64Zrm:
588   case X86::VMOVDQU8Z128rm:
589   case X86::VMOVDQU8Z256rm:
590   case X86::VMOVDQU8Zrm:
591   case X86::VMOVUPDZ128rm:
592   case X86::VMOVUPDZ256rm:
593   case X86::VMOVUPDZrm:
594   case X86::VMOVUPSZ128rm:
595   case X86::VMOVUPSZ256rm:
596   case X86::VMOVUPSZ128rm_NOVLX:
597   case X86::VMOVUPSZ256rm_NOVLX:
598   case X86::VMOVUPSZrm: {
599     // Loads from constant pools are trivially rematerializable.
600     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
601         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
602         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
603         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
604         MI.isDereferenceableInvariantLoad(AA)) {
605       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
606       if (BaseReg == 0 || BaseReg == X86::RIP)
607         return true;
608       // Allow re-materialization of PIC load.
609       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
610         return false;
611       const MachineFunction &MF = *MI.getParent()->getParent();
612       const MachineRegisterInfo &MRI = MF.getRegInfo();
613       return regIsPICBase(BaseReg, MRI);
614     }
615     return false;
616   }
617 
618   case X86::LEA32r:
619   case X86::LEA64r: {
620     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
621         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
622         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
623         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
624       // lea fi#, lea GV, etc. are all rematerializable.
625       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
626         return true;
627       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
628       if (BaseReg == 0)
629         return true;
630       // Allow re-materialization of lea PICBase + x.
631       const MachineFunction &MF = *MI.getParent()->getParent();
632       const MachineRegisterInfo &MRI = MF.getRegInfo();
633       return regIsPICBase(BaseReg, MRI);
634     }
635     return false;
636   }
637   }
638 }
639 
640 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
641                                  MachineBasicBlock::iterator I,
642                                  unsigned DestReg, unsigned SubIdx,
643                                  const MachineInstr &Orig,
644                                  const TargetRegisterInfo &TRI) const {
645   bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
646   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
647     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
648     // effects.
649     int Value;
650     switch (Orig.getOpcode()) {
651     case X86::MOV32r0:  Value = 0; break;
652     case X86::MOV32r1:  Value = 1; break;
653     case X86::MOV32r_1: Value = -1; break;
654     default:
655       llvm_unreachable("Unexpected instruction!");
656     }
657 
658     const DebugLoc &DL = Orig.getDebugLoc();
659     BuildMI(MBB, I, DL, get(X86::MOV32ri))
660         .add(Orig.getOperand(0))
661         .addImm(Value);
662   } else {
663     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
664     MBB.insert(I, MI);
665   }
666 
667   MachineInstr &NewMI = *std::prev(I);
668   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
669 }
670 
671 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
672 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
673   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
674     MachineOperand &MO = MI.getOperand(i);
675     if (MO.isReg() && MO.isDef() &&
676         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
677       return true;
678     }
679   }
680   return false;
681 }
682 
683 /// Check whether the shift count for a machine operand is non-zero.
684 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
685                                               unsigned ShiftAmtOperandIdx) {
686   // The shift count is six bits with the REX.W prefix and five bits without.
687   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
688   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
689   return Imm & ShiftCountMask;
690 }
691 
692 /// Check whether the given shift count is appropriate
693 /// can be represented by a LEA instruction.
694 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
695   // Left shift instructions can be transformed into load-effective-address
696   // instructions if we can encode them appropriately.
697   // A LEA instruction utilizes a SIB byte to encode its scale factor.
698   // The SIB.scale field is two bits wide which means that we can encode any
699   // shift amount less than 4.
700   return ShAmt < 4 && ShAmt > 0;
701 }
702 
703 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
704                                   unsigned Opc, bool AllowSP, Register &NewSrc,
705                                   bool &isKill, MachineOperand &ImplicitOp,
706                                   LiveVariables *LV) const {
707   MachineFunction &MF = *MI.getParent()->getParent();
708   const TargetRegisterClass *RC;
709   if (AllowSP) {
710     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
711   } else {
712     RC = Opc != X86::LEA32r ?
713       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
714   }
715   Register SrcReg = Src.getReg();
716 
717   // For both LEA64 and LEA32 the register already has essentially the right
718   // type (32-bit or 64-bit) we may just need to forbid SP.
719   if (Opc != X86::LEA64_32r) {
720     NewSrc = SrcReg;
721     isKill = Src.isKill();
722     assert(!Src.isUndef() && "Undef op doesn't need optimization");
723 
724     if (Register::isVirtualRegister(NewSrc) &&
725         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
726       return false;
727 
728     return true;
729   }
730 
731   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
732   // another we need to add 64-bit registers to the final MI.
733   if (Register::isPhysicalRegister(SrcReg)) {
734     ImplicitOp = Src;
735     ImplicitOp.setImplicit();
736 
737     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
738     isKill = Src.isKill();
739     assert(!Src.isUndef() && "Undef op doesn't need optimization");
740   } else {
741     // Virtual register of the wrong class, we have to create a temporary 64-bit
742     // vreg to feed into the LEA.
743     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
744     MachineInstr *Copy =
745         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
746             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
747             .add(Src);
748 
749     // Which is obviously going to be dead after we're done with it.
750     isKill = true;
751 
752     if (LV)
753       LV->replaceKillInstruction(SrcReg, MI, *Copy);
754   }
755 
756   // We've set all the parameters without issue.
757   return true;
758 }
759 
760 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
761     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
762     LiveVariables *LV, bool Is8BitOp) const {
763   // We handle 8-bit adds and various 16-bit opcodes in the switch below.
764   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
765   assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
766               *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
767          "Unexpected type for LEA transform");
768 
769   // TODO: For a 32-bit target, we need to adjust the LEA variables with
770   // something like this:
771   //   Opcode = X86::LEA32r;
772   //   InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
773   //   OutRegLEA =
774   //       Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
775   //                : RegInfo.createVirtualRegister(&X86::GR32RegClass);
776   if (!Subtarget.is64Bit())
777     return nullptr;
778 
779   unsigned Opcode = X86::LEA64_32r;
780   Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
781   Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
782 
783   // Build and insert into an implicit UNDEF value. This is OK because
784   // we will be shifting and then extracting the lower 8/16-bits.
785   // This has the potential to cause partial register stall. e.g.
786   //   movw    (%rbp,%rcx,2), %dx
787   //   leal    -65(%rdx), %esi
788   // But testing has shown this *does* help performance in 64-bit mode (at
789   // least on modern x86 machines).
790   MachineBasicBlock::iterator MBBI = MI.getIterator();
791   Register Dest = MI.getOperand(0).getReg();
792   Register Src = MI.getOperand(1).getReg();
793   bool IsDead = MI.getOperand(0).isDead();
794   bool IsKill = MI.getOperand(1).isKill();
795   unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
796   assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
797   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
798   MachineInstr *InsMI =
799       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
800           .addReg(InRegLEA, RegState::Define, SubReg)
801           .addReg(Src, getKillRegState(IsKill));
802 
803   MachineInstrBuilder MIB =
804       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
805   switch (MIOpc) {
806   default: llvm_unreachable("Unreachable!");
807   case X86::SHL8ri:
808   case X86::SHL16ri: {
809     unsigned ShAmt = MI.getOperand(2).getImm();
810     MIB.addReg(0).addImm(1ULL << ShAmt)
811        .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
812     break;
813   }
814   case X86::INC8r:
815   case X86::INC16r:
816     addRegOffset(MIB, InRegLEA, true, 1);
817     break;
818   case X86::DEC8r:
819   case X86::DEC16r:
820     addRegOffset(MIB, InRegLEA, true, -1);
821     break;
822   case X86::ADD8ri:
823   case X86::ADD8ri_DB:
824   case X86::ADD16ri:
825   case X86::ADD16ri8:
826   case X86::ADD16ri_DB:
827   case X86::ADD16ri8_DB:
828     addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
829     break;
830   case X86::ADD8rr:
831   case X86::ADD8rr_DB:
832   case X86::ADD16rr:
833   case X86::ADD16rr_DB: {
834     Register Src2 = MI.getOperand(2).getReg();
835     bool IsKill2 = MI.getOperand(2).isKill();
836     assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
837     unsigned InRegLEA2 = 0;
838     MachineInstr *InsMI2 = nullptr;
839     if (Src == Src2) {
840       // ADD8rr/ADD16rr killed %reg1028, %reg1028
841       // just a single insert_subreg.
842       addRegReg(MIB, InRegLEA, true, InRegLEA, false);
843     } else {
844       if (Subtarget.is64Bit())
845         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
846       else
847         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
848       // Build and insert into an implicit UNDEF value. This is OK because
849       // we will be shifting and then extracting the lower 8/16-bits.
850       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
851       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
852                    .addReg(InRegLEA2, RegState::Define, SubReg)
853                    .addReg(Src2, getKillRegState(IsKill2));
854       addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
855     }
856     if (LV && IsKill2 && InsMI2)
857       LV->replaceKillInstruction(Src2, MI, *InsMI2);
858     break;
859   }
860   }
861 
862   MachineInstr *NewMI = MIB;
863   MachineInstr *ExtMI =
864       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
865           .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
866           .addReg(OutRegLEA, RegState::Kill, SubReg);
867 
868   if (LV) {
869     // Update live variables.
870     LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
871     LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
872     if (IsKill)
873       LV->replaceKillInstruction(Src, MI, *InsMI);
874     if (IsDead)
875       LV->replaceKillInstruction(Dest, MI, *ExtMI);
876   }
877 
878   return ExtMI;
879 }
880 
881 /// This method must be implemented by targets that
882 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
883 /// may be able to convert a two-address instruction into a true
884 /// three-address instruction on demand.  This allows the X86 target (for
885 /// example) to convert ADD and SHL instructions into LEA instructions if they
886 /// would require register copies due to two-addressness.
887 ///
888 /// This method returns a null pointer if the transformation cannot be
889 /// performed, otherwise it returns the new instruction.
890 ///
891 MachineInstr *
892 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
893                                     MachineInstr &MI, LiveVariables *LV) const {
894   // The following opcodes also sets the condition code register(s). Only
895   // convert them to equivalent lea if the condition code register def's
896   // are dead!
897   if (hasLiveCondCodeDef(MI))
898     return nullptr;
899 
900   MachineFunction &MF = *MI.getParent()->getParent();
901   // All instructions input are two-addr instructions.  Get the known operands.
902   const MachineOperand &Dest = MI.getOperand(0);
903   const MachineOperand &Src = MI.getOperand(1);
904 
905   // Ideally, operations with undef should be folded before we get here, but we
906   // can't guarantee it. Bail out because optimizing undefs is a waste of time.
907   // Without this, we have to forward undef state to new register operands to
908   // avoid machine verifier errors.
909   if (Src.isUndef())
910     return nullptr;
911   if (MI.getNumOperands() > 2)
912     if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
913       return nullptr;
914 
915   MachineInstr *NewMI = nullptr;
916   bool Is64Bit = Subtarget.is64Bit();
917 
918   bool Is8BitOp = false;
919   unsigned MIOpc = MI.getOpcode();
920   switch (MIOpc) {
921   default: llvm_unreachable("Unreachable!");
922   case X86::SHL64ri: {
923     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
924     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
925     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
926 
927     // LEA can't handle RSP.
928     if (Register::isVirtualRegister(Src.getReg()) &&
929         !MF.getRegInfo().constrainRegClass(Src.getReg(),
930                                            &X86::GR64_NOSPRegClass))
931       return nullptr;
932 
933     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
934                 .add(Dest)
935                 .addReg(0)
936                 .addImm(1ULL << ShAmt)
937                 .add(Src)
938                 .addImm(0)
939                 .addReg(0);
940     break;
941   }
942   case X86::SHL32ri: {
943     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
944     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
945     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
946 
947     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
948 
949     // LEA can't handle ESP.
950     bool isKill;
951     Register SrcReg;
952     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
953     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
954                         SrcReg, isKill, ImplicitOp, LV))
955       return nullptr;
956 
957     MachineInstrBuilder MIB =
958         BuildMI(MF, MI.getDebugLoc(), get(Opc))
959             .add(Dest)
960             .addReg(0)
961             .addImm(1ULL << ShAmt)
962             .addReg(SrcReg, getKillRegState(isKill))
963             .addImm(0)
964             .addReg(0);
965     if (ImplicitOp.getReg() != 0)
966       MIB.add(ImplicitOp);
967     NewMI = MIB;
968 
969     break;
970   }
971   case X86::SHL8ri:
972     Is8BitOp = true;
973     LLVM_FALLTHROUGH;
974   case X86::SHL16ri: {
975     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
976     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
977     if (!isTruncatedShiftCountForLEA(ShAmt))
978       return nullptr;
979     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
980   }
981   case X86::INC64r:
982   case X86::INC32r: {
983     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
984     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
985         (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
986     bool isKill;
987     Register SrcReg;
988     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
989     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
990                         ImplicitOp, LV))
991       return nullptr;
992 
993     MachineInstrBuilder MIB =
994         BuildMI(MF, MI.getDebugLoc(), get(Opc))
995             .add(Dest)
996             .addReg(SrcReg, getKillRegState(isKill));
997     if (ImplicitOp.getReg() != 0)
998       MIB.add(ImplicitOp);
999 
1000     NewMI = addOffset(MIB, 1);
1001     break;
1002   }
1003   case X86::DEC64r:
1004   case X86::DEC32r: {
1005     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1006     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1007         : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1008 
1009     bool isKill;
1010     Register SrcReg;
1011     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1012     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1013                         ImplicitOp, LV))
1014       return nullptr;
1015 
1016     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1017                                   .add(Dest)
1018                                   .addReg(SrcReg, getKillRegState(isKill));
1019     if (ImplicitOp.getReg() != 0)
1020       MIB.add(ImplicitOp);
1021 
1022     NewMI = addOffset(MIB, -1);
1023 
1024     break;
1025   }
1026   case X86::DEC8r:
1027   case X86::INC8r:
1028     Is8BitOp = true;
1029     LLVM_FALLTHROUGH;
1030   case X86::DEC16r:
1031   case X86::INC16r:
1032     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1033   case X86::ADD64rr:
1034   case X86::ADD64rr_DB:
1035   case X86::ADD32rr:
1036   case X86::ADD32rr_DB: {
1037     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1038     unsigned Opc;
1039     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1040       Opc = X86::LEA64r;
1041     else
1042       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1043 
1044     bool isKill;
1045     Register SrcReg;
1046     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1047     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1048                         SrcReg, isKill, ImplicitOp, LV))
1049       return nullptr;
1050 
1051     const MachineOperand &Src2 = MI.getOperand(2);
1052     bool isKill2;
1053     Register SrcReg2;
1054     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1055     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1056                         SrcReg2, isKill2, ImplicitOp2, LV))
1057       return nullptr;
1058 
1059     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1060     if (ImplicitOp.getReg() != 0)
1061       MIB.add(ImplicitOp);
1062     if (ImplicitOp2.getReg() != 0)
1063       MIB.add(ImplicitOp2);
1064 
1065     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1066     if (LV && Src2.isKill())
1067       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1068     break;
1069   }
1070   case X86::ADD8rr:
1071   case X86::ADD8rr_DB:
1072     Is8BitOp = true;
1073     LLVM_FALLTHROUGH;
1074   case X86::ADD16rr:
1075   case X86::ADD16rr_DB:
1076     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1077   case X86::ADD64ri32:
1078   case X86::ADD64ri8:
1079   case X86::ADD64ri32_DB:
1080   case X86::ADD64ri8_DB:
1081     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1082     NewMI = addOffset(
1083         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1084         MI.getOperand(2));
1085     break;
1086   case X86::ADD32ri:
1087   case X86::ADD32ri8:
1088   case X86::ADD32ri_DB:
1089   case X86::ADD32ri8_DB: {
1090     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1091     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1092 
1093     bool isKill;
1094     Register SrcReg;
1095     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1096     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1097                         SrcReg, isKill, ImplicitOp, LV))
1098       return nullptr;
1099 
1100     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1101                                   .add(Dest)
1102                                   .addReg(SrcReg, getKillRegState(isKill));
1103     if (ImplicitOp.getReg() != 0)
1104       MIB.add(ImplicitOp);
1105 
1106     NewMI = addOffset(MIB, MI.getOperand(2));
1107     break;
1108   }
1109   case X86::ADD8ri:
1110   case X86::ADD8ri_DB:
1111     Is8BitOp = true;
1112     LLVM_FALLTHROUGH;
1113   case X86::ADD16ri:
1114   case X86::ADD16ri8:
1115   case X86::ADD16ri_DB:
1116   case X86::ADD16ri8_DB:
1117     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1118   case X86::SUB8ri:
1119   case X86::SUB16ri8:
1120   case X86::SUB16ri:
1121     /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1122     return nullptr;
1123   case X86::SUB32ri8:
1124   case X86::SUB32ri: {
1125     if (!MI.getOperand(2).isImm())
1126       return nullptr;
1127     int64_t Imm = MI.getOperand(2).getImm();
1128     if (!isInt<32>(-Imm))
1129       return nullptr;
1130 
1131     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1132     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1133 
1134     bool isKill;
1135     Register SrcReg;
1136     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1137     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1138                         SrcReg, isKill, ImplicitOp, LV))
1139       return nullptr;
1140 
1141     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1142                                   .add(Dest)
1143                                   .addReg(SrcReg, getKillRegState(isKill));
1144     if (ImplicitOp.getReg() != 0)
1145       MIB.add(ImplicitOp);
1146 
1147     NewMI = addOffset(MIB, -Imm);
1148     break;
1149   }
1150 
1151   case X86::SUB64ri8:
1152   case X86::SUB64ri32: {
1153     if (!MI.getOperand(2).isImm())
1154       return nullptr;
1155     int64_t Imm = MI.getOperand(2).getImm();
1156     if (!isInt<32>(-Imm))
1157       return nullptr;
1158 
1159     assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1160 
1161     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1162                                       get(X86::LEA64r)).add(Dest).add(Src);
1163     NewMI = addOffset(MIB, -Imm);
1164     break;
1165   }
1166 
1167   case X86::VMOVDQU8Z128rmk:
1168   case X86::VMOVDQU8Z256rmk:
1169   case X86::VMOVDQU8Zrmk:
1170   case X86::VMOVDQU16Z128rmk:
1171   case X86::VMOVDQU16Z256rmk:
1172   case X86::VMOVDQU16Zrmk:
1173   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1174   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1175   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
1176   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1177   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1178   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
1179   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
1180   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
1181   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
1182   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
1183   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
1184   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk:
1185   case X86::VBROADCASTSDZ256mk:
1186   case X86::VBROADCASTSDZmk:
1187   case X86::VBROADCASTSSZ128mk:
1188   case X86::VBROADCASTSSZ256mk:
1189   case X86::VBROADCASTSSZmk:
1190   case X86::VPBROADCASTDZ128mk:
1191   case X86::VPBROADCASTDZ256mk:
1192   case X86::VPBROADCASTDZmk:
1193   case X86::VPBROADCASTQZ128mk:
1194   case X86::VPBROADCASTQZ256mk:
1195   case X86::VPBROADCASTQZmk: {
1196     unsigned Opc;
1197     switch (MIOpc) {
1198     default: llvm_unreachable("Unreachable!");
1199     case X86::VMOVDQU8Z128rmk:    Opc = X86::VPBLENDMBZ128rmk; break;
1200     case X86::VMOVDQU8Z256rmk:    Opc = X86::VPBLENDMBZ256rmk; break;
1201     case X86::VMOVDQU8Zrmk:       Opc = X86::VPBLENDMBZrmk;    break;
1202     case X86::VMOVDQU16Z128rmk:   Opc = X86::VPBLENDMWZ128rmk; break;
1203     case X86::VMOVDQU16Z256rmk:   Opc = X86::VPBLENDMWZ256rmk; break;
1204     case X86::VMOVDQU16Zrmk:      Opc = X86::VPBLENDMWZrmk;    break;
1205     case X86::VMOVDQU32Z128rmk:   Opc = X86::VPBLENDMDZ128rmk; break;
1206     case X86::VMOVDQU32Z256rmk:   Opc = X86::VPBLENDMDZ256rmk; break;
1207     case X86::VMOVDQU32Zrmk:      Opc = X86::VPBLENDMDZrmk;    break;
1208     case X86::VMOVDQU64Z128rmk:   Opc = X86::VPBLENDMQZ128rmk; break;
1209     case X86::VMOVDQU64Z256rmk:   Opc = X86::VPBLENDMQZ256rmk; break;
1210     case X86::VMOVDQU64Zrmk:      Opc = X86::VPBLENDMQZrmk;    break;
1211     case X86::VMOVUPDZ128rmk:     Opc = X86::VBLENDMPDZ128rmk; break;
1212     case X86::VMOVUPDZ256rmk:     Opc = X86::VBLENDMPDZ256rmk; break;
1213     case X86::VMOVUPDZrmk:        Opc = X86::VBLENDMPDZrmk;    break;
1214     case X86::VMOVUPSZ128rmk:     Opc = X86::VBLENDMPSZ128rmk; break;
1215     case X86::VMOVUPSZ256rmk:     Opc = X86::VBLENDMPSZ256rmk; break;
1216     case X86::VMOVUPSZrmk:        Opc = X86::VBLENDMPSZrmk;    break;
1217     case X86::VMOVDQA32Z128rmk:   Opc = X86::VPBLENDMDZ128rmk; break;
1218     case X86::VMOVDQA32Z256rmk:   Opc = X86::VPBLENDMDZ256rmk; break;
1219     case X86::VMOVDQA32Zrmk:      Opc = X86::VPBLENDMDZrmk;    break;
1220     case X86::VMOVDQA64Z128rmk:   Opc = X86::VPBLENDMQZ128rmk; break;
1221     case X86::VMOVDQA64Z256rmk:   Opc = X86::VPBLENDMQZ256rmk; break;
1222     case X86::VMOVDQA64Zrmk:      Opc = X86::VPBLENDMQZrmk;    break;
1223     case X86::VMOVAPDZ128rmk:     Opc = X86::VBLENDMPDZ128rmk; break;
1224     case X86::VMOVAPDZ256rmk:     Opc = X86::VBLENDMPDZ256rmk; break;
1225     case X86::VMOVAPDZrmk:        Opc = X86::VBLENDMPDZrmk;    break;
1226     case X86::VMOVAPSZ128rmk:     Opc = X86::VBLENDMPSZ128rmk; break;
1227     case X86::VMOVAPSZ256rmk:     Opc = X86::VBLENDMPSZ256rmk; break;
1228     case X86::VMOVAPSZrmk:        Opc = X86::VBLENDMPSZrmk;    break;
1229     case X86::VBROADCASTSDZ256mk: Opc = X86::VBLENDMPDZ256rmbk; break;
1230     case X86::VBROADCASTSDZmk:    Opc = X86::VBLENDMPDZrmbk;    break;
1231     case X86::VBROADCASTSSZ128mk: Opc = X86::VBLENDMPSZ128rmbk; break;
1232     case X86::VBROADCASTSSZ256mk: Opc = X86::VBLENDMPSZ256rmbk; break;
1233     case X86::VBROADCASTSSZmk:    Opc = X86::VBLENDMPSZrmbk;    break;
1234     case X86::VPBROADCASTDZ128mk: Opc = X86::VPBLENDMDZ128rmbk; break;
1235     case X86::VPBROADCASTDZ256mk: Opc = X86::VPBLENDMDZ256rmbk; break;
1236     case X86::VPBROADCASTDZmk:    Opc = X86::VPBLENDMDZrmbk;    break;
1237     case X86::VPBROADCASTQZ128mk: Opc = X86::VPBLENDMQZ128rmbk; break;
1238     case X86::VPBROADCASTQZ256mk: Opc = X86::VPBLENDMQZ256rmbk; break;
1239     case X86::VPBROADCASTQZmk:    Opc = X86::VPBLENDMQZrmbk;    break;
1240     }
1241 
1242     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1243               .add(Dest)
1244               .add(MI.getOperand(2))
1245               .add(Src)
1246               .add(MI.getOperand(3))
1247               .add(MI.getOperand(4))
1248               .add(MI.getOperand(5))
1249               .add(MI.getOperand(6))
1250               .add(MI.getOperand(7));
1251     break;
1252   }
1253 
1254   case X86::VMOVDQU8Z128rrk:
1255   case X86::VMOVDQU8Z256rrk:
1256   case X86::VMOVDQU8Zrrk:
1257   case X86::VMOVDQU16Z128rrk:
1258   case X86::VMOVDQU16Z256rrk:
1259   case X86::VMOVDQU16Zrrk:
1260   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1261   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1262   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
1263   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1264   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1265   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
1266   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
1267   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
1268   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
1269   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
1270   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
1271   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
1272     unsigned Opc;
1273     switch (MIOpc) {
1274     default: llvm_unreachable("Unreachable!");
1275     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
1276     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
1277     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
1278     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1279     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1280     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
1281     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1282     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1283     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1284     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1285     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1286     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1287     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1288     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1289     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1290     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1291     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1292     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1293     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1294     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1295     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1296     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1297     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1298     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1299     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1300     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1301     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1302     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1303     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1304     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1305     }
1306 
1307     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1308               .add(Dest)
1309               .add(MI.getOperand(2))
1310               .add(Src)
1311               .add(MI.getOperand(3));
1312     break;
1313   }
1314   }
1315 
1316   if (!NewMI) return nullptr;
1317 
1318   if (LV) {  // Update live variables
1319     if (Src.isKill())
1320       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1321     if (Dest.isDead())
1322       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1323   }
1324 
1325   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1326   return NewMI;
1327 }
1328 
1329 /// This determines which of three possible cases of a three source commute
1330 /// the source indexes correspond to taking into account any mask operands.
1331 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1332 /// possible.
1333 /// Case 0 - Possible to commute the first and second operands.
1334 /// Case 1 - Possible to commute the first and third operands.
1335 /// Case 2 - Possible to commute the second and third operands.
1336 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1337                                        unsigned SrcOpIdx2) {
1338   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1339   if (SrcOpIdx1 > SrcOpIdx2)
1340     std::swap(SrcOpIdx1, SrcOpIdx2);
1341 
1342   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1343   if (X86II::isKMasked(TSFlags)) {
1344     Op2++;
1345     Op3++;
1346   }
1347 
1348   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1349     return 0;
1350   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1351     return 1;
1352   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1353     return 2;
1354   llvm_unreachable("Unknown three src commute case.");
1355 }
1356 
1357 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1358     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1359     const X86InstrFMA3Group &FMA3Group) const {
1360 
1361   unsigned Opc = MI.getOpcode();
1362 
1363   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1364   // analysis. The commute optimization is legal only if all users of FMA*_Int
1365   // use only the lowest element of the FMA*_Int instruction. Such analysis are
1366   // not implemented yet. So, just return 0 in that case.
1367   // When such analysis are available this place will be the right place for
1368   // calling it.
1369   assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1370          "Intrinsic instructions can't commute operand 1");
1371 
1372   // Determine which case this commute is or if it can't be done.
1373   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1374                                          SrcOpIdx2);
1375   assert(Case < 3 && "Unexpected case number!");
1376 
1377   // Define the FMA forms mapping array that helps to map input FMA form
1378   // to output FMA form to preserve the operation semantics after
1379   // commuting the operands.
1380   const unsigned Form132Index = 0;
1381   const unsigned Form213Index = 1;
1382   const unsigned Form231Index = 2;
1383   static const unsigned FormMapping[][3] = {
1384     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1385     // FMA132 A, C, b; ==> FMA231 C, A, b;
1386     // FMA213 B, A, c; ==> FMA213 A, B, c;
1387     // FMA231 C, A, b; ==> FMA132 A, C, b;
1388     { Form231Index, Form213Index, Form132Index },
1389     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1390     // FMA132 A, c, B; ==> FMA132 B, c, A;
1391     // FMA213 B, a, C; ==> FMA231 C, a, B;
1392     // FMA231 C, a, B; ==> FMA213 B, a, C;
1393     { Form132Index, Form231Index, Form213Index },
1394     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1395     // FMA132 a, C, B; ==> FMA213 a, B, C;
1396     // FMA213 b, A, C; ==> FMA132 b, C, A;
1397     // FMA231 c, A, B; ==> FMA231 c, B, A;
1398     { Form213Index, Form132Index, Form231Index }
1399   };
1400 
1401   unsigned FMAForms[3];
1402   FMAForms[0] = FMA3Group.get132Opcode();
1403   FMAForms[1] = FMA3Group.get213Opcode();
1404   FMAForms[2] = FMA3Group.get231Opcode();
1405   unsigned FormIndex;
1406   for (FormIndex = 0; FormIndex < 3; FormIndex++)
1407     if (Opc == FMAForms[FormIndex])
1408       break;
1409 
1410   // Everything is ready, just adjust the FMA opcode and return it.
1411   FormIndex = FormMapping[Case][FormIndex];
1412   return FMAForms[FormIndex];
1413 }
1414 
1415 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1416                              unsigned SrcOpIdx2) {
1417   // Determine which case this commute is or if it can't be done.
1418   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1419                                          SrcOpIdx2);
1420   assert(Case < 3 && "Unexpected case value!");
1421 
1422   // For each case we need to swap two pairs of bits in the final immediate.
1423   static const uint8_t SwapMasks[3][4] = {
1424     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1425     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1426     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1427   };
1428 
1429   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1430   // Clear out the bits we are swapping.
1431   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1432                            SwapMasks[Case][2] | SwapMasks[Case][3]);
1433   // If the immediate had a bit of the pair set, then set the opposite bit.
1434   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1435   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1436   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1437   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1438   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1439 }
1440 
1441 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1442 // commuted.
1443 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1444 #define VPERM_CASES(Suffix) \
1445   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
1446   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
1447   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
1448   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
1449   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
1450   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
1451   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
1452   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
1453   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
1454   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
1455   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
1456   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
1457 
1458 #define VPERM_CASES_BROADCAST(Suffix) \
1459   VPERM_CASES(Suffix) \
1460   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
1461   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
1462   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
1463   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1464   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1465   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
1466 
1467   switch (Opcode) {
1468   default: return false;
1469   VPERM_CASES(B)
1470   VPERM_CASES_BROADCAST(D)
1471   VPERM_CASES_BROADCAST(PD)
1472   VPERM_CASES_BROADCAST(PS)
1473   VPERM_CASES_BROADCAST(Q)
1474   VPERM_CASES(W)
1475     return true;
1476   }
1477 #undef VPERM_CASES_BROADCAST
1478 #undef VPERM_CASES
1479 }
1480 
1481 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1482 // from the I opcode to the T opcode and vice versa.
1483 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1484 #define VPERM_CASES(Orig, New) \
1485   case X86::Orig##128rr:    return X86::New##128rr;   \
1486   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
1487   case X86::Orig##128rm:    return X86::New##128rm;   \
1488   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
1489   case X86::Orig##256rr:    return X86::New##256rr;   \
1490   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
1491   case X86::Orig##256rm:    return X86::New##256rm;   \
1492   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
1493   case X86::Orig##rr:       return X86::New##rr;      \
1494   case X86::Orig##rrkz:     return X86::New##rrkz;    \
1495   case X86::Orig##rm:       return X86::New##rm;      \
1496   case X86::Orig##rmkz:     return X86::New##rmkz;
1497 
1498 #define VPERM_CASES_BROADCAST(Orig, New) \
1499   VPERM_CASES(Orig, New) \
1500   case X86::Orig##128rmb:   return X86::New##128rmb;   \
1501   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1502   case X86::Orig##256rmb:   return X86::New##256rmb;   \
1503   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1504   case X86::Orig##rmb:      return X86::New##rmb;      \
1505   case X86::Orig##rmbkz:    return X86::New##rmbkz;
1506 
1507   switch (Opcode) {
1508   VPERM_CASES(VPERMI2B, VPERMT2B)
1509   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
1510   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1511   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1512   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
1513   VPERM_CASES(VPERMI2W, VPERMT2W)
1514   VPERM_CASES(VPERMT2B, VPERMI2B)
1515   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
1516   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1517   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1518   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
1519   VPERM_CASES(VPERMT2W, VPERMI2W)
1520   }
1521 
1522   llvm_unreachable("Unreachable!");
1523 #undef VPERM_CASES_BROADCAST
1524 #undef VPERM_CASES
1525 }
1526 
1527 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1528                                                    unsigned OpIdx1,
1529                                                    unsigned OpIdx2) const {
1530   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1531     if (NewMI)
1532       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1533     return MI;
1534   };
1535 
1536   switch (MI.getOpcode()) {
1537   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1538   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1539   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1540   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1541   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1542   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1543     unsigned Opc;
1544     unsigned Size;
1545     switch (MI.getOpcode()) {
1546     default: llvm_unreachable("Unreachable!");
1547     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1548     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1549     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1550     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1551     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1552     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1553     }
1554     unsigned Amt = MI.getOperand(3).getImm();
1555     auto &WorkingMI = cloneIfNew(MI);
1556     WorkingMI.setDesc(get(Opc));
1557     WorkingMI.getOperand(3).setImm(Size - Amt);
1558     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1559                                                    OpIdx1, OpIdx2);
1560   }
1561   case X86::PFSUBrr:
1562   case X86::PFSUBRrr: {
1563     // PFSUB  x, y: x = x - y
1564     // PFSUBR x, y: x = y - x
1565     unsigned Opc =
1566         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1567     auto &WorkingMI = cloneIfNew(MI);
1568     WorkingMI.setDesc(get(Opc));
1569     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1570                                                    OpIdx1, OpIdx2);
1571   }
1572   case X86::BLENDPDrri:
1573   case X86::BLENDPSrri:
1574   case X86::VBLENDPDrri:
1575   case X86::VBLENDPSrri:
1576     // If we're optimizing for size, try to use MOVSD/MOVSS.
1577     if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
1578       unsigned Mask, Opc;
1579       switch (MI.getOpcode()) {
1580       default: llvm_unreachable("Unreachable!");
1581       case X86::BLENDPDrri:  Opc = X86::MOVSDrr;  Mask = 0x03; break;
1582       case X86::BLENDPSrri:  Opc = X86::MOVSSrr;  Mask = 0x0F; break;
1583       case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1584       case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1585       }
1586       if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1587         auto &WorkingMI = cloneIfNew(MI);
1588         WorkingMI.setDesc(get(Opc));
1589         WorkingMI.RemoveOperand(3);
1590         return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1591                                                        /*NewMI=*/false,
1592                                                        OpIdx1, OpIdx2);
1593       }
1594     }
1595     LLVM_FALLTHROUGH;
1596   case X86::PBLENDWrri:
1597   case X86::VBLENDPDYrri:
1598   case X86::VBLENDPSYrri:
1599   case X86::VPBLENDDrri:
1600   case X86::VPBLENDWrri:
1601   case X86::VPBLENDDYrri:
1602   case X86::VPBLENDWYrri:{
1603     int8_t Mask;
1604     switch (MI.getOpcode()) {
1605     default: llvm_unreachable("Unreachable!");
1606     case X86::BLENDPDrri:    Mask = (int8_t)0x03; break;
1607     case X86::BLENDPSrri:    Mask = (int8_t)0x0F; break;
1608     case X86::PBLENDWrri:    Mask = (int8_t)0xFF; break;
1609     case X86::VBLENDPDrri:   Mask = (int8_t)0x03; break;
1610     case X86::VBLENDPSrri:   Mask = (int8_t)0x0F; break;
1611     case X86::VBLENDPDYrri:  Mask = (int8_t)0x0F; break;
1612     case X86::VBLENDPSYrri:  Mask = (int8_t)0xFF; break;
1613     case X86::VPBLENDDrri:   Mask = (int8_t)0x0F; break;
1614     case X86::VPBLENDWrri:   Mask = (int8_t)0xFF; break;
1615     case X86::VPBLENDDYrri:  Mask = (int8_t)0xFF; break;
1616     case X86::VPBLENDWYrri:  Mask = (int8_t)0xFF; break;
1617     }
1618     // Only the least significant bits of Imm are used.
1619     // Using int8_t to ensure it will be sign extended to the int64_t that
1620     // setImm takes in order to match isel behavior.
1621     int8_t Imm = MI.getOperand(3).getImm() & Mask;
1622     auto &WorkingMI = cloneIfNew(MI);
1623     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1624     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1625                                                    OpIdx1, OpIdx2);
1626   }
1627   case X86::INSERTPSrr:
1628   case X86::VINSERTPSrr:
1629   case X86::VINSERTPSZrr: {
1630     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
1631     unsigned ZMask = Imm & 15;
1632     unsigned DstIdx = (Imm >> 4) & 3;
1633     unsigned SrcIdx = (Imm >> 6) & 3;
1634 
1635     // We can commute insertps if we zero 2 of the elements, the insertion is
1636     // "inline" and we don't override the insertion with a zero.
1637     if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
1638         countPopulation(ZMask) == 2) {
1639       unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
1640       assert(AltIdx < 4 && "Illegal insertion index");
1641       unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
1642       auto &WorkingMI = cloneIfNew(MI);
1643       WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
1644       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1645                                                      OpIdx1, OpIdx2);
1646     }
1647     return nullptr;
1648   }
1649   case X86::MOVSDrr:
1650   case X86::MOVSSrr:
1651   case X86::VMOVSDrr:
1652   case X86::VMOVSSrr:{
1653     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1654     if (Subtarget.hasSSE41()) {
1655       unsigned Mask, Opc;
1656       switch (MI.getOpcode()) {
1657       default: llvm_unreachable("Unreachable!");
1658       case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
1659       case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
1660       case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1661       case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1662       }
1663 
1664       auto &WorkingMI = cloneIfNew(MI);
1665       WorkingMI.setDesc(get(Opc));
1666       WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1667       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1668                                                      OpIdx1, OpIdx2);
1669     }
1670 
1671     // Convert to SHUFPD.
1672     assert(MI.getOpcode() == X86::MOVSDrr &&
1673            "Can only commute MOVSDrr without SSE4.1");
1674 
1675     auto &WorkingMI = cloneIfNew(MI);
1676     WorkingMI.setDesc(get(X86::SHUFPDrri));
1677     WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
1678     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1679                                                    OpIdx1, OpIdx2);
1680   }
1681   case X86::SHUFPDrri: {
1682     // Commute to MOVSD.
1683     assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
1684     auto &WorkingMI = cloneIfNew(MI);
1685     WorkingMI.setDesc(get(X86::MOVSDrr));
1686     WorkingMI.RemoveOperand(3);
1687     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1688                                                    OpIdx1, OpIdx2);
1689   }
1690   case X86::PCLMULQDQrr:
1691   case X86::VPCLMULQDQrr:
1692   case X86::VPCLMULQDQYrr:
1693   case X86::VPCLMULQDQZrr:
1694   case X86::VPCLMULQDQZ128rr:
1695   case X86::VPCLMULQDQZ256rr: {
1696     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
1697     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
1698     unsigned Imm = MI.getOperand(3).getImm();
1699     unsigned Src1Hi = Imm & 0x01;
1700     unsigned Src2Hi = Imm & 0x10;
1701     auto &WorkingMI = cloneIfNew(MI);
1702     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
1703     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1704                                                    OpIdx1, OpIdx2);
1705   }
1706   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
1707   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
1708   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
1709   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
1710   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
1711   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
1712   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
1713   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
1714   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
1715   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
1716   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
1717   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
1718   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
1719   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
1720   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
1721   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
1722   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
1723   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
1724   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
1725   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
1726   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
1727   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
1728   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
1729   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
1730     // Flip comparison mode immediate (if necessary).
1731     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
1732     Imm = X86::getSwappedVPCMPImm(Imm);
1733     auto &WorkingMI = cloneIfNew(MI);
1734     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1735     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1736                                                    OpIdx1, OpIdx2);
1737   }
1738   case X86::VPCOMBri: case X86::VPCOMUBri:
1739   case X86::VPCOMDri: case X86::VPCOMUDri:
1740   case X86::VPCOMQri: case X86::VPCOMUQri:
1741   case X86::VPCOMWri: case X86::VPCOMUWri: {
1742     // Flip comparison mode immediate (if necessary).
1743     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1744     Imm = X86::getSwappedVPCOMImm(Imm);
1745     auto &WorkingMI = cloneIfNew(MI);
1746     WorkingMI.getOperand(3).setImm(Imm);
1747     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1748                                                    OpIdx1, OpIdx2);
1749   }
1750   case X86::VCMPSDZrr:
1751   case X86::VCMPSSZrr:
1752   case X86::VCMPPDZrri:
1753   case X86::VCMPPSZrri:
1754   case X86::VCMPPDZ128rri:
1755   case X86::VCMPPSZ128rri:
1756   case X86::VCMPPDZ256rri:
1757   case X86::VCMPPSZ256rri:
1758   case X86::VCMPPDZrrik:
1759   case X86::VCMPPSZrrik:
1760   case X86::VCMPPDZ128rrik:
1761   case X86::VCMPPSZ128rrik:
1762   case X86::VCMPPDZ256rrik:
1763   case X86::VCMPPSZ256rrik: {
1764     unsigned Imm =
1765                 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f;
1766     Imm = X86::getSwappedVCMPImm(Imm);
1767     auto &WorkingMI = cloneIfNew(MI);
1768     WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm);
1769     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1770                                                    OpIdx1, OpIdx2);
1771   }
1772   case X86::VPERM2F128rr:
1773   case X86::VPERM2I128rr: {
1774     // Flip permute source immediate.
1775     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
1776     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
1777     int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
1778     auto &WorkingMI = cloneIfNew(MI);
1779     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
1780     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1781                                                    OpIdx1, OpIdx2);
1782   }
1783   case X86::MOVHLPSrr:
1784   case X86::UNPCKHPDrr:
1785   case X86::VMOVHLPSrr:
1786   case X86::VUNPCKHPDrr:
1787   case X86::VMOVHLPSZrr:
1788   case X86::VUNPCKHPDZ128rr: {
1789     assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
1790 
1791     unsigned Opc = MI.getOpcode();
1792     switch (Opc) {
1793     default: llvm_unreachable("Unreachable!");
1794     case X86::MOVHLPSrr:       Opc = X86::UNPCKHPDrr;      break;
1795     case X86::UNPCKHPDrr:      Opc = X86::MOVHLPSrr;       break;
1796     case X86::VMOVHLPSrr:      Opc = X86::VUNPCKHPDrr;     break;
1797     case X86::VUNPCKHPDrr:     Opc = X86::VMOVHLPSrr;      break;
1798     case X86::VMOVHLPSZrr:     Opc = X86::VUNPCKHPDZ128rr; break;
1799     case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr;     break;
1800     }
1801     auto &WorkingMI = cloneIfNew(MI);
1802     WorkingMI.setDesc(get(Opc));
1803     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1804                                                    OpIdx1, OpIdx2);
1805   }
1806   case X86::CMOV16rr:  case X86::CMOV32rr:  case X86::CMOV64rr: {
1807     auto &WorkingMI = cloneIfNew(MI);
1808     unsigned OpNo = MI.getDesc().getNumOperands() - 1;
1809     X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
1810     WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
1811     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1812                                                    OpIdx1, OpIdx2);
1813   }
1814   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
1815   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
1816   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
1817   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
1818   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
1819   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
1820   case X86::VPTERNLOGDZrrik:
1821   case X86::VPTERNLOGDZ128rrik:
1822   case X86::VPTERNLOGDZ256rrik:
1823   case X86::VPTERNLOGQZrrik:
1824   case X86::VPTERNLOGQZ128rrik:
1825   case X86::VPTERNLOGQZ256rrik:
1826   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
1827   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1828   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1829   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
1830   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1831   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1832   case X86::VPTERNLOGDZ128rmbi:
1833   case X86::VPTERNLOGDZ256rmbi:
1834   case X86::VPTERNLOGDZrmbi:
1835   case X86::VPTERNLOGQZ128rmbi:
1836   case X86::VPTERNLOGQZ256rmbi:
1837   case X86::VPTERNLOGQZrmbi:
1838   case X86::VPTERNLOGDZ128rmbikz:
1839   case X86::VPTERNLOGDZ256rmbikz:
1840   case X86::VPTERNLOGDZrmbikz:
1841   case X86::VPTERNLOGQZ128rmbikz:
1842   case X86::VPTERNLOGQZ256rmbikz:
1843   case X86::VPTERNLOGQZrmbikz: {
1844     auto &WorkingMI = cloneIfNew(MI);
1845     commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
1846     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1847                                                    OpIdx1, OpIdx2);
1848   }
1849   default: {
1850     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
1851       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
1852       auto &WorkingMI = cloneIfNew(MI);
1853       WorkingMI.setDesc(get(Opc));
1854       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1855                                                      OpIdx1, OpIdx2);
1856     }
1857 
1858     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
1859                                                       MI.getDesc().TSFlags);
1860     if (FMA3Group) {
1861       unsigned Opc =
1862         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
1863       auto &WorkingMI = cloneIfNew(MI);
1864       WorkingMI.setDesc(get(Opc));
1865       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1866                                                      OpIdx1, OpIdx2);
1867     }
1868 
1869     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1870   }
1871   }
1872 }
1873 
1874 bool
1875 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
1876                                             unsigned &SrcOpIdx1,
1877                                             unsigned &SrcOpIdx2,
1878                                             bool IsIntrinsic) const {
1879   uint64_t TSFlags = MI.getDesc().TSFlags;
1880 
1881   unsigned FirstCommutableVecOp = 1;
1882   unsigned LastCommutableVecOp = 3;
1883   unsigned KMaskOp = -1U;
1884   if (X86II::isKMasked(TSFlags)) {
1885     // For k-zero-masked operations it is Ok to commute the first vector
1886     // operand.
1887     // For regular k-masked operations a conservative choice is done as the
1888     // elements of the first vector operand, for which the corresponding bit
1889     // in the k-mask operand is set to 0, are copied to the result of the
1890     // instruction.
1891     // TODO/FIXME: The commute still may be legal if it is known that the
1892     // k-mask operand is set to either all ones or all zeroes.
1893     // It is also Ok to commute the 1st operand if all users of MI use only
1894     // the elements enabled by the k-mask operand. For example,
1895     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
1896     //                                                     : v1[i];
1897     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
1898     //                                  // Ok, to commute v1 in FMADD213PSZrk.
1899 
1900     // The k-mask operand has index = 2 for masked and zero-masked operations.
1901     KMaskOp = 2;
1902 
1903     // The operand with index = 1 is used as a source for those elements for
1904     // which the corresponding bit in the k-mask is set to 0.
1905     if (X86II::isKMergeMasked(TSFlags))
1906       FirstCommutableVecOp = 3;
1907 
1908     LastCommutableVecOp++;
1909   } else if (IsIntrinsic) {
1910     // Commuting the first operand of an intrinsic instruction isn't possible
1911     // unless we can prove that only the lowest element of the result is used.
1912     FirstCommutableVecOp = 2;
1913   }
1914 
1915   if (isMem(MI, LastCommutableVecOp))
1916     LastCommutableVecOp--;
1917 
1918   // Only the first RegOpsNum operands are commutable.
1919   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
1920   // that the operand is not specified/fixed.
1921   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1922       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
1923        SrcOpIdx1 == KMaskOp))
1924     return false;
1925   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
1926       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
1927        SrcOpIdx2 == KMaskOp))
1928     return false;
1929 
1930   // Look for two different register operands assumed to be commutable
1931   // regardless of the FMA opcode. The FMA opcode is adjusted later.
1932   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1933       SrcOpIdx2 == CommuteAnyOperandIndex) {
1934     unsigned CommutableOpIdx2 = SrcOpIdx2;
1935 
1936     // At least one of operands to be commuted is not specified and
1937     // this method is free to choose appropriate commutable operands.
1938     if (SrcOpIdx1 == SrcOpIdx2)
1939       // Both of operands are not fixed. By default set one of commutable
1940       // operands to the last register operand of the instruction.
1941       CommutableOpIdx2 = LastCommutableVecOp;
1942     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
1943       // Only one of operands is not fixed.
1944       CommutableOpIdx2 = SrcOpIdx1;
1945 
1946     // CommutableOpIdx2 is well defined now. Let's choose another commutable
1947     // operand and assign its index to CommutableOpIdx1.
1948     Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
1949 
1950     unsigned CommutableOpIdx1;
1951     for (CommutableOpIdx1 = LastCommutableVecOp;
1952          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
1953       // Just ignore and skip the k-mask operand.
1954       if (CommutableOpIdx1 == KMaskOp)
1955         continue;
1956 
1957       // The commuted operands must have different registers.
1958       // Otherwise, the commute transformation does not change anything and
1959       // is useless then.
1960       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
1961         break;
1962     }
1963 
1964     // No appropriate commutable operands were found.
1965     if (CommutableOpIdx1 < FirstCommutableVecOp)
1966       return false;
1967 
1968     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
1969     // to return those values.
1970     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1971                               CommutableOpIdx1, CommutableOpIdx2))
1972       return false;
1973   }
1974 
1975   return true;
1976 }
1977 
1978 bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
1979                                          unsigned &SrcOpIdx1,
1980                                          unsigned &SrcOpIdx2) const {
1981   const MCInstrDesc &Desc = MI.getDesc();
1982   if (!Desc.isCommutable())
1983     return false;
1984 
1985   switch (MI.getOpcode()) {
1986   case X86::CMPSDrr:
1987   case X86::CMPSSrr:
1988   case X86::CMPPDrri:
1989   case X86::CMPPSrri:
1990   case X86::VCMPSDrr:
1991   case X86::VCMPSSrr:
1992   case X86::VCMPPDrri:
1993   case X86::VCMPPSrri:
1994   case X86::VCMPPDYrri:
1995   case X86::VCMPPSYrri:
1996   case X86::VCMPSDZrr:
1997   case X86::VCMPSSZrr:
1998   case X86::VCMPPDZrri:
1999   case X86::VCMPPSZrri:
2000   case X86::VCMPPDZ128rri:
2001   case X86::VCMPPSZ128rri:
2002   case X86::VCMPPDZ256rri:
2003   case X86::VCMPPSZ256rri:
2004   case X86::VCMPPDZrrik:
2005   case X86::VCMPPSZrrik:
2006   case X86::VCMPPDZ128rrik:
2007   case X86::VCMPPSZ128rrik:
2008   case X86::VCMPPDZ256rrik:
2009   case X86::VCMPPSZ256rrik: {
2010     unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2011 
2012     // Float comparison can be safely commuted for
2013     // Ordered/Unordered/Equal/NotEqual tests
2014     unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2015     switch (Imm) {
2016     default:
2017       // EVEX versions can be commuted.
2018       if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2019         break;
2020       return false;
2021     case 0x00: // EQUAL
2022     case 0x03: // UNORDERED
2023     case 0x04: // NOT EQUAL
2024     case 0x07: // ORDERED
2025       break;
2026     }
2027 
2028     // The indices of the commutable operands are 1 and 2 (or 2 and 3
2029     // when masked).
2030     // Assign them to the returned operand indices here.
2031     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2032                                 2 + OpOffset);
2033   }
2034   case X86::MOVSSrr:
2035     // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2036     // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2037     // AVX implies sse4.1.
2038     if (Subtarget.hasSSE41())
2039       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2040     return false;
2041   case X86::SHUFPDrri:
2042     // We can commute this to MOVSD.
2043     if (MI.getOperand(3).getImm() == 0x02)
2044       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2045     return false;
2046   case X86::MOVHLPSrr:
2047   case X86::UNPCKHPDrr:
2048   case X86::VMOVHLPSrr:
2049   case X86::VUNPCKHPDrr:
2050   case X86::VMOVHLPSZrr:
2051   case X86::VUNPCKHPDZ128rr:
2052     if (Subtarget.hasSSE2())
2053       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2054     return false;
2055   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2056   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2057   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2058   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2059   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2060   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2061   case X86::VPTERNLOGDZrrik:
2062   case X86::VPTERNLOGDZ128rrik:
2063   case X86::VPTERNLOGDZ256rrik:
2064   case X86::VPTERNLOGQZrrik:
2065   case X86::VPTERNLOGQZ128rrik:
2066   case X86::VPTERNLOGQZ256rrik:
2067   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2068   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2069   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2070   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2071   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2072   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2073   case X86::VPTERNLOGDZ128rmbi:
2074   case X86::VPTERNLOGDZ256rmbi:
2075   case X86::VPTERNLOGDZrmbi:
2076   case X86::VPTERNLOGQZ128rmbi:
2077   case X86::VPTERNLOGQZ256rmbi:
2078   case X86::VPTERNLOGQZrmbi:
2079   case X86::VPTERNLOGDZ128rmbikz:
2080   case X86::VPTERNLOGDZ256rmbikz:
2081   case X86::VPTERNLOGDZrmbikz:
2082   case X86::VPTERNLOGQZ128rmbikz:
2083   case X86::VPTERNLOGQZ256rmbikz:
2084   case X86::VPTERNLOGQZrmbikz:
2085     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2086   case X86::VPDPWSSDZ128r:
2087   case X86::VPDPWSSDZ128rk:
2088   case X86::VPDPWSSDZ128rkz:
2089   case X86::VPDPWSSDZ256r:
2090   case X86::VPDPWSSDZ256rk:
2091   case X86::VPDPWSSDZ256rkz:
2092   case X86::VPDPWSSDZr:
2093   case X86::VPDPWSSDZrk:
2094   case X86::VPDPWSSDZrkz:
2095   case X86::VPDPWSSDSZ128r:
2096   case X86::VPDPWSSDSZ128rk:
2097   case X86::VPDPWSSDSZ128rkz:
2098   case X86::VPDPWSSDSZ256r:
2099   case X86::VPDPWSSDSZ256rk:
2100   case X86::VPDPWSSDSZ256rkz:
2101   case X86::VPDPWSSDSZr:
2102   case X86::VPDPWSSDSZrk:
2103   case X86::VPDPWSSDSZrkz:
2104   case X86::VPMADD52HUQZ128r:
2105   case X86::VPMADD52HUQZ128rk:
2106   case X86::VPMADD52HUQZ128rkz:
2107   case X86::VPMADD52HUQZ256r:
2108   case X86::VPMADD52HUQZ256rk:
2109   case X86::VPMADD52HUQZ256rkz:
2110   case X86::VPMADD52HUQZr:
2111   case X86::VPMADD52HUQZrk:
2112   case X86::VPMADD52HUQZrkz:
2113   case X86::VPMADD52LUQZ128r:
2114   case X86::VPMADD52LUQZ128rk:
2115   case X86::VPMADD52LUQZ128rkz:
2116   case X86::VPMADD52LUQZ256r:
2117   case X86::VPMADD52LUQZ256rk:
2118   case X86::VPMADD52LUQZ256rkz:
2119   case X86::VPMADD52LUQZr:
2120   case X86::VPMADD52LUQZrk:
2121   case X86::VPMADD52LUQZrkz: {
2122     unsigned CommutableOpIdx1 = 2;
2123     unsigned CommutableOpIdx2 = 3;
2124     if (X86II::isKMasked(Desc.TSFlags)) {
2125       // Skip the mask register.
2126       ++CommutableOpIdx1;
2127       ++CommutableOpIdx2;
2128     }
2129     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2130                               CommutableOpIdx1, CommutableOpIdx2))
2131       return false;
2132     if (!MI.getOperand(SrcOpIdx1).isReg() ||
2133         !MI.getOperand(SrcOpIdx2).isReg())
2134       // No idea.
2135       return false;
2136     return true;
2137   }
2138 
2139   default:
2140     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2141                                                       MI.getDesc().TSFlags);
2142     if (FMA3Group)
2143       return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2144                                            FMA3Group->isIntrinsic());
2145 
2146     // Handled masked instructions since we need to skip over the mask input
2147     // and the preserved input.
2148     if (X86II::isKMasked(Desc.TSFlags)) {
2149       // First assume that the first input is the mask operand and skip past it.
2150       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2151       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2152       // Check if the first input is tied. If there isn't one then we only
2153       // need to skip the mask operand which we did above.
2154       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2155                                              MCOI::TIED_TO) != -1)) {
2156         // If this is zero masking instruction with a tied operand, we need to
2157         // move the first index back to the first input since this must
2158         // be a 3 input instruction and we want the first two non-mask inputs.
2159         // Otherwise this is a 2 input instruction with a preserved input and
2160         // mask, so we need to move the indices to skip one more input.
2161         if (X86II::isKMergeMasked(Desc.TSFlags)) {
2162           ++CommutableOpIdx1;
2163           ++CommutableOpIdx2;
2164         } else {
2165           --CommutableOpIdx1;
2166         }
2167       }
2168 
2169       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2170                                 CommutableOpIdx1, CommutableOpIdx2))
2171         return false;
2172 
2173       if (!MI.getOperand(SrcOpIdx1).isReg() ||
2174           !MI.getOperand(SrcOpIdx2).isReg())
2175         // No idea.
2176         return false;
2177       return true;
2178     }
2179 
2180     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2181   }
2182   return false;
2183 }
2184 
2185 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2186   switch (MI.getOpcode()) {
2187   default: return X86::COND_INVALID;
2188   case X86::JCC_1:
2189     return static_cast<X86::CondCode>(
2190         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2191   }
2192 }
2193 
2194 /// Return condition code of a SETCC opcode.
2195 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2196   switch (MI.getOpcode()) {
2197   default: return X86::COND_INVALID;
2198   case X86::SETCCr: case X86::SETCCm:
2199     return static_cast<X86::CondCode>(
2200         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2201   }
2202 }
2203 
2204 /// Return condition code of a CMov opcode.
2205 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2206   switch (MI.getOpcode()) {
2207   default: return X86::COND_INVALID;
2208   case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2209   case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2210     return static_cast<X86::CondCode>(
2211         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2212   }
2213 }
2214 
2215 /// Return the inverse of the specified condition,
2216 /// e.g. turning COND_E to COND_NE.
2217 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2218   switch (CC) {
2219   default: llvm_unreachable("Illegal condition code!");
2220   case X86::COND_E:  return X86::COND_NE;
2221   case X86::COND_NE: return X86::COND_E;
2222   case X86::COND_L:  return X86::COND_GE;
2223   case X86::COND_LE: return X86::COND_G;
2224   case X86::COND_G:  return X86::COND_LE;
2225   case X86::COND_GE: return X86::COND_L;
2226   case X86::COND_B:  return X86::COND_AE;
2227   case X86::COND_BE: return X86::COND_A;
2228   case X86::COND_A:  return X86::COND_BE;
2229   case X86::COND_AE: return X86::COND_B;
2230   case X86::COND_S:  return X86::COND_NS;
2231   case X86::COND_NS: return X86::COND_S;
2232   case X86::COND_P:  return X86::COND_NP;
2233   case X86::COND_NP: return X86::COND_P;
2234   case X86::COND_O:  return X86::COND_NO;
2235   case X86::COND_NO: return X86::COND_O;
2236   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
2237   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2238   }
2239 }
2240 
2241 /// Assuming the flags are set by MI(a,b), return the condition code if we
2242 /// modify the instructions such that flags are set by MI(b,a).
2243 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2244   switch (CC) {
2245   default: return X86::COND_INVALID;
2246   case X86::COND_E:  return X86::COND_E;
2247   case X86::COND_NE: return X86::COND_NE;
2248   case X86::COND_L:  return X86::COND_G;
2249   case X86::COND_LE: return X86::COND_GE;
2250   case X86::COND_G:  return X86::COND_L;
2251   case X86::COND_GE: return X86::COND_LE;
2252   case X86::COND_B:  return X86::COND_A;
2253   case X86::COND_BE: return X86::COND_AE;
2254   case X86::COND_A:  return X86::COND_B;
2255   case X86::COND_AE: return X86::COND_BE;
2256   }
2257 }
2258 
2259 std::pair<X86::CondCode, bool>
2260 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2261   X86::CondCode CC = X86::COND_INVALID;
2262   bool NeedSwap = false;
2263   switch (Predicate) {
2264   default: break;
2265   // Floating-point Predicates
2266   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
2267   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
2268   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
2269   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
2270   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
2271   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
2272   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
2273   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
2274   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
2275   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
2276   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
2277   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
2278   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
2279   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2280 
2281   // Integer Predicates
2282   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
2283   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
2284   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
2285   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
2286   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
2287   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
2288   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
2289   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
2290   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
2291   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
2292   }
2293 
2294   return std::make_pair(CC, NeedSwap);
2295 }
2296 
2297 /// Return a setcc opcode based on whether it has memory operand.
2298 unsigned X86::getSETOpc(bool HasMemoryOperand) {
2299   return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2300 }
2301 
2302 /// Return a cmov opcode for the given register size in bytes, and operand type.
2303 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2304   switch(RegBytes) {
2305   default: llvm_unreachable("Illegal register size!");
2306   case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2307   case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2308   case 8: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV64rr;
2309   }
2310 }
2311 
2312 /// Get the VPCMP immediate for the given condition.
2313 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2314   switch (CC) {
2315   default: llvm_unreachable("Unexpected SETCC condition");
2316   case ISD::SETNE:  return 4;
2317   case ISD::SETEQ:  return 0;
2318   case ISD::SETULT:
2319   case ISD::SETLT: return 1;
2320   case ISD::SETUGT:
2321   case ISD::SETGT: return 6;
2322   case ISD::SETUGE:
2323   case ISD::SETGE: return 5;
2324   case ISD::SETULE:
2325   case ISD::SETLE: return 2;
2326   }
2327 }
2328 
2329 /// Get the VPCMP immediate if the operands are swapped.
2330 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2331   switch (Imm) {
2332   default: llvm_unreachable("Unreachable!");
2333   case 0x01: Imm = 0x06; break; // LT  -> NLE
2334   case 0x02: Imm = 0x05; break; // LE  -> NLT
2335   case 0x05: Imm = 0x02; break; // NLT -> LE
2336   case 0x06: Imm = 0x01; break; // NLE -> LT
2337   case 0x00: // EQ
2338   case 0x03: // FALSE
2339   case 0x04: // NE
2340   case 0x07: // TRUE
2341     break;
2342   }
2343 
2344   return Imm;
2345 }
2346 
2347 /// Get the VPCOM immediate if the operands are swapped.
2348 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2349   switch (Imm) {
2350   default: llvm_unreachable("Unreachable!");
2351   case 0x00: Imm = 0x02; break; // LT -> GT
2352   case 0x01: Imm = 0x03; break; // LE -> GE
2353   case 0x02: Imm = 0x00; break; // GT -> LT
2354   case 0x03: Imm = 0x01; break; // GE -> LE
2355   case 0x04: // EQ
2356   case 0x05: // NE
2357   case 0x06: // FALSE
2358   case 0x07: // TRUE
2359     break;
2360   }
2361 
2362   return Imm;
2363 }
2364 
2365 /// Get the VCMP immediate if the operands are swapped.
2366 unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2367   // Only need the lower 2 bits to distinquish.
2368   switch (Imm & 0x3) {
2369   default: llvm_unreachable("Unreachable!");
2370   case 0x00: case 0x03:
2371     // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2372     break;
2373   case 0x01: case 0x02:
2374     // Need to toggle bits 3:0. Bit 4 stays the same.
2375     Imm ^= 0xf;
2376     break;
2377   }
2378 
2379   return Imm;
2380 }
2381 
2382 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
2383   if (!MI.isTerminator()) return false;
2384 
2385   // Conditional branch is a special case.
2386   if (MI.isBranch() && !MI.isBarrier())
2387     return true;
2388   if (!MI.isPredicable())
2389     return true;
2390   return !isPredicated(MI);
2391 }
2392 
2393 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2394   switch (MI.getOpcode()) {
2395   case X86::TCRETURNdi:
2396   case X86::TCRETURNri:
2397   case X86::TCRETURNmi:
2398   case X86::TCRETURNdi64:
2399   case X86::TCRETURNri64:
2400   case X86::TCRETURNmi64:
2401     return true;
2402   default:
2403     return false;
2404   }
2405 }
2406 
2407 bool X86InstrInfo::canMakeTailCallConditional(
2408     SmallVectorImpl<MachineOperand> &BranchCond,
2409     const MachineInstr &TailCall) const {
2410   if (TailCall.getOpcode() != X86::TCRETURNdi &&
2411       TailCall.getOpcode() != X86::TCRETURNdi64) {
2412     // Only direct calls can be done with a conditional branch.
2413     return false;
2414   }
2415 
2416   const MachineFunction *MF = TailCall.getParent()->getParent();
2417   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2418     // Conditional tail calls confuse the Win64 unwinder.
2419     return false;
2420   }
2421 
2422   assert(BranchCond.size() == 1);
2423   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2424     // Can't make a conditional tail call with this condition.
2425     return false;
2426   }
2427 
2428   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2429   if (X86FI->getTCReturnAddrDelta() != 0 ||
2430       TailCall.getOperand(1).getImm() != 0) {
2431     // A conditional tail call cannot do any stack adjustment.
2432     return false;
2433   }
2434 
2435   return true;
2436 }
2437 
2438 void X86InstrInfo::replaceBranchWithTailCall(
2439     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2440     const MachineInstr &TailCall) const {
2441   assert(canMakeTailCallConditional(BranchCond, TailCall));
2442 
2443   MachineBasicBlock::iterator I = MBB.end();
2444   while (I != MBB.begin()) {
2445     --I;
2446     if (I->isDebugInstr())
2447       continue;
2448     if (!I->isBranch())
2449       assert(0 && "Can't find the branch to replace!");
2450 
2451     X86::CondCode CC = X86::getCondFromBranch(*I);
2452     assert(BranchCond.size() == 1);
2453     if (CC != BranchCond[0].getImm())
2454       continue;
2455 
2456     break;
2457   }
2458 
2459   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2460                                                          : X86::TCRETURNdi64cc;
2461 
2462   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2463   MIB->addOperand(TailCall.getOperand(0)); // Destination.
2464   MIB.addImm(0); // Stack offset (not used).
2465   MIB->addOperand(BranchCond[0]); // Condition.
2466   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2467 
2468   // Add implicit uses and defs of all live regs potentially clobbered by the
2469   // call. This way they still appear live across the call.
2470   LivePhysRegs LiveRegs(getRegisterInfo());
2471   LiveRegs.addLiveOuts(MBB);
2472   SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2473   LiveRegs.stepForward(*MIB, Clobbers);
2474   for (const auto &C : Clobbers) {
2475     MIB.addReg(C.first, RegState::Implicit);
2476     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2477   }
2478 
2479   I->eraseFromParent();
2480 }
2481 
2482 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2483 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2484 // fallthrough MBB cannot be identified.
2485 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2486                                             MachineBasicBlock *TBB) {
2487   // Look for non-EHPad successors other than TBB. If we find exactly one, it
2488   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2489   // and fallthrough MBB. If we find more than one, we cannot identify the
2490   // fallthrough MBB and should return nullptr.
2491   MachineBasicBlock *FallthroughBB = nullptr;
2492   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2493     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2494       continue;
2495     // Return a nullptr if we found more than one fallthrough successor.
2496     if (FallthroughBB && FallthroughBB != TBB)
2497       return nullptr;
2498     FallthroughBB = *SI;
2499   }
2500   return FallthroughBB;
2501 }
2502 
2503 bool X86InstrInfo::AnalyzeBranchImpl(
2504     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2505     SmallVectorImpl<MachineOperand> &Cond,
2506     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2507 
2508   // Start from the bottom of the block and work up, examining the
2509   // terminator instructions.
2510   MachineBasicBlock::iterator I = MBB.end();
2511   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2512   while (I != MBB.begin()) {
2513     --I;
2514     if (I->isDebugInstr())
2515       continue;
2516 
2517     // Working from the bottom, when we see a non-terminator instruction, we're
2518     // done.
2519     if (!isUnpredicatedTerminator(*I))
2520       break;
2521 
2522     // A terminator that isn't a branch can't easily be handled by this
2523     // analysis.
2524     if (!I->isBranch())
2525       return true;
2526 
2527     // Handle unconditional branches.
2528     if (I->getOpcode() == X86::JMP_1) {
2529       UnCondBrIter = I;
2530 
2531       if (!AllowModify) {
2532         TBB = I->getOperand(0).getMBB();
2533         continue;
2534       }
2535 
2536       // If the block has any instructions after a JMP, delete them.
2537       while (std::next(I) != MBB.end())
2538         std::next(I)->eraseFromParent();
2539 
2540       Cond.clear();
2541       FBB = nullptr;
2542 
2543       // Delete the JMP if it's equivalent to a fall-through.
2544       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2545         TBB = nullptr;
2546         I->eraseFromParent();
2547         I = MBB.end();
2548         UnCondBrIter = MBB.end();
2549         continue;
2550       }
2551 
2552       // TBB is used to indicate the unconditional destination.
2553       TBB = I->getOperand(0).getMBB();
2554       continue;
2555     }
2556 
2557     // Handle conditional branches.
2558     X86::CondCode BranchCode = X86::getCondFromBranch(*I);
2559     if (BranchCode == X86::COND_INVALID)
2560       return true;  // Can't handle indirect branch.
2561 
2562     // In practice we should never have an undef eflags operand, if we do
2563     // abort here as we are not prepared to preserve the flag.
2564     if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
2565       return true;
2566 
2567     // Working from the bottom, handle the first conditional branch.
2568     if (Cond.empty()) {
2569       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2570       if (AllowModify && UnCondBrIter != MBB.end() &&
2571           MBB.isLayoutSuccessor(TargetBB)) {
2572         // If we can modify the code and it ends in something like:
2573         //
2574         //     jCC L1
2575         //     jmp L2
2576         //   L1:
2577         //     ...
2578         //   L2:
2579         //
2580         // Then we can change this to:
2581         //
2582         //     jnCC L2
2583         //   L1:
2584         //     ...
2585         //   L2:
2586         //
2587         // Which is a bit more efficient.
2588         // We conditionally jump to the fall-through block.
2589         BranchCode = GetOppositeBranchCondition(BranchCode);
2590         MachineBasicBlock::iterator OldInst = I;
2591 
2592         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
2593           .addMBB(UnCondBrIter->getOperand(0).getMBB())
2594           .addImm(BranchCode);
2595         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
2596           .addMBB(TargetBB);
2597 
2598         OldInst->eraseFromParent();
2599         UnCondBrIter->eraseFromParent();
2600 
2601         // Restart the analysis.
2602         UnCondBrIter = MBB.end();
2603         I = MBB.end();
2604         continue;
2605       }
2606 
2607       FBB = TBB;
2608       TBB = I->getOperand(0).getMBB();
2609       Cond.push_back(MachineOperand::CreateImm(BranchCode));
2610       CondBranches.push_back(&*I);
2611       continue;
2612     }
2613 
2614     // Handle subsequent conditional branches. Only handle the case where all
2615     // conditional branches branch to the same destination and their condition
2616     // opcodes fit one of the special multi-branch idioms.
2617     assert(Cond.size() == 1);
2618     assert(TBB);
2619 
2620     // If the conditions are the same, we can leave them alone.
2621     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2622     auto NewTBB = I->getOperand(0).getMBB();
2623     if (OldBranchCode == BranchCode && TBB == NewTBB)
2624       continue;
2625 
2626     // If they differ, see if they fit one of the known patterns. Theoretically,
2627     // we could handle more patterns here, but we shouldn't expect to see them
2628     // if instruction selection has done a reasonable job.
2629     if (TBB == NewTBB &&
2630                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
2631                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
2632       BranchCode = X86::COND_NE_OR_P;
2633     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
2634                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
2635       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
2636         return true;
2637 
2638       // X86::COND_E_AND_NP usually has two different branch destinations.
2639       //
2640       // JP B1
2641       // JE B2
2642       // JMP B1
2643       // B1:
2644       // B2:
2645       //
2646       // Here this condition branches to B2 only if NP && E. It has another
2647       // equivalent form:
2648       //
2649       // JNE B1
2650       // JNP B2
2651       // JMP B1
2652       // B1:
2653       // B2:
2654       //
2655       // Similarly it branches to B2 only if E && NP. That is why this condition
2656       // is named with COND_E_AND_NP.
2657       BranchCode = X86::COND_E_AND_NP;
2658     } else
2659       return true;
2660 
2661     // Update the MachineOperand.
2662     Cond[0].setImm(BranchCode);
2663     CondBranches.push_back(&*I);
2664   }
2665 
2666   return false;
2667 }
2668 
2669 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
2670                                  MachineBasicBlock *&TBB,
2671                                  MachineBasicBlock *&FBB,
2672                                  SmallVectorImpl<MachineOperand> &Cond,
2673                                  bool AllowModify) const {
2674   SmallVector<MachineInstr *, 4> CondBranches;
2675   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
2676 }
2677 
2678 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
2679                                           MachineBranchPredicate &MBP,
2680                                           bool AllowModify) const {
2681   using namespace std::placeholders;
2682 
2683   SmallVector<MachineOperand, 4> Cond;
2684   SmallVector<MachineInstr *, 4> CondBranches;
2685   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
2686                         AllowModify))
2687     return true;
2688 
2689   if (Cond.size() != 1)
2690     return true;
2691 
2692   assert(MBP.TrueDest && "expected!");
2693 
2694   if (!MBP.FalseDest)
2695     MBP.FalseDest = MBB.getNextNode();
2696 
2697   const TargetRegisterInfo *TRI = &getRegisterInfo();
2698 
2699   MachineInstr *ConditionDef = nullptr;
2700   bool SingleUseCondition = true;
2701 
2702   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
2703     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
2704       ConditionDef = &*I;
2705       break;
2706     }
2707 
2708     if (I->readsRegister(X86::EFLAGS, TRI))
2709       SingleUseCondition = false;
2710   }
2711 
2712   if (!ConditionDef)
2713     return true;
2714 
2715   if (SingleUseCondition) {
2716     for (auto *Succ : MBB.successors())
2717       if (Succ->isLiveIn(X86::EFLAGS))
2718         SingleUseCondition = false;
2719   }
2720 
2721   MBP.ConditionDef = ConditionDef;
2722   MBP.SingleUseCondition = SingleUseCondition;
2723 
2724   // Currently we only recognize the simple pattern:
2725   //
2726   //   test %reg, %reg
2727   //   je %label
2728   //
2729   const unsigned TestOpcode =
2730       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
2731 
2732   if (ConditionDef->getOpcode() == TestOpcode &&
2733       ConditionDef->getNumOperands() == 3 &&
2734       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
2735       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
2736     MBP.LHS = ConditionDef->getOperand(0);
2737     MBP.RHS = MachineOperand::CreateImm(0);
2738     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
2739                         ? MachineBranchPredicate::PRED_NE
2740                         : MachineBranchPredicate::PRED_EQ;
2741     return false;
2742   }
2743 
2744   return true;
2745 }
2746 
2747 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
2748                                     int *BytesRemoved) const {
2749   assert(!BytesRemoved && "code size not handled");
2750 
2751   MachineBasicBlock::iterator I = MBB.end();
2752   unsigned Count = 0;
2753 
2754   while (I != MBB.begin()) {
2755     --I;
2756     if (I->isDebugInstr())
2757       continue;
2758     if (I->getOpcode() != X86::JMP_1 &&
2759         X86::getCondFromBranch(*I) == X86::COND_INVALID)
2760       break;
2761     // Remove the branch.
2762     I->eraseFromParent();
2763     I = MBB.end();
2764     ++Count;
2765   }
2766 
2767   return Count;
2768 }
2769 
2770 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
2771                                     MachineBasicBlock *TBB,
2772                                     MachineBasicBlock *FBB,
2773                                     ArrayRef<MachineOperand> Cond,
2774                                     const DebugLoc &DL,
2775                                     int *BytesAdded) const {
2776   // Shouldn't be a fall through.
2777   assert(TBB && "insertBranch must not be told to insert a fallthrough");
2778   assert((Cond.size() == 1 || Cond.size() == 0) &&
2779          "X86 branch conditions have one component!");
2780   assert(!BytesAdded && "code size not handled");
2781 
2782   if (Cond.empty()) {
2783     // Unconditional branch?
2784     assert(!FBB && "Unconditional branch with multiple successors!");
2785     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2786     return 1;
2787   }
2788 
2789   // If FBB is null, it is implied to be a fall-through block.
2790   bool FallThru = FBB == nullptr;
2791 
2792   // Conditional branch.
2793   unsigned Count = 0;
2794   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2795   switch (CC) {
2796   case X86::COND_NE_OR_P:
2797     // Synthesize NE_OR_P with two branches.
2798     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
2799     ++Count;
2800     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
2801     ++Count;
2802     break;
2803   case X86::COND_E_AND_NP:
2804     // Use the next block of MBB as FBB if it is null.
2805     if (FBB == nullptr) {
2806       FBB = getFallThroughMBB(&MBB, TBB);
2807       assert(FBB && "MBB cannot be the last block in function when the false "
2808                     "body is a fall-through.");
2809     }
2810     // Synthesize COND_E_AND_NP with two branches.
2811     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
2812     ++Count;
2813     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
2814     ++Count;
2815     break;
2816   default: {
2817     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
2818     ++Count;
2819   }
2820   }
2821   if (!FallThru) {
2822     // Two-way Conditional branch. Insert the second branch.
2823     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
2824     ++Count;
2825   }
2826   return Count;
2827 }
2828 
2829 bool X86InstrInfo::
2830 canInsertSelect(const MachineBasicBlock &MBB,
2831                 ArrayRef<MachineOperand> Cond,
2832                 unsigned TrueReg, unsigned FalseReg,
2833                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2834   // Not all subtargets have cmov instructions.
2835   if (!Subtarget.hasCMov())
2836     return false;
2837   if (Cond.size() != 1)
2838     return false;
2839   // We cannot do the composite conditions, at least not in SSA form.
2840   if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
2841     return false;
2842 
2843   // Check register classes.
2844   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2845   const TargetRegisterClass *RC =
2846     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2847   if (!RC)
2848     return false;
2849 
2850   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2851   if (X86::GR16RegClass.hasSubClassEq(RC) ||
2852       X86::GR32RegClass.hasSubClassEq(RC) ||
2853       X86::GR64RegClass.hasSubClassEq(RC)) {
2854     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2855     // Bridge. Probably Ivy Bridge as well.
2856     CondCycles = 2;
2857     TrueCycles = 2;
2858     FalseCycles = 2;
2859     return true;
2860   }
2861 
2862   // Can't do vectors.
2863   return false;
2864 }
2865 
2866 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2867                                 MachineBasicBlock::iterator I,
2868                                 const DebugLoc &DL, unsigned DstReg,
2869                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
2870                                 unsigned FalseReg) const {
2871   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2872   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
2873   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
2874   assert(Cond.size() == 1 && "Invalid Cond array");
2875   unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
2876                                     false /*HasMemoryOperand*/);
2877   BuildMI(MBB, I, DL, get(Opc), DstReg)
2878       .addReg(FalseReg)
2879       .addReg(TrueReg)
2880       .addImm(Cond[0].getImm());
2881 }
2882 
2883 /// Test if the given register is a physical h register.
2884 static bool isHReg(unsigned Reg) {
2885   return X86::GR8_ABCD_HRegClass.contains(Reg);
2886 }
2887 
2888 // Try and copy between VR128/VR64 and GR64 registers.
2889 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2890                                         const X86Subtarget &Subtarget) {
2891   bool HasAVX = Subtarget.hasAVX();
2892   bool HasAVX512 = Subtarget.hasAVX512();
2893 
2894   // SrcReg(MaskReg) -> DestReg(GR64)
2895   // SrcReg(MaskReg) -> DestReg(GR32)
2896 
2897   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2898   if (X86::VK16RegClass.contains(SrcReg)) {
2899     if (X86::GR64RegClass.contains(DestReg)) {
2900       assert(Subtarget.hasBWI());
2901       return X86::KMOVQrk;
2902     }
2903     if (X86::GR32RegClass.contains(DestReg))
2904       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
2905   }
2906 
2907   // SrcReg(GR64) -> DestReg(MaskReg)
2908   // SrcReg(GR32) -> DestReg(MaskReg)
2909 
2910   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2911   if (X86::VK16RegClass.contains(DestReg)) {
2912     if (X86::GR64RegClass.contains(SrcReg)) {
2913       assert(Subtarget.hasBWI());
2914       return X86::KMOVQkr;
2915     }
2916     if (X86::GR32RegClass.contains(SrcReg))
2917       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
2918   }
2919 
2920 
2921   // SrcReg(VR128) -> DestReg(GR64)
2922   // SrcReg(VR64)  -> DestReg(GR64)
2923   // SrcReg(GR64)  -> DestReg(VR128)
2924   // SrcReg(GR64)  -> DestReg(VR64)
2925 
2926   if (X86::GR64RegClass.contains(DestReg)) {
2927     if (X86::VR128XRegClass.contains(SrcReg))
2928       // Copy from a VR128 register to a GR64 register.
2929       return HasAVX512 ? X86::VMOVPQIto64Zrr :
2930              HasAVX    ? X86::VMOVPQIto64rr  :
2931                          X86::MOVPQIto64rr;
2932     if (X86::VR64RegClass.contains(SrcReg))
2933       // Copy from a VR64 register to a GR64 register.
2934       return X86::MMX_MOVD64from64rr;
2935   } else if (X86::GR64RegClass.contains(SrcReg)) {
2936     // Copy from a GR64 register to a VR128 register.
2937     if (X86::VR128XRegClass.contains(DestReg))
2938       return HasAVX512 ? X86::VMOV64toPQIZrr :
2939              HasAVX    ? X86::VMOV64toPQIrr  :
2940                          X86::MOV64toPQIrr;
2941     // Copy from a GR64 register to a VR64 register.
2942     if (X86::VR64RegClass.contains(DestReg))
2943       return X86::MMX_MOVD64to64rr;
2944   }
2945 
2946   // SrcReg(VR128) -> DestReg(GR32)
2947   // SrcReg(GR32)  -> DestReg(VR128)
2948 
2949   if (X86::GR32RegClass.contains(DestReg) &&
2950       X86::VR128XRegClass.contains(SrcReg))
2951     // Copy from a VR128 register to a GR32 register.
2952     return HasAVX512 ? X86::VMOVPDI2DIZrr :
2953            HasAVX    ? X86::VMOVPDI2DIrr  :
2954                        X86::MOVPDI2DIrr;
2955 
2956   if (X86::VR128XRegClass.contains(DestReg) &&
2957       X86::GR32RegClass.contains(SrcReg))
2958     // Copy from a VR128 register to a VR128 register.
2959     return HasAVX512 ? X86::VMOVDI2PDIZrr :
2960            HasAVX    ? X86::VMOVDI2PDIrr  :
2961                        X86::MOVDI2PDIrr;
2962   return 0;
2963 }
2964 
2965 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2966                                MachineBasicBlock::iterator MI,
2967                                const DebugLoc &DL, MCRegister DestReg,
2968                                MCRegister SrcReg, bool KillSrc) const {
2969   // First deal with the normal symmetric copies.
2970   bool HasAVX = Subtarget.hasAVX();
2971   bool HasVLX = Subtarget.hasVLX();
2972   unsigned Opc = 0;
2973   if (X86::GR64RegClass.contains(DestReg, SrcReg))
2974     Opc = X86::MOV64rr;
2975   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2976     Opc = X86::MOV32rr;
2977   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2978     Opc = X86::MOV16rr;
2979   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2980     // Copying to or from a physical H register on x86-64 requires a NOREX
2981     // move.  Otherwise use a normal move.
2982     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2983         Subtarget.is64Bit()) {
2984       Opc = X86::MOV8rr_NOREX;
2985       // Both operands must be encodable without an REX prefix.
2986       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2987              "8-bit H register can not be copied outside GR8_NOREX");
2988     } else
2989       Opc = X86::MOV8rr;
2990   }
2991   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2992     Opc = X86::MMX_MOVQ64rr;
2993   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
2994     if (HasVLX)
2995       Opc = X86::VMOVAPSZ128rr;
2996     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2997       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2998     else {
2999       // If this an extended register and we don't have VLX we need to use a
3000       // 512-bit move.
3001       Opc = X86::VMOVAPSZrr;
3002       const TargetRegisterInfo *TRI = &getRegisterInfo();
3003       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3004                                          &X86::VR512RegClass);
3005       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3006                                         &X86::VR512RegClass);
3007     }
3008   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3009     if (HasVLX)
3010       Opc = X86::VMOVAPSZ256rr;
3011     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3012       Opc = X86::VMOVAPSYrr;
3013     else {
3014       // If this an extended register and we don't have VLX we need to use a
3015       // 512-bit move.
3016       Opc = X86::VMOVAPSZrr;
3017       const TargetRegisterInfo *TRI = &getRegisterInfo();
3018       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3019                                          &X86::VR512RegClass);
3020       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3021                                         &X86::VR512RegClass);
3022     }
3023   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3024     Opc = X86::VMOVAPSZrr;
3025   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3026   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3027     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3028   if (!Opc)
3029     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3030 
3031   if (Opc) {
3032     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3033       .addReg(SrcReg, getKillRegState(KillSrc));
3034     return;
3035   }
3036 
3037   if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3038     // FIXME: We use a fatal error here because historically LLVM has tried
3039     // lower some of these physreg copies and we want to ensure we get
3040     // reasonable bug reports if someone encounters a case no other testing
3041     // found. This path should be removed after the LLVM 7 release.
3042     report_fatal_error("Unable to copy EFLAGS physical register!");
3043   }
3044 
3045   LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3046                     << RI.getName(DestReg) << '\n');
3047   report_fatal_error("Cannot emit physreg copy instruction");
3048 }
3049 
3050 Optional<DestSourcePair>
3051 X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
3052   if (MI.isMoveReg())
3053     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
3054   return None;
3055 }
3056 
3057 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3058                                       const TargetRegisterClass *RC,
3059                                       bool isStackAligned,
3060                                       const X86Subtarget &STI,
3061                                       bool load) {
3062   bool HasAVX = STI.hasAVX();
3063   bool HasAVX512 = STI.hasAVX512();
3064   bool HasVLX = STI.hasVLX();
3065 
3066   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3067   default:
3068     llvm_unreachable("Unknown spill size");
3069   case 1:
3070     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3071     if (STI.is64Bit())
3072       // Copying to or from a physical H register on x86-64 requires a NOREX
3073       // move.  Otherwise use a normal move.
3074       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3075         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3076     return load ? X86::MOV8rm : X86::MOV8mr;
3077   case 2:
3078     if (X86::VK16RegClass.hasSubClassEq(RC))
3079       return load ? X86::KMOVWkm : X86::KMOVWmk;
3080     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3081     return load ? X86::MOV16rm : X86::MOV16mr;
3082   case 4:
3083     if (X86::GR32RegClass.hasSubClassEq(RC))
3084       return load ? X86::MOV32rm : X86::MOV32mr;
3085     if (X86::FR32XRegClass.hasSubClassEq(RC))
3086       return load ?
3087         (HasAVX512 ? X86::VMOVSSZrm_alt :
3088          HasAVX    ? X86::VMOVSSrm_alt :
3089                      X86::MOVSSrm_alt) :
3090         (HasAVX512 ? X86::VMOVSSZmr :
3091          HasAVX    ? X86::VMOVSSmr :
3092                      X86::MOVSSmr);
3093     if (X86::RFP32RegClass.hasSubClassEq(RC))
3094       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3095     if (X86::VK32RegClass.hasSubClassEq(RC)) {
3096       assert(STI.hasBWI() && "KMOVD requires BWI");
3097       return load ? X86::KMOVDkm : X86::KMOVDmk;
3098     }
3099     // All of these mask pair classes have the same spill size, the same kind
3100     // of kmov instructions can be used with all of them.
3101     if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3102         X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3103         X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3104         X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3105         X86::VK16PAIRRegClass.hasSubClassEq(RC))
3106       return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3107     llvm_unreachable("Unknown 4-byte regclass");
3108   case 8:
3109     if (X86::GR64RegClass.hasSubClassEq(RC))
3110       return load ? X86::MOV64rm : X86::MOV64mr;
3111     if (X86::FR64XRegClass.hasSubClassEq(RC))
3112       return load ?
3113         (HasAVX512 ? X86::VMOVSDZrm_alt :
3114          HasAVX    ? X86::VMOVSDrm_alt :
3115                      X86::MOVSDrm_alt) :
3116         (HasAVX512 ? X86::VMOVSDZmr :
3117          HasAVX    ? X86::VMOVSDmr :
3118                      X86::MOVSDmr);
3119     if (X86::VR64RegClass.hasSubClassEq(RC))
3120       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3121     if (X86::RFP64RegClass.hasSubClassEq(RC))
3122       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3123     if (X86::VK64RegClass.hasSubClassEq(RC)) {
3124       assert(STI.hasBWI() && "KMOVQ requires BWI");
3125       return load ? X86::KMOVQkm : X86::KMOVQmk;
3126     }
3127     llvm_unreachable("Unknown 8-byte regclass");
3128   case 10:
3129     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3130     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3131   case 16: {
3132     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3133       // If stack is realigned we can use aligned stores.
3134       if (isStackAligned)
3135         return load ?
3136           (HasVLX    ? X86::VMOVAPSZ128rm :
3137            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3138            HasAVX    ? X86::VMOVAPSrm :
3139                        X86::MOVAPSrm):
3140           (HasVLX    ? X86::VMOVAPSZ128mr :
3141            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3142            HasAVX    ? X86::VMOVAPSmr :
3143                        X86::MOVAPSmr);
3144       else
3145         return load ?
3146           (HasVLX    ? X86::VMOVUPSZ128rm :
3147            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3148            HasAVX    ? X86::VMOVUPSrm :
3149                        X86::MOVUPSrm):
3150           (HasVLX    ? X86::VMOVUPSZ128mr :
3151            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3152            HasAVX    ? X86::VMOVUPSmr :
3153                        X86::MOVUPSmr);
3154     }
3155     if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3156       if (STI.is64Bit())
3157         return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3158       else
3159         return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3160     }
3161     llvm_unreachable("Unknown 16-byte regclass");
3162   }
3163   case 32:
3164     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3165     // If stack is realigned we can use aligned stores.
3166     if (isStackAligned)
3167       return load ?
3168         (HasVLX    ? X86::VMOVAPSZ256rm :
3169          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3170                      X86::VMOVAPSYrm) :
3171         (HasVLX    ? X86::VMOVAPSZ256mr :
3172          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3173                      X86::VMOVAPSYmr);
3174     else
3175       return load ?
3176         (HasVLX    ? X86::VMOVUPSZ256rm :
3177          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3178                      X86::VMOVUPSYrm) :
3179         (HasVLX    ? X86::VMOVUPSZ256mr :
3180          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3181                      X86::VMOVUPSYmr);
3182   case 64:
3183     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3184     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3185     if (isStackAligned)
3186       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3187     else
3188       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3189   }
3190 }
3191 
3192 bool X86InstrInfo::getMemOperandWithOffset(
3193     const MachineInstr &MemOp, const MachineOperand *&BaseOp, int64_t &Offset,
3194     const TargetRegisterInfo *TRI) const {
3195   const MCInstrDesc &Desc = MemOp.getDesc();
3196   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3197   if (MemRefBegin < 0)
3198     return false;
3199 
3200   MemRefBegin += X86II::getOperandBias(Desc);
3201 
3202   BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3203   if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3204     return false;
3205 
3206   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3207     return false;
3208 
3209   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3210       X86::NoRegister)
3211     return false;
3212 
3213   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3214 
3215   // Displacement can be symbolic
3216   if (!DispMO.isImm())
3217     return false;
3218 
3219   Offset = DispMO.getImm();
3220 
3221   assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
3222                             "operands of type register.");
3223   return true;
3224 }
3225 
3226 static unsigned getStoreRegOpcode(unsigned SrcReg,
3227                                   const TargetRegisterClass *RC,
3228                                   bool isStackAligned,
3229                                   const X86Subtarget &STI) {
3230   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3231 }
3232 
3233 
3234 static unsigned getLoadRegOpcode(unsigned DestReg,
3235                                  const TargetRegisterClass *RC,
3236                                  bool isStackAligned,
3237                                  const X86Subtarget &STI) {
3238   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3239 }
3240 
3241 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3242                                        MachineBasicBlock::iterator MI,
3243                                        unsigned SrcReg, bool isKill, int FrameIdx,
3244                                        const TargetRegisterClass *RC,
3245                                        const TargetRegisterInfo *TRI) const {
3246   const MachineFunction &MF = *MBB.getParent();
3247   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3248          "Stack slot too small for store");
3249   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3250   bool isAligned =
3251       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3252       RI.canRealignStack(MF);
3253   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3254   addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3255     .addReg(SrcReg, getKillRegState(isKill));
3256 }
3257 
3258 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3259                                         MachineBasicBlock::iterator MI,
3260                                         unsigned DestReg, int FrameIdx,
3261                                         const TargetRegisterClass *RC,
3262                                         const TargetRegisterInfo *TRI) const {
3263   const MachineFunction &MF = *MBB.getParent();
3264   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3265   bool isAligned =
3266       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3267       RI.canRealignStack(MF);
3268   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3269   addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3270 }
3271 
3272 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
3273                                   unsigned &SrcReg2, int &CmpMask,
3274                                   int &CmpValue) const {
3275   switch (MI.getOpcode()) {
3276   default: break;
3277   case X86::CMP64ri32:
3278   case X86::CMP64ri8:
3279   case X86::CMP32ri:
3280   case X86::CMP32ri8:
3281   case X86::CMP16ri:
3282   case X86::CMP16ri8:
3283   case X86::CMP8ri:
3284     SrcReg = MI.getOperand(0).getReg();
3285     SrcReg2 = 0;
3286     if (MI.getOperand(1).isImm()) {
3287       CmpMask = ~0;
3288       CmpValue = MI.getOperand(1).getImm();
3289     } else {
3290       CmpMask = CmpValue = 0;
3291     }
3292     return true;
3293   // A SUB can be used to perform comparison.
3294   case X86::SUB64rm:
3295   case X86::SUB32rm:
3296   case X86::SUB16rm:
3297   case X86::SUB8rm:
3298     SrcReg = MI.getOperand(1).getReg();
3299     SrcReg2 = 0;
3300     CmpMask = 0;
3301     CmpValue = 0;
3302     return true;
3303   case X86::SUB64rr:
3304   case X86::SUB32rr:
3305   case X86::SUB16rr:
3306   case X86::SUB8rr:
3307     SrcReg = MI.getOperand(1).getReg();
3308     SrcReg2 = MI.getOperand(2).getReg();
3309     CmpMask = 0;
3310     CmpValue = 0;
3311     return true;
3312   case X86::SUB64ri32:
3313   case X86::SUB64ri8:
3314   case X86::SUB32ri:
3315   case X86::SUB32ri8:
3316   case X86::SUB16ri:
3317   case X86::SUB16ri8:
3318   case X86::SUB8ri:
3319     SrcReg = MI.getOperand(1).getReg();
3320     SrcReg2 = 0;
3321     if (MI.getOperand(2).isImm()) {
3322       CmpMask = ~0;
3323       CmpValue = MI.getOperand(2).getImm();
3324     } else {
3325       CmpMask = CmpValue = 0;
3326     }
3327     return true;
3328   case X86::CMP64rr:
3329   case X86::CMP32rr:
3330   case X86::CMP16rr:
3331   case X86::CMP8rr:
3332     SrcReg = MI.getOperand(0).getReg();
3333     SrcReg2 = MI.getOperand(1).getReg();
3334     CmpMask = 0;
3335     CmpValue = 0;
3336     return true;
3337   case X86::TEST8rr:
3338   case X86::TEST16rr:
3339   case X86::TEST32rr:
3340   case X86::TEST64rr:
3341     SrcReg = MI.getOperand(0).getReg();
3342     if (MI.getOperand(1).getReg() != SrcReg)
3343       return false;
3344     // Compare against zero.
3345     SrcReg2 = 0;
3346     CmpMask = ~0;
3347     CmpValue = 0;
3348     return true;
3349   }
3350   return false;
3351 }
3352 
3353 /// Check whether the first instruction, whose only
3354 /// purpose is to update flags, can be made redundant.
3355 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3356 /// This function can be extended later on.
3357 /// SrcReg, SrcRegs: register operands for FlagI.
3358 /// ImmValue: immediate for FlagI if it takes an immediate.
3359 inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3360                                         unsigned SrcReg, unsigned SrcReg2,
3361                                         int ImmMask, int ImmValue,
3362                                         const MachineInstr &OI) {
3363   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3364        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3365        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3366        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3367       ((OI.getOperand(1).getReg() == SrcReg &&
3368         OI.getOperand(2).getReg() == SrcReg2) ||
3369        (OI.getOperand(1).getReg() == SrcReg2 &&
3370         OI.getOperand(2).getReg() == SrcReg)))
3371     return true;
3372 
3373   if (ImmMask != 0 &&
3374       ((FlagI.getOpcode() == X86::CMP64ri32 &&
3375         OI.getOpcode() == X86::SUB64ri32) ||
3376        (FlagI.getOpcode() == X86::CMP64ri8 &&
3377         OI.getOpcode() == X86::SUB64ri8) ||
3378        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3379        (FlagI.getOpcode() == X86::CMP32ri8 &&
3380         OI.getOpcode() == X86::SUB32ri8) ||
3381        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3382        (FlagI.getOpcode() == X86::CMP16ri8 &&
3383         OI.getOpcode() == X86::SUB16ri8) ||
3384        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3385       OI.getOperand(1).getReg() == SrcReg &&
3386       OI.getOperand(2).getImm() == ImmValue)
3387     return true;
3388   return false;
3389 }
3390 
3391 /// Check whether the definition can be converted
3392 /// to remove a comparison against zero.
3393 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3394   NoSignFlag = false;
3395 
3396   switch (MI.getOpcode()) {
3397   default: return false;
3398 
3399   // The shift instructions only modify ZF if their shift count is non-zero.
3400   // N.B.: The processor truncates the shift count depending on the encoding.
3401   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3402   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3403      return getTruncatedShiftCount(MI, 2) != 0;
3404 
3405   // Some left shift instructions can be turned into LEA instructions but only
3406   // if their flags aren't used. Avoid transforming such instructions.
3407   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3408     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3409     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3410     return ShAmt != 0;
3411   }
3412 
3413   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3414   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3415      return getTruncatedShiftCount(MI, 3) != 0;
3416 
3417   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3418   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3419   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3420   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3421   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3422   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3423   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3424   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3425   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3426   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3427   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3428   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3429   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3430   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3431   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3432   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3433   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3434   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3435   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3436   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3437   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3438   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3439   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3440   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3441   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3442   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3443   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3444   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3445   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
3446   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
3447   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
3448   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
3449   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3450   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
3451   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
3452   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
3453   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
3454   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
3455   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
3456   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
3457   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
3458   case X86::ANDN32rr:  case X86::ANDN32rm:
3459   case X86::ANDN64rr:  case X86::ANDN64rm:
3460   case X86::BLSI32rr:  case X86::BLSI32rm:
3461   case X86::BLSI64rr:  case X86::BLSI64rm:
3462   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3463   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3464   case X86::BLSR32rr:  case X86::BLSR32rm:
3465   case X86::BLSR64rr:  case X86::BLSR64rm:
3466   case X86::BZHI32rr:  case X86::BZHI32rm:
3467   case X86::BZHI64rr:  case X86::BZHI64rm:
3468   case X86::LZCNT16rr: case X86::LZCNT16rm:
3469   case X86::LZCNT32rr: case X86::LZCNT32rm:
3470   case X86::LZCNT64rr: case X86::LZCNT64rm:
3471   case X86::POPCNT16rr:case X86::POPCNT16rm:
3472   case X86::POPCNT32rr:case X86::POPCNT32rm:
3473   case X86::POPCNT64rr:case X86::POPCNT64rm:
3474   case X86::TZCNT16rr: case X86::TZCNT16rm:
3475   case X86::TZCNT32rr: case X86::TZCNT32rm:
3476   case X86::TZCNT64rr: case X86::TZCNT64rm:
3477   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
3478   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
3479   case X86::BLCI32rr:    case X86::BLCI32rm:
3480   case X86::BLCI64rr:    case X86::BLCI64rm:
3481   case X86::BLCIC32rr:   case X86::BLCIC32rm:
3482   case X86::BLCIC64rr:   case X86::BLCIC64rm:
3483   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
3484   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
3485   case X86::BLCS32rr:    case X86::BLCS32rm:
3486   case X86::BLCS64rr:    case X86::BLCS64rm:
3487   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
3488   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
3489   case X86::BLSIC32rr:   case X86::BLSIC32rm:
3490   case X86::BLSIC64rr:   case X86::BLSIC64rm:
3491   case X86::T1MSKC32rr:  case X86::T1MSKC32rm:
3492   case X86::T1MSKC64rr:  case X86::T1MSKC64rm:
3493   case X86::TZMSK32rr:   case X86::TZMSK32rm:
3494   case X86::TZMSK64rr:   case X86::TZMSK64rm:
3495     return true;
3496   case X86::BEXTR32rr:   case X86::BEXTR64rr:
3497   case X86::BEXTR32rm:   case X86::BEXTR64rm:
3498   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
3499   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
3500     // BEXTR doesn't update the sign flag so we can't use it.
3501     NoSignFlag = true;
3502     return true;
3503   }
3504 }
3505 
3506 /// Check whether the use can be converted to remove a comparison against zero.
3507 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
3508   switch (MI.getOpcode()) {
3509   default: return X86::COND_INVALID;
3510   case X86::NEG8r:
3511   case X86::NEG16r:
3512   case X86::NEG32r:
3513   case X86::NEG64r:
3514     return X86::COND_AE;
3515   case X86::LZCNT16rr:
3516   case X86::LZCNT32rr:
3517   case X86::LZCNT64rr:
3518     return X86::COND_B;
3519   case X86::POPCNT16rr:
3520   case X86::POPCNT32rr:
3521   case X86::POPCNT64rr:
3522     return X86::COND_E;
3523   case X86::TZCNT16rr:
3524   case X86::TZCNT32rr:
3525   case X86::TZCNT64rr:
3526     return X86::COND_B;
3527   case X86::BSF16rr:
3528   case X86::BSF32rr:
3529   case X86::BSF64rr:
3530   case X86::BSR16rr:
3531   case X86::BSR32rr:
3532   case X86::BSR64rr:
3533     return X86::COND_E;
3534   case X86::BLSI32rr:
3535   case X86::BLSI64rr:
3536     return X86::COND_AE;
3537   case X86::BLSR32rr:
3538   case X86::BLSR64rr:
3539   case X86::BLSMSK32rr:
3540   case X86::BLSMSK64rr:
3541     return X86::COND_B;
3542   // TODO: TBM instructions.
3543   }
3544 }
3545 
3546 /// Check if there exists an earlier instruction that
3547 /// operates on the same source operands and sets flags in the same way as
3548 /// Compare; remove Compare if possible.
3549 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
3550                                         unsigned SrcReg2, int CmpMask,
3551                                         int CmpValue,
3552                                         const MachineRegisterInfo *MRI) const {
3553   // Check whether we can replace SUB with CMP.
3554   switch (CmpInstr.getOpcode()) {
3555   default: break;
3556   case X86::SUB64ri32:
3557   case X86::SUB64ri8:
3558   case X86::SUB32ri:
3559   case X86::SUB32ri8:
3560   case X86::SUB16ri:
3561   case X86::SUB16ri8:
3562   case X86::SUB8ri:
3563   case X86::SUB64rm:
3564   case X86::SUB32rm:
3565   case X86::SUB16rm:
3566   case X86::SUB8rm:
3567   case X86::SUB64rr:
3568   case X86::SUB32rr:
3569   case X86::SUB16rr:
3570   case X86::SUB8rr: {
3571     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
3572       return false;
3573     // There is no use of the destination register, we can replace SUB with CMP.
3574     unsigned NewOpcode = 0;
3575     switch (CmpInstr.getOpcode()) {
3576     default: llvm_unreachable("Unreachable!");
3577     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
3578     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
3579     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
3580     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
3581     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
3582     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
3583     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
3584     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
3585     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3586     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
3587     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
3588     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
3589     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
3590     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
3591     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
3592     }
3593     CmpInstr.setDesc(get(NewOpcode));
3594     CmpInstr.RemoveOperand(0);
3595     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3596     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3597         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3598       return false;
3599   }
3600   }
3601 
3602   // Get the unique definition of SrcReg.
3603   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3604   if (!MI) return false;
3605 
3606   // CmpInstr is the first instruction of the BB.
3607   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3608 
3609   // If we are comparing against zero, check whether we can use MI to update
3610   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3611   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
3612   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
3613     return false;
3614 
3615   // If we have a use of the source register between the def and our compare
3616   // instruction we can eliminate the compare iff the use sets EFLAGS in the
3617   // right way.
3618   bool ShouldUpdateCC = false;
3619   bool NoSignFlag = false;
3620   X86::CondCode NewCC = X86::COND_INVALID;
3621   if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
3622     // Scan forward from the use until we hit the use we're looking for or the
3623     // compare instruction.
3624     for (MachineBasicBlock::iterator J = MI;; ++J) {
3625       // Do we have a convertible instruction?
3626       NewCC = isUseDefConvertible(*J);
3627       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3628           J->getOperand(1).getReg() == SrcReg) {
3629         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3630         ShouldUpdateCC = true; // Update CC later on.
3631         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3632         // with the new def.
3633         Def = J;
3634         MI = &*Def;
3635         break;
3636       }
3637 
3638       if (J == I)
3639         return false;
3640     }
3641   }
3642 
3643   // We are searching for an earlier instruction that can make CmpInstr
3644   // redundant and that instruction will be saved in Sub.
3645   MachineInstr *Sub = nullptr;
3646   const TargetRegisterInfo *TRI = &getRegisterInfo();
3647 
3648   // We iterate backward, starting from the instruction before CmpInstr and
3649   // stop when reaching the definition of a source register or done with the BB.
3650   // RI points to the instruction before CmpInstr.
3651   // If the definition is in this basic block, RE points to the definition;
3652   // otherwise, RE is the rend of the basic block.
3653   MachineBasicBlock::reverse_iterator
3654       RI = ++I.getReverse(),
3655       RE = CmpInstr.getParent() == MI->getParent()
3656                ? Def.getReverse() /* points to MI */
3657                : CmpInstr.getParent()->rend();
3658   MachineInstr *Movr0Inst = nullptr;
3659   for (; RI != RE; ++RI) {
3660     MachineInstr &Instr = *RI;
3661     // Check whether CmpInstr can be made redundant by the current instruction.
3662     if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
3663                                            CmpValue, Instr)) {
3664       Sub = &Instr;
3665       break;
3666     }
3667 
3668     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
3669         Instr.readsRegister(X86::EFLAGS, TRI)) {
3670       // This instruction modifies or uses EFLAGS.
3671 
3672       // MOV32r0 etc. are implemented with xor which clobbers condition code.
3673       // They are safe to move up, if the definition to EFLAGS is dead and
3674       // earlier instructions do not read or write EFLAGS.
3675       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
3676           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
3677         Movr0Inst = &Instr;
3678         continue;
3679       }
3680 
3681       // We can't remove CmpInstr.
3682       return false;
3683     }
3684   }
3685 
3686   // Return false if no candidates exist.
3687   if (!IsCmpZero && !Sub)
3688     return false;
3689 
3690   bool IsSwapped =
3691       (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
3692        Sub->getOperand(2).getReg() == SrcReg);
3693 
3694   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3695   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3696   // If we are done with the basic block, we need to check whether EFLAGS is
3697   // live-out.
3698   bool IsSafe = false;
3699   SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
3700   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
3701   for (++I; I != E; ++I) {
3702     const MachineInstr &Instr = *I;
3703     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3704     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3705     // We should check the usage if this instruction uses and updates EFLAGS.
3706     if (!UseEFLAGS && ModifyEFLAGS) {
3707       // It is safe to remove CmpInstr if EFLAGS is updated again.
3708       IsSafe = true;
3709       break;
3710     }
3711     if (!UseEFLAGS && !ModifyEFLAGS)
3712       continue;
3713 
3714     // EFLAGS is used by this instruction.
3715     X86::CondCode OldCC = X86::COND_INVALID;
3716     if (IsCmpZero || IsSwapped) {
3717       // We decode the condition code from opcode.
3718       if (Instr.isBranch())
3719         OldCC = X86::getCondFromBranch(Instr);
3720       else {
3721         OldCC = X86::getCondFromSETCC(Instr);
3722         if (OldCC == X86::COND_INVALID)
3723           OldCC = X86::getCondFromCMov(Instr);
3724       }
3725       if (OldCC == X86::COND_INVALID) return false;
3726     }
3727     X86::CondCode ReplacementCC = X86::COND_INVALID;
3728     if (IsCmpZero) {
3729       switch (OldCC) {
3730       default: break;
3731       case X86::COND_A: case X86::COND_AE:
3732       case X86::COND_B: case X86::COND_BE:
3733       case X86::COND_G: case X86::COND_GE:
3734       case X86::COND_L: case X86::COND_LE:
3735       case X86::COND_O: case X86::COND_NO:
3736         // CF and OF are used, we can't perform this optimization.
3737         return false;
3738       case X86::COND_S: case X86::COND_NS:
3739         // If SF is used, but the instruction doesn't update the SF, then we
3740         // can't do the optimization.
3741         if (NoSignFlag)
3742           return false;
3743         break;
3744       }
3745 
3746       // If we're updating the condition code check if we have to reverse the
3747       // condition.
3748       if (ShouldUpdateCC)
3749         switch (OldCC) {
3750         default:
3751           return false;
3752         case X86::COND_E:
3753           ReplacementCC = NewCC;
3754           break;
3755         case X86::COND_NE:
3756           ReplacementCC = GetOppositeBranchCondition(NewCC);
3757           break;
3758         }
3759     } else if (IsSwapped) {
3760       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3761       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3762       // We swap the condition code and synthesize the new opcode.
3763       ReplacementCC = getSwappedCondition(OldCC);
3764       if (ReplacementCC == X86::COND_INVALID) return false;
3765     }
3766 
3767     if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
3768       // Push the MachineInstr to OpsToUpdate.
3769       // If it is safe to remove CmpInstr, the condition code of these
3770       // instructions will be modified.
3771       OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
3772     }
3773     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3774       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3775       IsSafe = true;
3776       break;
3777     }
3778   }
3779 
3780   // If EFLAGS is not killed nor re-defined, we should check whether it is
3781   // live-out. If it is live-out, do not optimize.
3782   if ((IsCmpZero || IsSwapped) && !IsSafe) {
3783     MachineBasicBlock *MBB = CmpInstr.getParent();
3784     for (MachineBasicBlock *Successor : MBB->successors())
3785       if (Successor->isLiveIn(X86::EFLAGS))
3786         return false;
3787   }
3788 
3789   // The instruction to be updated is either Sub or MI.
3790   Sub = IsCmpZero ? MI : Sub;
3791   // Move Movr0Inst to the appropriate place before Sub.
3792   if (Movr0Inst) {
3793     // Look backwards until we find a def that doesn't use the current EFLAGS.
3794     Def = Sub;
3795     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
3796                                         InsertE = Sub->getParent()->rend();
3797     for (; InsertI != InsertE; ++InsertI) {
3798       MachineInstr *Instr = &*InsertI;
3799       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3800           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3801         Sub->getParent()->remove(Movr0Inst);
3802         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3803                                    Movr0Inst);
3804         break;
3805       }
3806     }
3807     if (InsertI == InsertE)
3808       return false;
3809   }
3810 
3811   // Make sure Sub instruction defines EFLAGS and mark the def live.
3812   MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
3813   assert(FlagDef && "Unable to locate a def EFLAGS operand");
3814   FlagDef->setIsDead(false);
3815 
3816   CmpInstr.eraseFromParent();
3817 
3818   // Modify the condition code of instructions in OpsToUpdate.
3819   for (auto &Op : OpsToUpdate) {
3820     Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
3821         .setImm(Op.second);
3822   }
3823   return true;
3824 }
3825 
3826 /// Try to remove the load by folding it to a register
3827 /// operand at the use. We fold the load instructions if load defines a virtual
3828 /// register, the virtual register is used once in the same BB, and the
3829 /// instructions in-between do not load or store, and have no side effects.
3830 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
3831                                               const MachineRegisterInfo *MRI,
3832                                               unsigned &FoldAsLoadDefReg,
3833                                               MachineInstr *&DefMI) const {
3834   // Check whether we can move DefMI here.
3835   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3836   assert(DefMI);
3837   bool SawStore = false;
3838   if (!DefMI->isSafeToMove(nullptr, SawStore))
3839     return nullptr;
3840 
3841   // Collect information about virtual register operands of MI.
3842   SmallVector<unsigned, 1> SrcOperandIds;
3843   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3844     MachineOperand &MO = MI.getOperand(i);
3845     if (!MO.isReg())
3846       continue;
3847     Register Reg = MO.getReg();
3848     if (Reg != FoldAsLoadDefReg)
3849       continue;
3850     // Do not fold if we have a subreg use or a def.
3851     if (MO.getSubReg() || MO.isDef())
3852       return nullptr;
3853     SrcOperandIds.push_back(i);
3854   }
3855   if (SrcOperandIds.empty())
3856     return nullptr;
3857 
3858   // Check whether we can fold the def into SrcOperandId.
3859   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
3860     FoldAsLoadDefReg = 0;
3861     return FoldMI;
3862   }
3863 
3864   return nullptr;
3865 }
3866 
3867 /// Expand a single-def pseudo instruction to a two-addr
3868 /// instruction with two undef reads of the register being defined.
3869 /// This is used for mapping:
3870 ///   %xmm4 = V_SET0
3871 /// to:
3872 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
3873 ///
3874 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3875                              const MCInstrDesc &Desc) {
3876   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3877   Register Reg = MIB->getOperand(0).getReg();
3878   MIB->setDesc(Desc);
3879 
3880   // MachineInstr::addOperand() will insert explicit operands before any
3881   // implicit operands.
3882   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3883   // But we don't trust that.
3884   assert(MIB->getOperand(1).getReg() == Reg &&
3885          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3886   return true;
3887 }
3888 
3889 /// Expand a single-def pseudo instruction to a two-addr
3890 /// instruction with two %k0 reads.
3891 /// This is used for mapping:
3892 ///   %k4 = K_SET1
3893 /// to:
3894 ///   %k4 = KXNORrr %k0, %k0
3895 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
3896                             const MCInstrDesc &Desc, unsigned Reg) {
3897   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3898   MIB->setDesc(Desc);
3899   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3900   return true;
3901 }
3902 
3903 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
3904                           bool MinusOne) {
3905   MachineBasicBlock &MBB = *MIB->getParent();
3906   DebugLoc DL = MIB->getDebugLoc();
3907   Register Reg = MIB->getOperand(0).getReg();
3908 
3909   // Insert the XOR.
3910   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
3911       .addReg(Reg, RegState::Undef)
3912       .addReg(Reg, RegState::Undef);
3913 
3914   // Turn the pseudo into an INC or DEC.
3915   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
3916   MIB.addReg(Reg);
3917 
3918   return true;
3919 }
3920 
3921 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
3922                                const TargetInstrInfo &TII,
3923                                const X86Subtarget &Subtarget) {
3924   MachineBasicBlock &MBB = *MIB->getParent();
3925   DebugLoc DL = MIB->getDebugLoc();
3926   int64_t Imm = MIB->getOperand(1).getImm();
3927   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
3928   MachineBasicBlock::iterator I = MIB.getInstr();
3929 
3930   int StackAdjustment;
3931 
3932   if (Subtarget.is64Bit()) {
3933     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
3934            MIB->getOpcode() == X86::MOV32ImmSExti8);
3935 
3936     // Can't use push/pop lowering if the function might write to the red zone.
3937     X86MachineFunctionInfo *X86FI =
3938         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
3939     if (X86FI->getUsesRedZone()) {
3940       MIB->setDesc(TII.get(MIB->getOpcode() ==
3941                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
3942       return true;
3943     }
3944 
3945     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
3946     // widen the register if necessary.
3947     StackAdjustment = 8;
3948     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
3949     MIB->setDesc(TII.get(X86::POP64r));
3950     MIB->getOperand(0)
3951         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
3952   } else {
3953     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
3954     StackAdjustment = 4;
3955     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
3956     MIB->setDesc(TII.get(X86::POP32r));
3957   }
3958 
3959   // Build CFI if necessary.
3960   MachineFunction &MF = *MBB.getParent();
3961   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
3962   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
3963   bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
3964   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
3965   if (EmitCFI) {
3966     TFL->BuildCFI(MBB, I, DL,
3967         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
3968     TFL->BuildCFI(MBB, std::next(I), DL,
3969         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
3970   }
3971 
3972   return true;
3973 }
3974 
3975 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
3976 // code sequence is needed for other targets.
3977 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
3978                                  const TargetInstrInfo &TII) {
3979   MachineBasicBlock &MBB = *MIB->getParent();
3980   DebugLoc DL = MIB->getDebugLoc();
3981   Register Reg = MIB->getOperand(0).getReg();
3982   const GlobalValue *GV =
3983       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
3984   auto Flags = MachineMemOperand::MOLoad |
3985                MachineMemOperand::MODereferenceable |
3986                MachineMemOperand::MOInvariant;
3987   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
3988       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
3989   MachineBasicBlock::iterator I = MIB.getInstr();
3990 
3991   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
3992       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
3993       .addMemOperand(MMO);
3994   MIB->setDebugLoc(DL);
3995   MIB->setDesc(TII.get(X86::MOV64rm));
3996   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
3997 }
3998 
3999 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4000   MachineBasicBlock &MBB = *MIB->getParent();
4001   MachineFunction &MF = *MBB.getParent();
4002   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4003   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4004   unsigned XorOp =
4005       MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4006   MIB->setDesc(TII.get(XorOp));
4007   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4008   return true;
4009 }
4010 
4011 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4012 // but not VLX. If it uses an extended register we need to use an instruction
4013 // that loads the lower 128/256-bit, but is available with only AVX512F.
4014 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4015                             const TargetRegisterInfo *TRI,
4016                             const MCInstrDesc &LoadDesc,
4017                             const MCInstrDesc &BroadcastDesc,
4018                             unsigned SubIdx) {
4019   Register DestReg = MIB->getOperand(0).getReg();
4020   // Check if DestReg is XMM16-31 or YMM16-31.
4021   if (TRI->getEncodingValue(DestReg) < 16) {
4022     // We can use a normal VEX encoded load.
4023     MIB->setDesc(LoadDesc);
4024   } else {
4025     // Use a 128/256-bit VBROADCAST instruction.
4026     MIB->setDesc(BroadcastDesc);
4027     // Change the destination to a 512-bit register.
4028     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4029     MIB->getOperand(0).setReg(DestReg);
4030   }
4031   return true;
4032 }
4033 
4034 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4035 // but not VLX. If it uses an extended register we need to use an instruction
4036 // that stores the lower 128/256-bit, but is available with only AVX512F.
4037 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4038                              const TargetRegisterInfo *TRI,
4039                              const MCInstrDesc &StoreDesc,
4040                              const MCInstrDesc &ExtractDesc,
4041                              unsigned SubIdx) {
4042   Register SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
4043   // Check if DestReg is XMM16-31 or YMM16-31.
4044   if (TRI->getEncodingValue(SrcReg) < 16) {
4045     // We can use a normal VEX encoded store.
4046     MIB->setDesc(StoreDesc);
4047   } else {
4048     // Use a VEXTRACTF instruction.
4049     MIB->setDesc(ExtractDesc);
4050     // Change the destination to a 512-bit register.
4051     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4052     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4053     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4054   }
4055 
4056   return true;
4057 }
4058 
4059 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4060   MIB->setDesc(Desc);
4061   int64_t ShiftAmt = MIB->getOperand(2).getImm();
4062   // Temporarily remove the immediate so we can add another source register.
4063   MIB->RemoveOperand(2);
4064   // Add the register. Don't copy the kill flag if there is one.
4065   MIB.addReg(MIB->getOperand(1).getReg(),
4066              getUndefRegState(MIB->getOperand(1).isUndef()));
4067   // Add back the immediate.
4068   MIB.addImm(ShiftAmt);
4069   return true;
4070 }
4071 
4072 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4073   bool HasAVX = Subtarget.hasAVX();
4074   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4075   switch (MI.getOpcode()) {
4076   case X86::MOV32r0:
4077     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4078   case X86::MOV32r1:
4079     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4080   case X86::MOV32r_1:
4081     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4082   case X86::MOV32ImmSExti8:
4083   case X86::MOV64ImmSExti8:
4084     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4085   case X86::SETB_C8r:
4086     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4087   case X86::SETB_C16r:
4088     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4089   case X86::SETB_C32r:
4090     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4091   case X86::SETB_C64r:
4092     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4093   case X86::MMX_SET0:
4094     return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4095   case X86::V_SET0:
4096   case X86::FsFLD0SS:
4097   case X86::FsFLD0SD:
4098   case X86::FsFLD0F128:
4099     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4100   case X86::AVX_SET0: {
4101     assert(HasAVX && "AVX not supported");
4102     const TargetRegisterInfo *TRI = &getRegisterInfo();
4103     Register SrcReg = MIB->getOperand(0).getReg();
4104     Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4105     MIB->getOperand(0).setReg(XReg);
4106     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4107     MIB.addReg(SrcReg, RegState::ImplicitDefine);
4108     return true;
4109   }
4110   case X86::AVX512_128_SET0:
4111   case X86::AVX512_FsFLD0SS:
4112   case X86::AVX512_FsFLD0SD:
4113   case X86::AVX512_FsFLD0F128: {
4114     bool HasVLX = Subtarget.hasVLX();
4115     Register SrcReg = MIB->getOperand(0).getReg();
4116     const TargetRegisterInfo *TRI = &getRegisterInfo();
4117     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4118       return Expand2AddrUndef(MIB,
4119                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4120     // Extended register without VLX. Use a larger XOR.
4121     SrcReg =
4122         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4123     MIB->getOperand(0).setReg(SrcReg);
4124     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4125   }
4126   case X86::AVX512_256_SET0:
4127   case X86::AVX512_512_SET0: {
4128     bool HasVLX = Subtarget.hasVLX();
4129     Register SrcReg = MIB->getOperand(0).getReg();
4130     const TargetRegisterInfo *TRI = &getRegisterInfo();
4131     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4132       Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4133       MIB->getOperand(0).setReg(XReg);
4134       Expand2AddrUndef(MIB,
4135                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4136       MIB.addReg(SrcReg, RegState::ImplicitDefine);
4137       return true;
4138     }
4139     if (MI.getOpcode() == X86::AVX512_256_SET0) {
4140       // No VLX so we must reference a zmm.
4141       unsigned ZReg =
4142         TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4143       MIB->getOperand(0).setReg(ZReg);
4144     }
4145     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4146   }
4147   case X86::V_SETALLONES:
4148     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4149   case X86::AVX2_SETALLONES:
4150     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4151   case X86::AVX1_SETALLONES: {
4152     Register Reg = MIB->getOperand(0).getReg();
4153     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4154     MIB->setDesc(get(X86::VCMPPSYrri));
4155     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4156     return true;
4157   }
4158   case X86::AVX512_512_SETALLONES: {
4159     Register Reg = MIB->getOperand(0).getReg();
4160     MIB->setDesc(get(X86::VPTERNLOGDZrri));
4161     // VPTERNLOGD needs 3 register inputs and an immediate.
4162     // 0xff will return 1s for any input.
4163     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4164        .addReg(Reg, RegState::Undef).addImm(0xff);
4165     return true;
4166   }
4167   case X86::AVX512_512_SEXT_MASK_32:
4168   case X86::AVX512_512_SEXT_MASK_64: {
4169     Register Reg = MIB->getOperand(0).getReg();
4170     Register MaskReg = MIB->getOperand(1).getReg();
4171     unsigned MaskState = getRegState(MIB->getOperand(1));
4172     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4173                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4174     MI.RemoveOperand(1);
4175     MIB->setDesc(get(Opc));
4176     // VPTERNLOG needs 3 register inputs and an immediate.
4177     // 0xff will return 1s for any input.
4178     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4179        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4180     return true;
4181   }
4182   case X86::VMOVAPSZ128rm_NOVLX:
4183     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4184                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4185   case X86::VMOVUPSZ128rm_NOVLX:
4186     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4187                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4188   case X86::VMOVAPSZ256rm_NOVLX:
4189     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4190                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4191   case X86::VMOVUPSZ256rm_NOVLX:
4192     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4193                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4194   case X86::VMOVAPSZ128mr_NOVLX:
4195     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4196                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4197   case X86::VMOVUPSZ128mr_NOVLX:
4198     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4199                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4200   case X86::VMOVAPSZ256mr_NOVLX:
4201     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4202                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4203   case X86::VMOVUPSZ256mr_NOVLX:
4204     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4205                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4206   case X86::MOV32ri64: {
4207     Register Reg = MIB->getOperand(0).getReg();
4208     Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4209     MI.setDesc(get(X86::MOV32ri));
4210     MIB->getOperand(0).setReg(Reg32);
4211     MIB.addReg(Reg, RegState::ImplicitDefine);
4212     return true;
4213   }
4214 
4215   // KNL does not recognize dependency-breaking idioms for mask registers,
4216   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4217   // Using %k0 as the undef input register is a performance heuristic based
4218   // on the assumption that %k0 is used less frequently than the other mask
4219   // registers, since it is not usable as a write mask.
4220   // FIXME: A more advanced approach would be to choose the best input mask
4221   // register based on context.
4222   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4223   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4224   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4225   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4226   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4227   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4228   case TargetOpcode::LOAD_STACK_GUARD:
4229     expandLoadStackGuard(MIB, *this);
4230     return true;
4231   case X86::XOR64_FP:
4232   case X86::XOR32_FP:
4233     return expandXorFP(MIB, *this);
4234   case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4235   case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4236   case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4237   case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4238   case X86::ADD8rr_DB:    MIB->setDesc(get(X86::OR8rr));    break;
4239   case X86::ADD16rr_DB:   MIB->setDesc(get(X86::OR16rr));   break;
4240   case X86::ADD32rr_DB:   MIB->setDesc(get(X86::OR32rr));   break;
4241   case X86::ADD64rr_DB:   MIB->setDesc(get(X86::OR64rr));   break;
4242   case X86::ADD8ri_DB:    MIB->setDesc(get(X86::OR8ri));    break;
4243   case X86::ADD16ri_DB:   MIB->setDesc(get(X86::OR16ri));   break;
4244   case X86::ADD32ri_DB:   MIB->setDesc(get(X86::OR32ri));   break;
4245   case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4246   case X86::ADD16ri8_DB:  MIB->setDesc(get(X86::OR16ri8));  break;
4247   case X86::ADD32ri8_DB:  MIB->setDesc(get(X86::OR32ri8));  break;
4248   case X86::ADD64ri8_DB:  MIB->setDesc(get(X86::OR64ri8));  break;
4249   }
4250   return false;
4251 }
4252 
4253 /// Return true for all instructions that only update
4254 /// the first 32 or 64-bits of the destination register and leave the rest
4255 /// unmodified. This can be used to avoid folding loads if the instructions
4256 /// only update part of the destination register, and the non-updated part is
4257 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4258 /// instructions breaks the partial register dependency and it can improve
4259 /// performance. e.g.:
4260 ///
4261 ///   movss (%rdi), %xmm0
4262 ///   cvtss2sd %xmm0, %xmm0
4263 ///
4264 /// Instead of
4265 ///   cvtss2sd (%rdi), %xmm0
4266 ///
4267 /// FIXME: This should be turned into a TSFlags.
4268 ///
4269 static bool hasPartialRegUpdate(unsigned Opcode,
4270                                 const X86Subtarget &Subtarget,
4271                                 bool ForLoadFold = false) {
4272   switch (Opcode) {
4273   case X86::CVTSI2SSrr:
4274   case X86::CVTSI2SSrm:
4275   case X86::CVTSI642SSrr:
4276   case X86::CVTSI642SSrm:
4277   case X86::CVTSI2SDrr:
4278   case X86::CVTSI2SDrm:
4279   case X86::CVTSI642SDrr:
4280   case X86::CVTSI642SDrm:
4281     // Load folding won't effect the undef register update since the input is
4282     // a GPR.
4283     return !ForLoadFold;
4284   case X86::CVTSD2SSrr:
4285   case X86::CVTSD2SSrm:
4286   case X86::CVTSS2SDrr:
4287   case X86::CVTSS2SDrm:
4288   case X86::MOVHPDrm:
4289   case X86::MOVHPSrm:
4290   case X86::MOVLPDrm:
4291   case X86::MOVLPSrm:
4292   case X86::RCPSSr:
4293   case X86::RCPSSm:
4294   case X86::RCPSSr_Int:
4295   case X86::RCPSSm_Int:
4296   case X86::ROUNDSDr:
4297   case X86::ROUNDSDm:
4298   case X86::ROUNDSSr:
4299   case X86::ROUNDSSm:
4300   case X86::RSQRTSSr:
4301   case X86::RSQRTSSm:
4302   case X86::RSQRTSSr_Int:
4303   case X86::RSQRTSSm_Int:
4304   case X86::SQRTSSr:
4305   case X86::SQRTSSm:
4306   case X86::SQRTSSr_Int:
4307   case X86::SQRTSSm_Int:
4308   case X86::SQRTSDr:
4309   case X86::SQRTSDm:
4310   case X86::SQRTSDr_Int:
4311   case X86::SQRTSDm_Int:
4312     return true;
4313   // GPR
4314   case X86::POPCNT32rm:
4315   case X86::POPCNT32rr:
4316   case X86::POPCNT64rm:
4317   case X86::POPCNT64rr:
4318     return Subtarget.hasPOPCNTFalseDeps();
4319   case X86::LZCNT32rm:
4320   case X86::LZCNT32rr:
4321   case X86::LZCNT64rm:
4322   case X86::LZCNT64rr:
4323   case X86::TZCNT32rm:
4324   case X86::TZCNT32rr:
4325   case X86::TZCNT64rm:
4326   case X86::TZCNT64rr:
4327     return Subtarget.hasLZCNTFalseDeps();
4328   }
4329 
4330   return false;
4331 }
4332 
4333 /// Inform the BreakFalseDeps pass how many idle
4334 /// instructions we would like before a partial register update.
4335 unsigned X86InstrInfo::getPartialRegUpdateClearance(
4336     const MachineInstr &MI, unsigned OpNum,
4337     const TargetRegisterInfo *TRI) const {
4338   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4339     return 0;
4340 
4341   // If MI is marked as reading Reg, the partial register update is wanted.
4342   const MachineOperand &MO = MI.getOperand(0);
4343   Register Reg = MO.getReg();
4344   if (Register::isVirtualRegister(Reg)) {
4345     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4346       return 0;
4347   } else {
4348     if (MI.readsRegister(Reg, TRI))
4349       return 0;
4350   }
4351 
4352   // If any instructions in the clearance range are reading Reg, insert a
4353   // dependency breaking instruction, which is inexpensive and is likely to
4354   // be hidden in other instruction's cycles.
4355   return PartialRegUpdateClearance;
4356 }
4357 
4358 // Return true for any instruction the copies the high bits of the first source
4359 // operand into the unused high bits of the destination operand.
4360 static bool hasUndefRegUpdate(unsigned Opcode, unsigned &OpNum,
4361                               bool ForLoadFold = false) {
4362   // Set the OpNum parameter to the first source operand.
4363   OpNum = 1;
4364   switch (Opcode) {
4365   case X86::VCVTSI2SSrr:
4366   case X86::VCVTSI2SSrm:
4367   case X86::VCVTSI2SSrr_Int:
4368   case X86::VCVTSI2SSrm_Int:
4369   case X86::VCVTSI642SSrr:
4370   case X86::VCVTSI642SSrm:
4371   case X86::VCVTSI642SSrr_Int:
4372   case X86::VCVTSI642SSrm_Int:
4373   case X86::VCVTSI2SDrr:
4374   case X86::VCVTSI2SDrm:
4375   case X86::VCVTSI2SDrr_Int:
4376   case X86::VCVTSI2SDrm_Int:
4377   case X86::VCVTSI642SDrr:
4378   case X86::VCVTSI642SDrm:
4379   case X86::VCVTSI642SDrr_Int:
4380   case X86::VCVTSI642SDrm_Int:
4381   // AVX-512
4382   case X86::VCVTSI2SSZrr:
4383   case X86::VCVTSI2SSZrm:
4384   case X86::VCVTSI2SSZrr_Int:
4385   case X86::VCVTSI2SSZrrb_Int:
4386   case X86::VCVTSI2SSZrm_Int:
4387   case X86::VCVTSI642SSZrr:
4388   case X86::VCVTSI642SSZrm:
4389   case X86::VCVTSI642SSZrr_Int:
4390   case X86::VCVTSI642SSZrrb_Int:
4391   case X86::VCVTSI642SSZrm_Int:
4392   case X86::VCVTSI2SDZrr:
4393   case X86::VCVTSI2SDZrm:
4394   case X86::VCVTSI2SDZrr_Int:
4395   case X86::VCVTSI2SDZrm_Int:
4396   case X86::VCVTSI642SDZrr:
4397   case X86::VCVTSI642SDZrm:
4398   case X86::VCVTSI642SDZrr_Int:
4399   case X86::VCVTSI642SDZrrb_Int:
4400   case X86::VCVTSI642SDZrm_Int:
4401   case X86::VCVTUSI2SSZrr:
4402   case X86::VCVTUSI2SSZrm:
4403   case X86::VCVTUSI2SSZrr_Int:
4404   case X86::VCVTUSI2SSZrrb_Int:
4405   case X86::VCVTUSI2SSZrm_Int:
4406   case X86::VCVTUSI642SSZrr:
4407   case X86::VCVTUSI642SSZrm:
4408   case X86::VCVTUSI642SSZrr_Int:
4409   case X86::VCVTUSI642SSZrrb_Int:
4410   case X86::VCVTUSI642SSZrm_Int:
4411   case X86::VCVTUSI2SDZrr:
4412   case X86::VCVTUSI2SDZrm:
4413   case X86::VCVTUSI2SDZrr_Int:
4414   case X86::VCVTUSI2SDZrm_Int:
4415   case X86::VCVTUSI642SDZrr:
4416   case X86::VCVTUSI642SDZrm:
4417   case X86::VCVTUSI642SDZrr_Int:
4418   case X86::VCVTUSI642SDZrrb_Int:
4419   case X86::VCVTUSI642SDZrm_Int:
4420     // Load folding won't effect the undef register update since the input is
4421     // a GPR.
4422     return !ForLoadFold;
4423   case X86::VCVTSD2SSrr:
4424   case X86::VCVTSD2SSrm:
4425   case X86::VCVTSD2SSrr_Int:
4426   case X86::VCVTSD2SSrm_Int:
4427   case X86::VCVTSS2SDrr:
4428   case X86::VCVTSS2SDrm:
4429   case X86::VCVTSS2SDrr_Int:
4430   case X86::VCVTSS2SDrm_Int:
4431   case X86::VRCPSSr:
4432   case X86::VRCPSSr_Int:
4433   case X86::VRCPSSm:
4434   case X86::VRCPSSm_Int:
4435   case X86::VROUNDSDr:
4436   case X86::VROUNDSDm:
4437   case X86::VROUNDSDr_Int:
4438   case X86::VROUNDSDm_Int:
4439   case X86::VROUNDSSr:
4440   case X86::VROUNDSSm:
4441   case X86::VROUNDSSr_Int:
4442   case X86::VROUNDSSm_Int:
4443   case X86::VRSQRTSSr:
4444   case X86::VRSQRTSSr_Int:
4445   case X86::VRSQRTSSm:
4446   case X86::VRSQRTSSm_Int:
4447   case X86::VSQRTSSr:
4448   case X86::VSQRTSSr_Int:
4449   case X86::VSQRTSSm:
4450   case X86::VSQRTSSm_Int:
4451   case X86::VSQRTSDr:
4452   case X86::VSQRTSDr_Int:
4453   case X86::VSQRTSDm:
4454   case X86::VSQRTSDm_Int:
4455   // AVX-512
4456   case X86::VCVTSD2SSZrr:
4457   case X86::VCVTSD2SSZrr_Int:
4458   case X86::VCVTSD2SSZrrb_Int:
4459   case X86::VCVTSD2SSZrm:
4460   case X86::VCVTSD2SSZrm_Int:
4461   case X86::VCVTSS2SDZrr:
4462   case X86::VCVTSS2SDZrr_Int:
4463   case X86::VCVTSS2SDZrrb_Int:
4464   case X86::VCVTSS2SDZrm:
4465   case X86::VCVTSS2SDZrm_Int:
4466   case X86::VGETEXPSDZr:
4467   case X86::VGETEXPSDZrb:
4468   case X86::VGETEXPSDZm:
4469   case X86::VGETEXPSSZr:
4470   case X86::VGETEXPSSZrb:
4471   case X86::VGETEXPSSZm:
4472   case X86::VGETMANTSDZrri:
4473   case X86::VGETMANTSDZrrib:
4474   case X86::VGETMANTSDZrmi:
4475   case X86::VGETMANTSSZrri:
4476   case X86::VGETMANTSSZrrib:
4477   case X86::VGETMANTSSZrmi:
4478   case X86::VRNDSCALESDZr:
4479   case X86::VRNDSCALESDZr_Int:
4480   case X86::VRNDSCALESDZrb_Int:
4481   case X86::VRNDSCALESDZm:
4482   case X86::VRNDSCALESDZm_Int:
4483   case X86::VRNDSCALESSZr:
4484   case X86::VRNDSCALESSZr_Int:
4485   case X86::VRNDSCALESSZrb_Int:
4486   case X86::VRNDSCALESSZm:
4487   case X86::VRNDSCALESSZm_Int:
4488   case X86::VRCP14SDZrr:
4489   case X86::VRCP14SDZrm:
4490   case X86::VRCP14SSZrr:
4491   case X86::VRCP14SSZrm:
4492   case X86::VRCP28SDZr:
4493   case X86::VRCP28SDZrb:
4494   case X86::VRCP28SDZm:
4495   case X86::VRCP28SSZr:
4496   case X86::VRCP28SSZrb:
4497   case X86::VRCP28SSZm:
4498   case X86::VREDUCESSZrmi:
4499   case X86::VREDUCESSZrri:
4500   case X86::VREDUCESSZrrib:
4501   case X86::VRSQRT14SDZrr:
4502   case X86::VRSQRT14SDZrm:
4503   case X86::VRSQRT14SSZrr:
4504   case X86::VRSQRT14SSZrm:
4505   case X86::VRSQRT28SDZr:
4506   case X86::VRSQRT28SDZrb:
4507   case X86::VRSQRT28SDZm:
4508   case X86::VRSQRT28SSZr:
4509   case X86::VRSQRT28SSZrb:
4510   case X86::VRSQRT28SSZm:
4511   case X86::VSQRTSSZr:
4512   case X86::VSQRTSSZr_Int:
4513   case X86::VSQRTSSZrb_Int:
4514   case X86::VSQRTSSZm:
4515   case X86::VSQRTSSZm_Int:
4516   case X86::VSQRTSDZr:
4517   case X86::VSQRTSDZr_Int:
4518   case X86::VSQRTSDZrb_Int:
4519   case X86::VSQRTSDZm:
4520   case X86::VSQRTSDZm_Int:
4521     return true;
4522   case X86::VMOVSSZrrk:
4523   case X86::VMOVSDZrrk:
4524     OpNum = 3;
4525     return true;
4526   case X86::VMOVSSZrrkz:
4527   case X86::VMOVSDZrrkz:
4528     OpNum = 2;
4529     return true;
4530   }
4531 
4532   return false;
4533 }
4534 
4535 /// Inform the BreakFalseDeps pass how many idle instructions we would like
4536 /// before certain undef register reads.
4537 ///
4538 /// This catches the VCVTSI2SD family of instructions:
4539 ///
4540 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
4541 ///
4542 /// We should to be careful *not* to catch VXOR idioms which are presumably
4543 /// handled specially in the pipeline:
4544 ///
4545 /// vxorps undef %xmm1, undef %xmm1, %xmm1
4546 ///
4547 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4548 /// high bits that are passed-through are not live.
4549 unsigned
4550 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
4551                                    const TargetRegisterInfo *TRI) const {
4552   if (!hasUndefRegUpdate(MI.getOpcode(), OpNum))
4553     return 0;
4554 
4555   const MachineOperand &MO = MI.getOperand(OpNum);
4556   if (MO.isUndef() && Register::isPhysicalRegister(MO.getReg())) {
4557     return UndefRegClearance;
4558   }
4559   return 0;
4560 }
4561 
4562 void X86InstrInfo::breakPartialRegDependency(
4563     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4564   Register Reg = MI.getOperand(OpNum).getReg();
4565   // If MI kills this register, the false dependence is already broken.
4566   if (MI.killsRegister(Reg, TRI))
4567     return;
4568 
4569   if (X86::VR128RegClass.contains(Reg)) {
4570     // These instructions are all floating point domain, so xorps is the best
4571     // choice.
4572     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
4573     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4574         .addReg(Reg, RegState::Undef)
4575         .addReg(Reg, RegState::Undef);
4576     MI.addRegisterKilled(Reg, TRI, true);
4577   } else if (X86::VR256RegClass.contains(Reg)) {
4578     // Use vxorps to clear the full ymm register.
4579     // It wants to read and write the xmm sub-register.
4580     Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4581     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4582         .addReg(XReg, RegState::Undef)
4583         .addReg(XReg, RegState::Undef)
4584         .addReg(Reg, RegState::ImplicitDefine);
4585     MI.addRegisterKilled(Reg, TRI, true);
4586   } else if (X86::GR64RegClass.contains(Reg)) {
4587     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
4588     // as well.
4589     Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
4590     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4591         .addReg(XReg, RegState::Undef)
4592         .addReg(XReg, RegState::Undef)
4593         .addReg(Reg, RegState::ImplicitDefine);
4594     MI.addRegisterKilled(Reg, TRI, true);
4595   } else if (X86::GR32RegClass.contains(Reg)) {
4596     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
4597         .addReg(Reg, RegState::Undef)
4598         .addReg(Reg, RegState::Undef);
4599     MI.addRegisterKilled(Reg, TRI, true);
4600   }
4601 }
4602 
4603 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
4604                         int PtrOffset = 0) {
4605   unsigned NumAddrOps = MOs.size();
4606 
4607   if (NumAddrOps < 4) {
4608     // FrameIndex only - add an immediate offset (whether its zero or not).
4609     for (unsigned i = 0; i != NumAddrOps; ++i)
4610       MIB.add(MOs[i]);
4611     addOffset(MIB, PtrOffset);
4612   } else {
4613     // General Memory Addressing - we need to add any offset to an existing
4614     // offset.
4615     assert(MOs.size() == 5 && "Unexpected memory operand list length");
4616     for (unsigned i = 0; i != NumAddrOps; ++i) {
4617       const MachineOperand &MO = MOs[i];
4618       if (i == 3 && PtrOffset != 0) {
4619         MIB.addDisp(MO, PtrOffset);
4620       } else {
4621         MIB.add(MO);
4622       }
4623     }
4624   }
4625 }
4626 
4627 static void updateOperandRegConstraints(MachineFunction &MF,
4628                                         MachineInstr &NewMI,
4629                                         const TargetInstrInfo &TII) {
4630   MachineRegisterInfo &MRI = MF.getRegInfo();
4631   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
4632 
4633   for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
4634     MachineOperand &MO = NewMI.getOperand(Idx);
4635     // We only need to update constraints on virtual register operands.
4636     if (!MO.isReg())
4637       continue;
4638     Register Reg = MO.getReg();
4639     if (!Register::isVirtualRegister(Reg))
4640       continue;
4641 
4642     auto *NewRC = MRI.constrainRegClass(
4643         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
4644     if (!NewRC) {
4645       LLVM_DEBUG(
4646           dbgs() << "WARNING: Unable to update register constraint for operand "
4647                  << Idx << " of instruction:\n";
4648           NewMI.dump(); dbgs() << "\n");
4649     }
4650   }
4651 }
4652 
4653 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4654                                      ArrayRef<MachineOperand> MOs,
4655                                      MachineBasicBlock::iterator InsertPt,
4656                                      MachineInstr &MI,
4657                                      const TargetInstrInfo &TII) {
4658   // Create the base instruction with the memory operand as the first part.
4659   // Omit the implicit operands, something BuildMI can't do.
4660   MachineInstr *NewMI =
4661       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4662   MachineInstrBuilder MIB(MF, NewMI);
4663   addOperands(MIB, MOs);
4664 
4665   // Loop over the rest of the ri operands, converting them over.
4666   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
4667   for (unsigned i = 0; i != NumOps; ++i) {
4668     MachineOperand &MO = MI.getOperand(i + 2);
4669     MIB.add(MO);
4670   }
4671   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
4672     MachineOperand &MO = MI.getOperand(i);
4673     MIB.add(MO);
4674   }
4675 
4676   updateOperandRegConstraints(MF, *NewMI, TII);
4677 
4678   MachineBasicBlock *MBB = InsertPt->getParent();
4679   MBB->insert(InsertPt, NewMI);
4680 
4681   return MIB;
4682 }
4683 
4684 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4685                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
4686                               MachineBasicBlock::iterator InsertPt,
4687                               MachineInstr &MI, const TargetInstrInfo &TII,
4688                               int PtrOffset = 0) {
4689   // Omit the implicit operands, something BuildMI can't do.
4690   MachineInstr *NewMI =
4691       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4692   MachineInstrBuilder MIB(MF, NewMI);
4693 
4694   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4695     MachineOperand &MO = MI.getOperand(i);
4696     if (i == OpNo) {
4697       assert(MO.isReg() && "Expected to fold into reg operand!");
4698       addOperands(MIB, MOs, PtrOffset);
4699     } else {
4700       MIB.add(MO);
4701     }
4702   }
4703 
4704   updateOperandRegConstraints(MF, *NewMI, TII);
4705 
4706   MachineBasicBlock *MBB = InsertPt->getParent();
4707   MBB->insert(InsertPt, NewMI);
4708 
4709   return MIB;
4710 }
4711 
4712 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4713                                 ArrayRef<MachineOperand> MOs,
4714                                 MachineBasicBlock::iterator InsertPt,
4715                                 MachineInstr &MI) {
4716   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4717                                     MI.getDebugLoc(), TII.get(Opcode));
4718   addOperands(MIB, MOs);
4719   return MIB.addImm(0);
4720 }
4721 
4722 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
4723     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4724     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4725     unsigned Size, unsigned Align) const {
4726   switch (MI.getOpcode()) {
4727   case X86::INSERTPSrr:
4728   case X86::VINSERTPSrr:
4729   case X86::VINSERTPSZrr:
4730     // Attempt to convert the load of inserted vector into a fold load
4731     // of a single float.
4732     if (OpNum == 2) {
4733       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
4734       unsigned ZMask = Imm & 15;
4735       unsigned DstIdx = (Imm >> 4) & 3;
4736       unsigned SrcIdx = (Imm >> 6) & 3;
4737 
4738       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4739       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4740       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4741       if ((Size == 0 || Size >= 16) && RCSize >= 16 && 4 <= Align) {
4742         int PtrOffset = SrcIdx * 4;
4743         unsigned NewImm = (DstIdx << 4) | ZMask;
4744         unsigned NewOpCode =
4745             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
4746             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
4747                                                     X86::INSERTPSrm;
4748         MachineInstr *NewMI =
4749             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
4750         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
4751         return NewMI;
4752       }
4753     }
4754     break;
4755   case X86::MOVHLPSrr:
4756   case X86::VMOVHLPSrr:
4757   case X86::VMOVHLPSZrr:
4758     // Move the upper 64-bits of the second operand to the lower 64-bits.
4759     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
4760     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
4761     if (OpNum == 2) {
4762       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4763       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4764       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4765       if ((Size == 0 || Size >= 16) && RCSize >= 16 && 8 <= Align) {
4766         unsigned NewOpCode =
4767             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
4768             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
4769                                                    X86::MOVLPSrm;
4770         MachineInstr *NewMI =
4771             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
4772         return NewMI;
4773       }
4774     }
4775     break;
4776   case X86::UNPCKLPDrr:
4777     // If we won't be able to fold this to the memory form of UNPCKL, use
4778     // MOVHPD instead. Done as custom because we can't have this in the load
4779     // table twice.
4780     if (OpNum == 2) {
4781       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4782       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4783       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4784       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Align < 16) {
4785         MachineInstr *NewMI =
4786             FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
4787         return NewMI;
4788       }
4789     }
4790     break;
4791   }
4792 
4793   return nullptr;
4794 }
4795 
4796 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
4797                                                MachineInstr &MI) {
4798   unsigned Ignored;
4799   if (!hasUndefRegUpdate(MI.getOpcode(), Ignored, /*ForLoadFold*/true) ||
4800       !MI.getOperand(1).isReg())
4801     return false;
4802 
4803   // The are two cases we need to handle depending on where in the pipeline
4804   // the folding attempt is being made.
4805   // -Register has the undef flag set.
4806   // -Register is produced by the IMPLICIT_DEF instruction.
4807 
4808   if (MI.getOperand(1).isUndef())
4809     return true;
4810 
4811   MachineRegisterInfo &RegInfo = MF.getRegInfo();
4812   MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
4813   return VRegDef && VRegDef->isImplicitDef();
4814 }
4815 
4816 
4817 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
4818     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4819     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4820     unsigned Size, unsigned Align, bool AllowCommute) const {
4821   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
4822   bool isTwoAddrFold = false;
4823 
4824   // For CPUs that favor the register form of a call or push,
4825   // do not fold loads into calls or pushes, unless optimizing for size
4826   // aggressively.
4827   if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
4828       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
4829        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
4830        MI.getOpcode() == X86::PUSH64r))
4831     return nullptr;
4832 
4833   // Avoid partial and undef register update stalls unless optimizing for size.
4834   if (!MF.getFunction().hasOptSize() &&
4835       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4836        shouldPreventUndefRegUpdateMemFold(MF, MI)))
4837     return nullptr;
4838 
4839   unsigned NumOps = MI.getDesc().getNumOperands();
4840   bool isTwoAddr =
4841       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4842 
4843   // FIXME: AsmPrinter doesn't know how to handle
4844   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4845   if (MI.getOpcode() == X86::ADD32ri &&
4846       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4847     return nullptr;
4848 
4849   // GOTTPOFF relocation loads can only be folded into add instructions.
4850   // FIXME: Need to exclude other relocations that only support specific
4851   // instructions.
4852   if (MOs.size() == X86::AddrNumOperands &&
4853       MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
4854       MI.getOpcode() != X86::ADD64rr)
4855     return nullptr;
4856 
4857   MachineInstr *NewMI = nullptr;
4858 
4859   // Attempt to fold any custom cases we have.
4860   if (MachineInstr *CustomMI =
4861           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
4862     return CustomMI;
4863 
4864   const X86MemoryFoldTableEntry *I = nullptr;
4865 
4866   // Folding a memory location into the two-address part of a two-address
4867   // instruction is different than folding it other places.  It requires
4868   // replacing the *two* registers with the memory location.
4869   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
4870       MI.getOperand(1).isReg() &&
4871       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4872     I = lookupTwoAddrFoldTable(MI.getOpcode());
4873     isTwoAddrFold = true;
4874   } else {
4875     if (OpNum == 0) {
4876       if (MI.getOpcode() == X86::MOV32r0) {
4877         NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
4878         if (NewMI)
4879           return NewMI;
4880       }
4881     }
4882 
4883     I = lookupFoldTable(MI.getOpcode(), OpNum);
4884   }
4885 
4886   if (I != nullptr) {
4887     unsigned Opcode = I->DstOp;
4888     unsigned MinAlign = (I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4889     MinAlign = MinAlign ? 1 << (MinAlign - 1) : 0;
4890     if (Align < MinAlign)
4891       return nullptr;
4892     bool NarrowToMOV32rm = false;
4893     if (Size) {
4894       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4895       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
4896                                                   &RI, MF);
4897       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4898       if (Size < RCSize) {
4899         // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
4900         // Check if it's safe to fold the load. If the size of the object is
4901         // narrower than the load width, then it's not.
4902         if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4903           return nullptr;
4904         // If this is a 64-bit load, but the spill slot is 32, then we can do
4905         // a 32-bit load which is implicitly zero-extended. This likely is
4906         // due to live interval analysis remat'ing a load from stack slot.
4907         if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4908           return nullptr;
4909         Opcode = X86::MOV32rm;
4910         NarrowToMOV32rm = true;
4911       }
4912     }
4913 
4914     if (isTwoAddrFold)
4915       NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
4916     else
4917       NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
4918 
4919     if (NarrowToMOV32rm) {
4920       // If this is the special case where we use a MOV32rm to load a 32-bit
4921       // value and zero-extend the top bits. Change the destination register
4922       // to a 32-bit one.
4923       Register DstReg = NewMI->getOperand(0).getReg();
4924       if (Register::isPhysicalRegister(DstReg))
4925         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4926       else
4927         NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4928     }
4929     return NewMI;
4930   }
4931 
4932   // If the instruction and target operand are commutable, commute the
4933   // instruction and try again.
4934   if (AllowCommute) {
4935     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
4936     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4937       bool HasDef = MI.getDesc().getNumDefs();
4938       Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
4939       Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4940       Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
4941       bool Tied1 =
4942           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4943       bool Tied2 =
4944           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4945 
4946       // If either of the commutable operands are tied to the destination
4947       // then we can not commute + fold.
4948       if ((HasDef && Reg0 == Reg1 && Tied1) ||
4949           (HasDef && Reg0 == Reg2 && Tied2))
4950         return nullptr;
4951 
4952       MachineInstr *CommutedMI =
4953           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4954       if (!CommutedMI) {
4955         // Unable to commute.
4956         return nullptr;
4957       }
4958       if (CommutedMI != &MI) {
4959         // New instruction. We can't fold from this.
4960         CommutedMI->eraseFromParent();
4961         return nullptr;
4962       }
4963 
4964       // Attempt to fold with the commuted version of the instruction.
4965       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
4966                                     Size, Align, /*AllowCommute=*/false);
4967       if (NewMI)
4968         return NewMI;
4969 
4970       // Folding failed again - undo the commute before returning.
4971       MachineInstr *UncommutedMI =
4972           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4973       if (!UncommutedMI) {
4974         // Unable to commute.
4975         return nullptr;
4976       }
4977       if (UncommutedMI != &MI) {
4978         // New instruction. It doesn't need to be kept.
4979         UncommutedMI->eraseFromParent();
4980         return nullptr;
4981       }
4982 
4983       // Return here to prevent duplicate fuse failure report.
4984       return nullptr;
4985     }
4986   }
4987 
4988   // No fusion
4989   if (PrintFailedFusing && !MI.isCopy())
4990     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
4991   return nullptr;
4992 }
4993 
4994 MachineInstr *
4995 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
4996                                     ArrayRef<unsigned> Ops,
4997                                     MachineBasicBlock::iterator InsertPt,
4998                                     int FrameIndex, LiveIntervals *LIS,
4999                                     VirtRegMap *VRM) const {
5000   // Check switch flag
5001   if (NoFusing)
5002     return nullptr;
5003 
5004   // Avoid partial and undef register update stalls unless optimizing for size.
5005   if (!MF.getFunction().hasOptSize() &&
5006       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5007        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5008     return nullptr;
5009 
5010   // Don't fold subreg spills, or reloads that use a high subreg.
5011   for (auto Op : Ops) {
5012     MachineOperand &MO = MI.getOperand(Op);
5013     auto SubReg = MO.getSubReg();
5014     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
5015       return nullptr;
5016   }
5017 
5018   const MachineFrameInfo &MFI = MF.getFrameInfo();
5019   unsigned Size = MFI.getObjectSize(FrameIndex);
5020   unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
5021   // If the function stack isn't realigned we don't want to fold instructions
5022   // that need increased alignment.
5023   if (!RI.needsStackRealignment(MF))
5024     Alignment =
5025         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
5026   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5027     unsigned NewOpc = 0;
5028     unsigned RCSize = 0;
5029     switch (MI.getOpcode()) {
5030     default: return nullptr;
5031     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5032     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5033     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5034     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5035     }
5036     // Check if it's safe to fold the load. If the size of the object is
5037     // narrower than the load width, then it's not.
5038     if (Size < RCSize)
5039       return nullptr;
5040     // Change to CMPXXri r, 0 first.
5041     MI.setDesc(get(NewOpc));
5042     MI.getOperand(1).ChangeToImmediate(0);
5043   } else if (Ops.size() != 1)
5044     return nullptr;
5045 
5046   return foldMemoryOperandImpl(MF, MI, Ops[0],
5047                                MachineOperand::CreateFI(FrameIndex), InsertPt,
5048                                Size, Alignment, /*AllowCommute=*/true);
5049 }
5050 
5051 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5052 /// because the latter uses contents that wouldn't be defined in the folded
5053 /// version.  For instance, this transformation isn't legal:
5054 ///   movss (%rdi), %xmm0
5055 ///   addps %xmm0, %xmm0
5056 /// ->
5057 ///   addps (%rdi), %xmm0
5058 ///
5059 /// But this one is:
5060 ///   movss (%rdi), %xmm0
5061 ///   addss %xmm0, %xmm0
5062 /// ->
5063 ///   addss (%rdi), %xmm0
5064 ///
5065 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5066                                              const MachineInstr &UserMI,
5067                                              const MachineFunction &MF) {
5068   unsigned Opc = LoadMI.getOpcode();
5069   unsigned UserOpc = UserMI.getOpcode();
5070   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5071   const TargetRegisterClass *RC =
5072       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5073   unsigned RegSize = TRI.getRegSizeInBits(*RC);
5074 
5075   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
5076        Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
5077        Opc == X86::VMOVSSZrm_alt) &&
5078       RegSize > 32) {
5079     // These instructions only load 32 bits, we can't fold them if the
5080     // destination register is wider than 32 bits (4 bytes), and its user
5081     // instruction isn't scalar (SS).
5082     switch (UserOpc) {
5083     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5084     case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5085     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5086     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5087     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5088     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5089     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5090     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5091     case X86::VCMPSSZrr_Intk:
5092     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5093     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5094     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5095     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5096     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5097     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
5098     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
5099     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
5100     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
5101     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
5102     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
5103     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
5104     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
5105     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5106     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5107     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5108     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5109     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5110     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5111     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5112     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5113     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5114     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5115     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5116     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5117     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5118     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5119     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5120     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5121     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5122     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5123       return false;
5124     default:
5125       return true;
5126     }
5127   }
5128 
5129   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
5130        Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
5131        Opc == X86::VMOVSDZrm_alt) &&
5132       RegSize > 64) {
5133     // These instructions only load 64 bits, we can't fold them if the
5134     // destination register is wider than 64 bits (8 bytes), and its user
5135     // instruction isn't scalar (SD).
5136     switch (UserOpc) {
5137     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5138     case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5139     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5140     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
5141     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
5142     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
5143     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5144     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5145     case X86::VCMPSDZrr_Intk:
5146     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5147     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5148     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5149     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5150     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5151     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
5152     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
5153     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
5154     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
5155     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
5156     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
5157     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
5158     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
5159     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5160     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5161     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5162     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5163     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5164     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5165     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5166     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5167     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5168     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5169     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5170     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5171     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5172     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5173     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5174     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5175     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5176     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5177       return false;
5178     default:
5179       return true;
5180     }
5181   }
5182 
5183   return false;
5184 }
5185 
5186 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5187     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
5188     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5189     LiveIntervals *LIS) const {
5190 
5191   // TODO: Support the case where LoadMI loads a wide register, but MI
5192   // only uses a subreg.
5193   for (auto Op : Ops) {
5194     if (MI.getOperand(Op).getSubReg())
5195       return nullptr;
5196   }
5197 
5198   // If loading from a FrameIndex, fold directly from the FrameIndex.
5199   unsigned NumOps = LoadMI.getDesc().getNumOperands();
5200   int FrameIndex;
5201   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5202     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5203       return nullptr;
5204     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5205   }
5206 
5207   // Check switch flag
5208   if (NoFusing) return nullptr;
5209 
5210   // Avoid partial and undef register update stalls unless optimizing for size.
5211   if (!MF.getFunction().hasOptSize() &&
5212       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5213        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5214     return nullptr;
5215 
5216   // Determine the alignment of the load.
5217   unsigned Alignment = 0;
5218   if (LoadMI.hasOneMemOperand())
5219     Alignment = (*LoadMI.memoperands_begin())->getAlignment();
5220   else
5221     switch (LoadMI.getOpcode()) {
5222     case X86::AVX512_512_SET0:
5223     case X86::AVX512_512_SETALLONES:
5224       Alignment = 64;
5225       break;
5226     case X86::AVX2_SETALLONES:
5227     case X86::AVX1_SETALLONES:
5228     case X86::AVX_SET0:
5229     case X86::AVX512_256_SET0:
5230       Alignment = 32;
5231       break;
5232     case X86::V_SET0:
5233     case X86::V_SETALLONES:
5234     case X86::AVX512_128_SET0:
5235     case X86::FsFLD0F128:
5236     case X86::AVX512_FsFLD0F128:
5237       Alignment = 16;
5238       break;
5239     case X86::MMX_SET0:
5240     case X86::FsFLD0SD:
5241     case X86::AVX512_FsFLD0SD:
5242       Alignment = 8;
5243       break;
5244     case X86::FsFLD0SS:
5245     case X86::AVX512_FsFLD0SS:
5246       Alignment = 4;
5247       break;
5248     default:
5249       return nullptr;
5250     }
5251   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5252     unsigned NewOpc = 0;
5253     switch (MI.getOpcode()) {
5254     default: return nullptr;
5255     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
5256     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5257     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5258     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5259     }
5260     // Change to CMPXXri r, 0 first.
5261     MI.setDesc(get(NewOpc));
5262     MI.getOperand(1).ChangeToImmediate(0);
5263   } else if (Ops.size() != 1)
5264     return nullptr;
5265 
5266   // Make sure the subregisters match.
5267   // Otherwise we risk changing the size of the load.
5268   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5269     return nullptr;
5270 
5271   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5272   switch (LoadMI.getOpcode()) {
5273   case X86::MMX_SET0:
5274   case X86::V_SET0:
5275   case X86::V_SETALLONES:
5276   case X86::AVX2_SETALLONES:
5277   case X86::AVX1_SETALLONES:
5278   case X86::AVX_SET0:
5279   case X86::AVX512_128_SET0:
5280   case X86::AVX512_256_SET0:
5281   case X86::AVX512_512_SET0:
5282   case X86::AVX512_512_SETALLONES:
5283   case X86::FsFLD0SD:
5284   case X86::AVX512_FsFLD0SD:
5285   case X86::FsFLD0SS:
5286   case X86::AVX512_FsFLD0SS:
5287   case X86::FsFLD0F128:
5288   case X86::AVX512_FsFLD0F128: {
5289     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5290     // Create a constant-pool entry and operands to load from it.
5291 
5292     // Medium and large mode can't fold loads this way.
5293     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5294         MF.getTarget().getCodeModel() != CodeModel::Kernel)
5295       return nullptr;
5296 
5297     // x86-32 PIC requires a PIC base register for constant pools.
5298     unsigned PICBase = 0;
5299     if (MF.getTarget().isPositionIndependent()) {
5300       if (Subtarget.is64Bit())
5301         PICBase = X86::RIP;
5302       else
5303         // FIXME: PICBase = getGlobalBaseReg(&MF);
5304         // This doesn't work for several reasons.
5305         // 1. GlobalBaseReg may have been spilled.
5306         // 2. It may not be live at MI.
5307         return nullptr;
5308     }
5309 
5310     // Create a constant-pool entry.
5311     MachineConstantPool &MCP = *MF.getConstantPool();
5312     Type *Ty;
5313     unsigned Opc = LoadMI.getOpcode();
5314     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
5315       Ty = Type::getFloatTy(MF.getFunction().getContext());
5316     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
5317       Ty = Type::getDoubleTy(MF.getFunction().getContext());
5318     else if (Opc == X86::FsFLD0F128 || Opc == X86::AVX512_FsFLD0F128)
5319       Ty = Type::getFP128Ty(MF.getFunction().getContext());
5320     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
5321       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),16);
5322     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
5323              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
5324       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 8);
5325     else if (Opc == X86::MMX_SET0)
5326       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 2);
5327     else
5328       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 4);
5329 
5330     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
5331                       Opc == X86::AVX512_512_SETALLONES ||
5332                       Opc == X86::AVX1_SETALLONES);
5333     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5334                                     Constant::getNullValue(Ty);
5335     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5336 
5337     // Create operands to load from the constant pool entry.
5338     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5339     MOs.push_back(MachineOperand::CreateImm(1));
5340     MOs.push_back(MachineOperand::CreateReg(0, false));
5341     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5342     MOs.push_back(MachineOperand::CreateReg(0, false));
5343     break;
5344   }
5345   default: {
5346     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5347       return nullptr;
5348 
5349     // Folding a normal load. Just copy the load's address operands.
5350     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
5351                LoadMI.operands_begin() + NumOps);
5352     break;
5353   }
5354   }
5355   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5356                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
5357 }
5358 
5359 static SmallVector<MachineMemOperand *, 2>
5360 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5361   SmallVector<MachineMemOperand *, 2> LoadMMOs;
5362 
5363   for (MachineMemOperand *MMO : MMOs) {
5364     if (!MMO->isLoad())
5365       continue;
5366 
5367     if (!MMO->isStore()) {
5368       // Reuse the MMO.
5369       LoadMMOs.push_back(MMO);
5370     } else {
5371       // Clone the MMO and unset the store flag.
5372       LoadMMOs.push_back(MF.getMachineMemOperand(
5373           MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
5374     }
5375   }
5376 
5377   return LoadMMOs;
5378 }
5379 
5380 static SmallVector<MachineMemOperand *, 2>
5381 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5382   SmallVector<MachineMemOperand *, 2> StoreMMOs;
5383 
5384   for (MachineMemOperand *MMO : MMOs) {
5385     if (!MMO->isStore())
5386       continue;
5387 
5388     if (!MMO->isLoad()) {
5389       // Reuse the MMO.
5390       StoreMMOs.push_back(MMO);
5391     } else {
5392       // Clone the MMO and unset the load flag.
5393       StoreMMOs.push_back(MF.getMachineMemOperand(
5394           MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
5395     }
5396   }
5397 
5398   return StoreMMOs;
5399 }
5400 
5401 static unsigned getBroadcastOpcode(const X86MemoryFoldTableEntry *I,
5402                                    const TargetRegisterClass *RC,
5403                                    const X86Subtarget &STI) {
5404   assert(STI.hasAVX512() && "Expected at least AVX512!");
5405   unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
5406   assert((SpillSize == 64 || STI.hasVLX()) &&
5407          "Can't broadcast less than 64 bytes without AVX512VL!");
5408 
5409   switch (I->Flags & TB_BCAST_MASK) {
5410   default: llvm_unreachable("Unexpected broadcast type!");
5411   case TB_BCAST_D:
5412     switch (SpillSize) {
5413     default: llvm_unreachable("Unknown spill size");
5414     case 16: return X86::VPBROADCASTDZ128m;
5415     case 32: return X86::VPBROADCASTDZ256m;
5416     case 64: return X86::VPBROADCASTDZm;
5417     }
5418     break;
5419   case TB_BCAST_Q:
5420     switch (SpillSize) {
5421     default: llvm_unreachable("Unknown spill size");
5422     case 16: return X86::VPBROADCASTQZ128m;
5423     case 32: return X86::VPBROADCASTQZ256m;
5424     case 64: return X86::VPBROADCASTQZm;
5425     }
5426     break;
5427   case TB_BCAST_SS:
5428     switch (SpillSize) {
5429     default: llvm_unreachable("Unknown spill size");
5430     case 16: return X86::VBROADCASTSSZ128m;
5431     case 32: return X86::VBROADCASTSSZ256m;
5432     case 64: return X86::VBROADCASTSSZm;
5433     }
5434     break;
5435   case TB_BCAST_SD:
5436     switch (SpillSize) {
5437     default: llvm_unreachable("Unknown spill size");
5438     case 16: return X86::VMOVDDUPZ128rm;
5439     case 32: return X86::VBROADCASTSDZ256m;
5440     case 64: return X86::VBROADCASTSDZm;
5441     }
5442     break;
5443   }
5444 }
5445 
5446 bool X86InstrInfo::unfoldMemoryOperand(
5447     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
5448     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
5449   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
5450   if (I == nullptr)
5451     return false;
5452   unsigned Opc = I->DstOp;
5453   unsigned Index = I->Flags & TB_INDEX_MASK;
5454   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5455   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5456   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
5457   if (UnfoldLoad && !FoldedLoad)
5458     return false;
5459   UnfoldLoad &= FoldedLoad;
5460   if (UnfoldStore && !FoldedStore)
5461     return false;
5462   UnfoldStore &= FoldedStore;
5463 
5464   const MCInstrDesc &MCID = get(Opc);
5465 
5466   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5467   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5468   // TODO: Check if 32-byte or greater accesses are slow too?
5469   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
5470       Subtarget.isUnalignedMem16Slow())
5471     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5472     // conservatively assume the address is unaligned. That's bad for
5473     // performance.
5474     return false;
5475   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5476   SmallVector<MachineOperand,2> BeforeOps;
5477   SmallVector<MachineOperand,2> AfterOps;
5478   SmallVector<MachineOperand,4> ImpOps;
5479   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5480     MachineOperand &Op = MI.getOperand(i);
5481     if (i >= Index && i < Index + X86::AddrNumOperands)
5482       AddrOps.push_back(Op);
5483     else if (Op.isReg() && Op.isImplicit())
5484       ImpOps.push_back(Op);
5485     else if (i < Index)
5486       BeforeOps.push_back(Op);
5487     else if (i > Index)
5488       AfterOps.push_back(Op);
5489   }
5490 
5491   // Emit the load or broadcast instruction.
5492   if (UnfoldLoad) {
5493     auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
5494 
5495     unsigned Opc;
5496     if (FoldedBCast) {
5497       Opc = getBroadcastOpcode(I, RC, Subtarget);
5498     } else {
5499       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5500       bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5501       Opc = getLoadRegOpcode(Reg, RC, isAligned, Subtarget);
5502     }
5503 
5504     DebugLoc DL;
5505     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
5506     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
5507       MIB.add(AddrOps[i]);
5508     MIB.setMemRefs(MMOs);
5509     NewMIs.push_back(MIB);
5510 
5511     if (UnfoldStore) {
5512       // Address operands cannot be marked isKill.
5513       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5514         MachineOperand &MO = NewMIs[0]->getOperand(i);
5515         if (MO.isReg())
5516           MO.setIsKill(false);
5517       }
5518     }
5519   }
5520 
5521   // Emit the data processing instruction.
5522   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
5523   MachineInstrBuilder MIB(MF, DataMI);
5524 
5525   if (FoldedStore)
5526     MIB.addReg(Reg, RegState::Define);
5527   for (MachineOperand &BeforeOp : BeforeOps)
5528     MIB.add(BeforeOp);
5529   if (FoldedLoad)
5530     MIB.addReg(Reg);
5531   for (MachineOperand &AfterOp : AfterOps)
5532     MIB.add(AfterOp);
5533   for (MachineOperand &ImpOp : ImpOps) {
5534     MIB.addReg(ImpOp.getReg(),
5535                getDefRegState(ImpOp.isDef()) |
5536                RegState::Implicit |
5537                getKillRegState(ImpOp.isKill()) |
5538                getDeadRegState(ImpOp.isDead()) |
5539                getUndefRegState(ImpOp.isUndef()));
5540   }
5541   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5542   switch (DataMI->getOpcode()) {
5543   default: break;
5544   case X86::CMP64ri32:
5545   case X86::CMP64ri8:
5546   case X86::CMP32ri:
5547   case X86::CMP32ri8:
5548   case X86::CMP16ri:
5549   case X86::CMP16ri8:
5550   case X86::CMP8ri: {
5551     MachineOperand &MO0 = DataMI->getOperand(0);
5552     MachineOperand &MO1 = DataMI->getOperand(1);
5553     if (MO1.getImm() == 0) {
5554       unsigned NewOpc;
5555       switch (DataMI->getOpcode()) {
5556       default: llvm_unreachable("Unreachable!");
5557       case X86::CMP64ri8:
5558       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5559       case X86::CMP32ri8:
5560       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
5561       case X86::CMP16ri8:
5562       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
5563       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
5564       }
5565       DataMI->setDesc(get(NewOpc));
5566       MO1.ChangeToRegister(MO0.getReg(), false);
5567     }
5568   }
5569   }
5570   NewMIs.push_back(DataMI);
5571 
5572   // Emit the store instruction.
5573   if (UnfoldStore) {
5574     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5575     auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
5576     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16);
5577     bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5578     unsigned Opc = getStoreRegOpcode(Reg, DstRC, isAligned, Subtarget);
5579     DebugLoc DL;
5580     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
5581     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
5582       MIB.add(AddrOps[i]);
5583     MIB.addReg(Reg, RegState::Kill);
5584     MIB.setMemRefs(MMOs);
5585     NewMIs.push_back(MIB);
5586   }
5587 
5588   return true;
5589 }
5590 
5591 bool
5592 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5593                                   SmallVectorImpl<SDNode*> &NewNodes) const {
5594   if (!N->isMachineOpcode())
5595     return false;
5596 
5597   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
5598   if (I == nullptr)
5599     return false;
5600   unsigned Opc = I->DstOp;
5601   unsigned Index = I->Flags & TB_INDEX_MASK;
5602   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5603   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5604   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
5605   const MCInstrDesc &MCID = get(Opc);
5606   MachineFunction &MF = DAG.getMachineFunction();
5607   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5608   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5609   unsigned NumDefs = MCID.NumDefs;
5610   std::vector<SDValue> AddrOps;
5611   std::vector<SDValue> BeforeOps;
5612   std::vector<SDValue> AfterOps;
5613   SDLoc dl(N);
5614   unsigned NumOps = N->getNumOperands();
5615   for (unsigned i = 0; i != NumOps-1; ++i) {
5616     SDValue Op = N->getOperand(i);
5617     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5618       AddrOps.push_back(Op);
5619     else if (i < Index-NumDefs)
5620       BeforeOps.push_back(Op);
5621     else if (i > Index-NumDefs)
5622       AfterOps.push_back(Op);
5623   }
5624   SDValue Chain = N->getOperand(NumOps-1);
5625   AddrOps.push_back(Chain);
5626 
5627   // Emit the load instruction.
5628   SDNode *Load = nullptr;
5629   if (FoldedLoad) {
5630     EVT VT = *TRI.legalclasstypes_begin(*RC);
5631     auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5632     if (MMOs.empty() && RC == &X86::VR128RegClass &&
5633         Subtarget.isUnalignedMem16Slow())
5634       // Do not introduce a slow unaligned load.
5635       return false;
5636     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5637     // memory access is slow above.
5638 
5639     unsigned Opc;
5640     if (FoldedBCast) {
5641       Opc = getBroadcastOpcode(I, RC, Subtarget);
5642     } else {
5643       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5644       bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5645       Opc = getLoadRegOpcode(0, RC, isAligned, Subtarget);
5646     }
5647 
5648     Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
5649     NewNodes.push_back(Load);
5650 
5651     // Preserve memory reference information.
5652     DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
5653   }
5654 
5655   // Emit the data processing instruction.
5656   std::vector<EVT> VTs;
5657   const TargetRegisterClass *DstRC = nullptr;
5658   if (MCID.getNumDefs() > 0) {
5659     DstRC = getRegClass(MCID, 0, &RI, MF);
5660     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
5661   }
5662   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5663     EVT VT = N->getValueType(i);
5664     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5665       VTs.push_back(VT);
5666   }
5667   if (Load)
5668     BeforeOps.push_back(SDValue(Load, 0));
5669   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
5670   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5671   switch (Opc) {
5672     default: break;
5673     case X86::CMP64ri32:
5674     case X86::CMP64ri8:
5675     case X86::CMP32ri:
5676     case X86::CMP32ri8:
5677     case X86::CMP16ri:
5678     case X86::CMP16ri8:
5679     case X86::CMP8ri:
5680       if (isNullConstant(BeforeOps[1])) {
5681         switch (Opc) {
5682           default: llvm_unreachable("Unreachable!");
5683           case X86::CMP64ri8:
5684           case X86::CMP64ri32: Opc = X86::TEST64rr; break;
5685           case X86::CMP32ri8:
5686           case X86::CMP32ri:   Opc = X86::TEST32rr; break;
5687           case X86::CMP16ri8:
5688           case X86::CMP16ri:   Opc = X86::TEST16rr; break;
5689           case X86::CMP8ri:    Opc = X86::TEST8rr; break;
5690         }
5691         BeforeOps[1] = BeforeOps[0];
5692       }
5693   }
5694   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5695   NewNodes.push_back(NewNode);
5696 
5697   // Emit the store instruction.
5698   if (FoldedStore) {
5699     AddrOps.pop_back();
5700     AddrOps.push_back(SDValue(NewNode, 0));
5701     AddrOps.push_back(Chain);
5702     auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5703     if (MMOs.empty() && RC == &X86::VR128RegClass &&
5704         Subtarget.isUnalignedMem16Slow())
5705       // Do not introduce a slow unaligned store.
5706       return false;
5707     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5708     // memory access is slow above.
5709     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5710     bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5711     SDNode *Store =
5712         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5713                            dl, MVT::Other, AddrOps);
5714     NewNodes.push_back(Store);
5715 
5716     // Preserve memory reference information.
5717     DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
5718   }
5719 
5720   return true;
5721 }
5722 
5723 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5724                                       bool UnfoldLoad, bool UnfoldStore,
5725                                       unsigned *LoadRegIndex) const {
5726   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
5727   if (I == nullptr)
5728     return 0;
5729   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5730   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5731   if (UnfoldLoad && !FoldedLoad)
5732     return 0;
5733   if (UnfoldStore && !FoldedStore)
5734     return 0;
5735   if (LoadRegIndex)
5736     *LoadRegIndex = I->Flags & TB_INDEX_MASK;
5737   return I->DstOp;
5738 }
5739 
5740 bool
5741 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5742                                      int64_t &Offset1, int64_t &Offset2) const {
5743   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5744     return false;
5745   unsigned Opc1 = Load1->getMachineOpcode();
5746   unsigned Opc2 = Load2->getMachineOpcode();
5747   switch (Opc1) {
5748   default: return false;
5749   case X86::MOV8rm:
5750   case X86::MOV16rm:
5751   case X86::MOV32rm:
5752   case X86::MOV64rm:
5753   case X86::LD_Fp32m:
5754   case X86::LD_Fp64m:
5755   case X86::LD_Fp80m:
5756   case X86::MOVSSrm:
5757   case X86::MOVSSrm_alt:
5758   case X86::MOVSDrm:
5759   case X86::MOVSDrm_alt:
5760   case X86::MMX_MOVD64rm:
5761   case X86::MMX_MOVQ64rm:
5762   case X86::MOVAPSrm:
5763   case X86::MOVUPSrm:
5764   case X86::MOVAPDrm:
5765   case X86::MOVUPDrm:
5766   case X86::MOVDQArm:
5767   case X86::MOVDQUrm:
5768   // AVX load instructions
5769   case X86::VMOVSSrm:
5770   case X86::VMOVSSrm_alt:
5771   case X86::VMOVSDrm:
5772   case X86::VMOVSDrm_alt:
5773   case X86::VMOVAPSrm:
5774   case X86::VMOVUPSrm:
5775   case X86::VMOVAPDrm:
5776   case X86::VMOVUPDrm:
5777   case X86::VMOVDQArm:
5778   case X86::VMOVDQUrm:
5779   case X86::VMOVAPSYrm:
5780   case X86::VMOVUPSYrm:
5781   case X86::VMOVAPDYrm:
5782   case X86::VMOVUPDYrm:
5783   case X86::VMOVDQAYrm:
5784   case X86::VMOVDQUYrm:
5785   // AVX512 load instructions
5786   case X86::VMOVSSZrm:
5787   case X86::VMOVSSZrm_alt:
5788   case X86::VMOVSDZrm:
5789   case X86::VMOVSDZrm_alt:
5790   case X86::VMOVAPSZ128rm:
5791   case X86::VMOVUPSZ128rm:
5792   case X86::VMOVAPSZ128rm_NOVLX:
5793   case X86::VMOVUPSZ128rm_NOVLX:
5794   case X86::VMOVAPDZ128rm:
5795   case X86::VMOVUPDZ128rm:
5796   case X86::VMOVDQU8Z128rm:
5797   case X86::VMOVDQU16Z128rm:
5798   case X86::VMOVDQA32Z128rm:
5799   case X86::VMOVDQU32Z128rm:
5800   case X86::VMOVDQA64Z128rm:
5801   case X86::VMOVDQU64Z128rm:
5802   case X86::VMOVAPSZ256rm:
5803   case X86::VMOVUPSZ256rm:
5804   case X86::VMOVAPSZ256rm_NOVLX:
5805   case X86::VMOVUPSZ256rm_NOVLX:
5806   case X86::VMOVAPDZ256rm:
5807   case X86::VMOVUPDZ256rm:
5808   case X86::VMOVDQU8Z256rm:
5809   case X86::VMOVDQU16Z256rm:
5810   case X86::VMOVDQA32Z256rm:
5811   case X86::VMOVDQU32Z256rm:
5812   case X86::VMOVDQA64Z256rm:
5813   case X86::VMOVDQU64Z256rm:
5814   case X86::VMOVAPSZrm:
5815   case X86::VMOVUPSZrm:
5816   case X86::VMOVAPDZrm:
5817   case X86::VMOVUPDZrm:
5818   case X86::VMOVDQU8Zrm:
5819   case X86::VMOVDQU16Zrm:
5820   case X86::VMOVDQA32Zrm:
5821   case X86::VMOVDQU32Zrm:
5822   case X86::VMOVDQA64Zrm:
5823   case X86::VMOVDQU64Zrm:
5824   case X86::KMOVBkm:
5825   case X86::KMOVWkm:
5826   case X86::KMOVDkm:
5827   case X86::KMOVQkm:
5828     break;
5829   }
5830   switch (Opc2) {
5831   default: return false;
5832   case X86::MOV8rm:
5833   case X86::MOV16rm:
5834   case X86::MOV32rm:
5835   case X86::MOV64rm:
5836   case X86::LD_Fp32m:
5837   case X86::LD_Fp64m:
5838   case X86::LD_Fp80m:
5839   case X86::MOVSSrm:
5840   case X86::MOVSSrm_alt:
5841   case X86::MOVSDrm:
5842   case X86::MOVSDrm_alt:
5843   case X86::MMX_MOVD64rm:
5844   case X86::MMX_MOVQ64rm:
5845   case X86::MOVAPSrm:
5846   case X86::MOVUPSrm:
5847   case X86::MOVAPDrm:
5848   case X86::MOVUPDrm:
5849   case X86::MOVDQArm:
5850   case X86::MOVDQUrm:
5851   // AVX load instructions
5852   case X86::VMOVSSrm:
5853   case X86::VMOVSSrm_alt:
5854   case X86::VMOVSDrm:
5855   case X86::VMOVSDrm_alt:
5856   case X86::VMOVAPSrm:
5857   case X86::VMOVUPSrm:
5858   case X86::VMOVAPDrm:
5859   case X86::VMOVUPDrm:
5860   case X86::VMOVDQArm:
5861   case X86::VMOVDQUrm:
5862   case X86::VMOVAPSYrm:
5863   case X86::VMOVUPSYrm:
5864   case X86::VMOVAPDYrm:
5865   case X86::VMOVUPDYrm:
5866   case X86::VMOVDQAYrm:
5867   case X86::VMOVDQUYrm:
5868   // AVX512 load instructions
5869   case X86::VMOVSSZrm:
5870   case X86::VMOVSSZrm_alt:
5871   case X86::VMOVSDZrm:
5872   case X86::VMOVSDZrm_alt:
5873   case X86::VMOVAPSZ128rm:
5874   case X86::VMOVUPSZ128rm:
5875   case X86::VMOVAPSZ128rm_NOVLX:
5876   case X86::VMOVUPSZ128rm_NOVLX:
5877   case X86::VMOVAPDZ128rm:
5878   case X86::VMOVUPDZ128rm:
5879   case X86::VMOVDQU8Z128rm:
5880   case X86::VMOVDQU16Z128rm:
5881   case X86::VMOVDQA32Z128rm:
5882   case X86::VMOVDQU32Z128rm:
5883   case X86::VMOVDQA64Z128rm:
5884   case X86::VMOVDQU64Z128rm:
5885   case X86::VMOVAPSZ256rm:
5886   case X86::VMOVUPSZ256rm:
5887   case X86::VMOVAPSZ256rm_NOVLX:
5888   case X86::VMOVUPSZ256rm_NOVLX:
5889   case X86::VMOVAPDZ256rm:
5890   case X86::VMOVUPDZ256rm:
5891   case X86::VMOVDQU8Z256rm:
5892   case X86::VMOVDQU16Z256rm:
5893   case X86::VMOVDQA32Z256rm:
5894   case X86::VMOVDQU32Z256rm:
5895   case X86::VMOVDQA64Z256rm:
5896   case X86::VMOVDQU64Z256rm:
5897   case X86::VMOVAPSZrm:
5898   case X86::VMOVUPSZrm:
5899   case X86::VMOVAPDZrm:
5900   case X86::VMOVUPDZrm:
5901   case X86::VMOVDQU8Zrm:
5902   case X86::VMOVDQU16Zrm:
5903   case X86::VMOVDQA32Zrm:
5904   case X86::VMOVDQU32Zrm:
5905   case X86::VMOVDQA64Zrm:
5906   case X86::VMOVDQU64Zrm:
5907   case X86::KMOVBkm:
5908   case X86::KMOVWkm:
5909   case X86::KMOVDkm:
5910   case X86::KMOVQkm:
5911     break;
5912   }
5913 
5914   // Lambda to check if both the loads have the same value for an operand index.
5915   auto HasSameOp = [&](int I) {
5916     return Load1->getOperand(I) == Load2->getOperand(I);
5917   };
5918 
5919   // All operands except the displacement should match.
5920   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
5921       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
5922     return false;
5923 
5924   // Chain Operand must be the same.
5925   if (!HasSameOp(5))
5926     return false;
5927 
5928   // Now let's examine if the displacements are constants.
5929   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
5930   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
5931   if (!Disp1 || !Disp2)
5932     return false;
5933 
5934   Offset1 = Disp1->getSExtValue();
5935   Offset2 = Disp2->getSExtValue();
5936   return true;
5937 }
5938 
5939 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5940                                            int64_t Offset1, int64_t Offset2,
5941                                            unsigned NumLoads) const {
5942   assert(Offset2 > Offset1);
5943   if ((Offset2 - Offset1) / 8 > 64)
5944     return false;
5945 
5946   unsigned Opc1 = Load1->getMachineOpcode();
5947   unsigned Opc2 = Load2->getMachineOpcode();
5948   if (Opc1 != Opc2)
5949     return false;  // FIXME: overly conservative?
5950 
5951   switch (Opc1) {
5952   default: break;
5953   case X86::LD_Fp32m:
5954   case X86::LD_Fp64m:
5955   case X86::LD_Fp80m:
5956   case X86::MMX_MOVD64rm:
5957   case X86::MMX_MOVQ64rm:
5958     return false;
5959   }
5960 
5961   EVT VT = Load1->getValueType(0);
5962   switch (VT.getSimpleVT().SimpleTy) {
5963   default:
5964     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5965     // have 16 of them to play with.
5966     if (Subtarget.is64Bit()) {
5967       if (NumLoads >= 3)
5968         return false;
5969     } else if (NumLoads) {
5970       return false;
5971     }
5972     break;
5973   case MVT::i8:
5974   case MVT::i16:
5975   case MVT::i32:
5976   case MVT::i64:
5977   case MVT::f32:
5978   case MVT::f64:
5979     if (NumLoads)
5980       return false;
5981     break;
5982   }
5983 
5984   return true;
5985 }
5986 
5987 bool X86InstrInfo::
5988 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5989   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5990   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5991   Cond[0].setImm(GetOppositeBranchCondition(CC));
5992   return false;
5993 }
5994 
5995 bool X86InstrInfo::
5996 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5997   // FIXME: Return false for x87 stack register classes for now. We can't
5998   // allow any loads of these registers before FpGet_ST0_80.
5999   return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
6000            RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
6001            RC == &X86::RFP80RegClass);
6002 }
6003 
6004 /// Return a virtual register initialized with the
6005 /// the global base register value. Output instructions required to
6006 /// initialize the register in the function entry block, if necessary.
6007 ///
6008 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6009 ///
6010 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6011   assert((!Subtarget.is64Bit() ||
6012           MF->getTarget().getCodeModel() == CodeModel::Medium ||
6013           MF->getTarget().getCodeModel() == CodeModel::Large) &&
6014          "X86-64 PIC uses RIP relative addressing");
6015 
6016   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6017   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6018   if (GlobalBaseReg != 0)
6019     return GlobalBaseReg;
6020 
6021   // Create the register. The code to initialize it is inserted
6022   // later, by the CGBR pass (below).
6023   MachineRegisterInfo &RegInfo = MF->getRegInfo();
6024   GlobalBaseReg = RegInfo.createVirtualRegister(
6025       Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
6026   X86FI->setGlobalBaseReg(GlobalBaseReg);
6027   return GlobalBaseReg;
6028 }
6029 
6030 // These are the replaceable SSE instructions. Some of these have Int variants
6031 // that we don't include here. We don't want to replace instructions selected
6032 // by intrinsics.
6033 static const uint16_t ReplaceableInstrs[][3] = {
6034   //PackedSingle     PackedDouble    PackedInt
6035   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
6036   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
6037   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
6038   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
6039   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
6040   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
6041   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
6042   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
6043   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
6044   { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
6045   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
6046   { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
6047   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
6048   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
6049   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
6050   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
6051   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
6052   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
6053   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
6054   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
6055   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
6056   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
6057   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
6058   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
6059   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
6060   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
6061   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
6062   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
6063   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
6064   { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
6065   { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
6066   // AVX 128-bit support
6067   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
6068   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
6069   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
6070   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
6071   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
6072   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
6073   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
6074   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
6075   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
6076   { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
6077   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
6078   { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
6079   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6080   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
6081   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
6082   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
6083   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
6084   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
6085   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
6086   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
6087   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
6088   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
6089   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
6090   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
6091   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
6092   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
6093   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
6094   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
6095   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
6096   { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
6097   { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
6098   // AVX 256-bit support
6099   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
6100   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
6101   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
6102   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
6103   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
6104   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
6105   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
6106   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
6107   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
6108   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
6109   // AVX512 support
6110   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
6111   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
6112   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
6113   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
6114   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
6115   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
6116   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
6117   { X86::VMOVSDZrm_alt,  X86::VMOVSDZrm_alt,  X86::VMOVQI2PQIZrm  },
6118   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
6119   { X86::VMOVSSZrm_alt,  X86::VMOVSSZrm_alt,  X86::VMOVDI2PDIZrm  },
6120   { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
6121   { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
6122   { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
6123   { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
6124   { X86::VBROADCASTSSZr,    X86::VBROADCASTSSZr,    X86::VPBROADCASTDZr },
6125   { X86::VBROADCASTSSZm,    X86::VBROADCASTSSZm,    X86::VPBROADCASTDZm },
6126   { X86::VMOVDDUPZ128rr,    X86::VMOVDDUPZ128rr,    X86::VPBROADCASTQZ128r },
6127   { X86::VMOVDDUPZ128rm,    X86::VMOVDDUPZ128rm,    X86::VPBROADCASTQZ128m },
6128   { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
6129   { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
6130   { X86::VBROADCASTSDZr,    X86::VBROADCASTSDZr,    X86::VPBROADCASTQZr },
6131   { X86::VBROADCASTSDZm,    X86::VBROADCASTSDZm,    X86::VPBROADCASTQZm },
6132   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
6133   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
6134   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
6135   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
6136   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
6137   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
6138   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
6139   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
6140   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
6141   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
6142   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
6143   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
6144   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
6145   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
6146   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
6147   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
6148   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
6149   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
6150   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
6151   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
6152   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
6153   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
6154   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
6155   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
6156   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
6157   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
6158   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
6159   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
6160   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
6161   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
6162   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
6163   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
6164   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
6165   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
6166   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
6167   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
6168   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
6169   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
6170   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
6171   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
6172   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
6173   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
6174   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
6175   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
6176   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
6177   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
6178   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
6179   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
6180   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
6181   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
6182   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
6183   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
6184   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
6185   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
6186   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
6187   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
6188   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
6189   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
6190   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
6191   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
6192   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
6193   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
6194   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
6195   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
6196   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
6197   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
6198   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
6199   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
6200   { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
6201   { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
6202 };
6203 
6204 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6205   //PackedSingle       PackedDouble       PackedInt
6206   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
6207   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
6208   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
6209   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
6210   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
6211   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
6212   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
6213   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
6214   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
6215   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
6216   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6217   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6218   { X86::VMOVDDUPrm,     X86::VMOVDDUPrm,     X86::VPBROADCASTQrm},
6219   { X86::VMOVDDUPrr,     X86::VMOVDDUPrr,     X86::VPBROADCASTQrr},
6220   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6221   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6222   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6223   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
6224   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
6225   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
6226   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
6227   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
6228   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
6229   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
6230   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
6231   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
6232   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
6233   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
6234   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
6235   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
6236   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
6237 };
6238 
6239 static const uint16_t ReplaceableInstrsFP[][3] = {
6240   //PackedSingle         PackedDouble
6241   { X86::MOVLPSrm,       X86::MOVLPDrm,      X86::INSTRUCTION_LIST_END },
6242   { X86::MOVHPSrm,       X86::MOVHPDrm,      X86::INSTRUCTION_LIST_END },
6243   { X86::MOVHPSmr,       X86::MOVHPDmr,      X86::INSTRUCTION_LIST_END },
6244   { X86::VMOVLPSrm,      X86::VMOVLPDrm,     X86::INSTRUCTION_LIST_END },
6245   { X86::VMOVHPSrm,      X86::VMOVHPDrm,     X86::INSTRUCTION_LIST_END },
6246   { X86::VMOVHPSmr,      X86::VMOVHPDmr,     X86::INSTRUCTION_LIST_END },
6247   { X86::VMOVLPSZ128rm,  X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
6248   { X86::VMOVHPSZ128rm,  X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
6249   { X86::VMOVHPSZ128mr,  X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
6250 };
6251 
6252 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
6253   //PackedSingle       PackedDouble       PackedInt
6254   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6255   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6256   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
6257   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
6258 };
6259 
6260 static const uint16_t ReplaceableInstrsAVX512[][4] = {
6261   // Two integer columns for 64-bit and 32-bit elements.
6262   //PackedSingle        PackedDouble        PackedInt             PackedInt
6263   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
6264   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
6265   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
6266   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
6267   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
6268   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
6269   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
6270   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
6271   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
6272   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
6273   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
6274   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
6275   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
6276   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
6277   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
6278 };
6279 
6280 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
6281   // Two integer columns for 64-bit and 32-bit elements.
6282   //PackedSingle        PackedDouble        PackedInt           PackedInt
6283   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6284   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6285   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
6286   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
6287   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
6288   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
6289   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
6290   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
6291   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6292   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6293   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
6294   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
6295   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
6296   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
6297   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
6298   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
6299   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
6300   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
6301   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
6302   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
6303   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
6304   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
6305   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
6306   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
6307 };
6308 
6309 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
6310   // Two integer columns for 64-bit and 32-bit elements.
6311   //PackedSingle          PackedDouble
6312   //PackedInt             PackedInt
6313   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
6314     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
6315   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
6316     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
6317   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
6318     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
6319   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
6320     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
6321   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
6322     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
6323   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
6324     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
6325   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
6326     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
6327   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
6328     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
6329   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
6330     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
6331   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
6332     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
6333   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
6334     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
6335   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
6336     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
6337   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
6338     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
6339   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
6340     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
6341   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
6342     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
6343   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
6344     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
6345   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
6346     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
6347   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
6348     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
6349   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
6350     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
6351   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
6352     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
6353   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
6354     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
6355   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
6356     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
6357   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
6358     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
6359   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
6360     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
6361   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
6362     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
6363   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
6364     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
6365   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
6366     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
6367   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
6368     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
6369   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
6370     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
6371   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
6372     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
6373   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
6374     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
6375   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
6376     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
6377   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
6378     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
6379   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
6380     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
6381   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
6382     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
6383   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
6384     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
6385   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
6386     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
6387   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
6388     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
6389   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
6390     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
6391   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
6392     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
6393   { X86::VORPSZrmk,       X86::VORPDZrmk,
6394     X86::VPORQZrmk,       X86::VPORDZrmk       },
6395   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
6396     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
6397   { X86::VORPSZrrk,       X86::VORPDZrrk,
6398     X86::VPORQZrrk,       X86::VPORDZrrk       },
6399   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
6400     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
6401   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
6402     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
6403   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
6404     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
6405   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
6406     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
6407   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
6408     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
6409   // Broadcast loads can be handled the same as masked operations to avoid
6410   // changing element size.
6411   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
6412     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
6413   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
6414     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
6415   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
6416     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
6417   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
6418     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
6419   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
6420     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
6421   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
6422     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
6423   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
6424     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
6425   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
6426     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
6427   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
6428     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
6429   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
6430     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
6431   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
6432     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
6433   { X86::VORPSZrmb,       X86::VORPDZrmb,
6434     X86::VPORQZrmb,       X86::VPORDZrmb       },
6435   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
6436     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
6437   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
6438     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
6439   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
6440     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
6441   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
6442     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
6443   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
6444     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
6445   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
6446     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
6447   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
6448     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
6449   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
6450     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
6451   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
6452     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
6453   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
6454     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
6455   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
6456     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
6457   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
6458     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
6459   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
6460     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
6461   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
6462     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
6463   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
6464     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
6465   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
6466     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
6467   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
6468     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
6469   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
6470     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
6471   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
6472     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
6473   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
6474     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
6475   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
6476     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
6477   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
6478     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
6479   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
6480     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
6481   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
6482     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
6483   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
6484     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
6485   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
6486     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
6487   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
6488     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
6489 };
6490 
6491 // NOTE: These should only be used by the custom domain methods.
6492 static const uint16_t ReplaceableBlendInstrs[][3] = {
6493   //PackedSingle             PackedDouble             PackedInt
6494   { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
6495   { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
6496   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
6497   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
6498   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
6499   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
6500 };
6501 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
6502   //PackedSingle             PackedDouble             PackedInt
6503   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
6504   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
6505   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
6506   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
6507 };
6508 
6509 // Special table for changing EVEX logic instructions to VEX.
6510 // TODO: Should we run EVEX->VEX earlier?
6511 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
6512   // Two integer columns for 64-bit and 32-bit elements.
6513   //PackedSingle     PackedDouble     PackedInt           PackedInt
6514   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6515   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6516   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
6517   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
6518   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORQZ128rm,   X86::VPORDZ128rm   },
6519   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORQZ128rr,   X86::VPORDZ128rr   },
6520   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
6521   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
6522   { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6523   { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6524   { X86::VANDPSYrm,  X86::VANDPDYrm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
6525   { X86::VANDPSYrr,  X86::VANDPDYrr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
6526   { X86::VORPSYrm,   X86::VORPDYrm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
6527   { X86::VORPSYrr,   X86::VORPDYrr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
6528   { X86::VXORPSYrm,  X86::VXORPDYrm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
6529   { X86::VXORPSYrr,  X86::VXORPDYrr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
6530 };
6531 
6532 // FIXME: Some shuffle and unpack instructions have equivalents in different
6533 // domains, but they require a bit more work than just switching opcodes.
6534 
6535 static const uint16_t *lookup(unsigned opcode, unsigned domain,
6536                               ArrayRef<uint16_t[3]> Table) {
6537   for (const uint16_t (&Row)[3] : Table)
6538     if (Row[domain-1] == opcode)
6539       return Row;
6540   return nullptr;
6541 }
6542 
6543 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
6544                                     ArrayRef<uint16_t[4]> Table) {
6545   // If this is the integer domain make sure to check both integer columns.
6546   for (const uint16_t (&Row)[4] : Table)
6547     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
6548       return Row;
6549   return nullptr;
6550 }
6551 
6552 // Helper to attempt to widen/narrow blend masks.
6553 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
6554                             unsigned NewWidth, unsigned *pNewMask = nullptr) {
6555   assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
6556          "Illegal blend mask scale");
6557   unsigned NewMask = 0;
6558 
6559   if ((OldWidth % NewWidth) == 0) {
6560     unsigned Scale = OldWidth / NewWidth;
6561     unsigned SubMask = (1u << Scale) - 1;
6562     for (unsigned i = 0; i != NewWidth; ++i) {
6563       unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
6564       if (Sub == SubMask)
6565         NewMask |= (1u << i);
6566       else if (Sub != 0x0)
6567         return false;
6568     }
6569   } else {
6570     unsigned Scale = NewWidth / OldWidth;
6571     unsigned SubMask = (1u << Scale) - 1;
6572     for (unsigned i = 0; i != OldWidth; ++i) {
6573       if (OldMask & (1 << i)) {
6574         NewMask |= (SubMask << (i * Scale));
6575       }
6576     }
6577   }
6578 
6579   if (pNewMask)
6580     *pNewMask = NewMask;
6581   return true;
6582 }
6583 
6584 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
6585   unsigned Opcode = MI.getOpcode();
6586   unsigned NumOperands = MI.getDesc().getNumOperands();
6587 
6588   auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
6589     uint16_t validDomains = 0;
6590     if (MI.getOperand(NumOperands - 1).isImm()) {
6591       unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
6592       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
6593         validDomains |= 0x2; // PackedSingle
6594       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
6595         validDomains |= 0x4; // PackedDouble
6596       if (!Is256 || Subtarget.hasAVX2())
6597         validDomains |= 0x8; // PackedInt
6598     }
6599     return validDomains;
6600   };
6601 
6602   switch (Opcode) {
6603   case X86::BLENDPDrmi:
6604   case X86::BLENDPDrri:
6605   case X86::VBLENDPDrmi:
6606   case X86::VBLENDPDrri:
6607     return GetBlendDomains(2, false);
6608   case X86::VBLENDPDYrmi:
6609   case X86::VBLENDPDYrri:
6610     return GetBlendDomains(4, true);
6611   case X86::BLENDPSrmi:
6612   case X86::BLENDPSrri:
6613   case X86::VBLENDPSrmi:
6614   case X86::VBLENDPSrri:
6615   case X86::VPBLENDDrmi:
6616   case X86::VPBLENDDrri:
6617     return GetBlendDomains(4, false);
6618   case X86::VBLENDPSYrmi:
6619   case X86::VBLENDPSYrri:
6620   case X86::VPBLENDDYrmi:
6621   case X86::VPBLENDDYrri:
6622     return GetBlendDomains(8, true);
6623   case X86::PBLENDWrmi:
6624   case X86::PBLENDWrri:
6625   case X86::VPBLENDWrmi:
6626   case X86::VPBLENDWrri:
6627   // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
6628   case X86::VPBLENDWYrmi:
6629   case X86::VPBLENDWYrri:
6630     return GetBlendDomains(8, false);
6631   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
6632   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
6633   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
6634   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
6635   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6636   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6637   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6638   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6639   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
6640   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
6641   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
6642   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
6643   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
6644   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
6645   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
6646   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm:
6647     // If we don't have DQI see if we can still switch from an EVEX integer
6648     // instruction to a VEX floating point instruction.
6649     if (Subtarget.hasDQI())
6650       return 0;
6651 
6652     if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
6653       return 0;
6654     if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
6655       return 0;
6656     // Register forms will have 3 operands. Memory form will have more.
6657     if (NumOperands == 3 &&
6658         RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
6659       return 0;
6660 
6661     // All domains are valid.
6662     return 0xe;
6663   case X86::MOVHLPSrr:
6664     // We can swap domains when both inputs are the same register.
6665     // FIXME: This doesn't catch all the cases we would like. If the input
6666     // register isn't KILLed by the instruction, the two address instruction
6667     // pass puts a COPY on one input. The other input uses the original
6668     // register. This prevents the same physical register from being used by
6669     // both inputs.
6670     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6671         MI.getOperand(0).getSubReg() == 0 &&
6672         MI.getOperand(1).getSubReg() == 0 &&
6673         MI.getOperand(2).getSubReg() == 0)
6674       return 0x6;
6675     return 0;
6676   case X86::SHUFPDrri:
6677     return 0x6;
6678   }
6679   return 0;
6680 }
6681 
6682 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
6683                                             unsigned Domain) const {
6684   assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
6685   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6686   assert(dom && "Not an SSE instruction");
6687 
6688   unsigned Opcode = MI.getOpcode();
6689   unsigned NumOperands = MI.getDesc().getNumOperands();
6690 
6691   auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
6692     if (MI.getOperand(NumOperands - 1).isImm()) {
6693       unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
6694       Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
6695       unsigned NewImm = Imm;
6696 
6697       const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
6698       if (!table)
6699         table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
6700 
6701       if (Domain == 1) { // PackedSingle
6702         AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6703       } else if (Domain == 2) { // PackedDouble
6704         AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
6705       } else if (Domain == 3) { // PackedInt
6706         if (Subtarget.hasAVX2()) {
6707           // If we are already VPBLENDW use that, else use VPBLENDD.
6708           if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
6709             table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
6710             AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6711           }
6712         } else {
6713           assert(!Is256 && "128-bit vector expected");
6714           AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
6715         }
6716       }
6717 
6718       assert(table && table[Domain - 1] && "Unknown domain op");
6719       MI.setDesc(get(table[Domain - 1]));
6720       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
6721     }
6722     return true;
6723   };
6724 
6725   switch (Opcode) {
6726   case X86::BLENDPDrmi:
6727   case X86::BLENDPDrri:
6728   case X86::VBLENDPDrmi:
6729   case X86::VBLENDPDrri:
6730     return SetBlendDomain(2, false);
6731   case X86::VBLENDPDYrmi:
6732   case X86::VBLENDPDYrri:
6733     return SetBlendDomain(4, true);
6734   case X86::BLENDPSrmi:
6735   case X86::BLENDPSrri:
6736   case X86::VBLENDPSrmi:
6737   case X86::VBLENDPSrri:
6738   case X86::VPBLENDDrmi:
6739   case X86::VPBLENDDrri:
6740     return SetBlendDomain(4, false);
6741   case X86::VBLENDPSYrmi:
6742   case X86::VBLENDPSYrri:
6743   case X86::VPBLENDDYrmi:
6744   case X86::VPBLENDDYrri:
6745     return SetBlendDomain(8, true);
6746   case X86::PBLENDWrmi:
6747   case X86::PBLENDWrri:
6748   case X86::VPBLENDWrmi:
6749   case X86::VPBLENDWrri:
6750     return SetBlendDomain(8, false);
6751   case X86::VPBLENDWYrmi:
6752   case X86::VPBLENDWYrri:
6753     return SetBlendDomain(16, true);
6754   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
6755   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
6756   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
6757   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
6758   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6759   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6760   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6761   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6762   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
6763   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
6764   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
6765   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
6766   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
6767   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
6768   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
6769   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm: {
6770     // Without DQI, convert EVEX instructions to VEX instructions.
6771     if (Subtarget.hasDQI())
6772       return false;
6773 
6774     const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
6775                                          ReplaceableCustomAVX512LogicInstrs);
6776     assert(table && "Instruction not found in table?");
6777     // Don't change integer Q instructions to D instructions and
6778     // use D intructions if we started with a PS instruction.
6779     if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6780       Domain = 4;
6781     MI.setDesc(get(table[Domain - 1]));
6782     return true;
6783   }
6784   case X86::UNPCKHPDrr:
6785   case X86::MOVHLPSrr:
6786     // We just need to commute the instruction which will switch the domains.
6787     if (Domain != dom && Domain != 3 &&
6788         MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6789         MI.getOperand(0).getSubReg() == 0 &&
6790         MI.getOperand(1).getSubReg() == 0 &&
6791         MI.getOperand(2).getSubReg() == 0) {
6792       commuteInstruction(MI, false);
6793       return true;
6794     }
6795     // We must always return true for MOVHLPSrr.
6796     if (Opcode == X86::MOVHLPSrr)
6797       return true;
6798     break;
6799   case X86::SHUFPDrri: {
6800     if (Domain == 1) {
6801       unsigned Imm = MI.getOperand(3).getImm();
6802       unsigned NewImm = 0x44;
6803       if (Imm & 1) NewImm |= 0x0a;
6804       if (Imm & 2) NewImm |= 0xa0;
6805       MI.getOperand(3).setImm(NewImm);
6806       MI.setDesc(get(X86::SHUFPSrri));
6807     }
6808     return true;
6809   }
6810   }
6811   return false;
6812 }
6813 
6814 std::pair<uint16_t, uint16_t>
6815 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
6816   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6817   unsigned opcode = MI.getOpcode();
6818   uint16_t validDomains = 0;
6819   if (domain) {
6820     // Attempt to match for custom instructions.
6821     validDomains = getExecutionDomainCustom(MI);
6822     if (validDomains)
6823       return std::make_pair(domain, validDomains);
6824 
6825     if (lookup(opcode, domain, ReplaceableInstrs)) {
6826       validDomains = 0xe;
6827     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
6828       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
6829     } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
6830       validDomains = 0x6;
6831     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
6832       // Insert/extract instructions should only effect domain if AVX2
6833       // is enabled.
6834       if (!Subtarget.hasAVX2())
6835         return std::make_pair(0, 0);
6836       validDomains = 0xe;
6837     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
6838       validDomains = 0xe;
6839     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
6840                                                   ReplaceableInstrsAVX512DQ)) {
6841       validDomains = 0xe;
6842     } else if (Subtarget.hasDQI()) {
6843       if (const uint16_t *table = lookupAVX512(opcode, domain,
6844                                              ReplaceableInstrsAVX512DQMasked)) {
6845         if (domain == 1 || (domain == 3 && table[3] == opcode))
6846           validDomains = 0xa;
6847         else
6848           validDomains = 0xc;
6849       }
6850     }
6851   }
6852   return std::make_pair(domain, validDomains);
6853 }
6854 
6855 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
6856   assert(Domain>0 && Domain<4 && "Invalid execution domain");
6857   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6858   assert(dom && "Not an SSE instruction");
6859 
6860   // Attempt to match for custom instructions.
6861   if (setExecutionDomainCustom(MI, Domain))
6862     return;
6863 
6864   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
6865   if (!table) { // try the other table
6866     assert((Subtarget.hasAVX2() || Domain < 3) &&
6867            "256-bit vector operations only available in AVX2");
6868     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
6869   }
6870   if (!table) { // try the FP table
6871     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
6872     assert((!table || Domain < 3) &&
6873            "Can only select PackedSingle or PackedDouble");
6874   }
6875   if (!table) { // try the other table
6876     assert(Subtarget.hasAVX2() &&
6877            "256-bit insert/extract only available in AVX2");
6878     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
6879   }
6880   if (!table) { // try the AVX512 table
6881     assert(Subtarget.hasAVX512() && "Requires AVX-512");
6882     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
6883     // Don't change integer Q instructions to D instructions.
6884     if (table && Domain == 3 && table[3] == MI.getOpcode())
6885       Domain = 4;
6886   }
6887   if (!table) { // try the AVX512DQ table
6888     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
6889     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
6890     // Don't change integer Q instructions to D instructions and
6891     // use D intructions if we started with a PS instruction.
6892     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6893       Domain = 4;
6894   }
6895   if (!table) { // try the AVX512DQMasked table
6896     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
6897     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
6898     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6899       Domain = 4;
6900   }
6901   assert(table && "Cannot change domain");
6902   MI.setDesc(get(table[Domain - 1]));
6903 }
6904 
6905 /// Return the noop instruction to use for a noop.
6906 void X86InstrInfo::getNoop(MCInst &NopInst) const {
6907   NopInst.setOpcode(X86::NOOP);
6908 }
6909 
6910 bool X86InstrInfo::isHighLatencyDef(int opc) const {
6911   switch (opc) {
6912   default: return false;
6913   case X86::DIVPDrm:
6914   case X86::DIVPDrr:
6915   case X86::DIVPSrm:
6916   case X86::DIVPSrr:
6917   case X86::DIVSDrm:
6918   case X86::DIVSDrm_Int:
6919   case X86::DIVSDrr:
6920   case X86::DIVSDrr_Int:
6921   case X86::DIVSSrm:
6922   case X86::DIVSSrm_Int:
6923   case X86::DIVSSrr:
6924   case X86::DIVSSrr_Int:
6925   case X86::SQRTPDm:
6926   case X86::SQRTPDr:
6927   case X86::SQRTPSm:
6928   case X86::SQRTPSr:
6929   case X86::SQRTSDm:
6930   case X86::SQRTSDm_Int:
6931   case X86::SQRTSDr:
6932   case X86::SQRTSDr_Int:
6933   case X86::SQRTSSm:
6934   case X86::SQRTSSm_Int:
6935   case X86::SQRTSSr:
6936   case X86::SQRTSSr_Int:
6937   // AVX instructions with high latency
6938   case X86::VDIVPDrm:
6939   case X86::VDIVPDrr:
6940   case X86::VDIVPDYrm:
6941   case X86::VDIVPDYrr:
6942   case X86::VDIVPSrm:
6943   case X86::VDIVPSrr:
6944   case X86::VDIVPSYrm:
6945   case X86::VDIVPSYrr:
6946   case X86::VDIVSDrm:
6947   case X86::VDIVSDrm_Int:
6948   case X86::VDIVSDrr:
6949   case X86::VDIVSDrr_Int:
6950   case X86::VDIVSSrm:
6951   case X86::VDIVSSrm_Int:
6952   case X86::VDIVSSrr:
6953   case X86::VDIVSSrr_Int:
6954   case X86::VSQRTPDm:
6955   case X86::VSQRTPDr:
6956   case X86::VSQRTPDYm:
6957   case X86::VSQRTPDYr:
6958   case X86::VSQRTPSm:
6959   case X86::VSQRTPSr:
6960   case X86::VSQRTPSYm:
6961   case X86::VSQRTPSYr:
6962   case X86::VSQRTSDm:
6963   case X86::VSQRTSDm_Int:
6964   case X86::VSQRTSDr:
6965   case X86::VSQRTSDr_Int:
6966   case X86::VSQRTSSm:
6967   case X86::VSQRTSSm_Int:
6968   case X86::VSQRTSSr:
6969   case X86::VSQRTSSr_Int:
6970   // AVX512 instructions with high latency
6971   case X86::VDIVPDZ128rm:
6972   case X86::VDIVPDZ128rmb:
6973   case X86::VDIVPDZ128rmbk:
6974   case X86::VDIVPDZ128rmbkz:
6975   case X86::VDIVPDZ128rmk:
6976   case X86::VDIVPDZ128rmkz:
6977   case X86::VDIVPDZ128rr:
6978   case X86::VDIVPDZ128rrk:
6979   case X86::VDIVPDZ128rrkz:
6980   case X86::VDIVPDZ256rm:
6981   case X86::VDIVPDZ256rmb:
6982   case X86::VDIVPDZ256rmbk:
6983   case X86::VDIVPDZ256rmbkz:
6984   case X86::VDIVPDZ256rmk:
6985   case X86::VDIVPDZ256rmkz:
6986   case X86::VDIVPDZ256rr:
6987   case X86::VDIVPDZ256rrk:
6988   case X86::VDIVPDZ256rrkz:
6989   case X86::VDIVPDZrrb:
6990   case X86::VDIVPDZrrbk:
6991   case X86::VDIVPDZrrbkz:
6992   case X86::VDIVPDZrm:
6993   case X86::VDIVPDZrmb:
6994   case X86::VDIVPDZrmbk:
6995   case X86::VDIVPDZrmbkz:
6996   case X86::VDIVPDZrmk:
6997   case X86::VDIVPDZrmkz:
6998   case X86::VDIVPDZrr:
6999   case X86::VDIVPDZrrk:
7000   case X86::VDIVPDZrrkz:
7001   case X86::VDIVPSZ128rm:
7002   case X86::VDIVPSZ128rmb:
7003   case X86::VDIVPSZ128rmbk:
7004   case X86::VDIVPSZ128rmbkz:
7005   case X86::VDIVPSZ128rmk:
7006   case X86::VDIVPSZ128rmkz:
7007   case X86::VDIVPSZ128rr:
7008   case X86::VDIVPSZ128rrk:
7009   case X86::VDIVPSZ128rrkz:
7010   case X86::VDIVPSZ256rm:
7011   case X86::VDIVPSZ256rmb:
7012   case X86::VDIVPSZ256rmbk:
7013   case X86::VDIVPSZ256rmbkz:
7014   case X86::VDIVPSZ256rmk:
7015   case X86::VDIVPSZ256rmkz:
7016   case X86::VDIVPSZ256rr:
7017   case X86::VDIVPSZ256rrk:
7018   case X86::VDIVPSZ256rrkz:
7019   case X86::VDIVPSZrrb:
7020   case X86::VDIVPSZrrbk:
7021   case X86::VDIVPSZrrbkz:
7022   case X86::VDIVPSZrm:
7023   case X86::VDIVPSZrmb:
7024   case X86::VDIVPSZrmbk:
7025   case X86::VDIVPSZrmbkz:
7026   case X86::VDIVPSZrmk:
7027   case X86::VDIVPSZrmkz:
7028   case X86::VDIVPSZrr:
7029   case X86::VDIVPSZrrk:
7030   case X86::VDIVPSZrrkz:
7031   case X86::VDIVSDZrm:
7032   case X86::VDIVSDZrr:
7033   case X86::VDIVSDZrm_Int:
7034   case X86::VDIVSDZrm_Intk:
7035   case X86::VDIVSDZrm_Intkz:
7036   case X86::VDIVSDZrr_Int:
7037   case X86::VDIVSDZrr_Intk:
7038   case X86::VDIVSDZrr_Intkz:
7039   case X86::VDIVSDZrrb_Int:
7040   case X86::VDIVSDZrrb_Intk:
7041   case X86::VDIVSDZrrb_Intkz:
7042   case X86::VDIVSSZrm:
7043   case X86::VDIVSSZrr:
7044   case X86::VDIVSSZrm_Int:
7045   case X86::VDIVSSZrm_Intk:
7046   case X86::VDIVSSZrm_Intkz:
7047   case X86::VDIVSSZrr_Int:
7048   case X86::VDIVSSZrr_Intk:
7049   case X86::VDIVSSZrr_Intkz:
7050   case X86::VDIVSSZrrb_Int:
7051   case X86::VDIVSSZrrb_Intk:
7052   case X86::VDIVSSZrrb_Intkz:
7053   case X86::VSQRTPDZ128m:
7054   case X86::VSQRTPDZ128mb:
7055   case X86::VSQRTPDZ128mbk:
7056   case X86::VSQRTPDZ128mbkz:
7057   case X86::VSQRTPDZ128mk:
7058   case X86::VSQRTPDZ128mkz:
7059   case X86::VSQRTPDZ128r:
7060   case X86::VSQRTPDZ128rk:
7061   case X86::VSQRTPDZ128rkz:
7062   case X86::VSQRTPDZ256m:
7063   case X86::VSQRTPDZ256mb:
7064   case X86::VSQRTPDZ256mbk:
7065   case X86::VSQRTPDZ256mbkz:
7066   case X86::VSQRTPDZ256mk:
7067   case X86::VSQRTPDZ256mkz:
7068   case X86::VSQRTPDZ256r:
7069   case X86::VSQRTPDZ256rk:
7070   case X86::VSQRTPDZ256rkz:
7071   case X86::VSQRTPDZm:
7072   case X86::VSQRTPDZmb:
7073   case X86::VSQRTPDZmbk:
7074   case X86::VSQRTPDZmbkz:
7075   case X86::VSQRTPDZmk:
7076   case X86::VSQRTPDZmkz:
7077   case X86::VSQRTPDZr:
7078   case X86::VSQRTPDZrb:
7079   case X86::VSQRTPDZrbk:
7080   case X86::VSQRTPDZrbkz:
7081   case X86::VSQRTPDZrk:
7082   case X86::VSQRTPDZrkz:
7083   case X86::VSQRTPSZ128m:
7084   case X86::VSQRTPSZ128mb:
7085   case X86::VSQRTPSZ128mbk:
7086   case X86::VSQRTPSZ128mbkz:
7087   case X86::VSQRTPSZ128mk:
7088   case X86::VSQRTPSZ128mkz:
7089   case X86::VSQRTPSZ128r:
7090   case X86::VSQRTPSZ128rk:
7091   case X86::VSQRTPSZ128rkz:
7092   case X86::VSQRTPSZ256m:
7093   case X86::VSQRTPSZ256mb:
7094   case X86::VSQRTPSZ256mbk:
7095   case X86::VSQRTPSZ256mbkz:
7096   case X86::VSQRTPSZ256mk:
7097   case X86::VSQRTPSZ256mkz:
7098   case X86::VSQRTPSZ256r:
7099   case X86::VSQRTPSZ256rk:
7100   case X86::VSQRTPSZ256rkz:
7101   case X86::VSQRTPSZm:
7102   case X86::VSQRTPSZmb:
7103   case X86::VSQRTPSZmbk:
7104   case X86::VSQRTPSZmbkz:
7105   case X86::VSQRTPSZmk:
7106   case X86::VSQRTPSZmkz:
7107   case X86::VSQRTPSZr:
7108   case X86::VSQRTPSZrb:
7109   case X86::VSQRTPSZrbk:
7110   case X86::VSQRTPSZrbkz:
7111   case X86::VSQRTPSZrk:
7112   case X86::VSQRTPSZrkz:
7113   case X86::VSQRTSDZm:
7114   case X86::VSQRTSDZm_Int:
7115   case X86::VSQRTSDZm_Intk:
7116   case X86::VSQRTSDZm_Intkz:
7117   case X86::VSQRTSDZr:
7118   case X86::VSQRTSDZr_Int:
7119   case X86::VSQRTSDZr_Intk:
7120   case X86::VSQRTSDZr_Intkz:
7121   case X86::VSQRTSDZrb_Int:
7122   case X86::VSQRTSDZrb_Intk:
7123   case X86::VSQRTSDZrb_Intkz:
7124   case X86::VSQRTSSZm:
7125   case X86::VSQRTSSZm_Int:
7126   case X86::VSQRTSSZm_Intk:
7127   case X86::VSQRTSSZm_Intkz:
7128   case X86::VSQRTSSZr:
7129   case X86::VSQRTSSZr_Int:
7130   case X86::VSQRTSSZr_Intk:
7131   case X86::VSQRTSSZr_Intkz:
7132   case X86::VSQRTSSZrb_Int:
7133   case X86::VSQRTSSZrb_Intk:
7134   case X86::VSQRTSSZrb_Intkz:
7135 
7136   case X86::VGATHERDPDYrm:
7137   case X86::VGATHERDPDZ128rm:
7138   case X86::VGATHERDPDZ256rm:
7139   case X86::VGATHERDPDZrm:
7140   case X86::VGATHERDPDrm:
7141   case X86::VGATHERDPSYrm:
7142   case X86::VGATHERDPSZ128rm:
7143   case X86::VGATHERDPSZ256rm:
7144   case X86::VGATHERDPSZrm:
7145   case X86::VGATHERDPSrm:
7146   case X86::VGATHERPF0DPDm:
7147   case X86::VGATHERPF0DPSm:
7148   case X86::VGATHERPF0QPDm:
7149   case X86::VGATHERPF0QPSm:
7150   case X86::VGATHERPF1DPDm:
7151   case X86::VGATHERPF1DPSm:
7152   case X86::VGATHERPF1QPDm:
7153   case X86::VGATHERPF1QPSm:
7154   case X86::VGATHERQPDYrm:
7155   case X86::VGATHERQPDZ128rm:
7156   case X86::VGATHERQPDZ256rm:
7157   case X86::VGATHERQPDZrm:
7158   case X86::VGATHERQPDrm:
7159   case X86::VGATHERQPSYrm:
7160   case X86::VGATHERQPSZ128rm:
7161   case X86::VGATHERQPSZ256rm:
7162   case X86::VGATHERQPSZrm:
7163   case X86::VGATHERQPSrm:
7164   case X86::VPGATHERDDYrm:
7165   case X86::VPGATHERDDZ128rm:
7166   case X86::VPGATHERDDZ256rm:
7167   case X86::VPGATHERDDZrm:
7168   case X86::VPGATHERDDrm:
7169   case X86::VPGATHERDQYrm:
7170   case X86::VPGATHERDQZ128rm:
7171   case X86::VPGATHERDQZ256rm:
7172   case X86::VPGATHERDQZrm:
7173   case X86::VPGATHERDQrm:
7174   case X86::VPGATHERQDYrm:
7175   case X86::VPGATHERQDZ128rm:
7176   case X86::VPGATHERQDZ256rm:
7177   case X86::VPGATHERQDZrm:
7178   case X86::VPGATHERQDrm:
7179   case X86::VPGATHERQQYrm:
7180   case X86::VPGATHERQQZ128rm:
7181   case X86::VPGATHERQQZ256rm:
7182   case X86::VPGATHERQQZrm:
7183   case X86::VPGATHERQQrm:
7184   case X86::VSCATTERDPDZ128mr:
7185   case X86::VSCATTERDPDZ256mr:
7186   case X86::VSCATTERDPDZmr:
7187   case X86::VSCATTERDPSZ128mr:
7188   case X86::VSCATTERDPSZ256mr:
7189   case X86::VSCATTERDPSZmr:
7190   case X86::VSCATTERPF0DPDm:
7191   case X86::VSCATTERPF0DPSm:
7192   case X86::VSCATTERPF0QPDm:
7193   case X86::VSCATTERPF0QPSm:
7194   case X86::VSCATTERPF1DPDm:
7195   case X86::VSCATTERPF1DPSm:
7196   case X86::VSCATTERPF1QPDm:
7197   case X86::VSCATTERPF1QPSm:
7198   case X86::VSCATTERQPDZ128mr:
7199   case X86::VSCATTERQPDZ256mr:
7200   case X86::VSCATTERQPDZmr:
7201   case X86::VSCATTERQPSZ128mr:
7202   case X86::VSCATTERQPSZ256mr:
7203   case X86::VSCATTERQPSZmr:
7204   case X86::VPSCATTERDDZ128mr:
7205   case X86::VPSCATTERDDZ256mr:
7206   case X86::VPSCATTERDDZmr:
7207   case X86::VPSCATTERDQZ128mr:
7208   case X86::VPSCATTERDQZ256mr:
7209   case X86::VPSCATTERDQZmr:
7210   case X86::VPSCATTERQDZ128mr:
7211   case X86::VPSCATTERQDZ256mr:
7212   case X86::VPSCATTERQDZmr:
7213   case X86::VPSCATTERQQZ128mr:
7214   case X86::VPSCATTERQQZ256mr:
7215   case X86::VPSCATTERQQZmr:
7216     return true;
7217   }
7218 }
7219 
7220 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7221                                          const MachineRegisterInfo *MRI,
7222                                          const MachineInstr &DefMI,
7223                                          unsigned DefIdx,
7224                                          const MachineInstr &UseMI,
7225                                          unsigned UseIdx) const {
7226   return isHighLatencyDef(DefMI.getOpcode());
7227 }
7228 
7229 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7230                                            const MachineBasicBlock *MBB) const {
7231   assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
7232          Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
7233 
7234   // Integer binary math/logic instructions have a third source operand:
7235   // the EFLAGS register. That operand must be both defined here and never
7236   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7237   // not change anything because rearranging the operands could affect other
7238   // instructions that depend on the exact status flags (zero, sign, etc.)
7239   // that are set by using these particular operands with this operation.
7240   const MachineOperand *FlagDef = Inst.findRegisterDefOperand(X86::EFLAGS);
7241   assert((Inst.getNumDefs() == 1 || FlagDef) &&
7242          "Implicit def isn't flags?");
7243   if (FlagDef && !FlagDef->isDead())
7244     return false;
7245 
7246   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7247 }
7248 
7249 // TODO: There are many more machine instruction opcodes to match:
7250 //       1. Other data types (integer, vectors)
7251 //       2. Other math / logic operations (xor, or)
7252 //       3. Other forms of the same operation (intrinsics and other variants)
7253 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7254   switch (Inst.getOpcode()) {
7255   case X86::AND8rr:
7256   case X86::AND16rr:
7257   case X86::AND32rr:
7258   case X86::AND64rr:
7259   case X86::OR8rr:
7260   case X86::OR16rr:
7261   case X86::OR32rr:
7262   case X86::OR64rr:
7263   case X86::XOR8rr:
7264   case X86::XOR16rr:
7265   case X86::XOR32rr:
7266   case X86::XOR64rr:
7267   case X86::IMUL16rr:
7268   case X86::IMUL32rr:
7269   case X86::IMUL64rr:
7270   case X86::PANDrr:
7271   case X86::PORrr:
7272   case X86::PXORrr:
7273   case X86::ANDPDrr:
7274   case X86::ANDPSrr:
7275   case X86::ORPDrr:
7276   case X86::ORPSrr:
7277   case X86::XORPDrr:
7278   case X86::XORPSrr:
7279   case X86::PADDBrr:
7280   case X86::PADDWrr:
7281   case X86::PADDDrr:
7282   case X86::PADDQrr:
7283   case X86::PMULLWrr:
7284   case X86::PMULLDrr:
7285   case X86::PMAXSBrr:
7286   case X86::PMAXSDrr:
7287   case X86::PMAXSWrr:
7288   case X86::PMAXUBrr:
7289   case X86::PMAXUDrr:
7290   case X86::PMAXUWrr:
7291   case X86::PMINSBrr:
7292   case X86::PMINSDrr:
7293   case X86::PMINSWrr:
7294   case X86::PMINUBrr:
7295   case X86::PMINUDrr:
7296   case X86::PMINUWrr:
7297   case X86::VPANDrr:
7298   case X86::VPANDYrr:
7299   case X86::VPANDDZ128rr:
7300   case X86::VPANDDZ256rr:
7301   case X86::VPANDDZrr:
7302   case X86::VPANDQZ128rr:
7303   case X86::VPANDQZ256rr:
7304   case X86::VPANDQZrr:
7305   case X86::VPORrr:
7306   case X86::VPORYrr:
7307   case X86::VPORDZ128rr:
7308   case X86::VPORDZ256rr:
7309   case X86::VPORDZrr:
7310   case X86::VPORQZ128rr:
7311   case X86::VPORQZ256rr:
7312   case X86::VPORQZrr:
7313   case X86::VPXORrr:
7314   case X86::VPXORYrr:
7315   case X86::VPXORDZ128rr:
7316   case X86::VPXORDZ256rr:
7317   case X86::VPXORDZrr:
7318   case X86::VPXORQZ128rr:
7319   case X86::VPXORQZ256rr:
7320   case X86::VPXORQZrr:
7321   case X86::VANDPDrr:
7322   case X86::VANDPSrr:
7323   case X86::VANDPDYrr:
7324   case X86::VANDPSYrr:
7325   case X86::VANDPDZ128rr:
7326   case X86::VANDPSZ128rr:
7327   case X86::VANDPDZ256rr:
7328   case X86::VANDPSZ256rr:
7329   case X86::VANDPDZrr:
7330   case X86::VANDPSZrr:
7331   case X86::VORPDrr:
7332   case X86::VORPSrr:
7333   case X86::VORPDYrr:
7334   case X86::VORPSYrr:
7335   case X86::VORPDZ128rr:
7336   case X86::VORPSZ128rr:
7337   case X86::VORPDZ256rr:
7338   case X86::VORPSZ256rr:
7339   case X86::VORPDZrr:
7340   case X86::VORPSZrr:
7341   case X86::VXORPDrr:
7342   case X86::VXORPSrr:
7343   case X86::VXORPDYrr:
7344   case X86::VXORPSYrr:
7345   case X86::VXORPDZ128rr:
7346   case X86::VXORPSZ128rr:
7347   case X86::VXORPDZ256rr:
7348   case X86::VXORPSZ256rr:
7349   case X86::VXORPDZrr:
7350   case X86::VXORPSZrr:
7351   case X86::KADDBrr:
7352   case X86::KADDWrr:
7353   case X86::KADDDrr:
7354   case X86::KADDQrr:
7355   case X86::KANDBrr:
7356   case X86::KANDWrr:
7357   case X86::KANDDrr:
7358   case X86::KANDQrr:
7359   case X86::KORBrr:
7360   case X86::KORWrr:
7361   case X86::KORDrr:
7362   case X86::KORQrr:
7363   case X86::KXORBrr:
7364   case X86::KXORWrr:
7365   case X86::KXORDrr:
7366   case X86::KXORQrr:
7367   case X86::VPADDBrr:
7368   case X86::VPADDWrr:
7369   case X86::VPADDDrr:
7370   case X86::VPADDQrr:
7371   case X86::VPADDBYrr:
7372   case X86::VPADDWYrr:
7373   case X86::VPADDDYrr:
7374   case X86::VPADDQYrr:
7375   case X86::VPADDBZ128rr:
7376   case X86::VPADDWZ128rr:
7377   case X86::VPADDDZ128rr:
7378   case X86::VPADDQZ128rr:
7379   case X86::VPADDBZ256rr:
7380   case X86::VPADDWZ256rr:
7381   case X86::VPADDDZ256rr:
7382   case X86::VPADDQZ256rr:
7383   case X86::VPADDBZrr:
7384   case X86::VPADDWZrr:
7385   case X86::VPADDDZrr:
7386   case X86::VPADDQZrr:
7387   case X86::VPMULLWrr:
7388   case X86::VPMULLWYrr:
7389   case X86::VPMULLWZ128rr:
7390   case X86::VPMULLWZ256rr:
7391   case X86::VPMULLWZrr:
7392   case X86::VPMULLDrr:
7393   case X86::VPMULLDYrr:
7394   case X86::VPMULLDZ128rr:
7395   case X86::VPMULLDZ256rr:
7396   case X86::VPMULLDZrr:
7397   case X86::VPMULLQZ128rr:
7398   case X86::VPMULLQZ256rr:
7399   case X86::VPMULLQZrr:
7400   case X86::VPMAXSBrr:
7401   case X86::VPMAXSBYrr:
7402   case X86::VPMAXSBZ128rr:
7403   case X86::VPMAXSBZ256rr:
7404   case X86::VPMAXSBZrr:
7405   case X86::VPMAXSDrr:
7406   case X86::VPMAXSDYrr:
7407   case X86::VPMAXSDZ128rr:
7408   case X86::VPMAXSDZ256rr:
7409   case X86::VPMAXSDZrr:
7410   case X86::VPMAXSQZ128rr:
7411   case X86::VPMAXSQZ256rr:
7412   case X86::VPMAXSQZrr:
7413   case X86::VPMAXSWrr:
7414   case X86::VPMAXSWYrr:
7415   case X86::VPMAXSWZ128rr:
7416   case X86::VPMAXSWZ256rr:
7417   case X86::VPMAXSWZrr:
7418   case X86::VPMAXUBrr:
7419   case X86::VPMAXUBYrr:
7420   case X86::VPMAXUBZ128rr:
7421   case X86::VPMAXUBZ256rr:
7422   case X86::VPMAXUBZrr:
7423   case X86::VPMAXUDrr:
7424   case X86::VPMAXUDYrr:
7425   case X86::VPMAXUDZ128rr:
7426   case X86::VPMAXUDZ256rr:
7427   case X86::VPMAXUDZrr:
7428   case X86::VPMAXUQZ128rr:
7429   case X86::VPMAXUQZ256rr:
7430   case X86::VPMAXUQZrr:
7431   case X86::VPMAXUWrr:
7432   case X86::VPMAXUWYrr:
7433   case X86::VPMAXUWZ128rr:
7434   case X86::VPMAXUWZ256rr:
7435   case X86::VPMAXUWZrr:
7436   case X86::VPMINSBrr:
7437   case X86::VPMINSBYrr:
7438   case X86::VPMINSBZ128rr:
7439   case X86::VPMINSBZ256rr:
7440   case X86::VPMINSBZrr:
7441   case X86::VPMINSDrr:
7442   case X86::VPMINSDYrr:
7443   case X86::VPMINSDZ128rr:
7444   case X86::VPMINSDZ256rr:
7445   case X86::VPMINSDZrr:
7446   case X86::VPMINSQZ128rr:
7447   case X86::VPMINSQZ256rr:
7448   case X86::VPMINSQZrr:
7449   case X86::VPMINSWrr:
7450   case X86::VPMINSWYrr:
7451   case X86::VPMINSWZ128rr:
7452   case X86::VPMINSWZ256rr:
7453   case X86::VPMINSWZrr:
7454   case X86::VPMINUBrr:
7455   case X86::VPMINUBYrr:
7456   case X86::VPMINUBZ128rr:
7457   case X86::VPMINUBZ256rr:
7458   case X86::VPMINUBZrr:
7459   case X86::VPMINUDrr:
7460   case X86::VPMINUDYrr:
7461   case X86::VPMINUDZ128rr:
7462   case X86::VPMINUDZ256rr:
7463   case X86::VPMINUDZrr:
7464   case X86::VPMINUQZ128rr:
7465   case X86::VPMINUQZ256rr:
7466   case X86::VPMINUQZrr:
7467   case X86::VPMINUWrr:
7468   case X86::VPMINUWYrr:
7469   case X86::VPMINUWZ128rr:
7470   case X86::VPMINUWZ256rr:
7471   case X86::VPMINUWZrr:
7472   // Normal min/max instructions are not commutative because of NaN and signed
7473   // zero semantics, but these are. Thus, there's no need to check for global
7474   // relaxed math; the instructions themselves have the properties we need.
7475   case X86::MAXCPDrr:
7476   case X86::MAXCPSrr:
7477   case X86::MAXCSDrr:
7478   case X86::MAXCSSrr:
7479   case X86::MINCPDrr:
7480   case X86::MINCPSrr:
7481   case X86::MINCSDrr:
7482   case X86::MINCSSrr:
7483   case X86::VMAXCPDrr:
7484   case X86::VMAXCPSrr:
7485   case X86::VMAXCPDYrr:
7486   case X86::VMAXCPSYrr:
7487   case X86::VMAXCPDZ128rr:
7488   case X86::VMAXCPSZ128rr:
7489   case X86::VMAXCPDZ256rr:
7490   case X86::VMAXCPSZ256rr:
7491   case X86::VMAXCPDZrr:
7492   case X86::VMAXCPSZrr:
7493   case X86::VMAXCSDrr:
7494   case X86::VMAXCSSrr:
7495   case X86::VMAXCSDZrr:
7496   case X86::VMAXCSSZrr:
7497   case X86::VMINCPDrr:
7498   case X86::VMINCPSrr:
7499   case X86::VMINCPDYrr:
7500   case X86::VMINCPSYrr:
7501   case X86::VMINCPDZ128rr:
7502   case X86::VMINCPSZ128rr:
7503   case X86::VMINCPDZ256rr:
7504   case X86::VMINCPSZ256rr:
7505   case X86::VMINCPDZrr:
7506   case X86::VMINCPSZrr:
7507   case X86::VMINCSDrr:
7508   case X86::VMINCSSrr:
7509   case X86::VMINCSDZrr:
7510   case X86::VMINCSSZrr:
7511     return true;
7512   case X86::ADDPDrr:
7513   case X86::ADDPSrr:
7514   case X86::ADDSDrr:
7515   case X86::ADDSSrr:
7516   case X86::MULPDrr:
7517   case X86::MULPSrr:
7518   case X86::MULSDrr:
7519   case X86::MULSSrr:
7520   case X86::VADDPDrr:
7521   case X86::VADDPSrr:
7522   case X86::VADDPDYrr:
7523   case X86::VADDPSYrr:
7524   case X86::VADDPDZ128rr:
7525   case X86::VADDPSZ128rr:
7526   case X86::VADDPDZ256rr:
7527   case X86::VADDPSZ256rr:
7528   case X86::VADDPDZrr:
7529   case X86::VADDPSZrr:
7530   case X86::VADDSDrr:
7531   case X86::VADDSSrr:
7532   case X86::VADDSDZrr:
7533   case X86::VADDSSZrr:
7534   case X86::VMULPDrr:
7535   case X86::VMULPSrr:
7536   case X86::VMULPDYrr:
7537   case X86::VMULPSYrr:
7538   case X86::VMULPDZ128rr:
7539   case X86::VMULPSZ128rr:
7540   case X86::VMULPDZ256rr:
7541   case X86::VMULPSZ256rr:
7542   case X86::VMULPDZrr:
7543   case X86::VMULPSZrr:
7544   case X86::VMULSDrr:
7545   case X86::VMULSSrr:
7546   case X86::VMULSDZrr:
7547   case X86::VMULSSZrr:
7548     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7549   default:
7550     return false;
7551   }
7552 }
7553 
7554 /// If \p DescribedReg overlaps with the MOVrr instruction's destination
7555 /// register then, if possible, describe the value in terms of the source
7556 /// register.
7557 static Optional<ParamLoadedValue>
7558 describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
7559                          const TargetRegisterInfo *TRI) {
7560   Register DestReg = MI.getOperand(0).getReg();
7561   Register SrcReg = MI.getOperand(1).getReg();
7562 
7563   auto Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
7564 
7565   // If the described register is the destination, just return the source.
7566   if (DestReg == DescribedReg)
7567     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
7568 
7569   // If the described register is a sub-register of the destination register,
7570   // then pick out the source register's corresponding sub-register.
7571   if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) {
7572     unsigned SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx);
7573     return ParamLoadedValue(MachineOperand::CreateReg(SrcSubReg, false), Expr);
7574   }
7575 
7576   // The remaining case to consider is when the described register is a
7577   // super-register of the destination register. MOV8rr and MOV16rr does not
7578   // write to any of the other bytes in the register, meaning that we'd have to
7579   // describe the value using a combination of the source register and the
7580   // non-overlapping bits in the described register, which is not currently
7581   // possible.
7582   if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
7583       !TRI->isSuperRegister(DestReg, DescribedReg))
7584     return None;
7585 
7586   assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
7587   return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
7588 }
7589 
7590 Optional<ParamLoadedValue>
7591 X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
7592   const MachineOperand *Op = nullptr;
7593   DIExpression *Expr = nullptr;
7594 
7595   const TargetRegisterInfo *TRI = &getRegisterInfo();
7596 
7597   switch (MI.getOpcode()) {
7598   case X86::LEA32r:
7599   case X86::LEA64r:
7600   case X86::LEA64_32r: {
7601     // We may need to describe a 64-bit parameter with a 32-bit LEA.
7602     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
7603       return None;
7604 
7605     // Operand 4 could be global address. For now we do not support
7606     // such situation.
7607     if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
7608       return None;
7609 
7610     const MachineOperand &Op1 = MI.getOperand(1);
7611     const MachineOperand &Op2 = MI.getOperand(3);
7612     assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
7613                            Register::isPhysicalRegister(Op2.getReg())));
7614 
7615     // Omit situations like:
7616     // %rsi = lea %rsi, 4, ...
7617     if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
7618         Op2.getReg() == MI.getOperand(0).getReg())
7619       return None;
7620     else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
7621               TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
7622              (Op2.getReg() != X86::NoRegister &&
7623               TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
7624       return None;
7625 
7626     int64_t Coef = MI.getOperand(2).getImm();
7627     int64_t Offset = MI.getOperand(4).getImm();
7628     SmallVector<uint64_t, 8> Ops;
7629 
7630     if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
7631       Op = &Op1;
7632     } else if (Op1.isFI())
7633       Op = &Op1;
7634 
7635     if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
7636       Ops.push_back(dwarf::DW_OP_constu);
7637       Ops.push_back(Coef + 1);
7638       Ops.push_back(dwarf::DW_OP_mul);
7639     } else {
7640       if (Op && Op2.getReg() != X86::NoRegister) {
7641         int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
7642         if (dwarfReg < 0)
7643           return None;
7644         else if (dwarfReg < 32) {
7645           Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
7646           Ops.push_back(0);
7647         } else {
7648           Ops.push_back(dwarf::DW_OP_bregx);
7649           Ops.push_back(dwarfReg);
7650           Ops.push_back(0);
7651         }
7652       } else if (!Op) {
7653         assert(Op2.getReg() != X86::NoRegister);
7654         Op = &Op2;
7655       }
7656 
7657       if (Coef > 1) {
7658         assert(Op2.getReg() != X86::NoRegister);
7659         Ops.push_back(dwarf::DW_OP_constu);
7660         Ops.push_back(Coef);
7661         Ops.push_back(dwarf::DW_OP_mul);
7662       }
7663 
7664       if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
7665           Op2.getReg() != X86::NoRegister) {
7666         Ops.push_back(dwarf::DW_OP_plus);
7667       }
7668     }
7669 
7670     DIExpression::appendOffset(Ops, Offset);
7671     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
7672 
7673     return ParamLoadedValue(*Op, Expr);;
7674   }
7675   case X86::MOV32ri:
7676   case X86::MOV64ri:
7677   case X86::MOV64ri32:
7678     // MOV32ri may be used for producing zero-extended 32-bit immediates in
7679     // 64-bit parameters, so we need to consider super-registers.
7680     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
7681       return None;
7682     return ParamLoadedValue(MI.getOperand(1), Expr);
7683   case X86::MOV8rr:
7684   case X86::MOV16rr:
7685   case X86::MOV32rr:
7686   case X86::MOV64rr:
7687     return describeMOVrrLoadedValue(MI, Reg, TRI);
7688   case X86::XOR32rr: {
7689     // 64-bit parameters are zero-materialized using XOR32rr, so also consider
7690     // super-registers.
7691     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
7692       return None;
7693     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
7694       return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
7695     return None;
7696   }
7697   case X86::MOVSX64rr32: {
7698     // We may need to describe the lower 32 bits of the MOVSX; for example, in
7699     // cases like this:
7700     //
7701     //  $ebx = [...]
7702     //  $rdi = MOVSX64rr32 $ebx
7703     //  $esi = MOV32rr $edi
7704     if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg))
7705       return None;
7706 
7707     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
7708 
7709     // If the described register is the destination register we need to
7710     // sign-extend the source register from 32 bits. The other case we handle
7711     // is when the described register is the 32-bit sub-register of the
7712     // destination register, in case we just need to return the source
7713     // register.
7714     if (Reg == MI.getOperand(0).getReg())
7715       Expr = DIExpression::appendExt(Expr, 32, 64, true);
7716     else
7717       assert(X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg) &&
7718              "Unhandled sub-register case for MOVSX64rr32");
7719 
7720     return ParamLoadedValue(MI.getOperand(1), Expr);
7721   }
7722   default:
7723     assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
7724     return TargetInstrInfo::describeLoadedValue(MI, Reg);
7725   }
7726 }
7727 
7728 /// This is an architecture-specific helper function of reassociateOps.
7729 /// Set special operand attributes for new instructions after reassociation.
7730 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7731                                          MachineInstr &OldMI2,
7732                                          MachineInstr &NewMI1,
7733                                          MachineInstr &NewMI2) const {
7734   // Integer instructions may define an implicit EFLAGS dest register operand.
7735   MachineOperand *OldFlagDef1 = OldMI1.findRegisterDefOperand(X86::EFLAGS);
7736   MachineOperand *OldFlagDef2 = OldMI2.findRegisterDefOperand(X86::EFLAGS);
7737 
7738   assert(!OldFlagDef1 == !OldFlagDef2 &&
7739          "Unexpected instruction type for reassociation");
7740 
7741   if (!OldFlagDef1 || !OldFlagDef2)
7742     return;
7743 
7744   assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
7745          "Must have dead EFLAGS operand in reassociable instruction");
7746 
7747   MachineOperand *NewFlagDef1 = NewMI1.findRegisterDefOperand(X86::EFLAGS);
7748   MachineOperand *NewFlagDef2 = NewMI2.findRegisterDefOperand(X86::EFLAGS);
7749 
7750   assert(NewFlagDef1 && NewFlagDef2 &&
7751          "Unexpected operand in reassociable instruction");
7752 
7753   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7754   // of this pass or other passes. The EFLAGS operands must be dead in these new
7755   // instructions because the EFLAGS operands in the original instructions must
7756   // be dead in order for reassociation to occur.
7757   NewFlagDef1->setIsDead();
7758   NewFlagDef2->setIsDead();
7759 }
7760 
7761 std::pair<unsigned, unsigned>
7762 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7763   return std::make_pair(TF, 0u);
7764 }
7765 
7766 ArrayRef<std::pair<unsigned, const char *>>
7767 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7768   using namespace X86II;
7769   static const std::pair<unsigned, const char *> TargetFlags[] = {
7770       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7771       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7772       {MO_GOT, "x86-got"},
7773       {MO_GOTOFF, "x86-gotoff"},
7774       {MO_GOTPCREL, "x86-gotpcrel"},
7775       {MO_PLT, "x86-plt"},
7776       {MO_TLSGD, "x86-tlsgd"},
7777       {MO_TLSLD, "x86-tlsld"},
7778       {MO_TLSLDM, "x86-tlsldm"},
7779       {MO_GOTTPOFF, "x86-gottpoff"},
7780       {MO_INDNTPOFF, "x86-indntpoff"},
7781       {MO_TPOFF, "x86-tpoff"},
7782       {MO_DTPOFF, "x86-dtpoff"},
7783       {MO_NTPOFF, "x86-ntpoff"},
7784       {MO_GOTNTPOFF, "x86-gotntpoff"},
7785       {MO_DLLIMPORT, "x86-dllimport"},
7786       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7787       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7788       {MO_TLVP, "x86-tlvp"},
7789       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7790       {MO_SECREL, "x86-secrel"},
7791       {MO_COFFSTUB, "x86-coffstub"}};
7792   return makeArrayRef(TargetFlags);
7793 }
7794 
7795 namespace {
7796   /// Create Global Base Reg pass. This initializes the PIC
7797   /// global base register for x86-32.
7798   struct CGBR : public MachineFunctionPass {
7799     static char ID;
7800     CGBR() : MachineFunctionPass(ID) {}
7801 
7802     bool runOnMachineFunction(MachineFunction &MF) override {
7803       const X86TargetMachine *TM =
7804         static_cast<const X86TargetMachine *>(&MF.getTarget());
7805       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7806 
7807       // Don't do anything in the 64-bit small and kernel code models. They use
7808       // RIP-relative addressing for everything.
7809       if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
7810                             TM->getCodeModel() == CodeModel::Kernel))
7811         return false;
7812 
7813       // Only emit a global base reg in PIC mode.
7814       if (!TM->isPositionIndependent())
7815         return false;
7816 
7817       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7818       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7819 
7820       // If we didn't need a GlobalBaseReg, don't insert code.
7821       if (GlobalBaseReg == 0)
7822         return false;
7823 
7824       // Insert the set of GlobalBaseReg into the first MBB of the function
7825       MachineBasicBlock &FirstMBB = MF.front();
7826       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7827       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7828       MachineRegisterInfo &RegInfo = MF.getRegInfo();
7829       const X86InstrInfo *TII = STI.getInstrInfo();
7830 
7831       unsigned PC;
7832       if (STI.isPICStyleGOT())
7833         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7834       else
7835         PC = GlobalBaseReg;
7836 
7837       if (STI.is64Bit()) {
7838         if (TM->getCodeModel() == CodeModel::Medium) {
7839           // In the medium code model, use a RIP-relative LEA to materialize the
7840           // GOT.
7841           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
7842               .addReg(X86::RIP)
7843               .addImm(0)
7844               .addReg(0)
7845               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
7846               .addReg(0);
7847         } else if (TM->getCodeModel() == CodeModel::Large) {
7848           // In the large code model, we are aiming for this code, though the
7849           // register allocation may vary:
7850           //   leaq .LN$pb(%rip), %rax
7851           //   movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
7852           //   addq %rcx, %rax
7853           // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
7854           Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7855           Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7856           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
7857               .addReg(X86::RIP)
7858               .addImm(0)
7859               .addReg(0)
7860               .addSym(MF.getPICBaseSymbol())
7861               .addReg(0);
7862           std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
7863           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
7864               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7865                                  X86II::MO_PIC_BASE_OFFSET);
7866           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
7867               .addReg(PBReg, RegState::Kill)
7868               .addReg(GOTReg, RegState::Kill);
7869         } else {
7870           llvm_unreachable("unexpected code model");
7871         }
7872       } else {
7873         // Operand of MovePCtoStack is completely ignored by asm printer. It's
7874         // only used in JIT code emission as displacement to pc.
7875         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7876 
7877         // If we're using vanilla 'GOT' PIC style, we should use relative
7878         // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7879         if (STI.isPICStyleGOT()) {
7880           // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
7881           // %some_register
7882           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7883               .addReg(PC)
7884               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7885                                  X86II::MO_GOT_ABSOLUTE_ADDRESS);
7886         }
7887       }
7888 
7889       return true;
7890     }
7891 
7892     StringRef getPassName() const override {
7893       return "X86 PIC Global Base Reg Initialization";
7894     }
7895 
7896     void getAnalysisUsage(AnalysisUsage &AU) const override {
7897       AU.setPreservesCFG();
7898       MachineFunctionPass::getAnalysisUsage(AU);
7899     }
7900   };
7901 }
7902 
7903 char CGBR::ID = 0;
7904 FunctionPass*
7905 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
7906 
7907 namespace {
7908   struct LDTLSCleanup : public MachineFunctionPass {
7909     static char ID;
7910     LDTLSCleanup() : MachineFunctionPass(ID) {}
7911 
7912     bool runOnMachineFunction(MachineFunction &MF) override {
7913       if (skipFunction(MF.getFunction()))
7914         return false;
7915 
7916       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
7917       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7918         // No point folding accesses if there isn't at least two.
7919         return false;
7920       }
7921 
7922       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7923       return VisitNode(DT->getRootNode(), 0);
7924     }
7925 
7926     // Visit the dominator subtree rooted at Node in pre-order.
7927     // If TLSBaseAddrReg is non-null, then use that to replace any
7928     // TLS_base_addr instructions. Otherwise, create the register
7929     // when the first such instruction is seen, and then use it
7930     // as we encounter more instructions.
7931     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7932       MachineBasicBlock *BB = Node->getBlock();
7933       bool Changed = false;
7934 
7935       // Traverse the current block.
7936       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7937            ++I) {
7938         switch (I->getOpcode()) {
7939           case X86::TLS_base_addr32:
7940           case X86::TLS_base_addr64:
7941             if (TLSBaseAddrReg)
7942               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
7943             else
7944               I = SetRegister(*I, &TLSBaseAddrReg);
7945             Changed = true;
7946             break;
7947           default:
7948             break;
7949         }
7950       }
7951 
7952       // Visit the children of this block in the dominator tree.
7953       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7954            I != E; ++I) {
7955         Changed |= VisitNode(*I, TLSBaseAddrReg);
7956       }
7957 
7958       return Changed;
7959     }
7960 
7961     // Replace the TLS_base_addr instruction I with a copy from
7962     // TLSBaseAddrReg, returning the new instruction.
7963     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
7964                                          unsigned TLSBaseAddrReg) {
7965       MachineFunction *MF = I.getParent()->getParent();
7966       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7967       const bool is64Bit = STI.is64Bit();
7968       const X86InstrInfo *TII = STI.getInstrInfo();
7969 
7970       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7971       MachineInstr *Copy =
7972           BuildMI(*I.getParent(), I, I.getDebugLoc(),
7973                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
7974               .addReg(TLSBaseAddrReg);
7975 
7976       // Erase the TLS_base_addr instruction.
7977       I.eraseFromParent();
7978 
7979       return Copy;
7980     }
7981 
7982     // Create a virtual register in *TLSBaseAddrReg, and populate it by
7983     // inserting a copy instruction after I. Returns the new instruction.
7984     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
7985       MachineFunction *MF = I.getParent()->getParent();
7986       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7987       const bool is64Bit = STI.is64Bit();
7988       const X86InstrInfo *TII = STI.getInstrInfo();
7989 
7990       // Create a virtual register for the TLS base address.
7991       MachineRegisterInfo &RegInfo = MF->getRegInfo();
7992       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7993                                                       ? &X86::GR64RegClass
7994                                                       : &X86::GR32RegClass);
7995 
7996       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7997       MachineInstr *Next = I.getNextNode();
7998       MachineInstr *Copy =
7999           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8000                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8001               .addReg(is64Bit ? X86::RAX : X86::EAX);
8002 
8003       return Copy;
8004     }
8005 
8006     StringRef getPassName() const override {
8007       return "Local Dynamic TLS Access Clean-up";
8008     }
8009 
8010     void getAnalysisUsage(AnalysisUsage &AU) const override {
8011       AU.setPreservesCFG();
8012       AU.addRequired<MachineDominatorTree>();
8013       MachineFunctionPass::getAnalysisUsage(AU);
8014     }
8015   };
8016 }
8017 
8018 char LDTLSCleanup::ID = 0;
8019 FunctionPass*
8020 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
8021 
8022 /// Constants defining how certain sequences should be outlined.
8023 ///
8024 /// \p MachineOutlinerDefault implies that the function is called with a call
8025 /// instruction, and a return must be emitted for the outlined function frame.
8026 ///
8027 /// That is,
8028 ///
8029 /// I1                                 OUTLINED_FUNCTION:
8030 /// I2 --> call OUTLINED_FUNCTION       I1
8031 /// I3                                  I2
8032 ///                                     I3
8033 ///                                     ret
8034 ///
8035 /// * Call construction overhead: 1 (call instruction)
8036 /// * Frame construction overhead: 1 (return instruction)
8037 ///
8038 /// \p MachineOutlinerTailCall implies that the function is being tail called.
8039 /// A jump is emitted instead of a call, and the return is already present in
8040 /// the outlined sequence. That is,
8041 ///
8042 /// I1                                 OUTLINED_FUNCTION:
8043 /// I2 --> jmp OUTLINED_FUNCTION       I1
8044 /// ret                                I2
8045 ///                                    ret
8046 ///
8047 /// * Call construction overhead: 1 (jump instruction)
8048 /// * Frame construction overhead: 0 (don't need to return)
8049 ///
8050 enum MachineOutlinerClass {
8051   MachineOutlinerDefault,
8052   MachineOutlinerTailCall
8053 };
8054 
8055 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
8056     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
8057   unsigned SequenceSize =
8058       std::accumulate(RepeatedSequenceLocs[0].front(),
8059                       std::next(RepeatedSequenceLocs[0].back()), 0,
8060                       [](unsigned Sum, const MachineInstr &MI) {
8061                         // FIXME: x86 doesn't implement getInstSizeInBytes, so
8062                         // we can't tell the cost.  Just assume each instruction
8063                         // is one byte.
8064                         if (MI.isDebugInstr() || MI.isKill())
8065                           return Sum;
8066                         return Sum + 1;
8067                       });
8068 
8069   // FIXME: Use real size in bytes for call and ret instructions.
8070   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
8071     for (outliner::Candidate &C : RepeatedSequenceLocs)
8072       C.setCallInfo(MachineOutlinerTailCall, 1);
8073 
8074     return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
8075                                       0, // Number of bytes to emit frame.
8076                                       MachineOutlinerTailCall // Type of frame.
8077     );
8078   }
8079 
8080   for (outliner::Candidate &C : RepeatedSequenceLocs)
8081     C.setCallInfo(MachineOutlinerDefault, 1);
8082 
8083   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
8084                                     MachineOutlinerDefault);
8085 }
8086 
8087 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
8088                                            bool OutlineFromLinkOnceODRs) const {
8089   const Function &F = MF.getFunction();
8090 
8091   // Does the function use a red zone? If it does, then we can't risk messing
8092   // with the stack.
8093   if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
8094     // It could have a red zone. If it does, then we don't want to touch it.
8095     const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8096     if (!X86FI || X86FI->getUsesRedZone())
8097       return false;
8098   }
8099 
8100   // If we *don't* want to outline from things that could potentially be deduped
8101   // then return false.
8102   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
8103       return false;
8104 
8105   // This function is viable for outlining, so return true.
8106   return true;
8107 }
8108 
8109 outliner::InstrType
8110 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  unsigned Flags) const {
8111   MachineInstr &MI = *MIT;
8112   // Don't allow debug values to impact outlining type.
8113   if (MI.isDebugInstr() || MI.isIndirectDebugValue())
8114     return outliner::InstrType::Invisible;
8115 
8116   // At this point, KILL instructions don't really tell us much so we can go
8117   // ahead and skip over them.
8118   if (MI.isKill())
8119     return outliner::InstrType::Invisible;
8120 
8121   // Is this a tail call? If yes, we can outline as a tail call.
8122   if (isTailCall(MI))
8123     return outliner::InstrType::Legal;
8124 
8125   // Is this the terminator of a basic block?
8126   if (MI.isTerminator() || MI.isReturn()) {
8127 
8128     // Does its parent have any successors in its MachineFunction?
8129     if (MI.getParent()->succ_empty())
8130       return outliner::InstrType::Legal;
8131 
8132     // It does, so we can't tail call it.
8133     return outliner::InstrType::Illegal;
8134   }
8135 
8136   // Don't outline anything that modifies or reads from the stack pointer.
8137   //
8138   // FIXME: There are instructions which are being manually built without
8139   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
8140   // able to remove the extra checks once those are fixed up. For example,
8141   // sometimes we might get something like %rax = POP64r 1. This won't be
8142   // caught by modifiesRegister or readsRegister even though the instruction
8143   // really ought to be formed so that modifiesRegister/readsRegister would
8144   // catch it.
8145   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
8146       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
8147       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
8148     return outliner::InstrType::Illegal;
8149 
8150   // Outlined calls change the instruction pointer, so don't read from it.
8151   if (MI.readsRegister(X86::RIP, &RI) ||
8152       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
8153       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
8154     return outliner::InstrType::Illegal;
8155 
8156   // Positions can't safely be outlined.
8157   if (MI.isPosition())
8158     return outliner::InstrType::Illegal;
8159 
8160   // Make sure none of the operands of this instruction do anything tricky.
8161   for (const MachineOperand &MOP : MI.operands())
8162     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
8163         MOP.isTargetIndex())
8164       return outliner::InstrType::Illegal;
8165 
8166   return outliner::InstrType::Legal;
8167 }
8168 
8169 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
8170                                           MachineFunction &MF,
8171                                           const outliner::OutlinedFunction &OF)
8172                                           const {
8173   // If we're a tail call, we already have a return, so don't do anything.
8174   if (OF.FrameConstructionID == MachineOutlinerTailCall)
8175     return;
8176 
8177   // We're a normal call, so our sequence doesn't have a return instruction.
8178   // Add it in.
8179   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
8180   MBB.insert(MBB.end(), retq);
8181 }
8182 
8183 MachineBasicBlock::iterator
8184 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
8185                                  MachineBasicBlock::iterator &It,
8186                                  MachineFunction &MF,
8187                                  const outliner::Candidate &C) const {
8188   // Is it a tail call?
8189   if (C.CallConstructionID == MachineOutlinerTailCall) {
8190     // Yes, just insert a JMP.
8191     It = MBB.insert(It,
8192                   BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
8193                       .addGlobalAddress(M.getNamedValue(MF.getName())));
8194   } else {
8195     // No, insert a call.
8196     It = MBB.insert(It,
8197                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
8198                       .addGlobalAddress(M.getNamedValue(MF.getName())));
8199   }
8200 
8201   return It;
8202 }
8203 
8204 #define GET_INSTRINFO_HELPERS
8205 #include "X86GenInstrInfo.inc"
8206