1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "x86-instr-info"
45 
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
48 
49 static cl::opt<bool>
50 NoFusing("disable-spill-fusing",
51          cl::desc("Disable fusing of spill code into instructions"));
52 static cl::opt<bool>
53 PrintFailedFusing("print-failed-fuse-candidates",
54                   cl::desc("Print instructions that the allocator wants to"
55                            " fuse, but the X86 backend currently can't"),
56                   cl::Hidden);
57 static cl::opt<bool>
58 ReMatPICStubLoad("remat-pic-stub-load",
59                  cl::desc("Re-materialize load from stub in PIC mode"),
60                  cl::init(false), cl::Hidden);
61 static cl::opt<unsigned>
62 PartialRegUpdateClearance("partial-reg-update-clearance",
63                           cl::desc("Clearance between two register writes "
64                                    "for inserting XOR to avoid partial "
65                                    "register update"),
66                           cl::init(64), cl::Hidden);
67 static cl::opt<unsigned>
68 UndefRegClearance("undef-reg-clearance",
69                   cl::desc("How many idle instructions we would like before "
70                            "certain undef register reads"),
71                   cl::init(128), cl::Hidden);
72 
73 enum {
74   // Select which memory operand is being unfolded.
75   // (stored in bits 0 - 3)
76   TB_INDEX_0    = 0,
77   TB_INDEX_1    = 1,
78   TB_INDEX_2    = 2,
79   TB_INDEX_3    = 3,
80   TB_INDEX_4    = 4,
81   TB_INDEX_MASK = 0xf,
82 
83   // Do not insert the reverse map (MemOp -> RegOp) into the table.
84   // This may be needed because there is a many -> one mapping.
85   TB_NO_REVERSE   = 1 << 4,
86 
87   // Do not insert the forward map (RegOp -> MemOp) into the table.
88   // This is needed for Native Client, which prohibits branch
89   // instructions from using a memory operand.
90   TB_NO_FORWARD   = 1 << 5,
91 
92   TB_FOLDED_LOAD  = 1 << 6,
93   TB_FOLDED_STORE = 1 << 7,
94 
95   // Minimum alignment required for load/store.
96   // Used for RegOp->MemOp conversion.
97   // (stored in bits 8 - 15)
98   TB_ALIGN_SHIFT = 8,
99   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
100   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
101   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
102   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
103   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
104 };
105 
106 struct X86MemoryFoldTableEntry {
107   uint16_t RegOp;
108   uint16_t MemOp;
109   uint16_t Flags;
110 };
111 
112 // Pin the vtable to this file.
113 void X86InstrInfo::anchor() {}
114 
115 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
116     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117                                                : X86::ADJCALLSTACKDOWN32),
118                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119                                                : X86::ADJCALLSTACKUP32),
120                       X86::CATCHRET,
121                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
122       Subtarget(STI), RI(STI.getTargetTriple()) {
123 
124   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
125     { X86::ADC32ri,     X86::ADC32mi,    0 },
126     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
127     { X86::ADC32rr,     X86::ADC32mr,    0 },
128     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
129     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
130     { X86::ADC64rr,     X86::ADC64mr,    0 },
131     { X86::ADD16ri,     X86::ADD16mi,    0 },
132     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
133     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
134     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
135     { X86::ADD16rr,     X86::ADD16mr,    0 },
136     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
137     { X86::ADD32ri,     X86::ADD32mi,    0 },
138     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
139     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
140     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
141     { X86::ADD32rr,     X86::ADD32mr,    0 },
142     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
143     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
144     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
145     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
146     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
147     { X86::ADD64rr,     X86::ADD64mr,    0 },
148     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
149     { X86::ADD8ri,      X86::ADD8mi,     0 },
150     { X86::ADD8rr,      X86::ADD8mr,     0 },
151     { X86::AND16ri,     X86::AND16mi,    0 },
152     { X86::AND16ri8,    X86::AND16mi8,   0 },
153     { X86::AND16rr,     X86::AND16mr,    0 },
154     { X86::AND32ri,     X86::AND32mi,    0 },
155     { X86::AND32ri8,    X86::AND32mi8,   0 },
156     { X86::AND32rr,     X86::AND32mr,    0 },
157     { X86::AND64ri32,   X86::AND64mi32,  0 },
158     { X86::AND64ri8,    X86::AND64mi8,   0 },
159     { X86::AND64rr,     X86::AND64mr,    0 },
160     { X86::AND8ri,      X86::AND8mi,     0 },
161     { X86::AND8rr,      X86::AND8mr,     0 },
162     { X86::DEC16r,      X86::DEC16m,     0 },
163     { X86::DEC32r,      X86::DEC32m,     0 },
164     { X86::DEC64r,      X86::DEC64m,     0 },
165     { X86::DEC8r,       X86::DEC8m,      0 },
166     { X86::INC16r,      X86::INC16m,     0 },
167     { X86::INC32r,      X86::INC32m,     0 },
168     { X86::INC64r,      X86::INC64m,     0 },
169     { X86::INC8r,       X86::INC8m,      0 },
170     { X86::NEG16r,      X86::NEG16m,     0 },
171     { X86::NEG32r,      X86::NEG32m,     0 },
172     { X86::NEG64r,      X86::NEG64m,     0 },
173     { X86::NEG8r,       X86::NEG8m,      0 },
174     { X86::NOT16r,      X86::NOT16m,     0 },
175     { X86::NOT32r,      X86::NOT32m,     0 },
176     { X86::NOT64r,      X86::NOT64m,     0 },
177     { X86::NOT8r,       X86::NOT8m,      0 },
178     { X86::OR16ri,      X86::OR16mi,     0 },
179     { X86::OR16ri8,     X86::OR16mi8,    0 },
180     { X86::OR16rr,      X86::OR16mr,     0 },
181     { X86::OR32ri,      X86::OR32mi,     0 },
182     { X86::OR32ri8,     X86::OR32mi8,    0 },
183     { X86::OR32rr,      X86::OR32mr,     0 },
184     { X86::OR64ri32,    X86::OR64mi32,   0 },
185     { X86::OR64ri8,     X86::OR64mi8,    0 },
186     { X86::OR64rr,      X86::OR64mr,     0 },
187     { X86::OR8ri,       X86::OR8mi,      0 },
188     { X86::OR8rr,       X86::OR8mr,      0 },
189     { X86::ROL16r1,     X86::ROL16m1,    0 },
190     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
191     { X86::ROL16ri,     X86::ROL16mi,    0 },
192     { X86::ROL32r1,     X86::ROL32m1,    0 },
193     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
194     { X86::ROL32ri,     X86::ROL32mi,    0 },
195     { X86::ROL64r1,     X86::ROL64m1,    0 },
196     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
197     { X86::ROL64ri,     X86::ROL64mi,    0 },
198     { X86::ROL8r1,      X86::ROL8m1,     0 },
199     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
200     { X86::ROL8ri,      X86::ROL8mi,     0 },
201     { X86::ROR16r1,     X86::ROR16m1,    0 },
202     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
203     { X86::ROR16ri,     X86::ROR16mi,    0 },
204     { X86::ROR32r1,     X86::ROR32m1,    0 },
205     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
206     { X86::ROR32ri,     X86::ROR32mi,    0 },
207     { X86::ROR64r1,     X86::ROR64m1,    0 },
208     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
209     { X86::ROR64ri,     X86::ROR64mi,    0 },
210     { X86::ROR8r1,      X86::ROR8m1,     0 },
211     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
212     { X86::ROR8ri,      X86::ROR8mi,     0 },
213     { X86::SAR16r1,     X86::SAR16m1,    0 },
214     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
215     { X86::SAR16ri,     X86::SAR16mi,    0 },
216     { X86::SAR32r1,     X86::SAR32m1,    0 },
217     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
218     { X86::SAR32ri,     X86::SAR32mi,    0 },
219     { X86::SAR64r1,     X86::SAR64m1,    0 },
220     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
221     { X86::SAR64ri,     X86::SAR64mi,    0 },
222     { X86::SAR8r1,      X86::SAR8m1,     0 },
223     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
224     { X86::SAR8ri,      X86::SAR8mi,     0 },
225     { X86::SBB32ri,     X86::SBB32mi,    0 },
226     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
227     { X86::SBB32rr,     X86::SBB32mr,    0 },
228     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
229     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
230     { X86::SBB64rr,     X86::SBB64mr,    0 },
231     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
232     { X86::SHL16ri,     X86::SHL16mi,    0 },
233     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
234     { X86::SHL32ri,     X86::SHL32mi,    0 },
235     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
236     { X86::SHL64ri,     X86::SHL64mi,    0 },
237     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
238     { X86::SHL8ri,      X86::SHL8mi,     0 },
239     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
240     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
241     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
242     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
243     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
244     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
245     { X86::SHR16r1,     X86::SHR16m1,    0 },
246     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
247     { X86::SHR16ri,     X86::SHR16mi,    0 },
248     { X86::SHR32r1,     X86::SHR32m1,    0 },
249     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
250     { X86::SHR32ri,     X86::SHR32mi,    0 },
251     { X86::SHR64r1,     X86::SHR64m1,    0 },
252     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
253     { X86::SHR64ri,     X86::SHR64mi,    0 },
254     { X86::SHR8r1,      X86::SHR8m1,     0 },
255     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
256     { X86::SHR8ri,      X86::SHR8mi,     0 },
257     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
258     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
259     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
260     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
261     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
262     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
263     { X86::SUB16ri,     X86::SUB16mi,    0 },
264     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
265     { X86::SUB16rr,     X86::SUB16mr,    0 },
266     { X86::SUB32ri,     X86::SUB32mi,    0 },
267     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
268     { X86::SUB32rr,     X86::SUB32mr,    0 },
269     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
270     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
271     { X86::SUB64rr,     X86::SUB64mr,    0 },
272     { X86::SUB8ri,      X86::SUB8mi,     0 },
273     { X86::SUB8rr,      X86::SUB8mr,     0 },
274     { X86::XOR16ri,     X86::XOR16mi,    0 },
275     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
276     { X86::XOR16rr,     X86::XOR16mr,    0 },
277     { X86::XOR32ri,     X86::XOR32mi,    0 },
278     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
279     { X86::XOR32rr,     X86::XOR32mr,    0 },
280     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
281     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
282     { X86::XOR64rr,     X86::XOR64mr,    0 },
283     { X86::XOR8ri,      X86::XOR8mi,     0 },
284     { X86::XOR8rr,      X86::XOR8mr,     0 }
285   };
286 
287   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
288     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
289                   Entry.RegOp, Entry.MemOp,
290                   // Index 0, folded load and store, no alignment requirement.
291                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
292   }
293 
294   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
295     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
296     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
297     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
298     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
299     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
300     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
301     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
302     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
303     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
304     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
305     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
306     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
307     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
308     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
309     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
310     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
311     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
312     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
313     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
314     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
315     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
316     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
317     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
318     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
319     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
320     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
321     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
322     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
323     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
324     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
325     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
326     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
327     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
328     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
329     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
330     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
331     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
332     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
333     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
334     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
335     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
336     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
337     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
338     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
339     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
340     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
341     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
342     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
343     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
344     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
345     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
346     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
347     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
348     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
349     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
350     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
351     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
352     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
353     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
354     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
355     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
356     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
357     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
358     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
359     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
360     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
361     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
362     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
363     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
364     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
365     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
366     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
367     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
368     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
369     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
370     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
371     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
372     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
373     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
374     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
375     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
376 
377     // AVX 128-bit versions of foldable instructions
378     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
379     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
380     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
381     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
382     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
383     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
384     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
385     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
386     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
387     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
388     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
389     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
390     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
391 
392     // AVX 256-bit foldable instructions
393     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
394     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
395     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
396     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
397     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
398     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
399 
400     // AVX-512 foldable instructions
401     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
402     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
403     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
404     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
405     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
406     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
407     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
408     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
409     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
410     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
411     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
412 
413     // AVX-512 foldable instructions (256-bit versions)
414     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
415     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
416     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
417     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
418     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
419     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
420     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
421     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
422     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
423     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
424 
425     // AVX-512 foldable instructions (128-bit versions)
426     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
427     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
428     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
429     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
430     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
431     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
432     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
433     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
434     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
435     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
436 
437     // F16C foldable instructions
438     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
439     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
440   };
441 
442   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
443     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
444                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
445   }
446 
447   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
448     { X86::BSF16rr,         X86::BSF16rm,             0 },
449     { X86::BSF32rr,         X86::BSF32rm,             0 },
450     { X86::BSF64rr,         X86::BSF64rm,             0 },
451     { X86::BSR16rr,         X86::BSR16rm,             0 },
452     { X86::BSR32rr,         X86::BSR32rm,             0 },
453     { X86::BSR64rr,         X86::BSR64rm,             0 },
454     { X86::CMP16rr,         X86::CMP16rm,             0 },
455     { X86::CMP32rr,         X86::CMP32rm,             0 },
456     { X86::CMP64rr,         X86::CMP64rm,             0 },
457     { X86::CMP8rr,          X86::CMP8rm,              0 },
458     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
459     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
460     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
461     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
462     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
463     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
464     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
465     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
466     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
467     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
468     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
469     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
470     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
471     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
472     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
473     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
474     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
475     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
476     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
477     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
478     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
479     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
480     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          0 },
481     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
482     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
483     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
484     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
485     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          0 },
486     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
487     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
488     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
489     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
490     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
491     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
492     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
493     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
494     { X86::MOV16rr,         X86::MOV16rm,             0 },
495     { X86::MOV32rr,         X86::MOV32rm,             0 },
496     { X86::MOV64rr,         X86::MOV64rm,             0 },
497     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
498     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
499     { X86::MOV8rr,          X86::MOV8rm,              0 },
500     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
501     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
502     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
503     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
504     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
505     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
506     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
507     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
508     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
509     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
510     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
511     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
512     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
513     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
514     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
515     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
516     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
517     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
518     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
519     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
520     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
521     { X86::PABSBrr,         X86::PABSBrm,             TB_ALIGN_16 },
522     { X86::PABSDrr,         X86::PABSDrm,             TB_ALIGN_16 },
523     { X86::PABSWrr,         X86::PABSWrm,             TB_ALIGN_16 },
524     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
525     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
526     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
527     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
528     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
529     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
530     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
531     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
532     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
533     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
534     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
535     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
536     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
537     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
538     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
539     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
540     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
541     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
542     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
543     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
544     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
545     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
546     { X86::RCPSSr,          X86::RCPSSm,              0 },
547     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          0 },
548     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
549     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
550     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
551     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
552     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
553     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
554     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
555     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
556     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
557     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
558     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
559     { X86::TEST16rr,        X86::TEST16rm,            0 },
560     { X86::TEST32rr,        X86::TEST32rm,            0 },
561     { X86::TEST64rr,        X86::TEST64rm,            0 },
562     { X86::TEST8rr,         X86::TEST8rm,             0 },
563     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
564     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
565     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
566 
567     // MMX version of foldable instructions
568     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
569     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
570     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
571     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
572     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
573     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
574     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
575     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
576     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
577     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
578 
579     // 3DNow! version of foldable instructions
580     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
581     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
582     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
583     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
584     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
585     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
586     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
587 
588     // AVX 128-bit versions of foldable instructions
589     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
590     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
591     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
592     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
593     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
594     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
595     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
596     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
597     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
598     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
599     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
600     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
601     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
602     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
603     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
604     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
605     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
606     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
607     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
608     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
609     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
610     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
611     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
612     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
613     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
614     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
615     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
616     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
617     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
618     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
619     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
620     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
621     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
622     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
623     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
624     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
625     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
626     { X86::VPABSBrr,        X86::VPABSBrm,            0 },
627     { X86::VPABSDrr,        X86::VPABSDrm,            0 },
628     { X86::VPABSWrr,        X86::VPABSWrm,            0 },
629     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
630     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
631     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
632     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
633     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
634     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
635     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
636     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
637     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
638     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
639     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
640     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
641     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
642     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
643     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
644     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
645     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
646     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
647     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
648     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
649     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
650     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
651     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
652     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
653     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
654     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
655     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
656     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
657     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
658     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
659     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
660     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
661     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
662 
663     // AVX 256-bit foldable instructions
664     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
665     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
666     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
667     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
668     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
669     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
670     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
671     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
672     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
673     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
674     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
675     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
676     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
677     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
678     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
679     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
680     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
681     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
682     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
683     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
684     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
685     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
686     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
687     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
688     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
689     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
690     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
691 
692     // AVX2 foldable instructions
693 
694     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
695     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
696     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
697     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
698     // so they don't need an equivalent limitation.
699     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
700     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
701     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
702     { X86::VPABSBYrr,       X86::VPABSBYrm,           0 },
703     { X86::VPABSDYrr,       X86::VPABSDYrm,           0 },
704     { X86::VPABSWYrr,       X86::VPABSWYrm,           0 },
705     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      0 },
706     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     0 },
707     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      0 },
708     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     0 },
709     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      0 },
710     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     0 },
711     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      0 },
712     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     0 },
713     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
714     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
715     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        0 },
716     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        0 },
717     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
718     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
719     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
720     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        0 },
721     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        0 },
722     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        0 },
723     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
724     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
725     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
726     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        0 },
727     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
728     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
729     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
730 
731     // XOP foldable instructions
732     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
733     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
734     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
735     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
736     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
737     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
738     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
739     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
740     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
741     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
742     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
743     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
744     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
745     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
746     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
747     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
748     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
749     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
750     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
751     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
752     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
753     { X86::VPROTBri,           X86::VPROTBmi,         0 },
754     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
755     { X86::VPROTDri,           X86::VPROTDmi,         0 },
756     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
757     { X86::VPROTQri,           X86::VPROTQmi,         0 },
758     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
759     { X86::VPROTWri,           X86::VPROTWmi,         0 },
760     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
761     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
762     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
763     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
764     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
765     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
766     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
767     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
768     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
769 
770     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
771     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
772     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
773     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
774     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
775     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
776     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
777     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
778     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
779     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
780     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
781     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
782     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
783     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
784     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
785     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
786     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
787     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
788     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
789     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
790     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
791     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
792     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
793     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
794     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
795     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
796     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
797     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
798     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
799     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
800     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
801     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
802     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
803     { X86::RORX32ri,        X86::RORX32mi,            0 },
804     { X86::RORX64ri,        X86::RORX64mi,            0 },
805     { X86::SARX32rr,        X86::SARX32rm,            0 },
806     { X86::SARX64rr,        X86::SARX64rm,            0 },
807     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
808     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
809     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
810     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
811     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
812     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
813     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
814     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
815     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
816     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
817     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
818 
819     // AVX-512 foldable instructions
820     { X86::VMOV64toPQIZrr,   X86::VMOVQI2PQIZrm,      0 },
821     { X86::VMOVDI2SSZrr,     X86::VMOVDI2SSZrm,       0 },
822     { X86::VMOVAPDZrr,       X86::VMOVAPDZrm,         TB_ALIGN_64 },
823     { X86::VMOVAPSZrr,       X86::VMOVAPSZrm,         TB_ALIGN_64 },
824     { X86::VMOVDQA32Zrr,     X86::VMOVDQA32Zrm,       TB_ALIGN_64 },
825     { X86::VMOVDQA64Zrr,     X86::VMOVDQA64Zrm,       TB_ALIGN_64 },
826     { X86::VMOVDQU8Zrr,      X86::VMOVDQU8Zrm,        0 },
827     { X86::VMOVDQU16Zrr,     X86::VMOVDQU16Zrm,       0 },
828     { X86::VMOVDQU32Zrr,     X86::VMOVDQU32Zrm,       0 },
829     { X86::VMOVDQU64Zrr,     X86::VMOVDQU64Zrm,       0 },
830     { X86::VMOVUPDZrr,       X86::VMOVUPDZrm,         0 },
831     { X86::VMOVUPSZrr,       X86::VMOVUPSZrm,         0 },
832     { X86::VPABSDZrr,        X86::VPABSDZrm,          0 },
833     { X86::VPABSQZrr,        X86::VPABSQZrm,          0 },
834     { X86::VBROADCASTSSZr,   X86::VBROADCASTSSZm,     TB_NO_REVERSE },
835     { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm,     TB_NO_REVERSE },
836     { X86::VBROADCASTSDZr,   X86::VBROADCASTSDZm,     TB_NO_REVERSE },
837     { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm,     TB_NO_REVERSE },
838 
839     // AVX-512 foldable instructions (256-bit versions)
840     { X86::VMOVAPDZ256rr,        X86::VMOVAPDZ256rm,        TB_ALIGN_32 },
841     { X86::VMOVAPSZ256rr,        X86::VMOVAPSZ256rm,        TB_ALIGN_32 },
842     { X86::VMOVDQA32Z256rr,      X86::VMOVDQA32Z256rm,      TB_ALIGN_32 },
843     { X86::VMOVDQA64Z256rr,      X86::VMOVDQA64Z256rm,      TB_ALIGN_32 },
844     { X86::VMOVDQU8Z256rr,       X86::VMOVDQU8Z256rm,       0 },
845     { X86::VMOVDQU16Z256rr,      X86::VMOVDQU16Z256rm,      0 },
846     { X86::VMOVDQU32Z256rr,      X86::VMOVDQU32Z256rm,      0 },
847     { X86::VMOVDQU64Z256rr,      X86::VMOVDQU64Z256rm,      0 },
848     { X86::VMOVUPDZ256rr,        X86::VMOVUPDZ256rm,        0 },
849     { X86::VMOVUPSZ256rr,        X86::VMOVUPSZ256rm,        0 },
850     { X86::VBROADCASTSSZ256r,    X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
851     { X86::VBROADCASTSSZ256r_s,  X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
852     { X86::VBROADCASTSDZ256r,    X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
853     { X86::VBROADCASTSDZ256r_s,  X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
854 
855     // AVX-512 foldable instructions (128-bit versions)
856     { X86::VMOVAPDZ128rr,        X86::VMOVAPDZ128rm,        TB_ALIGN_16 },
857     { X86::VMOVAPSZ128rr,        X86::VMOVAPSZ128rm,        TB_ALIGN_16 },
858     { X86::VMOVDQA32Z128rr,      X86::VMOVDQA32Z128rm,      TB_ALIGN_16 },
859     { X86::VMOVDQA64Z128rr,      X86::VMOVDQA64Z128rm,      TB_ALIGN_16 },
860     { X86::VMOVDQU8Z128rr,       X86::VMOVDQU8Z128rm,       0 },
861     { X86::VMOVDQU16Z128rr,      X86::VMOVDQU16Z128rm,      0 },
862     { X86::VMOVDQU32Z128rr,      X86::VMOVDQU32Z128rm,      0 },
863     { X86::VMOVDQU64Z128rr,      X86::VMOVDQU64Z128rm,      0 },
864     { X86::VMOVUPDZ128rr,        X86::VMOVUPDZ128rm,        0 },
865     { X86::VMOVUPSZ128rr,        X86::VMOVUPSZ128rm,        0 },
866     { X86::VBROADCASTSSZ128r,    X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
867     { X86::VBROADCASTSSZ128r_s,  X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
868     // F16C foldable instructions
869     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
870     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
871 
872     // AES foldable instructions
873     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
874     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
875     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
876     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
877   };
878 
879   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
880     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
881                   Entry.RegOp, Entry.MemOp,
882                   // Index 1, folded load
883                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
884   }
885 
886   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
887     { X86::ADC32rr,         X86::ADC32rm,       0 },
888     { X86::ADC64rr,         X86::ADC64rm,       0 },
889     { X86::ADD16rr,         X86::ADD16rm,       0 },
890     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
891     { X86::ADD32rr,         X86::ADD32rm,       0 },
892     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
893     { X86::ADD64rr,         X86::ADD64rm,       0 },
894     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
895     { X86::ADD8rr,          X86::ADD8rm,        0 },
896     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
897     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
898     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
899     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
900     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
901     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
902     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
903     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
904     { X86::AND16rr,         X86::AND16rm,       0 },
905     { X86::AND32rr,         X86::AND32rm,       0 },
906     { X86::AND64rr,         X86::AND64rm,       0 },
907     { X86::AND8rr,          X86::AND8rm,        0 },
908     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
909     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
910     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
911     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
912     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
913     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
914     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
915     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
916     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
917     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
918     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
919     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
920     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
921     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
922     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
923     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
924     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
925     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
926     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
927     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
928     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
929     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
930     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
931     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
932     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
933     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
934     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
935     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
936     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
937     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
938     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
939     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
940     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
941     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
942     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
943     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
944     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
945     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
946     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
947     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
948     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
949     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
950     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
951     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
952     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
953     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
954     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
955     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
956     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
957     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
958     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
959     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
960     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
961     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
962     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
963     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
964     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
965     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
966     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
967     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
968     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
969     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
970     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
971     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
972     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
973     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
974     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
975     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
976     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
977     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
978     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
979     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
980     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
981     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
982     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
983     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
984     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
985     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
986     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
987     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
988     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
989     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
990     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
991     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
992     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
993     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
994     { X86::MAXCPDrr,        X86::MAXCPDrm,      TB_ALIGN_16 },
995     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
996     { X86::MAXCPSrr,        X86::MAXCPSrm,      TB_ALIGN_16 },
997     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
998     { X86::MAXCSDrr,        X86::MAXCSDrm,      0 },
999     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
1000     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
1001     { X86::MAXCSSrr,        X86::MAXCSSrm,      0 },
1002     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
1003     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
1004     { X86::MINCPDrr,        X86::MINCPDrm,      TB_ALIGN_16 },
1005     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
1006     { X86::MINCPSrr,        X86::MINCPSrm,      TB_ALIGN_16 },
1007     { X86::MINSDrr,         X86::MINSDrm,       0 },
1008     { X86::MINCSDrr,        X86::MINCSDrm,      0 },
1009     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
1010     { X86::MINSSrr,         X86::MINSSrm,       0 },
1011     { X86::MINCSSrr,        X86::MINCSSrm,      0 },
1012     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
1013     { X86::MOVLHPSrr,       X86::MOVHPSrm,      TB_NO_REVERSE },
1014     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1015     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1016     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1017     { X86::MULSDrr,         X86::MULSDrm,       0 },
1018     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
1019     { X86::MULSSrr,         X86::MULSSrm,       0 },
1020     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
1021     { X86::OR16rr,          X86::OR16rm,        0 },
1022     { X86::OR32rr,          X86::OR32rm,        0 },
1023     { X86::OR64rr,          X86::OR64rm,        0 },
1024     { X86::OR8rr,           X86::OR8rm,         0 },
1025     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1026     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1027     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1028     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1029     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1030     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1031     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1032     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1033     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1034     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1035     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1036     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1037     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1038     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1039     { X86::PALIGNRrri,      X86::PALIGNRrmi,    TB_ALIGN_16 },
1040     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1041     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1042     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1043     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1044     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1045     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1046     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1047     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1048     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1049     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1050     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1051     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1052     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1053     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1054     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1055     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1056     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1057     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1058     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1059     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1060     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1061     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1062     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1063     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1064     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1065     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
1066     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1067     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1068     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1069     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1070     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1071     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1072     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1073     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1074     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1075     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1076     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1077     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1078     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1079     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1080     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
1081     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1082     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1083     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1084     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1085     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1086     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1087     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1088     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1089     { X86::PSIGNBrr128,     X86::PSIGNBrm128,   TB_ALIGN_16 },
1090     { X86::PSIGNWrr128,     X86::PSIGNWrm128,   TB_ALIGN_16 },
1091     { X86::PSIGNDrr128,     X86::PSIGNDrm128,   TB_ALIGN_16 },
1092     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1093     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1094     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1095     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1096     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1097     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1098     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1099     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1100     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1101     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1102     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1103     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1104     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1105     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1106     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1107     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1108     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1109     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1110     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1111     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1112     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1113     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1114     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1115     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1116     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1117     { X86::ROUNDSDr,        X86::ROUNDSDm,      0 },
1118     { X86::ROUNDSSr,        X86::ROUNDSSm,      0 },
1119     { X86::ROUNDSDr_Int,    X86::ROUNDSDm_Int,  0 },
1120     { X86::ROUNDSSr_Int,    X86::ROUNDSSm_Int,  0 },
1121     { X86::SBB32rr,         X86::SBB32rm,       0 },
1122     { X86::SBB64rr,         X86::SBB64rm,       0 },
1123     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1124     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1125     { X86::SUB16rr,         X86::SUB16rm,       0 },
1126     { X86::SUB32rr,         X86::SUB32rm,       0 },
1127     { X86::SUB64rr,         X86::SUB64rm,       0 },
1128     { X86::SUB8rr,          X86::SUB8rm,        0 },
1129     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1130     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1131     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1132     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1133     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1134     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1135     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1136     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1137     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1138     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1139     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1140     { X86::XOR16rr,         X86::XOR16rm,       0 },
1141     { X86::XOR32rr,         X86::XOR32rm,       0 },
1142     { X86::XOR64rr,         X86::XOR64rm,       0 },
1143     { X86::XOR8rr,          X86::XOR8rm,        0 },
1144     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1145     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1146 
1147     // MMX version of foldable instructions
1148     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1149     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1150     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1151     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1152     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1153     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1154     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1155     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1156     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1157     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1158     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1159     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1160     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1161     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1162     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1163     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1164     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1165     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1166     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1167     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1168     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1169     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1170     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1171     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1172     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1173     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1174     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1175     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1176     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1177     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1178     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1179     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1180     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1181     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1182     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1183     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1184     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1185     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1186     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1187     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1188     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1189     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1190     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1191     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1192     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1193     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1194     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1195     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1196     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1197     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1198     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1199     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1200     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1201     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1202     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1203     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1204     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1205     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1206     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1207     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1208     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1209     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1210     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1211     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1212     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1213     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1214     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1215     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1216     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1217     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1218 
1219     // 3DNow! version of foldable instructions
1220     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1221     { X86::PFACCrr,           X86::PFACCrm,           0 },
1222     { X86::PFADDrr,           X86::PFADDrm,           0 },
1223     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1224     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1225     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1226     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1227     { X86::PFMINrr,           X86::PFMINrm,           0 },
1228     { X86::PFMULrr,           X86::PFMULrm,           0 },
1229     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1230     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1231     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1232     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1233     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1234     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1235     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1236     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1237 
1238     // AVX 128-bit versions of foldable instructions
1239     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1240     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1241     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1242     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1243     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1244     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1245     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1246     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1247     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1248     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1249     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1250     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1251     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1252     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        0 },
1253     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1254     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      0 },
1255     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1256     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       0 },
1257     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1258     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       0 },
1259     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1260     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1261     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1262     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1263     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1264     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1265     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1266     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1267     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1268     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1269     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1270     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1271     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1272     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1273     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1274     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1275     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1276     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1277     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1278     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1279     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1280     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1281     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1282     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1283     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1284     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1285     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1286     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1287     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1288     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1289     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1290     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1291     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1292     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1293     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1294     { X86::VMAXCPDrr,         X86::VMAXCPDrm,          0 },
1295     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1296     { X86::VMAXCPSrr,         X86::VMAXCPSrm,          0 },
1297     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1298     { X86::VMAXCSDrr,         X86::VMAXCSDrm,          0 },
1299     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1300     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1301     { X86::VMAXCSSrr,         X86::VMAXCSSrm,          0 },
1302     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1303     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1304     { X86::VMINCPDrr,         X86::VMINCPDrm,          0 },
1305     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1306     { X86::VMINCPSrr,         X86::VMINCPSrm,          0 },
1307     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1308     { X86::VMINCSDrr,         X86::VMINCSDrm,          0 },
1309     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1310     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1311     { X86::VMINCSSrr,         X86::VMINCSSrm,          0 },
1312     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1313     { X86::VMOVLHPSrr,        X86::VMOVHPSrm,          TB_NO_REVERSE },
1314     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1315     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1316     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1317     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1318     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1319     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1320     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1321     { X86::VORPDrr,           X86::VORPDrm,            0 },
1322     { X86::VORPSrr,           X86::VORPSrm,            0 },
1323     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1324     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1325     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1326     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1327     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1328     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1329     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1330     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1331     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1332     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1333     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1334     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1335     { X86::VPALIGNRrri,       X86::VPALIGNRrmi,        0 },
1336     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1337     { X86::VPANDrr,           X86::VPANDrm,            0 },
1338     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1339     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1340     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1341     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1342     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1343     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1344     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1345     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1346     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1347     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1348     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1349     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1350     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1351     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1352     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1353     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1354     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1355     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1356     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1357     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1358     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1359     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1360     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1361     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1362     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1363     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1364     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1365     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1366     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1367     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1368     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1369     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1370     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1371     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1372     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1373     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1374     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1375     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1376     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1377     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1378     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1379     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1380     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1381     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1382     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1383     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1384     { X86::VPORrr,            X86::VPORrm,             0 },
1385     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1386     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1387     { X86::VPSIGNBrr128,      X86::VPSIGNBrm128,       0 },
1388     { X86::VPSIGNWrr128,      X86::VPSIGNWrm128,       0 },
1389     { X86::VPSIGNDrr128,      X86::VPSIGNDrm128,       0 },
1390     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1391     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1392     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1393     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1394     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1395     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1396     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1397     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1398     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1399     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1400     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1401     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1402     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1403     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1404     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1405     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1406     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1407     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1408     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1409     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1410     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1411     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1412     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1413     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1414     { X86::VPXORrr,           X86::VPXORrm,            0 },
1415     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1416     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1417     { X86::VROUNDSDr_Int,     X86::VROUNDSDm_Int,      0 },
1418     { X86::VROUNDSSr_Int,     X86::VROUNDSSm_Int,      0 },
1419     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1420     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1421     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1422     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1423     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1424     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1425     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1426     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1427     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1428     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1429     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1430     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1431     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1432     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1433 
1434     // AVX 256-bit foldable instructions
1435     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1436     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1437     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1438     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1439     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1440     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1441     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1442     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1443     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1444     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1445     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1446     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1447     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1448     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1449     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1450     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1451     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1452     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1453     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1454     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1455     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1456     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1457     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1458     { X86::VMAXCPDYrr,        X86::VMAXCPDYrm,         0 },
1459     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1460     { X86::VMAXCPSYrr,        X86::VMAXCPSYrm,         0 },
1461     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1462     { X86::VMINCPDYrr,        X86::VMINCPDYrm,         0 },
1463     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1464     { X86::VMINCPSYrr,        X86::VMINCPSYrm,         0 },
1465     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1466     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1467     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1468     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1469     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1470     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1471     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1472     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1473     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1474     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1475     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1476     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1477     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1478     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1479     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1480     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1481     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1482 
1483     // AVX2 foldable instructions
1484     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1485     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1486     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1487     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1488     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1489     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1490     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1491     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1492     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1493     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1494     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1495     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1496     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1497     { X86::VPALIGNRYrri,      X86::VPALIGNRYrmi,       0 },
1498     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1499     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1500     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1501     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1502     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1503     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1504     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1505     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1506     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1507     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1508     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1509     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1510     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1511     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1512     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1513     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1514     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1515     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1516     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1517     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1518     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1519     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1520     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1521     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1522     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1523     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1524     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1525     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1526     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1527     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1528     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1529     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1530     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1531     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1532     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1533     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1534     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1535     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1536     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1537     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1538     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1539     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1540     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1541     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1542     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1543     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1544     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1545     { X86::VPORYrr,           X86::VPORYrm,            0 },
1546     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1547     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1548     { X86::VPSIGNBYrr256,     X86::VPSIGNBYrm256,      0 },
1549     { X86::VPSIGNWYrr256,     X86::VPSIGNWYrm256,      0 },
1550     { X86::VPSIGNDYrr256,     X86::VPSIGNDYrm256,      0 },
1551     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1552     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1553     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1554     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1555     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1556     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1557     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1558     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1559     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1560     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1561     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1562     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1563     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1564     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1565     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1566     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1567     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1568     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1569     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1570     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1571     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1572     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1573     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1574     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1575     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1576     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1577     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1578     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1579     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1580     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1581     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1582     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1583     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1584     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1585     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1586 
1587     // FMA4 foldable patterns
1588     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1589     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1590     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1591     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1592     { X86::VFMADDPS4Yrr,      X86::VFMADDPS4Ymr,       TB_ALIGN_NONE },
1593     { X86::VFMADDPD4Yrr,      X86::VFMADDPD4Ymr,       TB_ALIGN_NONE },
1594     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1595     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1596     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1597     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1598     { X86::VFNMADDPS4Yrr,     X86::VFNMADDPS4Ymr,      TB_ALIGN_NONE },
1599     { X86::VFNMADDPD4Yrr,     X86::VFNMADDPD4Ymr,      TB_ALIGN_NONE },
1600     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1601     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1602     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1603     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1604     { X86::VFMSUBPS4Yrr,      X86::VFMSUBPS4Ymr,       TB_ALIGN_NONE },
1605     { X86::VFMSUBPD4Yrr,      X86::VFMSUBPD4Ymr,       TB_ALIGN_NONE },
1606     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1607     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1608     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1609     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1610     { X86::VFNMSUBPS4Yrr,     X86::VFNMSUBPS4Ymr,      TB_ALIGN_NONE },
1611     { X86::VFNMSUBPD4Yrr,     X86::VFNMSUBPD4Ymr,      TB_ALIGN_NONE },
1612     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1613     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1614     { X86::VFMADDSUBPS4Yrr,   X86::VFMADDSUBPS4Ymr,    TB_ALIGN_NONE },
1615     { X86::VFMADDSUBPD4Yrr,   X86::VFMADDSUBPD4Ymr,    TB_ALIGN_NONE },
1616     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1617     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1618     { X86::VFMSUBADDPS4Yrr,   X86::VFMSUBADDPS4Ymr,    TB_ALIGN_NONE },
1619     { X86::VFMSUBADDPD4Yrr,   X86::VFMSUBADDPD4Ymr,    TB_ALIGN_NONE },
1620 
1621     // XOP foldable instructions
1622     { X86::VPCMOVrrr,         X86::VPCMOVrmr,           0 },
1623     { X86::VPCMOVrrrY,        X86::VPCMOVrmrY,          0 },
1624     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1625     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1626     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1627     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1628     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1629     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1630     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1631     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1632     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1633     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1634     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1635     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1636     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1637     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1638     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1639     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1640     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1641     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1642     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1643     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1644     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1645     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1646     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1647     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1648     { X86::VPPERMrrr,         X86::VPPERMrmr,           0 },
1649     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1650     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1651     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1652     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1653     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1654     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1655     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1656     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1657     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1658     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1659     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1660     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1661 
1662     // BMI/BMI2 foldable instructions
1663     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1664     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1665     { X86::MULX32rr,          X86::MULX32rm,            0 },
1666     { X86::MULX64rr,          X86::MULX64rm,            0 },
1667     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1668     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1669     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1670     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1671 
1672     // ADX foldable instructions
1673     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1674     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1675     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1676     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1677 
1678     // AVX-512 foldable instructions
1679     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1680     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1681     { X86::VADDSSZrr,         X86::VADDSSZrm,           0 },
1682     { X86::VADDSSZrr_Int,     X86::VADDSSZrm_Int,       0 },
1683     { X86::VADDSDZrr,         X86::VADDSDZrm,           0 },
1684     { X86::VADDSDZrr_Int,     X86::VADDSDZrm_Int,       0 },
1685     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1686     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1687     { X86::VSUBSSZrr,         X86::VSUBSSZrm,           0 },
1688     { X86::VSUBSSZrr_Int,     X86::VSUBSSZrm_Int,       0 },
1689     { X86::VSUBSDZrr,         X86::VSUBSDZrm,           0 },
1690     { X86::VSUBSDZrr_Int,     X86::VSUBSDZrm_Int,       0 },
1691     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1692     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1693     { X86::VMULSSZrr,         X86::VMULSSZrm,           0 },
1694     { X86::VMULSSZrr_Int,     X86::VMULSSZrm_Int,       0 },
1695     { X86::VMULSDZrr,         X86::VMULSDZrm,           0 },
1696     { X86::VMULSDZrr_Int,     X86::VMULSDZrm_Int,       0 },
1697     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1698     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1699     { X86::VDIVSSZrr,         X86::VDIVSSZrm,           0 },
1700     { X86::VDIVSSZrr_Int,     X86::VDIVSSZrm_Int,       0 },
1701     { X86::VDIVSDZrr,         X86::VDIVSDZrm,           0 },
1702     { X86::VDIVSDZrr_Int,     X86::VDIVSDZrm_Int,       0 },
1703     { X86::VCMPPDZrri,        X86::VCMPPDZrmi,          0 },
1704     { X86::VCMPPSZrri,        X86::VCMPPSZrmi,          0 },
1705     { X86::VCMPSDZrr,         X86::VCMPSDZrm,           0 },
1706     { X86::VCMPSSZrr,         X86::VCMPSSZrm,           0 },
1707     { X86::VCMPSDZrr_Int,     X86::VCMPSDZrm_Int,       0 },
1708     { X86::VCMPSSZrr_Int,     X86::VCMPSSZrm_Int,       0 },
1709     { X86::VANDPDZrr,         X86::VANDPDZrm,           0 },
1710     { X86::VANDPSZrr,         X86::VANDPSZrm,           0 },
1711     { X86::VANDNPDZrr,        X86::VANDNPDZrm,          0 },
1712     { X86::VANDNPSZrr,        X86::VANDNPSZrm,          0 },
1713     { X86::VORPDZrr,          X86::VORPDZrm,            0 },
1714     { X86::VORPSZrr,          X86::VORPSZrm,            0 },
1715     { X86::VXORPDZrr,         X86::VXORPDZrm,           0 },
1716     { X86::VXORPSZrr,         X86::VXORPSZrm,           0 },
1717     { X86::VPANDDZrr,         X86::VPANDDZrm,           0 },
1718     { X86::VPANDQZrr,         X86::VPANDQZrm,           0 },
1719     { X86::VPANDNDZrr,        X86::VPANDNDZrm,          0 },
1720     { X86::VPANDNQZrr,        X86::VPANDNQZrm,          0 },
1721     { X86::VPORDZrr,          X86::VPORDZrm,            0 },
1722     { X86::VPORQZrr,          X86::VPORQZrm,            0 },
1723     { X86::VPXORDZrr,         X86::VPXORDZrm,           0 },
1724     { X86::VPXORQZrr,         X86::VPXORQZrm,           0 },
1725     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1726     { X86::VMAXCPDZrr,        X86::VMAXCPDZrm,          0 },
1727     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1728     { X86::VMAXCPSZrr,        X86::VMAXCPSZrm,          0 },
1729     { X86::VMAXSDZrr,         X86::VMAXSDZrm,           0 },
1730     { X86::VMAXCSDZrr,        X86::VMAXCSDZrm,          0 },
1731     { X86::VMAXSDZrr_Int,     X86::VMAXSDZrm_Int,       0 },
1732     { X86::VMAXSSZrr,         X86::VMAXSSZrm,           0 },
1733     { X86::VMAXCSSZrr,        X86::VMAXCSSZrm,          0 },
1734     { X86::VMAXSSZrr_Int,     X86::VMAXSSZrm_Int,       0 },
1735     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1736     { X86::VMINCPDZrr,        X86::VMINCPDZrm,          0 },
1737     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1738     { X86::VMINCPSZrr,        X86::VMINCPSZrm,          0 },
1739     { X86::VMINSDZrr,         X86::VMINSDZrm,           0 },
1740     { X86::VMINCSDZrr,        X86::VMINCSDZrm,          0 },
1741     { X86::VMINSDZrr_Int,     X86::VMINSDZrm_Int,       0 },
1742     { X86::VMINSSZrr,         X86::VMINSSZrm,           0 },
1743     { X86::VMINCSSZrr,        X86::VMINCSSZrm,          0 },
1744     { X86::VMINSSZrr_Int,     X86::VMINSSZrm_Int,       0 },
1745     { X86::VPADDBZrr,         X86::VPADDBZrm,           0 },
1746     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1747     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1748     { X86::VPADDSBZrr,        X86::VPADDSBZrm,          0 },
1749     { X86::VPADDSWZrr,        X86::VPADDSWZrm,          0 },
1750     { X86::VPADDUSBZrr,       X86::VPADDUSBZrm,         0 },
1751     { X86::VPADDUSWZrr,       X86::VPADDUSWZrm,         0 },
1752     { X86::VPADDWZrr,         X86::VPADDWZrm,           0 },
1753     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1754     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1755     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1756     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1757     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1758     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1759     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1760     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1761     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1762     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1763     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1764     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1765     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1766     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1767     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1768     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1769     { X86::VPSUBBZrr,         X86::VPSUBBZrm,           0 },
1770     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1771     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1772     { X86::VPSUBSBZrr,        X86::VPSUBSBZrm,          0 },
1773     { X86::VPSUBSWZrr,        X86::VPSUBSWZrm,          0 },
1774     { X86::VPSUBUSBZrr,       X86::VPSUBUSBZrm,         0 },
1775     { X86::VPSUBUSWZrr,       X86::VPSUBUSWZrm,         0 },
1776     { X86::VPSUBWZrr,         X86::VPSUBWZrm,           0 },
1777     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1778     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1779     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1780     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1781     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1782     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1783     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1784     { X86::VPCMPEQBZrr,       X86::VPCMPEQBZrm,         0 },
1785     { X86::VPCMPEQDZrr,       X86::VPCMPEQDZrm,         0 },
1786     { X86::VPCMPEQQZrr,       X86::VPCMPEQQZrm,         0 },
1787     { X86::VPCMPEQWZrr,       X86::VPCMPEQWZrm,         0 },
1788     { X86::VPCMPGTBZrr,       X86::VPCMPGTBZrm,         0 },
1789     { X86::VPCMPGTDZrr,       X86::VPCMPGTDZrm,         0 },
1790     { X86::VPCMPGTQZrr,       X86::VPCMPGTQZrm,         0 },
1791     { X86::VPCMPGTWZrr,       X86::VPCMPGTWZrm,         0 },
1792     { X86::VPCMPBZrri,        X86::VPCMPBZrmi,          0 },
1793     { X86::VPCMPDZrri,        X86::VPCMPDZrmi,          0 },
1794     { X86::VPCMPQZrri,        X86::VPCMPQZrmi,          0 },
1795     { X86::VPCMPWZrri,        X86::VPCMPWZrmi,          0 },
1796     { X86::VPCMPUBZrri,       X86::VPCMPUBZrmi,         0 },
1797     { X86::VPCMPUDZrri,       X86::VPCMPUDZrmi,         0 },
1798     { X86::VPCMPUQZrri,       X86::VPCMPUQZrmi,         0 },
1799     { X86::VPCMPUWZrri,       X86::VPCMPUWZrmi,         0 },
1800 
1801     // AVX-512{F,VL} foldable instructions
1802     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1803     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1804     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1805 
1806     // AVX-512{F,VL} foldable instructions
1807     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1808     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1809     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1810     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1811     { X86::VANDPDZ128rr,      X86::VANDPDZ128rm,        0 },
1812     { X86::VANDPDZ256rr,      X86::VANDPDZ256rm,        0 },
1813     { X86::VANDPSZ128rr,      X86::VANDPSZ128rm,        0 },
1814     { X86::VANDPSZ256rr,      X86::VANDPSZ256rm,        0 },
1815     { X86::VANDNPDZ128rr,     X86::VANDNPDZ128rm,       0 },
1816     { X86::VANDNPDZ256rr,     X86::VANDNPDZ256rm,       0 },
1817     { X86::VANDNPSZ128rr,     X86::VANDNPSZ128rm,       0 },
1818     { X86::VANDNPSZ256rr,     X86::VANDNPSZ256rm,       0 },
1819     { X86::VORPDZ128rr,       X86::VORPDZ128rm,         0 },
1820     { X86::VORPDZ256rr,       X86::VORPDZ256rm,         0 },
1821     { X86::VORPSZ128rr,       X86::VORPSZ128rm,         0 },
1822     { X86::VORPSZ256rr,       X86::VORPSZ256rm,         0 },
1823     { X86::VPANDDZ128rr,      X86::VPANDDZ128rm,        0 },
1824     { X86::VPANDDZ256rr,      X86::VPANDDZ256rm,        0 },
1825     { X86::VPANDQZ128rr,      X86::VPANDQZ128rm,        0 },
1826     { X86::VPANDQZ256rr,      X86::VPANDQZ256rm,        0 },
1827     { X86::VPANDNDZ128rr,     X86::VPANDNDZ128rm,       0 },
1828     { X86::VPANDNDZ256rr,     X86::VPANDNDZ256rm,       0 },
1829     { X86::VPANDNQZ128rr,     X86::VPANDNQZ128rm,       0 },
1830     { X86::VPANDNQZ256rr,     X86::VPANDNQZ256rm,       0 },
1831     { X86::VPORDZ128rr,       X86::VPORDZ128rm,         0 },
1832     { X86::VPORDZ256rr,       X86::VPORDZ256rm,         0 },
1833     { X86::VPORQZ128rr,       X86::VPORQZ128rm,         0 },
1834     { X86::VPORQZ256rr,       X86::VPORQZ256rm,         0 },
1835     { X86::VPXORDZ128rr,      X86::VPXORDZ128rm,        0 },
1836     { X86::VPXORDZ256rr,      X86::VPXORDZ256rm,        0 },
1837     { X86::VPXORQZ128rr,      X86::VPXORQZ128rm,        0 },
1838     { X86::VPXORQZ256rr,      X86::VPXORQZ256rm,        0 },
1839     { X86::VSUBPDZ128rr,      X86::VSUBPDZ128rm,        0 },
1840     { X86::VSUBPDZ256rr,      X86::VSUBPDZ256rm,        0 },
1841     { X86::VSUBPSZ128rr,      X86::VSUBPSZ128rm,        0 },
1842     { X86::VSUBPSZ256rr,      X86::VSUBPSZ256rm,        0 },
1843     { X86::VXORPDZ128rr,      X86::VXORPDZ128rm,        0 },
1844     { X86::VXORPDZ256rr,      X86::VXORPDZ256rm,        0 },
1845     { X86::VXORPSZ128rr,      X86::VXORPSZ128rm,        0 },
1846     { X86::VXORPSZ256rr,      X86::VXORPSZ256rm,        0 },
1847     { X86::VMAXPDZ128rr,      X86::VMAXPDZ128rm,        0 },
1848     { X86::VMAXPDZ256rr,      X86::VMAXPDZ256rm,        0 },
1849     { X86::VMAXCPDZ128rr,     X86::VMAXCPDZ128rm,       0 },
1850     { X86::VMAXCPDZ256rr,     X86::VMAXCPDZ256rm,       0 },
1851     { X86::VMAXPSZ128rr,      X86::VMAXPSZ128rm,        0 },
1852     { X86::VMAXPSZ256rr,      X86::VMAXPSZ256rm,        0 },
1853     { X86::VMAXCPSZ128rr,     X86::VMAXCPSZ128rm,       0 },
1854     { X86::VMAXCPSZ256rr,     X86::VMAXCPSZ256rm,       0 },
1855     { X86::VMINPDZ128rr,      X86::VMINPDZ128rm,        0 },
1856     { X86::VMINPDZ256rr,      X86::VMINPDZ256rm,        0 },
1857     { X86::VMINCPDZ128rr,     X86::VMINCPDZ128rm,       0 },
1858     { X86::VMINCPDZ256rr,     X86::VMINCPDZ256rm,       0 },
1859     { X86::VMINPSZ128rr,      X86::VMINPSZ128rm,        0 },
1860     { X86::VMINPSZ256rr,      X86::VMINPSZ256rm,        0 },
1861     { X86::VMINCPSZ128rr,     X86::VMINCPSZ128rm,       0 },
1862     { X86::VMINCPSZ256rr,     X86::VMINCPSZ256rm,       0 },
1863     { X86::VCMPPDZ128rri,     X86::VCMPPDZ128rmi,       0 },
1864     { X86::VCMPPDZ256rri,     X86::VCMPPDZ256rmi,       0 },
1865     { X86::VCMPPSZ128rri,     X86::VCMPPSZ128rmi,       0 },
1866     { X86::VCMPPSZ256rri,     X86::VCMPPSZ256rmi,       0 },
1867     { X86::VPCMPEQBZ128rr,    X86::VPCMPEQBZ128rm,      0 },
1868     { X86::VPCMPEQBZ256rr,    X86::VPCMPEQBZ256rm,      0 },
1869     { X86::VPCMPEQDZ128rr,    X86::VPCMPEQDZ128rm,      0 },
1870     { X86::VPCMPEQDZ256rr,    X86::VPCMPEQDZ256rm,      0 },
1871     { X86::VPCMPEQQZ128rr,    X86::VPCMPEQQZ128rm,      0 },
1872     { X86::VPCMPEQQZ256rr,    X86::VPCMPEQQZ256rm,      0 },
1873     { X86::VPCMPEQWZ128rr,    X86::VPCMPEQWZ128rm,      0 },
1874     { X86::VPCMPEQWZ256rr,    X86::VPCMPEQWZ256rm,      0 },
1875     { X86::VPCMPGTBZ128rr,    X86::VPCMPGTBZ128rm,      0 },
1876     { X86::VPCMPGTBZ256rr,    X86::VPCMPGTBZ256rm,      0 },
1877     { X86::VPCMPGTDZ128rr,    X86::VPCMPGTDZ128rm,      0 },
1878     { X86::VPCMPGTDZ256rr,    X86::VPCMPGTDZ256rm,      0 },
1879     { X86::VPCMPGTQZ128rr,    X86::VPCMPGTQZ128rm,      0 },
1880     { X86::VPCMPGTQZ256rr,    X86::VPCMPGTQZ256rm,      0 },
1881     { X86::VPCMPGTWZ128rr,    X86::VPCMPGTWZ128rm,      0 },
1882     { X86::VPCMPGTWZ256rr,    X86::VPCMPGTWZ256rm,      0 },
1883     { X86::VPCMPBZ128rri,     X86::VPCMPBZ128rmi,       0 },
1884     { X86::VPCMPBZ256rri,     X86::VPCMPBZ256rmi,       0 },
1885     { X86::VPCMPDZ128rri,     X86::VPCMPDZ128rmi,       0 },
1886     { X86::VPCMPDZ256rri,     X86::VPCMPDZ256rmi,       0 },
1887     { X86::VPCMPQZ128rri,     X86::VPCMPQZ128rmi,       0 },
1888     { X86::VPCMPQZ256rri,     X86::VPCMPQZ256rmi,       0 },
1889     { X86::VPCMPWZ128rri,     X86::VPCMPWZ128rmi,       0 },
1890     { X86::VPCMPWZ256rri,     X86::VPCMPWZ256rmi,       0 },
1891     { X86::VPCMPUBZ128rri,    X86::VPCMPUBZ128rmi,      0 },
1892     { X86::VPCMPUBZ256rri,    X86::VPCMPUBZ256rmi,      0 },
1893     { X86::VPCMPUDZ128rri,    X86::VPCMPUDZ128rmi,      0 },
1894     { X86::VPCMPUDZ256rri,    X86::VPCMPUDZ256rmi,      0 },
1895     { X86::VPCMPUQZ128rri,    X86::VPCMPUQZ128rmi,      0 },
1896     { X86::VPCMPUQZ256rri,    X86::VPCMPUQZ256rmi,      0 },
1897     { X86::VPCMPUWZ128rri,    X86::VPCMPUWZ128rmi,      0 },
1898     { X86::VPCMPUWZ256rri,    X86::VPCMPUWZ256rmi,      0 },
1899     { X86::VPADDBZ128rr,      X86::VPADDBZ128rm,        0 },
1900     { X86::VPADDBZ256rr,      X86::VPADDBZ256rm,        0 },
1901     { X86::VPADDDZ128rr,      X86::VPADDDZ128rm,        0 },
1902     { X86::VPADDDZ256rr,      X86::VPADDDZ256rm,        0 },
1903     { X86::VPADDQZ128rr,      X86::VPADDQZ128rm,        0 },
1904     { X86::VPADDQZ256rr,      X86::VPADDQZ256rm,        0 },
1905     { X86::VPADDSBZ128rr,     X86::VPADDSBZ128rm,       0 },
1906     { X86::VPADDSBZ256rr,     X86::VPADDSBZ256rm,       0 },
1907     { X86::VPADDSWZ128rr,     X86::VPADDSWZ128rm,       0 },
1908     { X86::VPADDSWZ256rr,     X86::VPADDSWZ256rm,       0 },
1909     { X86::VPADDUSBZ128rr,    X86::VPADDUSBZ128rm,      0 },
1910     { X86::VPADDUSBZ256rr,    X86::VPADDUSBZ256rm,      0 },
1911     { X86::VPADDUSWZ128rr,    X86::VPADDUSWZ128rm,      0 },
1912     { X86::VPADDUSWZ256rr,    X86::VPADDUSWZ256rm,      0 },
1913     { X86::VPADDWZ128rr,      X86::VPADDWZ128rm,        0 },
1914     { X86::VPADDWZ256rr,      X86::VPADDWZ256rm,        0 },
1915     { X86::VPSUBBZ128rr,      X86::VPSUBBZ128rm,        0 },
1916     { X86::VPSUBBZ256rr,      X86::VPSUBBZ256rm,        0 },
1917     { X86::VPSUBDZ128rr,      X86::VPSUBDZ128rm,        0 },
1918     { X86::VPSUBDZ256rr,      X86::VPSUBDZ256rm,        0 },
1919     { X86::VPSUBQZ128rr,      X86::VPSUBQZ128rm,        0 },
1920     { X86::VPSUBQZ256rr,      X86::VPSUBQZ256rm,        0 },
1921     { X86::VPSUBSBZ128rr,     X86::VPSUBSBZ128rm,       0 },
1922     { X86::VPSUBSBZ256rr,     X86::VPSUBSBZ256rm,       0 },
1923     { X86::VPSUBSWZ128rr,     X86::VPSUBSWZ128rm,       0 },
1924     { X86::VPSUBSWZ256rr,     X86::VPSUBSWZ256rm,       0 },
1925     { X86::VPSUBUSBZ128rr,    X86::VPSUBUSBZ128rm,      0 },
1926     { X86::VPSUBUSBZ256rr,    X86::VPSUBUSBZ256rm,      0 },
1927     { X86::VPSUBUSWZ128rr,    X86::VPSUBUSWZ128rm,      0 },
1928     { X86::VPSUBUSWZ256rr,    X86::VPSUBUSWZ256rm,      0 },
1929     { X86::VPSUBWZ128rr,      X86::VPSUBWZ128rm,        0 },
1930     { X86::VPSUBWZ256rr,      X86::VPSUBWZ256rm,        0 },
1931 
1932     // AES foldable instructions
1933     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1934     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1935     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1936     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1937     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
1938     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
1939     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
1940     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
1941 
1942     // SHA foldable instructions
1943     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1944     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1945     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1946     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1947     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1948     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1949     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
1950   };
1951 
1952   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
1953     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1954                   Entry.RegOp, Entry.MemOp,
1955                   // Index 2, folded load
1956                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1957   }
1958 
1959   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1960     // FMA4 foldable patterns
1961     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
1962     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
1963     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
1964     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
1965     { X86::VFMADDPS4Yrr,          X86::VFMADDPS4Yrm,          TB_ALIGN_NONE },
1966     { X86::VFMADDPD4Yrr,          X86::VFMADDPD4Yrm,          TB_ALIGN_NONE },
1967     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
1968     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
1969     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
1970     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
1971     { X86::VFNMADDPS4Yrr,         X86::VFNMADDPS4Yrm,         TB_ALIGN_NONE },
1972     { X86::VFNMADDPD4Yrr,         X86::VFNMADDPD4Yrm,         TB_ALIGN_NONE },
1973     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
1974     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
1975     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
1976     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
1977     { X86::VFMSUBPS4Yrr,          X86::VFMSUBPS4Yrm,          TB_ALIGN_NONE },
1978     { X86::VFMSUBPD4Yrr,          X86::VFMSUBPD4Yrm,          TB_ALIGN_NONE },
1979     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
1980     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
1981     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
1982     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
1983     { X86::VFNMSUBPS4Yrr,         X86::VFNMSUBPS4Yrm,         TB_ALIGN_NONE },
1984     { X86::VFNMSUBPD4Yrr,         X86::VFNMSUBPD4Yrm,         TB_ALIGN_NONE },
1985     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
1986     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
1987     { X86::VFMADDSUBPS4Yrr,       X86::VFMADDSUBPS4Yrm,       TB_ALIGN_NONE },
1988     { X86::VFMADDSUBPD4Yrr,       X86::VFMADDSUBPD4Yrm,       TB_ALIGN_NONE },
1989     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
1990     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
1991     { X86::VFMSUBADDPS4Yrr,       X86::VFMSUBADDPS4Yrm,       TB_ALIGN_NONE },
1992     { X86::VFMSUBADDPD4Yrr,       X86::VFMSUBADDPD4Yrm,       TB_ALIGN_NONE },
1993 
1994     // XOP foldable instructions
1995     { X86::VPCMOVrrr,             X86::VPCMOVrrm,             0 },
1996     { X86::VPCMOVrrrY,            X86::VPCMOVrrmY,            0 },
1997     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
1998     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
1999     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
2000     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
2001     { X86::VPPERMrrr,             X86::VPPERMrrm,             0 },
2002 
2003     // AVX-512 VPERMI instructions with 3 source operands.
2004     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
2005     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
2006     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
2007     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
2008     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
2009     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
2010     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
2011     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
2012     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
2013     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
2014     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
2015     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
2016     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
2017      // AVX-512 arithmetic instructions
2018     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
2019     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
2020     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
2021     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
2022     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
2023     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
2024     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
2025     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
2026     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
2027     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
2028     { X86::VMINCPSZrrkz,          X86::VMINCPSZrmkz,          0 },
2029     { X86::VMINCPDZrrkz,          X86::VMINCPDZrmkz,          0 },
2030     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
2031     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
2032     { X86::VMAXCPSZrrkz,          X86::VMAXCPSZrmkz,          0 },
2033     { X86::VMAXCPDZrrkz,          X86::VMAXCPDZrmkz,          0 },
2034     { X86::VANDPDZrrkz,           X86::VANDPDZrmkz,           0 },
2035     { X86::VANDPSZrrkz,           X86::VANDPSZrmkz,           0 },
2036     { X86::VANDNPDZrrkz,          X86::VANDNPDZrmkz,          0 },
2037     { X86::VANDNPSZrrkz,          X86::VANDNPSZrmkz,          0 },
2038     { X86::VORPDZrrkz,            X86::VORPDZrmkz,            0 },
2039     { X86::VORPSZrrkz,            X86::VORPSZrmkz,            0 },
2040     { X86::VXORPDZrrkz,           X86::VXORPDZrmkz,           0 },
2041     { X86::VXORPSZrrkz,           X86::VXORPSZrmkz,           0 },
2042     { X86::VPANDDZrrkz,           X86::VPANDDZrmkz,           0 },
2043     { X86::VPANDQZrrkz,           X86::VPANDQZrmkz,           0 },
2044     { X86::VPANDNDZrrkz,          X86::VPANDNDZrmkz,          0 },
2045     { X86::VPANDNQZrrkz,          X86::VPANDNQZrmkz,          0 },
2046     { X86::VPORDZrrkz,            X86::VPORDZrmkz,            0 },
2047     { X86::VPORQZrrkz,            X86::VPORQZrmkz,            0 },
2048     { X86::VPXORDZrrkz,           X86::VPXORDZrmkz,           0 },
2049     { X86::VPXORQZrrkz,           X86::VPXORQZrmkz,           0 },
2050     // AVX-512{F,VL} arithmetic instructions 256-bit
2051     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
2052     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
2053     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
2054     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
2055     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
2056     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
2057     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
2058     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
2059     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
2060     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
2061     { X86::VMINCPSZ256rrkz,       X86::VMINCPSZ256rmkz,       0 },
2062     { X86::VMINCPDZ256rrkz,       X86::VMINCPDZ256rmkz,       0 },
2063     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
2064     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
2065     { X86::VMAXCPSZ256rrkz,       X86::VMAXCPSZ256rmkz,       0 },
2066     { X86::VMAXCPDZ256rrkz,       X86::VMAXCPDZ256rmkz,       0 },
2067     { X86::VANDPDZ256rrkz,        X86::VANDPDZ256rmkz,        0 },
2068     { X86::VANDPSZ256rrkz,        X86::VANDPSZ256rmkz,        0 },
2069     { X86::VANDNPDZ256rrkz,       X86::VANDNPDZ256rmkz,       0 },
2070     { X86::VANDNPSZ256rrkz,       X86::VANDNPSZ256rmkz,       0 },
2071     { X86::VORPDZ256rrkz,         X86::VORPDZ256rmkz,         0 },
2072     { X86::VORPSZ256rrkz,         X86::VORPSZ256rmkz,         0 },
2073     { X86::VXORPDZ256rrkz,        X86::VXORPDZ256rmkz,        0 },
2074     { X86::VXORPSZ256rrkz,        X86::VXORPSZ256rmkz,        0 },
2075     { X86::VPANDDZ256rrkz,        X86::VPANDDZ256rmkz,        0 },
2076     { X86::VPANDQZ256rrkz,        X86::VPANDQZ256rmkz,        0 },
2077     { X86::VPANDNDZ256rrkz,       X86::VPANDNDZ256rmkz,       0 },
2078     { X86::VPANDNQZ256rrkz,       X86::VPANDNQZ256rmkz,       0 },
2079     { X86::VPORDZ256rrkz,         X86::VPORDZ256rmkz,         0 },
2080     { X86::VPORQZ256rrkz,         X86::VPORQZ256rmkz,         0 },
2081     { X86::VPXORDZ256rrkz,        X86::VPXORDZ256rmkz,        0 },
2082     { X86::VPXORQZ256rrkz,        X86::VPXORQZ256rmkz,        0 },
2083     // AVX-512{F,VL} arithmetic instructions 128-bit
2084     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
2085     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
2086     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
2087     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
2088     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
2089     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
2090     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
2091     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
2092     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
2093     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
2094     { X86::VMINCPSZ128rrkz,       X86::VMINCPSZ128rmkz,       0 },
2095     { X86::VMINCPDZ128rrkz,       X86::VMINCPDZ128rmkz,       0 },
2096     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
2097     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 },
2098     { X86::VMAXCPSZ128rrkz,       X86::VMAXCPSZ128rmkz,       0 },
2099     { X86::VMAXCPDZ128rrkz,       X86::VMAXCPDZ128rmkz,       0 },
2100     { X86::VANDPDZ128rrkz,        X86::VANDPDZ128rmkz,        0 },
2101     { X86::VANDPSZ128rrkz,        X86::VANDPSZ128rmkz,        0 },
2102     { X86::VANDNPDZ128rrkz,       X86::VANDNPDZ128rmkz,       0 },
2103     { X86::VANDNPSZ128rrkz,       X86::VANDNPSZ128rmkz,       0 },
2104     { X86::VORPDZ128rrkz,         X86::VORPDZ128rmkz,         0 },
2105     { X86::VORPSZ128rrkz,         X86::VORPSZ128rmkz,         0 },
2106     { X86::VXORPDZ128rrkz,        X86::VXORPDZ128rmkz,        0 },
2107     { X86::VXORPSZ128rrkz,        X86::VXORPSZ128rmkz,        0 },
2108     { X86::VPANDDZ128rrkz,        X86::VPANDDZ128rmkz,        0 },
2109     { X86::VPANDQZ128rrkz,        X86::VPANDQZ128rmkz,        0 },
2110     { X86::VPANDNDZ128rrkz,       X86::VPANDNDZ128rmkz,       0 },
2111     { X86::VPANDNQZ128rrkz,       X86::VPANDNQZ128rmkz,       0 },
2112     { X86::VPORDZ128rrkz,         X86::VPORDZ128rmkz,         0 },
2113     { X86::VPORQZ128rrkz,         X86::VPORQZ128rmkz,         0 },
2114     { X86::VPXORDZ128rrkz,        X86::VPXORDZ128rmkz,        0 },
2115     { X86::VPXORQZ128rrkz,        X86::VPXORQZ128rmkz,        0 },
2116   };
2117 
2118   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
2119     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2120                   Entry.RegOp, Entry.MemOp,
2121                   // Index 3, folded load
2122                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
2123   }
2124   auto I = X86InstrFMA3Info::rm_begin();
2125   auto E = X86InstrFMA3Info::rm_end();
2126   for (; I != E; ++I)
2127     if (!I.getGroup()->isKMasked())
2128       AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2129                     I.getRegOpcode(), I.getMemOpcode(),
2130                     TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD);
2131 
2132   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
2133      // AVX-512 foldable instructions
2134     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
2135     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
2136     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
2137     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
2138     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
2139     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
2140     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
2141     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
2142     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
2143     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
2144     { X86::VMINCPSZrrk,        X86::VMINCPSZrmk,          0 },
2145     { X86::VMINCPDZrrk,        X86::VMINCPDZrmk,          0 },
2146     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
2147     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
2148     { X86::VMAXCPSZrrk,        X86::VMAXCPSZrmk,          0 },
2149     { X86::VMAXCPDZrrk,        X86::VMAXCPDZrmk,          0 },
2150     { X86::VANDPDZrrk,         X86::VANDPDZrmk,           0 },
2151     { X86::VANDPSZrrk,         X86::VANDPSZrmk,           0 },
2152     { X86::VANDNPDZrrk,        X86::VANDNPDZrmk,          0 },
2153     { X86::VANDNPSZrrk,        X86::VANDNPSZrmk,          0 },
2154     { X86::VORPDZrrk,          X86::VORPDZrmk,            0 },
2155     { X86::VORPSZrrk,          X86::VORPSZrmk,            0 },
2156     { X86::VXORPDZrrk,         X86::VXORPDZrmk,           0 },
2157     { X86::VXORPSZrrk,         X86::VXORPSZrmk,           0 },
2158     { X86::VPANDDZrrk,         X86::VPANDDZrmk,           0 },
2159     { X86::VPANDQZrrk,         X86::VPANDQZrmk,           0 },
2160     { X86::VPANDNDZrrk,        X86::VPANDNDZrmk,          0 },
2161     { X86::VPANDNQZrrk,        X86::VPANDNQZrmk,          0 },
2162     { X86::VPORDZrrk,          X86::VPORDZrmk,            0 },
2163     { X86::VPORQZrrk,          X86::VPORQZrmk,            0 },
2164     { X86::VPXORDZrrk,         X86::VPXORDZrmk,           0 },
2165     { X86::VPXORQZrrk,         X86::VPXORQZrmk,           0 },
2166     // AVX-512{F,VL} foldable instructions 256-bit
2167     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
2168     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
2169     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
2170     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
2171     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
2172     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
2173     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
2174     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
2175     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
2176     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
2177     { X86::VMINCPSZ256rrk,     X86::VMINCPSZ256rmk,       0 },
2178     { X86::VMINCPDZ256rrk,     X86::VMINCPDZ256rmk,       0 },
2179     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
2180     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
2181     { X86::VMAXCPSZ256rrk,     X86::VMAXCPSZ256rmk,       0 },
2182     { X86::VMAXCPDZ256rrk,     X86::VMAXCPDZ256rmk,       0 },
2183     { X86::VANDPDZ256rrk,      X86::VANDPDZ256rmk,        0 },
2184     { X86::VANDPSZ256rrk,      X86::VANDPSZ256rmk,        0 },
2185     { X86::VANDNPDZ256rrk,     X86::VANDNPDZ256rmk,       0 },
2186     { X86::VANDNPSZ256rrk,     X86::VANDNPSZ256rmk,       0 },
2187     { X86::VORPDZ256rrk,       X86::VORPDZ256rmk,         0 },
2188     { X86::VORPSZ256rrk,       X86::VORPSZ256rmk,         0 },
2189     { X86::VXORPDZ256rrk,      X86::VXORPDZ256rmk,        0 },
2190     { X86::VXORPSZ256rrk,      X86::VXORPSZ256rmk,        0 },
2191     { X86::VPANDDZ256rrk,      X86::VPANDDZ256rmk,        0 },
2192     { X86::VPANDQZ256rrk,      X86::VPANDQZ256rmk,        0 },
2193     { X86::VPANDNDZ256rrk,     X86::VPANDNDZ256rmk,       0 },
2194     { X86::VPANDNQZ256rrk,     X86::VPANDNQZ256rmk,       0 },
2195     { X86::VPORDZ256rrk,       X86::VPORDZ256rmk,         0 },
2196     { X86::VPORQZ256rrk,       X86::VPORQZ256rmk,         0 },
2197     { X86::VPXORDZ256rrk,      X86::VPXORDZ256rmk,        0 },
2198     { X86::VPXORQZ256rrk,      X86::VPXORQZ256rmk,        0 },
2199     // AVX-512{F,VL} foldable instructions 128-bit
2200     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
2201     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
2202     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
2203     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
2204     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
2205     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
2206     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
2207     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
2208     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
2209     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
2210     { X86::VMINCPSZ128rrk,     X86::VMINCPSZ128rmk,       0 },
2211     { X86::VMINCPDZ128rrk,     X86::VMINCPDZ128rmk,       0 },
2212     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
2213     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 },
2214     { X86::VMAXCPSZ128rrk,     X86::VMAXCPSZ128rmk,       0 },
2215     { X86::VMAXCPDZ128rrk,     X86::VMAXCPDZ128rmk,       0 },
2216     { X86::VANDPDZ128rrk,      X86::VANDPDZ128rmk,        0 },
2217     { X86::VANDPSZ128rrk,      X86::VANDPSZ128rmk,        0 },
2218     { X86::VANDNPDZ128rrk,     X86::VANDNPDZ128rmk,       0 },
2219     { X86::VANDNPSZ128rrk,     X86::VANDNPSZ128rmk,       0 },
2220     { X86::VORPDZ128rrk,       X86::VORPDZ128rmk,         0 },
2221     { X86::VORPSZ128rrk,       X86::VORPSZ128rmk,         0 },
2222     { X86::VXORPDZ128rrk,      X86::VXORPDZ128rmk,        0 },
2223     { X86::VXORPSZ128rrk,      X86::VXORPSZ128rmk,        0 },
2224     { X86::VPANDDZ128rrk,      X86::VPANDDZ128rmk,        0 },
2225     { X86::VPANDQZ128rrk,      X86::VPANDQZ128rmk,        0 },
2226     { X86::VPANDNDZ128rrk,     X86::VPANDNDZ128rmk,       0 },
2227     { X86::VPANDNQZ128rrk,     X86::VPANDNQZ128rmk,       0 },
2228     { X86::VPORDZ128rrk,       X86::VPORDZ128rmk,         0 },
2229     { X86::VPORQZ128rrk,       X86::VPORQZ128rmk,         0 },
2230     { X86::VPXORDZ128rrk,      X86::VPXORDZ128rmk,        0 },
2231     { X86::VPXORQZ128rrk,      X86::VPXORQZ128rmk,        0 },
2232   };
2233 
2234   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
2235     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2236                   Entry.RegOp, Entry.MemOp,
2237                   // Index 4, folded load
2238                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
2239   }
2240   for (I = X86InstrFMA3Info::rm_begin(); I != E; ++I)
2241     if (I.getGroup()->isKMasked())
2242       AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2243                     I.getRegOpcode(), I.getMemOpcode(),
2244                     TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD);
2245 }
2246 
2247 void
2248 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2249                             MemOp2RegOpTableType &M2RTable,
2250                             uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
2251   if ((Flags & TB_NO_FORWARD) == 0) {
2252     assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2253     R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2254   }
2255   if ((Flags & TB_NO_REVERSE) == 0) {
2256     assert(!M2RTable.count(MemOp) &&
2257          "Duplicated entries in unfolding maps?");
2258     M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2259   }
2260 }
2261 
2262 bool
2263 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2264                                     unsigned &SrcReg, unsigned &DstReg,
2265                                     unsigned &SubIdx) const {
2266   switch (MI.getOpcode()) {
2267   default: break;
2268   case X86::MOVSX16rr8:
2269   case X86::MOVZX16rr8:
2270   case X86::MOVSX32rr8:
2271   case X86::MOVZX32rr8:
2272   case X86::MOVSX64rr8:
2273     if (!Subtarget.is64Bit())
2274       // It's not always legal to reference the low 8-bit of the larger
2275       // register in 32-bit mode.
2276       return false;
2277   case X86::MOVSX32rr16:
2278   case X86::MOVZX32rr16:
2279   case X86::MOVSX64rr16:
2280   case X86::MOVSX64rr32: {
2281     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2282       // Be conservative.
2283       return false;
2284     SrcReg = MI.getOperand(1).getReg();
2285     DstReg = MI.getOperand(0).getReg();
2286     switch (MI.getOpcode()) {
2287     default: llvm_unreachable("Unreachable!");
2288     case X86::MOVSX16rr8:
2289     case X86::MOVZX16rr8:
2290     case X86::MOVSX32rr8:
2291     case X86::MOVZX32rr8:
2292     case X86::MOVSX64rr8:
2293       SubIdx = X86::sub_8bit;
2294       break;
2295     case X86::MOVSX32rr16:
2296     case X86::MOVZX32rr16:
2297     case X86::MOVSX64rr16:
2298       SubIdx = X86::sub_16bit;
2299       break;
2300     case X86::MOVSX64rr32:
2301       SubIdx = X86::sub_32bit;
2302       break;
2303     }
2304     return true;
2305   }
2306   }
2307   return false;
2308 }
2309 
2310 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
2311   const MachineFunction *MF = MI.getParent()->getParent();
2312   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2313 
2314   if (MI.getOpcode() == getCallFrameSetupOpcode() ||
2315       MI.getOpcode() == getCallFrameDestroyOpcode()) {
2316     unsigned StackAlign = TFI->getStackAlignment();
2317     int SPAdj =
2318         (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
2319 
2320     SPAdj -= MI.getOperand(1).getImm();
2321 
2322     if (MI.getOpcode() == getCallFrameSetupOpcode())
2323       return SPAdj;
2324     else
2325       return -SPAdj;
2326   }
2327 
2328   // To know whether a call adjusts the stack, we need information
2329   // that is bound to the following ADJCALLSTACKUP pseudo.
2330   // Look for the next ADJCALLSTACKUP that follows the call.
2331   if (MI.isCall()) {
2332     const MachineBasicBlock *MBB = MI.getParent();
2333     auto I = ++MachineBasicBlock::const_iterator(MI);
2334     for (auto E = MBB->end(); I != E; ++I) {
2335       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2336           I->isCall())
2337         break;
2338     }
2339 
2340     // If we could not find a frame destroy opcode, then it has already
2341     // been simplified, so we don't care.
2342     if (I->getOpcode() != getCallFrameDestroyOpcode())
2343       return 0;
2344 
2345     return -(I->getOperand(1).getImm());
2346   }
2347 
2348   // Currently handle only PUSHes we can reasonably expect to see
2349   // in call sequences
2350   switch (MI.getOpcode()) {
2351   default:
2352     return 0;
2353   case X86::PUSH32i8:
2354   case X86::PUSH32r:
2355   case X86::PUSH32rmm:
2356   case X86::PUSH32rmr:
2357   case X86::PUSHi32:
2358     return 4;
2359   case X86::PUSH64i8:
2360   case X86::PUSH64r:
2361   case X86::PUSH64rmm:
2362   case X86::PUSH64rmr:
2363   case X86::PUSH64i32:
2364     return 8;
2365   }
2366 }
2367 
2368 /// Return true and the FrameIndex if the specified
2369 /// operand and follow operands form a reference to the stack frame.
2370 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
2371                                   int &FrameIndex) const {
2372   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
2373       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
2374       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
2375       MI.getOperand(Op + X86::AddrDisp).isImm() &&
2376       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
2377       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
2378       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
2379     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
2380     return true;
2381   }
2382   return false;
2383 }
2384 
2385 static bool isFrameLoadOpcode(int Opcode) {
2386   switch (Opcode) {
2387   default:
2388     return false;
2389   case X86::MOV8rm:
2390   case X86::MOV16rm:
2391   case X86::MOV32rm:
2392   case X86::MOV64rm:
2393   case X86::LD_Fp64m:
2394   case X86::MOVSSrm:
2395   case X86::MOVSDrm:
2396   case X86::MOVAPSrm:
2397   case X86::MOVUPSrm:
2398   case X86::MOVAPDrm:
2399   case X86::MOVUPDrm:
2400   case X86::MOVDQArm:
2401   case X86::MOVDQUrm:
2402   case X86::VMOVSSrm:
2403   case X86::VMOVSDrm:
2404   case X86::VMOVAPSrm:
2405   case X86::VMOVUPSrm:
2406   case X86::VMOVAPDrm:
2407   case X86::VMOVUPDrm:
2408   case X86::VMOVDQArm:
2409   case X86::VMOVDQUrm:
2410   case X86::VMOVUPSYrm:
2411   case X86::VMOVAPSYrm:
2412   case X86::VMOVUPDYrm:
2413   case X86::VMOVAPDYrm:
2414   case X86::VMOVDQUYrm:
2415   case X86::VMOVDQAYrm:
2416   case X86::MMX_MOVD64rm:
2417   case X86::MMX_MOVQ64rm:
2418   case X86::VMOVSSZrm:
2419   case X86::VMOVSDZrm:
2420   case X86::VMOVAPSZrm:
2421   case X86::VMOVAPSZ128rm:
2422   case X86::VMOVAPSZ256rm:
2423   case X86::VMOVUPSZrm:
2424   case X86::VMOVUPSZ128rm:
2425   case X86::VMOVUPSZ256rm:
2426   case X86::VMOVAPDZrm:
2427   case X86::VMOVAPDZ128rm:
2428   case X86::VMOVAPDZ256rm:
2429   case X86::VMOVUPDZrm:
2430   case X86::VMOVUPDZ128rm:
2431   case X86::VMOVUPDZ256rm:
2432   case X86::VMOVDQA32Zrm:
2433   case X86::VMOVDQA32Z128rm:
2434   case X86::VMOVDQA32Z256rm:
2435   case X86::VMOVDQU32Zrm:
2436   case X86::VMOVDQU32Z128rm:
2437   case X86::VMOVDQU32Z256rm:
2438   case X86::VMOVDQA64Zrm:
2439   case X86::VMOVDQA64Z128rm:
2440   case X86::VMOVDQA64Z256rm:
2441   case X86::VMOVDQU64Zrm:
2442   case X86::VMOVDQU64Z128rm:
2443   case X86::VMOVDQU64Z256rm:
2444   case X86::VMOVDQU8Zrm:
2445   case X86::VMOVDQU8Z128rm:
2446   case X86::VMOVDQU8Z256rm:
2447   case X86::VMOVDQU16Zrm:
2448   case X86::VMOVDQU16Z128rm:
2449   case X86::VMOVDQU16Z256rm:
2450   case X86::KMOVBkm:
2451   case X86::KMOVWkm:
2452   case X86::KMOVDkm:
2453   case X86::KMOVQkm:
2454     return true;
2455   }
2456 }
2457 
2458 static bool isFrameStoreOpcode(int Opcode) {
2459   switch (Opcode) {
2460   default: break;
2461   case X86::MOV8mr:
2462   case X86::MOV16mr:
2463   case X86::MOV32mr:
2464   case X86::MOV64mr:
2465   case X86::ST_FpP64m:
2466   case X86::MOVSSmr:
2467   case X86::MOVSDmr:
2468   case X86::MOVAPSmr:
2469   case X86::MOVUPSmr:
2470   case X86::MOVAPDmr:
2471   case X86::MOVUPDmr:
2472   case X86::MOVDQAmr:
2473   case X86::MOVDQUmr:
2474   case X86::VMOVSSmr:
2475   case X86::VMOVSDmr:
2476   case X86::VMOVAPSmr:
2477   case X86::VMOVUPSmr:
2478   case X86::VMOVAPDmr:
2479   case X86::VMOVUPDmr:
2480   case X86::VMOVDQAmr:
2481   case X86::VMOVDQUmr:
2482   case X86::VMOVUPSYmr:
2483   case X86::VMOVAPSYmr:
2484   case X86::VMOVUPDYmr:
2485   case X86::VMOVAPDYmr:
2486   case X86::VMOVDQUYmr:
2487   case X86::VMOVDQAYmr:
2488   case X86::VMOVSSZmr:
2489   case X86::VMOVSDZmr:
2490   case X86::VMOVUPSZmr:
2491   case X86::VMOVUPSZ128mr:
2492   case X86::VMOVUPSZ256mr:
2493   case X86::VMOVAPSZmr:
2494   case X86::VMOVAPSZ128mr:
2495   case X86::VMOVAPSZ256mr:
2496   case X86::VMOVUPDZmr:
2497   case X86::VMOVUPDZ128mr:
2498   case X86::VMOVUPDZ256mr:
2499   case X86::VMOVAPDZmr:
2500   case X86::VMOVAPDZ128mr:
2501   case X86::VMOVAPDZ256mr:
2502   case X86::VMOVDQA32Zmr:
2503   case X86::VMOVDQA32Z128mr:
2504   case X86::VMOVDQA32Z256mr:
2505   case X86::VMOVDQU32Zmr:
2506   case X86::VMOVDQU32Z128mr:
2507   case X86::VMOVDQU32Z256mr:
2508   case X86::VMOVDQA64Zmr:
2509   case X86::VMOVDQA64Z128mr:
2510   case X86::VMOVDQA64Z256mr:
2511   case X86::VMOVDQU64Zmr:
2512   case X86::VMOVDQU64Z128mr:
2513   case X86::VMOVDQU64Z256mr:
2514   case X86::VMOVDQU8Zmr:
2515   case X86::VMOVDQU8Z128mr:
2516   case X86::VMOVDQU8Z256mr:
2517   case X86::VMOVDQU16Zmr:
2518   case X86::VMOVDQU16Z128mr:
2519   case X86::VMOVDQU16Z256mr:
2520   case X86::MMX_MOVD64mr:
2521   case X86::MMX_MOVQ64mr:
2522   case X86::MMX_MOVNTQmr:
2523   case X86::KMOVBmk:
2524   case X86::KMOVWmk:
2525   case X86::KMOVDmk:
2526   case X86::KMOVQmk:
2527     return true;
2528   }
2529   return false;
2530 }
2531 
2532 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
2533                                            int &FrameIndex) const {
2534   if (isFrameLoadOpcode(MI.getOpcode()))
2535     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2536       return MI.getOperand(0).getReg();
2537   return 0;
2538 }
2539 
2540 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
2541                                                  int &FrameIndex) const {
2542   if (isFrameLoadOpcode(MI.getOpcode())) {
2543     unsigned Reg;
2544     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2545       return Reg;
2546     // Check for post-frame index elimination operations
2547     const MachineMemOperand *Dummy;
2548     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2549   }
2550   return 0;
2551 }
2552 
2553 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
2554                                           int &FrameIndex) const {
2555   if (isFrameStoreOpcode(MI.getOpcode()))
2556     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2557         isFrameOperand(MI, 0, FrameIndex))
2558       return MI.getOperand(X86::AddrNumOperands).getReg();
2559   return 0;
2560 }
2561 
2562 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
2563                                                 int &FrameIndex) const {
2564   if (isFrameStoreOpcode(MI.getOpcode())) {
2565     unsigned Reg;
2566     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2567       return Reg;
2568     // Check for post-frame index elimination operations
2569     const MachineMemOperand *Dummy;
2570     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2571   }
2572   return 0;
2573 }
2574 
2575 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2576 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2577   // Don't waste compile time scanning use-def chains of physregs.
2578   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2579     return false;
2580   bool isPICBase = false;
2581   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2582          E = MRI.def_instr_end(); I != E; ++I) {
2583     MachineInstr *DefMI = &*I;
2584     if (DefMI->getOpcode() != X86::MOVPC32r)
2585       return false;
2586     assert(!isPICBase && "More than one PIC base?");
2587     isPICBase = true;
2588   }
2589   return isPICBase;
2590 }
2591 
2592 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
2593                                                      AliasAnalysis *AA) const {
2594   switch (MI.getOpcode()) {
2595   default: break;
2596   case X86::MOV8rm:
2597   case X86::MOV16rm:
2598   case X86::MOV32rm:
2599   case X86::MOV64rm:
2600   case X86::LD_Fp64m:
2601   case X86::MOVSSrm:
2602   case X86::MOVSDrm:
2603   case X86::MOVAPSrm:
2604   case X86::MOVUPSrm:
2605   case X86::MOVAPDrm:
2606   case X86::MOVDQArm:
2607   case X86::MOVDQUrm:
2608   case X86::VMOVSSrm:
2609   case X86::VMOVSDrm:
2610   case X86::VMOVAPSrm:
2611   case X86::VMOVUPSrm:
2612   case X86::VMOVAPDrm:
2613   case X86::VMOVDQArm:
2614   case X86::VMOVDQUrm:
2615   case X86::VMOVAPSYrm:
2616   case X86::VMOVUPSYrm:
2617   case X86::VMOVAPDYrm:
2618   case X86::VMOVDQAYrm:
2619   case X86::VMOVDQUYrm:
2620   case X86::MMX_MOVD64rm:
2621   case X86::MMX_MOVQ64rm:
2622   // AVX-512
2623   case X86::VMOVSSZrm:
2624   case X86::VMOVSDZrm:
2625   case X86::VMOVAPDZ128rm:
2626   case X86::VMOVAPDZ256rm:
2627   case X86::VMOVAPDZrm:
2628   case X86::VMOVAPSZ128rm:
2629   case X86::VMOVAPSZ256rm:
2630   case X86::VMOVAPSZrm:
2631   case X86::VMOVDQA32Z128rm:
2632   case X86::VMOVDQA32Z256rm:
2633   case X86::VMOVDQA32Zrm:
2634   case X86::VMOVDQA64Z128rm:
2635   case X86::VMOVDQA64Z256rm:
2636   case X86::VMOVDQA64Zrm:
2637   case X86::VMOVDQU16Z128rm:
2638   case X86::VMOVDQU16Z256rm:
2639   case X86::VMOVDQU16Zrm:
2640   case X86::VMOVDQU32Z128rm:
2641   case X86::VMOVDQU32Z256rm:
2642   case X86::VMOVDQU32Zrm:
2643   case X86::VMOVDQU64Z128rm:
2644   case X86::VMOVDQU64Z256rm:
2645   case X86::VMOVDQU64Zrm:
2646   case X86::VMOVDQU8Z128rm:
2647   case X86::VMOVDQU8Z256rm:
2648   case X86::VMOVDQU8Zrm:
2649   case X86::VMOVUPSZ128rm:
2650   case X86::VMOVUPSZ256rm:
2651   case X86::VMOVUPSZrm: {
2652     // Loads from constant pools are trivially rematerializable.
2653     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
2654         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2655         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2656         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2657         MI.isInvariantLoad(AA)) {
2658       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
2659       if (BaseReg == 0 || BaseReg == X86::RIP)
2660         return true;
2661       // Allow re-materialization of PIC load.
2662       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
2663         return false;
2664       const MachineFunction &MF = *MI.getParent()->getParent();
2665       const MachineRegisterInfo &MRI = MF.getRegInfo();
2666       return regIsPICBase(BaseReg, MRI);
2667     }
2668     return false;
2669   }
2670 
2671   case X86::LEA32r:
2672   case X86::LEA64r: {
2673     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2674         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2675         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2676         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
2677       // lea fi#, lea GV, etc. are all rematerializable.
2678       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
2679         return true;
2680       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
2681       if (BaseReg == 0)
2682         return true;
2683       // Allow re-materialization of lea PICBase + x.
2684       const MachineFunction &MF = *MI.getParent()->getParent();
2685       const MachineRegisterInfo &MRI = MF.getRegInfo();
2686       return regIsPICBase(BaseReg, MRI);
2687     }
2688     return false;
2689   }
2690   }
2691 
2692   // All other instructions marked M_REMATERIALIZABLE are always trivially
2693   // rematerializable.
2694   return true;
2695 }
2696 
2697 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2698                                          MachineBasicBlock::iterator I) const {
2699   MachineBasicBlock::iterator E = MBB.end();
2700 
2701   // For compile time consideration, if we are not able to determine the
2702   // safety after visiting 4 instructions in each direction, we will assume
2703   // it's not safe.
2704   MachineBasicBlock::iterator Iter = I;
2705   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2706     bool SeenDef = false;
2707     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2708       MachineOperand &MO = Iter->getOperand(j);
2709       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2710         SeenDef = true;
2711       if (!MO.isReg())
2712         continue;
2713       if (MO.getReg() == X86::EFLAGS) {
2714         if (MO.isUse())
2715           return false;
2716         SeenDef = true;
2717       }
2718     }
2719 
2720     if (SeenDef)
2721       // This instruction defines EFLAGS, no need to look any further.
2722       return true;
2723     ++Iter;
2724     // Skip over DBG_VALUE.
2725     while (Iter != E && Iter->isDebugValue())
2726       ++Iter;
2727   }
2728 
2729   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2730   // live in.
2731   if (Iter == E) {
2732     for (MachineBasicBlock *S : MBB.successors())
2733       if (S->isLiveIn(X86::EFLAGS))
2734         return false;
2735     return true;
2736   }
2737 
2738   MachineBasicBlock::iterator B = MBB.begin();
2739   Iter = I;
2740   for (unsigned i = 0; i < 4; ++i) {
2741     // If we make it to the beginning of the block, it's safe to clobber
2742     // EFLAGS iff EFLAGS is not live-in.
2743     if (Iter == B)
2744       return !MBB.isLiveIn(X86::EFLAGS);
2745 
2746     --Iter;
2747     // Skip over DBG_VALUE.
2748     while (Iter != B && Iter->isDebugValue())
2749       --Iter;
2750 
2751     bool SawKill = false;
2752     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2753       MachineOperand &MO = Iter->getOperand(j);
2754       // A register mask may clobber EFLAGS, but we should still look for a
2755       // live EFLAGS def.
2756       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2757         SawKill = true;
2758       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2759         if (MO.isDef()) return MO.isDead();
2760         if (MO.isKill()) SawKill = true;
2761       }
2762     }
2763 
2764     if (SawKill)
2765       // This instruction kills EFLAGS and doesn't redefine it, so
2766       // there's no need to look further.
2767       return true;
2768   }
2769 
2770   // Conservative answer.
2771   return false;
2772 }
2773 
2774 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2775                                  MachineBasicBlock::iterator I,
2776                                  unsigned DestReg, unsigned SubIdx,
2777                                  const MachineInstr &Orig,
2778                                  const TargetRegisterInfo &TRI) const {
2779   bool ClobbersEFLAGS = false;
2780   for (const MachineOperand &MO : Orig.operands()) {
2781     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2782       ClobbersEFLAGS = true;
2783       break;
2784     }
2785   }
2786 
2787   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2788     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2789     // effects.
2790     int Value;
2791     switch (Orig.getOpcode()) {
2792     case X86::MOV32r0:  Value = 0; break;
2793     case X86::MOV32r1:  Value = 1; break;
2794     case X86::MOV32r_1: Value = -1; break;
2795     default:
2796       llvm_unreachable("Unexpected instruction!");
2797     }
2798 
2799     const DebugLoc &DL = Orig.getDebugLoc();
2800     BuildMI(MBB, I, DL, get(X86::MOV32ri))
2801         .addOperand(Orig.getOperand(0))
2802         .addImm(Value);
2803   } else {
2804     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
2805     MBB.insert(I, MI);
2806   }
2807 
2808   MachineInstr &NewMI = *std::prev(I);
2809   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
2810 }
2811 
2812 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2813 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
2814   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2815     MachineOperand &MO = MI.getOperand(i);
2816     if (MO.isReg() && MO.isDef() &&
2817         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2818       return true;
2819     }
2820   }
2821   return false;
2822 }
2823 
2824 /// Check whether the shift count for a machine operand is non-zero.
2825 inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
2826                                               unsigned ShiftAmtOperandIdx) {
2827   // The shift count is six bits with the REX.W prefix and five bits without.
2828   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2829   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
2830   return Imm & ShiftCountMask;
2831 }
2832 
2833 /// Check whether the given shift count is appropriate
2834 /// can be represented by a LEA instruction.
2835 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2836   // Left shift instructions can be transformed into load-effective-address
2837   // instructions if we can encode them appropriately.
2838   // A LEA instruction utilizes a SIB byte to encode its scale factor.
2839   // The SIB.scale field is two bits wide which means that we can encode any
2840   // shift amount less than 4.
2841   return ShAmt < 4 && ShAmt > 0;
2842 }
2843 
2844 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
2845                                   unsigned Opc, bool AllowSP, unsigned &NewSrc,
2846                                   bool &isKill, bool &isUndef,
2847                                   MachineOperand &ImplicitOp,
2848                                   LiveVariables *LV) const {
2849   MachineFunction &MF = *MI.getParent()->getParent();
2850   const TargetRegisterClass *RC;
2851   if (AllowSP) {
2852     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2853   } else {
2854     RC = Opc != X86::LEA32r ?
2855       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2856   }
2857   unsigned SrcReg = Src.getReg();
2858 
2859   // For both LEA64 and LEA32 the register already has essentially the right
2860   // type (32-bit or 64-bit) we may just need to forbid SP.
2861   if (Opc != X86::LEA64_32r) {
2862     NewSrc = SrcReg;
2863     isKill = Src.isKill();
2864     isUndef = Src.isUndef();
2865 
2866     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2867         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2868       return false;
2869 
2870     return true;
2871   }
2872 
2873   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2874   // another we need to add 64-bit registers to the final MI.
2875   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2876     ImplicitOp = Src;
2877     ImplicitOp.setImplicit();
2878 
2879     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
2880     isKill = Src.isKill();
2881     isUndef = Src.isUndef();
2882   } else {
2883     // Virtual register of the wrong class, we have to create a temporary 64-bit
2884     // vreg to feed into the LEA.
2885     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2886     MachineInstr *Copy = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
2887                                  get(TargetOpcode::COPY))
2888         .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2889         .addOperand(Src);
2890 
2891     // Which is obviously going to be dead after we're done with it.
2892     isKill = true;
2893     isUndef = false;
2894 
2895     if (LV)
2896       LV->replaceKillInstruction(SrcReg, MI, *Copy);
2897   }
2898 
2899   // We've set all the parameters without issue.
2900   return true;
2901 }
2902 
2903 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2904 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2905 /// truncating back down to a 16-bit subregister.
2906 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
2907     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
2908     LiveVariables *LV) const {
2909   MachineBasicBlock::iterator MBBI = MI.getIterator();
2910   unsigned Dest = MI.getOperand(0).getReg();
2911   unsigned Src = MI.getOperand(1).getReg();
2912   bool isDead = MI.getOperand(0).isDead();
2913   bool isKill = MI.getOperand(1).isKill();
2914 
2915   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2916   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2917   unsigned Opc, leaInReg;
2918   if (Subtarget.is64Bit()) {
2919     Opc = X86::LEA64_32r;
2920     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2921   } else {
2922     Opc = X86::LEA32r;
2923     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2924   }
2925 
2926   // Build and insert into an implicit UNDEF value. This is OK because
2927   // well be shifting and then extracting the lower 16-bits.
2928   // This has the potential to cause partial register stall. e.g.
2929   //   movw    (%rbp,%rcx,2), %dx
2930   //   leal    -65(%rdx), %esi
2931   // But testing has shown this *does* help performance in 64-bit mode (at
2932   // least on modern x86 machines).
2933   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2934   MachineInstr *InsMI =
2935       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2936           .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2937           .addReg(Src, getKillRegState(isKill));
2938 
2939   MachineInstrBuilder MIB =
2940       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
2941   switch (MIOpc) {
2942   default: llvm_unreachable("Unreachable!");
2943   case X86::SHL16ri: {
2944     unsigned ShAmt = MI.getOperand(2).getImm();
2945     MIB.addReg(0).addImm(1ULL << ShAmt)
2946        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2947     break;
2948   }
2949   case X86::INC16r:
2950     addRegOffset(MIB, leaInReg, true, 1);
2951     break;
2952   case X86::DEC16r:
2953     addRegOffset(MIB, leaInReg, true, -1);
2954     break;
2955   case X86::ADD16ri:
2956   case X86::ADD16ri8:
2957   case X86::ADD16ri_DB:
2958   case X86::ADD16ri8_DB:
2959     addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
2960     break;
2961   case X86::ADD16rr:
2962   case X86::ADD16rr_DB: {
2963     unsigned Src2 = MI.getOperand(2).getReg();
2964     bool isKill2 = MI.getOperand(2).isKill();
2965     unsigned leaInReg2 = 0;
2966     MachineInstr *InsMI2 = nullptr;
2967     if (Src == Src2) {
2968       // ADD16rr %reg1028<kill>, %reg1028
2969       // just a single insert_subreg.
2970       addRegReg(MIB, leaInReg, true, leaInReg, false);
2971     } else {
2972       if (Subtarget.is64Bit())
2973         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2974       else
2975         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2976       // Build and insert into an implicit UNDEF value. This is OK because
2977       // well be shifting and then extracting the lower 16-bits.
2978       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
2979       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
2980                    .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2981                    .addReg(Src2, getKillRegState(isKill2));
2982       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2983     }
2984     if (LV && isKill2 && InsMI2)
2985       LV->replaceKillInstruction(Src2, MI, *InsMI2);
2986     break;
2987   }
2988   }
2989 
2990   MachineInstr *NewMI = MIB;
2991   MachineInstr *ExtMI =
2992       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2993           .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2994           .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2995 
2996   if (LV) {
2997     // Update live variables
2998     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2999     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
3000     if (isKill)
3001       LV->replaceKillInstruction(Src, MI, *InsMI);
3002     if (isDead)
3003       LV->replaceKillInstruction(Dest, MI, *ExtMI);
3004   }
3005 
3006   return ExtMI;
3007 }
3008 
3009 /// This method must be implemented by targets that
3010 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
3011 /// may be able to convert a two-address instruction into a true
3012 /// three-address instruction on demand.  This allows the X86 target (for
3013 /// example) to convert ADD and SHL instructions into LEA instructions if they
3014 /// would require register copies due to two-addressness.
3015 ///
3016 /// This method returns a null pointer if the transformation cannot be
3017 /// performed, otherwise it returns the new instruction.
3018 ///
3019 MachineInstr *
3020 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
3021                                     MachineInstr &MI, LiveVariables *LV) const {
3022   // The following opcodes also sets the condition code register(s). Only
3023   // convert them to equivalent lea if the condition code register def's
3024   // are dead!
3025   if (hasLiveCondCodeDef(MI))
3026     return nullptr;
3027 
3028   MachineFunction &MF = *MI.getParent()->getParent();
3029   // All instructions input are two-addr instructions.  Get the known operands.
3030   const MachineOperand &Dest = MI.getOperand(0);
3031   const MachineOperand &Src = MI.getOperand(1);
3032 
3033   MachineInstr *NewMI = nullptr;
3034   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
3035   // we have better subtarget support, enable the 16-bit LEA generation here.
3036   // 16-bit LEA is also slow on Core2.
3037   bool DisableLEA16 = true;
3038   bool is64Bit = Subtarget.is64Bit();
3039 
3040   unsigned MIOpc = MI.getOpcode();
3041   switch (MIOpc) {
3042   default: return nullptr;
3043   case X86::SHL64ri: {
3044     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
3045     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3046     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
3047 
3048     // LEA can't handle RSP.
3049     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
3050         !MF.getRegInfo().constrainRegClass(Src.getReg(),
3051                                            &X86::GR64_NOSPRegClass))
3052       return nullptr;
3053 
3054     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3055                 .addOperand(Dest)
3056                 .addReg(0)
3057                 .addImm(1ULL << ShAmt)
3058                 .addOperand(Src)
3059                 .addImm(0)
3060                 .addReg(0);
3061     break;
3062   }
3063   case X86::SHL32ri: {
3064     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
3065     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3066     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
3067 
3068     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3069 
3070     // LEA can't handle ESP.
3071     bool isKill, isUndef;
3072     unsigned SrcReg;
3073     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3074     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
3075                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3076       return nullptr;
3077 
3078     MachineInstrBuilder MIB =
3079         BuildMI(MF, MI.getDebugLoc(), get(Opc))
3080             .addOperand(Dest)
3081             .addReg(0)
3082             .addImm(1ULL << ShAmt)
3083             .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
3084             .addImm(0)
3085             .addReg(0);
3086     if (ImplicitOp.getReg() != 0)
3087       MIB.addOperand(ImplicitOp);
3088     NewMI = MIB;
3089 
3090     break;
3091   }
3092   case X86::SHL16ri: {
3093     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
3094     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3095     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
3096 
3097     if (DisableLEA16)
3098       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3099                      : nullptr;
3100     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3101                 .addOperand(Dest)
3102                 .addReg(0)
3103                 .addImm(1ULL << ShAmt)
3104                 .addOperand(Src)
3105                 .addImm(0)
3106                 .addReg(0);
3107     break;
3108   }
3109   case X86::INC64r:
3110   case X86::INC32r: {
3111     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
3112     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
3113       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3114     bool isKill, isUndef;
3115     unsigned SrcReg;
3116     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3117     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
3118                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3119       return nullptr;
3120 
3121     MachineInstrBuilder MIB =
3122         BuildMI(MF, MI.getDebugLoc(), get(Opc))
3123             .addOperand(Dest)
3124             .addReg(SrcReg,
3125                     getKillRegState(isKill) | getUndefRegState(isUndef));
3126     if (ImplicitOp.getReg() != 0)
3127       MIB.addOperand(ImplicitOp);
3128 
3129     NewMI = addOffset(MIB, 1);
3130     break;
3131   }
3132   case X86::INC16r:
3133     if (DisableLEA16)
3134       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3135                      : nullptr;
3136     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
3137     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3138                           .addOperand(Dest)
3139                           .addOperand(Src),
3140                       1);
3141     break;
3142   case X86::DEC64r:
3143   case X86::DEC32r: {
3144     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
3145     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
3146       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3147 
3148     bool isKill, isUndef;
3149     unsigned SrcReg;
3150     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3151     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
3152                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3153       return nullptr;
3154 
3155     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3156                                   .addOperand(Dest)
3157                                   .addReg(SrcReg, getUndefRegState(isUndef) |
3158                                                       getKillRegState(isKill));
3159     if (ImplicitOp.getReg() != 0)
3160       MIB.addOperand(ImplicitOp);
3161 
3162     NewMI = addOffset(MIB, -1);
3163 
3164     break;
3165   }
3166   case X86::DEC16r:
3167     if (DisableLEA16)
3168       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3169                      : nullptr;
3170     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
3171     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3172                           .addOperand(Dest)
3173                           .addOperand(Src),
3174                       -1);
3175     break;
3176   case X86::ADD64rr:
3177   case X86::ADD64rr_DB:
3178   case X86::ADD32rr:
3179   case X86::ADD32rr_DB: {
3180     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3181     unsigned Opc;
3182     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
3183       Opc = X86::LEA64r;
3184     else
3185       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3186 
3187     bool isKill, isUndef;
3188     unsigned SrcReg;
3189     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3190     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3191                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3192       return nullptr;
3193 
3194     const MachineOperand &Src2 = MI.getOperand(2);
3195     bool isKill2, isUndef2;
3196     unsigned SrcReg2;
3197     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
3198     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
3199                         SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
3200       return nullptr;
3201 
3202     MachineInstrBuilder MIB =
3203         BuildMI(MF, MI.getDebugLoc(), get(Opc)).addOperand(Dest);
3204     if (ImplicitOp.getReg() != 0)
3205       MIB.addOperand(ImplicitOp);
3206     if (ImplicitOp2.getReg() != 0)
3207       MIB.addOperand(ImplicitOp2);
3208 
3209     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
3210 
3211     // Preserve undefness of the operands.
3212     NewMI->getOperand(1).setIsUndef(isUndef);
3213     NewMI->getOperand(3).setIsUndef(isUndef2);
3214 
3215     if (LV && Src2.isKill())
3216       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
3217     break;
3218   }
3219   case X86::ADD16rr:
3220   case X86::ADD16rr_DB: {
3221     if (DisableLEA16)
3222       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3223                      : nullptr;
3224     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3225     unsigned Src2 = MI.getOperand(2).getReg();
3226     bool isKill2 = MI.getOperand(2).isKill();
3227     NewMI = addRegReg(
3228         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).addOperand(Dest),
3229         Src.getReg(), Src.isKill(), Src2, isKill2);
3230 
3231     // Preserve undefness of the operands.
3232     bool isUndef = MI.getOperand(1).isUndef();
3233     bool isUndef2 = MI.getOperand(2).isUndef();
3234     NewMI->getOperand(1).setIsUndef(isUndef);
3235     NewMI->getOperand(3).setIsUndef(isUndef2);
3236 
3237     if (LV && isKill2)
3238       LV->replaceKillInstruction(Src2, MI, *NewMI);
3239     break;
3240   }
3241   case X86::ADD64ri32:
3242   case X86::ADD64ri8:
3243   case X86::ADD64ri32_DB:
3244   case X86::ADD64ri8_DB:
3245     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3246     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3247                           .addOperand(Dest)
3248                           .addOperand(Src),
3249                       MI.getOperand(2).getImm());
3250     break;
3251   case X86::ADD32ri:
3252   case X86::ADD32ri8:
3253   case X86::ADD32ri_DB:
3254   case X86::ADD32ri8_DB: {
3255     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3256     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3257 
3258     bool isKill, isUndef;
3259     unsigned SrcReg;
3260     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3261     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3262                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3263       return nullptr;
3264 
3265     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3266                                   .addOperand(Dest)
3267                                   .addReg(SrcReg, getUndefRegState(isUndef) |
3268                                                       getKillRegState(isKill));
3269     if (ImplicitOp.getReg() != 0)
3270       MIB.addOperand(ImplicitOp);
3271 
3272     NewMI = addOffset(MIB, MI.getOperand(2).getImm());
3273     break;
3274   }
3275   case X86::ADD16ri:
3276   case X86::ADD16ri8:
3277   case X86::ADD16ri_DB:
3278   case X86::ADD16ri8_DB:
3279     if (DisableLEA16)
3280       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3281                      : nullptr;
3282     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3283     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3284                           .addOperand(Dest)
3285                           .addOperand(Src),
3286                       MI.getOperand(2).getImm());
3287     break;
3288   }
3289 
3290   if (!NewMI) return nullptr;
3291 
3292   if (LV) {  // Update live variables
3293     if (Src.isKill())
3294       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
3295     if (Dest.isDead())
3296       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
3297   }
3298 
3299   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
3300   return NewMI;
3301 }
3302 
3303 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
3304     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
3305     const X86InstrFMA3Group &FMA3Group) const {
3306 
3307   unsigned Opc = MI.getOpcode();
3308 
3309   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3310   if (SrcOpIdx1 > SrcOpIdx2)
3311     std::swap(SrcOpIdx1, SrcOpIdx2);
3312 
3313   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3314   // analysis. The commute optimization is legal only if all users of FMA*_Int
3315   // use only the lowest element of the FMA*_Int instruction. Such analysis are
3316   // not implemented yet. So, just return 0 in that case.
3317   // When such analysis are available this place will be the right place for
3318   // calling it.
3319   if (FMA3Group.isIntrinsic() && SrcOpIdx1 == 1)
3320     return 0;
3321 
3322   unsigned FMAOp1 = 1, FMAOp2 = 2, FMAOp3 = 3;
3323   if (FMA3Group.isKMasked()) {
3324     // The k-mask operand cannot be commuted.
3325     if (SrcOpIdx1 == 2)
3326       return 0;
3327 
3328     // For k-zero-masked operations it is Ok to commute the first vector
3329     // operand.
3330     // For regular k-masked operations a conservative choice is done as the
3331     // elements of the first vector operand, for which the corresponding bit
3332     // in the k-mask operand is set to 0, are copied to the result of FMA.
3333     // TODO/FIXME: The commute still may be legal if it is known that the
3334     // k-mask operand is set to either all ones or all zeroes.
3335     // It is also Ok to commute the 1st operand if all users of MI use only
3336     // the elements enabled by the k-mask operand. For example,
3337     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
3338     //                                                     : v1[i];
3339     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
3340     //                                  // Ok, to commute v1 in FMADD213PSZrk.
3341     if (FMA3Group.isKMergeMasked() && SrcOpIdx1 == FMAOp1)
3342       return 0;
3343     FMAOp2++;
3344     FMAOp3++;
3345   }
3346 
3347   unsigned Case;
3348   if (SrcOpIdx1 == FMAOp1 && SrcOpIdx2 == FMAOp2)
3349     Case = 0;
3350   else if (SrcOpIdx1 == FMAOp1 && SrcOpIdx2 == FMAOp3)
3351     Case = 1;
3352   else if (SrcOpIdx1 == FMAOp2 && SrcOpIdx2 == FMAOp3)
3353     Case = 2;
3354   else
3355     return 0;
3356 
3357   // Define the FMA forms mapping array that helps to map input FMA form
3358   // to output FMA form to preserve the operation semantics after
3359   // commuting the operands.
3360   const unsigned Form132Index = 0;
3361   const unsigned Form213Index = 1;
3362   const unsigned Form231Index = 2;
3363   static const unsigned FormMapping[][3] = {
3364     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3365     // FMA132 A, C, b; ==> FMA231 C, A, b;
3366     // FMA213 B, A, c; ==> FMA213 A, B, c;
3367     // FMA231 C, A, b; ==> FMA132 A, C, b;
3368     { Form231Index, Form213Index, Form132Index },
3369     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3370     // FMA132 A, c, B; ==> FMA132 B, c, A;
3371     // FMA213 B, a, C; ==> FMA231 C, a, B;
3372     // FMA231 C, a, B; ==> FMA213 B, a, C;
3373     { Form132Index, Form231Index, Form213Index },
3374     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3375     // FMA132 a, C, B; ==> FMA213 a, B, C;
3376     // FMA213 b, A, C; ==> FMA132 b, C, A;
3377     // FMA231 c, A, B; ==> FMA231 c, B, A;
3378     { Form213Index, Form132Index, Form231Index }
3379   };
3380 
3381   unsigned FMAForms[3];
3382   if (FMA3Group.isRegOpcodeFromGroup(Opc)) {
3383     FMAForms[0] = FMA3Group.getReg132Opcode();
3384     FMAForms[1] = FMA3Group.getReg213Opcode();
3385     FMAForms[2] = FMA3Group.getReg231Opcode();
3386   } else {
3387     FMAForms[0] = FMA3Group.getMem132Opcode();
3388     FMAForms[1] = FMA3Group.getMem213Opcode();
3389     FMAForms[2] = FMA3Group.getMem231Opcode();
3390   }
3391   unsigned FormIndex;
3392   for (FormIndex = 0; FormIndex < 3; FormIndex++)
3393     if (Opc == FMAForms[FormIndex])
3394       break;
3395 
3396   // Everything is ready, just adjust the FMA opcode and return it.
3397   FormIndex = FormMapping[Case][FormIndex];
3398   return FMAForms[FormIndex];
3399 }
3400 
3401 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
3402                                                    unsigned OpIdx1,
3403                                                    unsigned OpIdx2) const {
3404   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
3405     if (NewMI)
3406       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
3407     return MI;
3408   };
3409 
3410   switch (MI.getOpcode()) {
3411   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3412   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
3413   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
3414   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3415   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3416   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
3417     unsigned Opc;
3418     unsigned Size;
3419     switch (MI.getOpcode()) {
3420     default: llvm_unreachable("Unreachable!");
3421     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3422     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3423     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3424     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
3425     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3426     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
3427     }
3428     unsigned Amt = MI.getOperand(3).getImm();
3429     auto &WorkingMI = cloneIfNew(MI);
3430     WorkingMI.setDesc(get(Opc));
3431     WorkingMI.getOperand(3).setImm(Size - Amt);
3432     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3433                                                    OpIdx1, OpIdx2);
3434   }
3435   case X86::BLENDPDrri:
3436   case X86::BLENDPSrri:
3437   case X86::PBLENDWrri:
3438   case X86::VBLENDPDrri:
3439   case X86::VBLENDPSrri:
3440   case X86::VBLENDPDYrri:
3441   case X86::VBLENDPSYrri:
3442   case X86::VPBLENDDrri:
3443   case X86::VPBLENDWrri:
3444   case X86::VPBLENDDYrri:
3445   case X86::VPBLENDWYrri:{
3446     unsigned Mask;
3447     switch (MI.getOpcode()) {
3448     default: llvm_unreachable("Unreachable!");
3449     case X86::BLENDPDrri:    Mask = 0x03; break;
3450     case X86::BLENDPSrri:    Mask = 0x0F; break;
3451     case X86::PBLENDWrri:    Mask = 0xFF; break;
3452     case X86::VBLENDPDrri:   Mask = 0x03; break;
3453     case X86::VBLENDPSrri:   Mask = 0x0F; break;
3454     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
3455     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
3456     case X86::VPBLENDDrri:   Mask = 0x0F; break;
3457     case X86::VPBLENDWrri:   Mask = 0xFF; break;
3458     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
3459     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
3460     }
3461     // Only the least significant bits of Imm are used.
3462     unsigned Imm = MI.getOperand(3).getImm() & Mask;
3463     auto &WorkingMI = cloneIfNew(MI);
3464     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
3465     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3466                                                    OpIdx1, OpIdx2);
3467   }
3468   case X86::PCLMULQDQrr:
3469   case X86::VPCLMULQDQrr:{
3470     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3471     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3472     unsigned Imm = MI.getOperand(3).getImm();
3473     unsigned Src1Hi = Imm & 0x01;
3474     unsigned Src2Hi = Imm & 0x10;
3475     auto &WorkingMI = cloneIfNew(MI);
3476     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3477     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3478                                                    OpIdx1, OpIdx2);
3479   }
3480   case X86::CMPSDrr:
3481   case X86::CMPSSrr:
3482   case X86::CMPPDrri:
3483   case X86::CMPPSrri:
3484   case X86::VCMPSDrr:
3485   case X86::VCMPSSrr:
3486   case X86::VCMPPDrri:
3487   case X86::VCMPPSrri:
3488   case X86::VCMPPDYrri:
3489   case X86::VCMPPSYrri:
3490   case X86::VCMPSDZrr:
3491   case X86::VCMPSSZrr:
3492   case X86::VCMPPDZrri:
3493   case X86::VCMPPSZrri:
3494   case X86::VCMPPDZ128rri:
3495   case X86::VCMPPSZ128rri:
3496   case X86::VCMPPDZ256rri:
3497   case X86::VCMPPSZ256rri: {
3498     // Float comparison can be safely commuted for
3499     // Ordered/Unordered/Equal/NotEqual tests
3500     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3501     switch (Imm) {
3502     case 0x00: // EQUAL
3503     case 0x03: // UNORDERED
3504     case 0x04: // NOT EQUAL
3505     case 0x07: // ORDERED
3506       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3507     default:
3508       return nullptr;
3509     }
3510   }
3511   case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
3512   case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
3513   case X86::VPCMPBZrri:    case X86::VPCMPUBZrri:
3514   case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
3515   case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
3516   case X86::VPCMPDZrri:    case X86::VPCMPUDZrri:
3517   case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
3518   case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
3519   case X86::VPCMPQZrri:    case X86::VPCMPUQZrri:
3520   case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
3521   case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
3522   case X86::VPCMPWZrri:    case X86::VPCMPUWZrri: {
3523     // Flip comparison mode immediate (if necessary).
3524     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3525     switch (Imm) {
3526     default: llvm_unreachable("Unreachable!");
3527     case 0x01: Imm = 0x06; break; // LT  -> NLE
3528     case 0x02: Imm = 0x05; break; // LE  -> NLT
3529     case 0x05: Imm = 0x02; break; // NLT -> LE
3530     case 0x06: Imm = 0x01; break; // NLE -> LT
3531     case 0x00: // EQ
3532     case 0x03: // FALSE
3533     case 0x04: // NE
3534     case 0x07: // TRUE
3535       break;
3536     }
3537     auto &WorkingMI = cloneIfNew(MI);
3538     WorkingMI.getOperand(3).setImm(Imm);
3539     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3540                                                    OpIdx1, OpIdx2);
3541   }
3542   case X86::VPCOMBri: case X86::VPCOMUBri:
3543   case X86::VPCOMDri: case X86::VPCOMUDri:
3544   case X86::VPCOMQri: case X86::VPCOMUQri:
3545   case X86::VPCOMWri: case X86::VPCOMUWri: {
3546     // Flip comparison mode immediate (if necessary).
3547     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3548     switch (Imm) {
3549     default: llvm_unreachable("Unreachable!");
3550     case 0x00: Imm = 0x02; break; // LT -> GT
3551     case 0x01: Imm = 0x03; break; // LE -> GE
3552     case 0x02: Imm = 0x00; break; // GT -> LT
3553     case 0x03: Imm = 0x01; break; // GE -> LE
3554     case 0x04: // EQ
3555     case 0x05: // NE
3556     case 0x06: // FALSE
3557     case 0x07: // TRUE
3558       break;
3559     }
3560     auto &WorkingMI = cloneIfNew(MI);
3561     WorkingMI.getOperand(3).setImm(Imm);
3562     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3563                                                    OpIdx1, OpIdx2);
3564   }
3565   case X86::VPERM2F128rr:
3566   case X86::VPERM2I128rr: {
3567     // Flip permute source immediate.
3568     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3569     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
3570     unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
3571     auto &WorkingMI = cloneIfNew(MI);
3572     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
3573     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3574                                                    OpIdx1, OpIdx2);
3575   }
3576   case X86::MOVHLPSrr:
3577   case X86::UNPCKHPDrr: {
3578     if (!Subtarget.hasSSE2())
3579       return nullptr;
3580 
3581     unsigned Opc = MI.getOpcode();
3582     switch (Opc) {
3583       default: llvm_unreachable("Unreachable!");
3584       case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
3585       case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
3586     }
3587     auto &WorkingMI = cloneIfNew(MI);
3588     WorkingMI.setDesc(get(Opc));
3589     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3590                                                    OpIdx1, OpIdx2);
3591   }
3592   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
3593   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3594   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
3595   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3596   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3597   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
3598   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
3599   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3600   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3601   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
3602   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
3603   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3604   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
3605   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3606   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
3607   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3608     unsigned Opc;
3609     switch (MI.getOpcode()) {
3610     default: llvm_unreachable("Unreachable!");
3611     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
3612     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
3613     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
3614     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3615     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3616     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3617     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
3618     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
3619     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
3620     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3621     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3622     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
3623     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3624     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3625     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3626     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
3627     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
3628     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
3629     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
3630     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
3631     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
3632     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3633     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3634     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3635     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3636     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3637     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3638     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
3639     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
3640     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
3641     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
3642     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
3643     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
3644     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3645     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3646     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3647     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
3648     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
3649     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
3650     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3651     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3652     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3653     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
3654     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
3655     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
3656     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3657     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3658     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3659     }
3660     auto &WorkingMI = cloneIfNew(MI);
3661     WorkingMI.setDesc(get(Opc));
3662     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3663                                                    OpIdx1, OpIdx2);
3664   }
3665   default:
3666     const X86InstrFMA3Group *FMA3Group =
3667         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
3668     if (FMA3Group) {
3669       unsigned Opc =
3670         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
3671       if (Opc == 0)
3672         return nullptr;
3673       auto &WorkingMI = cloneIfNew(MI);
3674       WorkingMI.setDesc(get(Opc));
3675       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3676                                                      OpIdx1, OpIdx2);
3677     }
3678 
3679     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3680   }
3681 }
3682 
3683 bool X86InstrInfo::findFMA3CommutedOpIndices(
3684     const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2,
3685     const X86InstrFMA3Group &FMA3Group) const {
3686   unsigned FirstCommutableVecOp = 1;
3687   unsigned LastCommutableVecOp = 3;
3688   unsigned KMaskOp = 0;
3689   if (FMA3Group.isKMasked()) {
3690     // The k-mask operand has index = 2 for masked and zero-masked operations.
3691     KMaskOp = 2;
3692 
3693     // The operand with index = 1 is used as a source for those elements for
3694     // which the corresponding bit in the k-mask is set to 0.
3695     if (FMA3Group.isKMergeMasked())
3696       FirstCommutableVecOp = 3;
3697 
3698     LastCommutableVecOp++;
3699   }
3700 
3701   if (isMem(MI, LastCommutableVecOp))
3702     LastCommutableVecOp--;
3703 
3704   // Only the first RegOpsNum operands are commutable.
3705   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3706   // that the operand is not specified/fixed.
3707   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3708       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
3709        SrcOpIdx1 == KMaskOp))
3710     return false;
3711   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3712       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
3713        SrcOpIdx2 == KMaskOp))
3714     return false;
3715 
3716   // Look for two different register operands assumed to be commutable
3717   // regardless of the FMA opcode. The FMA opcode is adjusted later.
3718   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3719       SrcOpIdx2 == CommuteAnyOperandIndex) {
3720     unsigned CommutableOpIdx1 = SrcOpIdx1;
3721     unsigned CommutableOpIdx2 = SrcOpIdx2;
3722 
3723     // At least one of operands to be commuted is not specified and
3724     // this method is free to choose appropriate commutable operands.
3725     if (SrcOpIdx1 == SrcOpIdx2)
3726       // Both of operands are not fixed. By default set one of commutable
3727       // operands to the last register operand of the instruction.
3728       CommutableOpIdx2 = LastCommutableVecOp;
3729     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3730       // Only one of operands is not fixed.
3731       CommutableOpIdx2 = SrcOpIdx1;
3732 
3733     // CommutableOpIdx2 is well defined now. Let's choose another commutable
3734     // operand and assign its index to CommutableOpIdx1.
3735     unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
3736     for (CommutableOpIdx1 = LastCommutableVecOp;
3737          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
3738       // Just ignore and skip the k-mask operand.
3739       if (CommutableOpIdx1 == KMaskOp)
3740         continue;
3741 
3742       // The commuted operands must have different registers.
3743       // Otherwise, the commute transformation does not change anything and
3744       // is useless then.
3745       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
3746         break;
3747     }
3748 
3749     // No appropriate commutable operands were found.
3750     if (CommutableOpIdx1 < FirstCommutableVecOp)
3751       return false;
3752 
3753     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3754     // to return those values.
3755     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3756                               CommutableOpIdx1, CommutableOpIdx2))
3757       return false;
3758   }
3759 
3760   // Check if we can adjust the opcode to preserve the semantics when
3761   // commute the register operands.
3762   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2, FMA3Group) != 0;
3763 }
3764 
3765 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
3766                                          unsigned &SrcOpIdx2) const {
3767   const MCInstrDesc &Desc = MI.getDesc();
3768   if (!Desc.isCommutable())
3769     return false;
3770 
3771   switch (MI.getOpcode()) {
3772   case X86::CMPSDrr:
3773   case X86::CMPSSrr:
3774   case X86::CMPPDrri:
3775   case X86::CMPPSrri:
3776   case X86::VCMPSDrr:
3777   case X86::VCMPSSrr:
3778   case X86::VCMPPDrri:
3779   case X86::VCMPPSrri:
3780   case X86::VCMPPDYrri:
3781   case X86::VCMPPSYrri:
3782   case X86::VCMPSDZrr:
3783   case X86::VCMPSSZrr:
3784   case X86::VCMPPDZrri:
3785   case X86::VCMPPSZrri:
3786   case X86::VCMPPDZ128rri:
3787   case X86::VCMPPSZ128rri:
3788   case X86::VCMPPDZ256rri:
3789   case X86::VCMPPSZ256rri: {
3790     // Float comparison can be safely commuted for
3791     // Ordered/Unordered/Equal/NotEqual tests
3792     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3793     switch (Imm) {
3794     case 0x00: // EQUAL
3795     case 0x03: // UNORDERED
3796     case 0x04: // NOT EQUAL
3797     case 0x07: // ORDERED
3798       // The indices of the commutable operands are 1 and 2.
3799       // Assign them to the returned operand indices here.
3800       return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
3801     }
3802     return false;
3803   }
3804   default:
3805     const X86InstrFMA3Group *FMA3Group =
3806         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
3807     if (FMA3Group)
3808       return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2, *FMA3Group);
3809 
3810     // Handled masked instructions since we need to skip over the mask input
3811     // and the preserved input.
3812     if (Desc.TSFlags & X86II::EVEX_K) {
3813       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
3814       // If there is no preserved input we only need to skip 1 operand.
3815       if (MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
3816                                             MCOI::TIED_TO) != -1)
3817         ++CommutableOpIdx1;
3818       unsigned CommutableOpIdx2 = CommutableOpIdx1 + 1;
3819       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3820                                 CommutableOpIdx1, CommutableOpIdx2))
3821         return false;
3822 
3823       if (!MI.getOperand(SrcOpIdx1).isReg() ||
3824           !MI.getOperand(SrcOpIdx2).isReg())
3825         // No idea.
3826         return false;
3827       return true;
3828     }
3829 
3830     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3831   }
3832   return false;
3833 }
3834 
3835 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
3836   switch (BrOpc) {
3837   default: return X86::COND_INVALID;
3838   case X86::JE_1:  return X86::COND_E;
3839   case X86::JNE_1: return X86::COND_NE;
3840   case X86::JL_1:  return X86::COND_L;
3841   case X86::JLE_1: return X86::COND_LE;
3842   case X86::JG_1:  return X86::COND_G;
3843   case X86::JGE_1: return X86::COND_GE;
3844   case X86::JB_1:  return X86::COND_B;
3845   case X86::JBE_1: return X86::COND_BE;
3846   case X86::JA_1:  return X86::COND_A;
3847   case X86::JAE_1: return X86::COND_AE;
3848   case X86::JS_1:  return X86::COND_S;
3849   case X86::JNS_1: return X86::COND_NS;
3850   case X86::JP_1:  return X86::COND_P;
3851   case X86::JNP_1: return X86::COND_NP;
3852   case X86::JO_1:  return X86::COND_O;
3853   case X86::JNO_1: return X86::COND_NO;
3854   }
3855 }
3856 
3857 /// Return condition code of a SET opcode.
3858 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3859   switch (Opc) {
3860   default: return X86::COND_INVALID;
3861   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
3862   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3863   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
3864   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3865   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
3866   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
3867   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3868   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
3869   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3870   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3871   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3872   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3873   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3874   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
3875   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
3876   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
3877   }
3878 }
3879 
3880 /// Return condition code of a CMov opcode.
3881 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
3882   switch (Opc) {
3883   default: return X86::COND_INVALID;
3884   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
3885   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
3886     return X86::COND_A;
3887   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3888   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3889     return X86::COND_AE;
3890   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
3891   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
3892     return X86::COND_B;
3893   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3894   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3895     return X86::COND_BE;
3896   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
3897   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
3898     return X86::COND_E;
3899   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
3900   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
3901     return X86::COND_G;
3902   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3903   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3904     return X86::COND_GE;
3905   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
3906   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
3907     return X86::COND_L;
3908   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3909   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3910     return X86::COND_LE;
3911   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3912   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3913     return X86::COND_NE;
3914   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3915   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3916     return X86::COND_NO;
3917   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3918   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3919     return X86::COND_NP;
3920   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3921   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3922     return X86::COND_NS;
3923   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
3924   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
3925     return X86::COND_O;
3926   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
3927   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
3928     return X86::COND_P;
3929   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
3930   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
3931     return X86::COND_S;
3932   }
3933 }
3934 
3935 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3936   switch (CC) {
3937   default: llvm_unreachable("Illegal condition code!");
3938   case X86::COND_E:  return X86::JE_1;
3939   case X86::COND_NE: return X86::JNE_1;
3940   case X86::COND_L:  return X86::JL_1;
3941   case X86::COND_LE: return X86::JLE_1;
3942   case X86::COND_G:  return X86::JG_1;
3943   case X86::COND_GE: return X86::JGE_1;
3944   case X86::COND_B:  return X86::JB_1;
3945   case X86::COND_BE: return X86::JBE_1;
3946   case X86::COND_A:  return X86::JA_1;
3947   case X86::COND_AE: return X86::JAE_1;
3948   case X86::COND_S:  return X86::JS_1;
3949   case X86::COND_NS: return X86::JNS_1;
3950   case X86::COND_P:  return X86::JP_1;
3951   case X86::COND_NP: return X86::JNP_1;
3952   case X86::COND_O:  return X86::JO_1;
3953   case X86::COND_NO: return X86::JNO_1;
3954   }
3955 }
3956 
3957 /// Return the inverse of the specified condition,
3958 /// e.g. turning COND_E to COND_NE.
3959 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3960   switch (CC) {
3961   default: llvm_unreachable("Illegal condition code!");
3962   case X86::COND_E:  return X86::COND_NE;
3963   case X86::COND_NE: return X86::COND_E;
3964   case X86::COND_L:  return X86::COND_GE;
3965   case X86::COND_LE: return X86::COND_G;
3966   case X86::COND_G:  return X86::COND_LE;
3967   case X86::COND_GE: return X86::COND_L;
3968   case X86::COND_B:  return X86::COND_AE;
3969   case X86::COND_BE: return X86::COND_A;
3970   case X86::COND_A:  return X86::COND_BE;
3971   case X86::COND_AE: return X86::COND_B;
3972   case X86::COND_S:  return X86::COND_NS;
3973   case X86::COND_NS: return X86::COND_S;
3974   case X86::COND_P:  return X86::COND_NP;
3975   case X86::COND_NP: return X86::COND_P;
3976   case X86::COND_O:  return X86::COND_NO;
3977   case X86::COND_NO: return X86::COND_O;
3978   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
3979   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
3980   }
3981 }
3982 
3983 /// Assuming the flags are set by MI(a,b), return the condition code if we
3984 /// modify the instructions such that flags are set by MI(b,a).
3985 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3986   switch (CC) {
3987   default: return X86::COND_INVALID;
3988   case X86::COND_E:  return X86::COND_E;
3989   case X86::COND_NE: return X86::COND_NE;
3990   case X86::COND_L:  return X86::COND_G;
3991   case X86::COND_LE: return X86::COND_GE;
3992   case X86::COND_G:  return X86::COND_L;
3993   case X86::COND_GE: return X86::COND_LE;
3994   case X86::COND_B:  return X86::COND_A;
3995   case X86::COND_BE: return X86::COND_AE;
3996   case X86::COND_A:  return X86::COND_B;
3997   case X86::COND_AE: return X86::COND_BE;
3998   }
3999 }
4000 
4001 /// Return a set opcode for the given condition and
4002 /// whether it has memory operand.
4003 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
4004   static const uint16_t Opc[16][2] = {
4005     { X86::SETAr,  X86::SETAm  },
4006     { X86::SETAEr, X86::SETAEm },
4007     { X86::SETBr,  X86::SETBm  },
4008     { X86::SETBEr, X86::SETBEm },
4009     { X86::SETEr,  X86::SETEm  },
4010     { X86::SETGr,  X86::SETGm  },
4011     { X86::SETGEr, X86::SETGEm },
4012     { X86::SETLr,  X86::SETLm  },
4013     { X86::SETLEr, X86::SETLEm },
4014     { X86::SETNEr, X86::SETNEm },
4015     { X86::SETNOr, X86::SETNOm },
4016     { X86::SETNPr, X86::SETNPm },
4017     { X86::SETNSr, X86::SETNSm },
4018     { X86::SETOr,  X86::SETOm  },
4019     { X86::SETPr,  X86::SETPm  },
4020     { X86::SETSr,  X86::SETSm  }
4021   };
4022 
4023   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
4024   return Opc[CC][HasMemoryOperand ? 1 : 0];
4025 }
4026 
4027 /// Return a cmov opcode for the given condition,
4028 /// register size in bytes, and operand type.
4029 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
4030                               bool HasMemoryOperand) {
4031   static const uint16_t Opc[32][3] = {
4032     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
4033     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
4034     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
4035     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
4036     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
4037     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
4038     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
4039     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
4040     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
4041     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
4042     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
4043     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
4044     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
4045     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
4046     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
4047     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
4048     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
4049     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
4050     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
4051     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
4052     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
4053     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
4054     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
4055     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
4056     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
4057     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
4058     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
4059     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
4060     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
4061     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
4062     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
4063     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
4064   };
4065 
4066   assert(CC < 16 && "Can only handle standard cond codes");
4067   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
4068   switch(RegBytes) {
4069   default: llvm_unreachable("Illegal register size!");
4070   case 2: return Opc[Idx][0];
4071   case 4: return Opc[Idx][1];
4072   case 8: return Opc[Idx][2];
4073   }
4074 }
4075 
4076 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
4077   if (!MI.isTerminator()) return false;
4078 
4079   // Conditional branch is a special case.
4080   if (MI.isBranch() && !MI.isBarrier())
4081     return true;
4082   if (!MI.isPredicable())
4083     return true;
4084   return !isPredicated(MI);
4085 }
4086 
4087 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
4088   switch (MI.getOpcode()) {
4089   case X86::TCRETURNdi:
4090   case X86::TCRETURNri:
4091   case X86::TCRETURNmi:
4092   case X86::TCRETURNdi64:
4093   case X86::TCRETURNri64:
4094   case X86::TCRETURNmi64:
4095     return true;
4096   default:
4097     return false;
4098   }
4099 }
4100 
4101 bool X86InstrInfo::canMakeTailCallConditional(
4102     SmallVectorImpl<MachineOperand> &BranchCond,
4103     const MachineInstr &TailCall) const {
4104   if (TailCall.getOpcode() != X86::TCRETURNdi &&
4105       TailCall.getOpcode() != X86::TCRETURNdi64) {
4106     // Only direct calls can be done with a conditional branch.
4107     return false;
4108   }
4109 
4110   if (Subtarget.isTargetWin64()) {
4111     // Conditional tail calls confuse the Win64 unwinder.
4112     // TODO: Allow them for "leaf" functions; PR30337.
4113     return false;
4114   }
4115 
4116   assert(BranchCond.size() == 1);
4117   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
4118     // Can't make a conditional tail call with this condition.
4119     return false;
4120   }
4121 
4122   const X86MachineFunctionInfo *X86FI =
4123       TailCall.getParent()->getParent()->getInfo<X86MachineFunctionInfo>();
4124   if (X86FI->getTCReturnAddrDelta() != 0 ||
4125       TailCall.getOperand(1).getImm() != 0) {
4126     // A conditional tail call cannot do any stack adjustment.
4127     return false;
4128   }
4129 
4130   return true;
4131 }
4132 
4133 void X86InstrInfo::replaceBranchWithTailCall(
4134     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
4135     const MachineInstr &TailCall) const {
4136   assert(canMakeTailCallConditional(BranchCond, TailCall));
4137 
4138   MachineBasicBlock::iterator I = MBB.end();
4139   while (I != MBB.begin()) {
4140     --I;
4141     if (I->isDebugValue())
4142       continue;
4143     if (!I->isBranch())
4144       assert(0 && "Can't find the branch to replace!");
4145 
4146     X86::CondCode CC = getCondFromBranchOpc(I->getOpcode());
4147     assert(BranchCond.size() == 1);
4148     if (CC != BranchCond[0].getImm())
4149       continue;
4150 
4151     break;
4152   }
4153 
4154   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
4155                                                          : X86::TCRETURNdi64cc;
4156 
4157   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
4158   MIB->addOperand(TailCall.getOperand(0)); // Destination.
4159   MIB.addImm(0); // Stack offset (not used).
4160   MIB->addOperand(BranchCond[0]); // Condition.
4161   MIB->addOperand(TailCall.getOperand(2)); // Regmask.
4162 
4163   I->eraseFromParent();
4164 }
4165 
4166 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
4167 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
4168 // fallthrough MBB cannot be identified.
4169 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
4170                                             MachineBasicBlock *TBB) {
4171   // Look for non-EHPad successors other than TBB. If we find exactly one, it
4172   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
4173   // and fallthrough MBB. If we find more than one, we cannot identify the
4174   // fallthrough MBB and should return nullptr.
4175   MachineBasicBlock *FallthroughBB = nullptr;
4176   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
4177     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
4178       continue;
4179     // Return a nullptr if we found more than one fallthrough successor.
4180     if (FallthroughBB && FallthroughBB != TBB)
4181       return nullptr;
4182     FallthroughBB = *SI;
4183   }
4184   return FallthroughBB;
4185 }
4186 
4187 bool X86InstrInfo::AnalyzeBranchImpl(
4188     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
4189     SmallVectorImpl<MachineOperand> &Cond,
4190     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
4191 
4192   // Start from the bottom of the block and work up, examining the
4193   // terminator instructions.
4194   MachineBasicBlock::iterator I = MBB.end();
4195   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
4196   while (I != MBB.begin()) {
4197     --I;
4198     if (I->isDebugValue())
4199       continue;
4200 
4201     // Working from the bottom, when we see a non-terminator instruction, we're
4202     // done.
4203     if (!isUnpredicatedTerminator(*I))
4204       break;
4205 
4206     // A terminator that isn't a branch can't easily be handled by this
4207     // analysis.
4208     if (!I->isBranch())
4209       return true;
4210 
4211     // Handle unconditional branches.
4212     if (I->getOpcode() == X86::JMP_1) {
4213       UnCondBrIter = I;
4214 
4215       if (!AllowModify) {
4216         TBB = I->getOperand(0).getMBB();
4217         continue;
4218       }
4219 
4220       // If the block has any instructions after a JMP, delete them.
4221       while (std::next(I) != MBB.end())
4222         std::next(I)->eraseFromParent();
4223 
4224       Cond.clear();
4225       FBB = nullptr;
4226 
4227       // Delete the JMP if it's equivalent to a fall-through.
4228       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
4229         TBB = nullptr;
4230         I->eraseFromParent();
4231         I = MBB.end();
4232         UnCondBrIter = MBB.end();
4233         continue;
4234       }
4235 
4236       // TBB is used to indicate the unconditional destination.
4237       TBB = I->getOperand(0).getMBB();
4238       continue;
4239     }
4240 
4241     // Handle conditional branches.
4242     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
4243     if (BranchCode == X86::COND_INVALID)
4244       return true;  // Can't handle indirect branch.
4245 
4246     // Working from the bottom, handle the first conditional branch.
4247     if (Cond.empty()) {
4248       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4249       if (AllowModify && UnCondBrIter != MBB.end() &&
4250           MBB.isLayoutSuccessor(TargetBB)) {
4251         // If we can modify the code and it ends in something like:
4252         //
4253         //     jCC L1
4254         //     jmp L2
4255         //   L1:
4256         //     ...
4257         //   L2:
4258         //
4259         // Then we can change this to:
4260         //
4261         //     jnCC L2
4262         //   L1:
4263         //     ...
4264         //   L2:
4265         //
4266         // Which is a bit more efficient.
4267         // We conditionally jump to the fall-through block.
4268         BranchCode = GetOppositeBranchCondition(BranchCode);
4269         unsigned JNCC = GetCondBranchFromCond(BranchCode);
4270         MachineBasicBlock::iterator OldInst = I;
4271 
4272         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
4273           .addMBB(UnCondBrIter->getOperand(0).getMBB());
4274         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
4275           .addMBB(TargetBB);
4276 
4277         OldInst->eraseFromParent();
4278         UnCondBrIter->eraseFromParent();
4279 
4280         // Restart the analysis.
4281         UnCondBrIter = MBB.end();
4282         I = MBB.end();
4283         continue;
4284       }
4285 
4286       FBB = TBB;
4287       TBB = I->getOperand(0).getMBB();
4288       Cond.push_back(MachineOperand::CreateImm(BranchCode));
4289       CondBranches.push_back(&*I);
4290       continue;
4291     }
4292 
4293     // Handle subsequent conditional branches. Only handle the case where all
4294     // conditional branches branch to the same destination and their condition
4295     // opcodes fit one of the special multi-branch idioms.
4296     assert(Cond.size() == 1);
4297     assert(TBB);
4298 
4299     // If the conditions are the same, we can leave them alone.
4300     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
4301     auto NewTBB = I->getOperand(0).getMBB();
4302     if (OldBranchCode == BranchCode && TBB == NewTBB)
4303       continue;
4304 
4305     // If they differ, see if they fit one of the known patterns. Theoretically,
4306     // we could handle more patterns here, but we shouldn't expect to see them
4307     // if instruction selection has done a reasonable job.
4308     if (TBB == NewTBB &&
4309                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4310                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
4311       BranchCode = X86::COND_NE_OR_P;
4312     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4313                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4314       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4315         return true;
4316 
4317       // X86::COND_E_AND_NP usually has two different branch destinations.
4318       //
4319       // JP B1
4320       // JE B2
4321       // JMP B1
4322       // B1:
4323       // B2:
4324       //
4325       // Here this condition branches to B2 only if NP && E. It has another
4326       // equivalent form:
4327       //
4328       // JNE B1
4329       // JNP B2
4330       // JMP B1
4331       // B1:
4332       // B2:
4333       //
4334       // Similarly it branches to B2 only if E && NP. That is why this condition
4335       // is named with COND_E_AND_NP.
4336       BranchCode = X86::COND_E_AND_NP;
4337     } else
4338       return true;
4339 
4340     // Update the MachineOperand.
4341     Cond[0].setImm(BranchCode);
4342     CondBranches.push_back(&*I);
4343   }
4344 
4345   return false;
4346 }
4347 
4348 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
4349                                  MachineBasicBlock *&TBB,
4350                                  MachineBasicBlock *&FBB,
4351                                  SmallVectorImpl<MachineOperand> &Cond,
4352                                  bool AllowModify) const {
4353   SmallVector<MachineInstr *, 4> CondBranches;
4354   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4355 }
4356 
4357 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
4358                                           MachineBranchPredicate &MBP,
4359                                           bool AllowModify) const {
4360   using namespace std::placeholders;
4361 
4362   SmallVector<MachineOperand, 4> Cond;
4363   SmallVector<MachineInstr *, 4> CondBranches;
4364   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4365                         AllowModify))
4366     return true;
4367 
4368   if (Cond.size() != 1)
4369     return true;
4370 
4371   assert(MBP.TrueDest && "expected!");
4372 
4373   if (!MBP.FalseDest)
4374     MBP.FalseDest = MBB.getNextNode();
4375 
4376   const TargetRegisterInfo *TRI = &getRegisterInfo();
4377 
4378   MachineInstr *ConditionDef = nullptr;
4379   bool SingleUseCondition = true;
4380 
4381   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4382     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4383       ConditionDef = &*I;
4384       break;
4385     }
4386 
4387     if (I->readsRegister(X86::EFLAGS, TRI))
4388       SingleUseCondition = false;
4389   }
4390 
4391   if (!ConditionDef)
4392     return true;
4393 
4394   if (SingleUseCondition) {
4395     for (auto *Succ : MBB.successors())
4396       if (Succ->isLiveIn(X86::EFLAGS))
4397         SingleUseCondition = false;
4398   }
4399 
4400   MBP.ConditionDef = ConditionDef;
4401   MBP.SingleUseCondition = SingleUseCondition;
4402 
4403   // Currently we only recognize the simple pattern:
4404   //
4405   //   test %reg, %reg
4406   //   je %label
4407   //
4408   const unsigned TestOpcode =
4409       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4410 
4411   if (ConditionDef->getOpcode() == TestOpcode &&
4412       ConditionDef->getNumOperands() == 3 &&
4413       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4414       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4415     MBP.LHS = ConditionDef->getOperand(0);
4416     MBP.RHS = MachineOperand::CreateImm(0);
4417     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4418                         ? MachineBranchPredicate::PRED_NE
4419                         : MachineBranchPredicate::PRED_EQ;
4420     return false;
4421   }
4422 
4423   return true;
4424 }
4425 
4426 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
4427   MachineBasicBlock::iterator I = MBB.end();
4428   unsigned Count = 0;
4429 
4430   while (I != MBB.begin()) {
4431     --I;
4432     if (I->isDebugValue())
4433       continue;
4434     if (I->getOpcode() != X86::JMP_1 &&
4435         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
4436       break;
4437     // Remove the branch.
4438     I->eraseFromParent();
4439     I = MBB.end();
4440     ++Count;
4441   }
4442 
4443   return Count;
4444 }
4445 
4446 unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB,
4447                                     MachineBasicBlock *TBB,
4448                                     MachineBasicBlock *FBB,
4449                                     ArrayRef<MachineOperand> Cond,
4450                                     const DebugLoc &DL) const {
4451   // Shouldn't be a fall through.
4452   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
4453   assert((Cond.size() == 1 || Cond.size() == 0) &&
4454          "X86 branch conditions have one component!");
4455 
4456   if (Cond.empty()) {
4457     // Unconditional branch?
4458     assert(!FBB && "Unconditional branch with multiple successors!");
4459     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
4460     return 1;
4461   }
4462 
4463   // If FBB is null, it is implied to be a fall-through block.
4464   bool FallThru = FBB == nullptr;
4465 
4466   // Conditional branch.
4467   unsigned Count = 0;
4468   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4469   switch (CC) {
4470   case X86::COND_NE_OR_P:
4471     // Synthesize NE_OR_P with two branches.
4472     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
4473     ++Count;
4474     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
4475     ++Count;
4476     break;
4477   case X86::COND_E_AND_NP:
4478     // Use the next block of MBB as FBB if it is null.
4479     if (FBB == nullptr) {
4480       FBB = getFallThroughMBB(&MBB, TBB);
4481       assert(FBB && "MBB cannot be the last block in function when the false "
4482                     "body is a fall-through.");
4483     }
4484     // Synthesize COND_E_AND_NP with two branches.
4485     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4486     ++Count;
4487     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4488     ++Count;
4489     break;
4490   default: {
4491     unsigned Opc = GetCondBranchFromCond(CC);
4492     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
4493     ++Count;
4494   }
4495   }
4496   if (!FallThru) {
4497     // Two-way Conditional branch. Insert the second branch.
4498     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
4499     ++Count;
4500   }
4501   return Count;
4502 }
4503 
4504 bool X86InstrInfo::
4505 canInsertSelect(const MachineBasicBlock &MBB,
4506                 ArrayRef<MachineOperand> Cond,
4507                 unsigned TrueReg, unsigned FalseReg,
4508                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4509   // Not all subtargets have cmov instructions.
4510   if (!Subtarget.hasCMov())
4511     return false;
4512   if (Cond.size() != 1)
4513     return false;
4514   // We cannot do the composite conditions, at least not in SSA form.
4515   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4516     return false;
4517 
4518   // Check register classes.
4519   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4520   const TargetRegisterClass *RC =
4521     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4522   if (!RC)
4523     return false;
4524 
4525   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4526   if (X86::GR16RegClass.hasSubClassEq(RC) ||
4527       X86::GR32RegClass.hasSubClassEq(RC) ||
4528       X86::GR64RegClass.hasSubClassEq(RC)) {
4529     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4530     // Bridge. Probably Ivy Bridge as well.
4531     CondCycles = 2;
4532     TrueCycles = 2;
4533     FalseCycles = 2;
4534     return true;
4535   }
4536 
4537   // Can't do vectors.
4538   return false;
4539 }
4540 
4541 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4542                                 MachineBasicBlock::iterator I,
4543                                 const DebugLoc &DL, unsigned DstReg,
4544                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
4545                                 unsigned FalseReg) const {
4546   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4547   assert(Cond.size() == 1 && "Invalid Cond array");
4548   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4549                                  MRI.getRegClass(DstReg)->getSize(),
4550                                  false /*HasMemoryOperand*/);
4551   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
4552 }
4553 
4554 /// Test if the given register is a physical h register.
4555 static bool isHReg(unsigned Reg) {
4556   return X86::GR8_ABCD_HRegClass.contains(Reg);
4557 }
4558 
4559 // Try and copy between VR128/VR64 and GR64 registers.
4560 static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg,
4561                                         const X86Subtarget &Subtarget) {
4562   bool HasAVX = Subtarget.hasAVX();
4563   bool HasAVX512 = Subtarget.hasAVX512();
4564 
4565   // SrcReg(MaskReg) -> DestReg(GR64)
4566   // SrcReg(MaskReg) -> DestReg(GR32)
4567   // SrcReg(MaskReg) -> DestReg(GR16)
4568   // SrcReg(MaskReg) -> DestReg(GR8)
4569 
4570   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4571   if (X86::VK16RegClass.contains(SrcReg)) {
4572     if (X86::GR64RegClass.contains(DestReg)) {
4573       assert(Subtarget.hasBWI());
4574       return X86::KMOVQrk;
4575     }
4576     if (X86::GR32RegClass.contains(DestReg))
4577       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
4578     if (X86::GR16RegClass.contains(DestReg)) {
4579       DestReg = getX86SubSuperRegister(DestReg, 32);
4580       return X86::KMOVWrk;
4581     }
4582     if (X86::GR8RegClass.contains(DestReg)) {
4583       DestReg = getX86SubSuperRegister(DestReg, 32);
4584       return Subtarget.hasDQI() ? X86::KMOVBrk : X86::KMOVWrk;
4585     }
4586   }
4587 
4588   // SrcReg(GR64) -> DestReg(MaskReg)
4589   // SrcReg(GR32) -> DestReg(MaskReg)
4590   // SrcReg(GR16) -> DestReg(MaskReg)
4591   // SrcReg(GR8)  -> DestReg(MaskReg)
4592 
4593   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4594   if (X86::VK16RegClass.contains(DestReg)) {
4595     if (X86::GR64RegClass.contains(SrcReg)) {
4596       assert(Subtarget.hasBWI());
4597       return X86::KMOVQkr;
4598     }
4599     if (X86::GR32RegClass.contains(SrcReg))
4600       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
4601     if (X86::GR16RegClass.contains(SrcReg)) {
4602       SrcReg = getX86SubSuperRegister(SrcReg, 32);
4603       return X86::KMOVWkr;
4604     }
4605     if (X86::GR8RegClass.contains(SrcReg)) {
4606       SrcReg = getX86SubSuperRegister(SrcReg, 32);
4607       return Subtarget.hasDQI() ? X86::KMOVBkr : X86::KMOVWkr;
4608     }
4609   }
4610 
4611 
4612   // SrcReg(VR128) -> DestReg(GR64)
4613   // SrcReg(VR64)  -> DestReg(GR64)
4614   // SrcReg(GR64)  -> DestReg(VR128)
4615   // SrcReg(GR64)  -> DestReg(VR64)
4616 
4617   if (X86::GR64RegClass.contains(DestReg)) {
4618     if (X86::VR128XRegClass.contains(SrcReg))
4619       // Copy from a VR128 register to a GR64 register.
4620       return HasAVX512 ? X86::VMOVPQIto64Zrr :
4621              HasAVX    ? X86::VMOVPQIto64rr  :
4622                          X86::MOVPQIto64rr;
4623     if (X86::VR64RegClass.contains(SrcReg))
4624       // Copy from a VR64 register to a GR64 register.
4625       return X86::MMX_MOVD64from64rr;
4626   } else if (X86::GR64RegClass.contains(SrcReg)) {
4627     // Copy from a GR64 register to a VR128 register.
4628     if (X86::VR128XRegClass.contains(DestReg))
4629       return HasAVX512 ? X86::VMOV64toPQIZrr :
4630              HasAVX    ? X86::VMOV64toPQIrr  :
4631                          X86::MOV64toPQIrr;
4632     // Copy from a GR64 register to a VR64 register.
4633     if (X86::VR64RegClass.contains(DestReg))
4634       return X86::MMX_MOVD64to64rr;
4635   }
4636 
4637   // SrcReg(FR32) -> DestReg(GR32)
4638   // SrcReg(GR32) -> DestReg(FR32)
4639 
4640   if (X86::GR32RegClass.contains(DestReg) &&
4641       X86::FR32XRegClass.contains(SrcReg))
4642     // Copy from a FR32 register to a GR32 register.
4643     return HasAVX512 ? X86::VMOVSS2DIZrr :
4644            HasAVX    ? X86::VMOVSS2DIrr  :
4645                        X86::MOVSS2DIrr;
4646 
4647   if (X86::FR32XRegClass.contains(DestReg) &&
4648       X86::GR32RegClass.contains(SrcReg))
4649     // Copy from a GR32 register to a FR32 register.
4650     return HasAVX512 ? X86::VMOVDI2SSZrr :
4651            HasAVX    ? X86::VMOVDI2SSrr  :
4652                        X86::MOVDI2SSrr;
4653   return 0;
4654 }
4655 
4656 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4657                                MachineBasicBlock::iterator MI,
4658                                const DebugLoc &DL, unsigned DestReg,
4659                                unsigned SrcReg, bool KillSrc) const {
4660   // First deal with the normal symmetric copies.
4661   bool HasAVX = Subtarget.hasAVX();
4662   bool HasVLX = Subtarget.hasVLX();
4663   unsigned Opc = 0;
4664   if (X86::GR64RegClass.contains(DestReg, SrcReg))
4665     Opc = X86::MOV64rr;
4666   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4667     Opc = X86::MOV32rr;
4668   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4669     Opc = X86::MOV16rr;
4670   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4671     // Copying to or from a physical H register on x86-64 requires a NOREX
4672     // move.  Otherwise use a normal move.
4673     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
4674         Subtarget.is64Bit()) {
4675       Opc = X86::MOV8rr_NOREX;
4676       // Both operands must be encodable without an REX prefix.
4677       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4678              "8-bit H register can not be copied outside GR8_NOREX");
4679     } else
4680       Opc = X86::MOV8rr;
4681   }
4682   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4683     Opc = X86::MMX_MOVQ64rr;
4684   else if (X86::VR128XRegClass.contains(DestReg, SrcReg))
4685     Opc = HasVLX ? X86::VMOVAPSZ128rr : HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4686   else if (X86::VR256XRegClass.contains(DestReg, SrcReg))
4687     Opc = HasVLX ? X86::VMOVAPSZ256rr : X86::VMOVAPSYrr;
4688   else if (X86::VR512RegClass.contains(DestReg, SrcReg))
4689     Opc = X86::VMOVAPSZrr;
4690   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4691   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
4692     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
4693   if (!Opc)
4694     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4695 
4696   if (Opc) {
4697     BuildMI(MBB, MI, DL, get(Opc), DestReg)
4698       .addReg(SrcReg, getKillRegState(KillSrc));
4699     return;
4700   }
4701 
4702   bool FromEFLAGS = SrcReg == X86::EFLAGS;
4703   bool ToEFLAGS = DestReg == X86::EFLAGS;
4704   int Reg = FromEFLAGS ? DestReg : SrcReg;
4705   bool is32 = X86::GR32RegClass.contains(Reg);
4706   bool is64 = X86::GR64RegClass.contains(Reg);
4707 
4708   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
4709     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4710     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4711     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4712     int Pop = is64 ? X86::POP64r : X86::POP32r;
4713     int PopF = is64 ? X86::POPF64 : X86::POPF32;
4714     int AX = is64 ? X86::RAX : X86::EAX;
4715 
4716     if (!Subtarget.hasLAHFSAHF()) {
4717       assert(Subtarget.is64Bit() &&
4718              "Not having LAHF/SAHF only happens on 64-bit.");
4719       // Moving EFLAGS to / from another register requires a push and a pop.
4720       // Notice that we have to adjust the stack if we don't want to clobber the
4721       // first frame index. See X86FrameLowering.cpp - usesTheStack.
4722       if (FromEFLAGS) {
4723         BuildMI(MBB, MI, DL, get(PushF));
4724         BuildMI(MBB, MI, DL, get(Pop), DestReg);
4725       }
4726       if (ToEFLAGS) {
4727         BuildMI(MBB, MI, DL, get(Push))
4728             .addReg(SrcReg, getKillRegState(KillSrc));
4729         BuildMI(MBB, MI, DL, get(PopF));
4730       }
4731       return;
4732     }
4733 
4734     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4735     // inefficient. Instead:
4736     //   - Save the overflow flag OF into AL using SETO, and restore it using a
4737     //     signed 8-bit addition of AL and INT8_MAX.
4738     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4739     //     using LAHF/SAHF.
4740     //   - When RAX/EAX is live and isn't the destination register, make sure it
4741     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4742     //     the flags.
4743     // This approach is ~2.25x faster than using PUSHF/POPF.
4744     //
4745     // This is still somewhat inefficient because we don't know which flags are
4746     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4747     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4748     //
4749     // PUSHF/POPF is also potentially incorrect because it affects other flags
4750     // such as TF/IF/DF, which LLVM doesn't model.
4751     //
4752     // Notice that we have to adjust the stack if we don't want to clobber the
4753     // first frame index.
4754     // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
4755 
4756     const TargetRegisterInfo *TRI = &getRegisterInfo();
4757     MachineBasicBlock::LivenessQueryResult LQR =
4758         MBB.computeRegisterLiveness(TRI, AX, MI);
4759     // We do not want to save and restore AX if we do not have to.
4760     // Moreover, if we do so whereas AX is dead, we would need to set
4761     // an undef flag on the use of AX, otherwise the verifier will
4762     // complain that we read an undef value.
4763     // We do not want to change the behavior of the machine verifier
4764     // as this is usually wrong to read an undef value.
4765     if (MachineBasicBlock::LQR_Unknown == LQR) {
4766       LivePhysRegs LPR(TRI);
4767       LPR.addLiveOuts(MBB);
4768       MachineBasicBlock::iterator I = MBB.end();
4769       while (I != MI) {
4770         --I;
4771         LPR.stepBackward(*I);
4772       }
4773       // AX contains the top most register in the aliasing hierarchy.
4774       // It may not be live, but one of its aliases may be.
4775       for (MCRegAliasIterator AI(AX, TRI, true);
4776            AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
4777         LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
4778                                 : MachineBasicBlock::LQR_Dead;
4779     }
4780     bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4781     if (!AXDead)
4782       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
4783     if (FromEFLAGS) {
4784       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4785       BuildMI(MBB, MI, DL, get(X86::LAHF));
4786       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
4787     }
4788     if (ToEFLAGS) {
4789       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4790       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4791           .addReg(X86::AL)
4792           .addImm(INT8_MAX);
4793       BuildMI(MBB, MI, DL, get(X86::SAHF));
4794     }
4795     if (!AXDead)
4796       BuildMI(MBB, MI, DL, get(Pop), AX);
4797     return;
4798   }
4799 
4800   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4801                << " to " << RI.getName(DestReg) << '\n');
4802   llvm_unreachable("Cannot emit physreg copy instruction");
4803 }
4804 
4805 static unsigned getLoadStoreRegOpcode(unsigned Reg,
4806                                       const TargetRegisterClass *RC,
4807                                       bool isStackAligned,
4808                                       const X86Subtarget &STI,
4809                                       bool load) {
4810   bool HasAVX = STI.hasAVX();
4811   bool HasAVX512 = STI.hasAVX512();
4812   bool HasVLX = STI.hasVLX();
4813 
4814   switch (RC->getSize()) {
4815   default:
4816     llvm_unreachable("Unknown spill size");
4817   case 1:
4818     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
4819     if (STI.is64Bit())
4820       // Copying to or from a physical H register on x86-64 requires a NOREX
4821       // move.  Otherwise use a normal move.
4822       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4823         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4824     return load ? X86::MOV8rm : X86::MOV8mr;
4825   case 2:
4826     if (X86::VK16RegClass.hasSubClassEq(RC))
4827       return load ? X86::KMOVWkm : X86::KMOVWmk;
4828     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4829     return load ? X86::MOV16rm : X86::MOV16mr;
4830   case 4:
4831     if (X86::GR32RegClass.hasSubClassEq(RC))
4832       return load ? X86::MOV32rm : X86::MOV32mr;
4833     if (X86::FR32XRegClass.hasSubClassEq(RC))
4834       return load ?
4835         (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4836         (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
4837     if (X86::RFP32RegClass.hasSubClassEq(RC))
4838       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4839     if (X86::VK32RegClass.hasSubClassEq(RC))
4840       return load ? X86::KMOVDkm : X86::KMOVDmk;
4841     llvm_unreachable("Unknown 4-byte regclass");
4842   case 8:
4843     if (X86::GR64RegClass.hasSubClassEq(RC))
4844       return load ? X86::MOV64rm : X86::MOV64mr;
4845     if (X86::FR64XRegClass.hasSubClassEq(RC))
4846       return load ?
4847         (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4848         (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
4849     if (X86::VR64RegClass.hasSubClassEq(RC))
4850       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4851     if (X86::RFP64RegClass.hasSubClassEq(RC))
4852       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4853     if (X86::VK64RegClass.hasSubClassEq(RC))
4854       return load ? X86::KMOVQkm : X86::KMOVQmk;
4855     llvm_unreachable("Unknown 8-byte regclass");
4856   case 10:
4857     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
4858     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
4859   case 16: {
4860     assert(X86::VR128XRegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
4861     // If stack is realigned we can use aligned stores.
4862     if (isStackAligned)
4863       return load ?
4864         (HasVLX ? X86::VMOVAPSZ128rm : HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm):
4865         (HasVLX ? X86::VMOVAPSZ128mr : HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4866     else
4867       return load ?
4868         (HasVLX ? X86::VMOVUPSZ128rm : HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm):
4869         (HasVLX ? X86::VMOVUPSZ128mr : HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4870   }
4871   case 32:
4872     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
4873     // If stack is realigned we can use aligned stores.
4874     if (isStackAligned)
4875       return load ?
4876         (HasVLX ? X86::VMOVAPSZ256rm : X86::VMOVAPSYrm) :
4877         (HasVLX ? X86::VMOVAPSZ256mr : X86::VMOVAPSYmr);
4878     else
4879       return load ?
4880         (HasVLX ? X86::VMOVUPSZ256rm : X86::VMOVUPSYrm) :
4881         (HasVLX ? X86::VMOVUPSZ256mr : X86::VMOVUPSYmr);
4882   case 64:
4883     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4884     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
4885     if (isStackAligned)
4886       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4887     else
4888       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4889   }
4890 }
4891 
4892 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
4893                                          int64_t &Offset,
4894                                          const TargetRegisterInfo *TRI) const {
4895   const MCInstrDesc &Desc = MemOp.getDesc();
4896   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
4897   if (MemRefBegin < 0)
4898     return false;
4899 
4900   MemRefBegin += X86II::getOperandBias(Desc);
4901 
4902   MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
4903   if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4904     return false;
4905 
4906   BaseReg = BaseMO.getReg();
4907   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4908     return false;
4909 
4910   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
4911       X86::NoRegister)
4912     return false;
4913 
4914   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
4915 
4916   // Displacement can be symbolic
4917   if (!DispMO.isImm())
4918     return false;
4919 
4920   Offset = DispMO.getImm();
4921 
4922   return MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4923          X86::NoRegister;
4924 }
4925 
4926 static unsigned getStoreRegOpcode(unsigned SrcReg,
4927                                   const TargetRegisterClass *RC,
4928                                   bool isStackAligned,
4929                                   const X86Subtarget &STI) {
4930   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
4931 }
4932 
4933 
4934 static unsigned getLoadRegOpcode(unsigned DestReg,
4935                                  const TargetRegisterClass *RC,
4936                                  bool isStackAligned,
4937                                  const X86Subtarget &STI) {
4938   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
4939 }
4940 
4941 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4942                                        MachineBasicBlock::iterator MI,
4943                                        unsigned SrcReg, bool isKill, int FrameIdx,
4944                                        const TargetRegisterClass *RC,
4945                                        const TargetRegisterInfo *TRI) const {
4946   const MachineFunction &MF = *MBB.getParent();
4947   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= RC->getSize() &&
4948          "Stack slot too small for store");
4949   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4950   bool isAligned =
4951       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4952       RI.canRealignStack(MF);
4953   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4954   DebugLoc DL = MBB.findDebugLoc(MI);
4955   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
4956     .addReg(SrcReg, getKillRegState(isKill));
4957 }
4958 
4959 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4960                                   bool isKill,
4961                                   SmallVectorImpl<MachineOperand> &Addr,
4962                                   const TargetRegisterClass *RC,
4963                                   MachineInstr::mmo_iterator MMOBegin,
4964                                   MachineInstr::mmo_iterator MMOEnd,
4965                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
4966   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4967   bool isAligned = MMOBegin != MMOEnd &&
4968                    (*MMOBegin)->getAlignment() >= Alignment;
4969   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4970   DebugLoc DL;
4971   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
4972   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4973     MIB.addOperand(Addr[i]);
4974   MIB.addReg(SrcReg, getKillRegState(isKill));
4975   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4976   NewMIs.push_back(MIB);
4977 }
4978 
4979 
4980 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4981                                         MachineBasicBlock::iterator MI,
4982                                         unsigned DestReg, int FrameIdx,
4983                                         const TargetRegisterClass *RC,
4984                                         const TargetRegisterInfo *TRI) const {
4985   const MachineFunction &MF = *MBB.getParent();
4986   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4987   bool isAligned =
4988       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4989       RI.canRealignStack(MF);
4990   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4991   DebugLoc DL = MBB.findDebugLoc(MI);
4992   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
4993 }
4994 
4995 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
4996                                  SmallVectorImpl<MachineOperand> &Addr,
4997                                  const TargetRegisterClass *RC,
4998                                  MachineInstr::mmo_iterator MMOBegin,
4999                                  MachineInstr::mmo_iterator MMOEnd,
5000                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
5001   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
5002   bool isAligned = MMOBegin != MMOEnd &&
5003                    (*MMOBegin)->getAlignment() >= Alignment;
5004   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
5005   DebugLoc DL;
5006   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
5007   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
5008     MIB.addOperand(Addr[i]);
5009   (*MIB).setMemRefs(MMOBegin, MMOEnd);
5010   NewMIs.push_back(MIB);
5011 }
5012 
5013 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
5014                                   unsigned &SrcReg2, int &CmpMask,
5015                                   int &CmpValue) const {
5016   switch (MI.getOpcode()) {
5017   default: break;
5018   case X86::CMP64ri32:
5019   case X86::CMP64ri8:
5020   case X86::CMP32ri:
5021   case X86::CMP32ri8:
5022   case X86::CMP16ri:
5023   case X86::CMP16ri8:
5024   case X86::CMP8ri:
5025     SrcReg = MI.getOperand(0).getReg();
5026     SrcReg2 = 0;
5027     CmpMask = ~0;
5028     CmpValue = MI.getOperand(1).getImm();
5029     return true;
5030   // A SUB can be used to perform comparison.
5031   case X86::SUB64rm:
5032   case X86::SUB32rm:
5033   case X86::SUB16rm:
5034   case X86::SUB8rm:
5035     SrcReg = MI.getOperand(1).getReg();
5036     SrcReg2 = 0;
5037     CmpMask = ~0;
5038     CmpValue = 0;
5039     return true;
5040   case X86::SUB64rr:
5041   case X86::SUB32rr:
5042   case X86::SUB16rr:
5043   case X86::SUB8rr:
5044     SrcReg = MI.getOperand(1).getReg();
5045     SrcReg2 = MI.getOperand(2).getReg();
5046     CmpMask = ~0;
5047     CmpValue = 0;
5048     return true;
5049   case X86::SUB64ri32:
5050   case X86::SUB64ri8:
5051   case X86::SUB32ri:
5052   case X86::SUB32ri8:
5053   case X86::SUB16ri:
5054   case X86::SUB16ri8:
5055   case X86::SUB8ri:
5056     SrcReg = MI.getOperand(1).getReg();
5057     SrcReg2 = 0;
5058     CmpMask = ~0;
5059     CmpValue = MI.getOperand(2).getImm();
5060     return true;
5061   case X86::CMP64rr:
5062   case X86::CMP32rr:
5063   case X86::CMP16rr:
5064   case X86::CMP8rr:
5065     SrcReg = MI.getOperand(0).getReg();
5066     SrcReg2 = MI.getOperand(1).getReg();
5067     CmpMask = ~0;
5068     CmpValue = 0;
5069     return true;
5070   case X86::TEST8rr:
5071   case X86::TEST16rr:
5072   case X86::TEST32rr:
5073   case X86::TEST64rr:
5074     SrcReg = MI.getOperand(0).getReg();
5075     if (MI.getOperand(1).getReg() != SrcReg)
5076       return false;
5077     // Compare against zero.
5078     SrcReg2 = 0;
5079     CmpMask = ~0;
5080     CmpValue = 0;
5081     return true;
5082   }
5083   return false;
5084 }
5085 
5086 /// Check whether the first instruction, whose only
5087 /// purpose is to update flags, can be made redundant.
5088 /// CMPrr can be made redundant by SUBrr if the operands are the same.
5089 /// This function can be extended later on.
5090 /// SrcReg, SrcRegs: register operands for FlagI.
5091 /// ImmValue: immediate for FlagI if it takes an immediate.
5092 inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
5093                                         unsigned SrcReg2, int ImmValue,
5094                                         MachineInstr &OI) {
5095   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
5096        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
5097        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
5098        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
5099       ((OI.getOperand(1).getReg() == SrcReg &&
5100         OI.getOperand(2).getReg() == SrcReg2) ||
5101        (OI.getOperand(1).getReg() == SrcReg2 &&
5102         OI.getOperand(2).getReg() == SrcReg)))
5103     return true;
5104 
5105   if (((FlagI.getOpcode() == X86::CMP64ri32 &&
5106         OI.getOpcode() == X86::SUB64ri32) ||
5107        (FlagI.getOpcode() == X86::CMP64ri8 &&
5108         OI.getOpcode() == X86::SUB64ri8) ||
5109        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
5110        (FlagI.getOpcode() == X86::CMP32ri8 &&
5111         OI.getOpcode() == X86::SUB32ri8) ||
5112        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
5113        (FlagI.getOpcode() == X86::CMP16ri8 &&
5114         OI.getOpcode() == X86::SUB16ri8) ||
5115        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
5116       OI.getOperand(1).getReg() == SrcReg &&
5117       OI.getOperand(2).getImm() == ImmValue)
5118     return true;
5119   return false;
5120 }
5121 
5122 /// Check whether the definition can be converted
5123 /// to remove a comparison against zero.
5124 inline static bool isDefConvertible(MachineInstr &MI) {
5125   switch (MI.getOpcode()) {
5126   default: return false;
5127 
5128   // The shift instructions only modify ZF if their shift count is non-zero.
5129   // N.B.: The processor truncates the shift count depending on the encoding.
5130   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
5131   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
5132      return getTruncatedShiftCount(MI, 2) != 0;
5133 
5134   // Some left shift instructions can be turned into LEA instructions but only
5135   // if their flags aren't used. Avoid transforming such instructions.
5136   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
5137     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
5138     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
5139     return ShAmt != 0;
5140   }
5141 
5142   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
5143   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
5144      return getTruncatedShiftCount(MI, 3) != 0;
5145 
5146   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
5147   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
5148   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
5149   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
5150   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
5151   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
5152   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
5153   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
5154   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
5155   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
5156   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
5157   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
5158   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
5159   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
5160   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
5161   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
5162   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
5163   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
5164   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
5165   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
5166   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
5167   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
5168   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
5169   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
5170   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
5171   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
5172   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
5173   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
5174   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
5175   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
5176   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
5177   case X86::ADC32ri:   case X86::ADC32ri8:
5178   case X86::ADC32rr:   case X86::ADC64ri32:
5179   case X86::ADC64ri8:  case X86::ADC64rr:
5180   case X86::SBB32ri:   case X86::SBB32ri8:
5181   case X86::SBB32rr:   case X86::SBB64ri32:
5182   case X86::SBB64ri8:  case X86::SBB64rr:
5183   case X86::ANDN32rr:  case X86::ANDN32rm:
5184   case X86::ANDN64rr:  case X86::ANDN64rm:
5185   case X86::BEXTR32rr: case X86::BEXTR64rr:
5186   case X86::BEXTR32rm: case X86::BEXTR64rm:
5187   case X86::BLSI32rr:  case X86::BLSI32rm:
5188   case X86::BLSI64rr:  case X86::BLSI64rm:
5189   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
5190   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
5191   case X86::BLSR32rr:  case X86::BLSR32rm:
5192   case X86::BLSR64rr:  case X86::BLSR64rm:
5193   case X86::BZHI32rr:  case X86::BZHI32rm:
5194   case X86::BZHI64rr:  case X86::BZHI64rm:
5195   case X86::LZCNT16rr: case X86::LZCNT16rm:
5196   case X86::LZCNT32rr: case X86::LZCNT32rm:
5197   case X86::LZCNT64rr: case X86::LZCNT64rm:
5198   case X86::POPCNT16rr:case X86::POPCNT16rm:
5199   case X86::POPCNT32rr:case X86::POPCNT32rm:
5200   case X86::POPCNT64rr:case X86::POPCNT64rm:
5201   case X86::TZCNT16rr: case X86::TZCNT16rm:
5202   case X86::TZCNT32rr: case X86::TZCNT32rm:
5203   case X86::TZCNT64rr: case X86::TZCNT64rm:
5204     return true;
5205   }
5206 }
5207 
5208 /// Check whether the use can be converted to remove a comparison against zero.
5209 static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
5210   switch (MI.getOpcode()) {
5211   default: return X86::COND_INVALID;
5212   case X86::LZCNT16rr: case X86::LZCNT16rm:
5213   case X86::LZCNT32rr: case X86::LZCNT32rm:
5214   case X86::LZCNT64rr: case X86::LZCNT64rm:
5215     return X86::COND_B;
5216   case X86::POPCNT16rr:case X86::POPCNT16rm:
5217   case X86::POPCNT32rr:case X86::POPCNT32rm:
5218   case X86::POPCNT64rr:case X86::POPCNT64rm:
5219     return X86::COND_E;
5220   case X86::TZCNT16rr: case X86::TZCNT16rm:
5221   case X86::TZCNT32rr: case X86::TZCNT32rm:
5222   case X86::TZCNT64rr: case X86::TZCNT64rm:
5223     return X86::COND_B;
5224   }
5225 }
5226 
5227 /// Check if there exists an earlier instruction that
5228 /// operates on the same source operands and sets flags in the same way as
5229 /// Compare; remove Compare if possible.
5230 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
5231                                         unsigned SrcReg2, int CmpMask,
5232                                         int CmpValue,
5233                                         const MachineRegisterInfo *MRI) const {
5234   // Check whether we can replace SUB with CMP.
5235   unsigned NewOpcode = 0;
5236   switch (CmpInstr.getOpcode()) {
5237   default: break;
5238   case X86::SUB64ri32:
5239   case X86::SUB64ri8:
5240   case X86::SUB32ri:
5241   case X86::SUB32ri8:
5242   case X86::SUB16ri:
5243   case X86::SUB16ri8:
5244   case X86::SUB8ri:
5245   case X86::SUB64rm:
5246   case X86::SUB32rm:
5247   case X86::SUB16rm:
5248   case X86::SUB8rm:
5249   case X86::SUB64rr:
5250   case X86::SUB32rr:
5251   case X86::SUB16rr:
5252   case X86::SUB8rr: {
5253     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
5254       return false;
5255     // There is no use of the destination register, we can replace SUB with CMP.
5256     switch (CmpInstr.getOpcode()) {
5257     default: llvm_unreachable("Unreachable!");
5258     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
5259     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
5260     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
5261     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
5262     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
5263     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
5264     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
5265     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
5266     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5267     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
5268     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
5269     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
5270     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
5271     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
5272     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
5273     }
5274     CmpInstr.setDesc(get(NewOpcode));
5275     CmpInstr.RemoveOperand(0);
5276     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5277     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5278         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5279       return false;
5280   }
5281   }
5282 
5283   // Get the unique definition of SrcReg.
5284   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5285   if (!MI) return false;
5286 
5287   // CmpInstr is the first instruction of the BB.
5288   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5289 
5290   // If we are comparing against zero, check whether we can use MI to update
5291   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5292   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
5293   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
5294     return false;
5295 
5296   // If we have a use of the source register between the def and our compare
5297   // instruction we can eliminate the compare iff the use sets EFLAGS in the
5298   // right way.
5299   bool ShouldUpdateCC = false;
5300   X86::CondCode NewCC = X86::COND_INVALID;
5301   if (IsCmpZero && !isDefConvertible(*MI)) {
5302     // Scan forward from the use until we hit the use we're looking for or the
5303     // compare instruction.
5304     for (MachineBasicBlock::iterator J = MI;; ++J) {
5305       // Do we have a convertible instruction?
5306       NewCC = isUseDefConvertible(*J);
5307       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5308           J->getOperand(1).getReg() == SrcReg) {
5309         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5310         ShouldUpdateCC = true; // Update CC later on.
5311         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5312         // with the new def.
5313         Def = J;
5314         MI = &*Def;
5315         break;
5316       }
5317 
5318       if (J == I)
5319         return false;
5320     }
5321   }
5322 
5323   // We are searching for an earlier instruction that can make CmpInstr
5324   // redundant and that instruction will be saved in Sub.
5325   MachineInstr *Sub = nullptr;
5326   const TargetRegisterInfo *TRI = &getRegisterInfo();
5327 
5328   // We iterate backward, starting from the instruction before CmpInstr and
5329   // stop when reaching the definition of a source register or done with the BB.
5330   // RI points to the instruction before CmpInstr.
5331   // If the definition is in this basic block, RE points to the definition;
5332   // otherwise, RE is the rend of the basic block.
5333   MachineBasicBlock::reverse_iterator
5334       RI = MachineBasicBlock::reverse_iterator(I),
5335       RE = CmpInstr.getParent() == MI->getParent()
5336                ? MachineBasicBlock::reverse_iterator(++Def) /* points to MI */
5337                : CmpInstr.getParent()->rend();
5338   MachineInstr *Movr0Inst = nullptr;
5339   for (; RI != RE; ++RI) {
5340     MachineInstr &Instr = *RI;
5341     // Check whether CmpInstr can be made redundant by the current instruction.
5342     if (!IsCmpZero &&
5343         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
5344       Sub = &Instr;
5345       break;
5346     }
5347 
5348     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
5349         Instr.readsRegister(X86::EFLAGS, TRI)) {
5350       // This instruction modifies or uses EFLAGS.
5351 
5352       // MOV32r0 etc. are implemented with xor which clobbers condition code.
5353       // They are safe to move up, if the definition to EFLAGS is dead and
5354       // earlier instructions do not read or write EFLAGS.
5355       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
5356           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
5357         Movr0Inst = &Instr;
5358         continue;
5359       }
5360 
5361       // We can't remove CmpInstr.
5362       return false;
5363     }
5364   }
5365 
5366   // Return false if no candidates exist.
5367   if (!IsCmpZero && !Sub)
5368     return false;
5369 
5370   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5371                     Sub->getOperand(2).getReg() == SrcReg);
5372 
5373   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
5374   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5375   // If we are done with the basic block, we need to check whether EFLAGS is
5376   // live-out.
5377   bool IsSafe = false;
5378   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
5379   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
5380   for (++I; I != E; ++I) {
5381     const MachineInstr &Instr = *I;
5382     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5383     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5384     // We should check the usage if this instruction uses and updates EFLAGS.
5385     if (!UseEFLAGS && ModifyEFLAGS) {
5386       // It is safe to remove CmpInstr if EFLAGS is updated again.
5387       IsSafe = true;
5388       break;
5389     }
5390     if (!UseEFLAGS && !ModifyEFLAGS)
5391       continue;
5392 
5393     // EFLAGS is used by this instruction.
5394     X86::CondCode OldCC = X86::COND_INVALID;
5395     bool OpcIsSET = false;
5396     if (IsCmpZero || IsSwapped) {
5397       // We decode the condition code from opcode.
5398       if (Instr.isBranch())
5399         OldCC = getCondFromBranchOpc(Instr.getOpcode());
5400       else {
5401         OldCC = getCondFromSETOpc(Instr.getOpcode());
5402         if (OldCC != X86::COND_INVALID)
5403           OpcIsSET = true;
5404         else
5405           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
5406       }
5407       if (OldCC == X86::COND_INVALID) return false;
5408     }
5409     if (IsCmpZero) {
5410       switch (OldCC) {
5411       default: break;
5412       case X86::COND_A: case X86::COND_AE:
5413       case X86::COND_B: case X86::COND_BE:
5414       case X86::COND_G: case X86::COND_GE:
5415       case X86::COND_L: case X86::COND_LE:
5416       case X86::COND_O: case X86::COND_NO:
5417         // CF and OF are used, we can't perform this optimization.
5418         return false;
5419       }
5420 
5421       // If we're updating the condition code check if we have to reverse the
5422       // condition.
5423       if (ShouldUpdateCC)
5424         switch (OldCC) {
5425         default:
5426           return false;
5427         case X86::COND_E:
5428           break;
5429         case X86::COND_NE:
5430           NewCC = GetOppositeBranchCondition(NewCC);
5431           break;
5432         }
5433     } else if (IsSwapped) {
5434       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5435       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5436       // We swap the condition code and synthesize the new opcode.
5437       NewCC = getSwappedCondition(OldCC);
5438       if (NewCC == X86::COND_INVALID) return false;
5439     }
5440 
5441     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
5442       // Synthesize the new opcode.
5443       bool HasMemoryOperand = Instr.hasOneMemOperand();
5444       unsigned NewOpc;
5445       if (Instr.isBranch())
5446         NewOpc = GetCondBranchFromCond(NewCC);
5447       else if(OpcIsSET)
5448         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5449       else {
5450         unsigned DstReg = Instr.getOperand(0).getReg();
5451         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5452                                  HasMemoryOperand);
5453       }
5454 
5455       // Push the MachineInstr to OpsToUpdate.
5456       // If it is safe to remove CmpInstr, the condition code of these
5457       // instructions will be modified.
5458       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5459     }
5460     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5461       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
5462       IsSafe = true;
5463       break;
5464     }
5465   }
5466 
5467   // If EFLAGS is not killed nor re-defined, we should check whether it is
5468   // live-out. If it is live-out, do not optimize.
5469   if ((IsCmpZero || IsSwapped) && !IsSafe) {
5470     MachineBasicBlock *MBB = CmpInstr.getParent();
5471     for (MachineBasicBlock *Successor : MBB->successors())
5472       if (Successor->isLiveIn(X86::EFLAGS))
5473         return false;
5474   }
5475 
5476   // The instruction to be updated is either Sub or MI.
5477   Sub = IsCmpZero ? MI : Sub;
5478   // Move Movr0Inst to the appropriate place before Sub.
5479   if (Movr0Inst) {
5480     // Look backwards until we find a def that doesn't use the current EFLAGS.
5481     Def = Sub;
5482     MachineBasicBlock::reverse_iterator
5483       InsertI = MachineBasicBlock::reverse_iterator(++Def),
5484                 InsertE = Sub->getParent()->rend();
5485     for (; InsertI != InsertE; ++InsertI) {
5486       MachineInstr *Instr = &*InsertI;
5487       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5488           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5489         Sub->getParent()->remove(Movr0Inst);
5490         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5491                                    Movr0Inst);
5492         break;
5493       }
5494     }
5495     if (InsertI == InsertE)
5496       return false;
5497   }
5498 
5499   // Make sure Sub instruction defines EFLAGS and mark the def live.
5500   unsigned i = 0, e = Sub->getNumOperands();
5501   for (; i != e; ++i) {
5502     MachineOperand &MO = Sub->getOperand(i);
5503     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5504       MO.setIsDead(false);
5505       break;
5506     }
5507   }
5508   assert(i != e && "Unable to locate a def EFLAGS operand");
5509 
5510   CmpInstr.eraseFromParent();
5511 
5512   // Modify the condition code of instructions in OpsToUpdate.
5513   for (auto &Op : OpsToUpdate)
5514     Op.first->setDesc(get(Op.second));
5515   return true;
5516 }
5517 
5518 /// Try to remove the load by folding it to a register
5519 /// operand at the use. We fold the load instructions if load defines a virtual
5520 /// register, the virtual register is used once in the same BB, and the
5521 /// instructions in-between do not load or store, and have no side effects.
5522 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
5523                                               const MachineRegisterInfo *MRI,
5524                                               unsigned &FoldAsLoadDefReg,
5525                                               MachineInstr *&DefMI) const {
5526   if (FoldAsLoadDefReg == 0)
5527     return nullptr;
5528   // To be conservative, if there exists another load, clear the load candidate.
5529   if (MI.mayLoad()) {
5530     FoldAsLoadDefReg = 0;
5531     return nullptr;
5532   }
5533 
5534   // Check whether we can move DefMI here.
5535   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5536   assert(DefMI);
5537   bool SawStore = false;
5538   if (!DefMI->isSafeToMove(nullptr, SawStore))
5539     return nullptr;
5540 
5541   // Collect information about virtual register operands of MI.
5542   unsigned SrcOperandId = 0;
5543   bool FoundSrcOperand = false;
5544   for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
5545     MachineOperand &MO = MI.getOperand(i);
5546     if (!MO.isReg())
5547       continue;
5548     unsigned Reg = MO.getReg();
5549     if (Reg != FoldAsLoadDefReg)
5550       continue;
5551     // Do not fold if we have a subreg use or a def or multiple uses.
5552     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
5553       return nullptr;
5554 
5555     SrcOperandId = i;
5556     FoundSrcOperand = true;
5557   }
5558   if (!FoundSrcOperand)
5559     return nullptr;
5560 
5561   // Check whether we can fold the def into SrcOperandId.
5562   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, *DefMI)) {
5563     FoldAsLoadDefReg = 0;
5564     return FoldMI;
5565   }
5566 
5567   return nullptr;
5568 }
5569 
5570 /// Expand a single-def pseudo instruction to a two-addr
5571 /// instruction with two undef reads of the register being defined.
5572 /// This is used for mapping:
5573 ///   %xmm4 = V_SET0
5574 /// to:
5575 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5576 ///
5577 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5578                              const MCInstrDesc &Desc) {
5579   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5580   unsigned Reg = MIB->getOperand(0).getReg();
5581   MIB->setDesc(Desc);
5582 
5583   // MachineInstr::addOperand() will insert explicit operands before any
5584   // implicit operands.
5585   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5586   // But we don't trust that.
5587   assert(MIB->getOperand(1).getReg() == Reg &&
5588          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
5589   return true;
5590 }
5591 
5592 /// Expand a single-def pseudo instruction to a two-addr
5593 /// instruction with two %k0 reads.
5594 /// This is used for mapping:
5595 ///   %k4 = K_SET1
5596 /// to:
5597 ///   %k4 = KXNORrr %k0, %k0
5598 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5599                             const MCInstrDesc &Desc, unsigned Reg) {
5600   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5601   MIB->setDesc(Desc);
5602   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5603   return true;
5604 }
5605 
5606 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5607                           bool MinusOne) {
5608   MachineBasicBlock &MBB = *MIB->getParent();
5609   DebugLoc DL = MIB->getDebugLoc();
5610   unsigned Reg = MIB->getOperand(0).getReg();
5611 
5612   // Insert the XOR.
5613   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5614       .addReg(Reg, RegState::Undef)
5615       .addReg(Reg, RegState::Undef);
5616 
5617   // Turn the pseudo into an INC or DEC.
5618   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5619   MIB.addReg(Reg);
5620 
5621   return true;
5622 }
5623 
5624 bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5625   MachineBasicBlock &MBB = *MIB->getParent();
5626   DebugLoc DL = MIB->getDebugLoc();
5627   int64_t Imm = MIB->getOperand(1).getImm();
5628   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5629   MachineBasicBlock::iterator I = MIB.getInstr();
5630 
5631   int StackAdjustment;
5632 
5633   if (Subtarget.is64Bit()) {
5634     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5635            MIB->getOpcode() == X86::MOV32ImmSExti8);
5636 
5637     // Can't use push/pop lowering if the function might write to the red zone.
5638     X86MachineFunctionInfo *X86FI =
5639         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5640     if (X86FI->getUsesRedZone()) {
5641       MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5642                                                                : X86::MOV64ri));
5643       return true;
5644     }
5645 
5646     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5647     // widen the register if necessary.
5648     StackAdjustment = 8;
5649     BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5650     MIB->setDesc(get(X86::POP64r));
5651     MIB->getOperand(0)
5652         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5653   } else {
5654     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5655     StackAdjustment = 4;
5656     BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5657     MIB->setDesc(get(X86::POP32r));
5658   }
5659 
5660   // Build CFI if necessary.
5661   MachineFunction &MF = *MBB.getParent();
5662   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5663   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5664   bool NeedsDwarfCFI =
5665       !IsWin64Prologue &&
5666       (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5667   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5668   if (EmitCFI) {
5669     TFL->BuildCFI(MBB, I, DL,
5670         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5671     TFL->BuildCFI(MBB, std::next(I), DL,
5672         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5673   }
5674 
5675   return true;
5676 }
5677 
5678 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5679 // code sequence is needed for other targets.
5680 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5681                                  const TargetInstrInfo &TII) {
5682   MachineBasicBlock &MBB = *MIB->getParent();
5683   DebugLoc DL = MIB->getDebugLoc();
5684   unsigned Reg = MIB->getOperand(0).getReg();
5685   const GlobalValue *GV =
5686       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
5687   auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
5688   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
5689       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
5690   MachineBasicBlock::iterator I = MIB.getInstr();
5691 
5692   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5693       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5694       .addMemOperand(MMO);
5695   MIB->setDebugLoc(DL);
5696   MIB->setDesc(TII.get(X86::MOV64rm));
5697   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5698 }
5699 
5700 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
5701   bool HasAVX = Subtarget.hasAVX();
5702   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
5703   switch (MI.getOpcode()) {
5704   case X86::MOV32r0:
5705     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
5706   case X86::MOV32r1:
5707     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5708   case X86::MOV32r_1:
5709     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
5710   case X86::MOV32ImmSExti8:
5711   case X86::MOV64ImmSExti8:
5712     return ExpandMOVImmSExti8(MIB);
5713   case X86::SETB_C8r:
5714     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
5715   case X86::SETB_C16r:
5716     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
5717   case X86::SETB_C32r:
5718     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
5719   case X86::SETB_C64r:
5720     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
5721   case X86::V_SET0:
5722   case X86::FsFLD0SS:
5723   case X86::FsFLD0SD:
5724     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
5725   case X86::AVX_SET0:
5726     assert(HasAVX && "AVX not supported");
5727     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
5728   case X86::AVX512_128_SET0:
5729     return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
5730   case X86::AVX512_256_SET0:
5731     return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
5732   case X86::AVX512_512_SET0:
5733     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
5734   case X86::V_SETALLONES:
5735     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
5736   case X86::AVX2_SETALLONES:
5737     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
5738   case X86::AVX512_512_SETALLONES: {
5739     unsigned Reg = MIB->getOperand(0).getReg();
5740     MIB->setDesc(get(X86::VPTERNLOGDZrri));
5741     // VPTERNLOGD needs 3 register inputs and an immediate.
5742     // 0xff will return 1s for any input.
5743     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
5744        .addReg(Reg, RegState::Undef).addImm(0xff);
5745     return true;
5746   }
5747   case X86::TEST8ri_NOREX:
5748     MI.setDesc(get(X86::TEST8ri));
5749     return true;
5750   case X86::MOV32ri64:
5751     MI.setDesc(get(X86::MOV32ri));
5752     return true;
5753 
5754   // KNL does not recognize dependency-breaking idioms for mask registers,
5755   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5756   // Using %k0 as the undef input register is a performance heuristic based
5757   // on the assumption that %k0 is used less frequently than the other mask
5758   // registers, since it is not usable as a write mask.
5759   // FIXME: A more advanced approach would be to choose the best input mask
5760   // register based on context.
5761   case X86::KSET0B:
5762   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5763   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5764   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
5765   case X86::KSET1B:
5766   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5767   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5768   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
5769   case TargetOpcode::LOAD_STACK_GUARD:
5770     expandLoadStackGuard(MIB, *this);
5771     return true;
5772   }
5773   return false;
5774 }
5775 
5776 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5777                         int PtrOffset = 0) {
5778   unsigned NumAddrOps = MOs.size();
5779 
5780   if (NumAddrOps < 4) {
5781     // FrameIndex only - add an immediate offset (whether its zero or not).
5782     for (unsigned i = 0; i != NumAddrOps; ++i)
5783       MIB.addOperand(MOs[i]);
5784     addOffset(MIB, PtrOffset);
5785   } else {
5786     // General Memory Addressing - we need to add any offset to an existing
5787     // offset.
5788     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5789     for (unsigned i = 0; i != NumAddrOps; ++i) {
5790       const MachineOperand &MO = MOs[i];
5791       if (i == 3 && PtrOffset != 0) {
5792         MIB.addDisp(MO, PtrOffset);
5793       } else {
5794         MIB.addOperand(MO);
5795       }
5796     }
5797   }
5798 }
5799 
5800 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5801                                      ArrayRef<MachineOperand> MOs,
5802                                      MachineBasicBlock::iterator InsertPt,
5803                                      MachineInstr &MI,
5804                                      const TargetInstrInfo &TII) {
5805   // Create the base instruction with the memory operand as the first part.
5806   // Omit the implicit operands, something BuildMI can't do.
5807   MachineInstr *NewMI =
5808       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5809   MachineInstrBuilder MIB(MF, NewMI);
5810   addOperands(MIB, MOs);
5811 
5812   // Loop over the rest of the ri operands, converting them over.
5813   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5814   for (unsigned i = 0; i != NumOps; ++i) {
5815     MachineOperand &MO = MI.getOperand(i + 2);
5816     MIB.addOperand(MO);
5817   }
5818   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5819     MachineOperand &MO = MI.getOperand(i);
5820     MIB.addOperand(MO);
5821   }
5822 
5823   MachineBasicBlock *MBB = InsertPt->getParent();
5824   MBB->insert(InsertPt, NewMI);
5825 
5826   return MIB;
5827 }
5828 
5829 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5830                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5831                               MachineBasicBlock::iterator InsertPt,
5832                               MachineInstr &MI, const TargetInstrInfo &TII,
5833                               int PtrOffset = 0) {
5834   // Omit the implicit operands, something BuildMI can't do.
5835   MachineInstr *NewMI =
5836       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5837   MachineInstrBuilder MIB(MF, NewMI);
5838 
5839   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5840     MachineOperand &MO = MI.getOperand(i);
5841     if (i == OpNo) {
5842       assert(MO.isReg() && "Expected to fold into reg operand!");
5843       addOperands(MIB, MOs, PtrOffset);
5844     } else {
5845       MIB.addOperand(MO);
5846     }
5847   }
5848 
5849   MachineBasicBlock *MBB = InsertPt->getParent();
5850   MBB->insert(InsertPt, NewMI);
5851 
5852   return MIB;
5853 }
5854 
5855 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5856                                 ArrayRef<MachineOperand> MOs,
5857                                 MachineBasicBlock::iterator InsertPt,
5858                                 MachineInstr &MI) {
5859   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5860                                     MI.getDebugLoc(), TII.get(Opcode));
5861   addOperands(MIB, MOs);
5862   return MIB.addImm(0);
5863 }
5864 
5865 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5866     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5867     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5868     unsigned Size, unsigned Align) const {
5869   switch (MI.getOpcode()) {
5870   case X86::INSERTPSrr:
5871   case X86::VINSERTPSrr:
5872   case X86::VINSERTPSZrr:
5873     // Attempt to convert the load of inserted vector into a fold load
5874     // of a single float.
5875     if (OpNum == 2) {
5876       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5877       unsigned ZMask = Imm & 15;
5878       unsigned DstIdx = (Imm >> 4) & 3;
5879       unsigned SrcIdx = (Imm >> 6) & 3;
5880 
5881       unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
5882       if (Size <= RCSize && 4 <= Align) {
5883         int PtrOffset = SrcIdx * 4;
5884         unsigned NewImm = (DstIdx << 4) | ZMask;
5885         unsigned NewOpCode =
5886             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5887             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
5888                                                     X86::INSERTPSrm;
5889         MachineInstr *NewMI =
5890             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5891         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5892         return NewMI;
5893       }
5894     }
5895     break;
5896   case X86::MOVHLPSrr:
5897   case X86::VMOVHLPSrr:
5898   case X86::VMOVHLPSZrr:
5899     // Move the upper 64-bits of the second operand to the lower 64-bits.
5900     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5901     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5902     if (OpNum == 2) {
5903       unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
5904       if (Size <= RCSize && 8 <= Align) {
5905         unsigned NewOpCode =
5906             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5907             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
5908                                                    X86::MOVLPSrm;
5909         MachineInstr *NewMI =
5910             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5911         return NewMI;
5912       }
5913     }
5914     break;
5915   };
5916 
5917   return nullptr;
5918 }
5919 
5920 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5921     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5922     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5923     unsigned Size, unsigned Align, bool AllowCommute) const {
5924   const DenseMap<unsigned,
5925                  std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
5926   bool isCallRegIndirect = Subtarget.callRegIndirect();
5927   bool isTwoAddrFold = false;
5928 
5929   // For CPUs that favor the register form of a call or push,
5930   // do not fold loads into calls or pushes, unless optimizing for size
5931   // aggressively.
5932   if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
5933       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5934        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5935        MI.getOpcode() == X86::PUSH64r))
5936     return nullptr;
5937 
5938   unsigned NumOps = MI.getDesc().getNumOperands();
5939   bool isTwoAddr =
5940       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5941 
5942   // FIXME: AsmPrinter doesn't know how to handle
5943   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5944   if (MI.getOpcode() == X86::ADD32ri &&
5945       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5946     return nullptr;
5947 
5948   MachineInstr *NewMI = nullptr;
5949 
5950   // Attempt to fold any custom cases we have.
5951   if (MachineInstr *CustomMI =
5952           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
5953     return CustomMI;
5954 
5955   // Folding a memory location into the two-address part of a two-address
5956   // instruction is different than folding it other places.  It requires
5957   // replacing the *two* registers with the memory location.
5958   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5959       MI.getOperand(1).isReg() &&
5960       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5961     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5962     isTwoAddrFold = true;
5963   } else if (OpNum == 0) {
5964     if (MI.getOpcode() == X86::MOV32r0) {
5965       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5966       if (NewMI)
5967         return NewMI;
5968     }
5969 
5970     OpcodeTablePtr = &RegOp2MemOpTable0;
5971   } else if (OpNum == 1) {
5972     OpcodeTablePtr = &RegOp2MemOpTable1;
5973   } else if (OpNum == 2) {
5974     OpcodeTablePtr = &RegOp2MemOpTable2;
5975   } else if (OpNum == 3) {
5976     OpcodeTablePtr = &RegOp2MemOpTable3;
5977   } else if (OpNum == 4) {
5978     OpcodeTablePtr = &RegOp2MemOpTable4;
5979   }
5980 
5981   // If table selected...
5982   if (OpcodeTablePtr) {
5983     // Find the Opcode to fuse
5984     auto I = OpcodeTablePtr->find(MI.getOpcode());
5985     if (I != OpcodeTablePtr->end()) {
5986       unsigned Opcode = I->second.first;
5987       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
5988       if (Align < MinAlign)
5989         return nullptr;
5990       bool NarrowToMOV32rm = false;
5991       if (Size) {
5992         unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
5993         if (Size < RCSize) {
5994           // Check if it's safe to fold the load. If the size of the object is
5995           // narrower than the load width, then it's not.
5996           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5997             return nullptr;
5998           // If this is a 64-bit load, but the spill slot is 32, then we can do
5999           // a 32-bit load which is implicitly zero-extended. This likely is
6000           // due to live interval analysis remat'ing a load from stack slot.
6001           if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
6002             return nullptr;
6003           Opcode = X86::MOV32rm;
6004           NarrowToMOV32rm = true;
6005         }
6006       }
6007 
6008       if (isTwoAddrFold)
6009         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
6010       else
6011         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
6012 
6013       if (NarrowToMOV32rm) {
6014         // If this is the special case where we use a MOV32rm to load a 32-bit
6015         // value and zero-extend the top bits. Change the destination register
6016         // to a 32-bit one.
6017         unsigned DstReg = NewMI->getOperand(0).getReg();
6018         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
6019           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
6020         else
6021           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
6022       }
6023       return NewMI;
6024     }
6025   }
6026 
6027   // If the instruction and target operand are commutable, commute the
6028   // instruction and try again.
6029   if (AllowCommute) {
6030     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
6031     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
6032       bool HasDef = MI.getDesc().getNumDefs();
6033       unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
6034       unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
6035       unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
6036       bool Tied1 =
6037           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
6038       bool Tied2 =
6039           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
6040 
6041       // If either of the commutable operands are tied to the destination
6042       // then we can not commute + fold.
6043       if ((HasDef && Reg0 == Reg1 && Tied1) ||
6044           (HasDef && Reg0 == Reg2 && Tied2))
6045         return nullptr;
6046 
6047       MachineInstr *CommutedMI =
6048           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
6049       if (!CommutedMI) {
6050         // Unable to commute.
6051         return nullptr;
6052       }
6053       if (CommutedMI != &MI) {
6054         // New instruction. We can't fold from this.
6055         CommutedMI->eraseFromParent();
6056         return nullptr;
6057       }
6058 
6059       // Attempt to fold with the commuted version of the instruction.
6060       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
6061                                     Size, Align, /*AllowCommute=*/false);
6062       if (NewMI)
6063         return NewMI;
6064 
6065       // Folding failed again - undo the commute before returning.
6066       MachineInstr *UncommutedMI =
6067           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
6068       if (!UncommutedMI) {
6069         // Unable to commute.
6070         return nullptr;
6071       }
6072       if (UncommutedMI != &MI) {
6073         // New instruction. It doesn't need to be kept.
6074         UncommutedMI->eraseFromParent();
6075         return nullptr;
6076       }
6077 
6078       // Return here to prevent duplicate fuse failure report.
6079       return nullptr;
6080     }
6081   }
6082 
6083   // No fusion
6084   if (PrintFailedFusing && !MI.isCopy())
6085     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
6086   return nullptr;
6087 }
6088 
6089 /// Return true for all instructions that only update
6090 /// the first 32 or 64-bits of the destination register and leave the rest
6091 /// unmodified. This can be used to avoid folding loads if the instructions
6092 /// only update part of the destination register, and the non-updated part is
6093 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
6094 /// instructions breaks the partial register dependency and it can improve
6095 /// performance. e.g.:
6096 ///
6097 ///   movss (%rdi), %xmm0
6098 ///   cvtss2sd %xmm0, %xmm0
6099 ///
6100 /// Instead of
6101 ///   cvtss2sd (%rdi), %xmm0
6102 ///
6103 /// FIXME: This should be turned into a TSFlags.
6104 ///
6105 static bool hasPartialRegUpdate(unsigned Opcode) {
6106   switch (Opcode) {
6107   case X86::CVTSI2SSrr:
6108   case X86::CVTSI2SSrm:
6109   case X86::CVTSI2SS64rr:
6110   case X86::CVTSI2SS64rm:
6111   case X86::CVTSI2SDrr:
6112   case X86::CVTSI2SDrm:
6113   case X86::CVTSI2SD64rr:
6114   case X86::CVTSI2SD64rm:
6115   case X86::CVTSD2SSrr:
6116   case X86::CVTSD2SSrm:
6117   case X86::Int_CVTSD2SSrr:
6118   case X86::Int_CVTSD2SSrm:
6119   case X86::CVTSS2SDrr:
6120   case X86::CVTSS2SDrm:
6121   case X86::Int_CVTSS2SDrr:
6122   case X86::Int_CVTSS2SDrm:
6123   case X86::MOVHPDrm:
6124   case X86::MOVHPSrm:
6125   case X86::MOVLPDrm:
6126   case X86::MOVLPSrm:
6127   case X86::RCPSSr:
6128   case X86::RCPSSm:
6129   case X86::RCPSSr_Int:
6130   case X86::RCPSSm_Int:
6131   case X86::ROUNDSDr:
6132   case X86::ROUNDSDm:
6133   case X86::ROUNDSDr_Int:
6134   case X86::ROUNDSDm_Int:
6135   case X86::ROUNDSSr:
6136   case X86::ROUNDSSm:
6137   case X86::ROUNDSSr_Int:
6138   case X86::ROUNDSSm_Int:
6139   case X86::RSQRTSSr:
6140   case X86::RSQRTSSm:
6141   case X86::RSQRTSSr_Int:
6142   case X86::RSQRTSSm_Int:
6143   case X86::SQRTSSr:
6144   case X86::SQRTSSm:
6145   case X86::SQRTSSr_Int:
6146   case X86::SQRTSSm_Int:
6147   case X86::SQRTSDr:
6148   case X86::SQRTSDm:
6149   case X86::SQRTSDr_Int:
6150   case X86::SQRTSDm_Int:
6151     return true;
6152   }
6153 
6154   return false;
6155 }
6156 
6157 /// Inform the ExeDepsFix pass how many idle
6158 /// instructions we would like before a partial register update.
6159 unsigned X86InstrInfo::getPartialRegUpdateClearance(
6160     const MachineInstr &MI, unsigned OpNum,
6161     const TargetRegisterInfo *TRI) const {
6162   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
6163     return 0;
6164 
6165   // If MI is marked as reading Reg, the partial register update is wanted.
6166   const MachineOperand &MO = MI.getOperand(0);
6167   unsigned Reg = MO.getReg();
6168   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6169     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
6170       return 0;
6171   } else {
6172     if (MI.readsRegister(Reg, TRI))
6173       return 0;
6174   }
6175 
6176   // If any instructions in the clearance range are reading Reg, insert a
6177   // dependency breaking instruction, which is inexpensive and is likely to
6178   // be hidden in other instruction's cycles.
6179   return PartialRegUpdateClearance;
6180 }
6181 
6182 // Return true for any instruction the copies the high bits of the first source
6183 // operand into the unused high bits of the destination operand.
6184 static bool hasUndefRegUpdate(unsigned Opcode) {
6185   switch (Opcode) {
6186   case X86::VCVTSI2SSrr:
6187   case X86::VCVTSI2SSrm:
6188   case X86::Int_VCVTSI2SSrr:
6189   case X86::Int_VCVTSI2SSrm:
6190   case X86::VCVTSI2SS64rr:
6191   case X86::VCVTSI2SS64rm:
6192   case X86::Int_VCVTSI2SS64rr:
6193   case X86::Int_VCVTSI2SS64rm:
6194   case X86::VCVTSI2SDrr:
6195   case X86::VCVTSI2SDrm:
6196   case X86::Int_VCVTSI2SDrr:
6197   case X86::Int_VCVTSI2SDrm:
6198   case X86::VCVTSI2SD64rr:
6199   case X86::VCVTSI2SD64rm:
6200   case X86::Int_VCVTSI2SD64rr:
6201   case X86::Int_VCVTSI2SD64rm:
6202   case X86::VCVTSD2SSrr:
6203   case X86::VCVTSD2SSrm:
6204   case X86::Int_VCVTSD2SSrr:
6205   case X86::Int_VCVTSD2SSrm:
6206   case X86::VCVTSS2SDrr:
6207   case X86::VCVTSS2SDrm:
6208   case X86::Int_VCVTSS2SDrr:
6209   case X86::Int_VCVTSS2SDrm:
6210   case X86::VRCPSSr:
6211   case X86::VRCPSSr_Int:
6212   case X86::VRCPSSm:
6213   case X86::VRCPSSm_Int:
6214   case X86::VROUNDSDr:
6215   case X86::VROUNDSDm:
6216   case X86::VROUNDSDr_Int:
6217   case X86::VROUNDSDm_Int:
6218   case X86::VROUNDSSr:
6219   case X86::VROUNDSSm:
6220   case X86::VROUNDSSr_Int:
6221   case X86::VROUNDSSm_Int:
6222   case X86::VRSQRTSSr:
6223   case X86::VRSQRTSSr_Int:
6224   case X86::VRSQRTSSm:
6225   case X86::VRSQRTSSm_Int:
6226   case X86::VSQRTSSr:
6227   case X86::VSQRTSSr_Int:
6228   case X86::VSQRTSSm:
6229   case X86::VSQRTSSm_Int:
6230   case X86::VSQRTSDr:
6231   case X86::VSQRTSDr_Int:
6232   case X86::VSQRTSDm:
6233   case X86::VSQRTSDm_Int:
6234   // AVX-512
6235   case X86::VCVTSI2SSZrr:
6236   case X86::VCVTSI2SSZrm:
6237   case X86::Int_VCVTSI2SSZrr:
6238   case X86::Int_VCVTSI2SSZrm:
6239   case X86::VCVTSI2SSZrr_Int:
6240   case X86::VCVTSI2SSZrm_Int:
6241   case X86::VCVTSI642SSZrr:
6242   case X86::VCVTSI642SSZrm:
6243   case X86::Int_VCVTSI2SS64Zrr:
6244   case X86::Int_VCVTSI2SS64Zrm:
6245   case X86::VCVTSI642SSZrr_Int:
6246   case X86::VCVTSI642SSZrm_Int:
6247   case X86::VCVTSI2SDZrr:
6248   case X86::VCVTSI2SDZrm:
6249   case X86::Int_VCVTSI2SDZrr:
6250   case X86::Int_VCVTSI2SDZrm:
6251   case X86::VCVTSI2SDZrr_Int:
6252   case X86::VCVTSI2SDZrm_Int:
6253   case X86::VCVTSI642SDZrr:
6254   case X86::VCVTSI642SDZrm:
6255   case X86::Int_VCVTSI2SD64Zrr:
6256   case X86::Int_VCVTSI2SD64Zrm:
6257   case X86::VCVTSI642SDZrr_Int:
6258   case X86::VCVTSI642SDZrm_Int:
6259   case X86::VCVTSD2SSZrr:
6260   case X86::VCVTSD2SSZrm:
6261   case X86::VCVTSS2SDZrr:
6262   case X86::VCVTSS2SDZrm:
6263   case X86::VRNDSCALESDr:
6264   case X86::VRNDSCALESDm:
6265   case X86::VRNDSCALESSr:
6266   case X86::VRNDSCALESSm:
6267   case X86::VRCP14SSrr:
6268   case X86::VRCP14SSrm:
6269   case X86::VRSQRT14SSrr:
6270   case X86::VRSQRT14SSrm:
6271   case X86::VSQRTSSZr:
6272   case X86::VSQRTSSZr_Int:
6273   case X86::VSQRTSSZm:
6274   case X86::VSQRTSSZm_Int:
6275   case X86::VSQRTSDZr:
6276   case X86::VSQRTSDZr_Int:
6277   case X86::VSQRTSDZm:
6278   case X86::VSQRTSDZm_Int:
6279     return true;
6280   }
6281 
6282   return false;
6283 }
6284 
6285 /// Inform the ExeDepsFix pass how many idle instructions we would like before
6286 /// certain undef register reads.
6287 ///
6288 /// This catches the VCVTSI2SD family of instructions:
6289 ///
6290 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6291 ///
6292 /// We should to be careful *not* to catch VXOR idioms which are presumably
6293 /// handled specially in the pipeline:
6294 ///
6295 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6296 ///
6297 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6298 /// high bits that are passed-through are not live.
6299 unsigned
6300 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
6301                                    const TargetRegisterInfo *TRI) const {
6302   if (!hasUndefRegUpdate(MI.getOpcode()))
6303     return 0;
6304 
6305   // Set the OpNum parameter to the first source operand.
6306   OpNum = 1;
6307 
6308   const MachineOperand &MO = MI.getOperand(OpNum);
6309   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
6310     return UndefRegClearance;
6311   }
6312   return 0;
6313 }
6314 
6315 void X86InstrInfo::breakPartialRegDependency(
6316     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
6317   unsigned Reg = MI.getOperand(OpNum).getReg();
6318   // If MI kills this register, the false dependence is already broken.
6319   if (MI.killsRegister(Reg, TRI))
6320     return;
6321 
6322   if (X86::VR128RegClass.contains(Reg)) {
6323     // These instructions are all floating point domain, so xorps is the best
6324     // choice.
6325     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
6326     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
6327         .addReg(Reg, RegState::Undef)
6328         .addReg(Reg, RegState::Undef);
6329     MI.addRegisterKilled(Reg, TRI, true);
6330   } else if (X86::VR256RegClass.contains(Reg)) {
6331     // Use vxorps to clear the full ymm register.
6332     // It wants to read and write the xmm sub-register.
6333     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
6334     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
6335         .addReg(XReg, RegState::Undef)
6336         .addReg(XReg, RegState::Undef)
6337         .addReg(Reg, RegState::ImplicitDefine);
6338     MI.addRegisterKilled(Reg, TRI, true);
6339   }
6340 }
6341 
6342 MachineInstr *
6343 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
6344                                     ArrayRef<unsigned> Ops,
6345                                     MachineBasicBlock::iterator InsertPt,
6346                                     int FrameIndex, LiveIntervals *LIS) const {
6347   // Check switch flag
6348   if (NoFusing)
6349     return nullptr;
6350 
6351   // Unless optimizing for size, don't fold to avoid partial
6352   // register update stalls
6353   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
6354     return nullptr;
6355 
6356   const MachineFrameInfo &MFI = MF.getFrameInfo();
6357   unsigned Size = MFI.getObjectSize(FrameIndex);
6358   unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
6359   // If the function stack isn't realigned we don't want to fold instructions
6360   // that need increased alignment.
6361   if (!RI.needsStackRealignment(MF))
6362     Alignment =
6363         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
6364   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6365     unsigned NewOpc = 0;
6366     unsigned RCSize = 0;
6367     switch (MI.getOpcode()) {
6368     default: return nullptr;
6369     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
6370     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6371     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6372     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
6373     }
6374     // Check if it's safe to fold the load. If the size of the object is
6375     // narrower than the load width, then it's not.
6376     if (Size < RCSize)
6377       return nullptr;
6378     // Change to CMPXXri r, 0 first.
6379     MI.setDesc(get(NewOpc));
6380     MI.getOperand(1).ChangeToImmediate(0);
6381   } else if (Ops.size() != 1)
6382     return nullptr;
6383 
6384   return foldMemoryOperandImpl(MF, MI, Ops[0],
6385                                MachineOperand::CreateFI(FrameIndex), InsertPt,
6386                                Size, Alignment, /*AllowCommute=*/true);
6387 }
6388 
6389 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6390 /// because the latter uses contents that wouldn't be defined in the folded
6391 /// version.  For instance, this transformation isn't legal:
6392 ///   movss (%rdi), %xmm0
6393 ///   addps %xmm0, %xmm0
6394 /// ->
6395 ///   addps (%rdi), %xmm0
6396 ///
6397 /// But this one is:
6398 ///   movss (%rdi), %xmm0
6399 ///   addss %xmm0, %xmm0
6400 /// ->
6401 ///   addss (%rdi), %xmm0
6402 ///
6403 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6404                                              const MachineInstr &UserMI,
6405                                              const MachineFunction &MF) {
6406   unsigned Opc = LoadMI.getOpcode();
6407   unsigned UserOpc = UserMI.getOpcode();
6408   unsigned RegSize =
6409       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6410 
6411   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
6412       RegSize > 4) {
6413     // These instructions only load 32 bits, we can't fold them if the
6414     // destination register is wider than 32 bits (4 bytes), and its user
6415     // instruction isn't scalar (SS).
6416     switch (UserOpc) {
6417     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
6418     case X86::Int_CMPSSrr: case X86::Int_VCMPSSrr: case X86::VCMPSSZrr_Int:
6419     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
6420     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
6421     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
6422     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
6423     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
6424     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
6425     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
6426     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
6427     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
6428     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
6429     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
6430     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
6431     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
6432     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
6433     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
6434     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
6435     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
6436       return false;
6437     default:
6438       return true;
6439     }
6440   }
6441 
6442   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
6443       RegSize > 8) {
6444     // These instructions only load 64 bits, we can't fold them if the
6445     // destination register is wider than 64 bits (8 bytes), and its user
6446     // instruction isn't scalar (SD).
6447     switch (UserOpc) {
6448     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
6449     case X86::Int_CMPSDrr: case X86::Int_VCMPSDrr: case X86::VCMPSDZrr_Int:
6450     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
6451     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
6452     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
6453     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
6454     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
6455     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
6456     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
6457     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
6458     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
6459     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
6460     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
6461     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
6462     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
6463     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
6464     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
6465     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
6466     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
6467       return false;
6468     default:
6469       return true;
6470     }
6471   }
6472 
6473   return false;
6474 }
6475 
6476 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6477     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6478     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
6479     LiveIntervals *LIS) const {
6480   // If loading from a FrameIndex, fold directly from the FrameIndex.
6481   unsigned NumOps = LoadMI.getDesc().getNumOperands();
6482   int FrameIndex;
6483   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6484     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6485       return nullptr;
6486     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
6487   }
6488 
6489   // Check switch flag
6490   if (NoFusing) return nullptr;
6491 
6492   // Avoid partial register update stalls unless optimizing for size.
6493   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
6494     return nullptr;
6495 
6496   // Determine the alignment of the load.
6497   unsigned Alignment = 0;
6498   if (LoadMI.hasOneMemOperand())
6499     Alignment = (*LoadMI.memoperands_begin())->getAlignment();
6500   else
6501     switch (LoadMI.getOpcode()) {
6502     case X86::AVX512_512_SET0:
6503     case X86::AVX512_512_SETALLONES:
6504       Alignment = 64;
6505       break;
6506     case X86::AVX2_SETALLONES:
6507     case X86::AVX_SET0:
6508     case X86::AVX512_256_SET0:
6509       Alignment = 32;
6510       break;
6511     case X86::V_SET0:
6512     case X86::V_SETALLONES:
6513     case X86::AVX512_128_SET0:
6514       Alignment = 16;
6515       break;
6516     case X86::FsFLD0SD:
6517       Alignment = 8;
6518       break;
6519     case X86::FsFLD0SS:
6520       Alignment = 4;
6521       break;
6522     default:
6523       return nullptr;
6524     }
6525   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6526     unsigned NewOpc = 0;
6527     switch (MI.getOpcode()) {
6528     default: return nullptr;
6529     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6530     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6531     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6532     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6533     }
6534     // Change to CMPXXri r, 0 first.
6535     MI.setDesc(get(NewOpc));
6536     MI.getOperand(1).ChangeToImmediate(0);
6537   } else if (Ops.size() != 1)
6538     return nullptr;
6539 
6540   // Make sure the subregisters match.
6541   // Otherwise we risk changing the size of the load.
6542   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6543     return nullptr;
6544 
6545   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6546   switch (LoadMI.getOpcode()) {
6547   case X86::V_SET0:
6548   case X86::V_SETALLONES:
6549   case X86::AVX2_SETALLONES:
6550   case X86::AVX_SET0:
6551   case X86::AVX512_128_SET0:
6552   case X86::AVX512_256_SET0:
6553   case X86::AVX512_512_SET0:
6554   case X86::AVX512_512_SETALLONES:
6555   case X86::FsFLD0SD:
6556   case X86::FsFLD0SS: {
6557     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6558     // Create a constant-pool entry and operands to load from it.
6559 
6560     // Medium and large mode can't fold loads this way.
6561     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6562         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6563       return nullptr;
6564 
6565     // x86-32 PIC requires a PIC base register for constant pools.
6566     unsigned PICBase = 0;
6567     if (MF.getTarget().isPositionIndependent()) {
6568       if (Subtarget.is64Bit())
6569         PICBase = X86::RIP;
6570       else
6571         // FIXME: PICBase = getGlobalBaseReg(&MF);
6572         // This doesn't work for several reasons.
6573         // 1. GlobalBaseReg may have been spilled.
6574         // 2. It may not be live at MI.
6575         return nullptr;
6576     }
6577 
6578     // Create a constant-pool entry.
6579     MachineConstantPool &MCP = *MF.getConstantPool();
6580     Type *Ty;
6581     unsigned Opc = LoadMI.getOpcode();
6582     if (Opc == X86::FsFLD0SS)
6583       Ty = Type::getFloatTy(MF.getFunction()->getContext());
6584     else if (Opc == X86::FsFLD0SD)
6585       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
6586     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
6587       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
6588     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6589              Opc == X86::AVX512_256_SET0)
6590       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
6591     else
6592       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
6593 
6594     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6595                       Opc == X86::AVX512_512_SETALLONES);
6596     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6597                                     Constant::getNullValue(Ty);
6598     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6599 
6600     // Create operands to load from the constant pool entry.
6601     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6602     MOs.push_back(MachineOperand::CreateImm(1));
6603     MOs.push_back(MachineOperand::CreateReg(0, false));
6604     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6605     MOs.push_back(MachineOperand::CreateReg(0, false));
6606     break;
6607   }
6608   default: {
6609     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6610       return nullptr;
6611 
6612     // Folding a normal load. Just copy the load's address operands.
6613     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6614                LoadMI.operands_begin() + NumOps);
6615     break;
6616   }
6617   }
6618   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6619                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6620 }
6621 
6622 bool X86InstrInfo::unfoldMemoryOperand(
6623     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6624     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6625   auto I = MemOp2RegOpTable.find(MI.getOpcode());
6626   if (I == MemOp2RegOpTable.end())
6627     return false;
6628   unsigned Opc = I->second.first;
6629   unsigned Index = I->second.second & TB_INDEX_MASK;
6630   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6631   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6632   if (UnfoldLoad && !FoldedLoad)
6633     return false;
6634   UnfoldLoad &= FoldedLoad;
6635   if (UnfoldStore && !FoldedStore)
6636     return false;
6637   UnfoldStore &= FoldedStore;
6638 
6639   const MCInstrDesc &MCID = get(Opc);
6640   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6641   // TODO: Check if 32-byte or greater accesses are slow too?
6642   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
6643       Subtarget.isUnalignedMem16Slow())
6644     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6645     // conservatively assume the address is unaligned. That's bad for
6646     // performance.
6647     return false;
6648   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6649   SmallVector<MachineOperand,2> BeforeOps;
6650   SmallVector<MachineOperand,2> AfterOps;
6651   SmallVector<MachineOperand,4> ImpOps;
6652   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6653     MachineOperand &Op = MI.getOperand(i);
6654     if (i >= Index && i < Index + X86::AddrNumOperands)
6655       AddrOps.push_back(Op);
6656     else if (Op.isReg() && Op.isImplicit())
6657       ImpOps.push_back(Op);
6658     else if (i < Index)
6659       BeforeOps.push_back(Op);
6660     else if (i > Index)
6661       AfterOps.push_back(Op);
6662   }
6663 
6664   // Emit the load instruction.
6665   if (UnfoldLoad) {
6666     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6667         MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
6668     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
6669     if (UnfoldStore) {
6670       // Address operands cannot be marked isKill.
6671       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6672         MachineOperand &MO = NewMIs[0]->getOperand(i);
6673         if (MO.isReg())
6674           MO.setIsKill(false);
6675       }
6676     }
6677   }
6678 
6679   // Emit the data processing instruction.
6680   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
6681   MachineInstrBuilder MIB(MF, DataMI);
6682 
6683   if (FoldedStore)
6684     MIB.addReg(Reg, RegState::Define);
6685   for (MachineOperand &BeforeOp : BeforeOps)
6686     MIB.addOperand(BeforeOp);
6687   if (FoldedLoad)
6688     MIB.addReg(Reg);
6689   for (MachineOperand &AfterOp : AfterOps)
6690     MIB.addOperand(AfterOp);
6691   for (MachineOperand &ImpOp : ImpOps) {
6692     MIB.addReg(ImpOp.getReg(),
6693                getDefRegState(ImpOp.isDef()) |
6694                RegState::Implicit |
6695                getKillRegState(ImpOp.isKill()) |
6696                getDeadRegState(ImpOp.isDead()) |
6697                getUndefRegState(ImpOp.isUndef()));
6698   }
6699   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6700   switch (DataMI->getOpcode()) {
6701   default: break;
6702   case X86::CMP64ri32:
6703   case X86::CMP64ri8:
6704   case X86::CMP32ri:
6705   case X86::CMP32ri8:
6706   case X86::CMP16ri:
6707   case X86::CMP16ri8:
6708   case X86::CMP8ri: {
6709     MachineOperand &MO0 = DataMI->getOperand(0);
6710     MachineOperand &MO1 = DataMI->getOperand(1);
6711     if (MO1.getImm() == 0) {
6712       unsigned NewOpc;
6713       switch (DataMI->getOpcode()) {
6714       default: llvm_unreachable("Unreachable!");
6715       case X86::CMP64ri8:
6716       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6717       case X86::CMP32ri8:
6718       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6719       case X86::CMP16ri8:
6720       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6721       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6722       }
6723       DataMI->setDesc(get(NewOpc));
6724       MO1.ChangeToRegister(MO0.getReg(), false);
6725     }
6726   }
6727   }
6728   NewMIs.push_back(DataMI);
6729 
6730   // Emit the store instruction.
6731   if (UnfoldStore) {
6732     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6733     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6734         MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
6735     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
6736   }
6737 
6738   return true;
6739 }
6740 
6741 bool
6742 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6743                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6744   if (!N->isMachineOpcode())
6745     return false;
6746 
6747   auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
6748   if (I == MemOp2RegOpTable.end())
6749     return false;
6750   unsigned Opc = I->second.first;
6751   unsigned Index = I->second.second & TB_INDEX_MASK;
6752   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6753   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6754   const MCInstrDesc &MCID = get(Opc);
6755   MachineFunction &MF = DAG.getMachineFunction();
6756   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6757   unsigned NumDefs = MCID.NumDefs;
6758   std::vector<SDValue> AddrOps;
6759   std::vector<SDValue> BeforeOps;
6760   std::vector<SDValue> AfterOps;
6761   SDLoc dl(N);
6762   unsigned NumOps = N->getNumOperands();
6763   for (unsigned i = 0; i != NumOps-1; ++i) {
6764     SDValue Op = N->getOperand(i);
6765     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6766       AddrOps.push_back(Op);
6767     else if (i < Index-NumDefs)
6768       BeforeOps.push_back(Op);
6769     else if (i > Index-NumDefs)
6770       AfterOps.push_back(Op);
6771   }
6772   SDValue Chain = N->getOperand(NumOps-1);
6773   AddrOps.push_back(Chain);
6774 
6775   // Emit the load instruction.
6776   SDNode *Load = nullptr;
6777   if (FoldedLoad) {
6778     EVT VT = *RC->vt_begin();
6779     std::pair<MachineInstr::mmo_iterator,
6780               MachineInstr::mmo_iterator> MMOs =
6781       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6782                             cast<MachineSDNode>(N)->memoperands_end());
6783     if (!(*MMOs.first) &&
6784         RC == &X86::VR128RegClass &&
6785         Subtarget.isUnalignedMem16Slow())
6786       // Do not introduce a slow unaligned load.
6787       return false;
6788     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6789     // memory access is slow above.
6790     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6791     bool isAligned = (*MMOs.first) &&
6792                      (*MMOs.first)->getAlignment() >= Alignment;
6793     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
6794                               VT, MVT::Other, AddrOps);
6795     NewNodes.push_back(Load);
6796 
6797     // Preserve memory reference information.
6798     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
6799   }
6800 
6801   // Emit the data processing instruction.
6802   std::vector<EVT> VTs;
6803   const TargetRegisterClass *DstRC = nullptr;
6804   if (MCID.getNumDefs() > 0) {
6805     DstRC = getRegClass(MCID, 0, &RI, MF);
6806     VTs.push_back(*DstRC->vt_begin());
6807   }
6808   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6809     EVT VT = N->getValueType(i);
6810     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6811       VTs.push_back(VT);
6812   }
6813   if (Load)
6814     BeforeOps.push_back(SDValue(Load, 0));
6815   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
6816   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6817   NewNodes.push_back(NewNode);
6818 
6819   // Emit the store instruction.
6820   if (FoldedStore) {
6821     AddrOps.pop_back();
6822     AddrOps.push_back(SDValue(NewNode, 0));
6823     AddrOps.push_back(Chain);
6824     std::pair<MachineInstr::mmo_iterator,
6825               MachineInstr::mmo_iterator> MMOs =
6826       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6827                              cast<MachineSDNode>(N)->memoperands_end());
6828     if (!(*MMOs.first) &&
6829         RC == &X86::VR128RegClass &&
6830         Subtarget.isUnalignedMem16Slow())
6831       // Do not introduce a slow unaligned store.
6832       return false;
6833     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6834     // memory access is slow above.
6835     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6836     bool isAligned = (*MMOs.first) &&
6837                      (*MMOs.first)->getAlignment() >= Alignment;
6838     SDNode *Store =
6839         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6840                            dl, MVT::Other, AddrOps);
6841     NewNodes.push_back(Store);
6842 
6843     // Preserve memory reference information.
6844     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
6845   }
6846 
6847   return true;
6848 }
6849 
6850 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6851                                       bool UnfoldLoad, bool UnfoldStore,
6852                                       unsigned *LoadRegIndex) const {
6853   auto I = MemOp2RegOpTable.find(Opc);
6854   if (I == MemOp2RegOpTable.end())
6855     return 0;
6856   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6857   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6858   if (UnfoldLoad && !FoldedLoad)
6859     return 0;
6860   if (UnfoldStore && !FoldedStore)
6861     return 0;
6862   if (LoadRegIndex)
6863     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
6864   return I->second.first;
6865 }
6866 
6867 bool
6868 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6869                                      int64_t &Offset1, int64_t &Offset2) const {
6870   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6871     return false;
6872   unsigned Opc1 = Load1->getMachineOpcode();
6873   unsigned Opc2 = Load2->getMachineOpcode();
6874   switch (Opc1) {
6875   default: return false;
6876   case X86::MOV8rm:
6877   case X86::MOV16rm:
6878   case X86::MOV32rm:
6879   case X86::MOV64rm:
6880   case X86::LD_Fp32m:
6881   case X86::LD_Fp64m:
6882   case X86::LD_Fp80m:
6883   case X86::MOVSSrm:
6884   case X86::MOVSDrm:
6885   case X86::MMX_MOVD64rm:
6886   case X86::MMX_MOVQ64rm:
6887   case X86::MOVAPSrm:
6888   case X86::MOVUPSrm:
6889   case X86::MOVAPDrm:
6890   case X86::MOVUPDrm:
6891   case X86::MOVDQArm:
6892   case X86::MOVDQUrm:
6893   // AVX load instructions
6894   case X86::VMOVSSrm:
6895   case X86::VMOVSDrm:
6896   case X86::VMOVAPSrm:
6897   case X86::VMOVUPSrm:
6898   case X86::VMOVAPDrm:
6899   case X86::VMOVUPDrm:
6900   case X86::VMOVDQArm:
6901   case X86::VMOVDQUrm:
6902   case X86::VMOVAPSYrm:
6903   case X86::VMOVUPSYrm:
6904   case X86::VMOVAPDYrm:
6905   case X86::VMOVUPDYrm:
6906   case X86::VMOVDQAYrm:
6907   case X86::VMOVDQUYrm:
6908   // AVX512 load instructions
6909   case X86::VMOVSSZrm:
6910   case X86::VMOVSDZrm:
6911   case X86::VMOVAPSZ128rm:
6912   case X86::VMOVUPSZ128rm:
6913   case X86::VMOVAPDZ128rm:
6914   case X86::VMOVUPDZ128rm:
6915   case X86::VMOVDQU8Z128rm:
6916   case X86::VMOVDQU16Z128rm:
6917   case X86::VMOVDQA32Z128rm:
6918   case X86::VMOVDQU32Z128rm:
6919   case X86::VMOVDQA64Z128rm:
6920   case X86::VMOVDQU64Z128rm:
6921   case X86::VMOVAPSZ256rm:
6922   case X86::VMOVUPSZ256rm:
6923   case X86::VMOVAPDZ256rm:
6924   case X86::VMOVUPDZ256rm:
6925   case X86::VMOVDQU8Z256rm:
6926   case X86::VMOVDQU16Z256rm:
6927   case X86::VMOVDQA32Z256rm:
6928   case X86::VMOVDQU32Z256rm:
6929   case X86::VMOVDQA64Z256rm:
6930   case X86::VMOVDQU64Z256rm:
6931   case X86::VMOVAPSZrm:
6932   case X86::VMOVUPSZrm:
6933   case X86::VMOVAPDZrm:
6934   case X86::VMOVUPDZrm:
6935   case X86::VMOVDQU8Zrm:
6936   case X86::VMOVDQU16Zrm:
6937   case X86::VMOVDQA32Zrm:
6938   case X86::VMOVDQU32Zrm:
6939   case X86::VMOVDQA64Zrm:
6940   case X86::VMOVDQU64Zrm:
6941   case X86::KMOVBkm:
6942   case X86::KMOVWkm:
6943   case X86::KMOVDkm:
6944   case X86::KMOVQkm:
6945     break;
6946   }
6947   switch (Opc2) {
6948   default: return false;
6949   case X86::MOV8rm:
6950   case X86::MOV16rm:
6951   case X86::MOV32rm:
6952   case X86::MOV64rm:
6953   case X86::LD_Fp32m:
6954   case X86::LD_Fp64m:
6955   case X86::LD_Fp80m:
6956   case X86::MOVSSrm:
6957   case X86::MOVSDrm:
6958   case X86::MMX_MOVD64rm:
6959   case X86::MMX_MOVQ64rm:
6960   case X86::MOVAPSrm:
6961   case X86::MOVUPSrm:
6962   case X86::MOVAPDrm:
6963   case X86::MOVUPDrm:
6964   case X86::MOVDQArm:
6965   case X86::MOVDQUrm:
6966   // AVX load instructions
6967   case X86::VMOVSSrm:
6968   case X86::VMOVSDrm:
6969   case X86::VMOVAPSrm:
6970   case X86::VMOVUPSrm:
6971   case X86::VMOVAPDrm:
6972   case X86::VMOVUPDrm:
6973   case X86::VMOVDQArm:
6974   case X86::VMOVDQUrm:
6975   case X86::VMOVAPSYrm:
6976   case X86::VMOVUPSYrm:
6977   case X86::VMOVAPDYrm:
6978   case X86::VMOVUPDYrm:
6979   case X86::VMOVDQAYrm:
6980   case X86::VMOVDQUYrm:
6981   // AVX512 load instructions
6982   case X86::VMOVSSZrm:
6983   case X86::VMOVSDZrm:
6984   case X86::VMOVAPSZ128rm:
6985   case X86::VMOVUPSZ128rm:
6986   case X86::VMOVAPDZ128rm:
6987   case X86::VMOVUPDZ128rm:
6988   case X86::VMOVDQU8Z128rm:
6989   case X86::VMOVDQU16Z128rm:
6990   case X86::VMOVDQA32Z128rm:
6991   case X86::VMOVDQU32Z128rm:
6992   case X86::VMOVDQA64Z128rm:
6993   case X86::VMOVDQU64Z128rm:
6994   case X86::VMOVAPSZ256rm:
6995   case X86::VMOVUPSZ256rm:
6996   case X86::VMOVAPDZ256rm:
6997   case X86::VMOVUPDZ256rm:
6998   case X86::VMOVDQU8Z256rm:
6999   case X86::VMOVDQU16Z256rm:
7000   case X86::VMOVDQA32Z256rm:
7001   case X86::VMOVDQU32Z256rm:
7002   case X86::VMOVDQA64Z256rm:
7003   case X86::VMOVDQU64Z256rm:
7004   case X86::VMOVAPSZrm:
7005   case X86::VMOVUPSZrm:
7006   case X86::VMOVAPDZrm:
7007   case X86::VMOVUPDZrm:
7008   case X86::VMOVDQU8Zrm:
7009   case X86::VMOVDQU16Zrm:
7010   case X86::VMOVDQA32Zrm:
7011   case X86::VMOVDQU32Zrm:
7012   case X86::VMOVDQA64Zrm:
7013   case X86::VMOVDQU64Zrm:
7014   case X86::KMOVBkm:
7015   case X86::KMOVWkm:
7016   case X86::KMOVDkm:
7017   case X86::KMOVQkm:
7018     break;
7019   }
7020 
7021   // Check if chain operands and base addresses match.
7022   if (Load1->getOperand(0) != Load2->getOperand(0) ||
7023       Load1->getOperand(5) != Load2->getOperand(5))
7024     return false;
7025   // Segment operands should match as well.
7026   if (Load1->getOperand(4) != Load2->getOperand(4))
7027     return false;
7028   // Scale should be 1, Index should be Reg0.
7029   if (Load1->getOperand(1) == Load2->getOperand(1) &&
7030       Load1->getOperand(2) == Load2->getOperand(2)) {
7031     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
7032       return false;
7033 
7034     // Now let's examine the displacements.
7035     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
7036         isa<ConstantSDNode>(Load2->getOperand(3))) {
7037       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
7038       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
7039       return true;
7040     }
7041   }
7042   return false;
7043 }
7044 
7045 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
7046                                            int64_t Offset1, int64_t Offset2,
7047                                            unsigned NumLoads) const {
7048   assert(Offset2 > Offset1);
7049   if ((Offset2 - Offset1) / 8 > 64)
7050     return false;
7051 
7052   unsigned Opc1 = Load1->getMachineOpcode();
7053   unsigned Opc2 = Load2->getMachineOpcode();
7054   if (Opc1 != Opc2)
7055     return false;  // FIXME: overly conservative?
7056 
7057   switch (Opc1) {
7058   default: break;
7059   case X86::LD_Fp32m:
7060   case X86::LD_Fp64m:
7061   case X86::LD_Fp80m:
7062   case X86::MMX_MOVD64rm:
7063   case X86::MMX_MOVQ64rm:
7064     return false;
7065   }
7066 
7067   EVT VT = Load1->getValueType(0);
7068   switch (VT.getSimpleVT().SimpleTy) {
7069   default:
7070     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
7071     // have 16 of them to play with.
7072     if (Subtarget.is64Bit()) {
7073       if (NumLoads >= 3)
7074         return false;
7075     } else if (NumLoads) {
7076       return false;
7077     }
7078     break;
7079   case MVT::i8:
7080   case MVT::i16:
7081   case MVT::i32:
7082   case MVT::i64:
7083   case MVT::f32:
7084   case MVT::f64:
7085     if (NumLoads)
7086       return false;
7087     break;
7088   }
7089 
7090   return true;
7091 }
7092 
7093 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr &First,
7094                                           MachineInstr &Second) const {
7095   // Check if this processor supports macro-fusion. Since this is a minor
7096   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
7097   // proxy for SandyBridge+.
7098   if (!Subtarget.hasAVX())
7099     return false;
7100 
7101   enum {
7102     FuseTest,
7103     FuseCmp,
7104     FuseInc
7105   } FuseKind;
7106 
7107   switch (Second.getOpcode()) {
7108   default:
7109     return false;
7110   case X86::JE_1:
7111   case X86::JNE_1:
7112   case X86::JL_1:
7113   case X86::JLE_1:
7114   case X86::JG_1:
7115   case X86::JGE_1:
7116     FuseKind = FuseInc;
7117     break;
7118   case X86::JB_1:
7119   case X86::JBE_1:
7120   case X86::JA_1:
7121   case X86::JAE_1:
7122     FuseKind = FuseCmp;
7123     break;
7124   case X86::JS_1:
7125   case X86::JNS_1:
7126   case X86::JP_1:
7127   case X86::JNP_1:
7128   case X86::JO_1:
7129   case X86::JNO_1:
7130     FuseKind = FuseTest;
7131     break;
7132   }
7133   switch (First.getOpcode()) {
7134   default:
7135     return false;
7136   case X86::TEST8rr:
7137   case X86::TEST16rr:
7138   case X86::TEST32rr:
7139   case X86::TEST64rr:
7140   case X86::TEST8ri:
7141   case X86::TEST16ri:
7142   case X86::TEST32ri:
7143   case X86::TEST32i32:
7144   case X86::TEST64i32:
7145   case X86::TEST64ri32:
7146   case X86::TEST8rm:
7147   case X86::TEST16rm:
7148   case X86::TEST32rm:
7149   case X86::TEST64rm:
7150   case X86::TEST8ri_NOREX:
7151   case X86::AND16i16:
7152   case X86::AND16ri:
7153   case X86::AND16ri8:
7154   case X86::AND16rm:
7155   case X86::AND16rr:
7156   case X86::AND32i32:
7157   case X86::AND32ri:
7158   case X86::AND32ri8:
7159   case X86::AND32rm:
7160   case X86::AND32rr:
7161   case X86::AND64i32:
7162   case X86::AND64ri32:
7163   case X86::AND64ri8:
7164   case X86::AND64rm:
7165   case X86::AND64rr:
7166   case X86::AND8i8:
7167   case X86::AND8ri:
7168   case X86::AND8rm:
7169   case X86::AND8rr:
7170     return true;
7171   case X86::CMP16i16:
7172   case X86::CMP16ri:
7173   case X86::CMP16ri8:
7174   case X86::CMP16rm:
7175   case X86::CMP16rr:
7176   case X86::CMP32i32:
7177   case X86::CMP32ri:
7178   case X86::CMP32ri8:
7179   case X86::CMP32rm:
7180   case X86::CMP32rr:
7181   case X86::CMP64i32:
7182   case X86::CMP64ri32:
7183   case X86::CMP64ri8:
7184   case X86::CMP64rm:
7185   case X86::CMP64rr:
7186   case X86::CMP8i8:
7187   case X86::CMP8ri:
7188   case X86::CMP8rm:
7189   case X86::CMP8rr:
7190   case X86::ADD16i16:
7191   case X86::ADD16ri:
7192   case X86::ADD16ri8:
7193   case X86::ADD16ri8_DB:
7194   case X86::ADD16ri_DB:
7195   case X86::ADD16rm:
7196   case X86::ADD16rr:
7197   case X86::ADD16rr_DB:
7198   case X86::ADD32i32:
7199   case X86::ADD32ri:
7200   case X86::ADD32ri8:
7201   case X86::ADD32ri8_DB:
7202   case X86::ADD32ri_DB:
7203   case X86::ADD32rm:
7204   case X86::ADD32rr:
7205   case X86::ADD32rr_DB:
7206   case X86::ADD64i32:
7207   case X86::ADD64ri32:
7208   case X86::ADD64ri32_DB:
7209   case X86::ADD64ri8:
7210   case X86::ADD64ri8_DB:
7211   case X86::ADD64rm:
7212   case X86::ADD64rr:
7213   case X86::ADD64rr_DB:
7214   case X86::ADD8i8:
7215   case X86::ADD8mi:
7216   case X86::ADD8mr:
7217   case X86::ADD8ri:
7218   case X86::ADD8rm:
7219   case X86::ADD8rr:
7220   case X86::SUB16i16:
7221   case X86::SUB16ri:
7222   case X86::SUB16ri8:
7223   case X86::SUB16rm:
7224   case X86::SUB16rr:
7225   case X86::SUB32i32:
7226   case X86::SUB32ri:
7227   case X86::SUB32ri8:
7228   case X86::SUB32rm:
7229   case X86::SUB32rr:
7230   case X86::SUB64i32:
7231   case X86::SUB64ri32:
7232   case X86::SUB64ri8:
7233   case X86::SUB64rm:
7234   case X86::SUB64rr:
7235   case X86::SUB8i8:
7236   case X86::SUB8ri:
7237   case X86::SUB8rm:
7238   case X86::SUB8rr:
7239     return FuseKind == FuseCmp || FuseKind == FuseInc;
7240   case X86::INC16r:
7241   case X86::INC32r:
7242   case X86::INC64r:
7243   case X86::INC8r:
7244   case X86::DEC16r:
7245   case X86::DEC32r:
7246   case X86::DEC64r:
7247   case X86::DEC8r:
7248     return FuseKind == FuseInc;
7249   }
7250 }
7251 
7252 bool X86InstrInfo::
7253 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
7254   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
7255   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
7256   Cond[0].setImm(GetOppositeBranchCondition(CC));
7257   return false;
7258 }
7259 
7260 bool X86InstrInfo::
7261 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
7262   // FIXME: Return false for x87 stack register classes for now. We can't
7263   // allow any loads of these registers before FpGet_ST0_80.
7264   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
7265            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
7266 }
7267 
7268 /// Return a virtual register initialized with the
7269 /// the global base register value. Output instructions required to
7270 /// initialize the register in the function entry block, if necessary.
7271 ///
7272 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
7273 ///
7274 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
7275   assert(!Subtarget.is64Bit() &&
7276          "X86-64 PIC uses RIP relative addressing");
7277 
7278   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
7279   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7280   if (GlobalBaseReg != 0)
7281     return GlobalBaseReg;
7282 
7283   // Create the register. The code to initialize it is inserted
7284   // later, by the CGBR pass (below).
7285   MachineRegisterInfo &RegInfo = MF->getRegInfo();
7286   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
7287   X86FI->setGlobalBaseReg(GlobalBaseReg);
7288   return GlobalBaseReg;
7289 }
7290 
7291 // These are the replaceable SSE instructions. Some of these have Int variants
7292 // that we don't include here. We don't want to replace instructions selected
7293 // by intrinsics.
7294 static const uint16_t ReplaceableInstrs[][3] = {
7295   //PackedSingle     PackedDouble    PackedInt
7296   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
7297   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
7298   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
7299   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
7300   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
7301   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr  },
7302   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
7303   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
7304   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
7305   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
7306   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
7307   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
7308   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
7309   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
7310   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
7311   // AVX 128-bit support
7312   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
7313   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
7314   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
7315   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
7316   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
7317   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr  },
7318   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7319   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
7320   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
7321   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
7322   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
7323   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
7324   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
7325   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
7326   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
7327   // AVX 256-bit support
7328   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
7329   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
7330   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
7331   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
7332   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
7333   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
7334   // AVX512 support
7335   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
7336   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7337   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7338   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
7339 };
7340 
7341 static const uint16_t ReplaceableInstrsAVX2[][3] = {
7342   //PackedSingle       PackedDouble       PackedInt
7343   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
7344   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
7345   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
7346   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
7347   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
7348   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
7349   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
7350   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
7351   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7352   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7353   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
7354   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
7355   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
7356   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
7357   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7358   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7359   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7360   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7361   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7362   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
7363 };
7364 
7365 static const uint16_t ReplaceableInstrsAVX512[][4] = {
7366   // Two integer columns for 64-bit and 32-bit elements.
7367   //PackedSingle        PackedDouble        PackedInt             PackedInt
7368   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
7369   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
7370   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
7371   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
7372   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
7373   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
7374   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
7375   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
7376   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
7377   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
7378   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
7379   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
7380   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
7381   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
7382   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
7383 };
7384 
7385 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7386   // Two integer columns for 64-bit and 32-bit elements.
7387   //PackedSingle        PackedDouble        PackedInt           PackedInt
7388   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7389   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7390   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7391   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7392   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7393   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7394   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7395   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7396   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7397   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7398   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7399   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7400   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7401   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7402   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7403   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7404   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
7405   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
7406   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
7407   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
7408   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
7409   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
7410   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
7411   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
7412 };
7413 
7414 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
7415   // Two integer columns for 64-bit and 32-bit elements.
7416   //PackedSingle          PackedDouble
7417   //PackedInt             PackedInt
7418   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
7419     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
7420   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
7421     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
7422   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
7423     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
7424   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
7425     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
7426   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
7427     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
7428   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
7429     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
7430   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
7431     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
7432   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
7433     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
7434   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
7435     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
7436   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
7437     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
7438   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
7439     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
7440   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
7441     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
7442   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
7443     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
7444   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
7445     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
7446   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
7447     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
7448   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
7449     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
7450   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
7451     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
7452   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
7453     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
7454   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
7455     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
7456   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
7457     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
7458   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
7459     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
7460   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
7461     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
7462   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
7463     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
7464   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
7465     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
7466   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
7467     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
7468   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
7469     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
7470   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
7471     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
7472   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
7473     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
7474   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
7475     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
7476   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
7477     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
7478   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
7479     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
7480   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
7481     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
7482   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
7483     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
7484   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
7485     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
7486   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
7487     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
7488   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
7489     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
7490   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
7491     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
7492   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
7493     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
7494   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
7495     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
7496   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
7497     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
7498   { X86::VORPSZrmk,       X86::VORPDZrmk,
7499     X86::VPORQZrmk,       X86::VPORDZrmk       },
7500   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
7501     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
7502   { X86::VORPSZrrk,       X86::VORPDZrrk,
7503     X86::VPORQZrrk,       X86::VPORDZrrk       },
7504   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
7505     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
7506   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
7507     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
7508   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
7509     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
7510   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
7511     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
7512   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
7513     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
7514   // Broadcast loads can be handled the same as masked operations to avoid
7515   // changing element size.
7516   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
7517     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
7518   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
7519     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
7520   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
7521     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
7522   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
7523     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
7524   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
7525     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
7526   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
7527     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
7528   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
7529     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
7530   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
7531     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
7532   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
7533     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
7534   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7535     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7536   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7537     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7538   { X86::VORPSZrmb,       X86::VORPDZrmb,
7539     X86::VPORQZrmb,       X86::VPORDZrmb       },
7540   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
7541     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
7542   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
7543     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
7544   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
7545     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
7546   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
7547     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
7548   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
7549     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
7550   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
7551     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
7552   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
7553     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
7554   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
7555     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
7556   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
7557     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
7558   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
7559     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
7560   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7561     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7562   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7563     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7564   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
7565     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
7566   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
7567     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
7568   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
7569     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
7570   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
7571     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
7572   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
7573     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
7574   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
7575     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
7576   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
7577     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
7578   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
7579     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
7580   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
7581     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
7582   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
7583     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
7584   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
7585     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
7586   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7587     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7588   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7589     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7590   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
7591     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
7592   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
7593     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
7594 };
7595 
7596 // FIXME: Some shuffle and unpack instructions have equivalents in different
7597 // domains, but they require a bit more work than just switching opcodes.
7598 
7599 static const uint16_t *lookup(unsigned opcode, unsigned domain,
7600                               ArrayRef<uint16_t[3]> Table) {
7601   for (const uint16_t (&Row)[3] : Table)
7602     if (Row[domain-1] == opcode)
7603       return Row;
7604   return nullptr;
7605 }
7606 
7607 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
7608                                     ArrayRef<uint16_t[4]> Table) {
7609   // If this is the integer domain make sure to check both integer columns.
7610   for (const uint16_t (&Row)[4] : Table)
7611     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7612       return Row;
7613   return nullptr;
7614 }
7615 
7616 std::pair<uint16_t, uint16_t>
7617 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7618   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7619   unsigned opcode = MI.getOpcode();
7620   uint16_t validDomains = 0;
7621   if (domain) {
7622     if (lookup(MI.getOpcode(), domain, ReplaceableInstrs)) {
7623       validDomains = 0xe;
7624     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
7625       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
7626     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
7627       validDomains = 0xe;
7628     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512DQ)) {
7629       validDomains = Subtarget.hasDQI() ? 0xe : 0x8;
7630     } else if (const uint16_t *table = lookupAVX512(opcode, domain,
7631                                              ReplaceableInstrsAVX512DQMasked)) {
7632       if (domain == 1 || (domain == 3 && table[3] == opcode))
7633         validDomains = Subtarget.hasDQI() ? 0xa : 0x8;
7634       else
7635         validDomains = Subtarget.hasDQI() ? 0xc : 0x8;
7636     }
7637   }
7638   return std::make_pair(domain, validDomains);
7639 }
7640 
7641 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
7642   assert(Domain>0 && Domain<4 && "Invalid execution domain");
7643   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7644   assert(dom && "Not an SSE instruction");
7645   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
7646   if (!table) { // try the other table
7647     assert((Subtarget.hasAVX2() || Domain < 3) &&
7648            "256-bit vector operations only available in AVX2");
7649     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
7650   }
7651   if (!table) { // try the AVX512 table
7652     assert(Subtarget.hasAVX512() && "Requires AVX-512");
7653     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
7654     // Don't change integer Q instructions to D instructions.
7655     if (table && Domain == 3 && table[3] == MI.getOpcode())
7656       Domain = 4;
7657   }
7658   if (!table) { // try the AVX512DQ table
7659     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7660     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
7661     // Don't change integer Q instructions to D instructions and
7662     // use D intructions if we started with a PS instruction.
7663     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7664       Domain = 4;
7665   }
7666   if (!table) { // try the AVX512DQMasked table
7667     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7668     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
7669     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7670       Domain = 4;
7671   }
7672   assert(table && "Cannot change domain");
7673   MI.setDesc(get(table[Domain - 1]));
7674 }
7675 
7676 /// Return the noop instruction to use for a noop.
7677 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7678   NopInst.setOpcode(X86::NOOP);
7679 }
7680 
7681 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
7682 // In particular, getJumpInstrTableEntryBound must always return an upper bound
7683 // on the encoding lengths of the instructions generated by
7684 // getUnconditionalBranch and getTrap.
7685 void X86InstrInfo::getUnconditionalBranch(
7686     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
7687   Branch.setOpcode(X86::JMP_1);
7688   Branch.addOperand(MCOperand::createExpr(BranchTarget));
7689 }
7690 
7691 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
7692 // In particular, getJumpInstrTableEntryBound must always return an upper bound
7693 // on the encoding lengths of the instructions generated by
7694 // getUnconditionalBranch and getTrap.
7695 void X86InstrInfo::getTrap(MCInst &MI) const {
7696   MI.setOpcode(X86::TRAP);
7697 }
7698 
7699 // See getTrap and getUnconditionalBranch for conditions on the value returned
7700 // by this function.
7701 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7702   // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7703   // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7704   return 5;
7705 }
7706 
7707 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7708   switch (opc) {
7709   default: return false;
7710   case X86::DIVPDrm:
7711   case X86::DIVPDrr:
7712   case X86::DIVPSrm:
7713   case X86::DIVPSrr:
7714   case X86::DIVSDrm:
7715   case X86::DIVSDrm_Int:
7716   case X86::DIVSDrr:
7717   case X86::DIVSDrr_Int:
7718   case X86::DIVSSrm:
7719   case X86::DIVSSrm_Int:
7720   case X86::DIVSSrr:
7721   case X86::DIVSSrr_Int:
7722   case X86::SQRTPDm:
7723   case X86::SQRTPDr:
7724   case X86::SQRTPSm:
7725   case X86::SQRTPSr:
7726   case X86::SQRTSDm:
7727   case X86::SQRTSDm_Int:
7728   case X86::SQRTSDr:
7729   case X86::SQRTSDr_Int:
7730   case X86::SQRTSSm:
7731   case X86::SQRTSSm_Int:
7732   case X86::SQRTSSr:
7733   case X86::SQRTSSr_Int:
7734   // AVX instructions with high latency
7735   case X86::VDIVPDrm:
7736   case X86::VDIVPDrr:
7737   case X86::VDIVPDYrm:
7738   case X86::VDIVPDYrr:
7739   case X86::VDIVPSrm:
7740   case X86::VDIVPSrr:
7741   case X86::VDIVPSYrm:
7742   case X86::VDIVPSYrr:
7743   case X86::VDIVSDrm:
7744   case X86::VDIVSDrm_Int:
7745   case X86::VDIVSDrr:
7746   case X86::VDIVSDrr_Int:
7747   case X86::VDIVSSrm:
7748   case X86::VDIVSSrm_Int:
7749   case X86::VDIVSSrr:
7750   case X86::VDIVSSrr_Int:
7751   case X86::VSQRTPDm:
7752   case X86::VSQRTPDr:
7753   case X86::VSQRTPDYm:
7754   case X86::VSQRTPDYr:
7755   case X86::VSQRTPSm:
7756   case X86::VSQRTPSr:
7757   case X86::VSQRTPSYm:
7758   case X86::VSQRTPSYr:
7759   case X86::VSQRTSDm:
7760   case X86::VSQRTSDm_Int:
7761   case X86::VSQRTSDr:
7762   case X86::VSQRTSDr_Int:
7763   case X86::VSQRTSSm:
7764   case X86::VSQRTSSm_Int:
7765   case X86::VSQRTSSr:
7766   case X86::VSQRTSSr_Int:
7767   // AVX512 instructions with high latency
7768   case X86::VDIVPDZ128rm:
7769   case X86::VDIVPDZ128rmb:
7770   case X86::VDIVPDZ128rmbk:
7771   case X86::VDIVPDZ128rmbkz:
7772   case X86::VDIVPDZ128rmk:
7773   case X86::VDIVPDZ128rmkz:
7774   case X86::VDIVPDZ128rr:
7775   case X86::VDIVPDZ128rrk:
7776   case X86::VDIVPDZ128rrkz:
7777   case X86::VDIVPDZ256rm:
7778   case X86::VDIVPDZ256rmb:
7779   case X86::VDIVPDZ256rmbk:
7780   case X86::VDIVPDZ256rmbkz:
7781   case X86::VDIVPDZ256rmk:
7782   case X86::VDIVPDZ256rmkz:
7783   case X86::VDIVPDZ256rr:
7784   case X86::VDIVPDZ256rrk:
7785   case X86::VDIVPDZ256rrkz:
7786   case X86::VDIVPDZrb:
7787   case X86::VDIVPDZrbk:
7788   case X86::VDIVPDZrbkz:
7789   case X86::VDIVPDZrm:
7790   case X86::VDIVPDZrmb:
7791   case X86::VDIVPDZrmbk:
7792   case X86::VDIVPDZrmbkz:
7793   case X86::VDIVPDZrmk:
7794   case X86::VDIVPDZrmkz:
7795   case X86::VDIVPDZrr:
7796   case X86::VDIVPDZrrk:
7797   case X86::VDIVPDZrrkz:
7798   case X86::VDIVPSZ128rm:
7799   case X86::VDIVPSZ128rmb:
7800   case X86::VDIVPSZ128rmbk:
7801   case X86::VDIVPSZ128rmbkz:
7802   case X86::VDIVPSZ128rmk:
7803   case X86::VDIVPSZ128rmkz:
7804   case X86::VDIVPSZ128rr:
7805   case X86::VDIVPSZ128rrk:
7806   case X86::VDIVPSZ128rrkz:
7807   case X86::VDIVPSZ256rm:
7808   case X86::VDIVPSZ256rmb:
7809   case X86::VDIVPSZ256rmbk:
7810   case X86::VDIVPSZ256rmbkz:
7811   case X86::VDIVPSZ256rmk:
7812   case X86::VDIVPSZ256rmkz:
7813   case X86::VDIVPSZ256rr:
7814   case X86::VDIVPSZ256rrk:
7815   case X86::VDIVPSZ256rrkz:
7816   case X86::VDIVPSZrb:
7817   case X86::VDIVPSZrbk:
7818   case X86::VDIVPSZrbkz:
7819   case X86::VDIVPSZrm:
7820   case X86::VDIVPSZrmb:
7821   case X86::VDIVPSZrmbk:
7822   case X86::VDIVPSZrmbkz:
7823   case X86::VDIVPSZrmk:
7824   case X86::VDIVPSZrmkz:
7825   case X86::VDIVPSZrr:
7826   case X86::VDIVPSZrrk:
7827   case X86::VDIVPSZrrkz:
7828   case X86::VDIVSDZrm:
7829   case X86::VDIVSDZrr:
7830   case X86::VDIVSDZrm_Int:
7831   case X86::VDIVSDZrm_Intk:
7832   case X86::VDIVSDZrm_Intkz:
7833   case X86::VDIVSDZrr_Int:
7834   case X86::VDIVSDZrr_Intk:
7835   case X86::VDIVSDZrr_Intkz:
7836   case X86::VDIVSDZrrb:
7837   case X86::VDIVSDZrrbk:
7838   case X86::VDIVSDZrrbkz:
7839   case X86::VDIVSSZrm:
7840   case X86::VDIVSSZrr:
7841   case X86::VDIVSSZrm_Int:
7842   case X86::VDIVSSZrm_Intk:
7843   case X86::VDIVSSZrm_Intkz:
7844   case X86::VDIVSSZrr_Int:
7845   case X86::VDIVSSZrr_Intk:
7846   case X86::VDIVSSZrr_Intkz:
7847   case X86::VDIVSSZrrb:
7848   case X86::VDIVSSZrrbk:
7849   case X86::VDIVSSZrrbkz:
7850   case X86::VSQRTPDZ128m:
7851   case X86::VSQRTPDZ128mb:
7852   case X86::VSQRTPDZ128mbk:
7853   case X86::VSQRTPDZ128mbkz:
7854   case X86::VSQRTPDZ128mk:
7855   case X86::VSQRTPDZ128mkz:
7856   case X86::VSQRTPDZ128r:
7857   case X86::VSQRTPDZ128rk:
7858   case X86::VSQRTPDZ128rkz:
7859   case X86::VSQRTPDZ256m:
7860   case X86::VSQRTPDZ256mb:
7861   case X86::VSQRTPDZ256mbk:
7862   case X86::VSQRTPDZ256mbkz:
7863   case X86::VSQRTPDZ256mk:
7864   case X86::VSQRTPDZ256mkz:
7865   case X86::VSQRTPDZ256r:
7866   case X86::VSQRTPDZ256rk:
7867   case X86::VSQRTPDZ256rkz:
7868   case X86::VSQRTPDZm:
7869   case X86::VSQRTPDZmb:
7870   case X86::VSQRTPDZmbk:
7871   case X86::VSQRTPDZmbkz:
7872   case X86::VSQRTPDZmk:
7873   case X86::VSQRTPDZmkz:
7874   case X86::VSQRTPDZr:
7875   case X86::VSQRTPDZrb:
7876   case X86::VSQRTPDZrbk:
7877   case X86::VSQRTPDZrbkz:
7878   case X86::VSQRTPDZrk:
7879   case X86::VSQRTPDZrkz:
7880   case X86::VSQRTPSZ128m:
7881   case X86::VSQRTPSZ128mb:
7882   case X86::VSQRTPSZ128mbk:
7883   case X86::VSQRTPSZ128mbkz:
7884   case X86::VSQRTPSZ128mk:
7885   case X86::VSQRTPSZ128mkz:
7886   case X86::VSQRTPSZ128r:
7887   case X86::VSQRTPSZ128rk:
7888   case X86::VSQRTPSZ128rkz:
7889   case X86::VSQRTPSZ256m:
7890   case X86::VSQRTPSZ256mb:
7891   case X86::VSQRTPSZ256mbk:
7892   case X86::VSQRTPSZ256mbkz:
7893   case X86::VSQRTPSZ256mk:
7894   case X86::VSQRTPSZ256mkz:
7895   case X86::VSQRTPSZ256r:
7896   case X86::VSQRTPSZ256rk:
7897   case X86::VSQRTPSZ256rkz:
7898   case X86::VSQRTPSZm:
7899   case X86::VSQRTPSZmb:
7900   case X86::VSQRTPSZmbk:
7901   case X86::VSQRTPSZmbkz:
7902   case X86::VSQRTPSZmk:
7903   case X86::VSQRTPSZmkz:
7904   case X86::VSQRTPSZr:
7905   case X86::VSQRTPSZrb:
7906   case X86::VSQRTPSZrbk:
7907   case X86::VSQRTPSZrbkz:
7908   case X86::VSQRTPSZrk:
7909   case X86::VSQRTPSZrkz:
7910   case X86::VSQRTSDZm:
7911   case X86::VSQRTSDZm_Int:
7912   case X86::VSQRTSDZm_Intk:
7913   case X86::VSQRTSDZm_Intkz:
7914   case X86::VSQRTSDZr:
7915   case X86::VSQRTSDZr_Int:
7916   case X86::VSQRTSDZr_Intk:
7917   case X86::VSQRTSDZr_Intkz:
7918   case X86::VSQRTSDZrb_Int:
7919   case X86::VSQRTSDZrb_Intk:
7920   case X86::VSQRTSDZrb_Intkz:
7921   case X86::VSQRTSSZm:
7922   case X86::VSQRTSSZm_Int:
7923   case X86::VSQRTSSZm_Intk:
7924   case X86::VSQRTSSZm_Intkz:
7925   case X86::VSQRTSSZr:
7926   case X86::VSQRTSSZr_Int:
7927   case X86::VSQRTSSZr_Intk:
7928   case X86::VSQRTSSZr_Intkz:
7929   case X86::VSQRTSSZrb_Int:
7930   case X86::VSQRTSSZrb_Intk:
7931   case X86::VSQRTSSZrb_Intkz:
7932 
7933   case X86::VGATHERDPDYrm:
7934   case X86::VGATHERDPDZ128rm:
7935   case X86::VGATHERDPDZ256rm:
7936   case X86::VGATHERDPDZrm:
7937   case X86::VGATHERDPDrm:
7938   case X86::VGATHERDPSYrm:
7939   case X86::VGATHERDPSZ128rm:
7940   case X86::VGATHERDPSZ256rm:
7941   case X86::VGATHERDPSZrm:
7942   case X86::VGATHERDPSrm:
7943   case X86::VGATHERPF0DPDm:
7944   case X86::VGATHERPF0DPSm:
7945   case X86::VGATHERPF0QPDm:
7946   case X86::VGATHERPF0QPSm:
7947   case X86::VGATHERPF1DPDm:
7948   case X86::VGATHERPF1DPSm:
7949   case X86::VGATHERPF1QPDm:
7950   case X86::VGATHERPF1QPSm:
7951   case X86::VGATHERQPDYrm:
7952   case X86::VGATHERQPDZ128rm:
7953   case X86::VGATHERQPDZ256rm:
7954   case X86::VGATHERQPDZrm:
7955   case X86::VGATHERQPDrm:
7956   case X86::VGATHERQPSYrm:
7957   case X86::VGATHERQPSZ128rm:
7958   case X86::VGATHERQPSZ256rm:
7959   case X86::VGATHERQPSZrm:
7960   case X86::VGATHERQPSrm:
7961   case X86::VPGATHERDDYrm:
7962   case X86::VPGATHERDDZ128rm:
7963   case X86::VPGATHERDDZ256rm:
7964   case X86::VPGATHERDDZrm:
7965   case X86::VPGATHERDDrm:
7966   case X86::VPGATHERDQYrm:
7967   case X86::VPGATHERDQZ128rm:
7968   case X86::VPGATHERDQZ256rm:
7969   case X86::VPGATHERDQZrm:
7970   case X86::VPGATHERDQrm:
7971   case X86::VPGATHERQDYrm:
7972   case X86::VPGATHERQDZ128rm:
7973   case X86::VPGATHERQDZ256rm:
7974   case X86::VPGATHERQDZrm:
7975   case X86::VPGATHERQDrm:
7976   case X86::VPGATHERQQYrm:
7977   case X86::VPGATHERQQZ128rm:
7978   case X86::VPGATHERQQZ256rm:
7979   case X86::VPGATHERQQZrm:
7980   case X86::VPGATHERQQrm:
7981   case X86::VSCATTERDPDZ128mr:
7982   case X86::VSCATTERDPDZ256mr:
7983   case X86::VSCATTERDPDZmr:
7984   case X86::VSCATTERDPSZ128mr:
7985   case X86::VSCATTERDPSZ256mr:
7986   case X86::VSCATTERDPSZmr:
7987   case X86::VSCATTERPF0DPDm:
7988   case X86::VSCATTERPF0DPSm:
7989   case X86::VSCATTERPF0QPDm:
7990   case X86::VSCATTERPF0QPSm:
7991   case X86::VSCATTERPF1DPDm:
7992   case X86::VSCATTERPF1DPSm:
7993   case X86::VSCATTERPF1QPDm:
7994   case X86::VSCATTERPF1QPSm:
7995   case X86::VSCATTERQPDZ128mr:
7996   case X86::VSCATTERQPDZ256mr:
7997   case X86::VSCATTERQPDZmr:
7998   case X86::VSCATTERQPSZ128mr:
7999   case X86::VSCATTERQPSZ256mr:
8000   case X86::VSCATTERQPSZmr:
8001   case X86::VPSCATTERDDZ128mr:
8002   case X86::VPSCATTERDDZ256mr:
8003   case X86::VPSCATTERDDZmr:
8004   case X86::VPSCATTERDQZ128mr:
8005   case X86::VPSCATTERDQZ256mr:
8006   case X86::VPSCATTERDQZmr:
8007   case X86::VPSCATTERQDZ128mr:
8008   case X86::VPSCATTERQDZ256mr:
8009   case X86::VPSCATTERQDZmr:
8010   case X86::VPSCATTERQQZ128mr:
8011   case X86::VPSCATTERQQZ256mr:
8012   case X86::VPSCATTERQQZmr:
8013     return true;
8014   }
8015 }
8016 
8017 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
8018                                          const MachineRegisterInfo *MRI,
8019                                          const MachineInstr &DefMI,
8020                                          unsigned DefIdx,
8021                                          const MachineInstr &UseMI,
8022                                          unsigned UseIdx) const {
8023   return isHighLatencyDef(DefMI.getOpcode());
8024 }
8025 
8026 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
8027                                            const MachineBasicBlock *MBB) const {
8028   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
8029          "Reassociation needs binary operators");
8030 
8031   // Integer binary math/logic instructions have a third source operand:
8032   // the EFLAGS register. That operand must be both defined here and never
8033   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
8034   // not change anything because rearranging the operands could affect other
8035   // instructions that depend on the exact status flags (zero, sign, etc.)
8036   // that are set by using these particular operands with this operation.
8037   if (Inst.getNumOperands() == 4) {
8038     assert(Inst.getOperand(3).isReg() &&
8039            Inst.getOperand(3).getReg() == X86::EFLAGS &&
8040            "Unexpected operand in reassociable instruction");
8041     if (!Inst.getOperand(3).isDead())
8042       return false;
8043   }
8044 
8045   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
8046 }
8047 
8048 // TODO: There are many more machine instruction opcodes to match:
8049 //       1. Other data types (integer, vectors)
8050 //       2. Other math / logic operations (xor, or)
8051 //       3. Other forms of the same operation (intrinsics and other variants)
8052 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
8053   switch (Inst.getOpcode()) {
8054   case X86::AND8rr:
8055   case X86::AND16rr:
8056   case X86::AND32rr:
8057   case X86::AND64rr:
8058   case X86::OR8rr:
8059   case X86::OR16rr:
8060   case X86::OR32rr:
8061   case X86::OR64rr:
8062   case X86::XOR8rr:
8063   case X86::XOR16rr:
8064   case X86::XOR32rr:
8065   case X86::XOR64rr:
8066   case X86::IMUL16rr:
8067   case X86::IMUL32rr:
8068   case X86::IMUL64rr:
8069   case X86::PANDrr:
8070   case X86::PORrr:
8071   case X86::PXORrr:
8072   case X86::ANDPDrr:
8073   case X86::ANDPSrr:
8074   case X86::ORPDrr:
8075   case X86::ORPSrr:
8076   case X86::XORPDrr:
8077   case X86::XORPSrr:
8078   case X86::PADDBrr:
8079   case X86::PADDWrr:
8080   case X86::PADDDrr:
8081   case X86::PADDQrr:
8082   case X86::VPANDrr:
8083   case X86::VPANDYrr:
8084   case X86::VPANDDZ128rr:
8085   case X86::VPANDDZ256rr:
8086   case X86::VPANDDZrr:
8087   case X86::VPANDQZ128rr:
8088   case X86::VPANDQZ256rr:
8089   case X86::VPANDQZrr:
8090   case X86::VPORrr:
8091   case X86::VPORYrr:
8092   case X86::VPORDZ128rr:
8093   case X86::VPORDZ256rr:
8094   case X86::VPORDZrr:
8095   case X86::VPORQZ128rr:
8096   case X86::VPORQZ256rr:
8097   case X86::VPORQZrr:
8098   case X86::VPXORrr:
8099   case X86::VPXORYrr:
8100   case X86::VPXORDZ128rr:
8101   case X86::VPXORDZ256rr:
8102   case X86::VPXORDZrr:
8103   case X86::VPXORQZ128rr:
8104   case X86::VPXORQZ256rr:
8105   case X86::VPXORQZrr:
8106   case X86::VANDPDrr:
8107   case X86::VANDPSrr:
8108   case X86::VANDPDYrr:
8109   case X86::VANDPSYrr:
8110   case X86::VANDPDZ128rr:
8111   case X86::VANDPSZ128rr:
8112   case X86::VANDPDZ256rr:
8113   case X86::VANDPSZ256rr:
8114   case X86::VANDPDZrr:
8115   case X86::VANDPSZrr:
8116   case X86::VORPDrr:
8117   case X86::VORPSrr:
8118   case X86::VORPDYrr:
8119   case X86::VORPSYrr:
8120   case X86::VORPDZ128rr:
8121   case X86::VORPSZ128rr:
8122   case X86::VORPDZ256rr:
8123   case X86::VORPSZ256rr:
8124   case X86::VORPDZrr:
8125   case X86::VORPSZrr:
8126   case X86::VXORPDrr:
8127   case X86::VXORPSrr:
8128   case X86::VXORPDYrr:
8129   case X86::VXORPSYrr:
8130   case X86::VXORPDZ128rr:
8131   case X86::VXORPSZ128rr:
8132   case X86::VXORPDZ256rr:
8133   case X86::VXORPSZ256rr:
8134   case X86::VXORPDZrr:
8135   case X86::VXORPSZrr:
8136   case X86::KADDBrr:
8137   case X86::KADDWrr:
8138   case X86::KADDDrr:
8139   case X86::KADDQrr:
8140   case X86::KANDBrr:
8141   case X86::KANDWrr:
8142   case X86::KANDDrr:
8143   case X86::KANDQrr:
8144   case X86::KORBrr:
8145   case X86::KORWrr:
8146   case X86::KORDrr:
8147   case X86::KORQrr:
8148   case X86::KXORBrr:
8149   case X86::KXORWrr:
8150   case X86::KXORDrr:
8151   case X86::KXORQrr:
8152   case X86::VPADDBrr:
8153   case X86::VPADDWrr:
8154   case X86::VPADDDrr:
8155   case X86::VPADDQrr:
8156   case X86::VPADDBYrr:
8157   case X86::VPADDWYrr:
8158   case X86::VPADDDYrr:
8159   case X86::VPADDQYrr:
8160   case X86::VPADDBZ128rr:
8161   case X86::VPADDWZ128rr:
8162   case X86::VPADDDZ128rr:
8163   case X86::VPADDQZ128rr:
8164   case X86::VPADDBZ256rr:
8165   case X86::VPADDWZ256rr:
8166   case X86::VPADDDZ256rr:
8167   case X86::VPADDQZ256rr:
8168   case X86::VPADDBZrr:
8169   case X86::VPADDWZrr:
8170   case X86::VPADDDZrr:
8171   case X86::VPADDQZrr:
8172   case X86::VPMULLWrr:
8173   case X86::VPMULLWYrr:
8174   case X86::VPMULLWZ128rr:
8175   case X86::VPMULLWZ256rr:
8176   case X86::VPMULLWZrr:
8177   case X86::VPMULLDrr:
8178   case X86::VPMULLDYrr:
8179   case X86::VPMULLDZ128rr:
8180   case X86::VPMULLDZ256rr:
8181   case X86::VPMULLDZrr:
8182   case X86::VPMULLQZ128rr:
8183   case X86::VPMULLQZ256rr:
8184   case X86::VPMULLQZrr:
8185   // Normal min/max instructions are not commutative because of NaN and signed
8186   // zero semantics, but these are. Thus, there's no need to check for global
8187   // relaxed math; the instructions themselves have the properties we need.
8188   case X86::MAXCPDrr:
8189   case X86::MAXCPSrr:
8190   case X86::MAXCSDrr:
8191   case X86::MAXCSSrr:
8192   case X86::MINCPDrr:
8193   case X86::MINCPSrr:
8194   case X86::MINCSDrr:
8195   case X86::MINCSSrr:
8196   case X86::VMAXCPDrr:
8197   case X86::VMAXCPSrr:
8198   case X86::VMAXCPDYrr:
8199   case X86::VMAXCPSYrr:
8200   case X86::VMAXCPDZ128rr:
8201   case X86::VMAXCPSZ128rr:
8202   case X86::VMAXCPDZ256rr:
8203   case X86::VMAXCPSZ256rr:
8204   case X86::VMAXCPDZrr:
8205   case X86::VMAXCPSZrr:
8206   case X86::VMAXCSDrr:
8207   case X86::VMAXCSSrr:
8208   case X86::VMAXCSDZrr:
8209   case X86::VMAXCSSZrr:
8210   case X86::VMINCPDrr:
8211   case X86::VMINCPSrr:
8212   case X86::VMINCPDYrr:
8213   case X86::VMINCPSYrr:
8214   case X86::VMINCPDZ128rr:
8215   case X86::VMINCPSZ128rr:
8216   case X86::VMINCPDZ256rr:
8217   case X86::VMINCPSZ256rr:
8218   case X86::VMINCPDZrr:
8219   case X86::VMINCPSZrr:
8220   case X86::VMINCSDrr:
8221   case X86::VMINCSSrr:
8222   case X86::VMINCSDZrr:
8223   case X86::VMINCSSZrr:
8224     return true;
8225   case X86::ADDPDrr:
8226   case X86::ADDPSrr:
8227   case X86::ADDSDrr:
8228   case X86::ADDSSrr:
8229   case X86::MULPDrr:
8230   case X86::MULPSrr:
8231   case X86::MULSDrr:
8232   case X86::MULSSrr:
8233   case X86::VADDPDrr:
8234   case X86::VADDPSrr:
8235   case X86::VADDPDYrr:
8236   case X86::VADDPSYrr:
8237   case X86::VADDPDZ128rr:
8238   case X86::VADDPSZ128rr:
8239   case X86::VADDPDZ256rr:
8240   case X86::VADDPSZ256rr:
8241   case X86::VADDPDZrr:
8242   case X86::VADDPSZrr:
8243   case X86::VADDSDrr:
8244   case X86::VADDSSrr:
8245   case X86::VADDSDZrr:
8246   case X86::VADDSSZrr:
8247   case X86::VMULPDrr:
8248   case X86::VMULPSrr:
8249   case X86::VMULPDYrr:
8250   case X86::VMULPSYrr:
8251   case X86::VMULPDZ128rr:
8252   case X86::VMULPSZ128rr:
8253   case X86::VMULPDZ256rr:
8254   case X86::VMULPSZ256rr:
8255   case X86::VMULPDZrr:
8256   case X86::VMULPSZrr:
8257   case X86::VMULSDrr:
8258   case X86::VMULSSrr:
8259   case X86::VMULSDZrr:
8260   case X86::VMULSSZrr:
8261     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
8262   default:
8263     return false;
8264   }
8265 }
8266 
8267 /// This is an architecture-specific helper function of reassociateOps.
8268 /// Set special operand attributes for new instructions after reassociation.
8269 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
8270                                          MachineInstr &OldMI2,
8271                                          MachineInstr &NewMI1,
8272                                          MachineInstr &NewMI2) const {
8273   // Integer instructions define an implicit EFLAGS source register operand as
8274   // the third source (fourth total) operand.
8275   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
8276     return;
8277 
8278   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
8279          "Unexpected instruction type for reassociation");
8280 
8281   MachineOperand &OldOp1 = OldMI1.getOperand(3);
8282   MachineOperand &OldOp2 = OldMI2.getOperand(3);
8283   MachineOperand &NewOp1 = NewMI1.getOperand(3);
8284   MachineOperand &NewOp2 = NewMI2.getOperand(3);
8285 
8286   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
8287          "Must have dead EFLAGS operand in reassociable instruction");
8288   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
8289          "Must have dead EFLAGS operand in reassociable instruction");
8290 
8291   (void)OldOp1;
8292   (void)OldOp2;
8293 
8294   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
8295          "Unexpected operand in reassociable instruction");
8296   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
8297          "Unexpected operand in reassociable instruction");
8298 
8299   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8300   // of this pass or other passes. The EFLAGS operands must be dead in these new
8301   // instructions because the EFLAGS operands in the original instructions must
8302   // be dead in order for reassociation to occur.
8303   NewOp1.setIsDead();
8304   NewOp2.setIsDead();
8305 }
8306 
8307 std::pair<unsigned, unsigned>
8308 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8309   return std::make_pair(TF, 0u);
8310 }
8311 
8312 ArrayRef<std::pair<unsigned, const char *>>
8313 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8314   using namespace X86II;
8315   static const std::pair<unsigned, const char *> TargetFlags[] = {
8316       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8317       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
8318       {MO_GOT, "x86-got"},
8319       {MO_GOTOFF, "x86-gotoff"},
8320       {MO_GOTPCREL, "x86-gotpcrel"},
8321       {MO_PLT, "x86-plt"},
8322       {MO_TLSGD, "x86-tlsgd"},
8323       {MO_TLSLD, "x86-tlsld"},
8324       {MO_TLSLDM, "x86-tlsldm"},
8325       {MO_GOTTPOFF, "x86-gottpoff"},
8326       {MO_INDNTPOFF, "x86-indntpoff"},
8327       {MO_TPOFF, "x86-tpoff"},
8328       {MO_DTPOFF, "x86-dtpoff"},
8329       {MO_NTPOFF, "x86-ntpoff"},
8330       {MO_GOTNTPOFF, "x86-gotntpoff"},
8331       {MO_DLLIMPORT, "x86-dllimport"},
8332       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
8333       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
8334       {MO_TLVP, "x86-tlvp"},
8335       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
8336       {MO_SECREL, "x86-secrel"}};
8337   return makeArrayRef(TargetFlags);
8338 }
8339 
8340 bool X86InstrInfo::isTailCall(const MachineInstr &Inst) const {
8341   switch (Inst.getOpcode()) {
8342     case X86::TCRETURNdi:
8343     case X86::TCRETURNmi:
8344     case X86::TCRETURNri:
8345     case X86::TCRETURNdi64:
8346     case X86::TCRETURNmi64:
8347     case X86::TCRETURNri64:
8348     case X86::TAILJMPd:
8349     case X86::TAILJMPm:
8350     case X86::TAILJMPr:
8351     case X86::TAILJMPd64:
8352     case X86::TAILJMPm64:
8353     case X86::TAILJMPr64:
8354     case X86::TAILJMPm64_REX:
8355     case X86::TAILJMPr64_REX:
8356       return true;
8357     default:
8358       return false;
8359   }
8360 }
8361 
8362 namespace {
8363   /// Create Global Base Reg pass. This initializes the PIC
8364   /// global base register for x86-32.
8365   struct CGBR : public MachineFunctionPass {
8366     static char ID;
8367     CGBR() : MachineFunctionPass(ID) {}
8368 
8369     bool runOnMachineFunction(MachineFunction &MF) override {
8370       const X86TargetMachine *TM =
8371         static_cast<const X86TargetMachine *>(&MF.getTarget());
8372       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
8373 
8374       // Don't do anything if this is 64-bit as 64-bit PIC
8375       // uses RIP relative addressing.
8376       if (STI.is64Bit())
8377         return false;
8378 
8379       // Only emit a global base reg in PIC mode.
8380       if (!TM->isPositionIndependent())
8381         return false;
8382 
8383       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8384       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
8385 
8386       // If we didn't need a GlobalBaseReg, don't insert code.
8387       if (GlobalBaseReg == 0)
8388         return false;
8389 
8390       // Insert the set of GlobalBaseReg into the first MBB of the function
8391       MachineBasicBlock &FirstMBB = MF.front();
8392       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
8393       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
8394       MachineRegisterInfo &RegInfo = MF.getRegInfo();
8395       const X86InstrInfo *TII = STI.getInstrInfo();
8396 
8397       unsigned PC;
8398       if (STI.isPICStyleGOT())
8399         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
8400       else
8401         PC = GlobalBaseReg;
8402 
8403       // Operand of MovePCtoStack is completely ignored by asm printer. It's
8404       // only used in JIT code emission as displacement to pc.
8405       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
8406 
8407       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
8408       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
8409       if (STI.isPICStyleGOT()) {
8410         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
8411         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
8412           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8413                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
8414       }
8415 
8416       return true;
8417     }
8418 
8419     const char *getPassName() const override {
8420       return "X86 PIC Global Base Reg Initialization";
8421     }
8422 
8423     void getAnalysisUsage(AnalysisUsage &AU) const override {
8424       AU.setPreservesCFG();
8425       MachineFunctionPass::getAnalysisUsage(AU);
8426     }
8427   };
8428 }
8429 
8430 char CGBR::ID = 0;
8431 FunctionPass*
8432 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
8433 
8434 namespace {
8435   struct LDTLSCleanup : public MachineFunctionPass {
8436     static char ID;
8437     LDTLSCleanup() : MachineFunctionPass(ID) {}
8438 
8439     bool runOnMachineFunction(MachineFunction &MF) override {
8440       if (skipFunction(*MF.getFunction()))
8441         return false;
8442 
8443       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
8444       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8445         // No point folding accesses if there isn't at least two.
8446         return false;
8447       }
8448 
8449       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8450       return VisitNode(DT->getRootNode(), 0);
8451     }
8452 
8453     // Visit the dominator subtree rooted at Node in pre-order.
8454     // If TLSBaseAddrReg is non-null, then use that to replace any
8455     // TLS_base_addr instructions. Otherwise, create the register
8456     // when the first such instruction is seen, and then use it
8457     // as we encounter more instructions.
8458     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8459       MachineBasicBlock *BB = Node->getBlock();
8460       bool Changed = false;
8461 
8462       // Traverse the current block.
8463       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8464            ++I) {
8465         switch (I->getOpcode()) {
8466           case X86::TLS_base_addr32:
8467           case X86::TLS_base_addr64:
8468             if (TLSBaseAddrReg)
8469               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
8470             else
8471               I = SetRegister(*I, &TLSBaseAddrReg);
8472             Changed = true;
8473             break;
8474           default:
8475             break;
8476         }
8477       }
8478 
8479       // Visit the children of this block in the dominator tree.
8480       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
8481            I != E; ++I) {
8482         Changed |= VisitNode(*I, TLSBaseAddrReg);
8483       }
8484 
8485       return Changed;
8486     }
8487 
8488     // Replace the TLS_base_addr instruction I with a copy from
8489     // TLSBaseAddrReg, returning the new instruction.
8490     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
8491                                          unsigned TLSBaseAddrReg) {
8492       MachineFunction *MF = I.getParent()->getParent();
8493       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8494       const bool is64Bit = STI.is64Bit();
8495       const X86InstrInfo *TII = STI.getInstrInfo();
8496 
8497       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
8498       MachineInstr *Copy =
8499           BuildMI(*I.getParent(), I, I.getDebugLoc(),
8500                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8501               .addReg(TLSBaseAddrReg);
8502 
8503       // Erase the TLS_base_addr instruction.
8504       I.eraseFromParent();
8505 
8506       return Copy;
8507     }
8508 
8509     // Create a virtal register in *TLSBaseAddrReg, and populate it by
8510     // inserting a copy instruction after I. Returns the new instruction.
8511     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8512       MachineFunction *MF = I.getParent()->getParent();
8513       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8514       const bool is64Bit = STI.is64Bit();
8515       const X86InstrInfo *TII = STI.getInstrInfo();
8516 
8517       // Create a virtual register for the TLS base address.
8518       MachineRegisterInfo &RegInfo = MF->getRegInfo();
8519       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8520                                                       ? &X86::GR64RegClass
8521                                                       : &X86::GR32RegClass);
8522 
8523       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
8524       MachineInstr *Next = I.getNextNode();
8525       MachineInstr *Copy =
8526           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8527                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8528               .addReg(is64Bit ? X86::RAX : X86::EAX);
8529 
8530       return Copy;
8531     }
8532 
8533     const char *getPassName() const override {
8534       return "Local Dynamic TLS Access Clean-up";
8535     }
8536 
8537     void getAnalysisUsage(AnalysisUsage &AU) const override {
8538       AU.setPreservesCFG();
8539       AU.addRequired<MachineDominatorTree>();
8540       MachineFunctionPass::getAnalysisUsage(AU);
8541     }
8542   };
8543 }
8544 
8545 char LDTLSCleanup::ID = 0;
8546 FunctionPass*
8547 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
8548