1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include <limits>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "x86-instr-info"
44 
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "X86GenInstrInfo.inc"
47 
48 static cl::opt<bool>
49 NoFusing("disable-spill-fusing",
50          cl::desc("Disable fusing of spill code into instructions"));
51 static cl::opt<bool>
52 PrintFailedFusing("print-failed-fuse-candidates",
53                   cl::desc("Print instructions that the allocator wants to"
54                            " fuse, but the X86 backend currently can't"),
55                   cl::Hidden);
56 static cl::opt<bool>
57 ReMatPICStubLoad("remat-pic-stub-load",
58                  cl::desc("Re-materialize load from stub in PIC mode"),
59                  cl::init(false), cl::Hidden);
60 
61 enum {
62   // Select which memory operand is being unfolded.
63   // (stored in bits 0 - 3)
64   TB_INDEX_0    = 0,
65   TB_INDEX_1    = 1,
66   TB_INDEX_2    = 2,
67   TB_INDEX_3    = 3,
68   TB_INDEX_4    = 4,
69   TB_INDEX_MASK = 0xf,
70 
71   // Do not insert the reverse map (MemOp -> RegOp) into the table.
72   // This may be needed because there is a many -> one mapping.
73   TB_NO_REVERSE   = 1 << 4,
74 
75   // Do not insert the forward map (RegOp -> MemOp) into the table.
76   // This is needed for Native Client, which prohibits branch
77   // instructions from using a memory operand.
78   TB_NO_FORWARD   = 1 << 5,
79 
80   TB_FOLDED_LOAD  = 1 << 6,
81   TB_FOLDED_STORE = 1 << 7,
82 
83   // Minimum alignment required for load/store.
84   // Used for RegOp->MemOp conversion.
85   // (stored in bits 8 - 15)
86   TB_ALIGN_SHIFT = 8,
87   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
88   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
89   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
90   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
91   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
92 };
93 
94 struct X86MemoryFoldTableEntry {
95   uint16_t RegOp;
96   uint16_t MemOp;
97   uint16_t Flags;
98 };
99 
100 // Pin the vtable to this file.
101 void X86InstrInfo::anchor() {}
102 
103 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
105                                                : X86::ADJCALLSTACKDOWN32),
106                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
107                                                : X86::ADJCALLSTACKUP32),
108                       X86::CATCHRET),
109       Subtarget(STI), RI(STI.getTargetTriple()) {
110 
111   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
112     { X86::ADC32ri,     X86::ADC32mi,    0 },
113     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
114     { X86::ADC32rr,     X86::ADC32mr,    0 },
115     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
116     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
117     { X86::ADC64rr,     X86::ADC64mr,    0 },
118     { X86::ADD16ri,     X86::ADD16mi,    0 },
119     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
120     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
121     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
122     { X86::ADD16rr,     X86::ADD16mr,    0 },
123     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
124     { X86::ADD32ri,     X86::ADD32mi,    0 },
125     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
126     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
127     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
128     { X86::ADD32rr,     X86::ADD32mr,    0 },
129     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
130     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
131     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
132     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
133     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
134     { X86::ADD64rr,     X86::ADD64mr,    0 },
135     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
136     { X86::ADD8ri,      X86::ADD8mi,     0 },
137     { X86::ADD8rr,      X86::ADD8mr,     0 },
138     { X86::AND16ri,     X86::AND16mi,    0 },
139     { X86::AND16ri8,    X86::AND16mi8,   0 },
140     { X86::AND16rr,     X86::AND16mr,    0 },
141     { X86::AND32ri,     X86::AND32mi,    0 },
142     { X86::AND32ri8,    X86::AND32mi8,   0 },
143     { X86::AND32rr,     X86::AND32mr,    0 },
144     { X86::AND64ri32,   X86::AND64mi32,  0 },
145     { X86::AND64ri8,    X86::AND64mi8,   0 },
146     { X86::AND64rr,     X86::AND64mr,    0 },
147     { X86::AND8ri,      X86::AND8mi,     0 },
148     { X86::AND8rr,      X86::AND8mr,     0 },
149     { X86::DEC16r,      X86::DEC16m,     0 },
150     { X86::DEC32r,      X86::DEC32m,     0 },
151     { X86::DEC64r,      X86::DEC64m,     0 },
152     { X86::DEC8r,       X86::DEC8m,      0 },
153     { X86::INC16r,      X86::INC16m,     0 },
154     { X86::INC32r,      X86::INC32m,     0 },
155     { X86::INC64r,      X86::INC64m,     0 },
156     { X86::INC8r,       X86::INC8m,      0 },
157     { X86::NEG16r,      X86::NEG16m,     0 },
158     { X86::NEG32r,      X86::NEG32m,     0 },
159     { X86::NEG64r,      X86::NEG64m,     0 },
160     { X86::NEG8r,       X86::NEG8m,      0 },
161     { X86::NOT16r,      X86::NOT16m,     0 },
162     { X86::NOT32r,      X86::NOT32m,     0 },
163     { X86::NOT64r,      X86::NOT64m,     0 },
164     { X86::NOT8r,       X86::NOT8m,      0 },
165     { X86::OR16ri,      X86::OR16mi,     0 },
166     { X86::OR16ri8,     X86::OR16mi8,    0 },
167     { X86::OR16rr,      X86::OR16mr,     0 },
168     { X86::OR32ri,      X86::OR32mi,     0 },
169     { X86::OR32ri8,     X86::OR32mi8,    0 },
170     { X86::OR32rr,      X86::OR32mr,     0 },
171     { X86::OR64ri32,    X86::OR64mi32,   0 },
172     { X86::OR64ri8,     X86::OR64mi8,    0 },
173     { X86::OR64rr,      X86::OR64mr,     0 },
174     { X86::OR8ri,       X86::OR8mi,      0 },
175     { X86::OR8rr,       X86::OR8mr,      0 },
176     { X86::ROL16r1,     X86::ROL16m1,    0 },
177     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
178     { X86::ROL16ri,     X86::ROL16mi,    0 },
179     { X86::ROL32r1,     X86::ROL32m1,    0 },
180     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
181     { X86::ROL32ri,     X86::ROL32mi,    0 },
182     { X86::ROL64r1,     X86::ROL64m1,    0 },
183     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
184     { X86::ROL64ri,     X86::ROL64mi,    0 },
185     { X86::ROL8r1,      X86::ROL8m1,     0 },
186     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
187     { X86::ROL8ri,      X86::ROL8mi,     0 },
188     { X86::ROR16r1,     X86::ROR16m1,    0 },
189     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
190     { X86::ROR16ri,     X86::ROR16mi,    0 },
191     { X86::ROR32r1,     X86::ROR32m1,    0 },
192     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
193     { X86::ROR32ri,     X86::ROR32mi,    0 },
194     { X86::ROR64r1,     X86::ROR64m1,    0 },
195     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
196     { X86::ROR64ri,     X86::ROR64mi,    0 },
197     { X86::ROR8r1,      X86::ROR8m1,     0 },
198     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
199     { X86::ROR8ri,      X86::ROR8mi,     0 },
200     { X86::SAR16r1,     X86::SAR16m1,    0 },
201     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
202     { X86::SAR16ri,     X86::SAR16mi,    0 },
203     { X86::SAR32r1,     X86::SAR32m1,    0 },
204     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
205     { X86::SAR32ri,     X86::SAR32mi,    0 },
206     { X86::SAR64r1,     X86::SAR64m1,    0 },
207     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
208     { X86::SAR64ri,     X86::SAR64mi,    0 },
209     { X86::SAR8r1,      X86::SAR8m1,     0 },
210     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
211     { X86::SAR8ri,      X86::SAR8mi,     0 },
212     { X86::SBB32ri,     X86::SBB32mi,    0 },
213     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
214     { X86::SBB32rr,     X86::SBB32mr,    0 },
215     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
216     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
217     { X86::SBB64rr,     X86::SBB64mr,    0 },
218     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
219     { X86::SHL16ri,     X86::SHL16mi,    0 },
220     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
221     { X86::SHL32ri,     X86::SHL32mi,    0 },
222     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
223     { X86::SHL64ri,     X86::SHL64mi,    0 },
224     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
225     { X86::SHL8ri,      X86::SHL8mi,     0 },
226     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
227     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
228     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
229     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
230     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
231     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
232     { X86::SHR16r1,     X86::SHR16m1,    0 },
233     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
234     { X86::SHR16ri,     X86::SHR16mi,    0 },
235     { X86::SHR32r1,     X86::SHR32m1,    0 },
236     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
237     { X86::SHR32ri,     X86::SHR32mi,    0 },
238     { X86::SHR64r1,     X86::SHR64m1,    0 },
239     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
240     { X86::SHR64ri,     X86::SHR64mi,    0 },
241     { X86::SHR8r1,      X86::SHR8m1,     0 },
242     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
243     { X86::SHR8ri,      X86::SHR8mi,     0 },
244     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
245     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
246     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
247     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
248     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
249     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
250     { X86::SUB16ri,     X86::SUB16mi,    0 },
251     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
252     { X86::SUB16rr,     X86::SUB16mr,    0 },
253     { X86::SUB32ri,     X86::SUB32mi,    0 },
254     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
255     { X86::SUB32rr,     X86::SUB32mr,    0 },
256     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
257     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
258     { X86::SUB64rr,     X86::SUB64mr,    0 },
259     { X86::SUB8ri,      X86::SUB8mi,     0 },
260     { X86::SUB8rr,      X86::SUB8mr,     0 },
261     { X86::XOR16ri,     X86::XOR16mi,    0 },
262     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
263     { X86::XOR16rr,     X86::XOR16mr,    0 },
264     { X86::XOR32ri,     X86::XOR32mi,    0 },
265     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
266     { X86::XOR32rr,     X86::XOR32mr,    0 },
267     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
268     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
269     { X86::XOR64rr,     X86::XOR64mr,    0 },
270     { X86::XOR8ri,      X86::XOR8mi,     0 },
271     { X86::XOR8rr,      X86::XOR8mr,     0 }
272   };
273 
274   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
275     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
276                   Entry.RegOp, Entry.MemOp,
277                   // Index 0, folded load and store, no alignment requirement.
278                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
279   }
280 
281   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
282     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
283     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
284     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
285     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
286     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
287     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
288     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
289     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
290     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
291     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
292     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
293     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
294     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
295     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
296     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
297     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
298     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
299     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
300     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
301     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
302     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
303     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
304     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
305     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
306     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
307     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
308     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
309     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
310     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
311     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
312     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
313     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
314     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
315     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
316     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
317     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
318     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
319     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
320     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
321     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
322     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
323     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
326     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
327     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
328     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
329     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
330     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
331     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
332     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
333     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
334     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
335     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
336     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
337     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
338     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
339     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
340     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
341     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
342     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
343     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
344     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
345     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
346     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
347     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
348     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
349     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
350     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
351     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
352     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
353     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
354     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
355     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
356     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
357     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
358     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
359     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
360     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
361     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
362     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
363 
364     // AVX 128-bit versions of foldable instructions
365     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
366     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
367     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
368     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
369     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
370     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
371     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
372     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
373     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
374     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
375     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
376     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
377     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
378 
379     // AVX 256-bit foldable instructions
380     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
381     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
382     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
383     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
384     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
385     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
386 
387     // AVX-512 foldable instructions
388     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
389     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
390     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
391     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
392     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
393     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
394     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
395     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
396     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
397     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
398     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
399 
400     // AVX-512 foldable instructions (256-bit versions)
401     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
402     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
403     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
404     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
405     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
406     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
407     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
408     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
409     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
410     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
411 
412     // AVX-512 foldable instructions (128-bit versions)
413     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
414     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
415     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
416     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
417     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
418     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
419     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
420     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
421     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
422     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
423 
424     // F16C foldable instructions
425     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
426     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
427   };
428 
429   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
430     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
431                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
432   }
433 
434   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
435     { X86::BSF16rr,         X86::BSF16rm,             0 },
436     { X86::BSF32rr,         X86::BSF32rm,             0 },
437     { X86::BSF64rr,         X86::BSF64rm,             0 },
438     { X86::BSR16rr,         X86::BSR16rm,             0 },
439     { X86::BSR32rr,         X86::BSR32rm,             0 },
440     { X86::BSR64rr,         X86::BSR64rm,             0 },
441     { X86::CMP16rr,         X86::CMP16rm,             0 },
442     { X86::CMP32rr,         X86::CMP32rm,             0 },
443     { X86::CMP64rr,         X86::CMP64rm,             0 },
444     { X86::CMP8rr,          X86::CMP8rm,              0 },
445     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
446     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
447     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
448     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
449     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
450     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
451     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
452     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
453     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
454     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
455     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
456     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
457     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
458     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
459     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
460     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
461     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
462     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
463     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
464     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
465     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
466     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
467     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
468     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
469     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
470     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
471     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
472     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
473     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
474     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
475     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
476     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
477     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
478     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
479     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
480     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
481     { X86::MOV16rr,         X86::MOV16rm,             0 },
482     { X86::MOV32rr,         X86::MOV32rm,             0 },
483     { X86::MOV64rr,         X86::MOV64rm,             0 },
484     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
485     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
486     { X86::MOV8rr,          X86::MOV8rm,              0 },
487     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
488     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
489     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
490     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
491     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
492     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
493     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
494     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
495     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
496     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
497     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
498     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
499     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
500     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
501     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
502     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
503     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
504     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
505     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
506     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
507     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
508     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
509     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
510     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
511     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
512     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
513     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
514     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
515     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
516     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
517     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
518     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
519     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
520     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
521     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
522     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
523     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
524     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
525     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
526     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
527     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
528     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
529     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
530     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
531     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
532     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
533     { X86::RCPSSr,          X86::RCPSSm,              0 },
534     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          0 },
535     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
536     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
537     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
538     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
539     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
540     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
541     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
542     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
543     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
544     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
545     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
546     { X86::TEST16rr,        X86::TEST16rm,            0 },
547     { X86::TEST32rr,        X86::TEST32rm,            0 },
548     { X86::TEST64rr,        X86::TEST64rm,            0 },
549     { X86::TEST8rr,         X86::TEST8rm,             0 },
550     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
551     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
552     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
553 
554     // MMX version of foldable instructions
555     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
556     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
557     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
558     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
559     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
560     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
561     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
562     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
563     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
564     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
565 
566     // 3DNow! version of foldable instructions
567     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
568     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
569     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
570     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
571     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
572     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
573     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
574 
575     // AVX 128-bit versions of foldable instructions
576     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
577     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
578     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
579     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
580     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
581     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
582     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
583     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
584     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
585     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
586     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
587     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
588     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
589     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
590     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
591     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
592     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
593     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
594     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
595     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
596     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
597     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
598     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
599     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
600     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
601     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
602     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
603     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
604     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
605     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
606     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
607     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
608     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
609     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
610     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
611     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
612     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
613     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
614     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
615     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
616     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
617     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
618     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
619     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
620     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
621     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
622     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
623     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
624     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
625     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
626     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
627     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
628     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
629     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
630     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
631     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
632     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
633     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
634     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
635     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
636     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
637     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
638     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
639     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
640     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
641     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
642     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
643     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
644     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
645     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
646     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
647     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
648     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
649 
650     // AVX 256-bit foldable instructions
651     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
652     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
653     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
654     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
655     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
656     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
657     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
658     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
659     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
660     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
661     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
662     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
663     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
664     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
665     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
666     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
667     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
668     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
669     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
670     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
671     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
672     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
673     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
674     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
675     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
676     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
677     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
678 
679     // AVX2 foldable instructions
680 
681     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
682     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
683     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
684     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
685     // so they don't need an equivalent limitation.
686     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
687     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
688     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
689     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
690     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
691     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
692     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      0 },
693     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     0 },
694     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      0 },
695     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     0 },
696     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      0 },
697     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     0 },
698     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      0 },
699     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     0 },
700     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
701     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
702     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        0 },
703     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        0 },
704     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
705     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
706     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
707     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        0 },
708     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        0 },
709     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        0 },
710     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
711     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
712     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
713     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        0 },
714     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
715     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
716     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
717 
718     // XOP foldable instructions
719     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
720     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
721     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
722     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
723     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
724     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
725     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
726     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
727     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
728     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
729     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
730     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
731     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
732     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
733     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
734     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
735     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
736     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
737     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
738     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
739     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
740     { X86::VPROTBri,           X86::VPROTBmi,         0 },
741     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
742     { X86::VPROTDri,           X86::VPROTDmi,         0 },
743     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
744     { X86::VPROTQri,           X86::VPROTQmi,         0 },
745     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
746     { X86::VPROTWri,           X86::VPROTWmi,         0 },
747     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
748     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
749     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
750     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
751     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
752     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
753     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
754     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
755     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
756 
757     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
758     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
759     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
760     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
761     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
762     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
763     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
764     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
765     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
766     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
767     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
768     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
769     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
770     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
771     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
772     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
773     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
774     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
775     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
776     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
777     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
778     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
779     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
780     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
781     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
782     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
783     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
784     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
785     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
786     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
787     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
788     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
789     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
790     { X86::RORX32ri,        X86::RORX32mi,            0 },
791     { X86::RORX64ri,        X86::RORX64mi,            0 },
792     { X86::SARX32rr,        X86::SARX32rm,            0 },
793     { X86::SARX64rr,        X86::SARX64rm,            0 },
794     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
795     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
796     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
797     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
798     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
799     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
800     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
801     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
802     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
803     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
804     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
805 
806     // AVX-512 foldable instructions
807     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
808     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
809     { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
810     { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
811     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
812     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
813     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zrm,         0 },
814     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zrm,        0 },
815     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
816     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
817     { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
818     { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
819     { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
820     { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
821     { X86::VBROADCASTSSZr,  X86::VBROADCASTSSZm,      TB_NO_REVERSE },
822     { X86::VBROADCASTSDZr,  X86::VBROADCASTSDZm,      TB_NO_REVERSE },
823 
824     // AVX-512 foldable instructions (256-bit versions)
825     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256rm,          TB_ALIGN_32 },
826     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256rm,          TB_ALIGN_32 },
827     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256rm,        TB_ALIGN_32 },
828     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256rm,        TB_ALIGN_32 },
829     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256rm,         0 },
830     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256rm,        0 },
831     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256rm,        0 },
832     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256rm,        0 },
833     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256rm,          0 },
834     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256rm,          0 },
835     { X86::VBROADCASTSSZ256r,  X86::VBROADCASTSSZ256m,      TB_NO_REVERSE },
836     { X86::VBROADCASTSDZ256r,  X86::VBROADCASTSDZ256m,      TB_NO_REVERSE },
837 
838     // AVX-512 foldable instructions (256-bit versions)
839     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128rm,          TB_ALIGN_16 },
840     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128rm,          TB_ALIGN_16 },
841     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128rm,        TB_ALIGN_16 },
842     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128rm,        TB_ALIGN_16 },
843     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128rm,         0 },
844     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128rm,        0 },
845     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128rm,        0 },
846     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128rm,        0 },
847     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128rm,          0 },
848     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128rm,          0 },
849     { X86::VBROADCASTSSZ128r,  X86::VBROADCASTSSZ128m,      TB_NO_REVERSE },
850 
851     // F16C foldable instructions
852     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
853     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
854 
855     // AES foldable instructions
856     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
857     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
858     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
859     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
860   };
861 
862   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
863     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
864                   Entry.RegOp, Entry.MemOp,
865                   // Index 1, folded load
866                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
867   }
868 
869   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
870     { X86::ADC32rr,         X86::ADC32rm,       0 },
871     { X86::ADC64rr,         X86::ADC64rm,       0 },
872     { X86::ADD16rr,         X86::ADD16rm,       0 },
873     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
874     { X86::ADD32rr,         X86::ADD32rm,       0 },
875     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
876     { X86::ADD64rr,         X86::ADD64rm,       0 },
877     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
878     { X86::ADD8rr,          X86::ADD8rm,        0 },
879     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
880     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
881     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
882     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
883     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
884     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
885     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
886     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
887     { X86::AND16rr,         X86::AND16rm,       0 },
888     { X86::AND32rr,         X86::AND32rm,       0 },
889     { X86::AND64rr,         X86::AND64rm,       0 },
890     { X86::AND8rr,          X86::AND8rm,        0 },
891     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
892     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
893     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
894     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
895     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
896     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
897     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
898     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
899     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
900     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
901     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
902     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
903     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
904     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
905     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
906     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
907     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
908     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
909     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
910     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
911     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
912     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
913     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
914     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
915     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
916     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
917     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
918     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
919     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
920     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
921     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
922     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
923     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
924     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
925     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
926     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
927     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
928     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
929     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
930     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
931     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
932     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
933     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
934     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
935     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
936     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
937     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
938     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
939     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
940     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
941     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
942     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
943     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
944     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
945     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
946     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
947     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
948     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
949     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
950     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
951     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
952     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
953     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
954     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
955     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
956     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
957     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
958     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
959     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
960     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
961 
962     // Do not fold Fs* scalar logical op loads because there are no scalar
963     // load variants for these instructions. When folded, the load is required
964     // to be 128-bits, so the load size would not match.
965 
966     { X86::FvANDNPDrr,      X86::FvANDNPDrm,    TB_ALIGN_16 },
967     { X86::FvANDNPSrr,      X86::FvANDNPSrm,    TB_ALIGN_16 },
968     { X86::FvANDPDrr,       X86::FvANDPDrm,     TB_ALIGN_16 },
969     { X86::FvANDPSrr,       X86::FvANDPSrm,     TB_ALIGN_16 },
970     { X86::FvORPDrr,        X86::FvORPDrm,      TB_ALIGN_16 },
971     { X86::FvORPSrr,        X86::FvORPSrm,      TB_ALIGN_16 },
972     { X86::FvXORPDrr,       X86::FvXORPDrm,     TB_ALIGN_16 },
973     { X86::FvXORPSrr,       X86::FvXORPSrm,     TB_ALIGN_16 },
974     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
975     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
976     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
977     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
978     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
979     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
980     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
981     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
982     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
983     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
984     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
985     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
986     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
987     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
988     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
989     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
990     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
991     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
992     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
993     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
994     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
995     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
996     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
997     { X86::MINSDrr,         X86::MINSDrm,       0 },
998     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
999     { X86::MINSSrr,         X86::MINSSrm,       0 },
1000     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
1001     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1002     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1003     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1004     { X86::MULSDrr,         X86::MULSDrm,       0 },
1005     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
1006     { X86::MULSSrr,         X86::MULSSrm,       0 },
1007     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
1008     { X86::OR16rr,          X86::OR16rm,        0 },
1009     { X86::OR32rr,          X86::OR32rm,        0 },
1010     { X86::OR64rr,          X86::OR64rm,        0 },
1011     { X86::OR8rr,           X86::OR8rm,         0 },
1012     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1013     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1014     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1015     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1016     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1017     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1018     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1019     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1020     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1021     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1022     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1023     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1024     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1025     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1026     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
1027     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1028     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1029     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1030     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1031     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1032     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1033     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1034     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1035     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1036     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1037     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1038     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1039     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1040     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1041     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1042     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1043     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1044     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1045     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1046     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1047     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1048     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1049     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1050     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1051     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1052     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
1053     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1054     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1055     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1056     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1057     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1058     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1059     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1060     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1061     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1062     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1063     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1064     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1065     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1066     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1067     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
1068     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1069     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1070     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1071     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1072     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1073     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1074     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1075     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1076     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
1077     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
1078     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
1079     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1080     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1081     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1082     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1083     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1084     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1085     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1086     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1087     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1088     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1089     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1090     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1091     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1092     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1093     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1094     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1095     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1096     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1097     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1098     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1099     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1100     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1101     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1102     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1103     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1104     { X86::ROUNDSDr,        X86::ROUNDSDm,      0 },
1105     { X86::ROUNDSSr,        X86::ROUNDSSm,      0 },
1106     { X86::SBB32rr,         X86::SBB32rm,       0 },
1107     { X86::SBB64rr,         X86::SBB64rm,       0 },
1108     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1109     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1110     { X86::SUB16rr,         X86::SUB16rm,       0 },
1111     { X86::SUB32rr,         X86::SUB32rm,       0 },
1112     { X86::SUB64rr,         X86::SUB64rm,       0 },
1113     { X86::SUB8rr,          X86::SUB8rm,        0 },
1114     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1115     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1116     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1117     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1118     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1119     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1120     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1121     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1122     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1123     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1124     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1125     { X86::XOR16rr,         X86::XOR16rm,       0 },
1126     { X86::XOR32rr,         X86::XOR32rm,       0 },
1127     { X86::XOR64rr,         X86::XOR64rm,       0 },
1128     { X86::XOR8rr,          X86::XOR8rm,        0 },
1129     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1130     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1131 
1132     // MMX version of foldable instructions
1133     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1134     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1135     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1136     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1137     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1138     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1139     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1140     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1141     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1142     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1143     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1144     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1145     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1146     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1147     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1148     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1149     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1150     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1151     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1152     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1153     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1154     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1155     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1156     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1157     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1158     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1159     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1160     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1161     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1162     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1163     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1164     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1165     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1166     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1167     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1168     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1169     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1170     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1171     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1172     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1173     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1174     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1175     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1176     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1177     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1178     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1179     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1180     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1181     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1182     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1183     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1184     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1185     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1186     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1187     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1188     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1189     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1190     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1191     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1192     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1193     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1194     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1195     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1196     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1197     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1198     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1199     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1200     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1201     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1202     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1203 
1204     // 3DNow! version of foldable instructions
1205     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1206     { X86::PFACCrr,           X86::PFACCrm,           0 },
1207     { X86::PFADDrr,           X86::PFADDrm,           0 },
1208     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1209     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1210     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1211     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1212     { X86::PFMINrr,           X86::PFMINrm,           0 },
1213     { X86::PFMULrr,           X86::PFMULrm,           0 },
1214     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1215     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1216     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1217     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1218     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1219     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1220     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1221     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1222 
1223     // AVX 128-bit versions of foldable instructions
1224     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1225     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1226     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1227     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1228     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1229     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1230     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1231     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1232     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1233     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1234     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1235     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1236     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1237     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        0 },
1238     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1239     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      0 },
1240     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1241     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       0 },
1242     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1243     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       0 },
1244     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1245     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1246     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1247     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1248     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1249     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1250     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1251     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1252     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1253     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1254     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1255     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1256     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1257     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1258     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1259     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1260     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1261     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1262     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1263     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1264     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1265     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1266     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1267     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1268     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1269     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1270     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1271     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1272     // Do not fold VFs* loads because there are no scalar load variants for
1273     // these instructions. When folded, the load is required to be 128-bits, so
1274     // the load size would not match.
1275     { X86::VFvANDNPDrr,       X86::VFvANDNPDrm,        0 },
1276     { X86::VFvANDNPSrr,       X86::VFvANDNPSrm,        0 },
1277     { X86::VFvANDPDrr,        X86::VFvANDPDrm,         0 },
1278     { X86::VFvANDPSrr,        X86::VFvANDPSrm,         0 },
1279     { X86::VFvORPDrr,         X86::VFvORPDrm,          0 },
1280     { X86::VFvORPSrr,         X86::VFvORPSrm,          0 },
1281     { X86::VFvXORPDrr,        X86::VFvXORPDrm,         0 },
1282     { X86::VFvXORPSrr,        X86::VFvXORPSrm,         0 },
1283     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1284     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1285     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1286     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1287     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1288     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1289     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1290     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1291     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1292     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1293     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1294     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1295     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1296     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1297     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1298     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1299     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1300     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1301     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1302     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1303     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1304     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1305     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1306     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1307     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1308     { X86::VORPDrr,           X86::VORPDrm,            0 },
1309     { X86::VORPSrr,           X86::VORPSrm,            0 },
1310     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1311     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1312     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1313     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1314     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1315     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1316     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1317     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1318     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1319     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1320     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1321     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1322     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
1323     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1324     { X86::VPANDrr,           X86::VPANDrm,            0 },
1325     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1326     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1327     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1328     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1329     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1330     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1331     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1332     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1333     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1334     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1335     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1336     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1337     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1338     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1339     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1340     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1341     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1342     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1343     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1344     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1345     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1346     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1347     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1348     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1349     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1350     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1351     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1352     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1353     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1354     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1355     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1356     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1357     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1358     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1359     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1360     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1361     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1362     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1363     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1364     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1365     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1366     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1367     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1368     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1369     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1370     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1371     { X86::VPORrr,            X86::VPORrm,             0 },
1372     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1373     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1374     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
1375     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
1376     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
1377     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1378     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1379     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1380     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1381     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1382     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1383     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1384     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1385     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1386     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1387     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1388     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1389     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1390     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1391     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1392     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1393     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1394     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1395     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1396     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1397     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1398     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1399     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1400     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1401     { X86::VPXORrr,           X86::VPXORrm,            0 },
1402     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1403     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1404     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1405     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1406     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1407     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1408     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1409     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1410     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1411     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1412     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1413     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1414     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1415     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1416     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1417     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1418 
1419     // AVX 256-bit foldable instructions
1420     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1421     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1422     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1423     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1424     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1425     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1426     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1427     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1428     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1429     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1430     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1431     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1432     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1433     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1434     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1435     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1436     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1437     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1438     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1439     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1440     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1441     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1442     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1443     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1444     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1445     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1446     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1447     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1448     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1449     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1450     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1451     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1452     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1453     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1454     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1455     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1456     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1457     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1458     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1459     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1460     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1461     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1462     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1463 
1464     // AVX2 foldable instructions
1465     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1466     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1467     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1468     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1469     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1470     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1471     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1472     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1473     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1474     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1475     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1476     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1477     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1478     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1479     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1480     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1481     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1482     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1483     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1484     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1485     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1486     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1487     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1488     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1489     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1490     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1491     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1492     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1493     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1494     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1495     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1496     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1497     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1498     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1499     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1500     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1501     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1502     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1503     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1504     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1505     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1506     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1507     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1508     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1509     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1510     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1511     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1512     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1513     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1514     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1515     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1516     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1517     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1518     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1519     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1520     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1521     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1522     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1523     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1524     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1525     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1526     { X86::VPORYrr,           X86::VPORYrm,            0 },
1527     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1528     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1529     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1530     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1531     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1532     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1533     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1534     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1535     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1536     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1537     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1538     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1539     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1540     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1541     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1542     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1543     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1544     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1545     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1546     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1547     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1548     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1549     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1550     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1551     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1552     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1553     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1554     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1555     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1556     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1557     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1558     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1559     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1560     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1561     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1562     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1563     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1564     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1565     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1566     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1567 
1568     // FMA4 foldable patterns
1569     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1570     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1571     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1572     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1573     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_NONE },
1574     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_NONE },
1575     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1576     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1577     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1578     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1579     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_NONE },
1580     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_NONE },
1581     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1582     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1583     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1584     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1585     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_NONE },
1586     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_NONE },
1587     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1588     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1589     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1590     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1591     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_NONE },
1592     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_NONE },
1593     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1594     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1595     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_NONE },
1596     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_NONE },
1597     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1598     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1599     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_NONE },
1600     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_NONE },
1601 
1602     // XOP foldable instructions
1603     { X86::VPCMOVrr,          X86::VPCMOVmr,            0 },
1604     { X86::VPCMOVrrY,         X86::VPCMOVmrY,           0 },
1605     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1606     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1607     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1608     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1609     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1610     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1611     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1612     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1613     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1614     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1615     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1616     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1617     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1618     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1619     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1620     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1621     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1622     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1623     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1624     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1625     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1626     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1627     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1628     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1629     { X86::VPPERMrr,          X86::VPPERMmr,            0 },
1630     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1631     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1632     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1633     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1634     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1635     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1636     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1637     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1638     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1639     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1640     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1641     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1642 
1643     // BMI/BMI2 foldable instructions
1644     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1645     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1646     { X86::MULX32rr,          X86::MULX32rm,            0 },
1647     { X86::MULX64rr,          X86::MULX64rm,            0 },
1648     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1649     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1650     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1651     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1652 
1653     // ADX foldable instructions
1654     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1655     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1656     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1657     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1658 
1659     // AVX-512 foldable instructions
1660     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1661     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1662     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1663     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1664     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1665     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1666     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1667     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1668     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1669     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1670     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1671     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1672     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1673     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1674     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1675     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1676     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1677     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1678     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1679     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1680     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1681     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1682     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1683     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1684     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1685     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1686     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1687     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1688     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1689     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1690     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1691     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1692     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1693     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1694     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1695     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1696     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1697     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1698     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1699 
1700     // AVX-512{F,VL} foldable instructions
1701     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1702     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1703     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1704 
1705     // AVX-512{F,VL} foldable instructions
1706     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1707     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1708     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1709     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1710 
1711     // AES foldable instructions
1712     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1713     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1714     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1715     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1716     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
1717     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
1718     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
1719     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
1720 
1721     // SHA foldable instructions
1722     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1723     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1724     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1725     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1726     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1727     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1728     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
1729   };
1730 
1731   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
1732     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1733                   Entry.RegOp, Entry.MemOp,
1734                   // Index 2, folded load
1735                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1736   }
1737 
1738   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1739     // FMA foldable instructions
1740     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1741     { X86::VFMADDSSr231r_Int,     X86::VFMADDSSr231m_Int,     TB_ALIGN_NONE },
1742     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1743     { X86::VFMADDSDr231r_Int,     X86::VFMADDSDr231m_Int,     TB_ALIGN_NONE },
1744     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1745     { X86::VFMADDSSr132r_Int,     X86::VFMADDSSr132m_Int,     TB_ALIGN_NONE },
1746     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1747     { X86::VFMADDSDr132r_Int,     X86::VFMADDSDr132m_Int,     TB_ALIGN_NONE },
1748     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1749     { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     TB_ALIGN_NONE },
1750     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1751     { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     TB_ALIGN_NONE },
1752 
1753     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1754     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1755     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1756     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1757     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1758     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1759     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1760     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1761     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1762     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1763     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1764     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1765 
1766     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1767     { X86::VFNMADDSSr231r_Int,    X86::VFNMADDSSr231m_Int,    TB_ALIGN_NONE },
1768     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1769     { X86::VFNMADDSDr231r_Int,    X86::VFNMADDSDr231m_Int,    TB_ALIGN_NONE },
1770     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1771     { X86::VFNMADDSSr132r_Int,    X86::VFNMADDSSr132m_Int,    TB_ALIGN_NONE },
1772     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1773     { X86::VFNMADDSDr132r_Int,    X86::VFNMADDSDr132m_Int,    TB_ALIGN_NONE },
1774     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1775     { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    TB_ALIGN_NONE },
1776     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1777     { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    TB_ALIGN_NONE },
1778 
1779     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1780     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1781     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1782     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1783     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1784     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1785     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1786     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1787     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1788     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1789     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1790     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1791 
1792     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1793     { X86::VFMSUBSSr231r_Int,     X86::VFMSUBSSr231m_Int,     TB_ALIGN_NONE },
1794     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1795     { X86::VFMSUBSDr231r_Int,     X86::VFMSUBSDr231m_Int,     TB_ALIGN_NONE },
1796     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1797     { X86::VFMSUBSSr132r_Int,     X86::VFMSUBSSr132m_Int,     TB_ALIGN_NONE },
1798     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1799     { X86::VFMSUBSDr132r_Int,     X86::VFMSUBSDr132m_Int,     TB_ALIGN_NONE },
1800     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1801     { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     TB_ALIGN_NONE },
1802     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1803     { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     TB_ALIGN_NONE },
1804 
1805     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1806     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1807     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1808     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1809     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1810     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1811     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1812     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1813     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1814     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1815     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1816     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1817 
1818     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1819     { X86::VFNMSUBSSr231r_Int,    X86::VFNMSUBSSr231m_Int,    TB_ALIGN_NONE },
1820     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1821     { X86::VFNMSUBSDr231r_Int,    X86::VFNMSUBSDr231m_Int,    TB_ALIGN_NONE },
1822     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1823     { X86::VFNMSUBSSr132r_Int,    X86::VFNMSUBSSr132m_Int,    TB_ALIGN_NONE },
1824     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1825     { X86::VFNMSUBSDr132r_Int,    X86::VFNMSUBSDr132m_Int,    TB_ALIGN_NONE },
1826     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1827     { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    TB_ALIGN_NONE },
1828     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1829     { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    TB_ALIGN_NONE },
1830 
1831     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1832     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1833     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1834     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1835     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1836     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1837     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1838     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1839     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1840     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1841     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1842     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1843 
1844     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1845     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1846     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1847     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1848     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1849     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1850     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1851     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1852     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1853     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1854     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1855     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1856 
1857     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1858     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1859     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1860     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1861     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1862     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1863     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1864     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1865     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1866     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1867     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1868     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1869 
1870     // FMA4 foldable patterns
1871     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
1872     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
1873     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
1874     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
1875     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_NONE },
1876     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_NONE },
1877     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
1878     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
1879     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
1880     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
1881     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_NONE },
1882     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_NONE },
1883     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
1884     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
1885     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
1886     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
1887     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_NONE },
1888     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_NONE },
1889     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
1890     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
1891     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
1892     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
1893     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_NONE },
1894     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_NONE },
1895     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
1896     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
1897     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_NONE },
1898     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_NONE },
1899     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
1900     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
1901     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_NONE },
1902     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_NONE },
1903 
1904     // XOP foldable instructions
1905     { X86::VPCMOVrr,              X86::VPCMOVrm,              0 },
1906     { X86::VPCMOVrrY,             X86::VPCMOVrmY,             0 },
1907     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
1908     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
1909     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
1910     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
1911     { X86::VPPERMrr,              X86::VPPERMrm,              0 },
1912 
1913     // AVX-512 VPERMI instructions with 3 source operands.
1914     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1915     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1916     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1917     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1918     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1919     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1920     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1921     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1922     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1923     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1924     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1925     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1926     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
1927      // AVX-512 arithmetic instructions
1928     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
1929     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
1930     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
1931     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
1932     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
1933     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
1934     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
1935     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
1936     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
1937     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
1938     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
1939     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
1940     // AVX-512{F,VL} arithmetic instructions 256-bit
1941     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
1942     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
1943     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
1944     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
1945     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
1946     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
1947     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
1948     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
1949     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
1950     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
1951     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
1952     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
1953     // AVX-512{F,VL} arithmetic instructions 128-bit
1954     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
1955     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
1956     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
1957     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
1958     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
1959     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
1960     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
1961     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
1962     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
1963     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
1964     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
1965     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
1966   };
1967 
1968   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
1969     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1970                   Entry.RegOp, Entry.MemOp,
1971                   // Index 3, folded load
1972                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1973   }
1974 
1975   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
1976      // AVX-512 foldable instructions
1977     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
1978     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
1979     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
1980     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
1981     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
1982     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
1983     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
1984     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
1985     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
1986     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
1987     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
1988     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
1989     // AVX-512{F,VL} foldable instructions 256-bit
1990     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
1991     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
1992     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
1993     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
1994     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
1995     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
1996     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
1997     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
1998     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
1999     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
2000     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
2001     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
2002     // AVX-512{F,VL} foldable instructions 128-bit
2003     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
2004     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
2005     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
2006     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
2007     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
2008     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
2009     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
2010     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
2011     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
2012     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
2013     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
2014     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
2015   };
2016 
2017   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
2018     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2019                   Entry.RegOp, Entry.MemOp,
2020                   // Index 4, folded load
2021                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
2022   }
2023 }
2024 
2025 void
2026 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2027                             MemOp2RegOpTableType &M2RTable,
2028                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
2029     if ((Flags & TB_NO_FORWARD) == 0) {
2030       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2031       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2032     }
2033     if ((Flags & TB_NO_REVERSE) == 0) {
2034       assert(!M2RTable.count(MemOp) &&
2035            "Duplicated entries in unfolding maps?");
2036       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2037     }
2038 }
2039 
2040 bool
2041 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2042                                     unsigned &SrcReg, unsigned &DstReg,
2043                                     unsigned &SubIdx) const {
2044   switch (MI.getOpcode()) {
2045   default: break;
2046   case X86::MOVSX16rr8:
2047   case X86::MOVZX16rr8:
2048   case X86::MOVSX32rr8:
2049   case X86::MOVZX32rr8:
2050   case X86::MOVSX64rr8:
2051     if (!Subtarget.is64Bit())
2052       // It's not always legal to reference the low 8-bit of the larger
2053       // register in 32-bit mode.
2054       return false;
2055   case X86::MOVSX32rr16:
2056   case X86::MOVZX32rr16:
2057   case X86::MOVSX64rr16:
2058   case X86::MOVSX64rr32: {
2059     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2060       // Be conservative.
2061       return false;
2062     SrcReg = MI.getOperand(1).getReg();
2063     DstReg = MI.getOperand(0).getReg();
2064     switch (MI.getOpcode()) {
2065     default: llvm_unreachable("Unreachable!");
2066     case X86::MOVSX16rr8:
2067     case X86::MOVZX16rr8:
2068     case X86::MOVSX32rr8:
2069     case X86::MOVZX32rr8:
2070     case X86::MOVSX64rr8:
2071       SubIdx = X86::sub_8bit;
2072       break;
2073     case X86::MOVSX32rr16:
2074     case X86::MOVZX32rr16:
2075     case X86::MOVSX64rr16:
2076       SubIdx = X86::sub_16bit;
2077       break;
2078     case X86::MOVSX64rr32:
2079       SubIdx = X86::sub_32bit;
2080       break;
2081     }
2082     return true;
2083   }
2084   }
2085   return false;
2086 }
2087 
2088 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
2089   const MachineFunction *MF = MI->getParent()->getParent();
2090   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2091 
2092   if (MI->getOpcode() == getCallFrameSetupOpcode() ||
2093       MI->getOpcode() == getCallFrameDestroyOpcode()) {
2094     unsigned StackAlign = TFI->getStackAlignment();
2095     int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
2096                  StackAlign;
2097 
2098     SPAdj -= MI->getOperand(1).getImm();
2099 
2100     if (MI->getOpcode() == getCallFrameSetupOpcode())
2101       return SPAdj;
2102     else
2103       return -SPAdj;
2104   }
2105 
2106   // To know whether a call adjusts the stack, we need information
2107   // that is bound to the following ADJCALLSTACKUP pseudo.
2108   // Look for the next ADJCALLSTACKUP that follows the call.
2109   if (MI->isCall()) {
2110     const MachineBasicBlock* MBB = MI->getParent();
2111     auto I = ++MachineBasicBlock::const_iterator(MI);
2112     for (auto E = MBB->end(); I != E; ++I) {
2113       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2114           I->isCall())
2115         break;
2116     }
2117 
2118     // If we could not find a frame destroy opcode, then it has already
2119     // been simplified, so we don't care.
2120     if (I->getOpcode() != getCallFrameDestroyOpcode())
2121       return 0;
2122 
2123     return -(I->getOperand(1).getImm());
2124   }
2125 
2126   // Currently handle only PUSHes we can reasonably expect to see
2127   // in call sequences
2128   switch (MI->getOpcode()) {
2129   default:
2130     return 0;
2131   case X86::PUSH32i8:
2132   case X86::PUSH32r:
2133   case X86::PUSH32rmm:
2134   case X86::PUSH32rmr:
2135   case X86::PUSHi32:
2136     return 4;
2137   }
2138 }
2139 
2140 /// Return true and the FrameIndex if the specified
2141 /// operand and follow operands form a reference to the stack frame.
2142 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2143                                   int &FrameIndex) const {
2144   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2145       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2146       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2147       MI->getOperand(Op+X86::AddrDisp).isImm() &&
2148       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2149       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2150       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2151     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
2152     return true;
2153   }
2154   return false;
2155 }
2156 
2157 static bool isFrameLoadOpcode(int Opcode) {
2158   switch (Opcode) {
2159   default:
2160     return false;
2161   case X86::MOV8rm:
2162   case X86::MOV16rm:
2163   case X86::MOV32rm:
2164   case X86::MOV64rm:
2165   case X86::LD_Fp64m:
2166   case X86::MOVSSrm:
2167   case X86::MOVSDrm:
2168   case X86::MOVAPSrm:
2169   case X86::MOVAPDrm:
2170   case X86::MOVDQArm:
2171   case X86::VMOVSSrm:
2172   case X86::VMOVSDrm:
2173   case X86::VMOVAPSrm:
2174   case X86::VMOVAPDrm:
2175   case X86::VMOVDQArm:
2176   case X86::VMOVUPSYrm:
2177   case X86::VMOVAPSYrm:
2178   case X86::VMOVUPDYrm:
2179   case X86::VMOVAPDYrm:
2180   case X86::VMOVDQUYrm:
2181   case X86::VMOVDQAYrm:
2182   case X86::MMX_MOVD64rm:
2183   case X86::MMX_MOVQ64rm:
2184   case X86::VMOVAPSZrm:
2185   case X86::VMOVUPSZrm:
2186     return true;
2187   }
2188 }
2189 
2190 static bool isFrameStoreOpcode(int Opcode) {
2191   switch (Opcode) {
2192   default: break;
2193   case X86::MOV8mr:
2194   case X86::MOV16mr:
2195   case X86::MOV32mr:
2196   case X86::MOV64mr:
2197   case X86::ST_FpP64m:
2198   case X86::MOVSSmr:
2199   case X86::MOVSDmr:
2200   case X86::MOVAPSmr:
2201   case X86::MOVAPDmr:
2202   case X86::MOVDQAmr:
2203   case X86::VMOVSSmr:
2204   case X86::VMOVSDmr:
2205   case X86::VMOVAPSmr:
2206   case X86::VMOVAPDmr:
2207   case X86::VMOVDQAmr:
2208   case X86::VMOVUPSYmr:
2209   case X86::VMOVAPSYmr:
2210   case X86::VMOVUPDYmr:
2211   case X86::VMOVAPDYmr:
2212   case X86::VMOVDQUYmr:
2213   case X86::VMOVDQAYmr:
2214   case X86::VMOVUPSZmr:
2215   case X86::VMOVAPSZmr:
2216   case X86::MMX_MOVD64mr:
2217   case X86::MMX_MOVQ64mr:
2218   case X86::MMX_MOVNTQmr:
2219     return true;
2220   }
2221   return false;
2222 }
2223 
2224 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
2225                                            int &FrameIndex) const {
2226   if (isFrameLoadOpcode(MI->getOpcode()))
2227     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2228       return MI->getOperand(0).getReg();
2229   return 0;
2230 }
2231 
2232 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
2233                                                  int &FrameIndex) const {
2234   if (isFrameLoadOpcode(MI->getOpcode())) {
2235     unsigned Reg;
2236     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2237       return Reg;
2238     // Check for post-frame index elimination operations
2239     const MachineMemOperand *Dummy;
2240     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2241   }
2242   return 0;
2243 }
2244 
2245 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
2246                                           int &FrameIndex) const {
2247   if (isFrameStoreOpcode(MI->getOpcode()))
2248     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2249         isFrameOperand(MI, 0, FrameIndex))
2250       return MI->getOperand(X86::AddrNumOperands).getReg();
2251   return 0;
2252 }
2253 
2254 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2255                                                 int &FrameIndex) const {
2256   if (isFrameStoreOpcode(MI->getOpcode())) {
2257     unsigned Reg;
2258     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2259       return Reg;
2260     // Check for post-frame index elimination operations
2261     const MachineMemOperand *Dummy;
2262     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2263   }
2264   return 0;
2265 }
2266 
2267 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2268 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2269   // Don't waste compile time scanning use-def chains of physregs.
2270   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2271     return false;
2272   bool isPICBase = false;
2273   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2274          E = MRI.def_instr_end(); I != E; ++I) {
2275     MachineInstr *DefMI = &*I;
2276     if (DefMI->getOpcode() != X86::MOVPC32r)
2277       return false;
2278     assert(!isPICBase && "More than one PIC base?");
2279     isPICBase = true;
2280   }
2281   return isPICBase;
2282 }
2283 
2284 bool
2285 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2286                                                 AliasAnalysis *AA) const {
2287   switch (MI->getOpcode()) {
2288   default: break;
2289   case X86::MOV8rm:
2290   case X86::MOV16rm:
2291   case X86::MOV32rm:
2292   case X86::MOV64rm:
2293   case X86::LD_Fp64m:
2294   case X86::MOVSSrm:
2295   case X86::MOVSDrm:
2296   case X86::MOVAPSrm:
2297   case X86::MOVUPSrm:
2298   case X86::MOVAPDrm:
2299   case X86::MOVDQArm:
2300   case X86::MOVDQUrm:
2301   case X86::VMOVSSrm:
2302   case X86::VMOVSDrm:
2303   case X86::VMOVAPSrm:
2304   case X86::VMOVUPSrm:
2305   case X86::VMOVAPDrm:
2306   case X86::VMOVDQArm:
2307   case X86::VMOVDQUrm:
2308   case X86::VMOVAPSYrm:
2309   case X86::VMOVUPSYrm:
2310   case X86::VMOVAPDYrm:
2311   case X86::VMOVDQAYrm:
2312   case X86::VMOVDQUYrm:
2313   case X86::MMX_MOVD64rm:
2314   case X86::MMX_MOVQ64rm:
2315   case X86::FsVMOVAPSrm:
2316   case X86::FsVMOVAPDrm:
2317   case X86::FsMOVAPSrm:
2318   case X86::FsMOVAPDrm:
2319   // AVX-512
2320   case X86::VMOVAPDZ128rm:
2321   case X86::VMOVAPDZ256rm:
2322   case X86::VMOVAPDZrm:
2323   case X86::VMOVAPSZ128rm:
2324   case X86::VMOVAPSZ256rm:
2325   case X86::VMOVAPSZrm:
2326   case X86::VMOVDQA32Z128rm:
2327   case X86::VMOVDQA32Z256rm:
2328   case X86::VMOVDQA32Zrm:
2329   case X86::VMOVDQA64Z128rm:
2330   case X86::VMOVDQA64Z256rm:
2331   case X86::VMOVDQA64Zrm:
2332   case X86::VMOVDQU16Z128rm:
2333   case X86::VMOVDQU16Z256rm:
2334   case X86::VMOVDQU16Zrm:
2335   case X86::VMOVDQU32Z128rm:
2336   case X86::VMOVDQU32Z256rm:
2337   case X86::VMOVDQU32Zrm:
2338   case X86::VMOVDQU64Z128rm:
2339   case X86::VMOVDQU64Z256rm:
2340   case X86::VMOVDQU64Zrm:
2341   case X86::VMOVDQU8Z128rm:
2342   case X86::VMOVDQU8Z256rm:
2343   case X86::VMOVDQU8Zrm:
2344   case X86::VMOVUPSZ128rm:
2345   case X86::VMOVUPSZ256rm:
2346   case X86::VMOVUPSZrm: {
2347     // Loads from constant pools are trivially rematerializable.
2348     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2349         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2350         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2351         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2352         MI->isInvariantLoad(AA)) {
2353       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2354       if (BaseReg == 0 || BaseReg == X86::RIP)
2355         return true;
2356       // Allow re-materialization of PIC load.
2357       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
2358         return false;
2359       const MachineFunction &MF = *MI->getParent()->getParent();
2360       const MachineRegisterInfo &MRI = MF.getRegInfo();
2361       return regIsPICBase(BaseReg, MRI);
2362     }
2363     return false;
2364   }
2365 
2366   case X86::LEA32r:
2367   case X86::LEA64r: {
2368     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2369         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2370         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2371         !MI->getOperand(1+X86::AddrDisp).isReg()) {
2372       // lea fi#, lea GV, etc. are all rematerializable.
2373       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
2374         return true;
2375       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2376       if (BaseReg == 0)
2377         return true;
2378       // Allow re-materialization of lea PICBase + x.
2379       const MachineFunction &MF = *MI->getParent()->getParent();
2380       const MachineRegisterInfo &MRI = MF.getRegInfo();
2381       return regIsPICBase(BaseReg, MRI);
2382     }
2383     return false;
2384   }
2385   }
2386 
2387   // All other instructions marked M_REMATERIALIZABLE are always trivially
2388   // rematerializable.
2389   return true;
2390 }
2391 
2392 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2393                                          MachineBasicBlock::iterator I) const {
2394   MachineBasicBlock::iterator E = MBB.end();
2395 
2396   // For compile time consideration, if we are not able to determine the
2397   // safety after visiting 4 instructions in each direction, we will assume
2398   // it's not safe.
2399   MachineBasicBlock::iterator Iter = I;
2400   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2401     bool SeenDef = false;
2402     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2403       MachineOperand &MO = Iter->getOperand(j);
2404       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2405         SeenDef = true;
2406       if (!MO.isReg())
2407         continue;
2408       if (MO.getReg() == X86::EFLAGS) {
2409         if (MO.isUse())
2410           return false;
2411         SeenDef = true;
2412       }
2413     }
2414 
2415     if (SeenDef)
2416       // This instruction defines EFLAGS, no need to look any further.
2417       return true;
2418     ++Iter;
2419     // Skip over DBG_VALUE.
2420     while (Iter != E && Iter->isDebugValue())
2421       ++Iter;
2422   }
2423 
2424   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2425   // live in.
2426   if (Iter == E) {
2427     for (MachineBasicBlock *S : MBB.successors())
2428       if (S->isLiveIn(X86::EFLAGS))
2429         return false;
2430     return true;
2431   }
2432 
2433   MachineBasicBlock::iterator B = MBB.begin();
2434   Iter = I;
2435   for (unsigned i = 0; i < 4; ++i) {
2436     // If we make it to the beginning of the block, it's safe to clobber
2437     // EFLAGS iff EFLAGS is not live-in.
2438     if (Iter == B)
2439       return !MBB.isLiveIn(X86::EFLAGS);
2440 
2441     --Iter;
2442     // Skip over DBG_VALUE.
2443     while (Iter != B && Iter->isDebugValue())
2444       --Iter;
2445 
2446     bool SawKill = false;
2447     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2448       MachineOperand &MO = Iter->getOperand(j);
2449       // A register mask may clobber EFLAGS, but we should still look for a
2450       // live EFLAGS def.
2451       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2452         SawKill = true;
2453       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2454         if (MO.isDef()) return MO.isDead();
2455         if (MO.isKill()) SawKill = true;
2456       }
2457     }
2458 
2459     if (SawKill)
2460       // This instruction kills EFLAGS and doesn't redefine it, so
2461       // there's no need to look further.
2462       return true;
2463   }
2464 
2465   // Conservative answer.
2466   return false;
2467 }
2468 
2469 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2470                                  MachineBasicBlock::iterator I,
2471                                  unsigned DestReg, unsigned SubIdx,
2472                                  const MachineInstr *Orig,
2473                                  const TargetRegisterInfo &TRI) const {
2474   bool ClobbersEFLAGS = false;
2475   for (const MachineOperand &MO : Orig->operands()) {
2476     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2477       ClobbersEFLAGS = true;
2478       break;
2479     }
2480   }
2481 
2482   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2483     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2484     // effects.
2485     int Value;
2486     switch (Orig->getOpcode()) {
2487     case X86::MOV32r0:  Value = 0; break;
2488     case X86::MOV32r1:  Value = 1; break;
2489     case X86::MOV32r_1: Value = -1; break;
2490     default:
2491       llvm_unreachable("Unexpected instruction!");
2492     }
2493 
2494     DebugLoc DL = Orig->getDebugLoc();
2495     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2496       .addImm(Value);
2497   } else {
2498     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2499     MBB.insert(I, MI);
2500   }
2501 
2502   MachineInstr *NewMI = std::prev(I);
2503   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2504 }
2505 
2506 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2507 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr *MI) const {
2508   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2509     MachineOperand &MO = MI->getOperand(i);
2510     if (MO.isReg() && MO.isDef() &&
2511         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2512       return true;
2513     }
2514   }
2515   return false;
2516 }
2517 
2518 /// Check whether the shift count for a machine operand is non-zero.
2519 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2520                                               unsigned ShiftAmtOperandIdx) {
2521   // The shift count is six bits with the REX.W prefix and five bits without.
2522   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2523   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2524   return Imm & ShiftCountMask;
2525 }
2526 
2527 /// Check whether the given shift count is appropriate
2528 /// can be represented by a LEA instruction.
2529 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2530   // Left shift instructions can be transformed into load-effective-address
2531   // instructions if we can encode them appropriately.
2532   // A LEA instruction utilizes a SIB byte to encode its scale factor.
2533   // The SIB.scale field is two bits wide which means that we can encode any
2534   // shift amount less than 4.
2535   return ShAmt < 4 && ShAmt > 0;
2536 }
2537 
2538 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2539                                   unsigned Opc, bool AllowSP,
2540                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
2541                                   MachineOperand &ImplicitOp) const {
2542   MachineFunction &MF = *MI->getParent()->getParent();
2543   const TargetRegisterClass *RC;
2544   if (AllowSP) {
2545     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2546   } else {
2547     RC = Opc != X86::LEA32r ?
2548       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2549   }
2550   unsigned SrcReg = Src.getReg();
2551 
2552   // For both LEA64 and LEA32 the register already has essentially the right
2553   // type (32-bit or 64-bit) we may just need to forbid SP.
2554   if (Opc != X86::LEA64_32r) {
2555     NewSrc = SrcReg;
2556     isKill = Src.isKill();
2557     isUndef = Src.isUndef();
2558 
2559     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2560         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2561       return false;
2562 
2563     return true;
2564   }
2565 
2566   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2567   // another we need to add 64-bit registers to the final MI.
2568   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2569     ImplicitOp = Src;
2570     ImplicitOp.setImplicit();
2571 
2572     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
2573     MachineBasicBlock::LivenessQueryResult LQR =
2574       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2575 
2576     switch (LQR) {
2577     case MachineBasicBlock::LQR_Unknown:
2578       // We can't give sane liveness flags to the instruction, abandon LEA
2579       // formation.
2580       return false;
2581     case MachineBasicBlock::LQR_Live:
2582       isKill = MI->killsRegister(SrcReg);
2583       isUndef = false;
2584       break;
2585     default:
2586       // The physreg itself is dead, so we have to use it as an <undef>.
2587       isKill = false;
2588       isUndef = true;
2589       break;
2590     }
2591   } else {
2592     // Virtual register of the wrong class, we have to create a temporary 64-bit
2593     // vreg to feed into the LEA.
2594     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2595     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2596             get(TargetOpcode::COPY))
2597       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2598         .addOperand(Src);
2599 
2600     // Which is obviously going to be dead after we're done with it.
2601     isKill = true;
2602     isUndef = false;
2603   }
2604 
2605   // We've set all the parameters without issue.
2606   return true;
2607 }
2608 
2609 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2610 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2611 /// truncating back down to a 16-bit subregister.
2612 MachineInstr *
2613 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2614                                            MachineFunction::iterator &MFI,
2615                                            MachineBasicBlock::iterator &MBBI,
2616                                            LiveVariables *LV) const {
2617   MachineInstr *MI = MBBI;
2618   unsigned Dest = MI->getOperand(0).getReg();
2619   unsigned Src = MI->getOperand(1).getReg();
2620   bool isDead = MI->getOperand(0).isDead();
2621   bool isKill = MI->getOperand(1).isKill();
2622 
2623   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2624   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2625   unsigned Opc, leaInReg;
2626   if (Subtarget.is64Bit()) {
2627     Opc = X86::LEA64_32r;
2628     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2629   } else {
2630     Opc = X86::LEA32r;
2631     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2632   }
2633 
2634   // Build and insert into an implicit UNDEF value. This is OK because
2635   // well be shifting and then extracting the lower 16-bits.
2636   // This has the potential to cause partial register stall. e.g.
2637   //   movw    (%rbp,%rcx,2), %dx
2638   //   leal    -65(%rdx), %esi
2639   // But testing has shown this *does* help performance in 64-bit mode (at
2640   // least on modern x86 machines).
2641   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2642   MachineInstr *InsMI =
2643     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2644     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2645     .addReg(Src, getKillRegState(isKill));
2646 
2647   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2648                                     get(Opc), leaOutReg);
2649   switch (MIOpc) {
2650   default: llvm_unreachable("Unreachable!");
2651   case X86::SHL16ri: {
2652     unsigned ShAmt = MI->getOperand(2).getImm();
2653     MIB.addReg(0).addImm(1 << ShAmt)
2654        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2655     break;
2656   }
2657   case X86::INC16r:
2658     addRegOffset(MIB, leaInReg, true, 1);
2659     break;
2660   case X86::DEC16r:
2661     addRegOffset(MIB, leaInReg, true, -1);
2662     break;
2663   case X86::ADD16ri:
2664   case X86::ADD16ri8:
2665   case X86::ADD16ri_DB:
2666   case X86::ADD16ri8_DB:
2667     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2668     break;
2669   case X86::ADD16rr:
2670   case X86::ADD16rr_DB: {
2671     unsigned Src2 = MI->getOperand(2).getReg();
2672     bool isKill2 = MI->getOperand(2).isKill();
2673     unsigned leaInReg2 = 0;
2674     MachineInstr *InsMI2 = nullptr;
2675     if (Src == Src2) {
2676       // ADD16rr %reg1028<kill>, %reg1028
2677       // just a single insert_subreg.
2678       addRegReg(MIB, leaInReg, true, leaInReg, false);
2679     } else {
2680       if (Subtarget.is64Bit())
2681         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2682       else
2683         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2684       // Build and insert into an implicit UNDEF value. This is OK because
2685       // well be shifting and then extracting the lower 16-bits.
2686       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2687       InsMI2 =
2688         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2689         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2690         .addReg(Src2, getKillRegState(isKill2));
2691       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2692     }
2693     if (LV && isKill2 && InsMI2)
2694       LV->replaceKillInstruction(Src2, MI, InsMI2);
2695     break;
2696   }
2697   }
2698 
2699   MachineInstr *NewMI = MIB;
2700   MachineInstr *ExtMI =
2701     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2702     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2703     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2704 
2705   if (LV) {
2706     // Update live variables
2707     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2708     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2709     if (isKill)
2710       LV->replaceKillInstruction(Src, MI, InsMI);
2711     if (isDead)
2712       LV->replaceKillInstruction(Dest, MI, ExtMI);
2713   }
2714 
2715   return ExtMI;
2716 }
2717 
2718 /// This method must be implemented by targets that
2719 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2720 /// may be able to convert a two-address instruction into a true
2721 /// three-address instruction on demand.  This allows the X86 target (for
2722 /// example) to convert ADD and SHL instructions into LEA instructions if they
2723 /// would require register copies due to two-addressness.
2724 ///
2725 /// This method returns a null pointer if the transformation cannot be
2726 /// performed, otherwise it returns the new instruction.
2727 ///
2728 MachineInstr *
2729 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2730                                     MachineBasicBlock::iterator &MBBI,
2731                                     LiveVariables *LV) const {
2732   MachineInstr *MI = MBBI;
2733 
2734   // The following opcodes also sets the condition code register(s). Only
2735   // convert them to equivalent lea if the condition code register def's
2736   // are dead!
2737   if (hasLiveCondCodeDef(MI))
2738     return nullptr;
2739 
2740   MachineFunction &MF = *MI->getParent()->getParent();
2741   // All instructions input are two-addr instructions.  Get the known operands.
2742   const MachineOperand &Dest = MI->getOperand(0);
2743   const MachineOperand &Src = MI->getOperand(1);
2744 
2745   MachineInstr *NewMI = nullptr;
2746   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2747   // we have better subtarget support, enable the 16-bit LEA generation here.
2748   // 16-bit LEA is also slow on Core2.
2749   bool DisableLEA16 = true;
2750   bool is64Bit = Subtarget.is64Bit();
2751 
2752   unsigned MIOpc = MI->getOpcode();
2753   switch (MIOpc) {
2754   default: return nullptr;
2755   case X86::SHL64ri: {
2756     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2757     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2758     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2759 
2760     // LEA can't handle RSP.
2761     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2762         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2763                                            &X86::GR64_NOSPRegClass))
2764       return nullptr;
2765 
2766     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2767       .addOperand(Dest)
2768       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2769     break;
2770   }
2771   case X86::SHL32ri: {
2772     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2773     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2774     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2775 
2776     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2777 
2778     // LEA can't handle ESP.
2779     bool isKill, isUndef;
2780     unsigned SrcReg;
2781     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2782     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2783                         SrcReg, isKill, isUndef, ImplicitOp))
2784       return nullptr;
2785 
2786     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2787       .addOperand(Dest)
2788       .addReg(0).addImm(1 << ShAmt)
2789       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2790       .addImm(0).addReg(0);
2791     if (ImplicitOp.getReg() != 0)
2792       MIB.addOperand(ImplicitOp);
2793     NewMI = MIB;
2794 
2795     break;
2796   }
2797   case X86::SHL16ri: {
2798     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2799     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2800     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2801 
2802     if (DisableLEA16)
2803       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2804     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2805       .addOperand(Dest)
2806       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2807     break;
2808   }
2809   case X86::INC64r:
2810   case X86::INC32r: {
2811     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2812     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2813       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2814     bool isKill, isUndef;
2815     unsigned SrcReg;
2816     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2817     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2818                         SrcReg, isKill, isUndef, ImplicitOp))
2819       return nullptr;
2820 
2821     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2822         .addOperand(Dest)
2823         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2824     if (ImplicitOp.getReg() != 0)
2825       MIB.addOperand(ImplicitOp);
2826 
2827     NewMI = addOffset(MIB, 1);
2828     break;
2829   }
2830   case X86::INC16r:
2831     if (DisableLEA16)
2832       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2833                      : nullptr;
2834     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2835     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2836                       .addOperand(Dest).addOperand(Src), 1);
2837     break;
2838   case X86::DEC64r:
2839   case X86::DEC32r: {
2840     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2841     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2842       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2843 
2844     bool isKill, isUndef;
2845     unsigned SrcReg;
2846     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2847     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2848                         SrcReg, isKill, isUndef, ImplicitOp))
2849       return nullptr;
2850 
2851     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2852         .addOperand(Dest)
2853         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2854     if (ImplicitOp.getReg() != 0)
2855       MIB.addOperand(ImplicitOp);
2856 
2857     NewMI = addOffset(MIB, -1);
2858 
2859     break;
2860   }
2861   case X86::DEC16r:
2862     if (DisableLEA16)
2863       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2864                      : nullptr;
2865     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2866     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2867                       .addOperand(Dest).addOperand(Src), -1);
2868     break;
2869   case X86::ADD64rr:
2870   case X86::ADD64rr_DB:
2871   case X86::ADD32rr:
2872   case X86::ADD32rr_DB: {
2873     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2874     unsigned Opc;
2875     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2876       Opc = X86::LEA64r;
2877     else
2878       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2879 
2880     bool isKill, isUndef;
2881     unsigned SrcReg;
2882     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2883     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2884                         SrcReg, isKill, isUndef, ImplicitOp))
2885       return nullptr;
2886 
2887     const MachineOperand &Src2 = MI->getOperand(2);
2888     bool isKill2, isUndef2;
2889     unsigned SrcReg2;
2890     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2891     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2892                         SrcReg2, isKill2, isUndef2, ImplicitOp2))
2893       return nullptr;
2894 
2895     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2896       .addOperand(Dest);
2897     if (ImplicitOp.getReg() != 0)
2898       MIB.addOperand(ImplicitOp);
2899     if (ImplicitOp2.getReg() != 0)
2900       MIB.addOperand(ImplicitOp2);
2901 
2902     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2903 
2904     // Preserve undefness of the operands.
2905     NewMI->getOperand(1).setIsUndef(isUndef);
2906     NewMI->getOperand(3).setIsUndef(isUndef2);
2907 
2908     if (LV && Src2.isKill())
2909       LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2910     break;
2911   }
2912   case X86::ADD16rr:
2913   case X86::ADD16rr_DB: {
2914     if (DisableLEA16)
2915       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2916                      : nullptr;
2917     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2918     unsigned Src2 = MI->getOperand(2).getReg();
2919     bool isKill2 = MI->getOperand(2).isKill();
2920     NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2921                       .addOperand(Dest),
2922                       Src.getReg(), Src.isKill(), Src2, isKill2);
2923 
2924     // Preserve undefness of the operands.
2925     bool isUndef = MI->getOperand(1).isUndef();
2926     bool isUndef2 = MI->getOperand(2).isUndef();
2927     NewMI->getOperand(1).setIsUndef(isUndef);
2928     NewMI->getOperand(3).setIsUndef(isUndef2);
2929 
2930     if (LV && isKill2)
2931       LV->replaceKillInstruction(Src2, MI, NewMI);
2932     break;
2933   }
2934   case X86::ADD64ri32:
2935   case X86::ADD64ri8:
2936   case X86::ADD64ri32_DB:
2937   case X86::ADD64ri8_DB:
2938     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2939     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2940                       .addOperand(Dest).addOperand(Src),
2941                       MI->getOperand(2).getImm());
2942     break;
2943   case X86::ADD32ri:
2944   case X86::ADD32ri8:
2945   case X86::ADD32ri_DB:
2946   case X86::ADD32ri8_DB: {
2947     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2948     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2949 
2950     bool isKill, isUndef;
2951     unsigned SrcReg;
2952     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2953     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2954                         SrcReg, isKill, isUndef, ImplicitOp))
2955       return nullptr;
2956 
2957     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2958         .addOperand(Dest)
2959         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2960     if (ImplicitOp.getReg() != 0)
2961       MIB.addOperand(ImplicitOp);
2962 
2963     NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2964     break;
2965   }
2966   case X86::ADD16ri:
2967   case X86::ADD16ri8:
2968   case X86::ADD16ri_DB:
2969   case X86::ADD16ri8_DB:
2970     if (DisableLEA16)
2971       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2972                      : nullptr;
2973     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2974     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2975                       .addOperand(Dest).addOperand(Src),
2976                       MI->getOperand(2).getImm());
2977     break;
2978   }
2979 
2980   if (!NewMI) return nullptr;
2981 
2982   if (LV) {  // Update live variables
2983     if (Src.isKill())
2984       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2985     if (Dest.isDead())
2986       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2987   }
2988 
2989   MFI->insert(MBBI, NewMI);          // Insert the new inst
2990   return NewMI;
2991 }
2992 
2993 /// Returns true if the given instruction opcode is FMA3.
2994 /// Otherwise, returns false.
2995 /// The second parameter is optional and is used as the second return from
2996 /// the function. It is set to true if the given instruction has FMA3 opcode
2997 /// that is used for lowering of scalar FMA intrinsics, and it is set to false
2998 /// otherwise.
2999 static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
3000   if (IsIntrinsic)
3001     *IsIntrinsic = false;
3002 
3003   switch (Opcode) {
3004     case X86::VFMADDSDr132r:      case X86::VFMADDSDr132m:
3005     case X86::VFMADDSSr132r:      case X86::VFMADDSSr132m:
3006     case X86::VFMSUBSDr132r:      case X86::VFMSUBSDr132m:
3007     case X86::VFMSUBSSr132r:      case X86::VFMSUBSSr132m:
3008     case X86::VFNMADDSDr132r:     case X86::VFNMADDSDr132m:
3009     case X86::VFNMADDSSr132r:     case X86::VFNMADDSSr132m:
3010     case X86::VFNMSUBSDr132r:     case X86::VFNMSUBSDr132m:
3011     case X86::VFNMSUBSSr132r:     case X86::VFNMSUBSSr132m:
3012 
3013     case X86::VFMADDSDr213r:      case X86::VFMADDSDr213m:
3014     case X86::VFMADDSSr213r:      case X86::VFMADDSSr213m:
3015     case X86::VFMSUBSDr213r:      case X86::VFMSUBSDr213m:
3016     case X86::VFMSUBSSr213r:      case X86::VFMSUBSSr213m:
3017     case X86::VFNMADDSDr213r:     case X86::VFNMADDSDr213m:
3018     case X86::VFNMADDSSr213r:     case X86::VFNMADDSSr213m:
3019     case X86::VFNMSUBSDr213r:     case X86::VFNMSUBSDr213m:
3020     case X86::VFNMSUBSSr213r:     case X86::VFNMSUBSSr213m:
3021 
3022     case X86::VFMADDSDr231r:      case X86::VFMADDSDr231m:
3023     case X86::VFMADDSSr231r:      case X86::VFMADDSSr231m:
3024     case X86::VFMSUBSDr231r:      case X86::VFMSUBSDr231m:
3025     case X86::VFMSUBSSr231r:      case X86::VFMSUBSSr231m:
3026     case X86::VFNMADDSDr231r:     case X86::VFNMADDSDr231m:
3027     case X86::VFNMADDSSr231r:     case X86::VFNMADDSSr231m:
3028     case X86::VFNMSUBSDr231r:     case X86::VFNMSUBSDr231m:
3029     case X86::VFNMSUBSSr231r:     case X86::VFNMSUBSSr231m:
3030 
3031     case X86::VFMADDSUBPDr132r:   case X86::VFMADDSUBPDr132m:
3032     case X86::VFMADDSUBPSr132r:   case X86::VFMADDSUBPSr132m:
3033     case X86::VFMSUBADDPDr132r:   case X86::VFMSUBADDPDr132m:
3034     case X86::VFMSUBADDPSr132r:   case X86::VFMSUBADDPSr132m:
3035     case X86::VFMADDSUBPDr132rY:  case X86::VFMADDSUBPDr132mY:
3036     case X86::VFMADDSUBPSr132rY:  case X86::VFMADDSUBPSr132mY:
3037     case X86::VFMSUBADDPDr132rY:  case X86::VFMSUBADDPDr132mY:
3038     case X86::VFMSUBADDPSr132rY:  case X86::VFMSUBADDPSr132mY:
3039 
3040     case X86::VFMADDPDr132r:      case X86::VFMADDPDr132m:
3041     case X86::VFMADDPSr132r:      case X86::VFMADDPSr132m:
3042     case X86::VFMSUBPDr132r:      case X86::VFMSUBPDr132m:
3043     case X86::VFMSUBPSr132r:      case X86::VFMSUBPSr132m:
3044     case X86::VFNMADDPDr132r:     case X86::VFNMADDPDr132m:
3045     case X86::VFNMADDPSr132r:     case X86::VFNMADDPSr132m:
3046     case X86::VFNMSUBPDr132r:     case X86::VFNMSUBPDr132m:
3047     case X86::VFNMSUBPSr132r:     case X86::VFNMSUBPSr132m:
3048     case X86::VFMADDPDr132rY:     case X86::VFMADDPDr132mY:
3049     case X86::VFMADDPSr132rY:     case X86::VFMADDPSr132mY:
3050     case X86::VFMSUBPDr132rY:     case X86::VFMSUBPDr132mY:
3051     case X86::VFMSUBPSr132rY:     case X86::VFMSUBPSr132mY:
3052     case X86::VFNMADDPDr132rY:    case X86::VFNMADDPDr132mY:
3053     case X86::VFNMADDPSr132rY:    case X86::VFNMADDPSr132mY:
3054     case X86::VFNMSUBPDr132rY:    case X86::VFNMSUBPDr132mY:
3055     case X86::VFNMSUBPSr132rY:    case X86::VFNMSUBPSr132mY:
3056 
3057     case X86::VFMADDSUBPDr213r:   case X86::VFMADDSUBPDr213m:
3058     case X86::VFMADDSUBPSr213r:   case X86::VFMADDSUBPSr213m:
3059     case X86::VFMSUBADDPDr213r:   case X86::VFMSUBADDPDr213m:
3060     case X86::VFMSUBADDPSr213r:   case X86::VFMSUBADDPSr213m:
3061     case X86::VFMADDSUBPDr213rY:  case X86::VFMADDSUBPDr213mY:
3062     case X86::VFMADDSUBPSr213rY:  case X86::VFMADDSUBPSr213mY:
3063     case X86::VFMSUBADDPDr213rY:  case X86::VFMSUBADDPDr213mY:
3064     case X86::VFMSUBADDPSr213rY:  case X86::VFMSUBADDPSr213mY:
3065 
3066     case X86::VFMADDPDr213r:      case X86::VFMADDPDr213m:
3067     case X86::VFMADDPSr213r:      case X86::VFMADDPSr213m:
3068     case X86::VFMSUBPDr213r:      case X86::VFMSUBPDr213m:
3069     case X86::VFMSUBPSr213r:      case X86::VFMSUBPSr213m:
3070     case X86::VFNMADDPDr213r:     case X86::VFNMADDPDr213m:
3071     case X86::VFNMADDPSr213r:     case X86::VFNMADDPSr213m:
3072     case X86::VFNMSUBPDr213r:     case X86::VFNMSUBPDr213m:
3073     case X86::VFNMSUBPSr213r:     case X86::VFNMSUBPSr213m:
3074     case X86::VFMADDPDr213rY:     case X86::VFMADDPDr213mY:
3075     case X86::VFMADDPSr213rY:     case X86::VFMADDPSr213mY:
3076     case X86::VFMSUBPDr213rY:     case X86::VFMSUBPDr213mY:
3077     case X86::VFMSUBPSr213rY:     case X86::VFMSUBPSr213mY:
3078     case X86::VFNMADDPDr213rY:    case X86::VFNMADDPDr213mY:
3079     case X86::VFNMADDPSr213rY:    case X86::VFNMADDPSr213mY:
3080     case X86::VFNMSUBPDr213rY:    case X86::VFNMSUBPDr213mY:
3081     case X86::VFNMSUBPSr213rY:    case X86::VFNMSUBPSr213mY:
3082 
3083     case X86::VFMADDSUBPDr231r:   case X86::VFMADDSUBPDr231m:
3084     case X86::VFMADDSUBPSr231r:   case X86::VFMADDSUBPSr231m:
3085     case X86::VFMSUBADDPDr231r:   case X86::VFMSUBADDPDr231m:
3086     case X86::VFMSUBADDPSr231r:   case X86::VFMSUBADDPSr231m:
3087     case X86::VFMADDSUBPDr231rY:  case X86::VFMADDSUBPDr231mY:
3088     case X86::VFMADDSUBPSr231rY:  case X86::VFMADDSUBPSr231mY:
3089     case X86::VFMSUBADDPDr231rY:  case X86::VFMSUBADDPDr231mY:
3090     case X86::VFMSUBADDPSr231rY:  case X86::VFMSUBADDPSr231mY:
3091 
3092     case X86::VFMADDPDr231r:      case X86::VFMADDPDr231m:
3093     case X86::VFMADDPSr231r:      case X86::VFMADDPSr231m:
3094     case X86::VFMSUBPDr231r:      case X86::VFMSUBPDr231m:
3095     case X86::VFMSUBPSr231r:      case X86::VFMSUBPSr231m:
3096     case X86::VFNMADDPDr231r:     case X86::VFNMADDPDr231m:
3097     case X86::VFNMADDPSr231r:     case X86::VFNMADDPSr231m:
3098     case X86::VFNMSUBPDr231r:     case X86::VFNMSUBPDr231m:
3099     case X86::VFNMSUBPSr231r:     case X86::VFNMSUBPSr231m:
3100     case X86::VFMADDPDr231rY:     case X86::VFMADDPDr231mY:
3101     case X86::VFMADDPSr231rY:     case X86::VFMADDPSr231mY:
3102     case X86::VFMSUBPDr231rY:     case X86::VFMSUBPDr231mY:
3103     case X86::VFMSUBPSr231rY:     case X86::VFMSUBPSr231mY:
3104     case X86::VFNMADDPDr231rY:    case X86::VFNMADDPDr231mY:
3105     case X86::VFNMADDPSr231rY:    case X86::VFNMADDPSr231mY:
3106     case X86::VFNMSUBPDr231rY:    case X86::VFNMSUBPDr231mY:
3107     case X86::VFNMSUBPSr231rY:    case X86::VFNMSUBPSr231mY:
3108       return true;
3109 
3110     case X86::VFMADDSDr132r_Int:  case X86::VFMADDSDr132m_Int:
3111     case X86::VFMADDSSr132r_Int:  case X86::VFMADDSSr132m_Int:
3112     case X86::VFMSUBSDr132r_Int:  case X86::VFMSUBSDr132m_Int:
3113     case X86::VFMSUBSSr132r_Int:  case X86::VFMSUBSSr132m_Int:
3114     case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int:
3115     case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int:
3116     case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int:
3117     case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int:
3118 
3119     case X86::VFMADDSDr213r_Int:  case X86::VFMADDSDr213m_Int:
3120     case X86::VFMADDSSr213r_Int:  case X86::VFMADDSSr213m_Int:
3121     case X86::VFMSUBSDr213r_Int:  case X86::VFMSUBSDr213m_Int:
3122     case X86::VFMSUBSSr213r_Int:  case X86::VFMSUBSSr213m_Int:
3123     case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int:
3124     case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int:
3125     case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int:
3126     case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int:
3127 
3128     case X86::VFMADDSDr231r_Int:  case X86::VFMADDSDr231m_Int:
3129     case X86::VFMADDSSr231r_Int:  case X86::VFMADDSSr231m_Int:
3130     case X86::VFMSUBSDr231r_Int:  case X86::VFMSUBSDr231m_Int:
3131     case X86::VFMSUBSSr231r_Int:  case X86::VFMSUBSSr231m_Int:
3132     case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int:
3133     case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
3134     case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
3135     case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
3136       if (IsIntrinsic)
3137         *IsIntrinsic = true;
3138       return true;
3139     default:
3140       return false;
3141   }
3142   llvm_unreachable("Opcode not handled by the switch");
3143 }
3144 
3145 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr *MI,
3146                                                    bool NewMI,
3147                                                    unsigned OpIdx1,
3148                                                    unsigned OpIdx2) const {
3149   switch (MI->getOpcode()) {
3150   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3151   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
3152   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
3153   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3154   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3155   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
3156     unsigned Opc;
3157     unsigned Size;
3158     switch (MI->getOpcode()) {
3159     default: llvm_unreachable("Unreachable!");
3160     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3161     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3162     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3163     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
3164     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3165     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
3166     }
3167     unsigned Amt = MI->getOperand(3).getImm();
3168     if (NewMI) {
3169       MachineFunction &MF = *MI->getParent()->getParent();
3170       MI = MF.CloneMachineInstr(MI);
3171       NewMI = false;
3172     }
3173     MI->setDesc(get(Opc));
3174     MI->getOperand(3).setImm(Size-Amt);
3175     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3176   }
3177   case X86::BLENDPDrri:
3178   case X86::BLENDPSrri:
3179   case X86::PBLENDWrri:
3180   case X86::VBLENDPDrri:
3181   case X86::VBLENDPSrri:
3182   case X86::VBLENDPDYrri:
3183   case X86::VBLENDPSYrri:
3184   case X86::VPBLENDDrri:
3185   case X86::VPBLENDWrri:
3186   case X86::VPBLENDDYrri:
3187   case X86::VPBLENDWYrri:{
3188     unsigned Mask;
3189     switch (MI->getOpcode()) {
3190     default: llvm_unreachable("Unreachable!");
3191     case X86::BLENDPDrri:    Mask = 0x03; break;
3192     case X86::BLENDPSrri:    Mask = 0x0F; break;
3193     case X86::PBLENDWrri:    Mask = 0xFF; break;
3194     case X86::VBLENDPDrri:   Mask = 0x03; break;
3195     case X86::VBLENDPSrri:   Mask = 0x0F; break;
3196     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
3197     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
3198     case X86::VPBLENDDrri:   Mask = 0x0F; break;
3199     case X86::VPBLENDWrri:   Mask = 0xFF; break;
3200     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
3201     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
3202     }
3203     // Only the least significant bits of Imm are used.
3204     unsigned Imm = MI->getOperand(3).getImm() & Mask;
3205     if (NewMI) {
3206       MachineFunction &MF = *MI->getParent()->getParent();
3207       MI = MF.CloneMachineInstr(MI);
3208       NewMI = false;
3209     }
3210     MI->getOperand(3).setImm(Mask ^ Imm);
3211     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3212   }
3213   case X86::PCLMULQDQrr:
3214   case X86::VPCLMULQDQrr:{
3215     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3216     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3217     unsigned Imm = MI->getOperand(3).getImm();
3218     unsigned Src1Hi = Imm & 0x01;
3219     unsigned Src2Hi = Imm & 0x10;
3220     if (NewMI) {
3221       MachineFunction &MF = *MI->getParent()->getParent();
3222       MI = MF.CloneMachineInstr(MI);
3223       NewMI = false;
3224     }
3225     MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3226     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3227   }
3228   case X86::CMPPDrri:
3229   case X86::CMPPSrri:
3230   case X86::VCMPPDrri:
3231   case X86::VCMPPSrri:
3232   case X86::VCMPPDYrri:
3233   case X86::VCMPPSYrri: {
3234     // Float comparison can be safely commuted for
3235     // Ordered/Unordered/Equal/NotEqual tests
3236     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3237     switch (Imm) {
3238     case 0x00: // EQUAL
3239     case 0x03: // UNORDERED
3240     case 0x04: // NOT EQUAL
3241     case 0x07: // ORDERED
3242       if (NewMI) {
3243         MachineFunction &MF = *MI->getParent()->getParent();
3244         MI = MF.CloneMachineInstr(MI);
3245         NewMI = false;
3246       }
3247       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3248     default:
3249       return nullptr;
3250     }
3251   }
3252   case X86::VPCOMBri: case X86::VPCOMUBri:
3253   case X86::VPCOMDri: case X86::VPCOMUDri:
3254   case X86::VPCOMQri: case X86::VPCOMUQri:
3255   case X86::VPCOMWri: case X86::VPCOMUWri: {
3256     // Flip comparison mode immediate (if necessary).
3257     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3258     switch (Imm) {
3259     case 0x00: Imm = 0x02; break; // LT -> GT
3260     case 0x01: Imm = 0x03; break; // LE -> GE
3261     case 0x02: Imm = 0x00; break; // GT -> LT
3262     case 0x03: Imm = 0x01; break; // GE -> LE
3263     case 0x04: // EQ
3264     case 0x05: // NE
3265     case 0x06: // FALSE
3266     case 0x07: // TRUE
3267     default:
3268       break;
3269     }
3270     if (NewMI) {
3271       MachineFunction &MF = *MI->getParent()->getParent();
3272       MI = MF.CloneMachineInstr(MI);
3273       NewMI = false;
3274     }
3275     MI->getOperand(3).setImm(Imm);
3276     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3277   }
3278   case X86::VPERM2F128rr:
3279   case X86::VPERM2I128rr: {
3280     // Flip permute source immediate.
3281     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3282     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
3283     unsigned Imm = MI->getOperand(3).getImm() & 0xFF;
3284     if (NewMI) {
3285       MachineFunction &MF = *MI->getParent()->getParent();
3286       MI = MF.CloneMachineInstr(MI);
3287       NewMI = false;
3288     }
3289     MI->getOperand(3).setImm(Imm ^ 0x22);
3290     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3291   }
3292   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
3293   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3294   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
3295   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3296   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3297   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
3298   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
3299   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3300   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3301   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
3302   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
3303   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3304   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
3305   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3306   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
3307   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3308     unsigned Opc;
3309     switch (MI->getOpcode()) {
3310     default: llvm_unreachable("Unreachable!");
3311     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
3312     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
3313     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
3314     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3315     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3316     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3317     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
3318     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
3319     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
3320     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3321     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3322     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
3323     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3324     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3325     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3326     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
3327     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
3328     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
3329     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
3330     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
3331     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
3332     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3333     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3334     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3335     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3336     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3337     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3338     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
3339     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
3340     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
3341     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
3342     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
3343     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
3344     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3345     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3346     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3347     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
3348     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
3349     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
3350     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3351     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3352     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3353     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
3354     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
3355     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
3356     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3357     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3358     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3359     }
3360     if (NewMI) {
3361       MachineFunction &MF = *MI->getParent()->getParent();
3362       MI = MF.CloneMachineInstr(MI);
3363       NewMI = false;
3364     }
3365     MI->setDesc(get(Opc));
3366     // Fallthrough intended.
3367   }
3368   default:
3369     if (isFMA3(MI->getOpcode())) {
3370       unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
3371       if (Opc == 0)
3372         return nullptr;
3373       if (NewMI) {
3374         MachineFunction &MF = *MI->getParent()->getParent();
3375         MI = MF.CloneMachineInstr(MI);
3376         NewMI = false;
3377       }
3378       MI->setDesc(get(Opc));
3379     }
3380     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3381   }
3382 }
3383 
3384 bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr *MI,
3385                                              unsigned &SrcOpIdx1,
3386                                              unsigned &SrcOpIdx2) const {
3387 
3388   unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3389 
3390   // Only the first RegOpsNum operands are commutable.
3391   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3392   // that the operand is not specified/fixed.
3393   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3394       (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3395     return false;
3396   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3397       (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3398     return false;
3399 
3400   // Look for two different register operands assumed to be commutable
3401   // regardless of the FMA opcode. The FMA opcode is adjusted later.
3402   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3403       SrcOpIdx2 == CommuteAnyOperandIndex) {
3404     unsigned CommutableOpIdx1 = SrcOpIdx1;
3405     unsigned CommutableOpIdx2 = SrcOpIdx2;
3406 
3407     // At least one of operands to be commuted is not specified and
3408     // this method is free to choose appropriate commutable operands.
3409     if (SrcOpIdx1 == SrcOpIdx2)
3410       // Both of operands are not fixed. By default set one of commutable
3411       // operands to the last register operand of the instruction.
3412       CommutableOpIdx2 = RegOpsNum;
3413     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3414       // Only one of operands is not fixed.
3415       CommutableOpIdx2 = SrcOpIdx1;
3416 
3417     // CommutableOpIdx2 is well defined now. Let's choose another commutable
3418     // operand and assign its index to CommutableOpIdx1.
3419     unsigned Op2Reg = MI->getOperand(CommutableOpIdx2).getReg();
3420     for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3421       // The commuted operands must have different registers.
3422       // Otherwise, the commute transformation does not change anything and
3423       // is useless then.
3424       if (Op2Reg != MI->getOperand(CommutableOpIdx1).getReg())
3425         break;
3426     }
3427 
3428     // No appropriate commutable operands were found.
3429     if (CommutableOpIdx1 == 0)
3430       return false;
3431 
3432     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3433     // to return those values.
3434     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3435                               CommutableOpIdx1, CommutableOpIdx2))
3436       return false;
3437   }
3438 
3439   // Check if we can adjust the opcode to preserve the semantics when
3440   // commute the register operands.
3441   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
3442 }
3443 
3444 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(MachineInstr *MI,
3445                                                       unsigned SrcOpIdx1,
3446                                                       unsigned SrcOpIdx2) const {
3447   unsigned Opc = MI->getOpcode();
3448 
3449   // Define the array that holds FMA opcodes in groups
3450   // of 3 opcodes(132, 213, 231) in each group.
3451   static const unsigned RegularOpcodeGroups[][3] = {
3452     { X86::VFMADDSSr132r,   X86::VFMADDSSr213r,   X86::VFMADDSSr231r  },
3453     { X86::VFMADDSDr132r,   X86::VFMADDSDr213r,   X86::VFMADDSDr231r  },
3454     { X86::VFMADDPSr132r,   X86::VFMADDPSr213r,   X86::VFMADDPSr231r  },
3455     { X86::VFMADDPDr132r,   X86::VFMADDPDr213r,   X86::VFMADDPDr231r  },
3456     { X86::VFMADDPSr132rY,  X86::VFMADDPSr213rY,  X86::VFMADDPSr231rY },
3457     { X86::VFMADDPDr132rY,  X86::VFMADDPDr213rY,  X86::VFMADDPDr231rY },
3458     { X86::VFMADDSSr132m,   X86::VFMADDSSr213m,   X86::VFMADDSSr231m  },
3459     { X86::VFMADDSDr132m,   X86::VFMADDSDr213m,   X86::VFMADDSDr231m  },
3460     { X86::VFMADDPSr132m,   X86::VFMADDPSr213m,   X86::VFMADDPSr231m  },
3461     { X86::VFMADDPDr132m,   X86::VFMADDPDr213m,   X86::VFMADDPDr231m  },
3462     { X86::VFMADDPSr132mY,  X86::VFMADDPSr213mY,  X86::VFMADDPSr231mY },
3463     { X86::VFMADDPDr132mY,  X86::VFMADDPDr213mY,  X86::VFMADDPDr231mY },
3464 
3465     { X86::VFMSUBSSr132r,   X86::VFMSUBSSr213r,   X86::VFMSUBSSr231r  },
3466     { X86::VFMSUBSDr132r,   X86::VFMSUBSDr213r,   X86::VFMSUBSDr231r  },
3467     { X86::VFMSUBPSr132r,   X86::VFMSUBPSr213r,   X86::VFMSUBPSr231r  },
3468     { X86::VFMSUBPDr132r,   X86::VFMSUBPDr213r,   X86::VFMSUBPDr231r  },
3469     { X86::VFMSUBPSr132rY,  X86::VFMSUBPSr213rY,  X86::VFMSUBPSr231rY },
3470     { X86::VFMSUBPDr132rY,  X86::VFMSUBPDr213rY,  X86::VFMSUBPDr231rY },
3471     { X86::VFMSUBSSr132m,   X86::VFMSUBSSr213m,   X86::VFMSUBSSr231m  },
3472     { X86::VFMSUBSDr132m,   X86::VFMSUBSDr213m,   X86::VFMSUBSDr231m  },
3473     { X86::VFMSUBPSr132m,   X86::VFMSUBPSr213m,   X86::VFMSUBPSr231m  },
3474     { X86::VFMSUBPDr132m,   X86::VFMSUBPDr213m,   X86::VFMSUBPDr231m  },
3475     { X86::VFMSUBPSr132mY,  X86::VFMSUBPSr213mY,  X86::VFMSUBPSr231mY },
3476     { X86::VFMSUBPDr132mY,  X86::VFMSUBPDr213mY,  X86::VFMSUBPDr231mY },
3477 
3478     { X86::VFNMADDSSr132r,  X86::VFNMADDSSr213r,  X86::VFNMADDSSr231r  },
3479     { X86::VFNMADDSDr132r,  X86::VFNMADDSDr213r,  X86::VFNMADDSDr231r  },
3480     { X86::VFNMADDPSr132r,  X86::VFNMADDPSr213r,  X86::VFNMADDPSr231r  },
3481     { X86::VFNMADDPDr132r,  X86::VFNMADDPDr213r,  X86::VFNMADDPDr231r  },
3482     { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
3483     { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
3484     { X86::VFNMADDSSr132m,  X86::VFNMADDSSr213m,  X86::VFNMADDSSr231m  },
3485     { X86::VFNMADDSDr132m,  X86::VFNMADDSDr213m,  X86::VFNMADDSDr231m  },
3486     { X86::VFNMADDPSr132m,  X86::VFNMADDPSr213m,  X86::VFNMADDPSr231m  },
3487     { X86::VFNMADDPDr132m,  X86::VFNMADDPDr213m,  X86::VFNMADDPDr231m  },
3488     { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
3489     { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
3490 
3491     { X86::VFNMSUBSSr132r,  X86::VFNMSUBSSr213r,  X86::VFNMSUBSSr231r  },
3492     { X86::VFNMSUBSDr132r,  X86::VFNMSUBSDr213r,  X86::VFNMSUBSDr231r  },
3493     { X86::VFNMSUBPSr132r,  X86::VFNMSUBPSr213r,  X86::VFNMSUBPSr231r  },
3494     { X86::VFNMSUBPDr132r,  X86::VFNMSUBPDr213r,  X86::VFNMSUBPDr231r  },
3495     { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
3496     { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
3497     { X86::VFNMSUBSSr132m,  X86::VFNMSUBSSr213m,  X86::VFNMSUBSSr231m  },
3498     { X86::VFNMSUBSDr132m,  X86::VFNMSUBSDr213m,  X86::VFNMSUBSDr231m  },
3499     { X86::VFNMSUBPSr132m,  X86::VFNMSUBPSr213m,  X86::VFNMSUBPSr231m  },
3500     { X86::VFNMSUBPDr132m,  X86::VFNMSUBPDr213m,  X86::VFNMSUBPDr231m  },
3501     { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
3502     { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
3503 
3504     { X86::VFMADDSUBPSr132r,  X86::VFMADDSUBPSr213r,  X86::VFMADDSUBPSr231r  },
3505     { X86::VFMADDSUBPDr132r,  X86::VFMADDSUBPDr213r,  X86::VFMADDSUBPDr231r  },
3506     { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
3507     { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
3508     { X86::VFMADDSUBPSr132m,  X86::VFMADDSUBPSr213m,  X86::VFMADDSUBPSr231m  },
3509     { X86::VFMADDSUBPDr132m,  X86::VFMADDSUBPDr213m,  X86::VFMADDSUBPDr231m  },
3510     { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
3511     { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
3512 
3513     { X86::VFMSUBADDPSr132r,  X86::VFMSUBADDPSr213r,  X86::VFMSUBADDPSr231r  },
3514     { X86::VFMSUBADDPDr132r,  X86::VFMSUBADDPDr213r,  X86::VFMSUBADDPDr231r  },
3515     { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
3516     { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
3517     { X86::VFMSUBADDPSr132m,  X86::VFMSUBADDPSr213m,  X86::VFMSUBADDPSr231m  },
3518     { X86::VFMSUBADDPDr132m,  X86::VFMSUBADDPDr213m,  X86::VFMSUBADDPDr231m  },
3519     { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
3520     { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
3521   };
3522 
3523   // Define the array that holds FMA*_Int opcodes in groups
3524   // of 3 opcodes(132, 213, 231) in each group.
3525   static const unsigned IntrinOpcodeGroups[][3] = {
3526     { X86::VFMADDSSr132r_Int,  X86::VFMADDSSr213r_Int,  X86::VFMADDSSr231r_Int },
3527     { X86::VFMADDSDr132r_Int,  X86::VFMADDSDr213r_Int,  X86::VFMADDSDr231r_Int },
3528     { X86::VFMADDSSr132m_Int,  X86::VFMADDSSr213m_Int,  X86::VFMADDSSr231m_Int },
3529     { X86::VFMADDSDr132m_Int,  X86::VFMADDSDr213m_Int,  X86::VFMADDSDr231m_Int },
3530 
3531     { X86::VFMSUBSSr132r_Int,  X86::VFMSUBSSr213r_Int,  X86::VFMSUBSSr231r_Int },
3532     { X86::VFMSUBSDr132r_Int,  X86::VFMSUBSDr213r_Int,  X86::VFMSUBSDr231r_Int },
3533     { X86::VFMSUBSSr132m_Int,  X86::VFMSUBSSr213m_Int,  X86::VFMSUBSSr231m_Int },
3534     { X86::VFMSUBSDr132m_Int,  X86::VFMSUBSDr213m_Int,  X86::VFMSUBSDr231m_Int },
3535 
3536     { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
3537     { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
3538     { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
3539     { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
3540 
3541     { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
3542     { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
3543     { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
3544     { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
3545   };
3546 
3547   const unsigned Form132Index = 0;
3548   const unsigned Form213Index = 1;
3549   const unsigned Form231Index = 2;
3550   const unsigned FormsNum = 3;
3551 
3552   bool IsIntrinOpcode;
3553   isFMA3(Opc, &IsIntrinOpcode);
3554 
3555   size_t GroupsNum;
3556   const unsigned (*OpcodeGroups)[3];
3557   if (IsIntrinOpcode) {
3558     GroupsNum = array_lengthof(IntrinOpcodeGroups);
3559     OpcodeGroups = IntrinOpcodeGroups;
3560   } else {
3561     GroupsNum = array_lengthof(RegularOpcodeGroups);
3562     OpcodeGroups = RegularOpcodeGroups;
3563   }
3564 
3565   const unsigned *FoundOpcodesGroup = nullptr;
3566   size_t FormIndex;
3567 
3568   // Look for the input opcode in the corresponding opcodes table.
3569   for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
3570          ++GroupIndex) {
3571     for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
3572       if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
3573         FoundOpcodesGroup = OpcodeGroups[GroupIndex];
3574         break;
3575       }
3576     }
3577   }
3578 
3579   // The input opcode does not match with any of the opcodes from the tables.
3580   // The unsupported FMA opcode must be added to one of the two opcode groups
3581   // defined above.
3582   assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
3583 
3584   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3585   if (SrcOpIdx1 > SrcOpIdx2)
3586     std::swap(SrcOpIdx1, SrcOpIdx2);
3587 
3588   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3589   // analysis. The commute optimization is legal only if all users of FMA*_Int
3590   // use only the lowest element of the FMA*_Int instruction. Such analysis are
3591   // not implemented yet. So, just return 0 in that case.
3592   // When such analysis are available this place will be the right place for
3593   // calling it.
3594   if (IsIntrinOpcode && SrcOpIdx1 == 1)
3595     return 0;
3596 
3597   unsigned Case;
3598   if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
3599     Case = 0;
3600   else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3601     Case = 1;
3602   else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3603     Case = 2;
3604   else
3605     return 0;
3606 
3607   // Define the FMA forms mapping array that helps to map input FMA form
3608   // to output FMA form to preserve the operation semantics after
3609   // commuting the operands.
3610   static const unsigned FormMapping[][3] = {
3611     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3612     // FMA132 A, C, b; ==> FMA231 C, A, b;
3613     // FMA213 B, A, c; ==> FMA213 A, B, c;
3614     // FMA231 C, A, b; ==> FMA132 A, C, b;
3615     { Form231Index, Form213Index, Form132Index },
3616     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3617     // FMA132 A, c, B; ==> FMA132 B, c, A;
3618     // FMA213 B, a, C; ==> FMA231 C, a, B;
3619     // FMA231 C, a, B; ==> FMA213 B, a, C;
3620     { Form132Index, Form231Index, Form213Index },
3621     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3622     // FMA132 a, C, B; ==> FMA213 a, B, C;
3623     // FMA213 b, A, C; ==> FMA132 b, C, A;
3624     // FMA231 c, A, B; ==> FMA231 c, B, A;
3625     { Form213Index, Form132Index, Form231Index }
3626   };
3627 
3628   // Everything is ready, just adjust the FMA opcode and return it.
3629   FormIndex = FormMapping[Case][FormIndex];
3630   return FoundOpcodesGroup[FormIndex];
3631 }
3632 
3633 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI,
3634                                          unsigned &SrcOpIdx1,
3635                                          unsigned &SrcOpIdx2) const {
3636   switch (MI->getOpcode()) {
3637     case X86::CMPPDrri:
3638     case X86::CMPPSrri:
3639     case X86::VCMPPDrri:
3640     case X86::VCMPPSrri:
3641     case X86::VCMPPDYrri:
3642     case X86::VCMPPSYrri: {
3643       // Float comparison can be safely commuted for
3644       // Ordered/Unordered/Equal/NotEqual tests
3645       unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3646       switch (Imm) {
3647         case 0x00: // EQUAL
3648         case 0x03: // UNORDERED
3649         case 0x04: // NOT EQUAL
3650         case 0x07: // ORDERED
3651           // The indices of the commutable operands are 1 and 2.
3652           // Assign them to the returned operand indices here.
3653           return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
3654       }
3655       return false;
3656     }
3657     default:
3658       if (isFMA3(MI->getOpcode()))
3659         return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3660       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3661   }
3662   return false;
3663 }
3664 
3665 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
3666   switch (BrOpc) {
3667   default: return X86::COND_INVALID;
3668   case X86::JE_1:  return X86::COND_E;
3669   case X86::JNE_1: return X86::COND_NE;
3670   case X86::JL_1:  return X86::COND_L;
3671   case X86::JLE_1: return X86::COND_LE;
3672   case X86::JG_1:  return X86::COND_G;
3673   case X86::JGE_1: return X86::COND_GE;
3674   case X86::JB_1:  return X86::COND_B;
3675   case X86::JBE_1: return X86::COND_BE;
3676   case X86::JA_1:  return X86::COND_A;
3677   case X86::JAE_1: return X86::COND_AE;
3678   case X86::JS_1:  return X86::COND_S;
3679   case X86::JNS_1: return X86::COND_NS;
3680   case X86::JP_1:  return X86::COND_P;
3681   case X86::JNP_1: return X86::COND_NP;
3682   case X86::JO_1:  return X86::COND_O;
3683   case X86::JNO_1: return X86::COND_NO;
3684   }
3685 }
3686 
3687 /// Return condition code of a SET opcode.
3688 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3689   switch (Opc) {
3690   default: return X86::COND_INVALID;
3691   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
3692   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3693   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
3694   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3695   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
3696   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
3697   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3698   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
3699   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3700   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3701   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3702   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3703   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3704   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
3705   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
3706   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
3707   }
3708 }
3709 
3710 /// Return condition code of a CMov opcode.
3711 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
3712   switch (Opc) {
3713   default: return X86::COND_INVALID;
3714   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
3715   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
3716     return X86::COND_A;
3717   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3718   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3719     return X86::COND_AE;
3720   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
3721   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
3722     return X86::COND_B;
3723   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3724   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3725     return X86::COND_BE;
3726   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
3727   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
3728     return X86::COND_E;
3729   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
3730   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
3731     return X86::COND_G;
3732   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3733   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3734     return X86::COND_GE;
3735   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
3736   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
3737     return X86::COND_L;
3738   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3739   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3740     return X86::COND_LE;
3741   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3742   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3743     return X86::COND_NE;
3744   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3745   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3746     return X86::COND_NO;
3747   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3748   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3749     return X86::COND_NP;
3750   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3751   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3752     return X86::COND_NS;
3753   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
3754   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
3755     return X86::COND_O;
3756   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
3757   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
3758     return X86::COND_P;
3759   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
3760   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
3761     return X86::COND_S;
3762   }
3763 }
3764 
3765 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3766   switch (CC) {
3767   default: llvm_unreachable("Illegal condition code!");
3768   case X86::COND_E:  return X86::JE_1;
3769   case X86::COND_NE: return X86::JNE_1;
3770   case X86::COND_L:  return X86::JL_1;
3771   case X86::COND_LE: return X86::JLE_1;
3772   case X86::COND_G:  return X86::JG_1;
3773   case X86::COND_GE: return X86::JGE_1;
3774   case X86::COND_B:  return X86::JB_1;
3775   case X86::COND_BE: return X86::JBE_1;
3776   case X86::COND_A:  return X86::JA_1;
3777   case X86::COND_AE: return X86::JAE_1;
3778   case X86::COND_S:  return X86::JS_1;
3779   case X86::COND_NS: return X86::JNS_1;
3780   case X86::COND_P:  return X86::JP_1;
3781   case X86::COND_NP: return X86::JNP_1;
3782   case X86::COND_O:  return X86::JO_1;
3783   case X86::COND_NO: return X86::JNO_1;
3784   }
3785 }
3786 
3787 /// Return the inverse of the specified condition,
3788 /// e.g. turning COND_E to COND_NE.
3789 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3790   switch (CC) {
3791   default: llvm_unreachable("Illegal condition code!");
3792   case X86::COND_E:  return X86::COND_NE;
3793   case X86::COND_NE: return X86::COND_E;
3794   case X86::COND_L:  return X86::COND_GE;
3795   case X86::COND_LE: return X86::COND_G;
3796   case X86::COND_G:  return X86::COND_LE;
3797   case X86::COND_GE: return X86::COND_L;
3798   case X86::COND_B:  return X86::COND_AE;
3799   case X86::COND_BE: return X86::COND_A;
3800   case X86::COND_A:  return X86::COND_BE;
3801   case X86::COND_AE: return X86::COND_B;
3802   case X86::COND_S:  return X86::COND_NS;
3803   case X86::COND_NS: return X86::COND_S;
3804   case X86::COND_P:  return X86::COND_NP;
3805   case X86::COND_NP: return X86::COND_P;
3806   case X86::COND_O:  return X86::COND_NO;
3807   case X86::COND_NO: return X86::COND_O;
3808   }
3809 }
3810 
3811 /// Assuming the flags are set by MI(a,b), return the condition code if we
3812 /// modify the instructions such that flags are set by MI(b,a).
3813 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3814   switch (CC) {
3815   default: return X86::COND_INVALID;
3816   case X86::COND_E:  return X86::COND_E;
3817   case X86::COND_NE: return X86::COND_NE;
3818   case X86::COND_L:  return X86::COND_G;
3819   case X86::COND_LE: return X86::COND_GE;
3820   case X86::COND_G:  return X86::COND_L;
3821   case X86::COND_GE: return X86::COND_LE;
3822   case X86::COND_B:  return X86::COND_A;
3823   case X86::COND_BE: return X86::COND_AE;
3824   case X86::COND_A:  return X86::COND_B;
3825   case X86::COND_AE: return X86::COND_BE;
3826   }
3827 }
3828 
3829 /// Return a set opcode for the given condition and
3830 /// whether it has memory operand.
3831 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
3832   static const uint16_t Opc[16][2] = {
3833     { X86::SETAr,  X86::SETAm  },
3834     { X86::SETAEr, X86::SETAEm },
3835     { X86::SETBr,  X86::SETBm  },
3836     { X86::SETBEr, X86::SETBEm },
3837     { X86::SETEr,  X86::SETEm  },
3838     { X86::SETGr,  X86::SETGm  },
3839     { X86::SETGEr, X86::SETGEm },
3840     { X86::SETLr,  X86::SETLm  },
3841     { X86::SETLEr, X86::SETLEm },
3842     { X86::SETNEr, X86::SETNEm },
3843     { X86::SETNOr, X86::SETNOm },
3844     { X86::SETNPr, X86::SETNPm },
3845     { X86::SETNSr, X86::SETNSm },
3846     { X86::SETOr,  X86::SETOm  },
3847     { X86::SETPr,  X86::SETPm  },
3848     { X86::SETSr,  X86::SETSm  }
3849   };
3850 
3851   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
3852   return Opc[CC][HasMemoryOperand ? 1 : 0];
3853 }
3854 
3855 /// Return a cmov opcode for the given condition,
3856 /// register size in bytes, and operand type.
3857 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3858                               bool HasMemoryOperand) {
3859   static const uint16_t Opc[32][3] = {
3860     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
3861     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3862     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
3863     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3864     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
3865     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
3866     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3867     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
3868     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3869     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3870     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3871     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3872     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3873     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
3874     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
3875     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
3876     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
3877     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3878     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
3879     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3880     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
3881     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
3882     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3883     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
3884     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3885     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3886     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3887     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3888     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3889     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
3890     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
3891     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
3892   };
3893 
3894   assert(CC < 16 && "Can only handle standard cond codes");
3895   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
3896   switch(RegBytes) {
3897   default: llvm_unreachable("Illegal register size!");
3898   case 2: return Opc[Idx][0];
3899   case 4: return Opc[Idx][1];
3900   case 8: return Opc[Idx][2];
3901   }
3902 }
3903 
3904 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
3905   if (!MI->isTerminator()) return false;
3906 
3907   // Conditional branch is a special case.
3908   if (MI->isBranch() && !MI->isBarrier())
3909     return true;
3910   if (!MI->isPredicable())
3911     return true;
3912   return !isPredicated(MI);
3913 }
3914 
3915 bool X86InstrInfo::AnalyzeBranchImpl(
3916     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3917     SmallVectorImpl<MachineOperand> &Cond,
3918     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3919 
3920   // Start from the bottom of the block and work up, examining the
3921   // terminator instructions.
3922   MachineBasicBlock::iterator I = MBB.end();
3923   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3924   while (I != MBB.begin()) {
3925     --I;
3926     if (I->isDebugValue())
3927       continue;
3928 
3929     // Working from the bottom, when we see a non-terminator instruction, we're
3930     // done.
3931     if (!isUnpredicatedTerminator(I))
3932       break;
3933 
3934     // A terminator that isn't a branch can't easily be handled by this
3935     // analysis.
3936     if (!I->isBranch())
3937       return true;
3938 
3939     // Handle unconditional branches.
3940     if (I->getOpcode() == X86::JMP_1) {
3941       UnCondBrIter = I;
3942 
3943       if (!AllowModify) {
3944         TBB = I->getOperand(0).getMBB();
3945         continue;
3946       }
3947 
3948       // If the block has any instructions after a JMP, delete them.
3949       while (std::next(I) != MBB.end())
3950         std::next(I)->eraseFromParent();
3951 
3952       Cond.clear();
3953       FBB = nullptr;
3954 
3955       // Delete the JMP if it's equivalent to a fall-through.
3956       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3957         TBB = nullptr;
3958         I->eraseFromParent();
3959         I = MBB.end();
3960         UnCondBrIter = MBB.end();
3961         continue;
3962       }
3963 
3964       // TBB is used to indicate the unconditional destination.
3965       TBB = I->getOperand(0).getMBB();
3966       continue;
3967     }
3968 
3969     // Handle conditional branches.
3970     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
3971     if (BranchCode == X86::COND_INVALID)
3972       return true;  // Can't handle indirect branch.
3973 
3974     // Working from the bottom, handle the first conditional branch.
3975     if (Cond.empty()) {
3976       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3977       if (AllowModify && UnCondBrIter != MBB.end() &&
3978           MBB.isLayoutSuccessor(TargetBB)) {
3979         // If we can modify the code and it ends in something like:
3980         //
3981         //     jCC L1
3982         //     jmp L2
3983         //   L1:
3984         //     ...
3985         //   L2:
3986         //
3987         // Then we can change this to:
3988         //
3989         //     jnCC L2
3990         //   L1:
3991         //     ...
3992         //   L2:
3993         //
3994         // Which is a bit more efficient.
3995         // We conditionally jump to the fall-through block.
3996         BranchCode = GetOppositeBranchCondition(BranchCode);
3997         unsigned JNCC = GetCondBranchFromCond(BranchCode);
3998         MachineBasicBlock::iterator OldInst = I;
3999 
4000         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
4001           .addMBB(UnCondBrIter->getOperand(0).getMBB());
4002         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
4003           .addMBB(TargetBB);
4004 
4005         OldInst->eraseFromParent();
4006         UnCondBrIter->eraseFromParent();
4007 
4008         // Restart the analysis.
4009         UnCondBrIter = MBB.end();
4010         I = MBB.end();
4011         continue;
4012       }
4013 
4014       FBB = TBB;
4015       TBB = I->getOperand(0).getMBB();
4016       Cond.push_back(MachineOperand::CreateImm(BranchCode));
4017       CondBranches.push_back(I);
4018       continue;
4019     }
4020 
4021     // Handle subsequent conditional branches. Only handle the case where all
4022     // conditional branches branch to the same destination and their condition
4023     // opcodes fit one of the special multi-branch idioms.
4024     assert(Cond.size() == 1);
4025     assert(TBB);
4026 
4027     // Only handle the case where all conditional branches branch to the same
4028     // destination.
4029     if (TBB != I->getOperand(0).getMBB())
4030       return true;
4031 
4032     // If the conditions are the same, we can leave them alone.
4033     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
4034     if (OldBranchCode == BranchCode)
4035       continue;
4036 
4037     // If they differ, see if they fit one of the known patterns. Theoretically,
4038     // we could handle more patterns here, but we shouldn't expect to see them
4039     // if instruction selection has done a reasonable job.
4040     if ((OldBranchCode == X86::COND_NP &&
4041          BranchCode == X86::COND_E) ||
4042         (OldBranchCode == X86::COND_E &&
4043          BranchCode == X86::COND_NP))
4044       BranchCode = X86::COND_NP_OR_E;
4045     else if ((OldBranchCode == X86::COND_P &&
4046               BranchCode == X86::COND_NE) ||
4047              (OldBranchCode == X86::COND_NE &&
4048               BranchCode == X86::COND_P))
4049       BranchCode = X86::COND_NE_OR_P;
4050     else
4051       return true;
4052 
4053     // Update the MachineOperand.
4054     Cond[0].setImm(BranchCode);
4055     CondBranches.push_back(I);
4056   }
4057 
4058   return false;
4059 }
4060 
4061 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
4062                                  MachineBasicBlock *&TBB,
4063                                  MachineBasicBlock *&FBB,
4064                                  SmallVectorImpl<MachineOperand> &Cond,
4065                                  bool AllowModify) const {
4066   SmallVector<MachineInstr *, 4> CondBranches;
4067   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4068 }
4069 
4070 bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB,
4071                                           MachineBranchPredicate &MBP,
4072                                           bool AllowModify) const {
4073   using namespace std::placeholders;
4074 
4075   SmallVector<MachineOperand, 4> Cond;
4076   SmallVector<MachineInstr *, 4> CondBranches;
4077   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4078                         AllowModify))
4079     return true;
4080 
4081   if (Cond.size() != 1)
4082     return true;
4083 
4084   assert(MBP.TrueDest && "expected!");
4085 
4086   if (!MBP.FalseDest)
4087     MBP.FalseDest = MBB.getNextNode();
4088 
4089   const TargetRegisterInfo *TRI = &getRegisterInfo();
4090 
4091   MachineInstr *ConditionDef = nullptr;
4092   bool SingleUseCondition = true;
4093 
4094   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4095     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4096       ConditionDef = &*I;
4097       break;
4098     }
4099 
4100     if (I->readsRegister(X86::EFLAGS, TRI))
4101       SingleUseCondition = false;
4102   }
4103 
4104   if (!ConditionDef)
4105     return true;
4106 
4107   if (SingleUseCondition) {
4108     for (auto *Succ : MBB.successors())
4109       if (Succ->isLiveIn(X86::EFLAGS))
4110         SingleUseCondition = false;
4111   }
4112 
4113   MBP.ConditionDef = ConditionDef;
4114   MBP.SingleUseCondition = SingleUseCondition;
4115 
4116   // Currently we only recognize the simple pattern:
4117   //
4118   //   test %reg, %reg
4119   //   je %label
4120   //
4121   const unsigned TestOpcode =
4122       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4123 
4124   if (ConditionDef->getOpcode() == TestOpcode &&
4125       ConditionDef->getNumOperands() == 3 &&
4126       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4127       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4128     MBP.LHS = ConditionDef->getOperand(0);
4129     MBP.RHS = MachineOperand::CreateImm(0);
4130     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4131                         ? MachineBranchPredicate::PRED_NE
4132                         : MachineBranchPredicate::PRED_EQ;
4133     return false;
4134   }
4135 
4136   return true;
4137 }
4138 
4139 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
4140   MachineBasicBlock::iterator I = MBB.end();
4141   unsigned Count = 0;
4142 
4143   while (I != MBB.begin()) {
4144     --I;
4145     if (I->isDebugValue())
4146       continue;
4147     if (I->getOpcode() != X86::JMP_1 &&
4148         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
4149       break;
4150     // Remove the branch.
4151     I->eraseFromParent();
4152     I = MBB.end();
4153     ++Count;
4154   }
4155 
4156   return Count;
4157 }
4158 
4159 unsigned
4160 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
4161                            MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
4162                            DebugLoc DL) const {
4163   // Shouldn't be a fall through.
4164   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
4165   assert((Cond.size() == 1 || Cond.size() == 0) &&
4166          "X86 branch conditions have one component!");
4167 
4168   if (Cond.empty()) {
4169     // Unconditional branch?
4170     assert(!FBB && "Unconditional branch with multiple successors!");
4171     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
4172     return 1;
4173   }
4174 
4175   // Conditional branch.
4176   unsigned Count = 0;
4177   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4178   switch (CC) {
4179   case X86::COND_NP_OR_E:
4180     // Synthesize NP_OR_E with two branches.
4181     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4182     ++Count;
4183     BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
4184     ++Count;
4185     break;
4186   case X86::COND_NE_OR_P:
4187     // Synthesize NE_OR_P with two branches.
4188     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
4189     ++Count;
4190     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
4191     ++Count;
4192     break;
4193   default: {
4194     unsigned Opc = GetCondBranchFromCond(CC);
4195     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
4196     ++Count;
4197   }
4198   }
4199   if (FBB) {
4200     // Two-way Conditional branch. Insert the second branch.
4201     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
4202     ++Count;
4203   }
4204   return Count;
4205 }
4206 
4207 bool X86InstrInfo::
4208 canInsertSelect(const MachineBasicBlock &MBB,
4209                 ArrayRef<MachineOperand> Cond,
4210                 unsigned TrueReg, unsigned FalseReg,
4211                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4212   // Not all subtargets have cmov instructions.
4213   if (!Subtarget.hasCMov())
4214     return false;
4215   if (Cond.size() != 1)
4216     return false;
4217   // We cannot do the composite conditions, at least not in SSA form.
4218   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4219     return false;
4220 
4221   // Check register classes.
4222   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4223   const TargetRegisterClass *RC =
4224     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4225   if (!RC)
4226     return false;
4227 
4228   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4229   if (X86::GR16RegClass.hasSubClassEq(RC) ||
4230       X86::GR32RegClass.hasSubClassEq(RC) ||
4231       X86::GR64RegClass.hasSubClassEq(RC)) {
4232     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4233     // Bridge. Probably Ivy Bridge as well.
4234     CondCycles = 2;
4235     TrueCycles = 2;
4236     FalseCycles = 2;
4237     return true;
4238   }
4239 
4240   // Can't do vectors.
4241   return false;
4242 }
4243 
4244 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4245                                 MachineBasicBlock::iterator I, DebugLoc DL,
4246                                 unsigned DstReg, ArrayRef<MachineOperand> Cond,
4247                                 unsigned TrueReg, unsigned FalseReg) const {
4248    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4249    assert(Cond.size() == 1 && "Invalid Cond array");
4250    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4251                                   MRI.getRegClass(DstReg)->getSize(),
4252                                   false/*HasMemoryOperand*/);
4253    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
4254 }
4255 
4256 /// Test if the given register is a physical h register.
4257 static bool isHReg(unsigned Reg) {
4258   return X86::GR8_ABCD_HRegClass.contains(Reg);
4259 }
4260 
4261 // Try and copy between VR128/VR64 and GR64 registers.
4262 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
4263                                         const X86Subtarget &Subtarget) {
4264 
4265   // SrcReg(VR128) -> DestReg(GR64)
4266   // SrcReg(VR64)  -> DestReg(GR64)
4267   // SrcReg(GR64)  -> DestReg(VR128)
4268   // SrcReg(GR64)  -> DestReg(VR64)
4269 
4270   bool HasAVX = Subtarget.hasAVX();
4271   bool HasAVX512 = Subtarget.hasAVX512();
4272   if (X86::GR64RegClass.contains(DestReg)) {
4273     if (X86::VR128XRegClass.contains(SrcReg))
4274       // Copy from a VR128 register to a GR64 register.
4275       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
4276                                                X86::MOVPQIto64rr);
4277     if (X86::VR64RegClass.contains(SrcReg))
4278       // Copy from a VR64 register to a GR64 register.
4279       return X86::MMX_MOVD64from64rr;
4280   } else if (X86::GR64RegClass.contains(SrcReg)) {
4281     // Copy from a GR64 register to a VR128 register.
4282     if (X86::VR128XRegClass.contains(DestReg))
4283       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
4284                                                X86::MOV64toPQIrr);
4285     // Copy from a GR64 register to a VR64 register.
4286     if (X86::VR64RegClass.contains(DestReg))
4287       return X86::MMX_MOVD64to64rr;
4288   }
4289 
4290   // SrcReg(FR32) -> DestReg(GR32)
4291   // SrcReg(GR32) -> DestReg(FR32)
4292 
4293   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
4294     // Copy from a FR32 register to a GR32 register.
4295     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
4296 
4297   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4298     // Copy from a GR32 register to a FR32 register.
4299     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
4300   return 0;
4301 }
4302 
4303 static bool MaskRegClassContains(unsigned Reg) {
4304   return X86::VK8RegClass.contains(Reg) ||
4305          X86::VK16RegClass.contains(Reg) ||
4306          X86::VK32RegClass.contains(Reg) ||
4307          X86::VK64RegClass.contains(Reg) ||
4308          X86::VK1RegClass.contains(Reg);
4309 }
4310 
4311 static bool GRRegClassContains(unsigned Reg) {
4312   return X86::GR64RegClass.contains(Reg) ||
4313          X86::GR32RegClass.contains(Reg) ||
4314          X86::GR16RegClass.contains(Reg) ||
4315          X86::GR8RegClass.contains(Reg);
4316 }
4317 static
4318 unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4319   if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
4320     DestReg = getX86SubSuperRegister(DestReg, 32);
4321     return X86::KMOVBrk;
4322   }
4323   if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
4324     SrcReg = getX86SubSuperRegister(SrcReg, 32);
4325     return X86::KMOVBkr;
4326   }
4327   return 0;
4328 }
4329 
4330 static
4331 unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4332   if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4333     return X86::KMOVQkk;
4334   if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4335     return X86::KMOVDrk;
4336   if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4337     return X86::KMOVQrk;
4338   if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4339     return X86::KMOVDkr;
4340   if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4341     return X86::KMOVQkr;
4342   return 0;
4343 }
4344 
4345 static
4346 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4347                                   const X86Subtarget &Subtarget)
4348 {
4349   if (Subtarget.hasDQI())
4350     if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4351       return Opc;
4352   if (Subtarget.hasBWI())
4353     if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4354       return Opc;
4355   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
4356       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
4357       X86::VR512RegClass.contains(DestReg, SrcReg)) {
4358      DestReg = get512BitSuperRegister(DestReg);
4359      SrcReg = get512BitSuperRegister(SrcReg);
4360      return X86::VMOVAPSZrr;
4361   }
4362   if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
4363     return X86::KMOVWkk;
4364   if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
4365     SrcReg = getX86SubSuperRegister(SrcReg, 32);
4366     return X86::KMOVWkr;
4367   }
4368   if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
4369     DestReg = getX86SubSuperRegister(DestReg, 32);
4370     return X86::KMOVWrk;
4371   }
4372   return 0;
4373 }
4374 
4375 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4376                                MachineBasicBlock::iterator MI, DebugLoc DL,
4377                                unsigned DestReg, unsigned SrcReg,
4378                                bool KillSrc) const {
4379   // First deal with the normal symmetric copies.
4380   bool HasAVX = Subtarget.hasAVX();
4381   bool HasAVX512 = Subtarget.hasAVX512();
4382   unsigned Opc = 0;
4383   if (X86::GR64RegClass.contains(DestReg, SrcReg))
4384     Opc = X86::MOV64rr;
4385   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4386     Opc = X86::MOV32rr;
4387   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4388     Opc = X86::MOV16rr;
4389   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4390     // Copying to or from a physical H register on x86-64 requires a NOREX
4391     // move.  Otherwise use a normal move.
4392     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
4393         Subtarget.is64Bit()) {
4394       Opc = X86::MOV8rr_NOREX;
4395       // Both operands must be encodable without an REX prefix.
4396       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4397              "8-bit H register can not be copied outside GR8_NOREX");
4398     } else
4399       Opc = X86::MOV8rr;
4400   }
4401   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4402     Opc = X86::MMX_MOVQ64rr;
4403   else if (HasAVX512)
4404     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
4405   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
4406     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4407   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4408     Opc = X86::VMOVAPSYrr;
4409   if (!Opc)
4410     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4411 
4412   if (Opc) {
4413     BuildMI(MBB, MI, DL, get(Opc), DestReg)
4414       .addReg(SrcReg, getKillRegState(KillSrc));
4415     return;
4416   }
4417 
4418   bool FromEFLAGS = SrcReg == X86::EFLAGS;
4419   bool ToEFLAGS = DestReg == X86::EFLAGS;
4420   int Reg = FromEFLAGS ? DestReg : SrcReg;
4421   bool is32 = X86::GR32RegClass.contains(Reg);
4422   bool is64 = X86::GR64RegClass.contains(Reg);
4423 
4424   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
4425     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4426     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4427     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4428     int Pop = is64 ? X86::POP64r : X86::POP32r;
4429     int PopF = is64 ? X86::POPF64 : X86::POPF32;
4430     int AX = is64 ? X86::RAX : X86::EAX;
4431 
4432     if (!Subtarget.hasLAHFSAHF()) {
4433       assert(Subtarget.is64Bit() &&
4434              "Not having LAHF/SAHF only happens on 64-bit.");
4435       // Moving EFLAGS to / from another register requires a push and a pop.
4436       // Notice that we have to adjust the stack if we don't want to clobber the
4437       // first frame index. See X86FrameLowering.cpp - usesTheStack.
4438       if (FromEFLAGS) {
4439         BuildMI(MBB, MI, DL, get(PushF));
4440         BuildMI(MBB, MI, DL, get(Pop), DestReg);
4441       }
4442       if (ToEFLAGS) {
4443         BuildMI(MBB, MI, DL, get(Push))
4444             .addReg(SrcReg, getKillRegState(KillSrc));
4445         BuildMI(MBB, MI, DL, get(PopF));
4446       }
4447       return;
4448     }
4449 
4450     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4451     // inefficient. Instead:
4452     //   - Save the overflow flag OF into AL using SETO, and restore it using a
4453     //     signed 8-bit addition of AL and INT8_MAX.
4454     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4455     //     using LAHF/SAHF.
4456     //   - When RAX/EAX is live and isn't the destination register, make sure it
4457     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4458     //     the flags.
4459     // This approach is ~2.25x faster than using PUSHF/POPF.
4460     //
4461     // This is still somewhat inefficient because we don't know which flags are
4462     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4463     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4464     //
4465     // PUSHF/POPF is also potentially incorrect because it affects other flags
4466     // such as TF/IF/DF, which LLVM doesn't model.
4467     //
4468     // Notice that we have to adjust the stack if we don't want to clobber the
4469     // first frame index.
4470     // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
4471 
4472 
4473     bool AXDead = (Reg == AX) ||
4474                   (MachineBasicBlock::LQR_Dead ==
4475                    MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI));
4476     if (!AXDead) {
4477       // FIXME: If computeRegisterLiveness() reported LQR_Unknown then AX may
4478       // actually be dead. This is not a problem for correctness as we are just
4479       // (unnecessarily) saving+restoring a dead register. However the
4480       // MachineVerifier expects operands that read from dead registers
4481       // to be marked with the "undef" flag.
4482       // An example of this can be found in
4483       // test/CodeGen/X86/peephole-na-phys-copy-folding.ll and
4484       // test/CodeGen/X86/cmpxchg-clobber-flags.ll when using
4485       // -verify-machineinstrs.
4486       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
4487     }
4488     if (FromEFLAGS) {
4489       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4490       BuildMI(MBB, MI, DL, get(X86::LAHF));
4491       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
4492     }
4493     if (ToEFLAGS) {
4494       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4495       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4496           .addReg(X86::AL)
4497           .addImm(INT8_MAX);
4498       BuildMI(MBB, MI, DL, get(X86::SAHF));
4499     }
4500     if (!AXDead)
4501       BuildMI(MBB, MI, DL, get(Pop), AX);
4502     return;
4503   }
4504 
4505   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4506                << " to " << RI.getName(DestReg) << '\n');
4507   llvm_unreachable("Cannot emit physreg copy instruction");
4508 }
4509 
4510 static unsigned getLoadStoreRegOpcode(unsigned Reg,
4511                                       const TargetRegisterClass *RC,
4512                                       bool isStackAligned,
4513                                       const X86Subtarget &STI,
4514                                       bool load) {
4515   if (STI.hasAVX512()) {
4516     if (X86::VK8RegClass.hasSubClassEq(RC)  ||
4517       X86::VK16RegClass.hasSubClassEq(RC))
4518       return load ? X86::KMOVWkm : X86::KMOVWmk;
4519     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
4520       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
4521     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
4522       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
4523     if (X86::VR512RegClass.hasSubClassEq(RC))
4524       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4525   }
4526 
4527   bool HasAVX = STI.hasAVX();
4528   switch (RC->getSize()) {
4529   default:
4530     llvm_unreachable("Unknown spill size");
4531   case 1:
4532     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
4533     if (STI.is64Bit())
4534       // Copying to or from a physical H register on x86-64 requires a NOREX
4535       // move.  Otherwise use a normal move.
4536       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4537         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4538     return load ? X86::MOV8rm : X86::MOV8mr;
4539   case 2:
4540     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4541     return load ? X86::MOV16rm : X86::MOV16mr;
4542   case 4:
4543     if (X86::GR32RegClass.hasSubClassEq(RC))
4544       return load ? X86::MOV32rm : X86::MOV32mr;
4545     if (X86::FR32RegClass.hasSubClassEq(RC))
4546       return load ?
4547         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4548         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
4549     if (X86::RFP32RegClass.hasSubClassEq(RC))
4550       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4551     llvm_unreachable("Unknown 4-byte regclass");
4552   case 8:
4553     if (X86::GR64RegClass.hasSubClassEq(RC))
4554       return load ? X86::MOV64rm : X86::MOV64mr;
4555     if (X86::FR64RegClass.hasSubClassEq(RC))
4556       return load ?
4557         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4558         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
4559     if (X86::VR64RegClass.hasSubClassEq(RC))
4560       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4561     if (X86::RFP64RegClass.hasSubClassEq(RC))
4562       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4563     llvm_unreachable("Unknown 8-byte regclass");
4564   case 10:
4565     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
4566     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
4567   case 16: {
4568     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4569             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
4570     // If stack is realigned we can use aligned stores.
4571     if (isStackAligned)
4572       return load ?
4573         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
4574         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4575     else
4576       return load ?
4577         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
4578         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4579   }
4580   case 32:
4581     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4582             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
4583     // If stack is realigned we can use aligned stores.
4584     if (isStackAligned)
4585       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4586     else
4587       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
4588   case 64:
4589     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4590     if (isStackAligned)
4591       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4592     else
4593       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4594   }
4595 }
4596 
4597 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
4598                                          unsigned &Offset,
4599                                          const TargetRegisterInfo *TRI) const {
4600   const MCInstrDesc &Desc = MemOp->getDesc();
4601   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags, MemOp->getOpcode());
4602   if (MemRefBegin < 0)
4603     return false;
4604 
4605   MemRefBegin += X86II::getOperandBias(Desc);
4606 
4607   BaseReg = MemOp->getOperand(MemRefBegin + X86::AddrBaseReg).getReg();
4608   if (MemOp->getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4609     return false;
4610 
4611   if (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
4612       X86::NoRegister)
4613     return false;
4614 
4615   const MachineOperand &DispMO = MemOp->getOperand(MemRefBegin + X86::AddrDisp);
4616 
4617   // Displacement can be symbolic
4618   if (!DispMO.isImm())
4619     return false;
4620 
4621   Offset = DispMO.getImm();
4622 
4623   return (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4624           X86::NoRegister);
4625 }
4626 
4627 static unsigned getStoreRegOpcode(unsigned SrcReg,
4628                                   const TargetRegisterClass *RC,
4629                                   bool isStackAligned,
4630                                   const X86Subtarget &STI) {
4631   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
4632 }
4633 
4634 
4635 static unsigned getLoadRegOpcode(unsigned DestReg,
4636                                  const TargetRegisterClass *RC,
4637                                  bool isStackAligned,
4638                                  const X86Subtarget &STI) {
4639   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
4640 }
4641 
4642 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4643                                        MachineBasicBlock::iterator MI,
4644                                        unsigned SrcReg, bool isKill, int FrameIdx,
4645                                        const TargetRegisterClass *RC,
4646                                        const TargetRegisterInfo *TRI) const {
4647   const MachineFunction &MF = *MBB.getParent();
4648   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4649          "Stack slot too small for store");
4650   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4651   bool isAligned =
4652       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4653       RI.canRealignStack(MF);
4654   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4655   DebugLoc DL = MBB.findDebugLoc(MI);
4656   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
4657     .addReg(SrcReg, getKillRegState(isKill));
4658 }
4659 
4660 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4661                                   bool isKill,
4662                                   SmallVectorImpl<MachineOperand> &Addr,
4663                                   const TargetRegisterClass *RC,
4664                                   MachineInstr::mmo_iterator MMOBegin,
4665                                   MachineInstr::mmo_iterator MMOEnd,
4666                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
4667   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4668   bool isAligned = MMOBegin != MMOEnd &&
4669                    (*MMOBegin)->getAlignment() >= Alignment;
4670   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4671   DebugLoc DL;
4672   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
4673   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4674     MIB.addOperand(Addr[i]);
4675   MIB.addReg(SrcReg, getKillRegState(isKill));
4676   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4677   NewMIs.push_back(MIB);
4678 }
4679 
4680 
4681 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4682                                         MachineBasicBlock::iterator MI,
4683                                         unsigned DestReg, int FrameIdx,
4684                                         const TargetRegisterClass *RC,
4685                                         const TargetRegisterInfo *TRI) const {
4686   const MachineFunction &MF = *MBB.getParent();
4687   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4688   bool isAligned =
4689       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4690       RI.canRealignStack(MF);
4691   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4692   DebugLoc DL = MBB.findDebugLoc(MI);
4693   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
4694 }
4695 
4696 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
4697                                  SmallVectorImpl<MachineOperand> &Addr,
4698                                  const TargetRegisterClass *RC,
4699                                  MachineInstr::mmo_iterator MMOBegin,
4700                                  MachineInstr::mmo_iterator MMOEnd,
4701                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
4702   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4703   bool isAligned = MMOBegin != MMOEnd &&
4704                    (*MMOBegin)->getAlignment() >= Alignment;
4705   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4706   DebugLoc DL;
4707   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
4708   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4709     MIB.addOperand(Addr[i]);
4710   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4711   NewMIs.push_back(MIB);
4712 }
4713 
4714 bool X86InstrInfo::
4715 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
4716                int &CmpMask, int &CmpValue) const {
4717   switch (MI->getOpcode()) {
4718   default: break;
4719   case X86::CMP64ri32:
4720   case X86::CMP64ri8:
4721   case X86::CMP32ri:
4722   case X86::CMP32ri8:
4723   case X86::CMP16ri:
4724   case X86::CMP16ri8:
4725   case X86::CMP8ri:
4726     SrcReg = MI->getOperand(0).getReg();
4727     SrcReg2 = 0;
4728     CmpMask = ~0;
4729     CmpValue = MI->getOperand(1).getImm();
4730     return true;
4731   // A SUB can be used to perform comparison.
4732   case X86::SUB64rm:
4733   case X86::SUB32rm:
4734   case X86::SUB16rm:
4735   case X86::SUB8rm:
4736     SrcReg = MI->getOperand(1).getReg();
4737     SrcReg2 = 0;
4738     CmpMask = ~0;
4739     CmpValue = 0;
4740     return true;
4741   case X86::SUB64rr:
4742   case X86::SUB32rr:
4743   case X86::SUB16rr:
4744   case X86::SUB8rr:
4745     SrcReg = MI->getOperand(1).getReg();
4746     SrcReg2 = MI->getOperand(2).getReg();
4747     CmpMask = ~0;
4748     CmpValue = 0;
4749     return true;
4750   case X86::SUB64ri32:
4751   case X86::SUB64ri8:
4752   case X86::SUB32ri:
4753   case X86::SUB32ri8:
4754   case X86::SUB16ri:
4755   case X86::SUB16ri8:
4756   case X86::SUB8ri:
4757     SrcReg = MI->getOperand(1).getReg();
4758     SrcReg2 = 0;
4759     CmpMask = ~0;
4760     CmpValue = MI->getOperand(2).getImm();
4761     return true;
4762   case X86::CMP64rr:
4763   case X86::CMP32rr:
4764   case X86::CMP16rr:
4765   case X86::CMP8rr:
4766     SrcReg = MI->getOperand(0).getReg();
4767     SrcReg2 = MI->getOperand(1).getReg();
4768     CmpMask = ~0;
4769     CmpValue = 0;
4770     return true;
4771   case X86::TEST8rr:
4772   case X86::TEST16rr:
4773   case X86::TEST32rr:
4774   case X86::TEST64rr:
4775     SrcReg = MI->getOperand(0).getReg();
4776     if (MI->getOperand(1).getReg() != SrcReg) return false;
4777     // Compare against zero.
4778     SrcReg2 = 0;
4779     CmpMask = ~0;
4780     CmpValue = 0;
4781     return true;
4782   }
4783   return false;
4784 }
4785 
4786 /// Check whether the first instruction, whose only
4787 /// purpose is to update flags, can be made redundant.
4788 /// CMPrr can be made redundant by SUBrr if the operands are the same.
4789 /// This function can be extended later on.
4790 /// SrcReg, SrcRegs: register operands for FlagI.
4791 /// ImmValue: immediate for FlagI if it takes an immediate.
4792 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4793                                         unsigned SrcReg2, int ImmValue,
4794                                         MachineInstr *OI) {
4795   if (((FlagI->getOpcode() == X86::CMP64rr &&
4796         OI->getOpcode() == X86::SUB64rr) ||
4797        (FlagI->getOpcode() == X86::CMP32rr &&
4798         OI->getOpcode() == X86::SUB32rr)||
4799        (FlagI->getOpcode() == X86::CMP16rr &&
4800         OI->getOpcode() == X86::SUB16rr)||
4801        (FlagI->getOpcode() == X86::CMP8rr &&
4802         OI->getOpcode() == X86::SUB8rr)) &&
4803       ((OI->getOperand(1).getReg() == SrcReg &&
4804         OI->getOperand(2).getReg() == SrcReg2) ||
4805        (OI->getOperand(1).getReg() == SrcReg2 &&
4806         OI->getOperand(2).getReg() == SrcReg)))
4807     return true;
4808 
4809   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4810         OI->getOpcode() == X86::SUB64ri32) ||
4811        (FlagI->getOpcode() == X86::CMP64ri8 &&
4812         OI->getOpcode() == X86::SUB64ri8) ||
4813        (FlagI->getOpcode() == X86::CMP32ri &&
4814         OI->getOpcode() == X86::SUB32ri) ||
4815        (FlagI->getOpcode() == X86::CMP32ri8 &&
4816         OI->getOpcode() == X86::SUB32ri8) ||
4817        (FlagI->getOpcode() == X86::CMP16ri &&
4818         OI->getOpcode() == X86::SUB16ri) ||
4819        (FlagI->getOpcode() == X86::CMP16ri8 &&
4820         OI->getOpcode() == X86::SUB16ri8) ||
4821        (FlagI->getOpcode() == X86::CMP8ri &&
4822         OI->getOpcode() == X86::SUB8ri)) &&
4823       OI->getOperand(1).getReg() == SrcReg &&
4824       OI->getOperand(2).getImm() == ImmValue)
4825     return true;
4826   return false;
4827 }
4828 
4829 /// Check whether the definition can be converted
4830 /// to remove a comparison against zero.
4831 inline static bool isDefConvertible(MachineInstr *MI) {
4832   switch (MI->getOpcode()) {
4833   default: return false;
4834 
4835   // The shift instructions only modify ZF if their shift count is non-zero.
4836   // N.B.: The processor truncates the shift count depending on the encoding.
4837   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
4838   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
4839      return getTruncatedShiftCount(MI, 2) != 0;
4840 
4841   // Some left shift instructions can be turned into LEA instructions but only
4842   // if their flags aren't used. Avoid transforming such instructions.
4843   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
4844     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4845     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4846     return ShAmt != 0;
4847   }
4848 
4849   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4850   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4851      return getTruncatedShiftCount(MI, 3) != 0;
4852 
4853   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4854   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
4855   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
4856   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
4857   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
4858   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
4859   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4860   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
4861   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
4862   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
4863   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
4864   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
4865   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4866   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
4867   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
4868   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
4869   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
4870   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4871   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
4872   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
4873   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
4874   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
4875   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
4876   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
4877   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
4878   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
4879   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
4880   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4881   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
4882   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
4883   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
4884   case X86::ADC32ri:   case X86::ADC32ri8:
4885   case X86::ADC32rr:   case X86::ADC64ri32:
4886   case X86::ADC64ri8:  case X86::ADC64rr:
4887   case X86::SBB32ri:   case X86::SBB32ri8:
4888   case X86::SBB32rr:   case X86::SBB64ri32:
4889   case X86::SBB64ri8:  case X86::SBB64rr:
4890   case X86::ANDN32rr:  case X86::ANDN32rm:
4891   case X86::ANDN64rr:  case X86::ANDN64rm:
4892   case X86::BEXTR32rr: case X86::BEXTR64rr:
4893   case X86::BEXTR32rm: case X86::BEXTR64rm:
4894   case X86::BLSI32rr:  case X86::BLSI32rm:
4895   case X86::BLSI64rr:  case X86::BLSI64rm:
4896   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4897   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4898   case X86::BLSR32rr:  case X86::BLSR32rm:
4899   case X86::BLSR64rr:  case X86::BLSR64rm:
4900   case X86::BZHI32rr:  case X86::BZHI32rm:
4901   case X86::BZHI64rr:  case X86::BZHI64rm:
4902   case X86::LZCNT16rr: case X86::LZCNT16rm:
4903   case X86::LZCNT32rr: case X86::LZCNT32rm:
4904   case X86::LZCNT64rr: case X86::LZCNT64rm:
4905   case X86::POPCNT16rr:case X86::POPCNT16rm:
4906   case X86::POPCNT32rr:case X86::POPCNT32rm:
4907   case X86::POPCNT64rr:case X86::POPCNT64rm:
4908   case X86::TZCNT16rr: case X86::TZCNT16rm:
4909   case X86::TZCNT32rr: case X86::TZCNT32rm:
4910   case X86::TZCNT64rr: case X86::TZCNT64rm:
4911     return true;
4912   }
4913 }
4914 
4915 /// Check whether the use can be converted to remove a comparison against zero.
4916 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
4917   switch (MI->getOpcode()) {
4918   default: return X86::COND_INVALID;
4919   case X86::LZCNT16rr: case X86::LZCNT16rm:
4920   case X86::LZCNT32rr: case X86::LZCNT32rm:
4921   case X86::LZCNT64rr: case X86::LZCNT64rm:
4922     return X86::COND_B;
4923   case X86::POPCNT16rr:case X86::POPCNT16rm:
4924   case X86::POPCNT32rr:case X86::POPCNT32rm:
4925   case X86::POPCNT64rr:case X86::POPCNT64rm:
4926     return X86::COND_E;
4927   case X86::TZCNT16rr: case X86::TZCNT16rm:
4928   case X86::TZCNT32rr: case X86::TZCNT32rm:
4929   case X86::TZCNT64rr: case X86::TZCNT64rm:
4930     return X86::COND_B;
4931   }
4932 }
4933 
4934 /// Check if there exists an earlier instruction that
4935 /// operates on the same source operands and sets flags in the same way as
4936 /// Compare; remove Compare if possible.
4937 bool X86InstrInfo::
4938 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
4939                      int CmpMask, int CmpValue,
4940                      const MachineRegisterInfo *MRI) const {
4941   // Check whether we can replace SUB with CMP.
4942   unsigned NewOpcode = 0;
4943   switch (CmpInstr->getOpcode()) {
4944   default: break;
4945   case X86::SUB64ri32:
4946   case X86::SUB64ri8:
4947   case X86::SUB32ri:
4948   case X86::SUB32ri8:
4949   case X86::SUB16ri:
4950   case X86::SUB16ri8:
4951   case X86::SUB8ri:
4952   case X86::SUB64rm:
4953   case X86::SUB32rm:
4954   case X86::SUB16rm:
4955   case X86::SUB8rm:
4956   case X86::SUB64rr:
4957   case X86::SUB32rr:
4958   case X86::SUB16rr:
4959   case X86::SUB8rr: {
4960     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
4961       return false;
4962     // There is no use of the destination register, we can replace SUB with CMP.
4963     switch (CmpInstr->getOpcode()) {
4964     default: llvm_unreachable("Unreachable!");
4965     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4966     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4967     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4968     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4969     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4970     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4971     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4972     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4973     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4974     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4975     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4976     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4977     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4978     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4979     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4980     }
4981     CmpInstr->setDesc(get(NewOpcode));
4982     CmpInstr->RemoveOperand(0);
4983     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4984     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4985         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4986       return false;
4987   }
4988   }
4989 
4990   // Get the unique definition of SrcReg.
4991   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4992   if (!MI) return false;
4993 
4994   // CmpInstr is the first instruction of the BB.
4995   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4996 
4997   // If we are comparing against zero, check whether we can use MI to update
4998   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4999   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
5000   if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
5001     return false;
5002 
5003   // If we have a use of the source register between the def and our compare
5004   // instruction we can eliminate the compare iff the use sets EFLAGS in the
5005   // right way.
5006   bool ShouldUpdateCC = false;
5007   X86::CondCode NewCC = X86::COND_INVALID;
5008   if (IsCmpZero && !isDefConvertible(MI)) {
5009     // Scan forward from the use until we hit the use we're looking for or the
5010     // compare instruction.
5011     for (MachineBasicBlock::iterator J = MI;; ++J) {
5012       // Do we have a convertible instruction?
5013       NewCC = isUseDefConvertible(J);
5014       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5015           J->getOperand(1).getReg() == SrcReg) {
5016         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5017         ShouldUpdateCC = true; // Update CC later on.
5018         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5019         // with the new def.
5020         MI = Def = J;
5021         break;
5022       }
5023 
5024       if (J == I)
5025         return false;
5026     }
5027   }
5028 
5029   // We are searching for an earlier instruction that can make CmpInstr
5030   // redundant and that instruction will be saved in Sub.
5031   MachineInstr *Sub = nullptr;
5032   const TargetRegisterInfo *TRI = &getRegisterInfo();
5033 
5034   // We iterate backward, starting from the instruction before CmpInstr and
5035   // stop when reaching the definition of a source register or done with the BB.
5036   // RI points to the instruction before CmpInstr.
5037   // If the definition is in this basic block, RE points to the definition;
5038   // otherwise, RE is the rend of the basic block.
5039   MachineBasicBlock::reverse_iterator
5040       RI = MachineBasicBlock::reverse_iterator(I),
5041       RE = CmpInstr->getParent() == MI->getParent() ?
5042            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
5043            CmpInstr->getParent()->rend();
5044   MachineInstr *Movr0Inst = nullptr;
5045   for (; RI != RE; ++RI) {
5046     MachineInstr *Instr = &*RI;
5047     // Check whether CmpInstr can be made redundant by the current instruction.
5048     if (!IsCmpZero &&
5049         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
5050       Sub = Instr;
5051       break;
5052     }
5053 
5054     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
5055         Instr->readsRegister(X86::EFLAGS, TRI)) {
5056       // This instruction modifies or uses EFLAGS.
5057 
5058       // MOV32r0 etc. are implemented with xor which clobbers condition code.
5059       // They are safe to move up, if the definition to EFLAGS is dead and
5060       // earlier instructions do not read or write EFLAGS.
5061       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
5062           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
5063         Movr0Inst = Instr;
5064         continue;
5065       }
5066 
5067       // We can't remove CmpInstr.
5068       return false;
5069     }
5070   }
5071 
5072   // Return false if no candidates exist.
5073   if (!IsCmpZero && !Sub)
5074     return false;
5075 
5076   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5077                     Sub->getOperand(2).getReg() == SrcReg);
5078 
5079   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
5080   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5081   // If we are done with the basic block, we need to check whether EFLAGS is
5082   // live-out.
5083   bool IsSafe = false;
5084   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
5085   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
5086   for (++I; I != E; ++I) {
5087     const MachineInstr &Instr = *I;
5088     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5089     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5090     // We should check the usage if this instruction uses and updates EFLAGS.
5091     if (!UseEFLAGS && ModifyEFLAGS) {
5092       // It is safe to remove CmpInstr if EFLAGS is updated again.
5093       IsSafe = true;
5094       break;
5095     }
5096     if (!UseEFLAGS && !ModifyEFLAGS)
5097       continue;
5098 
5099     // EFLAGS is used by this instruction.
5100     X86::CondCode OldCC = X86::COND_INVALID;
5101     bool OpcIsSET = false;
5102     if (IsCmpZero || IsSwapped) {
5103       // We decode the condition code from opcode.
5104       if (Instr.isBranch())
5105         OldCC = getCondFromBranchOpc(Instr.getOpcode());
5106       else {
5107         OldCC = getCondFromSETOpc(Instr.getOpcode());
5108         if (OldCC != X86::COND_INVALID)
5109           OpcIsSET = true;
5110         else
5111           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
5112       }
5113       if (OldCC == X86::COND_INVALID) return false;
5114     }
5115     if (IsCmpZero) {
5116       switch (OldCC) {
5117       default: break;
5118       case X86::COND_A: case X86::COND_AE:
5119       case X86::COND_B: case X86::COND_BE:
5120       case X86::COND_G: case X86::COND_GE:
5121       case X86::COND_L: case X86::COND_LE:
5122       case X86::COND_O: case X86::COND_NO:
5123         // CF and OF are used, we can't perform this optimization.
5124         return false;
5125       }
5126 
5127       // If we're updating the condition code check if we have to reverse the
5128       // condition.
5129       if (ShouldUpdateCC)
5130         switch (OldCC) {
5131         default:
5132           return false;
5133         case X86::COND_E:
5134           break;
5135         case X86::COND_NE:
5136           NewCC = GetOppositeBranchCondition(NewCC);
5137           break;
5138         }
5139     } else if (IsSwapped) {
5140       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5141       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5142       // We swap the condition code and synthesize the new opcode.
5143       NewCC = getSwappedCondition(OldCC);
5144       if (NewCC == X86::COND_INVALID) return false;
5145     }
5146 
5147     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
5148       // Synthesize the new opcode.
5149       bool HasMemoryOperand = Instr.hasOneMemOperand();
5150       unsigned NewOpc;
5151       if (Instr.isBranch())
5152         NewOpc = GetCondBranchFromCond(NewCC);
5153       else if(OpcIsSET)
5154         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5155       else {
5156         unsigned DstReg = Instr.getOperand(0).getReg();
5157         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5158                                  HasMemoryOperand);
5159       }
5160 
5161       // Push the MachineInstr to OpsToUpdate.
5162       // If it is safe to remove CmpInstr, the condition code of these
5163       // instructions will be modified.
5164       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5165     }
5166     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5167       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
5168       IsSafe = true;
5169       break;
5170     }
5171   }
5172 
5173   // If EFLAGS is not killed nor re-defined, we should check whether it is
5174   // live-out. If it is live-out, do not optimize.
5175   if ((IsCmpZero || IsSwapped) && !IsSafe) {
5176     MachineBasicBlock *MBB = CmpInstr->getParent();
5177     for (MachineBasicBlock *Successor : MBB->successors())
5178       if (Successor->isLiveIn(X86::EFLAGS))
5179         return false;
5180   }
5181 
5182   // The instruction to be updated is either Sub or MI.
5183   Sub = IsCmpZero ? MI : Sub;
5184   // Move Movr0Inst to the appropriate place before Sub.
5185   if (Movr0Inst) {
5186     // Look backwards until we find a def that doesn't use the current EFLAGS.
5187     Def = Sub;
5188     MachineBasicBlock::reverse_iterator
5189       InsertI = MachineBasicBlock::reverse_iterator(++Def),
5190                 InsertE = Sub->getParent()->rend();
5191     for (; InsertI != InsertE; ++InsertI) {
5192       MachineInstr *Instr = &*InsertI;
5193       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5194           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5195         Sub->getParent()->remove(Movr0Inst);
5196         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5197                                    Movr0Inst);
5198         break;
5199       }
5200     }
5201     if (InsertI == InsertE)
5202       return false;
5203   }
5204 
5205   // Make sure Sub instruction defines EFLAGS and mark the def live.
5206   unsigned i = 0, e = Sub->getNumOperands();
5207   for (; i != e; ++i) {
5208     MachineOperand &MO = Sub->getOperand(i);
5209     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5210       MO.setIsDead(false);
5211       break;
5212     }
5213   }
5214   assert(i != e && "Unable to locate a def EFLAGS operand");
5215 
5216   CmpInstr->eraseFromParent();
5217 
5218   // Modify the condition code of instructions in OpsToUpdate.
5219   for (auto &Op : OpsToUpdate)
5220     Op.first->setDesc(get(Op.second));
5221   return true;
5222 }
5223 
5224 /// Try to remove the load by folding it to a register
5225 /// operand at the use. We fold the load instructions if load defines a virtual
5226 /// register, the virtual register is used once in the same BB, and the
5227 /// instructions in-between do not load or store, and have no side effects.
5228 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
5229                                               const MachineRegisterInfo *MRI,
5230                                               unsigned &FoldAsLoadDefReg,
5231                                               MachineInstr *&DefMI) const {
5232   if (FoldAsLoadDefReg == 0)
5233     return nullptr;
5234   // To be conservative, if there exists another load, clear the load candidate.
5235   if (MI->mayLoad()) {
5236     FoldAsLoadDefReg = 0;
5237     return nullptr;
5238   }
5239 
5240   // Check whether we can move DefMI here.
5241   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5242   assert(DefMI);
5243   bool SawStore = false;
5244   if (!DefMI->isSafeToMove(nullptr, SawStore))
5245     return nullptr;
5246 
5247   // Collect information about virtual register operands of MI.
5248   unsigned SrcOperandId = 0;
5249   bool FoundSrcOperand = false;
5250   for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
5251     MachineOperand &MO = MI->getOperand(i);
5252     if (!MO.isReg())
5253       continue;
5254     unsigned Reg = MO.getReg();
5255     if (Reg != FoldAsLoadDefReg)
5256       continue;
5257     // Do not fold if we have a subreg use or a def or multiple uses.
5258     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
5259       return nullptr;
5260 
5261     SrcOperandId = i;
5262     FoundSrcOperand = true;
5263   }
5264   if (!FoundSrcOperand)
5265     return nullptr;
5266 
5267   // Check whether we can fold the def into SrcOperandId.
5268   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI)) {
5269     FoldAsLoadDefReg = 0;
5270     return FoldMI;
5271   }
5272 
5273   return nullptr;
5274 }
5275 
5276 /// Expand a single-def pseudo instruction to a two-addr
5277 /// instruction with two undef reads of the register being defined.
5278 /// This is used for mapping:
5279 ///   %xmm4 = V_SET0
5280 /// to:
5281 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5282 ///
5283 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5284                              const MCInstrDesc &Desc) {
5285   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5286   unsigned Reg = MIB->getOperand(0).getReg();
5287   MIB->setDesc(Desc);
5288 
5289   // MachineInstr::addOperand() will insert explicit operands before any
5290   // implicit operands.
5291   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5292   // But we don't trust that.
5293   assert(MIB->getOperand(1).getReg() == Reg &&
5294          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
5295   return true;
5296 }
5297 
5298 /// Expand a single-def pseudo instruction to a two-addr
5299 /// instruction with two %k0 reads.
5300 /// This is used for mapping:
5301 ///   %k4 = K_SET1
5302 /// to:
5303 ///   %k4 = KXNORrr %k0, %k0
5304 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5305                             const MCInstrDesc &Desc, unsigned Reg) {
5306   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5307   MIB->setDesc(Desc);
5308   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5309   return true;
5310 }
5311 
5312 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5313                           bool MinusOne) {
5314   MachineBasicBlock &MBB = *MIB->getParent();
5315   DebugLoc DL = MIB->getDebugLoc();
5316   unsigned Reg = MIB->getOperand(0).getReg();
5317 
5318   // Insert the XOR.
5319   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5320       .addReg(Reg, RegState::Undef)
5321       .addReg(Reg, RegState::Undef);
5322 
5323   // Turn the pseudo into an INC or DEC.
5324   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5325   MIB.addReg(Reg);
5326 
5327   return true;
5328 }
5329 
5330 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5331 // code sequence is needed for other targets.
5332 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5333                                  const TargetInstrInfo &TII) {
5334   MachineBasicBlock &MBB = *MIB->getParent();
5335   DebugLoc DL = MIB->getDebugLoc();
5336   unsigned Reg = MIB->getOperand(0).getReg();
5337   const GlobalValue *GV =
5338       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
5339   unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
5340   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
5341       MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8);
5342   MachineBasicBlock::iterator I = MIB.getInstr();
5343 
5344   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5345       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5346       .addMemOperand(MMO);
5347   MIB->setDebugLoc(DL);
5348   MIB->setDesc(TII.get(X86::MOV64rm));
5349   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5350 }
5351 
5352 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
5353   bool HasAVX = Subtarget.hasAVX();
5354   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
5355   switch (MI->getOpcode()) {
5356   case X86::MOV32r0:
5357     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
5358   case X86::MOV32r1:
5359     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5360   case X86::MOV32r_1:
5361     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
5362   case X86::SETB_C8r:
5363     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
5364   case X86::SETB_C16r:
5365     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
5366   case X86::SETB_C32r:
5367     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
5368   case X86::SETB_C64r:
5369     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
5370   case X86::V_SET0:
5371   case X86::FsFLD0SS:
5372   case X86::FsFLD0SD:
5373     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
5374   case X86::AVX_SET0:
5375     assert(HasAVX && "AVX not supported");
5376     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
5377   case X86::AVX512_512_SET0:
5378     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
5379   case X86::V_SETALLONES:
5380     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
5381   case X86::AVX2_SETALLONES:
5382     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
5383   case X86::TEST8ri_NOREX:
5384     MI->setDesc(get(X86::TEST8ri));
5385     return true;
5386   case X86::MOV32ri64:
5387     MI->setDesc(get(X86::MOV32ri));
5388     return true;
5389 
5390   // KNL does not recognize dependency-breaking idioms for mask registers,
5391   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5392   // Using %k0 as the undef input register is a performance heuristic based
5393   // on the assumption that %k0 is used less frequently than the other mask
5394   // registers, since it is not usable as a write mask.
5395   // FIXME: A more advanced approach would be to choose the best input mask
5396   // register based on context.
5397   case X86::KSET0B:
5398   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5399   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5400   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
5401   case X86::KSET1B:
5402   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5403   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5404   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
5405   case TargetOpcode::LOAD_STACK_GUARD:
5406     expandLoadStackGuard(MIB, *this);
5407     return true;
5408   }
5409   return false;
5410 }
5411 
5412 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5413                         int PtrOffset = 0) {
5414   unsigned NumAddrOps = MOs.size();
5415 
5416   if (NumAddrOps < 4) {
5417     // FrameIndex only - add an immediate offset (whether its zero or not).
5418     for (unsigned i = 0; i != NumAddrOps; ++i)
5419       MIB.addOperand(MOs[i]);
5420     addOffset(MIB, PtrOffset);
5421   } else {
5422     // General Memory Addressing - we need to add any offset to an existing
5423     // offset.
5424     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5425     for (unsigned i = 0; i != NumAddrOps; ++i) {
5426       const MachineOperand &MO = MOs[i];
5427       if (i == 3 && PtrOffset != 0) {
5428         MIB.addDisp(MO, PtrOffset);
5429       } else {
5430         MIB.addOperand(MO);
5431       }
5432     }
5433   }
5434 }
5435 
5436 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5437                                      ArrayRef<MachineOperand> MOs,
5438                                      MachineBasicBlock::iterator InsertPt,
5439                                      MachineInstr *MI,
5440                                      const TargetInstrInfo &TII) {
5441   // Create the base instruction with the memory operand as the first part.
5442   // Omit the implicit operands, something BuildMI can't do.
5443   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5444                                               MI->getDebugLoc(), true);
5445   MachineInstrBuilder MIB(MF, NewMI);
5446   addOperands(MIB, MOs);
5447 
5448   // Loop over the rest of the ri operands, converting them over.
5449   unsigned NumOps = MI->getDesc().getNumOperands()-2;
5450   for (unsigned i = 0; i != NumOps; ++i) {
5451     MachineOperand &MO = MI->getOperand(i+2);
5452     MIB.addOperand(MO);
5453   }
5454   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
5455     MachineOperand &MO = MI->getOperand(i);
5456     MIB.addOperand(MO);
5457   }
5458 
5459   MachineBasicBlock *MBB = InsertPt->getParent();
5460   MBB->insert(InsertPt, NewMI);
5461 
5462   return MIB;
5463 }
5464 
5465 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5466                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5467                               MachineBasicBlock::iterator InsertPt,
5468                               MachineInstr *MI, const TargetInstrInfo &TII,
5469                               int PtrOffset = 0) {
5470   // Omit the implicit operands, something BuildMI can't do.
5471   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5472                                               MI->getDebugLoc(), true);
5473   MachineInstrBuilder MIB(MF, NewMI);
5474 
5475   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5476     MachineOperand &MO = MI->getOperand(i);
5477     if (i == OpNo) {
5478       assert(MO.isReg() && "Expected to fold into reg operand!");
5479       addOperands(MIB, MOs, PtrOffset);
5480     } else {
5481       MIB.addOperand(MO);
5482     }
5483   }
5484 
5485   MachineBasicBlock *MBB = InsertPt->getParent();
5486   MBB->insert(InsertPt, NewMI);
5487 
5488   return MIB;
5489 }
5490 
5491 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5492                                 ArrayRef<MachineOperand> MOs,
5493                                 MachineBasicBlock::iterator InsertPt,
5494                                 MachineInstr *MI) {
5495   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5496                                     MI->getDebugLoc(), TII.get(Opcode));
5497   addOperands(MIB, MOs);
5498   return MIB.addImm(0);
5499 }
5500 
5501 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5502     MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5503     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5504     unsigned Size, unsigned Align) const {
5505   switch (MI->getOpcode()) {
5506   case X86::INSERTPSrr:
5507   case X86::VINSERTPSrr:
5508     // Attempt to convert the load of inserted vector into a fold load
5509     // of a single float.
5510     if (OpNum == 2) {
5511       unsigned Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
5512       unsigned ZMask = Imm & 15;
5513       unsigned DstIdx = (Imm >> 4) & 3;
5514       unsigned SrcIdx = (Imm >> 6) & 3;
5515 
5516       unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5517       if (Size <= RCSize && 4 <= Align) {
5518         int PtrOffset = SrcIdx * 4;
5519         unsigned NewImm = (DstIdx << 4) | ZMask;
5520         unsigned NewOpCode =
5521             (MI->getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
5522                                                  : X86::INSERTPSrm);
5523         MachineInstr *NewMI =
5524             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5525         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5526         return NewMI;
5527       }
5528     }
5529     break;
5530   };
5531 
5532   return nullptr;
5533 }
5534 
5535 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5536     MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5537     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5538     unsigned Size, unsigned Align, bool AllowCommute) const {
5539   const DenseMap<unsigned,
5540                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
5541   bool isCallRegIndirect = Subtarget.callRegIndirect();
5542   bool isTwoAddrFold = false;
5543 
5544   // For CPUs that favor the register form of a call or push,
5545   // do not fold loads into calls or pushes, unless optimizing for size
5546   // aggressively.
5547   if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
5548       (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r ||
5549        MI->getOpcode() == X86::PUSH16r || MI->getOpcode() == X86::PUSH32r ||
5550        MI->getOpcode() == X86::PUSH64r))
5551     return nullptr;
5552 
5553   unsigned NumOps = MI->getDesc().getNumOperands();
5554   bool isTwoAddr = NumOps > 1 &&
5555     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5556 
5557   // FIXME: AsmPrinter doesn't know how to handle
5558   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5559   if (MI->getOpcode() == X86::ADD32ri &&
5560       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5561     return nullptr;
5562 
5563   MachineInstr *NewMI = nullptr;
5564 
5565   // Attempt to fold any custom cases we have.
5566   if (MachineInstr *CustomMI =
5567           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
5568     return CustomMI;
5569 
5570   // Folding a memory location into the two-address part of a two-address
5571   // instruction is different than folding it other places.  It requires
5572   // replacing the *two* registers with the memory location.
5573   if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
5574       MI->getOperand(0).isReg() &&
5575       MI->getOperand(1).isReg() &&
5576       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
5577     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5578     isTwoAddrFold = true;
5579   } else if (OpNum == 0) {
5580     if (MI->getOpcode() == X86::MOV32r0) {
5581       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5582       if (NewMI)
5583         return NewMI;
5584     }
5585 
5586     OpcodeTablePtr = &RegOp2MemOpTable0;
5587   } else if (OpNum == 1) {
5588     OpcodeTablePtr = &RegOp2MemOpTable1;
5589   } else if (OpNum == 2) {
5590     OpcodeTablePtr = &RegOp2MemOpTable2;
5591   } else if (OpNum == 3) {
5592     OpcodeTablePtr = &RegOp2MemOpTable3;
5593   } else if (OpNum == 4) {
5594     OpcodeTablePtr = &RegOp2MemOpTable4;
5595   }
5596 
5597   // If table selected...
5598   if (OpcodeTablePtr) {
5599     // Find the Opcode to fuse
5600     DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5601       OpcodeTablePtr->find(MI->getOpcode());
5602     if (I != OpcodeTablePtr->end()) {
5603       unsigned Opcode = I->second.first;
5604       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
5605       if (Align < MinAlign)
5606         return nullptr;
5607       bool NarrowToMOV32rm = false;
5608       if (Size) {
5609         unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5610         if (Size < RCSize) {
5611           // Check if it's safe to fold the load. If the size of the object is
5612           // narrower than the load width, then it's not.
5613           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5614             return nullptr;
5615           // If this is a 64-bit load, but the spill slot is 32, then we can do
5616           // a 32-bit load which is implicitly zero-extended. This likely is
5617           // due to live interval analysis remat'ing a load from stack slot.
5618           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
5619             return nullptr;
5620           Opcode = X86::MOV32rm;
5621           NarrowToMOV32rm = true;
5622         }
5623       }
5624 
5625       if (isTwoAddrFold)
5626         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5627       else
5628         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5629 
5630       if (NarrowToMOV32rm) {
5631         // If this is the special case where we use a MOV32rm to load a 32-bit
5632         // value and zero-extend the top bits. Change the destination register
5633         // to a 32-bit one.
5634         unsigned DstReg = NewMI->getOperand(0).getReg();
5635         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
5636           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5637         else
5638           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5639       }
5640       return NewMI;
5641     }
5642   }
5643 
5644   // If the instruction and target operand are commutable, commute the
5645   // instruction and try again.
5646   if (AllowCommute) {
5647     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5648     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5649       bool HasDef = MI->getDesc().getNumDefs();
5650       unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
5651       unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
5652       unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
5653       bool Tied1 =
5654           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5655       bool Tied2 =
5656           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5657 
5658       // If either of the commutable operands are tied to the destination
5659       // then we can not commute + fold.
5660       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5661           (HasDef && Reg0 == Reg2 && Tied2))
5662         return nullptr;
5663 
5664       MachineInstr *CommutedMI =
5665           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5666       if (!CommutedMI) {
5667         // Unable to commute.
5668         return nullptr;
5669       }
5670       if (CommutedMI != MI) {
5671         // New instruction. We can't fold from this.
5672         CommutedMI->eraseFromParent();
5673         return nullptr;
5674       }
5675 
5676       // Attempt to fold with the commuted version of the instruction.
5677       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5678                                     Size, Align, /*AllowCommute=*/false);
5679       if (NewMI)
5680         return NewMI;
5681 
5682       // Folding failed again - undo the commute before returning.
5683       MachineInstr *UncommutedMI =
5684           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5685       if (!UncommutedMI) {
5686         // Unable to commute.
5687         return nullptr;
5688       }
5689       if (UncommutedMI != MI) {
5690         // New instruction. It doesn't need to be kept.
5691         UncommutedMI->eraseFromParent();
5692         return nullptr;
5693       }
5694 
5695       // Return here to prevent duplicate fuse failure report.
5696       return nullptr;
5697     }
5698   }
5699 
5700   // No fusion
5701   if (PrintFailedFusing && !MI->isCopy())
5702     dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
5703   return nullptr;
5704 }
5705 
5706 /// Return true for all instructions that only update
5707 /// the first 32 or 64-bits of the destination register and leave the rest
5708 /// unmodified. This can be used to avoid folding loads if the instructions
5709 /// only update part of the destination register, and the non-updated part is
5710 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5711 /// instructions breaks the partial register dependency and it can improve
5712 /// performance. e.g.:
5713 ///
5714 ///   movss (%rdi), %xmm0
5715 ///   cvtss2sd %xmm0, %xmm0
5716 ///
5717 /// Instead of
5718 ///   cvtss2sd (%rdi), %xmm0
5719 ///
5720 /// FIXME: This should be turned into a TSFlags.
5721 ///
5722 static bool hasPartialRegUpdate(unsigned Opcode) {
5723   switch (Opcode) {
5724   case X86::CVTSI2SSrr:
5725   case X86::CVTSI2SSrm:
5726   case X86::CVTSI2SS64rr:
5727   case X86::CVTSI2SS64rm:
5728   case X86::CVTSI2SDrr:
5729   case X86::CVTSI2SDrm:
5730   case X86::CVTSI2SD64rr:
5731   case X86::CVTSI2SD64rm:
5732   case X86::CVTSD2SSrr:
5733   case X86::CVTSD2SSrm:
5734   case X86::Int_CVTSD2SSrr:
5735   case X86::Int_CVTSD2SSrm:
5736   case X86::CVTSS2SDrr:
5737   case X86::CVTSS2SDrm:
5738   case X86::Int_CVTSS2SDrr:
5739   case X86::Int_CVTSS2SDrm:
5740   case X86::RCPSSr:
5741   case X86::RCPSSm:
5742   case X86::RCPSSr_Int:
5743   case X86::RCPSSm_Int:
5744   case X86::ROUNDSDr:
5745   case X86::ROUNDSDm:
5746   case X86::ROUNDSDr_Int:
5747   case X86::ROUNDSSr:
5748   case X86::ROUNDSSm:
5749   case X86::ROUNDSSr_Int:
5750   case X86::RSQRTSSr:
5751   case X86::RSQRTSSm:
5752   case X86::RSQRTSSr_Int:
5753   case X86::RSQRTSSm_Int:
5754   case X86::SQRTSSr:
5755   case X86::SQRTSSm:
5756   case X86::SQRTSSr_Int:
5757   case X86::SQRTSSm_Int:
5758   case X86::SQRTSDr:
5759   case X86::SQRTSDm:
5760   case X86::SQRTSDr_Int:
5761   case X86::SQRTSDm_Int:
5762     return true;
5763   }
5764 
5765   return false;
5766 }
5767 
5768 /// Inform the ExeDepsFix pass how many idle
5769 /// instructions we would like before a partial register update.
5770 unsigned X86InstrInfo::
5771 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
5772                              const TargetRegisterInfo *TRI) const {
5773   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
5774     return 0;
5775 
5776   // If MI is marked as reading Reg, the partial register update is wanted.
5777   const MachineOperand &MO = MI->getOperand(0);
5778   unsigned Reg = MO.getReg();
5779   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
5780     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
5781       return 0;
5782   } else {
5783     if (MI->readsRegister(Reg, TRI))
5784       return 0;
5785   }
5786 
5787   // If any of the preceding 16 instructions are reading Reg, insert a
5788   // dependency breaking instruction.  The magic number is based on a few
5789   // Nehalem experiments.
5790   return 16;
5791 }
5792 
5793 // Return true for any instruction the copies the high bits of the first source
5794 // operand into the unused high bits of the destination operand.
5795 static bool hasUndefRegUpdate(unsigned Opcode) {
5796   switch (Opcode) {
5797   case X86::VCVTSI2SSrr:
5798   case X86::VCVTSI2SSrm:
5799   case X86::Int_VCVTSI2SSrr:
5800   case X86::Int_VCVTSI2SSrm:
5801   case X86::VCVTSI2SS64rr:
5802   case X86::VCVTSI2SS64rm:
5803   case X86::Int_VCVTSI2SS64rr:
5804   case X86::Int_VCVTSI2SS64rm:
5805   case X86::VCVTSI2SDrr:
5806   case X86::VCVTSI2SDrm:
5807   case X86::Int_VCVTSI2SDrr:
5808   case X86::Int_VCVTSI2SDrm:
5809   case X86::VCVTSI2SD64rr:
5810   case X86::VCVTSI2SD64rm:
5811   case X86::Int_VCVTSI2SD64rr:
5812   case X86::Int_VCVTSI2SD64rm:
5813   case X86::VCVTSD2SSrr:
5814   case X86::VCVTSD2SSrm:
5815   case X86::Int_VCVTSD2SSrr:
5816   case X86::Int_VCVTSD2SSrm:
5817   case X86::VCVTSS2SDrr:
5818   case X86::VCVTSS2SDrm:
5819   case X86::Int_VCVTSS2SDrr:
5820   case X86::Int_VCVTSS2SDrm:
5821   case X86::VRCPSSr:
5822   case X86::VRCPSSm:
5823   case X86::VRCPSSm_Int:
5824   case X86::VROUNDSDr:
5825   case X86::VROUNDSDm:
5826   case X86::VROUNDSDr_Int:
5827   case X86::VROUNDSSr:
5828   case X86::VROUNDSSm:
5829   case X86::VROUNDSSr_Int:
5830   case X86::VRSQRTSSr:
5831   case X86::VRSQRTSSm:
5832   case X86::VRSQRTSSm_Int:
5833   case X86::VSQRTSSr:
5834   case X86::VSQRTSSm:
5835   case X86::VSQRTSSm_Int:
5836   case X86::VSQRTSDr:
5837   case X86::VSQRTSDm:
5838   case X86::VSQRTSDm_Int:
5839     // AVX-512
5840   case X86::VCVTSD2SSZrr:
5841   case X86::VCVTSD2SSZrm:
5842   case X86::VCVTSS2SDZrr:
5843   case X86::VCVTSS2SDZrm:
5844     return true;
5845   }
5846 
5847   return false;
5848 }
5849 
5850 /// Inform the ExeDepsFix pass how many idle instructions we would like before
5851 /// certain undef register reads.
5852 ///
5853 /// This catches the VCVTSI2SD family of instructions:
5854 ///
5855 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
5856 ///
5857 /// We should to be careful *not* to catch VXOR idioms which are presumably
5858 /// handled specially in the pipeline:
5859 ///
5860 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
5861 ///
5862 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5863 /// high bits that are passed-through are not live.
5864 unsigned X86InstrInfo::
5865 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
5866                      const TargetRegisterInfo *TRI) const {
5867   if (!hasUndefRegUpdate(MI->getOpcode()))
5868     return 0;
5869 
5870   // Set the OpNum parameter to the first source operand.
5871   OpNum = 1;
5872 
5873   const MachineOperand &MO = MI->getOperand(OpNum);
5874   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
5875     // Use the same magic number as getPartialRegUpdateClearance.
5876     return 16;
5877   }
5878   return 0;
5879 }
5880 
5881 void X86InstrInfo::
5882 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
5883                           const TargetRegisterInfo *TRI) const {
5884   unsigned Reg = MI->getOperand(OpNum).getReg();
5885   // If MI kills this register, the false dependence is already broken.
5886   if (MI->killsRegister(Reg, TRI))
5887     return;
5888 
5889   if (X86::VR128RegClass.contains(Reg)) {
5890     // These instructions are all floating point domain, so xorps is the best
5891     // choice.
5892     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
5893     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
5894       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5895     MI->addRegisterKilled(Reg, TRI, true);
5896   } else if (X86::VR256RegClass.contains(Reg)) {
5897     // Use vxorps to clear the full ymm register.
5898     // It wants to read and write the xmm sub-register.
5899     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5900     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
5901       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
5902       .addReg(Reg, RegState::ImplicitDefine);
5903     MI->addRegisterKilled(Reg, TRI, true);
5904   }
5905 }
5906 
5907 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5908     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
5909     MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
5910   // Check switch flag
5911   if (NoFusing)
5912     return nullptr;
5913 
5914   // Unless optimizing for size, don't fold to avoid partial
5915   // register update stalls
5916   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
5917     return nullptr;
5918 
5919   const MachineFrameInfo *MFI = MF.getFrameInfo();
5920   unsigned Size = MFI->getObjectSize(FrameIndex);
5921   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
5922   // If the function stack isn't realigned we don't want to fold instructions
5923   // that need increased alignment.
5924   if (!RI.needsStackRealignment(MF))
5925     Alignment =
5926         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
5927   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5928     unsigned NewOpc = 0;
5929     unsigned RCSize = 0;
5930     switch (MI->getOpcode()) {
5931     default: return nullptr;
5932     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5933     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5934     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5935     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5936     }
5937     // Check if it's safe to fold the load. If the size of the object is
5938     // narrower than the load width, then it's not.
5939     if (Size < RCSize)
5940       return nullptr;
5941     // Change to CMPXXri r, 0 first.
5942     MI->setDesc(get(NewOpc));
5943     MI->getOperand(1).ChangeToImmediate(0);
5944   } else if (Ops.size() != 1)
5945     return nullptr;
5946 
5947   return foldMemoryOperandImpl(MF, MI, Ops[0],
5948                                MachineOperand::CreateFI(FrameIndex), InsertPt,
5949                                Size, Alignment, /*AllowCommute=*/true);
5950 }
5951 
5952 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5953 /// because the latter uses contents that wouldn't be defined in the folded
5954 /// version.  For instance, this transformation isn't legal:
5955 ///   movss (%rdi), %xmm0
5956 ///   addps %xmm0, %xmm0
5957 /// ->
5958 ///   addps (%rdi), %xmm0
5959 ///
5960 /// But this one is:
5961 ///   movss (%rdi), %xmm0
5962 ///   addss %xmm0, %xmm0
5963 /// ->
5964 ///   addss (%rdi), %xmm0
5965 ///
5966 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5967                                              const MachineInstr &UserMI,
5968                                              const MachineFunction &MF) {
5969   unsigned Opc = LoadMI.getOpcode();
5970   unsigned UserOpc = UserMI.getOpcode();
5971   unsigned RegSize =
5972       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
5973 
5974   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
5975     // These instructions only load 32 bits, we can't fold them if the
5976     // destination register is wider than 32 bits (4 bytes), and its user
5977     // instruction isn't scalar (SS).
5978     switch (UserOpc) {
5979     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
5980     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
5981     case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
5982     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
5983     case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int:
5984     case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int:
5985     case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int:
5986     case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int:
5987     case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int:
5988     case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int:
5989       return false;
5990     default:
5991       return true;
5992     }
5993   }
5994 
5995   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
5996     // These instructions only load 64 bits, we can't fold them if the
5997     // destination register is wider than 64 bits (8 bytes), and its user
5998     // instruction isn't scalar (SD).
5999     switch (UserOpc) {
6000     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
6001     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
6002     case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
6003     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
6004     case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int:
6005     case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int:
6006     case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int:
6007     case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int:
6008     case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int:
6009     case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int:
6010       return false;
6011     default:
6012       return true;
6013     }
6014   }
6015 
6016   return false;
6017 }
6018 
6019 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6020     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
6021     MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
6022   // If loading from a FrameIndex, fold directly from the FrameIndex.
6023   unsigned NumOps = LoadMI->getDesc().getNumOperands();
6024   int FrameIndex;
6025   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6026     if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
6027       return nullptr;
6028     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex);
6029   }
6030 
6031   // Check switch flag
6032   if (NoFusing) return nullptr;
6033 
6034   // Avoid partial register update stalls unless optimizing for size.
6035   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
6036     return nullptr;
6037 
6038   // Determine the alignment of the load.
6039   unsigned Alignment = 0;
6040   if (LoadMI->hasOneMemOperand())
6041     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
6042   else
6043     switch (LoadMI->getOpcode()) {
6044     case X86::AVX2_SETALLONES:
6045     case X86::AVX_SET0:
6046       Alignment = 32;
6047       break;
6048     case X86::V_SET0:
6049     case X86::V_SETALLONES:
6050       Alignment = 16;
6051       break;
6052     case X86::FsFLD0SD:
6053       Alignment = 8;
6054       break;
6055     case X86::FsFLD0SS:
6056       Alignment = 4;
6057       break;
6058     default:
6059       return nullptr;
6060     }
6061   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6062     unsigned NewOpc = 0;
6063     switch (MI->getOpcode()) {
6064     default: return nullptr;
6065     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6066     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6067     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6068     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6069     }
6070     // Change to CMPXXri r, 0 first.
6071     MI->setDesc(get(NewOpc));
6072     MI->getOperand(1).ChangeToImmediate(0);
6073   } else if (Ops.size() != 1)
6074     return nullptr;
6075 
6076   // Make sure the subregisters match.
6077   // Otherwise we risk changing the size of the load.
6078   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
6079     return nullptr;
6080 
6081   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6082   switch (LoadMI->getOpcode()) {
6083   case X86::V_SET0:
6084   case X86::V_SETALLONES:
6085   case X86::AVX2_SETALLONES:
6086   case X86::AVX_SET0:
6087   case X86::FsFLD0SD:
6088   case X86::FsFLD0SS: {
6089     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6090     // Create a constant-pool entry and operands to load from it.
6091 
6092     // Medium and large mode can't fold loads this way.
6093     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6094         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6095       return nullptr;
6096 
6097     // x86-32 PIC requires a PIC base register for constant pools.
6098     unsigned PICBase = 0;
6099     if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
6100       if (Subtarget.is64Bit())
6101         PICBase = X86::RIP;
6102       else
6103         // FIXME: PICBase = getGlobalBaseReg(&MF);
6104         // This doesn't work for several reasons.
6105         // 1. GlobalBaseReg may have been spilled.
6106         // 2. It may not be live at MI.
6107         return nullptr;
6108     }
6109 
6110     // Create a constant-pool entry.
6111     MachineConstantPool &MCP = *MF.getConstantPool();
6112     Type *Ty;
6113     unsigned Opc = LoadMI->getOpcode();
6114     if (Opc == X86::FsFLD0SS)
6115       Ty = Type::getFloatTy(MF.getFunction()->getContext());
6116     else if (Opc == X86::FsFLD0SD)
6117       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
6118     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
6119       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
6120     else
6121       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
6122 
6123     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
6124     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6125                                     Constant::getNullValue(Ty);
6126     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6127 
6128     // Create operands to load from the constant pool entry.
6129     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6130     MOs.push_back(MachineOperand::CreateImm(1));
6131     MOs.push_back(MachineOperand::CreateReg(0, false));
6132     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6133     MOs.push_back(MachineOperand::CreateReg(0, false));
6134     break;
6135   }
6136   default: {
6137     if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
6138       return nullptr;
6139 
6140     // Folding a normal load. Just copy the load's address operands.
6141     MOs.append(LoadMI->operands_begin() + NumOps - X86::AddrNumOperands,
6142                LoadMI->operands_begin() + NumOps);
6143     break;
6144   }
6145   }
6146   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6147                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6148 }
6149 
6150 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
6151                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
6152                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
6153   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
6154     MemOp2RegOpTable.find(MI->getOpcode());
6155   if (I == MemOp2RegOpTable.end())
6156     return false;
6157   unsigned Opc = I->second.first;
6158   unsigned Index = I->second.second & TB_INDEX_MASK;
6159   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6160   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6161   if (UnfoldLoad && !FoldedLoad)
6162     return false;
6163   UnfoldLoad &= FoldedLoad;
6164   if (UnfoldStore && !FoldedStore)
6165     return false;
6166   UnfoldStore &= FoldedStore;
6167 
6168   const MCInstrDesc &MCID = get(Opc);
6169   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6170   // TODO: Check if 32-byte or greater accesses are slow too?
6171   if (!MI->hasOneMemOperand() &&
6172       RC == &X86::VR128RegClass &&
6173       Subtarget.isUnalignedMem16Slow())
6174     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6175     // conservatively assume the address is unaligned. That's bad for
6176     // performance.
6177     return false;
6178   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6179   SmallVector<MachineOperand,2> BeforeOps;
6180   SmallVector<MachineOperand,2> AfterOps;
6181   SmallVector<MachineOperand,4> ImpOps;
6182   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
6183     MachineOperand &Op = MI->getOperand(i);
6184     if (i >= Index && i < Index + X86::AddrNumOperands)
6185       AddrOps.push_back(Op);
6186     else if (Op.isReg() && Op.isImplicit())
6187       ImpOps.push_back(Op);
6188     else if (i < Index)
6189       BeforeOps.push_back(Op);
6190     else if (i > Index)
6191       AfterOps.push_back(Op);
6192   }
6193 
6194   // Emit the load instruction.
6195   if (UnfoldLoad) {
6196     std::pair<MachineInstr::mmo_iterator,
6197               MachineInstr::mmo_iterator> MMOs =
6198       MF.extractLoadMemRefs(MI->memoperands_begin(),
6199                             MI->memoperands_end());
6200     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
6201     if (UnfoldStore) {
6202       // Address operands cannot be marked isKill.
6203       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6204         MachineOperand &MO = NewMIs[0]->getOperand(i);
6205         if (MO.isReg())
6206           MO.setIsKill(false);
6207       }
6208     }
6209   }
6210 
6211   // Emit the data processing instruction.
6212   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
6213   MachineInstrBuilder MIB(MF, DataMI);
6214 
6215   if (FoldedStore)
6216     MIB.addReg(Reg, RegState::Define);
6217   for (MachineOperand &BeforeOp : BeforeOps)
6218     MIB.addOperand(BeforeOp);
6219   if (FoldedLoad)
6220     MIB.addReg(Reg);
6221   for (MachineOperand &AfterOp : AfterOps)
6222     MIB.addOperand(AfterOp);
6223   for (MachineOperand &ImpOp : ImpOps) {
6224     MIB.addReg(ImpOp.getReg(),
6225                getDefRegState(ImpOp.isDef()) |
6226                RegState::Implicit |
6227                getKillRegState(ImpOp.isKill()) |
6228                getDeadRegState(ImpOp.isDead()) |
6229                getUndefRegState(ImpOp.isUndef()));
6230   }
6231   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6232   switch (DataMI->getOpcode()) {
6233   default: break;
6234   case X86::CMP64ri32:
6235   case X86::CMP64ri8:
6236   case X86::CMP32ri:
6237   case X86::CMP32ri8:
6238   case X86::CMP16ri:
6239   case X86::CMP16ri8:
6240   case X86::CMP8ri: {
6241     MachineOperand &MO0 = DataMI->getOperand(0);
6242     MachineOperand &MO1 = DataMI->getOperand(1);
6243     if (MO1.getImm() == 0) {
6244       unsigned NewOpc;
6245       switch (DataMI->getOpcode()) {
6246       default: llvm_unreachable("Unreachable!");
6247       case X86::CMP64ri8:
6248       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6249       case X86::CMP32ri8:
6250       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6251       case X86::CMP16ri8:
6252       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6253       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6254       }
6255       DataMI->setDesc(get(NewOpc));
6256       MO1.ChangeToRegister(MO0.getReg(), false);
6257     }
6258   }
6259   }
6260   NewMIs.push_back(DataMI);
6261 
6262   // Emit the store instruction.
6263   if (UnfoldStore) {
6264     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6265     std::pair<MachineInstr::mmo_iterator,
6266               MachineInstr::mmo_iterator> MMOs =
6267       MF.extractStoreMemRefs(MI->memoperands_begin(),
6268                              MI->memoperands_end());
6269     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
6270   }
6271 
6272   return true;
6273 }
6274 
6275 bool
6276 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6277                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6278   if (!N->isMachineOpcode())
6279     return false;
6280 
6281   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
6282     MemOp2RegOpTable.find(N->getMachineOpcode());
6283   if (I == MemOp2RegOpTable.end())
6284     return false;
6285   unsigned Opc = I->second.first;
6286   unsigned Index = I->second.second & TB_INDEX_MASK;
6287   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6288   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6289   const MCInstrDesc &MCID = get(Opc);
6290   MachineFunction &MF = DAG.getMachineFunction();
6291   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6292   unsigned NumDefs = MCID.NumDefs;
6293   std::vector<SDValue> AddrOps;
6294   std::vector<SDValue> BeforeOps;
6295   std::vector<SDValue> AfterOps;
6296   SDLoc dl(N);
6297   unsigned NumOps = N->getNumOperands();
6298   for (unsigned i = 0; i != NumOps-1; ++i) {
6299     SDValue Op = N->getOperand(i);
6300     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6301       AddrOps.push_back(Op);
6302     else if (i < Index-NumDefs)
6303       BeforeOps.push_back(Op);
6304     else if (i > Index-NumDefs)
6305       AfterOps.push_back(Op);
6306   }
6307   SDValue Chain = N->getOperand(NumOps-1);
6308   AddrOps.push_back(Chain);
6309 
6310   // Emit the load instruction.
6311   SDNode *Load = nullptr;
6312   if (FoldedLoad) {
6313     EVT VT = *RC->vt_begin();
6314     std::pair<MachineInstr::mmo_iterator,
6315               MachineInstr::mmo_iterator> MMOs =
6316       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6317                             cast<MachineSDNode>(N)->memoperands_end());
6318     if (!(*MMOs.first) &&
6319         RC == &X86::VR128RegClass &&
6320         Subtarget.isUnalignedMem16Slow())
6321       // Do not introduce a slow unaligned load.
6322       return false;
6323     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6324     // memory access is slow above.
6325     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6326     bool isAligned = (*MMOs.first) &&
6327                      (*MMOs.first)->getAlignment() >= Alignment;
6328     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
6329                               VT, MVT::Other, AddrOps);
6330     NewNodes.push_back(Load);
6331 
6332     // Preserve memory reference information.
6333     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
6334   }
6335 
6336   // Emit the data processing instruction.
6337   std::vector<EVT> VTs;
6338   const TargetRegisterClass *DstRC = nullptr;
6339   if (MCID.getNumDefs() > 0) {
6340     DstRC = getRegClass(MCID, 0, &RI, MF);
6341     VTs.push_back(*DstRC->vt_begin());
6342   }
6343   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6344     EVT VT = N->getValueType(i);
6345     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6346       VTs.push_back(VT);
6347   }
6348   if (Load)
6349     BeforeOps.push_back(SDValue(Load, 0));
6350   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
6351   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6352   NewNodes.push_back(NewNode);
6353 
6354   // Emit the store instruction.
6355   if (FoldedStore) {
6356     AddrOps.pop_back();
6357     AddrOps.push_back(SDValue(NewNode, 0));
6358     AddrOps.push_back(Chain);
6359     std::pair<MachineInstr::mmo_iterator,
6360               MachineInstr::mmo_iterator> MMOs =
6361       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6362                              cast<MachineSDNode>(N)->memoperands_end());
6363     if (!(*MMOs.first) &&
6364         RC == &X86::VR128RegClass &&
6365         Subtarget.isUnalignedMem16Slow())
6366       // Do not introduce a slow unaligned store.
6367       return false;
6368     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6369     // memory access is slow above.
6370     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6371     bool isAligned = (*MMOs.first) &&
6372                      (*MMOs.first)->getAlignment() >= Alignment;
6373     SDNode *Store =
6374         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6375                            dl, MVT::Other, AddrOps);
6376     NewNodes.push_back(Store);
6377 
6378     // Preserve memory reference information.
6379     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
6380   }
6381 
6382   return true;
6383 }
6384 
6385 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6386                                       bool UnfoldLoad, bool UnfoldStore,
6387                                       unsigned *LoadRegIndex) const {
6388   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
6389     MemOp2RegOpTable.find(Opc);
6390   if (I == MemOp2RegOpTable.end())
6391     return 0;
6392   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6393   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6394   if (UnfoldLoad && !FoldedLoad)
6395     return 0;
6396   if (UnfoldStore && !FoldedStore)
6397     return 0;
6398   if (LoadRegIndex)
6399     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
6400   return I->second.first;
6401 }
6402 
6403 bool
6404 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6405                                      int64_t &Offset1, int64_t &Offset2) const {
6406   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6407     return false;
6408   unsigned Opc1 = Load1->getMachineOpcode();
6409   unsigned Opc2 = Load2->getMachineOpcode();
6410   switch (Opc1) {
6411   default: return false;
6412   case X86::MOV8rm:
6413   case X86::MOV16rm:
6414   case X86::MOV32rm:
6415   case X86::MOV64rm:
6416   case X86::LD_Fp32m:
6417   case X86::LD_Fp64m:
6418   case X86::LD_Fp80m:
6419   case X86::MOVSSrm:
6420   case X86::MOVSDrm:
6421   case X86::MMX_MOVD64rm:
6422   case X86::MMX_MOVQ64rm:
6423   case X86::FsMOVAPSrm:
6424   case X86::FsMOVAPDrm:
6425   case X86::MOVAPSrm:
6426   case X86::MOVUPSrm:
6427   case X86::MOVAPDrm:
6428   case X86::MOVDQArm:
6429   case X86::MOVDQUrm:
6430   // AVX load instructions
6431   case X86::VMOVSSrm:
6432   case X86::VMOVSDrm:
6433   case X86::FsVMOVAPSrm:
6434   case X86::FsVMOVAPDrm:
6435   case X86::VMOVAPSrm:
6436   case X86::VMOVUPSrm:
6437   case X86::VMOVAPDrm:
6438   case X86::VMOVDQArm:
6439   case X86::VMOVDQUrm:
6440   case X86::VMOVAPSYrm:
6441   case X86::VMOVUPSYrm:
6442   case X86::VMOVAPDYrm:
6443   case X86::VMOVDQAYrm:
6444   case X86::VMOVDQUYrm:
6445     break;
6446   }
6447   switch (Opc2) {
6448   default: return false;
6449   case X86::MOV8rm:
6450   case X86::MOV16rm:
6451   case X86::MOV32rm:
6452   case X86::MOV64rm:
6453   case X86::LD_Fp32m:
6454   case X86::LD_Fp64m:
6455   case X86::LD_Fp80m:
6456   case X86::MOVSSrm:
6457   case X86::MOVSDrm:
6458   case X86::MMX_MOVD64rm:
6459   case X86::MMX_MOVQ64rm:
6460   case X86::FsMOVAPSrm:
6461   case X86::FsMOVAPDrm:
6462   case X86::MOVAPSrm:
6463   case X86::MOVUPSrm:
6464   case X86::MOVAPDrm:
6465   case X86::MOVDQArm:
6466   case X86::MOVDQUrm:
6467   // AVX load instructions
6468   case X86::VMOVSSrm:
6469   case X86::VMOVSDrm:
6470   case X86::FsVMOVAPSrm:
6471   case X86::FsVMOVAPDrm:
6472   case X86::VMOVAPSrm:
6473   case X86::VMOVUPSrm:
6474   case X86::VMOVAPDrm:
6475   case X86::VMOVDQArm:
6476   case X86::VMOVDQUrm:
6477   case X86::VMOVAPSYrm:
6478   case X86::VMOVUPSYrm:
6479   case X86::VMOVAPDYrm:
6480   case X86::VMOVDQAYrm:
6481   case X86::VMOVDQUYrm:
6482     break;
6483   }
6484 
6485   // Check if chain operands and base addresses match.
6486   if (Load1->getOperand(0) != Load2->getOperand(0) ||
6487       Load1->getOperand(5) != Load2->getOperand(5))
6488     return false;
6489   // Segment operands should match as well.
6490   if (Load1->getOperand(4) != Load2->getOperand(4))
6491     return false;
6492   // Scale should be 1, Index should be Reg0.
6493   if (Load1->getOperand(1) == Load2->getOperand(1) &&
6494       Load1->getOperand(2) == Load2->getOperand(2)) {
6495     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6496       return false;
6497 
6498     // Now let's examine the displacements.
6499     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6500         isa<ConstantSDNode>(Load2->getOperand(3))) {
6501       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6502       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6503       return true;
6504     }
6505   }
6506   return false;
6507 }
6508 
6509 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6510                                            int64_t Offset1, int64_t Offset2,
6511                                            unsigned NumLoads) const {
6512   assert(Offset2 > Offset1);
6513   if ((Offset2 - Offset1) / 8 > 64)
6514     return false;
6515 
6516   unsigned Opc1 = Load1->getMachineOpcode();
6517   unsigned Opc2 = Load2->getMachineOpcode();
6518   if (Opc1 != Opc2)
6519     return false;  // FIXME: overly conservative?
6520 
6521   switch (Opc1) {
6522   default: break;
6523   case X86::LD_Fp32m:
6524   case X86::LD_Fp64m:
6525   case X86::LD_Fp80m:
6526   case X86::MMX_MOVD64rm:
6527   case X86::MMX_MOVQ64rm:
6528     return false;
6529   }
6530 
6531   EVT VT = Load1->getValueType(0);
6532   switch (VT.getSimpleVT().SimpleTy) {
6533   default:
6534     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6535     // have 16 of them to play with.
6536     if (Subtarget.is64Bit()) {
6537       if (NumLoads >= 3)
6538         return false;
6539     } else if (NumLoads) {
6540       return false;
6541     }
6542     break;
6543   case MVT::i8:
6544   case MVT::i16:
6545   case MVT::i32:
6546   case MVT::i64:
6547   case MVT::f32:
6548   case MVT::f64:
6549     if (NumLoads)
6550       return false;
6551     break;
6552   }
6553 
6554   return true;
6555 }
6556 
6557 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
6558                                           MachineInstr *Second) const {
6559   // Check if this processor supports macro-fusion. Since this is a minor
6560   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6561   // proxy for SandyBridge+.
6562   if (!Subtarget.hasAVX())
6563     return false;
6564 
6565   enum {
6566     FuseTest,
6567     FuseCmp,
6568     FuseInc
6569   } FuseKind;
6570 
6571   switch(Second->getOpcode()) {
6572   default:
6573     return false;
6574   case X86::JE_1:
6575   case X86::JNE_1:
6576   case X86::JL_1:
6577   case X86::JLE_1:
6578   case X86::JG_1:
6579   case X86::JGE_1:
6580     FuseKind = FuseInc;
6581     break;
6582   case X86::JB_1:
6583   case X86::JBE_1:
6584   case X86::JA_1:
6585   case X86::JAE_1:
6586     FuseKind = FuseCmp;
6587     break;
6588   case X86::JS_1:
6589   case X86::JNS_1:
6590   case X86::JP_1:
6591   case X86::JNP_1:
6592   case X86::JO_1:
6593   case X86::JNO_1:
6594     FuseKind = FuseTest;
6595     break;
6596   }
6597   switch (First->getOpcode()) {
6598   default:
6599     return false;
6600   case X86::TEST8rr:
6601   case X86::TEST16rr:
6602   case X86::TEST32rr:
6603   case X86::TEST64rr:
6604   case X86::TEST8ri:
6605   case X86::TEST16ri:
6606   case X86::TEST32ri:
6607   case X86::TEST32i32:
6608   case X86::TEST64i32:
6609   case X86::TEST64ri32:
6610   case X86::TEST8rm:
6611   case X86::TEST16rm:
6612   case X86::TEST32rm:
6613   case X86::TEST64rm:
6614   case X86::TEST8ri_NOREX:
6615   case X86::AND16i16:
6616   case X86::AND16ri:
6617   case X86::AND16ri8:
6618   case X86::AND16rm:
6619   case X86::AND16rr:
6620   case X86::AND32i32:
6621   case X86::AND32ri:
6622   case X86::AND32ri8:
6623   case X86::AND32rm:
6624   case X86::AND32rr:
6625   case X86::AND64i32:
6626   case X86::AND64ri32:
6627   case X86::AND64ri8:
6628   case X86::AND64rm:
6629   case X86::AND64rr:
6630   case X86::AND8i8:
6631   case X86::AND8ri:
6632   case X86::AND8rm:
6633   case X86::AND8rr:
6634     return true;
6635   case X86::CMP16i16:
6636   case X86::CMP16ri:
6637   case X86::CMP16ri8:
6638   case X86::CMP16rm:
6639   case X86::CMP16rr:
6640   case X86::CMP32i32:
6641   case X86::CMP32ri:
6642   case X86::CMP32ri8:
6643   case X86::CMP32rm:
6644   case X86::CMP32rr:
6645   case X86::CMP64i32:
6646   case X86::CMP64ri32:
6647   case X86::CMP64ri8:
6648   case X86::CMP64rm:
6649   case X86::CMP64rr:
6650   case X86::CMP8i8:
6651   case X86::CMP8ri:
6652   case X86::CMP8rm:
6653   case X86::CMP8rr:
6654   case X86::ADD16i16:
6655   case X86::ADD16ri:
6656   case X86::ADD16ri8:
6657   case X86::ADD16ri8_DB:
6658   case X86::ADD16ri_DB:
6659   case X86::ADD16rm:
6660   case X86::ADD16rr:
6661   case X86::ADD16rr_DB:
6662   case X86::ADD32i32:
6663   case X86::ADD32ri:
6664   case X86::ADD32ri8:
6665   case X86::ADD32ri8_DB:
6666   case X86::ADD32ri_DB:
6667   case X86::ADD32rm:
6668   case X86::ADD32rr:
6669   case X86::ADD32rr_DB:
6670   case X86::ADD64i32:
6671   case X86::ADD64ri32:
6672   case X86::ADD64ri32_DB:
6673   case X86::ADD64ri8:
6674   case X86::ADD64ri8_DB:
6675   case X86::ADD64rm:
6676   case X86::ADD64rr:
6677   case X86::ADD64rr_DB:
6678   case X86::ADD8i8:
6679   case X86::ADD8mi:
6680   case X86::ADD8mr:
6681   case X86::ADD8ri:
6682   case X86::ADD8rm:
6683   case X86::ADD8rr:
6684   case X86::SUB16i16:
6685   case X86::SUB16ri:
6686   case X86::SUB16ri8:
6687   case X86::SUB16rm:
6688   case X86::SUB16rr:
6689   case X86::SUB32i32:
6690   case X86::SUB32ri:
6691   case X86::SUB32ri8:
6692   case X86::SUB32rm:
6693   case X86::SUB32rr:
6694   case X86::SUB64i32:
6695   case X86::SUB64ri32:
6696   case X86::SUB64ri8:
6697   case X86::SUB64rm:
6698   case X86::SUB64rr:
6699   case X86::SUB8i8:
6700   case X86::SUB8ri:
6701   case X86::SUB8rm:
6702   case X86::SUB8rr:
6703     return FuseKind == FuseCmp || FuseKind == FuseInc;
6704   case X86::INC16r:
6705   case X86::INC32r:
6706   case X86::INC64r:
6707   case X86::INC8r:
6708   case X86::DEC16r:
6709   case X86::DEC32r:
6710   case X86::DEC64r:
6711   case X86::DEC8r:
6712     return FuseKind == FuseInc;
6713   }
6714 }
6715 
6716 bool X86InstrInfo::
6717 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6718   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6719   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6720   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
6721     return true;
6722   Cond[0].setImm(GetOppositeBranchCondition(CC));
6723   return false;
6724 }
6725 
6726 bool X86InstrInfo::
6727 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6728   // FIXME: Return false for x87 stack register classes for now. We can't
6729   // allow any loads of these registers before FpGet_ST0_80.
6730   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6731            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
6732 }
6733 
6734 /// Return a virtual register initialized with the
6735 /// the global base register value. Output instructions required to
6736 /// initialize the register in the function entry block, if necessary.
6737 ///
6738 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6739 ///
6740 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6741   assert(!Subtarget.is64Bit() &&
6742          "X86-64 PIC uses RIP relative addressing");
6743 
6744   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6745   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6746   if (GlobalBaseReg != 0)
6747     return GlobalBaseReg;
6748 
6749   // Create the register. The code to initialize it is inserted
6750   // later, by the CGBR pass (below).
6751   MachineRegisterInfo &RegInfo = MF->getRegInfo();
6752   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
6753   X86FI->setGlobalBaseReg(GlobalBaseReg);
6754   return GlobalBaseReg;
6755 }
6756 
6757 // These are the replaceable SSE instructions. Some of these have Int variants
6758 // that we don't include here. We don't want to replace instructions selected
6759 // by intrinsics.
6760 static const uint16_t ReplaceableInstrs[][3] = {
6761   //PackedSingle     PackedDouble    PackedInt
6762   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
6763   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
6764   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
6765   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
6766   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
6767   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr  },
6768   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
6769   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
6770   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
6771   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
6772   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
6773   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
6774   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
6775   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
6776   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
6777   // AVX 128-bit support
6778   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
6779   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
6780   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
6781   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
6782   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
6783   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr  },
6784   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6785   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
6786   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
6787   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
6788   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
6789   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
6790   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
6791   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
6792   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
6793   // AVX 256-bit support
6794   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
6795   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
6796   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
6797   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
6798   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
6799   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
6800 };
6801 
6802 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6803   //PackedSingle       PackedDouble       PackedInt
6804   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
6805   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
6806   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
6807   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
6808   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
6809   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
6810   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
6811   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
6812   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6813   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6814   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
6815   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
6816   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
6817   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
6818   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6819   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6820   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6821   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6822   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6823   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
6824 };
6825 
6826 // FIXME: Some shuffle and unpack instructions have equivalents in different
6827 // domains, but they require a bit more work than just switching opcodes.
6828 
6829 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
6830   for (const uint16_t (&Row)[3] : ReplaceableInstrs)
6831     if (Row[domain-1] == opcode)
6832       return Row;
6833   return nullptr;
6834 }
6835 
6836 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
6837   for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
6838     if (Row[domain-1] == opcode)
6839       return Row;
6840   return nullptr;
6841 }
6842 
6843 std::pair<uint16_t, uint16_t>
6844 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
6845   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6846   bool hasAVX2 = Subtarget.hasAVX2();
6847   uint16_t validDomains = 0;
6848   if (domain && lookup(MI->getOpcode(), domain))
6849     validDomains = 0xe;
6850   else if (domain && lookupAVX2(MI->getOpcode(), domain))
6851     validDomains = hasAVX2 ? 0xe : 0x6;
6852   return std::make_pair(domain, validDomains);
6853 }
6854 
6855 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
6856   assert(Domain>0 && Domain<4 && "Invalid execution domain");
6857   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6858   assert(dom && "Not an SSE instruction");
6859   const uint16_t *table = lookup(MI->getOpcode(), dom);
6860   if (!table) { // try the other table
6861     assert((Subtarget.hasAVX2() || Domain < 3) &&
6862            "256-bit vector operations only available in AVX2");
6863     table = lookupAVX2(MI->getOpcode(), dom);
6864   }
6865   assert(table && "Cannot change domain");
6866   MI->setDesc(get(table[Domain-1]));
6867 }
6868 
6869 /// Return the noop instruction to use for a noop.
6870 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
6871   NopInst.setOpcode(X86::NOOP);
6872 }
6873 
6874 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
6875 // In particular, getJumpInstrTableEntryBound must always return an upper bound
6876 // on the encoding lengths of the instructions generated by
6877 // getUnconditionalBranch and getTrap.
6878 void X86InstrInfo::getUnconditionalBranch(
6879     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
6880   Branch.setOpcode(X86::JMP_1);
6881   Branch.addOperand(MCOperand::createExpr(BranchTarget));
6882 }
6883 
6884 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
6885 // In particular, getJumpInstrTableEntryBound must always return an upper bound
6886 // on the encoding lengths of the instructions generated by
6887 // getUnconditionalBranch and getTrap.
6888 void X86InstrInfo::getTrap(MCInst &MI) const {
6889   MI.setOpcode(X86::TRAP);
6890 }
6891 
6892 // See getTrap and getUnconditionalBranch for conditions on the value returned
6893 // by this function.
6894 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
6895   // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
6896   // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
6897   return 5;
6898 }
6899 
6900 bool X86InstrInfo::isHighLatencyDef(int opc) const {
6901   switch (opc) {
6902   default: return false;
6903   case X86::DIVSDrm:
6904   case X86::DIVSDrm_Int:
6905   case X86::DIVSDrr:
6906   case X86::DIVSDrr_Int:
6907   case X86::DIVSSrm:
6908   case X86::DIVSSrm_Int:
6909   case X86::DIVSSrr:
6910   case X86::DIVSSrr_Int:
6911   case X86::SQRTPDm:
6912   case X86::SQRTPDr:
6913   case X86::SQRTPSm:
6914   case X86::SQRTPSr:
6915   case X86::SQRTSDm:
6916   case X86::SQRTSDm_Int:
6917   case X86::SQRTSDr:
6918   case X86::SQRTSDr_Int:
6919   case X86::SQRTSSm:
6920   case X86::SQRTSSm_Int:
6921   case X86::SQRTSSr:
6922   case X86::SQRTSSr_Int:
6923   // AVX instructions with high latency
6924   case X86::VDIVSDrm:
6925   case X86::VDIVSDrm_Int:
6926   case X86::VDIVSDrr:
6927   case X86::VDIVSDrr_Int:
6928   case X86::VDIVSSrm:
6929   case X86::VDIVSSrm_Int:
6930   case X86::VDIVSSrr:
6931   case X86::VDIVSSrr_Int:
6932   case X86::VSQRTPDm:
6933   case X86::VSQRTPDr:
6934   case X86::VSQRTPSm:
6935   case X86::VSQRTPSr:
6936   case X86::VSQRTSDm:
6937   case X86::VSQRTSDm_Int:
6938   case X86::VSQRTSDr:
6939   case X86::VSQRTSSm:
6940   case X86::VSQRTSSm_Int:
6941   case X86::VSQRTSSr:
6942   case X86::VSQRTPDZm:
6943   case X86::VSQRTPDZr:
6944   case X86::VSQRTPSZm:
6945   case X86::VSQRTPSZr:
6946   case X86::VSQRTSDZm:
6947   case X86::VSQRTSDZm_Int:
6948   case X86::VSQRTSDZr:
6949   case X86::VSQRTSSZm_Int:
6950   case X86::VSQRTSSZr:
6951   case X86::VSQRTSSZm:
6952   case X86::VDIVSDZrm:
6953   case X86::VDIVSDZrr:
6954   case X86::VDIVSSZrm:
6955   case X86::VDIVSSZrr:
6956 
6957   case X86::VGATHERQPSZrm:
6958   case X86::VGATHERQPDZrm:
6959   case X86::VGATHERDPDZrm:
6960   case X86::VGATHERDPSZrm:
6961   case X86::VPGATHERQDZrm:
6962   case X86::VPGATHERQQZrm:
6963   case X86::VPGATHERDDZrm:
6964   case X86::VPGATHERDQZrm:
6965   case X86::VSCATTERQPDZmr:
6966   case X86::VSCATTERQPSZmr:
6967   case X86::VSCATTERDPDZmr:
6968   case X86::VSCATTERDPSZmr:
6969   case X86::VPSCATTERQDZmr:
6970   case X86::VPSCATTERQQZmr:
6971   case X86::VPSCATTERDDZmr:
6972   case X86::VPSCATTERDQZmr:
6973     return true;
6974   }
6975 }
6976 
6977 bool X86InstrInfo::
6978 hasHighOperandLatency(const TargetSchedModel &SchedModel,
6979                       const MachineRegisterInfo *MRI,
6980                       const MachineInstr *DefMI, unsigned DefIdx,
6981                       const MachineInstr *UseMI, unsigned UseIdx) const {
6982   return isHighLatencyDef(DefMI->getOpcode());
6983 }
6984 
6985 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
6986                                            const MachineBasicBlock *MBB) const {
6987   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
6988          "Reassociation needs binary operators");
6989 
6990   // Integer binary math/logic instructions have a third source operand:
6991   // the EFLAGS register. That operand must be both defined here and never
6992   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
6993   // not change anything because rearranging the operands could affect other
6994   // instructions that depend on the exact status flags (zero, sign, etc.)
6995   // that are set by using these particular operands with this operation.
6996   if (Inst.getNumOperands() == 4) {
6997     assert(Inst.getOperand(3).isReg() &&
6998            Inst.getOperand(3).getReg() == X86::EFLAGS &&
6999            "Unexpected operand in reassociable instruction");
7000     if (!Inst.getOperand(3).isDead())
7001       return false;
7002   }
7003 
7004   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7005 }
7006 
7007 // TODO: There are many more machine instruction opcodes to match:
7008 //       1. Other data types (integer, vectors)
7009 //       2. Other math / logic operations (xor, or)
7010 //       3. Other forms of the same operation (intrinsics and other variants)
7011 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7012   switch (Inst.getOpcode()) {
7013   case X86::AND8rr:
7014   case X86::AND16rr:
7015   case X86::AND32rr:
7016   case X86::AND64rr:
7017   case X86::OR8rr:
7018   case X86::OR16rr:
7019   case X86::OR32rr:
7020   case X86::OR64rr:
7021   case X86::XOR8rr:
7022   case X86::XOR16rr:
7023   case X86::XOR32rr:
7024   case X86::XOR64rr:
7025   case X86::IMUL16rr:
7026   case X86::IMUL32rr:
7027   case X86::IMUL64rr:
7028   case X86::PANDrr:
7029   case X86::PORrr:
7030   case X86::PXORrr:
7031   case X86::VPANDrr:
7032   case X86::VPANDYrr:
7033   case X86::VPORrr:
7034   case X86::VPORYrr:
7035   case X86::VPXORrr:
7036   case X86::VPXORYrr:
7037   // Normal min/max instructions are not commutative because of NaN and signed
7038   // zero semantics, but these are. Thus, there's no need to check for global
7039   // relaxed math; the instructions themselves have the properties we need.
7040   case X86::MAXCPDrr:
7041   case X86::MAXCPSrr:
7042   case X86::MAXCSDrr:
7043   case X86::MAXCSSrr:
7044   case X86::MINCPDrr:
7045   case X86::MINCPSrr:
7046   case X86::MINCSDrr:
7047   case X86::MINCSSrr:
7048   case X86::VMAXCPDrr:
7049   case X86::VMAXCPSrr:
7050   case X86::VMAXCPDYrr:
7051   case X86::VMAXCPSYrr:
7052   case X86::VMAXCSDrr:
7053   case X86::VMAXCSSrr:
7054   case X86::VMINCPDrr:
7055   case X86::VMINCPSrr:
7056   case X86::VMINCPDYrr:
7057   case X86::VMINCPSYrr:
7058   case X86::VMINCSDrr:
7059   case X86::VMINCSSrr:
7060     return true;
7061   case X86::ADDPDrr:
7062   case X86::ADDPSrr:
7063   case X86::ADDSDrr:
7064   case X86::ADDSSrr:
7065   case X86::MULPDrr:
7066   case X86::MULPSrr:
7067   case X86::MULSDrr:
7068   case X86::MULSSrr:
7069   case X86::VADDPDrr:
7070   case X86::VADDPSrr:
7071   case X86::VADDPDYrr:
7072   case X86::VADDPSYrr:
7073   case X86::VADDSDrr:
7074   case X86::VADDSSrr:
7075   case X86::VMULPDrr:
7076   case X86::VMULPSrr:
7077   case X86::VMULPDYrr:
7078   case X86::VMULPSYrr:
7079   case X86::VMULSDrr:
7080   case X86::VMULSSrr:
7081     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7082   default:
7083     return false;
7084   }
7085 }
7086 
7087 /// This is an architecture-specific helper function of reassociateOps.
7088 /// Set special operand attributes for new instructions after reassociation.
7089 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7090                                          MachineInstr &OldMI2,
7091                                          MachineInstr &NewMI1,
7092                                          MachineInstr &NewMI2) const {
7093   // Integer instructions define an implicit EFLAGS source register operand as
7094   // the third source (fourth total) operand.
7095   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7096     return;
7097 
7098   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7099          "Unexpected instruction type for reassociation");
7100 
7101   MachineOperand &OldOp1 = OldMI1.getOperand(3);
7102   MachineOperand &OldOp2 = OldMI2.getOperand(3);
7103   MachineOperand &NewOp1 = NewMI1.getOperand(3);
7104   MachineOperand &NewOp2 = NewMI2.getOperand(3);
7105 
7106   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7107          "Must have dead EFLAGS operand in reassociable instruction");
7108   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7109          "Must have dead EFLAGS operand in reassociable instruction");
7110 
7111   (void)OldOp1;
7112   (void)OldOp2;
7113 
7114   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7115          "Unexpected operand in reassociable instruction");
7116   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7117          "Unexpected operand in reassociable instruction");
7118 
7119   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7120   // of this pass or other passes. The EFLAGS operands must be dead in these new
7121   // instructions because the EFLAGS operands in the original instructions must
7122   // be dead in order for reassociation to occur.
7123   NewOp1.setIsDead();
7124   NewOp2.setIsDead();
7125 }
7126 
7127 std::pair<unsigned, unsigned>
7128 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7129   return std::make_pair(TF, 0u);
7130 }
7131 
7132 ArrayRef<std::pair<unsigned, const char *>>
7133 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7134   using namespace X86II;
7135   static const std::pair<unsigned, const char *> TargetFlags[] = {
7136       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7137       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7138       {MO_GOT, "x86-got"},
7139       {MO_GOTOFF, "x86-gotoff"},
7140       {MO_GOTPCREL, "x86-gotpcrel"},
7141       {MO_PLT, "x86-plt"},
7142       {MO_TLSGD, "x86-tlsgd"},
7143       {MO_TLSLD, "x86-tlsld"},
7144       {MO_TLSLDM, "x86-tlsldm"},
7145       {MO_GOTTPOFF, "x86-gottpoff"},
7146       {MO_INDNTPOFF, "x86-indntpoff"},
7147       {MO_TPOFF, "x86-tpoff"},
7148       {MO_DTPOFF, "x86-dtpoff"},
7149       {MO_NTPOFF, "x86-ntpoff"},
7150       {MO_GOTNTPOFF, "x86-gotntpoff"},
7151       {MO_DLLIMPORT, "x86-dllimport"},
7152       {MO_DARWIN_STUB, "x86-darwin-stub"},
7153       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7154       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7155       {MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, "x86-darwin-hidden-nonlazy-pic-base"},
7156       {MO_TLVP, "x86-tlvp"},
7157       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7158       {MO_SECREL, "x86-secrel"}};
7159   return makeArrayRef(TargetFlags);
7160 }
7161 
7162 namespace {
7163   /// Create Global Base Reg pass. This initializes the PIC
7164   /// global base register for x86-32.
7165   struct CGBR : public MachineFunctionPass {
7166     static char ID;
7167     CGBR() : MachineFunctionPass(ID) {}
7168 
7169     bool runOnMachineFunction(MachineFunction &MF) override {
7170       const X86TargetMachine *TM =
7171         static_cast<const X86TargetMachine *>(&MF.getTarget());
7172       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7173 
7174       // Don't do anything if this is 64-bit as 64-bit PIC
7175       // uses RIP relative addressing.
7176       if (STI.is64Bit())
7177         return false;
7178 
7179       // Only emit a global base reg in PIC mode.
7180       if (TM->getRelocationModel() != Reloc::PIC_)
7181         return false;
7182 
7183       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7184       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7185 
7186       // If we didn't need a GlobalBaseReg, don't insert code.
7187       if (GlobalBaseReg == 0)
7188         return false;
7189 
7190       // Insert the set of GlobalBaseReg into the first MBB of the function
7191       MachineBasicBlock &FirstMBB = MF.front();
7192       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7193       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7194       MachineRegisterInfo &RegInfo = MF.getRegInfo();
7195       const X86InstrInfo *TII = STI.getInstrInfo();
7196 
7197       unsigned PC;
7198       if (STI.isPICStyleGOT())
7199         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7200       else
7201         PC = GlobalBaseReg;
7202 
7203       // Operand of MovePCtoStack is completely ignored by asm printer. It's
7204       // only used in JIT code emission as displacement to pc.
7205       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7206 
7207       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
7208       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7209       if (STI.isPICStyleGOT()) {
7210         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
7211         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7212           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7213                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
7214       }
7215 
7216       return true;
7217     }
7218 
7219     const char *getPassName() const override {
7220       return "X86 PIC Global Base Reg Initialization";
7221     }
7222 
7223     void getAnalysisUsage(AnalysisUsage &AU) const override {
7224       AU.setPreservesCFG();
7225       MachineFunctionPass::getAnalysisUsage(AU);
7226     }
7227   };
7228 }
7229 
7230 char CGBR::ID = 0;
7231 FunctionPass*
7232 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
7233 
7234 namespace {
7235   struct LDTLSCleanup : public MachineFunctionPass {
7236     static char ID;
7237     LDTLSCleanup() : MachineFunctionPass(ID) {}
7238 
7239     bool runOnMachineFunction(MachineFunction &MF) override {
7240       X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
7241       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7242         // No point folding accesses if there isn't at least two.
7243         return false;
7244       }
7245 
7246       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7247       return VisitNode(DT->getRootNode(), 0);
7248     }
7249 
7250     // Visit the dominator subtree rooted at Node in pre-order.
7251     // If TLSBaseAddrReg is non-null, then use that to replace any
7252     // TLS_base_addr instructions. Otherwise, create the register
7253     // when the first such instruction is seen, and then use it
7254     // as we encounter more instructions.
7255     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7256       MachineBasicBlock *BB = Node->getBlock();
7257       bool Changed = false;
7258 
7259       // Traverse the current block.
7260       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7261            ++I) {
7262         switch (I->getOpcode()) {
7263           case X86::TLS_base_addr32:
7264           case X86::TLS_base_addr64:
7265             if (TLSBaseAddrReg)
7266               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
7267             else
7268               I = SetRegister(I, &TLSBaseAddrReg);
7269             Changed = true;
7270             break;
7271           default:
7272             break;
7273         }
7274       }
7275 
7276       // Visit the children of this block in the dominator tree.
7277       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7278            I != E; ++I) {
7279         Changed |= VisitNode(*I, TLSBaseAddrReg);
7280       }
7281 
7282       return Changed;
7283     }
7284 
7285     // Replace the TLS_base_addr instruction I with a copy from
7286     // TLSBaseAddrReg, returning the new instruction.
7287     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
7288                                          unsigned TLSBaseAddrReg) {
7289       MachineFunction *MF = I->getParent()->getParent();
7290       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7291       const bool is64Bit = STI.is64Bit();
7292       const X86InstrInfo *TII = STI.getInstrInfo();
7293 
7294       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7295       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
7296                                    TII->get(TargetOpcode::COPY),
7297                                    is64Bit ? X86::RAX : X86::EAX)
7298                                    .addReg(TLSBaseAddrReg);
7299 
7300       // Erase the TLS_base_addr instruction.
7301       I->eraseFromParent();
7302 
7303       return Copy;
7304     }
7305 
7306     // Create a virtal register in *TLSBaseAddrReg, and populate it by
7307     // inserting a copy instruction after I. Returns the new instruction.
7308     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
7309       MachineFunction *MF = I->getParent()->getParent();
7310       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7311       const bool is64Bit = STI.is64Bit();
7312       const X86InstrInfo *TII = STI.getInstrInfo();
7313 
7314       // Create a virtual register for the TLS base address.
7315       MachineRegisterInfo &RegInfo = MF->getRegInfo();
7316       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7317                                                       ? &X86::GR64RegClass
7318                                                       : &X86::GR32RegClass);
7319 
7320       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7321       MachineInstr *Next = I->getNextNode();
7322       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
7323                                    TII->get(TargetOpcode::COPY),
7324                                    *TLSBaseAddrReg)
7325                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
7326 
7327       return Copy;
7328     }
7329 
7330     const char *getPassName() const override {
7331       return "Local Dynamic TLS Access Clean-up";
7332     }
7333 
7334     void getAnalysisUsage(AnalysisUsage &AU) const override {
7335       AU.setPreservesCFG();
7336       AU.addRequired<MachineDominatorTree>();
7337       MachineFunctionPass::getAnalysisUsage(AU);
7338     }
7339   };
7340 }
7341 
7342 char LDTLSCleanup::ID = 0;
7343 FunctionPass*
7344 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
7345