1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCExpr.h"
32 #include "llvm/MC/MCInst.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include <limits>
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "x86-instr-info"
43 
44 #define GET_INSTRINFO_CTOR_DTOR
45 #include "X86GenInstrInfo.inc"
46 
47 static cl::opt<bool>
48 NoFusing("disable-spill-fusing",
49          cl::desc("Disable fusing of spill code into instructions"));
50 static cl::opt<bool>
51 PrintFailedFusing("print-failed-fuse-candidates",
52                   cl::desc("Print instructions that the allocator wants to"
53                            " fuse, but the X86 backend currently can't"),
54                   cl::Hidden);
55 static cl::opt<bool>
56 ReMatPICStubLoad("remat-pic-stub-load",
57                  cl::desc("Re-materialize load from stub in PIC mode"),
58                  cl::init(false), cl::Hidden);
59 
60 enum {
61   // Select which memory operand is being unfolded.
62   // (stored in bits 0 - 3)
63   TB_INDEX_0    = 0,
64   TB_INDEX_1    = 1,
65   TB_INDEX_2    = 2,
66   TB_INDEX_3    = 3,
67   TB_INDEX_MASK = 0xf,
68 
69   // Do not insert the reverse map (MemOp -> RegOp) into the table.
70   // This may be needed because there is a many -> one mapping.
71   TB_NO_REVERSE   = 1 << 4,
72 
73   // Do not insert the forward map (RegOp -> MemOp) into the table.
74   // This is needed for Native Client, which prohibits branch
75   // instructions from using a memory operand.
76   TB_NO_FORWARD   = 1 << 5,
77 
78   TB_FOLDED_LOAD  = 1 << 6,
79   TB_FOLDED_STORE = 1 << 7,
80 
81   // Minimum alignment required for load/store.
82   // Used for RegOp->MemOp conversion.
83   // (stored in bits 8 - 15)
84   TB_ALIGN_SHIFT = 8,
85   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
86   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
87   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
88   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
89   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
90 };
91 
92 struct X86OpTblEntry {
93   uint16_t RegOp;
94   uint16_t MemOp;
95   uint16_t Flags;
96 };
97 
98 // Pin the vtable to this file.
99 void X86InstrInfo::anchor() {}
100 
101 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
102     : X86GenInstrInfo(
103           (STI.is64Bit() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
104           (STI.is64Bit() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
105       Subtarget(STI), RI(STI) {
106 
107   static const X86OpTblEntry OpTbl2Addr[] = {
108     { X86::ADC32ri,     X86::ADC32mi,    0 },
109     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
110     { X86::ADC32rr,     X86::ADC32mr,    0 },
111     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
112     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
113     { X86::ADC64rr,     X86::ADC64mr,    0 },
114     { X86::ADD16ri,     X86::ADD16mi,    0 },
115     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
116     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
117     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
118     { X86::ADD16rr,     X86::ADD16mr,    0 },
119     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
120     { X86::ADD32ri,     X86::ADD32mi,    0 },
121     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
122     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
123     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
124     { X86::ADD32rr,     X86::ADD32mr,    0 },
125     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
126     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
127     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
128     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
129     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
130     { X86::ADD64rr,     X86::ADD64mr,    0 },
131     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
132     { X86::ADD8ri,      X86::ADD8mi,     0 },
133     { X86::ADD8rr,      X86::ADD8mr,     0 },
134     { X86::AND16ri,     X86::AND16mi,    0 },
135     { X86::AND16ri8,    X86::AND16mi8,   0 },
136     { X86::AND16rr,     X86::AND16mr,    0 },
137     { X86::AND32ri,     X86::AND32mi,    0 },
138     { X86::AND32ri8,    X86::AND32mi8,   0 },
139     { X86::AND32rr,     X86::AND32mr,    0 },
140     { X86::AND64ri32,   X86::AND64mi32,  0 },
141     { X86::AND64ri8,    X86::AND64mi8,   0 },
142     { X86::AND64rr,     X86::AND64mr,    0 },
143     { X86::AND8ri,      X86::AND8mi,     0 },
144     { X86::AND8rr,      X86::AND8mr,     0 },
145     { X86::DEC16r,      X86::DEC16m,     0 },
146     { X86::DEC32r,      X86::DEC32m,     0 },
147     { X86::DEC64_16r,   X86::DEC64_16m,  0 },
148     { X86::DEC64_32r,   X86::DEC64_32m,  0 },
149     { X86::DEC64r,      X86::DEC64m,     0 },
150     { X86::DEC8r,       X86::DEC8m,      0 },
151     { X86::INC16r,      X86::INC16m,     0 },
152     { X86::INC32r,      X86::INC32m,     0 },
153     { X86::INC64_16r,   X86::INC64_16m,  0 },
154     { X86::INC64_32r,   X86::INC64_32m,  0 },
155     { X86::INC64r,      X86::INC64m,     0 },
156     { X86::INC8r,       X86::INC8m,      0 },
157     { X86::NEG16r,      X86::NEG16m,     0 },
158     { X86::NEG32r,      X86::NEG32m,     0 },
159     { X86::NEG64r,      X86::NEG64m,     0 },
160     { X86::NEG8r,       X86::NEG8m,      0 },
161     { X86::NOT16r,      X86::NOT16m,     0 },
162     { X86::NOT32r,      X86::NOT32m,     0 },
163     { X86::NOT64r,      X86::NOT64m,     0 },
164     { X86::NOT8r,       X86::NOT8m,      0 },
165     { X86::OR16ri,      X86::OR16mi,     0 },
166     { X86::OR16ri8,     X86::OR16mi8,    0 },
167     { X86::OR16rr,      X86::OR16mr,     0 },
168     { X86::OR32ri,      X86::OR32mi,     0 },
169     { X86::OR32ri8,     X86::OR32mi8,    0 },
170     { X86::OR32rr,      X86::OR32mr,     0 },
171     { X86::OR64ri32,    X86::OR64mi32,   0 },
172     { X86::OR64ri8,     X86::OR64mi8,    0 },
173     { X86::OR64rr,      X86::OR64mr,     0 },
174     { X86::OR8ri,       X86::OR8mi,      0 },
175     { X86::OR8rr,       X86::OR8mr,      0 },
176     { X86::ROL16r1,     X86::ROL16m1,    0 },
177     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
178     { X86::ROL16ri,     X86::ROL16mi,    0 },
179     { X86::ROL32r1,     X86::ROL32m1,    0 },
180     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
181     { X86::ROL32ri,     X86::ROL32mi,    0 },
182     { X86::ROL64r1,     X86::ROL64m1,    0 },
183     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
184     { X86::ROL64ri,     X86::ROL64mi,    0 },
185     { X86::ROL8r1,      X86::ROL8m1,     0 },
186     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
187     { X86::ROL8ri,      X86::ROL8mi,     0 },
188     { X86::ROR16r1,     X86::ROR16m1,    0 },
189     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
190     { X86::ROR16ri,     X86::ROR16mi,    0 },
191     { X86::ROR32r1,     X86::ROR32m1,    0 },
192     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
193     { X86::ROR32ri,     X86::ROR32mi,    0 },
194     { X86::ROR64r1,     X86::ROR64m1,    0 },
195     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
196     { X86::ROR64ri,     X86::ROR64mi,    0 },
197     { X86::ROR8r1,      X86::ROR8m1,     0 },
198     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
199     { X86::ROR8ri,      X86::ROR8mi,     0 },
200     { X86::SAR16r1,     X86::SAR16m1,    0 },
201     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
202     { X86::SAR16ri,     X86::SAR16mi,    0 },
203     { X86::SAR32r1,     X86::SAR32m1,    0 },
204     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
205     { X86::SAR32ri,     X86::SAR32mi,    0 },
206     { X86::SAR64r1,     X86::SAR64m1,    0 },
207     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
208     { X86::SAR64ri,     X86::SAR64mi,    0 },
209     { X86::SAR8r1,      X86::SAR8m1,     0 },
210     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
211     { X86::SAR8ri,      X86::SAR8mi,     0 },
212     { X86::SBB32ri,     X86::SBB32mi,    0 },
213     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
214     { X86::SBB32rr,     X86::SBB32mr,    0 },
215     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
216     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
217     { X86::SBB64rr,     X86::SBB64mr,    0 },
218     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
219     { X86::SHL16ri,     X86::SHL16mi,    0 },
220     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
221     { X86::SHL32ri,     X86::SHL32mi,    0 },
222     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
223     { X86::SHL64ri,     X86::SHL64mi,    0 },
224     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
225     { X86::SHL8ri,      X86::SHL8mi,     0 },
226     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
227     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
228     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
229     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
230     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
231     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
232     { X86::SHR16r1,     X86::SHR16m1,    0 },
233     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
234     { X86::SHR16ri,     X86::SHR16mi,    0 },
235     { X86::SHR32r1,     X86::SHR32m1,    0 },
236     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
237     { X86::SHR32ri,     X86::SHR32mi,    0 },
238     { X86::SHR64r1,     X86::SHR64m1,    0 },
239     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
240     { X86::SHR64ri,     X86::SHR64mi,    0 },
241     { X86::SHR8r1,      X86::SHR8m1,     0 },
242     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
243     { X86::SHR8ri,      X86::SHR8mi,     0 },
244     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
245     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
246     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
247     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
248     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
249     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
250     { X86::SUB16ri,     X86::SUB16mi,    0 },
251     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
252     { X86::SUB16rr,     X86::SUB16mr,    0 },
253     { X86::SUB32ri,     X86::SUB32mi,    0 },
254     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
255     { X86::SUB32rr,     X86::SUB32mr,    0 },
256     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
257     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
258     { X86::SUB64rr,     X86::SUB64mr,    0 },
259     { X86::SUB8ri,      X86::SUB8mi,     0 },
260     { X86::SUB8rr,      X86::SUB8mr,     0 },
261     { X86::XOR16ri,     X86::XOR16mi,    0 },
262     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
263     { X86::XOR16rr,     X86::XOR16mr,    0 },
264     { X86::XOR32ri,     X86::XOR32mi,    0 },
265     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
266     { X86::XOR32rr,     X86::XOR32mr,    0 },
267     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
268     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
269     { X86::XOR64rr,     X86::XOR64mr,    0 },
270     { X86::XOR8ri,      X86::XOR8mi,     0 },
271     { X86::XOR8rr,      X86::XOR8mr,     0 }
272   };
273 
274   for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
275     unsigned RegOp = OpTbl2Addr[i].RegOp;
276     unsigned MemOp = OpTbl2Addr[i].MemOp;
277     unsigned Flags = OpTbl2Addr[i].Flags;
278     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
279                   RegOp, MemOp,
280                   // Index 0, folded load and store, no alignment requirement.
281                   Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
282   }
283 
284   static const X86OpTblEntry OpTbl0[] = {
285     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
286     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
287     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
288     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
289     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
290     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
291     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
292     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
293     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
294     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
295     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
296     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
297     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
298     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
299     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
300     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
301     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
302     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
303     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
304     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
305     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
306     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
307     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
308     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
309     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
310     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
311     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
312     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
313     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
314     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
315     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
316     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
317     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
318     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
319     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
320     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
321     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
322     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
323     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
324     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
325     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
326     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
327     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
328     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
329     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
330     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
331     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
332     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
333     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
334     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
335     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
336     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
337     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
338     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
339     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
340     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
341     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
342     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
343     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
344     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
345     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
346     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
347     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
348     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
349     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
350     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
351     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
352     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
353     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
354     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
355     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
356     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
357     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
358     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
359     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
360     // AVX 128-bit versions of foldable instructions
361     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
362     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
363     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
364     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
365     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
366     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
367     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
368     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
369     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
370     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
371     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
372     // AVX 256-bit foldable instructions
373     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
374     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
375     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
376     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
377     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
378     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
379     // AVX-512 foldable instructions
380     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
381     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
382     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
383     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
384     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
385     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
386     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
387     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
388     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE }
389   };
390 
391   for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
392     unsigned RegOp      = OpTbl0[i].RegOp;
393     unsigned MemOp      = OpTbl0[i].MemOp;
394     unsigned Flags      = OpTbl0[i].Flags;
395     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
396                   RegOp, MemOp, TB_INDEX_0 | Flags);
397   }
398 
399   static const X86OpTblEntry OpTbl1[] = {
400     { X86::CMP16rr,         X86::CMP16rm,             0 },
401     { X86::CMP32rr,         X86::CMP32rm,             0 },
402     { X86::CMP64rr,         X86::CMP64rm,             0 },
403     { X86::CMP8rr,          X86::CMP8rm,              0 },
404     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
405     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
406     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
407     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
408     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
409     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
410     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
411     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
412     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
413     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
414     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
415     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
416     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
417     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
418     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
419     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
420     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
421     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
422     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
423     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
424     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
425     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
426     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
427     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
428     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
429     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
430     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
431     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
432     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
433     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
434     { X86::MOV16rr,         X86::MOV16rm,             0 },
435     { X86::MOV32rr,         X86::MOV32rm,             0 },
436     { X86::MOV64rr,         X86::MOV64rm,             0 },
437     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
438     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
439     { X86::MOV8rr,          X86::MOV8rm,              0 },
440     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
441     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
442     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
443     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
444     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
445     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
446     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
447     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
448     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
449     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
450     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
451     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
452     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
453     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
454     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
455     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
456     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
457     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
458     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
459     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
460     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
461     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
462     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
463     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
464     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
465     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
466     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
467     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
468     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
469     { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
470     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
471     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
472     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
473     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
474     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
475     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
476     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
477     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
478     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
479     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
480     { X86::TEST16rr,        X86::TEST16rm,            0 },
481     { X86::TEST32rr,        X86::TEST32rm,            0 },
482     { X86::TEST64rr,        X86::TEST64rm,            0 },
483     { X86::TEST8rr,         X86::TEST8rm,             0 },
484     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
485     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
486     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
487     // AVX 128-bit versions of foldable instructions
488     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
489     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
490     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
491     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
492     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
493     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
494     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
495     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
496     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
497     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
498     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
499     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
500     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
501     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
502     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
503     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
504     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
505     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
506     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
507     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
508     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
509     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
510     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
511     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
512     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
513     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
514     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
515     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
516     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
517     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
518     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
519     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
520     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
521     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
522     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
523     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
524     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
525     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
526     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
527     { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
528     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
529     { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
530     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
531     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
532     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
533     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
534     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
535 
536     // AVX 256-bit foldable instructions
537     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
538     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
539     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
540     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
541     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
542     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
543     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
544 
545     // AVX2 foldable instructions
546     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
547     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
548     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
549     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
550     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
551     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
552     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
553     { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
554     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
555     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
556     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
557     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
558     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
559 
560     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
561     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
562     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
563     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
564     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
565     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
566     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
567     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
568     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
569     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
570     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
571     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
572     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
573     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
574     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
575     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
576     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
577     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
578     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
579     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
580     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
581     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
582     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
583     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
584     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
585     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
586     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
587     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
588     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
589     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
590     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
591     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
592     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
593     { X86::RORX32ri,        X86::RORX32mi,            0 },
594     { X86::RORX64ri,        X86::RORX64mi,            0 },
595     { X86::SARX32rr,        X86::SARX32rm,            0 },
596     { X86::SARX64rr,        X86::SARX64rm,            0 },
597     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
598     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
599     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
600     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
601     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
602     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
603     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
604     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
605     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
606     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
607     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
608 
609     // AVX-512 foldable instructions
610     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
611     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
612     { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
613     { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
614     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
615     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
616     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
617     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
618     { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
619     { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
620     { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
621     { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
622 
623     // AES foldable instructions
624     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
625     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
626     { X86::VAESIMCrr,             X86::VAESIMCrm,             TB_ALIGN_16 },
627     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 }
628   };
629 
630   for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
631     unsigned RegOp = OpTbl1[i].RegOp;
632     unsigned MemOp = OpTbl1[i].MemOp;
633     unsigned Flags = OpTbl1[i].Flags;
634     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
635                   RegOp, MemOp,
636                   // Index 1, folded load
637                   Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
638   }
639 
640   static const X86OpTblEntry OpTbl2[] = {
641     { X86::ADC32rr,         X86::ADC32rm,       0 },
642     { X86::ADC64rr,         X86::ADC64rm,       0 },
643     { X86::ADD16rr,         X86::ADD16rm,       0 },
644     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
645     { X86::ADD32rr,         X86::ADD32rm,       0 },
646     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
647     { X86::ADD64rr,         X86::ADD64rm,       0 },
648     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
649     { X86::ADD8rr,          X86::ADD8rm,        0 },
650     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
651     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
652     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
653     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
654     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
655     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
656     { X86::AND16rr,         X86::AND16rm,       0 },
657     { X86::AND32rr,         X86::AND32rm,       0 },
658     { X86::AND64rr,         X86::AND64rm,       0 },
659     { X86::AND8rr,          X86::AND8rm,        0 },
660     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
661     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
662     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
663     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
664     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
665     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
666     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
667     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
668     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
669     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
670     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
671     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
672     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
673     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
674     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
675     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
676     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
677     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
678     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
679     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
680     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
681     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
682     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
683     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
684     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
685     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
686     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
687     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
688     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
689     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
690     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
691     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
692     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
693     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
694     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
695     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
696     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
697     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
698     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
699     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
700     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
701     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
702     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
703     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
704     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
705     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
706     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
707     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
708     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
709     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
710     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
711     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
712     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
713     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
714     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
715     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
716     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
717     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
718     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
719     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
720     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
721     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
722     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
723     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
724     { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
725     { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
726     { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
727     { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
728     { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
729     { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
730     { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
731     { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
732     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
733     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
734     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
735     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
736     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
737     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
738     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
739     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
740     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
741     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
742     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
743     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
744     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
745     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
746     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
747     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
748     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
749     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
750     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
751     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
752     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
753     { X86::MINSDrr,         X86::MINSDrm,       0 },
754     { X86::MINSSrr,         X86::MINSSrm,       0 },
755     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
756     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
757     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
758     { X86::MULSDrr,         X86::MULSDrm,       0 },
759     { X86::MULSSrr,         X86::MULSSrm,       0 },
760     { X86::OR16rr,          X86::OR16rm,        0 },
761     { X86::OR32rr,          X86::OR32rm,        0 },
762     { X86::OR64rr,          X86::OR64rm,        0 },
763     { X86::OR8rr,           X86::OR8rm,         0 },
764     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
765     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
766     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
767     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
768     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
769     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
770     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
771     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
772     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
773     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
774     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
775     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
776     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
777     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
778     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
779     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
780     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
781     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
782     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
783     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
784     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
785     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
786     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
787     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
788     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
789     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
790     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
791     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
792     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
793     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
794     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
795     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
796     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
797     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
798     { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
799     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
800     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
801     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
802     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
803     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
804     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
805     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
806     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
807     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
808     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
809     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
810     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
811     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
812     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
813     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
814     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
815     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
816     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
817     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
818     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
819     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
820     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
821     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
822     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
823     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
824     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
825     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
826     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
827     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
828     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
829     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
830     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
831     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
832     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
833     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
834     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
835     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
836     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
837     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
838     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
839     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
840     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
841     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
842     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
843     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
844     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
845     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
846     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
847     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
848     { X86::SBB32rr,         X86::SBB32rm,       0 },
849     { X86::SBB64rr,         X86::SBB64rm,       0 },
850     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
851     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
852     { X86::SUB16rr,         X86::SUB16rm,       0 },
853     { X86::SUB32rr,         X86::SUB32rm,       0 },
854     { X86::SUB64rr,         X86::SUB64rm,       0 },
855     { X86::SUB8rr,          X86::SUB8rm,        0 },
856     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
857     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
858     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
859     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
860     // FIXME: TEST*rr -> swapped operand of TEST*mr.
861     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
862     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
863     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
864     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
865     { X86::XOR16rr,         X86::XOR16rm,       0 },
866     { X86::XOR32rr,         X86::XOR32rm,       0 },
867     { X86::XOR64rr,         X86::XOR64rm,       0 },
868     { X86::XOR8rr,          X86::XOR8rm,        0 },
869     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
870     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
871     // AVX 128-bit versions of foldable instructions
872     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
873     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
874     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
875     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
876     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
877     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
878     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
879     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
880     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
881     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
882     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
883     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
884     { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQXrm,      0 },
885     { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       0 },
886     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
887     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
888     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
889     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
890     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
891     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
892     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
893     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
894     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
895     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
896     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
897     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
898     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
899     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
900     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
901     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
902     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
903     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
904     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
905     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
906     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
907     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
908     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
909     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
910     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
911     { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
912     { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
913     { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
914     { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
915     { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
916     { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
917     { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
918     { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
919     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
920     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
921     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
922     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
923     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
924     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
925     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
926     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
927     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
928     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
929     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
930     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
931     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
932     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
933     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
934     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
935     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
936     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
937     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
938     { X86::VORPDrr,           X86::VORPDrm,            0 },
939     { X86::VORPSrr,           X86::VORPSrm,            0 },
940     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
941     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
942     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
943     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
944     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
945     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
946     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
947     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
948     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
949     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
950     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
951     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
952     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
953     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
954     { X86::VPANDrr,           X86::VPANDrm,            0 },
955     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
956     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
957     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
958     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
959     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
960     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
961     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
962     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
963     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
964     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
965     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
966     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
967     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
968     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
969     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
970     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
971     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
972     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
973     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
974     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
975     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
976     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
977     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
978     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
979     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
980     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
981     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
982     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
983     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
984     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
985     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
986     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
987     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
988     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
989     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
990     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
991     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
992     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
993     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
994     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
995     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
996     { X86::VPORrr,            X86::VPORrm,             0 },
997     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
998     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
999     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
1000     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
1001     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
1002     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1003     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1004     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1005     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1006     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1007     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1008     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1009     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1010     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1011     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1012     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1013     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1014     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1015     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1016     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1017     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1018     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1019     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1020     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1021     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1022     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1023     { X86::VPXORrr,           X86::VPXORrm,            0 },
1024     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1025     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1026     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1027     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1028     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1029     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1030     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1031     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1032     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1033     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1034     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1035     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1036     // AVX 256-bit foldable instructions
1037     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1038     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1039     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1040     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1041     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1042     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1043     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1044     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1045     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1046     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1047     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1048     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1049     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1050     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1051     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1052     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1053     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1054     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1055     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1056     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1057     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1058     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1059     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1060     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1061     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1062     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1063     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1064     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1065     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1066     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1067     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1068     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1069     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1070     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1071     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1072     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1073     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1074     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1075     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1076     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1077     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1078     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1079     // AVX2 foldable instructions
1080     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1081     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1082     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1083     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1084     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1085     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1086     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1087     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1088     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1089     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1090     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1091     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1092     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1093     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1094     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1095     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1096     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1097     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1098     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1099     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1100     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1101     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1102     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1103     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1104     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1105     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1106     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1107     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1108     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1109     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1110     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1111     { X86::VPERMPDYri,        X86::VPERMPDYmi,         0 },
1112     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1113     { X86::VPERMQYri,         X86::VPERMQYmi,          0 },
1114     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1115     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1116     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1117     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1118     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1119     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1120     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1121     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1122     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1123     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1124     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1125     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1126     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1127     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1128     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1129     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1130     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1131     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1132     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1133     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1134     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1135     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1136     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1137     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1138     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1139     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1140     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1141     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1142     { X86::VPORYrr,           X86::VPORYrm,            0 },
1143     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1144     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1145     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1146     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1147     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1148     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1149     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1150     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1151     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1152     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1153     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1154     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1155     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1156     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1157     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1158     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1159     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1160     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1161     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1162     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1163     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1164     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1165     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1166     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1167     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1168     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1169     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1170     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1171     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1172     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1173     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1174     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1175     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1176     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1177     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1178     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1179     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1180     // FIXME: add AVX 256-bit foldable instructions
1181 
1182     // FMA4 foldable patterns
1183     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0           },
1184     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0           },
1185     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_16 },
1186     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_16 },
1187     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_32 },
1188     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_32 },
1189     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0           },
1190     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0           },
1191     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_16 },
1192     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_16 },
1193     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_32 },
1194     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_32 },
1195     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0           },
1196     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0           },
1197     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_16 },
1198     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_16 },
1199     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_32 },
1200     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_32 },
1201     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0           },
1202     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0           },
1203     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_16 },
1204     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_16 },
1205     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_32 },
1206     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_32 },
1207     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_16 },
1208     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_16 },
1209     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_32 },
1210     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_32 },
1211     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_16 },
1212     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_16 },
1213     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_32 },
1214     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_32 },
1215 
1216     // BMI/BMI2 foldable instructions
1217     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1218     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1219     { X86::MULX32rr,          X86::MULX32rm,            0 },
1220     { X86::MULX64rr,          X86::MULX64rm,            0 },
1221     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1222     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1223     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1224     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1225 
1226     // AVX-512 foldable instructions
1227     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1228     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1229     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1230     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1231     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1232     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1233     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1234     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1235     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1236     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1237     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1238     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1239     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1240     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1241     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1242     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1243     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1244     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1245     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1246     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1247     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1248     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1249     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1250     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1251     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1252     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1253     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1254     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1255     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1256     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1257     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1258     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1259     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1260     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1261     { X86::VALIGNQrri,        X86::VALIGNQrmi,          0 },
1262     { X86::VALIGNDrri,        X86::VALIGNDrmi,          0 },
1263     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1264 
1265     // AES foldable instructions
1266     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1267     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1268     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1269     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1270     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       TB_ALIGN_16 },
1271     { X86::VAESDECrr,         X86::VAESDECrm,           TB_ALIGN_16 },
1272     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       TB_ALIGN_16 },
1273     { X86::VAESENCrr,         X86::VAESENCrm,           TB_ALIGN_16 },
1274 
1275     // SHA foldable instructions
1276     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1277     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1278     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1279     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1280     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1281     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1282     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 },
1283   };
1284 
1285   for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1286     unsigned RegOp = OpTbl2[i].RegOp;
1287     unsigned MemOp = OpTbl2[i].MemOp;
1288     unsigned Flags = OpTbl2[i].Flags;
1289     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1290                   RegOp, MemOp,
1291                   // Index 2, folded load
1292                   Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1293   }
1294 
1295   static const X86OpTblEntry OpTbl3[] = {
1296     // FMA foldable instructions
1297     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1298     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1299     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1300     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1301     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1302     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1303 
1304     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1305     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1306     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1307     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1308     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1309     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1310     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1311     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1312     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1313     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1314     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1315     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1316 
1317     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1318     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1319     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1320     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1321     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1322     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1323 
1324     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1325     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1326     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1327     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1328     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1329     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1330     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1331     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1332     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1333     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1334     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1335     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1336 
1337     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1338     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1339     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1340     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1341     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1342     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1343 
1344     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1345     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1346     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1347     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1348     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1349     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1350     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1351     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1352     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1353     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1354     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1355     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1356 
1357     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1358     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1359     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1360     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1361     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1362     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1363 
1364     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1365     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1366     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1367     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1368     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1369     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1370     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1371     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1372     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1373     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1374     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1375     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1376 
1377     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1378     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1379     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1380     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1381     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1382     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1383     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1384     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1385     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1386     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1387     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1388     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1389 
1390     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1391     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1392     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1393     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1394     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1395     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1396     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1397     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1398     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1399     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1400     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1401     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1402 
1403     // FMA4 foldable patterns
1404     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1405     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1406     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1407     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1408     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1409     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1410     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1411     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1412     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1413     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1414     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1415     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1416     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1417     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1418     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1419     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1420     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1421     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1422     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1423     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1424     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1425     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1426     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1427     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1428     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1429     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1430     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1431     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1432     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1433     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1434     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1435     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1436     // AVX-512 VPERMI instructions with 3 source operands.
1437     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1438     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1439     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1440     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1441     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1442     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1443     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1444     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 }
1445   };
1446 
1447   for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1448     unsigned RegOp = OpTbl3[i].RegOp;
1449     unsigned MemOp = OpTbl3[i].MemOp;
1450     unsigned Flags = OpTbl3[i].Flags;
1451     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1452                   RegOp, MemOp,
1453                   // Index 3, folded load
1454                   Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1455   }
1456 
1457 }
1458 
1459 void
1460 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1461                             MemOp2RegOpTableType &M2RTable,
1462                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
1463     if ((Flags & TB_NO_FORWARD) == 0) {
1464       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1465       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1466     }
1467     if ((Flags & TB_NO_REVERSE) == 0) {
1468       assert(!M2RTable.count(MemOp) &&
1469            "Duplicated entries in unfolding maps?");
1470       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1471     }
1472 }
1473 
1474 bool
1475 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1476                                     unsigned &SrcReg, unsigned &DstReg,
1477                                     unsigned &SubIdx) const {
1478   switch (MI.getOpcode()) {
1479   default: break;
1480   case X86::MOVSX16rr8:
1481   case X86::MOVZX16rr8:
1482   case X86::MOVSX32rr8:
1483   case X86::MOVZX32rr8:
1484   case X86::MOVSX64rr8:
1485     if (!Subtarget.is64Bit())
1486       // It's not always legal to reference the low 8-bit of the larger
1487       // register in 32-bit mode.
1488       return false;
1489   case X86::MOVSX32rr16:
1490   case X86::MOVZX32rr16:
1491   case X86::MOVSX64rr16:
1492   case X86::MOVSX64rr32: {
1493     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1494       // Be conservative.
1495       return false;
1496     SrcReg = MI.getOperand(1).getReg();
1497     DstReg = MI.getOperand(0).getReg();
1498     switch (MI.getOpcode()) {
1499     default: llvm_unreachable("Unreachable!");
1500     case X86::MOVSX16rr8:
1501     case X86::MOVZX16rr8:
1502     case X86::MOVSX32rr8:
1503     case X86::MOVZX32rr8:
1504     case X86::MOVSX64rr8:
1505       SubIdx = X86::sub_8bit;
1506       break;
1507     case X86::MOVSX32rr16:
1508     case X86::MOVZX32rr16:
1509     case X86::MOVSX64rr16:
1510       SubIdx = X86::sub_16bit;
1511       break;
1512     case X86::MOVSX64rr32:
1513       SubIdx = X86::sub_32bit;
1514       break;
1515     }
1516     return true;
1517   }
1518   }
1519   return false;
1520 }
1521 
1522 /// isFrameOperand - Return true and the FrameIndex if the specified
1523 /// operand and follow operands form a reference to the stack frame.
1524 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1525                                   int &FrameIndex) const {
1526   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
1527       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
1528       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
1529       MI->getOperand(Op+X86::AddrDisp).isImm() &&
1530       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
1531       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
1532       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
1533     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
1534     return true;
1535   }
1536   return false;
1537 }
1538 
1539 static bool isFrameLoadOpcode(int Opcode) {
1540   switch (Opcode) {
1541   default:
1542     return false;
1543   case X86::MOV8rm:
1544   case X86::MOV16rm:
1545   case X86::MOV32rm:
1546   case X86::MOV64rm:
1547   case X86::LD_Fp64m:
1548   case X86::MOVSSrm:
1549   case X86::MOVSDrm:
1550   case X86::MOVAPSrm:
1551   case X86::MOVAPDrm:
1552   case X86::MOVDQArm:
1553   case X86::VMOVSSrm:
1554   case X86::VMOVSDrm:
1555   case X86::VMOVAPSrm:
1556   case X86::VMOVAPDrm:
1557   case X86::VMOVDQArm:
1558   case X86::VMOVAPSYrm:
1559   case X86::VMOVAPDYrm:
1560   case X86::VMOVDQAYrm:
1561   case X86::MMX_MOVD64rm:
1562   case X86::MMX_MOVQ64rm:
1563   case X86::VMOVAPSZrm:
1564   case X86::VMOVUPSZrm:
1565     return true;
1566   }
1567 }
1568 
1569 static bool isFrameStoreOpcode(int Opcode) {
1570   switch (Opcode) {
1571   default: break;
1572   case X86::MOV8mr:
1573   case X86::MOV16mr:
1574   case X86::MOV32mr:
1575   case X86::MOV64mr:
1576   case X86::ST_FpP64m:
1577   case X86::MOVSSmr:
1578   case X86::MOVSDmr:
1579   case X86::MOVAPSmr:
1580   case X86::MOVAPDmr:
1581   case X86::MOVDQAmr:
1582   case X86::VMOVSSmr:
1583   case X86::VMOVSDmr:
1584   case X86::VMOVAPSmr:
1585   case X86::VMOVAPDmr:
1586   case X86::VMOVDQAmr:
1587   case X86::VMOVAPSYmr:
1588   case X86::VMOVAPDYmr:
1589   case X86::VMOVDQAYmr:
1590   case X86::VMOVUPSZmr:
1591   case X86::VMOVAPSZmr:
1592   case X86::MMX_MOVD64mr:
1593   case X86::MMX_MOVQ64mr:
1594   case X86::MMX_MOVNTQmr:
1595     return true;
1596   }
1597   return false;
1598 }
1599 
1600 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1601                                            int &FrameIndex) const {
1602   if (isFrameLoadOpcode(MI->getOpcode()))
1603     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1604       return MI->getOperand(0).getReg();
1605   return 0;
1606 }
1607 
1608 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1609                                                  int &FrameIndex) const {
1610   if (isFrameLoadOpcode(MI->getOpcode())) {
1611     unsigned Reg;
1612     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1613       return Reg;
1614     // Check for post-frame index elimination operations
1615     const MachineMemOperand *Dummy;
1616     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1617   }
1618   return 0;
1619 }
1620 
1621 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1622                                           int &FrameIndex) const {
1623   if (isFrameStoreOpcode(MI->getOpcode()))
1624     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1625         isFrameOperand(MI, 0, FrameIndex))
1626       return MI->getOperand(X86::AddrNumOperands).getReg();
1627   return 0;
1628 }
1629 
1630 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1631                                                 int &FrameIndex) const {
1632   if (isFrameStoreOpcode(MI->getOpcode())) {
1633     unsigned Reg;
1634     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1635       return Reg;
1636     // Check for post-frame index elimination operations
1637     const MachineMemOperand *Dummy;
1638     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1639   }
1640   return 0;
1641 }
1642 
1643 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1644 /// X86::MOVPC32r.
1645 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1646   // Don't waste compile time scanning use-def chains of physregs.
1647   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1648     return false;
1649   bool isPICBase = false;
1650   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
1651          E = MRI.def_instr_end(); I != E; ++I) {
1652     MachineInstr *DefMI = &*I;
1653     if (DefMI->getOpcode() != X86::MOVPC32r)
1654       return false;
1655     assert(!isPICBase && "More than one PIC base?");
1656     isPICBase = true;
1657   }
1658   return isPICBase;
1659 }
1660 
1661 bool
1662 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1663                                                 AliasAnalysis *AA) const {
1664   switch (MI->getOpcode()) {
1665   default: break;
1666   case X86::MOV8rm:
1667   case X86::MOV16rm:
1668   case X86::MOV32rm:
1669   case X86::MOV64rm:
1670   case X86::LD_Fp64m:
1671   case X86::MOVSSrm:
1672   case X86::MOVSDrm:
1673   case X86::MOVAPSrm:
1674   case X86::MOVUPSrm:
1675   case X86::MOVAPDrm:
1676   case X86::MOVDQArm:
1677   case X86::MOVDQUrm:
1678   case X86::VMOVSSrm:
1679   case X86::VMOVSDrm:
1680   case X86::VMOVAPSrm:
1681   case X86::VMOVUPSrm:
1682   case X86::VMOVAPDrm:
1683   case X86::VMOVDQArm:
1684   case X86::VMOVDQUrm:
1685   case X86::VMOVAPSYrm:
1686   case X86::VMOVUPSYrm:
1687   case X86::VMOVAPDYrm:
1688   case X86::VMOVDQAYrm:
1689   case X86::VMOVDQUYrm:
1690   case X86::MMX_MOVD64rm:
1691   case X86::MMX_MOVQ64rm:
1692   case X86::FsVMOVAPSrm:
1693   case X86::FsVMOVAPDrm:
1694   case X86::FsMOVAPSrm:
1695   case X86::FsMOVAPDrm: {
1696     // Loads from constant pools are trivially rematerializable.
1697     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
1698         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1699         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1700         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1701         MI->isInvariantLoad(AA)) {
1702       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1703       if (BaseReg == 0 || BaseReg == X86::RIP)
1704         return true;
1705       // Allow re-materialization of PIC load.
1706       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
1707         return false;
1708       const MachineFunction &MF = *MI->getParent()->getParent();
1709       const MachineRegisterInfo &MRI = MF.getRegInfo();
1710       return regIsPICBase(BaseReg, MRI);
1711     }
1712     return false;
1713   }
1714 
1715   case X86::LEA32r:
1716   case X86::LEA64r: {
1717     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1718         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1719         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1720         !MI->getOperand(1+X86::AddrDisp).isReg()) {
1721       // lea fi#, lea GV, etc. are all rematerializable.
1722       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
1723         return true;
1724       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1725       if (BaseReg == 0)
1726         return true;
1727       // Allow re-materialization of lea PICBase + x.
1728       const MachineFunction &MF = *MI->getParent()->getParent();
1729       const MachineRegisterInfo &MRI = MF.getRegInfo();
1730       return regIsPICBase(BaseReg, MRI);
1731     }
1732     return false;
1733   }
1734   }
1735 
1736   // All other instructions marked M_REMATERIALIZABLE are always trivially
1737   // rematerializable.
1738   return true;
1739 }
1740 
1741 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1742                                          MachineBasicBlock::iterator I) const {
1743   MachineBasicBlock::iterator E = MBB.end();
1744 
1745   // For compile time consideration, if we are not able to determine the
1746   // safety after visiting 4 instructions in each direction, we will assume
1747   // it's not safe.
1748   MachineBasicBlock::iterator Iter = I;
1749   for (unsigned i = 0; Iter != E && i < 4; ++i) {
1750     bool SeenDef = false;
1751     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1752       MachineOperand &MO = Iter->getOperand(j);
1753       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1754         SeenDef = true;
1755       if (!MO.isReg())
1756         continue;
1757       if (MO.getReg() == X86::EFLAGS) {
1758         if (MO.isUse())
1759           return false;
1760         SeenDef = true;
1761       }
1762     }
1763 
1764     if (SeenDef)
1765       // This instruction defines EFLAGS, no need to look any further.
1766       return true;
1767     ++Iter;
1768     // Skip over DBG_VALUE.
1769     while (Iter != E && Iter->isDebugValue())
1770       ++Iter;
1771   }
1772 
1773   // It is safe to clobber EFLAGS at the end of a block of no successor has it
1774   // live in.
1775   if (Iter == E) {
1776     for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1777            SE = MBB.succ_end(); SI != SE; ++SI)
1778       if ((*SI)->isLiveIn(X86::EFLAGS))
1779         return false;
1780     return true;
1781   }
1782 
1783   MachineBasicBlock::iterator B = MBB.begin();
1784   Iter = I;
1785   for (unsigned i = 0; i < 4; ++i) {
1786     // If we make it to the beginning of the block, it's safe to clobber
1787     // EFLAGS iff EFLAGS is not live-in.
1788     if (Iter == B)
1789       return !MBB.isLiveIn(X86::EFLAGS);
1790 
1791     --Iter;
1792     // Skip over DBG_VALUE.
1793     while (Iter != B && Iter->isDebugValue())
1794       --Iter;
1795 
1796     bool SawKill = false;
1797     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1798       MachineOperand &MO = Iter->getOperand(j);
1799       // A register mask may clobber EFLAGS, but we should still look for a
1800       // live EFLAGS def.
1801       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1802         SawKill = true;
1803       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1804         if (MO.isDef()) return MO.isDead();
1805         if (MO.isKill()) SawKill = true;
1806       }
1807     }
1808 
1809     if (SawKill)
1810       // This instruction kills EFLAGS and doesn't redefine it, so
1811       // there's no need to look further.
1812       return true;
1813   }
1814 
1815   // Conservative answer.
1816   return false;
1817 }
1818 
1819 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1820                                  MachineBasicBlock::iterator I,
1821                                  unsigned DestReg, unsigned SubIdx,
1822                                  const MachineInstr *Orig,
1823                                  const TargetRegisterInfo &TRI) const {
1824   // MOV32r0 is implemented with a xor which clobbers condition code.
1825   // Re-materialize it as movri instructions to avoid side effects.
1826   unsigned Opc = Orig->getOpcode();
1827   if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
1828     DebugLoc DL = Orig->getDebugLoc();
1829     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
1830       .addImm(0);
1831   } else {
1832     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1833     MBB.insert(I, MI);
1834   }
1835 
1836   MachineInstr *NewMI = std::prev(I);
1837   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1838 }
1839 
1840 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1841 /// is not marked dead.
1842 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1843   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1844     MachineOperand &MO = MI->getOperand(i);
1845     if (MO.isReg() && MO.isDef() &&
1846         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1847       return true;
1848     }
1849   }
1850   return false;
1851 }
1852 
1853 /// getTruncatedShiftCount - check whether the shift count for a machine operand
1854 /// is non-zero.
1855 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
1856                                               unsigned ShiftAmtOperandIdx) {
1857   // The shift count is six bits with the REX.W prefix and five bits without.
1858   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1859   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
1860   return Imm & ShiftCountMask;
1861 }
1862 
1863 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
1864 /// can be represented by a LEA instruction.
1865 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1866   // Left shift instructions can be transformed into load-effective-address
1867   // instructions if we can encode them appropriately.
1868   // A LEA instruction utilizes a SIB byte to encode it's scale factor.
1869   // The SIB.scale field is two bits wide which means that we can encode any
1870   // shift amount less than 4.
1871   return ShAmt < 4 && ShAmt > 0;
1872 }
1873 
1874 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
1875                                   unsigned Opc, bool AllowSP,
1876                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
1877                                   MachineOperand &ImplicitOp) const {
1878   MachineFunction &MF = *MI->getParent()->getParent();
1879   const TargetRegisterClass *RC;
1880   if (AllowSP) {
1881     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1882   } else {
1883     RC = Opc != X86::LEA32r ?
1884       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1885   }
1886   unsigned SrcReg = Src.getReg();
1887 
1888   // For both LEA64 and LEA32 the register already has essentially the right
1889   // type (32-bit or 64-bit) we may just need to forbid SP.
1890   if (Opc != X86::LEA64_32r) {
1891     NewSrc = SrcReg;
1892     isKill = Src.isKill();
1893     isUndef = Src.isUndef();
1894 
1895     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
1896         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1897       return false;
1898 
1899     return true;
1900   }
1901 
1902   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1903   // another we need to add 64-bit registers to the final MI.
1904   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1905     ImplicitOp = Src;
1906     ImplicitOp.setImplicit();
1907 
1908     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
1909     MachineBasicBlock::LivenessQueryResult LQR =
1910       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
1911 
1912     switch (LQR) {
1913     case MachineBasicBlock::LQR_Unknown:
1914       // We can't give sane liveness flags to the instruction, abandon LEA
1915       // formation.
1916       return false;
1917     case MachineBasicBlock::LQR_Live:
1918       isKill = MI->killsRegister(SrcReg);
1919       isUndef = false;
1920       break;
1921     default:
1922       // The physreg itself is dead, so we have to use it as an <undef>.
1923       isKill = false;
1924       isUndef = true;
1925       break;
1926     }
1927   } else {
1928     // Virtual register of the wrong class, we have to create a temporary 64-bit
1929     // vreg to feed into the LEA.
1930     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1931     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1932             get(TargetOpcode::COPY))
1933       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1934         .addOperand(Src);
1935 
1936     // Which is obviously going to be dead after we're done with it.
1937     isKill = true;
1938     isUndef = false;
1939   }
1940 
1941   // We've set all the parameters without issue.
1942   return true;
1943 }
1944 
1945 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1946 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1947 /// to a 32-bit superregister and then truncating back down to a 16-bit
1948 /// subregister.
1949 MachineInstr *
1950 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1951                                            MachineFunction::iterator &MFI,
1952                                            MachineBasicBlock::iterator &MBBI,
1953                                            LiveVariables *LV) const {
1954   MachineInstr *MI = MBBI;
1955   unsigned Dest = MI->getOperand(0).getReg();
1956   unsigned Src = MI->getOperand(1).getReg();
1957   bool isDead = MI->getOperand(0).isDead();
1958   bool isKill = MI->getOperand(1).isKill();
1959 
1960   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1961   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1962   unsigned Opc, leaInReg;
1963   if (Subtarget.is64Bit()) {
1964     Opc = X86::LEA64_32r;
1965     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1966   } else {
1967     Opc = X86::LEA32r;
1968     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1969   }
1970 
1971   // Build and insert into an implicit UNDEF value. This is OK because
1972   // well be shifting and then extracting the lower 16-bits.
1973   // This has the potential to cause partial register stall. e.g.
1974   //   movw    (%rbp,%rcx,2), %dx
1975   //   leal    -65(%rdx), %esi
1976   // But testing has shown this *does* help performance in 64-bit mode (at
1977   // least on modern x86 machines).
1978   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1979   MachineInstr *InsMI =
1980     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1981     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1982     .addReg(Src, getKillRegState(isKill));
1983 
1984   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1985                                     get(Opc), leaOutReg);
1986   switch (MIOpc) {
1987   default: llvm_unreachable("Unreachable!");
1988   case X86::SHL16ri: {
1989     unsigned ShAmt = MI->getOperand(2).getImm();
1990     MIB.addReg(0).addImm(1 << ShAmt)
1991        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1992     break;
1993   }
1994   case X86::INC16r:
1995   case X86::INC64_16r:
1996     addRegOffset(MIB, leaInReg, true, 1);
1997     break;
1998   case X86::DEC16r:
1999   case X86::DEC64_16r:
2000     addRegOffset(MIB, leaInReg, true, -1);
2001     break;
2002   case X86::ADD16ri:
2003   case X86::ADD16ri8:
2004   case X86::ADD16ri_DB:
2005   case X86::ADD16ri8_DB:
2006     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2007     break;
2008   case X86::ADD16rr:
2009   case X86::ADD16rr_DB: {
2010     unsigned Src2 = MI->getOperand(2).getReg();
2011     bool isKill2 = MI->getOperand(2).isKill();
2012     unsigned leaInReg2 = 0;
2013     MachineInstr *InsMI2 = nullptr;
2014     if (Src == Src2) {
2015       // ADD16rr %reg1028<kill>, %reg1028
2016       // just a single insert_subreg.
2017       addRegReg(MIB, leaInReg, true, leaInReg, false);
2018     } else {
2019       if (Subtarget.is64Bit())
2020         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2021       else
2022         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2023       // Build and insert into an implicit UNDEF value. This is OK because
2024       // well be shifting and then extracting the lower 16-bits.
2025       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2026       InsMI2 =
2027         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2028         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2029         .addReg(Src2, getKillRegState(isKill2));
2030       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2031     }
2032     if (LV && isKill2 && InsMI2)
2033       LV->replaceKillInstruction(Src2, MI, InsMI2);
2034     break;
2035   }
2036   }
2037 
2038   MachineInstr *NewMI = MIB;
2039   MachineInstr *ExtMI =
2040     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2041     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2042     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2043 
2044   if (LV) {
2045     // Update live variables
2046     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2047     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2048     if (isKill)
2049       LV->replaceKillInstruction(Src, MI, InsMI);
2050     if (isDead)
2051       LV->replaceKillInstruction(Dest, MI, ExtMI);
2052   }
2053 
2054   return ExtMI;
2055 }
2056 
2057 /// convertToThreeAddress - This method must be implemented by targets that
2058 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2059 /// may be able to convert a two-address instruction into a true
2060 /// three-address instruction on demand.  This allows the X86 target (for
2061 /// example) to convert ADD and SHL instructions into LEA instructions if they
2062 /// would require register copies due to two-addressness.
2063 ///
2064 /// This method returns a null pointer if the transformation cannot be
2065 /// performed, otherwise it returns the new instruction.
2066 ///
2067 MachineInstr *
2068 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2069                                     MachineBasicBlock::iterator &MBBI,
2070                                     LiveVariables *LV) const {
2071   MachineInstr *MI = MBBI;
2072 
2073   // The following opcodes also sets the condition code register(s). Only
2074   // convert them to equivalent lea if the condition code register def's
2075   // are dead!
2076   if (hasLiveCondCodeDef(MI))
2077     return nullptr;
2078 
2079   MachineFunction &MF = *MI->getParent()->getParent();
2080   // All instructions input are two-addr instructions.  Get the known operands.
2081   const MachineOperand &Dest = MI->getOperand(0);
2082   const MachineOperand &Src = MI->getOperand(1);
2083 
2084   MachineInstr *NewMI = nullptr;
2085   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2086   // we have better subtarget support, enable the 16-bit LEA generation here.
2087   // 16-bit LEA is also slow on Core2.
2088   bool DisableLEA16 = true;
2089   bool is64Bit = Subtarget.is64Bit();
2090 
2091   unsigned MIOpc = MI->getOpcode();
2092   switch (MIOpc) {
2093   case X86::SHUFPSrri: {
2094     assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
2095     if (!Subtarget.hasSSE2()) return nullptr;
2096 
2097     unsigned B = MI->getOperand(1).getReg();
2098     unsigned C = MI->getOperand(2).getReg();
2099     if (B != C) return nullptr;
2100     unsigned M = MI->getOperand(3).getImm();
2101     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2102       .addOperand(Dest).addOperand(Src).addImm(M);
2103     break;
2104   }
2105   case X86::SHUFPDrri: {
2106     assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
2107     if (!Subtarget.hasSSE2()) return nullptr;
2108 
2109     unsigned B = MI->getOperand(1).getReg();
2110     unsigned C = MI->getOperand(2).getReg();
2111     if (B != C) return nullptr;
2112     unsigned M = MI->getOperand(3).getImm();
2113 
2114     // Convert to PSHUFD mask.
2115     M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
2116 
2117     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2118       .addOperand(Dest).addOperand(Src).addImm(M);
2119     break;
2120   }
2121   case X86::SHL64ri: {
2122     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2123     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2124     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2125 
2126     // LEA can't handle RSP.
2127     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2128         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2129                                            &X86::GR64_NOSPRegClass))
2130       return nullptr;
2131 
2132     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2133       .addOperand(Dest)
2134       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2135     break;
2136   }
2137   case X86::SHL32ri: {
2138     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2139     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2140     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2141 
2142     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2143 
2144     // LEA can't handle ESP.
2145     bool isKill, isUndef;
2146     unsigned SrcReg;
2147     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2148     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2149                         SrcReg, isKill, isUndef, ImplicitOp))
2150       return nullptr;
2151 
2152     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2153       .addOperand(Dest)
2154       .addReg(0).addImm(1 << ShAmt)
2155       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2156       .addImm(0).addReg(0);
2157     if (ImplicitOp.getReg() != 0)
2158       MIB.addOperand(ImplicitOp);
2159     NewMI = MIB;
2160 
2161     break;
2162   }
2163   case X86::SHL16ri: {
2164     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2165     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2166     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2167 
2168     if (DisableLEA16)
2169       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2170     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2171       .addOperand(Dest)
2172       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2173     break;
2174   }
2175   default: {
2176 
2177     switch (MIOpc) {
2178     default: return nullptr;
2179     case X86::INC64r:
2180     case X86::INC32r:
2181     case X86::INC64_32r: {
2182       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2183       unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2184         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2185       bool isKill, isUndef;
2186       unsigned SrcReg;
2187       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2188       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2189                           SrcReg, isKill, isUndef, ImplicitOp))
2190         return nullptr;
2191 
2192       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2193           .addOperand(Dest)
2194           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2195       if (ImplicitOp.getReg() != 0)
2196         MIB.addOperand(ImplicitOp);
2197 
2198       NewMI = addOffset(MIB, 1);
2199       break;
2200     }
2201     case X86::INC16r:
2202     case X86::INC64_16r:
2203       if (DisableLEA16)
2204         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2205                        : nullptr;
2206       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2207       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2208                         .addOperand(Dest).addOperand(Src), 1);
2209       break;
2210     case X86::DEC64r:
2211     case X86::DEC32r:
2212     case X86::DEC64_32r: {
2213       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2214       unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2215         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2216 
2217       bool isKill, isUndef;
2218       unsigned SrcReg;
2219       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2220       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2221                           SrcReg, isKill, isUndef, ImplicitOp))
2222         return nullptr;
2223 
2224       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2225           .addOperand(Dest)
2226           .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2227       if (ImplicitOp.getReg() != 0)
2228         MIB.addOperand(ImplicitOp);
2229 
2230       NewMI = addOffset(MIB, -1);
2231 
2232       break;
2233     }
2234     case X86::DEC16r:
2235     case X86::DEC64_16r:
2236       if (DisableLEA16)
2237         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2238                        : nullptr;
2239       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2240       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2241                         .addOperand(Dest).addOperand(Src), -1);
2242       break;
2243     case X86::ADD64rr:
2244     case X86::ADD64rr_DB:
2245     case X86::ADD32rr:
2246     case X86::ADD32rr_DB: {
2247       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2248       unsigned Opc;
2249       if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2250         Opc = X86::LEA64r;
2251       else
2252         Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2253 
2254       bool isKill, isUndef;
2255       unsigned SrcReg;
2256       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2257       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2258                           SrcReg, isKill, isUndef, ImplicitOp))
2259         return nullptr;
2260 
2261       const MachineOperand &Src2 = MI->getOperand(2);
2262       bool isKill2, isUndef2;
2263       unsigned SrcReg2;
2264       MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2265       if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2266                           SrcReg2, isKill2, isUndef2, ImplicitOp2))
2267         return nullptr;
2268 
2269       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2270         .addOperand(Dest);
2271       if (ImplicitOp.getReg() != 0)
2272         MIB.addOperand(ImplicitOp);
2273       if (ImplicitOp2.getReg() != 0)
2274         MIB.addOperand(ImplicitOp2);
2275 
2276       NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2277 
2278       // Preserve undefness of the operands.
2279       NewMI->getOperand(1).setIsUndef(isUndef);
2280       NewMI->getOperand(3).setIsUndef(isUndef2);
2281 
2282       if (LV && Src2.isKill())
2283         LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2284       break;
2285     }
2286     case X86::ADD16rr:
2287     case X86::ADD16rr_DB: {
2288       if (DisableLEA16)
2289         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2290                        : nullptr;
2291       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2292       unsigned Src2 = MI->getOperand(2).getReg();
2293       bool isKill2 = MI->getOperand(2).isKill();
2294       NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2295                         .addOperand(Dest),
2296                         Src.getReg(), Src.isKill(), Src2, isKill2);
2297 
2298       // Preserve undefness of the operands.
2299       bool isUndef = MI->getOperand(1).isUndef();
2300       bool isUndef2 = MI->getOperand(2).isUndef();
2301       NewMI->getOperand(1).setIsUndef(isUndef);
2302       NewMI->getOperand(3).setIsUndef(isUndef2);
2303 
2304       if (LV && isKill2)
2305         LV->replaceKillInstruction(Src2, MI, NewMI);
2306       break;
2307     }
2308     case X86::ADD64ri32:
2309     case X86::ADD64ri8:
2310     case X86::ADD64ri32_DB:
2311     case X86::ADD64ri8_DB:
2312       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2313       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2314                         .addOperand(Dest).addOperand(Src),
2315                         MI->getOperand(2).getImm());
2316       break;
2317     case X86::ADD32ri:
2318     case X86::ADD32ri8:
2319     case X86::ADD32ri_DB:
2320     case X86::ADD32ri8_DB: {
2321       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2322       unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2323 
2324       bool isKill, isUndef;
2325       unsigned SrcReg;
2326       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2327       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2328                           SrcReg, isKill, isUndef, ImplicitOp))
2329         return nullptr;
2330 
2331       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2332           .addOperand(Dest)
2333           .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2334       if (ImplicitOp.getReg() != 0)
2335         MIB.addOperand(ImplicitOp);
2336 
2337       NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2338       break;
2339     }
2340     case X86::ADD16ri:
2341     case X86::ADD16ri8:
2342     case X86::ADD16ri_DB:
2343     case X86::ADD16ri8_DB:
2344       if (DisableLEA16)
2345         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2346                        : nullptr;
2347       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2348       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2349                         .addOperand(Dest).addOperand(Src),
2350                         MI->getOperand(2).getImm());
2351       break;
2352     }
2353   }
2354   }
2355 
2356   if (!NewMI) return nullptr;
2357 
2358   if (LV) {  // Update live variables
2359     if (Src.isKill())
2360       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2361     if (Dest.isDead())
2362       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2363   }
2364 
2365   MFI->insert(MBBI, NewMI);          // Insert the new inst
2366   return NewMI;
2367 }
2368 
2369 /// commuteInstruction - We have a few instructions that must be hacked on to
2370 /// commute them.
2371 ///
2372 MachineInstr *
2373 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2374   switch (MI->getOpcode()) {
2375   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2376   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2377   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2378   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2379   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2380   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2381     unsigned Opc;
2382     unsigned Size;
2383     switch (MI->getOpcode()) {
2384     default: llvm_unreachable("Unreachable!");
2385     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2386     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2387     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2388     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2389     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2390     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2391     }
2392     unsigned Amt = MI->getOperand(3).getImm();
2393     if (NewMI) {
2394       MachineFunction &MF = *MI->getParent()->getParent();
2395       MI = MF.CloneMachineInstr(MI);
2396       NewMI = false;
2397     }
2398     MI->setDesc(get(Opc));
2399     MI->getOperand(3).setImm(Size-Amt);
2400     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2401   }
2402   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
2403   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2404   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
2405   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2406   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2407   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
2408   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
2409   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2410   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2411   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
2412   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
2413   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2414   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
2415   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2416   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
2417   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2418     unsigned Opc;
2419     switch (MI->getOpcode()) {
2420     default: llvm_unreachable("Unreachable!");
2421     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2422     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2423     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2424     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2425     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2426     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2427     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2428     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2429     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2430     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2431     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2432     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2433     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2434     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2435     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2436     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2437     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2438     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2439     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2440     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2441     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2442     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2443     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2444     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2445     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2446     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2447     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2448     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2449     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2450     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2451     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2452     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2453     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2454     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2455     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2456     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2457     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2458     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2459     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2460     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2461     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2462     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2463     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2464     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2465     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2466     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2467     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2468     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2469     }
2470     if (NewMI) {
2471       MachineFunction &MF = *MI->getParent()->getParent();
2472       MI = MF.CloneMachineInstr(MI);
2473       NewMI = false;
2474     }
2475     MI->setDesc(get(Opc));
2476     // Fallthrough intended.
2477   }
2478   default:
2479     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2480   }
2481 }
2482 
2483 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
2484                                          unsigned &SrcOpIdx2) const {
2485   switch (MI->getOpcode()) {
2486     case X86::VFMADDPDr231r:
2487     case X86::VFMADDPSr231r:
2488     case X86::VFMADDSDr231r:
2489     case X86::VFMADDSSr231r:
2490     case X86::VFMSUBPDr231r:
2491     case X86::VFMSUBPSr231r:
2492     case X86::VFMSUBSDr231r:
2493     case X86::VFMSUBSSr231r:
2494     case X86::VFNMADDPDr231r:
2495     case X86::VFNMADDPSr231r:
2496     case X86::VFNMADDSDr231r:
2497     case X86::VFNMADDSSr231r:
2498     case X86::VFNMSUBPDr231r:
2499     case X86::VFNMSUBPSr231r:
2500     case X86::VFNMSUBSDr231r:
2501     case X86::VFNMSUBSSr231r:
2502     case X86::VFMADDPDr231rY:
2503     case X86::VFMADDPSr231rY:
2504     case X86::VFMSUBPDr231rY:
2505     case X86::VFMSUBPSr231rY:
2506     case X86::VFNMADDPDr231rY:
2507     case X86::VFNMADDPSr231rY:
2508     case X86::VFNMSUBPDr231rY:
2509     case X86::VFNMSUBPSr231rY:
2510       SrcOpIdx1 = 2;
2511       SrcOpIdx2 = 3;
2512       return true;
2513     default:
2514       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2515   }
2516 }
2517 
2518 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2519   switch (BrOpc) {
2520   default: return X86::COND_INVALID;
2521   case X86::JE_4:  return X86::COND_E;
2522   case X86::JNE_4: return X86::COND_NE;
2523   case X86::JL_4:  return X86::COND_L;
2524   case X86::JLE_4: return X86::COND_LE;
2525   case X86::JG_4:  return X86::COND_G;
2526   case X86::JGE_4: return X86::COND_GE;
2527   case X86::JB_4:  return X86::COND_B;
2528   case X86::JBE_4: return X86::COND_BE;
2529   case X86::JA_4:  return X86::COND_A;
2530   case X86::JAE_4: return X86::COND_AE;
2531   case X86::JS_4:  return X86::COND_S;
2532   case X86::JNS_4: return X86::COND_NS;
2533   case X86::JP_4:  return X86::COND_P;
2534   case X86::JNP_4: return X86::COND_NP;
2535   case X86::JO_4:  return X86::COND_O;
2536   case X86::JNO_4: return X86::COND_NO;
2537   }
2538 }
2539 
2540 /// getCondFromSETOpc - return condition code of a SET opcode.
2541 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2542   switch (Opc) {
2543   default: return X86::COND_INVALID;
2544   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
2545   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2546   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
2547   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2548   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
2549   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
2550   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2551   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
2552   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2553   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2554   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2555   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2556   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2557   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
2558   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
2559   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
2560   }
2561 }
2562 
2563 /// getCondFromCmovOpc - return condition code of a CMov opcode.
2564 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2565   switch (Opc) {
2566   default: return X86::COND_INVALID;
2567   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
2568   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
2569     return X86::COND_A;
2570   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2571   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2572     return X86::COND_AE;
2573   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
2574   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
2575     return X86::COND_B;
2576   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2577   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2578     return X86::COND_BE;
2579   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
2580   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
2581     return X86::COND_E;
2582   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
2583   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
2584     return X86::COND_G;
2585   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2586   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2587     return X86::COND_GE;
2588   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
2589   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
2590     return X86::COND_L;
2591   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2592   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2593     return X86::COND_LE;
2594   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2595   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2596     return X86::COND_NE;
2597   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2598   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2599     return X86::COND_NO;
2600   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2601   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2602     return X86::COND_NP;
2603   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2604   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2605     return X86::COND_NS;
2606   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
2607   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
2608     return X86::COND_O;
2609   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
2610   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
2611     return X86::COND_P;
2612   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
2613   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
2614     return X86::COND_S;
2615   }
2616 }
2617 
2618 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2619   switch (CC) {
2620   default: llvm_unreachable("Illegal condition code!");
2621   case X86::COND_E:  return X86::JE_4;
2622   case X86::COND_NE: return X86::JNE_4;
2623   case X86::COND_L:  return X86::JL_4;
2624   case X86::COND_LE: return X86::JLE_4;
2625   case X86::COND_G:  return X86::JG_4;
2626   case X86::COND_GE: return X86::JGE_4;
2627   case X86::COND_B:  return X86::JB_4;
2628   case X86::COND_BE: return X86::JBE_4;
2629   case X86::COND_A:  return X86::JA_4;
2630   case X86::COND_AE: return X86::JAE_4;
2631   case X86::COND_S:  return X86::JS_4;
2632   case X86::COND_NS: return X86::JNS_4;
2633   case X86::COND_P:  return X86::JP_4;
2634   case X86::COND_NP: return X86::JNP_4;
2635   case X86::COND_O:  return X86::JO_4;
2636   case X86::COND_NO: return X86::JNO_4;
2637   }
2638 }
2639 
2640 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2641 /// e.g. turning COND_E to COND_NE.
2642 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2643   switch (CC) {
2644   default: llvm_unreachable("Illegal condition code!");
2645   case X86::COND_E:  return X86::COND_NE;
2646   case X86::COND_NE: return X86::COND_E;
2647   case X86::COND_L:  return X86::COND_GE;
2648   case X86::COND_LE: return X86::COND_G;
2649   case X86::COND_G:  return X86::COND_LE;
2650   case X86::COND_GE: return X86::COND_L;
2651   case X86::COND_B:  return X86::COND_AE;
2652   case X86::COND_BE: return X86::COND_A;
2653   case X86::COND_A:  return X86::COND_BE;
2654   case X86::COND_AE: return X86::COND_B;
2655   case X86::COND_S:  return X86::COND_NS;
2656   case X86::COND_NS: return X86::COND_S;
2657   case X86::COND_P:  return X86::COND_NP;
2658   case X86::COND_NP: return X86::COND_P;
2659   case X86::COND_O:  return X86::COND_NO;
2660   case X86::COND_NO: return X86::COND_O;
2661   }
2662 }
2663 
2664 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2665 /// the condition code if we modify the instructions such that flags are
2666 /// set by MI(b,a).
2667 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2668   switch (CC) {
2669   default: return X86::COND_INVALID;
2670   case X86::COND_E:  return X86::COND_E;
2671   case X86::COND_NE: return X86::COND_NE;
2672   case X86::COND_L:  return X86::COND_G;
2673   case X86::COND_LE: return X86::COND_GE;
2674   case X86::COND_G:  return X86::COND_L;
2675   case X86::COND_GE: return X86::COND_LE;
2676   case X86::COND_B:  return X86::COND_A;
2677   case X86::COND_BE: return X86::COND_AE;
2678   case X86::COND_A:  return X86::COND_B;
2679   case X86::COND_AE: return X86::COND_BE;
2680   }
2681 }
2682 
2683 /// getSETFromCond - Return a set opcode for the given condition and
2684 /// whether it has memory operand.
2685 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
2686   static const uint16_t Opc[16][2] = {
2687     { X86::SETAr,  X86::SETAm  },
2688     { X86::SETAEr, X86::SETAEm },
2689     { X86::SETBr,  X86::SETBm  },
2690     { X86::SETBEr, X86::SETBEm },
2691     { X86::SETEr,  X86::SETEm  },
2692     { X86::SETGr,  X86::SETGm  },
2693     { X86::SETGEr, X86::SETGEm },
2694     { X86::SETLr,  X86::SETLm  },
2695     { X86::SETLEr, X86::SETLEm },
2696     { X86::SETNEr, X86::SETNEm },
2697     { X86::SETNOr, X86::SETNOm },
2698     { X86::SETNPr, X86::SETNPm },
2699     { X86::SETNSr, X86::SETNSm },
2700     { X86::SETOr,  X86::SETOm  },
2701     { X86::SETPr,  X86::SETPm  },
2702     { X86::SETSr,  X86::SETSm  }
2703   };
2704 
2705   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
2706   return Opc[CC][HasMemoryOperand ? 1 : 0];
2707 }
2708 
2709 /// getCMovFromCond - Return a cmov opcode for the given condition,
2710 /// register size in bytes, and operand type.
2711 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
2712                               bool HasMemoryOperand) {
2713   static const uint16_t Opc[32][3] = {
2714     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
2715     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2716     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
2717     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2718     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
2719     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
2720     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2721     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
2722     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2723     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2724     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2725     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2726     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2727     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
2728     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
2729     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
2730     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
2731     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2732     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
2733     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2734     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
2735     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
2736     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2737     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
2738     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2739     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2740     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2741     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2742     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2743     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
2744     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
2745     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
2746   };
2747 
2748   assert(CC < 16 && "Can only handle standard cond codes");
2749   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2750   switch(RegBytes) {
2751   default: llvm_unreachable("Illegal register size!");
2752   case 2: return Opc[Idx][0];
2753   case 4: return Opc[Idx][1];
2754   case 8: return Opc[Idx][2];
2755   }
2756 }
2757 
2758 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2759   if (!MI->isTerminator()) return false;
2760 
2761   // Conditional branch is a special case.
2762   if (MI->isBranch() && !MI->isBarrier())
2763     return true;
2764   if (!MI->isPredicable())
2765     return true;
2766   return !isPredicated(MI);
2767 }
2768 
2769 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2770                                  MachineBasicBlock *&TBB,
2771                                  MachineBasicBlock *&FBB,
2772                                  SmallVectorImpl<MachineOperand> &Cond,
2773                                  bool AllowModify) const {
2774   // Start from the bottom of the block and work up, examining the
2775   // terminator instructions.
2776   MachineBasicBlock::iterator I = MBB.end();
2777   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2778   while (I != MBB.begin()) {
2779     --I;
2780     if (I->isDebugValue())
2781       continue;
2782 
2783     // Working from the bottom, when we see a non-terminator instruction, we're
2784     // done.
2785     if (!isUnpredicatedTerminator(I))
2786       break;
2787 
2788     // A terminator that isn't a branch can't easily be handled by this
2789     // analysis.
2790     if (!I->isBranch())
2791       return true;
2792 
2793     // Handle unconditional branches.
2794     if (I->getOpcode() == X86::JMP_4) {
2795       UnCondBrIter = I;
2796 
2797       if (!AllowModify) {
2798         TBB = I->getOperand(0).getMBB();
2799         continue;
2800       }
2801 
2802       // If the block has any instructions after a JMP, delete them.
2803       while (std::next(I) != MBB.end())
2804         std::next(I)->eraseFromParent();
2805 
2806       Cond.clear();
2807       FBB = nullptr;
2808 
2809       // Delete the JMP if it's equivalent to a fall-through.
2810       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2811         TBB = nullptr;
2812         I->eraseFromParent();
2813         I = MBB.end();
2814         UnCondBrIter = MBB.end();
2815         continue;
2816       }
2817 
2818       // TBB is used to indicate the unconditional destination.
2819       TBB = I->getOperand(0).getMBB();
2820       continue;
2821     }
2822 
2823     // Handle conditional branches.
2824     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2825     if (BranchCode == X86::COND_INVALID)
2826       return true;  // Can't handle indirect branch.
2827 
2828     // Working from the bottom, handle the first conditional branch.
2829     if (Cond.empty()) {
2830       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2831       if (AllowModify && UnCondBrIter != MBB.end() &&
2832           MBB.isLayoutSuccessor(TargetBB)) {
2833         // If we can modify the code and it ends in something like:
2834         //
2835         //     jCC L1
2836         //     jmp L2
2837         //   L1:
2838         //     ...
2839         //   L2:
2840         //
2841         // Then we can change this to:
2842         //
2843         //     jnCC L2
2844         //   L1:
2845         //     ...
2846         //   L2:
2847         //
2848         // Which is a bit more efficient.
2849         // We conditionally jump to the fall-through block.
2850         BranchCode = GetOppositeBranchCondition(BranchCode);
2851         unsigned JNCC = GetCondBranchFromCond(BranchCode);
2852         MachineBasicBlock::iterator OldInst = I;
2853 
2854         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2855           .addMBB(UnCondBrIter->getOperand(0).getMBB());
2856         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2857           .addMBB(TargetBB);
2858 
2859         OldInst->eraseFromParent();
2860         UnCondBrIter->eraseFromParent();
2861 
2862         // Restart the analysis.
2863         UnCondBrIter = MBB.end();
2864         I = MBB.end();
2865         continue;
2866       }
2867 
2868       FBB = TBB;
2869       TBB = I->getOperand(0).getMBB();
2870       Cond.push_back(MachineOperand::CreateImm(BranchCode));
2871       continue;
2872     }
2873 
2874     // Handle subsequent conditional branches. Only handle the case where all
2875     // conditional branches branch to the same destination and their condition
2876     // opcodes fit one of the special multi-branch idioms.
2877     assert(Cond.size() == 1);
2878     assert(TBB);
2879 
2880     // Only handle the case where all conditional branches branch to the same
2881     // destination.
2882     if (TBB != I->getOperand(0).getMBB())
2883       return true;
2884 
2885     // If the conditions are the same, we can leave them alone.
2886     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2887     if (OldBranchCode == BranchCode)
2888       continue;
2889 
2890     // If they differ, see if they fit one of the known patterns. Theoretically,
2891     // we could handle more patterns here, but we shouldn't expect to see them
2892     // if instruction selection has done a reasonable job.
2893     if ((OldBranchCode == X86::COND_NP &&
2894          BranchCode == X86::COND_E) ||
2895         (OldBranchCode == X86::COND_E &&
2896          BranchCode == X86::COND_NP))
2897       BranchCode = X86::COND_NP_OR_E;
2898     else if ((OldBranchCode == X86::COND_P &&
2899               BranchCode == X86::COND_NE) ||
2900              (OldBranchCode == X86::COND_NE &&
2901               BranchCode == X86::COND_P))
2902       BranchCode = X86::COND_NE_OR_P;
2903     else
2904       return true;
2905 
2906     // Update the MachineOperand.
2907     Cond[0].setImm(BranchCode);
2908   }
2909 
2910   return false;
2911 }
2912 
2913 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2914   MachineBasicBlock::iterator I = MBB.end();
2915   unsigned Count = 0;
2916 
2917   while (I != MBB.begin()) {
2918     --I;
2919     if (I->isDebugValue())
2920       continue;
2921     if (I->getOpcode() != X86::JMP_4 &&
2922         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2923       break;
2924     // Remove the branch.
2925     I->eraseFromParent();
2926     I = MBB.end();
2927     ++Count;
2928   }
2929 
2930   return Count;
2931 }
2932 
2933 unsigned
2934 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2935                            MachineBasicBlock *FBB,
2936                            const SmallVectorImpl<MachineOperand> &Cond,
2937                            DebugLoc DL) const {
2938   // Shouldn't be a fall through.
2939   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2940   assert((Cond.size() == 1 || Cond.size() == 0) &&
2941          "X86 branch conditions have one component!");
2942 
2943   if (Cond.empty()) {
2944     // Unconditional branch?
2945     assert(!FBB && "Unconditional branch with multiple successors!");
2946     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2947     return 1;
2948   }
2949 
2950   // Conditional branch.
2951   unsigned Count = 0;
2952   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2953   switch (CC) {
2954   case X86::COND_NP_OR_E:
2955     // Synthesize NP_OR_E with two branches.
2956     BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2957     ++Count;
2958     BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2959     ++Count;
2960     break;
2961   case X86::COND_NE_OR_P:
2962     // Synthesize NE_OR_P with two branches.
2963     BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2964     ++Count;
2965     BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2966     ++Count;
2967     break;
2968   default: {
2969     unsigned Opc = GetCondBranchFromCond(CC);
2970     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2971     ++Count;
2972   }
2973   }
2974   if (FBB) {
2975     // Two-way Conditional branch. Insert the second branch.
2976     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2977     ++Count;
2978   }
2979   return Count;
2980 }
2981 
2982 bool X86InstrInfo::
2983 canInsertSelect(const MachineBasicBlock &MBB,
2984                 const SmallVectorImpl<MachineOperand> &Cond,
2985                 unsigned TrueReg, unsigned FalseReg,
2986                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2987   // Not all subtargets have cmov instructions.
2988   if (!Subtarget.hasCMov())
2989     return false;
2990   if (Cond.size() != 1)
2991     return false;
2992   // We cannot do the composite conditions, at least not in SSA form.
2993   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2994     return false;
2995 
2996   // Check register classes.
2997   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2998   const TargetRegisterClass *RC =
2999     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3000   if (!RC)
3001     return false;
3002 
3003   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3004   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3005       X86::GR32RegClass.hasSubClassEq(RC) ||
3006       X86::GR64RegClass.hasSubClassEq(RC)) {
3007     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3008     // Bridge. Probably Ivy Bridge as well.
3009     CondCycles = 2;
3010     TrueCycles = 2;
3011     FalseCycles = 2;
3012     return true;
3013   }
3014 
3015   // Can't do vectors.
3016   return false;
3017 }
3018 
3019 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3020                                 MachineBasicBlock::iterator I, DebugLoc DL,
3021                                 unsigned DstReg,
3022                                 const SmallVectorImpl<MachineOperand> &Cond,
3023                                 unsigned TrueReg, unsigned FalseReg) const {
3024    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3025    assert(Cond.size() == 1 && "Invalid Cond array");
3026    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
3027                                   MRI.getRegClass(DstReg)->getSize(),
3028                                   false/*HasMemoryOperand*/);
3029    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3030 }
3031 
3032 /// isHReg - Test if the given register is a physical h register.
3033 static bool isHReg(unsigned Reg) {
3034   return X86::GR8_ABCD_HRegClass.contains(Reg);
3035 }
3036 
3037 // Try and copy between VR128/VR64 and GR64 registers.
3038 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3039                                         const X86Subtarget &Subtarget) {
3040 
3041   // SrcReg(VR128) -> DestReg(GR64)
3042   // SrcReg(VR64)  -> DestReg(GR64)
3043   // SrcReg(GR64)  -> DestReg(VR128)
3044   // SrcReg(GR64)  -> DestReg(VR64)
3045 
3046   bool HasAVX = Subtarget.hasAVX();
3047   bool HasAVX512 = Subtarget.hasAVX512();
3048   if (X86::GR64RegClass.contains(DestReg)) {
3049     if (X86::VR128XRegClass.contains(SrcReg))
3050       // Copy from a VR128 register to a GR64 register.
3051       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3052                                                X86::MOVPQIto64rr);
3053     if (X86::VR64RegClass.contains(SrcReg))
3054       // Copy from a VR64 register to a GR64 register.
3055       return X86::MOVSDto64rr;
3056   } else if (X86::GR64RegClass.contains(SrcReg)) {
3057     // Copy from a GR64 register to a VR128 register.
3058     if (X86::VR128XRegClass.contains(DestReg))
3059       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3060                                                X86::MOV64toPQIrr);
3061     // Copy from a GR64 register to a VR64 register.
3062     if (X86::VR64RegClass.contains(DestReg))
3063       return X86::MOV64toSDrr;
3064   }
3065 
3066   // SrcReg(FR32) -> DestReg(GR32)
3067   // SrcReg(GR32) -> DestReg(FR32)
3068 
3069   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3070     // Copy from a FR32 register to a GR32 register.
3071     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3072 
3073   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3074     // Copy from a GR32 register to a FR32 register.
3075     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3076   return 0;
3077 }
3078 
3079 inline static bool MaskRegClassContains(unsigned Reg) {
3080   return X86::VK8RegClass.contains(Reg) ||
3081          X86::VK16RegClass.contains(Reg) ||
3082          X86::VK32RegClass.contains(Reg) ||
3083          X86::VK64RegClass.contains(Reg) ||
3084          X86::VK1RegClass.contains(Reg);
3085 }
3086 static
3087 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3088   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3089       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3090       X86::VR512RegClass.contains(DestReg, SrcReg)) {
3091      DestReg = get512BitSuperRegister(DestReg);
3092      SrcReg = get512BitSuperRegister(SrcReg);
3093      return X86::VMOVAPSZrr;
3094   }
3095   if (MaskRegClassContains(DestReg) &&
3096       MaskRegClassContains(SrcReg))
3097     return X86::KMOVWkk;
3098   if (MaskRegClassContains(DestReg) &&
3099       (X86::GR32RegClass.contains(SrcReg) ||
3100        X86::GR16RegClass.contains(SrcReg) ||
3101        X86::GR8RegClass.contains(SrcReg))) {
3102     SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3103     return X86::KMOVWkr;
3104   }
3105   if ((X86::GR32RegClass.contains(DestReg) ||
3106        X86::GR16RegClass.contains(DestReg) ||
3107        X86::GR8RegClass.contains(DestReg)) &&
3108        MaskRegClassContains(SrcReg)) {
3109     DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3110     return X86::KMOVWrk;
3111   }
3112   return 0;
3113 }
3114 
3115 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3116                                MachineBasicBlock::iterator MI, DebugLoc DL,
3117                                unsigned DestReg, unsigned SrcReg,
3118                                bool KillSrc) const {
3119   // First deal with the normal symmetric copies.
3120   bool HasAVX = Subtarget.hasAVX();
3121   bool HasAVX512 = Subtarget.hasAVX512();
3122   unsigned Opc = 0;
3123   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3124     Opc = X86::MOV64rr;
3125   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3126     Opc = X86::MOV32rr;
3127   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3128     Opc = X86::MOV16rr;
3129   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3130     // Copying to or from a physical H register on x86-64 requires a NOREX
3131     // move.  Otherwise use a normal move.
3132     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3133         Subtarget.is64Bit()) {
3134       Opc = X86::MOV8rr_NOREX;
3135       // Both operands must be encodable without an REX prefix.
3136       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3137              "8-bit H register can not be copied outside GR8_NOREX");
3138     } else
3139       Opc = X86::MOV8rr;
3140   }
3141   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3142     Opc = X86::MMX_MOVQ64rr;
3143   else if (HasAVX512)
3144     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3145   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3146     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3147   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3148     Opc = X86::VMOVAPSYrr;
3149   if (!Opc)
3150     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3151 
3152   if (Opc) {
3153     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3154       .addReg(SrcReg, getKillRegState(KillSrc));
3155     return;
3156   }
3157 
3158   // Moving EFLAGS to / from another register requires a push and a pop.
3159   // Notice that we have to adjust the stack if we don't want to clobber the
3160   // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
3161   if (SrcReg == X86::EFLAGS) {
3162     if (X86::GR64RegClass.contains(DestReg)) {
3163       BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3164       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3165       return;
3166     }
3167     if (X86::GR32RegClass.contains(DestReg)) {
3168       BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3169       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3170       return;
3171     }
3172   }
3173   if (DestReg == X86::EFLAGS) {
3174     if (X86::GR64RegClass.contains(SrcReg)) {
3175       BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3176         .addReg(SrcReg, getKillRegState(KillSrc));
3177       BuildMI(MBB, MI, DL, get(X86::POPF64));
3178       return;
3179     }
3180     if (X86::GR32RegClass.contains(SrcReg)) {
3181       BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3182         .addReg(SrcReg, getKillRegState(KillSrc));
3183       BuildMI(MBB, MI, DL, get(X86::POPF32));
3184       return;
3185     }
3186   }
3187 
3188   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3189                << " to " << RI.getName(DestReg) << '\n');
3190   llvm_unreachable("Cannot emit physreg copy instruction");
3191 }
3192 
3193 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3194                                       const TargetRegisterClass *RC,
3195                                       bool isStackAligned,
3196                                       const X86Subtarget &STI,
3197                                       bool load) {
3198   if (STI.hasAVX512()) {
3199     if (X86::VK8RegClass.hasSubClassEq(RC)  ||
3200       X86::VK16RegClass.hasSubClassEq(RC))
3201       return load ? X86::KMOVWkm : X86::KMOVWmk;
3202     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3203       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3204     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3205       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3206     if (X86::VR512RegClass.hasSubClassEq(RC))
3207       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3208   }
3209 
3210   bool HasAVX = STI.hasAVX();
3211   switch (RC->getSize()) {
3212   default:
3213     llvm_unreachable("Unknown spill size");
3214   case 1:
3215     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3216     if (STI.is64Bit())
3217       // Copying to or from a physical H register on x86-64 requires a NOREX
3218       // move.  Otherwise use a normal move.
3219       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3220         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3221     return load ? X86::MOV8rm : X86::MOV8mr;
3222   case 2:
3223     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3224     return load ? X86::MOV16rm : X86::MOV16mr;
3225   case 4:
3226     if (X86::GR32RegClass.hasSubClassEq(RC))
3227       return load ? X86::MOV32rm : X86::MOV32mr;
3228     if (X86::FR32RegClass.hasSubClassEq(RC))
3229       return load ?
3230         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3231         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3232     if (X86::RFP32RegClass.hasSubClassEq(RC))
3233       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3234     llvm_unreachable("Unknown 4-byte regclass");
3235   case 8:
3236     if (X86::GR64RegClass.hasSubClassEq(RC))
3237       return load ? X86::MOV64rm : X86::MOV64mr;
3238     if (X86::FR64RegClass.hasSubClassEq(RC))
3239       return load ?
3240         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3241         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3242     if (X86::VR64RegClass.hasSubClassEq(RC))
3243       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3244     if (X86::RFP64RegClass.hasSubClassEq(RC))
3245       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3246     llvm_unreachable("Unknown 8-byte regclass");
3247   case 10:
3248     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3249     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3250   case 16: {
3251     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3252             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
3253     // If stack is realigned we can use aligned stores.
3254     if (isStackAligned)
3255       return load ?
3256         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3257         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3258     else
3259       return load ?
3260         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3261         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3262   }
3263   case 32:
3264     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3265             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
3266     // If stack is realigned we can use aligned stores.
3267     if (isStackAligned)
3268       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3269     else
3270       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3271   case 64:
3272     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3273     if (isStackAligned)
3274       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3275     else
3276       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3277   }
3278 }
3279 
3280 static unsigned getStoreRegOpcode(unsigned SrcReg,
3281                                   const TargetRegisterClass *RC,
3282                                   bool isStackAligned,
3283                                   const X86Subtarget &STI) {
3284   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3285 }
3286 
3287 
3288 static unsigned getLoadRegOpcode(unsigned DestReg,
3289                                  const TargetRegisterClass *RC,
3290                                  bool isStackAligned,
3291                                  const X86Subtarget &STI) {
3292   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3293 }
3294 
3295 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3296                                        MachineBasicBlock::iterator MI,
3297                                        unsigned SrcReg, bool isKill, int FrameIdx,
3298                                        const TargetRegisterClass *RC,
3299                                        const TargetRegisterInfo *TRI) const {
3300   const MachineFunction &MF = *MBB.getParent();
3301   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3302          "Stack slot too small for store");
3303   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3304   bool isAligned = (MF.getTarget()
3305                         .getSubtargetImpl()
3306                         ->getFrameLowering()
3307                         ->getStackAlignment() >= Alignment) ||
3308                    RI.canRealignStack(MF);
3309   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3310   DebugLoc DL = MBB.findDebugLoc(MI);
3311   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3312     .addReg(SrcReg, getKillRegState(isKill));
3313 }
3314 
3315 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3316                                   bool isKill,
3317                                   SmallVectorImpl<MachineOperand> &Addr,
3318                                   const TargetRegisterClass *RC,
3319                                   MachineInstr::mmo_iterator MMOBegin,
3320                                   MachineInstr::mmo_iterator MMOEnd,
3321                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
3322   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3323   bool isAligned = MMOBegin != MMOEnd &&
3324                    (*MMOBegin)->getAlignment() >= Alignment;
3325   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3326   DebugLoc DL;
3327   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3328   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3329     MIB.addOperand(Addr[i]);
3330   MIB.addReg(SrcReg, getKillRegState(isKill));
3331   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3332   NewMIs.push_back(MIB);
3333 }
3334 
3335 
3336 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3337                                         MachineBasicBlock::iterator MI,
3338                                         unsigned DestReg, int FrameIdx,
3339                                         const TargetRegisterClass *RC,
3340                                         const TargetRegisterInfo *TRI) const {
3341   const MachineFunction &MF = *MBB.getParent();
3342   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3343   bool isAligned = (MF.getTarget()
3344                         .getSubtargetImpl()
3345                         ->getFrameLowering()
3346                         ->getStackAlignment() >= Alignment) ||
3347                    RI.canRealignStack(MF);
3348   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3349   DebugLoc DL = MBB.findDebugLoc(MI);
3350   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
3351 }
3352 
3353 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
3354                                  SmallVectorImpl<MachineOperand> &Addr,
3355                                  const TargetRegisterClass *RC,
3356                                  MachineInstr::mmo_iterator MMOBegin,
3357                                  MachineInstr::mmo_iterator MMOEnd,
3358                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
3359   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3360   bool isAligned = MMOBegin != MMOEnd &&
3361                    (*MMOBegin)->getAlignment() >= Alignment;
3362   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3363   DebugLoc DL;
3364   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3365   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3366     MIB.addOperand(Addr[i]);
3367   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3368   NewMIs.push_back(MIB);
3369 }
3370 
3371 bool X86InstrInfo::
3372 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3373                int &CmpMask, int &CmpValue) const {
3374   switch (MI->getOpcode()) {
3375   default: break;
3376   case X86::CMP64ri32:
3377   case X86::CMP64ri8:
3378   case X86::CMP32ri:
3379   case X86::CMP32ri8:
3380   case X86::CMP16ri:
3381   case X86::CMP16ri8:
3382   case X86::CMP8ri:
3383     SrcReg = MI->getOperand(0).getReg();
3384     SrcReg2 = 0;
3385     CmpMask = ~0;
3386     CmpValue = MI->getOperand(1).getImm();
3387     return true;
3388   // A SUB can be used to perform comparison.
3389   case X86::SUB64rm:
3390   case X86::SUB32rm:
3391   case X86::SUB16rm:
3392   case X86::SUB8rm:
3393     SrcReg = MI->getOperand(1).getReg();
3394     SrcReg2 = 0;
3395     CmpMask = ~0;
3396     CmpValue = 0;
3397     return true;
3398   case X86::SUB64rr:
3399   case X86::SUB32rr:
3400   case X86::SUB16rr:
3401   case X86::SUB8rr:
3402     SrcReg = MI->getOperand(1).getReg();
3403     SrcReg2 = MI->getOperand(2).getReg();
3404     CmpMask = ~0;
3405     CmpValue = 0;
3406     return true;
3407   case X86::SUB64ri32:
3408   case X86::SUB64ri8:
3409   case X86::SUB32ri:
3410   case X86::SUB32ri8:
3411   case X86::SUB16ri:
3412   case X86::SUB16ri8:
3413   case X86::SUB8ri:
3414     SrcReg = MI->getOperand(1).getReg();
3415     SrcReg2 = 0;
3416     CmpMask = ~0;
3417     CmpValue = MI->getOperand(2).getImm();
3418     return true;
3419   case X86::CMP64rr:
3420   case X86::CMP32rr:
3421   case X86::CMP16rr:
3422   case X86::CMP8rr:
3423     SrcReg = MI->getOperand(0).getReg();
3424     SrcReg2 = MI->getOperand(1).getReg();
3425     CmpMask = ~0;
3426     CmpValue = 0;
3427     return true;
3428   case X86::TEST8rr:
3429   case X86::TEST16rr:
3430   case X86::TEST32rr:
3431   case X86::TEST64rr:
3432     SrcReg = MI->getOperand(0).getReg();
3433     if (MI->getOperand(1).getReg() != SrcReg) return false;
3434     // Compare against zero.
3435     SrcReg2 = 0;
3436     CmpMask = ~0;
3437     CmpValue = 0;
3438     return true;
3439   }
3440   return false;
3441 }
3442 
3443 /// isRedundantFlagInstr - check whether the first instruction, whose only
3444 /// purpose is to update flags, can be made redundant.
3445 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3446 /// This function can be extended later on.
3447 /// SrcReg, SrcRegs: register operands for FlagI.
3448 /// ImmValue: immediate for FlagI if it takes an immediate.
3449 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3450                                         unsigned SrcReg2, int ImmValue,
3451                                         MachineInstr *OI) {
3452   if (((FlagI->getOpcode() == X86::CMP64rr &&
3453         OI->getOpcode() == X86::SUB64rr) ||
3454        (FlagI->getOpcode() == X86::CMP32rr &&
3455         OI->getOpcode() == X86::SUB32rr)||
3456        (FlagI->getOpcode() == X86::CMP16rr &&
3457         OI->getOpcode() == X86::SUB16rr)||
3458        (FlagI->getOpcode() == X86::CMP8rr &&
3459         OI->getOpcode() == X86::SUB8rr)) &&
3460       ((OI->getOperand(1).getReg() == SrcReg &&
3461         OI->getOperand(2).getReg() == SrcReg2) ||
3462        (OI->getOperand(1).getReg() == SrcReg2 &&
3463         OI->getOperand(2).getReg() == SrcReg)))
3464     return true;
3465 
3466   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3467         OI->getOpcode() == X86::SUB64ri32) ||
3468        (FlagI->getOpcode() == X86::CMP64ri8 &&
3469         OI->getOpcode() == X86::SUB64ri8) ||
3470        (FlagI->getOpcode() == X86::CMP32ri &&
3471         OI->getOpcode() == X86::SUB32ri) ||
3472        (FlagI->getOpcode() == X86::CMP32ri8 &&
3473         OI->getOpcode() == X86::SUB32ri8) ||
3474        (FlagI->getOpcode() == X86::CMP16ri &&
3475         OI->getOpcode() == X86::SUB16ri) ||
3476        (FlagI->getOpcode() == X86::CMP16ri8 &&
3477         OI->getOpcode() == X86::SUB16ri8) ||
3478        (FlagI->getOpcode() == X86::CMP8ri &&
3479         OI->getOpcode() == X86::SUB8ri)) &&
3480       OI->getOperand(1).getReg() == SrcReg &&
3481       OI->getOperand(2).getImm() == ImmValue)
3482     return true;
3483   return false;
3484 }
3485 
3486 /// isDefConvertible - check whether the definition can be converted
3487 /// to remove a comparison against zero.
3488 inline static bool isDefConvertible(MachineInstr *MI) {
3489   switch (MI->getOpcode()) {
3490   default: return false;
3491 
3492   // The shift instructions only modify ZF if their shift count is non-zero.
3493   // N.B.: The processor truncates the shift count depending on the encoding.
3494   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3495   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3496      return getTruncatedShiftCount(MI, 2) != 0;
3497 
3498   // Some left shift instructions can be turned into LEA instructions but only
3499   // if their flags aren't used. Avoid transforming such instructions.
3500   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3501     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3502     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3503     return ShAmt != 0;
3504   }
3505 
3506   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3507   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3508      return getTruncatedShiftCount(MI, 3) != 0;
3509 
3510   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3511   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3512   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3513   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3514   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3515   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3516   case X86::DEC64_32r: case X86::DEC64_16r:
3517   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3518   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3519   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3520   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3521   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3522   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3523   case X86::INC64_32r: case X86::INC64_16r:
3524   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3525   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3526   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3527   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3528   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3529   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3530   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3531   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3532   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3533   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3534   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3535   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3536   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3537   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3538   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3539   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
3540   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
3541   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
3542   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
3543   case X86::ADC32ri:   case X86::ADC32ri8:
3544   case X86::ADC32rr:   case X86::ADC64ri32:
3545   case X86::ADC64ri8:  case X86::ADC64rr:
3546   case X86::SBB32ri:   case X86::SBB32ri8:
3547   case X86::SBB32rr:   case X86::SBB64ri32:
3548   case X86::SBB64ri8:  case X86::SBB64rr:
3549   case X86::ANDN32rr:  case X86::ANDN32rm:
3550   case X86::ANDN64rr:  case X86::ANDN64rm:
3551   case X86::BEXTR32rr: case X86::BEXTR64rr:
3552   case X86::BEXTR32rm: case X86::BEXTR64rm:
3553   case X86::BLSI32rr:  case X86::BLSI32rm:
3554   case X86::BLSI64rr:  case X86::BLSI64rm:
3555   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3556   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3557   case X86::BLSR32rr:  case X86::BLSR32rm:
3558   case X86::BLSR64rr:  case X86::BLSR64rm:
3559   case X86::BZHI32rr:  case X86::BZHI32rm:
3560   case X86::BZHI64rr:  case X86::BZHI64rm:
3561   case X86::LZCNT16rr: case X86::LZCNT16rm:
3562   case X86::LZCNT32rr: case X86::LZCNT32rm:
3563   case X86::LZCNT64rr: case X86::LZCNT64rm:
3564   case X86::POPCNT16rr:case X86::POPCNT16rm:
3565   case X86::POPCNT32rr:case X86::POPCNT32rm:
3566   case X86::POPCNT64rr:case X86::POPCNT64rm:
3567   case X86::TZCNT16rr: case X86::TZCNT16rm:
3568   case X86::TZCNT32rr: case X86::TZCNT32rm:
3569   case X86::TZCNT64rr: case X86::TZCNT64rm:
3570     return true;
3571   }
3572 }
3573 
3574 /// isUseDefConvertible - check whether the use can be converted
3575 /// to remove a comparison against zero.
3576 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
3577   switch (MI->getOpcode()) {
3578   default: return X86::COND_INVALID;
3579   case X86::LZCNT16rr: case X86::LZCNT16rm:
3580   case X86::LZCNT32rr: case X86::LZCNT32rm:
3581   case X86::LZCNT64rr: case X86::LZCNT64rm:
3582     return X86::COND_B;
3583   case X86::POPCNT16rr:case X86::POPCNT16rm:
3584   case X86::POPCNT32rr:case X86::POPCNT32rm:
3585   case X86::POPCNT64rr:case X86::POPCNT64rm:
3586     return X86::COND_E;
3587   case X86::TZCNT16rr: case X86::TZCNT16rm:
3588   case X86::TZCNT32rr: case X86::TZCNT32rm:
3589   case X86::TZCNT64rr: case X86::TZCNT64rm:
3590     return X86::COND_B;
3591   }
3592 }
3593 
3594 /// optimizeCompareInstr - Check if there exists an earlier instruction that
3595 /// operates on the same source operands and sets flags in the same way as
3596 /// Compare; remove Compare if possible.
3597 bool X86InstrInfo::
3598 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3599                      int CmpMask, int CmpValue,
3600                      const MachineRegisterInfo *MRI) const {
3601   // Check whether we can replace SUB with CMP.
3602   unsigned NewOpcode = 0;
3603   switch (CmpInstr->getOpcode()) {
3604   default: break;
3605   case X86::SUB64ri32:
3606   case X86::SUB64ri8:
3607   case X86::SUB32ri:
3608   case X86::SUB32ri8:
3609   case X86::SUB16ri:
3610   case X86::SUB16ri8:
3611   case X86::SUB8ri:
3612   case X86::SUB64rm:
3613   case X86::SUB32rm:
3614   case X86::SUB16rm:
3615   case X86::SUB8rm:
3616   case X86::SUB64rr:
3617   case X86::SUB32rr:
3618   case X86::SUB16rr:
3619   case X86::SUB8rr: {
3620     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3621       return false;
3622     // There is no use of the destination register, we can replace SUB with CMP.
3623     switch (CmpInstr->getOpcode()) {
3624     default: llvm_unreachable("Unreachable!");
3625     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
3626     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
3627     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
3628     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
3629     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
3630     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
3631     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
3632     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
3633     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3634     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
3635     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
3636     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
3637     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
3638     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
3639     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
3640     }
3641     CmpInstr->setDesc(get(NewOpcode));
3642     CmpInstr->RemoveOperand(0);
3643     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3644     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3645         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3646       return false;
3647   }
3648   }
3649 
3650   // Get the unique definition of SrcReg.
3651   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3652   if (!MI) return false;
3653 
3654   // CmpInstr is the first instruction of the BB.
3655   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3656 
3657   // If we are comparing against zero, check whether we can use MI to update
3658   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3659   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
3660   if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
3661     return false;
3662 
3663   // If we have a use of the source register between the def and our compare
3664   // instruction we can eliminate the compare iff the use sets EFLAGS in the
3665   // right way.
3666   bool ShouldUpdateCC = false;
3667   X86::CondCode NewCC = X86::COND_INVALID;
3668   if (IsCmpZero && !isDefConvertible(MI)) {
3669     // Scan forward from the use until we hit the use we're looking for or the
3670     // compare instruction.
3671     for (MachineBasicBlock::iterator J = MI;; ++J) {
3672       // Do we have a convertible instruction?
3673       NewCC = isUseDefConvertible(J);
3674       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3675           J->getOperand(1).getReg() == SrcReg) {
3676         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3677         ShouldUpdateCC = true; // Update CC later on.
3678         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3679         // with the new def.
3680         MI = Def = J;
3681         break;
3682       }
3683 
3684       if (J == I)
3685         return false;
3686     }
3687   }
3688 
3689   // We are searching for an earlier instruction that can make CmpInstr
3690   // redundant and that instruction will be saved in Sub.
3691   MachineInstr *Sub = nullptr;
3692   const TargetRegisterInfo *TRI = &getRegisterInfo();
3693 
3694   // We iterate backward, starting from the instruction before CmpInstr and
3695   // stop when reaching the definition of a source register or done with the BB.
3696   // RI points to the instruction before CmpInstr.
3697   // If the definition is in this basic block, RE points to the definition;
3698   // otherwise, RE is the rend of the basic block.
3699   MachineBasicBlock::reverse_iterator
3700       RI = MachineBasicBlock::reverse_iterator(I),
3701       RE = CmpInstr->getParent() == MI->getParent() ?
3702            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3703            CmpInstr->getParent()->rend();
3704   MachineInstr *Movr0Inst = nullptr;
3705   for (; RI != RE; ++RI) {
3706     MachineInstr *Instr = &*RI;
3707     // Check whether CmpInstr can be made redundant by the current instruction.
3708     if (!IsCmpZero &&
3709         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
3710       Sub = Instr;
3711       break;
3712     }
3713 
3714     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3715         Instr->readsRegister(X86::EFLAGS, TRI)) {
3716       // This instruction modifies or uses EFLAGS.
3717 
3718       // MOV32r0 etc. are implemented with xor which clobbers condition code.
3719       // They are safe to move up, if the definition to EFLAGS is dead and
3720       // earlier instructions do not read or write EFLAGS.
3721       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
3722           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3723         Movr0Inst = Instr;
3724         continue;
3725       }
3726 
3727       // We can't remove CmpInstr.
3728       return false;
3729     }
3730   }
3731 
3732   // Return false if no candidates exist.
3733   if (!IsCmpZero && !Sub)
3734     return false;
3735 
3736   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3737                     Sub->getOperand(2).getReg() == SrcReg);
3738 
3739   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3740   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3741   // If we are done with the basic block, we need to check whether EFLAGS is
3742   // live-out.
3743   bool IsSafe = false;
3744   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3745   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3746   for (++I; I != E; ++I) {
3747     const MachineInstr &Instr = *I;
3748     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3749     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3750     // We should check the usage if this instruction uses and updates EFLAGS.
3751     if (!UseEFLAGS && ModifyEFLAGS) {
3752       // It is safe to remove CmpInstr if EFLAGS is updated again.
3753       IsSafe = true;
3754       break;
3755     }
3756     if (!UseEFLAGS && !ModifyEFLAGS)
3757       continue;
3758 
3759     // EFLAGS is used by this instruction.
3760     X86::CondCode OldCC = X86::COND_INVALID;
3761     bool OpcIsSET = false;
3762     if (IsCmpZero || IsSwapped) {
3763       // We decode the condition code from opcode.
3764       if (Instr.isBranch())
3765         OldCC = getCondFromBranchOpc(Instr.getOpcode());
3766       else {
3767         OldCC = getCondFromSETOpc(Instr.getOpcode());
3768         if (OldCC != X86::COND_INVALID)
3769           OpcIsSET = true;
3770         else
3771           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3772       }
3773       if (OldCC == X86::COND_INVALID) return false;
3774     }
3775     if (IsCmpZero) {
3776       switch (OldCC) {
3777       default: break;
3778       case X86::COND_A: case X86::COND_AE:
3779       case X86::COND_B: case X86::COND_BE:
3780       case X86::COND_G: case X86::COND_GE:
3781       case X86::COND_L: case X86::COND_LE:
3782       case X86::COND_O: case X86::COND_NO:
3783         // CF and OF are used, we can't perform this optimization.
3784         return false;
3785       }
3786 
3787       // If we're updating the condition code check if we have to reverse the
3788       // condition.
3789       if (ShouldUpdateCC)
3790         switch (OldCC) {
3791         default:
3792           return false;
3793         case X86::COND_E:
3794           break;
3795         case X86::COND_NE:
3796           NewCC = GetOppositeBranchCondition(NewCC);
3797           break;
3798         }
3799     } else if (IsSwapped) {
3800       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3801       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3802       // We swap the condition code and synthesize the new opcode.
3803       NewCC = getSwappedCondition(OldCC);
3804       if (NewCC == X86::COND_INVALID) return false;
3805     }
3806 
3807     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
3808       // Synthesize the new opcode.
3809       bool HasMemoryOperand = Instr.hasOneMemOperand();
3810       unsigned NewOpc;
3811       if (Instr.isBranch())
3812         NewOpc = GetCondBranchFromCond(NewCC);
3813       else if(OpcIsSET)
3814         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3815       else {
3816         unsigned DstReg = Instr.getOperand(0).getReg();
3817         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3818                                  HasMemoryOperand);
3819       }
3820 
3821       // Push the MachineInstr to OpsToUpdate.
3822       // If it is safe to remove CmpInstr, the condition code of these
3823       // instructions will be modified.
3824       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3825     }
3826     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3827       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3828       IsSafe = true;
3829       break;
3830     }
3831   }
3832 
3833   // If EFLAGS is not killed nor re-defined, we should check whether it is
3834   // live-out. If it is live-out, do not optimize.
3835   if ((IsCmpZero || IsSwapped) && !IsSafe) {
3836     MachineBasicBlock *MBB = CmpInstr->getParent();
3837     for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
3838              SE = MBB->succ_end(); SI != SE; ++SI)
3839       if ((*SI)->isLiveIn(X86::EFLAGS))
3840         return false;
3841   }
3842 
3843   // The instruction to be updated is either Sub or MI.
3844   Sub = IsCmpZero ? MI : Sub;
3845   // Move Movr0Inst to the appropriate place before Sub.
3846   if (Movr0Inst) {
3847     // Look backwards until we find a def that doesn't use the current EFLAGS.
3848     Def = Sub;
3849     MachineBasicBlock::reverse_iterator
3850       InsertI = MachineBasicBlock::reverse_iterator(++Def),
3851                 InsertE = Sub->getParent()->rend();
3852     for (; InsertI != InsertE; ++InsertI) {
3853       MachineInstr *Instr = &*InsertI;
3854       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3855           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3856         Sub->getParent()->remove(Movr0Inst);
3857         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3858                                    Movr0Inst);
3859         break;
3860       }
3861     }
3862     if (InsertI == InsertE)
3863       return false;
3864   }
3865 
3866   // Make sure Sub instruction defines EFLAGS and mark the def live.
3867   unsigned i = 0, e = Sub->getNumOperands();
3868   for (; i != e; ++i) {
3869     MachineOperand &MO = Sub->getOperand(i);
3870     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3871       MO.setIsDead(false);
3872       break;
3873     }
3874   }
3875   assert(i != e && "Unable to locate a def EFLAGS operand");
3876 
3877   CmpInstr->eraseFromParent();
3878 
3879   // Modify the condition code of instructions in OpsToUpdate.
3880   for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
3881     OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
3882   return true;
3883 }
3884 
3885 /// optimizeLoadInstr - Try to remove the load by folding it to a register
3886 /// operand at the use. We fold the load instructions if load defines a virtual
3887 /// register, the virtual register is used once in the same BB, and the
3888 /// instructions in-between do not load or store, and have no side effects.
3889 MachineInstr* X86InstrInfo::
3890 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,
3891                   unsigned &FoldAsLoadDefReg,
3892                   MachineInstr *&DefMI) const {
3893   if (FoldAsLoadDefReg == 0)
3894     return nullptr;
3895   // To be conservative, if there exists another load, clear the load candidate.
3896   if (MI->mayLoad()) {
3897     FoldAsLoadDefReg = 0;
3898     return nullptr;
3899   }
3900 
3901   // Check whether we can move DefMI here.
3902   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3903   assert(DefMI);
3904   bool SawStore = false;
3905   if (!DefMI->isSafeToMove(this, nullptr, SawStore))
3906     return nullptr;
3907 
3908   // We try to commute MI if possible.
3909   unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1;
3910   for (unsigned Idx = 0; Idx < IdxEnd; Idx++) {
3911     // Collect information about virtual register operands of MI.
3912     unsigned SrcOperandId = 0;
3913     bool FoundSrcOperand = false;
3914     for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
3915       MachineOperand &MO = MI->getOperand(i);
3916       if (!MO.isReg())
3917         continue;
3918       unsigned Reg = MO.getReg();
3919       if (Reg != FoldAsLoadDefReg)
3920         continue;
3921       // Do not fold if we have a subreg use or a def or multiple uses.
3922       if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
3923         return nullptr;
3924 
3925       SrcOperandId = i;
3926       FoundSrcOperand = true;
3927     }
3928     if (!FoundSrcOperand) return nullptr;
3929 
3930     // Check whether we can fold the def into SrcOperandId.
3931     SmallVector<unsigned, 8> Ops;
3932     Ops.push_back(SrcOperandId);
3933     MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
3934     if (FoldMI) {
3935       FoldAsLoadDefReg = 0;
3936       return FoldMI;
3937     }
3938 
3939     if (Idx == 1) {
3940       // MI was changed but it didn't help, commute it back!
3941       commuteInstruction(MI, false);
3942       return nullptr;
3943     }
3944 
3945     // Check whether we can commute MI and enable folding.
3946     if (MI->isCommutable()) {
3947       MachineInstr *NewMI = commuteInstruction(MI, false);
3948       // Unable to commute.
3949       if (!NewMI) return nullptr;
3950       if (NewMI != MI) {
3951         // New instruction. It doesn't need to be kept.
3952         NewMI->eraseFromParent();
3953         return nullptr;
3954       }
3955     }
3956   }
3957   return nullptr;
3958 }
3959 
3960 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
3961 /// instruction with two undef reads of the register being defined.  This is
3962 /// used for mapping:
3963 ///   %xmm4 = V_SET0
3964 /// to:
3965 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
3966 ///
3967 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3968                              const MCInstrDesc &Desc) {
3969   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3970   unsigned Reg = MIB->getOperand(0).getReg();
3971   MIB->setDesc(Desc);
3972 
3973   // MachineInstr::addOperand() will insert explicit operands before any
3974   // implicit operands.
3975   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3976   // But we don't trust that.
3977   assert(MIB->getOperand(1).getReg() == Reg &&
3978          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3979   return true;
3980 }
3981 
3982 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
3983 // code sequence is needed for other targets.
3984 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
3985                                  const TargetInstrInfo &TII) {
3986   MachineBasicBlock &MBB = *MIB->getParent();
3987   DebugLoc DL = MIB->getDebugLoc();
3988   unsigned Reg = MIB->getOperand(0).getReg();
3989   const GlobalValue *GV =
3990       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
3991   unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
3992   MachineMemOperand *MMO = MBB.getParent()->
3993       getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8);
3994   MachineBasicBlock::iterator I = MIB;
3995 
3996   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
3997       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
3998       .addMemOperand(MMO);
3999   MIB->setDebugLoc(DL);
4000   MIB->setDesc(TII.get(X86::MOV64rm));
4001   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4002 }
4003 
4004 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
4005   bool HasAVX = Subtarget.hasAVX();
4006   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4007   switch (MI->getOpcode()) {
4008   case X86::MOV32r0:
4009     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4010   case X86::SETB_C8r:
4011     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4012   case X86::SETB_C16r:
4013     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4014   case X86::SETB_C32r:
4015     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4016   case X86::SETB_C64r:
4017     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4018   case X86::V_SET0:
4019   case X86::FsFLD0SS:
4020   case X86::FsFLD0SD:
4021     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4022   case X86::AVX_SET0:
4023     assert(HasAVX && "AVX not supported");
4024     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
4025   case X86::AVX512_512_SET0:
4026     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4027   case X86::V_SETALLONES:
4028     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4029   case X86::AVX2_SETALLONES:
4030     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4031   case X86::TEST8ri_NOREX:
4032     MI->setDesc(get(X86::TEST8ri));
4033     return true;
4034   case X86::KSET0B:
4035   case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4036   case X86::KSET1B:
4037   case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
4038   case TargetOpcode::LOAD_STACK_GUARD:
4039     expandLoadStackGuard(MIB, *this);
4040     return true;
4041   }
4042   return false;
4043 }
4044 
4045 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4046                                      const SmallVectorImpl<MachineOperand> &MOs,
4047                                      MachineInstr *MI,
4048                                      const TargetInstrInfo &TII) {
4049   // Create the base instruction with the memory operand as the first part.
4050   // Omit the implicit operands, something BuildMI can't do.
4051   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4052                                               MI->getDebugLoc(), true);
4053   MachineInstrBuilder MIB(MF, NewMI);
4054   unsigned NumAddrOps = MOs.size();
4055   for (unsigned i = 0; i != NumAddrOps; ++i)
4056     MIB.addOperand(MOs[i]);
4057   if (NumAddrOps < 4)  // FrameIndex only
4058     addOffset(MIB, 0);
4059 
4060   // Loop over the rest of the ri operands, converting them over.
4061   unsigned NumOps = MI->getDesc().getNumOperands()-2;
4062   for (unsigned i = 0; i != NumOps; ++i) {
4063     MachineOperand &MO = MI->getOperand(i+2);
4064     MIB.addOperand(MO);
4065   }
4066   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4067     MachineOperand &MO = MI->getOperand(i);
4068     MIB.addOperand(MO);
4069   }
4070   return MIB;
4071 }
4072 
4073 static MachineInstr *FuseInst(MachineFunction &MF,
4074                               unsigned Opcode, unsigned OpNo,
4075                               const SmallVectorImpl<MachineOperand> &MOs,
4076                               MachineInstr *MI, const TargetInstrInfo &TII) {
4077   // Omit the implicit operands, something BuildMI can't do.
4078   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4079                                               MI->getDebugLoc(), true);
4080   MachineInstrBuilder MIB(MF, NewMI);
4081 
4082   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4083     MachineOperand &MO = MI->getOperand(i);
4084     if (i == OpNo) {
4085       assert(MO.isReg() && "Expected to fold into reg operand!");
4086       unsigned NumAddrOps = MOs.size();
4087       for (unsigned i = 0; i != NumAddrOps; ++i)
4088         MIB.addOperand(MOs[i]);
4089       if (NumAddrOps < 4)  // FrameIndex only
4090         addOffset(MIB, 0);
4091     } else {
4092       MIB.addOperand(MO);
4093     }
4094   }
4095   return MIB;
4096 }
4097 
4098 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4099                                 const SmallVectorImpl<MachineOperand> &MOs,
4100                                 MachineInstr *MI) {
4101   MachineFunction &MF = *MI->getParent()->getParent();
4102   MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
4103 
4104   unsigned NumAddrOps = MOs.size();
4105   for (unsigned i = 0; i != NumAddrOps; ++i)
4106     MIB.addOperand(MOs[i]);
4107   if (NumAddrOps < 4)  // FrameIndex only
4108     addOffset(MIB, 0);
4109   return MIB.addImm(0);
4110 }
4111 
4112 MachineInstr*
4113 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4114                                     MachineInstr *MI, unsigned i,
4115                                     const SmallVectorImpl<MachineOperand> &MOs,
4116                                     unsigned Size, unsigned Align) const {
4117   const DenseMap<unsigned,
4118                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4119   bool isCallRegIndirect = Subtarget.callRegIndirect();
4120   bool isTwoAddrFold = false;
4121 
4122   // Atom favors register form of call. So, we do not fold loads into calls
4123   // when X86Subtarget is Atom.
4124   if (isCallRegIndirect &&
4125     (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
4126     return nullptr;
4127   }
4128 
4129   unsigned NumOps = MI->getDesc().getNumOperands();
4130   bool isTwoAddr = NumOps > 1 &&
4131     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4132 
4133   // FIXME: AsmPrinter doesn't know how to handle
4134   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4135   if (MI->getOpcode() == X86::ADD32ri &&
4136       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4137     return nullptr;
4138 
4139   MachineInstr *NewMI = nullptr;
4140   // Folding a memory location into the two-address part of a two-address
4141   // instruction is different than folding it other places.  It requires
4142   // replacing the *two* registers with the memory location.
4143   if (isTwoAddr && NumOps >= 2 && i < 2 &&
4144       MI->getOperand(0).isReg() &&
4145       MI->getOperand(1).isReg() &&
4146       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
4147     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4148     isTwoAddrFold = true;
4149   } else if (i == 0) { // If operand 0
4150     if (MI->getOpcode() == X86::MOV32r0) {
4151       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4152       if (NewMI)
4153         return NewMI;
4154     }
4155 
4156     OpcodeTablePtr = &RegOp2MemOpTable0;
4157   } else if (i == 1) {
4158     OpcodeTablePtr = &RegOp2MemOpTable1;
4159   } else if (i == 2) {
4160     OpcodeTablePtr = &RegOp2MemOpTable2;
4161   } else if (i == 3) {
4162     OpcodeTablePtr = &RegOp2MemOpTable3;
4163   }
4164 
4165   // If table selected...
4166   if (OpcodeTablePtr) {
4167     // Find the Opcode to fuse
4168     DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4169       OpcodeTablePtr->find(MI->getOpcode());
4170     if (I != OpcodeTablePtr->end()) {
4171       unsigned Opcode = I->second.first;
4172       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4173       if (Align < MinAlign)
4174         return nullptr;
4175       bool NarrowToMOV32rm = false;
4176       if (Size) {
4177         unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
4178         if (Size < RCSize) {
4179           // Check if it's safe to fold the load. If the size of the object is
4180           // narrower than the load width, then it's not.
4181           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4182             return nullptr;
4183           // If this is a 64-bit load, but the spill slot is 32, then we can do
4184           // a 32-bit load which is implicitly zero-extended. This likely is due
4185           // to liveintervalanalysis remat'ing a load from stack slot.
4186           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4187             return nullptr;
4188           Opcode = X86::MOV32rm;
4189           NarrowToMOV32rm = true;
4190         }
4191       }
4192 
4193       if (isTwoAddrFold)
4194         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
4195       else
4196         NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
4197 
4198       if (NarrowToMOV32rm) {
4199         // If this is the special case where we use a MOV32rm to load a 32-bit
4200         // value and zero-extend the top bits. Change the destination register
4201         // to a 32-bit one.
4202         unsigned DstReg = NewMI->getOperand(0).getReg();
4203         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4204           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
4205                                                    X86::sub_32bit));
4206         else
4207           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4208       }
4209       return NewMI;
4210     }
4211   }
4212 
4213   // No fusion
4214   if (PrintFailedFusing && !MI->isCopy())
4215     dbgs() << "We failed to fuse operand " << i << " in " << *MI;
4216   return nullptr;
4217 }
4218 
4219 /// hasPartialRegUpdate - Return true for all instructions that only update
4220 /// the first 32 or 64-bits of the destination register and leave the rest
4221 /// unmodified. This can be used to avoid folding loads if the instructions
4222 /// only update part of the destination register, and the non-updated part is
4223 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4224 /// instructions breaks the partial register dependency and it can improve
4225 /// performance. e.g.:
4226 ///
4227 ///   movss (%rdi), %xmm0
4228 ///   cvtss2sd %xmm0, %xmm0
4229 ///
4230 /// Instead of
4231 ///   cvtss2sd (%rdi), %xmm0
4232 ///
4233 /// FIXME: This should be turned into a TSFlags.
4234 ///
4235 static bool hasPartialRegUpdate(unsigned Opcode) {
4236   switch (Opcode) {
4237   case X86::CVTSI2SSrr:
4238   case X86::CVTSI2SS64rr:
4239   case X86::CVTSI2SDrr:
4240   case X86::CVTSI2SD64rr:
4241   case X86::CVTSD2SSrr:
4242   case X86::Int_CVTSD2SSrr:
4243   case X86::CVTSS2SDrr:
4244   case X86::Int_CVTSS2SDrr:
4245   case X86::RCPSSr:
4246   case X86::RCPSSr_Int:
4247   case X86::ROUNDSDr:
4248   case X86::ROUNDSDr_Int:
4249   case X86::ROUNDSSr:
4250   case X86::ROUNDSSr_Int:
4251   case X86::RSQRTSSr:
4252   case X86::RSQRTSSr_Int:
4253   case X86::SQRTSSr:
4254   case X86::SQRTSSr_Int:
4255     return true;
4256   }
4257 
4258   return false;
4259 }
4260 
4261 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4262 /// instructions we would like before a partial register update.
4263 unsigned X86InstrInfo::
4264 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4265                              const TargetRegisterInfo *TRI) const {
4266   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4267     return 0;
4268 
4269   // If MI is marked as reading Reg, the partial register update is wanted.
4270   const MachineOperand &MO = MI->getOperand(0);
4271   unsigned Reg = MO.getReg();
4272   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4273     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4274       return 0;
4275   } else {
4276     if (MI->readsRegister(Reg, TRI))
4277       return 0;
4278   }
4279 
4280   // If any of the preceding 16 instructions are reading Reg, insert a
4281   // dependency breaking instruction.  The magic number is based on a few
4282   // Nehalem experiments.
4283   return 16;
4284 }
4285 
4286 // Return true for any instruction the copies the high bits of the first source
4287 // operand into the unused high bits of the destination operand.
4288 static bool hasUndefRegUpdate(unsigned Opcode) {
4289   switch (Opcode) {
4290   case X86::VCVTSI2SSrr:
4291   case X86::Int_VCVTSI2SSrr:
4292   case X86::VCVTSI2SS64rr:
4293   case X86::Int_VCVTSI2SS64rr:
4294   case X86::VCVTSI2SDrr:
4295   case X86::Int_VCVTSI2SDrr:
4296   case X86::VCVTSI2SD64rr:
4297   case X86::Int_VCVTSI2SD64rr:
4298   case X86::VCVTSD2SSrr:
4299   case X86::Int_VCVTSD2SSrr:
4300   case X86::VCVTSS2SDrr:
4301   case X86::Int_VCVTSS2SDrr:
4302   case X86::VRCPSSr:
4303   case X86::VROUNDSDr:
4304   case X86::VROUNDSDr_Int:
4305   case X86::VROUNDSSr:
4306   case X86::VROUNDSSr_Int:
4307   case X86::VRSQRTSSr:
4308   case X86::VSQRTSSr:
4309 
4310   // AVX-512
4311   case X86::VCVTSD2SSZrr:
4312   case X86::VCVTSS2SDZrr:
4313     return true;
4314   }
4315 
4316   return false;
4317 }
4318 
4319 /// Inform the ExeDepsFix pass how many idle instructions we would like before
4320 /// certain undef register reads.
4321 ///
4322 /// This catches the VCVTSI2SD family of instructions:
4323 ///
4324 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4325 ///
4326 /// We should to be careful *not* to catch VXOR idioms which are presumably
4327 /// handled specially in the pipeline:
4328 ///
4329 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4330 ///
4331 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4332 /// high bits that are passed-through are not live.
4333 unsigned X86InstrInfo::
4334 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4335                      const TargetRegisterInfo *TRI) const {
4336   if (!hasUndefRegUpdate(MI->getOpcode()))
4337     return 0;
4338 
4339   // Set the OpNum parameter to the first source operand.
4340   OpNum = 1;
4341 
4342   const MachineOperand &MO = MI->getOperand(OpNum);
4343   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4344     // Use the same magic number as getPartialRegUpdateClearance.
4345     return 16;
4346   }
4347   return 0;
4348 }
4349 
4350 void X86InstrInfo::
4351 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4352                           const TargetRegisterInfo *TRI) const {
4353   unsigned Reg = MI->getOperand(OpNum).getReg();
4354   // If MI kills this register, the false dependence is already broken.
4355   if (MI->killsRegister(Reg, TRI))
4356     return;
4357   if (X86::VR128RegClass.contains(Reg)) {
4358     // These instructions are all floating point domain, so xorps is the best
4359     // choice.
4360     bool HasAVX = Subtarget.hasAVX();
4361     unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4362     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4363       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4364   } else if (X86::VR256RegClass.contains(Reg)) {
4365     // Use vxorps to clear the full ymm register.
4366     // It wants to read and write the xmm sub-register.
4367     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4368     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4369       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4370       .addReg(Reg, RegState::ImplicitDefine);
4371   } else
4372     return;
4373   MI->addRegisterKilled(Reg, TRI, true);
4374 }
4375 
4376 MachineInstr*
4377 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4378                                     const SmallVectorImpl<unsigned> &Ops,
4379                                     int FrameIndex) const {
4380   // Check switch flag
4381   if (NoFusing) return nullptr;
4382 
4383   // Unless optimizing for size, don't fold to avoid partial
4384   // register update stalls
4385   if (!MF.getFunction()->getAttributes().
4386         hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4387       hasPartialRegUpdate(MI->getOpcode()))
4388     return nullptr;
4389 
4390   const MachineFrameInfo *MFI = MF.getFrameInfo();
4391   unsigned Size = MFI->getObjectSize(FrameIndex);
4392   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
4393   // If the function stack isn't realigned we don't want to fold instructions
4394   // that need increased alignment.
4395   if (!RI.needsStackRealignment(MF))
4396     Alignment = std::min(Alignment, MF.getTarget()
4397                                         .getSubtargetImpl()
4398                                         ->getFrameLowering()
4399                                         ->getStackAlignment());
4400   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4401     unsigned NewOpc = 0;
4402     unsigned RCSize = 0;
4403     switch (MI->getOpcode()) {
4404     default: return nullptr;
4405     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
4406     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4407     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4408     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4409     }
4410     // Check if it's safe to fold the load. If the size of the object is
4411     // narrower than the load width, then it's not.
4412     if (Size < RCSize)
4413       return nullptr;
4414     // Change to CMPXXri r, 0 first.
4415     MI->setDesc(get(NewOpc));
4416     MI->getOperand(1).ChangeToImmediate(0);
4417   } else if (Ops.size() != 1)
4418     return nullptr;
4419 
4420   SmallVector<MachineOperand,4> MOs;
4421   MOs.push_back(MachineOperand::CreateFI(FrameIndex));
4422   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
4423 }
4424 
4425 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4426                                                   MachineInstr *MI,
4427                                            const SmallVectorImpl<unsigned> &Ops,
4428                                                   MachineInstr *LoadMI) const {
4429   // If loading from a FrameIndex, fold directly from the FrameIndex.
4430   unsigned NumOps = LoadMI->getDesc().getNumOperands();
4431   int FrameIndex;
4432   if (isLoadFromStackSlot(LoadMI, FrameIndex))
4433     return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
4434 
4435   // Check switch flag
4436   if (NoFusing) return nullptr;
4437 
4438   // Unless optimizing for size, don't fold to avoid partial
4439   // register update stalls
4440   if (!MF.getFunction()->getAttributes().
4441         hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4442       hasPartialRegUpdate(MI->getOpcode()))
4443     return nullptr;
4444 
4445   // Determine the alignment of the load.
4446   unsigned Alignment = 0;
4447   if (LoadMI->hasOneMemOperand())
4448     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
4449   else
4450     switch (LoadMI->getOpcode()) {
4451     case X86::AVX2_SETALLONES:
4452     case X86::AVX_SET0:
4453       Alignment = 32;
4454       break;
4455     case X86::V_SET0:
4456     case X86::V_SETALLONES:
4457       Alignment = 16;
4458       break;
4459     case X86::FsFLD0SD:
4460       Alignment = 8;
4461       break;
4462     case X86::FsFLD0SS:
4463       Alignment = 4;
4464       break;
4465     default:
4466       return nullptr;
4467     }
4468   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4469     unsigned NewOpc = 0;
4470     switch (MI->getOpcode()) {
4471     default: return nullptr;
4472     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
4473     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4474     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4475     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
4476     }
4477     // Change to CMPXXri r, 0 first.
4478     MI->setDesc(get(NewOpc));
4479     MI->getOperand(1).ChangeToImmediate(0);
4480   } else if (Ops.size() != 1)
4481     return nullptr;
4482 
4483   // Make sure the subregisters match.
4484   // Otherwise we risk changing the size of the load.
4485   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
4486     return nullptr;
4487 
4488   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
4489   switch (LoadMI->getOpcode()) {
4490   case X86::V_SET0:
4491   case X86::V_SETALLONES:
4492   case X86::AVX2_SETALLONES:
4493   case X86::AVX_SET0:
4494   case X86::FsFLD0SD:
4495   case X86::FsFLD0SS: {
4496     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
4497     // Create a constant-pool entry and operands to load from it.
4498 
4499     // Medium and large mode can't fold loads this way.
4500     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
4501         MF.getTarget().getCodeModel() != CodeModel::Kernel)
4502       return nullptr;
4503 
4504     // x86-32 PIC requires a PIC base register for constant pools.
4505     unsigned PICBase = 0;
4506     if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
4507       if (Subtarget.is64Bit())
4508         PICBase = X86::RIP;
4509       else
4510         // FIXME: PICBase = getGlobalBaseReg(&MF);
4511         // This doesn't work for several reasons.
4512         // 1. GlobalBaseReg may have been spilled.
4513         // 2. It may not be live at MI.
4514         return nullptr;
4515     }
4516 
4517     // Create a constant-pool entry.
4518     MachineConstantPool &MCP = *MF.getConstantPool();
4519     Type *Ty;
4520     unsigned Opc = LoadMI->getOpcode();
4521     if (Opc == X86::FsFLD0SS)
4522       Ty = Type::getFloatTy(MF.getFunction()->getContext());
4523     else if (Opc == X86::FsFLD0SD)
4524       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
4525     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
4526       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
4527     else
4528       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
4529 
4530     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
4531     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4532                                     Constant::getNullValue(Ty);
4533     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
4534 
4535     // Create operands to load from the constant pool entry.
4536     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4537     MOs.push_back(MachineOperand::CreateImm(1));
4538     MOs.push_back(MachineOperand::CreateReg(0, false));
4539     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
4540     MOs.push_back(MachineOperand::CreateReg(0, false));
4541     break;
4542   }
4543   default: {
4544     if ((LoadMI->getOpcode() == X86::MOVSSrm ||
4545          LoadMI->getOpcode() == X86::VMOVSSrm) &&
4546         MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4547           > 4)
4548       // These instructions only load 32 bits, we can't fold them if the
4549       // destination register is wider than 32 bits (4 bytes).
4550       return nullptr;
4551     if ((LoadMI->getOpcode() == X86::MOVSDrm ||
4552          LoadMI->getOpcode() == X86::VMOVSDrm) &&
4553         MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4554           > 8)
4555       // These instructions only load 64 bits, we can't fold them if the
4556       // destination register is wider than 64 bits (8 bytes).
4557       return nullptr;
4558 
4559     // Folding a normal load. Just copy the load's address operands.
4560     for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
4561       MOs.push_back(LoadMI->getOperand(i));
4562     break;
4563   }
4564   }
4565   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
4566 }
4567 
4568 
4569 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4570                                   const SmallVectorImpl<unsigned> &Ops) const {
4571   // Check switch flag
4572   if (NoFusing) return 0;
4573 
4574   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4575     switch (MI->getOpcode()) {
4576     default: return false;
4577     case X86::TEST8rr:
4578     case X86::TEST16rr:
4579     case X86::TEST32rr:
4580     case X86::TEST64rr:
4581       return true;
4582     case X86::ADD32ri:
4583       // FIXME: AsmPrinter doesn't know how to handle
4584       // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4585       if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4586         return false;
4587       break;
4588     }
4589   }
4590 
4591   if (Ops.size() != 1)
4592     return false;
4593 
4594   unsigned OpNum = Ops[0];
4595   unsigned Opc = MI->getOpcode();
4596   unsigned NumOps = MI->getDesc().getNumOperands();
4597   bool isTwoAddr = NumOps > 1 &&
4598     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4599 
4600   // Folding a memory location into the two-address part of a two-address
4601   // instruction is different than folding it other places.  It requires
4602   // replacing the *two* registers with the memory location.
4603   const DenseMap<unsigned,
4604                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4605   if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
4606     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4607   } else if (OpNum == 0) { // If operand 0
4608     if (Opc == X86::MOV32r0)
4609       return true;
4610 
4611     OpcodeTablePtr = &RegOp2MemOpTable0;
4612   } else if (OpNum == 1) {
4613     OpcodeTablePtr = &RegOp2MemOpTable1;
4614   } else if (OpNum == 2) {
4615     OpcodeTablePtr = &RegOp2MemOpTable2;
4616   } else if (OpNum == 3) {
4617     OpcodeTablePtr = &RegOp2MemOpTable3;
4618   }
4619 
4620   if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4621     return true;
4622   return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
4623 }
4624 
4625 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4626                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
4627                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4628   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4629     MemOp2RegOpTable.find(MI->getOpcode());
4630   if (I == MemOp2RegOpTable.end())
4631     return false;
4632   unsigned Opc = I->second.first;
4633   unsigned Index = I->second.second & TB_INDEX_MASK;
4634   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4635   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4636   if (UnfoldLoad && !FoldedLoad)
4637     return false;
4638   UnfoldLoad &= FoldedLoad;
4639   if (UnfoldStore && !FoldedStore)
4640     return false;
4641   UnfoldStore &= FoldedStore;
4642 
4643   const MCInstrDesc &MCID = get(Opc);
4644   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4645   if (!MI->hasOneMemOperand() &&
4646       RC == &X86::VR128RegClass &&
4647       !Subtarget.isUnalignedMemAccessFast())
4648     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4649     // conservatively assume the address is unaligned. That's bad for
4650     // performance.
4651     return false;
4652   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
4653   SmallVector<MachineOperand,2> BeforeOps;
4654   SmallVector<MachineOperand,2> AfterOps;
4655   SmallVector<MachineOperand,4> ImpOps;
4656   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4657     MachineOperand &Op = MI->getOperand(i);
4658     if (i >= Index && i < Index + X86::AddrNumOperands)
4659       AddrOps.push_back(Op);
4660     else if (Op.isReg() && Op.isImplicit())
4661       ImpOps.push_back(Op);
4662     else if (i < Index)
4663       BeforeOps.push_back(Op);
4664     else if (i > Index)
4665       AfterOps.push_back(Op);
4666   }
4667 
4668   // Emit the load instruction.
4669   if (UnfoldLoad) {
4670     std::pair<MachineInstr::mmo_iterator,
4671               MachineInstr::mmo_iterator> MMOs =
4672       MF.extractLoadMemRefs(MI->memoperands_begin(),
4673                             MI->memoperands_end());
4674     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
4675     if (UnfoldStore) {
4676       // Address operands cannot be marked isKill.
4677       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
4678         MachineOperand &MO = NewMIs[0]->getOperand(i);
4679         if (MO.isReg())
4680           MO.setIsKill(false);
4681       }
4682     }
4683   }
4684 
4685   // Emit the data processing instruction.
4686   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
4687   MachineInstrBuilder MIB(MF, DataMI);
4688 
4689   if (FoldedStore)
4690     MIB.addReg(Reg, RegState::Define);
4691   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
4692     MIB.addOperand(BeforeOps[i]);
4693   if (FoldedLoad)
4694     MIB.addReg(Reg);
4695   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
4696     MIB.addOperand(AfterOps[i]);
4697   for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
4698     MachineOperand &MO = ImpOps[i];
4699     MIB.addReg(MO.getReg(),
4700                getDefRegState(MO.isDef()) |
4701                RegState::Implicit |
4702                getKillRegState(MO.isKill()) |
4703                getDeadRegState(MO.isDead()) |
4704                getUndefRegState(MO.isUndef()));
4705   }
4706   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
4707   switch (DataMI->getOpcode()) {
4708   default: break;
4709   case X86::CMP64ri32:
4710   case X86::CMP64ri8:
4711   case X86::CMP32ri:
4712   case X86::CMP32ri8:
4713   case X86::CMP16ri:
4714   case X86::CMP16ri8:
4715   case X86::CMP8ri: {
4716     MachineOperand &MO0 = DataMI->getOperand(0);
4717     MachineOperand &MO1 = DataMI->getOperand(1);
4718     if (MO1.getImm() == 0) {
4719       unsigned NewOpc;
4720       switch (DataMI->getOpcode()) {
4721       default: llvm_unreachable("Unreachable!");
4722       case X86::CMP64ri8:
4723       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
4724       case X86::CMP32ri8:
4725       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
4726       case X86::CMP16ri8:
4727       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
4728       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
4729       }
4730       DataMI->setDesc(get(NewOpc));
4731       MO1.ChangeToRegister(MO0.getReg(), false);
4732     }
4733   }
4734   }
4735   NewMIs.push_back(DataMI);
4736 
4737   // Emit the store instruction.
4738   if (UnfoldStore) {
4739     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
4740     std::pair<MachineInstr::mmo_iterator,
4741               MachineInstr::mmo_iterator> MMOs =
4742       MF.extractStoreMemRefs(MI->memoperands_begin(),
4743                              MI->memoperands_end());
4744     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
4745   }
4746 
4747   return true;
4748 }
4749 
4750 bool
4751 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
4752                                   SmallVectorImpl<SDNode*> &NewNodes) const {
4753   if (!N->isMachineOpcode())
4754     return false;
4755 
4756   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4757     MemOp2RegOpTable.find(N->getMachineOpcode());
4758   if (I == MemOp2RegOpTable.end())
4759     return false;
4760   unsigned Opc = I->second.first;
4761   unsigned Index = I->second.second & TB_INDEX_MASK;
4762   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4763   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4764   const MCInstrDesc &MCID = get(Opc);
4765   MachineFunction &MF = DAG.getMachineFunction();
4766   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4767   unsigned NumDefs = MCID.NumDefs;
4768   std::vector<SDValue> AddrOps;
4769   std::vector<SDValue> BeforeOps;
4770   std::vector<SDValue> AfterOps;
4771   SDLoc dl(N);
4772   unsigned NumOps = N->getNumOperands();
4773   for (unsigned i = 0; i != NumOps-1; ++i) {
4774     SDValue Op = N->getOperand(i);
4775     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
4776       AddrOps.push_back(Op);
4777     else if (i < Index-NumDefs)
4778       BeforeOps.push_back(Op);
4779     else if (i > Index-NumDefs)
4780       AfterOps.push_back(Op);
4781   }
4782   SDValue Chain = N->getOperand(NumOps-1);
4783   AddrOps.push_back(Chain);
4784 
4785   // Emit the load instruction.
4786   SDNode *Load = nullptr;
4787   if (FoldedLoad) {
4788     EVT VT = *RC->vt_begin();
4789     std::pair<MachineInstr::mmo_iterator,
4790               MachineInstr::mmo_iterator> MMOs =
4791       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4792                             cast<MachineSDNode>(N)->memoperands_end());
4793     if (!(*MMOs.first) &&
4794         RC == &X86::VR128RegClass &&
4795         !Subtarget.isUnalignedMemAccessFast())
4796       // Do not introduce a slow unaligned load.
4797       return false;
4798     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4799     bool isAligned = (*MMOs.first) &&
4800                      (*MMOs.first)->getAlignment() >= Alignment;
4801     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
4802                               VT, MVT::Other, AddrOps);
4803     NewNodes.push_back(Load);
4804 
4805     // Preserve memory reference information.
4806     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4807   }
4808 
4809   // Emit the data processing instruction.
4810   std::vector<EVT> VTs;
4811   const TargetRegisterClass *DstRC = nullptr;
4812   if (MCID.getNumDefs() > 0) {
4813     DstRC = getRegClass(MCID, 0, &RI, MF);
4814     VTs.push_back(*DstRC->vt_begin());
4815   }
4816   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
4817     EVT VT = N->getValueType(i);
4818     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
4819       VTs.push_back(VT);
4820   }
4821   if (Load)
4822     BeforeOps.push_back(SDValue(Load, 0));
4823   std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
4824   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
4825   NewNodes.push_back(NewNode);
4826 
4827   // Emit the store instruction.
4828   if (FoldedStore) {
4829     AddrOps.pop_back();
4830     AddrOps.push_back(SDValue(NewNode, 0));
4831     AddrOps.push_back(Chain);
4832     std::pair<MachineInstr::mmo_iterator,
4833               MachineInstr::mmo_iterator> MMOs =
4834       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4835                              cast<MachineSDNode>(N)->memoperands_end());
4836     if (!(*MMOs.first) &&
4837         RC == &X86::VR128RegClass &&
4838         !Subtarget.isUnalignedMemAccessFast())
4839       // Do not introduce a slow unaligned store.
4840       return false;
4841     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4842     bool isAligned = (*MMOs.first) &&
4843                      (*MMOs.first)->getAlignment() >= Alignment;
4844     SDNode *Store =
4845         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
4846                            dl, MVT::Other, AddrOps);
4847     NewNodes.push_back(Store);
4848 
4849     // Preserve memory reference information.
4850     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4851   }
4852 
4853   return true;
4854 }
4855 
4856 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
4857                                       bool UnfoldLoad, bool UnfoldStore,
4858                                       unsigned *LoadRegIndex) const {
4859   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4860     MemOp2RegOpTable.find(Opc);
4861   if (I == MemOp2RegOpTable.end())
4862     return 0;
4863   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4864   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4865   if (UnfoldLoad && !FoldedLoad)
4866     return 0;
4867   if (UnfoldStore && !FoldedStore)
4868     return 0;
4869   if (LoadRegIndex)
4870     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
4871   return I->second.first;
4872 }
4873 
4874 bool
4875 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
4876                                      int64_t &Offset1, int64_t &Offset2) const {
4877   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
4878     return false;
4879   unsigned Opc1 = Load1->getMachineOpcode();
4880   unsigned Opc2 = Load2->getMachineOpcode();
4881   switch (Opc1) {
4882   default: return false;
4883   case X86::MOV8rm:
4884   case X86::MOV16rm:
4885   case X86::MOV32rm:
4886   case X86::MOV64rm:
4887   case X86::LD_Fp32m:
4888   case X86::LD_Fp64m:
4889   case X86::LD_Fp80m:
4890   case X86::MOVSSrm:
4891   case X86::MOVSDrm:
4892   case X86::MMX_MOVD64rm:
4893   case X86::MMX_MOVQ64rm:
4894   case X86::FsMOVAPSrm:
4895   case X86::FsMOVAPDrm:
4896   case X86::MOVAPSrm:
4897   case X86::MOVUPSrm:
4898   case X86::MOVAPDrm:
4899   case X86::MOVDQArm:
4900   case X86::MOVDQUrm:
4901   // AVX load instructions
4902   case X86::VMOVSSrm:
4903   case X86::VMOVSDrm:
4904   case X86::FsVMOVAPSrm:
4905   case X86::FsVMOVAPDrm:
4906   case X86::VMOVAPSrm:
4907   case X86::VMOVUPSrm:
4908   case X86::VMOVAPDrm:
4909   case X86::VMOVDQArm:
4910   case X86::VMOVDQUrm:
4911   case X86::VMOVAPSYrm:
4912   case X86::VMOVUPSYrm:
4913   case X86::VMOVAPDYrm:
4914   case X86::VMOVDQAYrm:
4915   case X86::VMOVDQUYrm:
4916     break;
4917   }
4918   switch (Opc2) {
4919   default: return false;
4920   case X86::MOV8rm:
4921   case X86::MOV16rm:
4922   case X86::MOV32rm:
4923   case X86::MOV64rm:
4924   case X86::LD_Fp32m:
4925   case X86::LD_Fp64m:
4926   case X86::LD_Fp80m:
4927   case X86::MOVSSrm:
4928   case X86::MOVSDrm:
4929   case X86::MMX_MOVD64rm:
4930   case X86::MMX_MOVQ64rm:
4931   case X86::FsMOVAPSrm:
4932   case X86::FsMOVAPDrm:
4933   case X86::MOVAPSrm:
4934   case X86::MOVUPSrm:
4935   case X86::MOVAPDrm:
4936   case X86::MOVDQArm:
4937   case X86::MOVDQUrm:
4938   // AVX load instructions
4939   case X86::VMOVSSrm:
4940   case X86::VMOVSDrm:
4941   case X86::FsVMOVAPSrm:
4942   case X86::FsVMOVAPDrm:
4943   case X86::VMOVAPSrm:
4944   case X86::VMOVUPSrm:
4945   case X86::VMOVAPDrm:
4946   case X86::VMOVDQArm:
4947   case X86::VMOVDQUrm:
4948   case X86::VMOVAPSYrm:
4949   case X86::VMOVUPSYrm:
4950   case X86::VMOVAPDYrm:
4951   case X86::VMOVDQAYrm:
4952   case X86::VMOVDQUYrm:
4953     break;
4954   }
4955 
4956   // Check if chain operands and base addresses match.
4957   if (Load1->getOperand(0) != Load2->getOperand(0) ||
4958       Load1->getOperand(5) != Load2->getOperand(5))
4959     return false;
4960   // Segment operands should match as well.
4961   if (Load1->getOperand(4) != Load2->getOperand(4))
4962     return false;
4963   // Scale should be 1, Index should be Reg0.
4964   if (Load1->getOperand(1) == Load2->getOperand(1) &&
4965       Load1->getOperand(2) == Load2->getOperand(2)) {
4966     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
4967       return false;
4968 
4969     // Now let's examine the displacements.
4970     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
4971         isa<ConstantSDNode>(Load2->getOperand(3))) {
4972       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
4973       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
4974       return true;
4975     }
4976   }
4977   return false;
4978 }
4979 
4980 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
4981                                            int64_t Offset1, int64_t Offset2,
4982                                            unsigned NumLoads) const {
4983   assert(Offset2 > Offset1);
4984   if ((Offset2 - Offset1) / 8 > 64)
4985     return false;
4986 
4987   unsigned Opc1 = Load1->getMachineOpcode();
4988   unsigned Opc2 = Load2->getMachineOpcode();
4989   if (Opc1 != Opc2)
4990     return false;  // FIXME: overly conservative?
4991 
4992   switch (Opc1) {
4993   default: break;
4994   case X86::LD_Fp32m:
4995   case X86::LD_Fp64m:
4996   case X86::LD_Fp80m:
4997   case X86::MMX_MOVD64rm:
4998   case X86::MMX_MOVQ64rm:
4999     return false;
5000   }
5001 
5002   EVT VT = Load1->getValueType(0);
5003   switch (VT.getSimpleVT().SimpleTy) {
5004   default:
5005     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5006     // have 16 of them to play with.
5007     if (Subtarget.is64Bit()) {
5008       if (NumLoads >= 3)
5009         return false;
5010     } else if (NumLoads) {
5011       return false;
5012     }
5013     break;
5014   case MVT::i8:
5015   case MVT::i16:
5016   case MVT::i32:
5017   case MVT::i64:
5018   case MVT::f32:
5019   case MVT::f64:
5020     if (NumLoads)
5021       return false;
5022     break;
5023   }
5024 
5025   return true;
5026 }
5027 
5028 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5029                                           MachineInstr *Second) const {
5030   // Check if this processor supports macro-fusion. Since this is a minor
5031   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5032   // proxy for SandyBridge+.
5033   if (!Subtarget.hasAVX())
5034     return false;
5035 
5036   enum {
5037     FuseTest,
5038     FuseCmp,
5039     FuseInc
5040   } FuseKind;
5041 
5042   switch(Second->getOpcode()) {
5043   default:
5044     return false;
5045   case X86::JE_4:
5046   case X86::JNE_4:
5047   case X86::JL_4:
5048   case X86::JLE_4:
5049   case X86::JG_4:
5050   case X86::JGE_4:
5051     FuseKind = FuseInc;
5052     break;
5053   case X86::JB_4:
5054   case X86::JBE_4:
5055   case X86::JA_4:
5056   case X86::JAE_4:
5057     FuseKind = FuseCmp;
5058     break;
5059   case X86::JS_4:
5060   case X86::JNS_4:
5061   case X86::JP_4:
5062   case X86::JNP_4:
5063   case X86::JO_4:
5064   case X86::JNO_4:
5065     FuseKind = FuseTest;
5066     break;
5067   }
5068   switch (First->getOpcode()) {
5069   default:
5070     return false;
5071   case X86::TEST8rr:
5072   case X86::TEST16rr:
5073   case X86::TEST32rr:
5074   case X86::TEST64rr:
5075   case X86::TEST8ri:
5076   case X86::TEST16ri:
5077   case X86::TEST32ri:
5078   case X86::TEST32i32:
5079   case X86::TEST64i32:
5080   case X86::TEST64ri32:
5081   case X86::TEST8rm:
5082   case X86::TEST16rm:
5083   case X86::TEST32rm:
5084   case X86::TEST64rm:
5085   case X86::TEST8ri_NOREX:
5086   case X86::AND16i16:
5087   case X86::AND16ri:
5088   case X86::AND16ri8:
5089   case X86::AND16rm:
5090   case X86::AND16rr:
5091   case X86::AND32i32:
5092   case X86::AND32ri:
5093   case X86::AND32ri8:
5094   case X86::AND32rm:
5095   case X86::AND32rr:
5096   case X86::AND64i32:
5097   case X86::AND64ri32:
5098   case X86::AND64ri8:
5099   case X86::AND64rm:
5100   case X86::AND64rr:
5101   case X86::AND8i8:
5102   case X86::AND8ri:
5103   case X86::AND8rm:
5104   case X86::AND8rr:
5105     return true;
5106   case X86::CMP16i16:
5107   case X86::CMP16ri:
5108   case X86::CMP16ri8:
5109   case X86::CMP16rm:
5110   case X86::CMP16rr:
5111   case X86::CMP32i32:
5112   case X86::CMP32ri:
5113   case X86::CMP32ri8:
5114   case X86::CMP32rm:
5115   case X86::CMP32rr:
5116   case X86::CMP64i32:
5117   case X86::CMP64ri32:
5118   case X86::CMP64ri8:
5119   case X86::CMP64rm:
5120   case X86::CMP64rr:
5121   case X86::CMP8i8:
5122   case X86::CMP8ri:
5123   case X86::CMP8rm:
5124   case X86::CMP8rr:
5125   case X86::ADD16i16:
5126   case X86::ADD16ri:
5127   case X86::ADD16ri8:
5128   case X86::ADD16ri8_DB:
5129   case X86::ADD16ri_DB:
5130   case X86::ADD16rm:
5131   case X86::ADD16rr:
5132   case X86::ADD16rr_DB:
5133   case X86::ADD32i32:
5134   case X86::ADD32ri:
5135   case X86::ADD32ri8:
5136   case X86::ADD32ri8_DB:
5137   case X86::ADD32ri_DB:
5138   case X86::ADD32rm:
5139   case X86::ADD32rr:
5140   case X86::ADD32rr_DB:
5141   case X86::ADD64i32:
5142   case X86::ADD64ri32:
5143   case X86::ADD64ri32_DB:
5144   case X86::ADD64ri8:
5145   case X86::ADD64ri8_DB:
5146   case X86::ADD64rm:
5147   case X86::ADD64rr:
5148   case X86::ADD64rr_DB:
5149   case X86::ADD8i8:
5150   case X86::ADD8mi:
5151   case X86::ADD8mr:
5152   case X86::ADD8ri:
5153   case X86::ADD8rm:
5154   case X86::ADD8rr:
5155   case X86::SUB16i16:
5156   case X86::SUB16ri:
5157   case X86::SUB16ri8:
5158   case X86::SUB16rm:
5159   case X86::SUB16rr:
5160   case X86::SUB32i32:
5161   case X86::SUB32ri:
5162   case X86::SUB32ri8:
5163   case X86::SUB32rm:
5164   case X86::SUB32rr:
5165   case X86::SUB64i32:
5166   case X86::SUB64ri32:
5167   case X86::SUB64ri8:
5168   case X86::SUB64rm:
5169   case X86::SUB64rr:
5170   case X86::SUB8i8:
5171   case X86::SUB8ri:
5172   case X86::SUB8rm:
5173   case X86::SUB8rr:
5174     return FuseKind == FuseCmp || FuseKind == FuseInc;
5175   case X86::INC16r:
5176   case X86::INC32r:
5177   case X86::INC64_16r:
5178   case X86::INC64_32r:
5179   case X86::INC64r:
5180   case X86::INC8r:
5181   case X86::DEC16r:
5182   case X86::DEC32r:
5183   case X86::DEC64_16r:
5184   case X86::DEC64_32r:
5185   case X86::DEC64r:
5186   case X86::DEC8r:
5187     return FuseKind == FuseInc;
5188   }
5189 }
5190 
5191 bool X86InstrInfo::
5192 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5193   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5194   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5195   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5196     return true;
5197   Cond[0].setImm(GetOppositeBranchCondition(CC));
5198   return false;
5199 }
5200 
5201 bool X86InstrInfo::
5202 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5203   // FIXME: Return false for x87 stack register classes for now. We can't
5204   // allow any loads of these registers before FpGet_ST0_80.
5205   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5206            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
5207 }
5208 
5209 /// getGlobalBaseReg - Return a virtual register initialized with the
5210 /// the global base register value. Output instructions required to
5211 /// initialize the register in the function entry block, if necessary.
5212 ///
5213 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5214 ///
5215 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5216   assert(!Subtarget.is64Bit() &&
5217          "X86-64 PIC uses RIP relative addressing");
5218 
5219   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5220   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5221   if (GlobalBaseReg != 0)
5222     return GlobalBaseReg;
5223 
5224   // Create the register. The code to initialize it is inserted
5225   // later, by the CGBR pass (below).
5226   MachineRegisterInfo &RegInfo = MF->getRegInfo();
5227   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
5228   X86FI->setGlobalBaseReg(GlobalBaseReg);
5229   return GlobalBaseReg;
5230 }
5231 
5232 // These are the replaceable SSE instructions. Some of these have Int variants
5233 // that we don't include here. We don't want to replace instructions selected
5234 // by intrinsics.
5235 static const uint16_t ReplaceableInstrs[][3] = {
5236   //PackedSingle     PackedDouble    PackedInt
5237   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
5238   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
5239   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
5240   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
5241   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
5242   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
5243   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
5244   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
5245   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
5246   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
5247   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
5248   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
5249   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
5250   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
5251   // AVX 128-bit support
5252   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
5253   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
5254   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
5255   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
5256   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
5257   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5258   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
5259   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
5260   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
5261   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
5262   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
5263   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
5264   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
5265   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
5266   // AVX 256-bit support
5267   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
5268   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
5269   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
5270   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
5271   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
5272   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
5273 };
5274 
5275 static const uint16_t ReplaceableInstrsAVX2[][3] = {
5276   //PackedSingle       PackedDouble       PackedInt
5277   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
5278   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
5279   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
5280   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
5281   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
5282   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
5283   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
5284   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
5285   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5286   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5287   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
5288   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
5289   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
5290   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
5291   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5292   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5293   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5294   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5295   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5296   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
5297 };
5298 
5299 // FIXME: Some shuffle and unpack instructions have equivalents in different
5300 // domains, but they require a bit more work than just switching opcodes.
5301 
5302 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
5303   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
5304     if (ReplaceableInstrs[i][domain-1] == opcode)
5305       return ReplaceableInstrs[i];
5306   return nullptr;
5307 }
5308 
5309 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
5310   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5311     if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5312       return ReplaceableInstrsAVX2[i];
5313   return nullptr;
5314 }
5315 
5316 std::pair<uint16_t, uint16_t>
5317 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
5318   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5319   bool hasAVX2 = Subtarget.hasAVX2();
5320   uint16_t validDomains = 0;
5321   if (domain && lookup(MI->getOpcode(), domain))
5322     validDomains = 0xe;
5323   else if (domain && lookupAVX2(MI->getOpcode(), domain))
5324     validDomains = hasAVX2 ? 0xe : 0x6;
5325   return std::make_pair(domain, validDomains);
5326 }
5327 
5328 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
5329   assert(Domain>0 && Domain<4 && "Invalid execution domain");
5330   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5331   assert(dom && "Not an SSE instruction");
5332   const uint16_t *table = lookup(MI->getOpcode(), dom);
5333   if (!table) { // try the other table
5334     assert((Subtarget.hasAVX2() || Domain < 3) &&
5335            "256-bit vector operations only available in AVX2");
5336     table = lookupAVX2(MI->getOpcode(), dom);
5337   }
5338   assert(table && "Cannot change domain");
5339   MI->setDesc(get(table[Domain-1]));
5340 }
5341 
5342 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5343 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5344   NopInst.setOpcode(X86::NOOP);
5345 }
5346 
5347 void X86InstrInfo::getUnconditionalBranch(
5348     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
5349   Branch.setOpcode(X86::JMP_4);
5350   Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
5351 }
5352 
5353 void X86InstrInfo::getTrap(MCInst &MI) const {
5354   MI.setOpcode(X86::TRAP);
5355 }
5356 
5357 bool X86InstrInfo::isHighLatencyDef(int opc) const {
5358   switch (opc) {
5359   default: return false;
5360   case X86::DIVSDrm:
5361   case X86::DIVSDrm_Int:
5362   case X86::DIVSDrr:
5363   case X86::DIVSDrr_Int:
5364   case X86::DIVSSrm:
5365   case X86::DIVSSrm_Int:
5366   case X86::DIVSSrr:
5367   case X86::DIVSSrr_Int:
5368   case X86::SQRTPDm:
5369   case X86::SQRTPDr:
5370   case X86::SQRTPSm:
5371   case X86::SQRTPSr:
5372   case X86::SQRTSDm:
5373   case X86::SQRTSDm_Int:
5374   case X86::SQRTSDr:
5375   case X86::SQRTSDr_Int:
5376   case X86::SQRTSSm:
5377   case X86::SQRTSSm_Int:
5378   case X86::SQRTSSr:
5379   case X86::SQRTSSr_Int:
5380   // AVX instructions with high latency
5381   case X86::VDIVSDrm:
5382   case X86::VDIVSDrm_Int:
5383   case X86::VDIVSDrr:
5384   case X86::VDIVSDrr_Int:
5385   case X86::VDIVSSrm:
5386   case X86::VDIVSSrm_Int:
5387   case X86::VDIVSSrr:
5388   case X86::VDIVSSrr_Int:
5389   case X86::VSQRTPDm:
5390   case X86::VSQRTPDr:
5391   case X86::VSQRTPSm:
5392   case X86::VSQRTPSr:
5393   case X86::VSQRTSDm:
5394   case X86::VSQRTSDm_Int:
5395   case X86::VSQRTSDr:
5396   case X86::VSQRTSSm:
5397   case X86::VSQRTSSm_Int:
5398   case X86::VSQRTSSr:
5399   case X86::VSQRTPDZrm:
5400   case X86::VSQRTPDZrr:
5401   case X86::VSQRTPSZrm:
5402   case X86::VSQRTPSZrr:
5403   case X86::VSQRTSDZm:
5404   case X86::VSQRTSDZm_Int:
5405   case X86::VSQRTSDZr:
5406   case X86::VSQRTSSZm_Int:
5407   case X86::VSQRTSSZr:
5408   case X86::VSQRTSSZm:
5409   case X86::VDIVSDZrm:
5410   case X86::VDIVSDZrr:
5411   case X86::VDIVSSZrm:
5412   case X86::VDIVSSZrr:
5413 
5414   case X86::VGATHERQPSZrm:
5415   case X86::VGATHERQPDZrm:
5416   case X86::VGATHERDPDZrm:
5417   case X86::VGATHERDPSZrm:
5418   case X86::VPGATHERQDZrm:
5419   case X86::VPGATHERQQZrm:
5420   case X86::VPGATHERDDZrm:
5421   case X86::VPGATHERDQZrm:
5422   case X86::VSCATTERQPDZmr:
5423   case X86::VSCATTERQPSZmr:
5424   case X86::VSCATTERDPDZmr:
5425   case X86::VSCATTERDPSZmr:
5426   case X86::VPSCATTERQDZmr:
5427   case X86::VPSCATTERQQZmr:
5428   case X86::VPSCATTERDDZmr:
5429   case X86::VPSCATTERDQZmr:
5430     return true;
5431   }
5432 }
5433 
5434 bool X86InstrInfo::
5435 hasHighOperandLatency(const InstrItineraryData *ItinData,
5436                       const MachineRegisterInfo *MRI,
5437                       const MachineInstr *DefMI, unsigned DefIdx,
5438                       const MachineInstr *UseMI, unsigned UseIdx) const {
5439   return isHighLatencyDef(DefMI->getOpcode());
5440 }
5441 
5442 namespace {
5443   /// CGBR - Create Global Base Reg pass. This initializes the PIC
5444   /// global base register for x86-32.
5445   struct CGBR : public MachineFunctionPass {
5446     static char ID;
5447     CGBR() : MachineFunctionPass(ID) {}
5448 
5449     bool runOnMachineFunction(MachineFunction &MF) override {
5450       const X86TargetMachine *TM =
5451         static_cast<const X86TargetMachine *>(&MF.getTarget());
5452 
5453       // Don't do anything if this is 64-bit as 64-bit PIC
5454       // uses RIP relative addressing.
5455       if (TM->getSubtarget<X86Subtarget>().is64Bit())
5456         return false;
5457 
5458       // Only emit a global base reg in PIC mode.
5459       if (TM->getRelocationModel() != Reloc::PIC_)
5460         return false;
5461 
5462       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
5463       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5464 
5465       // If we didn't need a GlobalBaseReg, don't insert code.
5466       if (GlobalBaseReg == 0)
5467         return false;
5468 
5469       // Insert the set of GlobalBaseReg into the first MBB of the function
5470       MachineBasicBlock &FirstMBB = MF.front();
5471       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
5472       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
5473       MachineRegisterInfo &RegInfo = MF.getRegInfo();
5474       const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5475 
5476       unsigned PC;
5477       if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
5478         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
5479       else
5480         PC = GlobalBaseReg;
5481 
5482       // Operand of MovePCtoStack is completely ignored by asm printer. It's
5483       // only used in JIT code emission as displacement to pc.
5484       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
5485 
5486       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
5487       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
5488       if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
5489         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
5490         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5491           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
5492                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
5493       }
5494 
5495       return true;
5496     }
5497 
5498     const char *getPassName() const override {
5499       return "X86 PIC Global Base Reg Initialization";
5500     }
5501 
5502     void getAnalysisUsage(AnalysisUsage &AU) const override {
5503       AU.setPreservesCFG();
5504       MachineFunctionPass::getAnalysisUsage(AU);
5505     }
5506   };
5507 }
5508 
5509 char CGBR::ID = 0;
5510 FunctionPass*
5511 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
5512 
5513 namespace {
5514   struct LDTLSCleanup : public MachineFunctionPass {
5515     static char ID;
5516     LDTLSCleanup() : MachineFunctionPass(ID) {}
5517 
5518     bool runOnMachineFunction(MachineFunction &MF) override {
5519       X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
5520       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
5521         // No point folding accesses if there isn't at least two.
5522         return false;
5523       }
5524 
5525       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
5526       return VisitNode(DT->getRootNode(), 0);
5527     }
5528 
5529     // Visit the dominator subtree rooted at Node in pre-order.
5530     // If TLSBaseAddrReg is non-null, then use that to replace any
5531     // TLS_base_addr instructions. Otherwise, create the register
5532     // when the first such instruction is seen, and then use it
5533     // as we encounter more instructions.
5534     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
5535       MachineBasicBlock *BB = Node->getBlock();
5536       bool Changed = false;
5537 
5538       // Traverse the current block.
5539       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
5540            ++I) {
5541         switch (I->getOpcode()) {
5542           case X86::TLS_base_addr32:
5543           case X86::TLS_base_addr64:
5544             if (TLSBaseAddrReg)
5545               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
5546             else
5547               I = SetRegister(I, &TLSBaseAddrReg);
5548             Changed = true;
5549             break;
5550           default:
5551             break;
5552         }
5553       }
5554 
5555       // Visit the children of this block in the dominator tree.
5556       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
5557            I != E; ++I) {
5558         Changed |= VisitNode(*I, TLSBaseAddrReg);
5559       }
5560 
5561       return Changed;
5562     }
5563 
5564     // Replace the TLS_base_addr instruction I with a copy from
5565     // TLSBaseAddrReg, returning the new instruction.
5566     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
5567                                          unsigned TLSBaseAddrReg) {
5568       MachineFunction *MF = I->getParent()->getParent();
5569       const X86TargetMachine *TM =
5570           static_cast<const X86TargetMachine *>(&MF->getTarget());
5571       const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5572       const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5573 
5574       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5575       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
5576                                    TII->get(TargetOpcode::COPY),
5577                                    is64Bit ? X86::RAX : X86::EAX)
5578                                    .addReg(TLSBaseAddrReg);
5579 
5580       // Erase the TLS_base_addr instruction.
5581       I->eraseFromParent();
5582 
5583       return Copy;
5584     }
5585 
5586     // Create a virtal register in *TLSBaseAddrReg, and populate it by
5587     // inserting a copy instruction after I. Returns the new instruction.
5588     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
5589       MachineFunction *MF = I->getParent()->getParent();
5590       const X86TargetMachine *TM =
5591           static_cast<const X86TargetMachine *>(&MF->getTarget());
5592       const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5593       const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5594 
5595       // Create a virtual register for the TLS base address.
5596       MachineRegisterInfo &RegInfo = MF->getRegInfo();
5597       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
5598                                                       ? &X86::GR64RegClass
5599                                                       : &X86::GR32RegClass);
5600 
5601       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
5602       MachineInstr *Next = I->getNextNode();
5603       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
5604                                    TII->get(TargetOpcode::COPY),
5605                                    *TLSBaseAddrReg)
5606                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
5607 
5608       return Copy;
5609     }
5610 
5611     const char *getPassName() const override {
5612       return "Local Dynamic TLS Access Clean-up";
5613     }
5614 
5615     void getAnalysisUsage(AnalysisUsage &AU) const override {
5616       AU.setPreservesCFG();
5617       AU.addRequired<MachineDominatorTree>();
5618       MachineFunctionPass::getAnalysisUsage(AU);
5619     }
5620   };
5621 }
5622 
5623 char LDTLSCleanup::ID = 0;
5624 FunctionPass*
5625 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
5626