1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LivePhysRegs.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DebugInfoMetadata.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "x86-instr-info"
46 
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "X86GenInstrInfo.inc"
49 
50 static cl::opt<bool>
51     NoFusing("disable-spill-fusing",
52              cl::desc("Disable fusing of spill code into instructions"),
53              cl::Hidden);
54 static cl::opt<bool>
55 PrintFailedFusing("print-failed-fuse-candidates",
56                   cl::desc("Print instructions that the allocator wants to"
57                            " fuse, but the X86 backend currently can't"),
58                   cl::Hidden);
59 static cl::opt<bool>
60 ReMatPICStubLoad("remat-pic-stub-load",
61                  cl::desc("Re-materialize load from stub in PIC mode"),
62                  cl::init(false), cl::Hidden);
63 static cl::opt<unsigned>
64 PartialRegUpdateClearance("partial-reg-update-clearance",
65                           cl::desc("Clearance between two register writes "
66                                    "for inserting XOR to avoid partial "
67                                    "register update"),
68                           cl::init(64), cl::Hidden);
69 static cl::opt<unsigned>
70 UndefRegClearance("undef-reg-clearance",
71                   cl::desc("How many idle instructions we would like before "
72                            "certain undef register reads"),
73                   cl::init(128), cl::Hidden);
74 
75 
76 // Pin the vtable to this file.
77 void X86InstrInfo::anchor() {}
78 
79 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81                                                : X86::ADJCALLSTACKDOWN32),
82                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83                                                : X86::ADJCALLSTACKUP32),
84                       X86::CATCHRET,
85                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86       Subtarget(STI), RI(STI.getTargetTriple()) {
87 }
88 
89 bool
90 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91                                     Register &SrcReg, Register &DstReg,
92                                     unsigned &SubIdx) const {
93   switch (MI.getOpcode()) {
94   default: break;
95   case X86::MOVSX16rr8:
96   case X86::MOVZX16rr8:
97   case X86::MOVSX32rr8:
98   case X86::MOVZX32rr8:
99   case X86::MOVSX64rr8:
100     if (!Subtarget.is64Bit())
101       // It's not always legal to reference the low 8-bit of the larger
102       // register in 32-bit mode.
103       return false;
104     LLVM_FALLTHROUGH;
105   case X86::MOVSX32rr16:
106   case X86::MOVZX32rr16:
107   case X86::MOVSX64rr16:
108   case X86::MOVSX64rr32: {
109     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110       // Be conservative.
111       return false;
112     SrcReg = MI.getOperand(1).getReg();
113     DstReg = MI.getOperand(0).getReg();
114     switch (MI.getOpcode()) {
115     default: llvm_unreachable("Unreachable!");
116     case X86::MOVSX16rr8:
117     case X86::MOVZX16rr8:
118     case X86::MOVSX32rr8:
119     case X86::MOVZX32rr8:
120     case X86::MOVSX64rr8:
121       SubIdx = X86::sub_8bit;
122       break;
123     case X86::MOVSX32rr16:
124     case X86::MOVZX32rr16:
125     case X86::MOVSX64rr16:
126       SubIdx = X86::sub_16bit;
127       break;
128     case X86::MOVSX64rr32:
129       SubIdx = X86::sub_32bit;
130       break;
131     }
132     return true;
133   }
134   }
135   return false;
136 }
137 
138 bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
139   switch (MI.getOpcode()) {
140   default:
141     // By default, assume that the instruction is not data invariant.
142     return false;
143 
144     // Some target-independent operations that trivially lower to data-invariant
145     // instructions.
146   case TargetOpcode::COPY:
147   case TargetOpcode::INSERT_SUBREG:
148   case TargetOpcode::SUBREG_TO_REG:
149     return true;
150 
151   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
152   // However, they set flags and are perhaps the most surprisingly constant
153   // time operations so we call them out here separately.
154   case X86::IMUL16rr:
155   case X86::IMUL16rri8:
156   case X86::IMUL16rri:
157   case X86::IMUL32rr:
158   case X86::IMUL32rri8:
159   case X86::IMUL32rri:
160   case X86::IMUL64rr:
161   case X86::IMUL64rri32:
162   case X86::IMUL64rri8:
163 
164   // Bit scanning and counting instructions that are somewhat surprisingly
165   // constant time as they scan across bits and do other fairly complex
166   // operations like popcnt, but are believed to be constant time on x86.
167   // However, these set flags.
168   case X86::BSF16rr:
169   case X86::BSF32rr:
170   case X86::BSF64rr:
171   case X86::BSR16rr:
172   case X86::BSR32rr:
173   case X86::BSR64rr:
174   case X86::LZCNT16rr:
175   case X86::LZCNT32rr:
176   case X86::LZCNT64rr:
177   case X86::POPCNT16rr:
178   case X86::POPCNT32rr:
179   case X86::POPCNT64rr:
180   case X86::TZCNT16rr:
181   case X86::TZCNT32rr:
182   case X86::TZCNT64rr:
183 
184   // Bit manipulation instructions are effectively combinations of basic
185   // arithmetic ops, and should still execute in constant time. These also
186   // set flags.
187   case X86::BLCFILL32rr:
188   case X86::BLCFILL64rr:
189   case X86::BLCI32rr:
190   case X86::BLCI64rr:
191   case X86::BLCIC32rr:
192   case X86::BLCIC64rr:
193   case X86::BLCMSK32rr:
194   case X86::BLCMSK64rr:
195   case X86::BLCS32rr:
196   case X86::BLCS64rr:
197   case X86::BLSFILL32rr:
198   case X86::BLSFILL64rr:
199   case X86::BLSI32rr:
200   case X86::BLSI64rr:
201   case X86::BLSIC32rr:
202   case X86::BLSIC64rr:
203   case X86::BLSMSK32rr:
204   case X86::BLSMSK64rr:
205   case X86::BLSR32rr:
206   case X86::BLSR64rr:
207   case X86::TZMSK32rr:
208   case X86::TZMSK64rr:
209 
210   // Bit extracting and clearing instructions should execute in constant time,
211   // and set flags.
212   case X86::BEXTR32rr:
213   case X86::BEXTR64rr:
214   case X86::BEXTRI32ri:
215   case X86::BEXTRI64ri:
216   case X86::BZHI32rr:
217   case X86::BZHI64rr:
218 
219   // Shift and rotate.
220   case X86::ROL8r1:
221   case X86::ROL16r1:
222   case X86::ROL32r1:
223   case X86::ROL64r1:
224   case X86::ROL8rCL:
225   case X86::ROL16rCL:
226   case X86::ROL32rCL:
227   case X86::ROL64rCL:
228   case X86::ROL8ri:
229   case X86::ROL16ri:
230   case X86::ROL32ri:
231   case X86::ROL64ri:
232   case X86::ROR8r1:
233   case X86::ROR16r1:
234   case X86::ROR32r1:
235   case X86::ROR64r1:
236   case X86::ROR8rCL:
237   case X86::ROR16rCL:
238   case X86::ROR32rCL:
239   case X86::ROR64rCL:
240   case X86::ROR8ri:
241   case X86::ROR16ri:
242   case X86::ROR32ri:
243   case X86::ROR64ri:
244   case X86::SAR8r1:
245   case X86::SAR16r1:
246   case X86::SAR32r1:
247   case X86::SAR64r1:
248   case X86::SAR8rCL:
249   case X86::SAR16rCL:
250   case X86::SAR32rCL:
251   case X86::SAR64rCL:
252   case X86::SAR8ri:
253   case X86::SAR16ri:
254   case X86::SAR32ri:
255   case X86::SAR64ri:
256   case X86::SHL8r1:
257   case X86::SHL16r1:
258   case X86::SHL32r1:
259   case X86::SHL64r1:
260   case X86::SHL8rCL:
261   case X86::SHL16rCL:
262   case X86::SHL32rCL:
263   case X86::SHL64rCL:
264   case X86::SHL8ri:
265   case X86::SHL16ri:
266   case X86::SHL32ri:
267   case X86::SHL64ri:
268   case X86::SHR8r1:
269   case X86::SHR16r1:
270   case X86::SHR32r1:
271   case X86::SHR64r1:
272   case X86::SHR8rCL:
273   case X86::SHR16rCL:
274   case X86::SHR32rCL:
275   case X86::SHR64rCL:
276   case X86::SHR8ri:
277   case X86::SHR16ri:
278   case X86::SHR32ri:
279   case X86::SHR64ri:
280   case X86::SHLD16rrCL:
281   case X86::SHLD32rrCL:
282   case X86::SHLD64rrCL:
283   case X86::SHLD16rri8:
284   case X86::SHLD32rri8:
285   case X86::SHLD64rri8:
286   case X86::SHRD16rrCL:
287   case X86::SHRD32rrCL:
288   case X86::SHRD64rrCL:
289   case X86::SHRD16rri8:
290   case X86::SHRD32rri8:
291   case X86::SHRD64rri8:
292 
293   // Basic arithmetic is constant time on the input but does set flags.
294   case X86::ADC8rr:
295   case X86::ADC8ri:
296   case X86::ADC16rr:
297   case X86::ADC16ri:
298   case X86::ADC16ri8:
299   case X86::ADC32rr:
300   case X86::ADC32ri:
301   case X86::ADC32ri8:
302   case X86::ADC64rr:
303   case X86::ADC64ri8:
304   case X86::ADC64ri32:
305   case X86::ADD8rr:
306   case X86::ADD8ri:
307   case X86::ADD16rr:
308   case X86::ADD16ri:
309   case X86::ADD16ri8:
310   case X86::ADD32rr:
311   case X86::ADD32ri:
312   case X86::ADD32ri8:
313   case X86::ADD64rr:
314   case X86::ADD64ri8:
315   case X86::ADD64ri32:
316   case X86::AND8rr:
317   case X86::AND8ri:
318   case X86::AND16rr:
319   case X86::AND16ri:
320   case X86::AND16ri8:
321   case X86::AND32rr:
322   case X86::AND32ri:
323   case X86::AND32ri8:
324   case X86::AND64rr:
325   case X86::AND64ri8:
326   case X86::AND64ri32:
327   case X86::OR8rr:
328   case X86::OR8ri:
329   case X86::OR16rr:
330   case X86::OR16ri:
331   case X86::OR16ri8:
332   case X86::OR32rr:
333   case X86::OR32ri:
334   case X86::OR32ri8:
335   case X86::OR64rr:
336   case X86::OR64ri8:
337   case X86::OR64ri32:
338   case X86::SBB8rr:
339   case X86::SBB8ri:
340   case X86::SBB16rr:
341   case X86::SBB16ri:
342   case X86::SBB16ri8:
343   case X86::SBB32rr:
344   case X86::SBB32ri:
345   case X86::SBB32ri8:
346   case X86::SBB64rr:
347   case X86::SBB64ri8:
348   case X86::SBB64ri32:
349   case X86::SUB8rr:
350   case X86::SUB8ri:
351   case X86::SUB16rr:
352   case X86::SUB16ri:
353   case X86::SUB16ri8:
354   case X86::SUB32rr:
355   case X86::SUB32ri:
356   case X86::SUB32ri8:
357   case X86::SUB64rr:
358   case X86::SUB64ri8:
359   case X86::SUB64ri32:
360   case X86::XOR8rr:
361   case X86::XOR8ri:
362   case X86::XOR16rr:
363   case X86::XOR16ri:
364   case X86::XOR16ri8:
365   case X86::XOR32rr:
366   case X86::XOR32ri:
367   case X86::XOR32ri8:
368   case X86::XOR64rr:
369   case X86::XOR64ri8:
370   case X86::XOR64ri32:
371   // Arithmetic with just 32-bit and 64-bit variants and no immediates.
372   case X86::ADCX32rr:
373   case X86::ADCX64rr:
374   case X86::ADOX32rr:
375   case X86::ADOX64rr:
376   case X86::ANDN32rr:
377   case X86::ANDN64rr:
378   // Unary arithmetic operations.
379   case X86::DEC8r:
380   case X86::DEC16r:
381   case X86::DEC32r:
382   case X86::DEC64r:
383   case X86::INC8r:
384   case X86::INC16r:
385   case X86::INC32r:
386   case X86::INC64r:
387   case X86::NEG8r:
388   case X86::NEG16r:
389   case X86::NEG32r:
390   case X86::NEG64r:
391 
392   // Unlike other arithmetic, NOT doesn't set EFLAGS.
393   case X86::NOT8r:
394   case X86::NOT16r:
395   case X86::NOT32r:
396   case X86::NOT64r:
397 
398   // Various move instructions used to zero or sign extend things. Note that we
399   // intentionally don't support the _NOREX variants as we can't handle that
400   // register constraint anyways.
401   case X86::MOVSX16rr8:
402   case X86::MOVSX32rr8:
403   case X86::MOVSX32rr16:
404   case X86::MOVSX64rr8:
405   case X86::MOVSX64rr16:
406   case X86::MOVSX64rr32:
407   case X86::MOVZX16rr8:
408   case X86::MOVZX32rr8:
409   case X86::MOVZX32rr16:
410   case X86::MOVZX64rr8:
411   case X86::MOVZX64rr16:
412   case X86::MOV32rr:
413 
414   // Arithmetic instructions that are both constant time and don't set flags.
415   case X86::RORX32ri:
416   case X86::RORX64ri:
417   case X86::SARX32rr:
418   case X86::SARX64rr:
419   case X86::SHLX32rr:
420   case X86::SHLX64rr:
421   case X86::SHRX32rr:
422   case X86::SHRX64rr:
423 
424   // LEA doesn't actually access memory, and its arithmetic is constant time.
425   case X86::LEA16r:
426   case X86::LEA32r:
427   case X86::LEA64_32r:
428   case X86::LEA64r:
429     return true;
430   }
431 }
432 
433 bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
434   switch (MI.getOpcode()) {
435   default:
436     // By default, assume that the load will immediately leak.
437     return false;
438 
439   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
440   // However, they set flags and are perhaps the most surprisingly constant
441   // time operations so we call them out here separately.
442   case X86::IMUL16rm:
443   case X86::IMUL16rmi8:
444   case X86::IMUL16rmi:
445   case X86::IMUL32rm:
446   case X86::IMUL32rmi8:
447   case X86::IMUL32rmi:
448   case X86::IMUL64rm:
449   case X86::IMUL64rmi32:
450   case X86::IMUL64rmi8:
451 
452   // Bit scanning and counting instructions that are somewhat surprisingly
453   // constant time as they scan across bits and do other fairly complex
454   // operations like popcnt, but are believed to be constant time on x86.
455   // However, these set flags.
456   case X86::BSF16rm:
457   case X86::BSF32rm:
458   case X86::BSF64rm:
459   case X86::BSR16rm:
460   case X86::BSR32rm:
461   case X86::BSR64rm:
462   case X86::LZCNT16rm:
463   case X86::LZCNT32rm:
464   case X86::LZCNT64rm:
465   case X86::POPCNT16rm:
466   case X86::POPCNT32rm:
467   case X86::POPCNT64rm:
468   case X86::TZCNT16rm:
469   case X86::TZCNT32rm:
470   case X86::TZCNT64rm:
471 
472   // Bit manipulation instructions are effectively combinations of basic
473   // arithmetic ops, and should still execute in constant time. These also
474   // set flags.
475   case X86::BLCFILL32rm:
476   case X86::BLCFILL64rm:
477   case X86::BLCI32rm:
478   case X86::BLCI64rm:
479   case X86::BLCIC32rm:
480   case X86::BLCIC64rm:
481   case X86::BLCMSK32rm:
482   case X86::BLCMSK64rm:
483   case X86::BLCS32rm:
484   case X86::BLCS64rm:
485   case X86::BLSFILL32rm:
486   case X86::BLSFILL64rm:
487   case X86::BLSI32rm:
488   case X86::BLSI64rm:
489   case X86::BLSIC32rm:
490   case X86::BLSIC64rm:
491   case X86::BLSMSK32rm:
492   case X86::BLSMSK64rm:
493   case X86::BLSR32rm:
494   case X86::BLSR64rm:
495   case X86::TZMSK32rm:
496   case X86::TZMSK64rm:
497 
498   // Bit extracting and clearing instructions should execute in constant time,
499   // and set flags.
500   case X86::BEXTR32rm:
501   case X86::BEXTR64rm:
502   case X86::BEXTRI32mi:
503   case X86::BEXTRI64mi:
504   case X86::BZHI32rm:
505   case X86::BZHI64rm:
506 
507   // Basic arithmetic is constant time on the input but does set flags.
508   case X86::ADC8rm:
509   case X86::ADC16rm:
510   case X86::ADC32rm:
511   case X86::ADC64rm:
512   case X86::ADCX32rm:
513   case X86::ADCX64rm:
514   case X86::ADD8rm:
515   case X86::ADD16rm:
516   case X86::ADD32rm:
517   case X86::ADD64rm:
518   case X86::ADOX32rm:
519   case X86::ADOX64rm:
520   case X86::AND8rm:
521   case X86::AND16rm:
522   case X86::AND32rm:
523   case X86::AND64rm:
524   case X86::ANDN32rm:
525   case X86::ANDN64rm:
526   case X86::OR8rm:
527   case X86::OR16rm:
528   case X86::OR32rm:
529   case X86::OR64rm:
530   case X86::SBB8rm:
531   case X86::SBB16rm:
532   case X86::SBB32rm:
533   case X86::SBB64rm:
534   case X86::SUB8rm:
535   case X86::SUB16rm:
536   case X86::SUB32rm:
537   case X86::SUB64rm:
538   case X86::XOR8rm:
539   case X86::XOR16rm:
540   case X86::XOR32rm:
541   case X86::XOR64rm:
542 
543   // Integer multiply w/o affecting flags is still believed to be constant
544   // time on x86. Called out separately as this is among the most surprising
545   // instructions to exhibit that behavior.
546   case X86::MULX32rm:
547   case X86::MULX64rm:
548 
549   // Arithmetic instructions that are both constant time and don't set flags.
550   case X86::RORX32mi:
551   case X86::RORX64mi:
552   case X86::SARX32rm:
553   case X86::SARX64rm:
554   case X86::SHLX32rm:
555   case X86::SHLX64rm:
556   case X86::SHRX32rm:
557   case X86::SHRX64rm:
558 
559   // Conversions are believed to be constant time and don't set flags.
560   case X86::CVTTSD2SI64rm:
561   case X86::VCVTTSD2SI64rm:
562   case X86::VCVTTSD2SI64Zrm:
563   case X86::CVTTSD2SIrm:
564   case X86::VCVTTSD2SIrm:
565   case X86::VCVTTSD2SIZrm:
566   case X86::CVTTSS2SI64rm:
567   case X86::VCVTTSS2SI64rm:
568   case X86::VCVTTSS2SI64Zrm:
569   case X86::CVTTSS2SIrm:
570   case X86::VCVTTSS2SIrm:
571   case X86::VCVTTSS2SIZrm:
572   case X86::CVTSI2SDrm:
573   case X86::VCVTSI2SDrm:
574   case X86::VCVTSI2SDZrm:
575   case X86::CVTSI2SSrm:
576   case X86::VCVTSI2SSrm:
577   case X86::VCVTSI2SSZrm:
578   case X86::CVTSI642SDrm:
579   case X86::VCVTSI642SDrm:
580   case X86::VCVTSI642SDZrm:
581   case X86::CVTSI642SSrm:
582   case X86::VCVTSI642SSrm:
583   case X86::VCVTSI642SSZrm:
584   case X86::CVTSS2SDrm:
585   case X86::VCVTSS2SDrm:
586   case X86::VCVTSS2SDZrm:
587   case X86::CVTSD2SSrm:
588   case X86::VCVTSD2SSrm:
589   case X86::VCVTSD2SSZrm:
590   // AVX512 added unsigned integer conversions.
591   case X86::VCVTTSD2USI64Zrm:
592   case X86::VCVTTSD2USIZrm:
593   case X86::VCVTTSS2USI64Zrm:
594   case X86::VCVTTSS2USIZrm:
595   case X86::VCVTUSI2SDZrm:
596   case X86::VCVTUSI642SDZrm:
597   case X86::VCVTUSI2SSZrm:
598   case X86::VCVTUSI642SSZrm:
599 
600   // Loads to register don't set flags.
601   case X86::MOV8rm:
602   case X86::MOV8rm_NOREX:
603   case X86::MOV16rm:
604   case X86::MOV32rm:
605   case X86::MOV64rm:
606   case X86::MOVSX16rm8:
607   case X86::MOVSX32rm16:
608   case X86::MOVSX32rm8:
609   case X86::MOVSX32rm8_NOREX:
610   case X86::MOVSX64rm16:
611   case X86::MOVSX64rm32:
612   case X86::MOVSX64rm8:
613   case X86::MOVZX16rm8:
614   case X86::MOVZX32rm16:
615   case X86::MOVZX32rm8:
616   case X86::MOVZX32rm8_NOREX:
617   case X86::MOVZX64rm16:
618   case X86::MOVZX64rm8:
619     return true;
620   }
621 }
622 
623 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
624   const MachineFunction *MF = MI.getParent()->getParent();
625   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
626 
627   if (isFrameInstr(MI)) {
628     int SPAdj = alignTo(getFrameSize(MI), TFI->getStackAlign());
629     SPAdj -= getFrameAdjustment(MI);
630     if (!isFrameSetup(MI))
631       SPAdj = -SPAdj;
632     return SPAdj;
633   }
634 
635   // To know whether a call adjusts the stack, we need information
636   // that is bound to the following ADJCALLSTACKUP pseudo.
637   // Look for the next ADJCALLSTACKUP that follows the call.
638   if (MI.isCall()) {
639     const MachineBasicBlock *MBB = MI.getParent();
640     auto I = ++MachineBasicBlock::const_iterator(MI);
641     for (auto E = MBB->end(); I != E; ++I) {
642       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
643           I->isCall())
644         break;
645     }
646 
647     // If we could not find a frame destroy opcode, then it has already
648     // been simplified, so we don't care.
649     if (I->getOpcode() != getCallFrameDestroyOpcode())
650       return 0;
651 
652     return -(I->getOperand(1).getImm());
653   }
654 
655   // Currently handle only PUSHes we can reasonably expect to see
656   // in call sequences
657   switch (MI.getOpcode()) {
658   default:
659     return 0;
660   case X86::PUSH32i8:
661   case X86::PUSH32r:
662   case X86::PUSH32rmm:
663   case X86::PUSH32rmr:
664   case X86::PUSHi32:
665     return 4;
666   case X86::PUSH64i8:
667   case X86::PUSH64r:
668   case X86::PUSH64rmm:
669   case X86::PUSH64rmr:
670   case X86::PUSH64i32:
671     return 8;
672   }
673 }
674 
675 /// Return true and the FrameIndex if the specified
676 /// operand and follow operands form a reference to the stack frame.
677 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
678                                   int &FrameIndex) const {
679   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
680       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
681       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
682       MI.getOperand(Op + X86::AddrDisp).isImm() &&
683       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
684       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
685       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
686     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
687     return true;
688   }
689   return false;
690 }
691 
692 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
693   switch (Opcode) {
694   default:
695     return false;
696   case X86::MOV8rm:
697   case X86::KMOVBkm:
698     MemBytes = 1;
699     return true;
700   case X86::MOV16rm:
701   case X86::KMOVWkm:
702     MemBytes = 2;
703     return true;
704   case X86::MOV32rm:
705   case X86::MOVSSrm:
706   case X86::MOVSSrm_alt:
707   case X86::VMOVSSrm:
708   case X86::VMOVSSrm_alt:
709   case X86::VMOVSSZrm:
710   case X86::VMOVSSZrm_alt:
711   case X86::KMOVDkm:
712     MemBytes = 4;
713     return true;
714   case X86::MOV64rm:
715   case X86::LD_Fp64m:
716   case X86::MOVSDrm:
717   case X86::MOVSDrm_alt:
718   case X86::VMOVSDrm:
719   case X86::VMOVSDrm_alt:
720   case X86::VMOVSDZrm:
721   case X86::VMOVSDZrm_alt:
722   case X86::MMX_MOVD64rm:
723   case X86::MMX_MOVQ64rm:
724   case X86::KMOVQkm:
725     MemBytes = 8;
726     return true;
727   case X86::MOVAPSrm:
728   case X86::MOVUPSrm:
729   case X86::MOVAPDrm:
730   case X86::MOVUPDrm:
731   case X86::MOVDQArm:
732   case X86::MOVDQUrm:
733   case X86::VMOVAPSrm:
734   case X86::VMOVUPSrm:
735   case X86::VMOVAPDrm:
736   case X86::VMOVUPDrm:
737   case X86::VMOVDQArm:
738   case X86::VMOVDQUrm:
739   case X86::VMOVAPSZ128rm:
740   case X86::VMOVUPSZ128rm:
741   case X86::VMOVAPSZ128rm_NOVLX:
742   case X86::VMOVUPSZ128rm_NOVLX:
743   case X86::VMOVAPDZ128rm:
744   case X86::VMOVUPDZ128rm:
745   case X86::VMOVDQU8Z128rm:
746   case X86::VMOVDQU16Z128rm:
747   case X86::VMOVDQA32Z128rm:
748   case X86::VMOVDQU32Z128rm:
749   case X86::VMOVDQA64Z128rm:
750   case X86::VMOVDQU64Z128rm:
751     MemBytes = 16;
752     return true;
753   case X86::VMOVAPSYrm:
754   case X86::VMOVUPSYrm:
755   case X86::VMOVAPDYrm:
756   case X86::VMOVUPDYrm:
757   case X86::VMOVDQAYrm:
758   case X86::VMOVDQUYrm:
759   case X86::VMOVAPSZ256rm:
760   case X86::VMOVUPSZ256rm:
761   case X86::VMOVAPSZ256rm_NOVLX:
762   case X86::VMOVUPSZ256rm_NOVLX:
763   case X86::VMOVAPDZ256rm:
764   case X86::VMOVUPDZ256rm:
765   case X86::VMOVDQU8Z256rm:
766   case X86::VMOVDQU16Z256rm:
767   case X86::VMOVDQA32Z256rm:
768   case X86::VMOVDQU32Z256rm:
769   case X86::VMOVDQA64Z256rm:
770   case X86::VMOVDQU64Z256rm:
771     MemBytes = 32;
772     return true;
773   case X86::VMOVAPSZrm:
774   case X86::VMOVUPSZrm:
775   case X86::VMOVAPDZrm:
776   case X86::VMOVUPDZrm:
777   case X86::VMOVDQU8Zrm:
778   case X86::VMOVDQU16Zrm:
779   case X86::VMOVDQA32Zrm:
780   case X86::VMOVDQU32Zrm:
781   case X86::VMOVDQA64Zrm:
782   case X86::VMOVDQU64Zrm:
783     MemBytes = 64;
784     return true;
785   }
786 }
787 
788 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
789   switch (Opcode) {
790   default:
791     return false;
792   case X86::MOV8mr:
793   case X86::KMOVBmk:
794     MemBytes = 1;
795     return true;
796   case X86::MOV16mr:
797   case X86::KMOVWmk:
798     MemBytes = 2;
799     return true;
800   case X86::MOV32mr:
801   case X86::MOVSSmr:
802   case X86::VMOVSSmr:
803   case X86::VMOVSSZmr:
804   case X86::KMOVDmk:
805     MemBytes = 4;
806     return true;
807   case X86::MOV64mr:
808   case X86::ST_FpP64m:
809   case X86::MOVSDmr:
810   case X86::VMOVSDmr:
811   case X86::VMOVSDZmr:
812   case X86::MMX_MOVD64mr:
813   case X86::MMX_MOVQ64mr:
814   case X86::MMX_MOVNTQmr:
815   case X86::KMOVQmk:
816     MemBytes = 8;
817     return true;
818   case X86::MOVAPSmr:
819   case X86::MOVUPSmr:
820   case X86::MOVAPDmr:
821   case X86::MOVUPDmr:
822   case X86::MOVDQAmr:
823   case X86::MOVDQUmr:
824   case X86::VMOVAPSmr:
825   case X86::VMOVUPSmr:
826   case X86::VMOVAPDmr:
827   case X86::VMOVUPDmr:
828   case X86::VMOVDQAmr:
829   case X86::VMOVDQUmr:
830   case X86::VMOVUPSZ128mr:
831   case X86::VMOVAPSZ128mr:
832   case X86::VMOVUPSZ128mr_NOVLX:
833   case X86::VMOVAPSZ128mr_NOVLX:
834   case X86::VMOVUPDZ128mr:
835   case X86::VMOVAPDZ128mr:
836   case X86::VMOVDQA32Z128mr:
837   case X86::VMOVDQU32Z128mr:
838   case X86::VMOVDQA64Z128mr:
839   case X86::VMOVDQU64Z128mr:
840   case X86::VMOVDQU8Z128mr:
841   case X86::VMOVDQU16Z128mr:
842     MemBytes = 16;
843     return true;
844   case X86::VMOVUPSYmr:
845   case X86::VMOVAPSYmr:
846   case X86::VMOVUPDYmr:
847   case X86::VMOVAPDYmr:
848   case X86::VMOVDQUYmr:
849   case X86::VMOVDQAYmr:
850   case X86::VMOVUPSZ256mr:
851   case X86::VMOVAPSZ256mr:
852   case X86::VMOVUPSZ256mr_NOVLX:
853   case X86::VMOVAPSZ256mr_NOVLX:
854   case X86::VMOVUPDZ256mr:
855   case X86::VMOVAPDZ256mr:
856   case X86::VMOVDQU8Z256mr:
857   case X86::VMOVDQU16Z256mr:
858   case X86::VMOVDQA32Z256mr:
859   case X86::VMOVDQU32Z256mr:
860   case X86::VMOVDQA64Z256mr:
861   case X86::VMOVDQU64Z256mr:
862     MemBytes = 32;
863     return true;
864   case X86::VMOVUPSZmr:
865   case X86::VMOVAPSZmr:
866   case X86::VMOVUPDZmr:
867   case X86::VMOVAPDZmr:
868   case X86::VMOVDQU8Zmr:
869   case X86::VMOVDQU16Zmr:
870   case X86::VMOVDQA32Zmr:
871   case X86::VMOVDQU32Zmr:
872   case X86::VMOVDQA64Zmr:
873   case X86::VMOVDQU64Zmr:
874     MemBytes = 64;
875     return true;
876   }
877   return false;
878 }
879 
880 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
881                                            int &FrameIndex) const {
882   unsigned Dummy;
883   return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
884 }
885 
886 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
887                                            int &FrameIndex,
888                                            unsigned &MemBytes) const {
889   if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
890     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
891       return MI.getOperand(0).getReg();
892   return 0;
893 }
894 
895 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
896                                                  int &FrameIndex) const {
897   unsigned Dummy;
898   if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
899     unsigned Reg;
900     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
901       return Reg;
902     // Check for post-frame index elimination operations
903     SmallVector<const MachineMemOperand *, 1> Accesses;
904     if (hasLoadFromStackSlot(MI, Accesses)) {
905       FrameIndex =
906           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
907               ->getFrameIndex();
908       return 1;
909     }
910   }
911   return 0;
912 }
913 
914 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
915                                           int &FrameIndex) const {
916   unsigned Dummy;
917   return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
918 }
919 
920 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
921                                           int &FrameIndex,
922                                           unsigned &MemBytes) const {
923   if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
924     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
925         isFrameOperand(MI, 0, FrameIndex))
926       return MI.getOperand(X86::AddrNumOperands).getReg();
927   return 0;
928 }
929 
930 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
931                                                 int &FrameIndex) const {
932   unsigned Dummy;
933   if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
934     unsigned Reg;
935     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
936       return Reg;
937     // Check for post-frame index elimination operations
938     SmallVector<const MachineMemOperand *, 1> Accesses;
939     if (hasStoreToStackSlot(MI, Accesses)) {
940       FrameIndex =
941           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
942               ->getFrameIndex();
943       return 1;
944     }
945   }
946   return 0;
947 }
948 
949 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
950 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
951   // Don't waste compile time scanning use-def chains of physregs.
952   if (!Register::isVirtualRegister(BaseReg))
953     return false;
954   bool isPICBase = false;
955   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
956          E = MRI.def_instr_end(); I != E; ++I) {
957     MachineInstr *DefMI = &*I;
958     if (DefMI->getOpcode() != X86::MOVPC32r)
959       return false;
960     assert(!isPICBase && "More than one PIC base?");
961     isPICBase = true;
962   }
963   return isPICBase;
964 }
965 
966 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
967                                                      AAResults *AA) const {
968   switch (MI.getOpcode()) {
969   default:
970     // This function should only be called for opcodes with the ReMaterializable
971     // flag set.
972     llvm_unreachable("Unknown rematerializable operation!");
973     break;
974 
975   case X86::LOAD_STACK_GUARD:
976   case X86::AVX1_SETALLONES:
977   case X86::AVX2_SETALLONES:
978   case X86::AVX512_128_SET0:
979   case X86::AVX512_256_SET0:
980   case X86::AVX512_512_SET0:
981   case X86::AVX512_512_SETALLONES:
982   case X86::AVX512_FsFLD0SD:
983   case X86::AVX512_FsFLD0SS:
984   case X86::AVX512_FsFLD0F128:
985   case X86::AVX_SET0:
986   case X86::FsFLD0SD:
987   case X86::FsFLD0SS:
988   case X86::FsFLD0F128:
989   case X86::KSET0D:
990   case X86::KSET0Q:
991   case X86::KSET0W:
992   case X86::KSET1D:
993   case X86::KSET1Q:
994   case X86::KSET1W:
995   case X86::MMX_SET0:
996   case X86::MOV32ImmSExti8:
997   case X86::MOV32r0:
998   case X86::MOV32r1:
999   case X86::MOV32r_1:
1000   case X86::MOV32ri64:
1001   case X86::MOV64ImmSExti8:
1002   case X86::V_SET0:
1003   case X86::V_SETALLONES:
1004   case X86::MOV16ri:
1005   case X86::MOV32ri:
1006   case X86::MOV64ri:
1007   case X86::MOV64ri32:
1008   case X86::MOV8ri:
1009     return true;
1010 
1011   case X86::MOV8rm:
1012   case X86::MOV8rm_NOREX:
1013   case X86::MOV16rm:
1014   case X86::MOV32rm:
1015   case X86::MOV64rm:
1016   case X86::MOVSSrm:
1017   case X86::MOVSSrm_alt:
1018   case X86::MOVSDrm:
1019   case X86::MOVSDrm_alt:
1020   case X86::MOVAPSrm:
1021   case X86::MOVUPSrm:
1022   case X86::MOVAPDrm:
1023   case X86::MOVUPDrm:
1024   case X86::MOVDQArm:
1025   case X86::MOVDQUrm:
1026   case X86::VMOVSSrm:
1027   case X86::VMOVSSrm_alt:
1028   case X86::VMOVSDrm:
1029   case X86::VMOVSDrm_alt:
1030   case X86::VMOVAPSrm:
1031   case X86::VMOVUPSrm:
1032   case X86::VMOVAPDrm:
1033   case X86::VMOVUPDrm:
1034   case X86::VMOVDQArm:
1035   case X86::VMOVDQUrm:
1036   case X86::VMOVAPSYrm:
1037   case X86::VMOVUPSYrm:
1038   case X86::VMOVAPDYrm:
1039   case X86::VMOVUPDYrm:
1040   case X86::VMOVDQAYrm:
1041   case X86::VMOVDQUYrm:
1042   case X86::MMX_MOVD64rm:
1043   case X86::MMX_MOVQ64rm:
1044   // AVX-512
1045   case X86::VMOVSSZrm:
1046   case X86::VMOVSSZrm_alt:
1047   case X86::VMOVSDZrm:
1048   case X86::VMOVSDZrm_alt:
1049   case X86::VMOVAPDZ128rm:
1050   case X86::VMOVAPDZ256rm:
1051   case X86::VMOVAPDZrm:
1052   case X86::VMOVAPSZ128rm:
1053   case X86::VMOVAPSZ256rm:
1054   case X86::VMOVAPSZ128rm_NOVLX:
1055   case X86::VMOVAPSZ256rm_NOVLX:
1056   case X86::VMOVAPSZrm:
1057   case X86::VMOVDQA32Z128rm:
1058   case X86::VMOVDQA32Z256rm:
1059   case X86::VMOVDQA32Zrm:
1060   case X86::VMOVDQA64Z128rm:
1061   case X86::VMOVDQA64Z256rm:
1062   case X86::VMOVDQA64Zrm:
1063   case X86::VMOVDQU16Z128rm:
1064   case X86::VMOVDQU16Z256rm:
1065   case X86::VMOVDQU16Zrm:
1066   case X86::VMOVDQU32Z128rm:
1067   case X86::VMOVDQU32Z256rm:
1068   case X86::VMOVDQU32Zrm:
1069   case X86::VMOVDQU64Z128rm:
1070   case X86::VMOVDQU64Z256rm:
1071   case X86::VMOVDQU64Zrm:
1072   case X86::VMOVDQU8Z128rm:
1073   case X86::VMOVDQU8Z256rm:
1074   case X86::VMOVDQU8Zrm:
1075   case X86::VMOVUPDZ128rm:
1076   case X86::VMOVUPDZ256rm:
1077   case X86::VMOVUPDZrm:
1078   case X86::VMOVUPSZ128rm:
1079   case X86::VMOVUPSZ256rm:
1080   case X86::VMOVUPSZ128rm_NOVLX:
1081   case X86::VMOVUPSZ256rm_NOVLX:
1082   case X86::VMOVUPSZrm: {
1083     // Loads from constant pools are trivially rematerializable.
1084     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
1085         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1086         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1087         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1088         MI.isDereferenceableInvariantLoad(AA)) {
1089       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1090       if (BaseReg == 0 || BaseReg == X86::RIP)
1091         return true;
1092       // Allow re-materialization of PIC load.
1093       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
1094         return false;
1095       const MachineFunction &MF = *MI.getParent()->getParent();
1096       const MachineRegisterInfo &MRI = MF.getRegInfo();
1097       return regIsPICBase(BaseReg, MRI);
1098     }
1099     return false;
1100   }
1101 
1102   case X86::LEA32r:
1103   case X86::LEA64r: {
1104     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1105         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1106         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1107         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
1108       // lea fi#, lea GV, etc. are all rematerializable.
1109       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
1110         return true;
1111       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1112       if (BaseReg == 0)
1113         return true;
1114       // Allow re-materialization of lea PICBase + x.
1115       const MachineFunction &MF = *MI.getParent()->getParent();
1116       const MachineRegisterInfo &MRI = MF.getRegInfo();
1117       return regIsPICBase(BaseReg, MRI);
1118     }
1119     return false;
1120   }
1121   }
1122 }
1123 
1124 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1125                                  MachineBasicBlock::iterator I,
1126                                  Register DestReg, unsigned SubIdx,
1127                                  const MachineInstr &Orig,
1128                                  const TargetRegisterInfo &TRI) const {
1129   bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
1130   if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
1131                             MachineBasicBlock::LQR_Dead) {
1132     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
1133     // effects.
1134     int Value;
1135     switch (Orig.getOpcode()) {
1136     case X86::MOV32r0:  Value = 0; break;
1137     case X86::MOV32r1:  Value = 1; break;
1138     case X86::MOV32r_1: Value = -1; break;
1139     default:
1140       llvm_unreachable("Unexpected instruction!");
1141     }
1142 
1143     const DebugLoc &DL = Orig.getDebugLoc();
1144     BuildMI(MBB, I, DL, get(X86::MOV32ri))
1145         .add(Orig.getOperand(0))
1146         .addImm(Value);
1147   } else {
1148     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1149     MBB.insert(I, MI);
1150   }
1151 
1152   MachineInstr &NewMI = *std::prev(I);
1153   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1154 }
1155 
1156 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
1157 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
1158   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1159     MachineOperand &MO = MI.getOperand(i);
1160     if (MO.isReg() && MO.isDef() &&
1161         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1162       return true;
1163     }
1164   }
1165   return false;
1166 }
1167 
1168 /// Check whether the shift count for a machine operand is non-zero.
1169 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
1170                                               unsigned ShiftAmtOperandIdx) {
1171   // The shift count is six bits with the REX.W prefix and five bits without.
1172   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1173   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
1174   return Imm & ShiftCountMask;
1175 }
1176 
1177 /// Check whether the given shift count is appropriate
1178 /// can be represented by a LEA instruction.
1179 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1180   // Left shift instructions can be transformed into load-effective-address
1181   // instructions if we can encode them appropriately.
1182   // A LEA instruction utilizes a SIB byte to encode its scale factor.
1183   // The SIB.scale field is two bits wide which means that we can encode any
1184   // shift amount less than 4.
1185   return ShAmt < 4 && ShAmt > 0;
1186 }
1187 
1188 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
1189                                   unsigned Opc, bool AllowSP, Register &NewSrc,
1190                                   bool &isKill, MachineOperand &ImplicitOp,
1191                                   LiveVariables *LV) const {
1192   MachineFunction &MF = *MI.getParent()->getParent();
1193   const TargetRegisterClass *RC;
1194   if (AllowSP) {
1195     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1196   } else {
1197     RC = Opc != X86::LEA32r ?
1198       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1199   }
1200   Register SrcReg = Src.getReg();
1201 
1202   // For both LEA64 and LEA32 the register already has essentially the right
1203   // type (32-bit or 64-bit) we may just need to forbid SP.
1204   if (Opc != X86::LEA64_32r) {
1205     NewSrc = SrcReg;
1206     isKill = Src.isKill();
1207     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1208 
1209     if (Register::isVirtualRegister(NewSrc) &&
1210         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1211       return false;
1212 
1213     return true;
1214   }
1215 
1216   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1217   // another we need to add 64-bit registers to the final MI.
1218   if (Register::isPhysicalRegister(SrcReg)) {
1219     ImplicitOp = Src;
1220     ImplicitOp.setImplicit();
1221 
1222     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
1223     isKill = Src.isKill();
1224     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1225   } else {
1226     // Virtual register of the wrong class, we have to create a temporary 64-bit
1227     // vreg to feed into the LEA.
1228     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1229     MachineInstr *Copy =
1230         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1231             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1232             .add(Src);
1233 
1234     // Which is obviously going to be dead after we're done with it.
1235     isKill = true;
1236 
1237     if (LV)
1238       LV->replaceKillInstruction(SrcReg, MI, *Copy);
1239   }
1240 
1241   // We've set all the parameters without issue.
1242   return true;
1243 }
1244 
1245 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
1246     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
1247     LiveVariables *LV, bool Is8BitOp) const {
1248   // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1249   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1250   assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1251               *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1252          "Unexpected type for LEA transform");
1253 
1254   // TODO: For a 32-bit target, we need to adjust the LEA variables with
1255   // something like this:
1256   //   Opcode = X86::LEA32r;
1257   //   InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1258   //   OutRegLEA =
1259   //       Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1260   //                : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1261   if (!Subtarget.is64Bit())
1262     return nullptr;
1263 
1264   unsigned Opcode = X86::LEA64_32r;
1265   Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1266   Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1267 
1268   // Build and insert into an implicit UNDEF value. This is OK because
1269   // we will be shifting and then extracting the lower 8/16-bits.
1270   // This has the potential to cause partial register stall. e.g.
1271   //   movw    (%rbp,%rcx,2), %dx
1272   //   leal    -65(%rdx), %esi
1273   // But testing has shown this *does* help performance in 64-bit mode (at
1274   // least on modern x86 machines).
1275   MachineBasicBlock::iterator MBBI = MI.getIterator();
1276   Register Dest = MI.getOperand(0).getReg();
1277   Register Src = MI.getOperand(1).getReg();
1278   bool IsDead = MI.getOperand(0).isDead();
1279   bool IsKill = MI.getOperand(1).isKill();
1280   unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1281   assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
1282   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
1283   MachineInstr *InsMI =
1284       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1285           .addReg(InRegLEA, RegState::Define, SubReg)
1286           .addReg(Src, getKillRegState(IsKill));
1287 
1288   MachineInstrBuilder MIB =
1289       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
1290   switch (MIOpc) {
1291   default: llvm_unreachable("Unreachable!");
1292   case X86::SHL8ri:
1293   case X86::SHL16ri: {
1294     unsigned ShAmt = MI.getOperand(2).getImm();
1295     MIB.addReg(0).addImm(1ULL << ShAmt)
1296        .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
1297     break;
1298   }
1299   case X86::INC8r:
1300   case X86::INC16r:
1301     addRegOffset(MIB, InRegLEA, true, 1);
1302     break;
1303   case X86::DEC8r:
1304   case X86::DEC16r:
1305     addRegOffset(MIB, InRegLEA, true, -1);
1306     break;
1307   case X86::ADD8ri:
1308   case X86::ADD8ri_DB:
1309   case X86::ADD16ri:
1310   case X86::ADD16ri8:
1311   case X86::ADD16ri_DB:
1312   case X86::ADD16ri8_DB:
1313     addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1314     break;
1315   case X86::ADD8rr:
1316   case X86::ADD8rr_DB:
1317   case X86::ADD16rr:
1318   case X86::ADD16rr_DB: {
1319     Register Src2 = MI.getOperand(2).getReg();
1320     bool IsKill2 = MI.getOperand(2).isKill();
1321     assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
1322     unsigned InRegLEA2 = 0;
1323     MachineInstr *InsMI2 = nullptr;
1324     if (Src == Src2) {
1325       // ADD8rr/ADD16rr killed %reg1028, %reg1028
1326       // just a single insert_subreg.
1327       addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1328     } else {
1329       if (Subtarget.is64Bit())
1330         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1331       else
1332         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1333       // Build and insert into an implicit UNDEF value. This is OK because
1334       // we will be shifting and then extracting the lower 8/16-bits.
1335       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
1336       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1337                    .addReg(InRegLEA2, RegState::Define, SubReg)
1338                    .addReg(Src2, getKillRegState(IsKill2));
1339       addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1340     }
1341     if (LV && IsKill2 && InsMI2)
1342       LV->replaceKillInstruction(Src2, MI, *InsMI2);
1343     break;
1344   }
1345   }
1346 
1347   MachineInstr *NewMI = MIB;
1348   MachineInstr *ExtMI =
1349       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1350           .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
1351           .addReg(OutRegLEA, RegState::Kill, SubReg);
1352 
1353   if (LV) {
1354     // Update live variables.
1355     LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1356     LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
1357     if (IsKill)
1358       LV->replaceKillInstruction(Src, MI, *InsMI);
1359     if (IsDead)
1360       LV->replaceKillInstruction(Dest, MI, *ExtMI);
1361   }
1362 
1363   return ExtMI;
1364 }
1365 
1366 /// This method must be implemented by targets that
1367 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1368 /// may be able to convert a two-address instruction into a true
1369 /// three-address instruction on demand.  This allows the X86 target (for
1370 /// example) to convert ADD and SHL instructions into LEA instructions if they
1371 /// would require register copies due to two-addressness.
1372 ///
1373 /// This method returns a null pointer if the transformation cannot be
1374 /// performed, otherwise it returns the new instruction.
1375 ///
1376 MachineInstr *
1377 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1378                                     MachineInstr &MI, LiveVariables *LV) const {
1379   // The following opcodes also sets the condition code register(s). Only
1380   // convert them to equivalent lea if the condition code register def's
1381   // are dead!
1382   if (hasLiveCondCodeDef(MI))
1383     return nullptr;
1384 
1385   MachineFunction &MF = *MI.getParent()->getParent();
1386   // All instructions input are two-addr instructions.  Get the known operands.
1387   const MachineOperand &Dest = MI.getOperand(0);
1388   const MachineOperand &Src = MI.getOperand(1);
1389 
1390   // Ideally, operations with undef should be folded before we get here, but we
1391   // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1392   // Without this, we have to forward undef state to new register operands to
1393   // avoid machine verifier errors.
1394   if (Src.isUndef())
1395     return nullptr;
1396   if (MI.getNumOperands() > 2)
1397     if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
1398       return nullptr;
1399 
1400   MachineInstr *NewMI = nullptr;
1401   bool Is64Bit = Subtarget.is64Bit();
1402 
1403   bool Is8BitOp = false;
1404   unsigned MIOpc = MI.getOpcode();
1405   switch (MIOpc) {
1406   default: llvm_unreachable("Unreachable!");
1407   case X86::SHL64ri: {
1408     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1409     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1410     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1411 
1412     // LEA can't handle RSP.
1413     if (Register::isVirtualRegister(Src.getReg()) &&
1414         !MF.getRegInfo().constrainRegClass(Src.getReg(),
1415                                            &X86::GR64_NOSPRegClass))
1416       return nullptr;
1417 
1418     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1419                 .add(Dest)
1420                 .addReg(0)
1421                 .addImm(1ULL << ShAmt)
1422                 .add(Src)
1423                 .addImm(0)
1424                 .addReg(0);
1425     break;
1426   }
1427   case X86::SHL32ri: {
1428     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1429     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1430     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1431 
1432     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1433 
1434     // LEA can't handle ESP.
1435     bool isKill;
1436     Register SrcReg;
1437     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1438     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
1439                         SrcReg, isKill, ImplicitOp, LV))
1440       return nullptr;
1441 
1442     MachineInstrBuilder MIB =
1443         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1444             .add(Dest)
1445             .addReg(0)
1446             .addImm(1ULL << ShAmt)
1447             .addReg(SrcReg, getKillRegState(isKill))
1448             .addImm(0)
1449             .addReg(0);
1450     if (ImplicitOp.getReg() != 0)
1451       MIB.add(ImplicitOp);
1452     NewMI = MIB;
1453 
1454     break;
1455   }
1456   case X86::SHL8ri:
1457     Is8BitOp = true;
1458     LLVM_FALLTHROUGH;
1459   case X86::SHL16ri: {
1460     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1461     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1462     if (!isTruncatedShiftCountForLEA(ShAmt))
1463       return nullptr;
1464     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1465   }
1466   case X86::INC64r:
1467   case X86::INC32r: {
1468     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1469     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1470         (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1471     bool isKill;
1472     Register SrcReg;
1473     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1474     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1475                         ImplicitOp, LV))
1476       return nullptr;
1477 
1478     MachineInstrBuilder MIB =
1479         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1480             .add(Dest)
1481             .addReg(SrcReg, getKillRegState(isKill));
1482     if (ImplicitOp.getReg() != 0)
1483       MIB.add(ImplicitOp);
1484 
1485     NewMI = addOffset(MIB, 1);
1486     break;
1487   }
1488   case X86::DEC64r:
1489   case X86::DEC32r: {
1490     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1491     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1492         : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1493 
1494     bool isKill;
1495     Register SrcReg;
1496     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1497     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1498                         ImplicitOp, LV))
1499       return nullptr;
1500 
1501     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1502                                   .add(Dest)
1503                                   .addReg(SrcReg, getKillRegState(isKill));
1504     if (ImplicitOp.getReg() != 0)
1505       MIB.add(ImplicitOp);
1506 
1507     NewMI = addOffset(MIB, -1);
1508 
1509     break;
1510   }
1511   case X86::DEC8r:
1512   case X86::INC8r:
1513     Is8BitOp = true;
1514     LLVM_FALLTHROUGH;
1515   case X86::DEC16r:
1516   case X86::INC16r:
1517     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1518   case X86::ADD64rr:
1519   case X86::ADD64rr_DB:
1520   case X86::ADD32rr:
1521   case X86::ADD32rr_DB: {
1522     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1523     unsigned Opc;
1524     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1525       Opc = X86::LEA64r;
1526     else
1527       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1528 
1529     bool isKill;
1530     Register SrcReg;
1531     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1532     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1533                         SrcReg, isKill, ImplicitOp, LV))
1534       return nullptr;
1535 
1536     const MachineOperand &Src2 = MI.getOperand(2);
1537     bool isKill2;
1538     Register SrcReg2;
1539     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1540     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1541                         SrcReg2, isKill2, ImplicitOp2, LV))
1542       return nullptr;
1543 
1544     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1545     if (ImplicitOp.getReg() != 0)
1546       MIB.add(ImplicitOp);
1547     if (ImplicitOp2.getReg() != 0)
1548       MIB.add(ImplicitOp2);
1549 
1550     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1551     if (LV && Src2.isKill())
1552       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1553     break;
1554   }
1555   case X86::ADD8rr:
1556   case X86::ADD8rr_DB:
1557     Is8BitOp = true;
1558     LLVM_FALLTHROUGH;
1559   case X86::ADD16rr:
1560   case X86::ADD16rr_DB:
1561     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1562   case X86::ADD64ri32:
1563   case X86::ADD64ri8:
1564   case X86::ADD64ri32_DB:
1565   case X86::ADD64ri8_DB:
1566     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1567     NewMI = addOffset(
1568         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1569         MI.getOperand(2));
1570     break;
1571   case X86::ADD32ri:
1572   case X86::ADD32ri8:
1573   case X86::ADD32ri_DB:
1574   case X86::ADD32ri8_DB: {
1575     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1576     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1577 
1578     bool isKill;
1579     Register SrcReg;
1580     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1581     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1582                         SrcReg, isKill, ImplicitOp, LV))
1583       return nullptr;
1584 
1585     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1586                                   .add(Dest)
1587                                   .addReg(SrcReg, getKillRegState(isKill));
1588     if (ImplicitOp.getReg() != 0)
1589       MIB.add(ImplicitOp);
1590 
1591     NewMI = addOffset(MIB, MI.getOperand(2));
1592     break;
1593   }
1594   case X86::ADD8ri:
1595   case X86::ADD8ri_DB:
1596     Is8BitOp = true;
1597     LLVM_FALLTHROUGH;
1598   case X86::ADD16ri:
1599   case X86::ADD16ri8:
1600   case X86::ADD16ri_DB:
1601   case X86::ADD16ri8_DB:
1602     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1603   case X86::SUB8ri:
1604   case X86::SUB16ri8:
1605   case X86::SUB16ri:
1606     /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1607     return nullptr;
1608   case X86::SUB32ri8:
1609   case X86::SUB32ri: {
1610     if (!MI.getOperand(2).isImm())
1611       return nullptr;
1612     int64_t Imm = MI.getOperand(2).getImm();
1613     if (!isInt<32>(-Imm))
1614       return nullptr;
1615 
1616     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1617     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1618 
1619     bool isKill;
1620     Register SrcReg;
1621     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1622     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1623                         SrcReg, isKill, ImplicitOp, LV))
1624       return nullptr;
1625 
1626     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1627                                   .add(Dest)
1628                                   .addReg(SrcReg, getKillRegState(isKill));
1629     if (ImplicitOp.getReg() != 0)
1630       MIB.add(ImplicitOp);
1631 
1632     NewMI = addOffset(MIB, -Imm);
1633     break;
1634   }
1635 
1636   case X86::SUB64ri8:
1637   case X86::SUB64ri32: {
1638     if (!MI.getOperand(2).isImm())
1639       return nullptr;
1640     int64_t Imm = MI.getOperand(2).getImm();
1641     if (!isInt<32>(-Imm))
1642       return nullptr;
1643 
1644     assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1645 
1646     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1647                                       get(X86::LEA64r)).add(Dest).add(Src);
1648     NewMI = addOffset(MIB, -Imm);
1649     break;
1650   }
1651 
1652   case X86::VMOVDQU8Z128rmk:
1653   case X86::VMOVDQU8Z256rmk:
1654   case X86::VMOVDQU8Zrmk:
1655   case X86::VMOVDQU16Z128rmk:
1656   case X86::VMOVDQU16Z256rmk:
1657   case X86::VMOVDQU16Zrmk:
1658   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1659   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1660   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
1661   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1662   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1663   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
1664   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
1665   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
1666   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
1667   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
1668   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
1669   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk:
1670   case X86::VBROADCASTSDZ256rmk:
1671   case X86::VBROADCASTSDZrmk:
1672   case X86::VBROADCASTSSZ128rmk:
1673   case X86::VBROADCASTSSZ256rmk:
1674   case X86::VBROADCASTSSZrmk:
1675   case X86::VPBROADCASTDZ128rmk:
1676   case X86::VPBROADCASTDZ256rmk:
1677   case X86::VPBROADCASTDZrmk:
1678   case X86::VPBROADCASTQZ128rmk:
1679   case X86::VPBROADCASTQZ256rmk:
1680   case X86::VPBROADCASTQZrmk: {
1681     unsigned Opc;
1682     switch (MIOpc) {
1683     default: llvm_unreachable("Unreachable!");
1684     case X86::VMOVDQU8Z128rmk:     Opc = X86::VPBLENDMBZ128rmk; break;
1685     case X86::VMOVDQU8Z256rmk:     Opc = X86::VPBLENDMBZ256rmk; break;
1686     case X86::VMOVDQU8Zrmk:        Opc = X86::VPBLENDMBZrmk;    break;
1687     case X86::VMOVDQU16Z128rmk:    Opc = X86::VPBLENDMWZ128rmk; break;
1688     case X86::VMOVDQU16Z256rmk:    Opc = X86::VPBLENDMWZ256rmk; break;
1689     case X86::VMOVDQU16Zrmk:       Opc = X86::VPBLENDMWZrmk;    break;
1690     case X86::VMOVDQU32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1691     case X86::VMOVDQU32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1692     case X86::VMOVDQU32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1693     case X86::VMOVDQU64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1694     case X86::VMOVDQU64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1695     case X86::VMOVDQU64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1696     case X86::VMOVUPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1697     case X86::VMOVUPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1698     case X86::VMOVUPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1699     case X86::VMOVUPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1700     case X86::VMOVUPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1701     case X86::VMOVUPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1702     case X86::VMOVDQA32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1703     case X86::VMOVDQA32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1704     case X86::VMOVDQA32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1705     case X86::VMOVDQA64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1706     case X86::VMOVDQA64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1707     case X86::VMOVDQA64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1708     case X86::VMOVAPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1709     case X86::VMOVAPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1710     case X86::VMOVAPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1711     case X86::VMOVAPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1712     case X86::VMOVAPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1713     case X86::VMOVAPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1714     case X86::VBROADCASTSDZ256rmk: Opc = X86::VBLENDMPDZ256rmbk; break;
1715     case X86::VBROADCASTSDZrmk:    Opc = X86::VBLENDMPDZrmbk;    break;
1716     case X86::VBROADCASTSSZ128rmk: Opc = X86::VBLENDMPSZ128rmbk; break;
1717     case X86::VBROADCASTSSZ256rmk: Opc = X86::VBLENDMPSZ256rmbk; break;
1718     case X86::VBROADCASTSSZrmk:    Opc = X86::VBLENDMPSZrmbk;    break;
1719     case X86::VPBROADCASTDZ128rmk: Opc = X86::VPBLENDMDZ128rmbk; break;
1720     case X86::VPBROADCASTDZ256rmk: Opc = X86::VPBLENDMDZ256rmbk; break;
1721     case X86::VPBROADCASTDZrmk:    Opc = X86::VPBLENDMDZrmbk;    break;
1722     case X86::VPBROADCASTQZ128rmk: Opc = X86::VPBLENDMQZ128rmbk; break;
1723     case X86::VPBROADCASTQZ256rmk: Opc = X86::VPBLENDMQZ256rmbk; break;
1724     case X86::VPBROADCASTQZrmk:    Opc = X86::VPBLENDMQZrmbk;    break;
1725     }
1726 
1727     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1728               .add(Dest)
1729               .add(MI.getOperand(2))
1730               .add(Src)
1731               .add(MI.getOperand(3))
1732               .add(MI.getOperand(4))
1733               .add(MI.getOperand(5))
1734               .add(MI.getOperand(6))
1735               .add(MI.getOperand(7));
1736     break;
1737   }
1738 
1739   case X86::VMOVDQU8Z128rrk:
1740   case X86::VMOVDQU8Z256rrk:
1741   case X86::VMOVDQU8Zrrk:
1742   case X86::VMOVDQU16Z128rrk:
1743   case X86::VMOVDQU16Z256rrk:
1744   case X86::VMOVDQU16Zrrk:
1745   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1746   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1747   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
1748   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1749   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1750   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
1751   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
1752   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
1753   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
1754   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
1755   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
1756   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
1757     unsigned Opc;
1758     switch (MIOpc) {
1759     default: llvm_unreachable("Unreachable!");
1760     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
1761     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
1762     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
1763     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1764     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1765     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
1766     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1767     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1768     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1769     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1770     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1771     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1772     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1773     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1774     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1775     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1776     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1777     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1778     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1779     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1780     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1781     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1782     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1783     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1784     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1785     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1786     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1787     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1788     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1789     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1790     }
1791 
1792     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1793               .add(Dest)
1794               .add(MI.getOperand(2))
1795               .add(Src)
1796               .add(MI.getOperand(3));
1797     break;
1798   }
1799   }
1800 
1801   if (!NewMI) return nullptr;
1802 
1803   if (LV) {  // Update live variables
1804     if (Src.isKill())
1805       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1806     if (Dest.isDead())
1807       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1808   }
1809 
1810   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1811   return NewMI;
1812 }
1813 
1814 /// This determines which of three possible cases of a three source commute
1815 /// the source indexes correspond to taking into account any mask operands.
1816 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1817 /// possible.
1818 /// Case 0 - Possible to commute the first and second operands.
1819 /// Case 1 - Possible to commute the first and third operands.
1820 /// Case 2 - Possible to commute the second and third operands.
1821 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1822                                        unsigned SrcOpIdx2) {
1823   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1824   if (SrcOpIdx1 > SrcOpIdx2)
1825     std::swap(SrcOpIdx1, SrcOpIdx2);
1826 
1827   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1828   if (X86II::isKMasked(TSFlags)) {
1829     Op2++;
1830     Op3++;
1831   }
1832 
1833   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1834     return 0;
1835   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1836     return 1;
1837   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1838     return 2;
1839   llvm_unreachable("Unknown three src commute case.");
1840 }
1841 
1842 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1843     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1844     const X86InstrFMA3Group &FMA3Group) const {
1845 
1846   unsigned Opc = MI.getOpcode();
1847 
1848   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1849   // analysis. The commute optimization is legal only if all users of FMA*_Int
1850   // use only the lowest element of the FMA*_Int instruction. Such analysis are
1851   // not implemented yet. So, just return 0 in that case.
1852   // When such analysis are available this place will be the right place for
1853   // calling it.
1854   assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1855          "Intrinsic instructions can't commute operand 1");
1856 
1857   // Determine which case this commute is or if it can't be done.
1858   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1859                                          SrcOpIdx2);
1860   assert(Case < 3 && "Unexpected case number!");
1861 
1862   // Define the FMA forms mapping array that helps to map input FMA form
1863   // to output FMA form to preserve the operation semantics after
1864   // commuting the operands.
1865   const unsigned Form132Index = 0;
1866   const unsigned Form213Index = 1;
1867   const unsigned Form231Index = 2;
1868   static const unsigned FormMapping[][3] = {
1869     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1870     // FMA132 A, C, b; ==> FMA231 C, A, b;
1871     // FMA213 B, A, c; ==> FMA213 A, B, c;
1872     // FMA231 C, A, b; ==> FMA132 A, C, b;
1873     { Form231Index, Form213Index, Form132Index },
1874     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1875     // FMA132 A, c, B; ==> FMA132 B, c, A;
1876     // FMA213 B, a, C; ==> FMA231 C, a, B;
1877     // FMA231 C, a, B; ==> FMA213 B, a, C;
1878     { Form132Index, Form231Index, Form213Index },
1879     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1880     // FMA132 a, C, B; ==> FMA213 a, B, C;
1881     // FMA213 b, A, C; ==> FMA132 b, C, A;
1882     // FMA231 c, A, B; ==> FMA231 c, B, A;
1883     { Form213Index, Form132Index, Form231Index }
1884   };
1885 
1886   unsigned FMAForms[3];
1887   FMAForms[0] = FMA3Group.get132Opcode();
1888   FMAForms[1] = FMA3Group.get213Opcode();
1889   FMAForms[2] = FMA3Group.get231Opcode();
1890   unsigned FormIndex;
1891   for (FormIndex = 0; FormIndex < 3; FormIndex++)
1892     if (Opc == FMAForms[FormIndex])
1893       break;
1894 
1895   // Everything is ready, just adjust the FMA opcode and return it.
1896   FormIndex = FormMapping[Case][FormIndex];
1897   return FMAForms[FormIndex];
1898 }
1899 
1900 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1901                              unsigned SrcOpIdx2) {
1902   // Determine which case this commute is or if it can't be done.
1903   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1904                                          SrcOpIdx2);
1905   assert(Case < 3 && "Unexpected case value!");
1906 
1907   // For each case we need to swap two pairs of bits in the final immediate.
1908   static const uint8_t SwapMasks[3][4] = {
1909     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1910     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1911     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1912   };
1913 
1914   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1915   // Clear out the bits we are swapping.
1916   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1917                            SwapMasks[Case][2] | SwapMasks[Case][3]);
1918   // If the immediate had a bit of the pair set, then set the opposite bit.
1919   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1920   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1921   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1922   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1923   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1924 }
1925 
1926 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1927 // commuted.
1928 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1929 #define VPERM_CASES(Suffix) \
1930   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
1931   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
1932   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
1933   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
1934   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
1935   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
1936   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
1937   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
1938   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
1939   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
1940   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
1941   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
1942 
1943 #define VPERM_CASES_BROADCAST(Suffix) \
1944   VPERM_CASES(Suffix) \
1945   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
1946   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
1947   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
1948   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1949   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1950   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
1951 
1952   switch (Opcode) {
1953   default: return false;
1954   VPERM_CASES(B)
1955   VPERM_CASES_BROADCAST(D)
1956   VPERM_CASES_BROADCAST(PD)
1957   VPERM_CASES_BROADCAST(PS)
1958   VPERM_CASES_BROADCAST(Q)
1959   VPERM_CASES(W)
1960     return true;
1961   }
1962 #undef VPERM_CASES_BROADCAST
1963 #undef VPERM_CASES
1964 }
1965 
1966 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1967 // from the I opcode to the T opcode and vice versa.
1968 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1969 #define VPERM_CASES(Orig, New) \
1970   case X86::Orig##128rr:    return X86::New##128rr;   \
1971   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
1972   case X86::Orig##128rm:    return X86::New##128rm;   \
1973   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
1974   case X86::Orig##256rr:    return X86::New##256rr;   \
1975   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
1976   case X86::Orig##256rm:    return X86::New##256rm;   \
1977   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
1978   case X86::Orig##rr:       return X86::New##rr;      \
1979   case X86::Orig##rrkz:     return X86::New##rrkz;    \
1980   case X86::Orig##rm:       return X86::New##rm;      \
1981   case X86::Orig##rmkz:     return X86::New##rmkz;
1982 
1983 #define VPERM_CASES_BROADCAST(Orig, New) \
1984   VPERM_CASES(Orig, New) \
1985   case X86::Orig##128rmb:   return X86::New##128rmb;   \
1986   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1987   case X86::Orig##256rmb:   return X86::New##256rmb;   \
1988   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1989   case X86::Orig##rmb:      return X86::New##rmb;      \
1990   case X86::Orig##rmbkz:    return X86::New##rmbkz;
1991 
1992   switch (Opcode) {
1993   VPERM_CASES(VPERMI2B, VPERMT2B)
1994   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
1995   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1996   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1997   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
1998   VPERM_CASES(VPERMI2W, VPERMT2W)
1999   VPERM_CASES(VPERMT2B, VPERMI2B)
2000   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
2001   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
2002   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
2003   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
2004   VPERM_CASES(VPERMT2W, VPERMI2W)
2005   }
2006 
2007   llvm_unreachable("Unreachable!");
2008 #undef VPERM_CASES_BROADCAST
2009 #undef VPERM_CASES
2010 }
2011 
2012 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2013                                                    unsigned OpIdx1,
2014                                                    unsigned OpIdx2) const {
2015   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
2016     if (NewMI)
2017       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
2018     return MI;
2019   };
2020 
2021   switch (MI.getOpcode()) {
2022   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2023   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2024   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2025   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2026   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2027   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2028     unsigned Opc;
2029     unsigned Size;
2030     switch (MI.getOpcode()) {
2031     default: llvm_unreachable("Unreachable!");
2032     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2033     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2034     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2035     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2036     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2037     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2038     }
2039     unsigned Amt = MI.getOperand(3).getImm();
2040     auto &WorkingMI = cloneIfNew(MI);
2041     WorkingMI.setDesc(get(Opc));
2042     WorkingMI.getOperand(3).setImm(Size - Amt);
2043     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2044                                                    OpIdx1, OpIdx2);
2045   }
2046   case X86::PFSUBrr:
2047   case X86::PFSUBRrr: {
2048     // PFSUB  x, y: x = x - y
2049     // PFSUBR x, y: x = y - x
2050     unsigned Opc =
2051         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
2052     auto &WorkingMI = cloneIfNew(MI);
2053     WorkingMI.setDesc(get(Opc));
2054     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2055                                                    OpIdx1, OpIdx2);
2056   }
2057   case X86::BLENDPDrri:
2058   case X86::BLENDPSrri:
2059   case X86::VBLENDPDrri:
2060   case X86::VBLENDPSrri:
2061     // If we're optimizing for size, try to use MOVSD/MOVSS.
2062     if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
2063       unsigned Mask, Opc;
2064       switch (MI.getOpcode()) {
2065       default: llvm_unreachable("Unreachable!");
2066       case X86::BLENDPDrri:  Opc = X86::MOVSDrr;  Mask = 0x03; break;
2067       case X86::BLENDPSrri:  Opc = X86::MOVSSrr;  Mask = 0x0F; break;
2068       case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
2069       case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
2070       }
2071       if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
2072         auto &WorkingMI = cloneIfNew(MI);
2073         WorkingMI.setDesc(get(Opc));
2074         WorkingMI.RemoveOperand(3);
2075         return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
2076                                                        /*NewMI=*/false,
2077                                                        OpIdx1, OpIdx2);
2078       }
2079     }
2080     LLVM_FALLTHROUGH;
2081   case X86::PBLENDWrri:
2082   case X86::VBLENDPDYrri:
2083   case X86::VBLENDPSYrri:
2084   case X86::VPBLENDDrri:
2085   case X86::VPBLENDWrri:
2086   case X86::VPBLENDDYrri:
2087   case X86::VPBLENDWYrri:{
2088     int8_t Mask;
2089     switch (MI.getOpcode()) {
2090     default: llvm_unreachable("Unreachable!");
2091     case X86::BLENDPDrri:    Mask = (int8_t)0x03; break;
2092     case X86::BLENDPSrri:    Mask = (int8_t)0x0F; break;
2093     case X86::PBLENDWrri:    Mask = (int8_t)0xFF; break;
2094     case X86::VBLENDPDrri:   Mask = (int8_t)0x03; break;
2095     case X86::VBLENDPSrri:   Mask = (int8_t)0x0F; break;
2096     case X86::VBLENDPDYrri:  Mask = (int8_t)0x0F; break;
2097     case X86::VBLENDPSYrri:  Mask = (int8_t)0xFF; break;
2098     case X86::VPBLENDDrri:   Mask = (int8_t)0x0F; break;
2099     case X86::VPBLENDWrri:   Mask = (int8_t)0xFF; break;
2100     case X86::VPBLENDDYrri:  Mask = (int8_t)0xFF; break;
2101     case X86::VPBLENDWYrri:  Mask = (int8_t)0xFF; break;
2102     }
2103     // Only the least significant bits of Imm are used.
2104     // Using int8_t to ensure it will be sign extended to the int64_t that
2105     // setImm takes in order to match isel behavior.
2106     int8_t Imm = MI.getOperand(3).getImm() & Mask;
2107     auto &WorkingMI = cloneIfNew(MI);
2108     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
2109     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2110                                                    OpIdx1, OpIdx2);
2111   }
2112   case X86::INSERTPSrr:
2113   case X86::VINSERTPSrr:
2114   case X86::VINSERTPSZrr: {
2115     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
2116     unsigned ZMask = Imm & 15;
2117     unsigned DstIdx = (Imm >> 4) & 3;
2118     unsigned SrcIdx = (Imm >> 6) & 3;
2119 
2120     // We can commute insertps if we zero 2 of the elements, the insertion is
2121     // "inline" and we don't override the insertion with a zero.
2122     if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2123         countPopulation(ZMask) == 2) {
2124       unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
2125       assert(AltIdx < 4 && "Illegal insertion index");
2126       unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2127       auto &WorkingMI = cloneIfNew(MI);
2128       WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
2129       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2130                                                      OpIdx1, OpIdx2);
2131     }
2132     return nullptr;
2133   }
2134   case X86::MOVSDrr:
2135   case X86::MOVSSrr:
2136   case X86::VMOVSDrr:
2137   case X86::VMOVSSrr:{
2138     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
2139     if (Subtarget.hasSSE41()) {
2140       unsigned Mask, Opc;
2141       switch (MI.getOpcode()) {
2142       default: llvm_unreachable("Unreachable!");
2143       case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
2144       case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
2145       case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
2146       case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
2147       }
2148 
2149       auto &WorkingMI = cloneIfNew(MI);
2150       WorkingMI.setDesc(get(Opc));
2151       WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
2152       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2153                                                      OpIdx1, OpIdx2);
2154     }
2155 
2156     // Convert to SHUFPD.
2157     assert(MI.getOpcode() == X86::MOVSDrr &&
2158            "Can only commute MOVSDrr without SSE4.1");
2159 
2160     auto &WorkingMI = cloneIfNew(MI);
2161     WorkingMI.setDesc(get(X86::SHUFPDrri));
2162     WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2163     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2164                                                    OpIdx1, OpIdx2);
2165   }
2166   case X86::SHUFPDrri: {
2167     // Commute to MOVSD.
2168     assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
2169     auto &WorkingMI = cloneIfNew(MI);
2170     WorkingMI.setDesc(get(X86::MOVSDrr));
2171     WorkingMI.RemoveOperand(3);
2172     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2173                                                    OpIdx1, OpIdx2);
2174   }
2175   case X86::PCLMULQDQrr:
2176   case X86::VPCLMULQDQrr:
2177   case X86::VPCLMULQDQYrr:
2178   case X86::VPCLMULQDQZrr:
2179   case X86::VPCLMULQDQZ128rr:
2180   case X86::VPCLMULQDQZ256rr: {
2181     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2182     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2183     unsigned Imm = MI.getOperand(3).getImm();
2184     unsigned Src1Hi = Imm & 0x01;
2185     unsigned Src2Hi = Imm & 0x10;
2186     auto &WorkingMI = cloneIfNew(MI);
2187     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2188     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2189                                                    OpIdx1, OpIdx2);
2190   }
2191   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
2192   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
2193   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
2194   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
2195   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
2196   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
2197   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
2198   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
2199   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
2200   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
2201   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
2202   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
2203   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
2204   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
2205   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
2206   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
2207   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
2208   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
2209   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
2210   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
2211   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
2212   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
2213   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
2214   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
2215     // Flip comparison mode immediate (if necessary).
2216     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
2217     Imm = X86::getSwappedVPCMPImm(Imm);
2218     auto &WorkingMI = cloneIfNew(MI);
2219     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
2220     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2221                                                    OpIdx1, OpIdx2);
2222   }
2223   case X86::VPCOMBri: case X86::VPCOMUBri:
2224   case X86::VPCOMDri: case X86::VPCOMUDri:
2225   case X86::VPCOMQri: case X86::VPCOMUQri:
2226   case X86::VPCOMWri: case X86::VPCOMUWri: {
2227     // Flip comparison mode immediate (if necessary).
2228     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
2229     Imm = X86::getSwappedVPCOMImm(Imm);
2230     auto &WorkingMI = cloneIfNew(MI);
2231     WorkingMI.getOperand(3).setImm(Imm);
2232     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2233                                                    OpIdx1, OpIdx2);
2234   }
2235   case X86::VCMPSDZrr:
2236   case X86::VCMPSSZrr:
2237   case X86::VCMPPDZrri:
2238   case X86::VCMPPSZrri:
2239   case X86::VCMPPDZ128rri:
2240   case X86::VCMPPSZ128rri:
2241   case X86::VCMPPDZ256rri:
2242   case X86::VCMPPSZ256rri:
2243   case X86::VCMPPDZrrik:
2244   case X86::VCMPPSZrrik:
2245   case X86::VCMPPDZ128rrik:
2246   case X86::VCMPPSZ128rrik:
2247   case X86::VCMPPDZ256rrik:
2248   case X86::VCMPPSZ256rrik: {
2249     unsigned Imm =
2250                 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f;
2251     Imm = X86::getSwappedVCMPImm(Imm);
2252     auto &WorkingMI = cloneIfNew(MI);
2253     WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm);
2254     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2255                                                    OpIdx1, OpIdx2);
2256   }
2257   case X86::VPERM2F128rr:
2258   case X86::VPERM2I128rr: {
2259     // Flip permute source immediate.
2260     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2261     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2262     int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
2263     auto &WorkingMI = cloneIfNew(MI);
2264     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
2265     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2266                                                    OpIdx1, OpIdx2);
2267   }
2268   case X86::MOVHLPSrr:
2269   case X86::UNPCKHPDrr:
2270   case X86::VMOVHLPSrr:
2271   case X86::VUNPCKHPDrr:
2272   case X86::VMOVHLPSZrr:
2273   case X86::VUNPCKHPDZ128rr: {
2274     assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
2275 
2276     unsigned Opc = MI.getOpcode();
2277     switch (Opc) {
2278     default: llvm_unreachable("Unreachable!");
2279     case X86::MOVHLPSrr:       Opc = X86::UNPCKHPDrr;      break;
2280     case X86::UNPCKHPDrr:      Opc = X86::MOVHLPSrr;       break;
2281     case X86::VMOVHLPSrr:      Opc = X86::VUNPCKHPDrr;     break;
2282     case X86::VUNPCKHPDrr:     Opc = X86::VMOVHLPSrr;      break;
2283     case X86::VMOVHLPSZrr:     Opc = X86::VUNPCKHPDZ128rr; break;
2284     case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr;     break;
2285     }
2286     auto &WorkingMI = cloneIfNew(MI);
2287     WorkingMI.setDesc(get(Opc));
2288     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2289                                                    OpIdx1, OpIdx2);
2290   }
2291   case X86::CMOV16rr:  case X86::CMOV32rr:  case X86::CMOV64rr: {
2292     auto &WorkingMI = cloneIfNew(MI);
2293     unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2294     X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
2295     WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2296     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2297                                                    OpIdx1, OpIdx2);
2298   }
2299   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2300   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2301   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2302   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2303   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2304   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2305   case X86::VPTERNLOGDZrrik:
2306   case X86::VPTERNLOGDZ128rrik:
2307   case X86::VPTERNLOGDZ256rrik:
2308   case X86::VPTERNLOGQZrrik:
2309   case X86::VPTERNLOGQZ128rrik:
2310   case X86::VPTERNLOGQZ256rrik:
2311   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2312   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2313   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2314   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2315   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2316   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2317   case X86::VPTERNLOGDZ128rmbi:
2318   case X86::VPTERNLOGDZ256rmbi:
2319   case X86::VPTERNLOGDZrmbi:
2320   case X86::VPTERNLOGQZ128rmbi:
2321   case X86::VPTERNLOGQZ256rmbi:
2322   case X86::VPTERNLOGQZrmbi:
2323   case X86::VPTERNLOGDZ128rmbikz:
2324   case X86::VPTERNLOGDZ256rmbikz:
2325   case X86::VPTERNLOGDZrmbikz:
2326   case X86::VPTERNLOGQZ128rmbikz:
2327   case X86::VPTERNLOGQZ256rmbikz:
2328   case X86::VPTERNLOGQZrmbikz: {
2329     auto &WorkingMI = cloneIfNew(MI);
2330     commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
2331     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2332                                                    OpIdx1, OpIdx2);
2333   }
2334   default: {
2335     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
2336       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
2337       auto &WorkingMI = cloneIfNew(MI);
2338       WorkingMI.setDesc(get(Opc));
2339       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2340                                                      OpIdx1, OpIdx2);
2341     }
2342 
2343     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2344                                                       MI.getDesc().TSFlags);
2345     if (FMA3Group) {
2346       unsigned Opc =
2347         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
2348       auto &WorkingMI = cloneIfNew(MI);
2349       WorkingMI.setDesc(get(Opc));
2350       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2351                                                      OpIdx1, OpIdx2);
2352     }
2353 
2354     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2355   }
2356   }
2357 }
2358 
2359 bool
2360 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2361                                             unsigned &SrcOpIdx1,
2362                                             unsigned &SrcOpIdx2,
2363                                             bool IsIntrinsic) const {
2364   uint64_t TSFlags = MI.getDesc().TSFlags;
2365 
2366   unsigned FirstCommutableVecOp = 1;
2367   unsigned LastCommutableVecOp = 3;
2368   unsigned KMaskOp = -1U;
2369   if (X86II::isKMasked(TSFlags)) {
2370     // For k-zero-masked operations it is Ok to commute the first vector
2371     // operand. Unless this is an intrinsic instruction.
2372     // For regular k-masked operations a conservative choice is done as the
2373     // elements of the first vector operand, for which the corresponding bit
2374     // in the k-mask operand is set to 0, are copied to the result of the
2375     // instruction.
2376     // TODO/FIXME: The commute still may be legal if it is known that the
2377     // k-mask operand is set to either all ones or all zeroes.
2378     // It is also Ok to commute the 1st operand if all users of MI use only
2379     // the elements enabled by the k-mask operand. For example,
2380     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2381     //                                                     : v1[i];
2382     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2383     //                                  // Ok, to commute v1 in FMADD213PSZrk.
2384 
2385     // The k-mask operand has index = 2 for masked and zero-masked operations.
2386     KMaskOp = 2;
2387 
2388     // The operand with index = 1 is used as a source for those elements for
2389     // which the corresponding bit in the k-mask is set to 0.
2390     if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2391       FirstCommutableVecOp = 3;
2392 
2393     LastCommutableVecOp++;
2394   } else if (IsIntrinsic) {
2395     // Commuting the first operand of an intrinsic instruction isn't possible
2396     // unless we can prove that only the lowest element of the result is used.
2397     FirstCommutableVecOp = 2;
2398   }
2399 
2400   if (isMem(MI, LastCommutableVecOp))
2401     LastCommutableVecOp--;
2402 
2403   // Only the first RegOpsNum operands are commutable.
2404   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2405   // that the operand is not specified/fixed.
2406   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2407       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2408        SrcOpIdx1 == KMaskOp))
2409     return false;
2410   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2411       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2412        SrcOpIdx2 == KMaskOp))
2413     return false;
2414 
2415   // Look for two different register operands assumed to be commutable
2416   // regardless of the FMA opcode. The FMA opcode is adjusted later.
2417   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2418       SrcOpIdx2 == CommuteAnyOperandIndex) {
2419     unsigned CommutableOpIdx2 = SrcOpIdx2;
2420 
2421     // At least one of operands to be commuted is not specified and
2422     // this method is free to choose appropriate commutable operands.
2423     if (SrcOpIdx1 == SrcOpIdx2)
2424       // Both of operands are not fixed. By default set one of commutable
2425       // operands to the last register operand of the instruction.
2426       CommutableOpIdx2 = LastCommutableVecOp;
2427     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2428       // Only one of operands is not fixed.
2429       CommutableOpIdx2 = SrcOpIdx1;
2430 
2431     // CommutableOpIdx2 is well defined now. Let's choose another commutable
2432     // operand and assign its index to CommutableOpIdx1.
2433     Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
2434 
2435     unsigned CommutableOpIdx1;
2436     for (CommutableOpIdx1 = LastCommutableVecOp;
2437          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2438       // Just ignore and skip the k-mask operand.
2439       if (CommutableOpIdx1 == KMaskOp)
2440         continue;
2441 
2442       // The commuted operands must have different registers.
2443       // Otherwise, the commute transformation does not change anything and
2444       // is useless then.
2445       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
2446         break;
2447     }
2448 
2449     // No appropriate commutable operands were found.
2450     if (CommutableOpIdx1 < FirstCommutableVecOp)
2451       return false;
2452 
2453     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2454     // to return those values.
2455     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2456                               CommutableOpIdx1, CommutableOpIdx2))
2457       return false;
2458   }
2459 
2460   return true;
2461 }
2462 
2463 bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2464                                          unsigned &SrcOpIdx1,
2465                                          unsigned &SrcOpIdx2) const {
2466   const MCInstrDesc &Desc = MI.getDesc();
2467   if (!Desc.isCommutable())
2468     return false;
2469 
2470   switch (MI.getOpcode()) {
2471   case X86::CMPSDrr:
2472   case X86::CMPSSrr:
2473   case X86::CMPPDrri:
2474   case X86::CMPPSrri:
2475   case X86::VCMPSDrr:
2476   case X86::VCMPSSrr:
2477   case X86::VCMPPDrri:
2478   case X86::VCMPPSrri:
2479   case X86::VCMPPDYrri:
2480   case X86::VCMPPSYrri:
2481   case X86::VCMPSDZrr:
2482   case X86::VCMPSSZrr:
2483   case X86::VCMPPDZrri:
2484   case X86::VCMPPSZrri:
2485   case X86::VCMPPDZ128rri:
2486   case X86::VCMPPSZ128rri:
2487   case X86::VCMPPDZ256rri:
2488   case X86::VCMPPSZ256rri:
2489   case X86::VCMPPDZrrik:
2490   case X86::VCMPPSZrrik:
2491   case X86::VCMPPDZ128rrik:
2492   case X86::VCMPPSZ128rrik:
2493   case X86::VCMPPDZ256rrik:
2494   case X86::VCMPPSZ256rrik: {
2495     unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2496 
2497     // Float comparison can be safely commuted for
2498     // Ordered/Unordered/Equal/NotEqual tests
2499     unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2500     switch (Imm) {
2501     default:
2502       // EVEX versions can be commuted.
2503       if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2504         break;
2505       return false;
2506     case 0x00: // EQUAL
2507     case 0x03: // UNORDERED
2508     case 0x04: // NOT EQUAL
2509     case 0x07: // ORDERED
2510       break;
2511     }
2512 
2513     // The indices of the commutable operands are 1 and 2 (or 2 and 3
2514     // when masked).
2515     // Assign them to the returned operand indices here.
2516     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2517                                 2 + OpOffset);
2518   }
2519   case X86::MOVSSrr:
2520     // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2521     // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2522     // AVX implies sse4.1.
2523     if (Subtarget.hasSSE41())
2524       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2525     return false;
2526   case X86::SHUFPDrri:
2527     // We can commute this to MOVSD.
2528     if (MI.getOperand(3).getImm() == 0x02)
2529       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2530     return false;
2531   case X86::MOVHLPSrr:
2532   case X86::UNPCKHPDrr:
2533   case X86::VMOVHLPSrr:
2534   case X86::VUNPCKHPDrr:
2535   case X86::VMOVHLPSZrr:
2536   case X86::VUNPCKHPDZ128rr:
2537     if (Subtarget.hasSSE2())
2538       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2539     return false;
2540   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2541   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2542   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2543   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2544   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2545   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2546   case X86::VPTERNLOGDZrrik:
2547   case X86::VPTERNLOGDZ128rrik:
2548   case X86::VPTERNLOGDZ256rrik:
2549   case X86::VPTERNLOGQZrrik:
2550   case X86::VPTERNLOGQZ128rrik:
2551   case X86::VPTERNLOGQZ256rrik:
2552   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2553   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2554   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2555   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2556   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2557   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2558   case X86::VPTERNLOGDZ128rmbi:
2559   case X86::VPTERNLOGDZ256rmbi:
2560   case X86::VPTERNLOGDZrmbi:
2561   case X86::VPTERNLOGQZ128rmbi:
2562   case X86::VPTERNLOGQZ256rmbi:
2563   case X86::VPTERNLOGQZrmbi:
2564   case X86::VPTERNLOGDZ128rmbikz:
2565   case X86::VPTERNLOGDZ256rmbikz:
2566   case X86::VPTERNLOGDZrmbikz:
2567   case X86::VPTERNLOGQZ128rmbikz:
2568   case X86::VPTERNLOGQZ256rmbikz:
2569   case X86::VPTERNLOGQZrmbikz:
2570     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2571   case X86::VPDPWSSDZ128r:
2572   case X86::VPDPWSSDZ128rk:
2573   case X86::VPDPWSSDZ128rkz:
2574   case X86::VPDPWSSDZ256r:
2575   case X86::VPDPWSSDZ256rk:
2576   case X86::VPDPWSSDZ256rkz:
2577   case X86::VPDPWSSDZr:
2578   case X86::VPDPWSSDZrk:
2579   case X86::VPDPWSSDZrkz:
2580   case X86::VPDPWSSDSZ128r:
2581   case X86::VPDPWSSDSZ128rk:
2582   case X86::VPDPWSSDSZ128rkz:
2583   case X86::VPDPWSSDSZ256r:
2584   case X86::VPDPWSSDSZ256rk:
2585   case X86::VPDPWSSDSZ256rkz:
2586   case X86::VPDPWSSDSZr:
2587   case X86::VPDPWSSDSZrk:
2588   case X86::VPDPWSSDSZrkz:
2589   case X86::VPMADD52HUQZ128r:
2590   case X86::VPMADD52HUQZ128rk:
2591   case X86::VPMADD52HUQZ128rkz:
2592   case X86::VPMADD52HUQZ256r:
2593   case X86::VPMADD52HUQZ256rk:
2594   case X86::VPMADD52HUQZ256rkz:
2595   case X86::VPMADD52HUQZr:
2596   case X86::VPMADD52HUQZrk:
2597   case X86::VPMADD52HUQZrkz:
2598   case X86::VPMADD52LUQZ128r:
2599   case X86::VPMADD52LUQZ128rk:
2600   case X86::VPMADD52LUQZ128rkz:
2601   case X86::VPMADD52LUQZ256r:
2602   case X86::VPMADD52LUQZ256rk:
2603   case X86::VPMADD52LUQZ256rkz:
2604   case X86::VPMADD52LUQZr:
2605   case X86::VPMADD52LUQZrk:
2606   case X86::VPMADD52LUQZrkz: {
2607     unsigned CommutableOpIdx1 = 2;
2608     unsigned CommutableOpIdx2 = 3;
2609     if (X86II::isKMasked(Desc.TSFlags)) {
2610       // Skip the mask register.
2611       ++CommutableOpIdx1;
2612       ++CommutableOpIdx2;
2613     }
2614     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2615                               CommutableOpIdx1, CommutableOpIdx2))
2616       return false;
2617     if (!MI.getOperand(SrcOpIdx1).isReg() ||
2618         !MI.getOperand(SrcOpIdx2).isReg())
2619       // No idea.
2620       return false;
2621     return true;
2622   }
2623 
2624   default:
2625     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2626                                                       MI.getDesc().TSFlags);
2627     if (FMA3Group)
2628       return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2629                                            FMA3Group->isIntrinsic());
2630 
2631     // Handled masked instructions since we need to skip over the mask input
2632     // and the preserved input.
2633     if (X86II::isKMasked(Desc.TSFlags)) {
2634       // First assume that the first input is the mask operand and skip past it.
2635       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2636       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2637       // Check if the first input is tied. If there isn't one then we only
2638       // need to skip the mask operand which we did above.
2639       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2640                                              MCOI::TIED_TO) != -1)) {
2641         // If this is zero masking instruction with a tied operand, we need to
2642         // move the first index back to the first input since this must
2643         // be a 3 input instruction and we want the first two non-mask inputs.
2644         // Otherwise this is a 2 input instruction with a preserved input and
2645         // mask, so we need to move the indices to skip one more input.
2646         if (X86II::isKMergeMasked(Desc.TSFlags)) {
2647           ++CommutableOpIdx1;
2648           ++CommutableOpIdx2;
2649         } else {
2650           --CommutableOpIdx1;
2651         }
2652       }
2653 
2654       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2655                                 CommutableOpIdx1, CommutableOpIdx2))
2656         return false;
2657 
2658       if (!MI.getOperand(SrcOpIdx1).isReg() ||
2659           !MI.getOperand(SrcOpIdx2).isReg())
2660         // No idea.
2661         return false;
2662       return true;
2663     }
2664 
2665     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2666   }
2667   return false;
2668 }
2669 
2670 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2671   switch (MI.getOpcode()) {
2672   default: return X86::COND_INVALID;
2673   case X86::JCC_1:
2674     return static_cast<X86::CondCode>(
2675         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2676   }
2677 }
2678 
2679 /// Return condition code of a SETCC opcode.
2680 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2681   switch (MI.getOpcode()) {
2682   default: return X86::COND_INVALID;
2683   case X86::SETCCr: case X86::SETCCm:
2684     return static_cast<X86::CondCode>(
2685         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2686   }
2687 }
2688 
2689 /// Return condition code of a CMov opcode.
2690 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2691   switch (MI.getOpcode()) {
2692   default: return X86::COND_INVALID;
2693   case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2694   case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2695     return static_cast<X86::CondCode>(
2696         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2697   }
2698 }
2699 
2700 /// Return the inverse of the specified condition,
2701 /// e.g. turning COND_E to COND_NE.
2702 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2703   switch (CC) {
2704   default: llvm_unreachable("Illegal condition code!");
2705   case X86::COND_E:  return X86::COND_NE;
2706   case X86::COND_NE: return X86::COND_E;
2707   case X86::COND_L:  return X86::COND_GE;
2708   case X86::COND_LE: return X86::COND_G;
2709   case X86::COND_G:  return X86::COND_LE;
2710   case X86::COND_GE: return X86::COND_L;
2711   case X86::COND_B:  return X86::COND_AE;
2712   case X86::COND_BE: return X86::COND_A;
2713   case X86::COND_A:  return X86::COND_BE;
2714   case X86::COND_AE: return X86::COND_B;
2715   case X86::COND_S:  return X86::COND_NS;
2716   case X86::COND_NS: return X86::COND_S;
2717   case X86::COND_P:  return X86::COND_NP;
2718   case X86::COND_NP: return X86::COND_P;
2719   case X86::COND_O:  return X86::COND_NO;
2720   case X86::COND_NO: return X86::COND_O;
2721   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
2722   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2723   }
2724 }
2725 
2726 /// Assuming the flags are set by MI(a,b), return the condition code if we
2727 /// modify the instructions such that flags are set by MI(b,a).
2728 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2729   switch (CC) {
2730   default: return X86::COND_INVALID;
2731   case X86::COND_E:  return X86::COND_E;
2732   case X86::COND_NE: return X86::COND_NE;
2733   case X86::COND_L:  return X86::COND_G;
2734   case X86::COND_LE: return X86::COND_GE;
2735   case X86::COND_G:  return X86::COND_L;
2736   case X86::COND_GE: return X86::COND_LE;
2737   case X86::COND_B:  return X86::COND_A;
2738   case X86::COND_BE: return X86::COND_AE;
2739   case X86::COND_A:  return X86::COND_B;
2740   case X86::COND_AE: return X86::COND_BE;
2741   }
2742 }
2743 
2744 std::pair<X86::CondCode, bool>
2745 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2746   X86::CondCode CC = X86::COND_INVALID;
2747   bool NeedSwap = false;
2748   switch (Predicate) {
2749   default: break;
2750   // Floating-point Predicates
2751   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
2752   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
2753   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
2754   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
2755   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
2756   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
2757   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
2758   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
2759   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
2760   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
2761   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
2762   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
2763   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
2764   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2765 
2766   // Integer Predicates
2767   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
2768   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
2769   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
2770   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
2771   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
2772   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
2773   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
2774   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
2775   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
2776   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
2777   }
2778 
2779   return std::make_pair(CC, NeedSwap);
2780 }
2781 
2782 /// Return a setcc opcode based on whether it has memory operand.
2783 unsigned X86::getSETOpc(bool HasMemoryOperand) {
2784   return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2785 }
2786 
2787 /// Return a cmov opcode for the given register size in bytes, and operand type.
2788 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2789   switch(RegBytes) {
2790   default: llvm_unreachable("Illegal register size!");
2791   case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2792   case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2793   case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr;
2794   }
2795 }
2796 
2797 /// Get the VPCMP immediate for the given condition.
2798 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2799   switch (CC) {
2800   default: llvm_unreachable("Unexpected SETCC condition");
2801   case ISD::SETNE:  return 4;
2802   case ISD::SETEQ:  return 0;
2803   case ISD::SETULT:
2804   case ISD::SETLT: return 1;
2805   case ISD::SETUGT:
2806   case ISD::SETGT: return 6;
2807   case ISD::SETUGE:
2808   case ISD::SETGE: return 5;
2809   case ISD::SETULE:
2810   case ISD::SETLE: return 2;
2811   }
2812 }
2813 
2814 /// Get the VPCMP immediate if the operands are swapped.
2815 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2816   switch (Imm) {
2817   default: llvm_unreachable("Unreachable!");
2818   case 0x01: Imm = 0x06; break; // LT  -> NLE
2819   case 0x02: Imm = 0x05; break; // LE  -> NLT
2820   case 0x05: Imm = 0x02; break; // NLT -> LE
2821   case 0x06: Imm = 0x01; break; // NLE -> LT
2822   case 0x00: // EQ
2823   case 0x03: // FALSE
2824   case 0x04: // NE
2825   case 0x07: // TRUE
2826     break;
2827   }
2828 
2829   return Imm;
2830 }
2831 
2832 /// Get the VPCOM immediate if the operands are swapped.
2833 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2834   switch (Imm) {
2835   default: llvm_unreachable("Unreachable!");
2836   case 0x00: Imm = 0x02; break; // LT -> GT
2837   case 0x01: Imm = 0x03; break; // LE -> GE
2838   case 0x02: Imm = 0x00; break; // GT -> LT
2839   case 0x03: Imm = 0x01; break; // GE -> LE
2840   case 0x04: // EQ
2841   case 0x05: // NE
2842   case 0x06: // FALSE
2843   case 0x07: // TRUE
2844     break;
2845   }
2846 
2847   return Imm;
2848 }
2849 
2850 /// Get the VCMP immediate if the operands are swapped.
2851 unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2852   // Only need the lower 2 bits to distinquish.
2853   switch (Imm & 0x3) {
2854   default: llvm_unreachable("Unreachable!");
2855   case 0x00: case 0x03:
2856     // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2857     break;
2858   case 0x01: case 0x02:
2859     // Need to toggle bits 3:0. Bit 4 stays the same.
2860     Imm ^= 0xf;
2861     break;
2862   }
2863 
2864   return Imm;
2865 }
2866 
2867 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2868   switch (MI.getOpcode()) {
2869   case X86::TCRETURNdi:
2870   case X86::TCRETURNri:
2871   case X86::TCRETURNmi:
2872   case X86::TCRETURNdi64:
2873   case X86::TCRETURNri64:
2874   case X86::TCRETURNmi64:
2875     return true;
2876   default:
2877     return false;
2878   }
2879 }
2880 
2881 bool X86InstrInfo::canMakeTailCallConditional(
2882     SmallVectorImpl<MachineOperand> &BranchCond,
2883     const MachineInstr &TailCall) const {
2884   if (TailCall.getOpcode() != X86::TCRETURNdi &&
2885       TailCall.getOpcode() != X86::TCRETURNdi64) {
2886     // Only direct calls can be done with a conditional branch.
2887     return false;
2888   }
2889 
2890   const MachineFunction *MF = TailCall.getParent()->getParent();
2891   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2892     // Conditional tail calls confuse the Win64 unwinder.
2893     return false;
2894   }
2895 
2896   assert(BranchCond.size() == 1);
2897   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2898     // Can't make a conditional tail call with this condition.
2899     return false;
2900   }
2901 
2902   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2903   if (X86FI->getTCReturnAddrDelta() != 0 ||
2904       TailCall.getOperand(1).getImm() != 0) {
2905     // A conditional tail call cannot do any stack adjustment.
2906     return false;
2907   }
2908 
2909   return true;
2910 }
2911 
2912 void X86InstrInfo::replaceBranchWithTailCall(
2913     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2914     const MachineInstr &TailCall) const {
2915   assert(canMakeTailCallConditional(BranchCond, TailCall));
2916 
2917   MachineBasicBlock::iterator I = MBB.end();
2918   while (I != MBB.begin()) {
2919     --I;
2920     if (I->isDebugInstr())
2921       continue;
2922     if (!I->isBranch())
2923       assert(0 && "Can't find the branch to replace!");
2924 
2925     X86::CondCode CC = X86::getCondFromBranch(*I);
2926     assert(BranchCond.size() == 1);
2927     if (CC != BranchCond[0].getImm())
2928       continue;
2929 
2930     break;
2931   }
2932 
2933   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2934                                                          : X86::TCRETURNdi64cc;
2935 
2936   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2937   MIB->addOperand(TailCall.getOperand(0)); // Destination.
2938   MIB.addImm(0); // Stack offset (not used).
2939   MIB->addOperand(BranchCond[0]); // Condition.
2940   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2941 
2942   // Add implicit uses and defs of all live regs potentially clobbered by the
2943   // call. This way they still appear live across the call.
2944   LivePhysRegs LiveRegs(getRegisterInfo());
2945   LiveRegs.addLiveOuts(MBB);
2946   SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2947   LiveRegs.stepForward(*MIB, Clobbers);
2948   for (const auto &C : Clobbers) {
2949     MIB.addReg(C.first, RegState::Implicit);
2950     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2951   }
2952 
2953   I->eraseFromParent();
2954 }
2955 
2956 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2957 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2958 // fallthrough MBB cannot be identified.
2959 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2960                                             MachineBasicBlock *TBB) {
2961   // Look for non-EHPad successors other than TBB. If we find exactly one, it
2962   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2963   // and fallthrough MBB. If we find more than one, we cannot identify the
2964   // fallthrough MBB and should return nullptr.
2965   MachineBasicBlock *FallthroughBB = nullptr;
2966   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2967     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2968       continue;
2969     // Return a nullptr if we found more than one fallthrough successor.
2970     if (FallthroughBB && FallthroughBB != TBB)
2971       return nullptr;
2972     FallthroughBB = *SI;
2973   }
2974   return FallthroughBB;
2975 }
2976 
2977 bool X86InstrInfo::AnalyzeBranchImpl(
2978     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2979     SmallVectorImpl<MachineOperand> &Cond,
2980     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2981 
2982   // Start from the bottom of the block and work up, examining the
2983   // terminator instructions.
2984   MachineBasicBlock::iterator I = MBB.end();
2985   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2986   while (I != MBB.begin()) {
2987     --I;
2988     if (I->isDebugInstr())
2989       continue;
2990 
2991     // Working from the bottom, when we see a non-terminator instruction, we're
2992     // done.
2993     if (!isUnpredicatedTerminator(*I))
2994       break;
2995 
2996     // A terminator that isn't a branch can't easily be handled by this
2997     // analysis.
2998     if (!I->isBranch())
2999       return true;
3000 
3001     // Handle unconditional branches.
3002     if (I->getOpcode() == X86::JMP_1) {
3003       UnCondBrIter = I;
3004 
3005       if (!AllowModify) {
3006         TBB = I->getOperand(0).getMBB();
3007         continue;
3008       }
3009 
3010       // If the block has any instructions after a JMP, delete them.
3011       while (std::next(I) != MBB.end())
3012         std::next(I)->eraseFromParent();
3013 
3014       Cond.clear();
3015       FBB = nullptr;
3016 
3017       // Delete the JMP if it's equivalent to a fall-through.
3018       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3019         TBB = nullptr;
3020         I->eraseFromParent();
3021         I = MBB.end();
3022         UnCondBrIter = MBB.end();
3023         continue;
3024       }
3025 
3026       // TBB is used to indicate the unconditional destination.
3027       TBB = I->getOperand(0).getMBB();
3028       continue;
3029     }
3030 
3031     // Handle conditional branches.
3032     X86::CondCode BranchCode = X86::getCondFromBranch(*I);
3033     if (BranchCode == X86::COND_INVALID)
3034       return true;  // Can't handle indirect branch.
3035 
3036     // In practice we should never have an undef eflags operand, if we do
3037     // abort here as we are not prepared to preserve the flag.
3038     if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
3039       return true;
3040 
3041     // Working from the bottom, handle the first conditional branch.
3042     if (Cond.empty()) {
3043       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3044       if (AllowModify && UnCondBrIter != MBB.end() &&
3045           MBB.isLayoutSuccessor(TargetBB)) {
3046         // If we can modify the code and it ends in something like:
3047         //
3048         //     jCC L1
3049         //     jmp L2
3050         //   L1:
3051         //     ...
3052         //   L2:
3053         //
3054         // Then we can change this to:
3055         //
3056         //     jnCC L2
3057         //   L1:
3058         //     ...
3059         //   L2:
3060         //
3061         // Which is a bit more efficient.
3062         // We conditionally jump to the fall-through block.
3063         BranchCode = GetOppositeBranchCondition(BranchCode);
3064         MachineBasicBlock::iterator OldInst = I;
3065 
3066         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
3067           .addMBB(UnCondBrIter->getOperand(0).getMBB())
3068           .addImm(BranchCode);
3069         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3070           .addMBB(TargetBB);
3071 
3072         OldInst->eraseFromParent();
3073         UnCondBrIter->eraseFromParent();
3074 
3075         // Restart the analysis.
3076         UnCondBrIter = MBB.end();
3077         I = MBB.end();
3078         continue;
3079       }
3080 
3081       FBB = TBB;
3082       TBB = I->getOperand(0).getMBB();
3083       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3084       CondBranches.push_back(&*I);
3085       continue;
3086     }
3087 
3088     // Handle subsequent conditional branches. Only handle the case where all
3089     // conditional branches branch to the same destination and their condition
3090     // opcodes fit one of the special multi-branch idioms.
3091     assert(Cond.size() == 1);
3092     assert(TBB);
3093 
3094     // If the conditions are the same, we can leave them alone.
3095     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3096     auto NewTBB = I->getOperand(0).getMBB();
3097     if (OldBranchCode == BranchCode && TBB == NewTBB)
3098       continue;
3099 
3100     // If they differ, see if they fit one of the known patterns. Theoretically,
3101     // we could handle more patterns here, but we shouldn't expect to see them
3102     // if instruction selection has done a reasonable job.
3103     if (TBB == NewTBB &&
3104                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3105                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3106       BranchCode = X86::COND_NE_OR_P;
3107     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3108                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3109       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
3110         return true;
3111 
3112       // X86::COND_E_AND_NP usually has two different branch destinations.
3113       //
3114       // JP B1
3115       // JE B2
3116       // JMP B1
3117       // B1:
3118       // B2:
3119       //
3120       // Here this condition branches to B2 only if NP && E. It has another
3121       // equivalent form:
3122       //
3123       // JNE B1
3124       // JNP B2
3125       // JMP B1
3126       // B1:
3127       // B2:
3128       //
3129       // Similarly it branches to B2 only if E && NP. That is why this condition
3130       // is named with COND_E_AND_NP.
3131       BranchCode = X86::COND_E_AND_NP;
3132     } else
3133       return true;
3134 
3135     // Update the MachineOperand.
3136     Cond[0].setImm(BranchCode);
3137     CondBranches.push_back(&*I);
3138   }
3139 
3140   return false;
3141 }
3142 
3143 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3144                                  MachineBasicBlock *&TBB,
3145                                  MachineBasicBlock *&FBB,
3146                                  SmallVectorImpl<MachineOperand> &Cond,
3147                                  bool AllowModify) const {
3148   SmallVector<MachineInstr *, 4> CondBranches;
3149   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3150 }
3151 
3152 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
3153                                           MachineBranchPredicate &MBP,
3154                                           bool AllowModify) const {
3155   using namespace std::placeholders;
3156 
3157   SmallVector<MachineOperand, 4> Cond;
3158   SmallVector<MachineInstr *, 4> CondBranches;
3159   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3160                         AllowModify))
3161     return true;
3162 
3163   if (Cond.size() != 1)
3164     return true;
3165 
3166   assert(MBP.TrueDest && "expected!");
3167 
3168   if (!MBP.FalseDest)
3169     MBP.FalseDest = MBB.getNextNode();
3170 
3171   const TargetRegisterInfo *TRI = &getRegisterInfo();
3172 
3173   MachineInstr *ConditionDef = nullptr;
3174   bool SingleUseCondition = true;
3175 
3176   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
3177     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
3178       ConditionDef = &*I;
3179       break;
3180     }
3181 
3182     if (I->readsRegister(X86::EFLAGS, TRI))
3183       SingleUseCondition = false;
3184   }
3185 
3186   if (!ConditionDef)
3187     return true;
3188 
3189   if (SingleUseCondition) {
3190     for (auto *Succ : MBB.successors())
3191       if (Succ->isLiveIn(X86::EFLAGS))
3192         SingleUseCondition = false;
3193   }
3194 
3195   MBP.ConditionDef = ConditionDef;
3196   MBP.SingleUseCondition = SingleUseCondition;
3197 
3198   // Currently we only recognize the simple pattern:
3199   //
3200   //   test %reg, %reg
3201   //   je %label
3202   //
3203   const unsigned TestOpcode =
3204       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3205 
3206   if (ConditionDef->getOpcode() == TestOpcode &&
3207       ConditionDef->getNumOperands() == 3 &&
3208       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3209       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3210     MBP.LHS = ConditionDef->getOperand(0);
3211     MBP.RHS = MachineOperand::CreateImm(0);
3212     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3213                         ? MachineBranchPredicate::PRED_NE
3214                         : MachineBranchPredicate::PRED_EQ;
3215     return false;
3216   }
3217 
3218   return true;
3219 }
3220 
3221 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
3222                                     int *BytesRemoved) const {
3223   assert(!BytesRemoved && "code size not handled");
3224 
3225   MachineBasicBlock::iterator I = MBB.end();
3226   unsigned Count = 0;
3227 
3228   while (I != MBB.begin()) {
3229     --I;
3230     if (I->isDebugInstr())
3231       continue;
3232     if (I->getOpcode() != X86::JMP_1 &&
3233         X86::getCondFromBranch(*I) == X86::COND_INVALID)
3234       break;
3235     // Remove the branch.
3236     I->eraseFromParent();
3237     I = MBB.end();
3238     ++Count;
3239   }
3240 
3241   return Count;
3242 }
3243 
3244 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
3245                                     MachineBasicBlock *TBB,
3246                                     MachineBasicBlock *FBB,
3247                                     ArrayRef<MachineOperand> Cond,
3248                                     const DebugLoc &DL,
3249                                     int *BytesAdded) const {
3250   // Shouldn't be a fall through.
3251   assert(TBB && "insertBranch must not be told to insert a fallthrough");
3252   assert((Cond.size() == 1 || Cond.size() == 0) &&
3253          "X86 branch conditions have one component!");
3254   assert(!BytesAdded && "code size not handled");
3255 
3256   if (Cond.empty()) {
3257     // Unconditional branch?
3258     assert(!FBB && "Unconditional branch with multiple successors!");
3259     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3260     return 1;
3261   }
3262 
3263   // If FBB is null, it is implied to be a fall-through block.
3264   bool FallThru = FBB == nullptr;
3265 
3266   // Conditional branch.
3267   unsigned Count = 0;
3268   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3269   switch (CC) {
3270   case X86::COND_NE_OR_P:
3271     // Synthesize NE_OR_P with two branches.
3272     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
3273     ++Count;
3274     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
3275     ++Count;
3276     break;
3277   case X86::COND_E_AND_NP:
3278     // Use the next block of MBB as FBB if it is null.
3279     if (FBB == nullptr) {
3280       FBB = getFallThroughMBB(&MBB, TBB);
3281       assert(FBB && "MBB cannot be the last block in function when the false "
3282                     "body is a fall-through.");
3283     }
3284     // Synthesize COND_E_AND_NP with two branches.
3285     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
3286     ++Count;
3287     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
3288     ++Count;
3289     break;
3290   default: {
3291     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
3292     ++Count;
3293   }
3294   }
3295   if (!FallThru) {
3296     // Two-way Conditional branch. Insert the second branch.
3297     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3298     ++Count;
3299   }
3300   return Count;
3301 }
3302 
3303 bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
3304                                    ArrayRef<MachineOperand> Cond,
3305                                    Register DstReg, Register TrueReg,
3306                                    Register FalseReg, int &CondCycles,
3307                                    int &TrueCycles, int &FalseCycles) const {
3308   // Not all subtargets have cmov instructions.
3309   if (!Subtarget.hasCMov())
3310     return false;
3311   if (Cond.size() != 1)
3312     return false;
3313   // We cannot do the composite conditions, at least not in SSA form.
3314   if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
3315     return false;
3316 
3317   // Check register classes.
3318   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3319   const TargetRegisterClass *RC =
3320     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3321   if (!RC)
3322     return false;
3323 
3324   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3325   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3326       X86::GR32RegClass.hasSubClassEq(RC) ||
3327       X86::GR64RegClass.hasSubClassEq(RC)) {
3328     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3329     // Bridge. Probably Ivy Bridge as well.
3330     CondCycles = 2;
3331     TrueCycles = 2;
3332     FalseCycles = 2;
3333     return true;
3334   }
3335 
3336   // Can't do vectors.
3337   return false;
3338 }
3339 
3340 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3341                                 MachineBasicBlock::iterator I,
3342                                 const DebugLoc &DL, Register DstReg,
3343                                 ArrayRef<MachineOperand> Cond, Register TrueReg,
3344                                 Register FalseReg) const {
3345   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3346   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3347   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
3348   assert(Cond.size() == 1 && "Invalid Cond array");
3349   unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
3350                                     false /*HasMemoryOperand*/);
3351   BuildMI(MBB, I, DL, get(Opc), DstReg)
3352       .addReg(FalseReg)
3353       .addReg(TrueReg)
3354       .addImm(Cond[0].getImm());
3355 }
3356 
3357 /// Test if the given register is a physical h register.
3358 static bool isHReg(unsigned Reg) {
3359   return X86::GR8_ABCD_HRegClass.contains(Reg);
3360 }
3361 
3362 // Try and copy between VR128/VR64 and GR64 registers.
3363 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3364                                         const X86Subtarget &Subtarget) {
3365   bool HasAVX = Subtarget.hasAVX();
3366   bool HasAVX512 = Subtarget.hasAVX512();
3367 
3368   // SrcReg(MaskReg) -> DestReg(GR64)
3369   // SrcReg(MaskReg) -> DestReg(GR32)
3370 
3371   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3372   if (X86::VK16RegClass.contains(SrcReg)) {
3373     if (X86::GR64RegClass.contains(DestReg)) {
3374       assert(Subtarget.hasBWI());
3375       return X86::KMOVQrk;
3376     }
3377     if (X86::GR32RegClass.contains(DestReg))
3378       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
3379   }
3380 
3381   // SrcReg(GR64) -> DestReg(MaskReg)
3382   // SrcReg(GR32) -> DestReg(MaskReg)
3383 
3384   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3385   if (X86::VK16RegClass.contains(DestReg)) {
3386     if (X86::GR64RegClass.contains(SrcReg)) {
3387       assert(Subtarget.hasBWI());
3388       return X86::KMOVQkr;
3389     }
3390     if (X86::GR32RegClass.contains(SrcReg))
3391       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
3392   }
3393 
3394 
3395   // SrcReg(VR128) -> DestReg(GR64)
3396   // SrcReg(VR64)  -> DestReg(GR64)
3397   // SrcReg(GR64)  -> DestReg(VR128)
3398   // SrcReg(GR64)  -> DestReg(VR64)
3399 
3400   if (X86::GR64RegClass.contains(DestReg)) {
3401     if (X86::VR128XRegClass.contains(SrcReg))
3402       // Copy from a VR128 register to a GR64 register.
3403       return HasAVX512 ? X86::VMOVPQIto64Zrr :
3404              HasAVX    ? X86::VMOVPQIto64rr  :
3405                          X86::MOVPQIto64rr;
3406     if (X86::VR64RegClass.contains(SrcReg))
3407       // Copy from a VR64 register to a GR64 register.
3408       return X86::MMX_MOVD64from64rr;
3409   } else if (X86::GR64RegClass.contains(SrcReg)) {
3410     // Copy from a GR64 register to a VR128 register.
3411     if (X86::VR128XRegClass.contains(DestReg))
3412       return HasAVX512 ? X86::VMOV64toPQIZrr :
3413              HasAVX    ? X86::VMOV64toPQIrr  :
3414                          X86::MOV64toPQIrr;
3415     // Copy from a GR64 register to a VR64 register.
3416     if (X86::VR64RegClass.contains(DestReg))
3417       return X86::MMX_MOVD64to64rr;
3418   }
3419 
3420   // SrcReg(VR128) -> DestReg(GR32)
3421   // SrcReg(GR32)  -> DestReg(VR128)
3422 
3423   if (X86::GR32RegClass.contains(DestReg) &&
3424       X86::VR128XRegClass.contains(SrcReg))
3425     // Copy from a VR128 register to a GR32 register.
3426     return HasAVX512 ? X86::VMOVPDI2DIZrr :
3427            HasAVX    ? X86::VMOVPDI2DIrr  :
3428                        X86::MOVPDI2DIrr;
3429 
3430   if (X86::VR128XRegClass.contains(DestReg) &&
3431       X86::GR32RegClass.contains(SrcReg))
3432     // Copy from a VR128 register to a VR128 register.
3433     return HasAVX512 ? X86::VMOVDI2PDIZrr :
3434            HasAVX    ? X86::VMOVDI2PDIrr  :
3435                        X86::MOVDI2PDIrr;
3436   return 0;
3437 }
3438 
3439 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3440                                MachineBasicBlock::iterator MI,
3441                                const DebugLoc &DL, MCRegister DestReg,
3442                                MCRegister SrcReg, bool KillSrc) const {
3443   // First deal with the normal symmetric copies.
3444   bool HasAVX = Subtarget.hasAVX();
3445   bool HasVLX = Subtarget.hasVLX();
3446   unsigned Opc = 0;
3447   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3448     Opc = X86::MOV64rr;
3449   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3450     Opc = X86::MOV32rr;
3451   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3452     Opc = X86::MOV16rr;
3453   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3454     // Copying to or from a physical H register on x86-64 requires a NOREX
3455     // move.  Otherwise use a normal move.
3456     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3457         Subtarget.is64Bit()) {
3458       Opc = X86::MOV8rr_NOREX;
3459       // Both operands must be encodable without an REX prefix.
3460       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3461              "8-bit H register can not be copied outside GR8_NOREX");
3462     } else
3463       Opc = X86::MOV8rr;
3464   }
3465   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3466     Opc = X86::MMX_MOVQ64rr;
3467   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3468     if (HasVLX)
3469       Opc = X86::VMOVAPSZ128rr;
3470     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3471       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3472     else {
3473       // If this an extended register and we don't have VLX we need to use a
3474       // 512-bit move.
3475       Opc = X86::VMOVAPSZrr;
3476       const TargetRegisterInfo *TRI = &getRegisterInfo();
3477       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3478                                          &X86::VR512RegClass);
3479       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3480                                         &X86::VR512RegClass);
3481     }
3482   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3483     if (HasVLX)
3484       Opc = X86::VMOVAPSZ256rr;
3485     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3486       Opc = X86::VMOVAPSYrr;
3487     else {
3488       // If this an extended register and we don't have VLX we need to use a
3489       // 512-bit move.
3490       Opc = X86::VMOVAPSZrr;
3491       const TargetRegisterInfo *TRI = &getRegisterInfo();
3492       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3493                                          &X86::VR512RegClass);
3494       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3495                                         &X86::VR512RegClass);
3496     }
3497   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3498     Opc = X86::VMOVAPSZrr;
3499   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3500   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3501     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3502   if (!Opc)
3503     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3504 
3505   if (Opc) {
3506     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3507       .addReg(SrcReg, getKillRegState(KillSrc));
3508     return;
3509   }
3510 
3511   if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3512     // FIXME: We use a fatal error here because historically LLVM has tried
3513     // lower some of these physreg copies and we want to ensure we get
3514     // reasonable bug reports if someone encounters a case no other testing
3515     // found. This path should be removed after the LLVM 7 release.
3516     report_fatal_error("Unable to copy EFLAGS physical register!");
3517   }
3518 
3519   LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3520                     << RI.getName(DestReg) << '\n');
3521   report_fatal_error("Cannot emit physreg copy instruction");
3522 }
3523 
3524 Optional<DestSourcePair>
3525 X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
3526   if (MI.isMoveReg())
3527     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
3528   return None;
3529 }
3530 
3531 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3532                                       const TargetRegisterClass *RC,
3533                                       bool isStackAligned,
3534                                       const X86Subtarget &STI,
3535                                       bool load) {
3536   bool HasAVX = STI.hasAVX();
3537   bool HasAVX512 = STI.hasAVX512();
3538   bool HasVLX = STI.hasVLX();
3539 
3540   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3541   default:
3542     llvm_unreachable("Unknown spill size");
3543   case 1:
3544     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3545     if (STI.is64Bit())
3546       // Copying to or from a physical H register on x86-64 requires a NOREX
3547       // move.  Otherwise use a normal move.
3548       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3549         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3550     return load ? X86::MOV8rm : X86::MOV8mr;
3551   case 2:
3552     if (X86::VK16RegClass.hasSubClassEq(RC))
3553       return load ? X86::KMOVWkm : X86::KMOVWmk;
3554     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3555     return load ? X86::MOV16rm : X86::MOV16mr;
3556   case 4:
3557     if (X86::GR32RegClass.hasSubClassEq(RC))
3558       return load ? X86::MOV32rm : X86::MOV32mr;
3559     if (X86::FR32XRegClass.hasSubClassEq(RC))
3560       return load ?
3561         (HasAVX512 ? X86::VMOVSSZrm_alt :
3562          HasAVX    ? X86::VMOVSSrm_alt :
3563                      X86::MOVSSrm_alt) :
3564         (HasAVX512 ? X86::VMOVSSZmr :
3565          HasAVX    ? X86::VMOVSSmr :
3566                      X86::MOVSSmr);
3567     if (X86::RFP32RegClass.hasSubClassEq(RC))
3568       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3569     if (X86::VK32RegClass.hasSubClassEq(RC)) {
3570       assert(STI.hasBWI() && "KMOVD requires BWI");
3571       return load ? X86::KMOVDkm : X86::KMOVDmk;
3572     }
3573     // All of these mask pair classes have the same spill size, the same kind
3574     // of kmov instructions can be used with all of them.
3575     if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3576         X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3577         X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3578         X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3579         X86::VK16PAIRRegClass.hasSubClassEq(RC))
3580       return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3581     llvm_unreachable("Unknown 4-byte regclass");
3582   case 8:
3583     if (X86::GR64RegClass.hasSubClassEq(RC))
3584       return load ? X86::MOV64rm : X86::MOV64mr;
3585     if (X86::FR64XRegClass.hasSubClassEq(RC))
3586       return load ?
3587         (HasAVX512 ? X86::VMOVSDZrm_alt :
3588          HasAVX    ? X86::VMOVSDrm_alt :
3589                      X86::MOVSDrm_alt) :
3590         (HasAVX512 ? X86::VMOVSDZmr :
3591          HasAVX    ? X86::VMOVSDmr :
3592                      X86::MOVSDmr);
3593     if (X86::VR64RegClass.hasSubClassEq(RC))
3594       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3595     if (X86::RFP64RegClass.hasSubClassEq(RC))
3596       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3597     if (X86::VK64RegClass.hasSubClassEq(RC)) {
3598       assert(STI.hasBWI() && "KMOVQ requires BWI");
3599       return load ? X86::KMOVQkm : X86::KMOVQmk;
3600     }
3601     llvm_unreachable("Unknown 8-byte regclass");
3602   case 10:
3603     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3604     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3605   case 16: {
3606     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3607       // If stack is realigned we can use aligned stores.
3608       if (isStackAligned)
3609         return load ?
3610           (HasVLX    ? X86::VMOVAPSZ128rm :
3611            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3612            HasAVX    ? X86::VMOVAPSrm :
3613                        X86::MOVAPSrm):
3614           (HasVLX    ? X86::VMOVAPSZ128mr :
3615            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3616            HasAVX    ? X86::VMOVAPSmr :
3617                        X86::MOVAPSmr);
3618       else
3619         return load ?
3620           (HasVLX    ? X86::VMOVUPSZ128rm :
3621            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3622            HasAVX    ? X86::VMOVUPSrm :
3623                        X86::MOVUPSrm):
3624           (HasVLX    ? X86::VMOVUPSZ128mr :
3625            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3626            HasAVX    ? X86::VMOVUPSmr :
3627                        X86::MOVUPSmr);
3628     }
3629     if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3630       if (STI.is64Bit())
3631         return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3632       else
3633         return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3634     }
3635     llvm_unreachable("Unknown 16-byte regclass");
3636   }
3637   case 32:
3638     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3639     // If stack is realigned we can use aligned stores.
3640     if (isStackAligned)
3641       return load ?
3642         (HasVLX    ? X86::VMOVAPSZ256rm :
3643          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3644                      X86::VMOVAPSYrm) :
3645         (HasVLX    ? X86::VMOVAPSZ256mr :
3646          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3647                      X86::VMOVAPSYmr);
3648     else
3649       return load ?
3650         (HasVLX    ? X86::VMOVUPSZ256rm :
3651          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3652                      X86::VMOVUPSYrm) :
3653         (HasVLX    ? X86::VMOVUPSZ256mr :
3654          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3655                      X86::VMOVUPSYmr);
3656   case 64:
3657     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3658     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3659     if (isStackAligned)
3660       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3661     else
3662       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3663   }
3664 }
3665 
3666 Optional<ExtAddrMode>
3667 X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
3668                                       const TargetRegisterInfo *TRI) const {
3669   const MCInstrDesc &Desc = MemI.getDesc();
3670   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3671   if (MemRefBegin < 0)
3672     return None;
3673 
3674   MemRefBegin += X86II::getOperandBias(Desc);
3675 
3676   auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg);
3677   if (!BaseOp.isReg()) // Can be an MO_FrameIndex
3678     return None;
3679 
3680   const MachineOperand &DispMO = MemI.getOperand(MemRefBegin + X86::AddrDisp);
3681   // Displacement can be symbolic
3682   if (!DispMO.isImm())
3683     return None;
3684 
3685   ExtAddrMode AM;
3686   AM.BaseReg = BaseOp.getReg();
3687   AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg();
3688   AM.Scale = MemI.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm();
3689   AM.Displacement = DispMO.getImm();
3690   return AM;
3691 }
3692 
3693 bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
3694                                            const Register Reg,
3695                                            int64_t &ImmVal) const {
3696   if (MI.getOpcode() != X86::MOV32ri && MI.getOpcode() != X86::MOV64ri)
3697     return false;
3698   // Mov Src can be a global address.
3699   if (!MI.getOperand(1).isImm() || MI.getOperand(0).getReg() != Reg)
3700     return false;
3701   ImmVal = MI.getOperand(1).getImm();
3702   return true;
3703 }
3704 
3705 bool X86InstrInfo::preservesZeroValueInReg(
3706     const MachineInstr *MI, const Register NullValueReg,
3707     const TargetRegisterInfo *TRI) const {
3708   if (!MI->modifiesRegister(NullValueReg, TRI))
3709     return true;
3710   switch (MI->getOpcode()) {
3711   // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
3712   // X.
3713   case X86::SHR64ri:
3714   case X86::SHR32ri:
3715   case X86::SHL64ri:
3716   case X86::SHL32ri:
3717     assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&
3718            "expected for shift opcode!");
3719     return MI->getOperand(0).getReg() == NullValueReg &&
3720            MI->getOperand(1).getReg() == NullValueReg;
3721   // Zero extend of a sub-reg of NullValueReg into itself does not change the
3722   // null value.
3723   case X86::MOV32rr:
3724     return llvm::all_of(MI->operands(), [&](const MachineOperand &MO) {
3725       return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
3726     });
3727   default:
3728     return false;
3729   }
3730   llvm_unreachable("Should be handled above!");
3731 }
3732 
3733 bool X86InstrInfo::getMemOperandsWithOffsetWidth(
3734     const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
3735     int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3736     const TargetRegisterInfo *TRI) const {
3737   const MCInstrDesc &Desc = MemOp.getDesc();
3738   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3739   if (MemRefBegin < 0)
3740     return false;
3741 
3742   MemRefBegin += X86II::getOperandBias(Desc);
3743 
3744   const MachineOperand *BaseOp =
3745       &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3746   if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3747     return false;
3748 
3749   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3750     return false;
3751 
3752   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3753       X86::NoRegister)
3754     return false;
3755 
3756   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3757 
3758   // Displacement can be symbolic
3759   if (!DispMO.isImm())
3760     return false;
3761 
3762   Offset = DispMO.getImm();
3763 
3764   if (!BaseOp->isReg())
3765     return false;
3766 
3767   OffsetIsScalable = false;
3768   // FIXME: Relying on memoperands() may not be right thing to do here. Check
3769   // with X86 maintainers, and fix it accordingly. For now, it is ok, since
3770   // there is no use of `Width` for X86 back-end at the moment.
3771   Width =
3772       !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0;
3773   BaseOps.push_back(BaseOp);
3774   return true;
3775 }
3776 
3777 static unsigned getStoreRegOpcode(unsigned SrcReg,
3778                                   const TargetRegisterClass *RC,
3779                                   bool isStackAligned,
3780                                   const X86Subtarget &STI) {
3781   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3782 }
3783 
3784 
3785 static unsigned getLoadRegOpcode(unsigned DestReg,
3786                                  const TargetRegisterClass *RC,
3787                                  bool isStackAligned,
3788                                  const X86Subtarget &STI) {
3789   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3790 }
3791 
3792 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3793                                        MachineBasicBlock::iterator MI,
3794                                        Register SrcReg, bool isKill, int FrameIdx,
3795                                        const TargetRegisterClass *RC,
3796                                        const TargetRegisterInfo *TRI) const {
3797   const MachineFunction &MF = *MBB.getParent();
3798   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3799          "Stack slot too small for store");
3800   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3801   bool isAligned =
3802       (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3803       RI.canRealignStack(MF);
3804   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3805   addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3806     .addReg(SrcReg, getKillRegState(isKill));
3807 }
3808 
3809 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3810                                         MachineBasicBlock::iterator MI,
3811                                         Register DestReg, int FrameIdx,
3812                                         const TargetRegisterClass *RC,
3813                                         const TargetRegisterInfo *TRI) const {
3814   const MachineFunction &MF = *MBB.getParent();
3815   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3816   bool isAligned =
3817       (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3818       RI.canRealignStack(MF);
3819   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3820   addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3821 }
3822 
3823 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
3824                                   Register &SrcReg2, int &CmpMask,
3825                                   int &CmpValue) const {
3826   switch (MI.getOpcode()) {
3827   default: break;
3828   case X86::CMP64ri32:
3829   case X86::CMP64ri8:
3830   case X86::CMP32ri:
3831   case X86::CMP32ri8:
3832   case X86::CMP16ri:
3833   case X86::CMP16ri8:
3834   case X86::CMP8ri:
3835     SrcReg = MI.getOperand(0).getReg();
3836     SrcReg2 = 0;
3837     if (MI.getOperand(1).isImm()) {
3838       CmpMask = ~0;
3839       CmpValue = MI.getOperand(1).getImm();
3840     } else {
3841       CmpMask = CmpValue = 0;
3842     }
3843     return true;
3844   // A SUB can be used to perform comparison.
3845   case X86::SUB64rm:
3846   case X86::SUB32rm:
3847   case X86::SUB16rm:
3848   case X86::SUB8rm:
3849     SrcReg = MI.getOperand(1).getReg();
3850     SrcReg2 = 0;
3851     CmpMask = 0;
3852     CmpValue = 0;
3853     return true;
3854   case X86::SUB64rr:
3855   case X86::SUB32rr:
3856   case X86::SUB16rr:
3857   case X86::SUB8rr:
3858     SrcReg = MI.getOperand(1).getReg();
3859     SrcReg2 = MI.getOperand(2).getReg();
3860     CmpMask = 0;
3861     CmpValue = 0;
3862     return true;
3863   case X86::SUB64ri32:
3864   case X86::SUB64ri8:
3865   case X86::SUB32ri:
3866   case X86::SUB32ri8:
3867   case X86::SUB16ri:
3868   case X86::SUB16ri8:
3869   case X86::SUB8ri:
3870     SrcReg = MI.getOperand(1).getReg();
3871     SrcReg2 = 0;
3872     if (MI.getOperand(2).isImm()) {
3873       CmpMask = ~0;
3874       CmpValue = MI.getOperand(2).getImm();
3875     } else {
3876       CmpMask = CmpValue = 0;
3877     }
3878     return true;
3879   case X86::CMP64rr:
3880   case X86::CMP32rr:
3881   case X86::CMP16rr:
3882   case X86::CMP8rr:
3883     SrcReg = MI.getOperand(0).getReg();
3884     SrcReg2 = MI.getOperand(1).getReg();
3885     CmpMask = 0;
3886     CmpValue = 0;
3887     return true;
3888   case X86::TEST8rr:
3889   case X86::TEST16rr:
3890   case X86::TEST32rr:
3891   case X86::TEST64rr:
3892     SrcReg = MI.getOperand(0).getReg();
3893     if (MI.getOperand(1).getReg() != SrcReg)
3894       return false;
3895     // Compare against zero.
3896     SrcReg2 = 0;
3897     CmpMask = ~0;
3898     CmpValue = 0;
3899     return true;
3900   }
3901   return false;
3902 }
3903 
3904 /// Check whether the first instruction, whose only
3905 /// purpose is to update flags, can be made redundant.
3906 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3907 /// This function can be extended later on.
3908 /// SrcReg, SrcRegs: register operands for FlagI.
3909 /// ImmValue: immediate for FlagI if it takes an immediate.
3910 inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3911                                         Register SrcReg, Register SrcReg2,
3912                                         int ImmMask, int ImmValue,
3913                                         const MachineInstr &OI) {
3914   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3915        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3916        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3917        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3918       ((OI.getOperand(1).getReg() == SrcReg &&
3919         OI.getOperand(2).getReg() == SrcReg2) ||
3920        (OI.getOperand(1).getReg() == SrcReg2 &&
3921         OI.getOperand(2).getReg() == SrcReg)))
3922     return true;
3923 
3924   if (ImmMask != 0 &&
3925       ((FlagI.getOpcode() == X86::CMP64ri32 &&
3926         OI.getOpcode() == X86::SUB64ri32) ||
3927        (FlagI.getOpcode() == X86::CMP64ri8 &&
3928         OI.getOpcode() == X86::SUB64ri8) ||
3929        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3930        (FlagI.getOpcode() == X86::CMP32ri8 &&
3931         OI.getOpcode() == X86::SUB32ri8) ||
3932        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3933        (FlagI.getOpcode() == X86::CMP16ri8 &&
3934         OI.getOpcode() == X86::SUB16ri8) ||
3935        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3936       OI.getOperand(1).getReg() == SrcReg &&
3937       OI.getOperand(2).getImm() == ImmValue)
3938     return true;
3939   return false;
3940 }
3941 
3942 /// Check whether the definition can be converted
3943 /// to remove a comparison against zero.
3944 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3945   NoSignFlag = false;
3946 
3947   switch (MI.getOpcode()) {
3948   default: return false;
3949 
3950   // The shift instructions only modify ZF if their shift count is non-zero.
3951   // N.B.: The processor truncates the shift count depending on the encoding.
3952   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3953   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3954      return getTruncatedShiftCount(MI, 2) != 0;
3955 
3956   // Some left shift instructions can be turned into LEA instructions but only
3957   // if their flags aren't used. Avoid transforming such instructions.
3958   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3959     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3960     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3961     return ShAmt != 0;
3962   }
3963 
3964   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3965   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3966      return getTruncatedShiftCount(MI, 3) != 0;
3967 
3968   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3969   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3970   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3971   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3972   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3973   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3974   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3975   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3976   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3977   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3978   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3979   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3980   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3981   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3982   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3983   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3984   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3985   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3986   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3987   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3988   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3989   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3990   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3991   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3992   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3993   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3994   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3995   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3996   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
3997   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
3998   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
3999   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
4000   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
4001   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
4002   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
4003   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
4004   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
4005   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4006   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
4007   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
4008   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
4009   case X86::ANDN32rr:  case X86::ANDN32rm:
4010   case X86::ANDN64rr:  case X86::ANDN64rm:
4011   case X86::BLSI32rr:  case X86::BLSI32rm:
4012   case X86::BLSI64rr:  case X86::BLSI64rm:
4013   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4014   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4015   case X86::BLSR32rr:  case X86::BLSR32rm:
4016   case X86::BLSR64rr:  case X86::BLSR64rm:
4017   case X86::BZHI32rr:  case X86::BZHI32rm:
4018   case X86::BZHI64rr:  case X86::BZHI64rm:
4019   case X86::LZCNT16rr: case X86::LZCNT16rm:
4020   case X86::LZCNT32rr: case X86::LZCNT32rm:
4021   case X86::LZCNT64rr: case X86::LZCNT64rm:
4022   case X86::POPCNT16rr:case X86::POPCNT16rm:
4023   case X86::POPCNT32rr:case X86::POPCNT32rm:
4024   case X86::POPCNT64rr:case X86::POPCNT64rm:
4025   case X86::TZCNT16rr: case X86::TZCNT16rm:
4026   case X86::TZCNT32rr: case X86::TZCNT32rm:
4027   case X86::TZCNT64rr: case X86::TZCNT64rm:
4028   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
4029   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
4030   case X86::BLCI32rr:    case X86::BLCI32rm:
4031   case X86::BLCI64rr:    case X86::BLCI64rm:
4032   case X86::BLCIC32rr:   case X86::BLCIC32rm:
4033   case X86::BLCIC64rr:   case X86::BLCIC64rm:
4034   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
4035   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
4036   case X86::BLCS32rr:    case X86::BLCS32rm:
4037   case X86::BLCS64rr:    case X86::BLCS64rm:
4038   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
4039   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
4040   case X86::BLSIC32rr:   case X86::BLSIC32rm:
4041   case X86::BLSIC64rr:   case X86::BLSIC64rm:
4042   case X86::T1MSKC32rr:  case X86::T1MSKC32rm:
4043   case X86::T1MSKC64rr:  case X86::T1MSKC64rm:
4044   case X86::TZMSK32rr:   case X86::TZMSK32rm:
4045   case X86::TZMSK64rr:   case X86::TZMSK64rm:
4046     return true;
4047   case X86::BEXTR32rr:   case X86::BEXTR64rr:
4048   case X86::BEXTR32rm:   case X86::BEXTR64rm:
4049   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
4050   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
4051     // BEXTR doesn't update the sign flag so we can't use it.
4052     NoSignFlag = true;
4053     return true;
4054   }
4055 }
4056 
4057 /// Check whether the use can be converted to remove a comparison against zero.
4058 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
4059   switch (MI.getOpcode()) {
4060   default: return X86::COND_INVALID;
4061   case X86::NEG8r:
4062   case X86::NEG16r:
4063   case X86::NEG32r:
4064   case X86::NEG64r:
4065     return X86::COND_AE;
4066   case X86::LZCNT16rr:
4067   case X86::LZCNT32rr:
4068   case X86::LZCNT64rr:
4069     return X86::COND_B;
4070   case X86::POPCNT16rr:
4071   case X86::POPCNT32rr:
4072   case X86::POPCNT64rr:
4073     return X86::COND_E;
4074   case X86::TZCNT16rr:
4075   case X86::TZCNT32rr:
4076   case X86::TZCNT64rr:
4077     return X86::COND_B;
4078   case X86::BSF16rr:
4079   case X86::BSF32rr:
4080   case X86::BSF64rr:
4081   case X86::BSR16rr:
4082   case X86::BSR32rr:
4083   case X86::BSR64rr:
4084     return X86::COND_E;
4085   case X86::BLSI32rr:
4086   case X86::BLSI64rr:
4087     return X86::COND_AE;
4088   case X86::BLSR32rr:
4089   case X86::BLSR64rr:
4090   case X86::BLSMSK32rr:
4091   case X86::BLSMSK64rr:
4092     return X86::COND_B;
4093   // TODO: TBM instructions.
4094   }
4095 }
4096 
4097 /// Check if there exists an earlier instruction that
4098 /// operates on the same source operands and sets flags in the same way as
4099 /// Compare; remove Compare if possible.
4100 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
4101                                         Register SrcReg2, int CmpMask,
4102                                         int CmpValue,
4103                                         const MachineRegisterInfo *MRI) const {
4104   // Check whether we can replace SUB with CMP.
4105   switch (CmpInstr.getOpcode()) {
4106   default: break;
4107   case X86::SUB64ri32:
4108   case X86::SUB64ri8:
4109   case X86::SUB32ri:
4110   case X86::SUB32ri8:
4111   case X86::SUB16ri:
4112   case X86::SUB16ri8:
4113   case X86::SUB8ri:
4114   case X86::SUB64rm:
4115   case X86::SUB32rm:
4116   case X86::SUB16rm:
4117   case X86::SUB8rm:
4118   case X86::SUB64rr:
4119   case X86::SUB32rr:
4120   case X86::SUB16rr:
4121   case X86::SUB8rr: {
4122     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
4123       return false;
4124     // There is no use of the destination register, we can replace SUB with CMP.
4125     unsigned NewOpcode = 0;
4126     switch (CmpInstr.getOpcode()) {
4127     default: llvm_unreachable("Unreachable!");
4128     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4129     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4130     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4131     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4132     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4133     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4134     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4135     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4136     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4137     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4138     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4139     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4140     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4141     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4142     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4143     }
4144     CmpInstr.setDesc(get(NewOpcode));
4145     CmpInstr.RemoveOperand(0);
4146     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4147     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4148         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4149       return false;
4150   }
4151   }
4152 
4153   // Get the unique definition of SrcReg.
4154   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4155   if (!MI) return false;
4156 
4157   // CmpInstr is the first instruction of the BB.
4158   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4159 
4160   // If we are comparing against zero, check whether we can use MI to update
4161   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4162   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
4163   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
4164     return false;
4165 
4166   // If we have a use of the source register between the def and our compare
4167   // instruction we can eliminate the compare iff the use sets EFLAGS in the
4168   // right way.
4169   bool ShouldUpdateCC = false;
4170   bool NoSignFlag = false;
4171   X86::CondCode NewCC = X86::COND_INVALID;
4172   if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
4173     // Scan forward from the use until we hit the use we're looking for or the
4174     // compare instruction.
4175     for (MachineBasicBlock::iterator J = MI;; ++J) {
4176       // Do we have a convertible instruction?
4177       NewCC = isUseDefConvertible(*J);
4178       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4179           J->getOperand(1).getReg() == SrcReg) {
4180         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4181         ShouldUpdateCC = true; // Update CC later on.
4182         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4183         // with the new def.
4184         Def = J;
4185         MI = &*Def;
4186         break;
4187       }
4188 
4189       if (J == I)
4190         return false;
4191     }
4192   }
4193 
4194   // We are searching for an earlier instruction that can make CmpInstr
4195   // redundant and that instruction will be saved in Sub.
4196   MachineInstr *Sub = nullptr;
4197   const TargetRegisterInfo *TRI = &getRegisterInfo();
4198 
4199   // We iterate backward, starting from the instruction before CmpInstr and
4200   // stop when reaching the definition of a source register or done with the BB.
4201   // RI points to the instruction before CmpInstr.
4202   // If the definition is in this basic block, RE points to the definition;
4203   // otherwise, RE is the rend of the basic block.
4204   MachineBasicBlock::reverse_iterator
4205       RI = ++I.getReverse(),
4206       RE = CmpInstr.getParent() == MI->getParent()
4207                ? Def.getReverse() /* points to MI */
4208                : CmpInstr.getParent()->rend();
4209   MachineInstr *Movr0Inst = nullptr;
4210   for (; RI != RE; ++RI) {
4211     MachineInstr &Instr = *RI;
4212     // Check whether CmpInstr can be made redundant by the current instruction.
4213     if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
4214                                            CmpValue, Instr)) {
4215       Sub = &Instr;
4216       break;
4217     }
4218 
4219     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
4220         Instr.readsRegister(X86::EFLAGS, TRI)) {
4221       // This instruction modifies or uses EFLAGS.
4222 
4223       // MOV32r0 etc. are implemented with xor which clobbers condition code.
4224       // They are safe to move up, if the definition to EFLAGS is dead and
4225       // earlier instructions do not read or write EFLAGS.
4226       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
4227           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
4228         Movr0Inst = &Instr;
4229         continue;
4230       }
4231 
4232       // We can't remove CmpInstr.
4233       return false;
4234     }
4235   }
4236 
4237   // Return false if no candidates exist.
4238   if (!IsCmpZero && !Sub)
4239     return false;
4240 
4241   bool IsSwapped =
4242       (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
4243        Sub->getOperand(2).getReg() == SrcReg);
4244 
4245   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4246   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4247   // If we are done with the basic block, we need to check whether EFLAGS is
4248   // live-out.
4249   bool IsSafe = false;
4250   SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
4251   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
4252   for (++I; I != E; ++I) {
4253     const MachineInstr &Instr = *I;
4254     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4255     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4256     // We should check the usage if this instruction uses and updates EFLAGS.
4257     if (!UseEFLAGS && ModifyEFLAGS) {
4258       // It is safe to remove CmpInstr if EFLAGS is updated again.
4259       IsSafe = true;
4260       break;
4261     }
4262     if (!UseEFLAGS && !ModifyEFLAGS)
4263       continue;
4264 
4265     // EFLAGS is used by this instruction.
4266     X86::CondCode OldCC = X86::COND_INVALID;
4267     if (IsCmpZero || IsSwapped) {
4268       // We decode the condition code from opcode.
4269       if (Instr.isBranch())
4270         OldCC = X86::getCondFromBranch(Instr);
4271       else {
4272         OldCC = X86::getCondFromSETCC(Instr);
4273         if (OldCC == X86::COND_INVALID)
4274           OldCC = X86::getCondFromCMov(Instr);
4275       }
4276       if (OldCC == X86::COND_INVALID) return false;
4277     }
4278     X86::CondCode ReplacementCC = X86::COND_INVALID;
4279     if (IsCmpZero) {
4280       switch (OldCC) {
4281       default: break;
4282       case X86::COND_A: case X86::COND_AE:
4283       case X86::COND_B: case X86::COND_BE:
4284       case X86::COND_G: case X86::COND_GE:
4285       case X86::COND_L: case X86::COND_LE:
4286       case X86::COND_O: case X86::COND_NO:
4287         // CF and OF are used, we can't perform this optimization.
4288         return false;
4289       case X86::COND_S: case X86::COND_NS:
4290         // If SF is used, but the instruction doesn't update the SF, then we
4291         // can't do the optimization.
4292         if (NoSignFlag)
4293           return false;
4294         break;
4295       }
4296 
4297       // If we're updating the condition code check if we have to reverse the
4298       // condition.
4299       if (ShouldUpdateCC)
4300         switch (OldCC) {
4301         default:
4302           return false;
4303         case X86::COND_E:
4304           ReplacementCC = NewCC;
4305           break;
4306         case X86::COND_NE:
4307           ReplacementCC = GetOppositeBranchCondition(NewCC);
4308           break;
4309         }
4310     } else if (IsSwapped) {
4311       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4312       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4313       // We swap the condition code and synthesize the new opcode.
4314       ReplacementCC = getSwappedCondition(OldCC);
4315       if (ReplacementCC == X86::COND_INVALID) return false;
4316     }
4317 
4318     if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
4319       // Push the MachineInstr to OpsToUpdate.
4320       // If it is safe to remove CmpInstr, the condition code of these
4321       // instructions will be modified.
4322       OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
4323     }
4324     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4325       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4326       IsSafe = true;
4327       break;
4328     }
4329   }
4330 
4331   // If EFLAGS is not killed nor re-defined, we should check whether it is
4332   // live-out. If it is live-out, do not optimize.
4333   if ((IsCmpZero || IsSwapped) && !IsSafe) {
4334     MachineBasicBlock *MBB = CmpInstr.getParent();
4335     for (MachineBasicBlock *Successor : MBB->successors())
4336       if (Successor->isLiveIn(X86::EFLAGS))
4337         return false;
4338   }
4339 
4340   // The instruction to be updated is either Sub or MI.
4341   Sub = IsCmpZero ? MI : Sub;
4342   // Move Movr0Inst to the appropriate place before Sub.
4343   if (Movr0Inst) {
4344     // Look backwards until we find a def that doesn't use the current EFLAGS.
4345     Def = Sub;
4346     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
4347                                         InsertE = Sub->getParent()->rend();
4348     for (; InsertI != InsertE; ++InsertI) {
4349       MachineInstr *Instr = &*InsertI;
4350       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4351           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4352         Sub->getParent()->remove(Movr0Inst);
4353         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4354                                    Movr0Inst);
4355         break;
4356       }
4357     }
4358     if (InsertI == InsertE)
4359       return false;
4360   }
4361 
4362   // Make sure Sub instruction defines EFLAGS and mark the def live.
4363   MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
4364   assert(FlagDef && "Unable to locate a def EFLAGS operand");
4365   FlagDef->setIsDead(false);
4366 
4367   CmpInstr.eraseFromParent();
4368 
4369   // Modify the condition code of instructions in OpsToUpdate.
4370   for (auto &Op : OpsToUpdate) {
4371     Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
4372         .setImm(Op.second);
4373   }
4374   return true;
4375 }
4376 
4377 /// Try to remove the load by folding it to a register
4378 /// operand at the use. We fold the load instructions if load defines a virtual
4379 /// register, the virtual register is used once in the same BB, and the
4380 /// instructions in-between do not load or store, and have no side effects.
4381 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
4382                                               const MachineRegisterInfo *MRI,
4383                                               Register &FoldAsLoadDefReg,
4384                                               MachineInstr *&DefMI) const {
4385   // Check whether we can move DefMI here.
4386   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4387   assert(DefMI);
4388   bool SawStore = false;
4389   if (!DefMI->isSafeToMove(nullptr, SawStore))
4390     return nullptr;
4391 
4392   // Collect information about virtual register operands of MI.
4393   SmallVector<unsigned, 1> SrcOperandIds;
4394   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4395     MachineOperand &MO = MI.getOperand(i);
4396     if (!MO.isReg())
4397       continue;
4398     Register Reg = MO.getReg();
4399     if (Reg != FoldAsLoadDefReg)
4400       continue;
4401     // Do not fold if we have a subreg use or a def.
4402     if (MO.getSubReg() || MO.isDef())
4403       return nullptr;
4404     SrcOperandIds.push_back(i);
4405   }
4406   if (SrcOperandIds.empty())
4407     return nullptr;
4408 
4409   // Check whether we can fold the def into SrcOperandId.
4410   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
4411     FoldAsLoadDefReg = 0;
4412     return FoldMI;
4413   }
4414 
4415   return nullptr;
4416 }
4417 
4418 /// Expand a single-def pseudo instruction to a two-addr
4419 /// instruction with two undef reads of the register being defined.
4420 /// This is used for mapping:
4421 ///   %xmm4 = V_SET0
4422 /// to:
4423 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
4424 ///
4425 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4426                              const MCInstrDesc &Desc) {
4427   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4428   Register Reg = MIB.getReg(0);
4429   MIB->setDesc(Desc);
4430 
4431   // MachineInstr::addOperand() will insert explicit operands before any
4432   // implicit operands.
4433   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4434   // But we don't trust that.
4435   assert(MIB.getReg(1) == Reg &&
4436          MIB.getReg(2) == Reg && "Misplaced operand");
4437   return true;
4438 }
4439 
4440 /// Expand a single-def pseudo instruction to a two-addr
4441 /// instruction with two %k0 reads.
4442 /// This is used for mapping:
4443 ///   %k4 = K_SET1
4444 /// to:
4445 ///   %k4 = KXNORrr %k0, %k0
4446 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
4447                             const MCInstrDesc &Desc, unsigned Reg) {
4448   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4449   MIB->setDesc(Desc);
4450   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4451   return true;
4452 }
4453 
4454 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
4455                           bool MinusOne) {
4456   MachineBasicBlock &MBB = *MIB->getParent();
4457   DebugLoc DL = MIB->getDebugLoc();
4458   Register Reg = MIB.getReg(0);
4459 
4460   // Insert the XOR.
4461   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
4462       .addReg(Reg, RegState::Undef)
4463       .addReg(Reg, RegState::Undef);
4464 
4465   // Turn the pseudo into an INC or DEC.
4466   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
4467   MIB.addReg(Reg);
4468 
4469   return true;
4470 }
4471 
4472 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
4473                                const TargetInstrInfo &TII,
4474                                const X86Subtarget &Subtarget) {
4475   MachineBasicBlock &MBB = *MIB->getParent();
4476   DebugLoc DL = MIB->getDebugLoc();
4477   int64_t Imm = MIB->getOperand(1).getImm();
4478   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
4479   MachineBasicBlock::iterator I = MIB.getInstr();
4480 
4481   int StackAdjustment;
4482 
4483   if (Subtarget.is64Bit()) {
4484     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
4485            MIB->getOpcode() == X86::MOV32ImmSExti8);
4486 
4487     // Can't use push/pop lowering if the function might write to the red zone.
4488     X86MachineFunctionInfo *X86FI =
4489         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
4490     if (X86FI->getUsesRedZone()) {
4491       MIB->setDesc(TII.get(MIB->getOpcode() ==
4492                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
4493       return true;
4494     }
4495 
4496     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4497     // widen the register if necessary.
4498     StackAdjustment = 8;
4499     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4500     MIB->setDesc(TII.get(X86::POP64r));
4501     MIB->getOperand(0)
4502         .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
4503   } else {
4504     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
4505     StackAdjustment = 4;
4506     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4507     MIB->setDesc(TII.get(X86::POP32r));
4508   }
4509   MIB->RemoveOperand(1);
4510   MIB->addImplicitDefUseOperands(*MBB.getParent());
4511 
4512   // Build CFI if necessary.
4513   MachineFunction &MF = *MBB.getParent();
4514   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4515   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4516   bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
4517   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4518   if (EmitCFI) {
4519     TFL->BuildCFI(MBB, I, DL,
4520         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4521     TFL->BuildCFI(MBB, std::next(I), DL,
4522         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4523   }
4524 
4525   return true;
4526 }
4527 
4528 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4529 // code sequence is needed for other targets.
4530 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4531                                  const TargetInstrInfo &TII) {
4532   MachineBasicBlock &MBB = *MIB->getParent();
4533   DebugLoc DL = MIB->getDebugLoc();
4534   Register Reg = MIB.getReg(0);
4535   const GlobalValue *GV =
4536       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4537   auto Flags = MachineMemOperand::MOLoad |
4538                MachineMemOperand::MODereferenceable |
4539                MachineMemOperand::MOInvariant;
4540   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4541       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, Align(8));
4542   MachineBasicBlock::iterator I = MIB.getInstr();
4543 
4544   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4545       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4546       .addMemOperand(MMO);
4547   MIB->setDebugLoc(DL);
4548   MIB->setDesc(TII.get(X86::MOV64rm));
4549   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4550 }
4551 
4552 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4553   MachineBasicBlock &MBB = *MIB->getParent();
4554   MachineFunction &MF = *MBB.getParent();
4555   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4556   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4557   unsigned XorOp =
4558       MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4559   MIB->setDesc(TII.get(XorOp));
4560   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4561   return true;
4562 }
4563 
4564 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4565 // but not VLX. If it uses an extended register we need to use an instruction
4566 // that loads the lower 128/256-bit, but is available with only AVX512F.
4567 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4568                             const TargetRegisterInfo *TRI,
4569                             const MCInstrDesc &LoadDesc,
4570                             const MCInstrDesc &BroadcastDesc,
4571                             unsigned SubIdx) {
4572   Register DestReg = MIB.getReg(0);
4573   // Check if DestReg is XMM16-31 or YMM16-31.
4574   if (TRI->getEncodingValue(DestReg) < 16) {
4575     // We can use a normal VEX encoded load.
4576     MIB->setDesc(LoadDesc);
4577   } else {
4578     // Use a 128/256-bit VBROADCAST instruction.
4579     MIB->setDesc(BroadcastDesc);
4580     // Change the destination to a 512-bit register.
4581     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4582     MIB->getOperand(0).setReg(DestReg);
4583   }
4584   return true;
4585 }
4586 
4587 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4588 // but not VLX. If it uses an extended register we need to use an instruction
4589 // that stores the lower 128/256-bit, but is available with only AVX512F.
4590 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4591                              const TargetRegisterInfo *TRI,
4592                              const MCInstrDesc &StoreDesc,
4593                              const MCInstrDesc &ExtractDesc,
4594                              unsigned SubIdx) {
4595   Register SrcReg = MIB.getReg(X86::AddrNumOperands);
4596   // Check if DestReg is XMM16-31 or YMM16-31.
4597   if (TRI->getEncodingValue(SrcReg) < 16) {
4598     // We can use a normal VEX encoded store.
4599     MIB->setDesc(StoreDesc);
4600   } else {
4601     // Use a VEXTRACTF instruction.
4602     MIB->setDesc(ExtractDesc);
4603     // Change the destination to a 512-bit register.
4604     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4605     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4606     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4607   }
4608 
4609   return true;
4610 }
4611 
4612 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4613   MIB->setDesc(Desc);
4614   int64_t ShiftAmt = MIB->getOperand(2).getImm();
4615   // Temporarily remove the immediate so we can add another source register.
4616   MIB->RemoveOperand(2);
4617   // Add the register. Don't copy the kill flag if there is one.
4618   MIB.addReg(MIB.getReg(1),
4619              getUndefRegState(MIB->getOperand(1).isUndef()));
4620   // Add back the immediate.
4621   MIB.addImm(ShiftAmt);
4622   return true;
4623 }
4624 
4625 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4626   bool HasAVX = Subtarget.hasAVX();
4627   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4628   switch (MI.getOpcode()) {
4629   case X86::MOV32r0:
4630     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4631   case X86::MOV32r1:
4632     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4633   case X86::MOV32r_1:
4634     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4635   case X86::MOV32ImmSExti8:
4636   case X86::MOV64ImmSExti8:
4637     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4638   case X86::SETB_C32r:
4639     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4640   case X86::SETB_C64r:
4641     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4642   case X86::MMX_SET0:
4643     return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4644   case X86::V_SET0:
4645   case X86::FsFLD0SS:
4646   case X86::FsFLD0SD:
4647   case X86::FsFLD0F128:
4648     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4649   case X86::AVX_SET0: {
4650     assert(HasAVX && "AVX not supported");
4651     const TargetRegisterInfo *TRI = &getRegisterInfo();
4652     Register SrcReg = MIB.getReg(0);
4653     Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4654     MIB->getOperand(0).setReg(XReg);
4655     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4656     MIB.addReg(SrcReg, RegState::ImplicitDefine);
4657     return true;
4658   }
4659   case X86::AVX512_128_SET0:
4660   case X86::AVX512_FsFLD0SS:
4661   case X86::AVX512_FsFLD0SD:
4662   case X86::AVX512_FsFLD0F128: {
4663     bool HasVLX = Subtarget.hasVLX();
4664     Register SrcReg = MIB.getReg(0);
4665     const TargetRegisterInfo *TRI = &getRegisterInfo();
4666     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4667       return Expand2AddrUndef(MIB,
4668                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4669     // Extended register without VLX. Use a larger XOR.
4670     SrcReg =
4671         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4672     MIB->getOperand(0).setReg(SrcReg);
4673     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4674   }
4675   case X86::AVX512_256_SET0:
4676   case X86::AVX512_512_SET0: {
4677     bool HasVLX = Subtarget.hasVLX();
4678     Register SrcReg = MIB.getReg(0);
4679     const TargetRegisterInfo *TRI = &getRegisterInfo();
4680     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4681       Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4682       MIB->getOperand(0).setReg(XReg);
4683       Expand2AddrUndef(MIB,
4684                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4685       MIB.addReg(SrcReg, RegState::ImplicitDefine);
4686       return true;
4687     }
4688     if (MI.getOpcode() == X86::AVX512_256_SET0) {
4689       // No VLX so we must reference a zmm.
4690       unsigned ZReg =
4691         TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4692       MIB->getOperand(0).setReg(ZReg);
4693     }
4694     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4695   }
4696   case X86::V_SETALLONES:
4697     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4698   case X86::AVX2_SETALLONES:
4699     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4700   case X86::AVX1_SETALLONES: {
4701     Register Reg = MIB.getReg(0);
4702     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4703     MIB->setDesc(get(X86::VCMPPSYrri));
4704     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4705     return true;
4706   }
4707   case X86::AVX512_512_SETALLONES: {
4708     Register Reg = MIB.getReg(0);
4709     MIB->setDesc(get(X86::VPTERNLOGDZrri));
4710     // VPTERNLOGD needs 3 register inputs and an immediate.
4711     // 0xff will return 1s for any input.
4712     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4713        .addReg(Reg, RegState::Undef).addImm(0xff);
4714     return true;
4715   }
4716   case X86::AVX512_512_SEXT_MASK_32:
4717   case X86::AVX512_512_SEXT_MASK_64: {
4718     Register Reg = MIB.getReg(0);
4719     Register MaskReg = MIB.getReg(1);
4720     unsigned MaskState = getRegState(MIB->getOperand(1));
4721     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4722                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4723     MI.RemoveOperand(1);
4724     MIB->setDesc(get(Opc));
4725     // VPTERNLOG needs 3 register inputs and an immediate.
4726     // 0xff will return 1s for any input.
4727     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4728        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4729     return true;
4730   }
4731   case X86::VMOVAPSZ128rm_NOVLX:
4732     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4733                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4734   case X86::VMOVUPSZ128rm_NOVLX:
4735     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4736                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4737   case X86::VMOVAPSZ256rm_NOVLX:
4738     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4739                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4740   case X86::VMOVUPSZ256rm_NOVLX:
4741     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4742                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4743   case X86::VMOVAPSZ128mr_NOVLX:
4744     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4745                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4746   case X86::VMOVUPSZ128mr_NOVLX:
4747     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4748                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4749   case X86::VMOVAPSZ256mr_NOVLX:
4750     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4751                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4752   case X86::VMOVUPSZ256mr_NOVLX:
4753     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4754                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4755   case X86::MOV32ri64: {
4756     Register Reg = MIB.getReg(0);
4757     Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4758     MI.setDesc(get(X86::MOV32ri));
4759     MIB->getOperand(0).setReg(Reg32);
4760     MIB.addReg(Reg, RegState::ImplicitDefine);
4761     return true;
4762   }
4763 
4764   // KNL does not recognize dependency-breaking idioms for mask registers,
4765   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4766   // Using %k0 as the undef input register is a performance heuristic based
4767   // on the assumption that %k0 is used less frequently than the other mask
4768   // registers, since it is not usable as a write mask.
4769   // FIXME: A more advanced approach would be to choose the best input mask
4770   // register based on context.
4771   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4772   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4773   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4774   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4775   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4776   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4777   case TargetOpcode::LOAD_STACK_GUARD:
4778     expandLoadStackGuard(MIB, *this);
4779     return true;
4780   case X86::XOR64_FP:
4781   case X86::XOR32_FP:
4782     return expandXorFP(MIB, *this);
4783   case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4784   case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4785   case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4786   case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4787   case X86::ADD8rr_DB:    MIB->setDesc(get(X86::OR8rr));    break;
4788   case X86::ADD16rr_DB:   MIB->setDesc(get(X86::OR16rr));   break;
4789   case X86::ADD32rr_DB:   MIB->setDesc(get(X86::OR32rr));   break;
4790   case X86::ADD64rr_DB:   MIB->setDesc(get(X86::OR64rr));   break;
4791   case X86::ADD8ri_DB:    MIB->setDesc(get(X86::OR8ri));    break;
4792   case X86::ADD16ri_DB:   MIB->setDesc(get(X86::OR16ri));   break;
4793   case X86::ADD32ri_DB:   MIB->setDesc(get(X86::OR32ri));   break;
4794   case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4795   case X86::ADD16ri8_DB:  MIB->setDesc(get(X86::OR16ri8));  break;
4796   case X86::ADD32ri8_DB:  MIB->setDesc(get(X86::OR32ri8));  break;
4797   case X86::ADD64ri8_DB:  MIB->setDesc(get(X86::OR64ri8));  break;
4798   }
4799   return false;
4800 }
4801 
4802 /// Return true for all instructions that only update
4803 /// the first 32 or 64-bits of the destination register and leave the rest
4804 /// unmodified. This can be used to avoid folding loads if the instructions
4805 /// only update part of the destination register, and the non-updated part is
4806 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4807 /// instructions breaks the partial register dependency and it can improve
4808 /// performance. e.g.:
4809 ///
4810 ///   movss (%rdi), %xmm0
4811 ///   cvtss2sd %xmm0, %xmm0
4812 ///
4813 /// Instead of
4814 ///   cvtss2sd (%rdi), %xmm0
4815 ///
4816 /// FIXME: This should be turned into a TSFlags.
4817 ///
4818 static bool hasPartialRegUpdate(unsigned Opcode,
4819                                 const X86Subtarget &Subtarget,
4820                                 bool ForLoadFold = false) {
4821   switch (Opcode) {
4822   case X86::CVTSI2SSrr:
4823   case X86::CVTSI2SSrm:
4824   case X86::CVTSI642SSrr:
4825   case X86::CVTSI642SSrm:
4826   case X86::CVTSI2SDrr:
4827   case X86::CVTSI2SDrm:
4828   case X86::CVTSI642SDrr:
4829   case X86::CVTSI642SDrm:
4830     // Load folding won't effect the undef register update since the input is
4831     // a GPR.
4832     return !ForLoadFold;
4833   case X86::CVTSD2SSrr:
4834   case X86::CVTSD2SSrm:
4835   case X86::CVTSS2SDrr:
4836   case X86::CVTSS2SDrm:
4837   case X86::MOVHPDrm:
4838   case X86::MOVHPSrm:
4839   case X86::MOVLPDrm:
4840   case X86::MOVLPSrm:
4841   case X86::RCPSSr:
4842   case X86::RCPSSm:
4843   case X86::RCPSSr_Int:
4844   case X86::RCPSSm_Int:
4845   case X86::ROUNDSDr:
4846   case X86::ROUNDSDm:
4847   case X86::ROUNDSSr:
4848   case X86::ROUNDSSm:
4849   case X86::RSQRTSSr:
4850   case X86::RSQRTSSm:
4851   case X86::RSQRTSSr_Int:
4852   case X86::RSQRTSSm_Int:
4853   case X86::SQRTSSr:
4854   case X86::SQRTSSm:
4855   case X86::SQRTSSr_Int:
4856   case X86::SQRTSSm_Int:
4857   case X86::SQRTSDr:
4858   case X86::SQRTSDm:
4859   case X86::SQRTSDr_Int:
4860   case X86::SQRTSDm_Int:
4861     return true;
4862   // GPR
4863   case X86::POPCNT32rm:
4864   case X86::POPCNT32rr:
4865   case X86::POPCNT64rm:
4866   case X86::POPCNT64rr:
4867     return Subtarget.hasPOPCNTFalseDeps();
4868   case X86::LZCNT32rm:
4869   case X86::LZCNT32rr:
4870   case X86::LZCNT64rm:
4871   case X86::LZCNT64rr:
4872   case X86::TZCNT32rm:
4873   case X86::TZCNT32rr:
4874   case X86::TZCNT64rm:
4875   case X86::TZCNT64rr:
4876     return Subtarget.hasLZCNTFalseDeps();
4877   }
4878 
4879   return false;
4880 }
4881 
4882 /// Inform the BreakFalseDeps pass how many idle
4883 /// instructions we would like before a partial register update.
4884 unsigned X86InstrInfo::getPartialRegUpdateClearance(
4885     const MachineInstr &MI, unsigned OpNum,
4886     const TargetRegisterInfo *TRI) const {
4887   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4888     return 0;
4889 
4890   // If MI is marked as reading Reg, the partial register update is wanted.
4891   const MachineOperand &MO = MI.getOperand(0);
4892   Register Reg = MO.getReg();
4893   if (Register::isVirtualRegister(Reg)) {
4894     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4895       return 0;
4896   } else {
4897     if (MI.readsRegister(Reg, TRI))
4898       return 0;
4899   }
4900 
4901   // If any instructions in the clearance range are reading Reg, insert a
4902   // dependency breaking instruction, which is inexpensive and is likely to
4903   // be hidden in other instruction's cycles.
4904   return PartialRegUpdateClearance;
4905 }
4906 
4907 // Return true for any instruction the copies the high bits of the first source
4908 // operand into the unused high bits of the destination operand.
4909 // Also returns true for instructions that have two inputs where one may
4910 // be undef and we want it to use the same register as the other input.
4911 static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
4912                               bool ForLoadFold = false) {
4913   // Set the OpNum parameter to the first source operand.
4914   switch (Opcode) {
4915   case X86::MMX_PUNPCKHBWirr:
4916   case X86::MMX_PUNPCKHWDirr:
4917   case X86::MMX_PUNPCKHDQirr:
4918   case X86::MMX_PUNPCKLBWirr:
4919   case X86::MMX_PUNPCKLWDirr:
4920   case X86::MMX_PUNPCKLDQirr:
4921   case X86::MOVHLPSrr:
4922   case X86::PACKSSWBrr:
4923   case X86::PACKUSWBrr:
4924   case X86::PACKSSDWrr:
4925   case X86::PACKUSDWrr:
4926   case X86::PUNPCKHBWrr:
4927   case X86::PUNPCKLBWrr:
4928   case X86::PUNPCKHWDrr:
4929   case X86::PUNPCKLWDrr:
4930   case X86::PUNPCKHDQrr:
4931   case X86::PUNPCKLDQrr:
4932   case X86::PUNPCKHQDQrr:
4933   case X86::PUNPCKLQDQrr:
4934   case X86::SHUFPDrri:
4935   case X86::SHUFPSrri:
4936     // These instructions are sometimes used with an undef first or second
4937     // source. Return true here so BreakFalseDeps will assign this source to the
4938     // same register as the first source to avoid a false dependency.
4939     // Operand 1 of these instructions is tied so they're separate from their
4940     // VEX counterparts.
4941     return OpNum == 2 && !ForLoadFold;
4942 
4943   case X86::VMOVLHPSrr:
4944   case X86::VMOVLHPSZrr:
4945   case X86::VPACKSSWBrr:
4946   case X86::VPACKUSWBrr:
4947   case X86::VPACKSSDWrr:
4948   case X86::VPACKUSDWrr:
4949   case X86::VPACKSSWBZ128rr:
4950   case X86::VPACKUSWBZ128rr:
4951   case X86::VPACKSSDWZ128rr:
4952   case X86::VPACKUSDWZ128rr:
4953   case X86::VPERM2F128rr:
4954   case X86::VPERM2I128rr:
4955   case X86::VSHUFF32X4Z256rri:
4956   case X86::VSHUFF32X4Zrri:
4957   case X86::VSHUFF64X2Z256rri:
4958   case X86::VSHUFF64X2Zrri:
4959   case X86::VSHUFI32X4Z256rri:
4960   case X86::VSHUFI32X4Zrri:
4961   case X86::VSHUFI64X2Z256rri:
4962   case X86::VSHUFI64X2Zrri:
4963   case X86::VPUNPCKHBWrr:
4964   case X86::VPUNPCKLBWrr:
4965   case X86::VPUNPCKHBWYrr:
4966   case X86::VPUNPCKLBWYrr:
4967   case X86::VPUNPCKHBWZ128rr:
4968   case X86::VPUNPCKLBWZ128rr:
4969   case X86::VPUNPCKHBWZ256rr:
4970   case X86::VPUNPCKLBWZ256rr:
4971   case X86::VPUNPCKHBWZrr:
4972   case X86::VPUNPCKLBWZrr:
4973   case X86::VPUNPCKHWDrr:
4974   case X86::VPUNPCKLWDrr:
4975   case X86::VPUNPCKHWDYrr:
4976   case X86::VPUNPCKLWDYrr:
4977   case X86::VPUNPCKHWDZ128rr:
4978   case X86::VPUNPCKLWDZ128rr:
4979   case X86::VPUNPCKHWDZ256rr:
4980   case X86::VPUNPCKLWDZ256rr:
4981   case X86::VPUNPCKHWDZrr:
4982   case X86::VPUNPCKLWDZrr:
4983   case X86::VPUNPCKHDQrr:
4984   case X86::VPUNPCKLDQrr:
4985   case X86::VPUNPCKHDQYrr:
4986   case X86::VPUNPCKLDQYrr:
4987   case X86::VPUNPCKHDQZ128rr:
4988   case X86::VPUNPCKLDQZ128rr:
4989   case X86::VPUNPCKHDQZ256rr:
4990   case X86::VPUNPCKLDQZ256rr:
4991   case X86::VPUNPCKHDQZrr:
4992   case X86::VPUNPCKLDQZrr:
4993   case X86::VPUNPCKHQDQrr:
4994   case X86::VPUNPCKLQDQrr:
4995   case X86::VPUNPCKHQDQYrr:
4996   case X86::VPUNPCKLQDQYrr:
4997   case X86::VPUNPCKHQDQZ128rr:
4998   case X86::VPUNPCKLQDQZ128rr:
4999   case X86::VPUNPCKHQDQZ256rr:
5000   case X86::VPUNPCKLQDQZ256rr:
5001   case X86::VPUNPCKHQDQZrr:
5002   case X86::VPUNPCKLQDQZrr:
5003     // These instructions are sometimes used with an undef first or second
5004     // source. Return true here so BreakFalseDeps will assign this source to the
5005     // same register as the first source to avoid a false dependency.
5006     return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
5007 
5008   case X86::VCVTSI2SSrr:
5009   case X86::VCVTSI2SSrm:
5010   case X86::VCVTSI2SSrr_Int:
5011   case X86::VCVTSI2SSrm_Int:
5012   case X86::VCVTSI642SSrr:
5013   case X86::VCVTSI642SSrm:
5014   case X86::VCVTSI642SSrr_Int:
5015   case X86::VCVTSI642SSrm_Int:
5016   case X86::VCVTSI2SDrr:
5017   case X86::VCVTSI2SDrm:
5018   case X86::VCVTSI2SDrr_Int:
5019   case X86::VCVTSI2SDrm_Int:
5020   case X86::VCVTSI642SDrr:
5021   case X86::VCVTSI642SDrm:
5022   case X86::VCVTSI642SDrr_Int:
5023   case X86::VCVTSI642SDrm_Int:
5024   // AVX-512
5025   case X86::VCVTSI2SSZrr:
5026   case X86::VCVTSI2SSZrm:
5027   case X86::VCVTSI2SSZrr_Int:
5028   case X86::VCVTSI2SSZrrb_Int:
5029   case X86::VCVTSI2SSZrm_Int:
5030   case X86::VCVTSI642SSZrr:
5031   case X86::VCVTSI642SSZrm:
5032   case X86::VCVTSI642SSZrr_Int:
5033   case X86::VCVTSI642SSZrrb_Int:
5034   case X86::VCVTSI642SSZrm_Int:
5035   case X86::VCVTSI2SDZrr:
5036   case X86::VCVTSI2SDZrm:
5037   case X86::VCVTSI2SDZrr_Int:
5038   case X86::VCVTSI2SDZrm_Int:
5039   case X86::VCVTSI642SDZrr:
5040   case X86::VCVTSI642SDZrm:
5041   case X86::VCVTSI642SDZrr_Int:
5042   case X86::VCVTSI642SDZrrb_Int:
5043   case X86::VCVTSI642SDZrm_Int:
5044   case X86::VCVTUSI2SSZrr:
5045   case X86::VCVTUSI2SSZrm:
5046   case X86::VCVTUSI2SSZrr_Int:
5047   case X86::VCVTUSI2SSZrrb_Int:
5048   case X86::VCVTUSI2SSZrm_Int:
5049   case X86::VCVTUSI642SSZrr:
5050   case X86::VCVTUSI642SSZrm:
5051   case X86::VCVTUSI642SSZrr_Int:
5052   case X86::VCVTUSI642SSZrrb_Int:
5053   case X86::VCVTUSI642SSZrm_Int:
5054   case X86::VCVTUSI2SDZrr:
5055   case X86::VCVTUSI2SDZrm:
5056   case X86::VCVTUSI2SDZrr_Int:
5057   case X86::VCVTUSI2SDZrm_Int:
5058   case X86::VCVTUSI642SDZrr:
5059   case X86::VCVTUSI642SDZrm:
5060   case X86::VCVTUSI642SDZrr_Int:
5061   case X86::VCVTUSI642SDZrrb_Int:
5062   case X86::VCVTUSI642SDZrm_Int:
5063     // Load folding won't effect the undef register update since the input is
5064     // a GPR.
5065     return OpNum == 1 && !ForLoadFold;
5066   case X86::VCVTSD2SSrr:
5067   case X86::VCVTSD2SSrm:
5068   case X86::VCVTSD2SSrr_Int:
5069   case X86::VCVTSD2SSrm_Int:
5070   case X86::VCVTSS2SDrr:
5071   case X86::VCVTSS2SDrm:
5072   case X86::VCVTSS2SDrr_Int:
5073   case X86::VCVTSS2SDrm_Int:
5074   case X86::VRCPSSr:
5075   case X86::VRCPSSr_Int:
5076   case X86::VRCPSSm:
5077   case X86::VRCPSSm_Int:
5078   case X86::VROUNDSDr:
5079   case X86::VROUNDSDm:
5080   case X86::VROUNDSDr_Int:
5081   case X86::VROUNDSDm_Int:
5082   case X86::VROUNDSSr:
5083   case X86::VROUNDSSm:
5084   case X86::VROUNDSSr_Int:
5085   case X86::VROUNDSSm_Int:
5086   case X86::VRSQRTSSr:
5087   case X86::VRSQRTSSr_Int:
5088   case X86::VRSQRTSSm:
5089   case X86::VRSQRTSSm_Int:
5090   case X86::VSQRTSSr:
5091   case X86::VSQRTSSr_Int:
5092   case X86::VSQRTSSm:
5093   case X86::VSQRTSSm_Int:
5094   case X86::VSQRTSDr:
5095   case X86::VSQRTSDr_Int:
5096   case X86::VSQRTSDm:
5097   case X86::VSQRTSDm_Int:
5098   // AVX-512
5099   case X86::VCVTSD2SSZrr:
5100   case X86::VCVTSD2SSZrr_Int:
5101   case X86::VCVTSD2SSZrrb_Int:
5102   case X86::VCVTSD2SSZrm:
5103   case X86::VCVTSD2SSZrm_Int:
5104   case X86::VCVTSS2SDZrr:
5105   case X86::VCVTSS2SDZrr_Int:
5106   case X86::VCVTSS2SDZrrb_Int:
5107   case X86::VCVTSS2SDZrm:
5108   case X86::VCVTSS2SDZrm_Int:
5109   case X86::VGETEXPSDZr:
5110   case X86::VGETEXPSDZrb:
5111   case X86::VGETEXPSDZm:
5112   case X86::VGETEXPSSZr:
5113   case X86::VGETEXPSSZrb:
5114   case X86::VGETEXPSSZm:
5115   case X86::VGETMANTSDZrri:
5116   case X86::VGETMANTSDZrrib:
5117   case X86::VGETMANTSDZrmi:
5118   case X86::VGETMANTSSZrri:
5119   case X86::VGETMANTSSZrrib:
5120   case X86::VGETMANTSSZrmi:
5121   case X86::VRNDSCALESDZr:
5122   case X86::VRNDSCALESDZr_Int:
5123   case X86::VRNDSCALESDZrb_Int:
5124   case X86::VRNDSCALESDZm:
5125   case X86::VRNDSCALESDZm_Int:
5126   case X86::VRNDSCALESSZr:
5127   case X86::VRNDSCALESSZr_Int:
5128   case X86::VRNDSCALESSZrb_Int:
5129   case X86::VRNDSCALESSZm:
5130   case X86::VRNDSCALESSZm_Int:
5131   case X86::VRCP14SDZrr:
5132   case X86::VRCP14SDZrm:
5133   case X86::VRCP14SSZrr:
5134   case X86::VRCP14SSZrm:
5135   case X86::VRCP28SDZr:
5136   case X86::VRCP28SDZrb:
5137   case X86::VRCP28SDZm:
5138   case X86::VRCP28SSZr:
5139   case X86::VRCP28SSZrb:
5140   case X86::VRCP28SSZm:
5141   case X86::VREDUCESSZrmi:
5142   case X86::VREDUCESSZrri:
5143   case X86::VREDUCESSZrrib:
5144   case X86::VRSQRT14SDZrr:
5145   case X86::VRSQRT14SDZrm:
5146   case X86::VRSQRT14SSZrr:
5147   case X86::VRSQRT14SSZrm:
5148   case X86::VRSQRT28SDZr:
5149   case X86::VRSQRT28SDZrb:
5150   case X86::VRSQRT28SDZm:
5151   case X86::VRSQRT28SSZr:
5152   case X86::VRSQRT28SSZrb:
5153   case X86::VRSQRT28SSZm:
5154   case X86::VSQRTSSZr:
5155   case X86::VSQRTSSZr_Int:
5156   case X86::VSQRTSSZrb_Int:
5157   case X86::VSQRTSSZm:
5158   case X86::VSQRTSSZm_Int:
5159   case X86::VSQRTSDZr:
5160   case X86::VSQRTSDZr_Int:
5161   case X86::VSQRTSDZrb_Int:
5162   case X86::VSQRTSDZm:
5163   case X86::VSQRTSDZm_Int:
5164     return OpNum == 1;
5165   case X86::VMOVSSZrrk:
5166   case X86::VMOVSDZrrk:
5167     return OpNum == 3 && !ForLoadFold;
5168   case X86::VMOVSSZrrkz:
5169   case X86::VMOVSDZrrkz:
5170     return OpNum == 2 && !ForLoadFold;
5171   }
5172 
5173   return false;
5174 }
5175 
5176 /// Inform the BreakFalseDeps pass how many idle instructions we would like
5177 /// before certain undef register reads.
5178 ///
5179 /// This catches the VCVTSI2SD family of instructions:
5180 ///
5181 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
5182 ///
5183 /// We should to be careful *not* to catch VXOR idioms which are presumably
5184 /// handled specially in the pipeline:
5185 ///
5186 /// vxorps undef %xmm1, undef %xmm1, %xmm1
5187 ///
5188 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5189 /// high bits that are passed-through are not live.
5190 unsigned
5191 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
5192                                    const TargetRegisterInfo *TRI) const {
5193   const MachineOperand &MO = MI.getOperand(OpNum);
5194   if (Register::isPhysicalRegister(MO.getReg()) &&
5195       hasUndefRegUpdate(MI.getOpcode(), OpNum))
5196     return UndefRegClearance;
5197 
5198   return 0;
5199 }
5200 
5201 void X86InstrInfo::breakPartialRegDependency(
5202     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5203   Register Reg = MI.getOperand(OpNum).getReg();
5204   // If MI kills this register, the false dependence is already broken.
5205   if (MI.killsRegister(Reg, TRI))
5206     return;
5207 
5208   if (X86::VR128RegClass.contains(Reg)) {
5209     // These instructions are all floating point domain, so xorps is the best
5210     // choice.
5211     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
5212     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
5213         .addReg(Reg, RegState::Undef)
5214         .addReg(Reg, RegState::Undef);
5215     MI.addRegisterKilled(Reg, TRI, true);
5216   } else if (X86::VR256RegClass.contains(Reg)) {
5217     // Use vxorps to clear the full ymm register.
5218     // It wants to read and write the xmm sub-register.
5219     Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5220     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
5221         .addReg(XReg, RegState::Undef)
5222         .addReg(XReg, RegState::Undef)
5223         .addReg(Reg, RegState::ImplicitDefine);
5224     MI.addRegisterKilled(Reg, TRI, true);
5225   } else if (X86::GR64RegClass.contains(Reg)) {
5226     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
5227     // as well.
5228     Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
5229     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
5230         .addReg(XReg, RegState::Undef)
5231         .addReg(XReg, RegState::Undef)
5232         .addReg(Reg, RegState::ImplicitDefine);
5233     MI.addRegisterKilled(Reg, TRI, true);
5234   } else if (X86::GR32RegClass.contains(Reg)) {
5235     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
5236         .addReg(Reg, RegState::Undef)
5237         .addReg(Reg, RegState::Undef);
5238     MI.addRegisterKilled(Reg, TRI, true);
5239   }
5240 }
5241 
5242 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5243                         int PtrOffset = 0) {
5244   unsigned NumAddrOps = MOs.size();
5245 
5246   if (NumAddrOps < 4) {
5247     // FrameIndex only - add an immediate offset (whether its zero or not).
5248     for (unsigned i = 0; i != NumAddrOps; ++i)
5249       MIB.add(MOs[i]);
5250     addOffset(MIB, PtrOffset);
5251   } else {
5252     // General Memory Addressing - we need to add any offset to an existing
5253     // offset.
5254     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5255     for (unsigned i = 0; i != NumAddrOps; ++i) {
5256       const MachineOperand &MO = MOs[i];
5257       if (i == 3 && PtrOffset != 0) {
5258         MIB.addDisp(MO, PtrOffset);
5259       } else {
5260         MIB.add(MO);
5261       }
5262     }
5263   }
5264 }
5265 
5266 static void updateOperandRegConstraints(MachineFunction &MF,
5267                                         MachineInstr &NewMI,
5268                                         const TargetInstrInfo &TII) {
5269   MachineRegisterInfo &MRI = MF.getRegInfo();
5270   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
5271 
5272   for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
5273     MachineOperand &MO = NewMI.getOperand(Idx);
5274     // We only need to update constraints on virtual register operands.
5275     if (!MO.isReg())
5276       continue;
5277     Register Reg = MO.getReg();
5278     if (!Register::isVirtualRegister(Reg))
5279       continue;
5280 
5281     auto *NewRC = MRI.constrainRegClass(
5282         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
5283     if (!NewRC) {
5284       LLVM_DEBUG(
5285           dbgs() << "WARNING: Unable to update register constraint for operand "
5286                  << Idx << " of instruction:\n";
5287           NewMI.dump(); dbgs() << "\n");
5288     }
5289   }
5290 }
5291 
5292 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5293                                      ArrayRef<MachineOperand> MOs,
5294                                      MachineBasicBlock::iterator InsertPt,
5295                                      MachineInstr &MI,
5296                                      const TargetInstrInfo &TII) {
5297   // Create the base instruction with the memory operand as the first part.
5298   // Omit the implicit operands, something BuildMI can't do.
5299   MachineInstr *NewMI =
5300       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5301   MachineInstrBuilder MIB(MF, NewMI);
5302   addOperands(MIB, MOs);
5303 
5304   // Loop over the rest of the ri operands, converting them over.
5305   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5306   for (unsigned i = 0; i != NumOps; ++i) {
5307     MachineOperand &MO = MI.getOperand(i + 2);
5308     MIB.add(MO);
5309   }
5310   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5311     MachineOperand &MO = MI.getOperand(i);
5312     MIB.add(MO);
5313   }
5314 
5315   updateOperandRegConstraints(MF, *NewMI, TII);
5316 
5317   MachineBasicBlock *MBB = InsertPt->getParent();
5318   MBB->insert(InsertPt, NewMI);
5319 
5320   return MIB;
5321 }
5322 
5323 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5324                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5325                               MachineBasicBlock::iterator InsertPt,
5326                               MachineInstr &MI, const TargetInstrInfo &TII,
5327                               int PtrOffset = 0) {
5328   // Omit the implicit operands, something BuildMI can't do.
5329   MachineInstr *NewMI =
5330       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5331   MachineInstrBuilder MIB(MF, NewMI);
5332 
5333   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5334     MachineOperand &MO = MI.getOperand(i);
5335     if (i == OpNo) {
5336       assert(MO.isReg() && "Expected to fold into reg operand!");
5337       addOperands(MIB, MOs, PtrOffset);
5338     } else {
5339       MIB.add(MO);
5340     }
5341   }
5342 
5343   updateOperandRegConstraints(MF, *NewMI, TII);
5344 
5345   // Copy the NoFPExcept flag from the instruction we're fusing.
5346   if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
5347     NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
5348 
5349   MachineBasicBlock *MBB = InsertPt->getParent();
5350   MBB->insert(InsertPt, NewMI);
5351 
5352   return MIB;
5353 }
5354 
5355 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5356                                 ArrayRef<MachineOperand> MOs,
5357                                 MachineBasicBlock::iterator InsertPt,
5358                                 MachineInstr &MI) {
5359   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5360                                     MI.getDebugLoc(), TII.get(Opcode));
5361   addOperands(MIB, MOs);
5362   return MIB.addImm(0);
5363 }
5364 
5365 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5366     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5367     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5368     unsigned Size, Align Alignment) const {
5369   switch (MI.getOpcode()) {
5370   case X86::INSERTPSrr:
5371   case X86::VINSERTPSrr:
5372   case X86::VINSERTPSZrr:
5373     // Attempt to convert the load of inserted vector into a fold load
5374     // of a single float.
5375     if (OpNum == 2) {
5376       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5377       unsigned ZMask = Imm & 15;
5378       unsigned DstIdx = (Imm >> 4) & 3;
5379       unsigned SrcIdx = (Imm >> 6) & 3;
5380 
5381       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5382       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5383       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5384       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(4)) {
5385         int PtrOffset = SrcIdx * 4;
5386         unsigned NewImm = (DstIdx << 4) | ZMask;
5387         unsigned NewOpCode =
5388             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5389             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
5390                                                     X86::INSERTPSrm;
5391         MachineInstr *NewMI =
5392             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5393         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5394         return NewMI;
5395       }
5396     }
5397     break;
5398   case X86::MOVHLPSrr:
5399   case X86::VMOVHLPSrr:
5400   case X86::VMOVHLPSZrr:
5401     // Move the upper 64-bits of the second operand to the lower 64-bits.
5402     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5403     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5404     if (OpNum == 2) {
5405       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5406       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5407       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5408       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
5409         unsigned NewOpCode =
5410             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5411             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
5412                                                    X86::MOVLPSrm;
5413         MachineInstr *NewMI =
5414             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5415         return NewMI;
5416       }
5417     }
5418     break;
5419   case X86::UNPCKLPDrr:
5420     // If we won't be able to fold this to the memory form of UNPCKL, use
5421     // MOVHPD instead. Done as custom because we can't have this in the load
5422     // table twice.
5423     if (OpNum == 2) {
5424       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5425       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5426       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5427       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
5428         MachineInstr *NewMI =
5429             FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
5430         return NewMI;
5431       }
5432     }
5433     break;
5434   }
5435 
5436   return nullptr;
5437 }
5438 
5439 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
5440                                                MachineInstr &MI) {
5441   if (!hasUndefRegUpdate(MI.getOpcode(), 1, /*ForLoadFold*/true) ||
5442       !MI.getOperand(1).isReg())
5443     return false;
5444 
5445   // The are two cases we need to handle depending on where in the pipeline
5446   // the folding attempt is being made.
5447   // -Register has the undef flag set.
5448   // -Register is produced by the IMPLICIT_DEF instruction.
5449 
5450   if (MI.getOperand(1).isUndef())
5451     return true;
5452 
5453   MachineRegisterInfo &RegInfo = MF.getRegInfo();
5454   MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
5455   return VRegDef && VRegDef->isImplicitDef();
5456 }
5457 
5458 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5459     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5460     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5461     unsigned Size, Align Alignment, bool AllowCommute) const {
5462   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
5463   bool isTwoAddrFold = false;
5464 
5465   // For CPUs that favor the register form of a call or push,
5466   // do not fold loads into calls or pushes, unless optimizing for size
5467   // aggressively.
5468   if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
5469       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5470        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5471        MI.getOpcode() == X86::PUSH64r))
5472     return nullptr;
5473 
5474   // Avoid partial and undef register update stalls unless optimizing for size.
5475   if (!MF.getFunction().hasOptSize() &&
5476       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5477        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5478     return nullptr;
5479 
5480   unsigned NumOps = MI.getDesc().getNumOperands();
5481   bool isTwoAddr =
5482       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5483 
5484   // FIXME: AsmPrinter doesn't know how to handle
5485   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5486   if (MI.getOpcode() == X86::ADD32ri &&
5487       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5488     return nullptr;
5489 
5490   // GOTTPOFF relocation loads can only be folded into add instructions.
5491   // FIXME: Need to exclude other relocations that only support specific
5492   // instructions.
5493   if (MOs.size() == X86::AddrNumOperands &&
5494       MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
5495       MI.getOpcode() != X86::ADD64rr)
5496     return nullptr;
5497 
5498   MachineInstr *NewMI = nullptr;
5499 
5500   // Attempt to fold any custom cases we have.
5501   if (MachineInstr *CustomMI = foldMemoryOperandCustom(
5502           MF, MI, OpNum, MOs, InsertPt, Size, Alignment))
5503     return CustomMI;
5504 
5505   const X86MemoryFoldTableEntry *I = nullptr;
5506 
5507   // Folding a memory location into the two-address part of a two-address
5508   // instruction is different than folding it other places.  It requires
5509   // replacing the *two* registers with the memory location.
5510   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5511       MI.getOperand(1).isReg() &&
5512       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5513     I = lookupTwoAddrFoldTable(MI.getOpcode());
5514     isTwoAddrFold = true;
5515   } else {
5516     if (OpNum == 0) {
5517       if (MI.getOpcode() == X86::MOV32r0) {
5518         NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5519         if (NewMI)
5520           return NewMI;
5521       }
5522     }
5523 
5524     I = lookupFoldTable(MI.getOpcode(), OpNum);
5525   }
5526 
5527   if (I != nullptr) {
5528     unsigned Opcode = I->DstOp;
5529     bool FoldedLoad =
5530         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_LOAD) || OpNum > 0;
5531     bool FoldedStore =
5532         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_STORE);
5533     MaybeAlign MinAlign =
5534         decodeMaybeAlign((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT);
5535     if (MinAlign && Alignment < *MinAlign)
5536       return nullptr;
5537     bool NarrowToMOV32rm = false;
5538     if (Size) {
5539       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5540       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
5541                                                   &RI, MF);
5542       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5543       // Check if it's safe to fold the load. If the size of the object is
5544       // narrower than the load width, then it's not.
5545       // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
5546       if (FoldedLoad && Size < RCSize) {
5547         // If this is a 64-bit load, but the spill slot is 32, then we can do
5548         // a 32-bit load which is implicitly zero-extended. This likely is
5549         // due to live interval analysis remat'ing a load from stack slot.
5550         if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5551           return nullptr;
5552         if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5553           return nullptr;
5554         Opcode = X86::MOV32rm;
5555         NarrowToMOV32rm = true;
5556       }
5557       // For stores, make sure the size of the object is equal to the size of
5558       // the store. If the object is larger, the extra bits would be garbage. If
5559       // the object is smaller we might overwrite another object or fault.
5560       if (FoldedStore && Size != RCSize)
5561         return nullptr;
5562     }
5563 
5564     if (isTwoAddrFold)
5565       NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5566     else
5567       NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5568 
5569     if (NarrowToMOV32rm) {
5570       // If this is the special case where we use a MOV32rm to load a 32-bit
5571       // value and zero-extend the top bits. Change the destination register
5572       // to a 32-bit one.
5573       Register DstReg = NewMI->getOperand(0).getReg();
5574       if (Register::isPhysicalRegister(DstReg))
5575         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5576       else
5577         NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5578     }
5579     return NewMI;
5580   }
5581 
5582   // If the instruction and target operand are commutable, commute the
5583   // instruction and try again.
5584   if (AllowCommute) {
5585     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5586     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5587       bool HasDef = MI.getDesc().getNumDefs();
5588       Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
5589       Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5590       Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5591       bool Tied1 =
5592           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5593       bool Tied2 =
5594           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5595 
5596       // If either of the commutable operands are tied to the destination
5597       // then we can not commute + fold.
5598       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5599           (HasDef && Reg0 == Reg2 && Tied2))
5600         return nullptr;
5601 
5602       MachineInstr *CommutedMI =
5603           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5604       if (!CommutedMI) {
5605         // Unable to commute.
5606         return nullptr;
5607       }
5608       if (CommutedMI != &MI) {
5609         // New instruction. We can't fold from this.
5610         CommutedMI->eraseFromParent();
5611         return nullptr;
5612       }
5613 
5614       // Attempt to fold with the commuted version of the instruction.
5615       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, Size,
5616                                     Alignment, /*AllowCommute=*/false);
5617       if (NewMI)
5618         return NewMI;
5619 
5620       // Folding failed again - undo the commute before returning.
5621       MachineInstr *UncommutedMI =
5622           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5623       if (!UncommutedMI) {
5624         // Unable to commute.
5625         return nullptr;
5626       }
5627       if (UncommutedMI != &MI) {
5628         // New instruction. It doesn't need to be kept.
5629         UncommutedMI->eraseFromParent();
5630         return nullptr;
5631       }
5632 
5633       // Return here to prevent duplicate fuse failure report.
5634       return nullptr;
5635     }
5636   }
5637 
5638   // No fusion
5639   if (PrintFailedFusing && !MI.isCopy())
5640     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
5641   return nullptr;
5642 }
5643 
5644 MachineInstr *
5645 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
5646                                     ArrayRef<unsigned> Ops,
5647                                     MachineBasicBlock::iterator InsertPt,
5648                                     int FrameIndex, LiveIntervals *LIS,
5649                                     VirtRegMap *VRM) const {
5650   // Check switch flag
5651   if (NoFusing)
5652     return nullptr;
5653 
5654   // Avoid partial and undef register update stalls unless optimizing for size.
5655   if (!MF.getFunction().hasOptSize() &&
5656       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5657        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5658     return nullptr;
5659 
5660   // Don't fold subreg spills, or reloads that use a high subreg.
5661   for (auto Op : Ops) {
5662     MachineOperand &MO = MI.getOperand(Op);
5663     auto SubReg = MO.getSubReg();
5664     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
5665       return nullptr;
5666   }
5667 
5668   const MachineFrameInfo &MFI = MF.getFrameInfo();
5669   unsigned Size = MFI.getObjectSize(FrameIndex);
5670   Align Alignment = MFI.getObjectAlign(FrameIndex);
5671   // If the function stack isn't realigned we don't want to fold instructions
5672   // that need increased alignment.
5673   if (!RI.needsStackRealignment(MF))
5674     Alignment =
5675         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlign());
5676   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5677     unsigned NewOpc = 0;
5678     unsigned RCSize = 0;
5679     switch (MI.getOpcode()) {
5680     default: return nullptr;
5681     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5682     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5683     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5684     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5685     }
5686     // Check if it's safe to fold the load. If the size of the object is
5687     // narrower than the load width, then it's not.
5688     if (Size < RCSize)
5689       return nullptr;
5690     // Change to CMPXXri r, 0 first.
5691     MI.setDesc(get(NewOpc));
5692     MI.getOperand(1).ChangeToImmediate(0);
5693   } else if (Ops.size() != 1)
5694     return nullptr;
5695 
5696   return foldMemoryOperandImpl(MF, MI, Ops[0],
5697                                MachineOperand::CreateFI(FrameIndex), InsertPt,
5698                                Size, Alignment, /*AllowCommute=*/true);
5699 }
5700 
5701 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5702 /// because the latter uses contents that wouldn't be defined in the folded
5703 /// version.  For instance, this transformation isn't legal:
5704 ///   movss (%rdi), %xmm0
5705 ///   addps %xmm0, %xmm0
5706 /// ->
5707 ///   addps (%rdi), %xmm0
5708 ///
5709 /// But this one is:
5710 ///   movss (%rdi), %xmm0
5711 ///   addss %xmm0, %xmm0
5712 /// ->
5713 ///   addss (%rdi), %xmm0
5714 ///
5715 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5716                                              const MachineInstr &UserMI,
5717                                              const MachineFunction &MF) {
5718   unsigned Opc = LoadMI.getOpcode();
5719   unsigned UserOpc = UserMI.getOpcode();
5720   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5721   const TargetRegisterClass *RC =
5722       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5723   unsigned RegSize = TRI.getRegSizeInBits(*RC);
5724 
5725   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
5726        Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
5727        Opc == X86::VMOVSSZrm_alt) &&
5728       RegSize > 32) {
5729     // These instructions only load 32 bits, we can't fold them if the
5730     // destination register is wider than 32 bits (4 bytes), and its user
5731     // instruction isn't scalar (SS).
5732     switch (UserOpc) {
5733     case X86::CVTSS2SDrr_Int:
5734     case X86::VCVTSS2SDrr_Int:
5735     case X86::VCVTSS2SDZrr_Int:
5736     case X86::VCVTSS2SDZrr_Intk:
5737     case X86::VCVTSS2SDZrr_Intkz:
5738     case X86::CVTSS2SIrr_Int:     case X86::CVTSS2SI64rr_Int:
5739     case X86::VCVTSS2SIrr_Int:    case X86::VCVTSS2SI64rr_Int:
5740     case X86::VCVTSS2SIZrr_Int:   case X86::VCVTSS2SI64Zrr_Int:
5741     case X86::CVTTSS2SIrr_Int:    case X86::CVTTSS2SI64rr_Int:
5742     case X86::VCVTTSS2SIrr_Int:   case X86::VCVTTSS2SI64rr_Int:
5743     case X86::VCVTTSS2SIZrr_Int:  case X86::VCVTTSS2SI64Zrr_Int:
5744     case X86::VCVTSS2USIZrr_Int:  case X86::VCVTSS2USI64Zrr_Int:
5745     case X86::VCVTTSS2USIZrr_Int: case X86::VCVTTSS2USI64Zrr_Int:
5746     case X86::RCPSSr_Int:   case X86::VRCPSSr_Int:
5747     case X86::RSQRTSSr_Int: case X86::VRSQRTSSr_Int:
5748     case X86::ROUNDSSr_Int: case X86::VROUNDSSr_Int:
5749     case X86::COMISSrr_Int: case X86::VCOMISSrr_Int: case X86::VCOMISSZrr_Int:
5750     case X86::UCOMISSrr_Int:case X86::VUCOMISSrr_Int:case X86::VUCOMISSZrr_Int:
5751     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5752     case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5753     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5754     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5755     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5756     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5757     case X86::SQRTSSr_Int: case X86::VSQRTSSr_Int: case X86::VSQRTSSZr_Int:
5758     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5759     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5760     case X86::VCMPSSZrr_Intk:
5761     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5762     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5763     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5764     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5765     case X86::VSQRTSSZr_Intk: case X86::VSQRTSSZr_Intkz:
5766     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5767     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
5768     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
5769     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
5770     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
5771     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
5772     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
5773     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
5774     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
5775     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5776     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5777     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5778     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5779     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5780     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5781     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5782     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5783     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5784     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5785     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5786     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5787     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5788     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5789     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5790     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5791     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5792     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5793     case X86::VFIXUPIMMSSZrri:
5794     case X86::VFIXUPIMMSSZrrik:
5795     case X86::VFIXUPIMMSSZrrikz:
5796     case X86::VFPCLASSSSZrr:
5797     case X86::VFPCLASSSSZrrk:
5798     case X86::VGETEXPSSZr:
5799     case X86::VGETEXPSSZrk:
5800     case X86::VGETEXPSSZrkz:
5801     case X86::VGETMANTSSZrri:
5802     case X86::VGETMANTSSZrrik:
5803     case X86::VGETMANTSSZrrikz:
5804     case X86::VRANGESSZrri:
5805     case X86::VRANGESSZrrik:
5806     case X86::VRANGESSZrrikz:
5807     case X86::VRCP14SSZrr:
5808     case X86::VRCP14SSZrrk:
5809     case X86::VRCP14SSZrrkz:
5810     case X86::VRCP28SSZr:
5811     case X86::VRCP28SSZrk:
5812     case X86::VRCP28SSZrkz:
5813     case X86::VREDUCESSZrri:
5814     case X86::VREDUCESSZrrik:
5815     case X86::VREDUCESSZrrikz:
5816     case X86::VRNDSCALESSZr_Int:
5817     case X86::VRNDSCALESSZr_Intk:
5818     case X86::VRNDSCALESSZr_Intkz:
5819     case X86::VRSQRT14SSZrr:
5820     case X86::VRSQRT14SSZrrk:
5821     case X86::VRSQRT14SSZrrkz:
5822     case X86::VRSQRT28SSZr:
5823     case X86::VRSQRT28SSZrk:
5824     case X86::VRSQRT28SSZrkz:
5825     case X86::VSCALEFSSZrr:
5826     case X86::VSCALEFSSZrrk:
5827     case X86::VSCALEFSSZrrkz:
5828       return false;
5829     default:
5830       return true;
5831     }
5832   }
5833 
5834   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
5835        Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
5836        Opc == X86::VMOVSDZrm_alt) &&
5837       RegSize > 64) {
5838     // These instructions only load 64 bits, we can't fold them if the
5839     // destination register is wider than 64 bits (8 bytes), and its user
5840     // instruction isn't scalar (SD).
5841     switch (UserOpc) {
5842     case X86::CVTSD2SSrr_Int:
5843     case X86::VCVTSD2SSrr_Int:
5844     case X86::VCVTSD2SSZrr_Int:
5845     case X86::VCVTSD2SSZrr_Intk:
5846     case X86::VCVTSD2SSZrr_Intkz:
5847     case X86::CVTSD2SIrr_Int:     case X86::CVTSD2SI64rr_Int:
5848     case X86::VCVTSD2SIrr_Int:    case X86::VCVTSD2SI64rr_Int:
5849     case X86::VCVTSD2SIZrr_Int:   case X86::VCVTSD2SI64Zrr_Int:
5850     case X86::CVTTSD2SIrr_Int:    case X86::CVTTSD2SI64rr_Int:
5851     case X86::VCVTTSD2SIrr_Int:   case X86::VCVTTSD2SI64rr_Int:
5852     case X86::VCVTTSD2SIZrr_Int:  case X86::VCVTTSD2SI64Zrr_Int:
5853     case X86::VCVTSD2USIZrr_Int:  case X86::VCVTSD2USI64Zrr_Int:
5854     case X86::VCVTTSD2USIZrr_Int: case X86::VCVTTSD2USI64Zrr_Int:
5855     case X86::ROUNDSDr_Int: case X86::VROUNDSDr_Int:
5856     case X86::COMISDrr_Int: case X86::VCOMISDrr_Int: case X86::VCOMISDZrr_Int:
5857     case X86::UCOMISDrr_Int:case X86::VUCOMISDrr_Int:case X86::VUCOMISDZrr_Int:
5858     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5859     case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5860     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5861     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
5862     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
5863     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
5864     case X86::SQRTSDr_Int: case X86::VSQRTSDr_Int: case X86::VSQRTSDZr_Int:
5865     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5866     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5867     case X86::VCMPSDZrr_Intk:
5868     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5869     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5870     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5871     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5872     case X86::VSQRTSDZr_Intk: case X86::VSQRTSDZr_Intkz:
5873     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5874     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
5875     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
5876     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
5877     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
5878     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
5879     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
5880     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
5881     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
5882     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5883     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5884     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5885     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5886     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5887     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5888     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5889     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5890     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5891     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5892     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5893     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5894     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5895     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5896     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5897     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5898     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5899     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5900     case X86::VFIXUPIMMSDZrri:
5901     case X86::VFIXUPIMMSDZrrik:
5902     case X86::VFIXUPIMMSDZrrikz:
5903     case X86::VFPCLASSSDZrr:
5904     case X86::VFPCLASSSDZrrk:
5905     case X86::VGETEXPSDZr:
5906     case X86::VGETEXPSDZrk:
5907     case X86::VGETEXPSDZrkz:
5908     case X86::VGETMANTSDZrri:
5909     case X86::VGETMANTSDZrrik:
5910     case X86::VGETMANTSDZrrikz:
5911     case X86::VRANGESDZrri:
5912     case X86::VRANGESDZrrik:
5913     case X86::VRANGESDZrrikz:
5914     case X86::VRCP14SDZrr:
5915     case X86::VRCP14SDZrrk:
5916     case X86::VRCP14SDZrrkz:
5917     case X86::VRCP28SDZr:
5918     case X86::VRCP28SDZrk:
5919     case X86::VRCP28SDZrkz:
5920     case X86::VREDUCESDZrri:
5921     case X86::VREDUCESDZrrik:
5922     case X86::VREDUCESDZrrikz:
5923     case X86::VRNDSCALESDZr_Int:
5924     case X86::VRNDSCALESDZr_Intk:
5925     case X86::VRNDSCALESDZr_Intkz:
5926     case X86::VRSQRT14SDZrr:
5927     case X86::VRSQRT14SDZrrk:
5928     case X86::VRSQRT14SDZrrkz:
5929     case X86::VRSQRT28SDZr:
5930     case X86::VRSQRT28SDZrk:
5931     case X86::VRSQRT28SDZrkz:
5932     case X86::VSCALEFSDZrr:
5933     case X86::VSCALEFSDZrrk:
5934     case X86::VSCALEFSDZrrkz:
5935       return false;
5936     default:
5937       return true;
5938     }
5939   }
5940 
5941   return false;
5942 }
5943 
5944 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5945     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
5946     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5947     LiveIntervals *LIS) const {
5948 
5949   // TODO: Support the case where LoadMI loads a wide register, but MI
5950   // only uses a subreg.
5951   for (auto Op : Ops) {
5952     if (MI.getOperand(Op).getSubReg())
5953       return nullptr;
5954   }
5955 
5956   // If loading from a FrameIndex, fold directly from the FrameIndex.
5957   unsigned NumOps = LoadMI.getDesc().getNumOperands();
5958   int FrameIndex;
5959   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5960     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5961       return nullptr;
5962     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5963   }
5964 
5965   // Check switch flag
5966   if (NoFusing) return nullptr;
5967 
5968   // Avoid partial and undef register update stalls unless optimizing for size.
5969   if (!MF.getFunction().hasOptSize() &&
5970       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5971        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5972     return nullptr;
5973 
5974   // Determine the alignment of the load.
5975   Align Alignment;
5976   if (LoadMI.hasOneMemOperand())
5977     Alignment = (*LoadMI.memoperands_begin())->getAlign();
5978   else
5979     switch (LoadMI.getOpcode()) {
5980     case X86::AVX512_512_SET0:
5981     case X86::AVX512_512_SETALLONES:
5982       Alignment = Align(64);
5983       break;
5984     case X86::AVX2_SETALLONES:
5985     case X86::AVX1_SETALLONES:
5986     case X86::AVX_SET0:
5987     case X86::AVX512_256_SET0:
5988       Alignment = Align(32);
5989       break;
5990     case X86::V_SET0:
5991     case X86::V_SETALLONES:
5992     case X86::AVX512_128_SET0:
5993     case X86::FsFLD0F128:
5994     case X86::AVX512_FsFLD0F128:
5995       Alignment = Align(16);
5996       break;
5997     case X86::MMX_SET0:
5998     case X86::FsFLD0SD:
5999     case X86::AVX512_FsFLD0SD:
6000       Alignment = Align(8);
6001       break;
6002     case X86::FsFLD0SS:
6003     case X86::AVX512_FsFLD0SS:
6004       Alignment = Align(4);
6005       break;
6006     default:
6007       return nullptr;
6008     }
6009   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6010     unsigned NewOpc = 0;
6011     switch (MI.getOpcode()) {
6012     default: return nullptr;
6013     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6014     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6015     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6016     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6017     }
6018     // Change to CMPXXri r, 0 first.
6019     MI.setDesc(get(NewOpc));
6020     MI.getOperand(1).ChangeToImmediate(0);
6021   } else if (Ops.size() != 1)
6022     return nullptr;
6023 
6024   // Make sure the subregisters match.
6025   // Otherwise we risk changing the size of the load.
6026   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6027     return nullptr;
6028 
6029   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6030   switch (LoadMI.getOpcode()) {
6031   case X86::MMX_SET0:
6032   case X86::V_SET0:
6033   case X86::V_SETALLONES:
6034   case X86::AVX2_SETALLONES:
6035   case X86::AVX1_SETALLONES:
6036   case X86::AVX_SET0:
6037   case X86::AVX512_128_SET0:
6038   case X86::AVX512_256_SET0:
6039   case X86::AVX512_512_SET0:
6040   case X86::AVX512_512_SETALLONES:
6041   case X86::FsFLD0SD:
6042   case X86::AVX512_FsFLD0SD:
6043   case X86::FsFLD0SS:
6044   case X86::AVX512_FsFLD0SS:
6045   case X86::FsFLD0F128:
6046   case X86::AVX512_FsFLD0F128: {
6047     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6048     // Create a constant-pool entry and operands to load from it.
6049 
6050     // Medium and large mode can't fold loads this way.
6051     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6052         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6053       return nullptr;
6054 
6055     // x86-32 PIC requires a PIC base register for constant pools.
6056     unsigned PICBase = 0;
6057     if (MF.getTarget().isPositionIndependent()) {
6058       if (Subtarget.is64Bit())
6059         PICBase = X86::RIP;
6060       else
6061         // FIXME: PICBase = getGlobalBaseReg(&MF);
6062         // This doesn't work for several reasons.
6063         // 1. GlobalBaseReg may have been spilled.
6064         // 2. It may not be live at MI.
6065         return nullptr;
6066     }
6067 
6068     // Create a constant-pool entry.
6069     MachineConstantPool &MCP = *MF.getConstantPool();
6070     Type *Ty;
6071     unsigned Opc = LoadMI.getOpcode();
6072     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
6073       Ty = Type::getFloatTy(MF.getFunction().getContext());
6074     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
6075       Ty = Type::getDoubleTy(MF.getFunction().getContext());
6076     else if (Opc == X86::FsFLD0F128 || Opc == X86::AVX512_FsFLD0F128)
6077       Ty = Type::getFP128Ty(MF.getFunction().getContext());
6078     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
6079       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6080                                 16);
6081     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6082              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
6083       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6084                                 8);
6085     else if (Opc == X86::MMX_SET0)
6086       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6087                                 2);
6088     else
6089       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6090                                 4);
6091 
6092     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6093                       Opc == X86::AVX512_512_SETALLONES ||
6094                       Opc == X86::AVX1_SETALLONES);
6095     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6096                                     Constant::getNullValue(Ty);
6097     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6098 
6099     // Create operands to load from the constant pool entry.
6100     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6101     MOs.push_back(MachineOperand::CreateImm(1));
6102     MOs.push_back(MachineOperand::CreateReg(0, false));
6103     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6104     MOs.push_back(MachineOperand::CreateReg(0, false));
6105     break;
6106   }
6107   default: {
6108     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6109       return nullptr;
6110 
6111     // Folding a normal load. Just copy the load's address operands.
6112     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6113                LoadMI.operands_begin() + NumOps);
6114     break;
6115   }
6116   }
6117   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6118                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6119 }
6120 
6121 static SmallVector<MachineMemOperand *, 2>
6122 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6123   SmallVector<MachineMemOperand *, 2> LoadMMOs;
6124 
6125   for (MachineMemOperand *MMO : MMOs) {
6126     if (!MMO->isLoad())
6127       continue;
6128 
6129     if (!MMO->isStore()) {
6130       // Reuse the MMO.
6131       LoadMMOs.push_back(MMO);
6132     } else {
6133       // Clone the MMO and unset the store flag.
6134       LoadMMOs.push_back(MF.getMachineMemOperand(
6135           MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
6136     }
6137   }
6138 
6139   return LoadMMOs;
6140 }
6141 
6142 static SmallVector<MachineMemOperand *, 2>
6143 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6144   SmallVector<MachineMemOperand *, 2> StoreMMOs;
6145 
6146   for (MachineMemOperand *MMO : MMOs) {
6147     if (!MMO->isStore())
6148       continue;
6149 
6150     if (!MMO->isLoad()) {
6151       // Reuse the MMO.
6152       StoreMMOs.push_back(MMO);
6153     } else {
6154       // Clone the MMO and unset the load flag.
6155       StoreMMOs.push_back(MF.getMachineMemOperand(
6156           MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
6157     }
6158   }
6159 
6160   return StoreMMOs;
6161 }
6162 
6163 static unsigned getBroadcastOpcode(const X86MemoryFoldTableEntry *I,
6164                                    const TargetRegisterClass *RC,
6165                                    const X86Subtarget &STI) {
6166   assert(STI.hasAVX512() && "Expected at least AVX512!");
6167   unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
6168   assert((SpillSize == 64 || STI.hasVLX()) &&
6169          "Can't broadcast less than 64 bytes without AVX512VL!");
6170 
6171   switch (I->Flags & TB_BCAST_MASK) {
6172   default: llvm_unreachable("Unexpected broadcast type!");
6173   case TB_BCAST_D:
6174     switch (SpillSize) {
6175     default: llvm_unreachable("Unknown spill size");
6176     case 16: return X86::VPBROADCASTDZ128rm;
6177     case 32: return X86::VPBROADCASTDZ256rm;
6178     case 64: return X86::VPBROADCASTDZrm;
6179     }
6180     break;
6181   case TB_BCAST_Q:
6182     switch (SpillSize) {
6183     default: llvm_unreachable("Unknown spill size");
6184     case 16: return X86::VPBROADCASTQZ128rm;
6185     case 32: return X86::VPBROADCASTQZ256rm;
6186     case 64: return X86::VPBROADCASTQZrm;
6187     }
6188     break;
6189   case TB_BCAST_SS:
6190     switch (SpillSize) {
6191     default: llvm_unreachable("Unknown spill size");
6192     case 16: return X86::VBROADCASTSSZ128rm;
6193     case 32: return X86::VBROADCASTSSZ256rm;
6194     case 64: return X86::VBROADCASTSSZrm;
6195     }
6196     break;
6197   case TB_BCAST_SD:
6198     switch (SpillSize) {
6199     default: llvm_unreachable("Unknown spill size");
6200     case 16: return X86::VMOVDDUPZ128rm;
6201     case 32: return X86::VBROADCASTSDZ256rm;
6202     case 64: return X86::VBROADCASTSDZrm;
6203     }
6204     break;
6205   }
6206 }
6207 
6208 bool X86InstrInfo::unfoldMemoryOperand(
6209     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6210     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6211   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
6212   if (I == nullptr)
6213     return false;
6214   unsigned Opc = I->DstOp;
6215   unsigned Index = I->Flags & TB_INDEX_MASK;
6216   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6217   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6218   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6219   if (UnfoldLoad && !FoldedLoad)
6220     return false;
6221   UnfoldLoad &= FoldedLoad;
6222   if (UnfoldStore && !FoldedStore)
6223     return false;
6224   UnfoldStore &= FoldedStore;
6225 
6226   const MCInstrDesc &MCID = get(Opc);
6227 
6228   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6229   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6230   // TODO: Check if 32-byte or greater accesses are slow too?
6231   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
6232       Subtarget.isUnalignedMem16Slow())
6233     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6234     // conservatively assume the address is unaligned. That's bad for
6235     // performance.
6236     return false;
6237   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6238   SmallVector<MachineOperand,2> BeforeOps;
6239   SmallVector<MachineOperand,2> AfterOps;
6240   SmallVector<MachineOperand,4> ImpOps;
6241   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6242     MachineOperand &Op = MI.getOperand(i);
6243     if (i >= Index && i < Index + X86::AddrNumOperands)
6244       AddrOps.push_back(Op);
6245     else if (Op.isReg() && Op.isImplicit())
6246       ImpOps.push_back(Op);
6247     else if (i < Index)
6248       BeforeOps.push_back(Op);
6249     else if (i > Index)
6250       AfterOps.push_back(Op);
6251   }
6252 
6253   // Emit the load or broadcast instruction.
6254   if (UnfoldLoad) {
6255     auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
6256 
6257     unsigned Opc;
6258     if (FoldedBCast) {
6259       Opc = getBroadcastOpcode(I, RC, Subtarget);
6260     } else {
6261       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6262       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6263       Opc = getLoadRegOpcode(Reg, RC, isAligned, Subtarget);
6264     }
6265 
6266     DebugLoc DL;
6267     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
6268     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6269       MIB.add(AddrOps[i]);
6270     MIB.setMemRefs(MMOs);
6271     NewMIs.push_back(MIB);
6272 
6273     if (UnfoldStore) {
6274       // Address operands cannot be marked isKill.
6275       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6276         MachineOperand &MO = NewMIs[0]->getOperand(i);
6277         if (MO.isReg())
6278           MO.setIsKill(false);
6279       }
6280     }
6281   }
6282 
6283   // Emit the data processing instruction.
6284   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
6285   MachineInstrBuilder MIB(MF, DataMI);
6286 
6287   if (FoldedStore)
6288     MIB.addReg(Reg, RegState::Define);
6289   for (MachineOperand &BeforeOp : BeforeOps)
6290     MIB.add(BeforeOp);
6291   if (FoldedLoad)
6292     MIB.addReg(Reg);
6293   for (MachineOperand &AfterOp : AfterOps)
6294     MIB.add(AfterOp);
6295   for (MachineOperand &ImpOp : ImpOps) {
6296     MIB.addReg(ImpOp.getReg(),
6297                getDefRegState(ImpOp.isDef()) |
6298                RegState::Implicit |
6299                getKillRegState(ImpOp.isKill()) |
6300                getDeadRegState(ImpOp.isDead()) |
6301                getUndefRegState(ImpOp.isUndef()));
6302   }
6303   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6304   switch (DataMI->getOpcode()) {
6305   default: break;
6306   case X86::CMP64ri32:
6307   case X86::CMP64ri8:
6308   case X86::CMP32ri:
6309   case X86::CMP32ri8:
6310   case X86::CMP16ri:
6311   case X86::CMP16ri8:
6312   case X86::CMP8ri: {
6313     MachineOperand &MO0 = DataMI->getOperand(0);
6314     MachineOperand &MO1 = DataMI->getOperand(1);
6315     if (MO1.getImm() == 0) {
6316       unsigned NewOpc;
6317       switch (DataMI->getOpcode()) {
6318       default: llvm_unreachable("Unreachable!");
6319       case X86::CMP64ri8:
6320       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6321       case X86::CMP32ri8:
6322       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6323       case X86::CMP16ri8:
6324       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6325       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6326       }
6327       DataMI->setDesc(get(NewOpc));
6328       MO1.ChangeToRegister(MO0.getReg(), false);
6329     }
6330   }
6331   }
6332   NewMIs.push_back(DataMI);
6333 
6334   // Emit the store instruction.
6335   if (UnfoldStore) {
6336     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6337     auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
6338     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16);
6339     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6340     unsigned Opc = getStoreRegOpcode(Reg, DstRC, isAligned, Subtarget);
6341     DebugLoc DL;
6342     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6343     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6344       MIB.add(AddrOps[i]);
6345     MIB.addReg(Reg, RegState::Kill);
6346     MIB.setMemRefs(MMOs);
6347     NewMIs.push_back(MIB);
6348   }
6349 
6350   return true;
6351 }
6352 
6353 bool
6354 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6355                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6356   if (!N->isMachineOpcode())
6357     return false;
6358 
6359   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
6360   if (I == nullptr)
6361     return false;
6362   unsigned Opc = I->DstOp;
6363   unsigned Index = I->Flags & TB_INDEX_MASK;
6364   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6365   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6366   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6367   const MCInstrDesc &MCID = get(Opc);
6368   MachineFunction &MF = DAG.getMachineFunction();
6369   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6370   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6371   unsigned NumDefs = MCID.NumDefs;
6372   std::vector<SDValue> AddrOps;
6373   std::vector<SDValue> BeforeOps;
6374   std::vector<SDValue> AfterOps;
6375   SDLoc dl(N);
6376   unsigned NumOps = N->getNumOperands();
6377   for (unsigned i = 0; i != NumOps-1; ++i) {
6378     SDValue Op = N->getOperand(i);
6379     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6380       AddrOps.push_back(Op);
6381     else if (i < Index-NumDefs)
6382       BeforeOps.push_back(Op);
6383     else if (i > Index-NumDefs)
6384       AfterOps.push_back(Op);
6385   }
6386   SDValue Chain = N->getOperand(NumOps-1);
6387   AddrOps.push_back(Chain);
6388 
6389   // Emit the load instruction.
6390   SDNode *Load = nullptr;
6391   if (FoldedLoad) {
6392     EVT VT = *TRI.legalclasstypes_begin(*RC);
6393     auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6394     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6395         Subtarget.isUnalignedMem16Slow())
6396       // Do not introduce a slow unaligned load.
6397       return false;
6398     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6399     // memory access is slow above.
6400 
6401     unsigned Opc;
6402     if (FoldedBCast) {
6403       Opc = getBroadcastOpcode(I, RC, Subtarget);
6404     } else {
6405       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6406       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6407       Opc = getLoadRegOpcode(0, RC, isAligned, Subtarget);
6408     }
6409 
6410     Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
6411     NewNodes.push_back(Load);
6412 
6413     // Preserve memory reference information.
6414     DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
6415   }
6416 
6417   // Emit the data processing instruction.
6418   std::vector<EVT> VTs;
6419   const TargetRegisterClass *DstRC = nullptr;
6420   if (MCID.getNumDefs() > 0) {
6421     DstRC = getRegClass(MCID, 0, &RI, MF);
6422     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
6423   }
6424   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6425     EVT VT = N->getValueType(i);
6426     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6427       VTs.push_back(VT);
6428   }
6429   if (Load)
6430     BeforeOps.push_back(SDValue(Load, 0));
6431   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
6432   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6433   switch (Opc) {
6434     default: break;
6435     case X86::CMP64ri32:
6436     case X86::CMP64ri8:
6437     case X86::CMP32ri:
6438     case X86::CMP32ri8:
6439     case X86::CMP16ri:
6440     case X86::CMP16ri8:
6441     case X86::CMP8ri:
6442       if (isNullConstant(BeforeOps[1])) {
6443         switch (Opc) {
6444           default: llvm_unreachable("Unreachable!");
6445           case X86::CMP64ri8:
6446           case X86::CMP64ri32: Opc = X86::TEST64rr; break;
6447           case X86::CMP32ri8:
6448           case X86::CMP32ri:   Opc = X86::TEST32rr; break;
6449           case X86::CMP16ri8:
6450           case X86::CMP16ri:   Opc = X86::TEST16rr; break;
6451           case X86::CMP8ri:    Opc = X86::TEST8rr; break;
6452         }
6453         BeforeOps[1] = BeforeOps[0];
6454       }
6455   }
6456   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6457   NewNodes.push_back(NewNode);
6458 
6459   // Emit the store instruction.
6460   if (FoldedStore) {
6461     AddrOps.pop_back();
6462     AddrOps.push_back(SDValue(NewNode, 0));
6463     AddrOps.push_back(Chain);
6464     auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6465     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6466         Subtarget.isUnalignedMem16Slow())
6467       // Do not introduce a slow unaligned store.
6468       return false;
6469     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6470     // memory access is slow above.
6471     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6472     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6473     SDNode *Store =
6474         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6475                            dl, MVT::Other, AddrOps);
6476     NewNodes.push_back(Store);
6477 
6478     // Preserve memory reference information.
6479     DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
6480   }
6481 
6482   return true;
6483 }
6484 
6485 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6486                                       bool UnfoldLoad, bool UnfoldStore,
6487                                       unsigned *LoadRegIndex) const {
6488   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
6489   if (I == nullptr)
6490     return 0;
6491   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6492   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6493   if (UnfoldLoad && !FoldedLoad)
6494     return 0;
6495   if (UnfoldStore && !FoldedStore)
6496     return 0;
6497   if (LoadRegIndex)
6498     *LoadRegIndex = I->Flags & TB_INDEX_MASK;
6499   return I->DstOp;
6500 }
6501 
6502 bool
6503 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6504                                      int64_t &Offset1, int64_t &Offset2) const {
6505   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6506     return false;
6507   unsigned Opc1 = Load1->getMachineOpcode();
6508   unsigned Opc2 = Load2->getMachineOpcode();
6509   switch (Opc1) {
6510   default: return false;
6511   case X86::MOV8rm:
6512   case X86::MOV16rm:
6513   case X86::MOV32rm:
6514   case X86::MOV64rm:
6515   case X86::LD_Fp32m:
6516   case X86::LD_Fp64m:
6517   case X86::LD_Fp80m:
6518   case X86::MOVSSrm:
6519   case X86::MOVSSrm_alt:
6520   case X86::MOVSDrm:
6521   case X86::MOVSDrm_alt:
6522   case X86::MMX_MOVD64rm:
6523   case X86::MMX_MOVQ64rm:
6524   case X86::MOVAPSrm:
6525   case X86::MOVUPSrm:
6526   case X86::MOVAPDrm:
6527   case X86::MOVUPDrm:
6528   case X86::MOVDQArm:
6529   case X86::MOVDQUrm:
6530   // AVX load instructions
6531   case X86::VMOVSSrm:
6532   case X86::VMOVSSrm_alt:
6533   case X86::VMOVSDrm:
6534   case X86::VMOVSDrm_alt:
6535   case X86::VMOVAPSrm:
6536   case X86::VMOVUPSrm:
6537   case X86::VMOVAPDrm:
6538   case X86::VMOVUPDrm:
6539   case X86::VMOVDQArm:
6540   case X86::VMOVDQUrm:
6541   case X86::VMOVAPSYrm:
6542   case X86::VMOVUPSYrm:
6543   case X86::VMOVAPDYrm:
6544   case X86::VMOVUPDYrm:
6545   case X86::VMOVDQAYrm:
6546   case X86::VMOVDQUYrm:
6547   // AVX512 load instructions
6548   case X86::VMOVSSZrm:
6549   case X86::VMOVSSZrm_alt:
6550   case X86::VMOVSDZrm:
6551   case X86::VMOVSDZrm_alt:
6552   case X86::VMOVAPSZ128rm:
6553   case X86::VMOVUPSZ128rm:
6554   case X86::VMOVAPSZ128rm_NOVLX:
6555   case X86::VMOVUPSZ128rm_NOVLX:
6556   case X86::VMOVAPDZ128rm:
6557   case X86::VMOVUPDZ128rm:
6558   case X86::VMOVDQU8Z128rm:
6559   case X86::VMOVDQU16Z128rm:
6560   case X86::VMOVDQA32Z128rm:
6561   case X86::VMOVDQU32Z128rm:
6562   case X86::VMOVDQA64Z128rm:
6563   case X86::VMOVDQU64Z128rm:
6564   case X86::VMOVAPSZ256rm:
6565   case X86::VMOVUPSZ256rm:
6566   case X86::VMOVAPSZ256rm_NOVLX:
6567   case X86::VMOVUPSZ256rm_NOVLX:
6568   case X86::VMOVAPDZ256rm:
6569   case X86::VMOVUPDZ256rm:
6570   case X86::VMOVDQU8Z256rm:
6571   case X86::VMOVDQU16Z256rm:
6572   case X86::VMOVDQA32Z256rm:
6573   case X86::VMOVDQU32Z256rm:
6574   case X86::VMOVDQA64Z256rm:
6575   case X86::VMOVDQU64Z256rm:
6576   case X86::VMOVAPSZrm:
6577   case X86::VMOVUPSZrm:
6578   case X86::VMOVAPDZrm:
6579   case X86::VMOVUPDZrm:
6580   case X86::VMOVDQU8Zrm:
6581   case X86::VMOVDQU16Zrm:
6582   case X86::VMOVDQA32Zrm:
6583   case X86::VMOVDQU32Zrm:
6584   case X86::VMOVDQA64Zrm:
6585   case X86::VMOVDQU64Zrm:
6586   case X86::KMOVBkm:
6587   case X86::KMOVWkm:
6588   case X86::KMOVDkm:
6589   case X86::KMOVQkm:
6590     break;
6591   }
6592   switch (Opc2) {
6593   default: return false;
6594   case X86::MOV8rm:
6595   case X86::MOV16rm:
6596   case X86::MOV32rm:
6597   case X86::MOV64rm:
6598   case X86::LD_Fp32m:
6599   case X86::LD_Fp64m:
6600   case X86::LD_Fp80m:
6601   case X86::MOVSSrm:
6602   case X86::MOVSSrm_alt:
6603   case X86::MOVSDrm:
6604   case X86::MOVSDrm_alt:
6605   case X86::MMX_MOVD64rm:
6606   case X86::MMX_MOVQ64rm:
6607   case X86::MOVAPSrm:
6608   case X86::MOVUPSrm:
6609   case X86::MOVAPDrm:
6610   case X86::MOVUPDrm:
6611   case X86::MOVDQArm:
6612   case X86::MOVDQUrm:
6613   // AVX load instructions
6614   case X86::VMOVSSrm:
6615   case X86::VMOVSSrm_alt:
6616   case X86::VMOVSDrm:
6617   case X86::VMOVSDrm_alt:
6618   case X86::VMOVAPSrm:
6619   case X86::VMOVUPSrm:
6620   case X86::VMOVAPDrm:
6621   case X86::VMOVUPDrm:
6622   case X86::VMOVDQArm:
6623   case X86::VMOVDQUrm:
6624   case X86::VMOVAPSYrm:
6625   case X86::VMOVUPSYrm:
6626   case X86::VMOVAPDYrm:
6627   case X86::VMOVUPDYrm:
6628   case X86::VMOVDQAYrm:
6629   case X86::VMOVDQUYrm:
6630   // AVX512 load instructions
6631   case X86::VMOVSSZrm:
6632   case X86::VMOVSSZrm_alt:
6633   case X86::VMOVSDZrm:
6634   case X86::VMOVSDZrm_alt:
6635   case X86::VMOVAPSZ128rm:
6636   case X86::VMOVUPSZ128rm:
6637   case X86::VMOVAPSZ128rm_NOVLX:
6638   case X86::VMOVUPSZ128rm_NOVLX:
6639   case X86::VMOVAPDZ128rm:
6640   case X86::VMOVUPDZ128rm:
6641   case X86::VMOVDQU8Z128rm:
6642   case X86::VMOVDQU16Z128rm:
6643   case X86::VMOVDQA32Z128rm:
6644   case X86::VMOVDQU32Z128rm:
6645   case X86::VMOVDQA64Z128rm:
6646   case X86::VMOVDQU64Z128rm:
6647   case X86::VMOVAPSZ256rm:
6648   case X86::VMOVUPSZ256rm:
6649   case X86::VMOVAPSZ256rm_NOVLX:
6650   case X86::VMOVUPSZ256rm_NOVLX:
6651   case X86::VMOVAPDZ256rm:
6652   case X86::VMOVUPDZ256rm:
6653   case X86::VMOVDQU8Z256rm:
6654   case X86::VMOVDQU16Z256rm:
6655   case X86::VMOVDQA32Z256rm:
6656   case X86::VMOVDQU32Z256rm:
6657   case X86::VMOVDQA64Z256rm:
6658   case X86::VMOVDQU64Z256rm:
6659   case X86::VMOVAPSZrm:
6660   case X86::VMOVUPSZrm:
6661   case X86::VMOVAPDZrm:
6662   case X86::VMOVUPDZrm:
6663   case X86::VMOVDQU8Zrm:
6664   case X86::VMOVDQU16Zrm:
6665   case X86::VMOVDQA32Zrm:
6666   case X86::VMOVDQU32Zrm:
6667   case X86::VMOVDQA64Zrm:
6668   case X86::VMOVDQU64Zrm:
6669   case X86::KMOVBkm:
6670   case X86::KMOVWkm:
6671   case X86::KMOVDkm:
6672   case X86::KMOVQkm:
6673     break;
6674   }
6675 
6676   // Lambda to check if both the loads have the same value for an operand index.
6677   auto HasSameOp = [&](int I) {
6678     return Load1->getOperand(I) == Load2->getOperand(I);
6679   };
6680 
6681   // All operands except the displacement should match.
6682   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
6683       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
6684     return false;
6685 
6686   // Chain Operand must be the same.
6687   if (!HasSameOp(5))
6688     return false;
6689 
6690   // Now let's examine if the displacements are constants.
6691   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
6692   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
6693   if (!Disp1 || !Disp2)
6694     return false;
6695 
6696   Offset1 = Disp1->getSExtValue();
6697   Offset2 = Disp2->getSExtValue();
6698   return true;
6699 }
6700 
6701 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6702                                            int64_t Offset1, int64_t Offset2,
6703                                            unsigned NumLoads) const {
6704   assert(Offset2 > Offset1);
6705   if ((Offset2 - Offset1) / 8 > 64)
6706     return false;
6707 
6708   unsigned Opc1 = Load1->getMachineOpcode();
6709   unsigned Opc2 = Load2->getMachineOpcode();
6710   if (Opc1 != Opc2)
6711     return false;  // FIXME: overly conservative?
6712 
6713   switch (Opc1) {
6714   default: break;
6715   case X86::LD_Fp32m:
6716   case X86::LD_Fp64m:
6717   case X86::LD_Fp80m:
6718   case X86::MMX_MOVD64rm:
6719   case X86::MMX_MOVQ64rm:
6720     return false;
6721   }
6722 
6723   EVT VT = Load1->getValueType(0);
6724   switch (VT.getSimpleVT().SimpleTy) {
6725   default:
6726     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6727     // have 16 of them to play with.
6728     if (Subtarget.is64Bit()) {
6729       if (NumLoads >= 3)
6730         return false;
6731     } else if (NumLoads) {
6732       return false;
6733     }
6734     break;
6735   case MVT::i8:
6736   case MVT::i16:
6737   case MVT::i32:
6738   case MVT::i64:
6739   case MVT::f32:
6740   case MVT::f64:
6741     if (NumLoads)
6742       return false;
6743     break;
6744   }
6745 
6746   return true;
6747 }
6748 
6749 bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
6750                                         const MachineBasicBlock *MBB,
6751                                         const MachineFunction &MF) const {
6752 
6753   // ENDBR instructions should not be scheduled around.
6754   unsigned Opcode = MI.getOpcode();
6755   if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32)
6756     return true;
6757 
6758   return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
6759 }
6760 
6761 bool X86InstrInfo::
6762 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6763   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6764   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6765   Cond[0].setImm(GetOppositeBranchCondition(CC));
6766   return false;
6767 }
6768 
6769 bool X86InstrInfo::
6770 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6771   // FIXME: Return false for x87 stack register classes for now. We can't
6772   // allow any loads of these registers before FpGet_ST0_80.
6773   return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
6774            RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
6775            RC == &X86::RFP80RegClass);
6776 }
6777 
6778 /// Return a virtual register initialized with the
6779 /// the global base register value. Output instructions required to
6780 /// initialize the register in the function entry block, if necessary.
6781 ///
6782 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6783 ///
6784 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6785   assert((!Subtarget.is64Bit() ||
6786           MF->getTarget().getCodeModel() == CodeModel::Medium ||
6787           MF->getTarget().getCodeModel() == CodeModel::Large) &&
6788          "X86-64 PIC uses RIP relative addressing");
6789 
6790   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6791   Register GlobalBaseReg = X86FI->getGlobalBaseReg();
6792   if (GlobalBaseReg != 0)
6793     return GlobalBaseReg;
6794 
6795   // Create the register. The code to initialize it is inserted
6796   // later, by the CGBR pass (below).
6797   MachineRegisterInfo &RegInfo = MF->getRegInfo();
6798   GlobalBaseReg = RegInfo.createVirtualRegister(
6799       Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
6800   X86FI->setGlobalBaseReg(GlobalBaseReg);
6801   return GlobalBaseReg;
6802 }
6803 
6804 // These are the replaceable SSE instructions. Some of these have Int variants
6805 // that we don't include here. We don't want to replace instructions selected
6806 // by intrinsics.
6807 static const uint16_t ReplaceableInstrs[][3] = {
6808   //PackedSingle     PackedDouble    PackedInt
6809   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
6810   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
6811   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
6812   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
6813   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
6814   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
6815   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
6816   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
6817   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
6818   { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
6819   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
6820   { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
6821   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
6822   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
6823   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
6824   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
6825   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
6826   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
6827   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
6828   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
6829   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
6830   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
6831   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
6832   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
6833   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
6834   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
6835   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
6836   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
6837   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
6838   { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
6839   { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
6840   // AVX 128-bit support
6841   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
6842   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
6843   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
6844   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
6845   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
6846   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
6847   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
6848   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
6849   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
6850   { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
6851   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
6852   { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
6853   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6854   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
6855   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
6856   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
6857   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
6858   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
6859   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
6860   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
6861   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
6862   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
6863   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
6864   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
6865   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
6866   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
6867   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
6868   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
6869   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
6870   { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
6871   { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
6872   // AVX 256-bit support
6873   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
6874   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
6875   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
6876   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
6877   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
6878   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
6879   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
6880   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
6881   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
6882   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
6883   // AVX512 support
6884   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
6885   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
6886   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
6887   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
6888   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
6889   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
6890   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
6891   { X86::VMOVSDZrm_alt,  X86::VMOVSDZrm_alt,  X86::VMOVQI2PQIZrm  },
6892   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
6893   { X86::VMOVSSZrm_alt,  X86::VMOVSSZrm_alt,  X86::VMOVDI2PDIZrm  },
6894   { X86::VBROADCASTSSZ128rr,X86::VBROADCASTSSZ128rr,X86::VPBROADCASTDZ128rr },
6895   { X86::VBROADCASTSSZ128rm,X86::VBROADCASTSSZ128rm,X86::VPBROADCASTDZ128rm },
6896   { X86::VBROADCASTSSZ256rr,X86::VBROADCASTSSZ256rr,X86::VPBROADCASTDZ256rr },
6897   { X86::VBROADCASTSSZ256rm,X86::VBROADCASTSSZ256rm,X86::VPBROADCASTDZ256rm },
6898   { X86::VBROADCASTSSZrr,   X86::VBROADCASTSSZrr,   X86::VPBROADCASTDZrr },
6899   { X86::VBROADCASTSSZrm,   X86::VBROADCASTSSZrm,   X86::VPBROADCASTDZrm },
6900   { X86::VMOVDDUPZ128rr,    X86::VMOVDDUPZ128rr,    X86::VPBROADCASTQZ128rr },
6901   { X86::VMOVDDUPZ128rm,    X86::VMOVDDUPZ128rm,    X86::VPBROADCASTQZ128rm },
6902   { X86::VBROADCASTSDZ256rr,X86::VBROADCASTSDZ256rr,X86::VPBROADCASTQZ256rr },
6903   { X86::VBROADCASTSDZ256rm,X86::VBROADCASTSDZ256rm,X86::VPBROADCASTQZ256rm },
6904   { X86::VBROADCASTSDZrr,   X86::VBROADCASTSDZrr,   X86::VPBROADCASTQZrr },
6905   { X86::VBROADCASTSDZrm,   X86::VBROADCASTSDZrm,   X86::VPBROADCASTQZrm },
6906   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
6907   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
6908   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
6909   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
6910   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
6911   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
6912   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
6913   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
6914   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
6915   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
6916   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
6917   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
6918   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
6919   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
6920   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
6921   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
6922   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
6923   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
6924   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
6925   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
6926   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
6927   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
6928   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
6929   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
6930   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
6931   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
6932   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
6933   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
6934   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
6935   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
6936   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
6937   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
6938   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
6939   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
6940   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
6941   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
6942   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
6943   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
6944   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
6945   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
6946   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
6947   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
6948   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
6949   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
6950   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
6951   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
6952   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
6953   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
6954   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
6955   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
6956   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
6957   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
6958   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
6959   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
6960   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
6961   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
6962   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
6963   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
6964   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
6965   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
6966   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
6967   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
6968   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
6969   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
6970   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
6971   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
6972   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
6973   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
6974   { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
6975   { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
6976 };
6977 
6978 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6979   //PackedSingle       PackedDouble       PackedInt
6980   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
6981   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
6982   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
6983   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
6984   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
6985   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
6986   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
6987   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
6988   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
6989   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
6990   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6991   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6992   { X86::VMOVDDUPrm,     X86::VMOVDDUPrm,     X86::VPBROADCASTQrm},
6993   { X86::VMOVDDUPrr,     X86::VMOVDDUPrr,     X86::VPBROADCASTQrr},
6994   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6995   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6996   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6997   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
6998   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
6999   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
7000   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
7001   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
7002   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
7003   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
7004   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
7005   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
7006   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
7007   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
7008   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
7009   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
7010   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
7011 };
7012 
7013 static const uint16_t ReplaceableInstrsFP[][3] = {
7014   //PackedSingle         PackedDouble
7015   { X86::MOVLPSrm,       X86::MOVLPDrm,      X86::INSTRUCTION_LIST_END },
7016   { X86::MOVHPSrm,       X86::MOVHPDrm,      X86::INSTRUCTION_LIST_END },
7017   { X86::MOVHPSmr,       X86::MOVHPDmr,      X86::INSTRUCTION_LIST_END },
7018   { X86::VMOVLPSrm,      X86::VMOVLPDrm,     X86::INSTRUCTION_LIST_END },
7019   { X86::VMOVHPSrm,      X86::VMOVHPDrm,     X86::INSTRUCTION_LIST_END },
7020   { X86::VMOVHPSmr,      X86::VMOVHPDmr,     X86::INSTRUCTION_LIST_END },
7021   { X86::VMOVLPSZ128rm,  X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
7022   { X86::VMOVHPSZ128rm,  X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
7023   { X86::VMOVHPSZ128mr,  X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
7024 };
7025 
7026 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
7027   //PackedSingle       PackedDouble       PackedInt
7028   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7029   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7030   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
7031   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
7032 };
7033 
7034 static const uint16_t ReplaceableInstrsAVX512[][4] = {
7035   // Two integer columns for 64-bit and 32-bit elements.
7036   //PackedSingle        PackedDouble        PackedInt             PackedInt
7037   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
7038   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
7039   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
7040   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
7041   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
7042   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
7043   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
7044   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
7045   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
7046   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
7047   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
7048   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
7049   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
7050   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
7051   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
7052 };
7053 
7054 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7055   // Two integer columns for 64-bit and 32-bit elements.
7056   //PackedSingle        PackedDouble        PackedInt           PackedInt
7057   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7058   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7059   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7060   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7061   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7062   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7063   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7064   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7065   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7066   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7067   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7068   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7069   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7070   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7071   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7072   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7073   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
7074   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
7075   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
7076   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
7077   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
7078   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
7079   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
7080   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
7081 };
7082 
7083 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
7084   // Two integer columns for 64-bit and 32-bit elements.
7085   //PackedSingle          PackedDouble
7086   //PackedInt             PackedInt
7087   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
7088     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
7089   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
7090     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
7091   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
7092     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
7093   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
7094     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
7095   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
7096     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
7097   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
7098     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
7099   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
7100     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
7101   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
7102     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
7103   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
7104     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
7105   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
7106     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
7107   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
7108     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
7109   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
7110     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
7111   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
7112     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
7113   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
7114     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
7115   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
7116     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
7117   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
7118     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
7119   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
7120     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
7121   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
7122     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
7123   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
7124     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
7125   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
7126     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
7127   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
7128     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
7129   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
7130     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
7131   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
7132     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
7133   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
7134     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
7135   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
7136     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
7137   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
7138     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
7139   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
7140     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
7141   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
7142     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
7143   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
7144     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
7145   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
7146     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
7147   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
7148     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
7149   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
7150     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
7151   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
7152     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
7153   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
7154     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
7155   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
7156     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
7157   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
7158     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
7159   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
7160     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
7161   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
7162     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
7163   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
7164     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
7165   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
7166     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
7167   { X86::VORPSZrmk,       X86::VORPDZrmk,
7168     X86::VPORQZrmk,       X86::VPORDZrmk       },
7169   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
7170     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
7171   { X86::VORPSZrrk,       X86::VORPDZrrk,
7172     X86::VPORQZrrk,       X86::VPORDZrrk       },
7173   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
7174     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
7175   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
7176     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
7177   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
7178     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
7179   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
7180     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
7181   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
7182     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
7183   // Broadcast loads can be handled the same as masked operations to avoid
7184   // changing element size.
7185   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
7186     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
7187   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
7188     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
7189   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
7190     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
7191   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
7192     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
7193   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
7194     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
7195   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
7196     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
7197   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
7198     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
7199   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
7200     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
7201   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
7202     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
7203   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7204     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7205   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7206     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7207   { X86::VORPSZrmb,       X86::VORPDZrmb,
7208     X86::VPORQZrmb,       X86::VPORDZrmb       },
7209   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
7210     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
7211   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
7212     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
7213   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
7214     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
7215   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
7216     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
7217   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
7218     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
7219   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
7220     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
7221   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
7222     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
7223   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
7224     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
7225   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
7226     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
7227   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
7228     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
7229   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7230     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7231   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7232     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7233   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
7234     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
7235   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
7236     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
7237   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
7238     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
7239   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
7240     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
7241   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
7242     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
7243   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
7244     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
7245   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
7246     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
7247   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
7248     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
7249   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
7250     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
7251   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
7252     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
7253   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
7254     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
7255   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7256     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7257   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7258     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7259   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
7260     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
7261   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
7262     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
7263 };
7264 
7265 // NOTE: These should only be used by the custom domain methods.
7266 static const uint16_t ReplaceableBlendInstrs[][3] = {
7267   //PackedSingle             PackedDouble             PackedInt
7268   { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
7269   { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
7270   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
7271   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
7272   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
7273   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
7274 };
7275 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
7276   //PackedSingle             PackedDouble             PackedInt
7277   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
7278   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
7279   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
7280   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
7281 };
7282 
7283 // Special table for changing EVEX logic instructions to VEX.
7284 // TODO: Should we run EVEX->VEX earlier?
7285 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
7286   // Two integer columns for 64-bit and 32-bit elements.
7287   //PackedSingle     PackedDouble     PackedInt           PackedInt
7288   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7289   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7290   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7291   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7292   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7293   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7294   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7295   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7296   { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7297   { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7298   { X86::VANDPSYrm,  X86::VANDPDYrm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7299   { X86::VANDPSYrr,  X86::VANDPDYrr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7300   { X86::VORPSYrm,   X86::VORPDYrm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7301   { X86::VORPSYrr,   X86::VORPDYrr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7302   { X86::VXORPSYrm,  X86::VXORPDYrm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7303   { X86::VXORPSYrr,  X86::VXORPDYrr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7304 };
7305 
7306 // FIXME: Some shuffle and unpack instructions have equivalents in different
7307 // domains, but they require a bit more work than just switching opcodes.
7308 
7309 static const uint16_t *lookup(unsigned opcode, unsigned domain,
7310                               ArrayRef<uint16_t[3]> Table) {
7311   for (const uint16_t (&Row)[3] : Table)
7312     if (Row[domain-1] == opcode)
7313       return Row;
7314   return nullptr;
7315 }
7316 
7317 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
7318                                     ArrayRef<uint16_t[4]> Table) {
7319   // If this is the integer domain make sure to check both integer columns.
7320   for (const uint16_t (&Row)[4] : Table)
7321     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7322       return Row;
7323   return nullptr;
7324 }
7325 
7326 // Helper to attempt to widen/narrow blend masks.
7327 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
7328                             unsigned NewWidth, unsigned *pNewMask = nullptr) {
7329   assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
7330          "Illegal blend mask scale");
7331   unsigned NewMask = 0;
7332 
7333   if ((OldWidth % NewWidth) == 0) {
7334     unsigned Scale = OldWidth / NewWidth;
7335     unsigned SubMask = (1u << Scale) - 1;
7336     for (unsigned i = 0; i != NewWidth; ++i) {
7337       unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
7338       if (Sub == SubMask)
7339         NewMask |= (1u << i);
7340       else if (Sub != 0x0)
7341         return false;
7342     }
7343   } else {
7344     unsigned Scale = NewWidth / OldWidth;
7345     unsigned SubMask = (1u << Scale) - 1;
7346     for (unsigned i = 0; i != OldWidth; ++i) {
7347       if (OldMask & (1 << i)) {
7348         NewMask |= (SubMask << (i * Scale));
7349       }
7350     }
7351   }
7352 
7353   if (pNewMask)
7354     *pNewMask = NewMask;
7355   return true;
7356 }
7357 
7358 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
7359   unsigned Opcode = MI.getOpcode();
7360   unsigned NumOperands = MI.getDesc().getNumOperands();
7361 
7362   auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
7363     uint16_t validDomains = 0;
7364     if (MI.getOperand(NumOperands - 1).isImm()) {
7365       unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
7366       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
7367         validDomains |= 0x2; // PackedSingle
7368       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
7369         validDomains |= 0x4; // PackedDouble
7370       if (!Is256 || Subtarget.hasAVX2())
7371         validDomains |= 0x8; // PackedInt
7372     }
7373     return validDomains;
7374   };
7375 
7376   switch (Opcode) {
7377   case X86::BLENDPDrmi:
7378   case X86::BLENDPDrri:
7379   case X86::VBLENDPDrmi:
7380   case X86::VBLENDPDrri:
7381     return GetBlendDomains(2, false);
7382   case X86::VBLENDPDYrmi:
7383   case X86::VBLENDPDYrri:
7384     return GetBlendDomains(4, true);
7385   case X86::BLENDPSrmi:
7386   case X86::BLENDPSrri:
7387   case X86::VBLENDPSrmi:
7388   case X86::VBLENDPSrri:
7389   case X86::VPBLENDDrmi:
7390   case X86::VPBLENDDrri:
7391     return GetBlendDomains(4, false);
7392   case X86::VBLENDPSYrmi:
7393   case X86::VBLENDPSYrri:
7394   case X86::VPBLENDDYrmi:
7395   case X86::VPBLENDDYrri:
7396     return GetBlendDomains(8, true);
7397   case X86::PBLENDWrmi:
7398   case X86::PBLENDWrri:
7399   case X86::VPBLENDWrmi:
7400   case X86::VPBLENDWrri:
7401   // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
7402   case X86::VPBLENDWYrmi:
7403   case X86::VPBLENDWYrri:
7404     return GetBlendDomains(8, false);
7405   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7406   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7407   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7408   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7409   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7410   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7411   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7412   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7413   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7414   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7415   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7416   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7417   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7418   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7419   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7420   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm:
7421     // If we don't have DQI see if we can still switch from an EVEX integer
7422     // instruction to a VEX floating point instruction.
7423     if (Subtarget.hasDQI())
7424       return 0;
7425 
7426     if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
7427       return 0;
7428     if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
7429       return 0;
7430     // Register forms will have 3 operands. Memory form will have more.
7431     if (NumOperands == 3 &&
7432         RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
7433       return 0;
7434 
7435     // All domains are valid.
7436     return 0xe;
7437   case X86::MOVHLPSrr:
7438     // We can swap domains when both inputs are the same register.
7439     // FIXME: This doesn't catch all the cases we would like. If the input
7440     // register isn't KILLed by the instruction, the two address instruction
7441     // pass puts a COPY on one input. The other input uses the original
7442     // register. This prevents the same physical register from being used by
7443     // both inputs.
7444     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7445         MI.getOperand(0).getSubReg() == 0 &&
7446         MI.getOperand(1).getSubReg() == 0 &&
7447         MI.getOperand(2).getSubReg() == 0)
7448       return 0x6;
7449     return 0;
7450   case X86::SHUFPDrri:
7451     return 0x6;
7452   }
7453   return 0;
7454 }
7455 
7456 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
7457                                             unsigned Domain) const {
7458   assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
7459   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7460   assert(dom && "Not an SSE instruction");
7461 
7462   unsigned Opcode = MI.getOpcode();
7463   unsigned NumOperands = MI.getDesc().getNumOperands();
7464 
7465   auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
7466     if (MI.getOperand(NumOperands - 1).isImm()) {
7467       unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
7468       Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
7469       unsigned NewImm = Imm;
7470 
7471       const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
7472       if (!table)
7473         table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7474 
7475       if (Domain == 1) { // PackedSingle
7476         AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7477       } else if (Domain == 2) { // PackedDouble
7478         AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
7479       } else if (Domain == 3) { // PackedInt
7480         if (Subtarget.hasAVX2()) {
7481           // If we are already VPBLENDW use that, else use VPBLENDD.
7482           if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
7483             table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7484             AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7485           }
7486         } else {
7487           assert(!Is256 && "128-bit vector expected");
7488           AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
7489         }
7490       }
7491 
7492       assert(table && table[Domain - 1] && "Unknown domain op");
7493       MI.setDesc(get(table[Domain - 1]));
7494       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
7495     }
7496     return true;
7497   };
7498 
7499   switch (Opcode) {
7500   case X86::BLENDPDrmi:
7501   case X86::BLENDPDrri:
7502   case X86::VBLENDPDrmi:
7503   case X86::VBLENDPDrri:
7504     return SetBlendDomain(2, false);
7505   case X86::VBLENDPDYrmi:
7506   case X86::VBLENDPDYrri:
7507     return SetBlendDomain(4, true);
7508   case X86::BLENDPSrmi:
7509   case X86::BLENDPSrri:
7510   case X86::VBLENDPSrmi:
7511   case X86::VBLENDPSrri:
7512   case X86::VPBLENDDrmi:
7513   case X86::VPBLENDDrri:
7514     return SetBlendDomain(4, false);
7515   case X86::VBLENDPSYrmi:
7516   case X86::VBLENDPSYrri:
7517   case X86::VPBLENDDYrmi:
7518   case X86::VPBLENDDYrri:
7519     return SetBlendDomain(8, true);
7520   case X86::PBLENDWrmi:
7521   case X86::PBLENDWrri:
7522   case X86::VPBLENDWrmi:
7523   case X86::VPBLENDWrri:
7524     return SetBlendDomain(8, false);
7525   case X86::VPBLENDWYrmi:
7526   case X86::VPBLENDWYrri:
7527     return SetBlendDomain(16, true);
7528   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7529   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7530   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7531   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7532   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7533   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7534   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7535   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7536   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7537   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7538   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7539   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7540   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7541   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7542   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7543   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm: {
7544     // Without DQI, convert EVEX instructions to VEX instructions.
7545     if (Subtarget.hasDQI())
7546       return false;
7547 
7548     const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
7549                                          ReplaceableCustomAVX512LogicInstrs);
7550     assert(table && "Instruction not found in table?");
7551     // Don't change integer Q instructions to D instructions and
7552     // use D intructions if we started with a PS instruction.
7553     if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7554       Domain = 4;
7555     MI.setDesc(get(table[Domain - 1]));
7556     return true;
7557   }
7558   case X86::UNPCKHPDrr:
7559   case X86::MOVHLPSrr:
7560     // We just need to commute the instruction which will switch the domains.
7561     if (Domain != dom && Domain != 3 &&
7562         MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7563         MI.getOperand(0).getSubReg() == 0 &&
7564         MI.getOperand(1).getSubReg() == 0 &&
7565         MI.getOperand(2).getSubReg() == 0) {
7566       commuteInstruction(MI, false);
7567       return true;
7568     }
7569     // We must always return true for MOVHLPSrr.
7570     if (Opcode == X86::MOVHLPSrr)
7571       return true;
7572     break;
7573   case X86::SHUFPDrri: {
7574     if (Domain == 1) {
7575       unsigned Imm = MI.getOperand(3).getImm();
7576       unsigned NewImm = 0x44;
7577       if (Imm & 1) NewImm |= 0x0a;
7578       if (Imm & 2) NewImm |= 0xa0;
7579       MI.getOperand(3).setImm(NewImm);
7580       MI.setDesc(get(X86::SHUFPSrri));
7581     }
7582     return true;
7583   }
7584   }
7585   return false;
7586 }
7587 
7588 std::pair<uint16_t, uint16_t>
7589 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7590   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7591   unsigned opcode = MI.getOpcode();
7592   uint16_t validDomains = 0;
7593   if (domain) {
7594     // Attempt to match for custom instructions.
7595     validDomains = getExecutionDomainCustom(MI);
7596     if (validDomains)
7597       return std::make_pair(domain, validDomains);
7598 
7599     if (lookup(opcode, domain, ReplaceableInstrs)) {
7600       validDomains = 0xe;
7601     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
7602       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
7603     } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
7604       validDomains = 0x6;
7605     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
7606       // Insert/extract instructions should only effect domain if AVX2
7607       // is enabled.
7608       if (!Subtarget.hasAVX2())
7609         return std::make_pair(0, 0);
7610       validDomains = 0xe;
7611     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
7612       validDomains = 0xe;
7613     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
7614                                                   ReplaceableInstrsAVX512DQ)) {
7615       validDomains = 0xe;
7616     } else if (Subtarget.hasDQI()) {
7617       if (const uint16_t *table = lookupAVX512(opcode, domain,
7618                                              ReplaceableInstrsAVX512DQMasked)) {
7619         if (domain == 1 || (domain == 3 && table[3] == opcode))
7620           validDomains = 0xa;
7621         else
7622           validDomains = 0xc;
7623       }
7624     }
7625   }
7626   return std::make_pair(domain, validDomains);
7627 }
7628 
7629 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
7630   assert(Domain>0 && Domain<4 && "Invalid execution domain");
7631   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7632   assert(dom && "Not an SSE instruction");
7633 
7634   // Attempt to match for custom instructions.
7635   if (setExecutionDomainCustom(MI, Domain))
7636     return;
7637 
7638   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
7639   if (!table) { // try the other table
7640     assert((Subtarget.hasAVX2() || Domain < 3) &&
7641            "256-bit vector operations only available in AVX2");
7642     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
7643   }
7644   if (!table) { // try the FP table
7645     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
7646     assert((!table || Domain < 3) &&
7647            "Can only select PackedSingle or PackedDouble");
7648   }
7649   if (!table) { // try the other table
7650     assert(Subtarget.hasAVX2() &&
7651            "256-bit insert/extract only available in AVX2");
7652     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
7653   }
7654   if (!table) { // try the AVX512 table
7655     assert(Subtarget.hasAVX512() && "Requires AVX-512");
7656     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
7657     // Don't change integer Q instructions to D instructions.
7658     if (table && Domain == 3 && table[3] == MI.getOpcode())
7659       Domain = 4;
7660   }
7661   if (!table) { // try the AVX512DQ table
7662     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7663     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
7664     // Don't change integer Q instructions to D instructions and
7665     // use D instructions if we started with a PS instruction.
7666     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7667       Domain = 4;
7668   }
7669   if (!table) { // try the AVX512DQMasked table
7670     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7671     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
7672     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7673       Domain = 4;
7674   }
7675   assert(table && "Cannot change domain");
7676   MI.setDesc(get(table[Domain - 1]));
7677 }
7678 
7679 /// Return the noop instruction to use for a noop.
7680 void X86InstrInfo::getNoop(MCInst &NopInst) const {
7681   NopInst.setOpcode(X86::NOOP);
7682 }
7683 
7684 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7685   switch (opc) {
7686   default: return false;
7687   case X86::DIVPDrm:
7688   case X86::DIVPDrr:
7689   case X86::DIVPSrm:
7690   case X86::DIVPSrr:
7691   case X86::DIVSDrm:
7692   case X86::DIVSDrm_Int:
7693   case X86::DIVSDrr:
7694   case X86::DIVSDrr_Int:
7695   case X86::DIVSSrm:
7696   case X86::DIVSSrm_Int:
7697   case X86::DIVSSrr:
7698   case X86::DIVSSrr_Int:
7699   case X86::SQRTPDm:
7700   case X86::SQRTPDr:
7701   case X86::SQRTPSm:
7702   case X86::SQRTPSr:
7703   case X86::SQRTSDm:
7704   case X86::SQRTSDm_Int:
7705   case X86::SQRTSDr:
7706   case X86::SQRTSDr_Int:
7707   case X86::SQRTSSm:
7708   case X86::SQRTSSm_Int:
7709   case X86::SQRTSSr:
7710   case X86::SQRTSSr_Int:
7711   // AVX instructions with high latency
7712   case X86::VDIVPDrm:
7713   case X86::VDIVPDrr:
7714   case X86::VDIVPDYrm:
7715   case X86::VDIVPDYrr:
7716   case X86::VDIVPSrm:
7717   case X86::VDIVPSrr:
7718   case X86::VDIVPSYrm:
7719   case X86::VDIVPSYrr:
7720   case X86::VDIVSDrm:
7721   case X86::VDIVSDrm_Int:
7722   case X86::VDIVSDrr:
7723   case X86::VDIVSDrr_Int:
7724   case X86::VDIVSSrm:
7725   case X86::VDIVSSrm_Int:
7726   case X86::VDIVSSrr:
7727   case X86::VDIVSSrr_Int:
7728   case X86::VSQRTPDm:
7729   case X86::VSQRTPDr:
7730   case X86::VSQRTPDYm:
7731   case X86::VSQRTPDYr:
7732   case X86::VSQRTPSm:
7733   case X86::VSQRTPSr:
7734   case X86::VSQRTPSYm:
7735   case X86::VSQRTPSYr:
7736   case X86::VSQRTSDm:
7737   case X86::VSQRTSDm_Int:
7738   case X86::VSQRTSDr:
7739   case X86::VSQRTSDr_Int:
7740   case X86::VSQRTSSm:
7741   case X86::VSQRTSSm_Int:
7742   case X86::VSQRTSSr:
7743   case X86::VSQRTSSr_Int:
7744   // AVX512 instructions with high latency
7745   case X86::VDIVPDZ128rm:
7746   case X86::VDIVPDZ128rmb:
7747   case X86::VDIVPDZ128rmbk:
7748   case X86::VDIVPDZ128rmbkz:
7749   case X86::VDIVPDZ128rmk:
7750   case X86::VDIVPDZ128rmkz:
7751   case X86::VDIVPDZ128rr:
7752   case X86::VDIVPDZ128rrk:
7753   case X86::VDIVPDZ128rrkz:
7754   case X86::VDIVPDZ256rm:
7755   case X86::VDIVPDZ256rmb:
7756   case X86::VDIVPDZ256rmbk:
7757   case X86::VDIVPDZ256rmbkz:
7758   case X86::VDIVPDZ256rmk:
7759   case X86::VDIVPDZ256rmkz:
7760   case X86::VDIVPDZ256rr:
7761   case X86::VDIVPDZ256rrk:
7762   case X86::VDIVPDZ256rrkz:
7763   case X86::VDIVPDZrrb:
7764   case X86::VDIVPDZrrbk:
7765   case X86::VDIVPDZrrbkz:
7766   case X86::VDIVPDZrm:
7767   case X86::VDIVPDZrmb:
7768   case X86::VDIVPDZrmbk:
7769   case X86::VDIVPDZrmbkz:
7770   case X86::VDIVPDZrmk:
7771   case X86::VDIVPDZrmkz:
7772   case X86::VDIVPDZrr:
7773   case X86::VDIVPDZrrk:
7774   case X86::VDIVPDZrrkz:
7775   case X86::VDIVPSZ128rm:
7776   case X86::VDIVPSZ128rmb:
7777   case X86::VDIVPSZ128rmbk:
7778   case X86::VDIVPSZ128rmbkz:
7779   case X86::VDIVPSZ128rmk:
7780   case X86::VDIVPSZ128rmkz:
7781   case X86::VDIVPSZ128rr:
7782   case X86::VDIVPSZ128rrk:
7783   case X86::VDIVPSZ128rrkz:
7784   case X86::VDIVPSZ256rm:
7785   case X86::VDIVPSZ256rmb:
7786   case X86::VDIVPSZ256rmbk:
7787   case X86::VDIVPSZ256rmbkz:
7788   case X86::VDIVPSZ256rmk:
7789   case X86::VDIVPSZ256rmkz:
7790   case X86::VDIVPSZ256rr:
7791   case X86::VDIVPSZ256rrk:
7792   case X86::VDIVPSZ256rrkz:
7793   case X86::VDIVPSZrrb:
7794   case X86::VDIVPSZrrbk:
7795   case X86::VDIVPSZrrbkz:
7796   case X86::VDIVPSZrm:
7797   case X86::VDIVPSZrmb:
7798   case X86::VDIVPSZrmbk:
7799   case X86::VDIVPSZrmbkz:
7800   case X86::VDIVPSZrmk:
7801   case X86::VDIVPSZrmkz:
7802   case X86::VDIVPSZrr:
7803   case X86::VDIVPSZrrk:
7804   case X86::VDIVPSZrrkz:
7805   case X86::VDIVSDZrm:
7806   case X86::VDIVSDZrr:
7807   case X86::VDIVSDZrm_Int:
7808   case X86::VDIVSDZrm_Intk:
7809   case X86::VDIVSDZrm_Intkz:
7810   case X86::VDIVSDZrr_Int:
7811   case X86::VDIVSDZrr_Intk:
7812   case X86::VDIVSDZrr_Intkz:
7813   case X86::VDIVSDZrrb_Int:
7814   case X86::VDIVSDZrrb_Intk:
7815   case X86::VDIVSDZrrb_Intkz:
7816   case X86::VDIVSSZrm:
7817   case X86::VDIVSSZrr:
7818   case X86::VDIVSSZrm_Int:
7819   case X86::VDIVSSZrm_Intk:
7820   case X86::VDIVSSZrm_Intkz:
7821   case X86::VDIVSSZrr_Int:
7822   case X86::VDIVSSZrr_Intk:
7823   case X86::VDIVSSZrr_Intkz:
7824   case X86::VDIVSSZrrb_Int:
7825   case X86::VDIVSSZrrb_Intk:
7826   case X86::VDIVSSZrrb_Intkz:
7827   case X86::VSQRTPDZ128m:
7828   case X86::VSQRTPDZ128mb:
7829   case X86::VSQRTPDZ128mbk:
7830   case X86::VSQRTPDZ128mbkz:
7831   case X86::VSQRTPDZ128mk:
7832   case X86::VSQRTPDZ128mkz:
7833   case X86::VSQRTPDZ128r:
7834   case X86::VSQRTPDZ128rk:
7835   case X86::VSQRTPDZ128rkz:
7836   case X86::VSQRTPDZ256m:
7837   case X86::VSQRTPDZ256mb:
7838   case X86::VSQRTPDZ256mbk:
7839   case X86::VSQRTPDZ256mbkz:
7840   case X86::VSQRTPDZ256mk:
7841   case X86::VSQRTPDZ256mkz:
7842   case X86::VSQRTPDZ256r:
7843   case X86::VSQRTPDZ256rk:
7844   case X86::VSQRTPDZ256rkz:
7845   case X86::VSQRTPDZm:
7846   case X86::VSQRTPDZmb:
7847   case X86::VSQRTPDZmbk:
7848   case X86::VSQRTPDZmbkz:
7849   case X86::VSQRTPDZmk:
7850   case X86::VSQRTPDZmkz:
7851   case X86::VSQRTPDZr:
7852   case X86::VSQRTPDZrb:
7853   case X86::VSQRTPDZrbk:
7854   case X86::VSQRTPDZrbkz:
7855   case X86::VSQRTPDZrk:
7856   case X86::VSQRTPDZrkz:
7857   case X86::VSQRTPSZ128m:
7858   case X86::VSQRTPSZ128mb:
7859   case X86::VSQRTPSZ128mbk:
7860   case X86::VSQRTPSZ128mbkz:
7861   case X86::VSQRTPSZ128mk:
7862   case X86::VSQRTPSZ128mkz:
7863   case X86::VSQRTPSZ128r:
7864   case X86::VSQRTPSZ128rk:
7865   case X86::VSQRTPSZ128rkz:
7866   case X86::VSQRTPSZ256m:
7867   case X86::VSQRTPSZ256mb:
7868   case X86::VSQRTPSZ256mbk:
7869   case X86::VSQRTPSZ256mbkz:
7870   case X86::VSQRTPSZ256mk:
7871   case X86::VSQRTPSZ256mkz:
7872   case X86::VSQRTPSZ256r:
7873   case X86::VSQRTPSZ256rk:
7874   case X86::VSQRTPSZ256rkz:
7875   case X86::VSQRTPSZm:
7876   case X86::VSQRTPSZmb:
7877   case X86::VSQRTPSZmbk:
7878   case X86::VSQRTPSZmbkz:
7879   case X86::VSQRTPSZmk:
7880   case X86::VSQRTPSZmkz:
7881   case X86::VSQRTPSZr:
7882   case X86::VSQRTPSZrb:
7883   case X86::VSQRTPSZrbk:
7884   case X86::VSQRTPSZrbkz:
7885   case X86::VSQRTPSZrk:
7886   case X86::VSQRTPSZrkz:
7887   case X86::VSQRTSDZm:
7888   case X86::VSQRTSDZm_Int:
7889   case X86::VSQRTSDZm_Intk:
7890   case X86::VSQRTSDZm_Intkz:
7891   case X86::VSQRTSDZr:
7892   case X86::VSQRTSDZr_Int:
7893   case X86::VSQRTSDZr_Intk:
7894   case X86::VSQRTSDZr_Intkz:
7895   case X86::VSQRTSDZrb_Int:
7896   case X86::VSQRTSDZrb_Intk:
7897   case X86::VSQRTSDZrb_Intkz:
7898   case X86::VSQRTSSZm:
7899   case X86::VSQRTSSZm_Int:
7900   case X86::VSQRTSSZm_Intk:
7901   case X86::VSQRTSSZm_Intkz:
7902   case X86::VSQRTSSZr:
7903   case X86::VSQRTSSZr_Int:
7904   case X86::VSQRTSSZr_Intk:
7905   case X86::VSQRTSSZr_Intkz:
7906   case X86::VSQRTSSZrb_Int:
7907   case X86::VSQRTSSZrb_Intk:
7908   case X86::VSQRTSSZrb_Intkz:
7909 
7910   case X86::VGATHERDPDYrm:
7911   case X86::VGATHERDPDZ128rm:
7912   case X86::VGATHERDPDZ256rm:
7913   case X86::VGATHERDPDZrm:
7914   case X86::VGATHERDPDrm:
7915   case X86::VGATHERDPSYrm:
7916   case X86::VGATHERDPSZ128rm:
7917   case X86::VGATHERDPSZ256rm:
7918   case X86::VGATHERDPSZrm:
7919   case X86::VGATHERDPSrm:
7920   case X86::VGATHERPF0DPDm:
7921   case X86::VGATHERPF0DPSm:
7922   case X86::VGATHERPF0QPDm:
7923   case X86::VGATHERPF0QPSm:
7924   case X86::VGATHERPF1DPDm:
7925   case X86::VGATHERPF1DPSm:
7926   case X86::VGATHERPF1QPDm:
7927   case X86::VGATHERPF1QPSm:
7928   case X86::VGATHERQPDYrm:
7929   case X86::VGATHERQPDZ128rm:
7930   case X86::VGATHERQPDZ256rm:
7931   case X86::VGATHERQPDZrm:
7932   case X86::VGATHERQPDrm:
7933   case X86::VGATHERQPSYrm:
7934   case X86::VGATHERQPSZ128rm:
7935   case X86::VGATHERQPSZ256rm:
7936   case X86::VGATHERQPSZrm:
7937   case X86::VGATHERQPSrm:
7938   case X86::VPGATHERDDYrm:
7939   case X86::VPGATHERDDZ128rm:
7940   case X86::VPGATHERDDZ256rm:
7941   case X86::VPGATHERDDZrm:
7942   case X86::VPGATHERDDrm:
7943   case X86::VPGATHERDQYrm:
7944   case X86::VPGATHERDQZ128rm:
7945   case X86::VPGATHERDQZ256rm:
7946   case X86::VPGATHERDQZrm:
7947   case X86::VPGATHERDQrm:
7948   case X86::VPGATHERQDYrm:
7949   case X86::VPGATHERQDZ128rm:
7950   case X86::VPGATHERQDZ256rm:
7951   case X86::VPGATHERQDZrm:
7952   case X86::VPGATHERQDrm:
7953   case X86::VPGATHERQQYrm:
7954   case X86::VPGATHERQQZ128rm:
7955   case X86::VPGATHERQQZ256rm:
7956   case X86::VPGATHERQQZrm:
7957   case X86::VPGATHERQQrm:
7958   case X86::VSCATTERDPDZ128mr:
7959   case X86::VSCATTERDPDZ256mr:
7960   case X86::VSCATTERDPDZmr:
7961   case X86::VSCATTERDPSZ128mr:
7962   case X86::VSCATTERDPSZ256mr:
7963   case X86::VSCATTERDPSZmr:
7964   case X86::VSCATTERPF0DPDm:
7965   case X86::VSCATTERPF0DPSm:
7966   case X86::VSCATTERPF0QPDm:
7967   case X86::VSCATTERPF0QPSm:
7968   case X86::VSCATTERPF1DPDm:
7969   case X86::VSCATTERPF1DPSm:
7970   case X86::VSCATTERPF1QPDm:
7971   case X86::VSCATTERPF1QPSm:
7972   case X86::VSCATTERQPDZ128mr:
7973   case X86::VSCATTERQPDZ256mr:
7974   case X86::VSCATTERQPDZmr:
7975   case X86::VSCATTERQPSZ128mr:
7976   case X86::VSCATTERQPSZ256mr:
7977   case X86::VSCATTERQPSZmr:
7978   case X86::VPSCATTERDDZ128mr:
7979   case X86::VPSCATTERDDZ256mr:
7980   case X86::VPSCATTERDDZmr:
7981   case X86::VPSCATTERDQZ128mr:
7982   case X86::VPSCATTERDQZ256mr:
7983   case X86::VPSCATTERDQZmr:
7984   case X86::VPSCATTERQDZ128mr:
7985   case X86::VPSCATTERQDZ256mr:
7986   case X86::VPSCATTERQDZmr:
7987   case X86::VPSCATTERQQZ128mr:
7988   case X86::VPSCATTERQQZ256mr:
7989   case X86::VPSCATTERQQZmr:
7990     return true;
7991   }
7992 }
7993 
7994 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7995                                          const MachineRegisterInfo *MRI,
7996                                          const MachineInstr &DefMI,
7997                                          unsigned DefIdx,
7998                                          const MachineInstr &UseMI,
7999                                          unsigned UseIdx) const {
8000   return isHighLatencyDef(DefMI.getOpcode());
8001 }
8002 
8003 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
8004                                            const MachineBasicBlock *MBB) const {
8005   assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
8006          Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
8007 
8008   // Integer binary math/logic instructions have a third source operand:
8009   // the EFLAGS register. That operand must be both defined here and never
8010   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
8011   // not change anything because rearranging the operands could affect other
8012   // instructions that depend on the exact status flags (zero, sign, etc.)
8013   // that are set by using these particular operands with this operation.
8014   const MachineOperand *FlagDef = Inst.findRegisterDefOperand(X86::EFLAGS);
8015   assert((Inst.getNumDefs() == 1 || FlagDef) &&
8016          "Implicit def isn't flags?");
8017   if (FlagDef && !FlagDef->isDead())
8018     return false;
8019 
8020   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
8021 }
8022 
8023 // TODO: There are many more machine instruction opcodes to match:
8024 //       1. Other data types (integer, vectors)
8025 //       2. Other math / logic operations (xor, or)
8026 //       3. Other forms of the same operation (intrinsics and other variants)
8027 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
8028   switch (Inst.getOpcode()) {
8029   case X86::AND8rr:
8030   case X86::AND16rr:
8031   case X86::AND32rr:
8032   case X86::AND64rr:
8033   case X86::OR8rr:
8034   case X86::OR16rr:
8035   case X86::OR32rr:
8036   case X86::OR64rr:
8037   case X86::XOR8rr:
8038   case X86::XOR16rr:
8039   case X86::XOR32rr:
8040   case X86::XOR64rr:
8041   case X86::IMUL16rr:
8042   case X86::IMUL32rr:
8043   case X86::IMUL64rr:
8044   case X86::PANDrr:
8045   case X86::PORrr:
8046   case X86::PXORrr:
8047   case X86::ANDPDrr:
8048   case X86::ANDPSrr:
8049   case X86::ORPDrr:
8050   case X86::ORPSrr:
8051   case X86::XORPDrr:
8052   case X86::XORPSrr:
8053   case X86::PADDBrr:
8054   case X86::PADDWrr:
8055   case X86::PADDDrr:
8056   case X86::PADDQrr:
8057   case X86::PMULLWrr:
8058   case X86::PMULLDrr:
8059   case X86::PMAXSBrr:
8060   case X86::PMAXSDrr:
8061   case X86::PMAXSWrr:
8062   case X86::PMAXUBrr:
8063   case X86::PMAXUDrr:
8064   case X86::PMAXUWrr:
8065   case X86::PMINSBrr:
8066   case X86::PMINSDrr:
8067   case X86::PMINSWrr:
8068   case X86::PMINUBrr:
8069   case X86::PMINUDrr:
8070   case X86::PMINUWrr:
8071   case X86::VPANDrr:
8072   case X86::VPANDYrr:
8073   case X86::VPANDDZ128rr:
8074   case X86::VPANDDZ256rr:
8075   case X86::VPANDDZrr:
8076   case X86::VPANDQZ128rr:
8077   case X86::VPANDQZ256rr:
8078   case X86::VPANDQZrr:
8079   case X86::VPORrr:
8080   case X86::VPORYrr:
8081   case X86::VPORDZ128rr:
8082   case X86::VPORDZ256rr:
8083   case X86::VPORDZrr:
8084   case X86::VPORQZ128rr:
8085   case X86::VPORQZ256rr:
8086   case X86::VPORQZrr:
8087   case X86::VPXORrr:
8088   case X86::VPXORYrr:
8089   case X86::VPXORDZ128rr:
8090   case X86::VPXORDZ256rr:
8091   case X86::VPXORDZrr:
8092   case X86::VPXORQZ128rr:
8093   case X86::VPXORQZ256rr:
8094   case X86::VPXORQZrr:
8095   case X86::VANDPDrr:
8096   case X86::VANDPSrr:
8097   case X86::VANDPDYrr:
8098   case X86::VANDPSYrr:
8099   case X86::VANDPDZ128rr:
8100   case X86::VANDPSZ128rr:
8101   case X86::VANDPDZ256rr:
8102   case X86::VANDPSZ256rr:
8103   case X86::VANDPDZrr:
8104   case X86::VANDPSZrr:
8105   case X86::VORPDrr:
8106   case X86::VORPSrr:
8107   case X86::VORPDYrr:
8108   case X86::VORPSYrr:
8109   case X86::VORPDZ128rr:
8110   case X86::VORPSZ128rr:
8111   case X86::VORPDZ256rr:
8112   case X86::VORPSZ256rr:
8113   case X86::VORPDZrr:
8114   case X86::VORPSZrr:
8115   case X86::VXORPDrr:
8116   case X86::VXORPSrr:
8117   case X86::VXORPDYrr:
8118   case X86::VXORPSYrr:
8119   case X86::VXORPDZ128rr:
8120   case X86::VXORPSZ128rr:
8121   case X86::VXORPDZ256rr:
8122   case X86::VXORPSZ256rr:
8123   case X86::VXORPDZrr:
8124   case X86::VXORPSZrr:
8125   case X86::KADDBrr:
8126   case X86::KADDWrr:
8127   case X86::KADDDrr:
8128   case X86::KADDQrr:
8129   case X86::KANDBrr:
8130   case X86::KANDWrr:
8131   case X86::KANDDrr:
8132   case X86::KANDQrr:
8133   case X86::KORBrr:
8134   case X86::KORWrr:
8135   case X86::KORDrr:
8136   case X86::KORQrr:
8137   case X86::KXORBrr:
8138   case X86::KXORWrr:
8139   case X86::KXORDrr:
8140   case X86::KXORQrr:
8141   case X86::VPADDBrr:
8142   case X86::VPADDWrr:
8143   case X86::VPADDDrr:
8144   case X86::VPADDQrr:
8145   case X86::VPADDBYrr:
8146   case X86::VPADDWYrr:
8147   case X86::VPADDDYrr:
8148   case X86::VPADDQYrr:
8149   case X86::VPADDBZ128rr:
8150   case X86::VPADDWZ128rr:
8151   case X86::VPADDDZ128rr:
8152   case X86::VPADDQZ128rr:
8153   case X86::VPADDBZ256rr:
8154   case X86::VPADDWZ256rr:
8155   case X86::VPADDDZ256rr:
8156   case X86::VPADDQZ256rr:
8157   case X86::VPADDBZrr:
8158   case X86::VPADDWZrr:
8159   case X86::VPADDDZrr:
8160   case X86::VPADDQZrr:
8161   case X86::VPMULLWrr:
8162   case X86::VPMULLWYrr:
8163   case X86::VPMULLWZ128rr:
8164   case X86::VPMULLWZ256rr:
8165   case X86::VPMULLWZrr:
8166   case X86::VPMULLDrr:
8167   case X86::VPMULLDYrr:
8168   case X86::VPMULLDZ128rr:
8169   case X86::VPMULLDZ256rr:
8170   case X86::VPMULLDZrr:
8171   case X86::VPMULLQZ128rr:
8172   case X86::VPMULLQZ256rr:
8173   case X86::VPMULLQZrr:
8174   case X86::VPMAXSBrr:
8175   case X86::VPMAXSBYrr:
8176   case X86::VPMAXSBZ128rr:
8177   case X86::VPMAXSBZ256rr:
8178   case X86::VPMAXSBZrr:
8179   case X86::VPMAXSDrr:
8180   case X86::VPMAXSDYrr:
8181   case X86::VPMAXSDZ128rr:
8182   case X86::VPMAXSDZ256rr:
8183   case X86::VPMAXSDZrr:
8184   case X86::VPMAXSQZ128rr:
8185   case X86::VPMAXSQZ256rr:
8186   case X86::VPMAXSQZrr:
8187   case X86::VPMAXSWrr:
8188   case X86::VPMAXSWYrr:
8189   case X86::VPMAXSWZ128rr:
8190   case X86::VPMAXSWZ256rr:
8191   case X86::VPMAXSWZrr:
8192   case X86::VPMAXUBrr:
8193   case X86::VPMAXUBYrr:
8194   case X86::VPMAXUBZ128rr:
8195   case X86::VPMAXUBZ256rr:
8196   case X86::VPMAXUBZrr:
8197   case X86::VPMAXUDrr:
8198   case X86::VPMAXUDYrr:
8199   case X86::VPMAXUDZ128rr:
8200   case X86::VPMAXUDZ256rr:
8201   case X86::VPMAXUDZrr:
8202   case X86::VPMAXUQZ128rr:
8203   case X86::VPMAXUQZ256rr:
8204   case X86::VPMAXUQZrr:
8205   case X86::VPMAXUWrr:
8206   case X86::VPMAXUWYrr:
8207   case X86::VPMAXUWZ128rr:
8208   case X86::VPMAXUWZ256rr:
8209   case X86::VPMAXUWZrr:
8210   case X86::VPMINSBrr:
8211   case X86::VPMINSBYrr:
8212   case X86::VPMINSBZ128rr:
8213   case X86::VPMINSBZ256rr:
8214   case X86::VPMINSBZrr:
8215   case X86::VPMINSDrr:
8216   case X86::VPMINSDYrr:
8217   case X86::VPMINSDZ128rr:
8218   case X86::VPMINSDZ256rr:
8219   case X86::VPMINSDZrr:
8220   case X86::VPMINSQZ128rr:
8221   case X86::VPMINSQZ256rr:
8222   case X86::VPMINSQZrr:
8223   case X86::VPMINSWrr:
8224   case X86::VPMINSWYrr:
8225   case X86::VPMINSWZ128rr:
8226   case X86::VPMINSWZ256rr:
8227   case X86::VPMINSWZrr:
8228   case X86::VPMINUBrr:
8229   case X86::VPMINUBYrr:
8230   case X86::VPMINUBZ128rr:
8231   case X86::VPMINUBZ256rr:
8232   case X86::VPMINUBZrr:
8233   case X86::VPMINUDrr:
8234   case X86::VPMINUDYrr:
8235   case X86::VPMINUDZ128rr:
8236   case X86::VPMINUDZ256rr:
8237   case X86::VPMINUDZrr:
8238   case X86::VPMINUQZ128rr:
8239   case X86::VPMINUQZ256rr:
8240   case X86::VPMINUQZrr:
8241   case X86::VPMINUWrr:
8242   case X86::VPMINUWYrr:
8243   case X86::VPMINUWZ128rr:
8244   case X86::VPMINUWZ256rr:
8245   case X86::VPMINUWZrr:
8246   // Normal min/max instructions are not commutative because of NaN and signed
8247   // zero semantics, but these are. Thus, there's no need to check for global
8248   // relaxed math; the instructions themselves have the properties we need.
8249   case X86::MAXCPDrr:
8250   case X86::MAXCPSrr:
8251   case X86::MAXCSDrr:
8252   case X86::MAXCSSrr:
8253   case X86::MINCPDrr:
8254   case X86::MINCPSrr:
8255   case X86::MINCSDrr:
8256   case X86::MINCSSrr:
8257   case X86::VMAXCPDrr:
8258   case X86::VMAXCPSrr:
8259   case X86::VMAXCPDYrr:
8260   case X86::VMAXCPSYrr:
8261   case X86::VMAXCPDZ128rr:
8262   case X86::VMAXCPSZ128rr:
8263   case X86::VMAXCPDZ256rr:
8264   case X86::VMAXCPSZ256rr:
8265   case X86::VMAXCPDZrr:
8266   case X86::VMAXCPSZrr:
8267   case X86::VMAXCSDrr:
8268   case X86::VMAXCSSrr:
8269   case X86::VMAXCSDZrr:
8270   case X86::VMAXCSSZrr:
8271   case X86::VMINCPDrr:
8272   case X86::VMINCPSrr:
8273   case X86::VMINCPDYrr:
8274   case X86::VMINCPSYrr:
8275   case X86::VMINCPDZ128rr:
8276   case X86::VMINCPSZ128rr:
8277   case X86::VMINCPDZ256rr:
8278   case X86::VMINCPSZ256rr:
8279   case X86::VMINCPDZrr:
8280   case X86::VMINCPSZrr:
8281   case X86::VMINCSDrr:
8282   case X86::VMINCSSrr:
8283   case X86::VMINCSDZrr:
8284   case X86::VMINCSSZrr:
8285     return true;
8286   case X86::ADDPDrr:
8287   case X86::ADDPSrr:
8288   case X86::ADDSDrr:
8289   case X86::ADDSSrr:
8290   case X86::MULPDrr:
8291   case X86::MULPSrr:
8292   case X86::MULSDrr:
8293   case X86::MULSSrr:
8294   case X86::VADDPDrr:
8295   case X86::VADDPSrr:
8296   case X86::VADDPDYrr:
8297   case X86::VADDPSYrr:
8298   case X86::VADDPDZ128rr:
8299   case X86::VADDPSZ128rr:
8300   case X86::VADDPDZ256rr:
8301   case X86::VADDPSZ256rr:
8302   case X86::VADDPDZrr:
8303   case X86::VADDPSZrr:
8304   case X86::VADDSDrr:
8305   case X86::VADDSSrr:
8306   case X86::VADDSDZrr:
8307   case X86::VADDSSZrr:
8308   case X86::VMULPDrr:
8309   case X86::VMULPSrr:
8310   case X86::VMULPDYrr:
8311   case X86::VMULPSYrr:
8312   case X86::VMULPDZ128rr:
8313   case X86::VMULPSZ128rr:
8314   case X86::VMULPDZ256rr:
8315   case X86::VMULPSZ256rr:
8316   case X86::VMULPDZrr:
8317   case X86::VMULPSZrr:
8318   case X86::VMULSDrr:
8319   case X86::VMULSSrr:
8320   case X86::VMULSDZrr:
8321   case X86::VMULSSZrr:
8322     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
8323            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
8324   default:
8325     return false;
8326   }
8327 }
8328 
8329 /// If \p DescribedReg overlaps with the MOVrr instruction's destination
8330 /// register then, if possible, describe the value in terms of the source
8331 /// register.
8332 static Optional<ParamLoadedValue>
8333 describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
8334                          const TargetRegisterInfo *TRI) {
8335   Register DestReg = MI.getOperand(0).getReg();
8336   Register SrcReg = MI.getOperand(1).getReg();
8337 
8338   auto Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8339 
8340   // If the described register is the destination, just return the source.
8341   if (DestReg == DescribedReg)
8342     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8343 
8344   // If the described register is a sub-register of the destination register,
8345   // then pick out the source register's corresponding sub-register.
8346   if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) {
8347     Register SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx);
8348     return ParamLoadedValue(MachineOperand::CreateReg(SrcSubReg, false), Expr);
8349   }
8350 
8351   // The remaining case to consider is when the described register is a
8352   // super-register of the destination register. MOV8rr and MOV16rr does not
8353   // write to any of the other bytes in the register, meaning that we'd have to
8354   // describe the value using a combination of the source register and the
8355   // non-overlapping bits in the described register, which is not currently
8356   // possible.
8357   if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
8358       !TRI->isSuperRegister(DestReg, DescribedReg))
8359     return None;
8360 
8361   assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
8362   return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8363 }
8364 
8365 Optional<ParamLoadedValue>
8366 X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
8367   const MachineOperand *Op = nullptr;
8368   DIExpression *Expr = nullptr;
8369 
8370   const TargetRegisterInfo *TRI = &getRegisterInfo();
8371 
8372   switch (MI.getOpcode()) {
8373   case X86::LEA32r:
8374   case X86::LEA64r:
8375   case X86::LEA64_32r: {
8376     // We may need to describe a 64-bit parameter with a 32-bit LEA.
8377     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8378       return None;
8379 
8380     // Operand 4 could be global address. For now we do not support
8381     // such situation.
8382     if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
8383       return None;
8384 
8385     const MachineOperand &Op1 = MI.getOperand(1);
8386     const MachineOperand &Op2 = MI.getOperand(3);
8387     assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
8388                            Register::isPhysicalRegister(Op2.getReg())));
8389 
8390     // Omit situations like:
8391     // %rsi = lea %rsi, 4, ...
8392     if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
8393         Op2.getReg() == MI.getOperand(0).getReg())
8394       return None;
8395     else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
8396               TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
8397              (Op2.getReg() != X86::NoRegister &&
8398               TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
8399       return None;
8400 
8401     int64_t Coef = MI.getOperand(2).getImm();
8402     int64_t Offset = MI.getOperand(4).getImm();
8403     SmallVector<uint64_t, 8> Ops;
8404 
8405     if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
8406       Op = &Op1;
8407     } else if (Op1.isFI())
8408       Op = &Op1;
8409 
8410     if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
8411       Ops.push_back(dwarf::DW_OP_constu);
8412       Ops.push_back(Coef + 1);
8413       Ops.push_back(dwarf::DW_OP_mul);
8414     } else {
8415       if (Op && Op2.getReg() != X86::NoRegister) {
8416         int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
8417         if (dwarfReg < 0)
8418           return None;
8419         else if (dwarfReg < 32) {
8420           Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
8421           Ops.push_back(0);
8422         } else {
8423           Ops.push_back(dwarf::DW_OP_bregx);
8424           Ops.push_back(dwarfReg);
8425           Ops.push_back(0);
8426         }
8427       } else if (!Op) {
8428         assert(Op2.getReg() != X86::NoRegister);
8429         Op = &Op2;
8430       }
8431 
8432       if (Coef > 1) {
8433         assert(Op2.getReg() != X86::NoRegister);
8434         Ops.push_back(dwarf::DW_OP_constu);
8435         Ops.push_back(Coef);
8436         Ops.push_back(dwarf::DW_OP_mul);
8437       }
8438 
8439       if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
8440           Op2.getReg() != X86::NoRegister) {
8441         Ops.push_back(dwarf::DW_OP_plus);
8442       }
8443     }
8444 
8445     DIExpression::appendOffset(Ops, Offset);
8446     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
8447 
8448     return ParamLoadedValue(*Op, Expr);;
8449   }
8450   case X86::MOV8ri:
8451   case X86::MOV16ri:
8452     // TODO: Handle MOV8ri and MOV16ri.
8453     return None;
8454   case X86::MOV32ri:
8455   case X86::MOV64ri:
8456   case X86::MOV64ri32:
8457     // MOV32ri may be used for producing zero-extended 32-bit immediates in
8458     // 64-bit parameters, so we need to consider super-registers.
8459     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8460       return None;
8461     return ParamLoadedValue(MI.getOperand(1), Expr);
8462   case X86::MOV8rr:
8463   case X86::MOV16rr:
8464   case X86::MOV32rr:
8465   case X86::MOV64rr:
8466     return describeMOVrrLoadedValue(MI, Reg, TRI);
8467   case X86::XOR32rr: {
8468     // 64-bit parameters are zero-materialized using XOR32rr, so also consider
8469     // super-registers.
8470     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8471       return None;
8472     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
8473       return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
8474     return None;
8475   }
8476   case X86::MOVSX64rr32: {
8477     // We may need to describe the lower 32 bits of the MOVSX; for example, in
8478     // cases like this:
8479     //
8480     //  $ebx = [...]
8481     //  $rdi = MOVSX64rr32 $ebx
8482     //  $esi = MOV32rr $edi
8483     if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg))
8484       return None;
8485 
8486     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8487 
8488     // If the described register is the destination register we need to
8489     // sign-extend the source register from 32 bits. The other case we handle
8490     // is when the described register is the 32-bit sub-register of the
8491     // destination register, in case we just need to return the source
8492     // register.
8493     if (Reg == MI.getOperand(0).getReg())
8494       Expr = DIExpression::appendExt(Expr, 32, 64, true);
8495     else
8496       assert(X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg) &&
8497              "Unhandled sub-register case for MOVSX64rr32");
8498 
8499     return ParamLoadedValue(MI.getOperand(1), Expr);
8500   }
8501   default:
8502     assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
8503     return TargetInstrInfo::describeLoadedValue(MI, Reg);
8504   }
8505 }
8506 
8507 /// This is an architecture-specific helper function of reassociateOps.
8508 /// Set special operand attributes for new instructions after reassociation.
8509 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
8510                                          MachineInstr &OldMI2,
8511                                          MachineInstr &NewMI1,
8512                                          MachineInstr &NewMI2) const {
8513   // Propagate FP flags from the original instructions.
8514   // But clear poison-generating flags because those may not be valid now.
8515   // TODO: There should be a helper function for copying only fast-math-flags.
8516   uint16_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
8517   NewMI1.setFlags(IntersectedFlags);
8518   NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
8519   NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
8520   NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
8521 
8522   NewMI2.setFlags(IntersectedFlags);
8523   NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
8524   NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
8525   NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
8526 
8527   // Integer instructions may define an implicit EFLAGS dest register operand.
8528   MachineOperand *OldFlagDef1 = OldMI1.findRegisterDefOperand(X86::EFLAGS);
8529   MachineOperand *OldFlagDef2 = OldMI2.findRegisterDefOperand(X86::EFLAGS);
8530 
8531   assert(!OldFlagDef1 == !OldFlagDef2 &&
8532          "Unexpected instruction type for reassociation");
8533 
8534   if (!OldFlagDef1 || !OldFlagDef2)
8535     return;
8536 
8537   assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
8538          "Must have dead EFLAGS operand in reassociable instruction");
8539 
8540   MachineOperand *NewFlagDef1 = NewMI1.findRegisterDefOperand(X86::EFLAGS);
8541   MachineOperand *NewFlagDef2 = NewMI2.findRegisterDefOperand(X86::EFLAGS);
8542 
8543   assert(NewFlagDef1 && NewFlagDef2 &&
8544          "Unexpected operand in reassociable instruction");
8545 
8546   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8547   // of this pass or other passes. The EFLAGS operands must be dead in these new
8548   // instructions because the EFLAGS operands in the original instructions must
8549   // be dead in order for reassociation to occur.
8550   NewFlagDef1->setIsDead();
8551   NewFlagDef2->setIsDead();
8552 }
8553 
8554 std::pair<unsigned, unsigned>
8555 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8556   return std::make_pair(TF, 0u);
8557 }
8558 
8559 ArrayRef<std::pair<unsigned, const char *>>
8560 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8561   using namespace X86II;
8562   static const std::pair<unsigned, const char *> TargetFlags[] = {
8563       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8564       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
8565       {MO_GOT, "x86-got"},
8566       {MO_GOTOFF, "x86-gotoff"},
8567       {MO_GOTPCREL, "x86-gotpcrel"},
8568       {MO_PLT, "x86-plt"},
8569       {MO_TLSGD, "x86-tlsgd"},
8570       {MO_TLSLD, "x86-tlsld"},
8571       {MO_TLSLDM, "x86-tlsldm"},
8572       {MO_GOTTPOFF, "x86-gottpoff"},
8573       {MO_INDNTPOFF, "x86-indntpoff"},
8574       {MO_TPOFF, "x86-tpoff"},
8575       {MO_DTPOFF, "x86-dtpoff"},
8576       {MO_NTPOFF, "x86-ntpoff"},
8577       {MO_GOTNTPOFF, "x86-gotntpoff"},
8578       {MO_DLLIMPORT, "x86-dllimport"},
8579       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
8580       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
8581       {MO_TLVP, "x86-tlvp"},
8582       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
8583       {MO_SECREL, "x86-secrel"},
8584       {MO_COFFSTUB, "x86-coffstub"}};
8585   return makeArrayRef(TargetFlags);
8586 }
8587 
8588 namespace {
8589   /// Create Global Base Reg pass. This initializes the PIC
8590   /// global base register for x86-32.
8591   struct CGBR : public MachineFunctionPass {
8592     static char ID;
8593     CGBR() : MachineFunctionPass(ID) {}
8594 
8595     bool runOnMachineFunction(MachineFunction &MF) override {
8596       const X86TargetMachine *TM =
8597         static_cast<const X86TargetMachine *>(&MF.getTarget());
8598       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
8599 
8600       // Don't do anything in the 64-bit small and kernel code models. They use
8601       // RIP-relative addressing for everything.
8602       if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
8603                             TM->getCodeModel() == CodeModel::Kernel))
8604         return false;
8605 
8606       // Only emit a global base reg in PIC mode.
8607       if (!TM->isPositionIndependent())
8608         return false;
8609 
8610       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8611       Register GlobalBaseReg = X86FI->getGlobalBaseReg();
8612 
8613       // If we didn't need a GlobalBaseReg, don't insert code.
8614       if (GlobalBaseReg == 0)
8615         return false;
8616 
8617       // Insert the set of GlobalBaseReg into the first MBB of the function
8618       MachineBasicBlock &FirstMBB = MF.front();
8619       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
8620       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
8621       MachineRegisterInfo &RegInfo = MF.getRegInfo();
8622       const X86InstrInfo *TII = STI.getInstrInfo();
8623 
8624       Register PC;
8625       if (STI.isPICStyleGOT())
8626         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
8627       else
8628         PC = GlobalBaseReg;
8629 
8630       if (STI.is64Bit()) {
8631         if (TM->getCodeModel() == CodeModel::Medium) {
8632           // In the medium code model, use a RIP-relative LEA to materialize the
8633           // GOT.
8634           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
8635               .addReg(X86::RIP)
8636               .addImm(0)
8637               .addReg(0)
8638               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
8639               .addReg(0);
8640         } else if (TM->getCodeModel() == CodeModel::Large) {
8641           // In the large code model, we are aiming for this code, though the
8642           // register allocation may vary:
8643           //   leaq .LN$pb(%rip), %rax
8644           //   movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
8645           //   addq %rcx, %rax
8646           // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
8647           Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8648           Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8649           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
8650               .addReg(X86::RIP)
8651               .addImm(0)
8652               .addReg(0)
8653               .addSym(MF.getPICBaseSymbol())
8654               .addReg(0);
8655           std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
8656           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
8657               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8658                                  X86II::MO_PIC_BASE_OFFSET);
8659           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
8660               .addReg(PBReg, RegState::Kill)
8661               .addReg(GOTReg, RegState::Kill);
8662         } else {
8663           llvm_unreachable("unexpected code model");
8664         }
8665       } else {
8666         // Operand of MovePCtoStack is completely ignored by asm printer. It's
8667         // only used in JIT code emission as displacement to pc.
8668         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
8669 
8670         // If we're using vanilla 'GOT' PIC style, we should use relative
8671         // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
8672         if (STI.isPICStyleGOT()) {
8673           // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
8674           // %some_register
8675           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
8676               .addReg(PC)
8677               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8678                                  X86II::MO_GOT_ABSOLUTE_ADDRESS);
8679         }
8680       }
8681 
8682       return true;
8683     }
8684 
8685     StringRef getPassName() const override {
8686       return "X86 PIC Global Base Reg Initialization";
8687     }
8688 
8689     void getAnalysisUsage(AnalysisUsage &AU) const override {
8690       AU.setPreservesCFG();
8691       MachineFunctionPass::getAnalysisUsage(AU);
8692     }
8693   };
8694 } // namespace
8695 
8696 char CGBR::ID = 0;
8697 FunctionPass*
8698 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
8699 
8700 namespace {
8701   struct LDTLSCleanup : public MachineFunctionPass {
8702     static char ID;
8703     LDTLSCleanup() : MachineFunctionPass(ID) {}
8704 
8705     bool runOnMachineFunction(MachineFunction &MF) override {
8706       if (skipFunction(MF.getFunction()))
8707         return false;
8708 
8709       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
8710       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8711         // No point folding accesses if there isn't at least two.
8712         return false;
8713       }
8714 
8715       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8716       return VisitNode(DT->getRootNode(), 0);
8717     }
8718 
8719     // Visit the dominator subtree rooted at Node in pre-order.
8720     // If TLSBaseAddrReg is non-null, then use that to replace any
8721     // TLS_base_addr instructions. Otherwise, create the register
8722     // when the first such instruction is seen, and then use it
8723     // as we encounter more instructions.
8724     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8725       MachineBasicBlock *BB = Node->getBlock();
8726       bool Changed = false;
8727 
8728       // Traverse the current block.
8729       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8730            ++I) {
8731         switch (I->getOpcode()) {
8732           case X86::TLS_base_addr32:
8733           case X86::TLS_base_addr64:
8734             if (TLSBaseAddrReg)
8735               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
8736             else
8737               I = SetRegister(*I, &TLSBaseAddrReg);
8738             Changed = true;
8739             break;
8740           default:
8741             break;
8742         }
8743       }
8744 
8745       // Visit the children of this block in the dominator tree.
8746       for (auto I = Node->begin(), E = Node->end(); I != E; ++I) {
8747         Changed |= VisitNode(*I, TLSBaseAddrReg);
8748       }
8749 
8750       return Changed;
8751     }
8752 
8753     // Replace the TLS_base_addr instruction I with a copy from
8754     // TLSBaseAddrReg, returning the new instruction.
8755     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
8756                                          unsigned TLSBaseAddrReg) {
8757       MachineFunction *MF = I.getParent()->getParent();
8758       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8759       const bool is64Bit = STI.is64Bit();
8760       const X86InstrInfo *TII = STI.getInstrInfo();
8761 
8762       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
8763       MachineInstr *Copy =
8764           BuildMI(*I.getParent(), I, I.getDebugLoc(),
8765                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8766               .addReg(TLSBaseAddrReg);
8767 
8768       // Erase the TLS_base_addr instruction.
8769       I.eraseFromParent();
8770 
8771       return Copy;
8772     }
8773 
8774     // Create a virtual register in *TLSBaseAddrReg, and populate it by
8775     // inserting a copy instruction after I. Returns the new instruction.
8776     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8777       MachineFunction *MF = I.getParent()->getParent();
8778       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8779       const bool is64Bit = STI.is64Bit();
8780       const X86InstrInfo *TII = STI.getInstrInfo();
8781 
8782       // Create a virtual register for the TLS base address.
8783       MachineRegisterInfo &RegInfo = MF->getRegInfo();
8784       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8785                                                       ? &X86::GR64RegClass
8786                                                       : &X86::GR32RegClass);
8787 
8788       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
8789       MachineInstr *Next = I.getNextNode();
8790       MachineInstr *Copy =
8791           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8792                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8793               .addReg(is64Bit ? X86::RAX : X86::EAX);
8794 
8795       return Copy;
8796     }
8797 
8798     StringRef getPassName() const override {
8799       return "Local Dynamic TLS Access Clean-up";
8800     }
8801 
8802     void getAnalysisUsage(AnalysisUsage &AU) const override {
8803       AU.setPreservesCFG();
8804       AU.addRequired<MachineDominatorTree>();
8805       MachineFunctionPass::getAnalysisUsage(AU);
8806     }
8807   };
8808 }
8809 
8810 char LDTLSCleanup::ID = 0;
8811 FunctionPass*
8812 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
8813 
8814 /// Constants defining how certain sequences should be outlined.
8815 ///
8816 /// \p MachineOutlinerDefault implies that the function is called with a call
8817 /// instruction, and a return must be emitted for the outlined function frame.
8818 ///
8819 /// That is,
8820 ///
8821 /// I1                                 OUTLINED_FUNCTION:
8822 /// I2 --> call OUTLINED_FUNCTION       I1
8823 /// I3                                  I2
8824 ///                                     I3
8825 ///                                     ret
8826 ///
8827 /// * Call construction overhead: 1 (call instruction)
8828 /// * Frame construction overhead: 1 (return instruction)
8829 ///
8830 /// \p MachineOutlinerTailCall implies that the function is being tail called.
8831 /// A jump is emitted instead of a call, and the return is already present in
8832 /// the outlined sequence. That is,
8833 ///
8834 /// I1                                 OUTLINED_FUNCTION:
8835 /// I2 --> jmp OUTLINED_FUNCTION       I1
8836 /// ret                                I2
8837 ///                                    ret
8838 ///
8839 /// * Call construction overhead: 1 (jump instruction)
8840 /// * Frame construction overhead: 0 (don't need to return)
8841 ///
8842 enum MachineOutlinerClass {
8843   MachineOutlinerDefault,
8844   MachineOutlinerTailCall
8845 };
8846 
8847 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
8848     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
8849   unsigned SequenceSize =
8850       std::accumulate(RepeatedSequenceLocs[0].front(),
8851                       std::next(RepeatedSequenceLocs[0].back()), 0,
8852                       [](unsigned Sum, const MachineInstr &MI) {
8853                         // FIXME: x86 doesn't implement getInstSizeInBytes, so
8854                         // we can't tell the cost.  Just assume each instruction
8855                         // is one byte.
8856                         if (MI.isDebugInstr() || MI.isKill())
8857                           return Sum;
8858                         return Sum + 1;
8859                       });
8860 
8861   // We check to see if CFI Instructions are present, and if they are
8862   // we find the number of CFI Instructions in the candidates.
8863   unsigned CFICount = 0;
8864   MachineBasicBlock::iterator MBBI = RepeatedSequenceLocs[0].front();
8865   for (unsigned Loc = RepeatedSequenceLocs[0].getStartIdx();
8866        Loc < RepeatedSequenceLocs[0].getEndIdx() + 1; Loc++) {
8867     const std::vector<MCCFIInstruction> &CFIInstructions =
8868         RepeatedSequenceLocs[0].getMF()->getFrameInstructions();
8869     if (MBBI->isCFIInstruction()) {
8870       unsigned CFIIndex = MBBI->getOperand(0).getCFIIndex();
8871       MCCFIInstruction CFI = CFIInstructions[CFIIndex];
8872       CFICount++;
8873     }
8874     MBBI++;
8875   }
8876 
8877   // We compare the number of found CFI Instructions to  the number of CFI
8878   // instructions in the parent function for each candidate.  We must check this
8879   // since if we outline one of the CFI instructions in a function, we have to
8880   // outline them all for correctness. If we do not, the address offsets will be
8881   // incorrect between the two sections of the program.
8882   for (outliner::Candidate &C : RepeatedSequenceLocs) {
8883     std::vector<MCCFIInstruction> CFIInstructions =
8884         C.getMF()->getFrameInstructions();
8885 
8886     if (CFICount > 0 && CFICount != CFIInstructions.size())
8887       return outliner::OutlinedFunction();
8888   }
8889 
8890   // FIXME: Use real size in bytes for call and ret instructions.
8891   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
8892     for (outliner::Candidate &C : RepeatedSequenceLocs)
8893       C.setCallInfo(MachineOutlinerTailCall, 1);
8894 
8895     return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
8896                                       0, // Number of bytes to emit frame.
8897                                       MachineOutlinerTailCall // Type of frame.
8898     );
8899   }
8900 
8901   if (CFICount > 0)
8902     return outliner::OutlinedFunction();
8903 
8904   for (outliner::Candidate &C : RepeatedSequenceLocs)
8905     C.setCallInfo(MachineOutlinerDefault, 1);
8906 
8907   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
8908                                     MachineOutlinerDefault);
8909 }
8910 
8911 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
8912                                            bool OutlineFromLinkOnceODRs) const {
8913   const Function &F = MF.getFunction();
8914 
8915   // Does the function use a red zone? If it does, then we can't risk messing
8916   // with the stack.
8917   if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
8918     // It could have a red zone. If it does, then we don't want to touch it.
8919     const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8920     if (!X86FI || X86FI->getUsesRedZone())
8921       return false;
8922   }
8923 
8924   // If we *don't* want to outline from things that could potentially be deduped
8925   // then return false.
8926   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
8927       return false;
8928 
8929   // This function is viable for outlining, so return true.
8930   return true;
8931 }
8932 
8933 outliner::InstrType
8934 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  unsigned Flags) const {
8935   MachineInstr &MI = *MIT;
8936   // Don't allow debug values to impact outlining type.
8937   if (MI.isDebugInstr() || MI.isIndirectDebugValue())
8938     return outliner::InstrType::Invisible;
8939 
8940   // At this point, KILL instructions don't really tell us much so we can go
8941   // ahead and skip over them.
8942   if (MI.isKill())
8943     return outliner::InstrType::Invisible;
8944 
8945   // Is this a tail call? If yes, we can outline as a tail call.
8946   if (isTailCall(MI))
8947     return outliner::InstrType::Legal;
8948 
8949   // Is this the terminator of a basic block?
8950   if (MI.isTerminator() || MI.isReturn()) {
8951 
8952     // Does its parent have any successors in its MachineFunction?
8953     if (MI.getParent()->succ_empty())
8954       return outliner::InstrType::Legal;
8955 
8956     // It does, so we can't tail call it.
8957     return outliner::InstrType::Illegal;
8958   }
8959 
8960   // Don't outline anything that modifies or reads from the stack pointer.
8961   //
8962   // FIXME: There are instructions which are being manually built without
8963   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
8964   // able to remove the extra checks once those are fixed up. For example,
8965   // sometimes we might get something like %rax = POP64r 1. This won't be
8966   // caught by modifiesRegister or readsRegister even though the instruction
8967   // really ought to be formed so that modifiesRegister/readsRegister would
8968   // catch it.
8969   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
8970       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
8971       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
8972     return outliner::InstrType::Illegal;
8973 
8974   // Outlined calls change the instruction pointer, so don't read from it.
8975   if (MI.readsRegister(X86::RIP, &RI) ||
8976       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
8977       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
8978     return outliner::InstrType::Illegal;
8979 
8980   // Positions can't safely be outlined.
8981   if (MI.isPosition())
8982     return outliner::InstrType::Illegal;
8983 
8984   // Make sure none of the operands of this instruction do anything tricky.
8985   for (const MachineOperand &MOP : MI.operands())
8986     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
8987         MOP.isTargetIndex())
8988       return outliner::InstrType::Illegal;
8989 
8990   return outliner::InstrType::Legal;
8991 }
8992 
8993 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
8994                                           MachineFunction &MF,
8995                                           const outliner::OutlinedFunction &OF)
8996                                           const {
8997   // If we're a tail call, we already have a return, so don't do anything.
8998   if (OF.FrameConstructionID == MachineOutlinerTailCall)
8999     return;
9000 
9001   // We're a normal call, so our sequence doesn't have a return instruction.
9002   // Add it in.
9003   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
9004   MBB.insert(MBB.end(), retq);
9005 }
9006 
9007 MachineBasicBlock::iterator
9008 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
9009                                  MachineBasicBlock::iterator &It,
9010                                  MachineFunction &MF,
9011                                  const outliner::Candidate &C) const {
9012   // Is it a tail call?
9013   if (C.CallConstructionID == MachineOutlinerTailCall) {
9014     // Yes, just insert a JMP.
9015     It = MBB.insert(It,
9016                   BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
9017                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9018   } else {
9019     // No, insert a call.
9020     It = MBB.insert(It,
9021                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
9022                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9023   }
9024 
9025   return It;
9026 }
9027 
9028 #define GET_INSTRINFO_HELPERS
9029 #include "X86GenInstrInfo.inc"
9030