1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include <limits>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "x86-instr-info"
44 
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "X86GenInstrInfo.inc"
47 
48 static cl::opt<bool>
49 NoFusing("disable-spill-fusing",
50          cl::desc("Disable fusing of spill code into instructions"));
51 static cl::opt<bool>
52 PrintFailedFusing("print-failed-fuse-candidates",
53                   cl::desc("Print instructions that the allocator wants to"
54                            " fuse, but the X86 backend currently can't"),
55                   cl::Hidden);
56 static cl::opt<bool>
57 ReMatPICStubLoad("remat-pic-stub-load",
58                  cl::desc("Re-materialize load from stub in PIC mode"),
59                  cl::init(false), cl::Hidden);
60 
61 enum {
62   // Select which memory operand is being unfolded.
63   // (stored in bits 0 - 3)
64   TB_INDEX_0    = 0,
65   TB_INDEX_1    = 1,
66   TB_INDEX_2    = 2,
67   TB_INDEX_3    = 3,
68   TB_INDEX_4    = 4,
69   TB_INDEX_MASK = 0xf,
70 
71   // Do not insert the reverse map (MemOp -> RegOp) into the table.
72   // This may be needed because there is a many -> one mapping.
73   TB_NO_REVERSE   = 1 << 4,
74 
75   // Do not insert the forward map (RegOp -> MemOp) into the table.
76   // This is needed for Native Client, which prohibits branch
77   // instructions from using a memory operand.
78   TB_NO_FORWARD   = 1 << 5,
79 
80   TB_FOLDED_LOAD  = 1 << 6,
81   TB_FOLDED_STORE = 1 << 7,
82 
83   // Minimum alignment required for load/store.
84   // Used for RegOp->MemOp conversion.
85   // (stored in bits 8 - 15)
86   TB_ALIGN_SHIFT = 8,
87   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
88   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
89   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
90   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
91   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
92 };
93 
94 struct X86MemoryFoldTableEntry {
95   uint16_t RegOp;
96   uint16_t MemOp;
97   uint16_t Flags;
98 };
99 
100 // Pin the vtable to this file.
101 void X86InstrInfo::anchor() {}
102 
103 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
105                                                : X86::ADJCALLSTACKDOWN32),
106                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
107                                                : X86::ADJCALLSTACKUP32),
108                       X86::CATCHRET),
109       Subtarget(STI), RI(STI.getTargetTriple()) {
110 
111   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
112     { X86::ADC32ri,     X86::ADC32mi,    0 },
113     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
114     { X86::ADC32rr,     X86::ADC32mr,    0 },
115     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
116     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
117     { X86::ADC64rr,     X86::ADC64mr,    0 },
118     { X86::ADD16ri,     X86::ADD16mi,    0 },
119     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
120     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
121     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
122     { X86::ADD16rr,     X86::ADD16mr,    0 },
123     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
124     { X86::ADD32ri,     X86::ADD32mi,    0 },
125     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
126     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
127     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
128     { X86::ADD32rr,     X86::ADD32mr,    0 },
129     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
130     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
131     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
132     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
133     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
134     { X86::ADD64rr,     X86::ADD64mr,    0 },
135     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
136     { X86::ADD8ri,      X86::ADD8mi,     0 },
137     { X86::ADD8rr,      X86::ADD8mr,     0 },
138     { X86::AND16ri,     X86::AND16mi,    0 },
139     { X86::AND16ri8,    X86::AND16mi8,   0 },
140     { X86::AND16rr,     X86::AND16mr,    0 },
141     { X86::AND32ri,     X86::AND32mi,    0 },
142     { X86::AND32ri8,    X86::AND32mi8,   0 },
143     { X86::AND32rr,     X86::AND32mr,    0 },
144     { X86::AND64ri32,   X86::AND64mi32,  0 },
145     { X86::AND64ri8,    X86::AND64mi8,   0 },
146     { X86::AND64rr,     X86::AND64mr,    0 },
147     { X86::AND8ri,      X86::AND8mi,     0 },
148     { X86::AND8rr,      X86::AND8mr,     0 },
149     { X86::DEC16r,      X86::DEC16m,     0 },
150     { X86::DEC32r,      X86::DEC32m,     0 },
151     { X86::DEC64r,      X86::DEC64m,     0 },
152     { X86::DEC8r,       X86::DEC8m,      0 },
153     { X86::INC16r,      X86::INC16m,     0 },
154     { X86::INC32r,      X86::INC32m,     0 },
155     { X86::INC64r,      X86::INC64m,     0 },
156     { X86::INC8r,       X86::INC8m,      0 },
157     { X86::NEG16r,      X86::NEG16m,     0 },
158     { X86::NEG32r,      X86::NEG32m,     0 },
159     { X86::NEG64r,      X86::NEG64m,     0 },
160     { X86::NEG8r,       X86::NEG8m,      0 },
161     { X86::NOT16r,      X86::NOT16m,     0 },
162     { X86::NOT32r,      X86::NOT32m,     0 },
163     { X86::NOT64r,      X86::NOT64m,     0 },
164     { X86::NOT8r,       X86::NOT8m,      0 },
165     { X86::OR16ri,      X86::OR16mi,     0 },
166     { X86::OR16ri8,     X86::OR16mi8,    0 },
167     { X86::OR16rr,      X86::OR16mr,     0 },
168     { X86::OR32ri,      X86::OR32mi,     0 },
169     { X86::OR32ri8,     X86::OR32mi8,    0 },
170     { X86::OR32rr,      X86::OR32mr,     0 },
171     { X86::OR64ri32,    X86::OR64mi32,   0 },
172     { X86::OR64ri8,     X86::OR64mi8,    0 },
173     { X86::OR64rr,      X86::OR64mr,     0 },
174     { X86::OR8ri,       X86::OR8mi,      0 },
175     { X86::OR8rr,       X86::OR8mr,      0 },
176     { X86::ROL16r1,     X86::ROL16m1,    0 },
177     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
178     { X86::ROL16ri,     X86::ROL16mi,    0 },
179     { X86::ROL32r1,     X86::ROL32m1,    0 },
180     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
181     { X86::ROL32ri,     X86::ROL32mi,    0 },
182     { X86::ROL64r1,     X86::ROL64m1,    0 },
183     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
184     { X86::ROL64ri,     X86::ROL64mi,    0 },
185     { X86::ROL8r1,      X86::ROL8m1,     0 },
186     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
187     { X86::ROL8ri,      X86::ROL8mi,     0 },
188     { X86::ROR16r1,     X86::ROR16m1,    0 },
189     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
190     { X86::ROR16ri,     X86::ROR16mi,    0 },
191     { X86::ROR32r1,     X86::ROR32m1,    0 },
192     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
193     { X86::ROR32ri,     X86::ROR32mi,    0 },
194     { X86::ROR64r1,     X86::ROR64m1,    0 },
195     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
196     { X86::ROR64ri,     X86::ROR64mi,    0 },
197     { X86::ROR8r1,      X86::ROR8m1,     0 },
198     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
199     { X86::ROR8ri,      X86::ROR8mi,     0 },
200     { X86::SAR16r1,     X86::SAR16m1,    0 },
201     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
202     { X86::SAR16ri,     X86::SAR16mi,    0 },
203     { X86::SAR32r1,     X86::SAR32m1,    0 },
204     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
205     { X86::SAR32ri,     X86::SAR32mi,    0 },
206     { X86::SAR64r1,     X86::SAR64m1,    0 },
207     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
208     { X86::SAR64ri,     X86::SAR64mi,    0 },
209     { X86::SAR8r1,      X86::SAR8m1,     0 },
210     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
211     { X86::SAR8ri,      X86::SAR8mi,     0 },
212     { X86::SBB32ri,     X86::SBB32mi,    0 },
213     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
214     { X86::SBB32rr,     X86::SBB32mr,    0 },
215     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
216     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
217     { X86::SBB64rr,     X86::SBB64mr,    0 },
218     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
219     { X86::SHL16ri,     X86::SHL16mi,    0 },
220     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
221     { X86::SHL32ri,     X86::SHL32mi,    0 },
222     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
223     { X86::SHL64ri,     X86::SHL64mi,    0 },
224     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
225     { X86::SHL8ri,      X86::SHL8mi,     0 },
226     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
227     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
228     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
229     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
230     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
231     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
232     { X86::SHR16r1,     X86::SHR16m1,    0 },
233     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
234     { X86::SHR16ri,     X86::SHR16mi,    0 },
235     { X86::SHR32r1,     X86::SHR32m1,    0 },
236     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
237     { X86::SHR32ri,     X86::SHR32mi,    0 },
238     { X86::SHR64r1,     X86::SHR64m1,    0 },
239     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
240     { X86::SHR64ri,     X86::SHR64mi,    0 },
241     { X86::SHR8r1,      X86::SHR8m1,     0 },
242     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
243     { X86::SHR8ri,      X86::SHR8mi,     0 },
244     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
245     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
246     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
247     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
248     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
249     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
250     { X86::SUB16ri,     X86::SUB16mi,    0 },
251     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
252     { X86::SUB16rr,     X86::SUB16mr,    0 },
253     { X86::SUB32ri,     X86::SUB32mi,    0 },
254     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
255     { X86::SUB32rr,     X86::SUB32mr,    0 },
256     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
257     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
258     { X86::SUB64rr,     X86::SUB64mr,    0 },
259     { X86::SUB8ri,      X86::SUB8mi,     0 },
260     { X86::SUB8rr,      X86::SUB8mr,     0 },
261     { X86::XOR16ri,     X86::XOR16mi,    0 },
262     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
263     { X86::XOR16rr,     X86::XOR16mr,    0 },
264     { X86::XOR32ri,     X86::XOR32mi,    0 },
265     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
266     { X86::XOR32rr,     X86::XOR32mr,    0 },
267     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
268     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
269     { X86::XOR64rr,     X86::XOR64mr,    0 },
270     { X86::XOR8ri,      X86::XOR8mi,     0 },
271     { X86::XOR8rr,      X86::XOR8mr,     0 }
272   };
273 
274   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
275     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
276                   Entry.RegOp, Entry.MemOp,
277                   // Index 0, folded load and store, no alignment requirement.
278                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
279   }
280 
281   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
282     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
283     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
284     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
285     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
286     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
287     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
288     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
289     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
290     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
291     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
292     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
293     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
294     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
295     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
296     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
297     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
298     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
299     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
300     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
301     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
302     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
303     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
304     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
305     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
306     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
307     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
308     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
309     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
310     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
311     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
312     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
313     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
314     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
315     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
316     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
317     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
318     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
319     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
320     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
321     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
322     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
323     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
326     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
327     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
328     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
329     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
330     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
331     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
332     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
333     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
334     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
335     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
336     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
337     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
338     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
339     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
340     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
341     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
342     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
343     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
344     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
345     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
346     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
347     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
348     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
349     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
350     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
351     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
352     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
353     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
354     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
355     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
356     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
357     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
358     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
359     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
360     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
361     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
362     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
363 
364     // AVX 128-bit versions of foldable instructions
365     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
366     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
367     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
368     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
369     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
370     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
371     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
372     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
373     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
374     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
375     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
376     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
377     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
378 
379     // AVX 256-bit foldable instructions
380     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
381     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
382     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
383     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
384     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
385     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
386 
387     // AVX-512 foldable instructions
388     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
389     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
390     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
391     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
392     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
393     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
394     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
395     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
396     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
397     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
398     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
399 
400     // AVX-512 foldable instructions (256-bit versions)
401     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
402     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
403     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
404     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
405     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
406     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
407     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
408     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
409     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
410     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
411 
412     // AVX-512 foldable instructions (128-bit versions)
413     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
414     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
415     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
416     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
417     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
418     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
419     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
420     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
421     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
422     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
423 
424     // F16C foldable instructions
425     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
426     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
427   };
428 
429   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
430     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
431                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
432   }
433 
434   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
435     { X86::BSF16rr,         X86::BSF16rm,             0 },
436     { X86::BSF32rr,         X86::BSF32rm,             0 },
437     { X86::BSF64rr,         X86::BSF64rm,             0 },
438     { X86::BSR16rr,         X86::BSR16rm,             0 },
439     { X86::BSR32rr,         X86::BSR32rm,             0 },
440     { X86::BSR64rr,         X86::BSR64rm,             0 },
441     { X86::CMP16rr,         X86::CMP16rm,             0 },
442     { X86::CMP32rr,         X86::CMP32rm,             0 },
443     { X86::CMP64rr,         X86::CMP64rm,             0 },
444     { X86::CMP8rr,          X86::CMP8rm,              0 },
445     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
446     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
447     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
448     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
449     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
450     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
451     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
452     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
453     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
454     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
455     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
456     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
457     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
458     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
459     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
460     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
461     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
462     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
463     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
464     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
465     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
466     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
467     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
468     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
469     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
470     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
471     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
472     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
473     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
474     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
475     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
476     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
477     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
478     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
479     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
480     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
481     { X86::MOV16rr,         X86::MOV16rm,             0 },
482     { X86::MOV32rr,         X86::MOV32rm,             0 },
483     { X86::MOV64rr,         X86::MOV64rm,             0 },
484     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
485     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
486     { X86::MOV8rr,          X86::MOV8rm,              0 },
487     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
488     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
489     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
490     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
491     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
492     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
493     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
494     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
495     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
496     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
497     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
498     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
499     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
500     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
501     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
502     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
503     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
504     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
505     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
506     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
507     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
508     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
509     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
510     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
511     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
512     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
513     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
514     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
515     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
516     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
517     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
518     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
519     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
520     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
521     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
522     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
523     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
524     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
525     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
526     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
527     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
528     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
529     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
530     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
531     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
532     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
533     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
534     { X86::RCPSSr,          X86::RCPSSm,              0 },
535     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          0 },
536     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
537     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
538     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
539     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
540     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
541     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
542     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
543     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
544     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
545     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
546     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
547     { X86::TEST16rr,        X86::TEST16rm,            0 },
548     { X86::TEST32rr,        X86::TEST32rm,            0 },
549     { X86::TEST64rr,        X86::TEST64rm,            0 },
550     { X86::TEST8rr,         X86::TEST8rm,             0 },
551     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
552     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
553     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
554 
555     // MMX version of foldable instructions
556     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
557     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
558     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
559     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
560     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
561     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
562     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
563     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
564     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
565     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
566 
567     // 3DNow! version of foldable instructions
568     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
569     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
570     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
571     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
572     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
573     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
574     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
575 
576     // AVX 128-bit versions of foldable instructions
577     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
578     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
579     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
580     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
581     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
582     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
583     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
584     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
585     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
586     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
587     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
588     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
589     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
590     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
591     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
592     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
593     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
594     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
595     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
596     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
597     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
598     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
599     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
600     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
601     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
602     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
603     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
604     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
605     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
606     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
607     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
608     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
609     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
610     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
611     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
612     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
613     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
614     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
615     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
616     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
617     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
618     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
619     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
620     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
621     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
622     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
623     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
624     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
625     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
626     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
627     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
628     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
629     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
630     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
631     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
632     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
633     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
634     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
635     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
636     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
637     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
638     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
639     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
640     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
641     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
642     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
643     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
644     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
645     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
646     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
647     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
648     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
649     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
650     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
651 
652     // AVX 256-bit foldable instructions
653     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
654     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
655     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
656     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
657     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
658     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
659     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
660     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
661     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
662     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
663     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
664     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
665     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
666     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
667     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
668     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
669     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
670     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
671     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
672     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
673     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
674     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
675     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
676     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
677     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
678     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
679     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
680 
681     // AVX2 foldable instructions
682 
683     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
684     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
685     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
686     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
687     // so they don't need an equivalent limitation.
688     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
689     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
690     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
691     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
692     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
693     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
694     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      0 },
695     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     0 },
696     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      0 },
697     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     0 },
698     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      0 },
699     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     0 },
700     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      0 },
701     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     0 },
702     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
703     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
704     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        0 },
705     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        0 },
706     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
707     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
708     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
709     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        0 },
710     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        0 },
711     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        0 },
712     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
713     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
714     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
715     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        0 },
716     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
717     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
718     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
719 
720     // XOP foldable instructions
721     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
722     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
723     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
724     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
725     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
726     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
727     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
728     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
729     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
730     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
731     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
732     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
733     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
734     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
735     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
736     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
737     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
738     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
739     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
740     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
741     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
742     { X86::VPROTBri,           X86::VPROTBmi,         0 },
743     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
744     { X86::VPROTDri,           X86::VPROTDmi,         0 },
745     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
746     { X86::VPROTQri,           X86::VPROTQmi,         0 },
747     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
748     { X86::VPROTWri,           X86::VPROTWmi,         0 },
749     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
750     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
751     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
752     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
753     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
754     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
755     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
756     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
757     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
758 
759     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
760     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
761     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
762     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
763     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
764     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
765     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
766     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
767     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
768     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
769     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
770     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
771     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
772     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
773     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
774     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
775     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
776     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
777     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
778     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
779     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
780     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
781     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
782     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
783     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
784     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
785     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
786     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
787     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
788     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
789     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
790     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
791     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
792     { X86::RORX32ri,        X86::RORX32mi,            0 },
793     { X86::RORX64ri,        X86::RORX64mi,            0 },
794     { X86::SARX32rr,        X86::SARX32rm,            0 },
795     { X86::SARX64rr,        X86::SARX64rm,            0 },
796     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
797     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
798     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
799     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
800     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
801     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
802     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
803     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
804     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
805     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
806     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
807 
808     // AVX-512 foldable instructions
809     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
810     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
811     { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
812     { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
813     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
814     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
815     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zrm,         0 },
816     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zrm,        0 },
817     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
818     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
819     { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
820     { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
821     { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
822     { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
823     { X86::VBROADCASTSSZr,  X86::VBROADCASTSSZm,      TB_NO_REVERSE },
824     { X86::VBROADCASTSDZr,  X86::VBROADCASTSDZm,      TB_NO_REVERSE },
825 
826     // AVX-512 foldable instructions (256-bit versions)
827     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256rm,          TB_ALIGN_32 },
828     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256rm,          TB_ALIGN_32 },
829     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256rm,        TB_ALIGN_32 },
830     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256rm,        TB_ALIGN_32 },
831     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256rm,         0 },
832     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256rm,        0 },
833     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256rm,        0 },
834     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256rm,        0 },
835     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256rm,          0 },
836     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256rm,          0 },
837     { X86::VBROADCASTSSZ256r,  X86::VBROADCASTSSZ256m,      TB_NO_REVERSE },
838     { X86::VBROADCASTSDZ256r,  X86::VBROADCASTSDZ256m,      TB_NO_REVERSE },
839 
840     // AVX-512 foldable instructions (256-bit versions)
841     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128rm,          TB_ALIGN_16 },
842     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128rm,          TB_ALIGN_16 },
843     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128rm,        TB_ALIGN_16 },
844     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128rm,        TB_ALIGN_16 },
845     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128rm,         0 },
846     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128rm,        0 },
847     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128rm,        0 },
848     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128rm,        0 },
849     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128rm,          0 },
850     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128rm,          0 },
851     { X86::VBROADCASTSSZ128r,  X86::VBROADCASTSSZ128m,      TB_NO_REVERSE },
852 
853     // F16C foldable instructions
854     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
855     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
856 
857     // AES foldable instructions
858     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
859     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
860     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
861     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
862   };
863 
864   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
865     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
866                   Entry.RegOp, Entry.MemOp,
867                   // Index 1, folded load
868                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
869   }
870 
871   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
872     { X86::ADC32rr,         X86::ADC32rm,       0 },
873     { X86::ADC64rr,         X86::ADC64rm,       0 },
874     { X86::ADD16rr,         X86::ADD16rm,       0 },
875     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
876     { X86::ADD32rr,         X86::ADD32rm,       0 },
877     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
878     { X86::ADD64rr,         X86::ADD64rm,       0 },
879     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
880     { X86::ADD8rr,          X86::ADD8rm,        0 },
881     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
882     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
883     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
884     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
885     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
886     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
887     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
888     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
889     { X86::AND16rr,         X86::AND16rm,       0 },
890     { X86::AND32rr,         X86::AND32rm,       0 },
891     { X86::AND64rr,         X86::AND64rm,       0 },
892     { X86::AND8rr,          X86::AND8rm,        0 },
893     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
894     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
895     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
896     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
897     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
898     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
899     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
900     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
901     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
902     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
903     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
904     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
905     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
906     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
907     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
908     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
909     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
910     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
911     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
912     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
913     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
914     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
915     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
916     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
917     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
918     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
919     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
920     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
921     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
922     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
923     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
924     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
925     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
926     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
927     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
928     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
929     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
930     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
931     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
932     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
933     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
934     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
935     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
936     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
937     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
938     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
939     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
940     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
941     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
942     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
943     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
944     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
945     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
946     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
947     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
948     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
949     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
950     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
951     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
952     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
953     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
954     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
955     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
956     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
957     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
958     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
959     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
960     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
961     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
962     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
963 
964     // Do not fold Fs* scalar logical op loads because there are no scalar
965     // load variants for these instructions. When folded, the load is required
966     // to be 128-bits, so the load size would not match.
967 
968     { X86::FvANDNPDrr,      X86::FvANDNPDrm,    TB_ALIGN_16 },
969     { X86::FvANDNPSrr,      X86::FvANDNPSrm,    TB_ALIGN_16 },
970     { X86::FvANDPDrr,       X86::FvANDPDrm,     TB_ALIGN_16 },
971     { X86::FvANDPSrr,       X86::FvANDPSrm,     TB_ALIGN_16 },
972     { X86::FvORPDrr,        X86::FvORPDrm,      TB_ALIGN_16 },
973     { X86::FvORPSrr,        X86::FvORPSrm,      TB_ALIGN_16 },
974     { X86::FvXORPDrr,       X86::FvXORPDrm,     TB_ALIGN_16 },
975     { X86::FvXORPSrr,       X86::FvXORPSrm,     TB_ALIGN_16 },
976     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
977     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
978     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
979     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
980     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
981     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
982     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
983     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
984     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
985     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
986     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
987     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
988     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
989     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
990     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
991     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
992     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
993     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
994     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
995     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
996     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
997     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
998     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
999     { X86::MINSDrr,         X86::MINSDrm,       0 },
1000     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
1001     { X86::MINSSrr,         X86::MINSSrm,       0 },
1002     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
1003     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1004     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1005     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1006     { X86::MULSDrr,         X86::MULSDrm,       0 },
1007     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
1008     { X86::MULSSrr,         X86::MULSSrm,       0 },
1009     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
1010     { X86::OR16rr,          X86::OR16rm,        0 },
1011     { X86::OR32rr,          X86::OR32rm,        0 },
1012     { X86::OR64rr,          X86::OR64rm,        0 },
1013     { X86::OR8rr,           X86::OR8rm,         0 },
1014     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1015     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1016     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1017     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1018     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1019     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1020     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1021     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1022     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1023     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1024     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1025     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1026     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1027     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1028     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
1029     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1030     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1031     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1032     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1033     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1034     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1035     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1036     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1037     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1038     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1039     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1040     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1041     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1042     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1043     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1044     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1045     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1046     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1047     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1048     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1049     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1050     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1051     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1052     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1053     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1054     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
1055     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1056     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1057     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1058     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1059     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1060     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1061     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1062     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1063     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1064     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1065     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1066     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1067     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1068     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1069     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
1070     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1071     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1072     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1073     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1074     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1075     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1076     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1077     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1078     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
1079     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
1080     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
1081     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1082     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1083     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1084     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1085     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1086     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1087     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1088     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1089     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1090     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1091     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1092     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1093     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1094     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1095     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1096     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1097     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1098     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1099     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1100     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1101     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1102     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1103     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1104     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1105     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1106     { X86::ROUNDSDr,        X86::ROUNDSDm,      0 },
1107     { X86::ROUNDSSr,        X86::ROUNDSSm,      0 },
1108     { X86::SBB32rr,         X86::SBB32rm,       0 },
1109     { X86::SBB64rr,         X86::SBB64rm,       0 },
1110     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1111     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1112     { X86::SUB16rr,         X86::SUB16rm,       0 },
1113     { X86::SUB32rr,         X86::SUB32rm,       0 },
1114     { X86::SUB64rr,         X86::SUB64rm,       0 },
1115     { X86::SUB8rr,          X86::SUB8rm,        0 },
1116     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1117     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1118     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1119     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1120     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1121     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1122     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1123     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1124     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1125     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1126     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1127     { X86::XOR16rr,         X86::XOR16rm,       0 },
1128     { X86::XOR32rr,         X86::XOR32rm,       0 },
1129     { X86::XOR64rr,         X86::XOR64rm,       0 },
1130     { X86::XOR8rr,          X86::XOR8rm,        0 },
1131     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1132     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1133 
1134     // MMX version of foldable instructions
1135     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1136     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1137     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1138     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1139     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1140     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1141     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1142     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1143     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1144     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1145     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1146     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1147     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1148     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1149     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1150     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1151     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1152     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1153     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1154     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1155     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1156     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1157     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1158     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1159     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1160     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1161     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1162     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1163     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1164     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1165     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1166     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1167     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1168     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1169     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1170     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1171     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1172     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1173     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1174     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1175     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1176     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1177     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1178     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1179     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1180     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1181     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1182     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1183     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1184     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1185     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1186     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1187     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1188     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1189     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1190     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1191     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1192     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1193     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1194     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1195     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1196     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1197     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1198     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1199     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1200     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1201     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1202     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1203     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1204     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1205 
1206     // 3DNow! version of foldable instructions
1207     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1208     { X86::PFACCrr,           X86::PFACCrm,           0 },
1209     { X86::PFADDrr,           X86::PFADDrm,           0 },
1210     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1211     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1212     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1213     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1214     { X86::PFMINrr,           X86::PFMINrm,           0 },
1215     { X86::PFMULrr,           X86::PFMULrm,           0 },
1216     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1217     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1218     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1219     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1220     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1221     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1222     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1223     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1224 
1225     // AVX 128-bit versions of foldable instructions
1226     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1227     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1228     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1229     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1230     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1231     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1232     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1233     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1234     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1235     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1236     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1237     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1238     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1239     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        0 },
1240     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1241     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      0 },
1242     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1243     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       0 },
1244     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1245     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       0 },
1246     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1247     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1248     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1249     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1250     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1251     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1252     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1253     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1254     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1255     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1256     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1257     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1258     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1259     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1260     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1261     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1262     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1263     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1264     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1265     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1266     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1267     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1268     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1269     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1270     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1271     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1272     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1273     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1274     // Do not fold VFs* loads because there are no scalar load variants for
1275     // these instructions. When folded, the load is required to be 128-bits, so
1276     // the load size would not match.
1277     { X86::VFvANDNPDrr,       X86::VFvANDNPDrm,        0 },
1278     { X86::VFvANDNPSrr,       X86::VFvANDNPSrm,        0 },
1279     { X86::VFvANDPDrr,        X86::VFvANDPDrm,         0 },
1280     { X86::VFvANDPSrr,        X86::VFvANDPSrm,         0 },
1281     { X86::VFvORPDrr,         X86::VFvORPDrm,          0 },
1282     { X86::VFvORPSrr,         X86::VFvORPSrm,          0 },
1283     { X86::VFvXORPDrr,        X86::VFvXORPDrm,         0 },
1284     { X86::VFvXORPSrr,        X86::VFvXORPSrm,         0 },
1285     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1286     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1287     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1288     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1289     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1290     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1291     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1292     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1293     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1294     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1295     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1296     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1297     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1298     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1299     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1300     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1301     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1302     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1303     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1304     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1305     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1306     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1307     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1308     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1309     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1310     { X86::VORPDrr,           X86::VORPDrm,            0 },
1311     { X86::VORPSrr,           X86::VORPSrm,            0 },
1312     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1313     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1314     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1315     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1316     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1317     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1318     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1319     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1320     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1321     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1322     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1323     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1324     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
1325     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1326     { X86::VPANDrr,           X86::VPANDrm,            0 },
1327     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1328     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1329     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1330     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1331     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1332     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1333     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1334     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1335     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1336     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1337     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1338     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1339     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1340     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1341     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1342     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1343     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1344     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1345     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1346     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1347     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1348     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1349     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1350     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1351     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1352     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1353     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1354     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1355     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1356     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1357     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1358     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1359     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1360     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1361     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1362     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1363     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1364     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1365     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1366     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1367     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1368     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1369     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1370     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1371     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1372     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1373     { X86::VPORrr,            X86::VPORrm,             0 },
1374     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1375     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1376     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
1377     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
1378     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
1379     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1380     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1381     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1382     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1383     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1384     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1385     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1386     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1387     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1388     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1389     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1390     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1391     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1392     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1393     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1394     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1395     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1396     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1397     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1398     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1399     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1400     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1401     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1402     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1403     { X86::VPXORrr,           X86::VPXORrm,            0 },
1404     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1405     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1406     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1407     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1408     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1409     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1410     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1411     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1412     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1413     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1414     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1415     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1416     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1417     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1418     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1419     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1420 
1421     // AVX 256-bit foldable instructions
1422     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1423     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1424     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1425     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1426     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1427     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1428     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1429     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1430     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1431     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1432     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1433     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1434     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1435     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1436     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1437     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1438     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1439     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1440     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1441     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1442     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1443     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1444     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1445     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1446     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1447     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1448     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1449     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1450     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1451     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1452     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1453     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1454     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1455     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1456     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1457     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1458     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1459     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1460     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1461     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1462     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1463     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1464     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1465 
1466     // AVX2 foldable instructions
1467     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1468     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1469     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1470     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1471     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1472     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1473     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1474     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1475     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1476     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1477     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1478     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1479     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1480     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1481     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1482     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1483     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1484     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1485     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1486     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1487     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1488     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1489     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1490     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1491     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1492     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1493     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1494     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1495     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1496     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1497     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1498     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1499     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1500     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1501     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1502     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1503     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1504     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1505     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1506     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1507     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1508     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1509     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1510     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1511     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1512     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1513     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1514     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1515     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1516     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1517     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1518     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1519     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1520     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1521     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1522     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1523     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1524     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1525     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1526     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1527     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1528     { X86::VPORYrr,           X86::VPORYrm,            0 },
1529     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1530     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1531     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1532     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1533     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1534     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1535     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1536     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1537     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1538     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1539     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1540     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1541     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1542     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1543     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1544     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1545     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1546     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1547     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1548     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1549     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1550     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1551     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1552     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1553     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1554     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1555     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1556     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1557     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1558     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1559     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1560     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1561     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1562     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1563     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1564     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1565     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1566     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1567     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1568     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1569 
1570     // FMA4 foldable patterns
1571     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1572     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1573     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1574     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1575     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_NONE },
1576     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_NONE },
1577     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1578     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1579     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1580     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1581     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_NONE },
1582     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_NONE },
1583     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1584     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1585     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1586     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1587     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_NONE },
1588     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_NONE },
1589     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1590     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1591     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1592     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1593     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_NONE },
1594     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_NONE },
1595     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1596     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1597     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_NONE },
1598     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_NONE },
1599     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1600     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1601     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_NONE },
1602     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_NONE },
1603 
1604     // XOP foldable instructions
1605     { X86::VPCMOVrr,          X86::VPCMOVmr,            0 },
1606     { X86::VPCMOVrrY,         X86::VPCMOVmrY,           0 },
1607     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1608     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1609     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1610     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1611     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1612     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1613     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1614     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1615     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1616     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1617     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1618     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1619     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1620     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1621     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1622     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1623     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1624     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1625     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1626     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1627     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1628     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1629     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1630     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1631     { X86::VPPERMrr,          X86::VPPERMmr,            0 },
1632     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1633     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1634     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1635     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1636     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1637     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1638     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1639     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1640     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1641     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1642     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1643     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1644 
1645     // BMI/BMI2 foldable instructions
1646     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1647     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1648     { X86::MULX32rr,          X86::MULX32rm,            0 },
1649     { X86::MULX64rr,          X86::MULX64rm,            0 },
1650     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1651     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1652     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1653     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1654 
1655     // AVX-512 foldable instructions
1656     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1657     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1658     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1659     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1660     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1661     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1662     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1663     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1664     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1665     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1666     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1667     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1668     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1669     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1670     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1671     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1672     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1673     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1674     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1675     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1676     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1677     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1678     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1679     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1680     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1681     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1682     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1683     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1684     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1685     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1686     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1687     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1688     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1689     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1690     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1691     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1692     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1693     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1694     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1695 
1696     // AVX-512{F,VL} foldable instructions
1697     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1698     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1699     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1700 
1701     // AVX-512{F,VL} foldable instructions
1702     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1703     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1704     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1705     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1706 
1707     // AES foldable instructions
1708     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1709     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1710     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1711     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1712     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
1713     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
1714     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
1715     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
1716 
1717     // SHA foldable instructions
1718     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1719     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1720     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1721     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1722     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1723     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1724     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
1725   };
1726 
1727   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
1728     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1729                   Entry.RegOp, Entry.MemOp,
1730                   // Index 2, folded load
1731                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1732   }
1733 
1734   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1735     // FMA foldable instructions
1736     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1737     { X86::VFMADDSSr231r_Int,     X86::VFMADDSSr231m_Int,     TB_ALIGN_NONE },
1738     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1739     { X86::VFMADDSDr231r_Int,     X86::VFMADDSDr231m_Int,     TB_ALIGN_NONE },
1740     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1741     { X86::VFMADDSSr132r_Int,     X86::VFMADDSSr132m_Int,     TB_ALIGN_NONE },
1742     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1743     { X86::VFMADDSDr132r_Int,     X86::VFMADDSDr132m_Int,     TB_ALIGN_NONE },
1744     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1745     { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     TB_ALIGN_NONE },
1746     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1747     { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     TB_ALIGN_NONE },
1748 
1749     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1750     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1751     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1752     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1753     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1754     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1755     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1756     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1757     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1758     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1759     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1760     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1761 
1762     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1763     { X86::VFNMADDSSr231r_Int,    X86::VFNMADDSSr231m_Int,    TB_ALIGN_NONE },
1764     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1765     { X86::VFNMADDSDr231r_Int,    X86::VFNMADDSDr231m_Int,    TB_ALIGN_NONE },
1766     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1767     { X86::VFNMADDSSr132r_Int,    X86::VFNMADDSSr132m_Int,    TB_ALIGN_NONE },
1768     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1769     { X86::VFNMADDSDr132r_Int,    X86::VFNMADDSDr132m_Int,    TB_ALIGN_NONE },
1770     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1771     { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    TB_ALIGN_NONE },
1772     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1773     { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    TB_ALIGN_NONE },
1774 
1775     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1776     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1777     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1778     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1779     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1780     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1781     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1782     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1783     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1784     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1785     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1786     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1787 
1788     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1789     { X86::VFMSUBSSr231r_Int,     X86::VFMSUBSSr231m_Int,     TB_ALIGN_NONE },
1790     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1791     { X86::VFMSUBSDr231r_Int,     X86::VFMSUBSDr231m_Int,     TB_ALIGN_NONE },
1792     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1793     { X86::VFMSUBSSr132r_Int,     X86::VFMSUBSSr132m_Int,     TB_ALIGN_NONE },
1794     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1795     { X86::VFMSUBSDr132r_Int,     X86::VFMSUBSDr132m_Int,     TB_ALIGN_NONE },
1796     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1797     { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     TB_ALIGN_NONE },
1798     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1799     { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     TB_ALIGN_NONE },
1800 
1801     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1802     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1803     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1804     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1805     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1806     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1807     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1808     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1809     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1810     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1811     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1812     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1813 
1814     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1815     { X86::VFNMSUBSSr231r_Int,    X86::VFNMSUBSSr231m_Int,    TB_ALIGN_NONE },
1816     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1817     { X86::VFNMSUBSDr231r_Int,    X86::VFNMSUBSDr231m_Int,    TB_ALIGN_NONE },
1818     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1819     { X86::VFNMSUBSSr132r_Int,    X86::VFNMSUBSSr132m_Int,    TB_ALIGN_NONE },
1820     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1821     { X86::VFNMSUBSDr132r_Int,    X86::VFNMSUBSDr132m_Int,    TB_ALIGN_NONE },
1822     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1823     { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    TB_ALIGN_NONE },
1824     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1825     { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    TB_ALIGN_NONE },
1826 
1827     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1828     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1829     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1830     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1831     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1832     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1833     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1834     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1835     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1836     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1837     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1838     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1839 
1840     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1841     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1842     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1843     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1844     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1845     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1846     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1847     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1848     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1849     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1850     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1851     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1852 
1853     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1854     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1855     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1856     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1857     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1858     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1859     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1860     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1861     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1862     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1863     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1864     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1865 
1866     // FMA4 foldable patterns
1867     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
1868     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
1869     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
1870     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
1871     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_NONE },
1872     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_NONE },
1873     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
1874     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
1875     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
1876     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
1877     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_NONE },
1878     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_NONE },
1879     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
1880     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
1881     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
1882     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
1883     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_NONE },
1884     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_NONE },
1885     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
1886     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
1887     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
1888     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
1889     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_NONE },
1890     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_NONE },
1891     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
1892     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
1893     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_NONE },
1894     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_NONE },
1895     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
1896     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
1897     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_NONE },
1898     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_NONE },
1899 
1900     // XOP foldable instructions
1901     { X86::VPCMOVrr,              X86::VPCMOVrm,              0 },
1902     { X86::VPCMOVrrY,             X86::VPCMOVrmY,             0 },
1903     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
1904     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
1905     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
1906     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
1907     { X86::VPPERMrr,              X86::VPPERMrm,              0 },
1908 
1909     // AVX-512 VPERMI instructions with 3 source operands.
1910     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1911     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1912     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1913     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1914     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1915     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1916     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1917     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1918     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1919     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1920     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1921     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1922     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
1923      // AVX-512 arithmetic instructions
1924     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
1925     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
1926     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
1927     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
1928     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
1929     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
1930     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
1931     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
1932     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
1933     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
1934     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
1935     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
1936     // AVX-512{F,VL} arithmetic instructions 256-bit
1937     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
1938     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
1939     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
1940     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
1941     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
1942     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
1943     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
1944     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
1945     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
1946     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
1947     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
1948     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
1949     // AVX-512{F,VL} arithmetic instructions 128-bit
1950     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
1951     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
1952     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
1953     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
1954     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
1955     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
1956     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
1957     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
1958     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
1959     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
1960     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
1961     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
1962   };
1963 
1964   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
1965     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1966                   Entry.RegOp, Entry.MemOp,
1967                   // Index 3, folded load
1968                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1969   }
1970 
1971   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
1972      // AVX-512 foldable instructions
1973     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
1974     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
1975     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
1976     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
1977     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
1978     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
1979     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
1980     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
1981     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
1982     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
1983     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
1984     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
1985     // AVX-512{F,VL} foldable instructions 256-bit
1986     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
1987     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
1988     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
1989     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
1990     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
1991     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
1992     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
1993     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
1994     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
1995     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
1996     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
1997     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
1998     // AVX-512{F,VL} foldable instructions 128-bit
1999     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
2000     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
2001     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
2002     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
2003     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
2004     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
2005     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
2006     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
2007     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
2008     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
2009     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
2010     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
2011   };
2012 
2013   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
2014     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2015                   Entry.RegOp, Entry.MemOp,
2016                   // Index 4, folded load
2017                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
2018   }
2019 }
2020 
2021 void
2022 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2023                             MemOp2RegOpTableType &M2RTable,
2024                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
2025     if ((Flags & TB_NO_FORWARD) == 0) {
2026       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2027       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2028     }
2029     if ((Flags & TB_NO_REVERSE) == 0) {
2030       assert(!M2RTable.count(MemOp) &&
2031            "Duplicated entries in unfolding maps?");
2032       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2033     }
2034 }
2035 
2036 bool
2037 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2038                                     unsigned &SrcReg, unsigned &DstReg,
2039                                     unsigned &SubIdx) const {
2040   switch (MI.getOpcode()) {
2041   default: break;
2042   case X86::MOVSX16rr8:
2043   case X86::MOVZX16rr8:
2044   case X86::MOVSX32rr8:
2045   case X86::MOVZX32rr8:
2046   case X86::MOVSX64rr8:
2047     if (!Subtarget.is64Bit())
2048       // It's not always legal to reference the low 8-bit of the larger
2049       // register in 32-bit mode.
2050       return false;
2051   case X86::MOVSX32rr16:
2052   case X86::MOVZX32rr16:
2053   case X86::MOVSX64rr16:
2054   case X86::MOVSX64rr32: {
2055     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2056       // Be conservative.
2057       return false;
2058     SrcReg = MI.getOperand(1).getReg();
2059     DstReg = MI.getOperand(0).getReg();
2060     switch (MI.getOpcode()) {
2061     default: llvm_unreachable("Unreachable!");
2062     case X86::MOVSX16rr8:
2063     case X86::MOVZX16rr8:
2064     case X86::MOVSX32rr8:
2065     case X86::MOVZX32rr8:
2066     case X86::MOVSX64rr8:
2067       SubIdx = X86::sub_8bit;
2068       break;
2069     case X86::MOVSX32rr16:
2070     case X86::MOVZX32rr16:
2071     case X86::MOVSX64rr16:
2072       SubIdx = X86::sub_16bit;
2073       break;
2074     case X86::MOVSX64rr32:
2075       SubIdx = X86::sub_32bit;
2076       break;
2077     }
2078     return true;
2079   }
2080   }
2081   return false;
2082 }
2083 
2084 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
2085   const MachineFunction *MF = MI->getParent()->getParent();
2086   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2087 
2088   if (MI->getOpcode() == getCallFrameSetupOpcode() ||
2089       MI->getOpcode() == getCallFrameDestroyOpcode()) {
2090     unsigned StackAlign = TFI->getStackAlignment();
2091     int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
2092                  StackAlign;
2093 
2094     SPAdj -= MI->getOperand(1).getImm();
2095 
2096     if (MI->getOpcode() == getCallFrameSetupOpcode())
2097       return SPAdj;
2098     else
2099       return -SPAdj;
2100   }
2101 
2102   // To know whether a call adjusts the stack, we need information
2103   // that is bound to the following ADJCALLSTACKUP pseudo.
2104   // Look for the next ADJCALLSTACKUP that follows the call.
2105   if (MI->isCall()) {
2106     const MachineBasicBlock* MBB = MI->getParent();
2107     auto I = ++MachineBasicBlock::const_iterator(MI);
2108     for (auto E = MBB->end(); I != E; ++I) {
2109       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2110           I->isCall())
2111         break;
2112     }
2113 
2114     // If we could not find a frame destroy opcode, then it has already
2115     // been simplified, so we don't care.
2116     if (I->getOpcode() != getCallFrameDestroyOpcode())
2117       return 0;
2118 
2119     return -(I->getOperand(1).getImm());
2120   }
2121 
2122   // Currently handle only PUSHes we can reasonably expect to see
2123   // in call sequences
2124   switch (MI->getOpcode()) {
2125   default:
2126     return 0;
2127   case X86::PUSH32i8:
2128   case X86::PUSH32r:
2129   case X86::PUSH32rmm:
2130   case X86::PUSH32rmr:
2131   case X86::PUSHi32:
2132     return 4;
2133   }
2134 }
2135 
2136 /// Return true and the FrameIndex if the specified
2137 /// operand and follow operands form a reference to the stack frame.
2138 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2139                                   int &FrameIndex) const {
2140   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2141       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2142       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2143       MI->getOperand(Op+X86::AddrDisp).isImm() &&
2144       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2145       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2146       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2147     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
2148     return true;
2149   }
2150   return false;
2151 }
2152 
2153 static bool isFrameLoadOpcode(int Opcode) {
2154   switch (Opcode) {
2155   default:
2156     return false;
2157   case X86::MOV8rm:
2158   case X86::MOV16rm:
2159   case X86::MOV32rm:
2160   case X86::MOV64rm:
2161   case X86::LD_Fp64m:
2162   case X86::MOVSSrm:
2163   case X86::MOVSDrm:
2164   case X86::MOVAPSrm:
2165   case X86::MOVAPDrm:
2166   case X86::MOVDQArm:
2167   case X86::VMOVSSrm:
2168   case X86::VMOVSDrm:
2169   case X86::VMOVAPSrm:
2170   case X86::VMOVAPDrm:
2171   case X86::VMOVDQArm:
2172   case X86::VMOVUPSYrm:
2173   case X86::VMOVAPSYrm:
2174   case X86::VMOVUPDYrm:
2175   case X86::VMOVAPDYrm:
2176   case X86::VMOVDQUYrm:
2177   case X86::VMOVDQAYrm:
2178   case X86::MMX_MOVD64rm:
2179   case X86::MMX_MOVQ64rm:
2180   case X86::VMOVAPSZrm:
2181   case X86::VMOVUPSZrm:
2182     return true;
2183   }
2184 }
2185 
2186 static bool isFrameStoreOpcode(int Opcode) {
2187   switch (Opcode) {
2188   default: break;
2189   case X86::MOV8mr:
2190   case X86::MOV16mr:
2191   case X86::MOV32mr:
2192   case X86::MOV64mr:
2193   case X86::ST_FpP64m:
2194   case X86::MOVSSmr:
2195   case X86::MOVSDmr:
2196   case X86::MOVAPSmr:
2197   case X86::MOVAPDmr:
2198   case X86::MOVDQAmr:
2199   case X86::VMOVSSmr:
2200   case X86::VMOVSDmr:
2201   case X86::VMOVAPSmr:
2202   case X86::VMOVAPDmr:
2203   case X86::VMOVDQAmr:
2204   case X86::VMOVUPSYmr:
2205   case X86::VMOVAPSYmr:
2206   case X86::VMOVUPDYmr:
2207   case X86::VMOVAPDYmr:
2208   case X86::VMOVDQUYmr:
2209   case X86::VMOVDQAYmr:
2210   case X86::VMOVUPSZmr:
2211   case X86::VMOVAPSZmr:
2212   case X86::MMX_MOVD64mr:
2213   case X86::MMX_MOVQ64mr:
2214   case X86::MMX_MOVNTQmr:
2215     return true;
2216   }
2217   return false;
2218 }
2219 
2220 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
2221                                            int &FrameIndex) const {
2222   if (isFrameLoadOpcode(MI->getOpcode()))
2223     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2224       return MI->getOperand(0).getReg();
2225   return 0;
2226 }
2227 
2228 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
2229                                                  int &FrameIndex) const {
2230   if (isFrameLoadOpcode(MI->getOpcode())) {
2231     unsigned Reg;
2232     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2233       return Reg;
2234     // Check for post-frame index elimination operations
2235     const MachineMemOperand *Dummy;
2236     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2237   }
2238   return 0;
2239 }
2240 
2241 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
2242                                           int &FrameIndex) const {
2243   if (isFrameStoreOpcode(MI->getOpcode()))
2244     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2245         isFrameOperand(MI, 0, FrameIndex))
2246       return MI->getOperand(X86::AddrNumOperands).getReg();
2247   return 0;
2248 }
2249 
2250 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2251                                                 int &FrameIndex) const {
2252   if (isFrameStoreOpcode(MI->getOpcode())) {
2253     unsigned Reg;
2254     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2255       return Reg;
2256     // Check for post-frame index elimination operations
2257     const MachineMemOperand *Dummy;
2258     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2259   }
2260   return 0;
2261 }
2262 
2263 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2264 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2265   // Don't waste compile time scanning use-def chains of physregs.
2266   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2267     return false;
2268   bool isPICBase = false;
2269   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2270          E = MRI.def_instr_end(); I != E; ++I) {
2271     MachineInstr *DefMI = &*I;
2272     if (DefMI->getOpcode() != X86::MOVPC32r)
2273       return false;
2274     assert(!isPICBase && "More than one PIC base?");
2275     isPICBase = true;
2276   }
2277   return isPICBase;
2278 }
2279 
2280 bool
2281 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2282                                                 AliasAnalysis *AA) const {
2283   switch (MI->getOpcode()) {
2284   default: break;
2285   case X86::MOV8rm:
2286   case X86::MOV16rm:
2287   case X86::MOV32rm:
2288   case X86::MOV64rm:
2289   case X86::LD_Fp64m:
2290   case X86::MOVSSrm:
2291   case X86::MOVSDrm:
2292   case X86::MOVAPSrm:
2293   case X86::MOVUPSrm:
2294   case X86::MOVAPDrm:
2295   case X86::MOVDQArm:
2296   case X86::MOVDQUrm:
2297   case X86::VMOVSSrm:
2298   case X86::VMOVSDrm:
2299   case X86::VMOVAPSrm:
2300   case X86::VMOVUPSrm:
2301   case X86::VMOVAPDrm:
2302   case X86::VMOVDQArm:
2303   case X86::VMOVDQUrm:
2304   case X86::VMOVAPSYrm:
2305   case X86::VMOVUPSYrm:
2306   case X86::VMOVAPDYrm:
2307   case X86::VMOVDQAYrm:
2308   case X86::VMOVDQUYrm:
2309   case X86::MMX_MOVD64rm:
2310   case X86::MMX_MOVQ64rm:
2311   case X86::FsVMOVAPSrm:
2312   case X86::FsVMOVAPDrm:
2313   case X86::FsMOVAPSrm:
2314   case X86::FsMOVAPDrm:
2315   // AVX-512
2316   case X86::VMOVAPDZ128rm:
2317   case X86::VMOVAPDZ256rm:
2318   case X86::VMOVAPDZrm:
2319   case X86::VMOVAPSZ128rm:
2320   case X86::VMOVAPSZ256rm:
2321   case X86::VMOVAPSZrm:
2322   case X86::VMOVDQA32Z128rm:
2323   case X86::VMOVDQA32Z256rm:
2324   case X86::VMOVDQA32Zrm:
2325   case X86::VMOVDQA64Z128rm:
2326   case X86::VMOVDQA64Z256rm:
2327   case X86::VMOVDQA64Zrm:
2328   case X86::VMOVDQU16Z128rm:
2329   case X86::VMOVDQU16Z256rm:
2330   case X86::VMOVDQU16Zrm:
2331   case X86::VMOVDQU32Z128rm:
2332   case X86::VMOVDQU32Z256rm:
2333   case X86::VMOVDQU32Zrm:
2334   case X86::VMOVDQU64Z128rm:
2335   case X86::VMOVDQU64Z256rm:
2336   case X86::VMOVDQU64Zrm:
2337   case X86::VMOVDQU8Z128rm:
2338   case X86::VMOVDQU8Z256rm:
2339   case X86::VMOVDQU8Zrm:
2340   case X86::VMOVUPSZ128rm:
2341   case X86::VMOVUPSZ256rm:
2342   case X86::VMOVUPSZrm: {
2343     // Loads from constant pools are trivially rematerializable.
2344     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2345         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2346         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2347         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2348         MI->isInvariantLoad(AA)) {
2349       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2350       if (BaseReg == 0 || BaseReg == X86::RIP)
2351         return true;
2352       // Allow re-materialization of PIC load.
2353       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
2354         return false;
2355       const MachineFunction &MF = *MI->getParent()->getParent();
2356       const MachineRegisterInfo &MRI = MF.getRegInfo();
2357       return regIsPICBase(BaseReg, MRI);
2358     }
2359     return false;
2360   }
2361 
2362   case X86::LEA32r:
2363   case X86::LEA64r: {
2364     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2365         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2366         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2367         !MI->getOperand(1+X86::AddrDisp).isReg()) {
2368       // lea fi#, lea GV, etc. are all rematerializable.
2369       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
2370         return true;
2371       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2372       if (BaseReg == 0)
2373         return true;
2374       // Allow re-materialization of lea PICBase + x.
2375       const MachineFunction &MF = *MI->getParent()->getParent();
2376       const MachineRegisterInfo &MRI = MF.getRegInfo();
2377       return regIsPICBase(BaseReg, MRI);
2378     }
2379     return false;
2380   }
2381   }
2382 
2383   // All other instructions marked M_REMATERIALIZABLE are always trivially
2384   // rematerializable.
2385   return true;
2386 }
2387 
2388 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2389                                          MachineBasicBlock::iterator I) const {
2390   MachineBasicBlock::iterator E = MBB.end();
2391 
2392   // For compile time consideration, if we are not able to determine the
2393   // safety after visiting 4 instructions in each direction, we will assume
2394   // it's not safe.
2395   MachineBasicBlock::iterator Iter = I;
2396   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2397     bool SeenDef = false;
2398     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2399       MachineOperand &MO = Iter->getOperand(j);
2400       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2401         SeenDef = true;
2402       if (!MO.isReg())
2403         continue;
2404       if (MO.getReg() == X86::EFLAGS) {
2405         if (MO.isUse())
2406           return false;
2407         SeenDef = true;
2408       }
2409     }
2410 
2411     if (SeenDef)
2412       // This instruction defines EFLAGS, no need to look any further.
2413       return true;
2414     ++Iter;
2415     // Skip over DBG_VALUE.
2416     while (Iter != E && Iter->isDebugValue())
2417       ++Iter;
2418   }
2419 
2420   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2421   // live in.
2422   if (Iter == E) {
2423     for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2424            SE = MBB.succ_end(); SI != SE; ++SI)
2425       if ((*SI)->isLiveIn(X86::EFLAGS))
2426         return false;
2427     return true;
2428   }
2429 
2430   MachineBasicBlock::iterator B = MBB.begin();
2431   Iter = I;
2432   for (unsigned i = 0; i < 4; ++i) {
2433     // If we make it to the beginning of the block, it's safe to clobber
2434     // EFLAGS iff EFLAGS is not live-in.
2435     if (Iter == B)
2436       return !MBB.isLiveIn(X86::EFLAGS);
2437 
2438     --Iter;
2439     // Skip over DBG_VALUE.
2440     while (Iter != B && Iter->isDebugValue())
2441       --Iter;
2442 
2443     bool SawKill = false;
2444     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2445       MachineOperand &MO = Iter->getOperand(j);
2446       // A register mask may clobber EFLAGS, but we should still look for a
2447       // live EFLAGS def.
2448       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2449         SawKill = true;
2450       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2451         if (MO.isDef()) return MO.isDead();
2452         if (MO.isKill()) SawKill = true;
2453       }
2454     }
2455 
2456     if (SawKill)
2457       // This instruction kills EFLAGS and doesn't redefine it, so
2458       // there's no need to look further.
2459       return true;
2460   }
2461 
2462   // Conservative answer.
2463   return false;
2464 }
2465 
2466 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2467                                  MachineBasicBlock::iterator I,
2468                                  unsigned DestReg, unsigned SubIdx,
2469                                  const MachineInstr *Orig,
2470                                  const TargetRegisterInfo &TRI) const {
2471   // MOV32r0 is implemented with a xor which clobbers condition code.
2472   // Re-materialize it as movri instructions to avoid side effects.
2473   unsigned Opc = Orig->getOpcode();
2474   if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2475     DebugLoc DL = Orig->getDebugLoc();
2476     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2477       .addImm(0);
2478   } else {
2479     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2480     MBB.insert(I, MI);
2481   }
2482 
2483   MachineInstr *NewMI = std::prev(I);
2484   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2485 }
2486 
2487 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2488 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr *MI) const {
2489   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2490     MachineOperand &MO = MI->getOperand(i);
2491     if (MO.isReg() && MO.isDef() &&
2492         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2493       return true;
2494     }
2495   }
2496   return false;
2497 }
2498 
2499 /// Check whether the shift count for a machine operand is non-zero.
2500 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2501                                               unsigned ShiftAmtOperandIdx) {
2502   // The shift count is six bits with the REX.W prefix and five bits without.
2503   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2504   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2505   return Imm & ShiftCountMask;
2506 }
2507 
2508 /// Check whether the given shift count is appropriate
2509 /// can be represented by a LEA instruction.
2510 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2511   // Left shift instructions can be transformed into load-effective-address
2512   // instructions if we can encode them appropriately.
2513   // A LEA instruction utilizes a SIB byte to encode its scale factor.
2514   // The SIB.scale field is two bits wide which means that we can encode any
2515   // shift amount less than 4.
2516   return ShAmt < 4 && ShAmt > 0;
2517 }
2518 
2519 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2520                                   unsigned Opc, bool AllowSP,
2521                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
2522                                   MachineOperand &ImplicitOp) const {
2523   MachineFunction &MF = *MI->getParent()->getParent();
2524   const TargetRegisterClass *RC;
2525   if (AllowSP) {
2526     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2527   } else {
2528     RC = Opc != X86::LEA32r ?
2529       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2530   }
2531   unsigned SrcReg = Src.getReg();
2532 
2533   // For both LEA64 and LEA32 the register already has essentially the right
2534   // type (32-bit or 64-bit) we may just need to forbid SP.
2535   if (Opc != X86::LEA64_32r) {
2536     NewSrc = SrcReg;
2537     isKill = Src.isKill();
2538     isUndef = Src.isUndef();
2539 
2540     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2541         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2542       return false;
2543 
2544     return true;
2545   }
2546 
2547   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2548   // another we need to add 64-bit registers to the final MI.
2549   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2550     ImplicitOp = Src;
2551     ImplicitOp.setImplicit();
2552 
2553     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2554     MachineBasicBlock::LivenessQueryResult LQR =
2555       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2556 
2557     switch (LQR) {
2558     case MachineBasicBlock::LQR_Unknown:
2559       // We can't give sane liveness flags to the instruction, abandon LEA
2560       // formation.
2561       return false;
2562     case MachineBasicBlock::LQR_Live:
2563       isKill = MI->killsRegister(SrcReg);
2564       isUndef = false;
2565       break;
2566     default:
2567       // The physreg itself is dead, so we have to use it as an <undef>.
2568       isKill = false;
2569       isUndef = true;
2570       break;
2571     }
2572   } else {
2573     // Virtual register of the wrong class, we have to create a temporary 64-bit
2574     // vreg to feed into the LEA.
2575     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2576     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2577             get(TargetOpcode::COPY))
2578       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2579         .addOperand(Src);
2580 
2581     // Which is obviously going to be dead after we're done with it.
2582     isKill = true;
2583     isUndef = false;
2584   }
2585 
2586   // We've set all the parameters without issue.
2587   return true;
2588 }
2589 
2590 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2591 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2592 /// truncating back down to a 16-bit subregister.
2593 MachineInstr *
2594 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2595                                            MachineFunction::iterator &MFI,
2596                                            MachineBasicBlock::iterator &MBBI,
2597                                            LiveVariables *LV) const {
2598   MachineInstr *MI = MBBI;
2599   unsigned Dest = MI->getOperand(0).getReg();
2600   unsigned Src = MI->getOperand(1).getReg();
2601   bool isDead = MI->getOperand(0).isDead();
2602   bool isKill = MI->getOperand(1).isKill();
2603 
2604   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2605   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2606   unsigned Opc, leaInReg;
2607   if (Subtarget.is64Bit()) {
2608     Opc = X86::LEA64_32r;
2609     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2610   } else {
2611     Opc = X86::LEA32r;
2612     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2613   }
2614 
2615   // Build and insert into an implicit UNDEF value. This is OK because
2616   // well be shifting and then extracting the lower 16-bits.
2617   // This has the potential to cause partial register stall. e.g.
2618   //   movw    (%rbp,%rcx,2), %dx
2619   //   leal    -65(%rdx), %esi
2620   // But testing has shown this *does* help performance in 64-bit mode (at
2621   // least on modern x86 machines).
2622   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2623   MachineInstr *InsMI =
2624     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2625     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2626     .addReg(Src, getKillRegState(isKill));
2627 
2628   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2629                                     get(Opc), leaOutReg);
2630   switch (MIOpc) {
2631   default: llvm_unreachable("Unreachable!");
2632   case X86::SHL16ri: {
2633     unsigned ShAmt = MI->getOperand(2).getImm();
2634     MIB.addReg(0).addImm(1 << ShAmt)
2635        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2636     break;
2637   }
2638   case X86::INC16r:
2639     addRegOffset(MIB, leaInReg, true, 1);
2640     break;
2641   case X86::DEC16r:
2642     addRegOffset(MIB, leaInReg, true, -1);
2643     break;
2644   case X86::ADD16ri:
2645   case X86::ADD16ri8:
2646   case X86::ADD16ri_DB:
2647   case X86::ADD16ri8_DB:
2648     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2649     break;
2650   case X86::ADD16rr:
2651   case X86::ADD16rr_DB: {
2652     unsigned Src2 = MI->getOperand(2).getReg();
2653     bool isKill2 = MI->getOperand(2).isKill();
2654     unsigned leaInReg2 = 0;
2655     MachineInstr *InsMI2 = nullptr;
2656     if (Src == Src2) {
2657       // ADD16rr %reg1028<kill>, %reg1028
2658       // just a single insert_subreg.
2659       addRegReg(MIB, leaInReg, true, leaInReg, false);
2660     } else {
2661       if (Subtarget.is64Bit())
2662         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2663       else
2664         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2665       // Build and insert into an implicit UNDEF value. This is OK because
2666       // well be shifting and then extracting the lower 16-bits.
2667       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2668       InsMI2 =
2669         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2670         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2671         .addReg(Src2, getKillRegState(isKill2));
2672       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2673     }
2674     if (LV && isKill2 && InsMI2)
2675       LV->replaceKillInstruction(Src2, MI, InsMI2);
2676     break;
2677   }
2678   }
2679 
2680   MachineInstr *NewMI = MIB;
2681   MachineInstr *ExtMI =
2682     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2683     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2684     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2685 
2686   if (LV) {
2687     // Update live variables
2688     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2689     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2690     if (isKill)
2691       LV->replaceKillInstruction(Src, MI, InsMI);
2692     if (isDead)
2693       LV->replaceKillInstruction(Dest, MI, ExtMI);
2694   }
2695 
2696   return ExtMI;
2697 }
2698 
2699 /// This method must be implemented by targets that
2700 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2701 /// may be able to convert a two-address instruction into a true
2702 /// three-address instruction on demand.  This allows the X86 target (for
2703 /// example) to convert ADD and SHL instructions into LEA instructions if they
2704 /// would require register copies due to two-addressness.
2705 ///
2706 /// This method returns a null pointer if the transformation cannot be
2707 /// performed, otherwise it returns the new instruction.
2708 ///
2709 MachineInstr *
2710 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2711                                     MachineBasicBlock::iterator &MBBI,
2712                                     LiveVariables *LV) const {
2713   MachineInstr *MI = MBBI;
2714 
2715   // The following opcodes also sets the condition code register(s). Only
2716   // convert them to equivalent lea if the condition code register def's
2717   // are dead!
2718   if (hasLiveCondCodeDef(MI))
2719     return nullptr;
2720 
2721   MachineFunction &MF = *MI->getParent()->getParent();
2722   // All instructions input are two-addr instructions.  Get the known operands.
2723   const MachineOperand &Dest = MI->getOperand(0);
2724   const MachineOperand &Src = MI->getOperand(1);
2725 
2726   MachineInstr *NewMI = nullptr;
2727   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2728   // we have better subtarget support, enable the 16-bit LEA generation here.
2729   // 16-bit LEA is also slow on Core2.
2730   bool DisableLEA16 = true;
2731   bool is64Bit = Subtarget.is64Bit();
2732 
2733   unsigned MIOpc = MI->getOpcode();
2734   switch (MIOpc) {
2735   default: return nullptr;
2736   case X86::SHL64ri: {
2737     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2738     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2739     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2740 
2741     // LEA can't handle RSP.
2742     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2743         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2744                                            &X86::GR64_NOSPRegClass))
2745       return nullptr;
2746 
2747     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2748       .addOperand(Dest)
2749       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2750     break;
2751   }
2752   case X86::SHL32ri: {
2753     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2754     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2755     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2756 
2757     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2758 
2759     // LEA can't handle ESP.
2760     bool isKill, isUndef;
2761     unsigned SrcReg;
2762     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2763     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2764                         SrcReg, isKill, isUndef, ImplicitOp))
2765       return nullptr;
2766 
2767     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2768       .addOperand(Dest)
2769       .addReg(0).addImm(1 << ShAmt)
2770       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2771       .addImm(0).addReg(0);
2772     if (ImplicitOp.getReg() != 0)
2773       MIB.addOperand(ImplicitOp);
2774     NewMI = MIB;
2775 
2776     break;
2777   }
2778   case X86::SHL16ri: {
2779     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2780     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2781     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2782 
2783     if (DisableLEA16)
2784       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2785     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2786       .addOperand(Dest)
2787       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2788     break;
2789   }
2790   case X86::INC64r:
2791   case X86::INC32r: {
2792     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2793     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2794       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2795     bool isKill, isUndef;
2796     unsigned SrcReg;
2797     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2798     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2799                         SrcReg, isKill, isUndef, ImplicitOp))
2800       return nullptr;
2801 
2802     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2803         .addOperand(Dest)
2804         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2805     if (ImplicitOp.getReg() != 0)
2806       MIB.addOperand(ImplicitOp);
2807 
2808     NewMI = addOffset(MIB, 1);
2809     break;
2810   }
2811   case X86::INC16r:
2812     if (DisableLEA16)
2813       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2814                      : nullptr;
2815     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2816     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2817                       .addOperand(Dest).addOperand(Src), 1);
2818     break;
2819   case X86::DEC64r:
2820   case X86::DEC32r: {
2821     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2822     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2823       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2824 
2825     bool isKill, isUndef;
2826     unsigned SrcReg;
2827     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2828     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2829                         SrcReg, isKill, isUndef, ImplicitOp))
2830       return nullptr;
2831 
2832     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2833         .addOperand(Dest)
2834         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2835     if (ImplicitOp.getReg() != 0)
2836       MIB.addOperand(ImplicitOp);
2837 
2838     NewMI = addOffset(MIB, -1);
2839 
2840     break;
2841   }
2842   case X86::DEC16r:
2843     if (DisableLEA16)
2844       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2845                      : nullptr;
2846     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2847     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2848                       .addOperand(Dest).addOperand(Src), -1);
2849     break;
2850   case X86::ADD64rr:
2851   case X86::ADD64rr_DB:
2852   case X86::ADD32rr:
2853   case X86::ADD32rr_DB: {
2854     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2855     unsigned Opc;
2856     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2857       Opc = X86::LEA64r;
2858     else
2859       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2860 
2861     bool isKill, isUndef;
2862     unsigned SrcReg;
2863     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2864     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2865                         SrcReg, isKill, isUndef, ImplicitOp))
2866       return nullptr;
2867 
2868     const MachineOperand &Src2 = MI->getOperand(2);
2869     bool isKill2, isUndef2;
2870     unsigned SrcReg2;
2871     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2872     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2873                         SrcReg2, isKill2, isUndef2, ImplicitOp2))
2874       return nullptr;
2875 
2876     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2877       .addOperand(Dest);
2878     if (ImplicitOp.getReg() != 0)
2879       MIB.addOperand(ImplicitOp);
2880     if (ImplicitOp2.getReg() != 0)
2881       MIB.addOperand(ImplicitOp2);
2882 
2883     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2884 
2885     // Preserve undefness of the operands.
2886     NewMI->getOperand(1).setIsUndef(isUndef);
2887     NewMI->getOperand(3).setIsUndef(isUndef2);
2888 
2889     if (LV && Src2.isKill())
2890       LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2891     break;
2892   }
2893   case X86::ADD16rr:
2894   case X86::ADD16rr_DB: {
2895     if (DisableLEA16)
2896       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2897                      : nullptr;
2898     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2899     unsigned Src2 = MI->getOperand(2).getReg();
2900     bool isKill2 = MI->getOperand(2).isKill();
2901     NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2902                       .addOperand(Dest),
2903                       Src.getReg(), Src.isKill(), Src2, isKill2);
2904 
2905     // Preserve undefness of the operands.
2906     bool isUndef = MI->getOperand(1).isUndef();
2907     bool isUndef2 = MI->getOperand(2).isUndef();
2908     NewMI->getOperand(1).setIsUndef(isUndef);
2909     NewMI->getOperand(3).setIsUndef(isUndef2);
2910 
2911     if (LV && isKill2)
2912       LV->replaceKillInstruction(Src2, MI, NewMI);
2913     break;
2914   }
2915   case X86::ADD64ri32:
2916   case X86::ADD64ri8:
2917   case X86::ADD64ri32_DB:
2918   case X86::ADD64ri8_DB:
2919     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2920     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2921                       .addOperand(Dest).addOperand(Src),
2922                       MI->getOperand(2).getImm());
2923     break;
2924   case X86::ADD32ri:
2925   case X86::ADD32ri8:
2926   case X86::ADD32ri_DB:
2927   case X86::ADD32ri8_DB: {
2928     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2929     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2930 
2931     bool isKill, isUndef;
2932     unsigned SrcReg;
2933     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2934     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2935                         SrcReg, isKill, isUndef, ImplicitOp))
2936       return nullptr;
2937 
2938     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2939         .addOperand(Dest)
2940         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2941     if (ImplicitOp.getReg() != 0)
2942       MIB.addOperand(ImplicitOp);
2943 
2944     NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2945     break;
2946   }
2947   case X86::ADD16ri:
2948   case X86::ADD16ri8:
2949   case X86::ADD16ri_DB:
2950   case X86::ADD16ri8_DB:
2951     if (DisableLEA16)
2952       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2953                      : nullptr;
2954     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2955     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2956                       .addOperand(Dest).addOperand(Src),
2957                       MI->getOperand(2).getImm());
2958     break;
2959   }
2960 
2961   if (!NewMI) return nullptr;
2962 
2963   if (LV) {  // Update live variables
2964     if (Src.isKill())
2965       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2966     if (Dest.isDead())
2967       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2968   }
2969 
2970   MFI->insert(MBBI, NewMI);          // Insert the new inst
2971   return NewMI;
2972 }
2973 
2974 /// Returns true if the given instruction opcode is FMA3.
2975 /// Otherwise, returns false.
2976 static bool isFMA3(unsigned Opcode) {
2977   switch (Opcode) {
2978     case X86::VFMADDSDr132r:     case X86::VFMADDSDr132m:
2979     case X86::VFMADDSSr132r:     case X86::VFMADDSSr132m:
2980     case X86::VFMSUBSDr132r:     case X86::VFMSUBSDr132m:
2981     case X86::VFMSUBSSr132r:     case X86::VFMSUBSSr132m:
2982     case X86::VFNMADDSDr132r:    case X86::VFNMADDSDr132m:
2983     case X86::VFNMADDSSr132r:    case X86::VFNMADDSSr132m:
2984     case X86::VFNMSUBSDr132r:    case X86::VFNMSUBSDr132m:
2985     case X86::VFNMSUBSSr132r:    case X86::VFNMSUBSSr132m:
2986 
2987     case X86::VFMADDSDr213r:     case X86::VFMADDSDr213m:
2988     case X86::VFMADDSSr213r:     case X86::VFMADDSSr213m:
2989     case X86::VFMSUBSDr213r:     case X86::VFMSUBSDr213m:
2990     case X86::VFMSUBSSr213r:     case X86::VFMSUBSSr213m:
2991     case X86::VFNMADDSDr213r:    case X86::VFNMADDSDr213m:
2992     case X86::VFNMADDSSr213r:    case X86::VFNMADDSSr213m:
2993     case X86::VFNMSUBSDr213r:    case X86::VFNMSUBSDr213m:
2994     case X86::VFNMSUBSSr213r:    case X86::VFNMSUBSSr213m:
2995 
2996     case X86::VFMADDSDr231r:     case X86::VFMADDSDr231m:
2997     case X86::VFMADDSSr231r:     case X86::VFMADDSSr231m:
2998     case X86::VFMSUBSDr231r:     case X86::VFMSUBSDr231m:
2999     case X86::VFMSUBSSr231r:     case X86::VFMSUBSSr231m:
3000     case X86::VFNMADDSDr231r:    case X86::VFNMADDSDr231m:
3001     case X86::VFNMADDSSr231r:    case X86::VFNMADDSSr231m:
3002     case X86::VFNMSUBSDr231r:    case X86::VFNMSUBSDr231m:
3003     case X86::VFNMSUBSSr231r:    case X86::VFNMSUBSSr231m:
3004 
3005     case X86::VFMADDSUBPDr132r:  case X86::VFMADDSUBPDr132m:
3006     case X86::VFMADDSUBPSr132r:  case X86::VFMADDSUBPSr132m:
3007     case X86::VFMSUBADDPDr132r:  case X86::VFMSUBADDPDr132m:
3008     case X86::VFMSUBADDPSr132r:  case X86::VFMSUBADDPSr132m:
3009     case X86::VFMADDSUBPDr132rY: case X86::VFMADDSUBPDr132mY:
3010     case X86::VFMADDSUBPSr132rY: case X86::VFMADDSUBPSr132mY:
3011     case X86::VFMSUBADDPDr132rY: case X86::VFMSUBADDPDr132mY:
3012     case X86::VFMSUBADDPSr132rY: case X86::VFMSUBADDPSr132mY:
3013 
3014     case X86::VFMADDPDr132r:     case X86::VFMADDPDr132m:
3015     case X86::VFMADDPSr132r:     case X86::VFMADDPSr132m:
3016     case X86::VFMSUBPDr132r:     case X86::VFMSUBPDr132m:
3017     case X86::VFMSUBPSr132r:     case X86::VFMSUBPSr132m:
3018     case X86::VFNMADDPDr132r:    case X86::VFNMADDPDr132m:
3019     case X86::VFNMADDPSr132r:    case X86::VFNMADDPSr132m:
3020     case X86::VFNMSUBPDr132r:    case X86::VFNMSUBPDr132m:
3021     case X86::VFNMSUBPSr132r:    case X86::VFNMSUBPSr132m:
3022     case X86::VFMADDPDr132rY:    case X86::VFMADDPDr132mY:
3023     case X86::VFMADDPSr132rY:    case X86::VFMADDPSr132mY:
3024     case X86::VFMSUBPDr132rY:    case X86::VFMSUBPDr132mY:
3025     case X86::VFMSUBPSr132rY:    case X86::VFMSUBPSr132mY:
3026     case X86::VFNMADDPDr132rY:   case X86::VFNMADDPDr132mY:
3027     case X86::VFNMADDPSr132rY:   case X86::VFNMADDPSr132mY:
3028     case X86::VFNMSUBPDr132rY:   case X86::VFNMSUBPDr132mY:
3029     case X86::VFNMSUBPSr132rY:   case X86::VFNMSUBPSr132mY:
3030 
3031     case X86::VFMADDSUBPDr213r:  case X86::VFMADDSUBPDr213m:
3032     case X86::VFMADDSUBPSr213r:  case X86::VFMADDSUBPSr213m:
3033     case X86::VFMSUBADDPDr213r:  case X86::VFMSUBADDPDr213m:
3034     case X86::VFMSUBADDPSr213r:  case X86::VFMSUBADDPSr213m:
3035     case X86::VFMADDSUBPDr213rY: case X86::VFMADDSUBPDr213mY:
3036     case X86::VFMADDSUBPSr213rY: case X86::VFMADDSUBPSr213mY:
3037     case X86::VFMSUBADDPDr213rY: case X86::VFMSUBADDPDr213mY:
3038     case X86::VFMSUBADDPSr213rY: case X86::VFMSUBADDPSr213mY:
3039 
3040     case X86::VFMADDPDr213r:     case X86::VFMADDPDr213m:
3041     case X86::VFMADDPSr213r:     case X86::VFMADDPSr213m:
3042     case X86::VFMSUBPDr213r:     case X86::VFMSUBPDr213m:
3043     case X86::VFMSUBPSr213r:     case X86::VFMSUBPSr213m:
3044     case X86::VFNMADDPDr213r:    case X86::VFNMADDPDr213m:
3045     case X86::VFNMADDPSr213r:    case X86::VFNMADDPSr213m:
3046     case X86::VFNMSUBPDr213r:    case X86::VFNMSUBPDr213m:
3047     case X86::VFNMSUBPSr213r:    case X86::VFNMSUBPSr213m:
3048     case X86::VFMADDPDr213rY:    case X86::VFMADDPDr213mY:
3049     case X86::VFMADDPSr213rY:    case X86::VFMADDPSr213mY:
3050     case X86::VFMSUBPDr213rY:    case X86::VFMSUBPDr213mY:
3051     case X86::VFMSUBPSr213rY:    case X86::VFMSUBPSr213mY:
3052     case X86::VFNMADDPDr213rY:   case X86::VFNMADDPDr213mY:
3053     case X86::VFNMADDPSr213rY:   case X86::VFNMADDPSr213mY:
3054     case X86::VFNMSUBPDr213rY:   case X86::VFNMSUBPDr213mY:
3055     case X86::VFNMSUBPSr213rY:   case X86::VFNMSUBPSr213mY:
3056 
3057     case X86::VFMADDSUBPDr231r:  case X86::VFMADDSUBPDr231m:
3058     case X86::VFMADDSUBPSr231r:  case X86::VFMADDSUBPSr231m:
3059     case X86::VFMSUBADDPDr231r:  case X86::VFMSUBADDPDr231m:
3060     case X86::VFMSUBADDPSr231r:  case X86::VFMSUBADDPSr231m:
3061     case X86::VFMADDSUBPDr231rY: case X86::VFMADDSUBPDr231mY:
3062     case X86::VFMADDSUBPSr231rY: case X86::VFMADDSUBPSr231mY:
3063     case X86::VFMSUBADDPDr231rY: case X86::VFMSUBADDPDr231mY:
3064     case X86::VFMSUBADDPSr231rY: case X86::VFMSUBADDPSr231mY:
3065 
3066     case X86::VFMADDPDr231r:     case X86::VFMADDPDr231m:
3067     case X86::VFMADDPSr231r:     case X86::VFMADDPSr231m:
3068     case X86::VFMSUBPDr231r:     case X86::VFMSUBPDr231m:
3069     case X86::VFMSUBPSr231r:     case X86::VFMSUBPSr231m:
3070     case X86::VFNMADDPDr231r:    case X86::VFNMADDPDr231m:
3071     case X86::VFNMADDPSr231r:    case X86::VFNMADDPSr231m:
3072     case X86::VFNMSUBPDr231r:    case X86::VFNMSUBPDr231m:
3073     case X86::VFNMSUBPSr231r:    case X86::VFNMSUBPSr231m:
3074     case X86::VFMADDPDr231rY:    case X86::VFMADDPDr231mY:
3075     case X86::VFMADDPSr231rY:    case X86::VFMADDPSr231mY:
3076     case X86::VFMSUBPDr231rY:    case X86::VFMSUBPDr231mY:
3077     case X86::VFMSUBPSr231rY:    case X86::VFMSUBPSr231mY:
3078     case X86::VFNMADDPDr231rY:   case X86::VFNMADDPDr231mY:
3079     case X86::VFNMADDPSr231rY:   case X86::VFNMADDPSr231mY:
3080     case X86::VFNMSUBPDr231rY:   case X86::VFNMSUBPDr231mY:
3081     case X86::VFNMSUBPSr231rY:   case X86::VFNMSUBPSr231mY:
3082       return true;
3083     default:
3084       return false;
3085   }
3086   llvm_unreachable("Opcode not handled by the switch");
3087 }
3088 
3089 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr *MI,
3090                                                    bool NewMI,
3091                                                    unsigned OpIdx1,
3092                                                    unsigned OpIdx2) const {
3093   switch (MI->getOpcode()) {
3094   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3095   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
3096   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
3097   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3098   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3099   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
3100     unsigned Opc;
3101     unsigned Size;
3102     switch (MI->getOpcode()) {
3103     default: llvm_unreachable("Unreachable!");
3104     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3105     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3106     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3107     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
3108     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3109     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
3110     }
3111     unsigned Amt = MI->getOperand(3).getImm();
3112     if (NewMI) {
3113       MachineFunction &MF = *MI->getParent()->getParent();
3114       MI = MF.CloneMachineInstr(MI);
3115       NewMI = false;
3116     }
3117     MI->setDesc(get(Opc));
3118     MI->getOperand(3).setImm(Size-Amt);
3119     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3120   }
3121   case X86::BLENDPDrri:
3122   case X86::BLENDPSrri:
3123   case X86::PBLENDWrri:
3124   case X86::VBLENDPDrri:
3125   case X86::VBLENDPSrri:
3126   case X86::VBLENDPDYrri:
3127   case X86::VBLENDPSYrri:
3128   case X86::VPBLENDDrri:
3129   case X86::VPBLENDWrri:
3130   case X86::VPBLENDDYrri:
3131   case X86::VPBLENDWYrri:{
3132     unsigned Mask;
3133     switch (MI->getOpcode()) {
3134     default: llvm_unreachable("Unreachable!");
3135     case X86::BLENDPDrri:    Mask = 0x03; break;
3136     case X86::BLENDPSrri:    Mask = 0x0F; break;
3137     case X86::PBLENDWrri:    Mask = 0xFF; break;
3138     case X86::VBLENDPDrri:   Mask = 0x03; break;
3139     case X86::VBLENDPSrri:   Mask = 0x0F; break;
3140     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
3141     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
3142     case X86::VPBLENDDrri:   Mask = 0x0F; break;
3143     case X86::VPBLENDWrri:   Mask = 0xFF; break;
3144     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
3145     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
3146     }
3147     // Only the least significant bits of Imm are used.
3148     unsigned Imm = MI->getOperand(3).getImm() & Mask;
3149     if (NewMI) {
3150       MachineFunction &MF = *MI->getParent()->getParent();
3151       MI = MF.CloneMachineInstr(MI);
3152       NewMI = false;
3153     }
3154     MI->getOperand(3).setImm(Mask ^ Imm);
3155     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3156   }
3157   case X86::PCLMULQDQrr:
3158   case X86::VPCLMULQDQrr:{
3159     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3160     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3161     unsigned Imm = MI->getOperand(3).getImm();
3162     unsigned Src1Hi = Imm & 0x01;
3163     unsigned Src2Hi = Imm & 0x10;
3164     if (NewMI) {
3165       MachineFunction &MF = *MI->getParent()->getParent();
3166       MI = MF.CloneMachineInstr(MI);
3167       NewMI = false;
3168     }
3169     MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3170     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3171   }
3172   case X86::CMPPDrri:
3173   case X86::CMPPSrri:
3174   case X86::VCMPPDrri:
3175   case X86::VCMPPSrri:
3176   case X86::VCMPPDYrri:
3177   case X86::VCMPPSYrri: {
3178     // Float comparison can be safely commuted for
3179     // Ordered/Unordered/Equal/NotEqual tests
3180     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3181     switch (Imm) {
3182     case 0x00: // EQUAL
3183     case 0x03: // UNORDERED
3184     case 0x04: // NOT EQUAL
3185     case 0x07: // ORDERED
3186       if (NewMI) {
3187         MachineFunction &MF = *MI->getParent()->getParent();
3188         MI = MF.CloneMachineInstr(MI);
3189         NewMI = false;
3190       }
3191       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3192     default:
3193       return nullptr;
3194     }
3195   }
3196   case X86::VPCOMBri: case X86::VPCOMUBri:
3197   case X86::VPCOMDri: case X86::VPCOMUDri:
3198   case X86::VPCOMQri: case X86::VPCOMUQri:
3199   case X86::VPCOMWri: case X86::VPCOMUWri: {
3200     // Flip comparison mode immediate (if necessary).
3201     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3202     switch (Imm) {
3203     case 0x00: Imm = 0x02; break; // LT -> GT
3204     case 0x01: Imm = 0x03; break; // LE -> GE
3205     case 0x02: Imm = 0x00; break; // GT -> LT
3206     case 0x03: Imm = 0x01; break; // GE -> LE
3207     case 0x04: // EQ
3208     case 0x05: // NE
3209     case 0x06: // FALSE
3210     case 0x07: // TRUE
3211     default:
3212       break;
3213     }
3214     if (NewMI) {
3215       MachineFunction &MF = *MI->getParent()->getParent();
3216       MI = MF.CloneMachineInstr(MI);
3217       NewMI = false;
3218     }
3219     MI->getOperand(3).setImm(Imm);
3220     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3221   }
3222   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
3223   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3224   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
3225   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3226   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3227   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
3228   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
3229   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3230   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3231   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
3232   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
3233   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3234   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
3235   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3236   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
3237   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3238     unsigned Opc;
3239     switch (MI->getOpcode()) {
3240     default: llvm_unreachable("Unreachable!");
3241     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
3242     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
3243     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
3244     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3245     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3246     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3247     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
3248     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
3249     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
3250     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3251     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3252     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
3253     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3254     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3255     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3256     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
3257     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
3258     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
3259     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
3260     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
3261     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
3262     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3263     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3264     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3265     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3266     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3267     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3268     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
3269     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
3270     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
3271     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
3272     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
3273     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
3274     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3275     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3276     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3277     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
3278     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
3279     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
3280     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3281     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3282     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3283     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
3284     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
3285     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
3286     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3287     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3288     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3289     }
3290     if (NewMI) {
3291       MachineFunction &MF = *MI->getParent()->getParent();
3292       MI = MF.CloneMachineInstr(MI);
3293       NewMI = false;
3294     }
3295     MI->setDesc(get(Opc));
3296     // Fallthrough intended.
3297   }
3298   default:
3299     if (isFMA3(MI->getOpcode())) {
3300       unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
3301       if (Opc == 0)
3302         return nullptr;
3303       if (NewMI) {
3304         MachineFunction &MF = *MI->getParent()->getParent();
3305         MI = MF.CloneMachineInstr(MI);
3306         NewMI = false;
3307       }
3308       MI->setDesc(get(Opc));
3309     }
3310     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3311   }
3312 }
3313 
3314 bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr *MI,
3315                                              unsigned &SrcOpIdx1,
3316                                              unsigned &SrcOpIdx2) const {
3317 
3318   unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3319 
3320   // Only the first RegOpsNum operands are commutable.
3321   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3322   // that the operand is not specified/fixed.
3323   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3324       (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3325     return false;
3326   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3327       (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3328     return false;
3329 
3330   // Look for two different register operands assumed to be commutable
3331   // regardless of the FMA opcode. The FMA opcode is adjusted later.
3332   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3333       SrcOpIdx2 == CommuteAnyOperandIndex) {
3334     unsigned CommutableOpIdx1 = SrcOpIdx1;
3335     unsigned CommutableOpIdx2 = SrcOpIdx2;
3336 
3337     // At least one of operands to be commuted is not specified and
3338     // this method is free to choose appropriate commutable operands.
3339     if (SrcOpIdx1 == SrcOpIdx2)
3340       // Both of operands are not fixed. By default set one of commutable
3341       // operands to the last register operand of the instruction.
3342       CommutableOpIdx2 = RegOpsNum;
3343     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3344       // Only one of operands is not fixed.
3345       CommutableOpIdx2 = SrcOpIdx1;
3346 
3347     // CommutableOpIdx2 is well defined now. Let's choose another commutable
3348     // operand and assign its index to CommutableOpIdx1.
3349     unsigned Op2Reg = MI->getOperand(CommutableOpIdx2).getReg();
3350     for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3351       // The commuted operands must have different registers.
3352       // Otherwise, the commute transformation does not change anything and
3353       // is useless then.
3354       if (Op2Reg != MI->getOperand(CommutableOpIdx1).getReg())
3355         break;
3356     }
3357 
3358     // No appropriate commutable operands were found.
3359     if (CommutableOpIdx1 == 0)
3360       return false;
3361 
3362     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3363     // to return those values.
3364     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3365                               CommutableOpIdx1, CommutableOpIdx2))
3366       return false;
3367   }
3368 
3369   // Check if we can adjust the opcode to preserve the semantics when
3370   // commute the register operands.
3371   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
3372 }
3373 
3374 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(MachineInstr *MI,
3375                                                       unsigned SrcOpIdx1,
3376                                                       unsigned SrcOpIdx2) const {
3377   unsigned Opc = MI->getOpcode();
3378 
3379   // Define the array that holds FMA opcodes in groups
3380   // of 3 opcodes(132, 213, 231) in each group.
3381   static const unsigned OpcodeGroups[][3] = {
3382     { X86::VFMADDSSr132r,   X86::VFMADDSSr213r,   X86::VFMADDSSr231r  },
3383     { X86::VFMADDSDr132r,   X86::VFMADDSDr213r,   X86::VFMADDSDr231r  },
3384     { X86::VFMADDPSr132r,   X86::VFMADDPSr213r,   X86::VFMADDPSr231r  },
3385     { X86::VFMADDPDr132r,   X86::VFMADDPDr213r,   X86::VFMADDPDr231r  },
3386     { X86::VFMADDPSr132rY,  X86::VFMADDPSr213rY,  X86::VFMADDPSr231rY },
3387     { X86::VFMADDPDr132rY,  X86::VFMADDPDr213rY,  X86::VFMADDPDr231rY },
3388     { X86::VFMADDSSr132m,   X86::VFMADDSSr213m,   X86::VFMADDSSr231m  },
3389     { X86::VFMADDSDr132m,   X86::VFMADDSDr213m,   X86::VFMADDSDr231m  },
3390     { X86::VFMADDPSr132m,   X86::VFMADDPSr213m,   X86::VFMADDPSr231m  },
3391     { X86::VFMADDPDr132m,   X86::VFMADDPDr213m,   X86::VFMADDPDr231m  },
3392     { X86::VFMADDPSr132mY,  X86::VFMADDPSr213mY,  X86::VFMADDPSr231mY },
3393     { X86::VFMADDPDr132mY,  X86::VFMADDPDr213mY,  X86::VFMADDPDr231mY },
3394 
3395     { X86::VFMSUBSSr132r,   X86::VFMSUBSSr213r,   X86::VFMSUBSSr231r  },
3396     { X86::VFMSUBSDr132r,   X86::VFMSUBSDr213r,   X86::VFMSUBSDr231r  },
3397     { X86::VFMSUBPSr132r,   X86::VFMSUBPSr213r,   X86::VFMSUBPSr231r  },
3398     { X86::VFMSUBPDr132r,   X86::VFMSUBPDr213r,   X86::VFMSUBPDr231r  },
3399     { X86::VFMSUBPSr132rY,  X86::VFMSUBPSr213rY,  X86::VFMSUBPSr231rY },
3400     { X86::VFMSUBPDr132rY,  X86::VFMSUBPDr213rY,  X86::VFMSUBPDr231rY },
3401     { X86::VFMSUBSSr132m,   X86::VFMSUBSSr213m,   X86::VFMSUBSSr231m  },
3402     { X86::VFMSUBSDr132m,   X86::VFMSUBSDr213m,   X86::VFMSUBSDr231m  },
3403     { X86::VFMSUBPSr132m,   X86::VFMSUBPSr213m,   X86::VFMSUBPSr231m  },
3404     { X86::VFMSUBPDr132m,   X86::VFMSUBPDr213m,   X86::VFMSUBPDr231m  },
3405     { X86::VFMSUBPSr132mY,  X86::VFMSUBPSr213mY,  X86::VFMSUBPSr231mY },
3406     { X86::VFMSUBPDr132mY,  X86::VFMSUBPDr213mY,  X86::VFMSUBPDr231mY },
3407 
3408     { X86::VFNMADDSSr132r,  X86::VFNMADDSSr213r,  X86::VFNMADDSSr231r  },
3409     { X86::VFNMADDSDr132r,  X86::VFNMADDSDr213r,  X86::VFNMADDSDr231r  },
3410     { X86::VFNMADDPSr132r,  X86::VFNMADDPSr213r,  X86::VFNMADDPSr231r  },
3411     { X86::VFNMADDPDr132r,  X86::VFNMADDPDr213r,  X86::VFNMADDPDr231r  },
3412     { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
3413     { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
3414     { X86::VFNMADDSSr132m,  X86::VFNMADDSSr213m,  X86::VFNMADDSSr231m  },
3415     { X86::VFNMADDSDr132m,  X86::VFNMADDSDr213m,  X86::VFNMADDSDr231m  },
3416     { X86::VFNMADDPSr132m,  X86::VFNMADDPSr213m,  X86::VFNMADDPSr231m  },
3417     { X86::VFNMADDPDr132m,  X86::VFNMADDPDr213m,  X86::VFNMADDPDr231m  },
3418     { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
3419     { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
3420 
3421     { X86::VFNMSUBSSr132r,  X86::VFNMSUBSSr213r,  X86::VFNMSUBSSr231r  },
3422     { X86::VFNMSUBSDr132r,  X86::VFNMSUBSDr213r,  X86::VFNMSUBSDr231r  },
3423     { X86::VFNMSUBPSr132r,  X86::VFNMSUBPSr213r,  X86::VFNMSUBPSr231r  },
3424     { X86::VFNMSUBPDr132r,  X86::VFNMSUBPDr213r,  X86::VFNMSUBPDr231r  },
3425     { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
3426     { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
3427     { X86::VFNMSUBSSr132m,  X86::VFNMSUBSSr213m,  X86::VFNMSUBSSr231m  },
3428     { X86::VFNMSUBSDr132m,  X86::VFNMSUBSDr213m,  X86::VFNMSUBSDr231m  },
3429     { X86::VFNMSUBPSr132m,  X86::VFNMSUBPSr213m,  X86::VFNMSUBPSr231m  },
3430     { X86::VFNMSUBPDr132m,  X86::VFNMSUBPDr213m,  X86::VFNMSUBPDr231m  },
3431     { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
3432     { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
3433 
3434     { X86::VFMADDSUBPSr132r,  X86::VFMADDSUBPSr213r,  X86::VFMADDSUBPSr231r  },
3435     { X86::VFMADDSUBPDr132r,  X86::VFMADDSUBPDr213r,  X86::VFMADDSUBPDr231r  },
3436     { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
3437     { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
3438     { X86::VFMADDSUBPSr132m,  X86::VFMADDSUBPSr213m,  X86::VFMADDSUBPSr231m  },
3439     { X86::VFMADDSUBPDr132m,  X86::VFMADDSUBPDr213m,  X86::VFMADDSUBPDr231m  },
3440     { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
3441     { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
3442 
3443     { X86::VFMSUBADDPSr132r,  X86::VFMSUBADDPSr213r,  X86::VFMSUBADDPSr231r  },
3444     { X86::VFMSUBADDPDr132r,  X86::VFMSUBADDPDr213r,  X86::VFMSUBADDPDr231r  },
3445     { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
3446     { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
3447     { X86::VFMSUBADDPSr132m,  X86::VFMSUBADDPSr213m,  X86::VFMSUBADDPSr231m  },
3448     { X86::VFMSUBADDPDr132m,  X86::VFMSUBADDPDr213m,  X86::VFMSUBADDPDr231m  },
3449     { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
3450     { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
3451   };
3452   const unsigned Form132Index = 0;
3453   const unsigned Form213Index = 1;
3454   const unsigned Form231Index = 2;
3455   const unsigned FormsNum = 3;
3456 
3457   // Look for the input opcode in the OpcodeGroups table.
3458   unsigned OpcodeGroupsNum = sizeof(OpcodeGroups) / sizeof(OpcodeGroups[0]);
3459   unsigned GroupIndex = 0, FormIndex = FormsNum;
3460   for (; GroupIndex < OpcodeGroupsNum && FormIndex == FormsNum; GroupIndex++) {
3461     for (FormIndex = 0; FormIndex < FormsNum; FormIndex++) {
3462       if (OpcodeGroups[GroupIndex][FormIndex] == Opc)
3463         break;
3464     }
3465   }
3466   // Input opcode does not match with any of the opcodes from the table.
3467   if (FormIndex == FormsNum)
3468     return 0;
3469   // Do not forget to fix the GroupIndex after the loop.
3470   GroupIndex--;
3471 
3472   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3473   if (SrcOpIdx1 > SrcOpIdx2)
3474     std::swap(SrcOpIdx1, SrcOpIdx2);
3475 
3476   unsigned Case;
3477   if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
3478     Case = 0;
3479   else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3480     Case = 1;
3481   else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3482     Case = 2;
3483   else
3484     return 0;
3485 
3486   // Define the FMA forms mapping array that helps to map input FMA form
3487   // to output FMA form to preserve the operation semantics after
3488   // commuting the operands.
3489   static const unsigned FormMapping[][3] = {
3490     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3491     // FMA132 A, C, b; ==> FMA231 C, A, b;
3492     // FMA213 B, A, c; ==> FMA213 A, B, c;
3493     // FMA231 C, A, b; ==> FMA132 A, C, b;
3494     { Form231Index, Form213Index, Form132Index },
3495     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3496     // FMA132 A, c, B; ==> FMA132 B, c, A;
3497     // FMA213 B, a, C; ==> FMA231 C, a, B;
3498     // FMA231 C, a, B; ==> FMA213 B, a, C;
3499     { Form132Index, Form231Index, Form213Index },
3500     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3501     // FMA132 a, C, B; ==> FMA213 a, B, C;
3502     // FMA213 b, A, C; ==> FMA132 b, C, A;
3503     // FMA231 c, A, B; ==> FMA231 c, B, A;
3504     { Form213Index, Form132Index, Form231Index }
3505   };
3506 
3507   // Everything is ready, just adjust the FMA opcode and return it.
3508   FormIndex = FormMapping[Case][FormIndex];
3509   return OpcodeGroups[GroupIndex][FormIndex];
3510 }
3511 
3512 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI,
3513                                          unsigned &SrcOpIdx1,
3514                                          unsigned &SrcOpIdx2) const {
3515   switch (MI->getOpcode()) {
3516     case X86::CMPPDrri:
3517     case X86::CMPPSrri:
3518     case X86::VCMPPDrri:
3519     case X86::VCMPPSrri:
3520     case X86::VCMPPDYrri:
3521     case X86::VCMPPSYrri: {
3522       // Float comparison can be safely commuted for
3523       // Ordered/Unordered/Equal/NotEqual tests
3524       unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3525       switch (Imm) {
3526         case 0x00: // EQUAL
3527         case 0x03: // UNORDERED
3528         case 0x04: // NOT EQUAL
3529         case 0x07: // ORDERED
3530           // The indices of the commutable operands are 1 and 2.
3531           // Assign them to the returned operand indices here.
3532           return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
3533       }
3534       return false;
3535     }
3536     default:
3537       if (isFMA3(MI->getOpcode()))
3538         return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3539       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3540   }
3541   return false;
3542 }
3543 
3544 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
3545   switch (BrOpc) {
3546   default: return X86::COND_INVALID;
3547   case X86::JE_1:  return X86::COND_E;
3548   case X86::JNE_1: return X86::COND_NE;
3549   case X86::JL_1:  return X86::COND_L;
3550   case X86::JLE_1: return X86::COND_LE;
3551   case X86::JG_1:  return X86::COND_G;
3552   case X86::JGE_1: return X86::COND_GE;
3553   case X86::JB_1:  return X86::COND_B;
3554   case X86::JBE_1: return X86::COND_BE;
3555   case X86::JA_1:  return X86::COND_A;
3556   case X86::JAE_1: return X86::COND_AE;
3557   case X86::JS_1:  return X86::COND_S;
3558   case X86::JNS_1: return X86::COND_NS;
3559   case X86::JP_1:  return X86::COND_P;
3560   case X86::JNP_1: return X86::COND_NP;
3561   case X86::JO_1:  return X86::COND_O;
3562   case X86::JNO_1: return X86::COND_NO;
3563   }
3564 }
3565 
3566 /// Return condition code of a SET opcode.
3567 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3568   switch (Opc) {
3569   default: return X86::COND_INVALID;
3570   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
3571   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3572   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
3573   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3574   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
3575   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
3576   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3577   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
3578   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3579   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3580   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3581   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3582   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3583   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
3584   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
3585   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
3586   }
3587 }
3588 
3589 /// Return condition code of a CMov opcode.
3590 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
3591   switch (Opc) {
3592   default: return X86::COND_INVALID;
3593   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
3594   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
3595     return X86::COND_A;
3596   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3597   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3598     return X86::COND_AE;
3599   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
3600   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
3601     return X86::COND_B;
3602   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3603   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3604     return X86::COND_BE;
3605   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
3606   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
3607     return X86::COND_E;
3608   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
3609   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
3610     return X86::COND_G;
3611   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3612   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3613     return X86::COND_GE;
3614   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
3615   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
3616     return X86::COND_L;
3617   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3618   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3619     return X86::COND_LE;
3620   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3621   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3622     return X86::COND_NE;
3623   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3624   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3625     return X86::COND_NO;
3626   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3627   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3628     return X86::COND_NP;
3629   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3630   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3631     return X86::COND_NS;
3632   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
3633   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
3634     return X86::COND_O;
3635   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
3636   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
3637     return X86::COND_P;
3638   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
3639   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
3640     return X86::COND_S;
3641   }
3642 }
3643 
3644 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3645   switch (CC) {
3646   default: llvm_unreachable("Illegal condition code!");
3647   case X86::COND_E:  return X86::JE_1;
3648   case X86::COND_NE: return X86::JNE_1;
3649   case X86::COND_L:  return X86::JL_1;
3650   case X86::COND_LE: return X86::JLE_1;
3651   case X86::COND_G:  return X86::JG_1;
3652   case X86::COND_GE: return X86::JGE_1;
3653   case X86::COND_B:  return X86::JB_1;
3654   case X86::COND_BE: return X86::JBE_1;
3655   case X86::COND_A:  return X86::JA_1;
3656   case X86::COND_AE: return X86::JAE_1;
3657   case X86::COND_S:  return X86::JS_1;
3658   case X86::COND_NS: return X86::JNS_1;
3659   case X86::COND_P:  return X86::JP_1;
3660   case X86::COND_NP: return X86::JNP_1;
3661   case X86::COND_O:  return X86::JO_1;
3662   case X86::COND_NO: return X86::JNO_1;
3663   }
3664 }
3665 
3666 /// Return the inverse of the specified condition,
3667 /// e.g. turning COND_E to COND_NE.
3668 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3669   switch (CC) {
3670   default: llvm_unreachable("Illegal condition code!");
3671   case X86::COND_E:  return X86::COND_NE;
3672   case X86::COND_NE: return X86::COND_E;
3673   case X86::COND_L:  return X86::COND_GE;
3674   case X86::COND_LE: return X86::COND_G;
3675   case X86::COND_G:  return X86::COND_LE;
3676   case X86::COND_GE: return X86::COND_L;
3677   case X86::COND_B:  return X86::COND_AE;
3678   case X86::COND_BE: return X86::COND_A;
3679   case X86::COND_A:  return X86::COND_BE;
3680   case X86::COND_AE: return X86::COND_B;
3681   case X86::COND_S:  return X86::COND_NS;
3682   case X86::COND_NS: return X86::COND_S;
3683   case X86::COND_P:  return X86::COND_NP;
3684   case X86::COND_NP: return X86::COND_P;
3685   case X86::COND_O:  return X86::COND_NO;
3686   case X86::COND_NO: return X86::COND_O;
3687   }
3688 }
3689 
3690 /// Assuming the flags are set by MI(a,b), return the condition code if we
3691 /// modify the instructions such that flags are set by MI(b,a).
3692 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3693   switch (CC) {
3694   default: return X86::COND_INVALID;
3695   case X86::COND_E:  return X86::COND_E;
3696   case X86::COND_NE: return X86::COND_NE;
3697   case X86::COND_L:  return X86::COND_G;
3698   case X86::COND_LE: return X86::COND_GE;
3699   case X86::COND_G:  return X86::COND_L;
3700   case X86::COND_GE: return X86::COND_LE;
3701   case X86::COND_B:  return X86::COND_A;
3702   case X86::COND_BE: return X86::COND_AE;
3703   case X86::COND_A:  return X86::COND_B;
3704   case X86::COND_AE: return X86::COND_BE;
3705   }
3706 }
3707 
3708 /// Return a set opcode for the given condition and
3709 /// whether it has memory operand.
3710 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
3711   static const uint16_t Opc[16][2] = {
3712     { X86::SETAr,  X86::SETAm  },
3713     { X86::SETAEr, X86::SETAEm },
3714     { X86::SETBr,  X86::SETBm  },
3715     { X86::SETBEr, X86::SETBEm },
3716     { X86::SETEr,  X86::SETEm  },
3717     { X86::SETGr,  X86::SETGm  },
3718     { X86::SETGEr, X86::SETGEm },
3719     { X86::SETLr,  X86::SETLm  },
3720     { X86::SETLEr, X86::SETLEm },
3721     { X86::SETNEr, X86::SETNEm },
3722     { X86::SETNOr, X86::SETNOm },
3723     { X86::SETNPr, X86::SETNPm },
3724     { X86::SETNSr, X86::SETNSm },
3725     { X86::SETOr,  X86::SETOm  },
3726     { X86::SETPr,  X86::SETPm  },
3727     { X86::SETSr,  X86::SETSm  }
3728   };
3729 
3730   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
3731   return Opc[CC][HasMemoryOperand ? 1 : 0];
3732 }
3733 
3734 /// Return a cmov opcode for the given condition,
3735 /// register size in bytes, and operand type.
3736 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3737                               bool HasMemoryOperand) {
3738   static const uint16_t Opc[32][3] = {
3739     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
3740     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3741     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
3742     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3743     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
3744     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
3745     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3746     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
3747     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3748     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3749     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3750     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3751     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3752     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
3753     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
3754     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
3755     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
3756     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3757     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
3758     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3759     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
3760     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
3761     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3762     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
3763     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3764     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3765     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3766     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3767     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3768     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
3769     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
3770     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
3771   };
3772 
3773   assert(CC < 16 && "Can only handle standard cond codes");
3774   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
3775   switch(RegBytes) {
3776   default: llvm_unreachable("Illegal register size!");
3777   case 2: return Opc[Idx][0];
3778   case 4: return Opc[Idx][1];
3779   case 8: return Opc[Idx][2];
3780   }
3781 }
3782 
3783 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
3784   if (!MI->isTerminator()) return false;
3785 
3786   // Conditional branch is a special case.
3787   if (MI->isBranch() && !MI->isBarrier())
3788     return true;
3789   if (!MI->isPredicable())
3790     return true;
3791   return !isPredicated(MI);
3792 }
3793 
3794 bool X86InstrInfo::AnalyzeBranchImpl(
3795     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3796     SmallVectorImpl<MachineOperand> &Cond,
3797     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3798 
3799   // Start from the bottom of the block and work up, examining the
3800   // terminator instructions.
3801   MachineBasicBlock::iterator I = MBB.end();
3802   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3803   while (I != MBB.begin()) {
3804     --I;
3805     if (I->isDebugValue())
3806       continue;
3807 
3808     // Working from the bottom, when we see a non-terminator instruction, we're
3809     // done.
3810     if (!isUnpredicatedTerminator(I))
3811       break;
3812 
3813     // A terminator that isn't a branch can't easily be handled by this
3814     // analysis.
3815     if (!I->isBranch())
3816       return true;
3817 
3818     // Handle unconditional branches.
3819     if (I->getOpcode() == X86::JMP_1) {
3820       UnCondBrIter = I;
3821 
3822       if (!AllowModify) {
3823         TBB = I->getOperand(0).getMBB();
3824         continue;
3825       }
3826 
3827       // If the block has any instructions after a JMP, delete them.
3828       while (std::next(I) != MBB.end())
3829         std::next(I)->eraseFromParent();
3830 
3831       Cond.clear();
3832       FBB = nullptr;
3833 
3834       // Delete the JMP if it's equivalent to a fall-through.
3835       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3836         TBB = nullptr;
3837         I->eraseFromParent();
3838         I = MBB.end();
3839         UnCondBrIter = MBB.end();
3840         continue;
3841       }
3842 
3843       // TBB is used to indicate the unconditional destination.
3844       TBB = I->getOperand(0).getMBB();
3845       continue;
3846     }
3847 
3848     // Handle conditional branches.
3849     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
3850     if (BranchCode == X86::COND_INVALID)
3851       return true;  // Can't handle indirect branch.
3852 
3853     // Working from the bottom, handle the first conditional branch.
3854     if (Cond.empty()) {
3855       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3856       if (AllowModify && UnCondBrIter != MBB.end() &&
3857           MBB.isLayoutSuccessor(TargetBB)) {
3858         // If we can modify the code and it ends in something like:
3859         //
3860         //     jCC L1
3861         //     jmp L2
3862         //   L1:
3863         //     ...
3864         //   L2:
3865         //
3866         // Then we can change this to:
3867         //
3868         //     jnCC L2
3869         //   L1:
3870         //     ...
3871         //   L2:
3872         //
3873         // Which is a bit more efficient.
3874         // We conditionally jump to the fall-through block.
3875         BranchCode = GetOppositeBranchCondition(BranchCode);
3876         unsigned JNCC = GetCondBranchFromCond(BranchCode);
3877         MachineBasicBlock::iterator OldInst = I;
3878 
3879         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3880           .addMBB(UnCondBrIter->getOperand(0).getMBB());
3881         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3882           .addMBB(TargetBB);
3883 
3884         OldInst->eraseFromParent();
3885         UnCondBrIter->eraseFromParent();
3886 
3887         // Restart the analysis.
3888         UnCondBrIter = MBB.end();
3889         I = MBB.end();
3890         continue;
3891       }
3892 
3893       FBB = TBB;
3894       TBB = I->getOperand(0).getMBB();
3895       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3896       CondBranches.push_back(I);
3897       continue;
3898     }
3899 
3900     // Handle subsequent conditional branches. Only handle the case where all
3901     // conditional branches branch to the same destination and their condition
3902     // opcodes fit one of the special multi-branch idioms.
3903     assert(Cond.size() == 1);
3904     assert(TBB);
3905 
3906     // Only handle the case where all conditional branches branch to the same
3907     // destination.
3908     if (TBB != I->getOperand(0).getMBB())
3909       return true;
3910 
3911     // If the conditions are the same, we can leave them alone.
3912     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3913     if (OldBranchCode == BranchCode)
3914       continue;
3915 
3916     // If they differ, see if they fit one of the known patterns. Theoretically,
3917     // we could handle more patterns here, but we shouldn't expect to see them
3918     // if instruction selection has done a reasonable job.
3919     if ((OldBranchCode == X86::COND_NP &&
3920          BranchCode == X86::COND_E) ||
3921         (OldBranchCode == X86::COND_E &&
3922          BranchCode == X86::COND_NP))
3923       BranchCode = X86::COND_NP_OR_E;
3924     else if ((OldBranchCode == X86::COND_P &&
3925               BranchCode == X86::COND_NE) ||
3926              (OldBranchCode == X86::COND_NE &&
3927               BranchCode == X86::COND_P))
3928       BranchCode = X86::COND_NE_OR_P;
3929     else
3930       return true;
3931 
3932     // Update the MachineOperand.
3933     Cond[0].setImm(BranchCode);
3934     CondBranches.push_back(I);
3935   }
3936 
3937   return false;
3938 }
3939 
3940 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
3941                                  MachineBasicBlock *&TBB,
3942                                  MachineBasicBlock *&FBB,
3943                                  SmallVectorImpl<MachineOperand> &Cond,
3944                                  bool AllowModify) const {
3945   SmallVector<MachineInstr *, 4> CondBranches;
3946   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3947 }
3948 
3949 bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB,
3950                                           MachineBranchPredicate &MBP,
3951                                           bool AllowModify) const {
3952   using namespace std::placeholders;
3953 
3954   SmallVector<MachineOperand, 4> Cond;
3955   SmallVector<MachineInstr *, 4> CondBranches;
3956   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3957                         AllowModify))
3958     return true;
3959 
3960   if (Cond.size() != 1)
3961     return true;
3962 
3963   assert(MBP.TrueDest && "expected!");
3964 
3965   if (!MBP.FalseDest)
3966     MBP.FalseDest = MBB.getNextNode();
3967 
3968   const TargetRegisterInfo *TRI = &getRegisterInfo();
3969 
3970   MachineInstr *ConditionDef = nullptr;
3971   bool SingleUseCondition = true;
3972 
3973   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
3974     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
3975       ConditionDef = &*I;
3976       break;
3977     }
3978 
3979     if (I->readsRegister(X86::EFLAGS, TRI))
3980       SingleUseCondition = false;
3981   }
3982 
3983   if (!ConditionDef)
3984     return true;
3985 
3986   if (SingleUseCondition) {
3987     for (auto *Succ : MBB.successors())
3988       if (Succ->isLiveIn(X86::EFLAGS))
3989         SingleUseCondition = false;
3990   }
3991 
3992   MBP.ConditionDef = ConditionDef;
3993   MBP.SingleUseCondition = SingleUseCondition;
3994 
3995   // Currently we only recognize the simple pattern:
3996   //
3997   //   test %reg, %reg
3998   //   je %label
3999   //
4000   const unsigned TestOpcode =
4001       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4002 
4003   if (ConditionDef->getOpcode() == TestOpcode &&
4004       ConditionDef->getNumOperands() == 3 &&
4005       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4006       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4007     MBP.LHS = ConditionDef->getOperand(0);
4008     MBP.RHS = MachineOperand::CreateImm(0);
4009     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4010                         ? MachineBranchPredicate::PRED_NE
4011                         : MachineBranchPredicate::PRED_EQ;
4012     return false;
4013   }
4014 
4015   return true;
4016 }
4017 
4018 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
4019   MachineBasicBlock::iterator I = MBB.end();
4020   unsigned Count = 0;
4021 
4022   while (I != MBB.begin()) {
4023     --I;
4024     if (I->isDebugValue())
4025       continue;
4026     if (I->getOpcode() != X86::JMP_1 &&
4027         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
4028       break;
4029     // Remove the branch.
4030     I->eraseFromParent();
4031     I = MBB.end();
4032     ++Count;
4033   }
4034 
4035   return Count;
4036 }
4037 
4038 unsigned
4039 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
4040                            MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
4041                            DebugLoc DL) const {
4042   // Shouldn't be a fall through.
4043   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
4044   assert((Cond.size() == 1 || Cond.size() == 0) &&
4045          "X86 branch conditions have one component!");
4046 
4047   if (Cond.empty()) {
4048     // Unconditional branch?
4049     assert(!FBB && "Unconditional branch with multiple successors!");
4050     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
4051     return 1;
4052   }
4053 
4054   // Conditional branch.
4055   unsigned Count = 0;
4056   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4057   switch (CC) {
4058   case X86::COND_NP_OR_E:
4059     // Synthesize NP_OR_E with two branches.
4060     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4061     ++Count;
4062     BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
4063     ++Count;
4064     break;
4065   case X86::COND_NE_OR_P:
4066     // Synthesize NE_OR_P with two branches.
4067     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
4068     ++Count;
4069     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
4070     ++Count;
4071     break;
4072   default: {
4073     unsigned Opc = GetCondBranchFromCond(CC);
4074     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
4075     ++Count;
4076   }
4077   }
4078   if (FBB) {
4079     // Two-way Conditional branch. Insert the second branch.
4080     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
4081     ++Count;
4082   }
4083   return Count;
4084 }
4085 
4086 bool X86InstrInfo::
4087 canInsertSelect(const MachineBasicBlock &MBB,
4088                 ArrayRef<MachineOperand> Cond,
4089                 unsigned TrueReg, unsigned FalseReg,
4090                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4091   // Not all subtargets have cmov instructions.
4092   if (!Subtarget.hasCMov())
4093     return false;
4094   if (Cond.size() != 1)
4095     return false;
4096   // We cannot do the composite conditions, at least not in SSA form.
4097   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4098     return false;
4099 
4100   // Check register classes.
4101   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4102   const TargetRegisterClass *RC =
4103     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4104   if (!RC)
4105     return false;
4106 
4107   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4108   if (X86::GR16RegClass.hasSubClassEq(RC) ||
4109       X86::GR32RegClass.hasSubClassEq(RC) ||
4110       X86::GR64RegClass.hasSubClassEq(RC)) {
4111     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4112     // Bridge. Probably Ivy Bridge as well.
4113     CondCycles = 2;
4114     TrueCycles = 2;
4115     FalseCycles = 2;
4116     return true;
4117   }
4118 
4119   // Can't do vectors.
4120   return false;
4121 }
4122 
4123 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4124                                 MachineBasicBlock::iterator I, DebugLoc DL,
4125                                 unsigned DstReg, ArrayRef<MachineOperand> Cond,
4126                                 unsigned TrueReg, unsigned FalseReg) const {
4127    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4128    assert(Cond.size() == 1 && "Invalid Cond array");
4129    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4130                                   MRI.getRegClass(DstReg)->getSize(),
4131                                   false/*HasMemoryOperand*/);
4132    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
4133 }
4134 
4135 /// Test if the given register is a physical h register.
4136 static bool isHReg(unsigned Reg) {
4137   return X86::GR8_ABCD_HRegClass.contains(Reg);
4138 }
4139 
4140 // Try and copy between VR128/VR64 and GR64 registers.
4141 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
4142                                         const X86Subtarget &Subtarget) {
4143 
4144   // SrcReg(VR128) -> DestReg(GR64)
4145   // SrcReg(VR64)  -> DestReg(GR64)
4146   // SrcReg(GR64)  -> DestReg(VR128)
4147   // SrcReg(GR64)  -> DestReg(VR64)
4148 
4149   bool HasAVX = Subtarget.hasAVX();
4150   bool HasAVX512 = Subtarget.hasAVX512();
4151   if (X86::GR64RegClass.contains(DestReg)) {
4152     if (X86::VR128XRegClass.contains(SrcReg))
4153       // Copy from a VR128 register to a GR64 register.
4154       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
4155                                                X86::MOVPQIto64rr);
4156     if (X86::VR64RegClass.contains(SrcReg))
4157       // Copy from a VR64 register to a GR64 register.
4158       return X86::MMX_MOVD64from64rr;
4159   } else if (X86::GR64RegClass.contains(SrcReg)) {
4160     // Copy from a GR64 register to a VR128 register.
4161     if (X86::VR128XRegClass.contains(DestReg))
4162       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
4163                                                X86::MOV64toPQIrr);
4164     // Copy from a GR64 register to a VR64 register.
4165     if (X86::VR64RegClass.contains(DestReg))
4166       return X86::MMX_MOVD64to64rr;
4167   }
4168 
4169   // SrcReg(FR32) -> DestReg(GR32)
4170   // SrcReg(GR32) -> DestReg(FR32)
4171 
4172   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
4173     // Copy from a FR32 register to a GR32 register.
4174     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
4175 
4176   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4177     // Copy from a GR32 register to a FR32 register.
4178     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
4179   return 0;
4180 }
4181 
4182 inline static bool MaskRegClassContains(unsigned Reg) {
4183   return X86::VK8RegClass.contains(Reg) ||
4184          X86::VK16RegClass.contains(Reg) ||
4185          X86::VK32RegClass.contains(Reg) ||
4186          X86::VK64RegClass.contains(Reg) ||
4187          X86::VK1RegClass.contains(Reg);
4188 }
4189 static
4190 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
4191   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
4192       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
4193       X86::VR512RegClass.contains(DestReg, SrcReg)) {
4194      DestReg = get512BitSuperRegister(DestReg);
4195      SrcReg = get512BitSuperRegister(SrcReg);
4196      return X86::VMOVAPSZrr;
4197   }
4198   if (MaskRegClassContains(DestReg) &&
4199       MaskRegClassContains(SrcReg))
4200     return X86::KMOVWkk;
4201   if (MaskRegClassContains(DestReg) &&
4202       (X86::GR32RegClass.contains(SrcReg) ||
4203        X86::GR16RegClass.contains(SrcReg) ||
4204        X86::GR8RegClass.contains(SrcReg))) {
4205     SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
4206     return X86::KMOVWkr;
4207   }
4208   if ((X86::GR32RegClass.contains(DestReg) ||
4209        X86::GR16RegClass.contains(DestReg) ||
4210        X86::GR8RegClass.contains(DestReg)) &&
4211        MaskRegClassContains(SrcReg)) {
4212     DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
4213     return X86::KMOVWrk;
4214   }
4215   return 0;
4216 }
4217 
4218 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4219                                MachineBasicBlock::iterator MI, DebugLoc DL,
4220                                unsigned DestReg, unsigned SrcReg,
4221                                bool KillSrc) const {
4222   // First deal with the normal symmetric copies.
4223   bool HasAVX = Subtarget.hasAVX();
4224   bool HasAVX512 = Subtarget.hasAVX512();
4225   unsigned Opc = 0;
4226   if (X86::GR64RegClass.contains(DestReg, SrcReg))
4227     Opc = X86::MOV64rr;
4228   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4229     Opc = X86::MOV32rr;
4230   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4231     Opc = X86::MOV16rr;
4232   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4233     // Copying to or from a physical H register on x86-64 requires a NOREX
4234     // move.  Otherwise use a normal move.
4235     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
4236         Subtarget.is64Bit()) {
4237       Opc = X86::MOV8rr_NOREX;
4238       // Both operands must be encodable without an REX prefix.
4239       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4240              "8-bit H register can not be copied outside GR8_NOREX");
4241     } else
4242       Opc = X86::MOV8rr;
4243   }
4244   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4245     Opc = X86::MMX_MOVQ64rr;
4246   else if (HasAVX512)
4247     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
4248   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
4249     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4250   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4251     Opc = X86::VMOVAPSYrr;
4252   if (!Opc)
4253     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4254 
4255   if (Opc) {
4256     BuildMI(MBB, MI, DL, get(Opc), DestReg)
4257       .addReg(SrcReg, getKillRegState(KillSrc));
4258     return;
4259   }
4260 
4261   bool FromEFLAGS = SrcReg == X86::EFLAGS;
4262   bool ToEFLAGS = DestReg == X86::EFLAGS;
4263   int Reg = FromEFLAGS ? DestReg : SrcReg;
4264   bool is32 = X86::GR32RegClass.contains(Reg);
4265   bool is64 = X86::GR64RegClass.contains(Reg);
4266   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
4267     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4268     // inefficient. Instead:
4269     //   - Save the overflow flag OF into AL using SETO, and restore it using a
4270     //     signed 8-bit addition of AL and INT8_MAX.
4271     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4272     //     using LAHF/SAHF.
4273     //   - When RAX/EAX is live and isn't the destination register, make sure it
4274     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4275     //     the flags.
4276     // This approach is ~2.25x faster than using PUSHF/POPF.
4277     //
4278     // This is still somewhat inefficient because we don't know which flags are
4279     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4280     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4281     //
4282     // PUSHF/POPF is also potentially incorrect because it affects other flags
4283     // such as TF/IF/DF, which LLVM doesn't model.
4284     //
4285     // Notice that we have to adjust the stack if we don't want to clobber the
4286     // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
4287 
4288     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4289     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4290     int Pop = is64 ? X86::POP64r : X86::POP32r;
4291     int AX = is64 ? X86::RAX : X86::EAX;
4292 
4293     bool AXDead = (Reg == AX) ||
4294                   (MachineBasicBlock::LQR_Dead ==
4295                    MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI));
4296 
4297     if (!AXDead)
4298       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
4299     if (FromEFLAGS) {
4300       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4301       BuildMI(MBB, MI, DL, get(X86::LAHF));
4302       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
4303     }
4304     if (ToEFLAGS) {
4305       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4306       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4307           .addReg(X86::AL)
4308           .addImm(INT8_MAX);
4309       BuildMI(MBB, MI, DL, get(X86::SAHF));
4310     }
4311     if (!AXDead)
4312       BuildMI(MBB, MI, DL, get(Pop), AX);
4313     return;
4314   }
4315 
4316   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4317                << " to " << RI.getName(DestReg) << '\n');
4318   llvm_unreachable("Cannot emit physreg copy instruction");
4319 }
4320 
4321 static unsigned getLoadStoreRegOpcode(unsigned Reg,
4322                                       const TargetRegisterClass *RC,
4323                                       bool isStackAligned,
4324                                       const X86Subtarget &STI,
4325                                       bool load) {
4326   if (STI.hasAVX512()) {
4327     if (X86::VK8RegClass.hasSubClassEq(RC)  ||
4328       X86::VK16RegClass.hasSubClassEq(RC))
4329       return load ? X86::KMOVWkm : X86::KMOVWmk;
4330     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
4331       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
4332     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
4333       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
4334     if (X86::VR512RegClass.hasSubClassEq(RC))
4335       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4336   }
4337 
4338   bool HasAVX = STI.hasAVX();
4339   switch (RC->getSize()) {
4340   default:
4341     llvm_unreachable("Unknown spill size");
4342   case 1:
4343     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
4344     if (STI.is64Bit())
4345       // Copying to or from a physical H register on x86-64 requires a NOREX
4346       // move.  Otherwise use a normal move.
4347       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4348         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4349     return load ? X86::MOV8rm : X86::MOV8mr;
4350   case 2:
4351     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4352     return load ? X86::MOV16rm : X86::MOV16mr;
4353   case 4:
4354     if (X86::GR32RegClass.hasSubClassEq(RC))
4355       return load ? X86::MOV32rm : X86::MOV32mr;
4356     if (X86::FR32RegClass.hasSubClassEq(RC))
4357       return load ?
4358         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4359         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
4360     if (X86::RFP32RegClass.hasSubClassEq(RC))
4361       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4362     llvm_unreachable("Unknown 4-byte regclass");
4363   case 8:
4364     if (X86::GR64RegClass.hasSubClassEq(RC))
4365       return load ? X86::MOV64rm : X86::MOV64mr;
4366     if (X86::FR64RegClass.hasSubClassEq(RC))
4367       return load ?
4368         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4369         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
4370     if (X86::VR64RegClass.hasSubClassEq(RC))
4371       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4372     if (X86::RFP64RegClass.hasSubClassEq(RC))
4373       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4374     llvm_unreachable("Unknown 8-byte regclass");
4375   case 10:
4376     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
4377     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
4378   case 16: {
4379     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4380             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
4381     // If stack is realigned we can use aligned stores.
4382     if (isStackAligned)
4383       return load ?
4384         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
4385         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4386     else
4387       return load ?
4388         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
4389         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4390   }
4391   case 32:
4392     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4393             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
4394     // If stack is realigned we can use aligned stores.
4395     if (isStackAligned)
4396       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4397     else
4398       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
4399   case 64:
4400     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4401     if (isStackAligned)
4402       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4403     else
4404       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4405   }
4406 }
4407 
4408 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
4409                                          unsigned &Offset,
4410                                          const TargetRegisterInfo *TRI) const {
4411   const MCInstrDesc &Desc = MemOp->getDesc();
4412   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags, MemOp->getOpcode());
4413   if (MemRefBegin < 0)
4414     return false;
4415 
4416   MemRefBegin += X86II::getOperandBias(Desc);
4417 
4418   BaseReg = MemOp->getOperand(MemRefBegin + X86::AddrBaseReg).getReg();
4419   if (MemOp->getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4420     return false;
4421 
4422   if (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
4423       X86::NoRegister)
4424     return false;
4425 
4426   const MachineOperand &DispMO = MemOp->getOperand(MemRefBegin + X86::AddrDisp);
4427 
4428   // Displacement can be symbolic
4429   if (!DispMO.isImm())
4430     return false;
4431 
4432   Offset = DispMO.getImm();
4433 
4434   return (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4435           X86::NoRegister);
4436 }
4437 
4438 static unsigned getStoreRegOpcode(unsigned SrcReg,
4439                                   const TargetRegisterClass *RC,
4440                                   bool isStackAligned,
4441                                   const X86Subtarget &STI) {
4442   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
4443 }
4444 
4445 
4446 static unsigned getLoadRegOpcode(unsigned DestReg,
4447                                  const TargetRegisterClass *RC,
4448                                  bool isStackAligned,
4449                                  const X86Subtarget &STI) {
4450   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
4451 }
4452 
4453 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4454                                        MachineBasicBlock::iterator MI,
4455                                        unsigned SrcReg, bool isKill, int FrameIdx,
4456                                        const TargetRegisterClass *RC,
4457                                        const TargetRegisterInfo *TRI) const {
4458   const MachineFunction &MF = *MBB.getParent();
4459   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4460          "Stack slot too small for store");
4461   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4462   bool isAligned =
4463       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4464       RI.canRealignStack(MF);
4465   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4466   DebugLoc DL = MBB.findDebugLoc(MI);
4467   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
4468     .addReg(SrcReg, getKillRegState(isKill));
4469 }
4470 
4471 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4472                                   bool isKill,
4473                                   SmallVectorImpl<MachineOperand> &Addr,
4474                                   const TargetRegisterClass *RC,
4475                                   MachineInstr::mmo_iterator MMOBegin,
4476                                   MachineInstr::mmo_iterator MMOEnd,
4477                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
4478   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4479   bool isAligned = MMOBegin != MMOEnd &&
4480                    (*MMOBegin)->getAlignment() >= Alignment;
4481   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4482   DebugLoc DL;
4483   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
4484   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4485     MIB.addOperand(Addr[i]);
4486   MIB.addReg(SrcReg, getKillRegState(isKill));
4487   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4488   NewMIs.push_back(MIB);
4489 }
4490 
4491 
4492 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4493                                         MachineBasicBlock::iterator MI,
4494                                         unsigned DestReg, int FrameIdx,
4495                                         const TargetRegisterClass *RC,
4496                                         const TargetRegisterInfo *TRI) const {
4497   const MachineFunction &MF = *MBB.getParent();
4498   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4499   bool isAligned =
4500       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4501       RI.canRealignStack(MF);
4502   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4503   DebugLoc DL = MBB.findDebugLoc(MI);
4504   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
4505 }
4506 
4507 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
4508                                  SmallVectorImpl<MachineOperand> &Addr,
4509                                  const TargetRegisterClass *RC,
4510                                  MachineInstr::mmo_iterator MMOBegin,
4511                                  MachineInstr::mmo_iterator MMOEnd,
4512                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
4513   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4514   bool isAligned = MMOBegin != MMOEnd &&
4515                    (*MMOBegin)->getAlignment() >= Alignment;
4516   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4517   DebugLoc DL;
4518   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
4519   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4520     MIB.addOperand(Addr[i]);
4521   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4522   NewMIs.push_back(MIB);
4523 }
4524 
4525 bool X86InstrInfo::
4526 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
4527                int &CmpMask, int &CmpValue) const {
4528   switch (MI->getOpcode()) {
4529   default: break;
4530   case X86::CMP64ri32:
4531   case X86::CMP64ri8:
4532   case X86::CMP32ri:
4533   case X86::CMP32ri8:
4534   case X86::CMP16ri:
4535   case X86::CMP16ri8:
4536   case X86::CMP8ri:
4537     SrcReg = MI->getOperand(0).getReg();
4538     SrcReg2 = 0;
4539     CmpMask = ~0;
4540     CmpValue = MI->getOperand(1).getImm();
4541     return true;
4542   // A SUB can be used to perform comparison.
4543   case X86::SUB64rm:
4544   case X86::SUB32rm:
4545   case X86::SUB16rm:
4546   case X86::SUB8rm:
4547     SrcReg = MI->getOperand(1).getReg();
4548     SrcReg2 = 0;
4549     CmpMask = ~0;
4550     CmpValue = 0;
4551     return true;
4552   case X86::SUB64rr:
4553   case X86::SUB32rr:
4554   case X86::SUB16rr:
4555   case X86::SUB8rr:
4556     SrcReg = MI->getOperand(1).getReg();
4557     SrcReg2 = MI->getOperand(2).getReg();
4558     CmpMask = ~0;
4559     CmpValue = 0;
4560     return true;
4561   case X86::SUB64ri32:
4562   case X86::SUB64ri8:
4563   case X86::SUB32ri:
4564   case X86::SUB32ri8:
4565   case X86::SUB16ri:
4566   case X86::SUB16ri8:
4567   case X86::SUB8ri:
4568     SrcReg = MI->getOperand(1).getReg();
4569     SrcReg2 = 0;
4570     CmpMask = ~0;
4571     CmpValue = MI->getOperand(2).getImm();
4572     return true;
4573   case X86::CMP64rr:
4574   case X86::CMP32rr:
4575   case X86::CMP16rr:
4576   case X86::CMP8rr:
4577     SrcReg = MI->getOperand(0).getReg();
4578     SrcReg2 = MI->getOperand(1).getReg();
4579     CmpMask = ~0;
4580     CmpValue = 0;
4581     return true;
4582   case X86::TEST8rr:
4583   case X86::TEST16rr:
4584   case X86::TEST32rr:
4585   case X86::TEST64rr:
4586     SrcReg = MI->getOperand(0).getReg();
4587     if (MI->getOperand(1).getReg() != SrcReg) return false;
4588     // Compare against zero.
4589     SrcReg2 = 0;
4590     CmpMask = ~0;
4591     CmpValue = 0;
4592     return true;
4593   }
4594   return false;
4595 }
4596 
4597 /// Check whether the first instruction, whose only
4598 /// purpose is to update flags, can be made redundant.
4599 /// CMPrr can be made redundant by SUBrr if the operands are the same.
4600 /// This function can be extended later on.
4601 /// SrcReg, SrcRegs: register operands for FlagI.
4602 /// ImmValue: immediate for FlagI if it takes an immediate.
4603 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4604                                         unsigned SrcReg2, int ImmValue,
4605                                         MachineInstr *OI) {
4606   if (((FlagI->getOpcode() == X86::CMP64rr &&
4607         OI->getOpcode() == X86::SUB64rr) ||
4608        (FlagI->getOpcode() == X86::CMP32rr &&
4609         OI->getOpcode() == X86::SUB32rr)||
4610        (FlagI->getOpcode() == X86::CMP16rr &&
4611         OI->getOpcode() == X86::SUB16rr)||
4612        (FlagI->getOpcode() == X86::CMP8rr &&
4613         OI->getOpcode() == X86::SUB8rr)) &&
4614       ((OI->getOperand(1).getReg() == SrcReg &&
4615         OI->getOperand(2).getReg() == SrcReg2) ||
4616        (OI->getOperand(1).getReg() == SrcReg2 &&
4617         OI->getOperand(2).getReg() == SrcReg)))
4618     return true;
4619 
4620   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4621         OI->getOpcode() == X86::SUB64ri32) ||
4622        (FlagI->getOpcode() == X86::CMP64ri8 &&
4623         OI->getOpcode() == X86::SUB64ri8) ||
4624        (FlagI->getOpcode() == X86::CMP32ri &&
4625         OI->getOpcode() == X86::SUB32ri) ||
4626        (FlagI->getOpcode() == X86::CMP32ri8 &&
4627         OI->getOpcode() == X86::SUB32ri8) ||
4628        (FlagI->getOpcode() == X86::CMP16ri &&
4629         OI->getOpcode() == X86::SUB16ri) ||
4630        (FlagI->getOpcode() == X86::CMP16ri8 &&
4631         OI->getOpcode() == X86::SUB16ri8) ||
4632        (FlagI->getOpcode() == X86::CMP8ri &&
4633         OI->getOpcode() == X86::SUB8ri)) &&
4634       OI->getOperand(1).getReg() == SrcReg &&
4635       OI->getOperand(2).getImm() == ImmValue)
4636     return true;
4637   return false;
4638 }
4639 
4640 /// Check whether the definition can be converted
4641 /// to remove a comparison against zero.
4642 inline static bool isDefConvertible(MachineInstr *MI) {
4643   switch (MI->getOpcode()) {
4644   default: return false;
4645 
4646   // The shift instructions only modify ZF if their shift count is non-zero.
4647   // N.B.: The processor truncates the shift count depending on the encoding.
4648   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
4649   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
4650      return getTruncatedShiftCount(MI, 2) != 0;
4651 
4652   // Some left shift instructions can be turned into LEA instructions but only
4653   // if their flags aren't used. Avoid transforming such instructions.
4654   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
4655     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4656     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4657     return ShAmt != 0;
4658   }
4659 
4660   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4661   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4662      return getTruncatedShiftCount(MI, 3) != 0;
4663 
4664   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4665   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
4666   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
4667   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
4668   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
4669   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
4670   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4671   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
4672   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
4673   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
4674   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
4675   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
4676   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4677   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
4678   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
4679   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
4680   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
4681   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4682   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
4683   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
4684   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
4685   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
4686   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
4687   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
4688   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
4689   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
4690   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
4691   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4692   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
4693   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
4694   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
4695   case X86::ADC32ri:   case X86::ADC32ri8:
4696   case X86::ADC32rr:   case X86::ADC64ri32:
4697   case X86::ADC64ri8:  case X86::ADC64rr:
4698   case X86::SBB32ri:   case X86::SBB32ri8:
4699   case X86::SBB32rr:   case X86::SBB64ri32:
4700   case X86::SBB64ri8:  case X86::SBB64rr:
4701   case X86::ANDN32rr:  case X86::ANDN32rm:
4702   case X86::ANDN64rr:  case X86::ANDN64rm:
4703   case X86::BEXTR32rr: case X86::BEXTR64rr:
4704   case X86::BEXTR32rm: case X86::BEXTR64rm:
4705   case X86::BLSI32rr:  case X86::BLSI32rm:
4706   case X86::BLSI64rr:  case X86::BLSI64rm:
4707   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4708   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4709   case X86::BLSR32rr:  case X86::BLSR32rm:
4710   case X86::BLSR64rr:  case X86::BLSR64rm:
4711   case X86::BZHI32rr:  case X86::BZHI32rm:
4712   case X86::BZHI64rr:  case X86::BZHI64rm:
4713   case X86::LZCNT16rr: case X86::LZCNT16rm:
4714   case X86::LZCNT32rr: case X86::LZCNT32rm:
4715   case X86::LZCNT64rr: case X86::LZCNT64rm:
4716   case X86::POPCNT16rr:case X86::POPCNT16rm:
4717   case X86::POPCNT32rr:case X86::POPCNT32rm:
4718   case X86::POPCNT64rr:case X86::POPCNT64rm:
4719   case X86::TZCNT16rr: case X86::TZCNT16rm:
4720   case X86::TZCNT32rr: case X86::TZCNT32rm:
4721   case X86::TZCNT64rr: case X86::TZCNT64rm:
4722     return true;
4723   }
4724 }
4725 
4726 /// Check whether the use can be converted to remove a comparison against zero.
4727 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
4728   switch (MI->getOpcode()) {
4729   default: return X86::COND_INVALID;
4730   case X86::LZCNT16rr: case X86::LZCNT16rm:
4731   case X86::LZCNT32rr: case X86::LZCNT32rm:
4732   case X86::LZCNT64rr: case X86::LZCNT64rm:
4733     return X86::COND_B;
4734   case X86::POPCNT16rr:case X86::POPCNT16rm:
4735   case X86::POPCNT32rr:case X86::POPCNT32rm:
4736   case X86::POPCNT64rr:case X86::POPCNT64rm:
4737     return X86::COND_E;
4738   case X86::TZCNT16rr: case X86::TZCNT16rm:
4739   case X86::TZCNT32rr: case X86::TZCNT32rm:
4740   case X86::TZCNT64rr: case X86::TZCNT64rm:
4741     return X86::COND_B;
4742   }
4743 }
4744 
4745 /// Check if there exists an earlier instruction that
4746 /// operates on the same source operands and sets flags in the same way as
4747 /// Compare; remove Compare if possible.
4748 bool X86InstrInfo::
4749 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
4750                      int CmpMask, int CmpValue,
4751                      const MachineRegisterInfo *MRI) const {
4752   // Check whether we can replace SUB with CMP.
4753   unsigned NewOpcode = 0;
4754   switch (CmpInstr->getOpcode()) {
4755   default: break;
4756   case X86::SUB64ri32:
4757   case X86::SUB64ri8:
4758   case X86::SUB32ri:
4759   case X86::SUB32ri8:
4760   case X86::SUB16ri:
4761   case X86::SUB16ri8:
4762   case X86::SUB8ri:
4763   case X86::SUB64rm:
4764   case X86::SUB32rm:
4765   case X86::SUB16rm:
4766   case X86::SUB8rm:
4767   case X86::SUB64rr:
4768   case X86::SUB32rr:
4769   case X86::SUB16rr:
4770   case X86::SUB8rr: {
4771     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
4772       return false;
4773     // There is no use of the destination register, we can replace SUB with CMP.
4774     switch (CmpInstr->getOpcode()) {
4775     default: llvm_unreachable("Unreachable!");
4776     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4777     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4778     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4779     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4780     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4781     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4782     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4783     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4784     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4785     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4786     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4787     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4788     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4789     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4790     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4791     }
4792     CmpInstr->setDesc(get(NewOpcode));
4793     CmpInstr->RemoveOperand(0);
4794     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4795     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4796         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4797       return false;
4798   }
4799   }
4800 
4801   // Get the unique definition of SrcReg.
4802   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4803   if (!MI) return false;
4804 
4805   // CmpInstr is the first instruction of the BB.
4806   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4807 
4808   // If we are comparing against zero, check whether we can use MI to update
4809   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4810   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
4811   if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
4812     return false;
4813 
4814   // If we have a use of the source register between the def and our compare
4815   // instruction we can eliminate the compare iff the use sets EFLAGS in the
4816   // right way.
4817   bool ShouldUpdateCC = false;
4818   X86::CondCode NewCC = X86::COND_INVALID;
4819   if (IsCmpZero && !isDefConvertible(MI)) {
4820     // Scan forward from the use until we hit the use we're looking for or the
4821     // compare instruction.
4822     for (MachineBasicBlock::iterator J = MI;; ++J) {
4823       // Do we have a convertible instruction?
4824       NewCC = isUseDefConvertible(J);
4825       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4826           J->getOperand(1).getReg() == SrcReg) {
4827         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4828         ShouldUpdateCC = true; // Update CC later on.
4829         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4830         // with the new def.
4831         MI = Def = J;
4832         break;
4833       }
4834 
4835       if (J == I)
4836         return false;
4837     }
4838   }
4839 
4840   // We are searching for an earlier instruction that can make CmpInstr
4841   // redundant and that instruction will be saved in Sub.
4842   MachineInstr *Sub = nullptr;
4843   const TargetRegisterInfo *TRI = &getRegisterInfo();
4844 
4845   // We iterate backward, starting from the instruction before CmpInstr and
4846   // stop when reaching the definition of a source register or done with the BB.
4847   // RI points to the instruction before CmpInstr.
4848   // If the definition is in this basic block, RE points to the definition;
4849   // otherwise, RE is the rend of the basic block.
4850   MachineBasicBlock::reverse_iterator
4851       RI = MachineBasicBlock::reverse_iterator(I),
4852       RE = CmpInstr->getParent() == MI->getParent() ?
4853            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
4854            CmpInstr->getParent()->rend();
4855   MachineInstr *Movr0Inst = nullptr;
4856   for (; RI != RE; ++RI) {
4857     MachineInstr *Instr = &*RI;
4858     // Check whether CmpInstr can be made redundant by the current instruction.
4859     if (!IsCmpZero &&
4860         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
4861       Sub = Instr;
4862       break;
4863     }
4864 
4865     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
4866         Instr->readsRegister(X86::EFLAGS, TRI)) {
4867       // This instruction modifies or uses EFLAGS.
4868 
4869       // MOV32r0 etc. are implemented with xor which clobbers condition code.
4870       // They are safe to move up, if the definition to EFLAGS is dead and
4871       // earlier instructions do not read or write EFLAGS.
4872       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
4873           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
4874         Movr0Inst = Instr;
4875         continue;
4876       }
4877 
4878       // We can't remove CmpInstr.
4879       return false;
4880     }
4881   }
4882 
4883   // Return false if no candidates exist.
4884   if (!IsCmpZero && !Sub)
4885     return false;
4886 
4887   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
4888                     Sub->getOperand(2).getReg() == SrcReg);
4889 
4890   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4891   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4892   // If we are done with the basic block, we need to check whether EFLAGS is
4893   // live-out.
4894   bool IsSafe = false;
4895   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
4896   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
4897   for (++I; I != E; ++I) {
4898     const MachineInstr &Instr = *I;
4899     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4900     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4901     // We should check the usage if this instruction uses and updates EFLAGS.
4902     if (!UseEFLAGS && ModifyEFLAGS) {
4903       // It is safe to remove CmpInstr if EFLAGS is updated again.
4904       IsSafe = true;
4905       break;
4906     }
4907     if (!UseEFLAGS && !ModifyEFLAGS)
4908       continue;
4909 
4910     // EFLAGS is used by this instruction.
4911     X86::CondCode OldCC = X86::COND_INVALID;
4912     bool OpcIsSET = false;
4913     if (IsCmpZero || IsSwapped) {
4914       // We decode the condition code from opcode.
4915       if (Instr.isBranch())
4916         OldCC = getCondFromBranchOpc(Instr.getOpcode());
4917       else {
4918         OldCC = getCondFromSETOpc(Instr.getOpcode());
4919         if (OldCC != X86::COND_INVALID)
4920           OpcIsSET = true;
4921         else
4922           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
4923       }
4924       if (OldCC == X86::COND_INVALID) return false;
4925     }
4926     if (IsCmpZero) {
4927       switch (OldCC) {
4928       default: break;
4929       case X86::COND_A: case X86::COND_AE:
4930       case X86::COND_B: case X86::COND_BE:
4931       case X86::COND_G: case X86::COND_GE:
4932       case X86::COND_L: case X86::COND_LE:
4933       case X86::COND_O: case X86::COND_NO:
4934         // CF and OF are used, we can't perform this optimization.
4935         return false;
4936       }
4937 
4938       // If we're updating the condition code check if we have to reverse the
4939       // condition.
4940       if (ShouldUpdateCC)
4941         switch (OldCC) {
4942         default:
4943           return false;
4944         case X86::COND_E:
4945           break;
4946         case X86::COND_NE:
4947           NewCC = GetOppositeBranchCondition(NewCC);
4948           break;
4949         }
4950     } else if (IsSwapped) {
4951       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4952       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4953       // We swap the condition code and synthesize the new opcode.
4954       NewCC = getSwappedCondition(OldCC);
4955       if (NewCC == X86::COND_INVALID) return false;
4956     }
4957 
4958     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
4959       // Synthesize the new opcode.
4960       bool HasMemoryOperand = Instr.hasOneMemOperand();
4961       unsigned NewOpc;
4962       if (Instr.isBranch())
4963         NewOpc = GetCondBranchFromCond(NewCC);
4964       else if(OpcIsSET)
4965         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
4966       else {
4967         unsigned DstReg = Instr.getOperand(0).getReg();
4968         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
4969                                  HasMemoryOperand);
4970       }
4971 
4972       // Push the MachineInstr to OpsToUpdate.
4973       // If it is safe to remove CmpInstr, the condition code of these
4974       // instructions will be modified.
4975       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4976     }
4977     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4978       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4979       IsSafe = true;
4980       break;
4981     }
4982   }
4983 
4984   // If EFLAGS is not killed nor re-defined, we should check whether it is
4985   // live-out. If it is live-out, do not optimize.
4986   if ((IsCmpZero || IsSwapped) && !IsSafe) {
4987     MachineBasicBlock *MBB = CmpInstr->getParent();
4988     for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
4989              SE = MBB->succ_end(); SI != SE; ++SI)
4990       if ((*SI)->isLiveIn(X86::EFLAGS))
4991         return false;
4992   }
4993 
4994   // The instruction to be updated is either Sub or MI.
4995   Sub = IsCmpZero ? MI : Sub;
4996   // Move Movr0Inst to the appropriate place before Sub.
4997   if (Movr0Inst) {
4998     // Look backwards until we find a def that doesn't use the current EFLAGS.
4999     Def = Sub;
5000     MachineBasicBlock::reverse_iterator
5001       InsertI = MachineBasicBlock::reverse_iterator(++Def),
5002                 InsertE = Sub->getParent()->rend();
5003     for (; InsertI != InsertE; ++InsertI) {
5004       MachineInstr *Instr = &*InsertI;
5005       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5006           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5007         Sub->getParent()->remove(Movr0Inst);
5008         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5009                                    Movr0Inst);
5010         break;
5011       }
5012     }
5013     if (InsertI == InsertE)
5014       return false;
5015   }
5016 
5017   // Make sure Sub instruction defines EFLAGS and mark the def live.
5018   unsigned i = 0, e = Sub->getNumOperands();
5019   for (; i != e; ++i) {
5020     MachineOperand &MO = Sub->getOperand(i);
5021     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5022       MO.setIsDead(false);
5023       break;
5024     }
5025   }
5026   assert(i != e && "Unable to locate a def EFLAGS operand");
5027 
5028   CmpInstr->eraseFromParent();
5029 
5030   // Modify the condition code of instructions in OpsToUpdate.
5031   for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
5032     OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
5033   return true;
5034 }
5035 
5036 /// Try to remove the load by folding it to a register
5037 /// operand at the use. We fold the load instructions if load defines a virtual
5038 /// register, the virtual register is used once in the same BB, and the
5039 /// instructions in-between do not load or store, and have no side effects.
5040 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
5041                                               const MachineRegisterInfo *MRI,
5042                                               unsigned &FoldAsLoadDefReg,
5043                                               MachineInstr *&DefMI) const {
5044   if (FoldAsLoadDefReg == 0)
5045     return nullptr;
5046   // To be conservative, if there exists another load, clear the load candidate.
5047   if (MI->mayLoad()) {
5048     FoldAsLoadDefReg = 0;
5049     return nullptr;
5050   }
5051 
5052   // Check whether we can move DefMI here.
5053   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5054   assert(DefMI);
5055   bool SawStore = false;
5056   if (!DefMI->isSafeToMove(nullptr, SawStore))
5057     return nullptr;
5058 
5059   // Collect information about virtual register operands of MI.
5060   unsigned SrcOperandId = 0;
5061   bool FoundSrcOperand = false;
5062   for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
5063     MachineOperand &MO = MI->getOperand(i);
5064     if (!MO.isReg())
5065       continue;
5066     unsigned Reg = MO.getReg();
5067     if (Reg != FoldAsLoadDefReg)
5068       continue;
5069     // Do not fold if we have a subreg use or a def or multiple uses.
5070     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
5071       return nullptr;
5072 
5073     SrcOperandId = i;
5074     FoundSrcOperand = true;
5075   }
5076   if (!FoundSrcOperand)
5077     return nullptr;
5078 
5079   // Check whether we can fold the def into SrcOperandId.
5080   MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI);
5081   if (FoldMI) {
5082     FoldAsLoadDefReg = 0;
5083     return FoldMI;
5084   }
5085 
5086   return nullptr;
5087 }
5088 
5089 /// Expand a single-def pseudo instruction to a two-addr
5090 /// instruction with two undef reads of the register being defined.
5091 /// This is used for mapping:
5092 ///   %xmm4 = V_SET0
5093 /// to:
5094 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5095 ///
5096 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5097                              const MCInstrDesc &Desc) {
5098   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5099   unsigned Reg = MIB->getOperand(0).getReg();
5100   MIB->setDesc(Desc);
5101 
5102   // MachineInstr::addOperand() will insert explicit operands before any
5103   // implicit operands.
5104   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5105   // But we don't trust that.
5106   assert(MIB->getOperand(1).getReg() == Reg &&
5107          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
5108   return true;
5109 }
5110 
5111 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5112 // code sequence is needed for other targets.
5113 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5114                                  const TargetInstrInfo &TII) {
5115   MachineBasicBlock &MBB = *MIB->getParent();
5116   DebugLoc DL = MIB->getDebugLoc();
5117   unsigned Reg = MIB->getOperand(0).getReg();
5118   const GlobalValue *GV =
5119       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
5120   unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
5121   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
5122       MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8);
5123   MachineBasicBlock::iterator I = MIB.getInstr();
5124 
5125   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5126       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5127       .addMemOperand(MMO);
5128   MIB->setDebugLoc(DL);
5129   MIB->setDesc(TII.get(X86::MOV64rm));
5130   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5131 }
5132 
5133 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
5134   bool HasAVX = Subtarget.hasAVX();
5135   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
5136   switch (MI->getOpcode()) {
5137   case X86::MOV32r0:
5138     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
5139   case X86::SETB_C8r:
5140     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
5141   case X86::SETB_C16r:
5142     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
5143   case X86::SETB_C32r:
5144     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
5145   case X86::SETB_C64r:
5146     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
5147   case X86::V_SET0:
5148   case X86::FsFLD0SS:
5149   case X86::FsFLD0SD:
5150     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
5151   case X86::AVX_SET0:
5152     assert(HasAVX && "AVX not supported");
5153     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
5154   case X86::AVX512_512_SET0:
5155     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
5156   case X86::V_SETALLONES:
5157     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
5158   case X86::AVX2_SETALLONES:
5159     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
5160   case X86::TEST8ri_NOREX:
5161     MI->setDesc(get(X86::TEST8ri));
5162     return true;
5163   case X86::KSET0B:
5164   case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
5165   case X86::KSET0D: return Expand2AddrUndef(MIB, get(X86::KXORDrr));
5166   case X86::KSET0Q: return Expand2AddrUndef(MIB, get(X86::KXORQrr));
5167   case X86::KSET1B:
5168   case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
5169   case X86::KSET1D: return Expand2AddrUndef(MIB, get(X86::KXNORDrr));
5170   case X86::KSET1Q: return Expand2AddrUndef(MIB, get(X86::KXNORQrr));
5171   case TargetOpcode::LOAD_STACK_GUARD:
5172     expandLoadStackGuard(MIB, *this);
5173     return true;
5174   }
5175   return false;
5176 }
5177 
5178 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5179                         int PtrOffset = 0) {
5180   unsigned NumAddrOps = MOs.size();
5181 
5182   if (NumAddrOps < 4) {
5183     // FrameIndex only - add an immediate offset (whether its zero or not).
5184     for (unsigned i = 0; i != NumAddrOps; ++i)
5185       MIB.addOperand(MOs[i]);
5186     addOffset(MIB, PtrOffset);
5187   } else {
5188     // General Memory Addressing - we need to add any offset to an existing
5189     // offset.
5190     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5191     for (unsigned i = 0; i != NumAddrOps; ++i) {
5192       const MachineOperand &MO = MOs[i];
5193       if (i == 3 && PtrOffset != 0) {
5194         assert((MO.isImm() || MO.isGlobal()) &&
5195                "Unexpected memory operand type");
5196         if (MO.isImm()) {
5197           MIB.addImm(MO.getImm() + PtrOffset);
5198         } else {
5199           MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset() + PtrOffset,
5200                                MO.getTargetFlags());
5201         }
5202       } else {
5203         MIB.addOperand(MO);
5204       }
5205     }
5206   }
5207 }
5208 
5209 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5210                                      ArrayRef<MachineOperand> MOs,
5211                                      MachineBasicBlock::iterator InsertPt,
5212                                      MachineInstr *MI,
5213                                      const TargetInstrInfo &TII) {
5214   // Create the base instruction with the memory operand as the first part.
5215   // Omit the implicit operands, something BuildMI can't do.
5216   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5217                                               MI->getDebugLoc(), true);
5218   MachineInstrBuilder MIB(MF, NewMI);
5219   addOperands(MIB, MOs);
5220 
5221   // Loop over the rest of the ri operands, converting them over.
5222   unsigned NumOps = MI->getDesc().getNumOperands()-2;
5223   for (unsigned i = 0; i != NumOps; ++i) {
5224     MachineOperand &MO = MI->getOperand(i+2);
5225     MIB.addOperand(MO);
5226   }
5227   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
5228     MachineOperand &MO = MI->getOperand(i);
5229     MIB.addOperand(MO);
5230   }
5231 
5232   MachineBasicBlock *MBB = InsertPt->getParent();
5233   MBB->insert(InsertPt, NewMI);
5234 
5235   return MIB;
5236 }
5237 
5238 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5239                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5240                               MachineBasicBlock::iterator InsertPt,
5241                               MachineInstr *MI, const TargetInstrInfo &TII,
5242                               int PtrOffset = 0) {
5243   // Omit the implicit operands, something BuildMI can't do.
5244   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5245                                               MI->getDebugLoc(), true);
5246   MachineInstrBuilder MIB(MF, NewMI);
5247 
5248   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5249     MachineOperand &MO = MI->getOperand(i);
5250     if (i == OpNo) {
5251       assert(MO.isReg() && "Expected to fold into reg operand!");
5252       addOperands(MIB, MOs, PtrOffset);
5253     } else {
5254       MIB.addOperand(MO);
5255     }
5256   }
5257 
5258   MachineBasicBlock *MBB = InsertPt->getParent();
5259   MBB->insert(InsertPt, NewMI);
5260 
5261   return MIB;
5262 }
5263 
5264 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5265                                 ArrayRef<MachineOperand> MOs,
5266                                 MachineBasicBlock::iterator InsertPt,
5267                                 MachineInstr *MI) {
5268   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5269                                     MI->getDebugLoc(), TII.get(Opcode));
5270   addOperands(MIB, MOs);
5271   return MIB.addImm(0);
5272 }
5273 
5274 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5275     MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5276     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5277     unsigned Size, unsigned Align) const {
5278   switch (MI->getOpcode()) {
5279   case X86::INSERTPSrr:
5280   case X86::VINSERTPSrr:
5281     // Attempt to convert the load of inserted vector into a fold load
5282     // of a single float.
5283     if (OpNum == 2) {
5284       unsigned Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
5285       unsigned ZMask = Imm & 15;
5286       unsigned DstIdx = (Imm >> 4) & 3;
5287       unsigned SrcIdx = (Imm >> 6) & 3;
5288 
5289       unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5290       if (Size <= RCSize && 4 <= Align) {
5291         int PtrOffset = SrcIdx * 4;
5292         unsigned NewImm = (DstIdx << 4) | ZMask;
5293         unsigned NewOpCode =
5294             (MI->getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
5295                                                  : X86::INSERTPSrm);
5296         MachineInstr *NewMI =
5297             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5298         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5299         return NewMI;
5300       }
5301     }
5302     break;
5303   };
5304 
5305   return nullptr;
5306 }
5307 
5308 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5309     MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5310     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5311     unsigned Size, unsigned Align, bool AllowCommute) const {
5312   const DenseMap<unsigned,
5313                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
5314   bool isCallRegIndirect = Subtarget.callRegIndirect();
5315   bool isTwoAddrFold = false;
5316 
5317   // For CPUs that favor the register form of a call or push,
5318   // do not fold loads into calls or pushes, unless optimizing for size
5319   // aggressively.
5320   if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
5321       (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r ||
5322        MI->getOpcode() == X86::PUSH16r || MI->getOpcode() == X86::PUSH32r ||
5323        MI->getOpcode() == X86::PUSH64r))
5324     return nullptr;
5325 
5326   unsigned NumOps = MI->getDesc().getNumOperands();
5327   bool isTwoAddr = NumOps > 1 &&
5328     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5329 
5330   // FIXME: AsmPrinter doesn't know how to handle
5331   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5332   if (MI->getOpcode() == X86::ADD32ri &&
5333       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5334     return nullptr;
5335 
5336   MachineInstr *NewMI = nullptr;
5337 
5338   // Attempt to fold any custom cases we have.
5339   if (MachineInstr *CustomMI =
5340           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
5341     return CustomMI;
5342 
5343   // Folding a memory location into the two-address part of a two-address
5344   // instruction is different than folding it other places.  It requires
5345   // replacing the *two* registers with the memory location.
5346   if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
5347       MI->getOperand(0).isReg() &&
5348       MI->getOperand(1).isReg() &&
5349       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
5350     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5351     isTwoAddrFold = true;
5352   } else if (OpNum == 0) {
5353     if (MI->getOpcode() == X86::MOV32r0) {
5354       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5355       if (NewMI)
5356         return NewMI;
5357     }
5358 
5359     OpcodeTablePtr = &RegOp2MemOpTable0;
5360   } else if (OpNum == 1) {
5361     OpcodeTablePtr = &RegOp2MemOpTable1;
5362   } else if (OpNum == 2) {
5363     OpcodeTablePtr = &RegOp2MemOpTable2;
5364   } else if (OpNum == 3) {
5365     OpcodeTablePtr = &RegOp2MemOpTable3;
5366   } else if (OpNum == 4) {
5367     OpcodeTablePtr = &RegOp2MemOpTable4;
5368   }
5369 
5370   // If table selected...
5371   if (OpcodeTablePtr) {
5372     // Find the Opcode to fuse
5373     DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5374       OpcodeTablePtr->find(MI->getOpcode());
5375     if (I != OpcodeTablePtr->end()) {
5376       unsigned Opcode = I->second.first;
5377       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
5378       if (Align < MinAlign)
5379         return nullptr;
5380       bool NarrowToMOV32rm = false;
5381       if (Size) {
5382         unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5383         if (Size < RCSize) {
5384           // Check if it's safe to fold the load. If the size of the object is
5385           // narrower than the load width, then it's not.
5386           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5387             return nullptr;
5388           // If this is a 64-bit load, but the spill slot is 32, then we can do
5389           // a 32-bit load which is implicitly zero-extended. This likely is
5390           // due to live interval analysis remat'ing a load from stack slot.
5391           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
5392             return nullptr;
5393           Opcode = X86::MOV32rm;
5394           NarrowToMOV32rm = true;
5395         }
5396       }
5397 
5398       if (isTwoAddrFold)
5399         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5400       else
5401         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5402 
5403       if (NarrowToMOV32rm) {
5404         // If this is the special case where we use a MOV32rm to load a 32-bit
5405         // value and zero-extend the top bits. Change the destination register
5406         // to a 32-bit one.
5407         unsigned DstReg = NewMI->getOperand(0).getReg();
5408         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
5409           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5410         else
5411           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5412       }
5413       return NewMI;
5414     }
5415   }
5416 
5417   // If the instruction and target operand are commutable, commute the
5418   // instruction and try again.
5419   if (AllowCommute) {
5420     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5421     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5422       bool HasDef = MI->getDesc().getNumDefs();
5423       unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
5424       unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
5425       unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
5426       bool Tied1 =
5427           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5428       bool Tied2 =
5429           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5430 
5431       // If either of the commutable operands are tied to the destination
5432       // then we can not commute + fold.
5433       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5434           (HasDef && Reg0 == Reg2 && Tied2))
5435         return nullptr;
5436 
5437       MachineInstr *CommutedMI =
5438           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5439       if (!CommutedMI) {
5440         // Unable to commute.
5441         return nullptr;
5442       }
5443       if (CommutedMI != MI) {
5444         // New instruction. We can't fold from this.
5445         CommutedMI->eraseFromParent();
5446         return nullptr;
5447       }
5448 
5449       // Attempt to fold with the commuted version of the instruction.
5450       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5451                                     Size, Align, /*AllowCommute=*/false);
5452       if (NewMI)
5453         return NewMI;
5454 
5455       // Folding failed again - undo the commute before returning.
5456       MachineInstr *UncommutedMI =
5457           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5458       if (!UncommutedMI) {
5459         // Unable to commute.
5460         return nullptr;
5461       }
5462       if (UncommutedMI != MI) {
5463         // New instruction. It doesn't need to be kept.
5464         UncommutedMI->eraseFromParent();
5465         return nullptr;
5466       }
5467 
5468       // Return here to prevent duplicate fuse failure report.
5469       return nullptr;
5470     }
5471   }
5472 
5473   // No fusion
5474   if (PrintFailedFusing && !MI->isCopy())
5475     dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
5476   return nullptr;
5477 }
5478 
5479 /// Return true for all instructions that only update
5480 /// the first 32 or 64-bits of the destination register and leave the rest
5481 /// unmodified. This can be used to avoid folding loads if the instructions
5482 /// only update part of the destination register, and the non-updated part is
5483 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5484 /// instructions breaks the partial register dependency and it can improve
5485 /// performance. e.g.:
5486 ///
5487 ///   movss (%rdi), %xmm0
5488 ///   cvtss2sd %xmm0, %xmm0
5489 ///
5490 /// Instead of
5491 ///   cvtss2sd (%rdi), %xmm0
5492 ///
5493 /// FIXME: This should be turned into a TSFlags.
5494 ///
5495 static bool hasPartialRegUpdate(unsigned Opcode) {
5496   switch (Opcode) {
5497   case X86::CVTSI2SSrr:
5498   case X86::CVTSI2SSrm:
5499   case X86::CVTSI2SS64rr:
5500   case X86::CVTSI2SS64rm:
5501   case X86::CVTSI2SDrr:
5502   case X86::CVTSI2SDrm:
5503   case X86::CVTSI2SD64rr:
5504   case X86::CVTSI2SD64rm:
5505   case X86::CVTSD2SSrr:
5506   case X86::CVTSD2SSrm:
5507   case X86::Int_CVTSD2SSrr:
5508   case X86::Int_CVTSD2SSrm:
5509   case X86::CVTSS2SDrr:
5510   case X86::CVTSS2SDrm:
5511   case X86::Int_CVTSS2SDrr:
5512   case X86::Int_CVTSS2SDrm:
5513   case X86::RCPSSr:
5514   case X86::RCPSSm:
5515   case X86::RCPSSr_Int:
5516   case X86::RCPSSm_Int:
5517   case X86::ROUNDSDr:
5518   case X86::ROUNDSDm:
5519   case X86::ROUNDSDr_Int:
5520   case X86::ROUNDSSr:
5521   case X86::ROUNDSSm:
5522   case X86::ROUNDSSr_Int:
5523   case X86::RSQRTSSr:
5524   case X86::RSQRTSSm:
5525   case X86::RSQRTSSr_Int:
5526   case X86::RSQRTSSm_Int:
5527   case X86::SQRTSSr:
5528   case X86::SQRTSSm:
5529   case X86::SQRTSSr_Int:
5530   case X86::SQRTSSm_Int:
5531   case X86::SQRTSDr:
5532   case X86::SQRTSDm:
5533   case X86::SQRTSDr_Int:
5534   case X86::SQRTSDm_Int:
5535     return true;
5536   }
5537 
5538   return false;
5539 }
5540 
5541 /// Inform the ExeDepsFix pass how many idle
5542 /// instructions we would like before a partial register update.
5543 unsigned X86InstrInfo::
5544 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
5545                              const TargetRegisterInfo *TRI) const {
5546   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
5547     return 0;
5548 
5549   // If MI is marked as reading Reg, the partial register update is wanted.
5550   const MachineOperand &MO = MI->getOperand(0);
5551   unsigned Reg = MO.getReg();
5552   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
5553     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
5554       return 0;
5555   } else {
5556     if (MI->readsRegister(Reg, TRI))
5557       return 0;
5558   }
5559 
5560   // If any of the preceding 16 instructions are reading Reg, insert a
5561   // dependency breaking instruction.  The magic number is based on a few
5562   // Nehalem experiments.
5563   return 16;
5564 }
5565 
5566 // Return true for any instruction the copies the high bits of the first source
5567 // operand into the unused high bits of the destination operand.
5568 static bool hasUndefRegUpdate(unsigned Opcode) {
5569   switch (Opcode) {
5570   case X86::VCVTSI2SSrr:
5571   case X86::VCVTSI2SSrm:
5572   case X86::Int_VCVTSI2SSrr:
5573   case X86::Int_VCVTSI2SSrm:
5574   case X86::VCVTSI2SS64rr:
5575   case X86::VCVTSI2SS64rm:
5576   case X86::Int_VCVTSI2SS64rr:
5577   case X86::Int_VCVTSI2SS64rm:
5578   case X86::VCVTSI2SDrr:
5579   case X86::VCVTSI2SDrm:
5580   case X86::Int_VCVTSI2SDrr:
5581   case X86::Int_VCVTSI2SDrm:
5582   case X86::VCVTSI2SD64rr:
5583   case X86::VCVTSI2SD64rm:
5584   case X86::Int_VCVTSI2SD64rr:
5585   case X86::Int_VCVTSI2SD64rm:
5586   case X86::VCVTSD2SSrr:
5587   case X86::VCVTSD2SSrm:
5588   case X86::Int_VCVTSD2SSrr:
5589   case X86::Int_VCVTSD2SSrm:
5590   case X86::VCVTSS2SDrr:
5591   case X86::VCVTSS2SDrm:
5592   case X86::Int_VCVTSS2SDrr:
5593   case X86::Int_VCVTSS2SDrm:
5594   case X86::VRCPSSr:
5595   case X86::VRCPSSm:
5596   case X86::VRCPSSm_Int:
5597   case X86::VROUNDSDr:
5598   case X86::VROUNDSDm:
5599   case X86::VROUNDSDr_Int:
5600   case X86::VROUNDSSr:
5601   case X86::VROUNDSSm:
5602   case X86::VROUNDSSr_Int:
5603   case X86::VRSQRTSSr:
5604   case X86::VRSQRTSSm:
5605   case X86::VRSQRTSSm_Int:
5606   case X86::VSQRTSSr:
5607   case X86::VSQRTSSm:
5608   case X86::VSQRTSSm_Int:
5609   case X86::VSQRTSDr:
5610   case X86::VSQRTSDm:
5611   case X86::VSQRTSDm_Int:
5612     // AVX-512
5613   case X86::VCVTSD2SSZrr:
5614   case X86::VCVTSD2SSZrm:
5615   case X86::VCVTSS2SDZrr:
5616   case X86::VCVTSS2SDZrm:
5617     return true;
5618   }
5619 
5620   return false;
5621 }
5622 
5623 /// Inform the ExeDepsFix pass how many idle instructions we would like before
5624 /// certain undef register reads.
5625 ///
5626 /// This catches the VCVTSI2SD family of instructions:
5627 ///
5628 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
5629 ///
5630 /// We should to be careful *not* to catch VXOR idioms which are presumably
5631 /// handled specially in the pipeline:
5632 ///
5633 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
5634 ///
5635 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5636 /// high bits that are passed-through are not live.
5637 unsigned X86InstrInfo::
5638 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
5639                      const TargetRegisterInfo *TRI) const {
5640   if (!hasUndefRegUpdate(MI->getOpcode()))
5641     return 0;
5642 
5643   // Set the OpNum parameter to the first source operand.
5644   OpNum = 1;
5645 
5646   const MachineOperand &MO = MI->getOperand(OpNum);
5647   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
5648     // Use the same magic number as getPartialRegUpdateClearance.
5649     return 16;
5650   }
5651   return 0;
5652 }
5653 
5654 void X86InstrInfo::
5655 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
5656                           const TargetRegisterInfo *TRI) const {
5657   unsigned Reg = MI->getOperand(OpNum).getReg();
5658   // If MI kills this register, the false dependence is already broken.
5659   if (MI->killsRegister(Reg, TRI))
5660     return;
5661   if (X86::VR128RegClass.contains(Reg)) {
5662     // These instructions are all floating point domain, so xorps is the best
5663     // choice.
5664     bool HasAVX = Subtarget.hasAVX();
5665     unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
5666     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
5667       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5668   } else if (X86::VR256RegClass.contains(Reg)) {
5669     // Use vxorps to clear the full ymm register.
5670     // It wants to read and write the xmm sub-register.
5671     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5672     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
5673       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
5674       .addReg(Reg, RegState::ImplicitDefine);
5675   } else
5676     return;
5677   MI->addRegisterKilled(Reg, TRI, true);
5678 }
5679 
5680 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5681     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
5682     MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
5683   // Check switch flag
5684   if (NoFusing) return nullptr;
5685 
5686   // Unless optimizing for size, don't fold to avoid partial
5687   // register update stalls
5688   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
5689     return nullptr;
5690 
5691   const MachineFrameInfo *MFI = MF.getFrameInfo();
5692   unsigned Size = MFI->getObjectSize(FrameIndex);
5693   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
5694   // If the function stack isn't realigned we don't want to fold instructions
5695   // that need increased alignment.
5696   if (!RI.needsStackRealignment(MF))
5697     Alignment =
5698         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
5699   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5700     unsigned NewOpc = 0;
5701     unsigned RCSize = 0;
5702     switch (MI->getOpcode()) {
5703     default: return nullptr;
5704     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5705     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5706     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5707     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5708     }
5709     // Check if it's safe to fold the load. If the size of the object is
5710     // narrower than the load width, then it's not.
5711     if (Size < RCSize)
5712       return nullptr;
5713     // Change to CMPXXri r, 0 first.
5714     MI->setDesc(get(NewOpc));
5715     MI->getOperand(1).ChangeToImmediate(0);
5716   } else if (Ops.size() != 1)
5717     return nullptr;
5718 
5719   return foldMemoryOperandImpl(MF, MI, Ops[0],
5720                                MachineOperand::CreateFI(FrameIndex), InsertPt,
5721                                Size, Alignment, /*AllowCommute=*/true);
5722 }
5723 
5724 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5725 /// because the latter uses contents that wouldn't be defined in the folded
5726 /// version.  For instance, this transformation isn't legal:
5727 ///   movss (%rdi), %xmm0
5728 ///   addps %xmm0, %xmm0
5729 /// ->
5730 ///   addps (%rdi), %xmm0
5731 ///
5732 /// But this one is:
5733 ///   movss (%rdi), %xmm0
5734 ///   addss %xmm0, %xmm0
5735 /// ->
5736 ///   addss (%rdi), %xmm0
5737 ///
5738 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5739                                              const MachineInstr &UserMI,
5740                                              const MachineFunction &MF) {
5741   unsigned Opc = LoadMI.getOpcode();
5742   unsigned UserOpc = UserMI.getOpcode();
5743   unsigned RegSize =
5744       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
5745 
5746   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
5747     // These instructions only load 32 bits, we can't fold them if the
5748     // destination register is wider than 32 bits (4 bytes), and its user
5749     // instruction isn't scalar (SS).
5750     switch (UserOpc) {
5751     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
5752     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
5753     case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
5754     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
5755       return false;
5756     default:
5757       return true;
5758     }
5759   }
5760 
5761   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
5762     // These instructions only load 64 bits, we can't fold them if the
5763     // destination register is wider than 64 bits (8 bytes), and its user
5764     // instruction isn't scalar (SD).
5765     switch (UserOpc) {
5766     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
5767     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
5768     case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
5769     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
5770       return false;
5771     default:
5772       return true;
5773     }
5774   }
5775 
5776   return false;
5777 }
5778 
5779 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5780     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
5781     MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
5782   // If loading from a FrameIndex, fold directly from the FrameIndex.
5783   unsigned NumOps = LoadMI->getDesc().getNumOperands();
5784   int FrameIndex;
5785   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5786     if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
5787       return nullptr;
5788     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex);
5789   }
5790 
5791   // Check switch flag
5792   if (NoFusing) return nullptr;
5793 
5794   // Avoid partial register update stalls unless optimizing for size.
5795   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
5796     return nullptr;
5797 
5798   // Determine the alignment of the load.
5799   unsigned Alignment = 0;
5800   if (LoadMI->hasOneMemOperand())
5801     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
5802   else
5803     switch (LoadMI->getOpcode()) {
5804     case X86::AVX2_SETALLONES:
5805     case X86::AVX_SET0:
5806       Alignment = 32;
5807       break;
5808     case X86::V_SET0:
5809     case X86::V_SETALLONES:
5810       Alignment = 16;
5811       break;
5812     case X86::FsFLD0SD:
5813       Alignment = 8;
5814       break;
5815     case X86::FsFLD0SS:
5816       Alignment = 4;
5817       break;
5818     default:
5819       return nullptr;
5820     }
5821   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5822     unsigned NewOpc = 0;
5823     switch (MI->getOpcode()) {
5824     default: return nullptr;
5825     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
5826     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5827     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5828     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5829     }
5830     // Change to CMPXXri r, 0 first.
5831     MI->setDesc(get(NewOpc));
5832     MI->getOperand(1).ChangeToImmediate(0);
5833   } else if (Ops.size() != 1)
5834     return nullptr;
5835 
5836   // Make sure the subregisters match.
5837   // Otherwise we risk changing the size of the load.
5838   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
5839     return nullptr;
5840 
5841   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5842   switch (LoadMI->getOpcode()) {
5843   case X86::V_SET0:
5844   case X86::V_SETALLONES:
5845   case X86::AVX2_SETALLONES:
5846   case X86::AVX_SET0:
5847   case X86::FsFLD0SD:
5848   case X86::FsFLD0SS: {
5849     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5850     // Create a constant-pool entry and operands to load from it.
5851 
5852     // Medium and large mode can't fold loads this way.
5853     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5854         MF.getTarget().getCodeModel() != CodeModel::Kernel)
5855       return nullptr;
5856 
5857     // x86-32 PIC requires a PIC base register for constant pools.
5858     unsigned PICBase = 0;
5859     if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
5860       if (Subtarget.is64Bit())
5861         PICBase = X86::RIP;
5862       else
5863         // FIXME: PICBase = getGlobalBaseReg(&MF);
5864         // This doesn't work for several reasons.
5865         // 1. GlobalBaseReg may have been spilled.
5866         // 2. It may not be live at MI.
5867         return nullptr;
5868     }
5869 
5870     // Create a constant-pool entry.
5871     MachineConstantPool &MCP = *MF.getConstantPool();
5872     Type *Ty;
5873     unsigned Opc = LoadMI->getOpcode();
5874     if (Opc == X86::FsFLD0SS)
5875       Ty = Type::getFloatTy(MF.getFunction()->getContext());
5876     else if (Opc == X86::FsFLD0SD)
5877       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
5878     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
5879       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
5880     else
5881       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
5882 
5883     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
5884     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5885                                     Constant::getNullValue(Ty);
5886     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5887 
5888     // Create operands to load from the constant pool entry.
5889     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5890     MOs.push_back(MachineOperand::CreateImm(1));
5891     MOs.push_back(MachineOperand::CreateReg(0, false));
5892     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5893     MOs.push_back(MachineOperand::CreateReg(0, false));
5894     break;
5895   }
5896   default: {
5897     if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
5898       return nullptr;
5899 
5900     // Folding a normal load. Just copy the load's address operands.
5901     MOs.append(LoadMI->operands_begin() + NumOps - X86::AddrNumOperands,
5902                LoadMI->operands_begin() + NumOps);
5903     break;
5904   }
5905   }
5906   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5907                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
5908 }
5909 
5910 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
5911                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
5912                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
5913   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5914     MemOp2RegOpTable.find(MI->getOpcode());
5915   if (I == MemOp2RegOpTable.end())
5916     return false;
5917   unsigned Opc = I->second.first;
5918   unsigned Index = I->second.second & TB_INDEX_MASK;
5919   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5920   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5921   if (UnfoldLoad && !FoldedLoad)
5922     return false;
5923   UnfoldLoad &= FoldedLoad;
5924   if (UnfoldStore && !FoldedStore)
5925     return false;
5926   UnfoldStore &= FoldedStore;
5927 
5928   const MCInstrDesc &MCID = get(Opc);
5929   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5930   // TODO: Check if 32-byte or greater accesses are slow too?
5931   if (!MI->hasOneMemOperand() &&
5932       RC == &X86::VR128RegClass &&
5933       Subtarget.isUnalignedMem16Slow())
5934     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5935     // conservatively assume the address is unaligned. That's bad for
5936     // performance.
5937     return false;
5938   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5939   SmallVector<MachineOperand,2> BeforeOps;
5940   SmallVector<MachineOperand,2> AfterOps;
5941   SmallVector<MachineOperand,4> ImpOps;
5942   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5943     MachineOperand &Op = MI->getOperand(i);
5944     if (i >= Index && i < Index + X86::AddrNumOperands)
5945       AddrOps.push_back(Op);
5946     else if (Op.isReg() && Op.isImplicit())
5947       ImpOps.push_back(Op);
5948     else if (i < Index)
5949       BeforeOps.push_back(Op);
5950     else if (i > Index)
5951       AfterOps.push_back(Op);
5952   }
5953 
5954   // Emit the load instruction.
5955   if (UnfoldLoad) {
5956     std::pair<MachineInstr::mmo_iterator,
5957               MachineInstr::mmo_iterator> MMOs =
5958       MF.extractLoadMemRefs(MI->memoperands_begin(),
5959                             MI->memoperands_end());
5960     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
5961     if (UnfoldStore) {
5962       // Address operands cannot be marked isKill.
5963       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5964         MachineOperand &MO = NewMIs[0]->getOperand(i);
5965         if (MO.isReg())
5966           MO.setIsKill(false);
5967       }
5968     }
5969   }
5970 
5971   // Emit the data processing instruction.
5972   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
5973   MachineInstrBuilder MIB(MF, DataMI);
5974 
5975   if (FoldedStore)
5976     MIB.addReg(Reg, RegState::Define);
5977   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
5978     MIB.addOperand(BeforeOps[i]);
5979   if (FoldedLoad)
5980     MIB.addReg(Reg);
5981   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
5982     MIB.addOperand(AfterOps[i]);
5983   for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
5984     MachineOperand &MO = ImpOps[i];
5985     MIB.addReg(MO.getReg(),
5986                getDefRegState(MO.isDef()) |
5987                RegState::Implicit |
5988                getKillRegState(MO.isKill()) |
5989                getDeadRegState(MO.isDead()) |
5990                getUndefRegState(MO.isUndef()));
5991   }
5992   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5993   switch (DataMI->getOpcode()) {
5994   default: break;
5995   case X86::CMP64ri32:
5996   case X86::CMP64ri8:
5997   case X86::CMP32ri:
5998   case X86::CMP32ri8:
5999   case X86::CMP16ri:
6000   case X86::CMP16ri8:
6001   case X86::CMP8ri: {
6002     MachineOperand &MO0 = DataMI->getOperand(0);
6003     MachineOperand &MO1 = DataMI->getOperand(1);
6004     if (MO1.getImm() == 0) {
6005       unsigned NewOpc;
6006       switch (DataMI->getOpcode()) {
6007       default: llvm_unreachable("Unreachable!");
6008       case X86::CMP64ri8:
6009       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6010       case X86::CMP32ri8:
6011       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6012       case X86::CMP16ri8:
6013       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6014       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6015       }
6016       DataMI->setDesc(get(NewOpc));
6017       MO1.ChangeToRegister(MO0.getReg(), false);
6018     }
6019   }
6020   }
6021   NewMIs.push_back(DataMI);
6022 
6023   // Emit the store instruction.
6024   if (UnfoldStore) {
6025     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6026     std::pair<MachineInstr::mmo_iterator,
6027               MachineInstr::mmo_iterator> MMOs =
6028       MF.extractStoreMemRefs(MI->memoperands_begin(),
6029                              MI->memoperands_end());
6030     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
6031   }
6032 
6033   return true;
6034 }
6035 
6036 bool
6037 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6038                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6039   if (!N->isMachineOpcode())
6040     return false;
6041 
6042   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
6043     MemOp2RegOpTable.find(N->getMachineOpcode());
6044   if (I == MemOp2RegOpTable.end())
6045     return false;
6046   unsigned Opc = I->second.first;
6047   unsigned Index = I->second.second & TB_INDEX_MASK;
6048   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6049   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6050   const MCInstrDesc &MCID = get(Opc);
6051   MachineFunction &MF = DAG.getMachineFunction();
6052   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6053   unsigned NumDefs = MCID.NumDefs;
6054   std::vector<SDValue> AddrOps;
6055   std::vector<SDValue> BeforeOps;
6056   std::vector<SDValue> AfterOps;
6057   SDLoc dl(N);
6058   unsigned NumOps = N->getNumOperands();
6059   for (unsigned i = 0; i != NumOps-1; ++i) {
6060     SDValue Op = N->getOperand(i);
6061     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6062       AddrOps.push_back(Op);
6063     else if (i < Index-NumDefs)
6064       BeforeOps.push_back(Op);
6065     else if (i > Index-NumDefs)
6066       AfterOps.push_back(Op);
6067   }
6068   SDValue Chain = N->getOperand(NumOps-1);
6069   AddrOps.push_back(Chain);
6070 
6071   // Emit the load instruction.
6072   SDNode *Load = nullptr;
6073   if (FoldedLoad) {
6074     EVT VT = *RC->vt_begin();
6075     std::pair<MachineInstr::mmo_iterator,
6076               MachineInstr::mmo_iterator> MMOs =
6077       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6078                             cast<MachineSDNode>(N)->memoperands_end());
6079     if (!(*MMOs.first) &&
6080         RC == &X86::VR128RegClass &&
6081         Subtarget.isUnalignedMem16Slow())
6082       // Do not introduce a slow unaligned load.
6083       return false;
6084     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6085     // memory access is slow above.
6086     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6087     bool isAligned = (*MMOs.first) &&
6088                      (*MMOs.first)->getAlignment() >= Alignment;
6089     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
6090                               VT, MVT::Other, AddrOps);
6091     NewNodes.push_back(Load);
6092 
6093     // Preserve memory reference information.
6094     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
6095   }
6096 
6097   // Emit the data processing instruction.
6098   std::vector<EVT> VTs;
6099   const TargetRegisterClass *DstRC = nullptr;
6100   if (MCID.getNumDefs() > 0) {
6101     DstRC = getRegClass(MCID, 0, &RI, MF);
6102     VTs.push_back(*DstRC->vt_begin());
6103   }
6104   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6105     EVT VT = N->getValueType(i);
6106     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6107       VTs.push_back(VT);
6108   }
6109   if (Load)
6110     BeforeOps.push_back(SDValue(Load, 0));
6111   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
6112   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6113   NewNodes.push_back(NewNode);
6114 
6115   // Emit the store instruction.
6116   if (FoldedStore) {
6117     AddrOps.pop_back();
6118     AddrOps.push_back(SDValue(NewNode, 0));
6119     AddrOps.push_back(Chain);
6120     std::pair<MachineInstr::mmo_iterator,
6121               MachineInstr::mmo_iterator> MMOs =
6122       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6123                              cast<MachineSDNode>(N)->memoperands_end());
6124     if (!(*MMOs.first) &&
6125         RC == &X86::VR128RegClass &&
6126         Subtarget.isUnalignedMem16Slow())
6127       // Do not introduce a slow unaligned store.
6128       return false;
6129     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6130     // memory access is slow above.
6131     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6132     bool isAligned = (*MMOs.first) &&
6133                      (*MMOs.first)->getAlignment() >= Alignment;
6134     SDNode *Store =
6135         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6136                            dl, MVT::Other, AddrOps);
6137     NewNodes.push_back(Store);
6138 
6139     // Preserve memory reference information.
6140     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
6141   }
6142 
6143   return true;
6144 }
6145 
6146 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6147                                       bool UnfoldLoad, bool UnfoldStore,
6148                                       unsigned *LoadRegIndex) const {
6149   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
6150     MemOp2RegOpTable.find(Opc);
6151   if (I == MemOp2RegOpTable.end())
6152     return 0;
6153   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6154   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6155   if (UnfoldLoad && !FoldedLoad)
6156     return 0;
6157   if (UnfoldStore && !FoldedStore)
6158     return 0;
6159   if (LoadRegIndex)
6160     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
6161   return I->second.first;
6162 }
6163 
6164 bool
6165 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6166                                      int64_t &Offset1, int64_t &Offset2) const {
6167   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6168     return false;
6169   unsigned Opc1 = Load1->getMachineOpcode();
6170   unsigned Opc2 = Load2->getMachineOpcode();
6171   switch (Opc1) {
6172   default: return false;
6173   case X86::MOV8rm:
6174   case X86::MOV16rm:
6175   case X86::MOV32rm:
6176   case X86::MOV64rm:
6177   case X86::LD_Fp32m:
6178   case X86::LD_Fp64m:
6179   case X86::LD_Fp80m:
6180   case X86::MOVSSrm:
6181   case X86::MOVSDrm:
6182   case X86::MMX_MOVD64rm:
6183   case X86::MMX_MOVQ64rm:
6184   case X86::FsMOVAPSrm:
6185   case X86::FsMOVAPDrm:
6186   case X86::MOVAPSrm:
6187   case X86::MOVUPSrm:
6188   case X86::MOVAPDrm:
6189   case X86::MOVDQArm:
6190   case X86::MOVDQUrm:
6191   // AVX load instructions
6192   case X86::VMOVSSrm:
6193   case X86::VMOVSDrm:
6194   case X86::FsVMOVAPSrm:
6195   case X86::FsVMOVAPDrm:
6196   case X86::VMOVAPSrm:
6197   case X86::VMOVUPSrm:
6198   case X86::VMOVAPDrm:
6199   case X86::VMOVDQArm:
6200   case X86::VMOVDQUrm:
6201   case X86::VMOVAPSYrm:
6202   case X86::VMOVUPSYrm:
6203   case X86::VMOVAPDYrm:
6204   case X86::VMOVDQAYrm:
6205   case X86::VMOVDQUYrm:
6206     break;
6207   }
6208   switch (Opc2) {
6209   default: return false;
6210   case X86::MOV8rm:
6211   case X86::MOV16rm:
6212   case X86::MOV32rm:
6213   case X86::MOV64rm:
6214   case X86::LD_Fp32m:
6215   case X86::LD_Fp64m:
6216   case X86::LD_Fp80m:
6217   case X86::MOVSSrm:
6218   case X86::MOVSDrm:
6219   case X86::MMX_MOVD64rm:
6220   case X86::MMX_MOVQ64rm:
6221   case X86::FsMOVAPSrm:
6222   case X86::FsMOVAPDrm:
6223   case X86::MOVAPSrm:
6224   case X86::MOVUPSrm:
6225   case X86::MOVAPDrm:
6226   case X86::MOVDQArm:
6227   case X86::MOVDQUrm:
6228   // AVX load instructions
6229   case X86::VMOVSSrm:
6230   case X86::VMOVSDrm:
6231   case X86::FsVMOVAPSrm:
6232   case X86::FsVMOVAPDrm:
6233   case X86::VMOVAPSrm:
6234   case X86::VMOVUPSrm:
6235   case X86::VMOVAPDrm:
6236   case X86::VMOVDQArm:
6237   case X86::VMOVDQUrm:
6238   case X86::VMOVAPSYrm:
6239   case X86::VMOVUPSYrm:
6240   case X86::VMOVAPDYrm:
6241   case X86::VMOVDQAYrm:
6242   case X86::VMOVDQUYrm:
6243     break;
6244   }
6245 
6246   // Check if chain operands and base addresses match.
6247   if (Load1->getOperand(0) != Load2->getOperand(0) ||
6248       Load1->getOperand(5) != Load2->getOperand(5))
6249     return false;
6250   // Segment operands should match as well.
6251   if (Load1->getOperand(4) != Load2->getOperand(4))
6252     return false;
6253   // Scale should be 1, Index should be Reg0.
6254   if (Load1->getOperand(1) == Load2->getOperand(1) &&
6255       Load1->getOperand(2) == Load2->getOperand(2)) {
6256     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6257       return false;
6258 
6259     // Now let's examine the displacements.
6260     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6261         isa<ConstantSDNode>(Load2->getOperand(3))) {
6262       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6263       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6264       return true;
6265     }
6266   }
6267   return false;
6268 }
6269 
6270 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6271                                            int64_t Offset1, int64_t Offset2,
6272                                            unsigned NumLoads) const {
6273   assert(Offset2 > Offset1);
6274   if ((Offset2 - Offset1) / 8 > 64)
6275     return false;
6276 
6277   unsigned Opc1 = Load1->getMachineOpcode();
6278   unsigned Opc2 = Load2->getMachineOpcode();
6279   if (Opc1 != Opc2)
6280     return false;  // FIXME: overly conservative?
6281 
6282   switch (Opc1) {
6283   default: break;
6284   case X86::LD_Fp32m:
6285   case X86::LD_Fp64m:
6286   case X86::LD_Fp80m:
6287   case X86::MMX_MOVD64rm:
6288   case X86::MMX_MOVQ64rm:
6289     return false;
6290   }
6291 
6292   EVT VT = Load1->getValueType(0);
6293   switch (VT.getSimpleVT().SimpleTy) {
6294   default:
6295     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6296     // have 16 of them to play with.
6297     if (Subtarget.is64Bit()) {
6298       if (NumLoads >= 3)
6299         return false;
6300     } else if (NumLoads) {
6301       return false;
6302     }
6303     break;
6304   case MVT::i8:
6305   case MVT::i16:
6306   case MVT::i32:
6307   case MVT::i64:
6308   case MVT::f32:
6309   case MVT::f64:
6310     if (NumLoads)
6311       return false;
6312     break;
6313   }
6314 
6315   return true;
6316 }
6317 
6318 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
6319                                           MachineInstr *Second) const {
6320   // Check if this processor supports macro-fusion. Since this is a minor
6321   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6322   // proxy for SandyBridge+.
6323   if (!Subtarget.hasAVX())
6324     return false;
6325 
6326   enum {
6327     FuseTest,
6328     FuseCmp,
6329     FuseInc
6330   } FuseKind;
6331 
6332   switch(Second->getOpcode()) {
6333   default:
6334     return false;
6335   case X86::JE_1:
6336   case X86::JNE_1:
6337   case X86::JL_1:
6338   case X86::JLE_1:
6339   case X86::JG_1:
6340   case X86::JGE_1:
6341     FuseKind = FuseInc;
6342     break;
6343   case X86::JB_1:
6344   case X86::JBE_1:
6345   case X86::JA_1:
6346   case X86::JAE_1:
6347     FuseKind = FuseCmp;
6348     break;
6349   case X86::JS_1:
6350   case X86::JNS_1:
6351   case X86::JP_1:
6352   case X86::JNP_1:
6353   case X86::JO_1:
6354   case X86::JNO_1:
6355     FuseKind = FuseTest;
6356     break;
6357   }
6358   switch (First->getOpcode()) {
6359   default:
6360     return false;
6361   case X86::TEST8rr:
6362   case X86::TEST16rr:
6363   case X86::TEST32rr:
6364   case X86::TEST64rr:
6365   case X86::TEST8ri:
6366   case X86::TEST16ri:
6367   case X86::TEST32ri:
6368   case X86::TEST32i32:
6369   case X86::TEST64i32:
6370   case X86::TEST64ri32:
6371   case X86::TEST8rm:
6372   case X86::TEST16rm:
6373   case X86::TEST32rm:
6374   case X86::TEST64rm:
6375   case X86::TEST8ri_NOREX:
6376   case X86::AND16i16:
6377   case X86::AND16ri:
6378   case X86::AND16ri8:
6379   case X86::AND16rm:
6380   case X86::AND16rr:
6381   case X86::AND32i32:
6382   case X86::AND32ri:
6383   case X86::AND32ri8:
6384   case X86::AND32rm:
6385   case X86::AND32rr:
6386   case X86::AND64i32:
6387   case X86::AND64ri32:
6388   case X86::AND64ri8:
6389   case X86::AND64rm:
6390   case X86::AND64rr:
6391   case X86::AND8i8:
6392   case X86::AND8ri:
6393   case X86::AND8rm:
6394   case X86::AND8rr:
6395     return true;
6396   case X86::CMP16i16:
6397   case X86::CMP16ri:
6398   case X86::CMP16ri8:
6399   case X86::CMP16rm:
6400   case X86::CMP16rr:
6401   case X86::CMP32i32:
6402   case X86::CMP32ri:
6403   case X86::CMP32ri8:
6404   case X86::CMP32rm:
6405   case X86::CMP32rr:
6406   case X86::CMP64i32:
6407   case X86::CMP64ri32:
6408   case X86::CMP64ri8:
6409   case X86::CMP64rm:
6410   case X86::CMP64rr:
6411   case X86::CMP8i8:
6412   case X86::CMP8ri:
6413   case X86::CMP8rm:
6414   case X86::CMP8rr:
6415   case X86::ADD16i16:
6416   case X86::ADD16ri:
6417   case X86::ADD16ri8:
6418   case X86::ADD16ri8_DB:
6419   case X86::ADD16ri_DB:
6420   case X86::ADD16rm:
6421   case X86::ADD16rr:
6422   case X86::ADD16rr_DB:
6423   case X86::ADD32i32:
6424   case X86::ADD32ri:
6425   case X86::ADD32ri8:
6426   case X86::ADD32ri8_DB:
6427   case X86::ADD32ri_DB:
6428   case X86::ADD32rm:
6429   case X86::ADD32rr:
6430   case X86::ADD32rr_DB:
6431   case X86::ADD64i32:
6432   case X86::ADD64ri32:
6433   case X86::ADD64ri32_DB:
6434   case X86::ADD64ri8:
6435   case X86::ADD64ri8_DB:
6436   case X86::ADD64rm:
6437   case X86::ADD64rr:
6438   case X86::ADD64rr_DB:
6439   case X86::ADD8i8:
6440   case X86::ADD8mi:
6441   case X86::ADD8mr:
6442   case X86::ADD8ri:
6443   case X86::ADD8rm:
6444   case X86::ADD8rr:
6445   case X86::SUB16i16:
6446   case X86::SUB16ri:
6447   case X86::SUB16ri8:
6448   case X86::SUB16rm:
6449   case X86::SUB16rr:
6450   case X86::SUB32i32:
6451   case X86::SUB32ri:
6452   case X86::SUB32ri8:
6453   case X86::SUB32rm:
6454   case X86::SUB32rr:
6455   case X86::SUB64i32:
6456   case X86::SUB64ri32:
6457   case X86::SUB64ri8:
6458   case X86::SUB64rm:
6459   case X86::SUB64rr:
6460   case X86::SUB8i8:
6461   case X86::SUB8ri:
6462   case X86::SUB8rm:
6463   case X86::SUB8rr:
6464     return FuseKind == FuseCmp || FuseKind == FuseInc;
6465   case X86::INC16r:
6466   case X86::INC32r:
6467   case X86::INC64r:
6468   case X86::INC8r:
6469   case X86::DEC16r:
6470   case X86::DEC32r:
6471   case X86::DEC64r:
6472   case X86::DEC8r:
6473     return FuseKind == FuseInc;
6474   }
6475 }
6476 
6477 bool X86InstrInfo::
6478 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6479   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6480   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6481   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
6482     return true;
6483   Cond[0].setImm(GetOppositeBranchCondition(CC));
6484   return false;
6485 }
6486 
6487 bool X86InstrInfo::
6488 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6489   // FIXME: Return false for x87 stack register classes for now. We can't
6490   // allow any loads of these registers before FpGet_ST0_80.
6491   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6492            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
6493 }
6494 
6495 /// Return a virtual register initialized with the
6496 /// the global base register value. Output instructions required to
6497 /// initialize the register in the function entry block, if necessary.
6498 ///
6499 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6500 ///
6501 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6502   assert(!Subtarget.is64Bit() &&
6503          "X86-64 PIC uses RIP relative addressing");
6504 
6505   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6506   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6507   if (GlobalBaseReg != 0)
6508     return GlobalBaseReg;
6509 
6510   // Create the register. The code to initialize it is inserted
6511   // later, by the CGBR pass (below).
6512   MachineRegisterInfo &RegInfo = MF->getRegInfo();
6513   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
6514   X86FI->setGlobalBaseReg(GlobalBaseReg);
6515   return GlobalBaseReg;
6516 }
6517 
6518 // These are the replaceable SSE instructions. Some of these have Int variants
6519 // that we don't include here. We don't want to replace instructions selected
6520 // by intrinsics.
6521 static const uint16_t ReplaceableInstrs[][3] = {
6522   //PackedSingle     PackedDouble    PackedInt
6523   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
6524   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
6525   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
6526   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
6527   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
6528   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr  },
6529   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
6530   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
6531   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
6532   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
6533   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
6534   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
6535   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
6536   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
6537   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
6538   // AVX 128-bit support
6539   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
6540   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
6541   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
6542   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
6543   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
6544   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr  },
6545   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6546   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
6547   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
6548   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
6549   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
6550   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
6551   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
6552   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
6553   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
6554   // AVX 256-bit support
6555   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
6556   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
6557   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
6558   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
6559   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
6560   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
6561 };
6562 
6563 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6564   //PackedSingle       PackedDouble       PackedInt
6565   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
6566   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
6567   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
6568   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
6569   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
6570   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
6571   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
6572   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
6573   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6574   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6575   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
6576   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
6577   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
6578   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
6579   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6580   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6581   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6582   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6583   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6584   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
6585 };
6586 
6587 // FIXME: Some shuffle and unpack instructions have equivalents in different
6588 // domains, but they require a bit more work than just switching opcodes.
6589 
6590 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
6591   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
6592     if (ReplaceableInstrs[i][domain-1] == opcode)
6593       return ReplaceableInstrs[i];
6594   return nullptr;
6595 }
6596 
6597 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
6598   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
6599     if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
6600       return ReplaceableInstrsAVX2[i];
6601   return nullptr;
6602 }
6603 
6604 std::pair<uint16_t, uint16_t>
6605 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
6606   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6607   bool hasAVX2 = Subtarget.hasAVX2();
6608   uint16_t validDomains = 0;
6609   if (domain && lookup(MI->getOpcode(), domain))
6610     validDomains = 0xe;
6611   else if (domain && lookupAVX2(MI->getOpcode(), domain))
6612     validDomains = hasAVX2 ? 0xe : 0x6;
6613   return std::make_pair(domain, validDomains);
6614 }
6615 
6616 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
6617   assert(Domain>0 && Domain<4 && "Invalid execution domain");
6618   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6619   assert(dom && "Not an SSE instruction");
6620   const uint16_t *table = lookup(MI->getOpcode(), dom);
6621   if (!table) { // try the other table
6622     assert((Subtarget.hasAVX2() || Domain < 3) &&
6623            "256-bit vector operations only available in AVX2");
6624     table = lookupAVX2(MI->getOpcode(), dom);
6625   }
6626   assert(table && "Cannot change domain");
6627   MI->setDesc(get(table[Domain-1]));
6628 }
6629 
6630 /// Return the noop instruction to use for a noop.
6631 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
6632   NopInst.setOpcode(X86::NOOP);
6633 }
6634 
6635 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
6636 // In particular, getJumpInstrTableEntryBound must always return an upper bound
6637 // on the encoding lengths of the instructions generated by
6638 // getUnconditionalBranch and getTrap.
6639 void X86InstrInfo::getUnconditionalBranch(
6640     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
6641   Branch.setOpcode(X86::JMP_1);
6642   Branch.addOperand(MCOperand::createExpr(BranchTarget));
6643 }
6644 
6645 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
6646 // In particular, getJumpInstrTableEntryBound must always return an upper bound
6647 // on the encoding lengths of the instructions generated by
6648 // getUnconditionalBranch and getTrap.
6649 void X86InstrInfo::getTrap(MCInst &MI) const {
6650   MI.setOpcode(X86::TRAP);
6651 }
6652 
6653 // See getTrap and getUnconditionalBranch for conditions on the value returned
6654 // by this function.
6655 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
6656   // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
6657   // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
6658   return 5;
6659 }
6660 
6661 bool X86InstrInfo::isHighLatencyDef(int opc) const {
6662   switch (opc) {
6663   default: return false;
6664   case X86::DIVSDrm:
6665   case X86::DIVSDrm_Int:
6666   case X86::DIVSDrr:
6667   case X86::DIVSDrr_Int:
6668   case X86::DIVSSrm:
6669   case X86::DIVSSrm_Int:
6670   case X86::DIVSSrr:
6671   case X86::DIVSSrr_Int:
6672   case X86::SQRTPDm:
6673   case X86::SQRTPDr:
6674   case X86::SQRTPSm:
6675   case X86::SQRTPSr:
6676   case X86::SQRTSDm:
6677   case X86::SQRTSDm_Int:
6678   case X86::SQRTSDr:
6679   case X86::SQRTSDr_Int:
6680   case X86::SQRTSSm:
6681   case X86::SQRTSSm_Int:
6682   case X86::SQRTSSr:
6683   case X86::SQRTSSr_Int:
6684   // AVX instructions with high latency
6685   case X86::VDIVSDrm:
6686   case X86::VDIVSDrm_Int:
6687   case X86::VDIVSDrr:
6688   case X86::VDIVSDrr_Int:
6689   case X86::VDIVSSrm:
6690   case X86::VDIVSSrm_Int:
6691   case X86::VDIVSSrr:
6692   case X86::VDIVSSrr_Int:
6693   case X86::VSQRTPDm:
6694   case X86::VSQRTPDr:
6695   case X86::VSQRTPSm:
6696   case X86::VSQRTPSr:
6697   case X86::VSQRTSDm:
6698   case X86::VSQRTSDm_Int:
6699   case X86::VSQRTSDr:
6700   case X86::VSQRTSSm:
6701   case X86::VSQRTSSm_Int:
6702   case X86::VSQRTSSr:
6703   case X86::VSQRTPDZm:
6704   case X86::VSQRTPDZr:
6705   case X86::VSQRTPSZm:
6706   case X86::VSQRTPSZr:
6707   case X86::VSQRTSDZm:
6708   case X86::VSQRTSDZm_Int:
6709   case X86::VSQRTSDZr:
6710   case X86::VSQRTSSZm_Int:
6711   case X86::VSQRTSSZr:
6712   case X86::VSQRTSSZm:
6713   case X86::VDIVSDZrm:
6714   case X86::VDIVSDZrr:
6715   case X86::VDIVSSZrm:
6716   case X86::VDIVSSZrr:
6717 
6718   case X86::VGATHERQPSZrm:
6719   case X86::VGATHERQPDZrm:
6720   case X86::VGATHERDPDZrm:
6721   case X86::VGATHERDPSZrm:
6722   case X86::VPGATHERQDZrm:
6723   case X86::VPGATHERQQZrm:
6724   case X86::VPGATHERDDZrm:
6725   case X86::VPGATHERDQZrm:
6726   case X86::VSCATTERQPDZmr:
6727   case X86::VSCATTERQPSZmr:
6728   case X86::VSCATTERDPDZmr:
6729   case X86::VSCATTERDPSZmr:
6730   case X86::VPSCATTERQDZmr:
6731   case X86::VPSCATTERQQZmr:
6732   case X86::VPSCATTERDDZmr:
6733   case X86::VPSCATTERDQZmr:
6734     return true;
6735   }
6736 }
6737 
6738 bool X86InstrInfo::
6739 hasHighOperandLatency(const TargetSchedModel &SchedModel,
6740                       const MachineRegisterInfo *MRI,
6741                       const MachineInstr *DefMI, unsigned DefIdx,
6742                       const MachineInstr *UseMI, unsigned UseIdx) const {
6743   return isHighLatencyDef(DefMI->getOpcode());
6744 }
6745 
6746 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
6747                                            const MachineBasicBlock *MBB) const {
6748   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
6749          "Reassociation needs binary operators");
6750 
6751   // Integer binary math/logic instructions have a third source operand:
6752   // the EFLAGS register. That operand must be both defined here and never
6753   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
6754   // not change anything because rearranging the operands could affect other
6755   // instructions that depend on the exact status flags (zero, sign, etc.)
6756   // that are set by using these particular operands with this operation.
6757   if (Inst.getNumOperands() == 4) {
6758     assert(Inst.getOperand(3).isReg() &&
6759            Inst.getOperand(3).getReg() == X86::EFLAGS &&
6760            "Unexpected operand in reassociable instruction");
6761     if (!Inst.getOperand(3).isDead())
6762       return false;
6763   }
6764 
6765   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
6766 }
6767 
6768 // TODO: There are many more machine instruction opcodes to match:
6769 //       1. Other data types (integer, vectors)
6770 //       2. Other math / logic operations (xor, or)
6771 //       3. Other forms of the same operation (intrinsics and other variants)
6772 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
6773   switch (Inst.getOpcode()) {
6774   case X86::AND8rr:
6775   case X86::AND16rr:
6776   case X86::AND32rr:
6777   case X86::AND64rr:
6778   case X86::OR8rr:
6779   case X86::OR16rr:
6780   case X86::OR32rr:
6781   case X86::OR64rr:
6782   case X86::XOR8rr:
6783   case X86::XOR16rr:
6784   case X86::XOR32rr:
6785   case X86::XOR64rr:
6786   case X86::IMUL16rr:
6787   case X86::IMUL32rr:
6788   case X86::IMUL64rr:
6789   case X86::PANDrr:
6790   case X86::PORrr:
6791   case X86::PXORrr:
6792   case X86::VPANDrr:
6793   case X86::VPANDYrr:
6794   case X86::VPORrr:
6795   case X86::VPORYrr:
6796   case X86::VPXORrr:
6797   case X86::VPXORYrr:
6798   // Normal min/max instructions are not commutative because of NaN and signed
6799   // zero semantics, but these are. Thus, there's no need to check for global
6800   // relaxed math; the instructions themselves have the properties we need.
6801   case X86::MAXCPDrr:
6802   case X86::MAXCPSrr:
6803   case X86::MAXCSDrr:
6804   case X86::MAXCSSrr:
6805   case X86::MINCPDrr:
6806   case X86::MINCPSrr:
6807   case X86::MINCSDrr:
6808   case X86::MINCSSrr:
6809   case X86::VMAXCPDrr:
6810   case X86::VMAXCPSrr:
6811   case X86::VMAXCPDYrr:
6812   case X86::VMAXCPSYrr:
6813   case X86::VMAXCSDrr:
6814   case X86::VMAXCSSrr:
6815   case X86::VMINCPDrr:
6816   case X86::VMINCPSrr:
6817   case X86::VMINCPDYrr:
6818   case X86::VMINCPSYrr:
6819   case X86::VMINCSDrr:
6820   case X86::VMINCSSrr:
6821     return true;
6822   case X86::ADDPDrr:
6823   case X86::ADDPSrr:
6824   case X86::ADDSDrr:
6825   case X86::ADDSSrr:
6826   case X86::MULPDrr:
6827   case X86::MULPSrr:
6828   case X86::MULSDrr:
6829   case X86::MULSSrr:
6830   case X86::VADDPDrr:
6831   case X86::VADDPSrr:
6832   case X86::VADDPDYrr:
6833   case X86::VADDPSYrr:
6834   case X86::VADDSDrr:
6835   case X86::VADDSSrr:
6836   case X86::VMULPDrr:
6837   case X86::VMULPSrr:
6838   case X86::VMULPDYrr:
6839   case X86::VMULPSYrr:
6840   case X86::VMULSDrr:
6841   case X86::VMULSSrr:
6842     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
6843   default:
6844     return false;
6845   }
6846 }
6847 
6848 /// This is an architecture-specific helper function of reassociateOps.
6849 /// Set special operand attributes for new instructions after reassociation.
6850 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
6851                                          MachineInstr &OldMI2,
6852                                          MachineInstr &NewMI1,
6853                                          MachineInstr &NewMI2) const {
6854   // Integer instructions define an implicit EFLAGS source register operand as
6855   // the third source (fourth total) operand.
6856   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
6857     return;
6858 
6859   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
6860          "Unexpected instruction type for reassociation");
6861 
6862   MachineOperand &OldOp1 = OldMI1.getOperand(3);
6863   MachineOperand &OldOp2 = OldMI2.getOperand(3);
6864   MachineOperand &NewOp1 = NewMI1.getOperand(3);
6865   MachineOperand &NewOp2 = NewMI2.getOperand(3);
6866 
6867   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
6868          "Must have dead EFLAGS operand in reassociable instruction");
6869   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
6870          "Must have dead EFLAGS operand in reassociable instruction");
6871 
6872   (void)OldOp1;
6873   (void)OldOp2;
6874 
6875   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
6876          "Unexpected operand in reassociable instruction");
6877   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
6878          "Unexpected operand in reassociable instruction");
6879 
6880   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
6881   // of this pass or other passes. The EFLAGS operands must be dead in these new
6882   // instructions because the EFLAGS operands in the original instructions must
6883   // be dead in order for reassociation to occur.
6884   NewOp1.setIsDead();
6885   NewOp2.setIsDead();
6886 }
6887 
6888 std::pair<unsigned, unsigned>
6889 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
6890   return std::make_pair(TF, 0u);
6891 }
6892 
6893 ArrayRef<std::pair<unsigned, const char *>>
6894 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
6895   using namespace X86II;
6896   static const std::pair<unsigned, const char *> TargetFlags[] = {
6897       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
6898       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
6899       {MO_GOT, "x86-got"},
6900       {MO_GOTOFF, "x86-gotoff"},
6901       {MO_GOTPCREL, "x86-gotpcrel"},
6902       {MO_PLT, "x86-plt"},
6903       {MO_TLSGD, "x86-tlsgd"},
6904       {MO_TLSLD, "x86-tlsld"},
6905       {MO_TLSLDM, "x86-tlsldm"},
6906       {MO_GOTTPOFF, "x86-gottpoff"},
6907       {MO_INDNTPOFF, "x86-indntpoff"},
6908       {MO_TPOFF, "x86-tpoff"},
6909       {MO_DTPOFF, "x86-dtpoff"},
6910       {MO_NTPOFF, "x86-ntpoff"},
6911       {MO_GOTNTPOFF, "x86-gotntpoff"},
6912       {MO_DLLIMPORT, "x86-dllimport"},
6913       {MO_DARWIN_STUB, "x86-darwin-stub"},
6914       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
6915       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
6916       {MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, "x86-darwin-hidden-nonlazy-pic-base"},
6917       {MO_TLVP, "x86-tlvp"},
6918       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
6919       {MO_SECREL, "x86-secrel"}};
6920   return makeArrayRef(TargetFlags);
6921 }
6922 
6923 namespace {
6924   /// Create Global Base Reg pass. This initializes the PIC
6925   /// global base register for x86-32.
6926   struct CGBR : public MachineFunctionPass {
6927     static char ID;
6928     CGBR() : MachineFunctionPass(ID) {}
6929 
6930     bool runOnMachineFunction(MachineFunction &MF) override {
6931       const X86TargetMachine *TM =
6932         static_cast<const X86TargetMachine *>(&MF.getTarget());
6933       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
6934 
6935       // Don't do anything if this is 64-bit as 64-bit PIC
6936       // uses RIP relative addressing.
6937       if (STI.is64Bit())
6938         return false;
6939 
6940       // Only emit a global base reg in PIC mode.
6941       if (TM->getRelocationModel() != Reloc::PIC_)
6942         return false;
6943 
6944       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
6945       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6946 
6947       // If we didn't need a GlobalBaseReg, don't insert code.
6948       if (GlobalBaseReg == 0)
6949         return false;
6950 
6951       // Insert the set of GlobalBaseReg into the first MBB of the function
6952       MachineBasicBlock &FirstMBB = MF.front();
6953       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
6954       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
6955       MachineRegisterInfo &RegInfo = MF.getRegInfo();
6956       const X86InstrInfo *TII = STI.getInstrInfo();
6957 
6958       unsigned PC;
6959       if (STI.isPICStyleGOT())
6960         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
6961       else
6962         PC = GlobalBaseReg;
6963 
6964       // Operand of MovePCtoStack is completely ignored by asm printer. It's
6965       // only used in JIT code emission as displacement to pc.
6966       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
6967 
6968       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
6969       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
6970       if (STI.isPICStyleGOT()) {
6971         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
6972         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
6973           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
6974                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
6975       }
6976 
6977       return true;
6978     }
6979 
6980     const char *getPassName() const override {
6981       return "X86 PIC Global Base Reg Initialization";
6982     }
6983 
6984     void getAnalysisUsage(AnalysisUsage &AU) const override {
6985       AU.setPreservesCFG();
6986       MachineFunctionPass::getAnalysisUsage(AU);
6987     }
6988   };
6989 }
6990 
6991 char CGBR::ID = 0;
6992 FunctionPass*
6993 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
6994 
6995 namespace {
6996   struct LDTLSCleanup : public MachineFunctionPass {
6997     static char ID;
6998     LDTLSCleanup() : MachineFunctionPass(ID) {}
6999 
7000     bool runOnMachineFunction(MachineFunction &MF) override {
7001       X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
7002       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7003         // No point folding accesses if there isn't at least two.
7004         return false;
7005       }
7006 
7007       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7008       return VisitNode(DT->getRootNode(), 0);
7009     }
7010 
7011     // Visit the dominator subtree rooted at Node in pre-order.
7012     // If TLSBaseAddrReg is non-null, then use that to replace any
7013     // TLS_base_addr instructions. Otherwise, create the register
7014     // when the first such instruction is seen, and then use it
7015     // as we encounter more instructions.
7016     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7017       MachineBasicBlock *BB = Node->getBlock();
7018       bool Changed = false;
7019 
7020       // Traverse the current block.
7021       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7022            ++I) {
7023         switch (I->getOpcode()) {
7024           case X86::TLS_base_addr32:
7025           case X86::TLS_base_addr64:
7026             if (TLSBaseAddrReg)
7027               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
7028             else
7029               I = SetRegister(I, &TLSBaseAddrReg);
7030             Changed = true;
7031             break;
7032           default:
7033             break;
7034         }
7035       }
7036 
7037       // Visit the children of this block in the dominator tree.
7038       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7039            I != E; ++I) {
7040         Changed |= VisitNode(*I, TLSBaseAddrReg);
7041       }
7042 
7043       return Changed;
7044     }
7045 
7046     // Replace the TLS_base_addr instruction I with a copy from
7047     // TLSBaseAddrReg, returning the new instruction.
7048     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
7049                                          unsigned TLSBaseAddrReg) {
7050       MachineFunction *MF = I->getParent()->getParent();
7051       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7052       const bool is64Bit = STI.is64Bit();
7053       const X86InstrInfo *TII = STI.getInstrInfo();
7054 
7055       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7056       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
7057                                    TII->get(TargetOpcode::COPY),
7058                                    is64Bit ? X86::RAX : X86::EAX)
7059                                    .addReg(TLSBaseAddrReg);
7060 
7061       // Erase the TLS_base_addr instruction.
7062       I->eraseFromParent();
7063 
7064       return Copy;
7065     }
7066 
7067     // Create a virtal register in *TLSBaseAddrReg, and populate it by
7068     // inserting a copy instruction after I. Returns the new instruction.
7069     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
7070       MachineFunction *MF = I->getParent()->getParent();
7071       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7072       const bool is64Bit = STI.is64Bit();
7073       const X86InstrInfo *TII = STI.getInstrInfo();
7074 
7075       // Create a virtual register for the TLS base address.
7076       MachineRegisterInfo &RegInfo = MF->getRegInfo();
7077       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7078                                                       ? &X86::GR64RegClass
7079                                                       : &X86::GR32RegClass);
7080 
7081       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7082       MachineInstr *Next = I->getNextNode();
7083       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
7084                                    TII->get(TargetOpcode::COPY),
7085                                    *TLSBaseAddrReg)
7086                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
7087 
7088       return Copy;
7089     }
7090 
7091     const char *getPassName() const override {
7092       return "Local Dynamic TLS Access Clean-up";
7093     }
7094 
7095     void getAnalysisUsage(AnalysisUsage &AU) const override {
7096       AU.setPreservesCFG();
7097       AU.addRequired<MachineDominatorTree>();
7098       MachineFunctionPass::getAnalysisUsage(AU);
7099     }
7100   };
7101 }
7102 
7103 char LDTLSCleanup::ID = 0;
7104 FunctionPass*
7105 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
7106