1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "x86-instr-info"
45 
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
48 
49 static cl::opt<bool>
50 NoFusing("disable-spill-fusing",
51          cl::desc("Disable fusing of spill code into instructions"));
52 static cl::opt<bool>
53 PrintFailedFusing("print-failed-fuse-candidates",
54                   cl::desc("Print instructions that the allocator wants to"
55                            " fuse, but the X86 backend currently can't"),
56                   cl::Hidden);
57 static cl::opt<bool>
58 ReMatPICStubLoad("remat-pic-stub-load",
59                  cl::desc("Re-materialize load from stub in PIC mode"),
60                  cl::init(false), cl::Hidden);
61 static cl::opt<unsigned>
62 PartialRegUpdateClearance("partial-reg-update-clearance",
63                           cl::desc("Clearance between two register writes "
64                                    "for inserting XOR to avoid partial "
65                                    "register update"),
66                           cl::init(64), cl::Hidden);
67 static cl::opt<unsigned>
68 UndefRegClearance("undef-reg-clearance",
69                   cl::desc("How many idle instructions we would like before "
70                            "certain undef register reads"),
71                   cl::init(128), cl::Hidden);
72 
73 enum {
74   // Select which memory operand is being unfolded.
75   // (stored in bits 0 - 3)
76   TB_INDEX_0    = 0,
77   TB_INDEX_1    = 1,
78   TB_INDEX_2    = 2,
79   TB_INDEX_3    = 3,
80   TB_INDEX_4    = 4,
81   TB_INDEX_MASK = 0xf,
82 
83   // Do not insert the reverse map (MemOp -> RegOp) into the table.
84   // This may be needed because there is a many -> one mapping.
85   TB_NO_REVERSE   = 1 << 4,
86 
87   // Do not insert the forward map (RegOp -> MemOp) into the table.
88   // This is needed for Native Client, which prohibits branch
89   // instructions from using a memory operand.
90   TB_NO_FORWARD   = 1 << 5,
91 
92   TB_FOLDED_LOAD  = 1 << 6,
93   TB_FOLDED_STORE = 1 << 7,
94 
95   // Minimum alignment required for load/store.
96   // Used for RegOp->MemOp conversion.
97   // (stored in bits 8 - 15)
98   TB_ALIGN_SHIFT = 8,
99   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
100   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
101   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
102   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
103   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
104 };
105 
106 struct X86MemoryFoldTableEntry {
107   uint16_t RegOp;
108   uint16_t MemOp;
109   uint16_t Flags;
110 };
111 
112 // Pin the vtable to this file.
113 void X86InstrInfo::anchor() {}
114 
115 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
116     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117                                                : X86::ADJCALLSTACKDOWN32),
118                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119                                                : X86::ADJCALLSTACKUP32),
120                       X86::CATCHRET,
121                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
122       Subtarget(STI), RI(STI.getTargetTriple()) {
123 
124   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
125     { X86::ADC32ri,     X86::ADC32mi,    0 },
126     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
127     { X86::ADC32rr,     X86::ADC32mr,    0 },
128     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
129     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
130     { X86::ADC64rr,     X86::ADC64mr,    0 },
131     { X86::ADD16ri,     X86::ADD16mi,    0 },
132     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
133     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
134     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
135     { X86::ADD16rr,     X86::ADD16mr,    0 },
136     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
137     { X86::ADD32ri,     X86::ADD32mi,    0 },
138     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
139     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
140     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
141     { X86::ADD32rr,     X86::ADD32mr,    0 },
142     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
143     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
144     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
145     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
146     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
147     { X86::ADD64rr,     X86::ADD64mr,    0 },
148     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
149     { X86::ADD8ri,      X86::ADD8mi,     0 },
150     { X86::ADD8rr,      X86::ADD8mr,     0 },
151     { X86::AND16ri,     X86::AND16mi,    0 },
152     { X86::AND16ri8,    X86::AND16mi8,   0 },
153     { X86::AND16rr,     X86::AND16mr,    0 },
154     { X86::AND32ri,     X86::AND32mi,    0 },
155     { X86::AND32ri8,    X86::AND32mi8,   0 },
156     { X86::AND32rr,     X86::AND32mr,    0 },
157     { X86::AND64ri32,   X86::AND64mi32,  0 },
158     { X86::AND64ri8,    X86::AND64mi8,   0 },
159     { X86::AND64rr,     X86::AND64mr,    0 },
160     { X86::AND8ri,      X86::AND8mi,     0 },
161     { X86::AND8rr,      X86::AND8mr,     0 },
162     { X86::DEC16r,      X86::DEC16m,     0 },
163     { X86::DEC32r,      X86::DEC32m,     0 },
164     { X86::DEC64r,      X86::DEC64m,     0 },
165     { X86::DEC8r,       X86::DEC8m,      0 },
166     { X86::INC16r,      X86::INC16m,     0 },
167     { X86::INC32r,      X86::INC32m,     0 },
168     { X86::INC64r,      X86::INC64m,     0 },
169     { X86::INC8r,       X86::INC8m,      0 },
170     { X86::NEG16r,      X86::NEG16m,     0 },
171     { X86::NEG32r,      X86::NEG32m,     0 },
172     { X86::NEG64r,      X86::NEG64m,     0 },
173     { X86::NEG8r,       X86::NEG8m,      0 },
174     { X86::NOT16r,      X86::NOT16m,     0 },
175     { X86::NOT32r,      X86::NOT32m,     0 },
176     { X86::NOT64r,      X86::NOT64m,     0 },
177     { X86::NOT8r,       X86::NOT8m,      0 },
178     { X86::OR16ri,      X86::OR16mi,     0 },
179     { X86::OR16ri8,     X86::OR16mi8,    0 },
180     { X86::OR16rr,      X86::OR16mr,     0 },
181     { X86::OR32ri,      X86::OR32mi,     0 },
182     { X86::OR32ri8,     X86::OR32mi8,    0 },
183     { X86::OR32rr,      X86::OR32mr,     0 },
184     { X86::OR64ri32,    X86::OR64mi32,   0 },
185     { X86::OR64ri8,     X86::OR64mi8,    0 },
186     { X86::OR64rr,      X86::OR64mr,     0 },
187     { X86::OR8ri,       X86::OR8mi,      0 },
188     { X86::OR8rr,       X86::OR8mr,      0 },
189     { X86::ROL16r1,     X86::ROL16m1,    0 },
190     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
191     { X86::ROL16ri,     X86::ROL16mi,    0 },
192     { X86::ROL32r1,     X86::ROL32m1,    0 },
193     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
194     { X86::ROL32ri,     X86::ROL32mi,    0 },
195     { X86::ROL64r1,     X86::ROL64m1,    0 },
196     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
197     { X86::ROL64ri,     X86::ROL64mi,    0 },
198     { X86::ROL8r1,      X86::ROL8m1,     0 },
199     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
200     { X86::ROL8ri,      X86::ROL8mi,     0 },
201     { X86::ROR16r1,     X86::ROR16m1,    0 },
202     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
203     { X86::ROR16ri,     X86::ROR16mi,    0 },
204     { X86::ROR32r1,     X86::ROR32m1,    0 },
205     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
206     { X86::ROR32ri,     X86::ROR32mi,    0 },
207     { X86::ROR64r1,     X86::ROR64m1,    0 },
208     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
209     { X86::ROR64ri,     X86::ROR64mi,    0 },
210     { X86::ROR8r1,      X86::ROR8m1,     0 },
211     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
212     { X86::ROR8ri,      X86::ROR8mi,     0 },
213     { X86::SAR16r1,     X86::SAR16m1,    0 },
214     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
215     { X86::SAR16ri,     X86::SAR16mi,    0 },
216     { X86::SAR32r1,     X86::SAR32m1,    0 },
217     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
218     { X86::SAR32ri,     X86::SAR32mi,    0 },
219     { X86::SAR64r1,     X86::SAR64m1,    0 },
220     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
221     { X86::SAR64ri,     X86::SAR64mi,    0 },
222     { X86::SAR8r1,      X86::SAR8m1,     0 },
223     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
224     { X86::SAR8ri,      X86::SAR8mi,     0 },
225     { X86::SBB32ri,     X86::SBB32mi,    0 },
226     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
227     { X86::SBB32rr,     X86::SBB32mr,    0 },
228     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
229     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
230     { X86::SBB64rr,     X86::SBB64mr,    0 },
231     { X86::SHL16r1,     X86::SHL16m1,    0 },
232     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
233     { X86::SHL16ri,     X86::SHL16mi,    0 },
234     { X86::SHL32r1,     X86::SHL32m1,    0 },
235     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
236     { X86::SHL32ri,     X86::SHL32mi,    0 },
237     { X86::SHL64r1,     X86::SHL64m1,    0 },
238     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
239     { X86::SHL64ri,     X86::SHL64mi,    0 },
240     { X86::SHL8r1,      X86::SHL8m1,     0 },
241     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
242     { X86::SHL8ri,      X86::SHL8mi,     0 },
243     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
244     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
245     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
246     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
247     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
248     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
249     { X86::SHR16r1,     X86::SHR16m1,    0 },
250     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
251     { X86::SHR16ri,     X86::SHR16mi,    0 },
252     { X86::SHR32r1,     X86::SHR32m1,    0 },
253     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
254     { X86::SHR32ri,     X86::SHR32mi,    0 },
255     { X86::SHR64r1,     X86::SHR64m1,    0 },
256     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
257     { X86::SHR64ri,     X86::SHR64mi,    0 },
258     { X86::SHR8r1,      X86::SHR8m1,     0 },
259     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
260     { X86::SHR8ri,      X86::SHR8mi,     0 },
261     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
262     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
263     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
264     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
265     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
266     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
267     { X86::SUB16ri,     X86::SUB16mi,    0 },
268     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
269     { X86::SUB16rr,     X86::SUB16mr,    0 },
270     { X86::SUB32ri,     X86::SUB32mi,    0 },
271     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
272     { X86::SUB32rr,     X86::SUB32mr,    0 },
273     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
274     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
275     { X86::SUB64rr,     X86::SUB64mr,    0 },
276     { X86::SUB8ri,      X86::SUB8mi,     0 },
277     { X86::SUB8rr,      X86::SUB8mr,     0 },
278     { X86::XOR16ri,     X86::XOR16mi,    0 },
279     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
280     { X86::XOR16rr,     X86::XOR16mr,    0 },
281     { X86::XOR32ri,     X86::XOR32mi,    0 },
282     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
283     { X86::XOR32rr,     X86::XOR32mr,    0 },
284     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
285     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
286     { X86::XOR64rr,     X86::XOR64mr,    0 },
287     { X86::XOR8ri,      X86::XOR8mi,     0 },
288     { X86::XOR8rr,      X86::XOR8mr,     0 }
289   };
290 
291   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
292     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
293                   Entry.RegOp, Entry.MemOp,
294                   // Index 0, folded load and store, no alignment requirement.
295                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
296   }
297 
298   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
299     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
300     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
301     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
302     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
303     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
304     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
305     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
306     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
307     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
308     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
309     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
310     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
311     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
312     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
313     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
314     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
315     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
316     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
317     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
318     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
319     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
320     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
321     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
322     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
323     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
324     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
325     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
326     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
327     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
328     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
329     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
330     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
331     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
332     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
333     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
334     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
335     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
336     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
337     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
338     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
339     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
340     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
341     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
342     { X86::MOVDQUrr,    X86::MOVDQUmr,      TB_FOLDED_STORE },
343     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
344     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
345     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
346     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
347     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
348     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
349     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
350     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
351     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
352     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
353     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
354     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
355     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
356     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
357     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
358     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
359     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
360     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
361     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
362     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
363     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
364     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
365     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
366     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
367     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
368     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
369     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
370     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
371     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
372     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
373     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
374     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
375     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
376     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
377     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
378     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
379     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
380     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
381 
382     // AVX 128-bit versions of foldable instructions
383     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
384     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
385     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
386     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
387     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
388     { X86::VMOVDQUrr,   X86::VMOVDQUmr,     TB_FOLDED_STORE },
389     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
390     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
391     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
392     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
393     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
394     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
395     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
396     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
397 
398     // AVX 256-bit foldable instructions
399     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
400     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
401     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
402     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
403     { X86::VMOVDQUYrr,  X86::VMOVDQUYmr,    TB_FOLDED_STORE },
404     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
405     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
406 
407     // AVX-512 foldable instructions
408     { X86::VEXTRACTF32x4Zrr,X86::VEXTRACTF32x4Zmr, TB_FOLDED_STORE },
409     { X86::VEXTRACTF32x8Zrr,X86::VEXTRACTF32x8Zmr, TB_FOLDED_STORE },
410     { X86::VEXTRACTF64x2Zrr,X86::VEXTRACTF64x2Zmr, TB_FOLDED_STORE },
411     { X86::VEXTRACTF64x4Zrr,X86::VEXTRACTF64x4Zmr, TB_FOLDED_STORE },
412     { X86::VEXTRACTI32x4Zrr,X86::VEXTRACTI32x4Zmr, TB_FOLDED_STORE },
413     { X86::VEXTRACTI32x8Zrr,X86::VEXTRACTI32x8Zmr, TB_FOLDED_STORE },
414     { X86::VEXTRACTI64x2Zrr,X86::VEXTRACTI64x2Zmr, TB_FOLDED_STORE },
415     { X86::VEXTRACTI64x4Zrr,X86::VEXTRACTI64x4Zmr, TB_FOLDED_STORE },
416     { X86::VEXTRACTPSZrr,   X86::VEXTRACTPSZmr,    TB_FOLDED_STORE },
417     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
418     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
419     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
420     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
421     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
422     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
423     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
424     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
425     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
426     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
427     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
428     { X86::VPMOVDBZrr,      X86::VPMOVDBZmr,    TB_FOLDED_STORE },
429     { X86::VPMOVDWZrr,      X86::VPMOVDWZmr,    TB_FOLDED_STORE },
430     { X86::VPMOVQDZrr,      X86::VPMOVQDZmr,    TB_FOLDED_STORE },
431     { X86::VPMOVQWZrr,      X86::VPMOVQWZmr,    TB_FOLDED_STORE },
432     { X86::VPMOVWBZrr,      X86::VPMOVWBZmr,    TB_FOLDED_STORE },
433     { X86::VPMOVSDBZrr,     X86::VPMOVSDBZmr,   TB_FOLDED_STORE },
434     { X86::VPMOVSDWZrr,     X86::VPMOVSDWZmr,   TB_FOLDED_STORE },
435     { X86::VPMOVSQDZrr,     X86::VPMOVSQDZmr,   TB_FOLDED_STORE },
436     { X86::VPMOVSQWZrr,     X86::VPMOVSQWZmr,   TB_FOLDED_STORE },
437     { X86::VPMOVSWBZrr,     X86::VPMOVSWBZmr,   TB_FOLDED_STORE },
438     { X86::VPMOVUSDBZrr,    X86::VPMOVUSDBZmr,  TB_FOLDED_STORE },
439     { X86::VPMOVUSDWZrr,    X86::VPMOVUSDWZmr,  TB_FOLDED_STORE },
440     { X86::VPMOVUSQDZrr,    X86::VPMOVUSQDZmr,  TB_FOLDED_STORE },
441     { X86::VPMOVUSQWZrr,    X86::VPMOVUSQWZmr,  TB_FOLDED_STORE },
442     { X86::VPMOVUSWBZrr,    X86::VPMOVUSWBZmr,  TB_FOLDED_STORE },
443 
444     // AVX-512 foldable instructions (256-bit versions)
445     { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256mr, TB_FOLDED_STORE },
446     { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256mr, TB_FOLDED_STORE },
447     { X86::VEXTRACTI32x4Z256rr,X86::VEXTRACTI32x4Z256mr, TB_FOLDED_STORE },
448     { X86::VEXTRACTI64x2Z256rr,X86::VEXTRACTI64x2Z256mr, TB_FOLDED_STORE },
449     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
450     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
451     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
452     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
453     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
454     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
455     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
456     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
457     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
458     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
459     { X86::VPMOVDWZ256rr,      X86::VPMOVDWZ256mr,    TB_FOLDED_STORE },
460     { X86::VPMOVQDZ256rr,      X86::VPMOVQDZ256mr,    TB_FOLDED_STORE },
461     { X86::VPMOVWBZ256rr,      X86::VPMOVWBZ256mr,    TB_FOLDED_STORE },
462     { X86::VPMOVSDWZ256rr,     X86::VPMOVSDWZ256mr,   TB_FOLDED_STORE },
463     { X86::VPMOVSQDZ256rr,     X86::VPMOVSQDZ256mr,   TB_FOLDED_STORE },
464     { X86::VPMOVSWBZ256rr,     X86::VPMOVSWBZ256mr,   TB_FOLDED_STORE },
465     { X86::VPMOVUSDWZ256rr,    X86::VPMOVUSDWZ256mr,  TB_FOLDED_STORE },
466     { X86::VPMOVUSQDZ256rr,    X86::VPMOVUSQDZ256mr,  TB_FOLDED_STORE },
467     { X86::VPMOVUSWBZ256rr,    X86::VPMOVUSWBZ256mr,  TB_FOLDED_STORE },
468 
469     // AVX-512 foldable instructions (128-bit versions)
470     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
471     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
472     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
473     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
474     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
475     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
476     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
477     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
478     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
479     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
480 
481     // F16C foldable instructions
482     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
483     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
484   };
485 
486   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
487     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
488                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
489   }
490 
491   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
492     { X86::BSF16rr,         X86::BSF16rm,             0 },
493     { X86::BSF32rr,         X86::BSF32rm,             0 },
494     { X86::BSF64rr,         X86::BSF64rm,             0 },
495     { X86::BSR16rr,         X86::BSR16rm,             0 },
496     { X86::BSR32rr,         X86::BSR32rm,             0 },
497     { X86::BSR64rr,         X86::BSR64rm,             0 },
498     { X86::CMP16rr,         X86::CMP16rm,             0 },
499     { X86::CMP32rr,         X86::CMP32rm,             0 },
500     { X86::CMP64rr,         X86::CMP64rm,             0 },
501     { X86::CMP8rr,          X86::CMP8rm,              0 },
502     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
503     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
504     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
505     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
506     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
507     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
508     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
509     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
510     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
511     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
512     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
513     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
514     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
515     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
516     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
517     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
518     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        TB_NO_REVERSE },
519     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        TB_NO_REVERSE },
520     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        TB_NO_REVERSE },
521     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          TB_NO_REVERSE },
522     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        TB_NO_REVERSE },
523     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          TB_NO_REVERSE },
524     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_NO_REVERSE },
525     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
526     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
527     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
528     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
529     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_NO_REVERSE },
530     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
531     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
532     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  TB_NO_REVERSE },
533     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     TB_NO_REVERSE },
534     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  TB_NO_REVERSE },
535     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     TB_NO_REVERSE },
536     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       TB_NO_REVERSE },
537     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       TB_NO_REVERSE },
538     { X86::MOV16rr,         X86::MOV16rm,             0 },
539     { X86::MOV32rr,         X86::MOV32rm,             0 },
540     { X86::MOV64rr,         X86::MOV64rm,             0 },
541     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
542     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
543     { X86::MOV8rr,          X86::MOV8rm,              0 },
544     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
545     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
546     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
547     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
548     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
549     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
550     { X86::MOVDQUrr,        X86::MOVDQUrm,            0 },
551     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
552     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
553     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
554     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
555     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
556     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
557     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
558     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
559     { X86::MOVUPDrr,        X86::MOVUPDrm,            0 },
560     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
561     { X86::MOVZPQILo2PQIrr, X86::MOVQI2PQIrm,         TB_NO_REVERSE },
562     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
563     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
564     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
565     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
566     { X86::PABSBrr,         X86::PABSBrm,             TB_ALIGN_16 },
567     { X86::PABSDrr,         X86::PABSDrm,             TB_ALIGN_16 },
568     { X86::PABSWrr,         X86::PABSWrm,             TB_ALIGN_16 },
569     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
570     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
571     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
572     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
573     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
574     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_NO_REVERSE },
575     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_NO_REVERSE },
576     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_NO_REVERSE },
577     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_NO_REVERSE },
578     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_NO_REVERSE },
579     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_NO_REVERSE },
580     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_NO_REVERSE },
581     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_NO_REVERSE },
582     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_NO_REVERSE },
583     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_NO_REVERSE },
584     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_NO_REVERSE },
585     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_NO_REVERSE },
586     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
587     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
588     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
589     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
590     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
591     { X86::RCPSSr,          X86::RCPSSm,              0 },
592     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          TB_NO_REVERSE },
593     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
594     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
595     { X86::ROUNDSDr,        X86::ROUNDSDm,            0 },
596     { X86::ROUNDSSr,        X86::ROUNDSSm,            0 },
597     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
598     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
599     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        TB_NO_REVERSE },
600     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
601     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
602     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
603     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         TB_NO_REVERSE },
604     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
605     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         TB_NO_REVERSE },
606     { X86::TEST16rr,        X86::TEST16rm,            0 },
607     { X86::TEST32rr,        X86::TEST32rm,            0 },
608     { X86::TEST64rr,        X86::TEST64rm,            0 },
609     { X86::TEST8rr,         X86::TEST8rm,             0 },
610     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
611     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
612     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
613 
614     // MMX version of foldable instructions
615     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
616     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
617     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
618     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
619     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
620     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
621     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
622     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
623     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
624     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
625 
626     // 3DNow! version of foldable instructions
627     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
628     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
629     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
630     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
631     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
632     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
633     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
634 
635     // AVX 128-bit versions of foldable instructions
636     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       TB_NO_REVERSE },
637     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       TB_NO_REVERSE },
638     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      TB_NO_REVERSE },
639     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      TB_NO_REVERSE },
640     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
641     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,TB_NO_REVERSE },
642     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
643     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    TB_NO_REVERSE },
644     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
645     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,TB_NO_REVERSE },
646     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
647     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    TB_NO_REVERSE },
648     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       TB_NO_REVERSE },
649     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         TB_NO_REVERSE },
650     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       TB_NO_REVERSE },
651     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         TB_NO_REVERSE },
652     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         TB_NO_REVERSE },
653     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
654     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQrm,         0 },
655     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSrm,         0 },
656     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
657     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         TB_NO_REVERSE },
658     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQrm,        0 },
659     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
660     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
661     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
662     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
663     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
664     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
665     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
666     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
667     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
668     { X86::VMOVDQUrr,       X86::VMOVDQUrm,           0 },
669     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
670     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
671     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
672     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
673     { X86::VMOVZPQILo2PQIrr,X86::VMOVQI2PQIrm,        TB_NO_REVERSE },
674     { X86::VPABSBrr,        X86::VPABSBrm,            0 },
675     { X86::VPABSDrr,        X86::VPABSDrm,            0 },
676     { X86::VPABSWrr,        X86::VPABSWrm,            0 },
677     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
678     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
679     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
680     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
681     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
682     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
683     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
684     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         TB_NO_REVERSE },
685     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         TB_NO_REVERSE },
686     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         TB_NO_REVERSE },
687     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         TB_NO_REVERSE },
688     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         TB_NO_REVERSE },
689     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         TB_NO_REVERSE },
690     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         TB_NO_REVERSE },
691     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         TB_NO_REVERSE },
692     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         TB_NO_REVERSE },
693     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         TB_NO_REVERSE },
694     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         TB_NO_REVERSE },
695     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         TB_NO_REVERSE },
696     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
697     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
698     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
699     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
700     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
701     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
702     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
703     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
704     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
705     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
706     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
707     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
708     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
709     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
710 
711     // AVX 256-bit foldable instructions
712     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        TB_NO_REVERSE },
713     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
714     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
715     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
716     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
717     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        TB_NO_REVERSE },
718     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
719     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
720     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
721     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
722     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
723     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
724     { X86::VMOVDQUYrr,      X86::VMOVDQUYrm,          0 },
725     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
726     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
727     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
728     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
729     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
730     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
731     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
732     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
733     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
734     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
735     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
736     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
737     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
738     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
739     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
740 
741     // AVX2 foldable instructions
742 
743     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
744     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
745     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
746     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
747     // so they don't need an equivalent limitation.
748     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
749     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
750     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
751     { X86::VPABSBYrr,       X86::VPABSBYrm,           0 },
752     { X86::VPABSDYrr,       X86::VPABSDYrm,           0 },
753     { X86::VPABSWYrr,       X86::VPABSWYrm,           0 },
754     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      TB_NO_REVERSE },
755     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     TB_NO_REVERSE },
756     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      TB_NO_REVERSE },
757     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     TB_NO_REVERSE },
758     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      TB_NO_REVERSE },
759     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     TB_NO_REVERSE },
760     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      TB_NO_REVERSE },
761     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     TB_NO_REVERSE },
762     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
763     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
764     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        TB_NO_REVERSE },
765     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        TB_NO_REVERSE },
766     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
767     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
768     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
769     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        TB_NO_REVERSE },
770     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        TB_NO_REVERSE },
771     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        TB_NO_REVERSE },
772     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
773     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
774     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
775     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        TB_NO_REVERSE },
776     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
777     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
778     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
779 
780     // XOP foldable instructions
781     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
782     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
783     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
784     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
785     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
786     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
787     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
788     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
789     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
790     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
791     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
792     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
793     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
794     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
795     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
796     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
797     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
798     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
799     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
800     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
801     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
802     { X86::VPROTBri,           X86::VPROTBmi,         0 },
803     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
804     { X86::VPROTDri,           X86::VPROTDmi,         0 },
805     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
806     { X86::VPROTQri,           X86::VPROTQmi,         0 },
807     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
808     { X86::VPROTWri,           X86::VPROTWmi,         0 },
809     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
810     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
811     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
812     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
813     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
814     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
815     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
816     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
817     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
818 
819     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
820     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
821     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
822     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
823     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
824     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
825     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
826     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
827     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
828     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
829     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
830     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
831     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
832     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
833     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
834     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
835     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
836     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
837     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
838     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
839     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
840     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
841     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
842     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
843     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
844     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
845     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
846     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
847     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
848     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
849     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
850     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
851     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
852     { X86::RORX32ri,        X86::RORX32mi,            0 },
853     { X86::RORX64ri,        X86::RORX64mi,            0 },
854     { X86::SARX32rr,        X86::SARX32rm,            0 },
855     { X86::SARX64rr,        X86::SARX64rm,            0 },
856     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
857     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
858     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
859     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
860     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
861     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
862     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
863     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
864     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
865     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
866     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
867 
868     // AVX-512 foldable instructions
869     { X86::VBROADCASTSSZr,   X86::VBROADCASTSSZm,     TB_NO_REVERSE },
870     { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm,     TB_NO_REVERSE },
871     { X86::VBROADCASTSDZr,   X86::VBROADCASTSDZm,     TB_NO_REVERSE },
872     { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm,     TB_NO_REVERSE },
873     { X86::VMOV64toPQIZrr,   X86::VMOVQI2PQIZrm,      0 },
874     { X86::VMOVZPQILo2PQIZrr,X86::VMOVQI2PQIZrm,      TB_NO_REVERSE },
875     { X86::VMOVDI2SSZrr,     X86::VMOVDI2SSZrm,       0 },
876     { X86::VMOVAPDZrr,       X86::VMOVAPDZrm,         TB_ALIGN_64 },
877     { X86::VMOVAPSZrr,       X86::VMOVAPSZrm,         TB_ALIGN_64 },
878     { X86::VMOVDQA32Zrr,     X86::VMOVDQA32Zrm,       TB_ALIGN_64 },
879     { X86::VMOVDQA64Zrr,     X86::VMOVDQA64Zrm,       TB_ALIGN_64 },
880     { X86::VMOVDQU8Zrr,      X86::VMOVDQU8Zrm,        0 },
881     { X86::VMOVDQU16Zrr,     X86::VMOVDQU16Zrm,       0 },
882     { X86::VMOVDQU32Zrr,     X86::VMOVDQU32Zrm,       0 },
883     { X86::VMOVDQU64Zrr,     X86::VMOVDQU64Zrm,       0 },
884     { X86::VMOVUPDZrr,       X86::VMOVUPDZrm,         0 },
885     { X86::VMOVUPSZrr,       X86::VMOVUPSZrm,         0 },
886     { X86::VPABSDZrr,        X86::VPABSDZrm,          0 },
887     { X86::VPABSQZrr,        X86::VPABSQZrm,          0 },
888     { X86::VPERMPDZri,       X86::VPERMPDZmi,         0 },
889     { X86::VPERMQZri,        X86::VPERMQZmi,          0 },
890     { X86::VPMOVSXBDZrr,     X86::VPMOVSXBDZrm,       0 },
891     { X86::VPMOVSXBQZrr,     X86::VPMOVSXBQZrm,       TB_NO_REVERSE },
892     { X86::VPMOVSXBWZrr,     X86::VPMOVSXBWZrm,       0 },
893     { X86::VPMOVSXDQZrr,     X86::VPMOVSXDQZrm,       0 },
894     { X86::VPMOVSXWDZrr,     X86::VPMOVSXWDZrm,       0 },
895     { X86::VPMOVSXWQZrr,     X86::VPMOVSXWQZrm,       0 },
896     { X86::VPMOVZXBDZrr,     X86::VPMOVZXBDZrm,       0 },
897     { X86::VPMOVZXBQZrr,     X86::VPMOVZXBQZrm,       TB_NO_REVERSE },
898     { X86::VPMOVZXBWZrr,     X86::VPMOVZXBWZrm,       0 },
899     { X86::VPMOVZXDQZrr,     X86::VPMOVZXDQZrm,       0 },
900     { X86::VPMOVZXWDZrr,     X86::VPMOVZXWDZrm,       0 },
901     { X86::VPMOVZXWQZrr,     X86::VPMOVZXWQZrm,       0 },
902     { X86::VPSHUFDZri,       X86::VPSHUFDZmi,         0 },
903     { X86::VPSHUFHWZri,      X86::VPSHUFHWZmi,        0 },
904     { X86::VPSHUFLWZri,      X86::VPSHUFLWZmi,        0 },
905 
906     // AVX-512 foldable instructions (256-bit versions)
907     { X86::VBROADCASTSSZ256r,    X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
908     { X86::VBROADCASTSSZ256r_s,  X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
909     { X86::VBROADCASTSDZ256r,    X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
910     { X86::VBROADCASTSDZ256r_s,  X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
911     { X86::VMOVAPDZ256rr,        X86::VMOVAPDZ256rm,        TB_ALIGN_32 },
912     { X86::VMOVAPSZ256rr,        X86::VMOVAPSZ256rm,        TB_ALIGN_32 },
913     { X86::VMOVDQA32Z256rr,      X86::VMOVDQA32Z256rm,      TB_ALIGN_32 },
914     { X86::VMOVDQA64Z256rr,      X86::VMOVDQA64Z256rm,      TB_ALIGN_32 },
915     { X86::VMOVDQU8Z256rr,       X86::VMOVDQU8Z256rm,       0 },
916     { X86::VMOVDQU16Z256rr,      X86::VMOVDQU16Z256rm,      0 },
917     { X86::VMOVDQU32Z256rr,      X86::VMOVDQU32Z256rm,      0 },
918     { X86::VMOVDQU64Z256rr,      X86::VMOVDQU64Z256rm,      0 },
919     { X86::VMOVUPDZ256rr,        X86::VMOVUPDZ256rm,        0 },
920     { X86::VMOVUPSZ256rr,        X86::VMOVUPSZ256rm,        0 },
921     { X86::VPERMPDZ256ri,        X86::VPERMPDZ256mi,        0 },
922     { X86::VPERMQZ256ri,         X86::VPERMQZ256mi,         0 },
923     { X86::VPMOVSXBDZ256rr,      X86::VPMOVSXBDZ256rm,      TB_NO_REVERSE },
924     { X86::VPMOVSXBQZ256rr,      X86::VPMOVSXBQZ256rm,      TB_NO_REVERSE },
925     { X86::VPMOVSXBWZ256rr,      X86::VPMOVSXBWZ256rm,      0 },
926     { X86::VPMOVSXDQZ256rr,      X86::VPMOVSXDQZ256rm,      0 },
927     { X86::VPMOVSXWDZ256rr,      X86::VPMOVSXWDZ256rm,      0 },
928     { X86::VPMOVSXWQZ256rr,      X86::VPMOVSXWQZ256rm,      TB_NO_REVERSE },
929     { X86::VPMOVZXBDZ256rr,      X86::VPMOVZXBDZ256rm,      TB_NO_REVERSE },
930     { X86::VPMOVZXBQZ256rr,      X86::VPMOVZXBQZ256rm,      TB_NO_REVERSE },
931     { X86::VPMOVZXBWZ256rr,      X86::VPMOVZXBWZ256rm,      0 },
932     { X86::VPMOVZXDQZ256rr,      X86::VPMOVZXDQZ256rm,      0 },
933     { X86::VPMOVZXWDZ256rr,      X86::VPMOVZXWDZ256rm,      0 },
934     { X86::VPMOVZXWQZ256rr,      X86::VPMOVZXWQZ256rm,      TB_NO_REVERSE },
935     { X86::VPSHUFDZ256ri,        X86::VPSHUFDZ256mi,        0 },
936     { X86::VPSHUFHWZ256ri,       X86::VPSHUFHWZ256mi,       0 },
937     { X86::VPSHUFLWZ256ri,       X86::VPSHUFLWZ256mi,       0 },
938 
939     // AVX-512 foldable instructions (128-bit versions)
940     { X86::VBROADCASTSSZ128r,    X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
941     { X86::VBROADCASTSSZ128r_s,  X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
942     { X86::VMOVAPDZ128rr,        X86::VMOVAPDZ128rm,        TB_ALIGN_16 },
943     { X86::VMOVAPSZ128rr,        X86::VMOVAPSZ128rm,        TB_ALIGN_16 },
944     { X86::VMOVDQA32Z128rr,      X86::VMOVDQA32Z128rm,      TB_ALIGN_16 },
945     { X86::VMOVDQA64Z128rr,      X86::VMOVDQA64Z128rm,      TB_ALIGN_16 },
946     { X86::VMOVDQU8Z128rr,       X86::VMOVDQU8Z128rm,       0 },
947     { X86::VMOVDQU16Z128rr,      X86::VMOVDQU16Z128rm,      0 },
948     { X86::VMOVDQU32Z128rr,      X86::VMOVDQU32Z128rm,      0 },
949     { X86::VMOVDQU64Z128rr,      X86::VMOVDQU64Z128rm,      0 },
950     { X86::VMOVUPDZ128rr,        X86::VMOVUPDZ128rm,        0 },
951     { X86::VMOVUPSZ128rr,        X86::VMOVUPSZ128rm,        0 },
952     { X86::VPMOVSXBDZ128rr,      X86::VPMOVSXBDZ128rm,      TB_NO_REVERSE },
953     { X86::VPMOVSXBQZ128rr,      X86::VPMOVSXBQZ128rm,      TB_NO_REVERSE },
954     { X86::VPMOVSXBWZ128rr,      X86::VPMOVSXBWZ128rm,      TB_NO_REVERSE },
955     { X86::VPMOVSXDQZ128rr,      X86::VPMOVSXDQZ128rm,      TB_NO_REVERSE },
956     { X86::VPMOVSXWDZ128rr,      X86::VPMOVSXWDZ128rm,      TB_NO_REVERSE },
957     { X86::VPMOVSXWQZ128rr,      X86::VPMOVSXWQZ128rm,      TB_NO_REVERSE },
958     { X86::VPMOVZXBDZ128rr,      X86::VPMOVZXBDZ128rm,      TB_NO_REVERSE },
959     { X86::VPMOVZXBQZ128rr,      X86::VPMOVZXBQZ128rm,      TB_NO_REVERSE },
960     { X86::VPMOVZXBWZ128rr,      X86::VPMOVZXBWZ128rm,      TB_NO_REVERSE },
961     { X86::VPMOVZXDQZ128rr,      X86::VPMOVZXDQZ128rm,      TB_NO_REVERSE },
962     { X86::VPMOVZXWDZ128rr,      X86::VPMOVZXWDZ128rm,      TB_NO_REVERSE },
963     { X86::VPMOVZXWQZ128rr,      X86::VPMOVZXWQZ128rm,      TB_NO_REVERSE },
964     { X86::VPSHUFDZ128ri,        X86::VPSHUFDZ128mi,        0 },
965     { X86::VPSHUFHWZ128ri,       X86::VPSHUFHWZ128mi,       0 },
966     { X86::VPSHUFLWZ128ri,       X86::VPSHUFLWZ128mi,       0 },
967 
968     // F16C foldable instructions
969     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
970     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
971 
972     // AES foldable instructions
973     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
974     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
975     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
976     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
977   };
978 
979   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
980     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
981                   Entry.RegOp, Entry.MemOp,
982                   // Index 1, folded load
983                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
984   }
985 
986   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
987     { X86::ADC32rr,         X86::ADC32rm,       0 },
988     { X86::ADC64rr,         X86::ADC64rm,       0 },
989     { X86::ADD16rr,         X86::ADD16rm,       0 },
990     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
991     { X86::ADD32rr,         X86::ADD32rm,       0 },
992     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
993     { X86::ADD64rr,         X86::ADD64rm,       0 },
994     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
995     { X86::ADD8rr,          X86::ADD8rm,        0 },
996     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
997     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
998     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
999     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   TB_NO_REVERSE },
1000     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
1001     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   TB_NO_REVERSE },
1002     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
1003     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
1004     { X86::AND16rr,         X86::AND16rm,       0 },
1005     { X86::AND32rr,         X86::AND32rm,       0 },
1006     { X86::AND64rr,         X86::AND64rm,       0 },
1007     { X86::AND8rr,          X86::AND8rm,        0 },
1008     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
1009     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
1010     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
1011     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
1012     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
1013     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
1014     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
1015     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
1016     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
1017     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
1018     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
1019     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
1020     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
1021     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
1022     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
1023     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
1024     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
1025     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
1026     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
1027     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
1028     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
1029     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
1030     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
1031     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
1032     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
1033     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
1034     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
1035     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
1036     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
1037     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
1038     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
1039     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
1040     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
1041     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
1042     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
1043     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
1044     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
1045     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
1046     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
1047     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
1048     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
1049     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
1050     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
1051     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
1052     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
1053     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
1054     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
1055     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
1056     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
1057     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
1058     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
1059     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
1060     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
1061     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
1062     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
1063     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
1064     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
1065     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
1066     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
1067     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
1068     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
1069     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
1070     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
1071     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
1072     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
1073     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   TB_NO_REVERSE },
1074     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
1075     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   TB_NO_REVERSE },
1076     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
1077     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
1078     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
1079     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
1080     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
1081     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
1082     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
1083     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
1084     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
1085     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   TB_NO_REVERSE },
1086     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   TB_NO_REVERSE },
1087     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      TB_NO_REVERSE },
1088     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
1089     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
1090     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
1091     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
1092     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      TB_NO_REVERSE },
1093     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
1094     { X86::MAXCPDrr,        X86::MAXCPDrm,      TB_ALIGN_16 },
1095     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
1096     { X86::MAXCPSrr,        X86::MAXCPSrm,      TB_ALIGN_16 },
1097     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
1098     { X86::MAXCSDrr,        X86::MAXCSDrm,      0 },
1099     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   TB_NO_REVERSE },
1100     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
1101     { X86::MAXCSSrr,        X86::MAXCSSrm,      0 },
1102     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   TB_NO_REVERSE },
1103     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
1104     { X86::MINCPDrr,        X86::MINCPDrm,      TB_ALIGN_16 },
1105     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
1106     { X86::MINCPSrr,        X86::MINCPSrm,      TB_ALIGN_16 },
1107     { X86::MINSDrr,         X86::MINSDrm,       0 },
1108     { X86::MINCSDrr,        X86::MINCSDrm,      0 },
1109     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   TB_NO_REVERSE },
1110     { X86::MINSSrr,         X86::MINSSrm,       0 },
1111     { X86::MINCSSrr,        X86::MINCSSrm,      0 },
1112     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   TB_NO_REVERSE },
1113     { X86::MOVLHPSrr,       X86::MOVHPSrm,      TB_NO_REVERSE },
1114     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1115     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1116     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1117     { X86::MULSDrr,         X86::MULSDrm,       0 },
1118     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   TB_NO_REVERSE },
1119     { X86::MULSSrr,         X86::MULSSrm,       0 },
1120     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   TB_NO_REVERSE },
1121     { X86::OR16rr,          X86::OR16rm,        0 },
1122     { X86::OR32rr,          X86::OR32rm,        0 },
1123     { X86::OR64rr,          X86::OR64rm,        0 },
1124     { X86::OR8rr,           X86::OR8rm,         0 },
1125     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1126     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1127     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1128     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1129     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1130     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1131     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1132     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1133     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1134     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1135     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1136     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1137     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1138     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1139     { X86::PALIGNRrri,      X86::PALIGNRrmi,    TB_ALIGN_16 },
1140     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1141     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1142     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1143     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1144     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1145     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1146     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1147     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1148     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1149     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1150     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1151     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1152     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1153     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1154     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1155     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1156     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1157     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1158     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1159     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1160     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1161     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1162     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1163     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1164     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1165     { X86::PMADDUBSWrr,     X86::PMADDUBSWrm,   TB_ALIGN_16 },
1166     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1167     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1168     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1169     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1170     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1171     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1172     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1173     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1174     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1175     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1176     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1177     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1178     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1179     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1180     { X86::PMULHRSWrr,      X86::PMULHRSWrm,    TB_ALIGN_16 },
1181     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1182     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1183     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1184     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1185     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1186     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1187     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1188     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1189     { X86::PSIGNBrr128,     X86::PSIGNBrm128,   TB_ALIGN_16 },
1190     { X86::PSIGNWrr128,     X86::PSIGNWrm128,   TB_ALIGN_16 },
1191     { X86::PSIGNDrr128,     X86::PSIGNDrm128,   TB_ALIGN_16 },
1192     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1193     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1194     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1195     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1196     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1197     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1198     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1199     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1200     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1201     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1202     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1203     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1204     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1205     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1206     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1207     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1208     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1209     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1210     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1211     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1212     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1213     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1214     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1215     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1216     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1217     { X86::ROUNDSDr_Int,    X86::ROUNDSDm_Int,  TB_NO_REVERSE },
1218     { X86::ROUNDSSr_Int,    X86::ROUNDSSm_Int,  TB_NO_REVERSE },
1219     { X86::SBB32rr,         X86::SBB32rm,       0 },
1220     { X86::SBB64rr,         X86::SBB64rm,       0 },
1221     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1222     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1223     { X86::SUB16rr,         X86::SUB16rm,       0 },
1224     { X86::SUB32rr,         X86::SUB32rm,       0 },
1225     { X86::SUB64rr,         X86::SUB64rm,       0 },
1226     { X86::SUB8rr,          X86::SUB8rm,        0 },
1227     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1228     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1229     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1230     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   TB_NO_REVERSE },
1231     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1232     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   TB_NO_REVERSE },
1233     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1234     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1235     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1236     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1237     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1238     { X86::XOR16rr,         X86::XOR16rm,       0 },
1239     { X86::XOR32rr,         X86::XOR32rm,       0 },
1240     { X86::XOR64rr,         X86::XOR64rm,       0 },
1241     { X86::XOR8rr,          X86::XOR8rm,        0 },
1242     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1243     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1244 
1245     // MMX version of foldable instructions
1246     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1247     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1248     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1249     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1250     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1251     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1252     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1253     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1254     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1255     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1256     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1257     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1258     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1259     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1260     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1261     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1262     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1263     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1264     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1265     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1266     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1267     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1268     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1269     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1270     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1271     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1272     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1273     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1274     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1275     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1276     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1277     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1278     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1279     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1280     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1281     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1282     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1283     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1284     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1285     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1286     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1287     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1288     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1289     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1290     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1291     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1292     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1293     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1294     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1295     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1296     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1297     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1298     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1299     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1300     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1301     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1302     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1303     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1304     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1305     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1306     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1307     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1308     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1309     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1310     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1311     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1312     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1313     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1314     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1315     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1316 
1317     // 3DNow! version of foldable instructions
1318     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1319     { X86::PFACCrr,           X86::PFACCrm,           0 },
1320     { X86::PFADDrr,           X86::PFADDrm,           0 },
1321     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1322     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1323     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1324     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1325     { X86::PFMINrr,           X86::PFMINrm,           0 },
1326     { X86::PFMULrr,           X86::PFMULrm,           0 },
1327     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1328     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1329     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1330     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1331     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1332     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1333     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1334     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1335 
1336     // AVX 128-bit versions of foldable instructions
1337     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1338     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    TB_NO_REVERSE },
1339     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1340     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1341     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1342     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1343     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1344     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1345     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1346     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1347     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1348     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    TB_NO_REVERSE },
1349     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1350     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1351     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1352     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       TB_NO_REVERSE },
1353     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1354     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       TB_NO_REVERSE },
1355     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1356     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1357     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1358     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1359     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1360     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1361     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1362     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1363     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1364     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1365     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1366     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1367     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1368     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1369     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1370     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1371     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1372     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       TB_NO_REVERSE },
1373     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1374     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       TB_NO_REVERSE },
1375     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1376     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1377     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1378     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1379     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1380     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1381     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       TB_NO_REVERSE },
1382     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       TB_NO_REVERSE },
1383     { X86::VMAXCPDrr,         X86::VMAXCPDrm,          0 },
1384     { X86::VMAXCPSrr,         X86::VMAXCPSrm,          0 },
1385     { X86::VMAXCSDrr,         X86::VMAXCSDrm,          0 },
1386     { X86::VMAXCSSrr,         X86::VMAXCSSrm,          0 },
1387     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1388     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1389     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1390     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       TB_NO_REVERSE },
1391     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1392     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       TB_NO_REVERSE },
1393     { X86::VMINCPDrr,         X86::VMINCPDrm,          0 },
1394     { X86::VMINCPSrr,         X86::VMINCPSrm,          0 },
1395     { X86::VMINCSDrr,         X86::VMINCSDrm,          0 },
1396     { X86::VMINCSSrr,         X86::VMINCSSrm,          0 },
1397     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1398     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1399     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1400     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       TB_NO_REVERSE },
1401     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1402     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       TB_NO_REVERSE },
1403     { X86::VMOVLHPSrr,        X86::VMOVHPSrm,          TB_NO_REVERSE },
1404     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1405     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1406     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1407     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1408     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       TB_NO_REVERSE },
1409     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1410     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       TB_NO_REVERSE },
1411     { X86::VORPDrr,           X86::VORPDrm,            0 },
1412     { X86::VORPSrr,           X86::VORPSrm,            0 },
1413     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1414     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1415     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1416     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1417     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1418     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1419     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1420     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1421     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1422     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1423     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1424     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1425     { X86::VPALIGNRrri,       X86::VPALIGNRrmi,        0 },
1426     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1427     { X86::VPANDrr,           X86::VPANDrm,            0 },
1428     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1429     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1430     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1431     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1432     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1433     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1434     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1435     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1436     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1437     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1438     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1439     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1440     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1441     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1442     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1443     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1444     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1445     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1446     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1447     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1448     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1449     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1450     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1451     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1452     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1453     { X86::VPMADDUBSWrr,      X86::VPMADDUBSWrm,       0 },
1454     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1455     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1456     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1457     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1458     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1459     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1460     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1461     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1462     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1463     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1464     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1465     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1466     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1467     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1468     { X86::VPMULHRSWrr,       X86::VPMULHRSWrm,        0 },
1469     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1470     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1471     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1472     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1473     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1474     { X86::VPORrr,            X86::VPORrm,             0 },
1475     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1476     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1477     { X86::VPSIGNBrr128,      X86::VPSIGNBrm128,       0 },
1478     { X86::VPSIGNWrr128,      X86::VPSIGNWrm128,       0 },
1479     { X86::VPSIGNDrr128,      X86::VPSIGNDrm128,       0 },
1480     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1481     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1482     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1483     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1484     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1485     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1486     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1487     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1488     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1489     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1490     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1491     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1492     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1493     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1494     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1495     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1496     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1497     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1498     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1499     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1500     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1501     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1502     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1503     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1504     { X86::VPXORrr,           X86::VPXORrm,            0 },
1505     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1506     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        TB_NO_REVERSE },
1507     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1508     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      TB_NO_REVERSE },
1509     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1510     { X86::VROUNDSDr_Int,     X86::VROUNDSDm_Int,      TB_NO_REVERSE },
1511     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1512     { X86::VROUNDSSr_Int,     X86::VROUNDSSm_Int,      TB_NO_REVERSE },
1513     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1514     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1515     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1516     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       TB_NO_REVERSE },
1517     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1518     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       TB_NO_REVERSE },
1519     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1520     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1521     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1522     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       TB_NO_REVERSE },
1523     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1524     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       TB_NO_REVERSE },
1525     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1526     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1527     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1528     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1529     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1530     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1531 
1532     // AVX 256-bit foldable instructions
1533     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1534     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1535     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1536     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1537     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1538     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1539     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1540     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1541     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1542     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1543     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1544     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1545     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1546     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1547     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1548     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1549     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1550     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1551     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1552     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1553     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1554     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1555     { X86::VMAXCPDYrr,        X86::VMAXCPDYrm,         0 },
1556     { X86::VMAXCPSYrr,        X86::VMAXCPSYrm,         0 },
1557     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1558     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1559     { X86::VMINCPDYrr,        X86::VMINCPDYrm,         0 },
1560     { X86::VMINCPSYrr,        X86::VMINCPSYrm,         0 },
1561     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1562     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1563     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1564     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1565     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1566     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1567     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1568     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1569     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1570     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1571     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1572     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1573     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1574     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1575     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1576     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1577     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1578     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1579     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1580 
1581     // AVX2 foldable instructions
1582     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1583     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1584     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1585     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1586     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1587     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1588     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1589     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1590     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1591     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1592     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1593     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1594     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1595     { X86::VPALIGNRYrri,      X86::VPALIGNRYrmi,       0 },
1596     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1597     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1598     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1599     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1600     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1601     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1602     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1603     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1604     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1605     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1606     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1607     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1608     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1609     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1610     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1611     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1612     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1613     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1614     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1615     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1616     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1617     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1618     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1619     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1620     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1621     { X86::VPMADDUBSWYrr,     X86::VPMADDUBSWYrm,      0 },
1622     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1623     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1624     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1625     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1626     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1627     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1628     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1629     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1630     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1631     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1632     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1633     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1634     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1635     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1636     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1637     { X86::VPMULHRSWYrr,      X86::VPMULHRSWYrm,       0 },
1638     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1639     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1640     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1641     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1642     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1643     { X86::VPORYrr,           X86::VPORYrm,            0 },
1644     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1645     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1646     { X86::VPSIGNBYrr256,     X86::VPSIGNBYrm256,      0 },
1647     { X86::VPSIGNWYrr256,     X86::VPSIGNWYrm256,      0 },
1648     { X86::VPSIGNDYrr256,     X86::VPSIGNDYrm256,      0 },
1649     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1650     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1651     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1652     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1653     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1654     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1655     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1656     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1657     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1658     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1659     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1660     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1661     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1662     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1663     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1664     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1665     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1666     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1667     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1668     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1669     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1670     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1671     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1672     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1673     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1674     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1675     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1676     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1677     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1678     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1679     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1680     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1681     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1682     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1683     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1684 
1685     // FMA4 foldable patterns
1686     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1687     { X86::VFMADDSS4rr_Int,   X86::VFMADDSS4mr_Int,    TB_NO_REVERSE },
1688     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1689     { X86::VFMADDSD4rr_Int,   X86::VFMADDSD4mr_Int,    TB_NO_REVERSE },
1690     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1691     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1692     { X86::VFMADDPS4Yrr,      X86::VFMADDPS4Ymr,       TB_ALIGN_NONE },
1693     { X86::VFMADDPD4Yrr,      X86::VFMADDPD4Ymr,       TB_ALIGN_NONE },
1694     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1695     { X86::VFNMADDSS4rr_Int,  X86::VFNMADDSS4mr_Int,   TB_NO_REVERSE },
1696     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1697     { X86::VFNMADDSD4rr_Int,  X86::VFNMADDSD4mr_Int,   TB_NO_REVERSE },
1698     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1699     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1700     { X86::VFNMADDPS4Yrr,     X86::VFNMADDPS4Ymr,      TB_ALIGN_NONE },
1701     { X86::VFNMADDPD4Yrr,     X86::VFNMADDPD4Ymr,      TB_ALIGN_NONE },
1702     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1703     { X86::VFMSUBSS4rr_Int,   X86::VFMSUBSS4mr_Int,    TB_NO_REVERSE },
1704     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1705     { X86::VFMSUBSD4rr_Int,   X86::VFMSUBSD4mr_Int,    TB_NO_REVERSE },
1706     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1707     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1708     { X86::VFMSUBPS4Yrr,      X86::VFMSUBPS4Ymr,       TB_ALIGN_NONE },
1709     { X86::VFMSUBPD4Yrr,      X86::VFMSUBPD4Ymr,       TB_ALIGN_NONE },
1710     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1711     { X86::VFNMSUBSS4rr_Int,  X86::VFNMSUBSS4mr_Int,   TB_NO_REVERSE },
1712     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1713     { X86::VFNMSUBSD4rr_Int,  X86::VFNMSUBSD4mr_Int,   TB_NO_REVERSE },
1714     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1715     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1716     { X86::VFNMSUBPS4Yrr,     X86::VFNMSUBPS4Ymr,      TB_ALIGN_NONE },
1717     { X86::VFNMSUBPD4Yrr,     X86::VFNMSUBPD4Ymr,      TB_ALIGN_NONE },
1718     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1719     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1720     { X86::VFMADDSUBPS4Yrr,   X86::VFMADDSUBPS4Ymr,    TB_ALIGN_NONE },
1721     { X86::VFMADDSUBPD4Yrr,   X86::VFMADDSUBPD4Ymr,    TB_ALIGN_NONE },
1722     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1723     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1724     { X86::VFMSUBADDPS4Yrr,   X86::VFMSUBADDPS4Ymr,    TB_ALIGN_NONE },
1725     { X86::VFMSUBADDPD4Yrr,   X86::VFMSUBADDPD4Ymr,    TB_ALIGN_NONE },
1726 
1727     // XOP foldable instructions
1728     { X86::VPCMOVrrr,         X86::VPCMOVrmr,           0 },
1729     { X86::VPCMOVrrrY,        X86::VPCMOVrmrY,          0 },
1730     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1731     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1732     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1733     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1734     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1735     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1736     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1737     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1738     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1739     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1740     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1741     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1742     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1743     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1744     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1745     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1746     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1747     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1748     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1749     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1750     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1751     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1752     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1753     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1754     { X86::VPPERMrrr,         X86::VPPERMrmr,           0 },
1755     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1756     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1757     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1758     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1759     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1760     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1761     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1762     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1763     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1764     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1765     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1766     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1767 
1768     // BMI/BMI2 foldable instructions
1769     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1770     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1771     { X86::MULX32rr,          X86::MULX32rm,            0 },
1772     { X86::MULX64rr,          X86::MULX64rm,            0 },
1773     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1774     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1775     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1776     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1777 
1778     // ADX foldable instructions
1779     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1780     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1781     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1782     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1783 
1784     // AVX-512 foldable instructions
1785     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1786     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1787     { X86::VADDSDZrr,         X86::VADDSDZrm,           0 },
1788     { X86::VADDSDZrr_Int,     X86::VADDSDZrm_Int,       TB_NO_REVERSE },
1789     { X86::VADDSSZrr,         X86::VADDSSZrm,           0 },
1790     { X86::VADDSSZrr_Int,     X86::VADDSSZrm_Int,       TB_NO_REVERSE },
1791     { X86::VANDNPDZrr,        X86::VANDNPDZrm,          0 },
1792     { X86::VANDNPSZrr,        X86::VANDNPSZrm,          0 },
1793     { X86::VANDPDZrr,         X86::VANDPDZrm,           0 },
1794     { X86::VANDPSZrr,         X86::VANDPSZrm,           0 },
1795     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1796     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1797     { X86::VCMPPDZrri,        X86::VCMPPDZrmi,          0 },
1798     { X86::VCMPPSZrri,        X86::VCMPPSZrmi,          0 },
1799     { X86::VCMPSDZrr,         X86::VCMPSDZrm,           0 },
1800     { X86::VCMPSDZrr_Int,     X86::VCMPSDZrm_Int,       TB_NO_REVERSE },
1801     { X86::VCMPSSZrr,         X86::VCMPSSZrm,           0 },
1802     { X86::VCMPSSZrr_Int,     X86::VCMPSSZrm_Int,       TB_NO_REVERSE },
1803     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1804     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1805     { X86::VDIVSDZrr,         X86::VDIVSDZrm,           0 },
1806     { X86::VDIVSDZrr_Int,     X86::VDIVSDZrm_Int,       TB_NO_REVERSE },
1807     { X86::VDIVSSZrr,         X86::VDIVSSZrm,           0 },
1808     { X86::VDIVSSZrr_Int,     X86::VDIVSSZrm_Int,       TB_NO_REVERSE },
1809     { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrm,     0 },
1810     { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrm,     0 },
1811     { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrm,     0 },
1812     { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrm,     0 },
1813     { X86::VINSERTI32x4Zrr,   X86::VINSERTI32x4Zrm,     0 },
1814     { X86::VINSERTI32x8Zrr,   X86::VINSERTI32x8Zrm,     0 },
1815     { X86::VINSERTI64x2Zrr,   X86::VINSERTI64x2Zrm,     0 },
1816     { X86::VINSERTI64x4Zrr,   X86::VINSERTI64x4Zrm,     0 },
1817     { X86::VMAXCPDZrr,        X86::VMAXCPDZrm,          0 },
1818     { X86::VMAXCPSZrr,        X86::VMAXCPSZrm,          0 },
1819     { X86::VMAXCSDZrr,        X86::VMAXCSDZrm,          0 },
1820     { X86::VMAXCSSZrr,        X86::VMAXCSSZrm,          0 },
1821     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1822     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1823     { X86::VMAXSDZrr,         X86::VMAXSDZrm,           0 },
1824     { X86::VMAXSDZrr_Int,     X86::VMAXSDZrm_Int,       TB_NO_REVERSE },
1825     { X86::VMAXSSZrr,         X86::VMAXSSZrm,           0 },
1826     { X86::VMAXSSZrr_Int,     X86::VMAXSSZrm_Int,       TB_NO_REVERSE },
1827     { X86::VMINCPDZrr,        X86::VMINCPDZrm,          0 },
1828     { X86::VMINCPSZrr,        X86::VMINCPSZrm,          0 },
1829     { X86::VMINCSDZrr,        X86::VMINCSDZrm,          0 },
1830     { X86::VMINCSSZrr,        X86::VMINCSSZrm,          0 },
1831     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1832     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1833     { X86::VMINSDZrr,         X86::VMINSDZrm,           0 },
1834     { X86::VMINSDZrr_Int,     X86::VMINSDZrm_Int,       TB_NO_REVERSE },
1835     { X86::VMINSSZrr,         X86::VMINSSZrm,           0 },
1836     { X86::VMINSSZrr_Int,     X86::VMINSSZrm_Int,       TB_NO_REVERSE },
1837     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1838     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1839     { X86::VMULSDZrr,         X86::VMULSDZrm,           0 },
1840     { X86::VMULSDZrr_Int,     X86::VMULSDZrm_Int,       TB_NO_REVERSE },
1841     { X86::VMULSSZrr,         X86::VMULSSZrm,           0 },
1842     { X86::VMULSSZrr_Int,     X86::VMULSSZrm_Int,       TB_NO_REVERSE },
1843     { X86::VORPDZrr,          X86::VORPDZrm,            0 },
1844     { X86::VORPSZrr,          X86::VORPSZrm,            0 },
1845     { X86::VPADDBZrr,         X86::VPADDBZrm,           0 },
1846     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1847     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1848     { X86::VPADDSBZrr,        X86::VPADDSBZrm,          0 },
1849     { X86::VPADDSWZrr,        X86::VPADDSWZrm,          0 },
1850     { X86::VPADDUSBZrr,       X86::VPADDUSBZrm,         0 },
1851     { X86::VPADDUSWZrr,       X86::VPADDUSWZrm,         0 },
1852     { X86::VPADDWZrr,         X86::VPADDWZrm,           0 },
1853     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1854     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1855     { X86::VPANDDZrr,         X86::VPANDDZrm,           0 },
1856     { X86::VPANDNDZrr,        X86::VPANDNDZrm,          0 },
1857     { X86::VPANDNQZrr,        X86::VPANDNQZrm,          0 },
1858     { X86::VPANDQZrr,         X86::VPANDQZrm,           0 },
1859     { X86::VPCMPBZrri,        X86::VPCMPBZrmi,          0 },
1860     { X86::VPCMPDZrri,        X86::VPCMPDZrmi,          0 },
1861     { X86::VPCMPEQBZrr,       X86::VPCMPEQBZrm,         0 },
1862     { X86::VPCMPEQDZrr,       X86::VPCMPEQDZrm,         0 },
1863     { X86::VPCMPEQQZrr,       X86::VPCMPEQQZrm,         0 },
1864     { X86::VPCMPEQWZrr,       X86::VPCMPEQWZrm,         0 },
1865     { X86::VPCMPGTBZrr,       X86::VPCMPGTBZrm,         0 },
1866     { X86::VPCMPGTDZrr,       X86::VPCMPGTDZrm,         0 },
1867     { X86::VPCMPGTQZrr,       X86::VPCMPGTQZrm,         0 },
1868     { X86::VPCMPGTWZrr,       X86::VPCMPGTWZrm,         0 },
1869     { X86::VPCMPQZrri,        X86::VPCMPQZrmi,          0 },
1870     { X86::VPCMPUBZrri,       X86::VPCMPUBZrmi,         0 },
1871     { X86::VPCMPUDZrri,       X86::VPCMPUDZrmi,         0 },
1872     { X86::VPCMPUQZrri,       X86::VPCMPUQZrmi,         0 },
1873     { X86::VPCMPUWZrri,       X86::VPCMPUWZrmi,         0 },
1874     { X86::VPCMPWZrri,        X86::VPCMPWZrmi,          0 },
1875     { X86::VPERMBZrr,         X86::VPERMBZrm,           0 },
1876     { X86::VPERMDZrr,         X86::VPERMDZrm,           0 },
1877     { X86::VPERMPDZrr,        X86::VPERMPDZrm,          0 },
1878     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1879     { X86::VPERMQZrr,         X86::VPERMQZrm,           0 },
1880     { X86::VPERMWZrr,         X86::VPERMWZrm,           0 },
1881     { X86::VPMADDUBSWZrr,     X86::VPMADDUBSWZrm,       0 },
1882     { X86::VPMADDWDZrr,       X86::VPMADDWDZrm,         0 },
1883     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1884     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1885     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1886     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1887     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1888     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1889     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1890     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1891     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1892     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1893     { X86::VPORDZrr,          X86::VPORDZrm,            0 },
1894     { X86::VPORQZrr,          X86::VPORQZrm,            0 },
1895     { X86::VPSHUFBZrr,        X86::VPSHUFBZrm,          0 },
1896     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1897     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1898     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1899     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1900     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1901     { X86::VPSUBBZrr,         X86::VPSUBBZrm,           0 },
1902     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1903     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1904     { X86::VPSUBSBZrr,        X86::VPSUBSBZrm,          0 },
1905     { X86::VPSUBSWZrr,        X86::VPSUBSWZrm,          0 },
1906     { X86::VPSUBUSBZrr,       X86::VPSUBUSBZrm,         0 },
1907     { X86::VPSUBUSWZrr,       X86::VPSUBUSWZrm,         0 },
1908     { X86::VPSUBWZrr,         X86::VPSUBWZrm,           0 },
1909     { X86::VPUNPCKHBWZrr,     X86::VPUNPCKHBWZrm,       0 },
1910     { X86::VPUNPCKHDQZrr,     X86::VPUNPCKHDQZrm,       0 },
1911     { X86::VPUNPCKHQDQZrr,    X86::VPUNPCKHQDQZrm,      0 },
1912     { X86::VPUNPCKHWDZrr,     X86::VPUNPCKHWDZrm,       0 },
1913     { X86::VPUNPCKLBWZrr,     X86::VPUNPCKLBWZrm,       0 },
1914     { X86::VPUNPCKLDQZrr,     X86::VPUNPCKLDQZrm,       0 },
1915     { X86::VPUNPCKLQDQZrr,    X86::VPUNPCKLQDQZrm,      0 },
1916     { X86::VPUNPCKLWDZrr,     X86::VPUNPCKLWDZrm,       0 },
1917     { X86::VPXORDZrr,         X86::VPXORDZrm,           0 },
1918     { X86::VPXORQZrr,         X86::VPXORQZrm,           0 },
1919     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1920     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1921     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1922     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1923     { X86::VSUBSDZrr,         X86::VSUBSDZrm,           0 },
1924     { X86::VSUBSDZrr_Int,     X86::VSUBSDZrm_Int,       TB_NO_REVERSE },
1925     { X86::VSUBSSZrr,         X86::VSUBSSZrm,           0 },
1926     { X86::VSUBSSZrr_Int,     X86::VSUBSSZrm_Int,       TB_NO_REVERSE },
1927     { X86::VUNPCKHPDZrr,      X86::VUNPCKHPDZrm,        0 },
1928     { X86::VUNPCKHPSZrr,      X86::VUNPCKHPSZrm,        0 },
1929     { X86::VUNPCKLPDZrr,      X86::VUNPCKLPDZrm,        0 },
1930     { X86::VUNPCKLPSZrr,      X86::VUNPCKLPSZrm,        0 },
1931     { X86::VXORPDZrr,         X86::VXORPDZrm,           0 },
1932     { X86::VXORPSZrr,         X86::VXORPSZrm,           0 },
1933 
1934     // AVX-512{F,VL} foldable instructions
1935     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1936     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1937     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1938     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1939     { X86::VANDNPDZ128rr,     X86::VANDNPDZ128rm,       0 },
1940     { X86::VANDNPDZ256rr,     X86::VANDNPDZ256rm,       0 },
1941     { X86::VANDNPSZ128rr,     X86::VANDNPSZ128rm,       0 },
1942     { X86::VANDNPSZ256rr,     X86::VANDNPSZ256rm,       0 },
1943     { X86::VANDPDZ128rr,      X86::VANDPDZ128rm,        0 },
1944     { X86::VANDPDZ256rr,      X86::VANDPDZ256rm,        0 },
1945     { X86::VANDPSZ128rr,      X86::VANDPSZ128rm,        0 },
1946     { X86::VANDPSZ256rr,      X86::VANDPSZ256rm,        0 },
1947     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1948     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1949     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1950     { X86::VCMPPDZ128rri,     X86::VCMPPDZ128rmi,       0 },
1951     { X86::VCMPPDZ256rri,     X86::VCMPPDZ256rmi,       0 },
1952     { X86::VCMPPSZ128rri,     X86::VCMPPSZ128rmi,       0 },
1953     { X86::VCMPPSZ256rri,     X86::VCMPPSZ256rmi,       0 },
1954     { X86::VDIVPDZ128rr,      X86::VDIVPDZ128rm,        0 },
1955     { X86::VDIVPDZ256rr,      X86::VDIVPDZ256rm,        0 },
1956     { X86::VDIVPSZ128rr,      X86::VDIVPSZ128rm,        0 },
1957     { X86::VDIVPSZ256rr,      X86::VDIVPSZ256rm,        0 },
1958     { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rm,  0 },
1959     { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rm,  0 },
1960     { X86::VINSERTI32x4Z256rr,X86::VINSERTI32x4Z256rm,  0 },
1961     { X86::VINSERTI64x2Z256rr,X86::VINSERTI64x2Z256rm,  0 },
1962     { X86::VMAXCPDZ128rr,     X86::VMAXCPDZ128rm,       0 },
1963     { X86::VMAXCPDZ256rr,     X86::VMAXCPDZ256rm,       0 },
1964     { X86::VMAXCPSZ128rr,     X86::VMAXCPSZ128rm,       0 },
1965     { X86::VMAXCPSZ256rr,     X86::VMAXCPSZ256rm,       0 },
1966     { X86::VMAXPDZ128rr,      X86::VMAXPDZ128rm,        0 },
1967     { X86::VMAXPDZ256rr,      X86::VMAXPDZ256rm,        0 },
1968     { X86::VMAXPSZ128rr,      X86::VMAXPSZ128rm,        0 },
1969     { X86::VMAXPSZ256rr,      X86::VMAXPSZ256rm,        0 },
1970     { X86::VMINCPDZ128rr,     X86::VMINCPDZ128rm,       0 },
1971     { X86::VMINCPDZ256rr,     X86::VMINCPDZ256rm,       0 },
1972     { X86::VMINCPSZ128rr,     X86::VMINCPSZ128rm,       0 },
1973     { X86::VMINCPSZ256rr,     X86::VMINCPSZ256rm,       0 },
1974     { X86::VMINPDZ128rr,      X86::VMINPDZ128rm,        0 },
1975     { X86::VMINPDZ256rr,      X86::VMINPDZ256rm,        0 },
1976     { X86::VMINPSZ128rr,      X86::VMINPSZ128rm,        0 },
1977     { X86::VMINPSZ256rr,      X86::VMINPSZ256rm,        0 },
1978     { X86::VMULPDZ128rr,      X86::VMULPDZ128rm,        0 },
1979     { X86::VMULPDZ256rr,      X86::VMULPDZ256rm,        0 },
1980     { X86::VMULPSZ128rr,      X86::VMULPSZ128rm,        0 },
1981     { X86::VMULPSZ256rr,      X86::VMULPSZ256rm,        0 },
1982     { X86::VORPDZ128rr,       X86::VORPDZ128rm,         0 },
1983     { X86::VORPDZ256rr,       X86::VORPDZ256rm,         0 },
1984     { X86::VORPSZ128rr,       X86::VORPSZ128rm,         0 },
1985     { X86::VORPSZ256rr,       X86::VORPSZ256rm,         0 },
1986     { X86::VPADDBZ128rr,      X86::VPADDBZ128rm,        0 },
1987     { X86::VPADDBZ256rr,      X86::VPADDBZ256rm,        0 },
1988     { X86::VPADDDZ128rr,      X86::VPADDDZ128rm,        0 },
1989     { X86::VPADDDZ256rr,      X86::VPADDDZ256rm,        0 },
1990     { X86::VPADDQZ128rr,      X86::VPADDQZ128rm,        0 },
1991     { X86::VPADDQZ256rr,      X86::VPADDQZ256rm,        0 },
1992     { X86::VPADDSBZ128rr,     X86::VPADDSBZ128rm,       0 },
1993     { X86::VPADDSBZ256rr,     X86::VPADDSBZ256rm,       0 },
1994     { X86::VPADDSWZ128rr,     X86::VPADDSWZ128rm,       0 },
1995     { X86::VPADDSWZ256rr,     X86::VPADDSWZ256rm,       0 },
1996     { X86::VPADDUSBZ128rr,    X86::VPADDUSBZ128rm,      0 },
1997     { X86::VPADDUSBZ256rr,    X86::VPADDUSBZ256rm,      0 },
1998     { X86::VPADDUSWZ128rr,    X86::VPADDUSWZ128rm,      0 },
1999     { X86::VPADDUSWZ256rr,    X86::VPADDUSWZ256rm,      0 },
2000     { X86::VPADDWZ128rr,      X86::VPADDWZ128rm,        0 },
2001     { X86::VPADDWZ256rr,      X86::VPADDWZ256rm,        0 },
2002     { X86::VPANDDZ128rr,      X86::VPANDDZ128rm,        0 },
2003     { X86::VPANDDZ256rr,      X86::VPANDDZ256rm,        0 },
2004     { X86::VPANDNDZ128rr,     X86::VPANDNDZ128rm,       0 },
2005     { X86::VPANDNDZ256rr,     X86::VPANDNDZ256rm,       0 },
2006     { X86::VPANDNQZ128rr,     X86::VPANDNQZ128rm,       0 },
2007     { X86::VPANDNQZ256rr,     X86::VPANDNQZ256rm,       0 },
2008     { X86::VPANDQZ128rr,      X86::VPANDQZ128rm,        0 },
2009     { X86::VPANDQZ256rr,      X86::VPANDQZ256rm,        0 },
2010     { X86::VPCMPBZ128rri,     X86::VPCMPBZ128rmi,       0 },
2011     { X86::VPCMPBZ256rri,     X86::VPCMPBZ256rmi,       0 },
2012     { X86::VPCMPDZ128rri,     X86::VPCMPDZ128rmi,       0 },
2013     { X86::VPCMPDZ256rri,     X86::VPCMPDZ256rmi,       0 },
2014     { X86::VPCMPEQBZ128rr,    X86::VPCMPEQBZ128rm,      0 },
2015     { X86::VPCMPEQBZ256rr,    X86::VPCMPEQBZ256rm,      0 },
2016     { X86::VPCMPEQDZ128rr,    X86::VPCMPEQDZ128rm,      0 },
2017     { X86::VPCMPEQDZ256rr,    X86::VPCMPEQDZ256rm,      0 },
2018     { X86::VPCMPEQQZ128rr,    X86::VPCMPEQQZ128rm,      0 },
2019     { X86::VPCMPEQQZ256rr,    X86::VPCMPEQQZ256rm,      0 },
2020     { X86::VPCMPEQWZ128rr,    X86::VPCMPEQWZ128rm,      0 },
2021     { X86::VPCMPEQWZ256rr,    X86::VPCMPEQWZ256rm,      0 },
2022     { X86::VPCMPGTBZ128rr,    X86::VPCMPGTBZ128rm,      0 },
2023     { X86::VPCMPGTBZ256rr,    X86::VPCMPGTBZ256rm,      0 },
2024     { X86::VPCMPGTDZ128rr,    X86::VPCMPGTDZ128rm,      0 },
2025     { X86::VPCMPGTDZ256rr,    X86::VPCMPGTDZ256rm,      0 },
2026     { X86::VPCMPGTQZ128rr,    X86::VPCMPGTQZ128rm,      0 },
2027     { X86::VPCMPGTQZ256rr,    X86::VPCMPGTQZ256rm,      0 },
2028     { X86::VPCMPGTWZ128rr,    X86::VPCMPGTWZ128rm,      0 },
2029     { X86::VPCMPGTWZ256rr,    X86::VPCMPGTWZ256rm,      0 },
2030     { X86::VPCMPQZ128rri,     X86::VPCMPQZ128rmi,       0 },
2031     { X86::VPCMPQZ256rri,     X86::VPCMPQZ256rmi,       0 },
2032     { X86::VPCMPUBZ128rri,    X86::VPCMPUBZ128rmi,      0 },
2033     { X86::VPCMPUBZ256rri,    X86::VPCMPUBZ256rmi,      0 },
2034     { X86::VPCMPUDZ128rri,    X86::VPCMPUDZ128rmi,      0 },
2035     { X86::VPCMPUDZ256rri,    X86::VPCMPUDZ256rmi,      0 },
2036     { X86::VPCMPUQZ128rri,    X86::VPCMPUQZ128rmi,      0 },
2037     { X86::VPCMPUQZ256rri,    X86::VPCMPUQZ256rmi,      0 },
2038     { X86::VPCMPUWZ128rri,    X86::VPCMPUWZ128rmi,      0 },
2039     { X86::VPCMPUWZ256rri,    X86::VPCMPUWZ256rmi,      0 },
2040     { X86::VPCMPWZ128rri,     X86::VPCMPWZ128rmi,       0 },
2041     { X86::VPCMPWZ256rri,     X86::VPCMPWZ256rmi,       0 },
2042     { X86::VPERMBZ128rr,      X86::VPERMBZ128rm,        0 },
2043     { X86::VPERMBZ256rr,      X86::VPERMBZ256rm,        0 },
2044     { X86::VPERMDZ256rr,      X86::VPERMDZ256rm,        0 },
2045     { X86::VPERMPDZ256rr,     X86::VPERMPDZ256rm,       0 },
2046     { X86::VPERMPSZ256rr,     X86::VPERMPSZ256rm,       0 },
2047     { X86::VPERMQZ256rr,      X86::VPERMQZ256rm,        0 },
2048     { X86::VPERMWZ128rr,      X86::VPERMWZ128rm,        0 },
2049     { X86::VPERMWZ256rr,      X86::VPERMWZ256rm,        0 },
2050     { X86::VPMADDUBSWZ128rr,  X86::VPMADDUBSWZ128rm,    0 },
2051     { X86::VPMADDUBSWZ256rr,  X86::VPMADDUBSWZ256rm,    0 },
2052     { X86::VPMADDWDZ128rr,    X86::VPMADDWDZ128rm,      0 },
2053     { X86::VPMADDWDZ256rr,    X86::VPMADDWDZ256rm,      0 },
2054     { X86::VPORDZ128rr,       X86::VPORDZ128rm,         0 },
2055     { X86::VPORDZ256rr,       X86::VPORDZ256rm,         0 },
2056     { X86::VPORQZ128rr,       X86::VPORQZ128rm,         0 },
2057     { X86::VPORQZ256rr,       X86::VPORQZ256rm,         0 },
2058     { X86::VPSHUFBZ128rr,     X86::VPSHUFBZ128rm,       0 },
2059     { X86::VPSHUFBZ256rr,     X86::VPSHUFBZ256rm,       0 },
2060     { X86::VPSUBBZ128rr,      X86::VPSUBBZ128rm,        0 },
2061     { X86::VPSUBBZ256rr,      X86::VPSUBBZ256rm,        0 },
2062     { X86::VPSUBDZ128rr,      X86::VPSUBDZ128rm,        0 },
2063     { X86::VPSUBDZ256rr,      X86::VPSUBDZ256rm,        0 },
2064     { X86::VPSUBQZ128rr,      X86::VPSUBQZ128rm,        0 },
2065     { X86::VPSUBQZ256rr,      X86::VPSUBQZ256rm,        0 },
2066     { X86::VPSUBSBZ128rr,     X86::VPSUBSBZ128rm,       0 },
2067     { X86::VPSUBSBZ256rr,     X86::VPSUBSBZ256rm,       0 },
2068     { X86::VPSUBSWZ128rr,     X86::VPSUBSWZ128rm,       0 },
2069     { X86::VPSUBSWZ256rr,     X86::VPSUBSWZ256rm,       0 },
2070     { X86::VPSUBUSBZ128rr,    X86::VPSUBUSBZ128rm,      0 },
2071     { X86::VPSUBUSBZ256rr,    X86::VPSUBUSBZ256rm,      0 },
2072     { X86::VPSUBUSWZ128rr,    X86::VPSUBUSWZ128rm,      0 },
2073     { X86::VPSUBUSWZ256rr,    X86::VPSUBUSWZ256rm,      0 },
2074     { X86::VPSUBWZ128rr,      X86::VPSUBWZ128rm,        0 },
2075     { X86::VPSUBWZ256rr,      X86::VPSUBWZ256rm,        0 },
2076     { X86::VPUNPCKHBWZ128rr,  X86::VPUNPCKHBWZ128rm,    0 },
2077     { X86::VPUNPCKHBWZ256rr,  X86::VPUNPCKHBWZ256rm,    0 },
2078     { X86::VPUNPCKHDQZ128rr,  X86::VPUNPCKHDQZ128rm,    0 },
2079     { X86::VPUNPCKHDQZ256rr,  X86::VPUNPCKHDQZ256rm,    0 },
2080     { X86::VPUNPCKHQDQZ128rr, X86::VPUNPCKHQDQZ128rm,   0 },
2081     { X86::VPUNPCKHQDQZ256rr, X86::VPUNPCKHQDQZ256rm,   0 },
2082     { X86::VPUNPCKHWDZ128rr,  X86::VPUNPCKHWDZ128rm,    0 },
2083     { X86::VPUNPCKHWDZ256rr,  X86::VPUNPCKHWDZ256rm,    0 },
2084     { X86::VPUNPCKLBWZ128rr,  X86::VPUNPCKLBWZ128rm,    0 },
2085     { X86::VPUNPCKLBWZ256rr,  X86::VPUNPCKLBWZ256rm,    0 },
2086     { X86::VPUNPCKLDQZ128rr,  X86::VPUNPCKLDQZ128rm,    0 },
2087     { X86::VPUNPCKLDQZ256rr,  X86::VPUNPCKLDQZ256rm,    0 },
2088     { X86::VPUNPCKLQDQZ128rr, X86::VPUNPCKLQDQZ128rm,   0 },
2089     { X86::VPUNPCKLQDQZ256rr, X86::VPUNPCKLQDQZ256rm,   0 },
2090     { X86::VPUNPCKLWDZ128rr,  X86::VPUNPCKLWDZ128rm,    0 },
2091     { X86::VPUNPCKLWDZ256rr,  X86::VPUNPCKLWDZ256rm,    0 },
2092     { X86::VPXORDZ128rr,      X86::VPXORDZ128rm,        0 },
2093     { X86::VPXORDZ256rr,      X86::VPXORDZ256rm,        0 },
2094     { X86::VPXORQZ128rr,      X86::VPXORQZ128rm,        0 },
2095     { X86::VPXORQZ256rr,      X86::VPXORQZ256rm,        0 },
2096     { X86::VSUBPDZ128rr,      X86::VSUBPDZ128rm,        0 },
2097     { X86::VSUBPDZ256rr,      X86::VSUBPDZ256rm,        0 },
2098     { X86::VSUBPSZ128rr,      X86::VSUBPSZ128rm,        0 },
2099     { X86::VSUBPSZ256rr,      X86::VSUBPSZ256rm,        0 },
2100     { X86::VUNPCKHPDZ128rr,   X86::VUNPCKHPDZ128rm,     0 },
2101     { X86::VUNPCKHPDZ256rr,   X86::VUNPCKHPDZ256rm,     0 },
2102     { X86::VUNPCKHPSZ128rr,   X86::VUNPCKHPSZ128rm,     0 },
2103     { X86::VUNPCKHPSZ256rr,   X86::VUNPCKHPSZ256rm,     0 },
2104     { X86::VUNPCKLPDZ128rr,   X86::VUNPCKLPDZ128rm,     0 },
2105     { X86::VUNPCKLPDZ256rr,   X86::VUNPCKLPDZ256rm,     0 },
2106     { X86::VUNPCKLPSZ128rr,   X86::VUNPCKLPSZ128rm,     0 },
2107     { X86::VUNPCKLPSZ256rr,   X86::VUNPCKLPSZ256rm,     0 },
2108     { X86::VXORPDZ128rr,      X86::VXORPDZ128rm,        0 },
2109     { X86::VXORPDZ256rr,      X86::VXORPDZ256rm,        0 },
2110     { X86::VXORPSZ128rr,      X86::VXORPSZ128rm,        0 },
2111     { X86::VXORPSZ256rr,      X86::VXORPSZ256rm,        0 },
2112 
2113     // AVX-512 masked foldable instructions
2114     { X86::VPERMPDZrikz,      X86::VPERMPDZmikz,        0 },
2115     { X86::VPERMQZrikz,       X86::VPERMQZmikz,         0 },
2116     { X86::VPMOVSXBDZrrkz,    X86::VPMOVSXBDZrmkz,      0 },
2117     { X86::VPMOVSXBQZrrkz,    X86::VPMOVSXBQZrmkz,      TB_NO_REVERSE },
2118     { X86::VPMOVSXBWZrrkz,    X86::VPMOVSXBWZrmkz,      0 },
2119     { X86::VPMOVSXDQZrrkz,    X86::VPMOVSXDQZrmkz,      0 },
2120     { X86::VPMOVSXWDZrrkz,    X86::VPMOVSXWDZrmkz,      0 },
2121     { X86::VPMOVSXWQZrrkz,    X86::VPMOVSXWQZrmkz,      0 },
2122     { X86::VPMOVZXBDZrrkz,    X86::VPMOVZXBDZrmkz,      0 },
2123     { X86::VPMOVZXBQZrrkz,    X86::VPMOVZXBQZrmkz,      TB_NO_REVERSE },
2124     { X86::VPMOVZXBWZrrkz,    X86::VPMOVZXBWZrmkz,      0 },
2125     { X86::VPMOVZXDQZrrkz,    X86::VPMOVZXDQZrmkz,      0 },
2126     { X86::VPMOVZXWDZrrkz,    X86::VPMOVZXWDZrmkz,      0 },
2127     { X86::VPMOVZXWQZrrkz,    X86::VPMOVZXWQZrmkz,      0 },
2128     { X86::VPSHUFDZrikz,      X86::VPSHUFDZmikz,        0 },
2129     { X86::VPSHUFHWZrikz,     X86::VPSHUFHWZmikz,       0 },
2130     { X86::VPSHUFLWZrikz,     X86::VPSHUFLWZmikz,       0 },
2131 
2132     // AVX-512VL 256-bit masked foldable instructions
2133     { X86::VPERMPDZ256rikz,   X86::VPERMPDZ256mikz,     0 },
2134     { X86::VPERMQZ256rikz,    X86::VPERMQZ256mikz,      0 },
2135     { X86::VPMOVSXBDZ256rrkz, X86::VPMOVSXBDZ256rmkz,   TB_NO_REVERSE },
2136     { X86::VPMOVSXBQZ256rrkz, X86::VPMOVSXBQZ256rmkz,   TB_NO_REVERSE },
2137     { X86::VPMOVSXBWZ256rrkz, X86::VPMOVSXBWZ256rmkz,   0 },
2138     { X86::VPMOVSXDQZ256rrkz, X86::VPMOVSXDQZ256rmkz,   0 },
2139     { X86::VPMOVSXWDZ256rrkz, X86::VPMOVSXWDZ256rmkz,   0 },
2140     { X86::VPMOVSXWQZ256rrkz, X86::VPMOVSXWQZ256rmkz,   TB_NO_REVERSE },
2141     { X86::VPMOVZXBDZ256rrkz, X86::VPMOVZXBDZ256rmkz,   TB_NO_REVERSE },
2142     { X86::VPMOVZXBQZ256rrkz, X86::VPMOVZXBQZ256rmkz,   TB_NO_REVERSE },
2143     { X86::VPMOVZXBWZ256rrkz, X86::VPMOVZXBWZ256rmkz,   0 },
2144     { X86::VPMOVZXDQZ256rrkz, X86::VPMOVZXDQZ256rmkz,   0 },
2145     { X86::VPMOVZXWDZ256rrkz, X86::VPMOVZXWDZ256rmkz,   0 },
2146     { X86::VPMOVZXWQZ256rrkz, X86::VPMOVZXWQZ256rmkz,   TB_NO_REVERSE },
2147     { X86::VPSHUFDZ256rikz,   X86::VPSHUFDZ256mikz,     0 },
2148     { X86::VPSHUFHWZ256rikz,  X86::VPSHUFHWZ256mikz,    0 },
2149     { X86::VPSHUFLWZ256rikz,  X86::VPSHUFLWZ256mikz,    0 },
2150 
2151     // AVX-512VL 128-bit masked foldable instructions
2152     { X86::VPMOVSXBDZ128rrkz, X86::VPMOVSXBDZ128rmkz,   TB_NO_REVERSE },
2153     { X86::VPMOVSXBQZ128rrkz, X86::VPMOVSXBQZ128rmkz,   TB_NO_REVERSE },
2154     { X86::VPMOVSXBWZ128rrkz, X86::VPMOVSXBWZ128rmkz,   TB_NO_REVERSE },
2155     { X86::VPMOVSXDQZ128rrkz, X86::VPMOVSXDQZ128rmkz,   TB_NO_REVERSE },
2156     { X86::VPMOVSXWDZ128rrkz, X86::VPMOVSXWDZ128rmkz,   TB_NO_REVERSE },
2157     { X86::VPMOVSXWQZ128rrkz, X86::VPMOVSXWQZ128rmkz,   TB_NO_REVERSE },
2158     { X86::VPMOVZXBDZ128rrkz, X86::VPMOVZXBDZ128rmkz,   TB_NO_REVERSE },
2159     { X86::VPMOVZXBQZ128rrkz, X86::VPMOVZXBQZ128rmkz,   TB_NO_REVERSE },
2160     { X86::VPMOVZXBWZ128rrkz, X86::VPMOVZXBWZ128rmkz,   TB_NO_REVERSE },
2161     { X86::VPMOVZXDQZ128rrkz, X86::VPMOVZXDQZ128rmkz,   TB_NO_REVERSE },
2162     { X86::VPMOVZXWDZ128rrkz, X86::VPMOVZXWDZ128rmkz,   TB_NO_REVERSE },
2163     { X86::VPMOVZXWQZ128rrkz, X86::VPMOVZXWQZ128rmkz,   TB_NO_REVERSE },
2164     { X86::VPSHUFDZ128rikz,   X86::VPSHUFDZ128mikz,     0 },
2165     { X86::VPSHUFHWZ128rikz,  X86::VPSHUFHWZ128mikz,    0 },
2166     { X86::VPSHUFLWZ128rikz,  X86::VPSHUFLWZ128mikz,    0 },
2167 
2168     // AES foldable instructions
2169     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
2170     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
2171     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
2172     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
2173     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
2174     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
2175     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
2176     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
2177 
2178     // SHA foldable instructions
2179     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
2180     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
2181     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
2182     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
2183     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
2184     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
2185     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
2186   };
2187 
2188   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
2189     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
2190                   Entry.RegOp, Entry.MemOp,
2191                   // Index 2, folded load
2192                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
2193   }
2194 
2195   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
2196     // FMA4 foldable patterns
2197     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
2198     { X86::VFMADDSS4rr_Int,       X86::VFMADDSS4rm_Int,       TB_NO_REVERSE },
2199     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
2200     { X86::VFMADDSD4rr_Int,       X86::VFMADDSD4rm_Int,       TB_NO_REVERSE },
2201     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
2202     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
2203     { X86::VFMADDPS4Yrr,          X86::VFMADDPS4Yrm,          TB_ALIGN_NONE },
2204     { X86::VFMADDPD4Yrr,          X86::VFMADDPD4Yrm,          TB_ALIGN_NONE },
2205     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
2206     { X86::VFNMADDSS4rr_Int,      X86::VFNMADDSS4rm_Int,      TB_NO_REVERSE },
2207     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
2208     { X86::VFNMADDSD4rr_Int,      X86::VFNMADDSD4rm_Int,      TB_NO_REVERSE },
2209     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
2210     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
2211     { X86::VFNMADDPS4Yrr,         X86::VFNMADDPS4Yrm,         TB_ALIGN_NONE },
2212     { X86::VFNMADDPD4Yrr,         X86::VFNMADDPD4Yrm,         TB_ALIGN_NONE },
2213     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
2214     { X86::VFMSUBSS4rr_Int,       X86::VFMSUBSS4rm_Int,       TB_NO_REVERSE },
2215     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
2216     { X86::VFMSUBSD4rr_Int,       X86::VFMSUBSD4rm_Int,       TB_NO_REVERSE },
2217     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
2218     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
2219     { X86::VFMSUBPS4Yrr,          X86::VFMSUBPS4Yrm,          TB_ALIGN_NONE },
2220     { X86::VFMSUBPD4Yrr,          X86::VFMSUBPD4Yrm,          TB_ALIGN_NONE },
2221     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
2222     { X86::VFNMSUBSS4rr_Int,      X86::VFNMSUBSS4rm_Int,      TB_NO_REVERSE },
2223     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
2224     { X86::VFNMSUBSD4rr_Int,      X86::VFNMSUBSD4rm_Int,      TB_NO_REVERSE },
2225     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
2226     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
2227     { X86::VFNMSUBPS4Yrr,         X86::VFNMSUBPS4Yrm,         TB_ALIGN_NONE },
2228     { X86::VFNMSUBPD4Yrr,         X86::VFNMSUBPD4Yrm,         TB_ALIGN_NONE },
2229     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
2230     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
2231     { X86::VFMADDSUBPS4Yrr,       X86::VFMADDSUBPS4Yrm,       TB_ALIGN_NONE },
2232     { X86::VFMADDSUBPD4Yrr,       X86::VFMADDSUBPD4Yrm,       TB_ALIGN_NONE },
2233     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
2234     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
2235     { X86::VFMSUBADDPS4Yrr,       X86::VFMSUBADDPS4Yrm,       TB_ALIGN_NONE },
2236     { X86::VFMSUBADDPD4Yrr,       X86::VFMSUBADDPD4Yrm,       TB_ALIGN_NONE },
2237 
2238     // XOP foldable instructions
2239     { X86::VPCMOVrrr,             X86::VPCMOVrrm,             0 },
2240     { X86::VPCMOVrrrY,            X86::VPCMOVrrmY,            0 },
2241     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
2242     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
2243     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
2244     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
2245     { X86::VPPERMrrr,             X86::VPPERMrrm,             0 },
2246 
2247     // AVX-512 instructions with 3 source operands.
2248     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
2249     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
2250     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
2251     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
2252     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
2253     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
2254     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
2255     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
2256     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
2257     { X86::VPERMI2Brr,            X86::VPERMI2Brm,            0 },
2258     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
2259     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
2260     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
2261     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
2262     { X86::VPERMI2Wrr,            X86::VPERMI2Wrm,            0 },
2263     { X86::VPERMT2Brr,            X86::VPERMT2Brm,            0 },
2264     { X86::VPERMT2Drr,            X86::VPERMT2Drm,            0 },
2265     { X86::VPERMT2PSrr,           X86::VPERMT2PSrm,           0 },
2266     { X86::VPERMT2PDrr,           X86::VPERMT2PDrm,           0 },
2267     { X86::VPERMT2Qrr,            X86::VPERMT2Qrm,            0 },
2268     { X86::VPERMT2Wrr,            X86::VPERMT2Wrm,            0 },
2269     { X86::VPTERNLOGDZrri,        X86::VPTERNLOGDZrmi,        0 },
2270     { X86::VPTERNLOGQZrri,        X86::VPTERNLOGQZrmi,        0 },
2271 
2272     // AVX-512VL 256-bit instructions with 3 source operands.
2273     { X86::VPERMI2B256rr,         X86::VPERMI2B256rm,         0 },
2274     { X86::VPERMI2D256rr,         X86::VPERMI2D256rm,         0 },
2275     { X86::VPERMI2PD256rr,        X86::VPERMI2PD256rm,        0 },
2276     { X86::VPERMI2PS256rr,        X86::VPERMI2PS256rm,        0 },
2277     { X86::VPERMI2Q256rr,         X86::VPERMI2Q256rm,         0 },
2278     { X86::VPERMI2W256rr,         X86::VPERMI2W256rm,         0 },
2279     { X86::VPERMT2B256rr,         X86::VPERMT2B256rm,         0 },
2280     { X86::VPERMT2D256rr,         X86::VPERMT2D256rm,         0 },
2281     { X86::VPERMT2PD256rr,        X86::VPERMT2PD256rm,        0 },
2282     { X86::VPERMT2PS256rr,        X86::VPERMT2PS256rm,        0 },
2283     { X86::VPERMT2Q256rr,         X86::VPERMT2Q256rm,         0 },
2284     { X86::VPERMT2W256rr,         X86::VPERMT2W256rm,         0 },
2285     { X86::VPTERNLOGDZ256rri,     X86::VPTERNLOGDZ256rmi,     0 },
2286     { X86::VPTERNLOGQZ256rri,     X86::VPTERNLOGQZ256rmi,     0 },
2287 
2288     // AVX-512VL 128-bit instructions with 3 source operands.
2289     { X86::VPERMI2B128rr,         X86::VPERMI2B128rm,         0 },
2290     { X86::VPERMI2D128rr,         X86::VPERMI2D128rm,         0 },
2291     { X86::VPERMI2PD128rr,        X86::VPERMI2PD128rm,        0 },
2292     { X86::VPERMI2PS128rr,        X86::VPERMI2PS128rm,        0 },
2293     { X86::VPERMI2Q128rr,         X86::VPERMI2Q128rm,         0 },
2294     { X86::VPERMI2W128rr,         X86::VPERMI2W128rm,         0 },
2295     { X86::VPERMT2B128rr,         X86::VPERMT2B128rm,         0 },
2296     { X86::VPERMT2D128rr,         X86::VPERMT2D128rm,         0 },
2297     { X86::VPERMT2PD128rr,        X86::VPERMT2PD128rm,        0 },
2298     { X86::VPERMT2PS128rr,        X86::VPERMT2PS128rm,        0 },
2299     { X86::VPERMT2Q128rr,         X86::VPERMT2Q128rm,         0 },
2300     { X86::VPERMT2W128rr,         X86::VPERMT2W128rm,         0 },
2301     { X86::VPTERNLOGDZ128rri,     X86::VPTERNLOGDZ128rmi,     0 },
2302     { X86::VPTERNLOGQZ128rri,     X86::VPTERNLOGQZ128rmi,     0 },
2303 
2304     // AVX-512 masked instructions
2305     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
2306     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
2307     { X86::VANDNPDZrrkz,          X86::VANDNPDZrmkz,          0 },
2308     { X86::VANDNPSZrrkz,          X86::VANDNPSZrmkz,          0 },
2309     { X86::VANDPDZrrkz,           X86::VANDPDZrmkz,           0 },
2310     { X86::VANDPSZrrkz,           X86::VANDPSZrmkz,           0 },
2311     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
2312     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
2313     { X86::VINSERTF32x4Zrrkz,     X86::VINSERTF32x4Zrmkz,     0 },
2314     { X86::VINSERTF32x8Zrrkz,     X86::VINSERTF32x8Zrmkz,     0 },
2315     { X86::VINSERTF64x2Zrrkz,     X86::VINSERTF64x2Zrmkz,     0 },
2316     { X86::VINSERTF64x4Zrrkz,     X86::VINSERTF64x4Zrmkz,     0 },
2317     { X86::VINSERTI32x4Zrrkz,     X86::VINSERTI32x4Zrmkz,     0 },
2318     { X86::VINSERTI32x8Zrrkz,     X86::VINSERTI32x8Zrmkz,     0 },
2319     { X86::VINSERTI64x2Zrrkz,     X86::VINSERTI64x2Zrmkz,     0 },
2320     { X86::VINSERTI64x4Zrrkz,     X86::VINSERTI64x4Zrmkz,     0 },
2321     { X86::VMAXCPDZrrkz,          X86::VMAXCPDZrmkz,          0 },
2322     { X86::VMAXCPSZrrkz,          X86::VMAXCPSZrmkz,          0 },
2323     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
2324     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
2325     { X86::VMINCPDZrrkz,          X86::VMINCPDZrmkz,          0 },
2326     { X86::VMINCPSZrrkz,          X86::VMINCPSZrmkz,          0 },
2327     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
2328     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
2329     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
2330     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
2331     { X86::VORPDZrrkz,            X86::VORPDZrmkz,            0 },
2332     { X86::VORPSZrrkz,            X86::VORPSZrmkz,            0 },
2333     { X86::VPADDBZrrkz,           X86::VPADDBZrmkz,           0 },
2334     { X86::VPADDDZrrkz,           X86::VPADDDZrmkz,           0 },
2335     { X86::VPADDQZrrkz,           X86::VPADDQZrmkz,           0 },
2336     { X86::VPADDSBZrrkz,          X86::VPADDSBZrmkz,          0 },
2337     { X86::VPADDSWZrrkz,          X86::VPADDSWZrmkz,          0 },
2338     { X86::VPADDUSBZrrkz,         X86::VPADDUSBZrmkz,         0 },
2339     { X86::VPADDUSWZrrkz,         X86::VPADDUSWZrmkz,         0 },
2340     { X86::VPADDWZrrkz,           X86::VPADDWZrmkz,           0 },
2341     { X86::VPANDDZrrkz,           X86::VPANDDZrmkz,           0 },
2342     { X86::VPANDNDZrrkz,          X86::VPANDNDZrmkz,          0 },
2343     { X86::VPANDNQZrrkz,          X86::VPANDNQZrmkz,          0 },
2344     { X86::VPANDQZrrkz,           X86::VPANDQZrmkz,           0 },
2345     { X86::VPERMBZrrkz,           X86::VPERMBZrmkz,           0 },
2346     { X86::VPERMDZrrkz,           X86::VPERMDZrmkz,           0 },
2347     { X86::VPERMPDZrrkz,          X86::VPERMPDZrmkz,          0 },
2348     { X86::VPERMPSZrrkz,          X86::VPERMPSZrmkz,          0 },
2349     { X86::VPERMQZrrkz,           X86::VPERMQZrmkz,           0 },
2350     { X86::VPERMWZrrkz,           X86::VPERMWZrmkz,           0 },
2351     { X86::VPMADDUBSWZrrkz,       X86::VPMADDUBSWZrmkz,       0 },
2352     { X86::VPMADDWDZrrkz,         X86::VPMADDWDZrmkz,         0 },
2353     { X86::VPORDZrrkz,            X86::VPORDZrmkz,            0 },
2354     { X86::VPORQZrrkz,            X86::VPORQZrmkz,            0 },
2355     { X86::VPSHUFBZrrkz,          X86::VPSHUFBZrmkz,          0 },
2356     { X86::VPSUBBZrrkz,           X86::VPSUBBZrmkz,           0 },
2357     { X86::VPSUBDZrrkz,           X86::VPSUBDZrmkz,           0 },
2358     { X86::VPSUBQZrrkz,           X86::VPSUBQZrmkz,           0 },
2359     { X86::VPSUBSBZrrkz,          X86::VPSUBSBZrmkz,          0 },
2360     { X86::VPSUBSWZrrkz,          X86::VPSUBSWZrmkz,          0 },
2361     { X86::VPSUBUSBZrrkz,         X86::VPSUBUSBZrmkz,         0 },
2362     { X86::VPSUBUSWZrrkz,         X86::VPSUBUSWZrmkz,         0 },
2363     { X86::VPSUBWZrrkz,           X86::VPSUBWZrmkz,           0 },
2364     { X86::VPUNPCKHBWZrrkz,       X86::VPUNPCKHBWZrmkz,       0 },
2365     { X86::VPUNPCKHDQZrrkz,       X86::VPUNPCKHDQZrmkz,       0 },
2366     { X86::VPUNPCKHQDQZrrkz,      X86::VPUNPCKHQDQZrmkz,      0 },
2367     { X86::VPUNPCKHWDZrrkz,       X86::VPUNPCKHWDZrmkz,       0 },
2368     { X86::VPUNPCKLBWZrrkz,       X86::VPUNPCKLBWZrmkz,       0 },
2369     { X86::VPUNPCKLDQZrrkz,       X86::VPUNPCKLDQZrmkz,       0 },
2370     { X86::VPUNPCKLQDQZrrkz,      X86::VPUNPCKLQDQZrmkz,      0 },
2371     { X86::VPUNPCKLWDZrrkz,       X86::VPUNPCKLWDZrmkz,       0 },
2372     { X86::VPXORDZrrkz,           X86::VPXORDZrmkz,           0 },
2373     { X86::VPXORQZrrkz,           X86::VPXORQZrmkz,           0 },
2374     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
2375     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
2376     { X86::VUNPCKHPDZrrkz,        X86::VUNPCKHPDZrmkz,        0 },
2377     { X86::VUNPCKHPSZrrkz,        X86::VUNPCKHPSZrmkz,        0 },
2378     { X86::VUNPCKLPDZrrkz,        X86::VUNPCKLPDZrmkz,        0 },
2379     { X86::VUNPCKLPSZrrkz,        X86::VUNPCKLPSZrmkz,        0 },
2380     { X86::VXORPDZrrkz,           X86::VXORPDZrmkz,           0 },
2381     { X86::VXORPSZrrkz,           X86::VXORPSZrmkz,           0 },
2382 
2383     // AVX-512{F,VL} masked arithmetic instructions 256-bit
2384     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
2385     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
2386     { X86::VANDNPDZ256rrkz,       X86::VANDNPDZ256rmkz,       0 },
2387     { X86::VANDNPSZ256rrkz,       X86::VANDNPSZ256rmkz,       0 },
2388     { X86::VANDPDZ256rrkz,        X86::VANDPDZ256rmkz,        0 },
2389     { X86::VANDPSZ256rrkz,        X86::VANDPSZ256rmkz,        0 },
2390     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
2391     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
2392     { X86::VINSERTF32x4Z256rrkz,  X86::VINSERTF32x4Z256rmkz,  0 },
2393     { X86::VINSERTF64x2Z256rrkz,  X86::VINSERTF64x2Z256rmkz,  0 },
2394     { X86::VINSERTI32x4Z256rrkz,  X86::VINSERTI32x4Z256rmkz,  0 },
2395     { X86::VINSERTI64x2Z256rrkz,  X86::VINSERTI64x2Z256rmkz,  0 },
2396     { X86::VMAXCPDZ256rrkz,       X86::VMAXCPDZ256rmkz,       0 },
2397     { X86::VMAXCPSZ256rrkz,       X86::VMAXCPSZ256rmkz,       0 },
2398     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
2399     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
2400     { X86::VMINCPDZ256rrkz,       X86::VMINCPDZ256rmkz,       0 },
2401     { X86::VMINCPSZ256rrkz,       X86::VMINCPSZ256rmkz,       0 },
2402     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
2403     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
2404     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
2405     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
2406     { X86::VORPDZ256rrkz,         X86::VORPDZ256rmkz,         0 },
2407     { X86::VORPSZ256rrkz,         X86::VORPSZ256rmkz,         0 },
2408     { X86::VPADDBZ256rrkz,        X86::VPADDBZ256rmkz,        0 },
2409     { X86::VPADDDZ256rrkz,        X86::VPADDDZ256rmkz,        0 },
2410     { X86::VPADDQZ256rrkz,        X86::VPADDQZ256rmkz,        0 },
2411     { X86::VPADDSBZ256rrkz,       X86::VPADDSBZ256rmkz,       0 },
2412     { X86::VPADDSWZ256rrkz,       X86::VPADDSWZ256rmkz,       0 },
2413     { X86::VPADDUSBZ256rrkz,      X86::VPADDUSBZ256rmkz,      0 },
2414     { X86::VPADDUSWZ256rrkz,      X86::VPADDUSWZ256rmkz,      0 },
2415     { X86::VPADDWZ256rrkz,        X86::VPADDWZ256rmkz,        0 },
2416     { X86::VPANDDZ256rrkz,        X86::VPANDDZ256rmkz,        0 },
2417     { X86::VPANDNDZ256rrkz,       X86::VPANDNDZ256rmkz,       0 },
2418     { X86::VPANDNQZ256rrkz,       X86::VPANDNQZ256rmkz,       0 },
2419     { X86::VPANDQZ256rrkz,        X86::VPANDQZ256rmkz,        0 },
2420     { X86::VPERMBZ256rrkz,        X86::VPERMBZ256rmkz,        0 },
2421     { X86::VPERMDZ256rrkz,        X86::VPERMDZ256rmkz,        0 },
2422     { X86::VPERMPDZ256rrkz,       X86::VPERMPDZ256rmkz,       0 },
2423     { X86::VPERMPSZ256rrkz,       X86::VPERMPSZ256rmkz,       0 },
2424     { X86::VPERMQZ256rrkz,        X86::VPERMQZ256rmkz,        0 },
2425     { X86::VPERMWZ256rrkz,        X86::VPERMWZ256rmkz,        0 },
2426     { X86::VPMADDUBSWZ256rrkz,    X86::VPMADDUBSWZ256rmkz,    0 },
2427     { X86::VPMADDWDZ256rrkz,      X86::VPMADDWDZ256rmkz,      0 },
2428     { X86::VPORDZ256rrkz,         X86::VPORDZ256rmkz,         0 },
2429     { X86::VPORQZ256rrkz,         X86::VPORQZ256rmkz,         0 },
2430     { X86::VPSHUFBZ256rrkz,       X86::VPSHUFBZ256rmkz,       0 },
2431     { X86::VPSUBBZ256rrkz,        X86::VPSUBBZ256rmkz,        0 },
2432     { X86::VPSUBDZ256rrkz,        X86::VPSUBDZ256rmkz,        0 },
2433     { X86::VPSUBQZ256rrkz,        X86::VPSUBQZ256rmkz,        0 },
2434     { X86::VPSUBSBZ256rrkz,       X86::VPSUBSBZ256rmkz,       0 },
2435     { X86::VPSUBSWZ256rrkz,       X86::VPSUBSWZ256rmkz,       0 },
2436     { X86::VPSUBUSBZ256rrkz,      X86::VPSUBUSBZ256rmkz,      0 },
2437     { X86::VPSUBUSWZ256rrkz,      X86::VPSUBUSWZ256rmkz,      0 },
2438     { X86::VPSUBWZ256rrkz,        X86::VPSUBWZ256rmkz,        0 },
2439     { X86::VPUNPCKHBWZ256rrkz,    X86::VPUNPCKHBWZ256rmkz,    0 },
2440     { X86::VPUNPCKHDQZ256rrkz,    X86::VPUNPCKHDQZ256rmkz,    0 },
2441     { X86::VPUNPCKHQDQZ256rrkz,   X86::VPUNPCKHQDQZ256rmkz,   0 },
2442     { X86::VPUNPCKHWDZ256rrkz,    X86::VPUNPCKHWDZ256rmkz,    0 },
2443     { X86::VPUNPCKLBWZ256rrkz,    X86::VPUNPCKLBWZ256rmkz,    0 },
2444     { X86::VPUNPCKLDQZ256rrkz,    X86::VPUNPCKLDQZ256rmkz,    0 },
2445     { X86::VPUNPCKLQDQZ256rrkz,   X86::VPUNPCKLQDQZ256rmkz,   0 },
2446     { X86::VPUNPCKLWDZ256rrkz,    X86::VPUNPCKLWDZ256rmkz,    0 },
2447     { X86::VPXORDZ256rrkz,        X86::VPXORDZ256rmkz,        0 },
2448     { X86::VPXORQZ256rrkz,        X86::VPXORQZ256rmkz,        0 },
2449     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
2450     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
2451     { X86::VUNPCKHPDZ256rrkz,     X86::VUNPCKHPDZ256rmkz,     0 },
2452     { X86::VUNPCKHPSZ256rrkz,     X86::VUNPCKHPSZ256rmkz,     0 },
2453     { X86::VUNPCKLPDZ256rrkz,     X86::VUNPCKLPDZ256rmkz,     0 },
2454     { X86::VUNPCKLPSZ256rrkz,     X86::VUNPCKLPSZ256rmkz,     0 },
2455     { X86::VXORPDZ256rrkz,        X86::VXORPDZ256rmkz,        0 },
2456     { X86::VXORPSZ256rrkz,        X86::VXORPSZ256rmkz,        0 },
2457 
2458     // AVX-512{F,VL} masked arithmetic instructions 128-bit
2459     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
2460     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
2461     { X86::VANDNPDZ128rrkz,       X86::VANDNPDZ128rmkz,       0 },
2462     { X86::VANDNPSZ128rrkz,       X86::VANDNPSZ128rmkz,       0 },
2463     { X86::VANDPDZ128rrkz,        X86::VANDPDZ128rmkz,        0 },
2464     { X86::VANDPSZ128rrkz,        X86::VANDPSZ128rmkz,        0 },
2465     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
2466     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
2467     { X86::VMAXCPDZ128rrkz,       X86::VMAXCPDZ128rmkz,       0 },
2468     { X86::VMAXCPSZ128rrkz,       X86::VMAXCPSZ128rmkz,       0 },
2469     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 },
2470     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
2471     { X86::VMINCPDZ128rrkz,       X86::VMINCPDZ128rmkz,       0 },
2472     { X86::VMINCPSZ128rrkz,       X86::VMINCPSZ128rmkz,       0 },
2473     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
2474     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
2475     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
2476     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
2477     { X86::VORPDZ128rrkz,         X86::VORPDZ128rmkz,         0 },
2478     { X86::VORPSZ128rrkz,         X86::VORPSZ128rmkz,         0 },
2479     { X86::VPADDBZ128rrkz,        X86::VPADDBZ128rmkz,        0 },
2480     { X86::VPADDDZ128rrkz,        X86::VPADDDZ128rmkz,        0 },
2481     { X86::VPADDQZ128rrkz,        X86::VPADDQZ128rmkz,        0 },
2482     { X86::VPADDSBZ128rrkz,       X86::VPADDSBZ128rmkz,       0 },
2483     { X86::VPADDSWZ128rrkz,       X86::VPADDSWZ128rmkz,       0 },
2484     { X86::VPADDUSBZ128rrkz,      X86::VPADDUSBZ128rmkz,      0 },
2485     { X86::VPADDUSWZ128rrkz,      X86::VPADDUSWZ128rmkz,      0 },
2486     { X86::VPADDWZ128rrkz,        X86::VPADDWZ128rmkz,        0 },
2487     { X86::VPANDDZ128rrkz,        X86::VPANDDZ128rmkz,        0 },
2488     { X86::VPANDNDZ128rrkz,       X86::VPANDNDZ128rmkz,       0 },
2489     { X86::VPANDNQZ128rrkz,       X86::VPANDNQZ128rmkz,       0 },
2490     { X86::VPANDQZ128rrkz,        X86::VPANDQZ128rmkz,        0 },
2491     { X86::VPERMBZ128rrkz,        X86::VPERMBZ128rmkz,        0 },
2492     { X86::VPERMWZ128rrkz,        X86::VPERMWZ128rmkz,        0 },
2493     { X86::VPMADDUBSWZ128rrkz,    X86::VPMADDUBSWZ128rmkz,    0 },
2494     { X86::VPMADDWDZ128rrkz,      X86::VPMADDWDZ128rmkz,      0 },
2495     { X86::VPORDZ128rrkz,         X86::VPORDZ128rmkz,         0 },
2496     { X86::VPORQZ128rrkz,         X86::VPORQZ128rmkz,         0 },
2497     { X86::VPSHUFBZ128rrkz,       X86::VPSHUFBZ128rmkz,       0 },
2498     { X86::VPSUBBZ128rrkz,        X86::VPSUBBZ128rmkz,        0 },
2499     { X86::VPSUBDZ128rrkz,        X86::VPSUBDZ128rmkz,        0 },
2500     { X86::VPSUBQZ128rrkz,        X86::VPSUBQZ128rmkz,        0 },
2501     { X86::VPSUBSBZ128rrkz,       X86::VPSUBSBZ128rmkz,       0 },
2502     { X86::VPSUBSWZ128rrkz,       X86::VPSUBSWZ128rmkz,       0 },
2503     { X86::VPSUBUSBZ128rrkz,      X86::VPSUBUSBZ128rmkz,      0 },
2504     { X86::VPSUBUSWZ128rrkz,      X86::VPSUBUSWZ128rmkz,      0 },
2505     { X86::VPSUBWZ128rrkz,        X86::VPSUBWZ128rmkz,        0 },
2506     { X86::VPUNPCKHBWZ128rrkz,    X86::VPUNPCKHBWZ128rmkz,    0 },
2507     { X86::VPUNPCKHDQZ128rrkz,    X86::VPUNPCKHDQZ128rmkz,    0 },
2508     { X86::VPUNPCKHQDQZ128rrkz,   X86::VPUNPCKHQDQZ128rmkz,   0 },
2509     { X86::VPUNPCKHWDZ128rrkz,    X86::VPUNPCKHWDZ128rmkz,    0 },
2510     { X86::VPUNPCKLBWZ128rrkz,    X86::VPUNPCKLBWZ128rmkz,    0 },
2511     { X86::VPUNPCKLDQZ128rrkz,    X86::VPUNPCKLDQZ128rmkz,    0 },
2512     { X86::VPUNPCKLQDQZ128rrkz,   X86::VPUNPCKLQDQZ128rmkz,   0 },
2513     { X86::VPUNPCKLWDZ128rrkz,    X86::VPUNPCKLWDZ128rmkz,    0 },
2514     { X86::VPXORDZ128rrkz,        X86::VPXORDZ128rmkz,        0 },
2515     { X86::VPXORQZ128rrkz,        X86::VPXORQZ128rmkz,        0 },
2516     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
2517     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
2518     { X86::VUNPCKHPDZ128rrkz,     X86::VUNPCKHPDZ128rmkz,     0 },
2519     { X86::VUNPCKHPSZ128rrkz,     X86::VUNPCKHPSZ128rmkz,     0 },
2520     { X86::VUNPCKLPDZ128rrkz,     X86::VUNPCKLPDZ128rmkz,     0 },
2521     { X86::VUNPCKLPSZ128rrkz,     X86::VUNPCKLPSZ128rmkz,     0 },
2522     { X86::VXORPDZ128rrkz,        X86::VXORPDZ128rmkz,        0 },
2523     { X86::VXORPSZ128rrkz,        X86::VXORPSZ128rmkz,        0 },
2524 
2525     // AVX-512 masked foldable instructions
2526     { X86::VPERMPDZrik,           X86::VPERMPDZmik,           0 },
2527     { X86::VPERMQZrik,            X86::VPERMQZmik,            0 },
2528     { X86::VPMOVSXBDZrrk,         X86::VPMOVSXBDZrmk,         0 },
2529     { X86::VPMOVSXBQZrrk,         X86::VPMOVSXBQZrmk,         TB_NO_REVERSE },
2530     { X86::VPMOVSXBWZrrk,         X86::VPMOVSXBWZrmk,         0 },
2531     { X86::VPMOVSXDQZrrk,         X86::VPMOVSXDQZrmk,         0 },
2532     { X86::VPMOVSXWDZrrk,         X86::VPMOVSXWDZrmk,         0 },
2533     { X86::VPMOVSXWQZrrk,         X86::VPMOVSXWQZrmk,         0 },
2534     { X86::VPMOVZXBDZrrk,         X86::VPMOVZXBDZrmk,         0 },
2535     { X86::VPMOVZXBQZrrk,         X86::VPMOVZXBQZrmk,         TB_NO_REVERSE },
2536     { X86::VPMOVZXBWZrrk,         X86::VPMOVZXBWZrmk,         0 },
2537     { X86::VPMOVZXDQZrrk,         X86::VPMOVZXDQZrmk,         0 },
2538     { X86::VPMOVZXWDZrrk,         X86::VPMOVZXWDZrmk,         0 },
2539     { X86::VPMOVZXWQZrrk,         X86::VPMOVZXWQZrmk,         0 },
2540     { X86::VPSHUFDZrik,           X86::VPSHUFDZmik,           0 },
2541     { X86::VPSHUFHWZrik,          X86::VPSHUFHWZmik,          0 },
2542     { X86::VPSHUFLWZrik,          X86::VPSHUFLWZmik,          0 },
2543 
2544     // AVX-512VL 256-bit masked foldable instructions
2545     { X86::VPERMPDZ256rik,        X86::VPERMPDZ256mik,        0 },
2546     { X86::VPERMQZ256rik,         X86::VPERMQZ256mik,         0 },
2547     { X86::VPMOVSXBDZ256rrk,      X86::VPMOVSXBDZ256rmk,      TB_NO_REVERSE },
2548     { X86::VPMOVSXBQZ256rrk,      X86::VPMOVSXBQZ256rmk,      TB_NO_REVERSE },
2549     { X86::VPMOVSXBWZ256rrk,      X86::VPMOVSXBWZ256rmk,      0 },
2550     { X86::VPMOVSXDQZ256rrk,      X86::VPMOVSXDQZ256rmk,      0 },
2551     { X86::VPMOVSXWDZ256rrk,      X86::VPMOVSXWDZ256rmk,      0 },
2552     { X86::VPMOVSXWQZ256rrk,      X86::VPMOVSXWQZ256rmk,      TB_NO_REVERSE },
2553     { X86::VPMOVZXBDZ256rrk,      X86::VPMOVZXBDZ256rmk,      TB_NO_REVERSE },
2554     { X86::VPMOVZXBQZ256rrk,      X86::VPMOVZXBQZ256rmk,      TB_NO_REVERSE },
2555     { X86::VPMOVZXBWZ256rrk,      X86::VPMOVZXBWZ256rmk,      0 },
2556     { X86::VPMOVZXDQZ256rrk,      X86::VPMOVZXDQZ256rmk,      0 },
2557     { X86::VPMOVZXWDZ256rrk,      X86::VPMOVZXWDZ256rmk,      0 },
2558     { X86::VPMOVZXWQZ256rrk,      X86::VPMOVZXWQZ256rmk,      TB_NO_REVERSE },
2559     { X86::VPSHUFDZ256rik,        X86::VPSHUFDZ256mik,        0 },
2560     { X86::VPSHUFHWZ256rik,       X86::VPSHUFHWZ256mik,       0 },
2561     { X86::VPSHUFLWZ256rik,       X86::VPSHUFLWZ256mik,       0 },
2562 
2563     // AVX-512VL 128-bit masked foldable instructions
2564     { X86::VPMOVSXBDZ128rrk,      X86::VPMOVSXBDZ128rmk,      TB_NO_REVERSE },
2565     { X86::VPMOVSXBQZ128rrk,      X86::VPMOVSXBQZ128rmk,      TB_NO_REVERSE },
2566     { X86::VPMOVSXBWZ128rrk,      X86::VPMOVSXBWZ128rmk,      TB_NO_REVERSE },
2567     { X86::VPMOVSXDQZ128rrk,      X86::VPMOVSXDQZ128rmk,      TB_NO_REVERSE },
2568     { X86::VPMOVSXWDZ128rrk,      X86::VPMOVSXWDZ128rmk,      TB_NO_REVERSE },
2569     { X86::VPMOVSXWQZ128rrk,      X86::VPMOVSXWQZ128rmk,      TB_NO_REVERSE },
2570     { X86::VPMOVZXBDZ128rrk,      X86::VPMOVZXBDZ128rmk,      TB_NO_REVERSE },
2571     { X86::VPMOVZXBQZ128rrk,      X86::VPMOVZXBQZ128rmk,      TB_NO_REVERSE },
2572     { X86::VPMOVZXBWZ128rrk,      X86::VPMOVZXBWZ128rmk,      TB_NO_REVERSE },
2573     { X86::VPMOVZXDQZ128rrk,      X86::VPMOVZXDQZ128rmk,      TB_NO_REVERSE },
2574     { X86::VPMOVZXWDZ128rrk,      X86::VPMOVZXWDZ128rmk,      TB_NO_REVERSE },
2575     { X86::VPMOVZXWQZ128rrk,      X86::VPMOVZXWQZ128rmk,      TB_NO_REVERSE },
2576     { X86::VPSHUFDZ128rik,        X86::VPSHUFDZ128mik,        0 },
2577     { X86::VPSHUFHWZ128rik,       X86::VPSHUFHWZ128mik,       0 },
2578     { X86::VPSHUFLWZ128rik,       X86::VPSHUFLWZ128mik,       0 },
2579   };
2580 
2581   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
2582     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2583                   Entry.RegOp, Entry.MemOp,
2584                   // Index 3, folded load
2585                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
2586   }
2587   auto I = X86InstrFMA3Info::rm_begin();
2588   auto E = X86InstrFMA3Info::rm_end();
2589   for (; I != E; ++I) {
2590     if (!I.getGroup()->isKMasked()) {
2591       // Intrinsic forms need to pass TB_NO_REVERSE.
2592       if (I.getGroup()->isIntrinsic()) {
2593         AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2594                       I.getRegOpcode(), I.getMemOpcode(),
2595                       TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD | TB_NO_REVERSE);
2596       } else {
2597         AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2598                       I.getRegOpcode(), I.getMemOpcode(),
2599                       TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD);
2600       }
2601     }
2602   }
2603 
2604   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
2605     // AVX-512 foldable masked instructions
2606     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
2607     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
2608     { X86::VANDNPDZrrk,        X86::VANDNPDZrmk,          0 },
2609     { X86::VANDNPSZrrk,        X86::VANDNPSZrmk,          0 },
2610     { X86::VANDPDZrrk,         X86::VANDPDZrmk,           0 },
2611     { X86::VANDPSZrrk,         X86::VANDPSZrmk,           0 },
2612     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
2613     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
2614     { X86::VINSERTF32x4Zrrk,   X86::VINSERTF32x4Zrmk,     0 },
2615     { X86::VINSERTF32x8Zrrk,   X86::VINSERTF32x8Zrmk,     0 },
2616     { X86::VINSERTF64x2Zrrk,   X86::VINSERTF64x2Zrmk,     0 },
2617     { X86::VINSERTF64x4Zrrk,   X86::VINSERTF64x4Zrmk,     0 },
2618     { X86::VINSERTI32x4Zrrk,   X86::VINSERTI32x4Zrmk,     0 },
2619     { X86::VINSERTI32x8Zrrk,   X86::VINSERTI32x8Zrmk,     0 },
2620     { X86::VINSERTI64x2Zrrk,   X86::VINSERTI64x2Zrmk,     0 },
2621     { X86::VINSERTI64x4Zrrk,   X86::VINSERTI64x4Zrmk,     0 },
2622     { X86::VMAXCPDZrrk,        X86::VMAXCPDZrmk,          0 },
2623     { X86::VMAXCPSZrrk,        X86::VMAXCPSZrmk,          0 },
2624     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
2625     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
2626     { X86::VMINCPDZrrk,        X86::VMINCPDZrmk,          0 },
2627     { X86::VMINCPSZrrk,        X86::VMINCPSZrmk,          0 },
2628     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
2629     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
2630     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
2631     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
2632     { X86::VORPDZrrk,          X86::VORPDZrmk,            0 },
2633     { X86::VORPSZrrk,          X86::VORPSZrmk,            0 },
2634     { X86::VPADDBZrrk,         X86::VPADDBZrmk,           0 },
2635     { X86::VPADDDZrrk,         X86::VPADDDZrmk,           0 },
2636     { X86::VPADDQZrrk,         X86::VPADDQZrmk,           0 },
2637     { X86::VPADDSBZrrk,        X86::VPADDSBZrmk,          0 },
2638     { X86::VPADDSWZrrk,        X86::VPADDSWZrmk,          0 },
2639     { X86::VPADDUSBZrrk,       X86::VPADDUSBZrmk,         0 },
2640     { X86::VPADDUSWZrrk,       X86::VPADDUSWZrmk,         0 },
2641     { X86::VPADDWZrrk,         X86::VPADDWZrmk,           0 },
2642     { X86::VPANDDZrrk,         X86::VPANDDZrmk,           0 },
2643     { X86::VPANDNDZrrk,        X86::VPANDNDZrmk,          0 },
2644     { X86::VPANDNQZrrk,        X86::VPANDNQZrmk,          0 },
2645     { X86::VPANDQZrrk,         X86::VPANDQZrmk,           0 },
2646     { X86::VPERMBZrrk,         X86::VPERMBZrmk,           0 },
2647     { X86::VPERMDZrrk,         X86::VPERMDZrmk,           0 },
2648     { X86::VPERMPDZrrk,        X86::VPERMPDZrmk,          0 },
2649     { X86::VPERMPSZrrk,        X86::VPERMPSZrmk,          0 },
2650     { X86::VPERMQZrrk,         X86::VPERMQZrmk,           0 },
2651     { X86::VPERMWZrrk,         X86::VPERMWZrmk,           0 },
2652     { X86::VPMADDUBSWZrrk,     X86::VPMADDUBSWZrmk,       0 },
2653     { X86::VPMADDWDZrrk,       X86::VPMADDWDZrmk,         0 },
2654     { X86::VPORDZrrk,          X86::VPORDZrmk,            0 },
2655     { X86::VPORQZrrk,          X86::VPORQZrmk,            0 },
2656     { X86::VPSHUFBZrrk,        X86::VPSHUFBZrmk,          0 },
2657     { X86::VPSUBBZrrk,         X86::VPSUBBZrmk,           0 },
2658     { X86::VPSUBDZrrk,         X86::VPSUBDZrmk,           0 },
2659     { X86::VPSUBQZrrk,         X86::VPSUBQZrmk,           0 },
2660     { X86::VPSUBSBZrrk,        X86::VPSUBSBZrmk,          0 },
2661     { X86::VPSUBSWZrrk,        X86::VPSUBSWZrmk,          0 },
2662     { X86::VPSUBUSBZrrk,       X86::VPSUBUSBZrmk,         0 },
2663     { X86::VPSUBUSWZrrk,       X86::VPSUBUSWZrmk,         0 },
2664     { X86::VPTERNLOGDZrrik,    X86::VPTERNLOGDZrmik,      0 },
2665     { X86::VPTERNLOGDZrrikz,   X86::VPTERNLOGDZrmikz,     0 },
2666     { X86::VPTERNLOGQZrrik,    X86::VPTERNLOGQZrmik,      0 },
2667     { X86::VPTERNLOGQZrrikz,   X86::VPTERNLOGQZrmikz,     0 },
2668     { X86::VPUNPCKHBWZrrk,     X86::VPUNPCKHBWZrmk,       0 },
2669     { X86::VPUNPCKHDQZrrk,     X86::VPUNPCKHDQZrmk,       0 },
2670     { X86::VPUNPCKHQDQZrrk,    X86::VPUNPCKHQDQZrmk,      0 },
2671     { X86::VPUNPCKHWDZrrk,     X86::VPUNPCKHWDZrmk,       0 },
2672     { X86::VPUNPCKLBWZrrk,     X86::VPUNPCKLBWZrmk,       0 },
2673     { X86::VPUNPCKLDQZrrk,     X86::VPUNPCKLDQZrmk,       0 },
2674     { X86::VPUNPCKLQDQZrrk,    X86::VPUNPCKLQDQZrmk,      0 },
2675     { X86::VPUNPCKLWDZrrk,     X86::VPUNPCKLWDZrmk,       0 },
2676     { X86::VPXORDZrrk,         X86::VPXORDZrmk,           0 },
2677     { X86::VPXORQZrrk,         X86::VPXORQZrmk,           0 },
2678     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
2679     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
2680     { X86::VUNPCKHPDZrrk,      X86::VUNPCKHPDZrmk,        0 },
2681     { X86::VUNPCKHPSZrrk,      X86::VUNPCKHPSZrmk,        0 },
2682     { X86::VUNPCKLPDZrrk,      X86::VUNPCKLPDZrmk,        0 },
2683     { X86::VUNPCKLPSZrrk,      X86::VUNPCKLPSZrmk,        0 },
2684     { X86::VXORPDZrrk,         X86::VXORPDZrmk,           0 },
2685     { X86::VXORPSZrrk,         X86::VXORPSZrmk,           0 },
2686 
2687     // AVX-512{F,VL} foldable masked instructions 256-bit
2688     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
2689     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
2690     { X86::VANDNPDZ256rrk,     X86::VANDNPDZ256rmk,       0 },
2691     { X86::VANDNPSZ256rrk,     X86::VANDNPSZ256rmk,       0 },
2692     { X86::VANDPDZ256rrk,      X86::VANDPDZ256rmk,        0 },
2693     { X86::VANDPSZ256rrk,      X86::VANDPSZ256rmk,        0 },
2694     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
2695     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
2696     { X86::VINSERTF32x4Z256rrk,X86::VINSERTF32x4Z256rmk,  0 },
2697     { X86::VINSERTF64x2Z256rrk,X86::VINSERTF64x2Z256rmk,  0 },
2698     { X86::VINSERTI32x4Z256rrk,X86::VINSERTI32x4Z256rmk,  0 },
2699     { X86::VINSERTI64x2Z256rrk,X86::VINSERTI64x2Z256rmk,  0 },
2700     { X86::VMAXCPDZ256rrk,     X86::VMAXCPDZ256rmk,       0 },
2701     { X86::VMAXCPSZ256rrk,     X86::VMAXCPSZ256rmk,       0 },
2702     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
2703     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
2704     { X86::VMINCPDZ256rrk,     X86::VMINCPDZ256rmk,       0 },
2705     { X86::VMINCPSZ256rrk,     X86::VMINCPSZ256rmk,       0 },
2706     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
2707     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
2708     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
2709     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
2710     { X86::VORPDZ256rrk,       X86::VORPDZ256rmk,         0 },
2711     { X86::VORPSZ256rrk,       X86::VORPSZ256rmk,         0 },
2712     { X86::VPADDBZ256rrk,      X86::VPADDBZ256rmk,        0 },
2713     { X86::VPADDDZ256rrk,      X86::VPADDDZ256rmk,        0 },
2714     { X86::VPADDQZ256rrk,      X86::VPADDQZ256rmk,        0 },
2715     { X86::VPADDSBZ256rrk,     X86::VPADDSBZ256rmk,       0 },
2716     { X86::VPADDSWZ256rrk,     X86::VPADDSWZ256rmk,       0 },
2717     { X86::VPADDUSBZ256rrk,    X86::VPADDUSBZ256rmk,      0 },
2718     { X86::VPADDUSWZ256rrk,    X86::VPADDUSWZ256rmk,      0 },
2719     { X86::VPADDWZ256rrk,      X86::VPADDWZ256rmk,        0 },
2720     { X86::VPANDDZ256rrk,      X86::VPANDDZ256rmk,        0 },
2721     { X86::VPANDNDZ256rrk,     X86::VPANDNDZ256rmk,       0 },
2722     { X86::VPANDNQZ256rrk,     X86::VPANDNQZ256rmk,       0 },
2723     { X86::VPANDQZ256rrk,      X86::VPANDQZ256rmk,        0 },
2724     { X86::VPERMBZ256rrk,      X86::VPERMBZ256rmk,        0 },
2725     { X86::VPERMDZ256rrk,      X86::VPERMDZ256rmk,        0 },
2726     { X86::VPERMPDZ256rrk,     X86::VPERMPDZ256rmk,       0 },
2727     { X86::VPERMPSZ256rrk,     X86::VPERMPSZ256rmk,       0 },
2728     { X86::VPERMQZ256rrk,      X86::VPERMQZ256rmk,        0 },
2729     { X86::VPERMWZ256rrk,      X86::VPERMWZ256rmk,        0 },
2730     { X86::VPMADDUBSWZ256rrk,  X86::VPMADDUBSWZ256rmk,    0 },
2731     { X86::VPMADDWDZ256rrk,    X86::VPMADDWDZ256rmk,      0 },
2732     { X86::VPORDZ256rrk,       X86::VPORDZ256rmk,         0 },
2733     { X86::VPORQZ256rrk,       X86::VPORQZ256rmk,         0 },
2734     { X86::VPSHUFBZ256rrk,     X86::VPSHUFBZ256rmk,       0 },
2735     { X86::VPSUBBZ256rrk,      X86::VPSUBBZ256rmk,        0 },
2736     { X86::VPSUBDZ256rrk,      X86::VPSUBDZ256rmk,        0 },
2737     { X86::VPSUBQZ256rrk,      X86::VPSUBQZ256rmk,        0 },
2738     { X86::VPSUBSBZ256rrk,     X86::VPSUBSBZ256rmk,       0 },
2739     { X86::VPSUBSWZ256rrk,     X86::VPSUBSWZ256rmk,       0 },
2740     { X86::VPSUBUSBZ256rrk,    X86::VPSUBUSBZ256rmk,      0 },
2741     { X86::VPSUBUSWZ256rrk,    X86::VPSUBUSWZ256rmk,      0 },
2742     { X86::VPSUBWZ256rrk,      X86::VPSUBWZ256rmk,        0 },
2743     { X86::VPTERNLOGDZ256rrik, X86::VPTERNLOGDZ256rmik,   0 },
2744     { X86::VPTERNLOGDZ256rrikz,X86::VPTERNLOGDZ256rmikz,  0 },
2745     { X86::VPTERNLOGQZ256rrik, X86::VPTERNLOGQZ256rmik,   0 },
2746     { X86::VPTERNLOGQZ256rrikz,X86::VPTERNLOGQZ256rmikz,  0 },
2747     { X86::VPUNPCKHBWZ256rrk,  X86::VPUNPCKHBWZ256rmk,    0 },
2748     { X86::VPUNPCKHDQZ256rrk,  X86::VPUNPCKHDQZ256rmk,    0 },
2749     { X86::VPUNPCKHQDQZ256rrk, X86::VPUNPCKHQDQZ256rmk,   0 },
2750     { X86::VPUNPCKHWDZ256rrk,  X86::VPUNPCKHWDZ256rmk,    0 },
2751     { X86::VPUNPCKLBWZ256rrk,  X86::VPUNPCKLBWZ256rmk,    0 },
2752     { X86::VPUNPCKLDQZ256rrk,  X86::VPUNPCKLDQZ256rmk,    0 },
2753     { X86::VPUNPCKLQDQZ256rrk, X86::VPUNPCKLQDQZ256rmk,   0 },
2754     { X86::VPUNPCKLWDZ256rrk,  X86::VPUNPCKLWDZ256rmk,    0 },
2755     { X86::VPXORDZ256rrk,      X86::VPXORDZ256rmk,        0 },
2756     { X86::VPXORQZ256rrk,      X86::VPXORQZ256rmk,        0 },
2757     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
2758     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
2759     { X86::VUNPCKHPDZ256rrk,   X86::VUNPCKHPDZ256rmk,     0 },
2760     { X86::VUNPCKHPSZ256rrk,   X86::VUNPCKHPSZ256rmk,     0 },
2761     { X86::VUNPCKLPDZ256rrk,   X86::VUNPCKLPDZ256rmk,     0 },
2762     { X86::VUNPCKLPSZ256rrk,   X86::VUNPCKLPSZ256rmk,     0 },
2763     { X86::VXORPDZ256rrk,      X86::VXORPDZ256rmk,        0 },
2764     { X86::VXORPSZ256rrk,      X86::VXORPSZ256rmk,        0 },
2765 
2766     // AVX-512{F,VL} foldable instructions 128-bit
2767     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
2768     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
2769     { X86::VANDNPDZ128rrk,     X86::VANDNPDZ128rmk,       0 },
2770     { X86::VANDNPSZ128rrk,     X86::VANDNPSZ128rmk,       0 },
2771     { X86::VANDPDZ128rrk,      X86::VANDPDZ128rmk,        0 },
2772     { X86::VANDPSZ128rrk,      X86::VANDPSZ128rmk,        0 },
2773     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
2774     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
2775     { X86::VMAXCPDZ128rrk,     X86::VMAXCPDZ128rmk,       0 },
2776     { X86::VMAXCPSZ128rrk,     X86::VMAXCPSZ128rmk,       0 },
2777     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 },
2778     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
2779     { X86::VMINCPDZ128rrk,     X86::VMINCPDZ128rmk,       0 },
2780     { X86::VMINCPSZ128rrk,     X86::VMINCPSZ128rmk,       0 },
2781     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
2782     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
2783     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
2784     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
2785     { X86::VORPDZ128rrk,       X86::VORPDZ128rmk,         0 },
2786     { X86::VORPSZ128rrk,       X86::VORPSZ128rmk,         0 },
2787     { X86::VPADDBZ128rrk,      X86::VPADDBZ128rmk,        0 },
2788     { X86::VPADDDZ128rrk,      X86::VPADDDZ128rmk,        0 },
2789     { X86::VPADDQZ128rrk,      X86::VPADDQZ128rmk,        0 },
2790     { X86::VPADDSBZ128rrk,     X86::VPADDSBZ128rmk,       0 },
2791     { X86::VPADDSWZ128rrk,     X86::VPADDSWZ128rmk,       0 },
2792     { X86::VPADDUSBZ128rrk,    X86::VPADDUSBZ128rmk,      0 },
2793     { X86::VPADDUSWZ128rrk,    X86::VPADDUSWZ128rmk,      0 },
2794     { X86::VPADDWZ128rrk,      X86::VPADDWZ128rmk,        0 },
2795     { X86::VPANDDZ128rrk,      X86::VPANDDZ128rmk,        0 },
2796     { X86::VPANDNDZ128rrk,     X86::VPANDNDZ128rmk,       0 },
2797     { X86::VPANDNQZ128rrk,     X86::VPANDNQZ128rmk,       0 },
2798     { X86::VPANDQZ128rrk,      X86::VPANDQZ128rmk,        0 },
2799     { X86::VPERMBZ128rrk,      X86::VPERMBZ128rmk,        0 },
2800     { X86::VPERMWZ128rrk,      X86::VPERMWZ128rmk,        0 },
2801     { X86::VPMADDUBSWZ128rrk,  X86::VPMADDUBSWZ128rmk,    0 },
2802     { X86::VPMADDWDZ128rrk,    X86::VPMADDWDZ128rmk,      0 },
2803     { X86::VPORDZ128rrk,       X86::VPORDZ128rmk,         0 },
2804     { X86::VPORQZ128rrk,       X86::VPORQZ128rmk,         0 },
2805     { X86::VPSHUFBZ128rrk,     X86::VPSHUFBZ128rmk,       0 },
2806     { X86::VPSUBBZ128rrk,      X86::VPSUBBZ128rmk,        0 },
2807     { X86::VPSUBDZ128rrk,      X86::VPSUBDZ128rmk,        0 },
2808     { X86::VPSUBQZ128rrk,      X86::VPSUBQZ128rmk,        0 },
2809     { X86::VPSUBSBZ128rrk,     X86::VPSUBSBZ128rmk,       0 },
2810     { X86::VPSUBSWZ128rrk,     X86::VPSUBSWZ128rmk,       0 },
2811     { X86::VPSUBUSBZ128rrk,    X86::VPSUBUSBZ128rmk,      0 },
2812     { X86::VPSUBUSWZ128rrk,    X86::VPSUBUSWZ128rmk,      0 },
2813     { X86::VPSUBWZ128rrk,      X86::VPSUBWZ128rmk,        0 },
2814     { X86::VPTERNLOGDZ128rrik, X86::VPTERNLOGDZ128rmik,   0 },
2815     { X86::VPTERNLOGDZ128rrikz,X86::VPTERNLOGDZ128rmikz,  0 },
2816     { X86::VPTERNLOGQZ128rrik, X86::VPTERNLOGQZ128rmik,   0 },
2817     { X86::VPTERNLOGQZ128rrikz,X86::VPTERNLOGQZ128rmikz,  0 },
2818     { X86::VPUNPCKHBWZ128rrk,  X86::VPUNPCKHBWZ128rmk,    0 },
2819     { X86::VPUNPCKHDQZ128rrk,  X86::VPUNPCKHDQZ128rmk,    0 },
2820     { X86::VPUNPCKHQDQZ128rrk, X86::VPUNPCKHQDQZ128rmk,   0 },
2821     { X86::VPUNPCKHWDZ128rrk,  X86::VPUNPCKHWDZ128rmk,    0 },
2822     { X86::VPUNPCKLBWZ128rrk,  X86::VPUNPCKLBWZ128rmk,    0 },
2823     { X86::VPUNPCKLDQZ128rrk,  X86::VPUNPCKLDQZ128rmk,    0 },
2824     { X86::VPUNPCKLQDQZ128rrk, X86::VPUNPCKLQDQZ128rmk,   0 },
2825     { X86::VPUNPCKLWDZ128rrk,  X86::VPUNPCKLWDZ128rmk,    0 },
2826     { X86::VPXORDZ128rrk,      X86::VPXORDZ128rmk,        0 },
2827     { X86::VPXORQZ128rrk,      X86::VPXORQZ128rmk,        0 },
2828     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
2829     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
2830     { X86::VUNPCKHPDZ128rrk,   X86::VUNPCKHPDZ128rmk,     0 },
2831     { X86::VUNPCKHPSZ128rrk,   X86::VUNPCKHPSZ128rmk,     0 },
2832     { X86::VUNPCKLPDZ128rrk,   X86::VUNPCKLPDZ128rmk,     0 },
2833     { X86::VUNPCKLPSZ128rrk,   X86::VUNPCKLPSZ128rmk,     0 },
2834     { X86::VXORPDZ128rrk,      X86::VXORPDZ128rmk,        0 },
2835     { X86::VXORPSZ128rrk,      X86::VXORPSZ128rmk,        0 },
2836   };
2837 
2838   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
2839     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2840                   Entry.RegOp, Entry.MemOp,
2841                   // Index 4, folded load
2842                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
2843   }
2844   for (I = X86InstrFMA3Info::rm_begin(); I != E; ++I) {
2845     if (I.getGroup()->isKMasked()) {
2846       // Intrinsics need to pass TB_NO_REVERSE.
2847       if (I.getGroup()->isIntrinsic()) {
2848         AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2849                       I.getRegOpcode(), I.getMemOpcode(),
2850                       TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD | TB_NO_REVERSE);
2851       } else {
2852         AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2853                       I.getRegOpcode(), I.getMemOpcode(),
2854                       TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD);
2855       }
2856     }
2857   }
2858 }
2859 
2860 void
2861 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2862                             MemOp2RegOpTableType &M2RTable,
2863                             uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
2864   if ((Flags & TB_NO_FORWARD) == 0) {
2865     assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2866     R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2867   }
2868   if ((Flags & TB_NO_REVERSE) == 0) {
2869     assert(!M2RTable.count(MemOp) &&
2870          "Duplicated entries in unfolding maps?");
2871     M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2872   }
2873 }
2874 
2875 bool
2876 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2877                                     unsigned &SrcReg, unsigned &DstReg,
2878                                     unsigned &SubIdx) const {
2879   switch (MI.getOpcode()) {
2880   default: break;
2881   case X86::MOVSX16rr8:
2882   case X86::MOVZX16rr8:
2883   case X86::MOVSX32rr8:
2884   case X86::MOVZX32rr8:
2885   case X86::MOVSX64rr8:
2886     if (!Subtarget.is64Bit())
2887       // It's not always legal to reference the low 8-bit of the larger
2888       // register in 32-bit mode.
2889       return false;
2890   case X86::MOVSX32rr16:
2891   case X86::MOVZX32rr16:
2892   case X86::MOVSX64rr16:
2893   case X86::MOVSX64rr32: {
2894     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2895       // Be conservative.
2896       return false;
2897     SrcReg = MI.getOperand(1).getReg();
2898     DstReg = MI.getOperand(0).getReg();
2899     switch (MI.getOpcode()) {
2900     default: llvm_unreachable("Unreachable!");
2901     case X86::MOVSX16rr8:
2902     case X86::MOVZX16rr8:
2903     case X86::MOVSX32rr8:
2904     case X86::MOVZX32rr8:
2905     case X86::MOVSX64rr8:
2906       SubIdx = X86::sub_8bit;
2907       break;
2908     case X86::MOVSX32rr16:
2909     case X86::MOVZX32rr16:
2910     case X86::MOVSX64rr16:
2911       SubIdx = X86::sub_16bit;
2912       break;
2913     case X86::MOVSX64rr32:
2914       SubIdx = X86::sub_32bit;
2915       break;
2916     }
2917     return true;
2918   }
2919   }
2920   return false;
2921 }
2922 
2923 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
2924   const MachineFunction *MF = MI.getParent()->getParent();
2925   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2926 
2927   if (MI.getOpcode() == getCallFrameSetupOpcode() ||
2928       MI.getOpcode() == getCallFrameDestroyOpcode()) {
2929     unsigned StackAlign = TFI->getStackAlignment();
2930     int SPAdj =
2931         (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
2932 
2933     SPAdj -= MI.getOperand(1).getImm();
2934 
2935     if (MI.getOpcode() == getCallFrameSetupOpcode())
2936       return SPAdj;
2937     else
2938       return -SPAdj;
2939   }
2940 
2941   // To know whether a call adjusts the stack, we need information
2942   // that is bound to the following ADJCALLSTACKUP pseudo.
2943   // Look for the next ADJCALLSTACKUP that follows the call.
2944   if (MI.isCall()) {
2945     const MachineBasicBlock *MBB = MI.getParent();
2946     auto I = ++MachineBasicBlock::const_iterator(MI);
2947     for (auto E = MBB->end(); I != E; ++I) {
2948       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2949           I->isCall())
2950         break;
2951     }
2952 
2953     // If we could not find a frame destroy opcode, then it has already
2954     // been simplified, so we don't care.
2955     if (I->getOpcode() != getCallFrameDestroyOpcode())
2956       return 0;
2957 
2958     return -(I->getOperand(1).getImm());
2959   }
2960 
2961   // Currently handle only PUSHes we can reasonably expect to see
2962   // in call sequences
2963   switch (MI.getOpcode()) {
2964   default:
2965     return 0;
2966   case X86::PUSH32i8:
2967   case X86::PUSH32r:
2968   case X86::PUSH32rmm:
2969   case X86::PUSH32rmr:
2970   case X86::PUSHi32:
2971     return 4;
2972   case X86::PUSH64i8:
2973   case X86::PUSH64r:
2974   case X86::PUSH64rmm:
2975   case X86::PUSH64rmr:
2976   case X86::PUSH64i32:
2977     return 8;
2978   }
2979 }
2980 
2981 /// Return true and the FrameIndex if the specified
2982 /// operand and follow operands form a reference to the stack frame.
2983 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
2984                                   int &FrameIndex) const {
2985   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
2986       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
2987       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
2988       MI.getOperand(Op + X86::AddrDisp).isImm() &&
2989       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
2990       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
2991       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
2992     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
2993     return true;
2994   }
2995   return false;
2996 }
2997 
2998 static bool isFrameLoadOpcode(int Opcode) {
2999   switch (Opcode) {
3000   default:
3001     return false;
3002   case X86::MOV8rm:
3003   case X86::MOV16rm:
3004   case X86::MOV32rm:
3005   case X86::MOV64rm:
3006   case X86::LD_Fp64m:
3007   case X86::MOVSSrm:
3008   case X86::MOVSDrm:
3009   case X86::MOVAPSrm:
3010   case X86::MOVUPSrm:
3011   case X86::MOVAPDrm:
3012   case X86::MOVUPDrm:
3013   case X86::MOVDQArm:
3014   case X86::MOVDQUrm:
3015   case X86::VMOVSSrm:
3016   case X86::VMOVSDrm:
3017   case X86::VMOVAPSrm:
3018   case X86::VMOVUPSrm:
3019   case X86::VMOVAPDrm:
3020   case X86::VMOVUPDrm:
3021   case X86::VMOVDQArm:
3022   case X86::VMOVDQUrm:
3023   case X86::VMOVUPSYrm:
3024   case X86::VMOVAPSYrm:
3025   case X86::VMOVUPDYrm:
3026   case X86::VMOVAPDYrm:
3027   case X86::VMOVDQUYrm:
3028   case X86::VMOVDQAYrm:
3029   case X86::MMX_MOVD64rm:
3030   case X86::MMX_MOVQ64rm:
3031   case X86::VMOVSSZrm:
3032   case X86::VMOVSDZrm:
3033   case X86::VMOVAPSZrm:
3034   case X86::VMOVAPSZ128rm:
3035   case X86::VMOVAPSZ256rm:
3036   case X86::VMOVAPSZ128rm_NOVLX:
3037   case X86::VMOVAPSZ256rm_NOVLX:
3038   case X86::VMOVUPSZrm:
3039   case X86::VMOVUPSZ128rm:
3040   case X86::VMOVUPSZ256rm:
3041   case X86::VMOVUPSZ128rm_NOVLX:
3042   case X86::VMOVUPSZ256rm_NOVLX:
3043   case X86::VMOVAPDZrm:
3044   case X86::VMOVAPDZ128rm:
3045   case X86::VMOVAPDZ256rm:
3046   case X86::VMOVUPDZrm:
3047   case X86::VMOVUPDZ128rm:
3048   case X86::VMOVUPDZ256rm:
3049   case X86::VMOVDQA32Zrm:
3050   case X86::VMOVDQA32Z128rm:
3051   case X86::VMOVDQA32Z256rm:
3052   case X86::VMOVDQU32Zrm:
3053   case X86::VMOVDQU32Z128rm:
3054   case X86::VMOVDQU32Z256rm:
3055   case X86::VMOVDQA64Zrm:
3056   case X86::VMOVDQA64Z128rm:
3057   case X86::VMOVDQA64Z256rm:
3058   case X86::VMOVDQU64Zrm:
3059   case X86::VMOVDQU64Z128rm:
3060   case X86::VMOVDQU64Z256rm:
3061   case X86::VMOVDQU8Zrm:
3062   case X86::VMOVDQU8Z128rm:
3063   case X86::VMOVDQU8Z256rm:
3064   case X86::VMOVDQU16Zrm:
3065   case X86::VMOVDQU16Z128rm:
3066   case X86::VMOVDQU16Z256rm:
3067   case X86::KMOVBkm:
3068   case X86::KMOVWkm:
3069   case X86::KMOVDkm:
3070   case X86::KMOVQkm:
3071     return true;
3072   }
3073 }
3074 
3075 static bool isFrameStoreOpcode(int Opcode) {
3076   switch (Opcode) {
3077   default: break;
3078   case X86::MOV8mr:
3079   case X86::MOV16mr:
3080   case X86::MOV32mr:
3081   case X86::MOV64mr:
3082   case X86::ST_FpP64m:
3083   case X86::MOVSSmr:
3084   case X86::MOVSDmr:
3085   case X86::MOVAPSmr:
3086   case X86::MOVUPSmr:
3087   case X86::MOVAPDmr:
3088   case X86::MOVUPDmr:
3089   case X86::MOVDQAmr:
3090   case X86::MOVDQUmr:
3091   case X86::VMOVSSmr:
3092   case X86::VMOVSDmr:
3093   case X86::VMOVAPSmr:
3094   case X86::VMOVUPSmr:
3095   case X86::VMOVAPDmr:
3096   case X86::VMOVUPDmr:
3097   case X86::VMOVDQAmr:
3098   case X86::VMOVDQUmr:
3099   case X86::VMOVUPSYmr:
3100   case X86::VMOVAPSYmr:
3101   case X86::VMOVUPDYmr:
3102   case X86::VMOVAPDYmr:
3103   case X86::VMOVDQUYmr:
3104   case X86::VMOVDQAYmr:
3105   case X86::VMOVSSZmr:
3106   case X86::VMOVSDZmr:
3107   case X86::VMOVUPSZmr:
3108   case X86::VMOVUPSZ128mr:
3109   case X86::VMOVUPSZ256mr:
3110   case X86::VMOVUPSZ128mr_NOVLX:
3111   case X86::VMOVUPSZ256mr_NOVLX:
3112   case X86::VMOVAPSZmr:
3113   case X86::VMOVAPSZ128mr:
3114   case X86::VMOVAPSZ256mr:
3115   case X86::VMOVAPSZ128mr_NOVLX:
3116   case X86::VMOVAPSZ256mr_NOVLX:
3117   case X86::VMOVUPDZmr:
3118   case X86::VMOVUPDZ128mr:
3119   case X86::VMOVUPDZ256mr:
3120   case X86::VMOVAPDZmr:
3121   case X86::VMOVAPDZ128mr:
3122   case X86::VMOVAPDZ256mr:
3123   case X86::VMOVDQA32Zmr:
3124   case X86::VMOVDQA32Z128mr:
3125   case X86::VMOVDQA32Z256mr:
3126   case X86::VMOVDQU32Zmr:
3127   case X86::VMOVDQU32Z128mr:
3128   case X86::VMOVDQU32Z256mr:
3129   case X86::VMOVDQA64Zmr:
3130   case X86::VMOVDQA64Z128mr:
3131   case X86::VMOVDQA64Z256mr:
3132   case X86::VMOVDQU64Zmr:
3133   case X86::VMOVDQU64Z128mr:
3134   case X86::VMOVDQU64Z256mr:
3135   case X86::VMOVDQU8Zmr:
3136   case X86::VMOVDQU8Z128mr:
3137   case X86::VMOVDQU8Z256mr:
3138   case X86::VMOVDQU16Zmr:
3139   case X86::VMOVDQU16Z128mr:
3140   case X86::VMOVDQU16Z256mr:
3141   case X86::MMX_MOVD64mr:
3142   case X86::MMX_MOVQ64mr:
3143   case X86::MMX_MOVNTQmr:
3144   case X86::KMOVBmk:
3145   case X86::KMOVWmk:
3146   case X86::KMOVDmk:
3147   case X86::KMOVQmk:
3148     return true;
3149   }
3150   return false;
3151 }
3152 
3153 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
3154                                            int &FrameIndex) const {
3155   if (isFrameLoadOpcode(MI.getOpcode()))
3156     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
3157       return MI.getOperand(0).getReg();
3158   return 0;
3159 }
3160 
3161 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
3162                                                  int &FrameIndex) const {
3163   if (isFrameLoadOpcode(MI.getOpcode())) {
3164     unsigned Reg;
3165     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
3166       return Reg;
3167     // Check for post-frame index elimination operations
3168     const MachineMemOperand *Dummy;
3169     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
3170   }
3171   return 0;
3172 }
3173 
3174 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
3175                                           int &FrameIndex) const {
3176   if (isFrameStoreOpcode(MI.getOpcode()))
3177     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
3178         isFrameOperand(MI, 0, FrameIndex))
3179       return MI.getOperand(X86::AddrNumOperands).getReg();
3180   return 0;
3181 }
3182 
3183 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
3184                                                 int &FrameIndex) const {
3185   if (isFrameStoreOpcode(MI.getOpcode())) {
3186     unsigned Reg;
3187     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
3188       return Reg;
3189     // Check for post-frame index elimination operations
3190     const MachineMemOperand *Dummy;
3191     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
3192   }
3193   return 0;
3194 }
3195 
3196 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
3197 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
3198   // Don't waste compile time scanning use-def chains of physregs.
3199   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
3200     return false;
3201   bool isPICBase = false;
3202   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
3203          E = MRI.def_instr_end(); I != E; ++I) {
3204     MachineInstr *DefMI = &*I;
3205     if (DefMI->getOpcode() != X86::MOVPC32r)
3206       return false;
3207     assert(!isPICBase && "More than one PIC base?");
3208     isPICBase = true;
3209   }
3210   return isPICBase;
3211 }
3212 
3213 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
3214                                                      AliasAnalysis *AA) const {
3215   switch (MI.getOpcode()) {
3216   default: break;
3217   case X86::MOV8rm:
3218   case X86::MOV8rm_NOREX:
3219   case X86::MOV16rm:
3220   case X86::MOV32rm:
3221   case X86::MOV64rm:
3222   case X86::LD_Fp64m:
3223   case X86::MOVSSrm:
3224   case X86::MOVSDrm:
3225   case X86::MOVAPSrm:
3226   case X86::MOVUPSrm:
3227   case X86::MOVAPDrm:
3228   case X86::MOVUPDrm:
3229   case X86::MOVDQArm:
3230   case X86::MOVDQUrm:
3231   case X86::VMOVSSrm:
3232   case X86::VMOVSDrm:
3233   case X86::VMOVAPSrm:
3234   case X86::VMOVUPSrm:
3235   case X86::VMOVAPDrm:
3236   case X86::VMOVUPDrm:
3237   case X86::VMOVDQArm:
3238   case X86::VMOVDQUrm:
3239   case X86::VMOVAPSYrm:
3240   case X86::VMOVUPSYrm:
3241   case X86::VMOVAPDYrm:
3242   case X86::VMOVUPDYrm:
3243   case X86::VMOVDQAYrm:
3244   case X86::VMOVDQUYrm:
3245   case X86::MMX_MOVD64rm:
3246   case X86::MMX_MOVQ64rm:
3247   // AVX-512
3248   case X86::VMOVSSZrm:
3249   case X86::VMOVSDZrm:
3250   case X86::VMOVAPDZ128rm:
3251   case X86::VMOVAPDZ256rm:
3252   case X86::VMOVAPDZrm:
3253   case X86::VMOVAPSZ128rm:
3254   case X86::VMOVAPSZ256rm:
3255   case X86::VMOVAPSZ128rm_NOVLX:
3256   case X86::VMOVAPSZ256rm_NOVLX:
3257   case X86::VMOVAPSZrm:
3258   case X86::VMOVDQA32Z128rm:
3259   case X86::VMOVDQA32Z256rm:
3260   case X86::VMOVDQA32Zrm:
3261   case X86::VMOVDQA64Z128rm:
3262   case X86::VMOVDQA64Z256rm:
3263   case X86::VMOVDQA64Zrm:
3264   case X86::VMOVDQU16Z128rm:
3265   case X86::VMOVDQU16Z256rm:
3266   case X86::VMOVDQU16Zrm:
3267   case X86::VMOVDQU32Z128rm:
3268   case X86::VMOVDQU32Z256rm:
3269   case X86::VMOVDQU32Zrm:
3270   case X86::VMOVDQU64Z128rm:
3271   case X86::VMOVDQU64Z256rm:
3272   case X86::VMOVDQU64Zrm:
3273   case X86::VMOVDQU8Z128rm:
3274   case X86::VMOVDQU8Z256rm:
3275   case X86::VMOVDQU8Zrm:
3276   case X86::VMOVUPDZ128rm:
3277   case X86::VMOVUPDZ256rm:
3278   case X86::VMOVUPDZrm:
3279   case X86::VMOVUPSZ128rm:
3280   case X86::VMOVUPSZ256rm:
3281   case X86::VMOVUPSZ128rm_NOVLX:
3282   case X86::VMOVUPSZ256rm_NOVLX:
3283   case X86::VMOVUPSZrm: {
3284     // Loads from constant pools are trivially rematerializable.
3285     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
3286         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
3287         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
3288         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
3289         MI.isDereferenceableInvariantLoad(AA)) {
3290       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
3291       if (BaseReg == 0 || BaseReg == X86::RIP)
3292         return true;
3293       // Allow re-materialization of PIC load.
3294       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
3295         return false;
3296       const MachineFunction &MF = *MI.getParent()->getParent();
3297       const MachineRegisterInfo &MRI = MF.getRegInfo();
3298       return regIsPICBase(BaseReg, MRI);
3299     }
3300     return false;
3301   }
3302 
3303   case X86::LEA32r:
3304   case X86::LEA64r: {
3305     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
3306         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
3307         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
3308         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
3309       // lea fi#, lea GV, etc. are all rematerializable.
3310       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
3311         return true;
3312       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
3313       if (BaseReg == 0)
3314         return true;
3315       // Allow re-materialization of lea PICBase + x.
3316       const MachineFunction &MF = *MI.getParent()->getParent();
3317       const MachineRegisterInfo &MRI = MF.getRegInfo();
3318       return regIsPICBase(BaseReg, MRI);
3319     }
3320     return false;
3321   }
3322   }
3323 
3324   // All other instructions marked M_REMATERIALIZABLE are always trivially
3325   // rematerializable.
3326   return true;
3327 }
3328 
3329 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
3330                                          MachineBasicBlock::iterator I) const {
3331   MachineBasicBlock::iterator E = MBB.end();
3332 
3333   // For compile time consideration, if we are not able to determine the
3334   // safety after visiting 4 instructions in each direction, we will assume
3335   // it's not safe.
3336   MachineBasicBlock::iterator Iter = I;
3337   for (unsigned i = 0; Iter != E && i < 4; ++i) {
3338     bool SeenDef = false;
3339     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
3340       MachineOperand &MO = Iter->getOperand(j);
3341       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
3342         SeenDef = true;
3343       if (!MO.isReg())
3344         continue;
3345       if (MO.getReg() == X86::EFLAGS) {
3346         if (MO.isUse())
3347           return false;
3348         SeenDef = true;
3349       }
3350     }
3351 
3352     if (SeenDef)
3353       // This instruction defines EFLAGS, no need to look any further.
3354       return true;
3355     ++Iter;
3356     // Skip over DBG_VALUE.
3357     while (Iter != E && Iter->isDebugValue())
3358       ++Iter;
3359   }
3360 
3361   // It is safe to clobber EFLAGS at the end of a block of no successor has it
3362   // live in.
3363   if (Iter == E) {
3364     for (MachineBasicBlock *S : MBB.successors())
3365       if (S->isLiveIn(X86::EFLAGS))
3366         return false;
3367     return true;
3368   }
3369 
3370   MachineBasicBlock::iterator B = MBB.begin();
3371   Iter = I;
3372   for (unsigned i = 0; i < 4; ++i) {
3373     // If we make it to the beginning of the block, it's safe to clobber
3374     // EFLAGS iff EFLAGS is not live-in.
3375     if (Iter == B)
3376       return !MBB.isLiveIn(X86::EFLAGS);
3377 
3378     --Iter;
3379     // Skip over DBG_VALUE.
3380     while (Iter != B && Iter->isDebugValue())
3381       --Iter;
3382 
3383     bool SawKill = false;
3384     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
3385       MachineOperand &MO = Iter->getOperand(j);
3386       // A register mask may clobber EFLAGS, but we should still look for a
3387       // live EFLAGS def.
3388       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
3389         SawKill = true;
3390       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
3391         if (MO.isDef()) return MO.isDead();
3392         if (MO.isKill()) SawKill = true;
3393       }
3394     }
3395 
3396     if (SawKill)
3397       // This instruction kills EFLAGS and doesn't redefine it, so
3398       // there's no need to look further.
3399       return true;
3400   }
3401 
3402   // Conservative answer.
3403   return false;
3404 }
3405 
3406 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
3407                                  MachineBasicBlock::iterator I,
3408                                  unsigned DestReg, unsigned SubIdx,
3409                                  const MachineInstr &Orig,
3410                                  const TargetRegisterInfo &TRI) const {
3411   bool ClobbersEFLAGS = false;
3412   for (const MachineOperand &MO : Orig.operands()) {
3413     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3414       ClobbersEFLAGS = true;
3415       break;
3416     }
3417   }
3418 
3419   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
3420     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
3421     // effects.
3422     int Value;
3423     switch (Orig.getOpcode()) {
3424     case X86::MOV32r0:  Value = 0; break;
3425     case X86::MOV32r1:  Value = 1; break;
3426     case X86::MOV32r_1: Value = -1; break;
3427     default:
3428       llvm_unreachable("Unexpected instruction!");
3429     }
3430 
3431     const DebugLoc &DL = Orig.getDebugLoc();
3432     BuildMI(MBB, I, DL, get(X86::MOV32ri))
3433         .addOperand(Orig.getOperand(0))
3434         .addImm(Value);
3435   } else {
3436     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
3437     MBB.insert(I, MI);
3438   }
3439 
3440   MachineInstr &NewMI = *std::prev(I);
3441   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
3442 }
3443 
3444 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
3445 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
3446   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3447     MachineOperand &MO = MI.getOperand(i);
3448     if (MO.isReg() && MO.isDef() &&
3449         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
3450       return true;
3451     }
3452   }
3453   return false;
3454 }
3455 
3456 /// Check whether the shift count for a machine operand is non-zero.
3457 inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
3458                                               unsigned ShiftAmtOperandIdx) {
3459   // The shift count is six bits with the REX.W prefix and five bits without.
3460   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
3461   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
3462   return Imm & ShiftCountMask;
3463 }
3464 
3465 /// Check whether the given shift count is appropriate
3466 /// can be represented by a LEA instruction.
3467 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
3468   // Left shift instructions can be transformed into load-effective-address
3469   // instructions if we can encode them appropriately.
3470   // A LEA instruction utilizes a SIB byte to encode its scale factor.
3471   // The SIB.scale field is two bits wide which means that we can encode any
3472   // shift amount less than 4.
3473   return ShAmt < 4 && ShAmt > 0;
3474 }
3475 
3476 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
3477                                   unsigned Opc, bool AllowSP, unsigned &NewSrc,
3478                                   bool &isKill, bool &isUndef,
3479                                   MachineOperand &ImplicitOp,
3480                                   LiveVariables *LV) const {
3481   MachineFunction &MF = *MI.getParent()->getParent();
3482   const TargetRegisterClass *RC;
3483   if (AllowSP) {
3484     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
3485   } else {
3486     RC = Opc != X86::LEA32r ?
3487       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
3488   }
3489   unsigned SrcReg = Src.getReg();
3490 
3491   // For both LEA64 and LEA32 the register already has essentially the right
3492   // type (32-bit or 64-bit) we may just need to forbid SP.
3493   if (Opc != X86::LEA64_32r) {
3494     NewSrc = SrcReg;
3495     isKill = Src.isKill();
3496     isUndef = Src.isUndef();
3497 
3498     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
3499         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
3500       return false;
3501 
3502     return true;
3503   }
3504 
3505   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
3506   // another we need to add 64-bit registers to the final MI.
3507   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
3508     ImplicitOp = Src;
3509     ImplicitOp.setImplicit();
3510 
3511     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
3512     isKill = Src.isKill();
3513     isUndef = Src.isUndef();
3514   } else {
3515     // Virtual register of the wrong class, we have to create a temporary 64-bit
3516     // vreg to feed into the LEA.
3517     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
3518     MachineInstr *Copy = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
3519                                  get(TargetOpcode::COPY))
3520         .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
3521         .addOperand(Src);
3522 
3523     // Which is obviously going to be dead after we're done with it.
3524     isKill = true;
3525     isUndef = false;
3526 
3527     if (LV)
3528       LV->replaceKillInstruction(SrcReg, MI, *Copy);
3529   }
3530 
3531   // We've set all the parameters without issue.
3532   return true;
3533 }
3534 
3535 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
3536 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
3537 /// truncating back down to a 16-bit subregister.
3538 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
3539     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
3540     LiveVariables *LV) const {
3541   MachineBasicBlock::iterator MBBI = MI.getIterator();
3542   unsigned Dest = MI.getOperand(0).getReg();
3543   unsigned Src = MI.getOperand(1).getReg();
3544   bool isDead = MI.getOperand(0).isDead();
3545   bool isKill = MI.getOperand(1).isKill();
3546 
3547   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
3548   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
3549   unsigned Opc, leaInReg;
3550   if (Subtarget.is64Bit()) {
3551     Opc = X86::LEA64_32r;
3552     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3553   } else {
3554     Opc = X86::LEA32r;
3555     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
3556   }
3557 
3558   // Build and insert into an implicit UNDEF value. This is OK because
3559   // well be shifting and then extracting the lower 16-bits.
3560   // This has the potential to cause partial register stall. e.g.
3561   //   movw    (%rbp,%rcx,2), %dx
3562   //   leal    -65(%rdx), %esi
3563   // But testing has shown this *does* help performance in 64-bit mode (at
3564   // least on modern x86 machines).
3565   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
3566   MachineInstr *InsMI =
3567       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
3568           .addReg(leaInReg, RegState::Define, X86::sub_16bit)
3569           .addReg(Src, getKillRegState(isKill));
3570 
3571   MachineInstrBuilder MIB =
3572       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
3573   switch (MIOpc) {
3574   default: llvm_unreachable("Unreachable!");
3575   case X86::SHL16ri: {
3576     unsigned ShAmt = MI.getOperand(2).getImm();
3577     MIB.addReg(0).addImm(1ULL << ShAmt)
3578        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
3579     break;
3580   }
3581   case X86::INC16r:
3582     addRegOffset(MIB, leaInReg, true, 1);
3583     break;
3584   case X86::DEC16r:
3585     addRegOffset(MIB, leaInReg, true, -1);
3586     break;
3587   case X86::ADD16ri:
3588   case X86::ADD16ri8:
3589   case X86::ADD16ri_DB:
3590   case X86::ADD16ri8_DB:
3591     addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
3592     break;
3593   case X86::ADD16rr:
3594   case X86::ADD16rr_DB: {
3595     unsigned Src2 = MI.getOperand(2).getReg();
3596     bool isKill2 = MI.getOperand(2).isKill();
3597     unsigned leaInReg2 = 0;
3598     MachineInstr *InsMI2 = nullptr;
3599     if (Src == Src2) {
3600       // ADD16rr %reg1028<kill>, %reg1028
3601       // just a single insert_subreg.
3602       addRegReg(MIB, leaInReg, true, leaInReg, false);
3603     } else {
3604       if (Subtarget.is64Bit())
3605         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3606       else
3607         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
3608       // Build and insert into an implicit UNDEF value. This is OK because
3609       // well be shifting and then extracting the lower 16-bits.
3610       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
3611       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
3612                    .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
3613                    .addReg(Src2, getKillRegState(isKill2));
3614       addRegReg(MIB, leaInReg, true, leaInReg2, true);
3615     }
3616     if (LV && isKill2 && InsMI2)
3617       LV->replaceKillInstruction(Src2, MI, *InsMI2);
3618     break;
3619   }
3620   }
3621 
3622   MachineInstr *NewMI = MIB;
3623   MachineInstr *ExtMI =
3624       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
3625           .addReg(Dest, RegState::Define | getDeadRegState(isDead))
3626           .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
3627 
3628   if (LV) {
3629     // Update live variables
3630     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
3631     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
3632     if (isKill)
3633       LV->replaceKillInstruction(Src, MI, *InsMI);
3634     if (isDead)
3635       LV->replaceKillInstruction(Dest, MI, *ExtMI);
3636   }
3637 
3638   return ExtMI;
3639 }
3640 
3641 /// This method must be implemented by targets that
3642 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
3643 /// may be able to convert a two-address instruction into a true
3644 /// three-address instruction on demand.  This allows the X86 target (for
3645 /// example) to convert ADD and SHL instructions into LEA instructions if they
3646 /// would require register copies due to two-addressness.
3647 ///
3648 /// This method returns a null pointer if the transformation cannot be
3649 /// performed, otherwise it returns the new instruction.
3650 ///
3651 MachineInstr *
3652 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
3653                                     MachineInstr &MI, LiveVariables *LV) const {
3654   // The following opcodes also sets the condition code register(s). Only
3655   // convert them to equivalent lea if the condition code register def's
3656   // are dead!
3657   if (hasLiveCondCodeDef(MI))
3658     return nullptr;
3659 
3660   MachineFunction &MF = *MI.getParent()->getParent();
3661   // All instructions input are two-addr instructions.  Get the known operands.
3662   const MachineOperand &Dest = MI.getOperand(0);
3663   const MachineOperand &Src = MI.getOperand(1);
3664 
3665   MachineInstr *NewMI = nullptr;
3666   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
3667   // we have better subtarget support, enable the 16-bit LEA generation here.
3668   // 16-bit LEA is also slow on Core2.
3669   bool DisableLEA16 = true;
3670   bool is64Bit = Subtarget.is64Bit();
3671 
3672   unsigned MIOpc = MI.getOpcode();
3673   switch (MIOpc) {
3674   default: return nullptr;
3675   case X86::SHL64ri: {
3676     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
3677     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3678     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
3679 
3680     // LEA can't handle RSP.
3681     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
3682         !MF.getRegInfo().constrainRegClass(Src.getReg(),
3683                                            &X86::GR64_NOSPRegClass))
3684       return nullptr;
3685 
3686     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3687                 .addOperand(Dest)
3688                 .addReg(0)
3689                 .addImm(1ULL << ShAmt)
3690                 .addOperand(Src)
3691                 .addImm(0)
3692                 .addReg(0);
3693     break;
3694   }
3695   case X86::SHL32ri: {
3696     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
3697     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3698     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
3699 
3700     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3701 
3702     // LEA can't handle ESP.
3703     bool isKill, isUndef;
3704     unsigned SrcReg;
3705     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3706     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
3707                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3708       return nullptr;
3709 
3710     MachineInstrBuilder MIB =
3711         BuildMI(MF, MI.getDebugLoc(), get(Opc))
3712             .addOperand(Dest)
3713             .addReg(0)
3714             .addImm(1ULL << ShAmt)
3715             .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
3716             .addImm(0)
3717             .addReg(0);
3718     if (ImplicitOp.getReg() != 0)
3719       MIB.addOperand(ImplicitOp);
3720     NewMI = MIB;
3721 
3722     break;
3723   }
3724   case X86::SHL16ri: {
3725     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
3726     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3727     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
3728 
3729     if (DisableLEA16)
3730       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3731                      : nullptr;
3732     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3733                 .addOperand(Dest)
3734                 .addReg(0)
3735                 .addImm(1ULL << ShAmt)
3736                 .addOperand(Src)
3737                 .addImm(0)
3738                 .addReg(0);
3739     break;
3740   }
3741   case X86::INC64r:
3742   case X86::INC32r: {
3743     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
3744     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
3745       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3746     bool isKill, isUndef;
3747     unsigned SrcReg;
3748     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3749     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
3750                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3751       return nullptr;
3752 
3753     MachineInstrBuilder MIB =
3754         BuildMI(MF, MI.getDebugLoc(), get(Opc))
3755             .addOperand(Dest)
3756             .addReg(SrcReg,
3757                     getKillRegState(isKill) | getUndefRegState(isUndef));
3758     if (ImplicitOp.getReg() != 0)
3759       MIB.addOperand(ImplicitOp);
3760 
3761     NewMI = addOffset(MIB, 1);
3762     break;
3763   }
3764   case X86::INC16r:
3765     if (DisableLEA16)
3766       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3767                      : nullptr;
3768     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
3769     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3770                           .addOperand(Dest)
3771                           .addOperand(Src),
3772                       1);
3773     break;
3774   case X86::DEC64r:
3775   case X86::DEC32r: {
3776     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
3777     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
3778       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3779 
3780     bool isKill, isUndef;
3781     unsigned SrcReg;
3782     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3783     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
3784                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3785       return nullptr;
3786 
3787     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3788                                   .addOperand(Dest)
3789                                   .addReg(SrcReg, getUndefRegState(isUndef) |
3790                                                       getKillRegState(isKill));
3791     if (ImplicitOp.getReg() != 0)
3792       MIB.addOperand(ImplicitOp);
3793 
3794     NewMI = addOffset(MIB, -1);
3795 
3796     break;
3797   }
3798   case X86::DEC16r:
3799     if (DisableLEA16)
3800       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3801                      : nullptr;
3802     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
3803     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3804                           .addOperand(Dest)
3805                           .addOperand(Src),
3806                       -1);
3807     break;
3808   case X86::ADD64rr:
3809   case X86::ADD64rr_DB:
3810   case X86::ADD32rr:
3811   case X86::ADD32rr_DB: {
3812     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3813     unsigned Opc;
3814     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
3815       Opc = X86::LEA64r;
3816     else
3817       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3818 
3819     bool isKill, isUndef;
3820     unsigned SrcReg;
3821     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3822     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3823                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3824       return nullptr;
3825 
3826     const MachineOperand &Src2 = MI.getOperand(2);
3827     bool isKill2, isUndef2;
3828     unsigned SrcReg2;
3829     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
3830     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
3831                         SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
3832       return nullptr;
3833 
3834     MachineInstrBuilder MIB =
3835         BuildMI(MF, MI.getDebugLoc(), get(Opc)).addOperand(Dest);
3836     if (ImplicitOp.getReg() != 0)
3837       MIB.addOperand(ImplicitOp);
3838     if (ImplicitOp2.getReg() != 0)
3839       MIB.addOperand(ImplicitOp2);
3840 
3841     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
3842 
3843     // Preserve undefness of the operands.
3844     NewMI->getOperand(1).setIsUndef(isUndef);
3845     NewMI->getOperand(3).setIsUndef(isUndef2);
3846 
3847     if (LV && Src2.isKill())
3848       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
3849     break;
3850   }
3851   case X86::ADD16rr:
3852   case X86::ADD16rr_DB: {
3853     if (DisableLEA16)
3854       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3855                      : nullptr;
3856     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3857     unsigned Src2 = MI.getOperand(2).getReg();
3858     bool isKill2 = MI.getOperand(2).isKill();
3859     NewMI = addRegReg(
3860         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).addOperand(Dest),
3861         Src.getReg(), Src.isKill(), Src2, isKill2);
3862 
3863     // Preserve undefness of the operands.
3864     bool isUndef = MI.getOperand(1).isUndef();
3865     bool isUndef2 = MI.getOperand(2).isUndef();
3866     NewMI->getOperand(1).setIsUndef(isUndef);
3867     NewMI->getOperand(3).setIsUndef(isUndef2);
3868 
3869     if (LV && isKill2)
3870       LV->replaceKillInstruction(Src2, MI, *NewMI);
3871     break;
3872   }
3873   case X86::ADD64ri32:
3874   case X86::ADD64ri8:
3875   case X86::ADD64ri32_DB:
3876   case X86::ADD64ri8_DB:
3877     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3878     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3879                           .addOperand(Dest)
3880                           .addOperand(Src),
3881                       MI.getOperand(2));
3882     break;
3883   case X86::ADD32ri:
3884   case X86::ADD32ri8:
3885   case X86::ADD32ri_DB:
3886   case X86::ADD32ri8_DB: {
3887     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3888     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3889 
3890     bool isKill, isUndef;
3891     unsigned SrcReg;
3892     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3893     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3894                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3895       return nullptr;
3896 
3897     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3898                                   .addOperand(Dest)
3899                                   .addReg(SrcReg, getUndefRegState(isUndef) |
3900                                                       getKillRegState(isKill));
3901     if (ImplicitOp.getReg() != 0)
3902       MIB.addOperand(ImplicitOp);
3903 
3904     NewMI = addOffset(MIB, MI.getOperand(2));
3905     break;
3906   }
3907   case X86::ADD16ri:
3908   case X86::ADD16ri8:
3909   case X86::ADD16ri_DB:
3910   case X86::ADD16ri8_DB:
3911     if (DisableLEA16)
3912       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3913                      : nullptr;
3914     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3915     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3916                           .addOperand(Dest)
3917                           .addOperand(Src),
3918                       MI.getOperand(2));
3919     break;
3920   }
3921 
3922   if (!NewMI) return nullptr;
3923 
3924   if (LV) {  // Update live variables
3925     if (Src.isKill())
3926       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
3927     if (Dest.isDead())
3928       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
3929   }
3930 
3931   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
3932   return NewMI;
3933 }
3934 
3935 /// This determines which of three possible cases of a three source commute
3936 /// the source indexes correspond to taking into account any mask operands.
3937 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
3938 /// possible.
3939 /// Case 0 - Possible to commute the first and second operands.
3940 /// Case 1 - Possible to commute the first and third operands.
3941 /// Case 2 - Possible to commute the second and third operands.
3942 static int getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
3943                                   unsigned SrcOpIdx2) {
3944   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3945   if (SrcOpIdx1 > SrcOpIdx2)
3946     std::swap(SrcOpIdx1, SrcOpIdx2);
3947 
3948   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
3949   if (X86II::isKMasked(TSFlags)) {
3950     // The k-mask operand cannot be commuted.
3951     if (SrcOpIdx1 == 2)
3952       return -1;
3953 
3954     // For k-zero-masked operations it is Ok to commute the first vector
3955     // operand.
3956     // For regular k-masked operations a conservative choice is done as the
3957     // elements of the first vector operand, for which the corresponding bit
3958     // in the k-mask operand is set to 0, are copied to the result of the
3959     // instruction.
3960     // TODO/FIXME: The commute still may be legal if it is known that the
3961     // k-mask operand is set to either all ones or all zeroes.
3962     // It is also Ok to commute the 1st operand if all users of MI use only
3963     // the elements enabled by the k-mask operand. For example,
3964     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
3965     //                                                     : v1[i];
3966     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
3967     //                                  // Ok, to commute v1 in FMADD213PSZrk.
3968     if (X86II::isKMergeMasked(TSFlags) && SrcOpIdx1 == Op1)
3969       return -1;
3970     Op2++;
3971     Op3++;
3972   }
3973 
3974   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
3975     return 0;
3976   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
3977     return 1;
3978   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
3979     return 2;
3980   return -1;
3981 }
3982 
3983 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
3984     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
3985     const X86InstrFMA3Group &FMA3Group) const {
3986 
3987   unsigned Opc = MI.getOpcode();
3988 
3989   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3990   if (SrcOpIdx1 > SrcOpIdx2)
3991     std::swap(SrcOpIdx1, SrcOpIdx2);
3992 
3993   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3994   // analysis. The commute optimization is legal only if all users of FMA*_Int
3995   // use only the lowest element of the FMA*_Int instruction. Such analysis are
3996   // not implemented yet. So, just return 0 in that case.
3997   // When such analysis are available this place will be the right place for
3998   // calling it.
3999   if (FMA3Group.isIntrinsic() && SrcOpIdx1 == 1)
4000     return 0;
4001 
4002   // Determine which case this commute is or if it can't be done.
4003   int Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
4004   if (Case < 0)
4005     return 0;
4006 
4007   // Define the FMA forms mapping array that helps to map input FMA form
4008   // to output FMA form to preserve the operation semantics after
4009   // commuting the operands.
4010   const unsigned Form132Index = 0;
4011   const unsigned Form213Index = 1;
4012   const unsigned Form231Index = 2;
4013   static const unsigned FormMapping[][3] = {
4014     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
4015     // FMA132 A, C, b; ==> FMA231 C, A, b;
4016     // FMA213 B, A, c; ==> FMA213 A, B, c;
4017     // FMA231 C, A, b; ==> FMA132 A, C, b;
4018     { Form231Index, Form213Index, Form132Index },
4019     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
4020     // FMA132 A, c, B; ==> FMA132 B, c, A;
4021     // FMA213 B, a, C; ==> FMA231 C, a, B;
4022     // FMA231 C, a, B; ==> FMA213 B, a, C;
4023     { Form132Index, Form231Index, Form213Index },
4024     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
4025     // FMA132 a, C, B; ==> FMA213 a, B, C;
4026     // FMA213 b, A, C; ==> FMA132 b, C, A;
4027     // FMA231 c, A, B; ==> FMA231 c, B, A;
4028     { Form213Index, Form132Index, Form231Index }
4029   };
4030 
4031   unsigned FMAForms[3];
4032   if (FMA3Group.isRegOpcodeFromGroup(Opc)) {
4033     FMAForms[0] = FMA3Group.getReg132Opcode();
4034     FMAForms[1] = FMA3Group.getReg213Opcode();
4035     FMAForms[2] = FMA3Group.getReg231Opcode();
4036   } else {
4037     FMAForms[0] = FMA3Group.getMem132Opcode();
4038     FMAForms[1] = FMA3Group.getMem213Opcode();
4039     FMAForms[2] = FMA3Group.getMem231Opcode();
4040   }
4041   unsigned FormIndex;
4042   for (FormIndex = 0; FormIndex < 3; FormIndex++)
4043     if (Opc == FMAForms[FormIndex])
4044       break;
4045 
4046   // Everything is ready, just adjust the FMA opcode and return it.
4047   FormIndex = FormMapping[Case][FormIndex];
4048   return FMAForms[FormIndex];
4049 }
4050 
4051 static bool commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
4052                              unsigned SrcOpIdx2) {
4053   uint64_t TSFlags = MI.getDesc().TSFlags;
4054 
4055   // Determine which case this commute is or if it can't be done.
4056   int Case = getThreeSrcCommuteCase(TSFlags, SrcOpIdx1, SrcOpIdx2);
4057   if (Case < 0)
4058     return false;
4059 
4060   // For each case we need to swap two pairs of bits in the final immediate.
4061   static const uint8_t SwapMasks[3][4] = {
4062     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
4063     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
4064     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
4065   };
4066 
4067   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
4068   // Clear out the bits we are swapping.
4069   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
4070                            SwapMasks[Case][2] | SwapMasks[Case][3]);
4071   // If the immediate had a bit of the pair set, then set the opposite bit.
4072   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
4073   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
4074   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
4075   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
4076   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
4077 
4078   return true;
4079 }
4080 
4081 // Returns true if this is a VPERMI2 or VPERMT2 instrution that can be
4082 // commuted.
4083 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
4084 #define VPERM_CASES(Suffix) \
4085   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
4086   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
4087   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
4088   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
4089   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
4090   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
4091   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
4092   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
4093   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
4094   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
4095   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
4096   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
4097 
4098 #define VPERM_CASES_BROADCAST(Suffix) \
4099   VPERM_CASES(Suffix) \
4100   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
4101   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
4102   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
4103   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
4104   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
4105   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
4106 
4107   switch (Opcode) {
4108   default: return false;
4109   VPERM_CASES(B)
4110   VPERM_CASES_BROADCAST(D)
4111   VPERM_CASES_BROADCAST(PD)
4112   VPERM_CASES_BROADCAST(PS)
4113   VPERM_CASES_BROADCAST(Q)
4114   VPERM_CASES(W)
4115     return true;
4116   }
4117 #undef VPERM_CASES_BROADCAST
4118 #undef VPERM_CASES
4119 }
4120 
4121 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
4122 // from the I opcod to the T opcode and vice versa.
4123 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
4124 #define VPERM_CASES(Orig, New) \
4125   case X86::Orig##128rr:    return X86::New##128rr;   \
4126   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
4127   case X86::Orig##128rm:    return X86::New##128rm;   \
4128   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
4129   case X86::Orig##256rr:    return X86::New##256rr;   \
4130   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
4131   case X86::Orig##256rm:    return X86::New##256rm;   \
4132   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
4133   case X86::Orig##rr:       return X86::New##rr;      \
4134   case X86::Orig##rrkz:     return X86::New##rrkz;    \
4135   case X86::Orig##rm:       return X86::New##rm;      \
4136   case X86::Orig##rmkz:     return X86::New##rmkz;
4137 
4138 #define VPERM_CASES_BROADCAST(Orig, New) \
4139   VPERM_CASES(Orig, New) \
4140   case X86::Orig##128rmb:   return X86::New##128rmb;   \
4141   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
4142   case X86::Orig##256rmb:   return X86::New##256rmb;   \
4143   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
4144   case X86::Orig##rmb:      return X86::New##rmb;      \
4145   case X86::Orig##rmbkz:    return X86::New##rmbkz;
4146 
4147   switch (Opcode) {
4148   VPERM_CASES(VPERMI2B, VPERMT2B)
4149   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
4150   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
4151   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
4152   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
4153   VPERM_CASES(VPERMI2W, VPERMT2W)
4154   VPERM_CASES(VPERMT2B, VPERMI2B)
4155   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
4156   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
4157   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
4158   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
4159   VPERM_CASES(VPERMT2W, VPERMI2W)
4160   }
4161 
4162   llvm_unreachable("Unreachable!");
4163 #undef VPERM_CASES_BROADCAST
4164 #undef VPERM_CASES
4165 }
4166 
4167 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
4168                                                    unsigned OpIdx1,
4169                                                    unsigned OpIdx2) const {
4170   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
4171     if (NewMI)
4172       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
4173     return MI;
4174   };
4175 
4176   switch (MI.getOpcode()) {
4177   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
4178   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
4179   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
4180   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
4181   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
4182   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
4183     unsigned Opc;
4184     unsigned Size;
4185     switch (MI.getOpcode()) {
4186     default: llvm_unreachable("Unreachable!");
4187     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
4188     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
4189     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
4190     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
4191     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
4192     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
4193     }
4194     unsigned Amt = MI.getOperand(3).getImm();
4195     auto &WorkingMI = cloneIfNew(MI);
4196     WorkingMI.setDesc(get(Opc));
4197     WorkingMI.getOperand(3).setImm(Size - Amt);
4198     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
4199                                                    OpIdx1, OpIdx2);
4200   }
4201   case X86::BLENDPDrri:
4202   case X86::BLENDPSrri:
4203   case X86::PBLENDWrri:
4204   case X86::VBLENDPDrri:
4205   case X86::VBLENDPSrri:
4206   case X86::VBLENDPDYrri:
4207   case X86::VBLENDPSYrri:
4208   case X86::VPBLENDDrri:
4209   case X86::VPBLENDWrri:
4210   case X86::VPBLENDDYrri:
4211   case X86::VPBLENDWYrri:{
4212     unsigned Mask;
4213     switch (MI.getOpcode()) {
4214     default: llvm_unreachable("Unreachable!");
4215     case X86::BLENDPDrri:    Mask = 0x03; break;
4216     case X86::BLENDPSrri:    Mask = 0x0F; break;
4217     case X86::PBLENDWrri:    Mask = 0xFF; break;
4218     case X86::VBLENDPDrri:   Mask = 0x03; break;
4219     case X86::VBLENDPSrri:   Mask = 0x0F; break;
4220     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
4221     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
4222     case X86::VPBLENDDrri:   Mask = 0x0F; break;
4223     case X86::VPBLENDWrri:   Mask = 0xFF; break;
4224     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
4225     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
4226     }
4227     // Only the least significant bits of Imm are used.
4228     unsigned Imm = MI.getOperand(3).getImm() & Mask;
4229     auto &WorkingMI = cloneIfNew(MI);
4230     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
4231     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
4232                                                    OpIdx1, OpIdx2);
4233   }
4234   case X86::MOVSDrr:
4235   case X86::MOVSSrr:
4236   case X86::VMOVSDrr:
4237   case X86::VMOVSSrr:{
4238     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
4239     if (!Subtarget.hasSSE41())
4240       return nullptr;
4241 
4242     unsigned Mask, Opc;
4243     switch (MI.getOpcode()) {
4244     default: llvm_unreachable("Unreachable!");
4245     case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
4246     case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
4247     case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
4248     case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
4249     }
4250 
4251     // MOVSD/MOVSS's 2nd operand is a FR64/FR32 reg class - we need to copy
4252     // this over to a VR128 class like the 1st operand to use a BLENDPD/BLENDPS.
4253     auto &MRI = MI.getParent()->getParent()->getRegInfo();
4254     auto VR128RC = MRI.getRegClass(MI.getOperand(1).getReg());
4255     unsigned VR128 = MRI.createVirtualRegister(VR128RC);
4256     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY),
4257             VR128)
4258         .addReg(MI.getOperand(2).getReg());
4259 
4260     auto &WorkingMI = cloneIfNew(MI);
4261     WorkingMI.setDesc(get(Opc));
4262     WorkingMI.getOperand(2).setReg(VR128);
4263     WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
4264     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
4265                                                    OpIdx1, OpIdx2);
4266   }
4267   case X86::PCLMULQDQrr:
4268   case X86::VPCLMULQDQrr:{
4269     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
4270     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
4271     unsigned Imm = MI.getOperand(3).getImm();
4272     unsigned Src1Hi = Imm & 0x01;
4273     unsigned Src2Hi = Imm & 0x10;
4274     auto &WorkingMI = cloneIfNew(MI);
4275     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
4276     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
4277                                                    OpIdx1, OpIdx2);
4278   }
4279   case X86::CMPSDrr:
4280   case X86::CMPSSrr:
4281   case X86::CMPPDrri:
4282   case X86::CMPPSrri:
4283   case X86::VCMPSDrr:
4284   case X86::VCMPSSrr:
4285   case X86::VCMPPDrri:
4286   case X86::VCMPPSrri:
4287   case X86::VCMPPDYrri:
4288   case X86::VCMPPSYrri:
4289   case X86::VCMPSDZrr:
4290   case X86::VCMPSSZrr:
4291   case X86::VCMPPDZrri:
4292   case X86::VCMPPSZrri:
4293   case X86::VCMPPDZ128rri:
4294   case X86::VCMPPSZ128rri:
4295   case X86::VCMPPDZ256rri:
4296   case X86::VCMPPSZ256rri: {
4297     // Float comparison can be safely commuted for
4298     // Ordered/Unordered/Equal/NotEqual tests
4299     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
4300     switch (Imm) {
4301     case 0x00: // EQUAL
4302     case 0x03: // UNORDERED
4303     case 0x04: // NOT EQUAL
4304     case 0x07: // ORDERED
4305       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
4306     default:
4307       return nullptr;
4308     }
4309   }
4310   case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
4311   case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
4312   case X86::VPCMPBZrri:    case X86::VPCMPUBZrri:
4313   case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
4314   case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
4315   case X86::VPCMPDZrri:    case X86::VPCMPUDZrri:
4316   case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
4317   case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
4318   case X86::VPCMPQZrri:    case X86::VPCMPUQZrri:
4319   case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
4320   case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
4321   case X86::VPCMPWZrri:    case X86::VPCMPUWZrri: {
4322     // Flip comparison mode immediate (if necessary).
4323     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
4324     switch (Imm) {
4325     default: llvm_unreachable("Unreachable!");
4326     case 0x01: Imm = 0x06; break; // LT  -> NLE
4327     case 0x02: Imm = 0x05; break; // LE  -> NLT
4328     case 0x05: Imm = 0x02; break; // NLT -> LE
4329     case 0x06: Imm = 0x01; break; // NLE -> LT
4330     case 0x00: // EQ
4331     case 0x03: // FALSE
4332     case 0x04: // NE
4333     case 0x07: // TRUE
4334       break;
4335     }
4336     auto &WorkingMI = cloneIfNew(MI);
4337     WorkingMI.getOperand(3).setImm(Imm);
4338     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
4339                                                    OpIdx1, OpIdx2);
4340   }
4341   case X86::VPCOMBri: case X86::VPCOMUBri:
4342   case X86::VPCOMDri: case X86::VPCOMUDri:
4343   case X86::VPCOMQri: case X86::VPCOMUQri:
4344   case X86::VPCOMWri: case X86::VPCOMUWri: {
4345     // Flip comparison mode immediate (if necessary).
4346     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
4347     switch (Imm) {
4348     default: llvm_unreachable("Unreachable!");
4349     case 0x00: Imm = 0x02; break; // LT -> GT
4350     case 0x01: Imm = 0x03; break; // LE -> GE
4351     case 0x02: Imm = 0x00; break; // GT -> LT
4352     case 0x03: Imm = 0x01; break; // GE -> LE
4353     case 0x04: // EQ
4354     case 0x05: // NE
4355     case 0x06: // FALSE
4356     case 0x07: // TRUE
4357       break;
4358     }
4359     auto &WorkingMI = cloneIfNew(MI);
4360     WorkingMI.getOperand(3).setImm(Imm);
4361     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
4362                                                    OpIdx1, OpIdx2);
4363   }
4364   case X86::VPERM2F128rr:
4365   case X86::VPERM2I128rr: {
4366     // Flip permute source immediate.
4367     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
4368     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
4369     unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
4370     auto &WorkingMI = cloneIfNew(MI);
4371     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
4372     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
4373                                                    OpIdx1, OpIdx2);
4374   }
4375   case X86::MOVHLPSrr:
4376   case X86::UNPCKHPDrr: {
4377     if (!Subtarget.hasSSE2())
4378       return nullptr;
4379 
4380     unsigned Opc = MI.getOpcode();
4381     switch (Opc) {
4382       default: llvm_unreachable("Unreachable!");
4383       case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
4384       case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
4385     }
4386     auto &WorkingMI = cloneIfNew(MI);
4387     WorkingMI.setDesc(get(Opc));
4388     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
4389                                                    OpIdx1, OpIdx2);
4390   }
4391   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
4392   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
4393   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
4394   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
4395   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
4396   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
4397   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
4398   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
4399   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
4400   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
4401   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
4402   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
4403   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
4404   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
4405   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
4406   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
4407     unsigned Opc;
4408     switch (MI.getOpcode()) {
4409     default: llvm_unreachable("Unreachable!");
4410     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
4411     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
4412     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
4413     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
4414     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
4415     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
4416     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
4417     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
4418     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
4419     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
4420     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
4421     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
4422     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
4423     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
4424     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
4425     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
4426     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
4427     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
4428     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
4429     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
4430     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
4431     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
4432     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
4433     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
4434     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
4435     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
4436     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
4437     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
4438     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
4439     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
4440     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
4441     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
4442     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
4443     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
4444     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
4445     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
4446     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
4447     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
4448     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
4449     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
4450     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
4451     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
4452     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
4453     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
4454     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
4455     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
4456     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
4457     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
4458     }
4459     auto &WorkingMI = cloneIfNew(MI);
4460     WorkingMI.setDesc(get(Opc));
4461     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
4462                                                    OpIdx1, OpIdx2);
4463   }
4464   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
4465   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
4466   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
4467   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
4468   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
4469   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
4470   case X86::VPTERNLOGDZrrik:     case X86::VPTERNLOGDZrmik:
4471   case X86::VPTERNLOGDZ128rrik:  case X86::VPTERNLOGDZ128rmik:
4472   case X86::VPTERNLOGDZ256rrik:  case X86::VPTERNLOGDZ256rmik:
4473   case X86::VPTERNLOGQZrrik:     case X86::VPTERNLOGQZrmik:
4474   case X86::VPTERNLOGQZ128rrik:  case X86::VPTERNLOGQZ128rmik:
4475   case X86::VPTERNLOGQZ256rrik:  case X86::VPTERNLOGQZ256rmik:
4476   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
4477   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
4478   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
4479   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
4480   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
4481   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz: {
4482     auto &WorkingMI = cloneIfNew(MI);
4483     if (!commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2))
4484       return nullptr;
4485     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
4486                                                    OpIdx1, OpIdx2);
4487   }
4488   default: {
4489     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
4490       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
4491       auto &WorkingMI = cloneIfNew(MI);
4492       WorkingMI.setDesc(get(Opc));
4493       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
4494                                                      OpIdx1, OpIdx2);
4495     }
4496 
4497     const X86InstrFMA3Group *FMA3Group =
4498         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
4499     if (FMA3Group) {
4500       unsigned Opc =
4501         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
4502       if (Opc == 0)
4503         return nullptr;
4504       auto &WorkingMI = cloneIfNew(MI);
4505       WorkingMI.setDesc(get(Opc));
4506       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
4507                                                      OpIdx1, OpIdx2);
4508     }
4509 
4510     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
4511   }
4512   }
4513 }
4514 
4515 bool X86InstrInfo::findFMA3CommutedOpIndices(
4516     const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2,
4517     const X86InstrFMA3Group &FMA3Group) const {
4518 
4519   if (!findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2))
4520     return false;
4521 
4522   // Check if we can adjust the opcode to preserve the semantics when
4523   // commute the register operands.
4524   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2, FMA3Group) != 0;
4525 }
4526 
4527 bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
4528                                                  unsigned &SrcOpIdx1,
4529                                                  unsigned &SrcOpIdx2) const {
4530   uint64_t TSFlags = MI.getDesc().TSFlags;
4531 
4532   unsigned FirstCommutableVecOp = 1;
4533   unsigned LastCommutableVecOp = 3;
4534   unsigned KMaskOp = 0;
4535   if (X86II::isKMasked(TSFlags)) {
4536     // The k-mask operand has index = 2 for masked and zero-masked operations.
4537     KMaskOp = 2;
4538 
4539     // The operand with index = 1 is used as a source for those elements for
4540     // which the corresponding bit in the k-mask is set to 0.
4541     if (X86II::isKMergeMasked(TSFlags))
4542       FirstCommutableVecOp = 3;
4543 
4544     LastCommutableVecOp++;
4545   }
4546 
4547   if (isMem(MI, LastCommutableVecOp))
4548     LastCommutableVecOp--;
4549 
4550   // Only the first RegOpsNum operands are commutable.
4551   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
4552   // that the operand is not specified/fixed.
4553   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
4554       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
4555        SrcOpIdx1 == KMaskOp))
4556     return false;
4557   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
4558       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
4559        SrcOpIdx2 == KMaskOp))
4560     return false;
4561 
4562   // Look for two different register operands assumed to be commutable
4563   // regardless of the FMA opcode. The FMA opcode is adjusted later.
4564   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
4565       SrcOpIdx2 == CommuteAnyOperandIndex) {
4566     unsigned CommutableOpIdx1 = SrcOpIdx1;
4567     unsigned CommutableOpIdx2 = SrcOpIdx2;
4568 
4569     // At least one of operands to be commuted is not specified and
4570     // this method is free to choose appropriate commutable operands.
4571     if (SrcOpIdx1 == SrcOpIdx2)
4572       // Both of operands are not fixed. By default set one of commutable
4573       // operands to the last register operand of the instruction.
4574       CommutableOpIdx2 = LastCommutableVecOp;
4575     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
4576       // Only one of operands is not fixed.
4577       CommutableOpIdx2 = SrcOpIdx1;
4578 
4579     // CommutableOpIdx2 is well defined now. Let's choose another commutable
4580     // operand and assign its index to CommutableOpIdx1.
4581     unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
4582     for (CommutableOpIdx1 = LastCommutableVecOp;
4583          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
4584       // Just ignore and skip the k-mask operand.
4585       if (CommutableOpIdx1 == KMaskOp)
4586         continue;
4587 
4588       // The commuted operands must have different registers.
4589       // Otherwise, the commute transformation does not change anything and
4590       // is useless then.
4591       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
4592         break;
4593     }
4594 
4595     // No appropriate commutable operands were found.
4596     if (CommutableOpIdx1 < FirstCommutableVecOp)
4597       return false;
4598 
4599     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
4600     // to return those values.
4601     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
4602                               CommutableOpIdx1, CommutableOpIdx2))
4603       return false;
4604   }
4605 
4606   return true;
4607 }
4608 
4609 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
4610                                          unsigned &SrcOpIdx2) const {
4611   const MCInstrDesc &Desc = MI.getDesc();
4612   if (!Desc.isCommutable())
4613     return false;
4614 
4615   switch (MI.getOpcode()) {
4616   case X86::CMPSDrr:
4617   case X86::CMPSSrr:
4618   case X86::CMPPDrri:
4619   case X86::CMPPSrri:
4620   case X86::VCMPSDrr:
4621   case X86::VCMPSSrr:
4622   case X86::VCMPPDrri:
4623   case X86::VCMPPSrri:
4624   case X86::VCMPPDYrri:
4625   case X86::VCMPPSYrri:
4626   case X86::VCMPSDZrr:
4627   case X86::VCMPSSZrr:
4628   case X86::VCMPPDZrri:
4629   case X86::VCMPPSZrri:
4630   case X86::VCMPPDZ128rri:
4631   case X86::VCMPPSZ128rri:
4632   case X86::VCMPPDZ256rri:
4633   case X86::VCMPPSZ256rri: {
4634     // Float comparison can be safely commuted for
4635     // Ordered/Unordered/Equal/NotEqual tests
4636     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
4637     switch (Imm) {
4638     case 0x00: // EQUAL
4639     case 0x03: // UNORDERED
4640     case 0x04: // NOT EQUAL
4641     case 0x07: // ORDERED
4642       // The indices of the commutable operands are 1 and 2.
4643       // Assign them to the returned operand indices here.
4644       return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
4645     }
4646     return false;
4647   }
4648   case X86::MOVSDrr:
4649   case X86::MOVSSrr:
4650   case X86::VMOVSDrr:
4651   case X86::VMOVSSrr: {
4652     if (Subtarget.hasSSE41())
4653       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
4654     return false;
4655   }
4656   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
4657   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
4658   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
4659   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
4660   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
4661   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
4662   case X86::VPTERNLOGDZrrik:     case X86::VPTERNLOGDZrmik:
4663   case X86::VPTERNLOGDZ128rrik:  case X86::VPTERNLOGDZ128rmik:
4664   case X86::VPTERNLOGDZ256rrik:  case X86::VPTERNLOGDZ256rmik:
4665   case X86::VPTERNLOGQZrrik:     case X86::VPTERNLOGQZrmik:
4666   case X86::VPTERNLOGQZ128rrik:  case X86::VPTERNLOGQZ128rmik:
4667   case X86::VPTERNLOGQZ256rrik:  case X86::VPTERNLOGQZ256rmik:
4668   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
4669   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
4670   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
4671   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
4672   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
4673   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
4674     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
4675   default:
4676     const X86InstrFMA3Group *FMA3Group =
4677         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
4678     if (FMA3Group)
4679       return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2, *FMA3Group);
4680 
4681     // Handled masked instructions since we need to skip over the mask input
4682     // and the preserved input.
4683     if (Desc.TSFlags & X86II::EVEX_K) {
4684       // First assume that the first input is the mask operand and skip past it.
4685       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
4686       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
4687       // Check if the first input is tied. If there isn't one then we only
4688       // need to skip the mask operand which we did above.
4689       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
4690                                              MCOI::TIED_TO) != -1)) {
4691         // If this is zero masking instruction with a tied operand, we need to
4692         // move the first index back to the first input since this must
4693         // be a 3 input instruction and we want the first two non-mask inputs.
4694         // Otherwise this is a 2 input instruction with a preserved input and
4695         // mask, so we need to move the indices to skip one more input.
4696         if (Desc.TSFlags & X86II::EVEX_Z)
4697           --CommutableOpIdx1;
4698         else {
4699           ++CommutableOpIdx1;
4700           ++CommutableOpIdx2;
4701         }
4702       }
4703 
4704       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
4705                                 CommutableOpIdx1, CommutableOpIdx2))
4706         return false;
4707 
4708       if (!MI.getOperand(SrcOpIdx1).isReg() ||
4709           !MI.getOperand(SrcOpIdx2).isReg())
4710         // No idea.
4711         return false;
4712       return true;
4713     }
4714 
4715     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
4716   }
4717   return false;
4718 }
4719 
4720 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
4721   switch (BrOpc) {
4722   default: return X86::COND_INVALID;
4723   case X86::JE_1:  return X86::COND_E;
4724   case X86::JNE_1: return X86::COND_NE;
4725   case X86::JL_1:  return X86::COND_L;
4726   case X86::JLE_1: return X86::COND_LE;
4727   case X86::JG_1:  return X86::COND_G;
4728   case X86::JGE_1: return X86::COND_GE;
4729   case X86::JB_1:  return X86::COND_B;
4730   case X86::JBE_1: return X86::COND_BE;
4731   case X86::JA_1:  return X86::COND_A;
4732   case X86::JAE_1: return X86::COND_AE;
4733   case X86::JS_1:  return X86::COND_S;
4734   case X86::JNS_1: return X86::COND_NS;
4735   case X86::JP_1:  return X86::COND_P;
4736   case X86::JNP_1: return X86::COND_NP;
4737   case X86::JO_1:  return X86::COND_O;
4738   case X86::JNO_1: return X86::COND_NO;
4739   }
4740 }
4741 
4742 /// Return condition code of a SET opcode.
4743 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
4744   switch (Opc) {
4745   default: return X86::COND_INVALID;
4746   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
4747   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
4748   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
4749   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
4750   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
4751   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
4752   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
4753   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
4754   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
4755   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
4756   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
4757   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
4758   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
4759   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
4760   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
4761   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
4762   }
4763 }
4764 
4765 /// Return condition code of a CMov opcode.
4766 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
4767   switch (Opc) {
4768   default: return X86::COND_INVALID;
4769   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
4770   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
4771     return X86::COND_A;
4772   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
4773   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
4774     return X86::COND_AE;
4775   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
4776   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
4777     return X86::COND_B;
4778   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
4779   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
4780     return X86::COND_BE;
4781   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
4782   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
4783     return X86::COND_E;
4784   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
4785   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
4786     return X86::COND_G;
4787   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
4788   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
4789     return X86::COND_GE;
4790   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
4791   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
4792     return X86::COND_L;
4793   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
4794   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
4795     return X86::COND_LE;
4796   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
4797   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
4798     return X86::COND_NE;
4799   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
4800   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
4801     return X86::COND_NO;
4802   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
4803   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
4804     return X86::COND_NP;
4805   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
4806   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
4807     return X86::COND_NS;
4808   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
4809   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
4810     return X86::COND_O;
4811   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
4812   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
4813     return X86::COND_P;
4814   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
4815   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
4816     return X86::COND_S;
4817   }
4818 }
4819 
4820 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
4821   switch (CC) {
4822   default: llvm_unreachable("Illegal condition code!");
4823   case X86::COND_E:  return X86::JE_1;
4824   case X86::COND_NE: return X86::JNE_1;
4825   case X86::COND_L:  return X86::JL_1;
4826   case X86::COND_LE: return X86::JLE_1;
4827   case X86::COND_G:  return X86::JG_1;
4828   case X86::COND_GE: return X86::JGE_1;
4829   case X86::COND_B:  return X86::JB_1;
4830   case X86::COND_BE: return X86::JBE_1;
4831   case X86::COND_A:  return X86::JA_1;
4832   case X86::COND_AE: return X86::JAE_1;
4833   case X86::COND_S:  return X86::JS_1;
4834   case X86::COND_NS: return X86::JNS_1;
4835   case X86::COND_P:  return X86::JP_1;
4836   case X86::COND_NP: return X86::JNP_1;
4837   case X86::COND_O:  return X86::JO_1;
4838   case X86::COND_NO: return X86::JNO_1;
4839   }
4840 }
4841 
4842 /// Return the inverse of the specified condition,
4843 /// e.g. turning COND_E to COND_NE.
4844 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
4845   switch (CC) {
4846   default: llvm_unreachable("Illegal condition code!");
4847   case X86::COND_E:  return X86::COND_NE;
4848   case X86::COND_NE: return X86::COND_E;
4849   case X86::COND_L:  return X86::COND_GE;
4850   case X86::COND_LE: return X86::COND_G;
4851   case X86::COND_G:  return X86::COND_LE;
4852   case X86::COND_GE: return X86::COND_L;
4853   case X86::COND_B:  return X86::COND_AE;
4854   case X86::COND_BE: return X86::COND_A;
4855   case X86::COND_A:  return X86::COND_BE;
4856   case X86::COND_AE: return X86::COND_B;
4857   case X86::COND_S:  return X86::COND_NS;
4858   case X86::COND_NS: return X86::COND_S;
4859   case X86::COND_P:  return X86::COND_NP;
4860   case X86::COND_NP: return X86::COND_P;
4861   case X86::COND_O:  return X86::COND_NO;
4862   case X86::COND_NO: return X86::COND_O;
4863   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
4864   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
4865   }
4866 }
4867 
4868 /// Assuming the flags are set by MI(a,b), return the condition code if we
4869 /// modify the instructions such that flags are set by MI(b,a).
4870 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
4871   switch (CC) {
4872   default: return X86::COND_INVALID;
4873   case X86::COND_E:  return X86::COND_E;
4874   case X86::COND_NE: return X86::COND_NE;
4875   case X86::COND_L:  return X86::COND_G;
4876   case X86::COND_LE: return X86::COND_GE;
4877   case X86::COND_G:  return X86::COND_L;
4878   case X86::COND_GE: return X86::COND_LE;
4879   case X86::COND_B:  return X86::COND_A;
4880   case X86::COND_BE: return X86::COND_AE;
4881   case X86::COND_A:  return X86::COND_B;
4882   case X86::COND_AE: return X86::COND_BE;
4883   }
4884 }
4885 
4886 /// Return a set opcode for the given condition and
4887 /// whether it has memory operand.
4888 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
4889   static const uint16_t Opc[16][2] = {
4890     { X86::SETAr,  X86::SETAm  },
4891     { X86::SETAEr, X86::SETAEm },
4892     { X86::SETBr,  X86::SETBm  },
4893     { X86::SETBEr, X86::SETBEm },
4894     { X86::SETEr,  X86::SETEm  },
4895     { X86::SETGr,  X86::SETGm  },
4896     { X86::SETGEr, X86::SETGEm },
4897     { X86::SETLr,  X86::SETLm  },
4898     { X86::SETLEr, X86::SETLEm },
4899     { X86::SETNEr, X86::SETNEm },
4900     { X86::SETNOr, X86::SETNOm },
4901     { X86::SETNPr, X86::SETNPm },
4902     { X86::SETNSr, X86::SETNSm },
4903     { X86::SETOr,  X86::SETOm  },
4904     { X86::SETPr,  X86::SETPm  },
4905     { X86::SETSr,  X86::SETSm  }
4906   };
4907 
4908   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
4909   return Opc[CC][HasMemoryOperand ? 1 : 0];
4910 }
4911 
4912 /// Return a cmov opcode for the given condition,
4913 /// register size in bytes, and operand type.
4914 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
4915                               bool HasMemoryOperand) {
4916   static const uint16_t Opc[32][3] = {
4917     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
4918     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
4919     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
4920     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
4921     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
4922     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
4923     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
4924     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
4925     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
4926     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
4927     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
4928     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
4929     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
4930     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
4931     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
4932     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
4933     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
4934     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
4935     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
4936     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
4937     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
4938     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
4939     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
4940     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
4941     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
4942     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
4943     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
4944     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
4945     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
4946     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
4947     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
4948     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
4949   };
4950 
4951   assert(CC < 16 && "Can only handle standard cond codes");
4952   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
4953   switch(RegBytes) {
4954   default: llvm_unreachable("Illegal register size!");
4955   case 2: return Opc[Idx][0];
4956   case 4: return Opc[Idx][1];
4957   case 8: return Opc[Idx][2];
4958   }
4959 }
4960 
4961 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
4962   if (!MI.isTerminator()) return false;
4963 
4964   // Conditional branch is a special case.
4965   if (MI.isBranch() && !MI.isBarrier())
4966     return true;
4967   if (!MI.isPredicable())
4968     return true;
4969   return !isPredicated(MI);
4970 }
4971 
4972 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
4973   switch (MI.getOpcode()) {
4974   case X86::TCRETURNdi:
4975   case X86::TCRETURNri:
4976   case X86::TCRETURNmi:
4977   case X86::TCRETURNdi64:
4978   case X86::TCRETURNri64:
4979   case X86::TCRETURNmi64:
4980     return true;
4981   default:
4982     return false;
4983   }
4984 }
4985 
4986 bool X86InstrInfo::canMakeTailCallConditional(
4987     SmallVectorImpl<MachineOperand> &BranchCond,
4988     const MachineInstr &TailCall) const {
4989   if (TailCall.getOpcode() != X86::TCRETURNdi &&
4990       TailCall.getOpcode() != X86::TCRETURNdi64) {
4991     // Only direct calls can be done with a conditional branch.
4992     return false;
4993   }
4994 
4995   if (Subtarget.isTargetWin64()) {
4996     // Conditional tail calls confuse the Win64 unwinder.
4997     // TODO: Allow them for "leaf" functions; PR30337.
4998     return false;
4999   }
5000 
5001   assert(BranchCond.size() == 1);
5002   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
5003     // Can't make a conditional tail call with this condition.
5004     return false;
5005   }
5006 
5007   const X86MachineFunctionInfo *X86FI =
5008       TailCall.getParent()->getParent()->getInfo<X86MachineFunctionInfo>();
5009   if (X86FI->getTCReturnAddrDelta() != 0 ||
5010       TailCall.getOperand(1).getImm() != 0) {
5011     // A conditional tail call cannot do any stack adjustment.
5012     return false;
5013   }
5014 
5015   return true;
5016 }
5017 
5018 void X86InstrInfo::replaceBranchWithTailCall(
5019     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
5020     const MachineInstr &TailCall) const {
5021   assert(canMakeTailCallConditional(BranchCond, TailCall));
5022 
5023   MachineBasicBlock::iterator I = MBB.end();
5024   while (I != MBB.begin()) {
5025     --I;
5026     if (I->isDebugValue())
5027       continue;
5028     if (!I->isBranch())
5029       assert(0 && "Can't find the branch to replace!");
5030 
5031     X86::CondCode CC = getCondFromBranchOpc(I->getOpcode());
5032     assert(BranchCond.size() == 1);
5033     if (CC != BranchCond[0].getImm())
5034       continue;
5035 
5036     break;
5037   }
5038 
5039   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
5040                                                          : X86::TCRETURNdi64cc;
5041 
5042   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
5043   MIB->addOperand(TailCall.getOperand(0)); // Destination.
5044   MIB.addImm(0); // Stack offset (not used).
5045   MIB->addOperand(BranchCond[0]); // Condition.
5046   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
5047 
5048   I->eraseFromParent();
5049 }
5050 
5051 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
5052 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
5053 // fallthrough MBB cannot be identified.
5054 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
5055                                             MachineBasicBlock *TBB) {
5056   // Look for non-EHPad successors other than TBB. If we find exactly one, it
5057   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
5058   // and fallthrough MBB. If we find more than one, we cannot identify the
5059   // fallthrough MBB and should return nullptr.
5060   MachineBasicBlock *FallthroughBB = nullptr;
5061   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
5062     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
5063       continue;
5064     // Return a nullptr if we found more than one fallthrough successor.
5065     if (FallthroughBB && FallthroughBB != TBB)
5066       return nullptr;
5067     FallthroughBB = *SI;
5068   }
5069   return FallthroughBB;
5070 }
5071 
5072 bool X86InstrInfo::AnalyzeBranchImpl(
5073     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
5074     SmallVectorImpl<MachineOperand> &Cond,
5075     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
5076 
5077   // Start from the bottom of the block and work up, examining the
5078   // terminator instructions.
5079   MachineBasicBlock::iterator I = MBB.end();
5080   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
5081   while (I != MBB.begin()) {
5082     --I;
5083     if (I->isDebugValue())
5084       continue;
5085 
5086     // Working from the bottom, when we see a non-terminator instruction, we're
5087     // done.
5088     if (!isUnpredicatedTerminator(*I))
5089       break;
5090 
5091     // A terminator that isn't a branch can't easily be handled by this
5092     // analysis.
5093     if (!I->isBranch())
5094       return true;
5095 
5096     // Handle unconditional branches.
5097     if (I->getOpcode() == X86::JMP_1) {
5098       UnCondBrIter = I;
5099 
5100       if (!AllowModify) {
5101         TBB = I->getOperand(0).getMBB();
5102         continue;
5103       }
5104 
5105       // If the block has any instructions after a JMP, delete them.
5106       while (std::next(I) != MBB.end())
5107         std::next(I)->eraseFromParent();
5108 
5109       Cond.clear();
5110       FBB = nullptr;
5111 
5112       // Delete the JMP if it's equivalent to a fall-through.
5113       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
5114         TBB = nullptr;
5115         I->eraseFromParent();
5116         I = MBB.end();
5117         UnCondBrIter = MBB.end();
5118         continue;
5119       }
5120 
5121       // TBB is used to indicate the unconditional destination.
5122       TBB = I->getOperand(0).getMBB();
5123       continue;
5124     }
5125 
5126     // Handle conditional branches.
5127     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
5128     if (BranchCode == X86::COND_INVALID)
5129       return true;  // Can't handle indirect branch.
5130 
5131     // Working from the bottom, handle the first conditional branch.
5132     if (Cond.empty()) {
5133       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
5134       if (AllowModify && UnCondBrIter != MBB.end() &&
5135           MBB.isLayoutSuccessor(TargetBB)) {
5136         // If we can modify the code and it ends in something like:
5137         //
5138         //     jCC L1
5139         //     jmp L2
5140         //   L1:
5141         //     ...
5142         //   L2:
5143         //
5144         // Then we can change this to:
5145         //
5146         //     jnCC L2
5147         //   L1:
5148         //     ...
5149         //   L2:
5150         //
5151         // Which is a bit more efficient.
5152         // We conditionally jump to the fall-through block.
5153         BranchCode = GetOppositeBranchCondition(BranchCode);
5154         unsigned JNCC = GetCondBranchFromCond(BranchCode);
5155         MachineBasicBlock::iterator OldInst = I;
5156 
5157         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
5158           .addMBB(UnCondBrIter->getOperand(0).getMBB());
5159         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
5160           .addMBB(TargetBB);
5161 
5162         OldInst->eraseFromParent();
5163         UnCondBrIter->eraseFromParent();
5164 
5165         // Restart the analysis.
5166         UnCondBrIter = MBB.end();
5167         I = MBB.end();
5168         continue;
5169       }
5170 
5171       FBB = TBB;
5172       TBB = I->getOperand(0).getMBB();
5173       Cond.push_back(MachineOperand::CreateImm(BranchCode));
5174       CondBranches.push_back(&*I);
5175       continue;
5176     }
5177 
5178     // Handle subsequent conditional branches. Only handle the case where all
5179     // conditional branches branch to the same destination and their condition
5180     // opcodes fit one of the special multi-branch idioms.
5181     assert(Cond.size() == 1);
5182     assert(TBB);
5183 
5184     // If the conditions are the same, we can leave them alone.
5185     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
5186     auto NewTBB = I->getOperand(0).getMBB();
5187     if (OldBranchCode == BranchCode && TBB == NewTBB)
5188       continue;
5189 
5190     // If they differ, see if they fit one of the known patterns. Theoretically,
5191     // we could handle more patterns here, but we shouldn't expect to see them
5192     // if instruction selection has done a reasonable job.
5193     if (TBB == NewTBB &&
5194                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
5195                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
5196       BranchCode = X86::COND_NE_OR_P;
5197     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
5198                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
5199       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
5200         return true;
5201 
5202       // X86::COND_E_AND_NP usually has two different branch destinations.
5203       //
5204       // JP B1
5205       // JE B2
5206       // JMP B1
5207       // B1:
5208       // B2:
5209       //
5210       // Here this condition branches to B2 only if NP && E. It has another
5211       // equivalent form:
5212       //
5213       // JNE B1
5214       // JNP B2
5215       // JMP B1
5216       // B1:
5217       // B2:
5218       //
5219       // Similarly it branches to B2 only if E && NP. That is why this condition
5220       // is named with COND_E_AND_NP.
5221       BranchCode = X86::COND_E_AND_NP;
5222     } else
5223       return true;
5224 
5225     // Update the MachineOperand.
5226     Cond[0].setImm(BranchCode);
5227     CondBranches.push_back(&*I);
5228   }
5229 
5230   return false;
5231 }
5232 
5233 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
5234                                  MachineBasicBlock *&TBB,
5235                                  MachineBasicBlock *&FBB,
5236                                  SmallVectorImpl<MachineOperand> &Cond,
5237                                  bool AllowModify) const {
5238   SmallVector<MachineInstr *, 4> CondBranches;
5239   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
5240 }
5241 
5242 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
5243                                           MachineBranchPredicate &MBP,
5244                                           bool AllowModify) const {
5245   using namespace std::placeholders;
5246 
5247   SmallVector<MachineOperand, 4> Cond;
5248   SmallVector<MachineInstr *, 4> CondBranches;
5249   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
5250                         AllowModify))
5251     return true;
5252 
5253   if (Cond.size() != 1)
5254     return true;
5255 
5256   assert(MBP.TrueDest && "expected!");
5257 
5258   if (!MBP.FalseDest)
5259     MBP.FalseDest = MBB.getNextNode();
5260 
5261   const TargetRegisterInfo *TRI = &getRegisterInfo();
5262 
5263   MachineInstr *ConditionDef = nullptr;
5264   bool SingleUseCondition = true;
5265 
5266   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
5267     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
5268       ConditionDef = &*I;
5269       break;
5270     }
5271 
5272     if (I->readsRegister(X86::EFLAGS, TRI))
5273       SingleUseCondition = false;
5274   }
5275 
5276   if (!ConditionDef)
5277     return true;
5278 
5279   if (SingleUseCondition) {
5280     for (auto *Succ : MBB.successors())
5281       if (Succ->isLiveIn(X86::EFLAGS))
5282         SingleUseCondition = false;
5283   }
5284 
5285   MBP.ConditionDef = ConditionDef;
5286   MBP.SingleUseCondition = SingleUseCondition;
5287 
5288   // Currently we only recognize the simple pattern:
5289   //
5290   //   test %reg, %reg
5291   //   je %label
5292   //
5293   const unsigned TestOpcode =
5294       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
5295 
5296   if (ConditionDef->getOpcode() == TestOpcode &&
5297       ConditionDef->getNumOperands() == 3 &&
5298       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
5299       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
5300     MBP.LHS = ConditionDef->getOperand(0);
5301     MBP.RHS = MachineOperand::CreateImm(0);
5302     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
5303                         ? MachineBranchPredicate::PRED_NE
5304                         : MachineBranchPredicate::PRED_EQ;
5305     return false;
5306   }
5307 
5308   return true;
5309 }
5310 
5311 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
5312                                     int *BytesRemoved) const {
5313   assert(!BytesRemoved && "code size not handled");
5314 
5315   MachineBasicBlock::iterator I = MBB.end();
5316   unsigned Count = 0;
5317 
5318   while (I != MBB.begin()) {
5319     --I;
5320     if (I->isDebugValue())
5321       continue;
5322     if (I->getOpcode() != X86::JMP_1 &&
5323         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
5324       break;
5325     // Remove the branch.
5326     I->eraseFromParent();
5327     I = MBB.end();
5328     ++Count;
5329   }
5330 
5331   return Count;
5332 }
5333 
5334 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
5335                                     MachineBasicBlock *TBB,
5336                                     MachineBasicBlock *FBB,
5337                                     ArrayRef<MachineOperand> Cond,
5338                                     const DebugLoc &DL,
5339                                     int *BytesAdded) const {
5340   // Shouldn't be a fall through.
5341   assert(TBB && "insertBranch must not be told to insert a fallthrough");
5342   assert((Cond.size() == 1 || Cond.size() == 0) &&
5343          "X86 branch conditions have one component!");
5344   assert(!BytesAdded && "code size not handled");
5345 
5346   if (Cond.empty()) {
5347     // Unconditional branch?
5348     assert(!FBB && "Unconditional branch with multiple successors!");
5349     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
5350     return 1;
5351   }
5352 
5353   // If FBB is null, it is implied to be a fall-through block.
5354   bool FallThru = FBB == nullptr;
5355 
5356   // Conditional branch.
5357   unsigned Count = 0;
5358   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
5359   switch (CC) {
5360   case X86::COND_NE_OR_P:
5361     // Synthesize NE_OR_P with two branches.
5362     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
5363     ++Count;
5364     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
5365     ++Count;
5366     break;
5367   case X86::COND_E_AND_NP:
5368     // Use the next block of MBB as FBB if it is null.
5369     if (FBB == nullptr) {
5370       FBB = getFallThroughMBB(&MBB, TBB);
5371       assert(FBB && "MBB cannot be the last block in function when the false "
5372                     "body is a fall-through.");
5373     }
5374     // Synthesize COND_E_AND_NP with two branches.
5375     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
5376     ++Count;
5377     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
5378     ++Count;
5379     break;
5380   default: {
5381     unsigned Opc = GetCondBranchFromCond(CC);
5382     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
5383     ++Count;
5384   }
5385   }
5386   if (!FallThru) {
5387     // Two-way Conditional branch. Insert the second branch.
5388     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
5389     ++Count;
5390   }
5391   return Count;
5392 }
5393 
5394 bool X86InstrInfo::
5395 canInsertSelect(const MachineBasicBlock &MBB,
5396                 ArrayRef<MachineOperand> Cond,
5397                 unsigned TrueReg, unsigned FalseReg,
5398                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
5399   // Not all subtargets have cmov instructions.
5400   if (!Subtarget.hasCMov())
5401     return false;
5402   if (Cond.size() != 1)
5403     return false;
5404   // We cannot do the composite conditions, at least not in SSA form.
5405   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
5406     return false;
5407 
5408   // Check register classes.
5409   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5410   const TargetRegisterClass *RC =
5411     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
5412   if (!RC)
5413     return false;
5414 
5415   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
5416   if (X86::GR16RegClass.hasSubClassEq(RC) ||
5417       X86::GR32RegClass.hasSubClassEq(RC) ||
5418       X86::GR64RegClass.hasSubClassEq(RC)) {
5419     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
5420     // Bridge. Probably Ivy Bridge as well.
5421     CondCycles = 2;
5422     TrueCycles = 2;
5423     FalseCycles = 2;
5424     return true;
5425   }
5426 
5427   // Can't do vectors.
5428   return false;
5429 }
5430 
5431 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
5432                                 MachineBasicBlock::iterator I,
5433                                 const DebugLoc &DL, unsigned DstReg,
5434                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
5435                                 unsigned FalseReg) const {
5436   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5437   assert(Cond.size() == 1 && "Invalid Cond array");
5438   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
5439                                  MRI.getRegClass(DstReg)->getSize(),
5440                                  false /*HasMemoryOperand*/);
5441   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
5442 }
5443 
5444 /// Test if the given register is a physical h register.
5445 static bool isHReg(unsigned Reg) {
5446   return X86::GR8_ABCD_HRegClass.contains(Reg);
5447 }
5448 
5449 // Try and copy between VR128/VR64 and GR64 registers.
5450 static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg,
5451                                         const X86Subtarget &Subtarget) {
5452   bool HasAVX = Subtarget.hasAVX();
5453   bool HasAVX512 = Subtarget.hasAVX512();
5454 
5455   // SrcReg(MaskReg) -> DestReg(GR64)
5456   // SrcReg(MaskReg) -> DestReg(GR32)
5457   // SrcReg(MaskReg) -> DestReg(GR16)
5458   // SrcReg(MaskReg) -> DestReg(GR8)
5459 
5460   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
5461   if (X86::VK16RegClass.contains(SrcReg)) {
5462     if (X86::GR64RegClass.contains(DestReg)) {
5463       assert(Subtarget.hasBWI());
5464       return X86::KMOVQrk;
5465     }
5466     if (X86::GR32RegClass.contains(DestReg))
5467       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
5468     if (X86::GR16RegClass.contains(DestReg)) {
5469       DestReg = getX86SubSuperRegister(DestReg, 32);
5470       return X86::KMOVWrk;
5471     }
5472     if (X86::GR8RegClass.contains(DestReg)) {
5473       DestReg = getX86SubSuperRegister(DestReg, 32);
5474       return Subtarget.hasDQI() ? X86::KMOVBrk : X86::KMOVWrk;
5475     }
5476   }
5477 
5478   // SrcReg(GR64) -> DestReg(MaskReg)
5479   // SrcReg(GR32) -> DestReg(MaskReg)
5480   // SrcReg(GR16) -> DestReg(MaskReg)
5481   // SrcReg(GR8)  -> DestReg(MaskReg)
5482 
5483   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
5484   if (X86::VK16RegClass.contains(DestReg)) {
5485     if (X86::GR64RegClass.contains(SrcReg)) {
5486       assert(Subtarget.hasBWI());
5487       return X86::KMOVQkr;
5488     }
5489     if (X86::GR32RegClass.contains(SrcReg))
5490       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
5491     if (X86::GR16RegClass.contains(SrcReg)) {
5492       SrcReg = getX86SubSuperRegister(SrcReg, 32);
5493       return X86::KMOVWkr;
5494     }
5495     if (X86::GR8RegClass.contains(SrcReg)) {
5496       SrcReg = getX86SubSuperRegister(SrcReg, 32);
5497       return Subtarget.hasDQI() ? X86::KMOVBkr : X86::KMOVWkr;
5498     }
5499   }
5500 
5501 
5502   // SrcReg(VR128) -> DestReg(GR64)
5503   // SrcReg(VR64)  -> DestReg(GR64)
5504   // SrcReg(GR64)  -> DestReg(VR128)
5505   // SrcReg(GR64)  -> DestReg(VR64)
5506 
5507   if (X86::GR64RegClass.contains(DestReg)) {
5508     if (X86::VR128XRegClass.contains(SrcReg))
5509       // Copy from a VR128 register to a GR64 register.
5510       return HasAVX512 ? X86::VMOVPQIto64Zrr :
5511              HasAVX    ? X86::VMOVPQIto64rr  :
5512                          X86::MOVPQIto64rr;
5513     if (X86::VR64RegClass.contains(SrcReg))
5514       // Copy from a VR64 register to a GR64 register.
5515       return X86::MMX_MOVD64from64rr;
5516   } else if (X86::GR64RegClass.contains(SrcReg)) {
5517     // Copy from a GR64 register to a VR128 register.
5518     if (X86::VR128XRegClass.contains(DestReg))
5519       return HasAVX512 ? X86::VMOV64toPQIZrr :
5520              HasAVX    ? X86::VMOV64toPQIrr  :
5521                          X86::MOV64toPQIrr;
5522     // Copy from a GR64 register to a VR64 register.
5523     if (X86::VR64RegClass.contains(DestReg))
5524       return X86::MMX_MOVD64to64rr;
5525   }
5526 
5527   // SrcReg(FR32) -> DestReg(GR32)
5528   // SrcReg(GR32) -> DestReg(FR32)
5529 
5530   if (X86::GR32RegClass.contains(DestReg) &&
5531       X86::FR32XRegClass.contains(SrcReg))
5532     // Copy from a FR32 register to a GR32 register.
5533     return HasAVX512 ? X86::VMOVSS2DIZrr :
5534            HasAVX    ? X86::VMOVSS2DIrr  :
5535                        X86::MOVSS2DIrr;
5536 
5537   if (X86::FR32XRegClass.contains(DestReg) &&
5538       X86::GR32RegClass.contains(SrcReg))
5539     // Copy from a GR32 register to a FR32 register.
5540     return HasAVX512 ? X86::VMOVDI2SSZrr :
5541            HasAVX    ? X86::VMOVDI2SSrr  :
5542                        X86::MOVDI2SSrr;
5543   return 0;
5544 }
5545 
5546 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
5547                                MachineBasicBlock::iterator MI,
5548                                const DebugLoc &DL, unsigned DestReg,
5549                                unsigned SrcReg, bool KillSrc) const {
5550   // First deal with the normal symmetric copies.
5551   bool HasAVX = Subtarget.hasAVX();
5552   bool HasVLX = Subtarget.hasVLX();
5553   unsigned Opc = 0;
5554   if (X86::GR64RegClass.contains(DestReg, SrcReg))
5555     Opc = X86::MOV64rr;
5556   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
5557     Opc = X86::MOV32rr;
5558   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
5559     Opc = X86::MOV16rr;
5560   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
5561     // Copying to or from a physical H register on x86-64 requires a NOREX
5562     // move.  Otherwise use a normal move.
5563     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
5564         Subtarget.is64Bit()) {
5565       Opc = X86::MOV8rr_NOREX;
5566       // Both operands must be encodable without an REX prefix.
5567       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
5568              "8-bit H register can not be copied outside GR8_NOREX");
5569     } else
5570       Opc = X86::MOV8rr;
5571   }
5572   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
5573     Opc = X86::MMX_MOVQ64rr;
5574   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
5575     if (HasVLX)
5576       Opc = X86::VMOVAPSZ128rr;
5577     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
5578       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
5579     else {
5580       // If this an extended register and we don't have VLX we need to use a
5581       // 512-bit move.
5582       Opc = X86::VMOVAPSZrr;
5583       const TargetRegisterInfo *TRI = &getRegisterInfo();
5584       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
5585                                          &X86::VR512RegClass);
5586       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
5587                                         &X86::VR512RegClass);
5588     }
5589   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
5590     if (HasVLX)
5591       Opc = X86::VMOVAPSZ256rr;
5592     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
5593       Opc = X86::VMOVAPSYrr;
5594     else {
5595       // If this an extended register and we don't have VLX we need to use a
5596       // 512-bit move.
5597       Opc = X86::VMOVAPSZrr;
5598       const TargetRegisterInfo *TRI = &getRegisterInfo();
5599       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
5600                                          &X86::VR512RegClass);
5601       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
5602                                         &X86::VR512RegClass);
5603     }
5604   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
5605     Opc = X86::VMOVAPSZrr;
5606   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
5607   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
5608     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
5609   if (!Opc)
5610     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
5611 
5612   if (Opc) {
5613     BuildMI(MBB, MI, DL, get(Opc), DestReg)
5614       .addReg(SrcReg, getKillRegState(KillSrc));
5615     return;
5616   }
5617 
5618   bool FromEFLAGS = SrcReg == X86::EFLAGS;
5619   bool ToEFLAGS = DestReg == X86::EFLAGS;
5620   int Reg = FromEFLAGS ? DestReg : SrcReg;
5621   bool is32 = X86::GR32RegClass.contains(Reg);
5622   bool is64 = X86::GR64RegClass.contains(Reg);
5623 
5624   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
5625     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
5626     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
5627     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
5628     int Pop = is64 ? X86::POP64r : X86::POP32r;
5629     int PopF = is64 ? X86::POPF64 : X86::POPF32;
5630     int AX = is64 ? X86::RAX : X86::EAX;
5631 
5632     if (!Subtarget.hasLAHFSAHF()) {
5633       assert(Subtarget.is64Bit() &&
5634              "Not having LAHF/SAHF only happens on 64-bit.");
5635       // Moving EFLAGS to / from another register requires a push and a pop.
5636       // Notice that we have to adjust the stack if we don't want to clobber the
5637       // first frame index. See X86FrameLowering.cpp - usesTheStack.
5638       if (FromEFLAGS) {
5639         BuildMI(MBB, MI, DL, get(PushF));
5640         BuildMI(MBB, MI, DL, get(Pop), DestReg);
5641       }
5642       if (ToEFLAGS) {
5643         BuildMI(MBB, MI, DL, get(Push))
5644             .addReg(SrcReg, getKillRegState(KillSrc));
5645         BuildMI(MBB, MI, DL, get(PopF));
5646       }
5647       return;
5648     }
5649 
5650     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
5651     // inefficient. Instead:
5652     //   - Save the overflow flag OF into AL using SETO, and restore it using a
5653     //     signed 8-bit addition of AL and INT8_MAX.
5654     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
5655     //     using LAHF/SAHF.
5656     //   - When RAX/EAX is live and isn't the destination register, make sure it
5657     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
5658     //     the flags.
5659     // This approach is ~2.25x faster than using PUSHF/POPF.
5660     //
5661     // This is still somewhat inefficient because we don't know which flags are
5662     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
5663     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
5664     //
5665     // PUSHF/POPF is also potentially incorrect because it affects other flags
5666     // such as TF/IF/DF, which LLVM doesn't model.
5667     //
5668     // Notice that we have to adjust the stack if we don't want to clobber the
5669     // first frame index.
5670     // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
5671 
5672     const TargetRegisterInfo *TRI = &getRegisterInfo();
5673     MachineBasicBlock::LivenessQueryResult LQR =
5674         MBB.computeRegisterLiveness(TRI, AX, MI);
5675     // We do not want to save and restore AX if we do not have to.
5676     // Moreover, if we do so whereas AX is dead, we would need to set
5677     // an undef flag on the use of AX, otherwise the verifier will
5678     // complain that we read an undef value.
5679     // We do not want to change the behavior of the machine verifier
5680     // as this is usually wrong to read an undef value.
5681     if (MachineBasicBlock::LQR_Unknown == LQR) {
5682       LivePhysRegs LPR(TRI);
5683       LPR.addLiveOuts(MBB);
5684       MachineBasicBlock::iterator I = MBB.end();
5685       while (I != MI) {
5686         --I;
5687         LPR.stepBackward(*I);
5688       }
5689       // AX contains the top most register in the aliasing hierarchy.
5690       // It may not be live, but one of its aliases may be.
5691       for (MCRegAliasIterator AI(AX, TRI, true);
5692            AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
5693         LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
5694                                 : MachineBasicBlock::LQR_Dead;
5695     }
5696     bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
5697     if (!AXDead)
5698       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
5699     if (FromEFLAGS) {
5700       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
5701       BuildMI(MBB, MI, DL, get(X86::LAHF));
5702       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
5703     }
5704     if (ToEFLAGS) {
5705       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
5706       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
5707           .addReg(X86::AL)
5708           .addImm(INT8_MAX);
5709       BuildMI(MBB, MI, DL, get(X86::SAHF));
5710     }
5711     if (!AXDead)
5712       BuildMI(MBB, MI, DL, get(Pop), AX);
5713     return;
5714   }
5715 
5716   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
5717                << " to " << RI.getName(DestReg) << '\n');
5718   llvm_unreachable("Cannot emit physreg copy instruction");
5719 }
5720 
5721 static unsigned getLoadStoreRegOpcode(unsigned Reg,
5722                                       const TargetRegisterClass *RC,
5723                                       bool isStackAligned,
5724                                       const X86Subtarget &STI,
5725                                       bool load) {
5726   bool HasAVX = STI.hasAVX();
5727   bool HasAVX512 = STI.hasAVX512();
5728   bool HasVLX = STI.hasVLX();
5729 
5730   switch (RC->getSize()) {
5731   default:
5732     llvm_unreachable("Unknown spill size");
5733   case 1:
5734     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
5735     if (STI.is64Bit())
5736       // Copying to or from a physical H register on x86-64 requires a NOREX
5737       // move.  Otherwise use a normal move.
5738       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
5739         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
5740     return load ? X86::MOV8rm : X86::MOV8mr;
5741   case 2:
5742     if (X86::VK16RegClass.hasSubClassEq(RC))
5743       return load ? X86::KMOVWkm : X86::KMOVWmk;
5744     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
5745     return load ? X86::MOV16rm : X86::MOV16mr;
5746   case 4:
5747     if (X86::GR32RegClass.hasSubClassEq(RC))
5748       return load ? X86::MOV32rm : X86::MOV32mr;
5749     if (X86::FR32XRegClass.hasSubClassEq(RC))
5750       return load ?
5751         (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
5752         (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
5753     if (X86::RFP32RegClass.hasSubClassEq(RC))
5754       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
5755     if (X86::VK32RegClass.hasSubClassEq(RC))
5756       return load ? X86::KMOVDkm : X86::KMOVDmk;
5757     llvm_unreachable("Unknown 4-byte regclass");
5758   case 8:
5759     if (X86::GR64RegClass.hasSubClassEq(RC))
5760       return load ? X86::MOV64rm : X86::MOV64mr;
5761     if (X86::FR64XRegClass.hasSubClassEq(RC))
5762       return load ?
5763         (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
5764         (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
5765     if (X86::VR64RegClass.hasSubClassEq(RC))
5766       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
5767     if (X86::RFP64RegClass.hasSubClassEq(RC))
5768       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
5769     if (X86::VK64RegClass.hasSubClassEq(RC))
5770       return load ? X86::KMOVQkm : X86::KMOVQmk;
5771     llvm_unreachable("Unknown 8-byte regclass");
5772   case 10:
5773     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
5774     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
5775   case 16: {
5776     assert(X86::VR128XRegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
5777     // If stack is realigned we can use aligned stores.
5778     if (isStackAligned)
5779       return load ?
5780         (HasVLX    ? X86::VMOVAPSZ128rm :
5781          HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
5782          HasAVX    ? X86::VMOVAPSrm :
5783                      X86::MOVAPSrm):
5784         (HasVLX    ? X86::VMOVAPSZ128mr :
5785          HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
5786          HasAVX    ? X86::VMOVAPSmr :
5787                      X86::MOVAPSmr);
5788     else
5789       return load ?
5790         (HasVLX    ? X86::VMOVUPSZ128rm :
5791          HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
5792          HasAVX    ? X86::VMOVUPSrm :
5793                      X86::MOVUPSrm):
5794         (HasVLX    ? X86::VMOVUPSZ128mr :
5795          HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
5796          HasAVX    ? X86::VMOVUPSmr :
5797                      X86::MOVUPSmr);
5798   }
5799   case 32:
5800     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
5801     // If stack is realigned we can use aligned stores.
5802     if (isStackAligned)
5803       return load ?
5804         (HasVLX    ? X86::VMOVAPSZ256rm :
5805          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
5806                      X86::VMOVAPSYrm) :
5807         (HasVLX    ? X86::VMOVAPSZ256mr :
5808          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
5809                      X86::VMOVAPSYmr);
5810     else
5811       return load ?
5812         (HasVLX    ? X86::VMOVUPSZ256rm :
5813          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
5814                      X86::VMOVUPSYrm) :
5815         (HasVLX    ? X86::VMOVUPSZ256mr :
5816          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
5817                      X86::VMOVUPSYmr);
5818   case 64:
5819     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
5820     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
5821     if (isStackAligned)
5822       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
5823     else
5824       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
5825   }
5826 }
5827 
5828 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
5829                                          int64_t &Offset,
5830                                          const TargetRegisterInfo *TRI) const {
5831   const MCInstrDesc &Desc = MemOp.getDesc();
5832   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
5833   if (MemRefBegin < 0)
5834     return false;
5835 
5836   MemRefBegin += X86II::getOperandBias(Desc);
5837 
5838   MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
5839   if (!BaseMO.isReg()) // Can be an MO_FrameIndex
5840     return false;
5841 
5842   BaseReg = BaseMO.getReg();
5843   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
5844     return false;
5845 
5846   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
5847       X86::NoRegister)
5848     return false;
5849 
5850   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
5851 
5852   // Displacement can be symbolic
5853   if (!DispMO.isImm())
5854     return false;
5855 
5856   Offset = DispMO.getImm();
5857 
5858   return MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
5859          X86::NoRegister;
5860 }
5861 
5862 static unsigned getStoreRegOpcode(unsigned SrcReg,
5863                                   const TargetRegisterClass *RC,
5864                                   bool isStackAligned,
5865                                   const X86Subtarget &STI) {
5866   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
5867 }
5868 
5869 
5870 static unsigned getLoadRegOpcode(unsigned DestReg,
5871                                  const TargetRegisterClass *RC,
5872                                  bool isStackAligned,
5873                                  const X86Subtarget &STI) {
5874   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
5875 }
5876 
5877 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
5878                                        MachineBasicBlock::iterator MI,
5879                                        unsigned SrcReg, bool isKill, int FrameIdx,
5880                                        const TargetRegisterClass *RC,
5881                                        const TargetRegisterInfo *TRI) const {
5882   const MachineFunction &MF = *MBB.getParent();
5883   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= RC->getSize() &&
5884          "Stack slot too small for store");
5885   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
5886   bool isAligned =
5887       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
5888       RI.canRealignStack(MF);
5889   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
5890   DebugLoc DL = MBB.findDebugLoc(MI);
5891   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
5892     .addReg(SrcReg, getKillRegState(isKill));
5893 }
5894 
5895 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
5896                                   bool isKill,
5897                                   SmallVectorImpl<MachineOperand> &Addr,
5898                                   const TargetRegisterClass *RC,
5899                                   MachineInstr::mmo_iterator MMOBegin,
5900                                   MachineInstr::mmo_iterator MMOEnd,
5901                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
5902   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
5903   bool isAligned = MMOBegin != MMOEnd &&
5904                    (*MMOBegin)->getAlignment() >= Alignment;
5905   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
5906   DebugLoc DL;
5907   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
5908   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
5909     MIB.addOperand(Addr[i]);
5910   MIB.addReg(SrcReg, getKillRegState(isKill));
5911   (*MIB).setMemRefs(MMOBegin, MMOEnd);
5912   NewMIs.push_back(MIB);
5913 }
5914 
5915 
5916 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
5917                                         MachineBasicBlock::iterator MI,
5918                                         unsigned DestReg, int FrameIdx,
5919                                         const TargetRegisterClass *RC,
5920                                         const TargetRegisterInfo *TRI) const {
5921   const MachineFunction &MF = *MBB.getParent();
5922   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
5923   bool isAligned =
5924       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
5925       RI.canRealignStack(MF);
5926   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
5927   DebugLoc DL = MBB.findDebugLoc(MI);
5928   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
5929 }
5930 
5931 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
5932                                  SmallVectorImpl<MachineOperand> &Addr,
5933                                  const TargetRegisterClass *RC,
5934                                  MachineInstr::mmo_iterator MMOBegin,
5935                                  MachineInstr::mmo_iterator MMOEnd,
5936                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
5937   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
5938   bool isAligned = MMOBegin != MMOEnd &&
5939                    (*MMOBegin)->getAlignment() >= Alignment;
5940   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
5941   DebugLoc DL;
5942   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
5943   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
5944     MIB.addOperand(Addr[i]);
5945   (*MIB).setMemRefs(MMOBegin, MMOEnd);
5946   NewMIs.push_back(MIB);
5947 }
5948 
5949 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
5950                                   unsigned &SrcReg2, int &CmpMask,
5951                                   int &CmpValue) const {
5952   switch (MI.getOpcode()) {
5953   default: break;
5954   case X86::CMP64ri32:
5955   case X86::CMP64ri8:
5956   case X86::CMP32ri:
5957   case X86::CMP32ri8:
5958   case X86::CMP16ri:
5959   case X86::CMP16ri8:
5960   case X86::CMP8ri:
5961     if (!MI.getOperand(1).isImm())
5962       return false;
5963     SrcReg = MI.getOperand(0).getReg();
5964     SrcReg2 = 0;
5965     CmpMask = ~0;
5966     CmpValue = MI.getOperand(1).getImm();
5967     return true;
5968   // A SUB can be used to perform comparison.
5969   case X86::SUB64rm:
5970   case X86::SUB32rm:
5971   case X86::SUB16rm:
5972   case X86::SUB8rm:
5973     SrcReg = MI.getOperand(1).getReg();
5974     SrcReg2 = 0;
5975     CmpMask = ~0;
5976     CmpValue = 0;
5977     return true;
5978   case X86::SUB64rr:
5979   case X86::SUB32rr:
5980   case X86::SUB16rr:
5981   case X86::SUB8rr:
5982     SrcReg = MI.getOperand(1).getReg();
5983     SrcReg2 = MI.getOperand(2).getReg();
5984     CmpMask = ~0;
5985     CmpValue = 0;
5986     return true;
5987   case X86::SUB64ri32:
5988   case X86::SUB64ri8:
5989   case X86::SUB32ri:
5990   case X86::SUB32ri8:
5991   case X86::SUB16ri:
5992   case X86::SUB16ri8:
5993   case X86::SUB8ri:
5994     if (!MI.getOperand(2).isImm())
5995       return false;
5996     SrcReg = MI.getOperand(1).getReg();
5997     SrcReg2 = 0;
5998     CmpMask = ~0;
5999     CmpValue = MI.getOperand(2).getImm();
6000     return true;
6001   case X86::CMP64rr:
6002   case X86::CMP32rr:
6003   case X86::CMP16rr:
6004   case X86::CMP8rr:
6005     SrcReg = MI.getOperand(0).getReg();
6006     SrcReg2 = MI.getOperand(1).getReg();
6007     CmpMask = ~0;
6008     CmpValue = 0;
6009     return true;
6010   case X86::TEST8rr:
6011   case X86::TEST16rr:
6012   case X86::TEST32rr:
6013   case X86::TEST64rr:
6014     SrcReg = MI.getOperand(0).getReg();
6015     if (MI.getOperand(1).getReg() != SrcReg)
6016       return false;
6017     // Compare against zero.
6018     SrcReg2 = 0;
6019     CmpMask = ~0;
6020     CmpValue = 0;
6021     return true;
6022   }
6023   return false;
6024 }
6025 
6026 /// Check whether the first instruction, whose only
6027 /// purpose is to update flags, can be made redundant.
6028 /// CMPrr can be made redundant by SUBrr if the operands are the same.
6029 /// This function can be extended later on.
6030 /// SrcReg, SrcRegs: register operands for FlagI.
6031 /// ImmValue: immediate for FlagI if it takes an immediate.
6032 inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
6033                                         unsigned SrcReg2, int ImmValue,
6034                                         MachineInstr &OI) {
6035   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
6036        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
6037        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
6038        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
6039       ((OI.getOperand(1).getReg() == SrcReg &&
6040         OI.getOperand(2).getReg() == SrcReg2) ||
6041        (OI.getOperand(1).getReg() == SrcReg2 &&
6042         OI.getOperand(2).getReg() == SrcReg)))
6043     return true;
6044 
6045   if (((FlagI.getOpcode() == X86::CMP64ri32 &&
6046         OI.getOpcode() == X86::SUB64ri32) ||
6047        (FlagI.getOpcode() == X86::CMP64ri8 &&
6048         OI.getOpcode() == X86::SUB64ri8) ||
6049        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
6050        (FlagI.getOpcode() == X86::CMP32ri8 &&
6051         OI.getOpcode() == X86::SUB32ri8) ||
6052        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
6053        (FlagI.getOpcode() == X86::CMP16ri8 &&
6054         OI.getOpcode() == X86::SUB16ri8) ||
6055        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
6056       OI.getOperand(1).getReg() == SrcReg &&
6057       OI.getOperand(2).getImm() == ImmValue)
6058     return true;
6059   return false;
6060 }
6061 
6062 /// Check whether the definition can be converted
6063 /// to remove a comparison against zero.
6064 inline static bool isDefConvertible(MachineInstr &MI) {
6065   switch (MI.getOpcode()) {
6066   default: return false;
6067 
6068   // The shift instructions only modify ZF if their shift count is non-zero.
6069   // N.B.: The processor truncates the shift count depending on the encoding.
6070   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
6071   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
6072      return getTruncatedShiftCount(MI, 2) != 0;
6073 
6074   // Some left shift instructions can be turned into LEA instructions but only
6075   // if their flags aren't used. Avoid transforming such instructions.
6076   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
6077     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
6078     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
6079     return ShAmt != 0;
6080   }
6081 
6082   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
6083   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
6084      return getTruncatedShiftCount(MI, 3) != 0;
6085 
6086   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
6087   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
6088   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
6089   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
6090   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
6091   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
6092   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
6093   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
6094   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
6095   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
6096   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
6097   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
6098   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
6099   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
6100   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
6101   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
6102   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
6103   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
6104   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
6105   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
6106   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
6107   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
6108   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
6109   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
6110   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
6111   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
6112   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
6113   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
6114   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
6115   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
6116   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
6117   case X86::ADC32ri:   case X86::ADC32ri8:
6118   case X86::ADC32rr:   case X86::ADC64ri32:
6119   case X86::ADC64ri8:  case X86::ADC64rr:
6120   case X86::SBB32ri:   case X86::SBB32ri8:
6121   case X86::SBB32rr:   case X86::SBB64ri32:
6122   case X86::SBB64ri8:  case X86::SBB64rr:
6123   case X86::ANDN32rr:  case X86::ANDN32rm:
6124   case X86::ANDN64rr:  case X86::ANDN64rm:
6125   case X86::BEXTR32rr: case X86::BEXTR64rr:
6126   case X86::BEXTR32rm: case X86::BEXTR64rm:
6127   case X86::BLSI32rr:  case X86::BLSI32rm:
6128   case X86::BLSI64rr:  case X86::BLSI64rm:
6129   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
6130   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
6131   case X86::BLSR32rr:  case X86::BLSR32rm:
6132   case X86::BLSR64rr:  case X86::BLSR64rm:
6133   case X86::BZHI32rr:  case X86::BZHI32rm:
6134   case X86::BZHI64rr:  case X86::BZHI64rm:
6135   case X86::LZCNT16rr: case X86::LZCNT16rm:
6136   case X86::LZCNT32rr: case X86::LZCNT32rm:
6137   case X86::LZCNT64rr: case X86::LZCNT64rm:
6138   case X86::POPCNT16rr:case X86::POPCNT16rm:
6139   case X86::POPCNT32rr:case X86::POPCNT32rm:
6140   case X86::POPCNT64rr:case X86::POPCNT64rm:
6141   case X86::TZCNT16rr: case X86::TZCNT16rm:
6142   case X86::TZCNT32rr: case X86::TZCNT32rm:
6143   case X86::TZCNT64rr: case X86::TZCNT64rm:
6144     return true;
6145   }
6146 }
6147 
6148 /// Check whether the use can be converted to remove a comparison against zero.
6149 static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
6150   switch (MI.getOpcode()) {
6151   default: return X86::COND_INVALID;
6152   case X86::LZCNT16rr: case X86::LZCNT16rm:
6153   case X86::LZCNT32rr: case X86::LZCNT32rm:
6154   case X86::LZCNT64rr: case X86::LZCNT64rm:
6155     return X86::COND_B;
6156   case X86::POPCNT16rr:case X86::POPCNT16rm:
6157   case X86::POPCNT32rr:case X86::POPCNT32rm:
6158   case X86::POPCNT64rr:case X86::POPCNT64rm:
6159     return X86::COND_E;
6160   case X86::TZCNT16rr: case X86::TZCNT16rm:
6161   case X86::TZCNT32rr: case X86::TZCNT32rm:
6162   case X86::TZCNT64rr: case X86::TZCNT64rm:
6163     return X86::COND_B;
6164   }
6165 }
6166 
6167 /// Check if there exists an earlier instruction that
6168 /// operates on the same source operands and sets flags in the same way as
6169 /// Compare; remove Compare if possible.
6170 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
6171                                         unsigned SrcReg2, int CmpMask,
6172                                         int CmpValue,
6173                                         const MachineRegisterInfo *MRI) const {
6174   // Check whether we can replace SUB with CMP.
6175   unsigned NewOpcode = 0;
6176   switch (CmpInstr.getOpcode()) {
6177   default: break;
6178   case X86::SUB64ri32:
6179   case X86::SUB64ri8:
6180   case X86::SUB32ri:
6181   case X86::SUB32ri8:
6182   case X86::SUB16ri:
6183   case X86::SUB16ri8:
6184   case X86::SUB8ri:
6185   case X86::SUB64rm:
6186   case X86::SUB32rm:
6187   case X86::SUB16rm:
6188   case X86::SUB8rm:
6189   case X86::SUB64rr:
6190   case X86::SUB32rr:
6191   case X86::SUB16rr:
6192   case X86::SUB8rr: {
6193     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
6194       return false;
6195     // There is no use of the destination register, we can replace SUB with CMP.
6196     switch (CmpInstr.getOpcode()) {
6197     default: llvm_unreachable("Unreachable!");
6198     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
6199     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
6200     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
6201     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
6202     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
6203     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
6204     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
6205     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
6206     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
6207     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
6208     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
6209     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
6210     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
6211     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
6212     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
6213     }
6214     CmpInstr.setDesc(get(NewOpcode));
6215     CmpInstr.RemoveOperand(0);
6216     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
6217     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
6218         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
6219       return false;
6220   }
6221   }
6222 
6223   // Get the unique definition of SrcReg.
6224   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
6225   if (!MI) return false;
6226 
6227   // CmpInstr is the first instruction of the BB.
6228   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
6229 
6230   // If we are comparing against zero, check whether we can use MI to update
6231   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
6232   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
6233   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
6234     return false;
6235 
6236   // If we have a use of the source register between the def and our compare
6237   // instruction we can eliminate the compare iff the use sets EFLAGS in the
6238   // right way.
6239   bool ShouldUpdateCC = false;
6240   X86::CondCode NewCC = X86::COND_INVALID;
6241   if (IsCmpZero && !isDefConvertible(*MI)) {
6242     // Scan forward from the use until we hit the use we're looking for or the
6243     // compare instruction.
6244     for (MachineBasicBlock::iterator J = MI;; ++J) {
6245       // Do we have a convertible instruction?
6246       NewCC = isUseDefConvertible(*J);
6247       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
6248           J->getOperand(1).getReg() == SrcReg) {
6249         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
6250         ShouldUpdateCC = true; // Update CC later on.
6251         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
6252         // with the new def.
6253         Def = J;
6254         MI = &*Def;
6255         break;
6256       }
6257 
6258       if (J == I)
6259         return false;
6260     }
6261   }
6262 
6263   // We are searching for an earlier instruction that can make CmpInstr
6264   // redundant and that instruction will be saved in Sub.
6265   MachineInstr *Sub = nullptr;
6266   const TargetRegisterInfo *TRI = &getRegisterInfo();
6267 
6268   // We iterate backward, starting from the instruction before CmpInstr and
6269   // stop when reaching the definition of a source register or done with the BB.
6270   // RI points to the instruction before CmpInstr.
6271   // If the definition is in this basic block, RE points to the definition;
6272   // otherwise, RE is the rend of the basic block.
6273   MachineBasicBlock::reverse_iterator
6274       RI = ++I.getReverse(),
6275       RE = CmpInstr.getParent() == MI->getParent()
6276                ? Def.getReverse() /* points to MI */
6277                : CmpInstr.getParent()->rend();
6278   MachineInstr *Movr0Inst = nullptr;
6279   for (; RI != RE; ++RI) {
6280     MachineInstr &Instr = *RI;
6281     // Check whether CmpInstr can be made redundant by the current instruction.
6282     if (!IsCmpZero &&
6283         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
6284       Sub = &Instr;
6285       break;
6286     }
6287 
6288     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
6289         Instr.readsRegister(X86::EFLAGS, TRI)) {
6290       // This instruction modifies or uses EFLAGS.
6291 
6292       // MOV32r0 etc. are implemented with xor which clobbers condition code.
6293       // They are safe to move up, if the definition to EFLAGS is dead and
6294       // earlier instructions do not read or write EFLAGS.
6295       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
6296           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
6297         Movr0Inst = &Instr;
6298         continue;
6299       }
6300 
6301       // We can't remove CmpInstr.
6302       return false;
6303     }
6304   }
6305 
6306   // Return false if no candidates exist.
6307   if (!IsCmpZero && !Sub)
6308     return false;
6309 
6310   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
6311                     Sub->getOperand(2).getReg() == SrcReg);
6312 
6313   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
6314   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
6315   // If we are done with the basic block, we need to check whether EFLAGS is
6316   // live-out.
6317   bool IsSafe = false;
6318   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
6319   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
6320   for (++I; I != E; ++I) {
6321     const MachineInstr &Instr = *I;
6322     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
6323     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
6324     // We should check the usage if this instruction uses and updates EFLAGS.
6325     if (!UseEFLAGS && ModifyEFLAGS) {
6326       // It is safe to remove CmpInstr if EFLAGS is updated again.
6327       IsSafe = true;
6328       break;
6329     }
6330     if (!UseEFLAGS && !ModifyEFLAGS)
6331       continue;
6332 
6333     // EFLAGS is used by this instruction.
6334     X86::CondCode OldCC = X86::COND_INVALID;
6335     bool OpcIsSET = false;
6336     if (IsCmpZero || IsSwapped) {
6337       // We decode the condition code from opcode.
6338       if (Instr.isBranch())
6339         OldCC = getCondFromBranchOpc(Instr.getOpcode());
6340       else {
6341         OldCC = getCondFromSETOpc(Instr.getOpcode());
6342         if (OldCC != X86::COND_INVALID)
6343           OpcIsSET = true;
6344         else
6345           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
6346       }
6347       if (OldCC == X86::COND_INVALID) return false;
6348     }
6349     if (IsCmpZero) {
6350       switch (OldCC) {
6351       default: break;
6352       case X86::COND_A: case X86::COND_AE:
6353       case X86::COND_B: case X86::COND_BE:
6354       case X86::COND_G: case X86::COND_GE:
6355       case X86::COND_L: case X86::COND_LE:
6356       case X86::COND_O: case X86::COND_NO:
6357         // CF and OF are used, we can't perform this optimization.
6358         return false;
6359       }
6360 
6361       // If we're updating the condition code check if we have to reverse the
6362       // condition.
6363       if (ShouldUpdateCC)
6364         switch (OldCC) {
6365         default:
6366           return false;
6367         case X86::COND_E:
6368           break;
6369         case X86::COND_NE:
6370           NewCC = GetOppositeBranchCondition(NewCC);
6371           break;
6372         }
6373     } else if (IsSwapped) {
6374       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
6375       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
6376       // We swap the condition code and synthesize the new opcode.
6377       NewCC = getSwappedCondition(OldCC);
6378       if (NewCC == X86::COND_INVALID) return false;
6379     }
6380 
6381     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
6382       // Synthesize the new opcode.
6383       bool HasMemoryOperand = Instr.hasOneMemOperand();
6384       unsigned NewOpc;
6385       if (Instr.isBranch())
6386         NewOpc = GetCondBranchFromCond(NewCC);
6387       else if(OpcIsSET)
6388         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
6389       else {
6390         unsigned DstReg = Instr.getOperand(0).getReg();
6391         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
6392                                  HasMemoryOperand);
6393       }
6394 
6395       // Push the MachineInstr to OpsToUpdate.
6396       // If it is safe to remove CmpInstr, the condition code of these
6397       // instructions will be modified.
6398       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
6399     }
6400     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
6401       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
6402       IsSafe = true;
6403       break;
6404     }
6405   }
6406 
6407   // If EFLAGS is not killed nor re-defined, we should check whether it is
6408   // live-out. If it is live-out, do not optimize.
6409   if ((IsCmpZero || IsSwapped) && !IsSafe) {
6410     MachineBasicBlock *MBB = CmpInstr.getParent();
6411     for (MachineBasicBlock *Successor : MBB->successors())
6412       if (Successor->isLiveIn(X86::EFLAGS))
6413         return false;
6414   }
6415 
6416   // The instruction to be updated is either Sub or MI.
6417   Sub = IsCmpZero ? MI : Sub;
6418   // Move Movr0Inst to the appropriate place before Sub.
6419   if (Movr0Inst) {
6420     // Look backwards until we find a def that doesn't use the current EFLAGS.
6421     Def = Sub;
6422     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
6423                                         InsertE = Sub->getParent()->rend();
6424     for (; InsertI != InsertE; ++InsertI) {
6425       MachineInstr *Instr = &*InsertI;
6426       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
6427           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
6428         Sub->getParent()->remove(Movr0Inst);
6429         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
6430                                    Movr0Inst);
6431         break;
6432       }
6433     }
6434     if (InsertI == InsertE)
6435       return false;
6436   }
6437 
6438   // Make sure Sub instruction defines EFLAGS and mark the def live.
6439   unsigned i = 0, e = Sub->getNumOperands();
6440   for (; i != e; ++i) {
6441     MachineOperand &MO = Sub->getOperand(i);
6442     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
6443       MO.setIsDead(false);
6444       break;
6445     }
6446   }
6447   assert(i != e && "Unable to locate a def EFLAGS operand");
6448 
6449   CmpInstr.eraseFromParent();
6450 
6451   // Modify the condition code of instructions in OpsToUpdate.
6452   for (auto &Op : OpsToUpdate)
6453     Op.first->setDesc(get(Op.second));
6454   return true;
6455 }
6456 
6457 /// Try to remove the load by folding it to a register
6458 /// operand at the use. We fold the load instructions if load defines a virtual
6459 /// register, the virtual register is used once in the same BB, and the
6460 /// instructions in-between do not load or store, and have no side effects.
6461 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
6462                                               const MachineRegisterInfo *MRI,
6463                                               unsigned &FoldAsLoadDefReg,
6464                                               MachineInstr *&DefMI) const {
6465   if (FoldAsLoadDefReg == 0)
6466     return nullptr;
6467   // To be conservative, if there exists another load, clear the load candidate.
6468   if (MI.mayLoad()) {
6469     FoldAsLoadDefReg = 0;
6470     return nullptr;
6471   }
6472 
6473   // Check whether we can move DefMI here.
6474   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
6475   assert(DefMI);
6476   bool SawStore = false;
6477   if (!DefMI->isSafeToMove(nullptr, SawStore))
6478     return nullptr;
6479 
6480   // Collect information about virtual register operands of MI.
6481   unsigned SrcOperandId = 0;
6482   bool FoundSrcOperand = false;
6483   for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
6484     MachineOperand &MO = MI.getOperand(i);
6485     if (!MO.isReg())
6486       continue;
6487     unsigned Reg = MO.getReg();
6488     if (Reg != FoldAsLoadDefReg)
6489       continue;
6490     // Do not fold if we have a subreg use or a def or multiple uses.
6491     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
6492       return nullptr;
6493 
6494     SrcOperandId = i;
6495     FoundSrcOperand = true;
6496   }
6497   if (!FoundSrcOperand)
6498     return nullptr;
6499 
6500   // Check whether we can fold the def into SrcOperandId.
6501   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, *DefMI)) {
6502     FoldAsLoadDefReg = 0;
6503     return FoldMI;
6504   }
6505 
6506   return nullptr;
6507 }
6508 
6509 /// Expand a single-def pseudo instruction to a two-addr
6510 /// instruction with two undef reads of the register being defined.
6511 /// This is used for mapping:
6512 ///   %xmm4 = V_SET0
6513 /// to:
6514 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
6515 ///
6516 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
6517                              const MCInstrDesc &Desc) {
6518   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
6519   unsigned Reg = MIB->getOperand(0).getReg();
6520   MIB->setDesc(Desc);
6521 
6522   // MachineInstr::addOperand() will insert explicit operands before any
6523   // implicit operands.
6524   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
6525   // But we don't trust that.
6526   assert(MIB->getOperand(1).getReg() == Reg &&
6527          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
6528   return true;
6529 }
6530 
6531 /// Expand a single-def pseudo instruction to a two-addr
6532 /// instruction with two %k0 reads.
6533 /// This is used for mapping:
6534 ///   %k4 = K_SET1
6535 /// to:
6536 ///   %k4 = KXNORrr %k0, %k0
6537 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
6538                             const MCInstrDesc &Desc, unsigned Reg) {
6539   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
6540   MIB->setDesc(Desc);
6541   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
6542   return true;
6543 }
6544 
6545 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
6546                           bool MinusOne) {
6547   MachineBasicBlock &MBB = *MIB->getParent();
6548   DebugLoc DL = MIB->getDebugLoc();
6549   unsigned Reg = MIB->getOperand(0).getReg();
6550 
6551   // Insert the XOR.
6552   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
6553       .addReg(Reg, RegState::Undef)
6554       .addReg(Reg, RegState::Undef);
6555 
6556   // Turn the pseudo into an INC or DEC.
6557   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
6558   MIB.addReg(Reg);
6559 
6560   return true;
6561 }
6562 
6563 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
6564                                const TargetInstrInfo &TII,
6565                                const X86Subtarget &Subtarget) {
6566   MachineBasicBlock &MBB = *MIB->getParent();
6567   DebugLoc DL = MIB->getDebugLoc();
6568   int64_t Imm = MIB->getOperand(1).getImm();
6569   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
6570   MachineBasicBlock::iterator I = MIB.getInstr();
6571 
6572   int StackAdjustment;
6573 
6574   if (Subtarget.is64Bit()) {
6575     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
6576            MIB->getOpcode() == X86::MOV32ImmSExti8);
6577 
6578     // Can't use push/pop lowering if the function might write to the red zone.
6579     X86MachineFunctionInfo *X86FI =
6580         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
6581     if (X86FI->getUsesRedZone()) {
6582       MIB->setDesc(TII.get(MIB->getOpcode() ==
6583                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
6584       return true;
6585     }
6586 
6587     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
6588     // widen the register if necessary.
6589     StackAdjustment = 8;
6590     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
6591     MIB->setDesc(TII.get(X86::POP64r));
6592     MIB->getOperand(0)
6593         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
6594   } else {
6595     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
6596     StackAdjustment = 4;
6597     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
6598     MIB->setDesc(TII.get(X86::POP32r));
6599   }
6600 
6601   // Build CFI if necessary.
6602   MachineFunction &MF = *MBB.getParent();
6603   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
6604   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
6605   bool NeedsDwarfCFI =
6606       !IsWin64Prologue &&
6607       (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
6608   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
6609   if (EmitCFI) {
6610     TFL->BuildCFI(MBB, I, DL,
6611         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
6612     TFL->BuildCFI(MBB, std::next(I), DL,
6613         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
6614   }
6615 
6616   return true;
6617 }
6618 
6619 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
6620 // code sequence is needed for other targets.
6621 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
6622                                  const TargetInstrInfo &TII) {
6623   MachineBasicBlock &MBB = *MIB->getParent();
6624   DebugLoc DL = MIB->getDebugLoc();
6625   unsigned Reg = MIB->getOperand(0).getReg();
6626   const GlobalValue *GV =
6627       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
6628   auto Flags = MachineMemOperand::MOLoad |
6629                MachineMemOperand::MODereferenceable |
6630                MachineMemOperand::MOInvariant;
6631   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
6632       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
6633   MachineBasicBlock::iterator I = MIB.getInstr();
6634 
6635   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
6636       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
6637       .addMemOperand(MMO);
6638   MIB->setDebugLoc(DL);
6639   MIB->setDesc(TII.get(X86::MOV64rm));
6640   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
6641 }
6642 
6643 // This is used to handle spills for 128/256-bit registers when we have AVX512,
6644 // but not VLX. If it uses an extended register we need to use an instruction
6645 // that loads the lower 128/256-bit, but is available with only AVX512F.
6646 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
6647                             const TargetRegisterInfo *TRI,
6648                             const MCInstrDesc &LoadDesc,
6649                             const MCInstrDesc &BroadcastDesc,
6650                             unsigned SubIdx) {
6651   unsigned DestReg = MIB->getOperand(0).getReg();
6652   // Check if DestReg is XMM16-31 or YMM16-31.
6653   if (TRI->getEncodingValue(DestReg) < 16) {
6654     // We can use a normal VEX encoded load.
6655     MIB->setDesc(LoadDesc);
6656   } else {
6657     // Use a 128/256-bit VBROADCAST instruction.
6658     MIB->setDesc(BroadcastDesc);
6659     // Change the destination to a 512-bit register.
6660     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
6661     MIB->getOperand(0).setReg(DestReg);
6662   }
6663   return true;
6664 }
6665 
6666 // This is used to handle spills for 128/256-bit registers when we have AVX512,
6667 // but not VLX. If it uses an extended register we need to use an instruction
6668 // that stores the lower 128/256-bit, but is available with only AVX512F.
6669 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
6670                              const TargetRegisterInfo *TRI,
6671                              const MCInstrDesc &StoreDesc,
6672                              const MCInstrDesc &ExtractDesc,
6673                              unsigned SubIdx) {
6674   unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
6675   // Check if DestReg is XMM16-31 or YMM16-31.
6676   if (TRI->getEncodingValue(SrcReg) < 16) {
6677     // We can use a normal VEX encoded store.
6678     MIB->setDesc(StoreDesc);
6679   } else {
6680     // Use a VEXTRACTF instruction.
6681     MIB->setDesc(ExtractDesc);
6682     // Change the destination to a 512-bit register.
6683     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
6684     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
6685     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
6686   }
6687 
6688   return true;
6689 }
6690 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
6691   bool HasAVX = Subtarget.hasAVX();
6692   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
6693   switch (MI.getOpcode()) {
6694   case X86::MOV32r0:
6695     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
6696   case X86::MOV32r1:
6697     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
6698   case X86::MOV32r_1:
6699     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
6700   case X86::MOV32ImmSExti8:
6701   case X86::MOV64ImmSExti8:
6702     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
6703   case X86::SETB_C8r:
6704     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
6705   case X86::SETB_C16r:
6706     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
6707   case X86::SETB_C32r:
6708     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
6709   case X86::SETB_C64r:
6710     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
6711   case X86::V_SET0:
6712   case X86::FsFLD0SS:
6713   case X86::FsFLD0SD:
6714     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
6715   case X86::AVX_SET0:
6716     assert(HasAVX && "AVX not supported");
6717     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
6718   case X86::AVX512_128_SET0:
6719     return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
6720   case X86::AVX512_256_SET0:
6721     return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
6722   case X86::AVX512_512_SET0:
6723     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
6724   case X86::V_SETALLONES:
6725     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
6726   case X86::AVX2_SETALLONES:
6727     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
6728   case X86::AVX512_512_SETALLONES: {
6729     unsigned Reg = MIB->getOperand(0).getReg();
6730     MIB->setDesc(get(X86::VPTERNLOGDZrri));
6731     // VPTERNLOGD needs 3 register inputs and an immediate.
6732     // 0xff will return 1s for any input.
6733     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
6734        .addReg(Reg, RegState::Undef).addImm(0xff);
6735     return true;
6736   }
6737   case X86::VMOVAPSZ128rm_NOVLX:
6738     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
6739                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
6740   case X86::VMOVUPSZ128rm_NOVLX:
6741     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
6742                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
6743   case X86::VMOVAPSZ256rm_NOVLX:
6744     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
6745                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
6746   case X86::VMOVUPSZ256rm_NOVLX:
6747     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
6748                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
6749   case X86::VMOVAPSZ128mr_NOVLX:
6750     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
6751                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
6752   case X86::VMOVUPSZ128mr_NOVLX:
6753     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
6754                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
6755   case X86::VMOVAPSZ256mr_NOVLX:
6756     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
6757                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
6758   case X86::VMOVUPSZ256mr_NOVLX:
6759     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
6760                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
6761   case X86::TEST8ri_NOREX:
6762     MI.setDesc(get(X86::TEST8ri));
6763     return true;
6764   case X86::MOV32ri64:
6765     MI.setDesc(get(X86::MOV32ri));
6766     return true;
6767 
6768   // KNL does not recognize dependency-breaking idioms for mask registers,
6769   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
6770   // Using %k0 as the undef input register is a performance heuristic based
6771   // on the assumption that %k0 is used less frequently than the other mask
6772   // registers, since it is not usable as a write mask.
6773   // FIXME: A more advanced approach would be to choose the best input mask
6774   // register based on context.
6775   case X86::KSET0B:
6776   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
6777   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
6778   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
6779   case X86::KSET1B:
6780   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
6781   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
6782   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
6783   case TargetOpcode::LOAD_STACK_GUARD:
6784     expandLoadStackGuard(MIB, *this);
6785     return true;
6786   }
6787   return false;
6788 }
6789 
6790 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
6791                         int PtrOffset = 0) {
6792   unsigned NumAddrOps = MOs.size();
6793 
6794   if (NumAddrOps < 4) {
6795     // FrameIndex only - add an immediate offset (whether its zero or not).
6796     for (unsigned i = 0; i != NumAddrOps; ++i)
6797       MIB.addOperand(MOs[i]);
6798     addOffset(MIB, PtrOffset);
6799   } else {
6800     // General Memory Addressing - we need to add any offset to an existing
6801     // offset.
6802     assert(MOs.size() == 5 && "Unexpected memory operand list length");
6803     for (unsigned i = 0; i != NumAddrOps; ++i) {
6804       const MachineOperand &MO = MOs[i];
6805       if (i == 3 && PtrOffset != 0) {
6806         MIB.addDisp(MO, PtrOffset);
6807       } else {
6808         MIB.addOperand(MO);
6809       }
6810     }
6811   }
6812 }
6813 
6814 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
6815                                      ArrayRef<MachineOperand> MOs,
6816                                      MachineBasicBlock::iterator InsertPt,
6817                                      MachineInstr &MI,
6818                                      const TargetInstrInfo &TII) {
6819   // Create the base instruction with the memory operand as the first part.
6820   // Omit the implicit operands, something BuildMI can't do.
6821   MachineInstr *NewMI =
6822       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
6823   MachineInstrBuilder MIB(MF, NewMI);
6824   addOperands(MIB, MOs);
6825 
6826   // Loop over the rest of the ri operands, converting them over.
6827   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
6828   for (unsigned i = 0; i != NumOps; ++i) {
6829     MachineOperand &MO = MI.getOperand(i + 2);
6830     MIB.addOperand(MO);
6831   }
6832   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
6833     MachineOperand &MO = MI.getOperand(i);
6834     MIB.addOperand(MO);
6835   }
6836 
6837   MachineBasicBlock *MBB = InsertPt->getParent();
6838   MBB->insert(InsertPt, NewMI);
6839 
6840   return MIB;
6841 }
6842 
6843 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
6844                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
6845                               MachineBasicBlock::iterator InsertPt,
6846                               MachineInstr &MI, const TargetInstrInfo &TII,
6847                               int PtrOffset = 0) {
6848   // Omit the implicit operands, something BuildMI can't do.
6849   MachineInstr *NewMI =
6850       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
6851   MachineInstrBuilder MIB(MF, NewMI);
6852 
6853   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6854     MachineOperand &MO = MI.getOperand(i);
6855     if (i == OpNo) {
6856       assert(MO.isReg() && "Expected to fold into reg operand!");
6857       addOperands(MIB, MOs, PtrOffset);
6858     } else {
6859       MIB.addOperand(MO);
6860     }
6861   }
6862 
6863   MachineBasicBlock *MBB = InsertPt->getParent();
6864   MBB->insert(InsertPt, NewMI);
6865 
6866   return MIB;
6867 }
6868 
6869 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
6870                                 ArrayRef<MachineOperand> MOs,
6871                                 MachineBasicBlock::iterator InsertPt,
6872                                 MachineInstr &MI) {
6873   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
6874                                     MI.getDebugLoc(), TII.get(Opcode));
6875   addOperands(MIB, MOs);
6876   return MIB.addImm(0);
6877 }
6878 
6879 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
6880     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
6881     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
6882     unsigned Size, unsigned Align) const {
6883   switch (MI.getOpcode()) {
6884   case X86::INSERTPSrr:
6885   case X86::VINSERTPSrr:
6886   case X86::VINSERTPSZrr:
6887     // Attempt to convert the load of inserted vector into a fold load
6888     // of a single float.
6889     if (OpNum == 2) {
6890       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
6891       unsigned ZMask = Imm & 15;
6892       unsigned DstIdx = (Imm >> 4) & 3;
6893       unsigned SrcIdx = (Imm >> 6) & 3;
6894 
6895       unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
6896       if (Size <= RCSize && 4 <= Align) {
6897         int PtrOffset = SrcIdx * 4;
6898         unsigned NewImm = (DstIdx << 4) | ZMask;
6899         unsigned NewOpCode =
6900             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
6901             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
6902                                                     X86::INSERTPSrm;
6903         MachineInstr *NewMI =
6904             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
6905         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
6906         return NewMI;
6907       }
6908     }
6909     break;
6910   case X86::MOVHLPSrr:
6911   case X86::VMOVHLPSrr:
6912   case X86::VMOVHLPSZrr:
6913     // Move the upper 64-bits of the second operand to the lower 64-bits.
6914     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
6915     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
6916     if (OpNum == 2) {
6917       unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
6918       if (Size <= RCSize && 8 <= Align) {
6919         unsigned NewOpCode =
6920             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
6921             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
6922                                                    X86::MOVLPSrm;
6923         MachineInstr *NewMI =
6924             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
6925         return NewMI;
6926       }
6927     }
6928     break;
6929   };
6930 
6931   return nullptr;
6932 }
6933 
6934 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6935     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
6936     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
6937     unsigned Size, unsigned Align, bool AllowCommute) const {
6938   const DenseMap<unsigned,
6939                  std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
6940   bool isCallRegIndirect = Subtarget.callRegIndirect();
6941   bool isTwoAddrFold = false;
6942 
6943   // For CPUs that favor the register form of a call or push,
6944   // do not fold loads into calls or pushes, unless optimizing for size
6945   // aggressively.
6946   if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
6947       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
6948        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
6949        MI.getOpcode() == X86::PUSH64r))
6950     return nullptr;
6951 
6952   unsigned NumOps = MI.getDesc().getNumOperands();
6953   bool isTwoAddr =
6954       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
6955 
6956   // FIXME: AsmPrinter doesn't know how to handle
6957   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
6958   if (MI.getOpcode() == X86::ADD32ri &&
6959       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
6960     return nullptr;
6961 
6962   MachineInstr *NewMI = nullptr;
6963 
6964   // Attempt to fold any custom cases we have.
6965   if (MachineInstr *CustomMI =
6966           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
6967     return CustomMI;
6968 
6969   // Folding a memory location into the two-address part of a two-address
6970   // instruction is different than folding it other places.  It requires
6971   // replacing the *two* registers with the memory location.
6972   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
6973       MI.getOperand(1).isReg() &&
6974       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
6975     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
6976     isTwoAddrFold = true;
6977   } else if (OpNum == 0) {
6978     if (MI.getOpcode() == X86::MOV32r0) {
6979       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
6980       if (NewMI)
6981         return NewMI;
6982     }
6983 
6984     OpcodeTablePtr = &RegOp2MemOpTable0;
6985   } else if (OpNum == 1) {
6986     OpcodeTablePtr = &RegOp2MemOpTable1;
6987   } else if (OpNum == 2) {
6988     OpcodeTablePtr = &RegOp2MemOpTable2;
6989   } else if (OpNum == 3) {
6990     OpcodeTablePtr = &RegOp2MemOpTable3;
6991   } else if (OpNum == 4) {
6992     OpcodeTablePtr = &RegOp2MemOpTable4;
6993   }
6994 
6995   // If table selected...
6996   if (OpcodeTablePtr) {
6997     // Find the Opcode to fuse
6998     auto I = OpcodeTablePtr->find(MI.getOpcode());
6999     if (I != OpcodeTablePtr->end()) {
7000       unsigned Opcode = I->second.first;
7001       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
7002       if (Align < MinAlign)
7003         return nullptr;
7004       bool NarrowToMOV32rm = false;
7005       if (Size) {
7006         unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
7007         if (Size < RCSize) {
7008           // Check if it's safe to fold the load. If the size of the object is
7009           // narrower than the load width, then it's not.
7010           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
7011             return nullptr;
7012           // If this is a 64-bit load, but the spill slot is 32, then we can do
7013           // a 32-bit load which is implicitly zero-extended. This likely is
7014           // due to live interval analysis remat'ing a load from stack slot.
7015           if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
7016             return nullptr;
7017           Opcode = X86::MOV32rm;
7018           NarrowToMOV32rm = true;
7019         }
7020       }
7021 
7022       if (isTwoAddrFold)
7023         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
7024       else
7025         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
7026 
7027       if (NarrowToMOV32rm) {
7028         // If this is the special case where we use a MOV32rm to load a 32-bit
7029         // value and zero-extend the top bits. Change the destination register
7030         // to a 32-bit one.
7031         unsigned DstReg = NewMI->getOperand(0).getReg();
7032         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
7033           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
7034         else
7035           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
7036       }
7037       return NewMI;
7038     }
7039   }
7040 
7041   // If the instruction and target operand are commutable, commute the
7042   // instruction and try again.
7043   if (AllowCommute) {
7044     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
7045     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
7046       bool HasDef = MI.getDesc().getNumDefs();
7047       unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
7048       unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
7049       unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
7050       bool Tied1 =
7051           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
7052       bool Tied2 =
7053           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
7054 
7055       // If either of the commutable operands are tied to the destination
7056       // then we can not commute + fold.
7057       if ((HasDef && Reg0 == Reg1 && Tied1) ||
7058           (HasDef && Reg0 == Reg2 && Tied2))
7059         return nullptr;
7060 
7061       MachineInstr *CommutedMI =
7062           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
7063       if (!CommutedMI) {
7064         // Unable to commute.
7065         return nullptr;
7066       }
7067       if (CommutedMI != &MI) {
7068         // New instruction. We can't fold from this.
7069         CommutedMI->eraseFromParent();
7070         return nullptr;
7071       }
7072 
7073       // Attempt to fold with the commuted version of the instruction.
7074       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
7075                                     Size, Align, /*AllowCommute=*/false);
7076       if (NewMI)
7077         return NewMI;
7078 
7079       // Folding failed again - undo the commute before returning.
7080       MachineInstr *UncommutedMI =
7081           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
7082       if (!UncommutedMI) {
7083         // Unable to commute.
7084         return nullptr;
7085       }
7086       if (UncommutedMI != &MI) {
7087         // New instruction. It doesn't need to be kept.
7088         UncommutedMI->eraseFromParent();
7089         return nullptr;
7090       }
7091 
7092       // Return here to prevent duplicate fuse failure report.
7093       return nullptr;
7094     }
7095   }
7096 
7097   // No fusion
7098   if (PrintFailedFusing && !MI.isCopy())
7099     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
7100   return nullptr;
7101 }
7102 
7103 /// Return true for all instructions that only update
7104 /// the first 32 or 64-bits of the destination register and leave the rest
7105 /// unmodified. This can be used to avoid folding loads if the instructions
7106 /// only update part of the destination register, and the non-updated part is
7107 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
7108 /// instructions breaks the partial register dependency and it can improve
7109 /// performance. e.g.:
7110 ///
7111 ///   movss (%rdi), %xmm0
7112 ///   cvtss2sd %xmm0, %xmm0
7113 ///
7114 /// Instead of
7115 ///   cvtss2sd (%rdi), %xmm0
7116 ///
7117 /// FIXME: This should be turned into a TSFlags.
7118 ///
7119 static bool hasPartialRegUpdate(unsigned Opcode) {
7120   switch (Opcode) {
7121   case X86::CVTSI2SSrr:
7122   case X86::CVTSI2SSrm:
7123   case X86::CVTSI2SS64rr:
7124   case X86::CVTSI2SS64rm:
7125   case X86::CVTSI2SDrr:
7126   case X86::CVTSI2SDrm:
7127   case X86::CVTSI2SD64rr:
7128   case X86::CVTSI2SD64rm:
7129   case X86::CVTSD2SSrr:
7130   case X86::CVTSD2SSrm:
7131   case X86::Int_CVTSD2SSrr:
7132   case X86::Int_CVTSD2SSrm:
7133   case X86::CVTSS2SDrr:
7134   case X86::CVTSS2SDrm:
7135   case X86::Int_CVTSS2SDrr:
7136   case X86::Int_CVTSS2SDrm:
7137   case X86::MOVHPDrm:
7138   case X86::MOVHPSrm:
7139   case X86::MOVLPDrm:
7140   case X86::MOVLPSrm:
7141   case X86::RCPSSr:
7142   case X86::RCPSSm:
7143   case X86::RCPSSr_Int:
7144   case X86::RCPSSm_Int:
7145   case X86::ROUNDSDr:
7146   case X86::ROUNDSDm:
7147   case X86::ROUNDSDr_Int:
7148   case X86::ROUNDSDm_Int:
7149   case X86::ROUNDSSr:
7150   case X86::ROUNDSSm:
7151   case X86::ROUNDSSr_Int:
7152   case X86::ROUNDSSm_Int:
7153   case X86::RSQRTSSr:
7154   case X86::RSQRTSSm:
7155   case X86::RSQRTSSr_Int:
7156   case X86::RSQRTSSm_Int:
7157   case X86::SQRTSSr:
7158   case X86::SQRTSSm:
7159   case X86::SQRTSSr_Int:
7160   case X86::SQRTSSm_Int:
7161   case X86::SQRTSDr:
7162   case X86::SQRTSDm:
7163   case X86::SQRTSDr_Int:
7164   case X86::SQRTSDm_Int:
7165     return true;
7166   }
7167 
7168   return false;
7169 }
7170 
7171 /// Inform the ExeDepsFix pass how many idle
7172 /// instructions we would like before a partial register update.
7173 unsigned X86InstrInfo::getPartialRegUpdateClearance(
7174     const MachineInstr &MI, unsigned OpNum,
7175     const TargetRegisterInfo *TRI) const {
7176   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
7177     return 0;
7178 
7179   // If MI is marked as reading Reg, the partial register update is wanted.
7180   const MachineOperand &MO = MI.getOperand(0);
7181   unsigned Reg = MO.getReg();
7182   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7183     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
7184       return 0;
7185   } else {
7186     if (MI.readsRegister(Reg, TRI))
7187       return 0;
7188   }
7189 
7190   // If any instructions in the clearance range are reading Reg, insert a
7191   // dependency breaking instruction, which is inexpensive and is likely to
7192   // be hidden in other instruction's cycles.
7193   return PartialRegUpdateClearance;
7194 }
7195 
7196 // Return true for any instruction the copies the high bits of the first source
7197 // operand into the unused high bits of the destination operand.
7198 static bool hasUndefRegUpdate(unsigned Opcode) {
7199   switch (Opcode) {
7200   case X86::VCVTSI2SSrr:
7201   case X86::VCVTSI2SSrm:
7202   case X86::Int_VCVTSI2SSrr:
7203   case X86::Int_VCVTSI2SSrm:
7204   case X86::VCVTSI2SS64rr:
7205   case X86::VCVTSI2SS64rm:
7206   case X86::Int_VCVTSI2SS64rr:
7207   case X86::Int_VCVTSI2SS64rm:
7208   case X86::VCVTSI2SDrr:
7209   case X86::VCVTSI2SDrm:
7210   case X86::Int_VCVTSI2SDrr:
7211   case X86::Int_VCVTSI2SDrm:
7212   case X86::VCVTSI2SD64rr:
7213   case X86::VCVTSI2SD64rm:
7214   case X86::Int_VCVTSI2SD64rr:
7215   case X86::Int_VCVTSI2SD64rm:
7216   case X86::VCVTSD2SSrr:
7217   case X86::VCVTSD2SSrm:
7218   case X86::Int_VCVTSD2SSrr:
7219   case X86::Int_VCVTSD2SSrm:
7220   case X86::VCVTSS2SDrr:
7221   case X86::VCVTSS2SDrm:
7222   case X86::Int_VCVTSS2SDrr:
7223   case X86::Int_VCVTSS2SDrm:
7224   case X86::VRCPSSr:
7225   case X86::VRCPSSr_Int:
7226   case X86::VRCPSSm:
7227   case X86::VRCPSSm_Int:
7228   case X86::VROUNDSDr:
7229   case X86::VROUNDSDm:
7230   case X86::VROUNDSDr_Int:
7231   case X86::VROUNDSDm_Int:
7232   case X86::VROUNDSSr:
7233   case X86::VROUNDSSm:
7234   case X86::VROUNDSSr_Int:
7235   case X86::VROUNDSSm_Int:
7236   case X86::VRSQRTSSr:
7237   case X86::VRSQRTSSr_Int:
7238   case X86::VRSQRTSSm:
7239   case X86::VRSQRTSSm_Int:
7240   case X86::VSQRTSSr:
7241   case X86::VSQRTSSr_Int:
7242   case X86::VSQRTSSm:
7243   case X86::VSQRTSSm_Int:
7244   case X86::VSQRTSDr:
7245   case X86::VSQRTSDr_Int:
7246   case X86::VSQRTSDm:
7247   case X86::VSQRTSDm_Int:
7248   // AVX-512
7249   case X86::VCVTSI2SSZrr:
7250   case X86::VCVTSI2SSZrm:
7251   case X86::VCVTSI2SSZrr_Int:
7252   case X86::VCVTSI2SSZrrb_Int:
7253   case X86::VCVTSI2SSZrm_Int:
7254   case X86::VCVTSI642SSZrr:
7255   case X86::VCVTSI642SSZrm:
7256   case X86::VCVTSI642SSZrr_Int:
7257   case X86::VCVTSI642SSZrrb_Int:
7258   case X86::VCVTSI642SSZrm_Int:
7259   case X86::VCVTSI2SDZrr:
7260   case X86::VCVTSI2SDZrm:
7261   case X86::VCVTSI2SDZrr_Int:
7262   case X86::VCVTSI2SDZrrb_Int:
7263   case X86::VCVTSI2SDZrm_Int:
7264   case X86::VCVTSI642SDZrr:
7265   case X86::VCVTSI642SDZrm:
7266   case X86::VCVTSI642SDZrr_Int:
7267   case X86::VCVTSI642SDZrrb_Int:
7268   case X86::VCVTSI642SDZrm_Int:
7269   case X86::VCVTUSI2SSZrr:
7270   case X86::VCVTUSI2SSZrm:
7271   case X86::VCVTUSI2SSZrr_Int:
7272   case X86::VCVTUSI2SSZrrb_Int:
7273   case X86::VCVTUSI2SSZrm_Int:
7274   case X86::VCVTUSI642SSZrr:
7275   case X86::VCVTUSI642SSZrm:
7276   case X86::VCVTUSI642SSZrr_Int:
7277   case X86::VCVTUSI642SSZrrb_Int:
7278   case X86::VCVTUSI642SSZrm_Int:
7279   case X86::VCVTUSI2SDZrr:
7280   case X86::VCVTUSI2SDZrm:
7281   case X86::VCVTUSI2SDZrr_Int:
7282   case X86::VCVTUSI2SDZrm_Int:
7283   case X86::VCVTUSI642SDZrr:
7284   case X86::VCVTUSI642SDZrm:
7285   case X86::VCVTUSI642SDZrr_Int:
7286   case X86::VCVTUSI642SDZrrb_Int:
7287   case X86::VCVTUSI642SDZrm_Int:
7288   case X86::VCVTSD2SSZrr:
7289   case X86::VCVTSD2SSZrrb:
7290   case X86::VCVTSD2SSZrm:
7291   case X86::VCVTSS2SDZrr:
7292   case X86::VCVTSS2SDZrrb:
7293   case X86::VCVTSS2SDZrm:
7294   case X86::VRNDSCALESDr:
7295   case X86::VRNDSCALESDrb:
7296   case X86::VRNDSCALESDm:
7297   case X86::VRNDSCALESSr:
7298   case X86::VRNDSCALESSrb:
7299   case X86::VRNDSCALESSm:
7300   case X86::VRCP14SSrr:
7301   case X86::VRCP14SSrm:
7302   case X86::VRSQRT14SSrr:
7303   case X86::VRSQRT14SSrm:
7304   case X86::VSQRTSSZr:
7305   case X86::VSQRTSSZr_Int:
7306   case X86::VSQRTSSZrb_Int:
7307   case X86::VSQRTSSZm:
7308   case X86::VSQRTSSZm_Int:
7309   case X86::VSQRTSDZr:
7310   case X86::VSQRTSDZr_Int:
7311   case X86::VSQRTSDZrb_Int:
7312   case X86::VSQRTSDZm:
7313   case X86::VSQRTSDZm_Int:
7314     return true;
7315   }
7316 
7317   return false;
7318 }
7319 
7320 /// Inform the ExeDepsFix pass how many idle instructions we would like before
7321 /// certain undef register reads.
7322 ///
7323 /// This catches the VCVTSI2SD family of instructions:
7324 ///
7325 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
7326 ///
7327 /// We should to be careful *not* to catch VXOR idioms which are presumably
7328 /// handled specially in the pipeline:
7329 ///
7330 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
7331 ///
7332 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
7333 /// high bits that are passed-through are not live.
7334 unsigned
7335 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
7336                                    const TargetRegisterInfo *TRI) const {
7337   if (!hasUndefRegUpdate(MI.getOpcode()))
7338     return 0;
7339 
7340   // Set the OpNum parameter to the first source operand.
7341   OpNum = 1;
7342 
7343   const MachineOperand &MO = MI.getOperand(OpNum);
7344   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
7345     return UndefRegClearance;
7346   }
7347   return 0;
7348 }
7349 
7350 void X86InstrInfo::breakPartialRegDependency(
7351     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
7352   unsigned Reg = MI.getOperand(OpNum).getReg();
7353   // If MI kills this register, the false dependence is already broken.
7354   if (MI.killsRegister(Reg, TRI))
7355     return;
7356 
7357   if (X86::VR128RegClass.contains(Reg)) {
7358     // These instructions are all floating point domain, so xorps is the best
7359     // choice.
7360     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
7361     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
7362         .addReg(Reg, RegState::Undef)
7363         .addReg(Reg, RegState::Undef);
7364     MI.addRegisterKilled(Reg, TRI, true);
7365   } else if (X86::VR256RegClass.contains(Reg)) {
7366     // Use vxorps to clear the full ymm register.
7367     // It wants to read and write the xmm sub-register.
7368     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
7369     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
7370         .addReg(XReg, RegState::Undef)
7371         .addReg(XReg, RegState::Undef)
7372         .addReg(Reg, RegState::ImplicitDefine);
7373     MI.addRegisterKilled(Reg, TRI, true);
7374   }
7375 }
7376 
7377 MachineInstr *
7378 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
7379                                     ArrayRef<unsigned> Ops,
7380                                     MachineBasicBlock::iterator InsertPt,
7381                                     int FrameIndex, LiveIntervals *LIS) const {
7382   // Check switch flag
7383   if (NoFusing)
7384     return nullptr;
7385 
7386   // Unless optimizing for size, don't fold to avoid partial
7387   // register update stalls
7388   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
7389     return nullptr;
7390 
7391   // Don't fold subreg spills, or reloads that use a high subreg.
7392   for (auto Op : Ops) {
7393     MachineOperand &MO = MI.getOperand(Op);
7394     auto SubReg = MO.getSubReg();
7395     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
7396       return nullptr;
7397   }
7398 
7399   const MachineFrameInfo &MFI = MF.getFrameInfo();
7400   unsigned Size = MFI.getObjectSize(FrameIndex);
7401   unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
7402   // If the function stack isn't realigned we don't want to fold instructions
7403   // that need increased alignment.
7404   if (!RI.needsStackRealignment(MF))
7405     Alignment =
7406         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
7407   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
7408     unsigned NewOpc = 0;
7409     unsigned RCSize = 0;
7410     switch (MI.getOpcode()) {
7411     default: return nullptr;
7412     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
7413     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
7414     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
7415     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
7416     }
7417     // Check if it's safe to fold the load. If the size of the object is
7418     // narrower than the load width, then it's not.
7419     if (Size < RCSize)
7420       return nullptr;
7421     // Change to CMPXXri r, 0 first.
7422     MI.setDesc(get(NewOpc));
7423     MI.getOperand(1).ChangeToImmediate(0);
7424   } else if (Ops.size() != 1)
7425     return nullptr;
7426 
7427   return foldMemoryOperandImpl(MF, MI, Ops[0],
7428                                MachineOperand::CreateFI(FrameIndex), InsertPt,
7429                                Size, Alignment, /*AllowCommute=*/true);
7430 }
7431 
7432 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
7433 /// because the latter uses contents that wouldn't be defined in the folded
7434 /// version.  For instance, this transformation isn't legal:
7435 ///   movss (%rdi), %xmm0
7436 ///   addps %xmm0, %xmm0
7437 /// ->
7438 ///   addps (%rdi), %xmm0
7439 ///
7440 /// But this one is:
7441 ///   movss (%rdi), %xmm0
7442 ///   addss %xmm0, %xmm0
7443 /// ->
7444 ///   addss (%rdi), %xmm0
7445 ///
7446 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
7447                                              const MachineInstr &UserMI,
7448                                              const MachineFunction &MF) {
7449   unsigned Opc = LoadMI.getOpcode();
7450   unsigned UserOpc = UserMI.getOpcode();
7451   unsigned RegSize =
7452       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
7453 
7454   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
7455       RegSize > 4) {
7456     // These instructions only load 32 bits, we can't fold them if the
7457     // destination register is wider than 32 bits (4 bytes), and its user
7458     // instruction isn't scalar (SS).
7459     switch (UserOpc) {
7460     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
7461     case X86::Int_CMPSSrr: case X86::Int_VCMPSSrr: case X86::VCMPSSZrr_Int:
7462     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
7463     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
7464     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
7465     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
7466     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
7467     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
7468     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
7469     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
7470     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
7471     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
7472     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
7473     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
7474     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
7475     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
7476     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
7477     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
7478     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
7479     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
7480     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
7481       return false;
7482     default:
7483       return true;
7484     }
7485   }
7486 
7487   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
7488       RegSize > 8) {
7489     // These instructions only load 64 bits, we can't fold them if the
7490     // destination register is wider than 64 bits (8 bytes), and its user
7491     // instruction isn't scalar (SD).
7492     switch (UserOpc) {
7493     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
7494     case X86::Int_CMPSDrr: case X86::Int_VCMPSDrr: case X86::VCMPSDZrr_Int:
7495     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
7496     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
7497     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
7498     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
7499     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
7500     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
7501     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
7502     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
7503     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
7504     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
7505     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
7506     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
7507     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
7508     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
7509     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
7510     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
7511     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
7512     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
7513     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
7514       return false;
7515     default:
7516       return true;
7517     }
7518   }
7519 
7520   return false;
7521 }
7522 
7523 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
7524     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
7525     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
7526     LiveIntervals *LIS) const {
7527 
7528   // TODO: Support the case where LoadMI loads a wide register, but MI
7529   // only uses a subreg.
7530   for (auto Op : Ops) {
7531     if (MI.getOperand(Op).getSubReg())
7532       return nullptr;
7533   }
7534 
7535   // If loading from a FrameIndex, fold directly from the FrameIndex.
7536   unsigned NumOps = LoadMI.getDesc().getNumOperands();
7537   int FrameIndex;
7538   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
7539     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
7540       return nullptr;
7541     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
7542   }
7543 
7544   // Check switch flag
7545   if (NoFusing) return nullptr;
7546 
7547   // Avoid partial register update stalls unless optimizing for size.
7548   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
7549     return nullptr;
7550 
7551   // Determine the alignment of the load.
7552   unsigned Alignment = 0;
7553   if (LoadMI.hasOneMemOperand())
7554     Alignment = (*LoadMI.memoperands_begin())->getAlignment();
7555   else
7556     switch (LoadMI.getOpcode()) {
7557     case X86::AVX512_512_SET0:
7558     case X86::AVX512_512_SETALLONES:
7559       Alignment = 64;
7560       break;
7561     case X86::AVX2_SETALLONES:
7562     case X86::AVX_SET0:
7563     case X86::AVX512_256_SET0:
7564       Alignment = 32;
7565       break;
7566     case X86::V_SET0:
7567     case X86::V_SETALLONES:
7568     case X86::AVX512_128_SET0:
7569       Alignment = 16;
7570       break;
7571     case X86::FsFLD0SD:
7572       Alignment = 8;
7573       break;
7574     case X86::FsFLD0SS:
7575       Alignment = 4;
7576       break;
7577     default:
7578       return nullptr;
7579     }
7580   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
7581     unsigned NewOpc = 0;
7582     switch (MI.getOpcode()) {
7583     default: return nullptr;
7584     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
7585     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
7586     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
7587     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
7588     }
7589     // Change to CMPXXri r, 0 first.
7590     MI.setDesc(get(NewOpc));
7591     MI.getOperand(1).ChangeToImmediate(0);
7592   } else if (Ops.size() != 1)
7593     return nullptr;
7594 
7595   // Make sure the subregisters match.
7596   // Otherwise we risk changing the size of the load.
7597   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
7598     return nullptr;
7599 
7600   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
7601   switch (LoadMI.getOpcode()) {
7602   case X86::V_SET0:
7603   case X86::V_SETALLONES:
7604   case X86::AVX2_SETALLONES:
7605   case X86::AVX_SET0:
7606   case X86::AVX512_128_SET0:
7607   case X86::AVX512_256_SET0:
7608   case X86::AVX512_512_SET0:
7609   case X86::AVX512_512_SETALLONES:
7610   case X86::FsFLD0SD:
7611   case X86::FsFLD0SS: {
7612     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
7613     // Create a constant-pool entry and operands to load from it.
7614 
7615     // Medium and large mode can't fold loads this way.
7616     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
7617         MF.getTarget().getCodeModel() != CodeModel::Kernel)
7618       return nullptr;
7619 
7620     // x86-32 PIC requires a PIC base register for constant pools.
7621     unsigned PICBase = 0;
7622     if (MF.getTarget().isPositionIndependent()) {
7623       if (Subtarget.is64Bit())
7624         PICBase = X86::RIP;
7625       else
7626         // FIXME: PICBase = getGlobalBaseReg(&MF);
7627         // This doesn't work for several reasons.
7628         // 1. GlobalBaseReg may have been spilled.
7629         // 2. It may not be live at MI.
7630         return nullptr;
7631     }
7632 
7633     // Create a constant-pool entry.
7634     MachineConstantPool &MCP = *MF.getConstantPool();
7635     Type *Ty;
7636     unsigned Opc = LoadMI.getOpcode();
7637     if (Opc == X86::FsFLD0SS)
7638       Ty = Type::getFloatTy(MF.getFunction()->getContext());
7639     else if (Opc == X86::FsFLD0SD)
7640       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
7641     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
7642       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
7643     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
7644              Opc == X86::AVX512_256_SET0)
7645       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
7646     else
7647       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
7648 
7649     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
7650                       Opc == X86::AVX512_512_SETALLONES);
7651     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
7652                                     Constant::getNullValue(Ty);
7653     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
7654 
7655     // Create operands to load from the constant pool entry.
7656     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
7657     MOs.push_back(MachineOperand::CreateImm(1));
7658     MOs.push_back(MachineOperand::CreateReg(0, false));
7659     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
7660     MOs.push_back(MachineOperand::CreateReg(0, false));
7661     break;
7662   }
7663   default: {
7664     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
7665       return nullptr;
7666 
7667     // Folding a normal load. Just copy the load's address operands.
7668     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
7669                LoadMI.operands_begin() + NumOps);
7670     break;
7671   }
7672   }
7673   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
7674                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
7675 }
7676 
7677 bool X86InstrInfo::unfoldMemoryOperand(
7678     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
7679     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
7680   auto I = MemOp2RegOpTable.find(MI.getOpcode());
7681   if (I == MemOp2RegOpTable.end())
7682     return false;
7683   unsigned Opc = I->second.first;
7684   unsigned Index = I->second.second & TB_INDEX_MASK;
7685   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
7686   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
7687   if (UnfoldLoad && !FoldedLoad)
7688     return false;
7689   UnfoldLoad &= FoldedLoad;
7690   if (UnfoldStore && !FoldedStore)
7691     return false;
7692   UnfoldStore &= FoldedStore;
7693 
7694   const MCInstrDesc &MCID = get(Opc);
7695   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
7696   // TODO: Check if 32-byte or greater accesses are slow too?
7697   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
7698       Subtarget.isUnalignedMem16Slow())
7699     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
7700     // conservatively assume the address is unaligned. That's bad for
7701     // performance.
7702     return false;
7703   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
7704   SmallVector<MachineOperand,2> BeforeOps;
7705   SmallVector<MachineOperand,2> AfterOps;
7706   SmallVector<MachineOperand,4> ImpOps;
7707   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
7708     MachineOperand &Op = MI.getOperand(i);
7709     if (i >= Index && i < Index + X86::AddrNumOperands)
7710       AddrOps.push_back(Op);
7711     else if (Op.isReg() && Op.isImplicit())
7712       ImpOps.push_back(Op);
7713     else if (i < Index)
7714       BeforeOps.push_back(Op);
7715     else if (i > Index)
7716       AfterOps.push_back(Op);
7717   }
7718 
7719   // Emit the load instruction.
7720   if (UnfoldLoad) {
7721     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
7722         MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
7723     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
7724     if (UnfoldStore) {
7725       // Address operands cannot be marked isKill.
7726       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
7727         MachineOperand &MO = NewMIs[0]->getOperand(i);
7728         if (MO.isReg())
7729           MO.setIsKill(false);
7730       }
7731     }
7732   }
7733 
7734   // Emit the data processing instruction.
7735   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
7736   MachineInstrBuilder MIB(MF, DataMI);
7737 
7738   if (FoldedStore)
7739     MIB.addReg(Reg, RegState::Define);
7740   for (MachineOperand &BeforeOp : BeforeOps)
7741     MIB.addOperand(BeforeOp);
7742   if (FoldedLoad)
7743     MIB.addReg(Reg);
7744   for (MachineOperand &AfterOp : AfterOps)
7745     MIB.addOperand(AfterOp);
7746   for (MachineOperand &ImpOp : ImpOps) {
7747     MIB.addReg(ImpOp.getReg(),
7748                getDefRegState(ImpOp.isDef()) |
7749                RegState::Implicit |
7750                getKillRegState(ImpOp.isKill()) |
7751                getDeadRegState(ImpOp.isDead()) |
7752                getUndefRegState(ImpOp.isUndef()));
7753   }
7754   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
7755   switch (DataMI->getOpcode()) {
7756   default: break;
7757   case X86::CMP64ri32:
7758   case X86::CMP64ri8:
7759   case X86::CMP32ri:
7760   case X86::CMP32ri8:
7761   case X86::CMP16ri:
7762   case X86::CMP16ri8:
7763   case X86::CMP8ri: {
7764     MachineOperand &MO0 = DataMI->getOperand(0);
7765     MachineOperand &MO1 = DataMI->getOperand(1);
7766     if (MO1.getImm() == 0) {
7767       unsigned NewOpc;
7768       switch (DataMI->getOpcode()) {
7769       default: llvm_unreachable("Unreachable!");
7770       case X86::CMP64ri8:
7771       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
7772       case X86::CMP32ri8:
7773       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
7774       case X86::CMP16ri8:
7775       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
7776       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
7777       }
7778       DataMI->setDesc(get(NewOpc));
7779       MO1.ChangeToRegister(MO0.getReg(), false);
7780     }
7781   }
7782   }
7783   NewMIs.push_back(DataMI);
7784 
7785   // Emit the store instruction.
7786   if (UnfoldStore) {
7787     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
7788     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
7789         MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
7790     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
7791   }
7792 
7793   return true;
7794 }
7795 
7796 bool
7797 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
7798                                   SmallVectorImpl<SDNode*> &NewNodes) const {
7799   if (!N->isMachineOpcode())
7800     return false;
7801 
7802   auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
7803   if (I == MemOp2RegOpTable.end())
7804     return false;
7805   unsigned Opc = I->second.first;
7806   unsigned Index = I->second.second & TB_INDEX_MASK;
7807   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
7808   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
7809   const MCInstrDesc &MCID = get(Opc);
7810   MachineFunction &MF = DAG.getMachineFunction();
7811   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
7812   unsigned NumDefs = MCID.NumDefs;
7813   std::vector<SDValue> AddrOps;
7814   std::vector<SDValue> BeforeOps;
7815   std::vector<SDValue> AfterOps;
7816   SDLoc dl(N);
7817   unsigned NumOps = N->getNumOperands();
7818   for (unsigned i = 0; i != NumOps-1; ++i) {
7819     SDValue Op = N->getOperand(i);
7820     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
7821       AddrOps.push_back(Op);
7822     else if (i < Index-NumDefs)
7823       BeforeOps.push_back(Op);
7824     else if (i > Index-NumDefs)
7825       AfterOps.push_back(Op);
7826   }
7827   SDValue Chain = N->getOperand(NumOps-1);
7828   AddrOps.push_back(Chain);
7829 
7830   // Emit the load instruction.
7831   SDNode *Load = nullptr;
7832   if (FoldedLoad) {
7833     EVT VT = *RC->vt_begin();
7834     std::pair<MachineInstr::mmo_iterator,
7835               MachineInstr::mmo_iterator> MMOs =
7836       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
7837                             cast<MachineSDNode>(N)->memoperands_end());
7838     if (!(*MMOs.first) &&
7839         RC == &X86::VR128RegClass &&
7840         Subtarget.isUnalignedMem16Slow())
7841       // Do not introduce a slow unaligned load.
7842       return false;
7843     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
7844     // memory access is slow above.
7845     unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
7846     bool isAligned = (*MMOs.first) &&
7847                      (*MMOs.first)->getAlignment() >= Alignment;
7848     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
7849                               VT, MVT::Other, AddrOps);
7850     NewNodes.push_back(Load);
7851 
7852     // Preserve memory reference information.
7853     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
7854   }
7855 
7856   // Emit the data processing instruction.
7857   std::vector<EVT> VTs;
7858   const TargetRegisterClass *DstRC = nullptr;
7859   if (MCID.getNumDefs() > 0) {
7860     DstRC = getRegClass(MCID, 0, &RI, MF);
7861     VTs.push_back(*DstRC->vt_begin());
7862   }
7863   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
7864     EVT VT = N->getValueType(i);
7865     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
7866       VTs.push_back(VT);
7867   }
7868   if (Load)
7869     BeforeOps.push_back(SDValue(Load, 0));
7870   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
7871   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
7872   NewNodes.push_back(NewNode);
7873 
7874   // Emit the store instruction.
7875   if (FoldedStore) {
7876     AddrOps.pop_back();
7877     AddrOps.push_back(SDValue(NewNode, 0));
7878     AddrOps.push_back(Chain);
7879     std::pair<MachineInstr::mmo_iterator,
7880               MachineInstr::mmo_iterator> MMOs =
7881       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
7882                              cast<MachineSDNode>(N)->memoperands_end());
7883     if (!(*MMOs.first) &&
7884         RC == &X86::VR128RegClass &&
7885         Subtarget.isUnalignedMem16Slow())
7886       // Do not introduce a slow unaligned store.
7887       return false;
7888     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
7889     // memory access is slow above.
7890     unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
7891     bool isAligned = (*MMOs.first) &&
7892                      (*MMOs.first)->getAlignment() >= Alignment;
7893     SDNode *Store =
7894         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
7895                            dl, MVT::Other, AddrOps);
7896     NewNodes.push_back(Store);
7897 
7898     // Preserve memory reference information.
7899     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
7900   }
7901 
7902   return true;
7903 }
7904 
7905 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
7906                                       bool UnfoldLoad, bool UnfoldStore,
7907                                       unsigned *LoadRegIndex) const {
7908   auto I = MemOp2RegOpTable.find(Opc);
7909   if (I == MemOp2RegOpTable.end())
7910     return 0;
7911   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
7912   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
7913   if (UnfoldLoad && !FoldedLoad)
7914     return 0;
7915   if (UnfoldStore && !FoldedStore)
7916     return 0;
7917   if (LoadRegIndex)
7918     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
7919   return I->second.first;
7920 }
7921 
7922 bool
7923 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
7924                                      int64_t &Offset1, int64_t &Offset2) const {
7925   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
7926     return false;
7927   unsigned Opc1 = Load1->getMachineOpcode();
7928   unsigned Opc2 = Load2->getMachineOpcode();
7929   switch (Opc1) {
7930   default: return false;
7931   case X86::MOV8rm:
7932   case X86::MOV16rm:
7933   case X86::MOV32rm:
7934   case X86::MOV64rm:
7935   case X86::LD_Fp32m:
7936   case X86::LD_Fp64m:
7937   case X86::LD_Fp80m:
7938   case X86::MOVSSrm:
7939   case X86::MOVSDrm:
7940   case X86::MMX_MOVD64rm:
7941   case X86::MMX_MOVQ64rm:
7942   case X86::MOVAPSrm:
7943   case X86::MOVUPSrm:
7944   case X86::MOVAPDrm:
7945   case X86::MOVUPDrm:
7946   case X86::MOVDQArm:
7947   case X86::MOVDQUrm:
7948   // AVX load instructions
7949   case X86::VMOVSSrm:
7950   case X86::VMOVSDrm:
7951   case X86::VMOVAPSrm:
7952   case X86::VMOVUPSrm:
7953   case X86::VMOVAPDrm:
7954   case X86::VMOVUPDrm:
7955   case X86::VMOVDQArm:
7956   case X86::VMOVDQUrm:
7957   case X86::VMOVAPSYrm:
7958   case X86::VMOVUPSYrm:
7959   case X86::VMOVAPDYrm:
7960   case X86::VMOVUPDYrm:
7961   case X86::VMOVDQAYrm:
7962   case X86::VMOVDQUYrm:
7963   // AVX512 load instructions
7964   case X86::VMOVSSZrm:
7965   case X86::VMOVSDZrm:
7966   case X86::VMOVAPSZ128rm:
7967   case X86::VMOVUPSZ128rm:
7968   case X86::VMOVAPSZ128rm_NOVLX:
7969   case X86::VMOVUPSZ128rm_NOVLX:
7970   case X86::VMOVAPDZ128rm:
7971   case X86::VMOVUPDZ128rm:
7972   case X86::VMOVDQU8Z128rm:
7973   case X86::VMOVDQU16Z128rm:
7974   case X86::VMOVDQA32Z128rm:
7975   case X86::VMOVDQU32Z128rm:
7976   case X86::VMOVDQA64Z128rm:
7977   case X86::VMOVDQU64Z128rm:
7978   case X86::VMOVAPSZ256rm:
7979   case X86::VMOVUPSZ256rm:
7980   case X86::VMOVAPSZ256rm_NOVLX:
7981   case X86::VMOVUPSZ256rm_NOVLX:
7982   case X86::VMOVAPDZ256rm:
7983   case X86::VMOVUPDZ256rm:
7984   case X86::VMOVDQU8Z256rm:
7985   case X86::VMOVDQU16Z256rm:
7986   case X86::VMOVDQA32Z256rm:
7987   case X86::VMOVDQU32Z256rm:
7988   case X86::VMOVDQA64Z256rm:
7989   case X86::VMOVDQU64Z256rm:
7990   case X86::VMOVAPSZrm:
7991   case X86::VMOVUPSZrm:
7992   case X86::VMOVAPDZrm:
7993   case X86::VMOVUPDZrm:
7994   case X86::VMOVDQU8Zrm:
7995   case X86::VMOVDQU16Zrm:
7996   case X86::VMOVDQA32Zrm:
7997   case X86::VMOVDQU32Zrm:
7998   case X86::VMOVDQA64Zrm:
7999   case X86::VMOVDQU64Zrm:
8000   case X86::KMOVBkm:
8001   case X86::KMOVWkm:
8002   case X86::KMOVDkm:
8003   case X86::KMOVQkm:
8004     break;
8005   }
8006   switch (Opc2) {
8007   default: return false;
8008   case X86::MOV8rm:
8009   case X86::MOV16rm:
8010   case X86::MOV32rm:
8011   case X86::MOV64rm:
8012   case X86::LD_Fp32m:
8013   case X86::LD_Fp64m:
8014   case X86::LD_Fp80m:
8015   case X86::MOVSSrm:
8016   case X86::MOVSDrm:
8017   case X86::MMX_MOVD64rm:
8018   case X86::MMX_MOVQ64rm:
8019   case X86::MOVAPSrm:
8020   case X86::MOVUPSrm:
8021   case X86::MOVAPDrm:
8022   case X86::MOVUPDrm:
8023   case X86::MOVDQArm:
8024   case X86::MOVDQUrm:
8025   // AVX load instructions
8026   case X86::VMOVSSrm:
8027   case X86::VMOVSDrm:
8028   case X86::VMOVAPSrm:
8029   case X86::VMOVUPSrm:
8030   case X86::VMOVAPDrm:
8031   case X86::VMOVUPDrm:
8032   case X86::VMOVDQArm:
8033   case X86::VMOVDQUrm:
8034   case X86::VMOVAPSYrm:
8035   case X86::VMOVUPSYrm:
8036   case X86::VMOVAPDYrm:
8037   case X86::VMOVUPDYrm:
8038   case X86::VMOVDQAYrm:
8039   case X86::VMOVDQUYrm:
8040   // AVX512 load instructions
8041   case X86::VMOVSSZrm:
8042   case X86::VMOVSDZrm:
8043   case X86::VMOVAPSZ128rm:
8044   case X86::VMOVUPSZ128rm:
8045   case X86::VMOVAPSZ128rm_NOVLX:
8046   case X86::VMOVUPSZ128rm_NOVLX:
8047   case X86::VMOVAPDZ128rm:
8048   case X86::VMOVUPDZ128rm:
8049   case X86::VMOVDQU8Z128rm:
8050   case X86::VMOVDQU16Z128rm:
8051   case X86::VMOVDQA32Z128rm:
8052   case X86::VMOVDQU32Z128rm:
8053   case X86::VMOVDQA64Z128rm:
8054   case X86::VMOVDQU64Z128rm:
8055   case X86::VMOVAPSZ256rm:
8056   case X86::VMOVUPSZ256rm:
8057   case X86::VMOVAPSZ256rm_NOVLX:
8058   case X86::VMOVUPSZ256rm_NOVLX:
8059   case X86::VMOVAPDZ256rm:
8060   case X86::VMOVUPDZ256rm:
8061   case X86::VMOVDQU8Z256rm:
8062   case X86::VMOVDQU16Z256rm:
8063   case X86::VMOVDQA32Z256rm:
8064   case X86::VMOVDQU32Z256rm:
8065   case X86::VMOVDQA64Z256rm:
8066   case X86::VMOVDQU64Z256rm:
8067   case X86::VMOVAPSZrm:
8068   case X86::VMOVUPSZrm:
8069   case X86::VMOVAPDZrm:
8070   case X86::VMOVUPDZrm:
8071   case X86::VMOVDQU8Zrm:
8072   case X86::VMOVDQU16Zrm:
8073   case X86::VMOVDQA32Zrm:
8074   case X86::VMOVDQU32Zrm:
8075   case X86::VMOVDQA64Zrm:
8076   case X86::VMOVDQU64Zrm:
8077   case X86::KMOVBkm:
8078   case X86::KMOVWkm:
8079   case X86::KMOVDkm:
8080   case X86::KMOVQkm:
8081     break;
8082   }
8083 
8084   // Check if chain operands and base addresses match.
8085   if (Load1->getOperand(0) != Load2->getOperand(0) ||
8086       Load1->getOperand(5) != Load2->getOperand(5))
8087     return false;
8088   // Segment operands should match as well.
8089   if (Load1->getOperand(4) != Load2->getOperand(4))
8090     return false;
8091   // Scale should be 1, Index should be Reg0.
8092   if (Load1->getOperand(1) == Load2->getOperand(1) &&
8093       Load1->getOperand(2) == Load2->getOperand(2)) {
8094     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
8095       return false;
8096 
8097     // Now let's examine the displacements.
8098     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
8099         isa<ConstantSDNode>(Load2->getOperand(3))) {
8100       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
8101       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
8102       return true;
8103     }
8104   }
8105   return false;
8106 }
8107 
8108 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
8109                                            int64_t Offset1, int64_t Offset2,
8110                                            unsigned NumLoads) const {
8111   assert(Offset2 > Offset1);
8112   if ((Offset2 - Offset1) / 8 > 64)
8113     return false;
8114 
8115   unsigned Opc1 = Load1->getMachineOpcode();
8116   unsigned Opc2 = Load2->getMachineOpcode();
8117   if (Opc1 != Opc2)
8118     return false;  // FIXME: overly conservative?
8119 
8120   switch (Opc1) {
8121   default: break;
8122   case X86::LD_Fp32m:
8123   case X86::LD_Fp64m:
8124   case X86::LD_Fp80m:
8125   case X86::MMX_MOVD64rm:
8126   case X86::MMX_MOVQ64rm:
8127     return false;
8128   }
8129 
8130   EVT VT = Load1->getValueType(0);
8131   switch (VT.getSimpleVT().SimpleTy) {
8132   default:
8133     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
8134     // have 16 of them to play with.
8135     if (Subtarget.is64Bit()) {
8136       if (NumLoads >= 3)
8137         return false;
8138     } else if (NumLoads) {
8139       return false;
8140     }
8141     break;
8142   case MVT::i8:
8143   case MVT::i16:
8144   case MVT::i32:
8145   case MVT::i64:
8146   case MVT::f32:
8147   case MVT::f64:
8148     if (NumLoads)
8149       return false;
8150     break;
8151   }
8152 
8153   return true;
8154 }
8155 
8156 bool X86InstrInfo::shouldScheduleAdjacent(const MachineInstr &First,
8157                                           const MachineInstr &Second) const {
8158   // Check if this processor supports macro-fusion. Since this is a minor
8159   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
8160   // proxy for SandyBridge+.
8161   if (!Subtarget.hasAVX())
8162     return false;
8163 
8164   enum {
8165     FuseTest,
8166     FuseCmp,
8167     FuseInc
8168   } FuseKind;
8169 
8170   switch (Second.getOpcode()) {
8171   default:
8172     return false;
8173   case X86::JE_1:
8174   case X86::JNE_1:
8175   case X86::JL_1:
8176   case X86::JLE_1:
8177   case X86::JG_1:
8178   case X86::JGE_1:
8179     FuseKind = FuseInc;
8180     break;
8181   case X86::JB_1:
8182   case X86::JBE_1:
8183   case X86::JA_1:
8184   case X86::JAE_1:
8185     FuseKind = FuseCmp;
8186     break;
8187   case X86::JS_1:
8188   case X86::JNS_1:
8189   case X86::JP_1:
8190   case X86::JNP_1:
8191   case X86::JO_1:
8192   case X86::JNO_1:
8193     FuseKind = FuseTest;
8194     break;
8195   }
8196   switch (First.getOpcode()) {
8197   default:
8198     return false;
8199   case X86::TEST8rr:
8200   case X86::TEST16rr:
8201   case X86::TEST32rr:
8202   case X86::TEST64rr:
8203   case X86::TEST8ri:
8204   case X86::TEST16ri:
8205   case X86::TEST32ri:
8206   case X86::TEST32i32:
8207   case X86::TEST64i32:
8208   case X86::TEST64ri32:
8209   case X86::TEST8rm:
8210   case X86::TEST16rm:
8211   case X86::TEST32rm:
8212   case X86::TEST64rm:
8213   case X86::TEST8ri_NOREX:
8214   case X86::AND16i16:
8215   case X86::AND16ri:
8216   case X86::AND16ri8:
8217   case X86::AND16rm:
8218   case X86::AND16rr:
8219   case X86::AND32i32:
8220   case X86::AND32ri:
8221   case X86::AND32ri8:
8222   case X86::AND32rm:
8223   case X86::AND32rr:
8224   case X86::AND64i32:
8225   case X86::AND64ri32:
8226   case X86::AND64ri8:
8227   case X86::AND64rm:
8228   case X86::AND64rr:
8229   case X86::AND8i8:
8230   case X86::AND8ri:
8231   case X86::AND8rm:
8232   case X86::AND8rr:
8233     return true;
8234   case X86::CMP16i16:
8235   case X86::CMP16ri:
8236   case X86::CMP16ri8:
8237   case X86::CMP16rm:
8238   case X86::CMP16rr:
8239   case X86::CMP32i32:
8240   case X86::CMP32ri:
8241   case X86::CMP32ri8:
8242   case X86::CMP32rm:
8243   case X86::CMP32rr:
8244   case X86::CMP64i32:
8245   case X86::CMP64ri32:
8246   case X86::CMP64ri8:
8247   case X86::CMP64rm:
8248   case X86::CMP64rr:
8249   case X86::CMP8i8:
8250   case X86::CMP8ri:
8251   case X86::CMP8rm:
8252   case X86::CMP8rr:
8253   case X86::ADD16i16:
8254   case X86::ADD16ri:
8255   case X86::ADD16ri8:
8256   case X86::ADD16ri8_DB:
8257   case X86::ADD16ri_DB:
8258   case X86::ADD16rm:
8259   case X86::ADD16rr:
8260   case X86::ADD16rr_DB:
8261   case X86::ADD32i32:
8262   case X86::ADD32ri:
8263   case X86::ADD32ri8:
8264   case X86::ADD32ri8_DB:
8265   case X86::ADD32ri_DB:
8266   case X86::ADD32rm:
8267   case X86::ADD32rr:
8268   case X86::ADD32rr_DB:
8269   case X86::ADD64i32:
8270   case X86::ADD64ri32:
8271   case X86::ADD64ri32_DB:
8272   case X86::ADD64ri8:
8273   case X86::ADD64ri8_DB:
8274   case X86::ADD64rm:
8275   case X86::ADD64rr:
8276   case X86::ADD64rr_DB:
8277   case X86::ADD8i8:
8278   case X86::ADD8mi:
8279   case X86::ADD8mr:
8280   case X86::ADD8ri:
8281   case X86::ADD8rm:
8282   case X86::ADD8rr:
8283   case X86::SUB16i16:
8284   case X86::SUB16ri:
8285   case X86::SUB16ri8:
8286   case X86::SUB16rm:
8287   case X86::SUB16rr:
8288   case X86::SUB32i32:
8289   case X86::SUB32ri:
8290   case X86::SUB32ri8:
8291   case X86::SUB32rm:
8292   case X86::SUB32rr:
8293   case X86::SUB64i32:
8294   case X86::SUB64ri32:
8295   case X86::SUB64ri8:
8296   case X86::SUB64rm:
8297   case X86::SUB64rr:
8298   case X86::SUB8i8:
8299   case X86::SUB8ri:
8300   case X86::SUB8rm:
8301   case X86::SUB8rr:
8302     return FuseKind == FuseCmp || FuseKind == FuseInc;
8303   case X86::INC16r:
8304   case X86::INC32r:
8305   case X86::INC64r:
8306   case X86::INC8r:
8307   case X86::DEC16r:
8308   case X86::DEC32r:
8309   case X86::DEC64r:
8310   case X86::DEC8r:
8311     return FuseKind == FuseInc;
8312   }
8313 }
8314 
8315 bool X86InstrInfo::
8316 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
8317   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
8318   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
8319   Cond[0].setImm(GetOppositeBranchCondition(CC));
8320   return false;
8321 }
8322 
8323 bool X86InstrInfo::
8324 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
8325   // FIXME: Return false for x87 stack register classes for now. We can't
8326   // allow any loads of these registers before FpGet_ST0_80.
8327   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
8328            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
8329 }
8330 
8331 /// Return a virtual register initialized with the
8332 /// the global base register value. Output instructions required to
8333 /// initialize the register in the function entry block, if necessary.
8334 ///
8335 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
8336 ///
8337 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
8338   assert(!Subtarget.is64Bit() &&
8339          "X86-64 PIC uses RIP relative addressing");
8340 
8341   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
8342   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
8343   if (GlobalBaseReg != 0)
8344     return GlobalBaseReg;
8345 
8346   // Create the register. The code to initialize it is inserted
8347   // later, by the CGBR pass (below).
8348   MachineRegisterInfo &RegInfo = MF->getRegInfo();
8349   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
8350   X86FI->setGlobalBaseReg(GlobalBaseReg);
8351   return GlobalBaseReg;
8352 }
8353 
8354 // These are the replaceable SSE instructions. Some of these have Int variants
8355 // that we don't include here. We don't want to replace instructions selected
8356 // by intrinsics.
8357 static const uint16_t ReplaceableInstrs[][3] = {
8358   //PackedSingle     PackedDouble    PackedInt
8359   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
8360   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
8361   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
8362   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
8363   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
8364   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr  },
8365   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
8366   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
8367   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
8368   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
8369   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
8370   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
8371   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
8372   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
8373   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
8374   // AVX 128-bit support
8375   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
8376   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
8377   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
8378   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
8379   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
8380   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr  },
8381   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
8382   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
8383   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
8384   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
8385   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
8386   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
8387   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
8388   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
8389   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
8390   // AVX 256-bit support
8391   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
8392   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
8393   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
8394   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
8395   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
8396   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
8397   // AVX512 support
8398   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
8399   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
8400   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
8401   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
8402   { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
8403   { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
8404   { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
8405   { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
8406   { X86::VBROADCASTSSZr,    X86::VBROADCASTSSZr,    X86::VPBROADCASTDZr },
8407   { X86::VBROADCASTSSZm,    X86::VBROADCASTSSZm,    X86::VPBROADCASTDZm },
8408   { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
8409   { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
8410   { X86::VBROADCASTSDZr,    X86::VBROADCASTSDZr,    X86::VPBROADCASTQZr },
8411   { X86::VBROADCASTSDZm,    X86::VBROADCASTSDZm,    X86::VPBROADCASTQZm },
8412 };
8413 
8414 static const uint16_t ReplaceableInstrsAVX2[][3] = {
8415   //PackedSingle       PackedDouble       PackedInt
8416   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
8417   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
8418   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
8419   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
8420   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
8421   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
8422   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
8423   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
8424   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
8425   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
8426   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
8427   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
8428   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
8429   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
8430   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
8431   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
8432   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
8433   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
8434   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
8435   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
8436   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
8437 };
8438 
8439 static const uint16_t ReplaceableInstrsAVX512[][4] = {
8440   // Two integer columns for 64-bit and 32-bit elements.
8441   //PackedSingle        PackedDouble        PackedInt             PackedInt
8442   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
8443   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
8444   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
8445   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
8446   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
8447   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
8448   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
8449   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
8450   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
8451   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
8452   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
8453   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
8454   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
8455   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
8456   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
8457 };
8458 
8459 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
8460   // Two integer columns for 64-bit and 32-bit elements.
8461   //PackedSingle        PackedDouble        PackedInt           PackedInt
8462   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
8463   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
8464   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
8465   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
8466   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
8467   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
8468   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
8469   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
8470   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
8471   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
8472   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
8473   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
8474   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
8475   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
8476   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
8477   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
8478   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
8479   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
8480   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
8481   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
8482   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
8483   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
8484   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
8485   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
8486 };
8487 
8488 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
8489   // Two integer columns for 64-bit and 32-bit elements.
8490   //PackedSingle          PackedDouble
8491   //PackedInt             PackedInt
8492   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
8493     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
8494   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
8495     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
8496   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
8497     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
8498   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
8499     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
8500   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
8501     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
8502   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
8503     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
8504   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
8505     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
8506   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
8507     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
8508   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
8509     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
8510   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
8511     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
8512   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
8513     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
8514   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
8515     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
8516   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
8517     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
8518   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
8519     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
8520   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
8521     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
8522   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
8523     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
8524   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
8525     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
8526   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
8527     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
8528   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
8529     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
8530   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
8531     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
8532   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
8533     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
8534   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
8535     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
8536   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
8537     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
8538   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
8539     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
8540   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
8541     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
8542   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
8543     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
8544   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
8545     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
8546   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
8547     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
8548   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
8549     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
8550   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
8551     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
8552   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
8553     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
8554   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
8555     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
8556   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
8557     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
8558   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
8559     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
8560   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
8561     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
8562   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
8563     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
8564   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
8565     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
8566   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
8567     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
8568   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
8569     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
8570   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
8571     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
8572   { X86::VORPSZrmk,       X86::VORPDZrmk,
8573     X86::VPORQZrmk,       X86::VPORDZrmk       },
8574   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
8575     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
8576   { X86::VORPSZrrk,       X86::VORPDZrrk,
8577     X86::VPORQZrrk,       X86::VPORDZrrk       },
8578   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
8579     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
8580   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
8581     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
8582   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
8583     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
8584   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
8585     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
8586   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
8587     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
8588   // Broadcast loads can be handled the same as masked operations to avoid
8589   // changing element size.
8590   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
8591     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
8592   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
8593     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
8594   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
8595     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
8596   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
8597     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
8598   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
8599     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
8600   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
8601     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
8602   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
8603     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
8604   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
8605     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
8606   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
8607     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
8608   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
8609     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
8610   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
8611     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
8612   { X86::VORPSZrmb,       X86::VORPDZrmb,
8613     X86::VPORQZrmb,       X86::VPORDZrmb       },
8614   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
8615     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
8616   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
8617     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
8618   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
8619     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
8620   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
8621     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
8622   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
8623     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
8624   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
8625     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
8626   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
8627     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
8628   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
8629     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
8630   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
8631     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
8632   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
8633     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
8634   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
8635     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
8636   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
8637     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
8638   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
8639     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
8640   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
8641     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
8642   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
8643     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
8644   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
8645     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
8646   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
8647     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
8648   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
8649     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
8650   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
8651     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
8652   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
8653     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
8654   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
8655     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
8656   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
8657     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
8658   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
8659     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
8660   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
8661     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
8662   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
8663     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
8664   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
8665     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
8666   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
8667     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
8668 };
8669 
8670 // FIXME: Some shuffle and unpack instructions have equivalents in different
8671 // domains, but they require a bit more work than just switching opcodes.
8672 
8673 static const uint16_t *lookup(unsigned opcode, unsigned domain,
8674                               ArrayRef<uint16_t[3]> Table) {
8675   for (const uint16_t (&Row)[3] : Table)
8676     if (Row[domain-1] == opcode)
8677       return Row;
8678   return nullptr;
8679 }
8680 
8681 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
8682                                     ArrayRef<uint16_t[4]> Table) {
8683   // If this is the integer domain make sure to check both integer columns.
8684   for (const uint16_t (&Row)[4] : Table)
8685     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
8686       return Row;
8687   return nullptr;
8688 }
8689 
8690 std::pair<uint16_t, uint16_t>
8691 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
8692   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
8693   unsigned opcode = MI.getOpcode();
8694   uint16_t validDomains = 0;
8695   if (domain) {
8696     if (lookup(MI.getOpcode(), domain, ReplaceableInstrs)) {
8697       validDomains = 0xe;
8698     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
8699       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
8700     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
8701       validDomains = 0xe;
8702     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512DQ)) {
8703       validDomains = Subtarget.hasDQI() ? 0xe : 0x8;
8704     } else if (const uint16_t *table = lookupAVX512(opcode, domain,
8705                                              ReplaceableInstrsAVX512DQMasked)) {
8706       if (domain == 1 || (domain == 3 && table[3] == opcode))
8707         validDomains = Subtarget.hasDQI() ? 0xa : 0x8;
8708       else
8709         validDomains = Subtarget.hasDQI() ? 0xc : 0x8;
8710     }
8711   }
8712   return std::make_pair(domain, validDomains);
8713 }
8714 
8715 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
8716   assert(Domain>0 && Domain<4 && "Invalid execution domain");
8717   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
8718   assert(dom && "Not an SSE instruction");
8719   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
8720   if (!table) { // try the other table
8721     assert((Subtarget.hasAVX2() || Domain < 3) &&
8722            "256-bit vector operations only available in AVX2");
8723     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
8724   }
8725   if (!table) { // try the AVX512 table
8726     assert(Subtarget.hasAVX512() && "Requires AVX-512");
8727     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
8728     // Don't change integer Q instructions to D instructions.
8729     if (table && Domain == 3 && table[3] == MI.getOpcode())
8730       Domain = 4;
8731   }
8732   if (!table) { // try the AVX512DQ table
8733     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
8734     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
8735     // Don't change integer Q instructions to D instructions and
8736     // use D intructions if we started with a PS instruction.
8737     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
8738       Domain = 4;
8739   }
8740   if (!table) { // try the AVX512DQMasked table
8741     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
8742     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
8743     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
8744       Domain = 4;
8745   }
8746   assert(table && "Cannot change domain");
8747   MI.setDesc(get(table[Domain - 1]));
8748 }
8749 
8750 /// Return the noop instruction to use for a noop.
8751 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
8752   NopInst.setOpcode(X86::NOOP);
8753 }
8754 
8755 bool X86InstrInfo::isHighLatencyDef(int opc) const {
8756   switch (opc) {
8757   default: return false;
8758   case X86::DIVPDrm:
8759   case X86::DIVPDrr:
8760   case X86::DIVPSrm:
8761   case X86::DIVPSrr:
8762   case X86::DIVSDrm:
8763   case X86::DIVSDrm_Int:
8764   case X86::DIVSDrr:
8765   case X86::DIVSDrr_Int:
8766   case X86::DIVSSrm:
8767   case X86::DIVSSrm_Int:
8768   case X86::DIVSSrr:
8769   case X86::DIVSSrr_Int:
8770   case X86::SQRTPDm:
8771   case X86::SQRTPDr:
8772   case X86::SQRTPSm:
8773   case X86::SQRTPSr:
8774   case X86::SQRTSDm:
8775   case X86::SQRTSDm_Int:
8776   case X86::SQRTSDr:
8777   case X86::SQRTSDr_Int:
8778   case X86::SQRTSSm:
8779   case X86::SQRTSSm_Int:
8780   case X86::SQRTSSr:
8781   case X86::SQRTSSr_Int:
8782   // AVX instructions with high latency
8783   case X86::VDIVPDrm:
8784   case X86::VDIVPDrr:
8785   case X86::VDIVPDYrm:
8786   case X86::VDIVPDYrr:
8787   case X86::VDIVPSrm:
8788   case X86::VDIVPSrr:
8789   case X86::VDIVPSYrm:
8790   case X86::VDIVPSYrr:
8791   case X86::VDIVSDrm:
8792   case X86::VDIVSDrm_Int:
8793   case X86::VDIVSDrr:
8794   case X86::VDIVSDrr_Int:
8795   case X86::VDIVSSrm:
8796   case X86::VDIVSSrm_Int:
8797   case X86::VDIVSSrr:
8798   case X86::VDIVSSrr_Int:
8799   case X86::VSQRTPDm:
8800   case X86::VSQRTPDr:
8801   case X86::VSQRTPDYm:
8802   case X86::VSQRTPDYr:
8803   case X86::VSQRTPSm:
8804   case X86::VSQRTPSr:
8805   case X86::VSQRTPSYm:
8806   case X86::VSQRTPSYr:
8807   case X86::VSQRTSDm:
8808   case X86::VSQRTSDm_Int:
8809   case X86::VSQRTSDr:
8810   case X86::VSQRTSDr_Int:
8811   case X86::VSQRTSSm:
8812   case X86::VSQRTSSm_Int:
8813   case X86::VSQRTSSr:
8814   case X86::VSQRTSSr_Int:
8815   // AVX512 instructions with high latency
8816   case X86::VDIVPDZ128rm:
8817   case X86::VDIVPDZ128rmb:
8818   case X86::VDIVPDZ128rmbk:
8819   case X86::VDIVPDZ128rmbkz:
8820   case X86::VDIVPDZ128rmk:
8821   case X86::VDIVPDZ128rmkz:
8822   case X86::VDIVPDZ128rr:
8823   case X86::VDIVPDZ128rrk:
8824   case X86::VDIVPDZ128rrkz:
8825   case X86::VDIVPDZ256rm:
8826   case X86::VDIVPDZ256rmb:
8827   case X86::VDIVPDZ256rmbk:
8828   case X86::VDIVPDZ256rmbkz:
8829   case X86::VDIVPDZ256rmk:
8830   case X86::VDIVPDZ256rmkz:
8831   case X86::VDIVPDZ256rr:
8832   case X86::VDIVPDZ256rrk:
8833   case X86::VDIVPDZ256rrkz:
8834   case X86::VDIVPDZrb:
8835   case X86::VDIVPDZrbk:
8836   case X86::VDIVPDZrbkz:
8837   case X86::VDIVPDZrm:
8838   case X86::VDIVPDZrmb:
8839   case X86::VDIVPDZrmbk:
8840   case X86::VDIVPDZrmbkz:
8841   case X86::VDIVPDZrmk:
8842   case X86::VDIVPDZrmkz:
8843   case X86::VDIVPDZrr:
8844   case X86::VDIVPDZrrk:
8845   case X86::VDIVPDZrrkz:
8846   case X86::VDIVPSZ128rm:
8847   case X86::VDIVPSZ128rmb:
8848   case X86::VDIVPSZ128rmbk:
8849   case X86::VDIVPSZ128rmbkz:
8850   case X86::VDIVPSZ128rmk:
8851   case X86::VDIVPSZ128rmkz:
8852   case X86::VDIVPSZ128rr:
8853   case X86::VDIVPSZ128rrk:
8854   case X86::VDIVPSZ128rrkz:
8855   case X86::VDIVPSZ256rm:
8856   case X86::VDIVPSZ256rmb:
8857   case X86::VDIVPSZ256rmbk:
8858   case X86::VDIVPSZ256rmbkz:
8859   case X86::VDIVPSZ256rmk:
8860   case X86::VDIVPSZ256rmkz:
8861   case X86::VDIVPSZ256rr:
8862   case X86::VDIVPSZ256rrk:
8863   case X86::VDIVPSZ256rrkz:
8864   case X86::VDIVPSZrb:
8865   case X86::VDIVPSZrbk:
8866   case X86::VDIVPSZrbkz:
8867   case X86::VDIVPSZrm:
8868   case X86::VDIVPSZrmb:
8869   case X86::VDIVPSZrmbk:
8870   case X86::VDIVPSZrmbkz:
8871   case X86::VDIVPSZrmk:
8872   case X86::VDIVPSZrmkz:
8873   case X86::VDIVPSZrr:
8874   case X86::VDIVPSZrrk:
8875   case X86::VDIVPSZrrkz:
8876   case X86::VDIVSDZrm:
8877   case X86::VDIVSDZrr:
8878   case X86::VDIVSDZrm_Int:
8879   case X86::VDIVSDZrm_Intk:
8880   case X86::VDIVSDZrm_Intkz:
8881   case X86::VDIVSDZrr_Int:
8882   case X86::VDIVSDZrr_Intk:
8883   case X86::VDIVSDZrr_Intkz:
8884   case X86::VDIVSDZrrb:
8885   case X86::VDIVSDZrrbk:
8886   case X86::VDIVSDZrrbkz:
8887   case X86::VDIVSSZrm:
8888   case X86::VDIVSSZrr:
8889   case X86::VDIVSSZrm_Int:
8890   case X86::VDIVSSZrm_Intk:
8891   case X86::VDIVSSZrm_Intkz:
8892   case X86::VDIVSSZrr_Int:
8893   case X86::VDIVSSZrr_Intk:
8894   case X86::VDIVSSZrr_Intkz:
8895   case X86::VDIVSSZrrb:
8896   case X86::VDIVSSZrrbk:
8897   case X86::VDIVSSZrrbkz:
8898   case X86::VSQRTPDZ128m:
8899   case X86::VSQRTPDZ128mb:
8900   case X86::VSQRTPDZ128mbk:
8901   case X86::VSQRTPDZ128mbkz:
8902   case X86::VSQRTPDZ128mk:
8903   case X86::VSQRTPDZ128mkz:
8904   case X86::VSQRTPDZ128r:
8905   case X86::VSQRTPDZ128rk:
8906   case X86::VSQRTPDZ128rkz:
8907   case X86::VSQRTPDZ256m:
8908   case X86::VSQRTPDZ256mb:
8909   case X86::VSQRTPDZ256mbk:
8910   case X86::VSQRTPDZ256mbkz:
8911   case X86::VSQRTPDZ256mk:
8912   case X86::VSQRTPDZ256mkz:
8913   case X86::VSQRTPDZ256r:
8914   case X86::VSQRTPDZ256rk:
8915   case X86::VSQRTPDZ256rkz:
8916   case X86::VSQRTPDZm:
8917   case X86::VSQRTPDZmb:
8918   case X86::VSQRTPDZmbk:
8919   case X86::VSQRTPDZmbkz:
8920   case X86::VSQRTPDZmk:
8921   case X86::VSQRTPDZmkz:
8922   case X86::VSQRTPDZr:
8923   case X86::VSQRTPDZrb:
8924   case X86::VSQRTPDZrbk:
8925   case X86::VSQRTPDZrbkz:
8926   case X86::VSQRTPDZrk:
8927   case X86::VSQRTPDZrkz:
8928   case X86::VSQRTPSZ128m:
8929   case X86::VSQRTPSZ128mb:
8930   case X86::VSQRTPSZ128mbk:
8931   case X86::VSQRTPSZ128mbkz:
8932   case X86::VSQRTPSZ128mk:
8933   case X86::VSQRTPSZ128mkz:
8934   case X86::VSQRTPSZ128r:
8935   case X86::VSQRTPSZ128rk:
8936   case X86::VSQRTPSZ128rkz:
8937   case X86::VSQRTPSZ256m:
8938   case X86::VSQRTPSZ256mb:
8939   case X86::VSQRTPSZ256mbk:
8940   case X86::VSQRTPSZ256mbkz:
8941   case X86::VSQRTPSZ256mk:
8942   case X86::VSQRTPSZ256mkz:
8943   case X86::VSQRTPSZ256r:
8944   case X86::VSQRTPSZ256rk:
8945   case X86::VSQRTPSZ256rkz:
8946   case X86::VSQRTPSZm:
8947   case X86::VSQRTPSZmb:
8948   case X86::VSQRTPSZmbk:
8949   case X86::VSQRTPSZmbkz:
8950   case X86::VSQRTPSZmk:
8951   case X86::VSQRTPSZmkz:
8952   case X86::VSQRTPSZr:
8953   case X86::VSQRTPSZrb:
8954   case X86::VSQRTPSZrbk:
8955   case X86::VSQRTPSZrbkz:
8956   case X86::VSQRTPSZrk:
8957   case X86::VSQRTPSZrkz:
8958   case X86::VSQRTSDZm:
8959   case X86::VSQRTSDZm_Int:
8960   case X86::VSQRTSDZm_Intk:
8961   case X86::VSQRTSDZm_Intkz:
8962   case X86::VSQRTSDZr:
8963   case X86::VSQRTSDZr_Int:
8964   case X86::VSQRTSDZr_Intk:
8965   case X86::VSQRTSDZr_Intkz:
8966   case X86::VSQRTSDZrb_Int:
8967   case X86::VSQRTSDZrb_Intk:
8968   case X86::VSQRTSDZrb_Intkz:
8969   case X86::VSQRTSSZm:
8970   case X86::VSQRTSSZm_Int:
8971   case X86::VSQRTSSZm_Intk:
8972   case X86::VSQRTSSZm_Intkz:
8973   case X86::VSQRTSSZr:
8974   case X86::VSQRTSSZr_Int:
8975   case X86::VSQRTSSZr_Intk:
8976   case X86::VSQRTSSZr_Intkz:
8977   case X86::VSQRTSSZrb_Int:
8978   case X86::VSQRTSSZrb_Intk:
8979   case X86::VSQRTSSZrb_Intkz:
8980 
8981   case X86::VGATHERDPDYrm:
8982   case X86::VGATHERDPDZ128rm:
8983   case X86::VGATHERDPDZ256rm:
8984   case X86::VGATHERDPDZrm:
8985   case X86::VGATHERDPDrm:
8986   case X86::VGATHERDPSYrm:
8987   case X86::VGATHERDPSZ128rm:
8988   case X86::VGATHERDPSZ256rm:
8989   case X86::VGATHERDPSZrm:
8990   case X86::VGATHERDPSrm:
8991   case X86::VGATHERPF0DPDm:
8992   case X86::VGATHERPF0DPSm:
8993   case X86::VGATHERPF0QPDm:
8994   case X86::VGATHERPF0QPSm:
8995   case X86::VGATHERPF1DPDm:
8996   case X86::VGATHERPF1DPSm:
8997   case X86::VGATHERPF1QPDm:
8998   case X86::VGATHERPF1QPSm:
8999   case X86::VGATHERQPDYrm:
9000   case X86::VGATHERQPDZ128rm:
9001   case X86::VGATHERQPDZ256rm:
9002   case X86::VGATHERQPDZrm:
9003   case X86::VGATHERQPDrm:
9004   case X86::VGATHERQPSYrm:
9005   case X86::VGATHERQPSZ128rm:
9006   case X86::VGATHERQPSZ256rm:
9007   case X86::VGATHERQPSZrm:
9008   case X86::VGATHERQPSrm:
9009   case X86::VPGATHERDDYrm:
9010   case X86::VPGATHERDDZ128rm:
9011   case X86::VPGATHERDDZ256rm:
9012   case X86::VPGATHERDDZrm:
9013   case X86::VPGATHERDDrm:
9014   case X86::VPGATHERDQYrm:
9015   case X86::VPGATHERDQZ128rm:
9016   case X86::VPGATHERDQZ256rm:
9017   case X86::VPGATHERDQZrm:
9018   case X86::VPGATHERDQrm:
9019   case X86::VPGATHERQDYrm:
9020   case X86::VPGATHERQDZ128rm:
9021   case X86::VPGATHERQDZ256rm:
9022   case X86::VPGATHERQDZrm:
9023   case X86::VPGATHERQDrm:
9024   case X86::VPGATHERQQYrm:
9025   case X86::VPGATHERQQZ128rm:
9026   case X86::VPGATHERQQZ256rm:
9027   case X86::VPGATHERQQZrm:
9028   case X86::VPGATHERQQrm:
9029   case X86::VSCATTERDPDZ128mr:
9030   case X86::VSCATTERDPDZ256mr:
9031   case X86::VSCATTERDPDZmr:
9032   case X86::VSCATTERDPSZ128mr:
9033   case X86::VSCATTERDPSZ256mr:
9034   case X86::VSCATTERDPSZmr:
9035   case X86::VSCATTERPF0DPDm:
9036   case X86::VSCATTERPF0DPSm:
9037   case X86::VSCATTERPF0QPDm:
9038   case X86::VSCATTERPF0QPSm:
9039   case X86::VSCATTERPF1DPDm:
9040   case X86::VSCATTERPF1DPSm:
9041   case X86::VSCATTERPF1QPDm:
9042   case X86::VSCATTERPF1QPSm:
9043   case X86::VSCATTERQPDZ128mr:
9044   case X86::VSCATTERQPDZ256mr:
9045   case X86::VSCATTERQPDZmr:
9046   case X86::VSCATTERQPSZ128mr:
9047   case X86::VSCATTERQPSZ256mr:
9048   case X86::VSCATTERQPSZmr:
9049   case X86::VPSCATTERDDZ128mr:
9050   case X86::VPSCATTERDDZ256mr:
9051   case X86::VPSCATTERDDZmr:
9052   case X86::VPSCATTERDQZ128mr:
9053   case X86::VPSCATTERDQZ256mr:
9054   case X86::VPSCATTERDQZmr:
9055   case X86::VPSCATTERQDZ128mr:
9056   case X86::VPSCATTERQDZ256mr:
9057   case X86::VPSCATTERQDZmr:
9058   case X86::VPSCATTERQQZ128mr:
9059   case X86::VPSCATTERQQZ256mr:
9060   case X86::VPSCATTERQQZmr:
9061     return true;
9062   }
9063 }
9064 
9065 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
9066                                          const MachineRegisterInfo *MRI,
9067                                          const MachineInstr &DefMI,
9068                                          unsigned DefIdx,
9069                                          const MachineInstr &UseMI,
9070                                          unsigned UseIdx) const {
9071   return isHighLatencyDef(DefMI.getOpcode());
9072 }
9073 
9074 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
9075                                            const MachineBasicBlock *MBB) const {
9076   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
9077          "Reassociation needs binary operators");
9078 
9079   // Integer binary math/logic instructions have a third source operand:
9080   // the EFLAGS register. That operand must be both defined here and never
9081   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
9082   // not change anything because rearranging the operands could affect other
9083   // instructions that depend on the exact status flags (zero, sign, etc.)
9084   // that are set by using these particular operands with this operation.
9085   if (Inst.getNumOperands() == 4) {
9086     assert(Inst.getOperand(3).isReg() &&
9087            Inst.getOperand(3).getReg() == X86::EFLAGS &&
9088            "Unexpected operand in reassociable instruction");
9089     if (!Inst.getOperand(3).isDead())
9090       return false;
9091   }
9092 
9093   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
9094 }
9095 
9096 // TODO: There are many more machine instruction opcodes to match:
9097 //       1. Other data types (integer, vectors)
9098 //       2. Other math / logic operations (xor, or)
9099 //       3. Other forms of the same operation (intrinsics and other variants)
9100 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
9101   switch (Inst.getOpcode()) {
9102   case X86::AND8rr:
9103   case X86::AND16rr:
9104   case X86::AND32rr:
9105   case X86::AND64rr:
9106   case X86::OR8rr:
9107   case X86::OR16rr:
9108   case X86::OR32rr:
9109   case X86::OR64rr:
9110   case X86::XOR8rr:
9111   case X86::XOR16rr:
9112   case X86::XOR32rr:
9113   case X86::XOR64rr:
9114   case X86::IMUL16rr:
9115   case X86::IMUL32rr:
9116   case X86::IMUL64rr:
9117   case X86::PANDrr:
9118   case X86::PORrr:
9119   case X86::PXORrr:
9120   case X86::ANDPDrr:
9121   case X86::ANDPSrr:
9122   case X86::ORPDrr:
9123   case X86::ORPSrr:
9124   case X86::XORPDrr:
9125   case X86::XORPSrr:
9126   case X86::PADDBrr:
9127   case X86::PADDWrr:
9128   case X86::PADDDrr:
9129   case X86::PADDQrr:
9130   case X86::VPANDrr:
9131   case X86::VPANDYrr:
9132   case X86::VPANDDZ128rr:
9133   case X86::VPANDDZ256rr:
9134   case X86::VPANDDZrr:
9135   case X86::VPANDQZ128rr:
9136   case X86::VPANDQZ256rr:
9137   case X86::VPANDQZrr:
9138   case X86::VPORrr:
9139   case X86::VPORYrr:
9140   case X86::VPORDZ128rr:
9141   case X86::VPORDZ256rr:
9142   case X86::VPORDZrr:
9143   case X86::VPORQZ128rr:
9144   case X86::VPORQZ256rr:
9145   case X86::VPORQZrr:
9146   case X86::VPXORrr:
9147   case X86::VPXORYrr:
9148   case X86::VPXORDZ128rr:
9149   case X86::VPXORDZ256rr:
9150   case X86::VPXORDZrr:
9151   case X86::VPXORQZ128rr:
9152   case X86::VPXORQZ256rr:
9153   case X86::VPXORQZrr:
9154   case X86::VANDPDrr:
9155   case X86::VANDPSrr:
9156   case X86::VANDPDYrr:
9157   case X86::VANDPSYrr:
9158   case X86::VANDPDZ128rr:
9159   case X86::VANDPSZ128rr:
9160   case X86::VANDPDZ256rr:
9161   case X86::VANDPSZ256rr:
9162   case X86::VANDPDZrr:
9163   case X86::VANDPSZrr:
9164   case X86::VORPDrr:
9165   case X86::VORPSrr:
9166   case X86::VORPDYrr:
9167   case X86::VORPSYrr:
9168   case X86::VORPDZ128rr:
9169   case X86::VORPSZ128rr:
9170   case X86::VORPDZ256rr:
9171   case X86::VORPSZ256rr:
9172   case X86::VORPDZrr:
9173   case X86::VORPSZrr:
9174   case X86::VXORPDrr:
9175   case X86::VXORPSrr:
9176   case X86::VXORPDYrr:
9177   case X86::VXORPSYrr:
9178   case X86::VXORPDZ128rr:
9179   case X86::VXORPSZ128rr:
9180   case X86::VXORPDZ256rr:
9181   case X86::VXORPSZ256rr:
9182   case X86::VXORPDZrr:
9183   case X86::VXORPSZrr:
9184   case X86::KADDBrr:
9185   case X86::KADDWrr:
9186   case X86::KADDDrr:
9187   case X86::KADDQrr:
9188   case X86::KANDBrr:
9189   case X86::KANDWrr:
9190   case X86::KANDDrr:
9191   case X86::KANDQrr:
9192   case X86::KORBrr:
9193   case X86::KORWrr:
9194   case X86::KORDrr:
9195   case X86::KORQrr:
9196   case X86::KXORBrr:
9197   case X86::KXORWrr:
9198   case X86::KXORDrr:
9199   case X86::KXORQrr:
9200   case X86::VPADDBrr:
9201   case X86::VPADDWrr:
9202   case X86::VPADDDrr:
9203   case X86::VPADDQrr:
9204   case X86::VPADDBYrr:
9205   case X86::VPADDWYrr:
9206   case X86::VPADDDYrr:
9207   case X86::VPADDQYrr:
9208   case X86::VPADDBZ128rr:
9209   case X86::VPADDWZ128rr:
9210   case X86::VPADDDZ128rr:
9211   case X86::VPADDQZ128rr:
9212   case X86::VPADDBZ256rr:
9213   case X86::VPADDWZ256rr:
9214   case X86::VPADDDZ256rr:
9215   case X86::VPADDQZ256rr:
9216   case X86::VPADDBZrr:
9217   case X86::VPADDWZrr:
9218   case X86::VPADDDZrr:
9219   case X86::VPADDQZrr:
9220   case X86::VPMULLWrr:
9221   case X86::VPMULLWYrr:
9222   case X86::VPMULLWZ128rr:
9223   case X86::VPMULLWZ256rr:
9224   case X86::VPMULLWZrr:
9225   case X86::VPMULLDrr:
9226   case X86::VPMULLDYrr:
9227   case X86::VPMULLDZ128rr:
9228   case X86::VPMULLDZ256rr:
9229   case X86::VPMULLDZrr:
9230   case X86::VPMULLQZ128rr:
9231   case X86::VPMULLQZ256rr:
9232   case X86::VPMULLQZrr:
9233   // Normal min/max instructions are not commutative because of NaN and signed
9234   // zero semantics, but these are. Thus, there's no need to check for global
9235   // relaxed math; the instructions themselves have the properties we need.
9236   case X86::MAXCPDrr:
9237   case X86::MAXCPSrr:
9238   case X86::MAXCSDrr:
9239   case X86::MAXCSSrr:
9240   case X86::MINCPDrr:
9241   case X86::MINCPSrr:
9242   case X86::MINCSDrr:
9243   case X86::MINCSSrr:
9244   case X86::VMAXCPDrr:
9245   case X86::VMAXCPSrr:
9246   case X86::VMAXCPDYrr:
9247   case X86::VMAXCPSYrr:
9248   case X86::VMAXCPDZ128rr:
9249   case X86::VMAXCPSZ128rr:
9250   case X86::VMAXCPDZ256rr:
9251   case X86::VMAXCPSZ256rr:
9252   case X86::VMAXCPDZrr:
9253   case X86::VMAXCPSZrr:
9254   case X86::VMAXCSDrr:
9255   case X86::VMAXCSSrr:
9256   case X86::VMAXCSDZrr:
9257   case X86::VMAXCSSZrr:
9258   case X86::VMINCPDrr:
9259   case X86::VMINCPSrr:
9260   case X86::VMINCPDYrr:
9261   case X86::VMINCPSYrr:
9262   case X86::VMINCPDZ128rr:
9263   case X86::VMINCPSZ128rr:
9264   case X86::VMINCPDZ256rr:
9265   case X86::VMINCPSZ256rr:
9266   case X86::VMINCPDZrr:
9267   case X86::VMINCPSZrr:
9268   case X86::VMINCSDrr:
9269   case X86::VMINCSSrr:
9270   case X86::VMINCSDZrr:
9271   case X86::VMINCSSZrr:
9272     return true;
9273   case X86::ADDPDrr:
9274   case X86::ADDPSrr:
9275   case X86::ADDSDrr:
9276   case X86::ADDSSrr:
9277   case X86::MULPDrr:
9278   case X86::MULPSrr:
9279   case X86::MULSDrr:
9280   case X86::MULSSrr:
9281   case X86::VADDPDrr:
9282   case X86::VADDPSrr:
9283   case X86::VADDPDYrr:
9284   case X86::VADDPSYrr:
9285   case X86::VADDPDZ128rr:
9286   case X86::VADDPSZ128rr:
9287   case X86::VADDPDZ256rr:
9288   case X86::VADDPSZ256rr:
9289   case X86::VADDPDZrr:
9290   case X86::VADDPSZrr:
9291   case X86::VADDSDrr:
9292   case X86::VADDSSrr:
9293   case X86::VADDSDZrr:
9294   case X86::VADDSSZrr:
9295   case X86::VMULPDrr:
9296   case X86::VMULPSrr:
9297   case X86::VMULPDYrr:
9298   case X86::VMULPSYrr:
9299   case X86::VMULPDZ128rr:
9300   case X86::VMULPSZ128rr:
9301   case X86::VMULPDZ256rr:
9302   case X86::VMULPSZ256rr:
9303   case X86::VMULPDZrr:
9304   case X86::VMULPSZrr:
9305   case X86::VMULSDrr:
9306   case X86::VMULSSrr:
9307   case X86::VMULSDZrr:
9308   case X86::VMULSSZrr:
9309     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
9310   default:
9311     return false;
9312   }
9313 }
9314 
9315 /// This is an architecture-specific helper function of reassociateOps.
9316 /// Set special operand attributes for new instructions after reassociation.
9317 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
9318                                          MachineInstr &OldMI2,
9319                                          MachineInstr &NewMI1,
9320                                          MachineInstr &NewMI2) const {
9321   // Integer instructions define an implicit EFLAGS source register operand as
9322   // the third source (fourth total) operand.
9323   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
9324     return;
9325 
9326   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
9327          "Unexpected instruction type for reassociation");
9328 
9329   MachineOperand &OldOp1 = OldMI1.getOperand(3);
9330   MachineOperand &OldOp2 = OldMI2.getOperand(3);
9331   MachineOperand &NewOp1 = NewMI1.getOperand(3);
9332   MachineOperand &NewOp2 = NewMI2.getOperand(3);
9333 
9334   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
9335          "Must have dead EFLAGS operand in reassociable instruction");
9336   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
9337          "Must have dead EFLAGS operand in reassociable instruction");
9338 
9339   (void)OldOp1;
9340   (void)OldOp2;
9341 
9342   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
9343          "Unexpected operand in reassociable instruction");
9344   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
9345          "Unexpected operand in reassociable instruction");
9346 
9347   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
9348   // of this pass or other passes. The EFLAGS operands must be dead in these new
9349   // instructions because the EFLAGS operands in the original instructions must
9350   // be dead in order for reassociation to occur.
9351   NewOp1.setIsDead();
9352   NewOp2.setIsDead();
9353 }
9354 
9355 std::pair<unsigned, unsigned>
9356 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
9357   return std::make_pair(TF, 0u);
9358 }
9359 
9360 ArrayRef<std::pair<unsigned, const char *>>
9361 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
9362   using namespace X86II;
9363   static const std::pair<unsigned, const char *> TargetFlags[] = {
9364       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
9365       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
9366       {MO_GOT, "x86-got"},
9367       {MO_GOTOFF, "x86-gotoff"},
9368       {MO_GOTPCREL, "x86-gotpcrel"},
9369       {MO_PLT, "x86-plt"},
9370       {MO_TLSGD, "x86-tlsgd"},
9371       {MO_TLSLD, "x86-tlsld"},
9372       {MO_TLSLDM, "x86-tlsldm"},
9373       {MO_GOTTPOFF, "x86-gottpoff"},
9374       {MO_INDNTPOFF, "x86-indntpoff"},
9375       {MO_TPOFF, "x86-tpoff"},
9376       {MO_DTPOFF, "x86-dtpoff"},
9377       {MO_NTPOFF, "x86-ntpoff"},
9378       {MO_GOTNTPOFF, "x86-gotntpoff"},
9379       {MO_DLLIMPORT, "x86-dllimport"},
9380       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
9381       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
9382       {MO_TLVP, "x86-tlvp"},
9383       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
9384       {MO_SECREL, "x86-secrel"}};
9385   return makeArrayRef(TargetFlags);
9386 }
9387 
9388 bool X86InstrInfo::isTailCall(const MachineInstr &Inst) const {
9389   switch (Inst.getOpcode()) {
9390     case X86::TCRETURNdi:
9391     case X86::TCRETURNmi:
9392     case X86::TCRETURNri:
9393     case X86::TCRETURNdi64:
9394     case X86::TCRETURNmi64:
9395     case X86::TCRETURNri64:
9396     case X86::TAILJMPd:
9397     case X86::TAILJMPm:
9398     case X86::TAILJMPr:
9399     case X86::TAILJMPd64:
9400     case X86::TAILJMPm64:
9401     case X86::TAILJMPr64:
9402     case X86::TAILJMPm64_REX:
9403     case X86::TAILJMPr64_REX:
9404       return true;
9405     default:
9406       return false;
9407   }
9408 }
9409 
9410 namespace {
9411   /// Create Global Base Reg pass. This initializes the PIC
9412   /// global base register for x86-32.
9413   struct CGBR : public MachineFunctionPass {
9414     static char ID;
9415     CGBR() : MachineFunctionPass(ID) {}
9416 
9417     bool runOnMachineFunction(MachineFunction &MF) override {
9418       const X86TargetMachine *TM =
9419         static_cast<const X86TargetMachine *>(&MF.getTarget());
9420       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
9421 
9422       // Don't do anything if this is 64-bit as 64-bit PIC
9423       // uses RIP relative addressing.
9424       if (STI.is64Bit())
9425         return false;
9426 
9427       // Only emit a global base reg in PIC mode.
9428       if (!TM->isPositionIndependent())
9429         return false;
9430 
9431       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
9432       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
9433 
9434       // If we didn't need a GlobalBaseReg, don't insert code.
9435       if (GlobalBaseReg == 0)
9436         return false;
9437 
9438       // Insert the set of GlobalBaseReg into the first MBB of the function
9439       MachineBasicBlock &FirstMBB = MF.front();
9440       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
9441       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
9442       MachineRegisterInfo &RegInfo = MF.getRegInfo();
9443       const X86InstrInfo *TII = STI.getInstrInfo();
9444 
9445       unsigned PC;
9446       if (STI.isPICStyleGOT())
9447         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
9448       else
9449         PC = GlobalBaseReg;
9450 
9451       // Operand of MovePCtoStack is completely ignored by asm printer. It's
9452       // only used in JIT code emission as displacement to pc.
9453       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
9454 
9455       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
9456       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
9457       if (STI.isPICStyleGOT()) {
9458         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
9459         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
9460           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
9461                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
9462       }
9463 
9464       return true;
9465     }
9466 
9467     StringRef getPassName() const override {
9468       return "X86 PIC Global Base Reg Initialization";
9469     }
9470 
9471     void getAnalysisUsage(AnalysisUsage &AU) const override {
9472       AU.setPreservesCFG();
9473       MachineFunctionPass::getAnalysisUsage(AU);
9474     }
9475   };
9476 }
9477 
9478 char CGBR::ID = 0;
9479 FunctionPass*
9480 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
9481 
9482 namespace {
9483   struct LDTLSCleanup : public MachineFunctionPass {
9484     static char ID;
9485     LDTLSCleanup() : MachineFunctionPass(ID) {}
9486 
9487     bool runOnMachineFunction(MachineFunction &MF) override {
9488       if (skipFunction(*MF.getFunction()))
9489         return false;
9490 
9491       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
9492       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
9493         // No point folding accesses if there isn't at least two.
9494         return false;
9495       }
9496 
9497       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
9498       return VisitNode(DT->getRootNode(), 0);
9499     }
9500 
9501     // Visit the dominator subtree rooted at Node in pre-order.
9502     // If TLSBaseAddrReg is non-null, then use that to replace any
9503     // TLS_base_addr instructions. Otherwise, create the register
9504     // when the first such instruction is seen, and then use it
9505     // as we encounter more instructions.
9506     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
9507       MachineBasicBlock *BB = Node->getBlock();
9508       bool Changed = false;
9509 
9510       // Traverse the current block.
9511       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
9512            ++I) {
9513         switch (I->getOpcode()) {
9514           case X86::TLS_base_addr32:
9515           case X86::TLS_base_addr64:
9516             if (TLSBaseAddrReg)
9517               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
9518             else
9519               I = SetRegister(*I, &TLSBaseAddrReg);
9520             Changed = true;
9521             break;
9522           default:
9523             break;
9524         }
9525       }
9526 
9527       // Visit the children of this block in the dominator tree.
9528       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
9529            I != E; ++I) {
9530         Changed |= VisitNode(*I, TLSBaseAddrReg);
9531       }
9532 
9533       return Changed;
9534     }
9535 
9536     // Replace the TLS_base_addr instruction I with a copy from
9537     // TLSBaseAddrReg, returning the new instruction.
9538     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
9539                                          unsigned TLSBaseAddrReg) {
9540       MachineFunction *MF = I.getParent()->getParent();
9541       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
9542       const bool is64Bit = STI.is64Bit();
9543       const X86InstrInfo *TII = STI.getInstrInfo();
9544 
9545       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
9546       MachineInstr *Copy =
9547           BuildMI(*I.getParent(), I, I.getDebugLoc(),
9548                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
9549               .addReg(TLSBaseAddrReg);
9550 
9551       // Erase the TLS_base_addr instruction.
9552       I.eraseFromParent();
9553 
9554       return Copy;
9555     }
9556 
9557     // Create a virtal register in *TLSBaseAddrReg, and populate it by
9558     // inserting a copy instruction after I. Returns the new instruction.
9559     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
9560       MachineFunction *MF = I.getParent()->getParent();
9561       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
9562       const bool is64Bit = STI.is64Bit();
9563       const X86InstrInfo *TII = STI.getInstrInfo();
9564 
9565       // Create a virtual register for the TLS base address.
9566       MachineRegisterInfo &RegInfo = MF->getRegInfo();
9567       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
9568                                                       ? &X86::GR64RegClass
9569                                                       : &X86::GR32RegClass);
9570 
9571       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
9572       MachineInstr *Next = I.getNextNode();
9573       MachineInstr *Copy =
9574           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
9575                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
9576               .addReg(is64Bit ? X86::RAX : X86::EAX);
9577 
9578       return Copy;
9579     }
9580 
9581     StringRef getPassName() const override {
9582       return "Local Dynamic TLS Access Clean-up";
9583     }
9584 
9585     void getAnalysisUsage(AnalysisUsage &AU) const override {
9586       AU.setPreservesCFG();
9587       AU.addRequired<MachineDominatorTree>();
9588       MachineFunctionPass::getAnalysisUsage(AU);
9589     }
9590   };
9591 }
9592 
9593 char LDTLSCleanup::ID = 0;
9594 FunctionPass*
9595 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
9596