1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LiveIntervals.h"
23 #include "llvm/CodeGen/LivePhysRegs.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineDominators.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/IR/DebugInfoMetadata.h"
33 #include "llvm/IR/DerivedTypes.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/Target/TargetOptions.h"
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "x86-instr-info"
47 
48 #define GET_INSTRINFO_CTOR_DTOR
49 #include "X86GenInstrInfo.inc"
50 
51 static cl::opt<bool>
52     NoFusing("disable-spill-fusing",
53              cl::desc("Disable fusing of spill code into instructions"),
54              cl::Hidden);
55 static cl::opt<bool>
56 PrintFailedFusing("print-failed-fuse-candidates",
57                   cl::desc("Print instructions that the allocator wants to"
58                            " fuse, but the X86 backend currently can't"),
59                   cl::Hidden);
60 static cl::opt<bool>
61 ReMatPICStubLoad("remat-pic-stub-load",
62                  cl::desc("Re-materialize load from stub in PIC mode"),
63                  cl::init(false), cl::Hidden);
64 static cl::opt<unsigned>
65 PartialRegUpdateClearance("partial-reg-update-clearance",
66                           cl::desc("Clearance between two register writes "
67                                    "for inserting XOR to avoid partial "
68                                    "register update"),
69                           cl::init(64), cl::Hidden);
70 static cl::opt<unsigned>
71 UndefRegClearance("undef-reg-clearance",
72                   cl::desc("How many idle instructions we would like before "
73                            "certain undef register reads"),
74                   cl::init(128), cl::Hidden);
75 
76 
77 // Pin the vtable to this file.
78 void X86InstrInfo::anchor() {}
79 
80 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
81     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
82                                                : X86::ADJCALLSTACKDOWN32),
83                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
84                                                : X86::ADJCALLSTACKUP32),
85                       X86::CATCHRET,
86                       (STI.is64Bit() ? X86::RET64 : X86::RET32)),
87       Subtarget(STI), RI(STI.getTargetTriple()) {
88 }
89 
90 bool
91 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
92                                     Register &SrcReg, Register &DstReg,
93                                     unsigned &SubIdx) const {
94   switch (MI.getOpcode()) {
95   default: break;
96   case X86::MOVSX16rr8:
97   case X86::MOVZX16rr8:
98   case X86::MOVSX32rr8:
99   case X86::MOVZX32rr8:
100   case X86::MOVSX64rr8:
101     if (!Subtarget.is64Bit())
102       // It's not always legal to reference the low 8-bit of the larger
103       // register in 32-bit mode.
104       return false;
105     LLVM_FALLTHROUGH;
106   case X86::MOVSX32rr16:
107   case X86::MOVZX32rr16:
108   case X86::MOVSX64rr16:
109   case X86::MOVSX64rr32: {
110     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
111       // Be conservative.
112       return false;
113     SrcReg = MI.getOperand(1).getReg();
114     DstReg = MI.getOperand(0).getReg();
115     switch (MI.getOpcode()) {
116     default: llvm_unreachable("Unreachable!");
117     case X86::MOVSX16rr8:
118     case X86::MOVZX16rr8:
119     case X86::MOVSX32rr8:
120     case X86::MOVZX32rr8:
121     case X86::MOVSX64rr8:
122       SubIdx = X86::sub_8bit;
123       break;
124     case X86::MOVSX32rr16:
125     case X86::MOVZX32rr16:
126     case X86::MOVSX64rr16:
127       SubIdx = X86::sub_16bit;
128       break;
129     case X86::MOVSX64rr32:
130       SubIdx = X86::sub_32bit;
131       break;
132     }
133     return true;
134   }
135   }
136   return false;
137 }
138 
139 bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
140   if (MI.mayLoad() || MI.mayStore())
141     return false;
142 
143   // Some target-independent operations that trivially lower to data-invariant
144   // instructions.
145   if (MI.isCopyLike() || MI.isInsertSubreg())
146     return true;
147 
148   unsigned Opcode = MI.getOpcode();
149   using namespace X86;
150   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
151   // However, they set flags and are perhaps the most surprisingly constant
152   // time operations so we call them out here separately.
153   if (isIMUL(Opcode))
154     return true;
155   // Bit scanning and counting instructions that are somewhat surprisingly
156   // constant time as they scan across bits and do other fairly complex
157   // operations like popcnt, but are believed to be constant time on x86.
158   // However, these set flags.
159   if (isBSF(Opcode) || isBSR(Opcode) || isLZCNT(Opcode) || isPOPCNT(Opcode) ||
160       isTZCNT(Opcode))
161     return true;
162   // Bit manipulation instructions are effectively combinations of basic
163   // arithmetic ops, and should still execute in constant time. These also
164   // set flags.
165   if (isBLCFILL(Opcode) || isBLCI(Opcode) || isBLCIC(Opcode) ||
166       isBLCMSK(Opcode) || isBLCS(Opcode) || isBLSFILL(Opcode) ||
167       isBLSI(Opcode) || isBLSIC(Opcode) || isBLSMSK(Opcode) || isBLSR(Opcode) ||
168       isTZMSK(Opcode))
169     return true;
170   // Bit extracting and clearing instructions should execute in constant time,
171   // and set flags.
172   if (isBEXTR(Opcode) || isBZHI(Opcode))
173     return true;
174   // Shift and rotate.
175   if (isROL(Opcode) || isROR(Opcode) || isSAR(Opcode) || isSHL(Opcode) ||
176       isSHR(Opcode) || isSHLD(Opcode) || isSHRD(Opcode))
177     return true;
178   // Basic arithmetic is constant time on the input but does set flags.
179   if (isADC(Opcode) || isADD(Opcode) || isAND(Opcode) || isOR(Opcode) ||
180       isSBB(Opcode) || isSUB(Opcode) || isXOR(Opcode))
181     return true;
182   // Arithmetic with just 32-bit and 64-bit variants and no immediates.
183   if (isADCX(Opcode) || isADOX(Opcode) || isANDN(Opcode))
184     return true;
185   // Unary arithmetic operations.
186   if (isDEC(Opcode) || isINC(Opcode) || isNEG(Opcode))
187     return true;
188   // Unlike other arithmetic, NOT doesn't set EFLAGS.
189   if (isNOT(Opcode))
190     return true;
191   // Various move instructions used to zero or sign extend things. Note that we
192   // intentionally don't support the _NOREX variants as we can't handle that
193   // register constraint anyways.
194   if (isMOVSX(Opcode) || isMOVZX(Opcode) || isMOVSXD(Opcode) || isMOV(Opcode))
195     return true;
196   // Arithmetic instructions that are both constant time and don't set flags.
197   if (isRORX(Opcode) || isSARX(Opcode) || isSHLX(Opcode) || isSHRX(Opcode))
198     return true;
199   // LEA doesn't actually access memory, and its arithmetic is constant time.
200   if (isLEA(Opcode))
201     return true;
202   // By default, assume that the instruction is not data invariant.
203   return false;
204 }
205 
206 bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
207   switch (MI.getOpcode()) {
208   default:
209     // By default, assume that the load will immediately leak.
210     return false;
211 
212   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
213   // However, they set flags and are perhaps the most surprisingly constant
214   // time operations so we call them out here separately.
215   case X86::IMUL16rm:
216   case X86::IMUL16rmi8:
217   case X86::IMUL16rmi:
218   case X86::IMUL32rm:
219   case X86::IMUL32rmi8:
220   case X86::IMUL32rmi:
221   case X86::IMUL64rm:
222   case X86::IMUL64rmi32:
223   case X86::IMUL64rmi8:
224 
225   // Bit scanning and counting instructions that are somewhat surprisingly
226   // constant time as they scan across bits and do other fairly complex
227   // operations like popcnt, but are believed to be constant time on x86.
228   // However, these set flags.
229   case X86::BSF16rm:
230   case X86::BSF32rm:
231   case X86::BSF64rm:
232   case X86::BSR16rm:
233   case X86::BSR32rm:
234   case X86::BSR64rm:
235   case X86::LZCNT16rm:
236   case X86::LZCNT32rm:
237   case X86::LZCNT64rm:
238   case X86::POPCNT16rm:
239   case X86::POPCNT32rm:
240   case X86::POPCNT64rm:
241   case X86::TZCNT16rm:
242   case X86::TZCNT32rm:
243   case X86::TZCNT64rm:
244 
245   // Bit manipulation instructions are effectively combinations of basic
246   // arithmetic ops, and should still execute in constant time. These also
247   // set flags.
248   case X86::BLCFILL32rm:
249   case X86::BLCFILL64rm:
250   case X86::BLCI32rm:
251   case X86::BLCI64rm:
252   case X86::BLCIC32rm:
253   case X86::BLCIC64rm:
254   case X86::BLCMSK32rm:
255   case X86::BLCMSK64rm:
256   case X86::BLCS32rm:
257   case X86::BLCS64rm:
258   case X86::BLSFILL32rm:
259   case X86::BLSFILL64rm:
260   case X86::BLSI32rm:
261   case X86::BLSI64rm:
262   case X86::BLSIC32rm:
263   case X86::BLSIC64rm:
264   case X86::BLSMSK32rm:
265   case X86::BLSMSK64rm:
266   case X86::BLSR32rm:
267   case X86::BLSR64rm:
268   case X86::TZMSK32rm:
269   case X86::TZMSK64rm:
270 
271   // Bit extracting and clearing instructions should execute in constant time,
272   // and set flags.
273   case X86::BEXTR32rm:
274   case X86::BEXTR64rm:
275   case X86::BEXTRI32mi:
276   case X86::BEXTRI64mi:
277   case X86::BZHI32rm:
278   case X86::BZHI64rm:
279 
280   // Basic arithmetic is constant time on the input but does set flags.
281   case X86::ADC8rm:
282   case X86::ADC16rm:
283   case X86::ADC32rm:
284   case X86::ADC64rm:
285   case X86::ADCX32rm:
286   case X86::ADCX64rm:
287   case X86::ADD8rm:
288   case X86::ADD16rm:
289   case X86::ADD32rm:
290   case X86::ADD64rm:
291   case X86::ADOX32rm:
292   case X86::ADOX64rm:
293   case X86::AND8rm:
294   case X86::AND16rm:
295   case X86::AND32rm:
296   case X86::AND64rm:
297   case X86::ANDN32rm:
298   case X86::ANDN64rm:
299   case X86::OR8rm:
300   case X86::OR16rm:
301   case X86::OR32rm:
302   case X86::OR64rm:
303   case X86::SBB8rm:
304   case X86::SBB16rm:
305   case X86::SBB32rm:
306   case X86::SBB64rm:
307   case X86::SUB8rm:
308   case X86::SUB16rm:
309   case X86::SUB32rm:
310   case X86::SUB64rm:
311   case X86::XOR8rm:
312   case X86::XOR16rm:
313   case X86::XOR32rm:
314   case X86::XOR64rm:
315 
316   // Integer multiply w/o affecting flags is still believed to be constant
317   // time on x86. Called out separately as this is among the most surprising
318   // instructions to exhibit that behavior.
319   case X86::MULX32rm:
320   case X86::MULX64rm:
321 
322   // Arithmetic instructions that are both constant time and don't set flags.
323   case X86::RORX32mi:
324   case X86::RORX64mi:
325   case X86::SARX32rm:
326   case X86::SARX64rm:
327   case X86::SHLX32rm:
328   case X86::SHLX64rm:
329   case X86::SHRX32rm:
330   case X86::SHRX64rm:
331 
332   // Conversions are believed to be constant time and don't set flags.
333   case X86::CVTTSD2SI64rm:
334   case X86::VCVTTSD2SI64rm:
335   case X86::VCVTTSD2SI64Zrm:
336   case X86::CVTTSD2SIrm:
337   case X86::VCVTTSD2SIrm:
338   case X86::VCVTTSD2SIZrm:
339   case X86::CVTTSS2SI64rm:
340   case X86::VCVTTSS2SI64rm:
341   case X86::VCVTTSS2SI64Zrm:
342   case X86::CVTTSS2SIrm:
343   case X86::VCVTTSS2SIrm:
344   case X86::VCVTTSS2SIZrm:
345   case X86::CVTSI2SDrm:
346   case X86::VCVTSI2SDrm:
347   case X86::VCVTSI2SDZrm:
348   case X86::CVTSI2SSrm:
349   case X86::VCVTSI2SSrm:
350   case X86::VCVTSI2SSZrm:
351   case X86::CVTSI642SDrm:
352   case X86::VCVTSI642SDrm:
353   case X86::VCVTSI642SDZrm:
354   case X86::CVTSI642SSrm:
355   case X86::VCVTSI642SSrm:
356   case X86::VCVTSI642SSZrm:
357   case X86::CVTSS2SDrm:
358   case X86::VCVTSS2SDrm:
359   case X86::VCVTSS2SDZrm:
360   case X86::CVTSD2SSrm:
361   case X86::VCVTSD2SSrm:
362   case X86::VCVTSD2SSZrm:
363   // AVX512 added unsigned integer conversions.
364   case X86::VCVTTSD2USI64Zrm:
365   case X86::VCVTTSD2USIZrm:
366   case X86::VCVTTSS2USI64Zrm:
367   case X86::VCVTTSS2USIZrm:
368   case X86::VCVTUSI2SDZrm:
369   case X86::VCVTUSI642SDZrm:
370   case X86::VCVTUSI2SSZrm:
371   case X86::VCVTUSI642SSZrm:
372 
373   // Loads to register don't set flags.
374   case X86::MOV8rm:
375   case X86::MOV8rm_NOREX:
376   case X86::MOV16rm:
377   case X86::MOV32rm:
378   case X86::MOV64rm:
379   case X86::MOVSX16rm8:
380   case X86::MOVSX32rm16:
381   case X86::MOVSX32rm8:
382   case X86::MOVSX32rm8_NOREX:
383   case X86::MOVSX64rm16:
384   case X86::MOVSX64rm32:
385   case X86::MOVSX64rm8:
386   case X86::MOVZX16rm8:
387   case X86::MOVZX32rm16:
388   case X86::MOVZX32rm8:
389   case X86::MOVZX32rm8_NOREX:
390   case X86::MOVZX64rm16:
391   case X86::MOVZX64rm8:
392     return true;
393   }
394 }
395 
396 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
397   const MachineFunction *MF = MI.getParent()->getParent();
398   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
399 
400   if (isFrameInstr(MI)) {
401     int SPAdj = alignTo(getFrameSize(MI), TFI->getStackAlign());
402     SPAdj -= getFrameAdjustment(MI);
403     if (!isFrameSetup(MI))
404       SPAdj = -SPAdj;
405     return SPAdj;
406   }
407 
408   // To know whether a call adjusts the stack, we need information
409   // that is bound to the following ADJCALLSTACKUP pseudo.
410   // Look for the next ADJCALLSTACKUP that follows the call.
411   if (MI.isCall()) {
412     const MachineBasicBlock *MBB = MI.getParent();
413     auto I = ++MachineBasicBlock::const_iterator(MI);
414     for (auto E = MBB->end(); I != E; ++I) {
415       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
416           I->isCall())
417         break;
418     }
419 
420     // If we could not find a frame destroy opcode, then it has already
421     // been simplified, so we don't care.
422     if (I->getOpcode() != getCallFrameDestroyOpcode())
423       return 0;
424 
425     return -(I->getOperand(1).getImm());
426   }
427 
428   // Currently handle only PUSHes we can reasonably expect to see
429   // in call sequences
430   switch (MI.getOpcode()) {
431   default:
432     return 0;
433   case X86::PUSH32i8:
434   case X86::PUSH32r:
435   case X86::PUSH32rmm:
436   case X86::PUSH32rmr:
437   case X86::PUSHi32:
438     return 4;
439   case X86::PUSH64i8:
440   case X86::PUSH64r:
441   case X86::PUSH64rmm:
442   case X86::PUSH64rmr:
443   case X86::PUSH64i32:
444     return 8;
445   }
446 }
447 
448 /// Return true and the FrameIndex if the specified
449 /// operand and follow operands form a reference to the stack frame.
450 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
451                                   int &FrameIndex) const {
452   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
453       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
454       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
455       MI.getOperand(Op + X86::AddrDisp).isImm() &&
456       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
457       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
458       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
459     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
460     return true;
461   }
462   return false;
463 }
464 
465 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
466   switch (Opcode) {
467   default:
468     return false;
469   case X86::MOV8rm:
470   case X86::KMOVBkm:
471     MemBytes = 1;
472     return true;
473   case X86::MOV16rm:
474   case X86::KMOVWkm:
475   case X86::VMOVSHZrm:
476   case X86::VMOVSHZrm_alt:
477     MemBytes = 2;
478     return true;
479   case X86::MOV32rm:
480   case X86::MOVSSrm:
481   case X86::MOVSSrm_alt:
482   case X86::VMOVSSrm:
483   case X86::VMOVSSrm_alt:
484   case X86::VMOVSSZrm:
485   case X86::VMOVSSZrm_alt:
486   case X86::KMOVDkm:
487     MemBytes = 4;
488     return true;
489   case X86::MOV64rm:
490   case X86::LD_Fp64m:
491   case X86::MOVSDrm:
492   case X86::MOVSDrm_alt:
493   case X86::VMOVSDrm:
494   case X86::VMOVSDrm_alt:
495   case X86::VMOVSDZrm:
496   case X86::VMOVSDZrm_alt:
497   case X86::MMX_MOVD64rm:
498   case X86::MMX_MOVQ64rm:
499   case X86::KMOVQkm:
500     MemBytes = 8;
501     return true;
502   case X86::MOVAPSrm:
503   case X86::MOVUPSrm:
504   case X86::MOVAPDrm:
505   case X86::MOVUPDrm:
506   case X86::MOVDQArm:
507   case X86::MOVDQUrm:
508   case X86::VMOVAPSrm:
509   case X86::VMOVUPSrm:
510   case X86::VMOVAPDrm:
511   case X86::VMOVUPDrm:
512   case X86::VMOVDQArm:
513   case X86::VMOVDQUrm:
514   case X86::VMOVAPSZ128rm:
515   case X86::VMOVUPSZ128rm:
516   case X86::VMOVAPSZ128rm_NOVLX:
517   case X86::VMOVUPSZ128rm_NOVLX:
518   case X86::VMOVAPDZ128rm:
519   case X86::VMOVUPDZ128rm:
520   case X86::VMOVDQU8Z128rm:
521   case X86::VMOVDQU16Z128rm:
522   case X86::VMOVDQA32Z128rm:
523   case X86::VMOVDQU32Z128rm:
524   case X86::VMOVDQA64Z128rm:
525   case X86::VMOVDQU64Z128rm:
526     MemBytes = 16;
527     return true;
528   case X86::VMOVAPSYrm:
529   case X86::VMOVUPSYrm:
530   case X86::VMOVAPDYrm:
531   case X86::VMOVUPDYrm:
532   case X86::VMOVDQAYrm:
533   case X86::VMOVDQUYrm:
534   case X86::VMOVAPSZ256rm:
535   case X86::VMOVUPSZ256rm:
536   case X86::VMOVAPSZ256rm_NOVLX:
537   case X86::VMOVUPSZ256rm_NOVLX:
538   case X86::VMOVAPDZ256rm:
539   case X86::VMOVUPDZ256rm:
540   case X86::VMOVDQU8Z256rm:
541   case X86::VMOVDQU16Z256rm:
542   case X86::VMOVDQA32Z256rm:
543   case X86::VMOVDQU32Z256rm:
544   case X86::VMOVDQA64Z256rm:
545   case X86::VMOVDQU64Z256rm:
546     MemBytes = 32;
547     return true;
548   case X86::VMOVAPSZrm:
549   case X86::VMOVUPSZrm:
550   case X86::VMOVAPDZrm:
551   case X86::VMOVUPDZrm:
552   case X86::VMOVDQU8Zrm:
553   case X86::VMOVDQU16Zrm:
554   case X86::VMOVDQA32Zrm:
555   case X86::VMOVDQU32Zrm:
556   case X86::VMOVDQA64Zrm:
557   case X86::VMOVDQU64Zrm:
558     MemBytes = 64;
559     return true;
560   }
561 }
562 
563 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
564   switch (Opcode) {
565   default:
566     return false;
567   case X86::MOV8mr:
568   case X86::KMOVBmk:
569     MemBytes = 1;
570     return true;
571   case X86::MOV16mr:
572   case X86::KMOVWmk:
573   case X86::VMOVSHZmr:
574     MemBytes = 2;
575     return true;
576   case X86::MOV32mr:
577   case X86::MOVSSmr:
578   case X86::VMOVSSmr:
579   case X86::VMOVSSZmr:
580   case X86::KMOVDmk:
581     MemBytes = 4;
582     return true;
583   case X86::MOV64mr:
584   case X86::ST_FpP64m:
585   case X86::MOVSDmr:
586   case X86::VMOVSDmr:
587   case X86::VMOVSDZmr:
588   case X86::MMX_MOVD64mr:
589   case X86::MMX_MOVQ64mr:
590   case X86::MMX_MOVNTQmr:
591   case X86::KMOVQmk:
592     MemBytes = 8;
593     return true;
594   case X86::MOVAPSmr:
595   case X86::MOVUPSmr:
596   case X86::MOVAPDmr:
597   case X86::MOVUPDmr:
598   case X86::MOVDQAmr:
599   case X86::MOVDQUmr:
600   case X86::VMOVAPSmr:
601   case X86::VMOVUPSmr:
602   case X86::VMOVAPDmr:
603   case X86::VMOVUPDmr:
604   case X86::VMOVDQAmr:
605   case X86::VMOVDQUmr:
606   case X86::VMOVUPSZ128mr:
607   case X86::VMOVAPSZ128mr:
608   case X86::VMOVUPSZ128mr_NOVLX:
609   case X86::VMOVAPSZ128mr_NOVLX:
610   case X86::VMOVUPDZ128mr:
611   case X86::VMOVAPDZ128mr:
612   case X86::VMOVDQA32Z128mr:
613   case X86::VMOVDQU32Z128mr:
614   case X86::VMOVDQA64Z128mr:
615   case X86::VMOVDQU64Z128mr:
616   case X86::VMOVDQU8Z128mr:
617   case X86::VMOVDQU16Z128mr:
618     MemBytes = 16;
619     return true;
620   case X86::VMOVUPSYmr:
621   case X86::VMOVAPSYmr:
622   case X86::VMOVUPDYmr:
623   case X86::VMOVAPDYmr:
624   case X86::VMOVDQUYmr:
625   case X86::VMOVDQAYmr:
626   case X86::VMOVUPSZ256mr:
627   case X86::VMOVAPSZ256mr:
628   case X86::VMOVUPSZ256mr_NOVLX:
629   case X86::VMOVAPSZ256mr_NOVLX:
630   case X86::VMOVUPDZ256mr:
631   case X86::VMOVAPDZ256mr:
632   case X86::VMOVDQU8Z256mr:
633   case X86::VMOVDQU16Z256mr:
634   case X86::VMOVDQA32Z256mr:
635   case X86::VMOVDQU32Z256mr:
636   case X86::VMOVDQA64Z256mr:
637   case X86::VMOVDQU64Z256mr:
638     MemBytes = 32;
639     return true;
640   case X86::VMOVUPSZmr:
641   case X86::VMOVAPSZmr:
642   case X86::VMOVUPDZmr:
643   case X86::VMOVAPDZmr:
644   case X86::VMOVDQU8Zmr:
645   case X86::VMOVDQU16Zmr:
646   case X86::VMOVDQA32Zmr:
647   case X86::VMOVDQU32Zmr:
648   case X86::VMOVDQA64Zmr:
649   case X86::VMOVDQU64Zmr:
650     MemBytes = 64;
651     return true;
652   }
653   return false;
654 }
655 
656 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
657                                            int &FrameIndex) const {
658   unsigned Dummy;
659   return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
660 }
661 
662 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
663                                            int &FrameIndex,
664                                            unsigned &MemBytes) const {
665   if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
666     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
667       return MI.getOperand(0).getReg();
668   return 0;
669 }
670 
671 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
672                                                  int &FrameIndex) const {
673   unsigned Dummy;
674   if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
675     unsigned Reg;
676     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
677       return Reg;
678     // Check for post-frame index elimination operations
679     SmallVector<const MachineMemOperand *, 1> Accesses;
680     if (hasLoadFromStackSlot(MI, Accesses)) {
681       FrameIndex =
682           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
683               ->getFrameIndex();
684       return MI.getOperand(0).getReg();
685     }
686   }
687   return 0;
688 }
689 
690 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
691                                           int &FrameIndex) const {
692   unsigned Dummy;
693   return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
694 }
695 
696 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
697                                           int &FrameIndex,
698                                           unsigned &MemBytes) const {
699   if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
700     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
701         isFrameOperand(MI, 0, FrameIndex))
702       return MI.getOperand(X86::AddrNumOperands).getReg();
703   return 0;
704 }
705 
706 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
707                                                 int &FrameIndex) const {
708   unsigned Dummy;
709   if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
710     unsigned Reg;
711     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
712       return Reg;
713     // Check for post-frame index elimination operations
714     SmallVector<const MachineMemOperand *, 1> Accesses;
715     if (hasStoreToStackSlot(MI, Accesses)) {
716       FrameIndex =
717           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
718               ->getFrameIndex();
719       return MI.getOperand(X86::AddrNumOperands).getReg();
720     }
721   }
722   return 0;
723 }
724 
725 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
726 static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI) {
727   // Don't waste compile time scanning use-def chains of physregs.
728   if (!BaseReg.isVirtual())
729     return false;
730   bool isPICBase = false;
731   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
732          E = MRI.def_instr_end(); I != E; ++I) {
733     MachineInstr *DefMI = &*I;
734     if (DefMI->getOpcode() != X86::MOVPC32r)
735       return false;
736     assert(!isPICBase && "More than one PIC base?");
737     isPICBase = true;
738   }
739   return isPICBase;
740 }
741 
742 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
743                                                      AAResults *AA) const {
744   switch (MI.getOpcode()) {
745   default:
746     // This function should only be called for opcodes with the ReMaterializable
747     // flag set.
748     llvm_unreachable("Unknown rematerializable operation!");
749     break;
750 
751   case X86::LOAD_STACK_GUARD:
752   case X86::AVX1_SETALLONES:
753   case X86::AVX2_SETALLONES:
754   case X86::AVX512_128_SET0:
755   case X86::AVX512_256_SET0:
756   case X86::AVX512_512_SET0:
757   case X86::AVX512_512_SETALLONES:
758   case X86::AVX512_FsFLD0SD:
759   case X86::AVX512_FsFLD0SH:
760   case X86::AVX512_FsFLD0SS:
761   case X86::AVX512_FsFLD0F128:
762   case X86::AVX_SET0:
763   case X86::FsFLD0SD:
764   case X86::FsFLD0SS:
765   case X86::FsFLD0F128:
766   case X86::KSET0D:
767   case X86::KSET0Q:
768   case X86::KSET0W:
769   case X86::KSET1D:
770   case X86::KSET1Q:
771   case X86::KSET1W:
772   case X86::MMX_SET0:
773   case X86::MOV32ImmSExti8:
774   case X86::MOV32r0:
775   case X86::MOV32r1:
776   case X86::MOV32r_1:
777   case X86::MOV32ri64:
778   case X86::MOV64ImmSExti8:
779   case X86::V_SET0:
780   case X86::V_SETALLONES:
781   case X86::MOV16ri:
782   case X86::MOV32ri:
783   case X86::MOV64ri:
784   case X86::MOV64ri32:
785   case X86::MOV8ri:
786   case X86::PTILEZEROV:
787     return true;
788 
789   case X86::MOV8rm:
790   case X86::MOV8rm_NOREX:
791   case X86::MOV16rm:
792   case X86::MOV32rm:
793   case X86::MOV64rm:
794   case X86::MOVSSrm:
795   case X86::MOVSSrm_alt:
796   case X86::MOVSDrm:
797   case X86::MOVSDrm_alt:
798   case X86::MOVAPSrm:
799   case X86::MOVUPSrm:
800   case X86::MOVAPDrm:
801   case X86::MOVUPDrm:
802   case X86::MOVDQArm:
803   case X86::MOVDQUrm:
804   case X86::VMOVSSrm:
805   case X86::VMOVSSrm_alt:
806   case X86::VMOVSDrm:
807   case X86::VMOVSDrm_alt:
808   case X86::VMOVAPSrm:
809   case X86::VMOVUPSrm:
810   case X86::VMOVAPDrm:
811   case X86::VMOVUPDrm:
812   case X86::VMOVDQArm:
813   case X86::VMOVDQUrm:
814   case X86::VMOVAPSYrm:
815   case X86::VMOVUPSYrm:
816   case X86::VMOVAPDYrm:
817   case X86::VMOVUPDYrm:
818   case X86::VMOVDQAYrm:
819   case X86::VMOVDQUYrm:
820   case X86::MMX_MOVD64rm:
821   case X86::MMX_MOVQ64rm:
822   // AVX-512
823   case X86::VMOVSSZrm:
824   case X86::VMOVSSZrm_alt:
825   case X86::VMOVSDZrm:
826   case X86::VMOVSDZrm_alt:
827   case X86::VMOVSHZrm:
828   case X86::VMOVSHZrm_alt:
829   case X86::VMOVAPDZ128rm:
830   case X86::VMOVAPDZ256rm:
831   case X86::VMOVAPDZrm:
832   case X86::VMOVAPSZ128rm:
833   case X86::VMOVAPSZ256rm:
834   case X86::VMOVAPSZ128rm_NOVLX:
835   case X86::VMOVAPSZ256rm_NOVLX:
836   case X86::VMOVAPSZrm:
837   case X86::VMOVDQA32Z128rm:
838   case X86::VMOVDQA32Z256rm:
839   case X86::VMOVDQA32Zrm:
840   case X86::VMOVDQA64Z128rm:
841   case X86::VMOVDQA64Z256rm:
842   case X86::VMOVDQA64Zrm:
843   case X86::VMOVDQU16Z128rm:
844   case X86::VMOVDQU16Z256rm:
845   case X86::VMOVDQU16Zrm:
846   case X86::VMOVDQU32Z128rm:
847   case X86::VMOVDQU32Z256rm:
848   case X86::VMOVDQU32Zrm:
849   case X86::VMOVDQU64Z128rm:
850   case X86::VMOVDQU64Z256rm:
851   case X86::VMOVDQU64Zrm:
852   case X86::VMOVDQU8Z128rm:
853   case X86::VMOVDQU8Z256rm:
854   case X86::VMOVDQU8Zrm:
855   case X86::VMOVUPDZ128rm:
856   case X86::VMOVUPDZ256rm:
857   case X86::VMOVUPDZrm:
858   case X86::VMOVUPSZ128rm:
859   case X86::VMOVUPSZ256rm:
860   case X86::VMOVUPSZ128rm_NOVLX:
861   case X86::VMOVUPSZ256rm_NOVLX:
862   case X86::VMOVUPSZrm: {
863     // Loads from constant pools are trivially rematerializable.
864     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
865         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
866         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
867         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
868         MI.isDereferenceableInvariantLoad(AA)) {
869       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
870       if (BaseReg == 0 || BaseReg == X86::RIP)
871         return true;
872       // Allow re-materialization of PIC load.
873       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
874         return false;
875       const MachineFunction &MF = *MI.getParent()->getParent();
876       const MachineRegisterInfo &MRI = MF.getRegInfo();
877       return regIsPICBase(BaseReg, MRI);
878     }
879     return false;
880   }
881 
882   case X86::LEA32r:
883   case X86::LEA64r: {
884     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
885         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
886         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
887         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
888       // lea fi#, lea GV, etc. are all rematerializable.
889       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
890         return true;
891       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
892       if (BaseReg == 0)
893         return true;
894       // Allow re-materialization of lea PICBase + x.
895       const MachineFunction &MF = *MI.getParent()->getParent();
896       const MachineRegisterInfo &MRI = MF.getRegInfo();
897       return regIsPICBase(BaseReg, MRI);
898     }
899     return false;
900   }
901   }
902 }
903 
904 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
905                                  MachineBasicBlock::iterator I,
906                                  Register DestReg, unsigned SubIdx,
907                                  const MachineInstr &Orig,
908                                  const TargetRegisterInfo &TRI) const {
909   bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
910   if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
911                             MachineBasicBlock::LQR_Dead) {
912     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
913     // effects.
914     int Value;
915     switch (Orig.getOpcode()) {
916     case X86::MOV32r0:  Value = 0; break;
917     case X86::MOV32r1:  Value = 1; break;
918     case X86::MOV32r_1: Value = -1; break;
919     default:
920       llvm_unreachable("Unexpected instruction!");
921     }
922 
923     const DebugLoc &DL = Orig.getDebugLoc();
924     BuildMI(MBB, I, DL, get(X86::MOV32ri))
925         .add(Orig.getOperand(0))
926         .addImm(Value);
927   } else {
928     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
929     MBB.insert(I, MI);
930   }
931 
932   MachineInstr &NewMI = *std::prev(I);
933   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
934 }
935 
936 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
937 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
938   for (const MachineOperand &MO : MI.operands()) {
939     if (MO.isReg() && MO.isDef() &&
940         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
941       return true;
942     }
943   }
944   return false;
945 }
946 
947 /// Check whether the shift count for a machine operand is non-zero.
948 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
949                                               unsigned ShiftAmtOperandIdx) {
950   // The shift count is six bits with the REX.W prefix and five bits without.
951   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
952   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
953   return Imm & ShiftCountMask;
954 }
955 
956 /// Check whether the given shift count is appropriate
957 /// can be represented by a LEA instruction.
958 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
959   // Left shift instructions can be transformed into load-effective-address
960   // instructions if we can encode them appropriately.
961   // A LEA instruction utilizes a SIB byte to encode its scale factor.
962   // The SIB.scale field is two bits wide which means that we can encode any
963   // shift amount less than 4.
964   return ShAmt < 4 && ShAmt > 0;
965 }
966 
967 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
968                                   unsigned Opc, bool AllowSP, Register &NewSrc,
969                                   bool &isKill, MachineOperand &ImplicitOp,
970                                   LiveVariables *LV, LiveIntervals *LIS) const {
971   MachineFunction &MF = *MI.getParent()->getParent();
972   const TargetRegisterClass *RC;
973   if (AllowSP) {
974     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
975   } else {
976     RC = Opc != X86::LEA32r ?
977       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
978   }
979   Register SrcReg = Src.getReg();
980   isKill = MI.killsRegister(SrcReg);
981 
982   // For both LEA64 and LEA32 the register already has essentially the right
983   // type (32-bit or 64-bit) we may just need to forbid SP.
984   if (Opc != X86::LEA64_32r) {
985     NewSrc = SrcReg;
986     assert(!Src.isUndef() && "Undef op doesn't need optimization");
987 
988     if (NewSrc.isVirtual() && !MF.getRegInfo().constrainRegClass(NewSrc, RC))
989       return false;
990 
991     return true;
992   }
993 
994   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
995   // another we need to add 64-bit registers to the final MI.
996   if (SrcReg.isPhysical()) {
997     ImplicitOp = Src;
998     ImplicitOp.setImplicit();
999 
1000     NewSrc = getX86SubSuperRegister(SrcReg, 64);
1001     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1002   } else {
1003     // Virtual register of the wrong class, we have to create a temporary 64-bit
1004     // vreg to feed into the LEA.
1005     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1006     MachineInstr *Copy =
1007         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1008             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1009             .addReg(SrcReg, getKillRegState(isKill));
1010 
1011     // Which is obviously going to be dead after we're done with it.
1012     isKill = true;
1013 
1014     if (LV)
1015       LV->replaceKillInstruction(SrcReg, MI, *Copy);
1016 
1017     if (LIS) {
1018       SlotIndex CopyIdx = LIS->InsertMachineInstrInMaps(*Copy);
1019       SlotIndex Idx = LIS->getInstructionIndex(MI);
1020       LiveInterval &LI = LIS->getInterval(SrcReg);
1021       LiveRange::Segment *S = LI.getSegmentContaining(Idx);
1022       if (S->end.getBaseIndex() == Idx)
1023         S->end = CopyIdx.getRegSlot();
1024     }
1025   }
1026 
1027   // We've set all the parameters without issue.
1028   return true;
1029 }
1030 
1031 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1032                                                          MachineInstr &MI,
1033                                                          LiveVariables *LV,
1034                                                          LiveIntervals *LIS,
1035                                                          bool Is8BitOp) const {
1036   // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1037   MachineBasicBlock &MBB = *MI.getParent();
1038   MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
1039   assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1040               *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1041          "Unexpected type for LEA transform");
1042 
1043   // TODO: For a 32-bit target, we need to adjust the LEA variables with
1044   // something like this:
1045   //   Opcode = X86::LEA32r;
1046   //   InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1047   //   OutRegLEA =
1048   //       Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1049   //                : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1050   if (!Subtarget.is64Bit())
1051     return nullptr;
1052 
1053   unsigned Opcode = X86::LEA64_32r;
1054   Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1055   Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1056   Register InRegLEA2;
1057 
1058   // Build and insert into an implicit UNDEF value. This is OK because
1059   // we will be shifting and then extracting the lower 8/16-bits.
1060   // This has the potential to cause partial register stall. e.g.
1061   //   movw    (%rbp,%rcx,2), %dx
1062   //   leal    -65(%rdx), %esi
1063   // But testing has shown this *does* help performance in 64-bit mode (at
1064   // least on modern x86 machines).
1065   MachineBasicBlock::iterator MBBI = MI.getIterator();
1066   Register Dest = MI.getOperand(0).getReg();
1067   Register Src = MI.getOperand(1).getReg();
1068   Register Src2;
1069   bool IsDead = MI.getOperand(0).isDead();
1070   bool IsKill = MI.getOperand(1).isKill();
1071   unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1072   assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
1073   MachineInstr *ImpDef =
1074       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
1075   MachineInstr *InsMI =
1076       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1077           .addReg(InRegLEA, RegState::Define, SubReg)
1078           .addReg(Src, getKillRegState(IsKill));
1079   MachineInstr *ImpDef2 = nullptr;
1080   MachineInstr *InsMI2 = nullptr;
1081 
1082   MachineInstrBuilder MIB =
1083       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
1084   switch (MIOpc) {
1085   default: llvm_unreachable("Unreachable!");
1086   case X86::SHL8ri:
1087   case X86::SHL16ri: {
1088     unsigned ShAmt = MI.getOperand(2).getImm();
1089     MIB.addReg(0).addImm(1ULL << ShAmt)
1090        .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
1091     break;
1092   }
1093   case X86::INC8r:
1094   case X86::INC16r:
1095     addRegOffset(MIB, InRegLEA, true, 1);
1096     break;
1097   case X86::DEC8r:
1098   case X86::DEC16r:
1099     addRegOffset(MIB, InRegLEA, true, -1);
1100     break;
1101   case X86::ADD8ri:
1102   case X86::ADD8ri_DB:
1103   case X86::ADD16ri:
1104   case X86::ADD16ri8:
1105   case X86::ADD16ri_DB:
1106   case X86::ADD16ri8_DB:
1107     addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1108     break;
1109   case X86::ADD8rr:
1110   case X86::ADD8rr_DB:
1111   case X86::ADD16rr:
1112   case X86::ADD16rr_DB: {
1113     Src2 = MI.getOperand(2).getReg();
1114     bool IsKill2 = MI.getOperand(2).isKill();
1115     assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
1116     if (Src == Src2) {
1117       // ADD8rr/ADD16rr killed %reg1028, %reg1028
1118       // just a single insert_subreg.
1119       addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1120     } else {
1121       if (Subtarget.is64Bit())
1122         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1123       else
1124         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1125       // Build and insert into an implicit UNDEF value. This is OK because
1126       // we will be shifting and then extracting the lower 8/16-bits.
1127       ImpDef2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF),
1128                         InRegLEA2);
1129       InsMI2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1130                    .addReg(InRegLEA2, RegState::Define, SubReg)
1131                    .addReg(Src2, getKillRegState(IsKill2));
1132       addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1133     }
1134     if (LV && IsKill2 && InsMI2)
1135       LV->replaceKillInstruction(Src2, MI, *InsMI2);
1136     break;
1137   }
1138   }
1139 
1140   MachineInstr *NewMI = MIB;
1141   MachineInstr *ExtMI =
1142       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1143           .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
1144           .addReg(OutRegLEA, RegState::Kill, SubReg);
1145 
1146   if (LV) {
1147     // Update live variables.
1148     LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1149     LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
1150     if (IsKill)
1151       LV->replaceKillInstruction(Src, MI, *InsMI);
1152     if (IsDead)
1153       LV->replaceKillInstruction(Dest, MI, *ExtMI);
1154   }
1155 
1156   if (LIS) {
1157     LIS->InsertMachineInstrInMaps(*ImpDef);
1158     SlotIndex InsIdx = LIS->InsertMachineInstrInMaps(*InsMI);
1159     if (ImpDef2)
1160       LIS->InsertMachineInstrInMaps(*ImpDef2);
1161     SlotIndex Ins2Idx;
1162     if (InsMI2)
1163       Ins2Idx = LIS->InsertMachineInstrInMaps(*InsMI2);
1164     SlotIndex NewIdx = LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
1165     SlotIndex ExtIdx = LIS->InsertMachineInstrInMaps(*ExtMI);
1166     LIS->getInterval(InRegLEA);
1167     LIS->getInterval(OutRegLEA);
1168     if (InRegLEA2)
1169       LIS->getInterval(InRegLEA2);
1170 
1171     // Move the use of Src up to InsMI.
1172     LiveInterval &SrcLI = LIS->getInterval(Src);
1173     LiveRange::Segment *SrcSeg = SrcLI.getSegmentContaining(NewIdx);
1174     if (SrcSeg->end == NewIdx.getRegSlot())
1175       SrcSeg->end = InsIdx.getRegSlot();
1176 
1177     if (InsMI2) {
1178       // Move the use of Src2 up to InsMI2.
1179       LiveInterval &Src2LI = LIS->getInterval(Src2);
1180       LiveRange::Segment *Src2Seg = Src2LI.getSegmentContaining(NewIdx);
1181       if (Src2Seg->end == NewIdx.getRegSlot())
1182         Src2Seg->end = Ins2Idx.getRegSlot();
1183     }
1184 
1185     // Move the definition of Dest down to ExtMI.
1186     LiveInterval &DestLI = LIS->getInterval(Dest);
1187     LiveRange::Segment *DestSeg =
1188         DestLI.getSegmentContaining(NewIdx.getRegSlot());
1189     assert(DestSeg->start == NewIdx.getRegSlot() &&
1190            DestSeg->valno->def == NewIdx.getRegSlot());
1191     DestSeg->start = ExtIdx.getRegSlot();
1192     DestSeg->valno->def = ExtIdx.getRegSlot();
1193   }
1194 
1195   return ExtMI;
1196 }
1197 
1198 /// This method must be implemented by targets that
1199 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1200 /// may be able to convert a two-address instruction into a true
1201 /// three-address instruction on demand.  This allows the X86 target (for
1202 /// example) to convert ADD and SHL instructions into LEA instructions if they
1203 /// would require register copies due to two-addressness.
1204 ///
1205 /// This method returns a null pointer if the transformation cannot be
1206 /// performed, otherwise it returns the new instruction.
1207 ///
1208 MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
1209                                                   LiveVariables *LV,
1210                                                   LiveIntervals *LIS) const {
1211   // The following opcodes also sets the condition code register(s). Only
1212   // convert them to equivalent lea if the condition code register def's
1213   // are dead!
1214   if (hasLiveCondCodeDef(MI))
1215     return nullptr;
1216 
1217   MachineFunction &MF = *MI.getParent()->getParent();
1218   // All instructions input are two-addr instructions.  Get the known operands.
1219   const MachineOperand &Dest = MI.getOperand(0);
1220   const MachineOperand &Src = MI.getOperand(1);
1221 
1222   // Ideally, operations with undef should be folded before we get here, but we
1223   // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1224   // Without this, we have to forward undef state to new register operands to
1225   // avoid machine verifier errors.
1226   if (Src.isUndef())
1227     return nullptr;
1228   if (MI.getNumOperands() > 2)
1229     if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
1230       return nullptr;
1231 
1232   MachineInstr *NewMI = nullptr;
1233   Register SrcReg, SrcReg2;
1234   bool Is64Bit = Subtarget.is64Bit();
1235 
1236   bool Is8BitOp = false;
1237   unsigned MIOpc = MI.getOpcode();
1238   switch (MIOpc) {
1239   default: llvm_unreachable("Unreachable!");
1240   case X86::SHL64ri: {
1241     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1242     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1243     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1244 
1245     // LEA can't handle RSP.
1246     if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass(
1247                                         Src.getReg(), &X86::GR64_NOSPRegClass))
1248       return nullptr;
1249 
1250     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1251                 .add(Dest)
1252                 .addReg(0)
1253                 .addImm(1ULL << ShAmt)
1254                 .add(Src)
1255                 .addImm(0)
1256                 .addReg(0);
1257     break;
1258   }
1259   case X86::SHL32ri: {
1260     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1261     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1262     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1263 
1264     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1265 
1266     // LEA can't handle ESP.
1267     bool isKill;
1268     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1269     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1270                         ImplicitOp, LV, LIS))
1271       return nullptr;
1272 
1273     MachineInstrBuilder MIB =
1274         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1275             .add(Dest)
1276             .addReg(0)
1277             .addImm(1ULL << ShAmt)
1278             .addReg(SrcReg, getKillRegState(isKill))
1279             .addImm(0)
1280             .addReg(0);
1281     if (ImplicitOp.getReg() != 0)
1282       MIB.add(ImplicitOp);
1283     NewMI = MIB;
1284 
1285     break;
1286   }
1287   case X86::SHL8ri:
1288     Is8BitOp = true;
1289     LLVM_FALLTHROUGH;
1290   case X86::SHL16ri: {
1291     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1292     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1293     if (!isTruncatedShiftCountForLEA(ShAmt))
1294       return nullptr;
1295     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1296   }
1297   case X86::INC64r:
1298   case X86::INC32r: {
1299     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1300     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1301         (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1302     bool isKill;
1303     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1304     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1305                         ImplicitOp, LV, LIS))
1306       return nullptr;
1307 
1308     MachineInstrBuilder MIB =
1309         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1310             .add(Dest)
1311             .addReg(SrcReg, getKillRegState(isKill));
1312     if (ImplicitOp.getReg() != 0)
1313       MIB.add(ImplicitOp);
1314 
1315     NewMI = addOffset(MIB, 1);
1316     break;
1317   }
1318   case X86::DEC64r:
1319   case X86::DEC32r: {
1320     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1321     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1322         : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1323 
1324     bool isKill;
1325     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1326     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1327                         ImplicitOp, LV, LIS))
1328       return nullptr;
1329 
1330     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1331                                   .add(Dest)
1332                                   .addReg(SrcReg, getKillRegState(isKill));
1333     if (ImplicitOp.getReg() != 0)
1334       MIB.add(ImplicitOp);
1335 
1336     NewMI = addOffset(MIB, -1);
1337 
1338     break;
1339   }
1340   case X86::DEC8r:
1341   case X86::INC8r:
1342     Is8BitOp = true;
1343     LLVM_FALLTHROUGH;
1344   case X86::DEC16r:
1345   case X86::INC16r:
1346     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1347   case X86::ADD64rr:
1348   case X86::ADD64rr_DB:
1349   case X86::ADD32rr:
1350   case X86::ADD32rr_DB: {
1351     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1352     unsigned Opc;
1353     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1354       Opc = X86::LEA64r;
1355     else
1356       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1357 
1358     const MachineOperand &Src2 = MI.getOperand(2);
1359     bool isKill2;
1360     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1361     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/false, SrcReg2, isKill2,
1362                         ImplicitOp2, LV, LIS))
1363       return nullptr;
1364 
1365     bool isKill;
1366     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1367     if (Src.getReg() == Src2.getReg()) {
1368       // Don't call classify LEAReg a second time on the same register, in case
1369       // the first call inserted a COPY from Src2 and marked it as killed.
1370       isKill = isKill2;
1371       SrcReg = SrcReg2;
1372     } else {
1373       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1374                           ImplicitOp, LV, LIS))
1375         return nullptr;
1376     }
1377 
1378     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1379     if (ImplicitOp.getReg() != 0)
1380       MIB.add(ImplicitOp);
1381     if (ImplicitOp2.getReg() != 0)
1382       MIB.add(ImplicitOp2);
1383 
1384     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1385     if (LV && Src2.isKill())
1386       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1387     break;
1388   }
1389   case X86::ADD8rr:
1390   case X86::ADD8rr_DB:
1391     Is8BitOp = true;
1392     LLVM_FALLTHROUGH;
1393   case X86::ADD16rr:
1394   case X86::ADD16rr_DB:
1395     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1396   case X86::ADD64ri32:
1397   case X86::ADD64ri8:
1398   case X86::ADD64ri32_DB:
1399   case X86::ADD64ri8_DB:
1400     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1401     NewMI = addOffset(
1402         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1403         MI.getOperand(2));
1404     break;
1405   case X86::ADD32ri:
1406   case X86::ADD32ri8:
1407   case X86::ADD32ri_DB:
1408   case X86::ADD32ri8_DB: {
1409     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1410     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1411 
1412     bool isKill;
1413     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1414     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1415                         ImplicitOp, LV, LIS))
1416       return nullptr;
1417 
1418     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1419                                   .add(Dest)
1420                                   .addReg(SrcReg, getKillRegState(isKill));
1421     if (ImplicitOp.getReg() != 0)
1422       MIB.add(ImplicitOp);
1423 
1424     NewMI = addOffset(MIB, MI.getOperand(2));
1425     break;
1426   }
1427   case X86::ADD8ri:
1428   case X86::ADD8ri_DB:
1429     Is8BitOp = true;
1430     LLVM_FALLTHROUGH;
1431   case X86::ADD16ri:
1432   case X86::ADD16ri8:
1433   case X86::ADD16ri_DB:
1434   case X86::ADD16ri8_DB:
1435     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1436   case X86::SUB8ri:
1437   case X86::SUB16ri8:
1438   case X86::SUB16ri:
1439     /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1440     return nullptr;
1441   case X86::SUB32ri8:
1442   case X86::SUB32ri: {
1443     if (!MI.getOperand(2).isImm())
1444       return nullptr;
1445     int64_t Imm = MI.getOperand(2).getImm();
1446     if (!isInt<32>(-Imm))
1447       return nullptr;
1448 
1449     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1450     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1451 
1452     bool isKill;
1453     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1454     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1455                         ImplicitOp, LV, LIS))
1456       return nullptr;
1457 
1458     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1459                                   .add(Dest)
1460                                   .addReg(SrcReg, getKillRegState(isKill));
1461     if (ImplicitOp.getReg() != 0)
1462       MIB.add(ImplicitOp);
1463 
1464     NewMI = addOffset(MIB, -Imm);
1465     break;
1466   }
1467 
1468   case X86::SUB64ri8:
1469   case X86::SUB64ri32: {
1470     if (!MI.getOperand(2).isImm())
1471       return nullptr;
1472     int64_t Imm = MI.getOperand(2).getImm();
1473     if (!isInt<32>(-Imm))
1474       return nullptr;
1475 
1476     assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1477 
1478     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1479                                       get(X86::LEA64r)).add(Dest).add(Src);
1480     NewMI = addOffset(MIB, -Imm);
1481     break;
1482   }
1483 
1484   case X86::VMOVDQU8Z128rmk:
1485   case X86::VMOVDQU8Z256rmk:
1486   case X86::VMOVDQU8Zrmk:
1487   case X86::VMOVDQU16Z128rmk:
1488   case X86::VMOVDQU16Z256rmk:
1489   case X86::VMOVDQU16Zrmk:
1490   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1491   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1492   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
1493   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1494   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1495   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
1496   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
1497   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
1498   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
1499   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
1500   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
1501   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk:
1502   case X86::VBROADCASTSDZ256rmk:
1503   case X86::VBROADCASTSDZrmk:
1504   case X86::VBROADCASTSSZ128rmk:
1505   case X86::VBROADCASTSSZ256rmk:
1506   case X86::VBROADCASTSSZrmk:
1507   case X86::VPBROADCASTDZ128rmk:
1508   case X86::VPBROADCASTDZ256rmk:
1509   case X86::VPBROADCASTDZrmk:
1510   case X86::VPBROADCASTQZ128rmk:
1511   case X86::VPBROADCASTQZ256rmk:
1512   case X86::VPBROADCASTQZrmk: {
1513     unsigned Opc;
1514     switch (MIOpc) {
1515     default: llvm_unreachable("Unreachable!");
1516     case X86::VMOVDQU8Z128rmk:     Opc = X86::VPBLENDMBZ128rmk; break;
1517     case X86::VMOVDQU8Z256rmk:     Opc = X86::VPBLENDMBZ256rmk; break;
1518     case X86::VMOVDQU8Zrmk:        Opc = X86::VPBLENDMBZrmk;    break;
1519     case X86::VMOVDQU16Z128rmk:    Opc = X86::VPBLENDMWZ128rmk; break;
1520     case X86::VMOVDQU16Z256rmk:    Opc = X86::VPBLENDMWZ256rmk; break;
1521     case X86::VMOVDQU16Zrmk:       Opc = X86::VPBLENDMWZrmk;    break;
1522     case X86::VMOVDQU32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1523     case X86::VMOVDQU32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1524     case X86::VMOVDQU32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1525     case X86::VMOVDQU64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1526     case X86::VMOVDQU64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1527     case X86::VMOVDQU64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1528     case X86::VMOVUPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1529     case X86::VMOVUPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1530     case X86::VMOVUPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1531     case X86::VMOVUPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1532     case X86::VMOVUPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1533     case X86::VMOVUPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1534     case X86::VMOVDQA32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1535     case X86::VMOVDQA32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1536     case X86::VMOVDQA32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1537     case X86::VMOVDQA64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1538     case X86::VMOVDQA64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1539     case X86::VMOVDQA64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1540     case X86::VMOVAPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1541     case X86::VMOVAPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1542     case X86::VMOVAPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1543     case X86::VMOVAPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1544     case X86::VMOVAPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1545     case X86::VMOVAPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1546     case X86::VBROADCASTSDZ256rmk: Opc = X86::VBLENDMPDZ256rmbk; break;
1547     case X86::VBROADCASTSDZrmk:    Opc = X86::VBLENDMPDZrmbk;    break;
1548     case X86::VBROADCASTSSZ128rmk: Opc = X86::VBLENDMPSZ128rmbk; break;
1549     case X86::VBROADCASTSSZ256rmk: Opc = X86::VBLENDMPSZ256rmbk; break;
1550     case X86::VBROADCASTSSZrmk:    Opc = X86::VBLENDMPSZrmbk;    break;
1551     case X86::VPBROADCASTDZ128rmk: Opc = X86::VPBLENDMDZ128rmbk; break;
1552     case X86::VPBROADCASTDZ256rmk: Opc = X86::VPBLENDMDZ256rmbk; break;
1553     case X86::VPBROADCASTDZrmk:    Opc = X86::VPBLENDMDZrmbk;    break;
1554     case X86::VPBROADCASTQZ128rmk: Opc = X86::VPBLENDMQZ128rmbk; break;
1555     case X86::VPBROADCASTQZ256rmk: Opc = X86::VPBLENDMQZ256rmbk; break;
1556     case X86::VPBROADCASTQZrmk:    Opc = X86::VPBLENDMQZrmbk;    break;
1557     }
1558 
1559     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1560               .add(Dest)
1561               .add(MI.getOperand(2))
1562               .add(Src)
1563               .add(MI.getOperand(3))
1564               .add(MI.getOperand(4))
1565               .add(MI.getOperand(5))
1566               .add(MI.getOperand(6))
1567               .add(MI.getOperand(7));
1568     break;
1569   }
1570 
1571   case X86::VMOVDQU8Z128rrk:
1572   case X86::VMOVDQU8Z256rrk:
1573   case X86::VMOVDQU8Zrrk:
1574   case X86::VMOVDQU16Z128rrk:
1575   case X86::VMOVDQU16Z256rrk:
1576   case X86::VMOVDQU16Zrrk:
1577   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1578   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1579   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
1580   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1581   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1582   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
1583   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
1584   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
1585   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
1586   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
1587   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
1588   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
1589     unsigned Opc;
1590     switch (MIOpc) {
1591     default: llvm_unreachable("Unreachable!");
1592     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
1593     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
1594     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
1595     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1596     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1597     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
1598     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1599     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1600     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1601     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1602     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1603     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1604     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1605     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1606     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1607     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1608     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1609     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1610     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1611     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1612     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1613     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1614     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1615     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1616     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1617     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1618     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1619     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1620     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1621     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1622     }
1623 
1624     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1625               .add(Dest)
1626               .add(MI.getOperand(2))
1627               .add(Src)
1628               .add(MI.getOperand(3));
1629     break;
1630   }
1631   }
1632 
1633   if (!NewMI) return nullptr;
1634 
1635   if (LV) {  // Update live variables
1636     if (Src.isKill())
1637       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1638     if (Dest.isDead())
1639       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1640   }
1641 
1642   MachineBasicBlock &MBB = *MI.getParent();
1643   MBB.insert(MI.getIterator(), NewMI); // Insert the new inst
1644 
1645   if (LIS) {
1646     LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
1647     if (SrcReg)
1648       LIS->getInterval(SrcReg);
1649     if (SrcReg2)
1650       LIS->getInterval(SrcReg2);
1651   }
1652 
1653   return NewMI;
1654 }
1655 
1656 /// This determines which of three possible cases of a three source commute
1657 /// the source indexes correspond to taking into account any mask operands.
1658 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1659 /// possible.
1660 /// Case 0 - Possible to commute the first and second operands.
1661 /// Case 1 - Possible to commute the first and third operands.
1662 /// Case 2 - Possible to commute the second and third operands.
1663 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1664                                        unsigned SrcOpIdx2) {
1665   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1666   if (SrcOpIdx1 > SrcOpIdx2)
1667     std::swap(SrcOpIdx1, SrcOpIdx2);
1668 
1669   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1670   if (X86II::isKMasked(TSFlags)) {
1671     Op2++;
1672     Op3++;
1673   }
1674 
1675   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1676     return 0;
1677   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1678     return 1;
1679   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1680     return 2;
1681   llvm_unreachable("Unknown three src commute case.");
1682 }
1683 
1684 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1685     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1686     const X86InstrFMA3Group &FMA3Group) const {
1687 
1688   unsigned Opc = MI.getOpcode();
1689 
1690   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1691   // analysis. The commute optimization is legal only if all users of FMA*_Int
1692   // use only the lowest element of the FMA*_Int instruction. Such analysis are
1693   // not implemented yet. So, just return 0 in that case.
1694   // When such analysis are available this place will be the right place for
1695   // calling it.
1696   assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1697          "Intrinsic instructions can't commute operand 1");
1698 
1699   // Determine which case this commute is or if it can't be done.
1700   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1701                                          SrcOpIdx2);
1702   assert(Case < 3 && "Unexpected case number!");
1703 
1704   // Define the FMA forms mapping array that helps to map input FMA form
1705   // to output FMA form to preserve the operation semantics after
1706   // commuting the operands.
1707   const unsigned Form132Index = 0;
1708   const unsigned Form213Index = 1;
1709   const unsigned Form231Index = 2;
1710   static const unsigned FormMapping[][3] = {
1711     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1712     // FMA132 A, C, b; ==> FMA231 C, A, b;
1713     // FMA213 B, A, c; ==> FMA213 A, B, c;
1714     // FMA231 C, A, b; ==> FMA132 A, C, b;
1715     { Form231Index, Form213Index, Form132Index },
1716     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1717     // FMA132 A, c, B; ==> FMA132 B, c, A;
1718     // FMA213 B, a, C; ==> FMA231 C, a, B;
1719     // FMA231 C, a, B; ==> FMA213 B, a, C;
1720     { Form132Index, Form231Index, Form213Index },
1721     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1722     // FMA132 a, C, B; ==> FMA213 a, B, C;
1723     // FMA213 b, A, C; ==> FMA132 b, C, A;
1724     // FMA231 c, A, B; ==> FMA231 c, B, A;
1725     { Form213Index, Form132Index, Form231Index }
1726   };
1727 
1728   unsigned FMAForms[3];
1729   FMAForms[0] = FMA3Group.get132Opcode();
1730   FMAForms[1] = FMA3Group.get213Opcode();
1731   FMAForms[2] = FMA3Group.get231Opcode();
1732 
1733   // Everything is ready, just adjust the FMA opcode and return it.
1734   for (unsigned FormIndex = 0; FormIndex < 3; FormIndex++)
1735     if (Opc == FMAForms[FormIndex])
1736       return FMAForms[FormMapping[Case][FormIndex]];
1737 
1738   llvm_unreachable("Illegal FMA3 format");
1739 }
1740 
1741 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1742                              unsigned SrcOpIdx2) {
1743   // Determine which case this commute is or if it can't be done.
1744   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1745                                          SrcOpIdx2);
1746   assert(Case < 3 && "Unexpected case value!");
1747 
1748   // For each case we need to swap two pairs of bits in the final immediate.
1749   static const uint8_t SwapMasks[3][4] = {
1750     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1751     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1752     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1753   };
1754 
1755   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1756   // Clear out the bits we are swapping.
1757   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1758                            SwapMasks[Case][2] | SwapMasks[Case][3]);
1759   // If the immediate had a bit of the pair set, then set the opposite bit.
1760   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1761   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1762   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1763   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1764   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1765 }
1766 
1767 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1768 // commuted.
1769 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1770 #define VPERM_CASES(Suffix) \
1771   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
1772   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
1773   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
1774   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
1775   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
1776   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
1777   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
1778   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
1779   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
1780   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
1781   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
1782   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
1783 
1784 #define VPERM_CASES_BROADCAST(Suffix) \
1785   VPERM_CASES(Suffix) \
1786   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
1787   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
1788   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
1789   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1790   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1791   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
1792 
1793   switch (Opcode) {
1794   default: return false;
1795   VPERM_CASES(B)
1796   VPERM_CASES_BROADCAST(D)
1797   VPERM_CASES_BROADCAST(PD)
1798   VPERM_CASES_BROADCAST(PS)
1799   VPERM_CASES_BROADCAST(Q)
1800   VPERM_CASES(W)
1801     return true;
1802   }
1803 #undef VPERM_CASES_BROADCAST
1804 #undef VPERM_CASES
1805 }
1806 
1807 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1808 // from the I opcode to the T opcode and vice versa.
1809 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1810 #define VPERM_CASES(Orig, New) \
1811   case X86::Orig##128rr:    return X86::New##128rr;   \
1812   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
1813   case X86::Orig##128rm:    return X86::New##128rm;   \
1814   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
1815   case X86::Orig##256rr:    return X86::New##256rr;   \
1816   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
1817   case X86::Orig##256rm:    return X86::New##256rm;   \
1818   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
1819   case X86::Orig##rr:       return X86::New##rr;      \
1820   case X86::Orig##rrkz:     return X86::New##rrkz;    \
1821   case X86::Orig##rm:       return X86::New##rm;      \
1822   case X86::Orig##rmkz:     return X86::New##rmkz;
1823 
1824 #define VPERM_CASES_BROADCAST(Orig, New) \
1825   VPERM_CASES(Orig, New) \
1826   case X86::Orig##128rmb:   return X86::New##128rmb;   \
1827   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1828   case X86::Orig##256rmb:   return X86::New##256rmb;   \
1829   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1830   case X86::Orig##rmb:      return X86::New##rmb;      \
1831   case X86::Orig##rmbkz:    return X86::New##rmbkz;
1832 
1833   switch (Opcode) {
1834   VPERM_CASES(VPERMI2B, VPERMT2B)
1835   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
1836   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1837   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1838   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
1839   VPERM_CASES(VPERMI2W, VPERMT2W)
1840   VPERM_CASES(VPERMT2B, VPERMI2B)
1841   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
1842   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1843   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1844   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
1845   VPERM_CASES(VPERMT2W, VPERMI2W)
1846   }
1847 
1848   llvm_unreachable("Unreachable!");
1849 #undef VPERM_CASES_BROADCAST
1850 #undef VPERM_CASES
1851 }
1852 
1853 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1854                                                    unsigned OpIdx1,
1855                                                    unsigned OpIdx2) const {
1856   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1857     if (NewMI)
1858       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1859     return MI;
1860   };
1861 
1862   switch (MI.getOpcode()) {
1863   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1864   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1865   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1866   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1867   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1868   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1869     unsigned Opc;
1870     unsigned Size;
1871     switch (MI.getOpcode()) {
1872     default: llvm_unreachable("Unreachable!");
1873     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1874     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1875     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1876     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1877     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1878     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1879     }
1880     unsigned Amt = MI.getOperand(3).getImm();
1881     auto &WorkingMI = cloneIfNew(MI);
1882     WorkingMI.setDesc(get(Opc));
1883     WorkingMI.getOperand(3).setImm(Size - Amt);
1884     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1885                                                    OpIdx1, OpIdx2);
1886   }
1887   case X86::PFSUBrr:
1888   case X86::PFSUBRrr: {
1889     // PFSUB  x, y: x = x - y
1890     // PFSUBR x, y: x = y - x
1891     unsigned Opc =
1892         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1893     auto &WorkingMI = cloneIfNew(MI);
1894     WorkingMI.setDesc(get(Opc));
1895     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1896                                                    OpIdx1, OpIdx2);
1897   }
1898   case X86::BLENDPDrri:
1899   case X86::BLENDPSrri:
1900   case X86::VBLENDPDrri:
1901   case X86::VBLENDPSrri:
1902     // If we're optimizing for size, try to use MOVSD/MOVSS.
1903     if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
1904       unsigned Mask, Opc;
1905       switch (MI.getOpcode()) {
1906       default: llvm_unreachable("Unreachable!");
1907       case X86::BLENDPDrri:  Opc = X86::MOVSDrr;  Mask = 0x03; break;
1908       case X86::BLENDPSrri:  Opc = X86::MOVSSrr;  Mask = 0x0F; break;
1909       case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1910       case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1911       }
1912       if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1913         auto &WorkingMI = cloneIfNew(MI);
1914         WorkingMI.setDesc(get(Opc));
1915         WorkingMI.removeOperand(3);
1916         return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1917                                                        /*NewMI=*/false,
1918                                                        OpIdx1, OpIdx2);
1919       }
1920     }
1921     LLVM_FALLTHROUGH;
1922   case X86::PBLENDWrri:
1923   case X86::VBLENDPDYrri:
1924   case X86::VBLENDPSYrri:
1925   case X86::VPBLENDDrri:
1926   case X86::VPBLENDWrri:
1927   case X86::VPBLENDDYrri:
1928   case X86::VPBLENDWYrri:{
1929     int8_t Mask;
1930     switch (MI.getOpcode()) {
1931     default: llvm_unreachable("Unreachable!");
1932     case X86::BLENDPDrri:    Mask = (int8_t)0x03; break;
1933     case X86::BLENDPSrri:    Mask = (int8_t)0x0F; break;
1934     case X86::PBLENDWrri:    Mask = (int8_t)0xFF; break;
1935     case X86::VBLENDPDrri:   Mask = (int8_t)0x03; break;
1936     case X86::VBLENDPSrri:   Mask = (int8_t)0x0F; break;
1937     case X86::VBLENDPDYrri:  Mask = (int8_t)0x0F; break;
1938     case X86::VBLENDPSYrri:  Mask = (int8_t)0xFF; break;
1939     case X86::VPBLENDDrri:   Mask = (int8_t)0x0F; break;
1940     case X86::VPBLENDWrri:   Mask = (int8_t)0xFF; break;
1941     case X86::VPBLENDDYrri:  Mask = (int8_t)0xFF; break;
1942     case X86::VPBLENDWYrri:  Mask = (int8_t)0xFF; break;
1943     }
1944     // Only the least significant bits of Imm are used.
1945     // Using int8_t to ensure it will be sign extended to the int64_t that
1946     // setImm takes in order to match isel behavior.
1947     int8_t Imm = MI.getOperand(3).getImm() & Mask;
1948     auto &WorkingMI = cloneIfNew(MI);
1949     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1950     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1951                                                    OpIdx1, OpIdx2);
1952   }
1953   case X86::INSERTPSrr:
1954   case X86::VINSERTPSrr:
1955   case X86::VINSERTPSZrr: {
1956     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
1957     unsigned ZMask = Imm & 15;
1958     unsigned DstIdx = (Imm >> 4) & 3;
1959     unsigned SrcIdx = (Imm >> 6) & 3;
1960 
1961     // We can commute insertps if we zero 2 of the elements, the insertion is
1962     // "inline" and we don't override the insertion with a zero.
1963     if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
1964         countPopulation(ZMask) == 2) {
1965       unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
1966       assert(AltIdx < 4 && "Illegal insertion index");
1967       unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
1968       auto &WorkingMI = cloneIfNew(MI);
1969       WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
1970       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1971                                                      OpIdx1, OpIdx2);
1972     }
1973     return nullptr;
1974   }
1975   case X86::MOVSDrr:
1976   case X86::MOVSSrr:
1977   case X86::VMOVSDrr:
1978   case X86::VMOVSSrr:{
1979     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1980     if (Subtarget.hasSSE41()) {
1981       unsigned Mask, Opc;
1982       switch (MI.getOpcode()) {
1983       default: llvm_unreachable("Unreachable!");
1984       case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
1985       case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
1986       case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1987       case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1988       }
1989 
1990       auto &WorkingMI = cloneIfNew(MI);
1991       WorkingMI.setDesc(get(Opc));
1992       WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1993       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1994                                                      OpIdx1, OpIdx2);
1995     }
1996 
1997     // Convert to SHUFPD.
1998     assert(MI.getOpcode() == X86::MOVSDrr &&
1999            "Can only commute MOVSDrr without SSE4.1");
2000 
2001     auto &WorkingMI = cloneIfNew(MI);
2002     WorkingMI.setDesc(get(X86::SHUFPDrri));
2003     WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2004     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2005                                                    OpIdx1, OpIdx2);
2006   }
2007   case X86::SHUFPDrri: {
2008     // Commute to MOVSD.
2009     assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
2010     auto &WorkingMI = cloneIfNew(MI);
2011     WorkingMI.setDesc(get(X86::MOVSDrr));
2012     WorkingMI.removeOperand(3);
2013     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2014                                                    OpIdx1, OpIdx2);
2015   }
2016   case X86::PCLMULQDQrr:
2017   case X86::VPCLMULQDQrr:
2018   case X86::VPCLMULQDQYrr:
2019   case X86::VPCLMULQDQZrr:
2020   case X86::VPCLMULQDQZ128rr:
2021   case X86::VPCLMULQDQZ256rr: {
2022     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2023     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2024     unsigned Imm = MI.getOperand(3).getImm();
2025     unsigned Src1Hi = Imm & 0x01;
2026     unsigned Src2Hi = Imm & 0x10;
2027     auto &WorkingMI = cloneIfNew(MI);
2028     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2029     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2030                                                    OpIdx1, OpIdx2);
2031   }
2032   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
2033   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
2034   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
2035   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
2036   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
2037   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
2038   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
2039   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
2040   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
2041   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
2042   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
2043   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
2044   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
2045   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
2046   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
2047   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
2048   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
2049   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
2050   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
2051   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
2052   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
2053   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
2054   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
2055   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
2056     // Flip comparison mode immediate (if necessary).
2057     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
2058     Imm = X86::getSwappedVPCMPImm(Imm);
2059     auto &WorkingMI = cloneIfNew(MI);
2060     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
2061     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2062                                                    OpIdx1, OpIdx2);
2063   }
2064   case X86::VPCOMBri: case X86::VPCOMUBri:
2065   case X86::VPCOMDri: case X86::VPCOMUDri:
2066   case X86::VPCOMQri: case X86::VPCOMUQri:
2067   case X86::VPCOMWri: case X86::VPCOMUWri: {
2068     // Flip comparison mode immediate (if necessary).
2069     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
2070     Imm = X86::getSwappedVPCOMImm(Imm);
2071     auto &WorkingMI = cloneIfNew(MI);
2072     WorkingMI.getOperand(3).setImm(Imm);
2073     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2074                                                    OpIdx1, OpIdx2);
2075   }
2076   case X86::VCMPSDZrr:
2077   case X86::VCMPSSZrr:
2078   case X86::VCMPPDZrri:
2079   case X86::VCMPPSZrri:
2080   case X86::VCMPSHZrr:
2081   case X86::VCMPPHZrri:
2082   case X86::VCMPPHZ128rri:
2083   case X86::VCMPPHZ256rri:
2084   case X86::VCMPPDZ128rri:
2085   case X86::VCMPPSZ128rri:
2086   case X86::VCMPPDZ256rri:
2087   case X86::VCMPPSZ256rri:
2088   case X86::VCMPPDZrrik:
2089   case X86::VCMPPSZrrik:
2090   case X86::VCMPPDZ128rrik:
2091   case X86::VCMPPSZ128rrik:
2092   case X86::VCMPPDZ256rrik:
2093   case X86::VCMPPSZ256rrik: {
2094     unsigned Imm =
2095                 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f;
2096     Imm = X86::getSwappedVCMPImm(Imm);
2097     auto &WorkingMI = cloneIfNew(MI);
2098     WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm);
2099     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2100                                                    OpIdx1, OpIdx2);
2101   }
2102   case X86::VPERM2F128rr:
2103   case X86::VPERM2I128rr: {
2104     // Flip permute source immediate.
2105     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2106     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2107     int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
2108     auto &WorkingMI = cloneIfNew(MI);
2109     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
2110     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2111                                                    OpIdx1, OpIdx2);
2112   }
2113   case X86::MOVHLPSrr:
2114   case X86::UNPCKHPDrr:
2115   case X86::VMOVHLPSrr:
2116   case X86::VUNPCKHPDrr:
2117   case X86::VMOVHLPSZrr:
2118   case X86::VUNPCKHPDZ128rr: {
2119     assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
2120 
2121     unsigned Opc = MI.getOpcode();
2122     switch (Opc) {
2123     default: llvm_unreachable("Unreachable!");
2124     case X86::MOVHLPSrr:       Opc = X86::UNPCKHPDrr;      break;
2125     case X86::UNPCKHPDrr:      Opc = X86::MOVHLPSrr;       break;
2126     case X86::VMOVHLPSrr:      Opc = X86::VUNPCKHPDrr;     break;
2127     case X86::VUNPCKHPDrr:     Opc = X86::VMOVHLPSrr;      break;
2128     case X86::VMOVHLPSZrr:     Opc = X86::VUNPCKHPDZ128rr; break;
2129     case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr;     break;
2130     }
2131     auto &WorkingMI = cloneIfNew(MI);
2132     WorkingMI.setDesc(get(Opc));
2133     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2134                                                    OpIdx1, OpIdx2);
2135   }
2136   case X86::CMOV16rr:  case X86::CMOV32rr:  case X86::CMOV64rr: {
2137     auto &WorkingMI = cloneIfNew(MI);
2138     unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2139     X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
2140     WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2141     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2142                                                    OpIdx1, OpIdx2);
2143   }
2144   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2145   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2146   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2147   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2148   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2149   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2150   case X86::VPTERNLOGDZrrik:
2151   case X86::VPTERNLOGDZ128rrik:
2152   case X86::VPTERNLOGDZ256rrik:
2153   case X86::VPTERNLOGQZrrik:
2154   case X86::VPTERNLOGQZ128rrik:
2155   case X86::VPTERNLOGQZ256rrik:
2156   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2157   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2158   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2159   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2160   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2161   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2162   case X86::VPTERNLOGDZ128rmbi:
2163   case X86::VPTERNLOGDZ256rmbi:
2164   case X86::VPTERNLOGDZrmbi:
2165   case X86::VPTERNLOGQZ128rmbi:
2166   case X86::VPTERNLOGQZ256rmbi:
2167   case X86::VPTERNLOGQZrmbi:
2168   case X86::VPTERNLOGDZ128rmbikz:
2169   case X86::VPTERNLOGDZ256rmbikz:
2170   case X86::VPTERNLOGDZrmbikz:
2171   case X86::VPTERNLOGQZ128rmbikz:
2172   case X86::VPTERNLOGQZ256rmbikz:
2173   case X86::VPTERNLOGQZrmbikz: {
2174     auto &WorkingMI = cloneIfNew(MI);
2175     commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
2176     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2177                                                    OpIdx1, OpIdx2);
2178   }
2179   default: {
2180     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
2181       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
2182       auto &WorkingMI = cloneIfNew(MI);
2183       WorkingMI.setDesc(get(Opc));
2184       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2185                                                      OpIdx1, OpIdx2);
2186     }
2187 
2188     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2189                                                       MI.getDesc().TSFlags);
2190     if (FMA3Group) {
2191       unsigned Opc =
2192         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
2193       auto &WorkingMI = cloneIfNew(MI);
2194       WorkingMI.setDesc(get(Opc));
2195       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2196                                                      OpIdx1, OpIdx2);
2197     }
2198 
2199     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2200   }
2201   }
2202 }
2203 
2204 bool
2205 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2206                                             unsigned &SrcOpIdx1,
2207                                             unsigned &SrcOpIdx2,
2208                                             bool IsIntrinsic) const {
2209   uint64_t TSFlags = MI.getDesc().TSFlags;
2210 
2211   unsigned FirstCommutableVecOp = 1;
2212   unsigned LastCommutableVecOp = 3;
2213   unsigned KMaskOp = -1U;
2214   if (X86II::isKMasked(TSFlags)) {
2215     // For k-zero-masked operations it is Ok to commute the first vector
2216     // operand. Unless this is an intrinsic instruction.
2217     // For regular k-masked operations a conservative choice is done as the
2218     // elements of the first vector operand, for which the corresponding bit
2219     // in the k-mask operand is set to 0, are copied to the result of the
2220     // instruction.
2221     // TODO/FIXME: The commute still may be legal if it is known that the
2222     // k-mask operand is set to either all ones or all zeroes.
2223     // It is also Ok to commute the 1st operand if all users of MI use only
2224     // the elements enabled by the k-mask operand. For example,
2225     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2226     //                                                     : v1[i];
2227     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2228     //                                  // Ok, to commute v1 in FMADD213PSZrk.
2229 
2230     // The k-mask operand has index = 2 for masked and zero-masked operations.
2231     KMaskOp = 2;
2232 
2233     // The operand with index = 1 is used as a source for those elements for
2234     // which the corresponding bit in the k-mask is set to 0.
2235     if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2236       FirstCommutableVecOp = 3;
2237 
2238     LastCommutableVecOp++;
2239   } else if (IsIntrinsic) {
2240     // Commuting the first operand of an intrinsic instruction isn't possible
2241     // unless we can prove that only the lowest element of the result is used.
2242     FirstCommutableVecOp = 2;
2243   }
2244 
2245   if (isMem(MI, LastCommutableVecOp))
2246     LastCommutableVecOp--;
2247 
2248   // Only the first RegOpsNum operands are commutable.
2249   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2250   // that the operand is not specified/fixed.
2251   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2252       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2253        SrcOpIdx1 == KMaskOp))
2254     return false;
2255   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2256       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2257        SrcOpIdx2 == KMaskOp))
2258     return false;
2259 
2260   // Look for two different register operands assumed to be commutable
2261   // regardless of the FMA opcode. The FMA opcode is adjusted later.
2262   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2263       SrcOpIdx2 == CommuteAnyOperandIndex) {
2264     unsigned CommutableOpIdx2 = SrcOpIdx2;
2265 
2266     // At least one of operands to be commuted is not specified and
2267     // this method is free to choose appropriate commutable operands.
2268     if (SrcOpIdx1 == SrcOpIdx2)
2269       // Both of operands are not fixed. By default set one of commutable
2270       // operands to the last register operand of the instruction.
2271       CommutableOpIdx2 = LastCommutableVecOp;
2272     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2273       // Only one of operands is not fixed.
2274       CommutableOpIdx2 = SrcOpIdx1;
2275 
2276     // CommutableOpIdx2 is well defined now. Let's choose another commutable
2277     // operand and assign its index to CommutableOpIdx1.
2278     Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
2279 
2280     unsigned CommutableOpIdx1;
2281     for (CommutableOpIdx1 = LastCommutableVecOp;
2282          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2283       // Just ignore and skip the k-mask operand.
2284       if (CommutableOpIdx1 == KMaskOp)
2285         continue;
2286 
2287       // The commuted operands must have different registers.
2288       // Otherwise, the commute transformation does not change anything and
2289       // is useless then.
2290       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
2291         break;
2292     }
2293 
2294     // No appropriate commutable operands were found.
2295     if (CommutableOpIdx1 < FirstCommutableVecOp)
2296       return false;
2297 
2298     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2299     // to return those values.
2300     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2301                               CommutableOpIdx1, CommutableOpIdx2))
2302       return false;
2303   }
2304 
2305   return true;
2306 }
2307 
2308 bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2309                                          unsigned &SrcOpIdx1,
2310                                          unsigned &SrcOpIdx2) const {
2311   const MCInstrDesc &Desc = MI.getDesc();
2312   if (!Desc.isCommutable())
2313     return false;
2314 
2315   switch (MI.getOpcode()) {
2316   case X86::CMPSDrr:
2317   case X86::CMPSSrr:
2318   case X86::CMPPDrri:
2319   case X86::CMPPSrri:
2320   case X86::VCMPSDrr:
2321   case X86::VCMPSSrr:
2322   case X86::VCMPPDrri:
2323   case X86::VCMPPSrri:
2324   case X86::VCMPPDYrri:
2325   case X86::VCMPPSYrri:
2326   case X86::VCMPSDZrr:
2327   case X86::VCMPSSZrr:
2328   case X86::VCMPPDZrri:
2329   case X86::VCMPPSZrri:
2330   case X86::VCMPSHZrr:
2331   case X86::VCMPPHZrri:
2332   case X86::VCMPPHZ128rri:
2333   case X86::VCMPPHZ256rri:
2334   case X86::VCMPPDZ128rri:
2335   case X86::VCMPPSZ128rri:
2336   case X86::VCMPPDZ256rri:
2337   case X86::VCMPPSZ256rri:
2338   case X86::VCMPPDZrrik:
2339   case X86::VCMPPSZrrik:
2340   case X86::VCMPPDZ128rrik:
2341   case X86::VCMPPSZ128rrik:
2342   case X86::VCMPPDZ256rrik:
2343   case X86::VCMPPSZ256rrik: {
2344     unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2345 
2346     // Float comparison can be safely commuted for
2347     // Ordered/Unordered/Equal/NotEqual tests
2348     unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2349     switch (Imm) {
2350     default:
2351       // EVEX versions can be commuted.
2352       if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2353         break;
2354       return false;
2355     case 0x00: // EQUAL
2356     case 0x03: // UNORDERED
2357     case 0x04: // NOT EQUAL
2358     case 0x07: // ORDERED
2359       break;
2360     }
2361 
2362     // The indices of the commutable operands are 1 and 2 (or 2 and 3
2363     // when masked).
2364     // Assign them to the returned operand indices here.
2365     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2366                                 2 + OpOffset);
2367   }
2368   case X86::MOVSSrr:
2369     // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2370     // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2371     // AVX implies sse4.1.
2372     if (Subtarget.hasSSE41())
2373       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2374     return false;
2375   case X86::SHUFPDrri:
2376     // We can commute this to MOVSD.
2377     if (MI.getOperand(3).getImm() == 0x02)
2378       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2379     return false;
2380   case X86::MOVHLPSrr:
2381   case X86::UNPCKHPDrr:
2382   case X86::VMOVHLPSrr:
2383   case X86::VUNPCKHPDrr:
2384   case X86::VMOVHLPSZrr:
2385   case X86::VUNPCKHPDZ128rr:
2386     if (Subtarget.hasSSE2())
2387       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2388     return false;
2389   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2390   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2391   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2392   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2393   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2394   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2395   case X86::VPTERNLOGDZrrik:
2396   case X86::VPTERNLOGDZ128rrik:
2397   case X86::VPTERNLOGDZ256rrik:
2398   case X86::VPTERNLOGQZrrik:
2399   case X86::VPTERNLOGQZ128rrik:
2400   case X86::VPTERNLOGQZ256rrik:
2401   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2402   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2403   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2404   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2405   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2406   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2407   case X86::VPTERNLOGDZ128rmbi:
2408   case X86::VPTERNLOGDZ256rmbi:
2409   case X86::VPTERNLOGDZrmbi:
2410   case X86::VPTERNLOGQZ128rmbi:
2411   case X86::VPTERNLOGQZ256rmbi:
2412   case X86::VPTERNLOGQZrmbi:
2413   case X86::VPTERNLOGDZ128rmbikz:
2414   case X86::VPTERNLOGDZ256rmbikz:
2415   case X86::VPTERNLOGDZrmbikz:
2416   case X86::VPTERNLOGQZ128rmbikz:
2417   case X86::VPTERNLOGQZ256rmbikz:
2418   case X86::VPTERNLOGQZrmbikz:
2419     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2420   case X86::VPDPWSSDYrr:
2421   case X86::VPDPWSSDrr:
2422   case X86::VPDPWSSDSYrr:
2423   case X86::VPDPWSSDSrr:
2424   case X86::VPDPWSSDZ128r:
2425   case X86::VPDPWSSDZ128rk:
2426   case X86::VPDPWSSDZ128rkz:
2427   case X86::VPDPWSSDZ256r:
2428   case X86::VPDPWSSDZ256rk:
2429   case X86::VPDPWSSDZ256rkz:
2430   case X86::VPDPWSSDZr:
2431   case X86::VPDPWSSDZrk:
2432   case X86::VPDPWSSDZrkz:
2433   case X86::VPDPWSSDSZ128r:
2434   case X86::VPDPWSSDSZ128rk:
2435   case X86::VPDPWSSDSZ128rkz:
2436   case X86::VPDPWSSDSZ256r:
2437   case X86::VPDPWSSDSZ256rk:
2438   case X86::VPDPWSSDSZ256rkz:
2439   case X86::VPDPWSSDSZr:
2440   case X86::VPDPWSSDSZrk:
2441   case X86::VPDPWSSDSZrkz:
2442   case X86::VPMADD52HUQZ128r:
2443   case X86::VPMADD52HUQZ128rk:
2444   case X86::VPMADD52HUQZ128rkz:
2445   case X86::VPMADD52HUQZ256r:
2446   case X86::VPMADD52HUQZ256rk:
2447   case X86::VPMADD52HUQZ256rkz:
2448   case X86::VPMADD52HUQZr:
2449   case X86::VPMADD52HUQZrk:
2450   case X86::VPMADD52HUQZrkz:
2451   case X86::VPMADD52LUQZ128r:
2452   case X86::VPMADD52LUQZ128rk:
2453   case X86::VPMADD52LUQZ128rkz:
2454   case X86::VPMADD52LUQZ256r:
2455   case X86::VPMADD52LUQZ256rk:
2456   case X86::VPMADD52LUQZ256rkz:
2457   case X86::VPMADD52LUQZr:
2458   case X86::VPMADD52LUQZrk:
2459   case X86::VPMADD52LUQZrkz:
2460   case X86::VFMADDCPHZr:
2461   case X86::VFMADDCPHZrk:
2462   case X86::VFMADDCPHZrkz:
2463   case X86::VFMADDCPHZ128r:
2464   case X86::VFMADDCPHZ128rk:
2465   case X86::VFMADDCPHZ128rkz:
2466   case X86::VFMADDCPHZ256r:
2467   case X86::VFMADDCPHZ256rk:
2468   case X86::VFMADDCPHZ256rkz:
2469   case X86::VFMADDCSHZr:
2470   case X86::VFMADDCSHZrk:
2471   case X86::VFMADDCSHZrkz: {
2472     unsigned CommutableOpIdx1 = 2;
2473     unsigned CommutableOpIdx2 = 3;
2474     if (X86II::isKMasked(Desc.TSFlags)) {
2475       // Skip the mask register.
2476       ++CommutableOpIdx1;
2477       ++CommutableOpIdx2;
2478     }
2479     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2480                               CommutableOpIdx1, CommutableOpIdx2))
2481       return false;
2482     if (!MI.getOperand(SrcOpIdx1).isReg() ||
2483         !MI.getOperand(SrcOpIdx2).isReg())
2484       // No idea.
2485       return false;
2486     return true;
2487   }
2488 
2489   default:
2490     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2491                                                       MI.getDesc().TSFlags);
2492     if (FMA3Group)
2493       return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2494                                            FMA3Group->isIntrinsic());
2495 
2496     // Handled masked instructions since we need to skip over the mask input
2497     // and the preserved input.
2498     if (X86II::isKMasked(Desc.TSFlags)) {
2499       // First assume that the first input is the mask operand and skip past it.
2500       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2501       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2502       // Check if the first input is tied. If there isn't one then we only
2503       // need to skip the mask operand which we did above.
2504       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2505                                              MCOI::TIED_TO) != -1)) {
2506         // If this is zero masking instruction with a tied operand, we need to
2507         // move the first index back to the first input since this must
2508         // be a 3 input instruction and we want the first two non-mask inputs.
2509         // Otherwise this is a 2 input instruction with a preserved input and
2510         // mask, so we need to move the indices to skip one more input.
2511         if (X86II::isKMergeMasked(Desc.TSFlags)) {
2512           ++CommutableOpIdx1;
2513           ++CommutableOpIdx2;
2514         } else {
2515           --CommutableOpIdx1;
2516         }
2517       }
2518 
2519       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2520                                 CommutableOpIdx1, CommutableOpIdx2))
2521         return false;
2522 
2523       if (!MI.getOperand(SrcOpIdx1).isReg() ||
2524           !MI.getOperand(SrcOpIdx2).isReg())
2525         // No idea.
2526         return false;
2527       return true;
2528     }
2529 
2530     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2531   }
2532   return false;
2533 }
2534 
2535 static bool isConvertibleLEA(MachineInstr *MI) {
2536   unsigned Opcode = MI->getOpcode();
2537   if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
2538       Opcode != X86::LEA64_32r)
2539     return false;
2540 
2541   const MachineOperand &Scale = MI->getOperand(1 + X86::AddrScaleAmt);
2542   const MachineOperand &Disp = MI->getOperand(1 + X86::AddrDisp);
2543   const MachineOperand &Segment = MI->getOperand(1 + X86::AddrSegmentReg);
2544 
2545   if (Segment.getReg() != 0 || !Disp.isImm() || Disp.getImm() != 0 ||
2546       Scale.getImm() > 1)
2547     return false;
2548 
2549   return true;
2550 }
2551 
2552 bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
2553   // Currently we're interested in following sequence only.
2554   //   r3 = lea r1, r2
2555   //   r5 = add r3, r4
2556   // Both r3 and r4 are killed in add, we hope the add instruction has the
2557   // operand order
2558   //   r5 = add r4, r3
2559   // So later in X86FixupLEAs the lea instruction can be rewritten as add.
2560   unsigned Opcode = MI.getOpcode();
2561   if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
2562     return false;
2563 
2564   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2565   Register Reg1 = MI.getOperand(1).getReg();
2566   Register Reg2 = MI.getOperand(2).getReg();
2567 
2568   // Check if Reg1 comes from LEA in the same MBB.
2569   if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg1)) {
2570     if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2571       Commute = true;
2572       return true;
2573     }
2574   }
2575 
2576   // Check if Reg2 comes from LEA in the same MBB.
2577   if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg2)) {
2578     if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2579       Commute = false;
2580       return true;
2581     }
2582   }
2583 
2584   return false;
2585 }
2586 
2587 int X86::getCondSrcNoFromDesc(const MCInstrDesc &MCID) {
2588   unsigned Opcode = MCID.getOpcode();
2589   if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isCMOVCC(Opcode)))
2590     return -1;
2591   // Assume that condition code is always the last use operand.
2592   unsigned NumUses = MCID.getNumOperands() - MCID.getNumDefs();
2593   return NumUses - 1;
2594 }
2595 
2596 X86::CondCode X86::getCondFromMI(const MachineInstr &MI) {
2597   const MCInstrDesc &MCID = MI.getDesc();
2598   int CondNo = getCondSrcNoFromDesc(MCID);
2599   if (CondNo < 0)
2600     return X86::COND_INVALID;
2601   CondNo += MCID.getNumDefs();
2602   return static_cast<X86::CondCode>(MI.getOperand(CondNo).getImm());
2603 }
2604 
2605 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2606   return X86::isJCC(MI.getOpcode()) ? X86::getCondFromMI(MI)
2607                                     : X86::COND_INVALID;
2608 }
2609 
2610 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2611   return X86::isSETCC(MI.getOpcode()) ? X86::getCondFromMI(MI)
2612                                       : X86::COND_INVALID;
2613 }
2614 
2615 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2616   return X86::isCMOVCC(MI.getOpcode()) ? X86::getCondFromMI(MI)
2617                                        : X86::COND_INVALID;
2618 }
2619 
2620 /// Return the inverse of the specified condition,
2621 /// e.g. turning COND_E to COND_NE.
2622 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2623   switch (CC) {
2624   default: llvm_unreachable("Illegal condition code!");
2625   case X86::COND_E:  return X86::COND_NE;
2626   case X86::COND_NE: return X86::COND_E;
2627   case X86::COND_L:  return X86::COND_GE;
2628   case X86::COND_LE: return X86::COND_G;
2629   case X86::COND_G:  return X86::COND_LE;
2630   case X86::COND_GE: return X86::COND_L;
2631   case X86::COND_B:  return X86::COND_AE;
2632   case X86::COND_BE: return X86::COND_A;
2633   case X86::COND_A:  return X86::COND_BE;
2634   case X86::COND_AE: return X86::COND_B;
2635   case X86::COND_S:  return X86::COND_NS;
2636   case X86::COND_NS: return X86::COND_S;
2637   case X86::COND_P:  return X86::COND_NP;
2638   case X86::COND_NP: return X86::COND_P;
2639   case X86::COND_O:  return X86::COND_NO;
2640   case X86::COND_NO: return X86::COND_O;
2641   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
2642   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2643   }
2644 }
2645 
2646 /// Assuming the flags are set by MI(a,b), return the condition code if we
2647 /// modify the instructions such that flags are set by MI(b,a).
2648 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2649   switch (CC) {
2650   default: return X86::COND_INVALID;
2651   case X86::COND_E:  return X86::COND_E;
2652   case X86::COND_NE: return X86::COND_NE;
2653   case X86::COND_L:  return X86::COND_G;
2654   case X86::COND_LE: return X86::COND_GE;
2655   case X86::COND_G:  return X86::COND_L;
2656   case X86::COND_GE: return X86::COND_LE;
2657   case X86::COND_B:  return X86::COND_A;
2658   case X86::COND_BE: return X86::COND_AE;
2659   case X86::COND_A:  return X86::COND_B;
2660   case X86::COND_AE: return X86::COND_BE;
2661   }
2662 }
2663 
2664 std::pair<X86::CondCode, bool>
2665 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2666   X86::CondCode CC = X86::COND_INVALID;
2667   bool NeedSwap = false;
2668   switch (Predicate) {
2669   default: break;
2670   // Floating-point Predicates
2671   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
2672   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
2673   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
2674   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
2675   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
2676   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
2677   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
2678   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
2679   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
2680   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
2681   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
2682   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
2683   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
2684   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2685 
2686   // Integer Predicates
2687   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
2688   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
2689   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
2690   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
2691   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
2692   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
2693   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
2694   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
2695   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
2696   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
2697   }
2698 
2699   return std::make_pair(CC, NeedSwap);
2700 }
2701 
2702 /// Return a cmov opcode for the given register size in bytes, and operand type.
2703 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2704   switch(RegBytes) {
2705   default: llvm_unreachable("Illegal register size!");
2706   case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2707   case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2708   case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr;
2709   }
2710 }
2711 
2712 /// Get the VPCMP immediate for the given condition.
2713 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2714   switch (CC) {
2715   default: llvm_unreachable("Unexpected SETCC condition");
2716   case ISD::SETNE:  return 4;
2717   case ISD::SETEQ:  return 0;
2718   case ISD::SETULT:
2719   case ISD::SETLT: return 1;
2720   case ISD::SETUGT:
2721   case ISD::SETGT: return 6;
2722   case ISD::SETUGE:
2723   case ISD::SETGE: return 5;
2724   case ISD::SETULE:
2725   case ISD::SETLE: return 2;
2726   }
2727 }
2728 
2729 /// Get the VPCMP immediate if the operands are swapped.
2730 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2731   switch (Imm) {
2732   default: llvm_unreachable("Unreachable!");
2733   case 0x01: Imm = 0x06; break; // LT  -> NLE
2734   case 0x02: Imm = 0x05; break; // LE  -> NLT
2735   case 0x05: Imm = 0x02; break; // NLT -> LE
2736   case 0x06: Imm = 0x01; break; // NLE -> LT
2737   case 0x00: // EQ
2738   case 0x03: // FALSE
2739   case 0x04: // NE
2740   case 0x07: // TRUE
2741     break;
2742   }
2743 
2744   return Imm;
2745 }
2746 
2747 /// Get the VPCOM immediate if the operands are swapped.
2748 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2749   switch (Imm) {
2750   default: llvm_unreachable("Unreachable!");
2751   case 0x00: Imm = 0x02; break; // LT -> GT
2752   case 0x01: Imm = 0x03; break; // LE -> GE
2753   case 0x02: Imm = 0x00; break; // GT -> LT
2754   case 0x03: Imm = 0x01; break; // GE -> LE
2755   case 0x04: // EQ
2756   case 0x05: // NE
2757   case 0x06: // FALSE
2758   case 0x07: // TRUE
2759     break;
2760   }
2761 
2762   return Imm;
2763 }
2764 
2765 /// Get the VCMP immediate if the operands are swapped.
2766 unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2767   // Only need the lower 2 bits to distinquish.
2768   switch (Imm & 0x3) {
2769   default: llvm_unreachable("Unreachable!");
2770   case 0x00: case 0x03:
2771     // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2772     break;
2773   case 0x01: case 0x02:
2774     // Need to toggle bits 3:0. Bit 4 stays the same.
2775     Imm ^= 0xf;
2776     break;
2777   }
2778 
2779   return Imm;
2780 }
2781 
2782 /// Return true if the Reg is X87 register.
2783 static bool isX87Reg(unsigned Reg) {
2784   return (Reg == X86::FPCW || Reg == X86::FPSW ||
2785           (Reg >= X86::ST0 && Reg <= X86::ST7));
2786 }
2787 
2788 /// check if the instruction is X87 instruction
2789 bool X86::isX87Instruction(MachineInstr &MI) {
2790   for (const MachineOperand &MO : MI.operands()) {
2791     if (!MO.isReg())
2792       continue;
2793     if (isX87Reg(MO.getReg()))
2794       return true;
2795   }
2796   return false;
2797 }
2798 
2799 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2800   switch (MI.getOpcode()) {
2801   case X86::TCRETURNdi:
2802   case X86::TCRETURNri:
2803   case X86::TCRETURNmi:
2804   case X86::TCRETURNdi64:
2805   case X86::TCRETURNri64:
2806   case X86::TCRETURNmi64:
2807     return true;
2808   default:
2809     return false;
2810   }
2811 }
2812 
2813 bool X86InstrInfo::canMakeTailCallConditional(
2814     SmallVectorImpl<MachineOperand> &BranchCond,
2815     const MachineInstr &TailCall) const {
2816   if (TailCall.getOpcode() != X86::TCRETURNdi &&
2817       TailCall.getOpcode() != X86::TCRETURNdi64) {
2818     // Only direct calls can be done with a conditional branch.
2819     return false;
2820   }
2821 
2822   const MachineFunction *MF = TailCall.getParent()->getParent();
2823   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2824     // Conditional tail calls confuse the Win64 unwinder.
2825     return false;
2826   }
2827 
2828   assert(BranchCond.size() == 1);
2829   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2830     // Can't make a conditional tail call with this condition.
2831     return false;
2832   }
2833 
2834   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2835   if (X86FI->getTCReturnAddrDelta() != 0 ||
2836       TailCall.getOperand(1).getImm() != 0) {
2837     // A conditional tail call cannot do any stack adjustment.
2838     return false;
2839   }
2840 
2841   return true;
2842 }
2843 
2844 void X86InstrInfo::replaceBranchWithTailCall(
2845     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2846     const MachineInstr &TailCall) const {
2847   assert(canMakeTailCallConditional(BranchCond, TailCall));
2848 
2849   MachineBasicBlock::iterator I = MBB.end();
2850   while (I != MBB.begin()) {
2851     --I;
2852     if (I->isDebugInstr())
2853       continue;
2854     if (!I->isBranch())
2855       assert(0 && "Can't find the branch to replace!");
2856 
2857     X86::CondCode CC = X86::getCondFromBranch(*I);
2858     assert(BranchCond.size() == 1);
2859     if (CC != BranchCond[0].getImm())
2860       continue;
2861 
2862     break;
2863   }
2864 
2865   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2866                                                          : X86::TCRETURNdi64cc;
2867 
2868   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2869   MIB->addOperand(TailCall.getOperand(0)); // Destination.
2870   MIB.addImm(0); // Stack offset (not used).
2871   MIB->addOperand(BranchCond[0]); // Condition.
2872   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2873 
2874   // Add implicit uses and defs of all live regs potentially clobbered by the
2875   // call. This way they still appear live across the call.
2876   LivePhysRegs LiveRegs(getRegisterInfo());
2877   LiveRegs.addLiveOuts(MBB);
2878   SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2879   LiveRegs.stepForward(*MIB, Clobbers);
2880   for (const auto &C : Clobbers) {
2881     MIB.addReg(C.first, RegState::Implicit);
2882     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2883   }
2884 
2885   I->eraseFromParent();
2886 }
2887 
2888 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2889 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2890 // fallthrough MBB cannot be identified.
2891 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2892                                             MachineBasicBlock *TBB) {
2893   // Look for non-EHPad successors other than TBB. If we find exactly one, it
2894   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2895   // and fallthrough MBB. If we find more than one, we cannot identify the
2896   // fallthrough MBB and should return nullptr.
2897   MachineBasicBlock *FallthroughBB = nullptr;
2898   for (MachineBasicBlock *Succ : MBB->successors()) {
2899     if (Succ->isEHPad() || (Succ == TBB && FallthroughBB))
2900       continue;
2901     // Return a nullptr if we found more than one fallthrough successor.
2902     if (FallthroughBB && FallthroughBB != TBB)
2903       return nullptr;
2904     FallthroughBB = Succ;
2905   }
2906   return FallthroughBB;
2907 }
2908 
2909 bool X86InstrInfo::AnalyzeBranchImpl(
2910     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2911     SmallVectorImpl<MachineOperand> &Cond,
2912     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2913 
2914   // Start from the bottom of the block and work up, examining the
2915   // terminator instructions.
2916   MachineBasicBlock::iterator I = MBB.end();
2917   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2918   while (I != MBB.begin()) {
2919     --I;
2920     if (I->isDebugInstr())
2921       continue;
2922 
2923     // Working from the bottom, when we see a non-terminator instruction, we're
2924     // done.
2925     if (!isUnpredicatedTerminator(*I))
2926       break;
2927 
2928     // A terminator that isn't a branch can't easily be handled by this
2929     // analysis.
2930     if (!I->isBranch())
2931       return true;
2932 
2933     // Handle unconditional branches.
2934     if (I->getOpcode() == X86::JMP_1) {
2935       UnCondBrIter = I;
2936 
2937       if (!AllowModify) {
2938         TBB = I->getOperand(0).getMBB();
2939         continue;
2940       }
2941 
2942       // If the block has any instructions after a JMP, delete them.
2943       while (std::next(I) != MBB.end())
2944         std::next(I)->eraseFromParent();
2945 
2946       Cond.clear();
2947       FBB = nullptr;
2948 
2949       // Delete the JMP if it's equivalent to a fall-through.
2950       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2951         TBB = nullptr;
2952         I->eraseFromParent();
2953         I = MBB.end();
2954         UnCondBrIter = MBB.end();
2955         continue;
2956       }
2957 
2958       // TBB is used to indicate the unconditional destination.
2959       TBB = I->getOperand(0).getMBB();
2960       continue;
2961     }
2962 
2963     // Handle conditional branches.
2964     X86::CondCode BranchCode = X86::getCondFromBranch(*I);
2965     if (BranchCode == X86::COND_INVALID)
2966       return true;  // Can't handle indirect branch.
2967 
2968     // In practice we should never have an undef eflags operand, if we do
2969     // abort here as we are not prepared to preserve the flag.
2970     if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
2971       return true;
2972 
2973     // Working from the bottom, handle the first conditional branch.
2974     if (Cond.empty()) {
2975       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2976       if (AllowModify && UnCondBrIter != MBB.end() &&
2977           MBB.isLayoutSuccessor(TargetBB)) {
2978         // If we can modify the code and it ends in something like:
2979         //
2980         //     jCC L1
2981         //     jmp L2
2982         //   L1:
2983         //     ...
2984         //   L2:
2985         //
2986         // Then we can change this to:
2987         //
2988         //     jnCC L2
2989         //   L1:
2990         //     ...
2991         //   L2:
2992         //
2993         // Which is a bit more efficient.
2994         // We conditionally jump to the fall-through block.
2995         BranchCode = GetOppositeBranchCondition(BranchCode);
2996         MachineBasicBlock::iterator OldInst = I;
2997 
2998         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
2999           .addMBB(UnCondBrIter->getOperand(0).getMBB())
3000           .addImm(BranchCode);
3001         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3002           .addMBB(TargetBB);
3003 
3004         OldInst->eraseFromParent();
3005         UnCondBrIter->eraseFromParent();
3006 
3007         // Restart the analysis.
3008         UnCondBrIter = MBB.end();
3009         I = MBB.end();
3010         continue;
3011       }
3012 
3013       FBB = TBB;
3014       TBB = I->getOperand(0).getMBB();
3015       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3016       CondBranches.push_back(&*I);
3017       continue;
3018     }
3019 
3020     // Handle subsequent conditional branches. Only handle the case where all
3021     // conditional branches branch to the same destination and their condition
3022     // opcodes fit one of the special multi-branch idioms.
3023     assert(Cond.size() == 1);
3024     assert(TBB);
3025 
3026     // If the conditions are the same, we can leave them alone.
3027     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3028     auto NewTBB = I->getOperand(0).getMBB();
3029     if (OldBranchCode == BranchCode && TBB == NewTBB)
3030       continue;
3031 
3032     // If they differ, see if they fit one of the known patterns. Theoretically,
3033     // we could handle more patterns here, but we shouldn't expect to see them
3034     // if instruction selection has done a reasonable job.
3035     if (TBB == NewTBB &&
3036                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3037                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3038       BranchCode = X86::COND_NE_OR_P;
3039     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3040                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3041       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
3042         return true;
3043 
3044       // X86::COND_E_AND_NP usually has two different branch destinations.
3045       //
3046       // JP B1
3047       // JE B2
3048       // JMP B1
3049       // B1:
3050       // B2:
3051       //
3052       // Here this condition branches to B2 only if NP && E. It has another
3053       // equivalent form:
3054       //
3055       // JNE B1
3056       // JNP B2
3057       // JMP B1
3058       // B1:
3059       // B2:
3060       //
3061       // Similarly it branches to B2 only if E && NP. That is why this condition
3062       // is named with COND_E_AND_NP.
3063       BranchCode = X86::COND_E_AND_NP;
3064     } else
3065       return true;
3066 
3067     // Update the MachineOperand.
3068     Cond[0].setImm(BranchCode);
3069     CondBranches.push_back(&*I);
3070   }
3071 
3072   return false;
3073 }
3074 
3075 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3076                                  MachineBasicBlock *&TBB,
3077                                  MachineBasicBlock *&FBB,
3078                                  SmallVectorImpl<MachineOperand> &Cond,
3079                                  bool AllowModify) const {
3080   SmallVector<MachineInstr *, 4> CondBranches;
3081   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3082 }
3083 
3084 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
3085                                           MachineBranchPredicate &MBP,
3086                                           bool AllowModify) const {
3087   using namespace std::placeholders;
3088 
3089   SmallVector<MachineOperand, 4> Cond;
3090   SmallVector<MachineInstr *, 4> CondBranches;
3091   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3092                         AllowModify))
3093     return true;
3094 
3095   if (Cond.size() != 1)
3096     return true;
3097 
3098   assert(MBP.TrueDest && "expected!");
3099 
3100   if (!MBP.FalseDest)
3101     MBP.FalseDest = MBB.getNextNode();
3102 
3103   const TargetRegisterInfo *TRI = &getRegisterInfo();
3104 
3105   MachineInstr *ConditionDef = nullptr;
3106   bool SingleUseCondition = true;
3107 
3108   for (MachineInstr &MI : llvm::drop_begin(llvm::reverse(MBB))) {
3109     if (MI.modifiesRegister(X86::EFLAGS, TRI)) {
3110       ConditionDef = &MI;
3111       break;
3112     }
3113 
3114     if (MI.readsRegister(X86::EFLAGS, TRI))
3115       SingleUseCondition = false;
3116   }
3117 
3118   if (!ConditionDef)
3119     return true;
3120 
3121   if (SingleUseCondition) {
3122     for (auto *Succ : MBB.successors())
3123       if (Succ->isLiveIn(X86::EFLAGS))
3124         SingleUseCondition = false;
3125   }
3126 
3127   MBP.ConditionDef = ConditionDef;
3128   MBP.SingleUseCondition = SingleUseCondition;
3129 
3130   // Currently we only recognize the simple pattern:
3131   //
3132   //   test %reg, %reg
3133   //   je %label
3134   //
3135   const unsigned TestOpcode =
3136       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3137 
3138   if (ConditionDef->getOpcode() == TestOpcode &&
3139       ConditionDef->getNumOperands() == 3 &&
3140       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3141       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3142     MBP.LHS = ConditionDef->getOperand(0);
3143     MBP.RHS = MachineOperand::CreateImm(0);
3144     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3145                         ? MachineBranchPredicate::PRED_NE
3146                         : MachineBranchPredicate::PRED_EQ;
3147     return false;
3148   }
3149 
3150   return true;
3151 }
3152 
3153 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
3154                                     int *BytesRemoved) const {
3155   assert(!BytesRemoved && "code size not handled");
3156 
3157   MachineBasicBlock::iterator I = MBB.end();
3158   unsigned Count = 0;
3159 
3160   while (I != MBB.begin()) {
3161     --I;
3162     if (I->isDebugInstr())
3163       continue;
3164     if (I->getOpcode() != X86::JMP_1 &&
3165         X86::getCondFromBranch(*I) == X86::COND_INVALID)
3166       break;
3167     // Remove the branch.
3168     I->eraseFromParent();
3169     I = MBB.end();
3170     ++Count;
3171   }
3172 
3173   return Count;
3174 }
3175 
3176 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
3177                                     MachineBasicBlock *TBB,
3178                                     MachineBasicBlock *FBB,
3179                                     ArrayRef<MachineOperand> Cond,
3180                                     const DebugLoc &DL,
3181                                     int *BytesAdded) const {
3182   // Shouldn't be a fall through.
3183   assert(TBB && "insertBranch must not be told to insert a fallthrough");
3184   assert((Cond.size() == 1 || Cond.size() == 0) &&
3185          "X86 branch conditions have one component!");
3186   assert(!BytesAdded && "code size not handled");
3187 
3188   if (Cond.empty()) {
3189     // Unconditional branch?
3190     assert(!FBB && "Unconditional branch with multiple successors!");
3191     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3192     return 1;
3193   }
3194 
3195   // If FBB is null, it is implied to be a fall-through block.
3196   bool FallThru = FBB == nullptr;
3197 
3198   // Conditional branch.
3199   unsigned Count = 0;
3200   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3201   switch (CC) {
3202   case X86::COND_NE_OR_P:
3203     // Synthesize NE_OR_P with two branches.
3204     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
3205     ++Count;
3206     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
3207     ++Count;
3208     break;
3209   case X86::COND_E_AND_NP:
3210     // Use the next block of MBB as FBB if it is null.
3211     if (FBB == nullptr) {
3212       FBB = getFallThroughMBB(&MBB, TBB);
3213       assert(FBB && "MBB cannot be the last block in function when the false "
3214                     "body is a fall-through.");
3215     }
3216     // Synthesize COND_E_AND_NP with two branches.
3217     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
3218     ++Count;
3219     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
3220     ++Count;
3221     break;
3222   default: {
3223     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
3224     ++Count;
3225   }
3226   }
3227   if (!FallThru) {
3228     // Two-way Conditional branch. Insert the second branch.
3229     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3230     ++Count;
3231   }
3232   return Count;
3233 }
3234 
3235 bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
3236                                    ArrayRef<MachineOperand> Cond,
3237                                    Register DstReg, Register TrueReg,
3238                                    Register FalseReg, int &CondCycles,
3239                                    int &TrueCycles, int &FalseCycles) const {
3240   // Not all subtargets have cmov instructions.
3241   if (!Subtarget.canUseCMOV())
3242     return false;
3243   if (Cond.size() != 1)
3244     return false;
3245   // We cannot do the composite conditions, at least not in SSA form.
3246   if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
3247     return false;
3248 
3249   // Check register classes.
3250   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3251   const TargetRegisterClass *RC =
3252     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3253   if (!RC)
3254     return false;
3255 
3256   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3257   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3258       X86::GR32RegClass.hasSubClassEq(RC) ||
3259       X86::GR64RegClass.hasSubClassEq(RC)) {
3260     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3261     // Bridge. Probably Ivy Bridge as well.
3262     CondCycles = 2;
3263     TrueCycles = 2;
3264     FalseCycles = 2;
3265     return true;
3266   }
3267 
3268   // Can't do vectors.
3269   return false;
3270 }
3271 
3272 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3273                                 MachineBasicBlock::iterator I,
3274                                 const DebugLoc &DL, Register DstReg,
3275                                 ArrayRef<MachineOperand> Cond, Register TrueReg,
3276                                 Register FalseReg) const {
3277   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3278   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3279   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
3280   assert(Cond.size() == 1 && "Invalid Cond array");
3281   unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
3282                                     false /*HasMemoryOperand*/);
3283   BuildMI(MBB, I, DL, get(Opc), DstReg)
3284       .addReg(FalseReg)
3285       .addReg(TrueReg)
3286       .addImm(Cond[0].getImm());
3287 }
3288 
3289 /// Test if the given register is a physical h register.
3290 static bool isHReg(unsigned Reg) {
3291   return X86::GR8_ABCD_HRegClass.contains(Reg);
3292 }
3293 
3294 // Try and copy between VR128/VR64 and GR64 registers.
3295 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3296                                         const X86Subtarget &Subtarget) {
3297   bool HasAVX = Subtarget.hasAVX();
3298   bool HasAVX512 = Subtarget.hasAVX512();
3299 
3300   // SrcReg(MaskReg) -> DestReg(GR64)
3301   // SrcReg(MaskReg) -> DestReg(GR32)
3302 
3303   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3304   if (X86::VK16RegClass.contains(SrcReg)) {
3305     if (X86::GR64RegClass.contains(DestReg)) {
3306       assert(Subtarget.hasBWI());
3307       return X86::KMOVQrk;
3308     }
3309     if (X86::GR32RegClass.contains(DestReg))
3310       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
3311   }
3312 
3313   // SrcReg(GR64) -> DestReg(MaskReg)
3314   // SrcReg(GR32) -> DestReg(MaskReg)
3315 
3316   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3317   if (X86::VK16RegClass.contains(DestReg)) {
3318     if (X86::GR64RegClass.contains(SrcReg)) {
3319       assert(Subtarget.hasBWI());
3320       return X86::KMOVQkr;
3321     }
3322     if (X86::GR32RegClass.contains(SrcReg))
3323       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
3324   }
3325 
3326 
3327   // SrcReg(VR128) -> DestReg(GR64)
3328   // SrcReg(VR64)  -> DestReg(GR64)
3329   // SrcReg(GR64)  -> DestReg(VR128)
3330   // SrcReg(GR64)  -> DestReg(VR64)
3331 
3332   if (X86::GR64RegClass.contains(DestReg)) {
3333     if (X86::VR128XRegClass.contains(SrcReg))
3334       // Copy from a VR128 register to a GR64 register.
3335       return HasAVX512 ? X86::VMOVPQIto64Zrr :
3336              HasAVX    ? X86::VMOVPQIto64rr  :
3337                          X86::MOVPQIto64rr;
3338     if (X86::VR64RegClass.contains(SrcReg))
3339       // Copy from a VR64 register to a GR64 register.
3340       return X86::MMX_MOVD64from64rr;
3341   } else if (X86::GR64RegClass.contains(SrcReg)) {
3342     // Copy from a GR64 register to a VR128 register.
3343     if (X86::VR128XRegClass.contains(DestReg))
3344       return HasAVX512 ? X86::VMOV64toPQIZrr :
3345              HasAVX    ? X86::VMOV64toPQIrr  :
3346                          X86::MOV64toPQIrr;
3347     // Copy from a GR64 register to a VR64 register.
3348     if (X86::VR64RegClass.contains(DestReg))
3349       return X86::MMX_MOVD64to64rr;
3350   }
3351 
3352   // SrcReg(VR128) -> DestReg(GR32)
3353   // SrcReg(GR32)  -> DestReg(VR128)
3354 
3355   if (X86::GR32RegClass.contains(DestReg) &&
3356       X86::VR128XRegClass.contains(SrcReg))
3357     // Copy from a VR128 register to a GR32 register.
3358     return HasAVX512 ? X86::VMOVPDI2DIZrr :
3359            HasAVX    ? X86::VMOVPDI2DIrr  :
3360                        X86::MOVPDI2DIrr;
3361 
3362   if (X86::VR128XRegClass.contains(DestReg) &&
3363       X86::GR32RegClass.contains(SrcReg))
3364     // Copy from a VR128 register to a VR128 register.
3365     return HasAVX512 ? X86::VMOVDI2PDIZrr :
3366            HasAVX    ? X86::VMOVDI2PDIrr  :
3367                        X86::MOVDI2PDIrr;
3368   return 0;
3369 }
3370 
3371 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3372                                MachineBasicBlock::iterator MI,
3373                                const DebugLoc &DL, MCRegister DestReg,
3374                                MCRegister SrcReg, bool KillSrc) const {
3375   // First deal with the normal symmetric copies.
3376   bool HasAVX = Subtarget.hasAVX();
3377   bool HasVLX = Subtarget.hasVLX();
3378   unsigned Opc = 0;
3379   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3380     Opc = X86::MOV64rr;
3381   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3382     Opc = X86::MOV32rr;
3383   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3384     Opc = X86::MOV16rr;
3385   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3386     // Copying to or from a physical H register on x86-64 requires a NOREX
3387     // move.  Otherwise use a normal move.
3388     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3389         Subtarget.is64Bit()) {
3390       Opc = X86::MOV8rr_NOREX;
3391       // Both operands must be encodable without an REX prefix.
3392       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3393              "8-bit H register can not be copied outside GR8_NOREX");
3394     } else
3395       Opc = X86::MOV8rr;
3396   }
3397   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3398     Opc = X86::MMX_MOVQ64rr;
3399   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3400     if (HasVLX)
3401       Opc = X86::VMOVAPSZ128rr;
3402     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3403       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3404     else {
3405       // If this an extended register and we don't have VLX we need to use a
3406       // 512-bit move.
3407       Opc = X86::VMOVAPSZrr;
3408       const TargetRegisterInfo *TRI = &getRegisterInfo();
3409       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3410                                          &X86::VR512RegClass);
3411       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3412                                         &X86::VR512RegClass);
3413     }
3414   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3415     if (HasVLX)
3416       Opc = X86::VMOVAPSZ256rr;
3417     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3418       Opc = X86::VMOVAPSYrr;
3419     else {
3420       // If this an extended register and we don't have VLX we need to use a
3421       // 512-bit move.
3422       Opc = X86::VMOVAPSZrr;
3423       const TargetRegisterInfo *TRI = &getRegisterInfo();
3424       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3425                                          &X86::VR512RegClass);
3426       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3427                                         &X86::VR512RegClass);
3428     }
3429   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3430     Opc = X86::VMOVAPSZrr;
3431   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3432   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3433     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3434   if (!Opc)
3435     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3436 
3437   if (Opc) {
3438     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3439       .addReg(SrcReg, getKillRegState(KillSrc));
3440     return;
3441   }
3442 
3443   if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3444     // FIXME: We use a fatal error here because historically LLVM has tried
3445     // lower some of these physreg copies and we want to ensure we get
3446     // reasonable bug reports if someone encounters a case no other testing
3447     // found. This path should be removed after the LLVM 7 release.
3448     report_fatal_error("Unable to copy EFLAGS physical register!");
3449   }
3450 
3451   LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3452                     << RI.getName(DestReg) << '\n');
3453   report_fatal_error("Cannot emit physreg copy instruction");
3454 }
3455 
3456 Optional<DestSourcePair>
3457 X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
3458   if (MI.isMoveReg())
3459     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
3460   return None;
3461 }
3462 
3463 static unsigned getLoadStoreRegOpcode(Register Reg,
3464                                       const TargetRegisterClass *RC,
3465                                       bool IsStackAligned,
3466                                       const X86Subtarget &STI, bool load) {
3467   bool HasAVX = STI.hasAVX();
3468   bool HasAVX512 = STI.hasAVX512();
3469   bool HasVLX = STI.hasVLX();
3470 
3471   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3472   default:
3473     llvm_unreachable("Unknown spill size");
3474   case 1:
3475     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3476     if (STI.is64Bit())
3477       // Copying to or from a physical H register on x86-64 requires a NOREX
3478       // move.  Otherwise use a normal move.
3479       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3480         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3481     return load ? X86::MOV8rm : X86::MOV8mr;
3482   case 2:
3483     if (X86::VK16RegClass.hasSubClassEq(RC))
3484       return load ? X86::KMOVWkm : X86::KMOVWmk;
3485     if (X86::FR16XRegClass.hasSubClassEq(RC)) {
3486       assert(STI.hasFP16());
3487       return load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
3488     }
3489     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3490     return load ? X86::MOV16rm : X86::MOV16mr;
3491   case 4:
3492     if (X86::GR32RegClass.hasSubClassEq(RC))
3493       return load ? X86::MOV32rm : X86::MOV32mr;
3494     if (X86::FR32XRegClass.hasSubClassEq(RC))
3495       return load ?
3496         (HasAVX512 ? X86::VMOVSSZrm_alt :
3497          HasAVX    ? X86::VMOVSSrm_alt :
3498                      X86::MOVSSrm_alt) :
3499         (HasAVX512 ? X86::VMOVSSZmr :
3500          HasAVX    ? X86::VMOVSSmr :
3501                      X86::MOVSSmr);
3502     if (X86::RFP32RegClass.hasSubClassEq(RC))
3503       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3504     if (X86::VK32RegClass.hasSubClassEq(RC)) {
3505       assert(STI.hasBWI() && "KMOVD requires BWI");
3506       return load ? X86::KMOVDkm : X86::KMOVDmk;
3507     }
3508     // All of these mask pair classes have the same spill size, the same kind
3509     // of kmov instructions can be used with all of them.
3510     if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3511         X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3512         X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3513         X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3514         X86::VK16PAIRRegClass.hasSubClassEq(RC))
3515       return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3516     llvm_unreachable("Unknown 4-byte regclass");
3517   case 8:
3518     if (X86::GR64RegClass.hasSubClassEq(RC))
3519       return load ? X86::MOV64rm : X86::MOV64mr;
3520     if (X86::FR64XRegClass.hasSubClassEq(RC))
3521       return load ?
3522         (HasAVX512 ? X86::VMOVSDZrm_alt :
3523          HasAVX    ? X86::VMOVSDrm_alt :
3524                      X86::MOVSDrm_alt) :
3525         (HasAVX512 ? X86::VMOVSDZmr :
3526          HasAVX    ? X86::VMOVSDmr :
3527                      X86::MOVSDmr);
3528     if (X86::VR64RegClass.hasSubClassEq(RC))
3529       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3530     if (X86::RFP64RegClass.hasSubClassEq(RC))
3531       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3532     if (X86::VK64RegClass.hasSubClassEq(RC)) {
3533       assert(STI.hasBWI() && "KMOVQ requires BWI");
3534       return load ? X86::KMOVQkm : X86::KMOVQmk;
3535     }
3536     llvm_unreachable("Unknown 8-byte regclass");
3537   case 10:
3538     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3539     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3540   case 16: {
3541     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3542       // If stack is realigned we can use aligned stores.
3543       if (IsStackAligned)
3544         return load ?
3545           (HasVLX    ? X86::VMOVAPSZ128rm :
3546            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3547            HasAVX    ? X86::VMOVAPSrm :
3548                        X86::MOVAPSrm):
3549           (HasVLX    ? X86::VMOVAPSZ128mr :
3550            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3551            HasAVX    ? X86::VMOVAPSmr :
3552                        X86::MOVAPSmr);
3553       else
3554         return load ?
3555           (HasVLX    ? X86::VMOVUPSZ128rm :
3556            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3557            HasAVX    ? X86::VMOVUPSrm :
3558                        X86::MOVUPSrm):
3559           (HasVLX    ? X86::VMOVUPSZ128mr :
3560            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3561            HasAVX    ? X86::VMOVUPSmr :
3562                        X86::MOVUPSmr);
3563     }
3564     llvm_unreachable("Unknown 16-byte regclass");
3565   }
3566   case 32:
3567     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3568     // If stack is realigned we can use aligned stores.
3569     if (IsStackAligned)
3570       return load ?
3571         (HasVLX    ? X86::VMOVAPSZ256rm :
3572          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3573                      X86::VMOVAPSYrm) :
3574         (HasVLX    ? X86::VMOVAPSZ256mr :
3575          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3576                      X86::VMOVAPSYmr);
3577     else
3578       return load ?
3579         (HasVLX    ? X86::VMOVUPSZ256rm :
3580          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3581                      X86::VMOVUPSYrm) :
3582         (HasVLX    ? X86::VMOVUPSZ256mr :
3583          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3584                      X86::VMOVUPSYmr);
3585   case 64:
3586     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3587     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3588     if (IsStackAligned)
3589       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3590     else
3591       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3592   }
3593 }
3594 
3595 Optional<ExtAddrMode>
3596 X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
3597                                       const TargetRegisterInfo *TRI) const {
3598   const MCInstrDesc &Desc = MemI.getDesc();
3599   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3600   if (MemRefBegin < 0)
3601     return None;
3602 
3603   MemRefBegin += X86II::getOperandBias(Desc);
3604 
3605   auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg);
3606   if (!BaseOp.isReg()) // Can be an MO_FrameIndex
3607     return None;
3608 
3609   const MachineOperand &DispMO = MemI.getOperand(MemRefBegin + X86::AddrDisp);
3610   // Displacement can be symbolic
3611   if (!DispMO.isImm())
3612     return None;
3613 
3614   ExtAddrMode AM;
3615   AM.BaseReg = BaseOp.getReg();
3616   AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg();
3617   AM.Scale = MemI.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm();
3618   AM.Displacement = DispMO.getImm();
3619   return AM;
3620 }
3621 
3622 bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
3623                                            const Register Reg,
3624                                            int64_t &ImmVal) const {
3625   if (MI.getOpcode() != X86::MOV32ri && MI.getOpcode() != X86::MOV64ri)
3626     return false;
3627   // Mov Src can be a global address.
3628   if (!MI.getOperand(1).isImm() || MI.getOperand(0).getReg() != Reg)
3629     return false;
3630   ImmVal = MI.getOperand(1).getImm();
3631   return true;
3632 }
3633 
3634 bool X86InstrInfo::preservesZeroValueInReg(
3635     const MachineInstr *MI, const Register NullValueReg,
3636     const TargetRegisterInfo *TRI) const {
3637   if (!MI->modifiesRegister(NullValueReg, TRI))
3638     return true;
3639   switch (MI->getOpcode()) {
3640   // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
3641   // X.
3642   case X86::SHR64ri:
3643   case X86::SHR32ri:
3644   case X86::SHL64ri:
3645   case X86::SHL32ri:
3646     assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&
3647            "expected for shift opcode!");
3648     return MI->getOperand(0).getReg() == NullValueReg &&
3649            MI->getOperand(1).getReg() == NullValueReg;
3650   // Zero extend of a sub-reg of NullValueReg into itself does not change the
3651   // null value.
3652   case X86::MOV32rr:
3653     return llvm::all_of(MI->operands(), [&](const MachineOperand &MO) {
3654       return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
3655     });
3656   default:
3657     return false;
3658   }
3659   llvm_unreachable("Should be handled above!");
3660 }
3661 
3662 bool X86InstrInfo::getMemOperandsWithOffsetWidth(
3663     const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
3664     int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3665     const TargetRegisterInfo *TRI) const {
3666   const MCInstrDesc &Desc = MemOp.getDesc();
3667   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3668   if (MemRefBegin < 0)
3669     return false;
3670 
3671   MemRefBegin += X86II::getOperandBias(Desc);
3672 
3673   const MachineOperand *BaseOp =
3674       &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3675   if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3676     return false;
3677 
3678   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3679     return false;
3680 
3681   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3682       X86::NoRegister)
3683     return false;
3684 
3685   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3686 
3687   // Displacement can be symbolic
3688   if (!DispMO.isImm())
3689     return false;
3690 
3691   Offset = DispMO.getImm();
3692 
3693   if (!BaseOp->isReg())
3694     return false;
3695 
3696   OffsetIsScalable = false;
3697   // FIXME: Relying on memoperands() may not be right thing to do here. Check
3698   // with X86 maintainers, and fix it accordingly. For now, it is ok, since
3699   // there is no use of `Width` for X86 back-end at the moment.
3700   Width =
3701       !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0;
3702   BaseOps.push_back(BaseOp);
3703   return true;
3704 }
3705 
3706 static unsigned getStoreRegOpcode(Register SrcReg,
3707                                   const TargetRegisterClass *RC,
3708                                   bool IsStackAligned,
3709                                   const X86Subtarget &STI) {
3710   return getLoadStoreRegOpcode(SrcReg, RC, IsStackAligned, STI, false);
3711 }
3712 
3713 static unsigned getLoadRegOpcode(Register DestReg,
3714                                  const TargetRegisterClass *RC,
3715                                  bool IsStackAligned, const X86Subtarget &STI) {
3716   return getLoadStoreRegOpcode(DestReg, RC, IsStackAligned, STI, true);
3717 }
3718 
3719 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3720                                        MachineBasicBlock::iterator MI,
3721                                        Register SrcReg, bool isKill, int FrameIdx,
3722                                        const TargetRegisterClass *RC,
3723                                        const TargetRegisterInfo *TRI) const {
3724   const MachineFunction &MF = *MBB.getParent();
3725   const MachineFrameInfo &MFI = MF.getFrameInfo();
3726   assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3727          "Stack slot too small for store");
3728   if (RC->getID() == X86::TILERegClassID) {
3729     unsigned Opc = X86::TILESTORED;
3730     // tilestored %tmm, (%sp, %idx)
3731     MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3732     Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3733     BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3734     MachineInstr *NewMI =
3735         addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3736             .addReg(SrcReg, getKillRegState(isKill));
3737     MachineOperand &MO = NewMI->getOperand(2);
3738     MO.setReg(VirtReg);
3739     MO.setIsKill(true);
3740   } else {
3741     unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3742     bool isAligned =
3743         (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3744         (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3745     unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3746     addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3747         .addReg(SrcReg, getKillRegState(isKill));
3748   }
3749 }
3750 
3751 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3752                                         MachineBasicBlock::iterator MI,
3753                                         Register DestReg, int FrameIdx,
3754                                         const TargetRegisterClass *RC,
3755                                         const TargetRegisterInfo *TRI) const {
3756   if (RC->getID() == X86::TILERegClassID) {
3757     unsigned Opc = X86::TILELOADD;
3758     // tileloadd (%sp, %idx), %tmm
3759     MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3760     Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3761     MachineInstr *NewMI =
3762         BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3763     NewMI = addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3764                               FrameIdx);
3765     MachineOperand &MO = NewMI->getOperand(3);
3766     MO.setReg(VirtReg);
3767     MO.setIsKill(true);
3768   } else {
3769     const MachineFunction &MF = *MBB.getParent();
3770     const MachineFrameInfo &MFI = MF.getFrameInfo();
3771     unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3772     bool isAligned =
3773         (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3774         (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3775     unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3776     addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3777                       FrameIdx);
3778   }
3779 }
3780 
3781 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
3782                                   Register &SrcReg2, int64_t &CmpMask,
3783                                   int64_t &CmpValue) const {
3784   switch (MI.getOpcode()) {
3785   default: break;
3786   case X86::CMP64ri32:
3787   case X86::CMP64ri8:
3788   case X86::CMP32ri:
3789   case X86::CMP32ri8:
3790   case X86::CMP16ri:
3791   case X86::CMP16ri8:
3792   case X86::CMP8ri:
3793     SrcReg = MI.getOperand(0).getReg();
3794     SrcReg2 = 0;
3795     if (MI.getOperand(1).isImm()) {
3796       CmpMask = ~0;
3797       CmpValue = MI.getOperand(1).getImm();
3798     } else {
3799       CmpMask = CmpValue = 0;
3800     }
3801     return true;
3802   // A SUB can be used to perform comparison.
3803   case X86::SUB64rm:
3804   case X86::SUB32rm:
3805   case X86::SUB16rm:
3806   case X86::SUB8rm:
3807     SrcReg = MI.getOperand(1).getReg();
3808     SrcReg2 = 0;
3809     CmpMask = 0;
3810     CmpValue = 0;
3811     return true;
3812   case X86::SUB64rr:
3813   case X86::SUB32rr:
3814   case X86::SUB16rr:
3815   case X86::SUB8rr:
3816     SrcReg = MI.getOperand(1).getReg();
3817     SrcReg2 = MI.getOperand(2).getReg();
3818     CmpMask = 0;
3819     CmpValue = 0;
3820     return true;
3821   case X86::SUB64ri32:
3822   case X86::SUB64ri8:
3823   case X86::SUB32ri:
3824   case X86::SUB32ri8:
3825   case X86::SUB16ri:
3826   case X86::SUB16ri8:
3827   case X86::SUB8ri:
3828     SrcReg = MI.getOperand(1).getReg();
3829     SrcReg2 = 0;
3830     if (MI.getOperand(2).isImm()) {
3831       CmpMask = ~0;
3832       CmpValue = MI.getOperand(2).getImm();
3833     } else {
3834       CmpMask = CmpValue = 0;
3835     }
3836     return true;
3837   case X86::CMP64rr:
3838   case X86::CMP32rr:
3839   case X86::CMP16rr:
3840   case X86::CMP8rr:
3841     SrcReg = MI.getOperand(0).getReg();
3842     SrcReg2 = MI.getOperand(1).getReg();
3843     CmpMask = 0;
3844     CmpValue = 0;
3845     return true;
3846   case X86::TEST8rr:
3847   case X86::TEST16rr:
3848   case X86::TEST32rr:
3849   case X86::TEST64rr:
3850     SrcReg = MI.getOperand(0).getReg();
3851     if (MI.getOperand(1).getReg() != SrcReg)
3852       return false;
3853     // Compare against zero.
3854     SrcReg2 = 0;
3855     CmpMask = ~0;
3856     CmpValue = 0;
3857     return true;
3858   }
3859   return false;
3860 }
3861 
3862 bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
3863                                         Register SrcReg, Register SrcReg2,
3864                                         int64_t ImmMask, int64_t ImmValue,
3865                                         const MachineInstr &OI, bool *IsSwapped,
3866                                         int64_t *ImmDelta) const {
3867   switch (OI.getOpcode()) {
3868   case X86::CMP64rr:
3869   case X86::CMP32rr:
3870   case X86::CMP16rr:
3871   case X86::CMP8rr:
3872   case X86::SUB64rr:
3873   case X86::SUB32rr:
3874   case X86::SUB16rr:
3875   case X86::SUB8rr: {
3876     Register OISrcReg;
3877     Register OISrcReg2;
3878     int64_t OIMask;
3879     int64_t OIValue;
3880     if (!analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) ||
3881         OIMask != ImmMask || OIValue != ImmValue)
3882       return false;
3883     if (SrcReg == OISrcReg && SrcReg2 == OISrcReg2) {
3884       *IsSwapped = false;
3885       return true;
3886     }
3887     if (SrcReg == OISrcReg2 && SrcReg2 == OISrcReg) {
3888       *IsSwapped = true;
3889       return true;
3890     }
3891     return false;
3892   }
3893   case X86::CMP64ri32:
3894   case X86::CMP64ri8:
3895   case X86::CMP32ri:
3896   case X86::CMP32ri8:
3897   case X86::CMP16ri:
3898   case X86::CMP16ri8:
3899   case X86::CMP8ri:
3900   case X86::SUB64ri32:
3901   case X86::SUB64ri8:
3902   case X86::SUB32ri:
3903   case X86::SUB32ri8:
3904   case X86::SUB16ri:
3905   case X86::SUB16ri8:
3906   case X86::SUB8ri:
3907   case X86::TEST64rr:
3908   case X86::TEST32rr:
3909   case X86::TEST16rr:
3910   case X86::TEST8rr: {
3911     if (ImmMask != 0) {
3912       Register OISrcReg;
3913       Register OISrcReg2;
3914       int64_t OIMask;
3915       int64_t OIValue;
3916       if (analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) &&
3917           SrcReg == OISrcReg && ImmMask == OIMask) {
3918         if (OIValue == ImmValue) {
3919           *ImmDelta = 0;
3920           return true;
3921         } else if (static_cast<uint64_t>(ImmValue) ==
3922                    static_cast<uint64_t>(OIValue) - 1) {
3923           *ImmDelta = -1;
3924           return true;
3925         } else if (static_cast<uint64_t>(ImmValue) ==
3926                    static_cast<uint64_t>(OIValue) + 1) {
3927           *ImmDelta = 1;
3928           return true;
3929         } else {
3930           return false;
3931         }
3932       }
3933     }
3934     return FlagI.isIdenticalTo(OI);
3935   }
3936   default:
3937     return false;
3938   }
3939 }
3940 
3941 /// Check whether the definition can be converted
3942 /// to remove a comparison against zero.
3943 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
3944                                     bool &ClearsOverflowFlag) {
3945   NoSignFlag = false;
3946   ClearsOverflowFlag = false;
3947 
3948   switch (MI.getOpcode()) {
3949   default: return false;
3950 
3951   // The shift instructions only modify ZF if their shift count is non-zero.
3952   // N.B.: The processor truncates the shift count depending on the encoding.
3953   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3954   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3955      return getTruncatedShiftCount(MI, 2) != 0;
3956 
3957   // Some left shift instructions can be turned into LEA instructions but only
3958   // if their flags aren't used. Avoid transforming such instructions.
3959   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3960     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3961     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3962     return ShAmt != 0;
3963   }
3964 
3965   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3966   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3967      return getTruncatedShiftCount(MI, 3) != 0;
3968 
3969   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3970   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3971   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3972   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3973   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3974   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3975   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3976   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3977   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3978   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3979   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3980   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3981   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3982   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
3983   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
3984   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
3985   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
3986   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3987   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
3988   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
3989   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
3990   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
3991   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
3992   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
3993   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
3994   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
3995   case X86::LZCNT16rr: case X86::LZCNT16rm:
3996   case X86::LZCNT32rr: case X86::LZCNT32rm:
3997   case X86::LZCNT64rr: case X86::LZCNT64rm:
3998   case X86::POPCNT16rr:case X86::POPCNT16rm:
3999   case X86::POPCNT32rr:case X86::POPCNT32rm:
4000   case X86::POPCNT64rr:case X86::POPCNT64rm:
4001   case X86::TZCNT16rr: case X86::TZCNT16rm:
4002   case X86::TZCNT32rr: case X86::TZCNT32rm:
4003   case X86::TZCNT64rr: case X86::TZCNT64rm:
4004     return true;
4005   case X86::AND64ri32:   case X86::AND64ri8:  case X86::AND32ri:
4006   case X86::AND32ri8:    case X86::AND16ri:   case X86::AND16ri8:
4007   case X86::AND8ri:      case X86::AND64rr:   case X86::AND32rr:
4008   case X86::AND16rr:     case X86::AND8rr:    case X86::AND64rm:
4009   case X86::AND32rm:     case X86::AND16rm:   case X86::AND8rm:
4010   case X86::XOR64ri32:   case X86::XOR64ri8:  case X86::XOR32ri:
4011   case X86::XOR32ri8:    case X86::XOR16ri:   case X86::XOR16ri8:
4012   case X86::XOR8ri:      case X86::XOR64rr:   case X86::XOR32rr:
4013   case X86::XOR16rr:     case X86::XOR8rr:    case X86::XOR64rm:
4014   case X86::XOR32rm:     case X86::XOR16rm:   case X86::XOR8rm:
4015   case X86::OR64ri32:    case X86::OR64ri8:   case X86::OR32ri:
4016   case X86::OR32ri8:     case X86::OR16ri:    case X86::OR16ri8:
4017   case X86::OR8ri:       case X86::OR64rr:    case X86::OR32rr:
4018   case X86::OR16rr:      case X86::OR8rr:     case X86::OR64rm:
4019   case X86::OR32rm:      case X86::OR16rm:    case X86::OR8rm:
4020   case X86::ANDN32rr:    case X86::ANDN32rm:
4021   case X86::ANDN64rr:    case X86::ANDN64rm:
4022   case X86::BLSI32rr:    case X86::BLSI32rm:
4023   case X86::BLSI64rr:    case X86::BLSI64rm:
4024   case X86::BLSMSK32rr:  case X86::BLSMSK32rm:
4025   case X86::BLSMSK64rr:  case X86::BLSMSK64rm:
4026   case X86::BLSR32rr:    case X86::BLSR32rm:
4027   case X86::BLSR64rr:    case X86::BLSR64rm:
4028   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
4029   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
4030   case X86::BLCI32rr:    case X86::BLCI32rm:
4031   case X86::BLCI64rr:    case X86::BLCI64rm:
4032   case X86::BLCIC32rr:   case X86::BLCIC32rm:
4033   case X86::BLCIC64rr:   case X86::BLCIC64rm:
4034   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
4035   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
4036   case X86::BLCS32rr:    case X86::BLCS32rm:
4037   case X86::BLCS64rr:    case X86::BLCS64rm:
4038   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
4039   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
4040   case X86::BLSIC32rr:   case X86::BLSIC32rm:
4041   case X86::BLSIC64rr:   case X86::BLSIC64rm:
4042   case X86::BZHI32rr:    case X86::BZHI32rm:
4043   case X86::BZHI64rr:    case X86::BZHI64rm:
4044   case X86::T1MSKC32rr:  case X86::T1MSKC32rm:
4045   case X86::T1MSKC64rr:  case X86::T1MSKC64rm:
4046   case X86::TZMSK32rr:   case X86::TZMSK32rm:
4047   case X86::TZMSK64rr:   case X86::TZMSK64rm:
4048     // These instructions clear the overflow flag just like TEST.
4049     // FIXME: These are not the only instructions in this switch that clear the
4050     // overflow flag.
4051     ClearsOverflowFlag = true;
4052     return true;
4053   case X86::BEXTR32rr:   case X86::BEXTR64rr:
4054   case X86::BEXTR32rm:   case X86::BEXTR64rm:
4055   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
4056   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
4057     // BEXTR doesn't update the sign flag so we can't use it. It does clear
4058     // the overflow flag, but that's not useful without the sign flag.
4059     NoSignFlag = true;
4060     return true;
4061   }
4062 }
4063 
4064 /// Check whether the use can be converted to remove a comparison against zero.
4065 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
4066   switch (MI.getOpcode()) {
4067   default: return X86::COND_INVALID;
4068   case X86::NEG8r:
4069   case X86::NEG16r:
4070   case X86::NEG32r:
4071   case X86::NEG64r:
4072     return X86::COND_AE;
4073   case X86::LZCNT16rr:
4074   case X86::LZCNT32rr:
4075   case X86::LZCNT64rr:
4076     return X86::COND_B;
4077   case X86::POPCNT16rr:
4078   case X86::POPCNT32rr:
4079   case X86::POPCNT64rr:
4080     return X86::COND_E;
4081   case X86::TZCNT16rr:
4082   case X86::TZCNT32rr:
4083   case X86::TZCNT64rr:
4084     return X86::COND_B;
4085   case X86::BSF16rr:
4086   case X86::BSF32rr:
4087   case X86::BSF64rr:
4088   case X86::BSR16rr:
4089   case X86::BSR32rr:
4090   case X86::BSR64rr:
4091     return X86::COND_E;
4092   case X86::BLSI32rr:
4093   case X86::BLSI64rr:
4094     return X86::COND_AE;
4095   case X86::BLSR32rr:
4096   case X86::BLSR64rr:
4097   case X86::BLSMSK32rr:
4098   case X86::BLSMSK64rr:
4099     return X86::COND_B;
4100   // TODO: TBM instructions.
4101   }
4102 }
4103 
4104 /// Check if there exists an earlier instruction that
4105 /// operates on the same source operands and sets flags in the same way as
4106 /// Compare; remove Compare if possible.
4107 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
4108                                         Register SrcReg2, int64_t CmpMask,
4109                                         int64_t CmpValue,
4110                                         const MachineRegisterInfo *MRI) const {
4111   // Check whether we can replace SUB with CMP.
4112   switch (CmpInstr.getOpcode()) {
4113   default: break;
4114   case X86::SUB64ri32:
4115   case X86::SUB64ri8:
4116   case X86::SUB32ri:
4117   case X86::SUB32ri8:
4118   case X86::SUB16ri:
4119   case X86::SUB16ri8:
4120   case X86::SUB8ri:
4121   case X86::SUB64rm:
4122   case X86::SUB32rm:
4123   case X86::SUB16rm:
4124   case X86::SUB8rm:
4125   case X86::SUB64rr:
4126   case X86::SUB32rr:
4127   case X86::SUB16rr:
4128   case X86::SUB8rr: {
4129     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
4130       return false;
4131     // There is no use of the destination register, we can replace SUB with CMP.
4132     unsigned NewOpcode = 0;
4133     switch (CmpInstr.getOpcode()) {
4134     default: llvm_unreachable("Unreachable!");
4135     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4136     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4137     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4138     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4139     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4140     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4141     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4142     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4143     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4144     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4145     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4146     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4147     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4148     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4149     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4150     }
4151     CmpInstr.setDesc(get(NewOpcode));
4152     CmpInstr.removeOperand(0);
4153     // Mutating this instruction invalidates any debug data associated with it.
4154     CmpInstr.dropDebugNumber();
4155     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4156     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4157         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4158       return false;
4159   }
4160   }
4161 
4162   // The following code tries to remove the comparison by re-using EFLAGS
4163   // from earlier instructions.
4164 
4165   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
4166 
4167   // Transformation currently requires SSA values.
4168   if (SrcReg2.isPhysical())
4169     return false;
4170   MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg);
4171   assert(SrcRegDef && "Must have a definition (SSA)");
4172 
4173   MachineInstr *MI = nullptr;
4174   MachineInstr *Sub = nullptr;
4175   MachineInstr *Movr0Inst = nullptr;
4176   bool NoSignFlag = false;
4177   bool ClearsOverflowFlag = false;
4178   bool ShouldUpdateCC = false;
4179   bool IsSwapped = false;
4180   X86::CondCode NewCC = X86::COND_INVALID;
4181   int64_t ImmDelta = 0;
4182 
4183   // Search backward from CmpInstr for the next instruction defining EFLAGS.
4184   const TargetRegisterInfo *TRI = &getRegisterInfo();
4185   MachineBasicBlock &CmpMBB = *CmpInstr.getParent();
4186   MachineBasicBlock::reverse_iterator From =
4187       std::next(MachineBasicBlock::reverse_iterator(CmpInstr));
4188   for (MachineBasicBlock *MBB = &CmpMBB;;) {
4189     for (MachineInstr &Inst : make_range(From, MBB->rend())) {
4190       // Try to use EFLAGS from the instruction defining %SrcReg. Example:
4191       //     %eax = addl ...
4192       //     ...                // EFLAGS not changed
4193       //     testl %eax, %eax   // <-- can be removed
4194       if (&Inst == SrcRegDef) {
4195         if (IsCmpZero &&
4196             isDefConvertible(Inst, NoSignFlag, ClearsOverflowFlag)) {
4197           MI = &Inst;
4198           break;
4199         }
4200         // Cannot find other candidates before definition of SrcReg.
4201         return false;
4202       }
4203 
4204       if (Inst.modifiesRegister(X86::EFLAGS, TRI)) {
4205         // Try to use EFLAGS produced by an instruction reading %SrcReg.
4206         // Example:
4207         //      %eax = ...
4208         //      ...
4209         //      popcntl %eax
4210         //      ...                 // EFLAGS not changed
4211         //      testl %eax, %eax    // <-- can be removed
4212         if (IsCmpZero) {
4213           NewCC = isUseDefConvertible(Inst);
4214           if (NewCC != X86::COND_INVALID && Inst.getOperand(1).isReg() &&
4215               Inst.getOperand(1).getReg() == SrcReg) {
4216             ShouldUpdateCC = true;
4217             MI = &Inst;
4218             break;
4219           }
4220         }
4221 
4222         // Try to use EFLAGS from an instruction with similar flag results.
4223         // Example:
4224         //     sub x, y  or  cmp x, y
4225         //     ...           // EFLAGS not changed
4226         //     cmp x, y      // <-- can be removed
4227         if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask, CmpValue,
4228                                  Inst, &IsSwapped, &ImmDelta)) {
4229           Sub = &Inst;
4230           break;
4231         }
4232 
4233         // MOV32r0 is implemented with xor which clobbers condition code. It is
4234         // safe to move up, if the definition to EFLAGS is dead and earlier
4235         // instructions do not read or write EFLAGS.
4236         if (!Movr0Inst && Inst.getOpcode() == X86::MOV32r0 &&
4237             Inst.registerDefIsDead(X86::EFLAGS, TRI)) {
4238           Movr0Inst = &Inst;
4239           continue;
4240         }
4241 
4242         // Cannot do anything for any other EFLAG changes.
4243         return false;
4244       }
4245     }
4246 
4247     if (MI || Sub)
4248       break;
4249 
4250     // Reached begin of basic block. Continue in predecessor if there is
4251     // exactly one.
4252     if (MBB->pred_size() != 1)
4253       return false;
4254     MBB = *MBB->pred_begin();
4255     From = MBB->rbegin();
4256   }
4257 
4258   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4259   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4260   // If we are done with the basic block, we need to check whether EFLAGS is
4261   // live-out.
4262   bool FlagsMayLiveOut = true;
4263   SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
4264   MachineBasicBlock::iterator AfterCmpInstr =
4265       std::next(MachineBasicBlock::iterator(CmpInstr));
4266   for (MachineInstr &Instr : make_range(AfterCmpInstr, CmpMBB.end())) {
4267     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4268     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4269     // We should check the usage if this instruction uses and updates EFLAGS.
4270     if (!UseEFLAGS && ModifyEFLAGS) {
4271       // It is safe to remove CmpInstr if EFLAGS is updated again.
4272       FlagsMayLiveOut = false;
4273       break;
4274     }
4275     if (!UseEFLAGS && !ModifyEFLAGS)
4276       continue;
4277 
4278     // EFLAGS is used by this instruction.
4279     X86::CondCode OldCC = X86::COND_INVALID;
4280     if (MI || IsSwapped || ImmDelta != 0) {
4281       // We decode the condition code from opcode.
4282       if (Instr.isBranch())
4283         OldCC = X86::getCondFromBranch(Instr);
4284       else {
4285         OldCC = X86::getCondFromSETCC(Instr);
4286         if (OldCC == X86::COND_INVALID)
4287           OldCC = X86::getCondFromCMov(Instr);
4288       }
4289       if (OldCC == X86::COND_INVALID) return false;
4290     }
4291     X86::CondCode ReplacementCC = X86::COND_INVALID;
4292     if (MI) {
4293       switch (OldCC) {
4294       default: break;
4295       case X86::COND_A: case X86::COND_AE:
4296       case X86::COND_B: case X86::COND_BE:
4297         // CF is used, we can't perform this optimization.
4298         return false;
4299       case X86::COND_G: case X86::COND_GE:
4300       case X86::COND_L: case X86::COND_LE:
4301       case X86::COND_O: case X86::COND_NO:
4302         // If OF is used, the instruction needs to clear it like CmpZero does.
4303         if (!ClearsOverflowFlag)
4304           return false;
4305         break;
4306       case X86::COND_S: case X86::COND_NS:
4307         // If SF is used, but the instruction doesn't update the SF, then we
4308         // can't do the optimization.
4309         if (NoSignFlag)
4310           return false;
4311         break;
4312       }
4313 
4314       // If we're updating the condition code check if we have to reverse the
4315       // condition.
4316       if (ShouldUpdateCC)
4317         switch (OldCC) {
4318         default:
4319           return false;
4320         case X86::COND_E:
4321           ReplacementCC = NewCC;
4322           break;
4323         case X86::COND_NE:
4324           ReplacementCC = GetOppositeBranchCondition(NewCC);
4325           break;
4326         }
4327     } else if (IsSwapped) {
4328       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4329       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4330       // We swap the condition code and synthesize the new opcode.
4331       ReplacementCC = getSwappedCondition(OldCC);
4332       if (ReplacementCC == X86::COND_INVALID)
4333         return false;
4334       ShouldUpdateCC = true;
4335     } else if (ImmDelta != 0) {
4336       unsigned BitWidth = TRI->getRegSizeInBits(*MRI->getRegClass(SrcReg));
4337       // Shift amount for min/max constants to adjust for 8/16/32 instruction
4338       // sizes.
4339       switch (OldCC) {
4340       case X86::COND_L: // x <s (C + 1)  -->  x <=s C
4341         if (ImmDelta != 1 || APInt::getSignedMinValue(BitWidth) == CmpValue)
4342           return false;
4343         ReplacementCC = X86::COND_LE;
4344         break;
4345       case X86::COND_B: // x <u (C + 1)  -->  x <=u C
4346         if (ImmDelta != 1 || CmpValue == 0)
4347           return false;
4348         ReplacementCC = X86::COND_BE;
4349         break;
4350       case X86::COND_GE: // x >=s (C + 1)  -->  x >s C
4351         if (ImmDelta != 1 || APInt::getSignedMinValue(BitWidth) == CmpValue)
4352           return false;
4353         ReplacementCC = X86::COND_G;
4354         break;
4355       case X86::COND_AE: // x >=u (C + 1)  -->  x >u C
4356         if (ImmDelta != 1 || CmpValue == 0)
4357           return false;
4358         ReplacementCC = X86::COND_A;
4359         break;
4360       case X86::COND_G: // x >s (C - 1)  -->  x >=s C
4361         if (ImmDelta != -1 || APInt::getSignedMaxValue(BitWidth) == CmpValue)
4362           return false;
4363         ReplacementCC = X86::COND_GE;
4364         break;
4365       case X86::COND_A: // x >u (C - 1)  -->  x >=u C
4366         if (ImmDelta != -1 || APInt::getMaxValue(BitWidth) == CmpValue)
4367           return false;
4368         ReplacementCC = X86::COND_AE;
4369         break;
4370       case X86::COND_LE: // x <=s (C - 1)  -->  x <s C
4371         if (ImmDelta != -1 || APInt::getSignedMaxValue(BitWidth) == CmpValue)
4372           return false;
4373         ReplacementCC = X86::COND_L;
4374         break;
4375       case X86::COND_BE: // x <=u (C - 1)  -->  x <u C
4376         if (ImmDelta != -1 || APInt::getMaxValue(BitWidth) == CmpValue)
4377           return false;
4378         ReplacementCC = X86::COND_B;
4379         break;
4380       default:
4381         return false;
4382       }
4383       ShouldUpdateCC = true;
4384     }
4385 
4386     if (ShouldUpdateCC && ReplacementCC != OldCC) {
4387       // Push the MachineInstr to OpsToUpdate.
4388       // If it is safe to remove CmpInstr, the condition code of these
4389       // instructions will be modified.
4390       OpsToUpdate.push_back(std::make_pair(&Instr, ReplacementCC));
4391     }
4392     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4393       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4394       FlagsMayLiveOut = false;
4395       break;
4396     }
4397   }
4398 
4399   // If we have to update users but EFLAGS is live-out abort, since we cannot
4400   // easily find all of the users.
4401   if ((MI != nullptr || ShouldUpdateCC) && FlagsMayLiveOut) {
4402     for (MachineBasicBlock *Successor : CmpMBB.successors())
4403       if (Successor->isLiveIn(X86::EFLAGS))
4404         return false;
4405   }
4406 
4407   // The instruction to be updated is either Sub or MI.
4408   assert((MI == nullptr || Sub == nullptr) && "Should not have Sub and MI set");
4409   Sub = MI != nullptr ? MI : Sub;
4410   MachineBasicBlock *SubBB = Sub->getParent();
4411   // Move Movr0Inst to the appropriate place before Sub.
4412   if (Movr0Inst) {
4413     // Only move within the same block so we don't accidentally move to a
4414     // block with higher execution frequency.
4415     if (&CmpMBB != SubBB)
4416       return false;
4417     // Look backwards until we find a def that doesn't use the current EFLAGS.
4418     MachineBasicBlock::reverse_iterator InsertI = Sub,
4419                                         InsertE = Sub->getParent()->rend();
4420     for (; InsertI != InsertE; ++InsertI) {
4421       MachineInstr *Instr = &*InsertI;
4422       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4423           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4424         Movr0Inst->getParent()->remove(Movr0Inst);
4425         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4426                                    Movr0Inst);
4427         break;
4428       }
4429     }
4430     if (InsertI == InsertE)
4431       return false;
4432   }
4433 
4434   // Make sure Sub instruction defines EFLAGS and mark the def live.
4435   MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
4436   assert(FlagDef && "Unable to locate a def EFLAGS operand");
4437   FlagDef->setIsDead(false);
4438 
4439   CmpInstr.eraseFromParent();
4440 
4441   // Modify the condition code of instructions in OpsToUpdate.
4442   for (auto &Op : OpsToUpdate) {
4443     Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
4444         .setImm(Op.second);
4445   }
4446   // Add EFLAGS to block live-ins between CmpBB and block of flags producer.
4447   for (MachineBasicBlock *MBB = &CmpMBB; MBB != SubBB;
4448        MBB = *MBB->pred_begin()) {
4449     assert(MBB->pred_size() == 1 && "Expected exactly one predecessor");
4450     if (!MBB->isLiveIn(X86::EFLAGS))
4451       MBB->addLiveIn(X86::EFLAGS);
4452   }
4453   return true;
4454 }
4455 
4456 /// Try to remove the load by folding it to a register
4457 /// operand at the use. We fold the load instructions if load defines a virtual
4458 /// register, the virtual register is used once in the same BB, and the
4459 /// instructions in-between do not load or store, and have no side effects.
4460 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
4461                                               const MachineRegisterInfo *MRI,
4462                                               Register &FoldAsLoadDefReg,
4463                                               MachineInstr *&DefMI) const {
4464   // Check whether we can move DefMI here.
4465   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4466   assert(DefMI);
4467   bool SawStore = false;
4468   if (!DefMI->isSafeToMove(nullptr, SawStore))
4469     return nullptr;
4470 
4471   // Collect information about virtual register operands of MI.
4472   SmallVector<unsigned, 1> SrcOperandIds;
4473   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4474     MachineOperand &MO = MI.getOperand(i);
4475     if (!MO.isReg())
4476       continue;
4477     Register Reg = MO.getReg();
4478     if (Reg != FoldAsLoadDefReg)
4479       continue;
4480     // Do not fold if we have a subreg use or a def.
4481     if (MO.getSubReg() || MO.isDef())
4482       return nullptr;
4483     SrcOperandIds.push_back(i);
4484   }
4485   if (SrcOperandIds.empty())
4486     return nullptr;
4487 
4488   // Check whether we can fold the def into SrcOperandId.
4489   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
4490     FoldAsLoadDefReg = 0;
4491     return FoldMI;
4492   }
4493 
4494   return nullptr;
4495 }
4496 
4497 /// Expand a single-def pseudo instruction to a two-addr
4498 /// instruction with two undef reads of the register being defined.
4499 /// This is used for mapping:
4500 ///   %xmm4 = V_SET0
4501 /// to:
4502 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
4503 ///
4504 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4505                              const MCInstrDesc &Desc) {
4506   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4507   Register Reg = MIB.getReg(0);
4508   MIB->setDesc(Desc);
4509 
4510   // MachineInstr::addOperand() will insert explicit operands before any
4511   // implicit operands.
4512   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4513   // But we don't trust that.
4514   assert(MIB.getReg(1) == Reg &&
4515          MIB.getReg(2) == Reg && "Misplaced operand");
4516   return true;
4517 }
4518 
4519 /// Expand a single-def pseudo instruction to a two-addr
4520 /// instruction with two %k0 reads.
4521 /// This is used for mapping:
4522 ///   %k4 = K_SET1
4523 /// to:
4524 ///   %k4 = KXNORrr %k0, %k0
4525 static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
4526                             Register Reg) {
4527   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4528   MIB->setDesc(Desc);
4529   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4530   return true;
4531 }
4532 
4533 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
4534                           bool MinusOne) {
4535   MachineBasicBlock &MBB = *MIB->getParent();
4536   const DebugLoc &DL = MIB->getDebugLoc();
4537   Register Reg = MIB.getReg(0);
4538 
4539   // Insert the XOR.
4540   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
4541       .addReg(Reg, RegState::Undef)
4542       .addReg(Reg, RegState::Undef);
4543 
4544   // Turn the pseudo into an INC or DEC.
4545   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
4546   MIB.addReg(Reg);
4547 
4548   return true;
4549 }
4550 
4551 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
4552                                const TargetInstrInfo &TII,
4553                                const X86Subtarget &Subtarget) {
4554   MachineBasicBlock &MBB = *MIB->getParent();
4555   const DebugLoc &DL = MIB->getDebugLoc();
4556   int64_t Imm = MIB->getOperand(1).getImm();
4557   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
4558   MachineBasicBlock::iterator I = MIB.getInstr();
4559 
4560   int StackAdjustment;
4561 
4562   if (Subtarget.is64Bit()) {
4563     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
4564            MIB->getOpcode() == X86::MOV32ImmSExti8);
4565 
4566     // Can't use push/pop lowering if the function might write to the red zone.
4567     X86MachineFunctionInfo *X86FI =
4568         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
4569     if (X86FI->getUsesRedZone()) {
4570       MIB->setDesc(TII.get(MIB->getOpcode() ==
4571                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
4572       return true;
4573     }
4574 
4575     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4576     // widen the register if necessary.
4577     StackAdjustment = 8;
4578     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4579     MIB->setDesc(TII.get(X86::POP64r));
4580     MIB->getOperand(0)
4581         .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
4582   } else {
4583     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
4584     StackAdjustment = 4;
4585     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4586     MIB->setDesc(TII.get(X86::POP32r));
4587   }
4588   MIB->removeOperand(1);
4589   MIB->addImplicitDefUseOperands(*MBB.getParent());
4590 
4591   // Build CFI if necessary.
4592   MachineFunction &MF = *MBB.getParent();
4593   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4594   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4595   bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
4596   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4597   if (EmitCFI) {
4598     TFL->BuildCFI(MBB, I, DL,
4599         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4600     TFL->BuildCFI(MBB, std::next(I), DL,
4601         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4602   }
4603 
4604   return true;
4605 }
4606 
4607 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4608 // code sequence is needed for other targets.
4609 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4610                                  const TargetInstrInfo &TII) {
4611   MachineBasicBlock &MBB = *MIB->getParent();
4612   const DebugLoc &DL = MIB->getDebugLoc();
4613   Register Reg = MIB.getReg(0);
4614   const GlobalValue *GV =
4615       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4616   auto Flags = MachineMemOperand::MOLoad |
4617                MachineMemOperand::MODereferenceable |
4618                MachineMemOperand::MOInvariant;
4619   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4620       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, Align(8));
4621   MachineBasicBlock::iterator I = MIB.getInstr();
4622 
4623   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4624       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4625       .addMemOperand(MMO);
4626   MIB->setDebugLoc(DL);
4627   MIB->setDesc(TII.get(X86::MOV64rm));
4628   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4629 }
4630 
4631 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4632   MachineBasicBlock &MBB = *MIB->getParent();
4633   MachineFunction &MF = *MBB.getParent();
4634   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4635   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4636   unsigned XorOp =
4637       MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4638   MIB->setDesc(TII.get(XorOp));
4639   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4640   return true;
4641 }
4642 
4643 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4644 // but not VLX. If it uses an extended register we need to use an instruction
4645 // that loads the lower 128/256-bit, but is available with only AVX512F.
4646 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4647                             const TargetRegisterInfo *TRI,
4648                             const MCInstrDesc &LoadDesc,
4649                             const MCInstrDesc &BroadcastDesc,
4650                             unsigned SubIdx) {
4651   Register DestReg = MIB.getReg(0);
4652   // Check if DestReg is XMM16-31 or YMM16-31.
4653   if (TRI->getEncodingValue(DestReg) < 16) {
4654     // We can use a normal VEX encoded load.
4655     MIB->setDesc(LoadDesc);
4656   } else {
4657     // Use a 128/256-bit VBROADCAST instruction.
4658     MIB->setDesc(BroadcastDesc);
4659     // Change the destination to a 512-bit register.
4660     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4661     MIB->getOperand(0).setReg(DestReg);
4662   }
4663   return true;
4664 }
4665 
4666 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4667 // but not VLX. If it uses an extended register we need to use an instruction
4668 // that stores the lower 128/256-bit, but is available with only AVX512F.
4669 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4670                              const TargetRegisterInfo *TRI,
4671                              const MCInstrDesc &StoreDesc,
4672                              const MCInstrDesc &ExtractDesc,
4673                              unsigned SubIdx) {
4674   Register SrcReg = MIB.getReg(X86::AddrNumOperands);
4675   // Check if DestReg is XMM16-31 or YMM16-31.
4676   if (TRI->getEncodingValue(SrcReg) < 16) {
4677     // We can use a normal VEX encoded store.
4678     MIB->setDesc(StoreDesc);
4679   } else {
4680     // Use a VEXTRACTF instruction.
4681     MIB->setDesc(ExtractDesc);
4682     // Change the destination to a 512-bit register.
4683     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4684     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4685     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4686   }
4687 
4688   return true;
4689 }
4690 
4691 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4692   MIB->setDesc(Desc);
4693   int64_t ShiftAmt = MIB->getOperand(2).getImm();
4694   // Temporarily remove the immediate so we can add another source register.
4695   MIB->removeOperand(2);
4696   // Add the register. Don't copy the kill flag if there is one.
4697   MIB.addReg(MIB.getReg(1),
4698              getUndefRegState(MIB->getOperand(1).isUndef()));
4699   // Add back the immediate.
4700   MIB.addImm(ShiftAmt);
4701   return true;
4702 }
4703 
4704 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4705   bool HasAVX = Subtarget.hasAVX();
4706   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4707   switch (MI.getOpcode()) {
4708   case X86::MOV32r0:
4709     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4710   case X86::MOV32r1:
4711     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4712   case X86::MOV32r_1:
4713     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4714   case X86::MOV32ImmSExti8:
4715   case X86::MOV64ImmSExti8:
4716     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4717   case X86::SETB_C32r:
4718     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4719   case X86::SETB_C64r:
4720     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4721   case X86::MMX_SET0:
4722     return Expand2AddrUndef(MIB, get(X86::MMX_PXORrr));
4723   case X86::V_SET0:
4724   case X86::FsFLD0SS:
4725   case X86::FsFLD0SD:
4726   case X86::FsFLD0F128:
4727     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4728   case X86::AVX_SET0: {
4729     assert(HasAVX && "AVX not supported");
4730     const TargetRegisterInfo *TRI = &getRegisterInfo();
4731     Register SrcReg = MIB.getReg(0);
4732     Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4733     MIB->getOperand(0).setReg(XReg);
4734     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4735     MIB.addReg(SrcReg, RegState::ImplicitDefine);
4736     return true;
4737   }
4738   case X86::AVX512_128_SET0:
4739   case X86::AVX512_FsFLD0SH:
4740   case X86::AVX512_FsFLD0SS:
4741   case X86::AVX512_FsFLD0SD:
4742   case X86::AVX512_FsFLD0F128: {
4743     bool HasVLX = Subtarget.hasVLX();
4744     Register SrcReg = MIB.getReg(0);
4745     const TargetRegisterInfo *TRI = &getRegisterInfo();
4746     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4747       return Expand2AddrUndef(MIB,
4748                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4749     // Extended register without VLX. Use a larger XOR.
4750     SrcReg =
4751         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4752     MIB->getOperand(0).setReg(SrcReg);
4753     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4754   }
4755   case X86::AVX512_256_SET0:
4756   case X86::AVX512_512_SET0: {
4757     bool HasVLX = Subtarget.hasVLX();
4758     Register SrcReg = MIB.getReg(0);
4759     const TargetRegisterInfo *TRI = &getRegisterInfo();
4760     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4761       Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4762       MIB->getOperand(0).setReg(XReg);
4763       Expand2AddrUndef(MIB,
4764                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4765       MIB.addReg(SrcReg, RegState::ImplicitDefine);
4766       return true;
4767     }
4768     if (MI.getOpcode() == X86::AVX512_256_SET0) {
4769       // No VLX so we must reference a zmm.
4770       unsigned ZReg =
4771         TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4772       MIB->getOperand(0).setReg(ZReg);
4773     }
4774     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4775   }
4776   case X86::V_SETALLONES:
4777     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4778   case X86::AVX2_SETALLONES:
4779     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4780   case X86::AVX1_SETALLONES: {
4781     Register Reg = MIB.getReg(0);
4782     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4783     MIB->setDesc(get(X86::VCMPPSYrri));
4784     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4785     return true;
4786   }
4787   case X86::AVX512_512_SETALLONES: {
4788     Register Reg = MIB.getReg(0);
4789     MIB->setDesc(get(X86::VPTERNLOGDZrri));
4790     // VPTERNLOGD needs 3 register inputs and an immediate.
4791     // 0xff will return 1s for any input.
4792     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4793        .addReg(Reg, RegState::Undef).addImm(0xff);
4794     return true;
4795   }
4796   case X86::AVX512_512_SEXT_MASK_32:
4797   case X86::AVX512_512_SEXT_MASK_64: {
4798     Register Reg = MIB.getReg(0);
4799     Register MaskReg = MIB.getReg(1);
4800     unsigned MaskState = getRegState(MIB->getOperand(1));
4801     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4802                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4803     MI.removeOperand(1);
4804     MIB->setDesc(get(Opc));
4805     // VPTERNLOG needs 3 register inputs and an immediate.
4806     // 0xff will return 1s for any input.
4807     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4808        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4809     return true;
4810   }
4811   case X86::VMOVAPSZ128rm_NOVLX:
4812     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4813                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4814   case X86::VMOVUPSZ128rm_NOVLX:
4815     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4816                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4817   case X86::VMOVAPSZ256rm_NOVLX:
4818     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4819                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4820   case X86::VMOVUPSZ256rm_NOVLX:
4821     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4822                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4823   case X86::VMOVAPSZ128mr_NOVLX:
4824     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4825                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4826   case X86::VMOVUPSZ128mr_NOVLX:
4827     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4828                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4829   case X86::VMOVAPSZ256mr_NOVLX:
4830     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4831                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4832   case X86::VMOVUPSZ256mr_NOVLX:
4833     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4834                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4835   case X86::MOV32ri64: {
4836     Register Reg = MIB.getReg(0);
4837     Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4838     MI.setDesc(get(X86::MOV32ri));
4839     MIB->getOperand(0).setReg(Reg32);
4840     MIB.addReg(Reg, RegState::ImplicitDefine);
4841     return true;
4842   }
4843 
4844   // KNL does not recognize dependency-breaking idioms for mask registers,
4845   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4846   // Using %k0 as the undef input register is a performance heuristic based
4847   // on the assumption that %k0 is used less frequently than the other mask
4848   // registers, since it is not usable as a write mask.
4849   // FIXME: A more advanced approach would be to choose the best input mask
4850   // register based on context.
4851   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4852   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4853   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4854   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4855   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4856   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4857   case TargetOpcode::LOAD_STACK_GUARD:
4858     expandLoadStackGuard(MIB, *this);
4859     return true;
4860   case X86::XOR64_FP:
4861   case X86::XOR32_FP:
4862     return expandXorFP(MIB, *this);
4863   case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4864   case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4865   case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4866   case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4867   case X86::ADD8rr_DB:    MIB->setDesc(get(X86::OR8rr));    break;
4868   case X86::ADD16rr_DB:   MIB->setDesc(get(X86::OR16rr));   break;
4869   case X86::ADD32rr_DB:   MIB->setDesc(get(X86::OR32rr));   break;
4870   case X86::ADD64rr_DB:   MIB->setDesc(get(X86::OR64rr));   break;
4871   case X86::ADD8ri_DB:    MIB->setDesc(get(X86::OR8ri));    break;
4872   case X86::ADD16ri_DB:   MIB->setDesc(get(X86::OR16ri));   break;
4873   case X86::ADD32ri_DB:   MIB->setDesc(get(X86::OR32ri));   break;
4874   case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4875   case X86::ADD16ri8_DB:  MIB->setDesc(get(X86::OR16ri8));  break;
4876   case X86::ADD32ri8_DB:  MIB->setDesc(get(X86::OR32ri8));  break;
4877   case X86::ADD64ri8_DB:  MIB->setDesc(get(X86::OR64ri8));  break;
4878   }
4879   return false;
4880 }
4881 
4882 /// Return true for all instructions that only update
4883 /// the first 32 or 64-bits of the destination register and leave the rest
4884 /// unmodified. This can be used to avoid folding loads if the instructions
4885 /// only update part of the destination register, and the non-updated part is
4886 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4887 /// instructions breaks the partial register dependency and it can improve
4888 /// performance. e.g.:
4889 ///
4890 ///   movss (%rdi), %xmm0
4891 ///   cvtss2sd %xmm0, %xmm0
4892 ///
4893 /// Instead of
4894 ///   cvtss2sd (%rdi), %xmm0
4895 ///
4896 /// FIXME: This should be turned into a TSFlags.
4897 ///
4898 static bool hasPartialRegUpdate(unsigned Opcode,
4899                                 const X86Subtarget &Subtarget,
4900                                 bool ForLoadFold = false) {
4901   switch (Opcode) {
4902   case X86::CVTSI2SSrr:
4903   case X86::CVTSI2SSrm:
4904   case X86::CVTSI642SSrr:
4905   case X86::CVTSI642SSrm:
4906   case X86::CVTSI2SDrr:
4907   case X86::CVTSI2SDrm:
4908   case X86::CVTSI642SDrr:
4909   case X86::CVTSI642SDrm:
4910     // Load folding won't effect the undef register update since the input is
4911     // a GPR.
4912     return !ForLoadFold;
4913   case X86::CVTSD2SSrr:
4914   case X86::CVTSD2SSrm:
4915   case X86::CVTSS2SDrr:
4916   case X86::CVTSS2SDrm:
4917   case X86::MOVHPDrm:
4918   case X86::MOVHPSrm:
4919   case X86::MOVLPDrm:
4920   case X86::MOVLPSrm:
4921   case X86::RCPSSr:
4922   case X86::RCPSSm:
4923   case X86::RCPSSr_Int:
4924   case X86::RCPSSm_Int:
4925   case X86::ROUNDSDr:
4926   case X86::ROUNDSDm:
4927   case X86::ROUNDSSr:
4928   case X86::ROUNDSSm:
4929   case X86::RSQRTSSr:
4930   case X86::RSQRTSSm:
4931   case X86::RSQRTSSr_Int:
4932   case X86::RSQRTSSm_Int:
4933   case X86::SQRTSSr:
4934   case X86::SQRTSSm:
4935   case X86::SQRTSSr_Int:
4936   case X86::SQRTSSm_Int:
4937   case X86::SQRTSDr:
4938   case X86::SQRTSDm:
4939   case X86::SQRTSDr_Int:
4940   case X86::SQRTSDm_Int:
4941     return true;
4942   // GPR
4943   case X86::POPCNT32rm:
4944   case X86::POPCNT32rr:
4945   case X86::POPCNT64rm:
4946   case X86::POPCNT64rr:
4947     return Subtarget.hasPOPCNTFalseDeps();
4948   case X86::LZCNT32rm:
4949   case X86::LZCNT32rr:
4950   case X86::LZCNT64rm:
4951   case X86::LZCNT64rr:
4952   case X86::TZCNT32rm:
4953   case X86::TZCNT32rr:
4954   case X86::TZCNT64rm:
4955   case X86::TZCNT64rr:
4956     return Subtarget.hasLZCNTFalseDeps();
4957   }
4958 
4959   return false;
4960 }
4961 
4962 /// Inform the BreakFalseDeps pass how many idle
4963 /// instructions we would like before a partial register update.
4964 unsigned X86InstrInfo::getPartialRegUpdateClearance(
4965     const MachineInstr &MI, unsigned OpNum,
4966     const TargetRegisterInfo *TRI) const {
4967   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4968     return 0;
4969 
4970   // If MI is marked as reading Reg, the partial register update is wanted.
4971   const MachineOperand &MO = MI.getOperand(0);
4972   Register Reg = MO.getReg();
4973   if (Reg.isVirtual()) {
4974     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4975       return 0;
4976   } else {
4977     if (MI.readsRegister(Reg, TRI))
4978       return 0;
4979   }
4980 
4981   // If any instructions in the clearance range are reading Reg, insert a
4982   // dependency breaking instruction, which is inexpensive and is likely to
4983   // be hidden in other instruction's cycles.
4984   return PartialRegUpdateClearance;
4985 }
4986 
4987 // Return true for any instruction the copies the high bits of the first source
4988 // operand into the unused high bits of the destination operand.
4989 // Also returns true for instructions that have two inputs where one may
4990 // be undef and we want it to use the same register as the other input.
4991 static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
4992                               bool ForLoadFold = false) {
4993   // Set the OpNum parameter to the first source operand.
4994   switch (Opcode) {
4995   case X86::MMX_PUNPCKHBWrr:
4996   case X86::MMX_PUNPCKHWDrr:
4997   case X86::MMX_PUNPCKHDQrr:
4998   case X86::MMX_PUNPCKLBWrr:
4999   case X86::MMX_PUNPCKLWDrr:
5000   case X86::MMX_PUNPCKLDQrr:
5001   case X86::MOVHLPSrr:
5002   case X86::PACKSSWBrr:
5003   case X86::PACKUSWBrr:
5004   case X86::PACKSSDWrr:
5005   case X86::PACKUSDWrr:
5006   case X86::PUNPCKHBWrr:
5007   case X86::PUNPCKLBWrr:
5008   case X86::PUNPCKHWDrr:
5009   case X86::PUNPCKLWDrr:
5010   case X86::PUNPCKHDQrr:
5011   case X86::PUNPCKLDQrr:
5012   case X86::PUNPCKHQDQrr:
5013   case X86::PUNPCKLQDQrr:
5014   case X86::SHUFPDrri:
5015   case X86::SHUFPSrri:
5016     // These instructions are sometimes used with an undef first or second
5017     // source. Return true here so BreakFalseDeps will assign this source to the
5018     // same register as the first source to avoid a false dependency.
5019     // Operand 1 of these instructions is tied so they're separate from their
5020     // VEX counterparts.
5021     return OpNum == 2 && !ForLoadFold;
5022 
5023   case X86::VMOVLHPSrr:
5024   case X86::VMOVLHPSZrr:
5025   case X86::VPACKSSWBrr:
5026   case X86::VPACKUSWBrr:
5027   case X86::VPACKSSDWrr:
5028   case X86::VPACKUSDWrr:
5029   case X86::VPACKSSWBZ128rr:
5030   case X86::VPACKUSWBZ128rr:
5031   case X86::VPACKSSDWZ128rr:
5032   case X86::VPACKUSDWZ128rr:
5033   case X86::VPERM2F128rr:
5034   case X86::VPERM2I128rr:
5035   case X86::VSHUFF32X4Z256rri:
5036   case X86::VSHUFF32X4Zrri:
5037   case X86::VSHUFF64X2Z256rri:
5038   case X86::VSHUFF64X2Zrri:
5039   case X86::VSHUFI32X4Z256rri:
5040   case X86::VSHUFI32X4Zrri:
5041   case X86::VSHUFI64X2Z256rri:
5042   case X86::VSHUFI64X2Zrri:
5043   case X86::VPUNPCKHBWrr:
5044   case X86::VPUNPCKLBWrr:
5045   case X86::VPUNPCKHBWYrr:
5046   case X86::VPUNPCKLBWYrr:
5047   case X86::VPUNPCKHBWZ128rr:
5048   case X86::VPUNPCKLBWZ128rr:
5049   case X86::VPUNPCKHBWZ256rr:
5050   case X86::VPUNPCKLBWZ256rr:
5051   case X86::VPUNPCKHBWZrr:
5052   case X86::VPUNPCKLBWZrr:
5053   case X86::VPUNPCKHWDrr:
5054   case X86::VPUNPCKLWDrr:
5055   case X86::VPUNPCKHWDYrr:
5056   case X86::VPUNPCKLWDYrr:
5057   case X86::VPUNPCKHWDZ128rr:
5058   case X86::VPUNPCKLWDZ128rr:
5059   case X86::VPUNPCKHWDZ256rr:
5060   case X86::VPUNPCKLWDZ256rr:
5061   case X86::VPUNPCKHWDZrr:
5062   case X86::VPUNPCKLWDZrr:
5063   case X86::VPUNPCKHDQrr:
5064   case X86::VPUNPCKLDQrr:
5065   case X86::VPUNPCKHDQYrr:
5066   case X86::VPUNPCKLDQYrr:
5067   case X86::VPUNPCKHDQZ128rr:
5068   case X86::VPUNPCKLDQZ128rr:
5069   case X86::VPUNPCKHDQZ256rr:
5070   case X86::VPUNPCKLDQZ256rr:
5071   case X86::VPUNPCKHDQZrr:
5072   case X86::VPUNPCKLDQZrr:
5073   case X86::VPUNPCKHQDQrr:
5074   case X86::VPUNPCKLQDQrr:
5075   case X86::VPUNPCKHQDQYrr:
5076   case X86::VPUNPCKLQDQYrr:
5077   case X86::VPUNPCKHQDQZ128rr:
5078   case X86::VPUNPCKLQDQZ128rr:
5079   case X86::VPUNPCKHQDQZ256rr:
5080   case X86::VPUNPCKLQDQZ256rr:
5081   case X86::VPUNPCKHQDQZrr:
5082   case X86::VPUNPCKLQDQZrr:
5083     // These instructions are sometimes used with an undef first or second
5084     // source. Return true here so BreakFalseDeps will assign this source to the
5085     // same register as the first source to avoid a false dependency.
5086     return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
5087 
5088   case X86::VCVTSI2SSrr:
5089   case X86::VCVTSI2SSrm:
5090   case X86::VCVTSI2SSrr_Int:
5091   case X86::VCVTSI2SSrm_Int:
5092   case X86::VCVTSI642SSrr:
5093   case X86::VCVTSI642SSrm:
5094   case X86::VCVTSI642SSrr_Int:
5095   case X86::VCVTSI642SSrm_Int:
5096   case X86::VCVTSI2SDrr:
5097   case X86::VCVTSI2SDrm:
5098   case X86::VCVTSI2SDrr_Int:
5099   case X86::VCVTSI2SDrm_Int:
5100   case X86::VCVTSI642SDrr:
5101   case X86::VCVTSI642SDrm:
5102   case X86::VCVTSI642SDrr_Int:
5103   case X86::VCVTSI642SDrm_Int:
5104   // AVX-512
5105   case X86::VCVTSI2SSZrr:
5106   case X86::VCVTSI2SSZrm:
5107   case X86::VCVTSI2SSZrr_Int:
5108   case X86::VCVTSI2SSZrrb_Int:
5109   case X86::VCVTSI2SSZrm_Int:
5110   case X86::VCVTSI642SSZrr:
5111   case X86::VCVTSI642SSZrm:
5112   case X86::VCVTSI642SSZrr_Int:
5113   case X86::VCVTSI642SSZrrb_Int:
5114   case X86::VCVTSI642SSZrm_Int:
5115   case X86::VCVTSI2SDZrr:
5116   case X86::VCVTSI2SDZrm:
5117   case X86::VCVTSI2SDZrr_Int:
5118   case X86::VCVTSI2SDZrm_Int:
5119   case X86::VCVTSI642SDZrr:
5120   case X86::VCVTSI642SDZrm:
5121   case X86::VCVTSI642SDZrr_Int:
5122   case X86::VCVTSI642SDZrrb_Int:
5123   case X86::VCVTSI642SDZrm_Int:
5124   case X86::VCVTUSI2SSZrr:
5125   case X86::VCVTUSI2SSZrm:
5126   case X86::VCVTUSI2SSZrr_Int:
5127   case X86::VCVTUSI2SSZrrb_Int:
5128   case X86::VCVTUSI2SSZrm_Int:
5129   case X86::VCVTUSI642SSZrr:
5130   case X86::VCVTUSI642SSZrm:
5131   case X86::VCVTUSI642SSZrr_Int:
5132   case X86::VCVTUSI642SSZrrb_Int:
5133   case X86::VCVTUSI642SSZrm_Int:
5134   case X86::VCVTUSI2SDZrr:
5135   case X86::VCVTUSI2SDZrm:
5136   case X86::VCVTUSI2SDZrr_Int:
5137   case X86::VCVTUSI2SDZrm_Int:
5138   case X86::VCVTUSI642SDZrr:
5139   case X86::VCVTUSI642SDZrm:
5140   case X86::VCVTUSI642SDZrr_Int:
5141   case X86::VCVTUSI642SDZrrb_Int:
5142   case X86::VCVTUSI642SDZrm_Int:
5143   case X86::VCVTSI2SHZrr:
5144   case X86::VCVTSI2SHZrm:
5145   case X86::VCVTSI2SHZrr_Int:
5146   case X86::VCVTSI2SHZrrb_Int:
5147   case X86::VCVTSI2SHZrm_Int:
5148   case X86::VCVTSI642SHZrr:
5149   case X86::VCVTSI642SHZrm:
5150   case X86::VCVTSI642SHZrr_Int:
5151   case X86::VCVTSI642SHZrrb_Int:
5152   case X86::VCVTSI642SHZrm_Int:
5153   case X86::VCVTUSI2SHZrr:
5154   case X86::VCVTUSI2SHZrm:
5155   case X86::VCVTUSI2SHZrr_Int:
5156   case X86::VCVTUSI2SHZrrb_Int:
5157   case X86::VCVTUSI2SHZrm_Int:
5158   case X86::VCVTUSI642SHZrr:
5159   case X86::VCVTUSI642SHZrm:
5160   case X86::VCVTUSI642SHZrr_Int:
5161   case X86::VCVTUSI642SHZrrb_Int:
5162   case X86::VCVTUSI642SHZrm_Int:
5163     // Load folding won't effect the undef register update since the input is
5164     // a GPR.
5165     return OpNum == 1 && !ForLoadFold;
5166   case X86::VCVTSD2SSrr:
5167   case X86::VCVTSD2SSrm:
5168   case X86::VCVTSD2SSrr_Int:
5169   case X86::VCVTSD2SSrm_Int:
5170   case X86::VCVTSS2SDrr:
5171   case X86::VCVTSS2SDrm:
5172   case X86::VCVTSS2SDrr_Int:
5173   case X86::VCVTSS2SDrm_Int:
5174   case X86::VRCPSSr:
5175   case X86::VRCPSSr_Int:
5176   case X86::VRCPSSm:
5177   case X86::VRCPSSm_Int:
5178   case X86::VROUNDSDr:
5179   case X86::VROUNDSDm:
5180   case X86::VROUNDSDr_Int:
5181   case X86::VROUNDSDm_Int:
5182   case X86::VROUNDSSr:
5183   case X86::VROUNDSSm:
5184   case X86::VROUNDSSr_Int:
5185   case X86::VROUNDSSm_Int:
5186   case X86::VRSQRTSSr:
5187   case X86::VRSQRTSSr_Int:
5188   case X86::VRSQRTSSm:
5189   case X86::VRSQRTSSm_Int:
5190   case X86::VSQRTSSr:
5191   case X86::VSQRTSSr_Int:
5192   case X86::VSQRTSSm:
5193   case X86::VSQRTSSm_Int:
5194   case X86::VSQRTSDr:
5195   case X86::VSQRTSDr_Int:
5196   case X86::VSQRTSDm:
5197   case X86::VSQRTSDm_Int:
5198   // AVX-512
5199   case X86::VCVTSD2SSZrr:
5200   case X86::VCVTSD2SSZrr_Int:
5201   case X86::VCVTSD2SSZrrb_Int:
5202   case X86::VCVTSD2SSZrm:
5203   case X86::VCVTSD2SSZrm_Int:
5204   case X86::VCVTSS2SDZrr:
5205   case X86::VCVTSS2SDZrr_Int:
5206   case X86::VCVTSS2SDZrrb_Int:
5207   case X86::VCVTSS2SDZrm:
5208   case X86::VCVTSS2SDZrm_Int:
5209   case X86::VGETEXPSDZr:
5210   case X86::VGETEXPSDZrb:
5211   case X86::VGETEXPSDZm:
5212   case X86::VGETEXPSSZr:
5213   case X86::VGETEXPSSZrb:
5214   case X86::VGETEXPSSZm:
5215   case X86::VGETMANTSDZrri:
5216   case X86::VGETMANTSDZrrib:
5217   case X86::VGETMANTSDZrmi:
5218   case X86::VGETMANTSSZrri:
5219   case X86::VGETMANTSSZrrib:
5220   case X86::VGETMANTSSZrmi:
5221   case X86::VRNDSCALESDZr:
5222   case X86::VRNDSCALESDZr_Int:
5223   case X86::VRNDSCALESDZrb_Int:
5224   case X86::VRNDSCALESDZm:
5225   case X86::VRNDSCALESDZm_Int:
5226   case X86::VRNDSCALESSZr:
5227   case X86::VRNDSCALESSZr_Int:
5228   case X86::VRNDSCALESSZrb_Int:
5229   case X86::VRNDSCALESSZm:
5230   case X86::VRNDSCALESSZm_Int:
5231   case X86::VRCP14SDZrr:
5232   case X86::VRCP14SDZrm:
5233   case X86::VRCP14SSZrr:
5234   case X86::VRCP14SSZrm:
5235   case X86::VRCPSHZrr:
5236   case X86::VRCPSHZrm:
5237   case X86::VRSQRTSHZrr:
5238   case X86::VRSQRTSHZrm:
5239   case X86::VREDUCESHZrmi:
5240   case X86::VREDUCESHZrri:
5241   case X86::VREDUCESHZrrib:
5242   case X86::VGETEXPSHZr:
5243   case X86::VGETEXPSHZrb:
5244   case X86::VGETEXPSHZm:
5245   case X86::VGETMANTSHZrri:
5246   case X86::VGETMANTSHZrrib:
5247   case X86::VGETMANTSHZrmi:
5248   case X86::VRNDSCALESHZr:
5249   case X86::VRNDSCALESHZr_Int:
5250   case X86::VRNDSCALESHZrb_Int:
5251   case X86::VRNDSCALESHZm:
5252   case X86::VRNDSCALESHZm_Int:
5253   case X86::VSQRTSHZr:
5254   case X86::VSQRTSHZr_Int:
5255   case X86::VSQRTSHZrb_Int:
5256   case X86::VSQRTSHZm:
5257   case X86::VSQRTSHZm_Int:
5258   case X86::VRCP28SDZr:
5259   case X86::VRCP28SDZrb:
5260   case X86::VRCP28SDZm:
5261   case X86::VRCP28SSZr:
5262   case X86::VRCP28SSZrb:
5263   case X86::VRCP28SSZm:
5264   case X86::VREDUCESSZrmi:
5265   case X86::VREDUCESSZrri:
5266   case X86::VREDUCESSZrrib:
5267   case X86::VRSQRT14SDZrr:
5268   case X86::VRSQRT14SDZrm:
5269   case X86::VRSQRT14SSZrr:
5270   case X86::VRSQRT14SSZrm:
5271   case X86::VRSQRT28SDZr:
5272   case X86::VRSQRT28SDZrb:
5273   case X86::VRSQRT28SDZm:
5274   case X86::VRSQRT28SSZr:
5275   case X86::VRSQRT28SSZrb:
5276   case X86::VRSQRT28SSZm:
5277   case X86::VSQRTSSZr:
5278   case X86::VSQRTSSZr_Int:
5279   case X86::VSQRTSSZrb_Int:
5280   case X86::VSQRTSSZm:
5281   case X86::VSQRTSSZm_Int:
5282   case X86::VSQRTSDZr:
5283   case X86::VSQRTSDZr_Int:
5284   case X86::VSQRTSDZrb_Int:
5285   case X86::VSQRTSDZm:
5286   case X86::VSQRTSDZm_Int:
5287   case X86::VCVTSD2SHZrr:
5288   case X86::VCVTSD2SHZrr_Int:
5289   case X86::VCVTSD2SHZrrb_Int:
5290   case X86::VCVTSD2SHZrm:
5291   case X86::VCVTSD2SHZrm_Int:
5292   case X86::VCVTSS2SHZrr:
5293   case X86::VCVTSS2SHZrr_Int:
5294   case X86::VCVTSS2SHZrrb_Int:
5295   case X86::VCVTSS2SHZrm:
5296   case X86::VCVTSS2SHZrm_Int:
5297   case X86::VCVTSH2SDZrr:
5298   case X86::VCVTSH2SDZrr_Int:
5299   case X86::VCVTSH2SDZrrb_Int:
5300   case X86::VCVTSH2SDZrm:
5301   case X86::VCVTSH2SDZrm_Int:
5302   case X86::VCVTSH2SSZrr:
5303   case X86::VCVTSH2SSZrr_Int:
5304   case X86::VCVTSH2SSZrrb_Int:
5305   case X86::VCVTSH2SSZrm:
5306   case X86::VCVTSH2SSZrm_Int:
5307     return OpNum == 1;
5308   case X86::VMOVSSZrrk:
5309   case X86::VMOVSDZrrk:
5310     return OpNum == 3 && !ForLoadFold;
5311   case X86::VMOVSSZrrkz:
5312   case X86::VMOVSDZrrkz:
5313     return OpNum == 2 && !ForLoadFold;
5314   }
5315 
5316   return false;
5317 }
5318 
5319 /// Inform the BreakFalseDeps pass how many idle instructions we would like
5320 /// before certain undef register reads.
5321 ///
5322 /// This catches the VCVTSI2SD family of instructions:
5323 ///
5324 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
5325 ///
5326 /// We should to be careful *not* to catch VXOR idioms which are presumably
5327 /// handled specially in the pipeline:
5328 ///
5329 /// vxorps undef %xmm1, undef %xmm1, %xmm1
5330 ///
5331 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5332 /// high bits that are passed-through are not live.
5333 unsigned
5334 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
5335                                    const TargetRegisterInfo *TRI) const {
5336   const MachineOperand &MO = MI.getOperand(OpNum);
5337   if (Register::isPhysicalRegister(MO.getReg()) &&
5338       hasUndefRegUpdate(MI.getOpcode(), OpNum))
5339     return UndefRegClearance;
5340 
5341   return 0;
5342 }
5343 
5344 void X86InstrInfo::breakPartialRegDependency(
5345     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5346   Register Reg = MI.getOperand(OpNum).getReg();
5347   // If MI kills this register, the false dependence is already broken.
5348   if (MI.killsRegister(Reg, TRI))
5349     return;
5350 
5351   if (X86::VR128RegClass.contains(Reg)) {
5352     // These instructions are all floating point domain, so xorps is the best
5353     // choice.
5354     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
5355     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
5356         .addReg(Reg, RegState::Undef)
5357         .addReg(Reg, RegState::Undef);
5358     MI.addRegisterKilled(Reg, TRI, true);
5359   } else if (X86::VR256RegClass.contains(Reg)) {
5360     // Use vxorps to clear the full ymm register.
5361     // It wants to read and write the xmm sub-register.
5362     Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5363     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
5364         .addReg(XReg, RegState::Undef)
5365         .addReg(XReg, RegState::Undef)
5366         .addReg(Reg, RegState::ImplicitDefine);
5367     MI.addRegisterKilled(Reg, TRI, true);
5368   } else if (X86::GR64RegClass.contains(Reg)) {
5369     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
5370     // as well.
5371     Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
5372     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
5373         .addReg(XReg, RegState::Undef)
5374         .addReg(XReg, RegState::Undef)
5375         .addReg(Reg, RegState::ImplicitDefine);
5376     MI.addRegisterKilled(Reg, TRI, true);
5377   } else if (X86::GR32RegClass.contains(Reg)) {
5378     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
5379         .addReg(Reg, RegState::Undef)
5380         .addReg(Reg, RegState::Undef);
5381     MI.addRegisterKilled(Reg, TRI, true);
5382   }
5383 }
5384 
5385 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5386                         int PtrOffset = 0) {
5387   unsigned NumAddrOps = MOs.size();
5388 
5389   if (NumAddrOps < 4) {
5390     // FrameIndex only - add an immediate offset (whether its zero or not).
5391     for (unsigned i = 0; i != NumAddrOps; ++i)
5392       MIB.add(MOs[i]);
5393     addOffset(MIB, PtrOffset);
5394   } else {
5395     // General Memory Addressing - we need to add any offset to an existing
5396     // offset.
5397     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5398     for (unsigned i = 0; i != NumAddrOps; ++i) {
5399       const MachineOperand &MO = MOs[i];
5400       if (i == 3 && PtrOffset != 0) {
5401         MIB.addDisp(MO, PtrOffset);
5402       } else {
5403         MIB.add(MO);
5404       }
5405     }
5406   }
5407 }
5408 
5409 static void updateOperandRegConstraints(MachineFunction &MF,
5410                                         MachineInstr &NewMI,
5411                                         const TargetInstrInfo &TII) {
5412   MachineRegisterInfo &MRI = MF.getRegInfo();
5413   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
5414 
5415   for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
5416     MachineOperand &MO = NewMI.getOperand(Idx);
5417     // We only need to update constraints on virtual register operands.
5418     if (!MO.isReg())
5419       continue;
5420     Register Reg = MO.getReg();
5421     if (!Reg.isVirtual())
5422       continue;
5423 
5424     auto *NewRC = MRI.constrainRegClass(
5425         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
5426     if (!NewRC) {
5427       LLVM_DEBUG(
5428           dbgs() << "WARNING: Unable to update register constraint for operand "
5429                  << Idx << " of instruction:\n";
5430           NewMI.dump(); dbgs() << "\n");
5431     }
5432   }
5433 }
5434 
5435 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5436                                      ArrayRef<MachineOperand> MOs,
5437                                      MachineBasicBlock::iterator InsertPt,
5438                                      MachineInstr &MI,
5439                                      const TargetInstrInfo &TII) {
5440   // Create the base instruction with the memory operand as the first part.
5441   // Omit the implicit operands, something BuildMI can't do.
5442   MachineInstr *NewMI =
5443       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5444   MachineInstrBuilder MIB(MF, NewMI);
5445   addOperands(MIB, MOs);
5446 
5447   // Loop over the rest of the ri operands, converting them over.
5448   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5449   for (unsigned i = 0; i != NumOps; ++i) {
5450     MachineOperand &MO = MI.getOperand(i + 2);
5451     MIB.add(MO);
5452   }
5453   for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), NumOps + 2))
5454     MIB.add(MO);
5455 
5456   updateOperandRegConstraints(MF, *NewMI, TII);
5457 
5458   MachineBasicBlock *MBB = InsertPt->getParent();
5459   MBB->insert(InsertPt, NewMI);
5460 
5461   return MIB;
5462 }
5463 
5464 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5465                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5466                               MachineBasicBlock::iterator InsertPt,
5467                               MachineInstr &MI, const TargetInstrInfo &TII,
5468                               int PtrOffset = 0) {
5469   // Omit the implicit operands, something BuildMI can't do.
5470   MachineInstr *NewMI =
5471       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5472   MachineInstrBuilder MIB(MF, NewMI);
5473 
5474   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5475     MachineOperand &MO = MI.getOperand(i);
5476     if (i == OpNo) {
5477       assert(MO.isReg() && "Expected to fold into reg operand!");
5478       addOperands(MIB, MOs, PtrOffset);
5479     } else {
5480       MIB.add(MO);
5481     }
5482   }
5483 
5484   updateOperandRegConstraints(MF, *NewMI, TII);
5485 
5486   // Copy the NoFPExcept flag from the instruction we're fusing.
5487   if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
5488     NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
5489 
5490   MachineBasicBlock *MBB = InsertPt->getParent();
5491   MBB->insert(InsertPt, NewMI);
5492 
5493   return MIB;
5494 }
5495 
5496 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5497                                 ArrayRef<MachineOperand> MOs,
5498                                 MachineBasicBlock::iterator InsertPt,
5499                                 MachineInstr &MI) {
5500   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5501                                     MI.getDebugLoc(), TII.get(Opcode));
5502   addOperands(MIB, MOs);
5503   return MIB.addImm(0);
5504 }
5505 
5506 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5507     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5508     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5509     unsigned Size, Align Alignment) const {
5510   switch (MI.getOpcode()) {
5511   case X86::INSERTPSrr:
5512   case X86::VINSERTPSrr:
5513   case X86::VINSERTPSZrr:
5514     // Attempt to convert the load of inserted vector into a fold load
5515     // of a single float.
5516     if (OpNum == 2) {
5517       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5518       unsigned ZMask = Imm & 15;
5519       unsigned DstIdx = (Imm >> 4) & 3;
5520       unsigned SrcIdx = (Imm >> 6) & 3;
5521 
5522       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5523       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5524       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5525       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(4)) {
5526         int PtrOffset = SrcIdx * 4;
5527         unsigned NewImm = (DstIdx << 4) | ZMask;
5528         unsigned NewOpCode =
5529             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5530             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
5531                                                     X86::INSERTPSrm;
5532         MachineInstr *NewMI =
5533             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5534         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5535         return NewMI;
5536       }
5537     }
5538     break;
5539   case X86::MOVHLPSrr:
5540   case X86::VMOVHLPSrr:
5541   case X86::VMOVHLPSZrr:
5542     // Move the upper 64-bits of the second operand to the lower 64-bits.
5543     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5544     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5545     if (OpNum == 2) {
5546       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5547       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5548       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5549       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
5550         unsigned NewOpCode =
5551             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5552             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
5553                                                    X86::MOVLPSrm;
5554         MachineInstr *NewMI =
5555             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5556         return NewMI;
5557       }
5558     }
5559     break;
5560   case X86::UNPCKLPDrr:
5561     // If we won't be able to fold this to the memory form of UNPCKL, use
5562     // MOVHPD instead. Done as custom because we can't have this in the load
5563     // table twice.
5564     if (OpNum == 2) {
5565       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5566       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5567       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5568       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
5569         MachineInstr *NewMI =
5570             FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
5571         return NewMI;
5572       }
5573     }
5574     break;
5575   }
5576 
5577   return nullptr;
5578 }
5579 
5580 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
5581                                                MachineInstr &MI) {
5582   if (!hasUndefRegUpdate(MI.getOpcode(), 1, /*ForLoadFold*/true) ||
5583       !MI.getOperand(1).isReg())
5584     return false;
5585 
5586   // The are two cases we need to handle depending on where in the pipeline
5587   // the folding attempt is being made.
5588   // -Register has the undef flag set.
5589   // -Register is produced by the IMPLICIT_DEF instruction.
5590 
5591   if (MI.getOperand(1).isUndef())
5592     return true;
5593 
5594   MachineRegisterInfo &RegInfo = MF.getRegInfo();
5595   MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
5596   return VRegDef && VRegDef->isImplicitDef();
5597 }
5598 
5599 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5600     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5601     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5602     unsigned Size, Align Alignment, bool AllowCommute) const {
5603   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
5604   bool isTwoAddrFold = false;
5605 
5606   // For CPUs that favor the register form of a call or push,
5607   // do not fold loads into calls or pushes, unless optimizing for size
5608   // aggressively.
5609   if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
5610       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5611        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5612        MI.getOpcode() == X86::PUSH64r))
5613     return nullptr;
5614 
5615   // Avoid partial and undef register update stalls unless optimizing for size.
5616   if (!MF.getFunction().hasOptSize() &&
5617       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5618        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5619     return nullptr;
5620 
5621   unsigned NumOps = MI.getDesc().getNumOperands();
5622   bool isTwoAddr =
5623       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5624 
5625   // FIXME: AsmPrinter doesn't know how to handle
5626   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5627   if (MI.getOpcode() == X86::ADD32ri &&
5628       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5629     return nullptr;
5630 
5631   // GOTTPOFF relocation loads can only be folded into add instructions.
5632   // FIXME: Need to exclude other relocations that only support specific
5633   // instructions.
5634   if (MOs.size() == X86::AddrNumOperands &&
5635       MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
5636       MI.getOpcode() != X86::ADD64rr)
5637     return nullptr;
5638 
5639   MachineInstr *NewMI = nullptr;
5640 
5641   // Attempt to fold any custom cases we have.
5642   if (MachineInstr *CustomMI = foldMemoryOperandCustom(
5643           MF, MI, OpNum, MOs, InsertPt, Size, Alignment))
5644     return CustomMI;
5645 
5646   const X86MemoryFoldTableEntry *I = nullptr;
5647 
5648   // Folding a memory location into the two-address part of a two-address
5649   // instruction is different than folding it other places.  It requires
5650   // replacing the *two* registers with the memory location.
5651   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5652       MI.getOperand(1).isReg() &&
5653       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5654     I = lookupTwoAddrFoldTable(MI.getOpcode());
5655     isTwoAddrFold = true;
5656   } else {
5657     if (OpNum == 0) {
5658       if (MI.getOpcode() == X86::MOV32r0) {
5659         NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5660         if (NewMI)
5661           return NewMI;
5662       }
5663     }
5664 
5665     I = lookupFoldTable(MI.getOpcode(), OpNum);
5666   }
5667 
5668   if (I != nullptr) {
5669     unsigned Opcode = I->DstOp;
5670     bool FoldedLoad =
5671         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_LOAD) || OpNum > 0;
5672     bool FoldedStore =
5673         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_STORE);
5674     MaybeAlign MinAlign =
5675         decodeMaybeAlign((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT);
5676     if (MinAlign && Alignment < *MinAlign)
5677       return nullptr;
5678     bool NarrowToMOV32rm = false;
5679     if (Size) {
5680       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5681       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
5682                                                   &RI, MF);
5683       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5684       // Check if it's safe to fold the load. If the size of the object is
5685       // narrower than the load width, then it's not.
5686       // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
5687       if (FoldedLoad && Size < RCSize) {
5688         // If this is a 64-bit load, but the spill slot is 32, then we can do
5689         // a 32-bit load which is implicitly zero-extended. This likely is
5690         // due to live interval analysis remat'ing a load from stack slot.
5691         if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5692           return nullptr;
5693         if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5694           return nullptr;
5695         Opcode = X86::MOV32rm;
5696         NarrowToMOV32rm = true;
5697       }
5698       // For stores, make sure the size of the object is equal to the size of
5699       // the store. If the object is larger, the extra bits would be garbage. If
5700       // the object is smaller we might overwrite another object or fault.
5701       if (FoldedStore && Size != RCSize)
5702         return nullptr;
5703     }
5704 
5705     if (isTwoAddrFold)
5706       NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5707     else
5708       NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5709 
5710     if (NarrowToMOV32rm) {
5711       // If this is the special case where we use a MOV32rm to load a 32-bit
5712       // value and zero-extend the top bits. Change the destination register
5713       // to a 32-bit one.
5714       Register DstReg = NewMI->getOperand(0).getReg();
5715       if (DstReg.isPhysical())
5716         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5717       else
5718         NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5719     }
5720     return NewMI;
5721   }
5722 
5723   // If the instruction and target operand are commutable, commute the
5724   // instruction and try again.
5725   if (AllowCommute) {
5726     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5727     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5728       bool HasDef = MI.getDesc().getNumDefs();
5729       Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
5730       Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5731       Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5732       bool Tied1 =
5733           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5734       bool Tied2 =
5735           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5736 
5737       // If either of the commutable operands are tied to the destination
5738       // then we can not commute + fold.
5739       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5740           (HasDef && Reg0 == Reg2 && Tied2))
5741         return nullptr;
5742 
5743       MachineInstr *CommutedMI =
5744           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5745       if (!CommutedMI) {
5746         // Unable to commute.
5747         return nullptr;
5748       }
5749       if (CommutedMI != &MI) {
5750         // New instruction. We can't fold from this.
5751         CommutedMI->eraseFromParent();
5752         return nullptr;
5753       }
5754 
5755       // Attempt to fold with the commuted version of the instruction.
5756       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, Size,
5757                                     Alignment, /*AllowCommute=*/false);
5758       if (NewMI)
5759         return NewMI;
5760 
5761       // Folding failed again - undo the commute before returning.
5762       MachineInstr *UncommutedMI =
5763           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5764       if (!UncommutedMI) {
5765         // Unable to commute.
5766         return nullptr;
5767       }
5768       if (UncommutedMI != &MI) {
5769         // New instruction. It doesn't need to be kept.
5770         UncommutedMI->eraseFromParent();
5771         return nullptr;
5772       }
5773 
5774       // Return here to prevent duplicate fuse failure report.
5775       return nullptr;
5776     }
5777   }
5778 
5779   // No fusion
5780   if (PrintFailedFusing && !MI.isCopy())
5781     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
5782   return nullptr;
5783 }
5784 
5785 MachineInstr *
5786 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
5787                                     ArrayRef<unsigned> Ops,
5788                                     MachineBasicBlock::iterator InsertPt,
5789                                     int FrameIndex, LiveIntervals *LIS,
5790                                     VirtRegMap *VRM) const {
5791   // Check switch flag
5792   if (NoFusing)
5793     return nullptr;
5794 
5795   // Avoid partial and undef register update stalls unless optimizing for size.
5796   if (!MF.getFunction().hasOptSize() &&
5797       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5798        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5799     return nullptr;
5800 
5801   // Don't fold subreg spills, or reloads that use a high subreg.
5802   for (auto Op : Ops) {
5803     MachineOperand &MO = MI.getOperand(Op);
5804     auto SubReg = MO.getSubReg();
5805     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
5806       return nullptr;
5807   }
5808 
5809   const MachineFrameInfo &MFI = MF.getFrameInfo();
5810   unsigned Size = MFI.getObjectSize(FrameIndex);
5811   Align Alignment = MFI.getObjectAlign(FrameIndex);
5812   // If the function stack isn't realigned we don't want to fold instructions
5813   // that need increased alignment.
5814   if (!RI.hasStackRealignment(MF))
5815     Alignment =
5816         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlign());
5817   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5818     unsigned NewOpc = 0;
5819     unsigned RCSize = 0;
5820     switch (MI.getOpcode()) {
5821     default: return nullptr;
5822     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5823     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5824     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5825     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5826     }
5827     // Check if it's safe to fold the load. If the size of the object is
5828     // narrower than the load width, then it's not.
5829     if (Size < RCSize)
5830       return nullptr;
5831     // Change to CMPXXri r, 0 first.
5832     MI.setDesc(get(NewOpc));
5833     MI.getOperand(1).ChangeToImmediate(0);
5834   } else if (Ops.size() != 1)
5835     return nullptr;
5836 
5837   return foldMemoryOperandImpl(MF, MI, Ops[0],
5838                                MachineOperand::CreateFI(FrameIndex), InsertPt,
5839                                Size, Alignment, /*AllowCommute=*/true);
5840 }
5841 
5842 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5843 /// because the latter uses contents that wouldn't be defined in the folded
5844 /// version.  For instance, this transformation isn't legal:
5845 ///   movss (%rdi), %xmm0
5846 ///   addps %xmm0, %xmm0
5847 /// ->
5848 ///   addps (%rdi), %xmm0
5849 ///
5850 /// But this one is:
5851 ///   movss (%rdi), %xmm0
5852 ///   addss %xmm0, %xmm0
5853 /// ->
5854 ///   addss (%rdi), %xmm0
5855 ///
5856 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5857                                              const MachineInstr &UserMI,
5858                                              const MachineFunction &MF) {
5859   unsigned Opc = LoadMI.getOpcode();
5860   unsigned UserOpc = UserMI.getOpcode();
5861   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5862   const TargetRegisterClass *RC =
5863       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5864   unsigned RegSize = TRI.getRegSizeInBits(*RC);
5865 
5866   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
5867        Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
5868        Opc == X86::VMOVSSZrm_alt) &&
5869       RegSize > 32) {
5870     // These instructions only load 32 bits, we can't fold them if the
5871     // destination register is wider than 32 bits (4 bytes), and its user
5872     // instruction isn't scalar (SS).
5873     switch (UserOpc) {
5874     case X86::CVTSS2SDrr_Int:
5875     case X86::VCVTSS2SDrr_Int:
5876     case X86::VCVTSS2SDZrr_Int:
5877     case X86::VCVTSS2SDZrr_Intk:
5878     case X86::VCVTSS2SDZrr_Intkz:
5879     case X86::CVTSS2SIrr_Int:     case X86::CVTSS2SI64rr_Int:
5880     case X86::VCVTSS2SIrr_Int:    case X86::VCVTSS2SI64rr_Int:
5881     case X86::VCVTSS2SIZrr_Int:   case X86::VCVTSS2SI64Zrr_Int:
5882     case X86::CVTTSS2SIrr_Int:    case X86::CVTTSS2SI64rr_Int:
5883     case X86::VCVTTSS2SIrr_Int:   case X86::VCVTTSS2SI64rr_Int:
5884     case X86::VCVTTSS2SIZrr_Int:  case X86::VCVTTSS2SI64Zrr_Int:
5885     case X86::VCVTSS2USIZrr_Int:  case X86::VCVTSS2USI64Zrr_Int:
5886     case X86::VCVTTSS2USIZrr_Int: case X86::VCVTTSS2USI64Zrr_Int:
5887     case X86::RCPSSr_Int:   case X86::VRCPSSr_Int:
5888     case X86::RSQRTSSr_Int: case X86::VRSQRTSSr_Int:
5889     case X86::ROUNDSSr_Int: case X86::VROUNDSSr_Int:
5890     case X86::COMISSrr_Int: case X86::VCOMISSrr_Int: case X86::VCOMISSZrr_Int:
5891     case X86::UCOMISSrr_Int:case X86::VUCOMISSrr_Int:case X86::VUCOMISSZrr_Int:
5892     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5893     case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5894     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5895     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5896     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5897     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5898     case X86::SQRTSSr_Int: case X86::VSQRTSSr_Int: case X86::VSQRTSSZr_Int:
5899     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5900     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5901     case X86::VCMPSSZrr_Intk:
5902     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5903     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5904     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5905     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5906     case X86::VSQRTSSZr_Intk: case X86::VSQRTSSZr_Intkz:
5907     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5908     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
5909     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
5910     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
5911     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
5912     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
5913     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
5914     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
5915     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
5916     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5917     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5918     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5919     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5920     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5921     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5922     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5923     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5924     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5925     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5926     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5927     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5928     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5929     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5930     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5931     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5932     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5933     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5934     case X86::VFIXUPIMMSSZrri:
5935     case X86::VFIXUPIMMSSZrrik:
5936     case X86::VFIXUPIMMSSZrrikz:
5937     case X86::VFPCLASSSSZrr:
5938     case X86::VFPCLASSSSZrrk:
5939     case X86::VGETEXPSSZr:
5940     case X86::VGETEXPSSZrk:
5941     case X86::VGETEXPSSZrkz:
5942     case X86::VGETMANTSSZrri:
5943     case X86::VGETMANTSSZrrik:
5944     case X86::VGETMANTSSZrrikz:
5945     case X86::VRANGESSZrri:
5946     case X86::VRANGESSZrrik:
5947     case X86::VRANGESSZrrikz:
5948     case X86::VRCP14SSZrr:
5949     case X86::VRCP14SSZrrk:
5950     case X86::VRCP14SSZrrkz:
5951     case X86::VRCP28SSZr:
5952     case X86::VRCP28SSZrk:
5953     case X86::VRCP28SSZrkz:
5954     case X86::VREDUCESSZrri:
5955     case X86::VREDUCESSZrrik:
5956     case X86::VREDUCESSZrrikz:
5957     case X86::VRNDSCALESSZr_Int:
5958     case X86::VRNDSCALESSZr_Intk:
5959     case X86::VRNDSCALESSZr_Intkz:
5960     case X86::VRSQRT14SSZrr:
5961     case X86::VRSQRT14SSZrrk:
5962     case X86::VRSQRT14SSZrrkz:
5963     case X86::VRSQRT28SSZr:
5964     case X86::VRSQRT28SSZrk:
5965     case X86::VRSQRT28SSZrkz:
5966     case X86::VSCALEFSSZrr:
5967     case X86::VSCALEFSSZrrk:
5968     case X86::VSCALEFSSZrrkz:
5969       return false;
5970     default:
5971       return true;
5972     }
5973   }
5974 
5975   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
5976        Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
5977        Opc == X86::VMOVSDZrm_alt) &&
5978       RegSize > 64) {
5979     // These instructions only load 64 bits, we can't fold them if the
5980     // destination register is wider than 64 bits (8 bytes), and its user
5981     // instruction isn't scalar (SD).
5982     switch (UserOpc) {
5983     case X86::CVTSD2SSrr_Int:
5984     case X86::VCVTSD2SSrr_Int:
5985     case X86::VCVTSD2SSZrr_Int:
5986     case X86::VCVTSD2SSZrr_Intk:
5987     case X86::VCVTSD2SSZrr_Intkz:
5988     case X86::CVTSD2SIrr_Int:     case X86::CVTSD2SI64rr_Int:
5989     case X86::VCVTSD2SIrr_Int:    case X86::VCVTSD2SI64rr_Int:
5990     case X86::VCVTSD2SIZrr_Int:   case X86::VCVTSD2SI64Zrr_Int:
5991     case X86::CVTTSD2SIrr_Int:    case X86::CVTTSD2SI64rr_Int:
5992     case X86::VCVTTSD2SIrr_Int:   case X86::VCVTTSD2SI64rr_Int:
5993     case X86::VCVTTSD2SIZrr_Int:  case X86::VCVTTSD2SI64Zrr_Int:
5994     case X86::VCVTSD2USIZrr_Int:  case X86::VCVTSD2USI64Zrr_Int:
5995     case X86::VCVTTSD2USIZrr_Int: case X86::VCVTTSD2USI64Zrr_Int:
5996     case X86::ROUNDSDr_Int: case X86::VROUNDSDr_Int:
5997     case X86::COMISDrr_Int: case X86::VCOMISDrr_Int: case X86::VCOMISDZrr_Int:
5998     case X86::UCOMISDrr_Int:case X86::VUCOMISDrr_Int:case X86::VUCOMISDZrr_Int:
5999     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
6000     case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
6001     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
6002     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
6003     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
6004     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
6005     case X86::SQRTSDr_Int: case X86::VSQRTSDr_Int: case X86::VSQRTSDZr_Int:
6006     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
6007     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
6008     case X86::VCMPSDZrr_Intk:
6009     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
6010     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
6011     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
6012     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
6013     case X86::VSQRTSDZr_Intk: case X86::VSQRTSDZr_Intkz:
6014     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
6015     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
6016     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
6017     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
6018     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
6019     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
6020     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
6021     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
6022     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
6023     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
6024     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
6025     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
6026     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
6027     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
6028     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
6029     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
6030     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
6031     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
6032     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
6033     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
6034     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
6035     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
6036     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
6037     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
6038     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
6039     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
6040     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
6041     case X86::VFIXUPIMMSDZrri:
6042     case X86::VFIXUPIMMSDZrrik:
6043     case X86::VFIXUPIMMSDZrrikz:
6044     case X86::VFPCLASSSDZrr:
6045     case X86::VFPCLASSSDZrrk:
6046     case X86::VGETEXPSDZr:
6047     case X86::VGETEXPSDZrk:
6048     case X86::VGETEXPSDZrkz:
6049     case X86::VGETMANTSDZrri:
6050     case X86::VGETMANTSDZrrik:
6051     case X86::VGETMANTSDZrrikz:
6052     case X86::VRANGESDZrri:
6053     case X86::VRANGESDZrrik:
6054     case X86::VRANGESDZrrikz:
6055     case X86::VRCP14SDZrr:
6056     case X86::VRCP14SDZrrk:
6057     case X86::VRCP14SDZrrkz:
6058     case X86::VRCP28SDZr:
6059     case X86::VRCP28SDZrk:
6060     case X86::VRCP28SDZrkz:
6061     case X86::VREDUCESDZrri:
6062     case X86::VREDUCESDZrrik:
6063     case X86::VREDUCESDZrrikz:
6064     case X86::VRNDSCALESDZr_Int:
6065     case X86::VRNDSCALESDZr_Intk:
6066     case X86::VRNDSCALESDZr_Intkz:
6067     case X86::VRSQRT14SDZrr:
6068     case X86::VRSQRT14SDZrrk:
6069     case X86::VRSQRT14SDZrrkz:
6070     case X86::VRSQRT28SDZr:
6071     case X86::VRSQRT28SDZrk:
6072     case X86::VRSQRT28SDZrkz:
6073     case X86::VSCALEFSDZrr:
6074     case X86::VSCALEFSDZrrk:
6075     case X86::VSCALEFSDZrrkz:
6076       return false;
6077     default:
6078       return true;
6079     }
6080   }
6081 
6082   if ((Opc == X86::VMOVSHZrm || Opc == X86::VMOVSHZrm_alt) && RegSize > 16) {
6083     // These instructions only load 16 bits, we can't fold them if the
6084     // destination register is wider than 16 bits (2 bytes), and its user
6085     // instruction isn't scalar (SH).
6086     switch (UserOpc) {
6087     case X86::VADDSHZrr_Int:
6088     case X86::VCMPSHZrr_Int:
6089     case X86::VDIVSHZrr_Int:
6090     case X86::VMAXSHZrr_Int:
6091     case X86::VMINSHZrr_Int:
6092     case X86::VMULSHZrr_Int:
6093     case X86::VSUBSHZrr_Int:
6094     case X86::VADDSHZrr_Intk: case X86::VADDSHZrr_Intkz:
6095     case X86::VCMPSHZrr_Intk:
6096     case X86::VDIVSHZrr_Intk: case X86::VDIVSHZrr_Intkz:
6097     case X86::VMAXSHZrr_Intk: case X86::VMAXSHZrr_Intkz:
6098     case X86::VMINSHZrr_Intk: case X86::VMINSHZrr_Intkz:
6099     case X86::VMULSHZrr_Intk: case X86::VMULSHZrr_Intkz:
6100     case X86::VSUBSHZrr_Intk: case X86::VSUBSHZrr_Intkz:
6101     case X86::VFMADD132SHZr_Int: case X86::VFNMADD132SHZr_Int:
6102     case X86::VFMADD213SHZr_Int: case X86::VFNMADD213SHZr_Int:
6103     case X86::VFMADD231SHZr_Int: case X86::VFNMADD231SHZr_Int:
6104     case X86::VFMSUB132SHZr_Int: case X86::VFNMSUB132SHZr_Int:
6105     case X86::VFMSUB213SHZr_Int: case X86::VFNMSUB213SHZr_Int:
6106     case X86::VFMSUB231SHZr_Int: case X86::VFNMSUB231SHZr_Int:
6107     case X86::VFMADD132SHZr_Intk: case X86::VFNMADD132SHZr_Intk:
6108     case X86::VFMADD213SHZr_Intk: case X86::VFNMADD213SHZr_Intk:
6109     case X86::VFMADD231SHZr_Intk: case X86::VFNMADD231SHZr_Intk:
6110     case X86::VFMSUB132SHZr_Intk: case X86::VFNMSUB132SHZr_Intk:
6111     case X86::VFMSUB213SHZr_Intk: case X86::VFNMSUB213SHZr_Intk:
6112     case X86::VFMSUB231SHZr_Intk: case X86::VFNMSUB231SHZr_Intk:
6113     case X86::VFMADD132SHZr_Intkz: case X86::VFNMADD132SHZr_Intkz:
6114     case X86::VFMADD213SHZr_Intkz: case X86::VFNMADD213SHZr_Intkz:
6115     case X86::VFMADD231SHZr_Intkz: case X86::VFNMADD231SHZr_Intkz:
6116     case X86::VFMSUB132SHZr_Intkz: case X86::VFNMSUB132SHZr_Intkz:
6117     case X86::VFMSUB213SHZr_Intkz: case X86::VFNMSUB213SHZr_Intkz:
6118     case X86::VFMSUB231SHZr_Intkz: case X86::VFNMSUB231SHZr_Intkz:
6119       return false;
6120     default:
6121       return true;
6122     }
6123   }
6124 
6125   return false;
6126 }
6127 
6128 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6129     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6130     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
6131     LiveIntervals *LIS) const {
6132 
6133   // TODO: Support the case where LoadMI loads a wide register, but MI
6134   // only uses a subreg.
6135   for (auto Op : Ops) {
6136     if (MI.getOperand(Op).getSubReg())
6137       return nullptr;
6138   }
6139 
6140   // If loading from a FrameIndex, fold directly from the FrameIndex.
6141   unsigned NumOps = LoadMI.getDesc().getNumOperands();
6142   int FrameIndex;
6143   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6144     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6145       return nullptr;
6146     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
6147   }
6148 
6149   // Check switch flag
6150   if (NoFusing) return nullptr;
6151 
6152   // Avoid partial and undef register update stalls unless optimizing for size.
6153   if (!MF.getFunction().hasOptSize() &&
6154       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
6155        shouldPreventUndefRegUpdateMemFold(MF, MI)))
6156     return nullptr;
6157 
6158   // Determine the alignment of the load.
6159   Align Alignment;
6160   if (LoadMI.hasOneMemOperand())
6161     Alignment = (*LoadMI.memoperands_begin())->getAlign();
6162   else
6163     switch (LoadMI.getOpcode()) {
6164     case X86::AVX512_512_SET0:
6165     case X86::AVX512_512_SETALLONES:
6166       Alignment = Align(64);
6167       break;
6168     case X86::AVX2_SETALLONES:
6169     case X86::AVX1_SETALLONES:
6170     case X86::AVX_SET0:
6171     case X86::AVX512_256_SET0:
6172       Alignment = Align(32);
6173       break;
6174     case X86::V_SET0:
6175     case X86::V_SETALLONES:
6176     case X86::AVX512_128_SET0:
6177     case X86::FsFLD0F128:
6178     case X86::AVX512_FsFLD0F128:
6179       Alignment = Align(16);
6180       break;
6181     case X86::MMX_SET0:
6182     case X86::FsFLD0SD:
6183     case X86::AVX512_FsFLD0SD:
6184       Alignment = Align(8);
6185       break;
6186     case X86::FsFLD0SS:
6187     case X86::AVX512_FsFLD0SS:
6188       Alignment = Align(4);
6189       break;
6190     case X86::AVX512_FsFLD0SH:
6191       Alignment = Align(2);
6192       break;
6193     default:
6194       return nullptr;
6195     }
6196   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6197     unsigned NewOpc = 0;
6198     switch (MI.getOpcode()) {
6199     default: return nullptr;
6200     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6201     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6202     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6203     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6204     }
6205     // Change to CMPXXri r, 0 first.
6206     MI.setDesc(get(NewOpc));
6207     MI.getOperand(1).ChangeToImmediate(0);
6208   } else if (Ops.size() != 1)
6209     return nullptr;
6210 
6211   // Make sure the subregisters match.
6212   // Otherwise we risk changing the size of the load.
6213   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6214     return nullptr;
6215 
6216   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6217   switch (LoadMI.getOpcode()) {
6218   case X86::MMX_SET0:
6219   case X86::V_SET0:
6220   case X86::V_SETALLONES:
6221   case X86::AVX2_SETALLONES:
6222   case X86::AVX1_SETALLONES:
6223   case X86::AVX_SET0:
6224   case X86::AVX512_128_SET0:
6225   case X86::AVX512_256_SET0:
6226   case X86::AVX512_512_SET0:
6227   case X86::AVX512_512_SETALLONES:
6228   case X86::AVX512_FsFLD0SH:
6229   case X86::FsFLD0SD:
6230   case X86::AVX512_FsFLD0SD:
6231   case X86::FsFLD0SS:
6232   case X86::AVX512_FsFLD0SS:
6233   case X86::FsFLD0F128:
6234   case X86::AVX512_FsFLD0F128: {
6235     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6236     // Create a constant-pool entry and operands to load from it.
6237 
6238     // Medium and large mode can't fold loads this way.
6239     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6240         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6241       return nullptr;
6242 
6243     // x86-32 PIC requires a PIC base register for constant pools.
6244     unsigned PICBase = 0;
6245     // Since we're using Small or Kernel code model, we can always use
6246     // RIP-relative addressing for a smaller encoding.
6247     if (Subtarget.is64Bit()) {
6248       PICBase = X86::RIP;
6249     } else if (MF.getTarget().isPositionIndependent()) {
6250       // FIXME: PICBase = getGlobalBaseReg(&MF);
6251       // This doesn't work for several reasons.
6252       // 1. GlobalBaseReg may have been spilled.
6253       // 2. It may not be live at MI.
6254       return nullptr;
6255     }
6256 
6257     // Create a constant-pool entry.
6258     MachineConstantPool &MCP = *MF.getConstantPool();
6259     Type *Ty;
6260     unsigned Opc = LoadMI.getOpcode();
6261     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
6262       Ty = Type::getFloatTy(MF.getFunction().getContext());
6263     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
6264       Ty = Type::getDoubleTy(MF.getFunction().getContext());
6265     else if (Opc == X86::FsFLD0F128 || Opc == X86::AVX512_FsFLD0F128)
6266       Ty = Type::getFP128Ty(MF.getFunction().getContext());
6267     else if (Opc == X86::AVX512_FsFLD0SH)
6268       Ty = Type::getHalfTy(MF.getFunction().getContext());
6269     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
6270       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6271                                 16);
6272     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6273              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
6274       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6275                                 8);
6276     else if (Opc == X86::MMX_SET0)
6277       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6278                                 2);
6279     else
6280       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6281                                 4);
6282 
6283     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6284                       Opc == X86::AVX512_512_SETALLONES ||
6285                       Opc == X86::AVX1_SETALLONES);
6286     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6287                                     Constant::getNullValue(Ty);
6288     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6289 
6290     // Create operands to load from the constant pool entry.
6291     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6292     MOs.push_back(MachineOperand::CreateImm(1));
6293     MOs.push_back(MachineOperand::CreateReg(0, false));
6294     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6295     MOs.push_back(MachineOperand::CreateReg(0, false));
6296     break;
6297   }
6298   default: {
6299     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6300       return nullptr;
6301 
6302     // Folding a normal load. Just copy the load's address operands.
6303     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6304                LoadMI.operands_begin() + NumOps);
6305     break;
6306   }
6307   }
6308   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6309                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6310 }
6311 
6312 static SmallVector<MachineMemOperand *, 2>
6313 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6314   SmallVector<MachineMemOperand *, 2> LoadMMOs;
6315 
6316   for (MachineMemOperand *MMO : MMOs) {
6317     if (!MMO->isLoad())
6318       continue;
6319 
6320     if (!MMO->isStore()) {
6321       // Reuse the MMO.
6322       LoadMMOs.push_back(MMO);
6323     } else {
6324       // Clone the MMO and unset the store flag.
6325       LoadMMOs.push_back(MF.getMachineMemOperand(
6326           MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
6327     }
6328   }
6329 
6330   return LoadMMOs;
6331 }
6332 
6333 static SmallVector<MachineMemOperand *, 2>
6334 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6335   SmallVector<MachineMemOperand *, 2> StoreMMOs;
6336 
6337   for (MachineMemOperand *MMO : MMOs) {
6338     if (!MMO->isStore())
6339       continue;
6340 
6341     if (!MMO->isLoad()) {
6342       // Reuse the MMO.
6343       StoreMMOs.push_back(MMO);
6344     } else {
6345       // Clone the MMO and unset the load flag.
6346       StoreMMOs.push_back(MF.getMachineMemOperand(
6347           MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
6348     }
6349   }
6350 
6351   return StoreMMOs;
6352 }
6353 
6354 static unsigned getBroadcastOpcode(const X86MemoryFoldTableEntry *I,
6355                                    const TargetRegisterClass *RC,
6356                                    const X86Subtarget &STI) {
6357   assert(STI.hasAVX512() && "Expected at least AVX512!");
6358   unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
6359   assert((SpillSize == 64 || STI.hasVLX()) &&
6360          "Can't broadcast less than 64 bytes without AVX512VL!");
6361 
6362   switch (I->Flags & TB_BCAST_MASK) {
6363   default: llvm_unreachable("Unexpected broadcast type!");
6364   case TB_BCAST_D:
6365     switch (SpillSize) {
6366     default: llvm_unreachable("Unknown spill size");
6367     case 16: return X86::VPBROADCASTDZ128rm;
6368     case 32: return X86::VPBROADCASTDZ256rm;
6369     case 64: return X86::VPBROADCASTDZrm;
6370     }
6371     break;
6372   case TB_BCAST_Q:
6373     switch (SpillSize) {
6374     default: llvm_unreachable("Unknown spill size");
6375     case 16: return X86::VPBROADCASTQZ128rm;
6376     case 32: return X86::VPBROADCASTQZ256rm;
6377     case 64: return X86::VPBROADCASTQZrm;
6378     }
6379     break;
6380   case TB_BCAST_SS:
6381     switch (SpillSize) {
6382     default: llvm_unreachable("Unknown spill size");
6383     case 16: return X86::VBROADCASTSSZ128rm;
6384     case 32: return X86::VBROADCASTSSZ256rm;
6385     case 64: return X86::VBROADCASTSSZrm;
6386     }
6387     break;
6388   case TB_BCAST_SD:
6389     switch (SpillSize) {
6390     default: llvm_unreachable("Unknown spill size");
6391     case 16: return X86::VMOVDDUPZ128rm;
6392     case 32: return X86::VBROADCASTSDZ256rm;
6393     case 64: return X86::VBROADCASTSDZrm;
6394     }
6395     break;
6396   }
6397 }
6398 
6399 bool X86InstrInfo::unfoldMemoryOperand(
6400     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6401     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6402   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
6403   if (I == nullptr)
6404     return false;
6405   unsigned Opc = I->DstOp;
6406   unsigned Index = I->Flags & TB_INDEX_MASK;
6407   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6408   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6409   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6410   if (UnfoldLoad && !FoldedLoad)
6411     return false;
6412   UnfoldLoad &= FoldedLoad;
6413   if (UnfoldStore && !FoldedStore)
6414     return false;
6415   UnfoldStore &= FoldedStore;
6416 
6417   const MCInstrDesc &MCID = get(Opc);
6418 
6419   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6420   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6421   // TODO: Check if 32-byte or greater accesses are slow too?
6422   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
6423       Subtarget.isUnalignedMem16Slow())
6424     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6425     // conservatively assume the address is unaligned. That's bad for
6426     // performance.
6427     return false;
6428   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6429   SmallVector<MachineOperand,2> BeforeOps;
6430   SmallVector<MachineOperand,2> AfterOps;
6431   SmallVector<MachineOperand,4> ImpOps;
6432   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6433     MachineOperand &Op = MI.getOperand(i);
6434     if (i >= Index && i < Index + X86::AddrNumOperands)
6435       AddrOps.push_back(Op);
6436     else if (Op.isReg() && Op.isImplicit())
6437       ImpOps.push_back(Op);
6438     else if (i < Index)
6439       BeforeOps.push_back(Op);
6440     else if (i > Index)
6441       AfterOps.push_back(Op);
6442   }
6443 
6444   // Emit the load or broadcast instruction.
6445   if (UnfoldLoad) {
6446     auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
6447 
6448     unsigned Opc;
6449     if (FoldedBCast) {
6450       Opc = getBroadcastOpcode(I, RC, Subtarget);
6451     } else {
6452       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6453       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6454       Opc = getLoadRegOpcode(Reg, RC, isAligned, Subtarget);
6455     }
6456 
6457     DebugLoc DL;
6458     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
6459     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6460       MIB.add(AddrOps[i]);
6461     MIB.setMemRefs(MMOs);
6462     NewMIs.push_back(MIB);
6463 
6464     if (UnfoldStore) {
6465       // Address operands cannot be marked isKill.
6466       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6467         MachineOperand &MO = NewMIs[0]->getOperand(i);
6468         if (MO.isReg())
6469           MO.setIsKill(false);
6470       }
6471     }
6472   }
6473 
6474   // Emit the data processing instruction.
6475   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
6476   MachineInstrBuilder MIB(MF, DataMI);
6477 
6478   if (FoldedStore)
6479     MIB.addReg(Reg, RegState::Define);
6480   for (MachineOperand &BeforeOp : BeforeOps)
6481     MIB.add(BeforeOp);
6482   if (FoldedLoad)
6483     MIB.addReg(Reg);
6484   for (MachineOperand &AfterOp : AfterOps)
6485     MIB.add(AfterOp);
6486   for (MachineOperand &ImpOp : ImpOps) {
6487     MIB.addReg(ImpOp.getReg(),
6488                getDefRegState(ImpOp.isDef()) |
6489                RegState::Implicit |
6490                getKillRegState(ImpOp.isKill()) |
6491                getDeadRegState(ImpOp.isDead()) |
6492                getUndefRegState(ImpOp.isUndef()));
6493   }
6494   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6495   switch (DataMI->getOpcode()) {
6496   default: break;
6497   case X86::CMP64ri32:
6498   case X86::CMP64ri8:
6499   case X86::CMP32ri:
6500   case X86::CMP32ri8:
6501   case X86::CMP16ri:
6502   case X86::CMP16ri8:
6503   case X86::CMP8ri: {
6504     MachineOperand &MO0 = DataMI->getOperand(0);
6505     MachineOperand &MO1 = DataMI->getOperand(1);
6506     if (MO1.isImm() && MO1.getImm() == 0) {
6507       unsigned NewOpc;
6508       switch (DataMI->getOpcode()) {
6509       default: llvm_unreachable("Unreachable!");
6510       case X86::CMP64ri8:
6511       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6512       case X86::CMP32ri8:
6513       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6514       case X86::CMP16ri8:
6515       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6516       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6517       }
6518       DataMI->setDesc(get(NewOpc));
6519       MO1.ChangeToRegister(MO0.getReg(), false);
6520     }
6521   }
6522   }
6523   NewMIs.push_back(DataMI);
6524 
6525   // Emit the store instruction.
6526   if (UnfoldStore) {
6527     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6528     auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
6529     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16);
6530     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6531     unsigned Opc = getStoreRegOpcode(Reg, DstRC, isAligned, Subtarget);
6532     DebugLoc DL;
6533     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6534     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6535       MIB.add(AddrOps[i]);
6536     MIB.addReg(Reg, RegState::Kill);
6537     MIB.setMemRefs(MMOs);
6538     NewMIs.push_back(MIB);
6539   }
6540 
6541   return true;
6542 }
6543 
6544 bool
6545 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6546                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6547   if (!N->isMachineOpcode())
6548     return false;
6549 
6550   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
6551   if (I == nullptr)
6552     return false;
6553   unsigned Opc = I->DstOp;
6554   unsigned Index = I->Flags & TB_INDEX_MASK;
6555   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6556   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6557   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6558   const MCInstrDesc &MCID = get(Opc);
6559   MachineFunction &MF = DAG.getMachineFunction();
6560   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6561   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6562   unsigned NumDefs = MCID.NumDefs;
6563   std::vector<SDValue> AddrOps;
6564   std::vector<SDValue> BeforeOps;
6565   std::vector<SDValue> AfterOps;
6566   SDLoc dl(N);
6567   unsigned NumOps = N->getNumOperands();
6568   for (unsigned i = 0; i != NumOps-1; ++i) {
6569     SDValue Op = N->getOperand(i);
6570     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6571       AddrOps.push_back(Op);
6572     else if (i < Index-NumDefs)
6573       BeforeOps.push_back(Op);
6574     else if (i > Index-NumDefs)
6575       AfterOps.push_back(Op);
6576   }
6577   SDValue Chain = N->getOperand(NumOps-1);
6578   AddrOps.push_back(Chain);
6579 
6580   // Emit the load instruction.
6581   SDNode *Load = nullptr;
6582   if (FoldedLoad) {
6583     EVT VT = *TRI.legalclasstypes_begin(*RC);
6584     auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6585     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6586         Subtarget.isUnalignedMem16Slow())
6587       // Do not introduce a slow unaligned load.
6588       return false;
6589     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6590     // memory access is slow above.
6591 
6592     unsigned Opc;
6593     if (FoldedBCast) {
6594       Opc = getBroadcastOpcode(I, RC, Subtarget);
6595     } else {
6596       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6597       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6598       Opc = getLoadRegOpcode(0, RC, isAligned, Subtarget);
6599     }
6600 
6601     Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
6602     NewNodes.push_back(Load);
6603 
6604     // Preserve memory reference information.
6605     DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
6606   }
6607 
6608   // Emit the data processing instruction.
6609   std::vector<EVT> VTs;
6610   const TargetRegisterClass *DstRC = nullptr;
6611   if (MCID.getNumDefs() > 0) {
6612     DstRC = getRegClass(MCID, 0, &RI, MF);
6613     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
6614   }
6615   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6616     EVT VT = N->getValueType(i);
6617     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6618       VTs.push_back(VT);
6619   }
6620   if (Load)
6621     BeforeOps.push_back(SDValue(Load, 0));
6622   llvm::append_range(BeforeOps, AfterOps);
6623   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6624   switch (Opc) {
6625     default: break;
6626     case X86::CMP64ri32:
6627     case X86::CMP64ri8:
6628     case X86::CMP32ri:
6629     case X86::CMP32ri8:
6630     case X86::CMP16ri:
6631     case X86::CMP16ri8:
6632     case X86::CMP8ri:
6633       if (isNullConstant(BeforeOps[1])) {
6634         switch (Opc) {
6635           default: llvm_unreachable("Unreachable!");
6636           case X86::CMP64ri8:
6637           case X86::CMP64ri32: Opc = X86::TEST64rr; break;
6638           case X86::CMP32ri8:
6639           case X86::CMP32ri:   Opc = X86::TEST32rr; break;
6640           case X86::CMP16ri8:
6641           case X86::CMP16ri:   Opc = X86::TEST16rr; break;
6642           case X86::CMP8ri:    Opc = X86::TEST8rr; break;
6643         }
6644         BeforeOps[1] = BeforeOps[0];
6645       }
6646   }
6647   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6648   NewNodes.push_back(NewNode);
6649 
6650   // Emit the store instruction.
6651   if (FoldedStore) {
6652     AddrOps.pop_back();
6653     AddrOps.push_back(SDValue(NewNode, 0));
6654     AddrOps.push_back(Chain);
6655     auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6656     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6657         Subtarget.isUnalignedMem16Slow())
6658       // Do not introduce a slow unaligned store.
6659       return false;
6660     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6661     // memory access is slow above.
6662     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6663     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6664     SDNode *Store =
6665         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6666                            dl, MVT::Other, AddrOps);
6667     NewNodes.push_back(Store);
6668 
6669     // Preserve memory reference information.
6670     DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
6671   }
6672 
6673   return true;
6674 }
6675 
6676 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6677                                       bool UnfoldLoad, bool UnfoldStore,
6678                                       unsigned *LoadRegIndex) const {
6679   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
6680   if (I == nullptr)
6681     return 0;
6682   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6683   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6684   if (UnfoldLoad && !FoldedLoad)
6685     return 0;
6686   if (UnfoldStore && !FoldedStore)
6687     return 0;
6688   if (LoadRegIndex)
6689     *LoadRegIndex = I->Flags & TB_INDEX_MASK;
6690   return I->DstOp;
6691 }
6692 
6693 bool
6694 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6695                                      int64_t &Offset1, int64_t &Offset2) const {
6696   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6697     return false;
6698   unsigned Opc1 = Load1->getMachineOpcode();
6699   unsigned Opc2 = Load2->getMachineOpcode();
6700   switch (Opc1) {
6701   default: return false;
6702   case X86::MOV8rm:
6703   case X86::MOV16rm:
6704   case X86::MOV32rm:
6705   case X86::MOV64rm:
6706   case X86::LD_Fp32m:
6707   case X86::LD_Fp64m:
6708   case X86::LD_Fp80m:
6709   case X86::MOVSSrm:
6710   case X86::MOVSSrm_alt:
6711   case X86::MOVSDrm:
6712   case X86::MOVSDrm_alt:
6713   case X86::MMX_MOVD64rm:
6714   case X86::MMX_MOVQ64rm:
6715   case X86::MOVAPSrm:
6716   case X86::MOVUPSrm:
6717   case X86::MOVAPDrm:
6718   case X86::MOVUPDrm:
6719   case X86::MOVDQArm:
6720   case X86::MOVDQUrm:
6721   // AVX load instructions
6722   case X86::VMOVSSrm:
6723   case X86::VMOVSSrm_alt:
6724   case X86::VMOVSDrm:
6725   case X86::VMOVSDrm_alt:
6726   case X86::VMOVAPSrm:
6727   case X86::VMOVUPSrm:
6728   case X86::VMOVAPDrm:
6729   case X86::VMOVUPDrm:
6730   case X86::VMOVDQArm:
6731   case X86::VMOVDQUrm:
6732   case X86::VMOVAPSYrm:
6733   case X86::VMOVUPSYrm:
6734   case X86::VMOVAPDYrm:
6735   case X86::VMOVUPDYrm:
6736   case X86::VMOVDQAYrm:
6737   case X86::VMOVDQUYrm:
6738   // AVX512 load instructions
6739   case X86::VMOVSSZrm:
6740   case X86::VMOVSSZrm_alt:
6741   case X86::VMOVSDZrm:
6742   case X86::VMOVSDZrm_alt:
6743   case X86::VMOVAPSZ128rm:
6744   case X86::VMOVUPSZ128rm:
6745   case X86::VMOVAPSZ128rm_NOVLX:
6746   case X86::VMOVUPSZ128rm_NOVLX:
6747   case X86::VMOVAPDZ128rm:
6748   case X86::VMOVUPDZ128rm:
6749   case X86::VMOVDQU8Z128rm:
6750   case X86::VMOVDQU16Z128rm:
6751   case X86::VMOVDQA32Z128rm:
6752   case X86::VMOVDQU32Z128rm:
6753   case X86::VMOVDQA64Z128rm:
6754   case X86::VMOVDQU64Z128rm:
6755   case X86::VMOVAPSZ256rm:
6756   case X86::VMOVUPSZ256rm:
6757   case X86::VMOVAPSZ256rm_NOVLX:
6758   case X86::VMOVUPSZ256rm_NOVLX:
6759   case X86::VMOVAPDZ256rm:
6760   case X86::VMOVUPDZ256rm:
6761   case X86::VMOVDQU8Z256rm:
6762   case X86::VMOVDQU16Z256rm:
6763   case X86::VMOVDQA32Z256rm:
6764   case X86::VMOVDQU32Z256rm:
6765   case X86::VMOVDQA64Z256rm:
6766   case X86::VMOVDQU64Z256rm:
6767   case X86::VMOVAPSZrm:
6768   case X86::VMOVUPSZrm:
6769   case X86::VMOVAPDZrm:
6770   case X86::VMOVUPDZrm:
6771   case X86::VMOVDQU8Zrm:
6772   case X86::VMOVDQU16Zrm:
6773   case X86::VMOVDQA32Zrm:
6774   case X86::VMOVDQU32Zrm:
6775   case X86::VMOVDQA64Zrm:
6776   case X86::VMOVDQU64Zrm:
6777   case X86::KMOVBkm:
6778   case X86::KMOVWkm:
6779   case X86::KMOVDkm:
6780   case X86::KMOVQkm:
6781     break;
6782   }
6783   switch (Opc2) {
6784   default: return false;
6785   case X86::MOV8rm:
6786   case X86::MOV16rm:
6787   case X86::MOV32rm:
6788   case X86::MOV64rm:
6789   case X86::LD_Fp32m:
6790   case X86::LD_Fp64m:
6791   case X86::LD_Fp80m:
6792   case X86::MOVSSrm:
6793   case X86::MOVSSrm_alt:
6794   case X86::MOVSDrm:
6795   case X86::MOVSDrm_alt:
6796   case X86::MMX_MOVD64rm:
6797   case X86::MMX_MOVQ64rm:
6798   case X86::MOVAPSrm:
6799   case X86::MOVUPSrm:
6800   case X86::MOVAPDrm:
6801   case X86::MOVUPDrm:
6802   case X86::MOVDQArm:
6803   case X86::MOVDQUrm:
6804   // AVX load instructions
6805   case X86::VMOVSSrm:
6806   case X86::VMOVSSrm_alt:
6807   case X86::VMOVSDrm:
6808   case X86::VMOVSDrm_alt:
6809   case X86::VMOVAPSrm:
6810   case X86::VMOVUPSrm:
6811   case X86::VMOVAPDrm:
6812   case X86::VMOVUPDrm:
6813   case X86::VMOVDQArm:
6814   case X86::VMOVDQUrm:
6815   case X86::VMOVAPSYrm:
6816   case X86::VMOVUPSYrm:
6817   case X86::VMOVAPDYrm:
6818   case X86::VMOVUPDYrm:
6819   case X86::VMOVDQAYrm:
6820   case X86::VMOVDQUYrm:
6821   // AVX512 load instructions
6822   case X86::VMOVSSZrm:
6823   case X86::VMOVSSZrm_alt:
6824   case X86::VMOVSDZrm:
6825   case X86::VMOVSDZrm_alt:
6826   case X86::VMOVAPSZ128rm:
6827   case X86::VMOVUPSZ128rm:
6828   case X86::VMOVAPSZ128rm_NOVLX:
6829   case X86::VMOVUPSZ128rm_NOVLX:
6830   case X86::VMOVAPDZ128rm:
6831   case X86::VMOVUPDZ128rm:
6832   case X86::VMOVDQU8Z128rm:
6833   case X86::VMOVDQU16Z128rm:
6834   case X86::VMOVDQA32Z128rm:
6835   case X86::VMOVDQU32Z128rm:
6836   case X86::VMOVDQA64Z128rm:
6837   case X86::VMOVDQU64Z128rm:
6838   case X86::VMOVAPSZ256rm:
6839   case X86::VMOVUPSZ256rm:
6840   case X86::VMOVAPSZ256rm_NOVLX:
6841   case X86::VMOVUPSZ256rm_NOVLX:
6842   case X86::VMOVAPDZ256rm:
6843   case X86::VMOVUPDZ256rm:
6844   case X86::VMOVDQU8Z256rm:
6845   case X86::VMOVDQU16Z256rm:
6846   case X86::VMOVDQA32Z256rm:
6847   case X86::VMOVDQU32Z256rm:
6848   case X86::VMOVDQA64Z256rm:
6849   case X86::VMOVDQU64Z256rm:
6850   case X86::VMOVAPSZrm:
6851   case X86::VMOVUPSZrm:
6852   case X86::VMOVAPDZrm:
6853   case X86::VMOVUPDZrm:
6854   case X86::VMOVDQU8Zrm:
6855   case X86::VMOVDQU16Zrm:
6856   case X86::VMOVDQA32Zrm:
6857   case X86::VMOVDQU32Zrm:
6858   case X86::VMOVDQA64Zrm:
6859   case X86::VMOVDQU64Zrm:
6860   case X86::KMOVBkm:
6861   case X86::KMOVWkm:
6862   case X86::KMOVDkm:
6863   case X86::KMOVQkm:
6864     break;
6865   }
6866 
6867   // Lambda to check if both the loads have the same value for an operand index.
6868   auto HasSameOp = [&](int I) {
6869     return Load1->getOperand(I) == Load2->getOperand(I);
6870   };
6871 
6872   // All operands except the displacement should match.
6873   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
6874       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
6875     return false;
6876 
6877   // Chain Operand must be the same.
6878   if (!HasSameOp(5))
6879     return false;
6880 
6881   // Now let's examine if the displacements are constants.
6882   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
6883   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
6884   if (!Disp1 || !Disp2)
6885     return false;
6886 
6887   Offset1 = Disp1->getSExtValue();
6888   Offset2 = Disp2->getSExtValue();
6889   return true;
6890 }
6891 
6892 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6893                                            int64_t Offset1, int64_t Offset2,
6894                                            unsigned NumLoads) const {
6895   assert(Offset2 > Offset1);
6896   if ((Offset2 - Offset1) / 8 > 64)
6897     return false;
6898 
6899   unsigned Opc1 = Load1->getMachineOpcode();
6900   unsigned Opc2 = Load2->getMachineOpcode();
6901   if (Opc1 != Opc2)
6902     return false;  // FIXME: overly conservative?
6903 
6904   switch (Opc1) {
6905   default: break;
6906   case X86::LD_Fp32m:
6907   case X86::LD_Fp64m:
6908   case X86::LD_Fp80m:
6909   case X86::MMX_MOVD64rm:
6910   case X86::MMX_MOVQ64rm:
6911     return false;
6912   }
6913 
6914   EVT VT = Load1->getValueType(0);
6915   switch (VT.getSimpleVT().SimpleTy) {
6916   default:
6917     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6918     // have 16 of them to play with.
6919     if (Subtarget.is64Bit()) {
6920       if (NumLoads >= 3)
6921         return false;
6922     } else if (NumLoads) {
6923       return false;
6924     }
6925     break;
6926   case MVT::i8:
6927   case MVT::i16:
6928   case MVT::i32:
6929   case MVT::i64:
6930   case MVT::f32:
6931   case MVT::f64:
6932     if (NumLoads)
6933       return false;
6934     break;
6935   }
6936 
6937   return true;
6938 }
6939 
6940 bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
6941                                         const MachineBasicBlock *MBB,
6942                                         const MachineFunction &MF) const {
6943 
6944   // ENDBR instructions should not be scheduled around.
6945   unsigned Opcode = MI.getOpcode();
6946   if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32 ||
6947       Opcode == X86::LDTILECFG)
6948     return true;
6949 
6950   return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
6951 }
6952 
6953 bool X86InstrInfo::
6954 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6955   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6956   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6957   Cond[0].setImm(GetOppositeBranchCondition(CC));
6958   return false;
6959 }
6960 
6961 bool X86InstrInfo::
6962 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6963   // FIXME: Return false for x87 stack register classes for now. We can't
6964   // allow any loads of these registers before FpGet_ST0_80.
6965   return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
6966            RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
6967            RC == &X86::RFP80RegClass);
6968 }
6969 
6970 /// Return a virtual register initialized with the
6971 /// the global base register value. Output instructions required to
6972 /// initialize the register in the function entry block, if necessary.
6973 ///
6974 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6975 ///
6976 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6977   assert((!Subtarget.is64Bit() ||
6978           MF->getTarget().getCodeModel() == CodeModel::Medium ||
6979           MF->getTarget().getCodeModel() == CodeModel::Large) &&
6980          "X86-64 PIC uses RIP relative addressing");
6981 
6982   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6983   Register GlobalBaseReg = X86FI->getGlobalBaseReg();
6984   if (GlobalBaseReg != 0)
6985     return GlobalBaseReg;
6986 
6987   // Create the register. The code to initialize it is inserted
6988   // later, by the CGBR pass (below).
6989   MachineRegisterInfo &RegInfo = MF->getRegInfo();
6990   GlobalBaseReg = RegInfo.createVirtualRegister(
6991       Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
6992   X86FI->setGlobalBaseReg(GlobalBaseReg);
6993   return GlobalBaseReg;
6994 }
6995 
6996 // These are the replaceable SSE instructions. Some of these have Int variants
6997 // that we don't include here. We don't want to replace instructions selected
6998 // by intrinsics.
6999 static const uint16_t ReplaceableInstrs[][3] = {
7000   //PackedSingle     PackedDouble    PackedInt
7001   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
7002   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
7003   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
7004   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
7005   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
7006   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
7007   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
7008   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
7009   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
7010   { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
7011   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
7012   { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
7013   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
7014   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
7015   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
7016   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
7017   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
7018   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
7019   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
7020   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
7021   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
7022   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
7023   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
7024   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
7025   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
7026   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
7027   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
7028   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
7029   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
7030   { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
7031   { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
7032   // AVX 128-bit support
7033   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
7034   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
7035   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
7036   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
7037   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
7038   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
7039   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
7040   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
7041   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
7042   { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
7043   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
7044   { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
7045   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7046   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
7047   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
7048   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
7049   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
7050   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
7051   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
7052   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
7053   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
7054   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
7055   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
7056   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
7057   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
7058   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
7059   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
7060   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
7061   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
7062   { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
7063   { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
7064   // AVX 256-bit support
7065   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
7066   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
7067   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
7068   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
7069   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
7070   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
7071   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
7072   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
7073   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
7074   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
7075   // AVX512 support
7076   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
7077   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7078   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
7079   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
7080   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
7081   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
7082   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
7083   { X86::VMOVSDZrm_alt,  X86::VMOVSDZrm_alt,  X86::VMOVQI2PQIZrm  },
7084   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
7085   { X86::VMOVSSZrm_alt,  X86::VMOVSSZrm_alt,  X86::VMOVDI2PDIZrm  },
7086   { X86::VBROADCASTSSZ128rr,X86::VBROADCASTSSZ128rr,X86::VPBROADCASTDZ128rr },
7087   { X86::VBROADCASTSSZ128rm,X86::VBROADCASTSSZ128rm,X86::VPBROADCASTDZ128rm },
7088   { X86::VBROADCASTSSZ256rr,X86::VBROADCASTSSZ256rr,X86::VPBROADCASTDZ256rr },
7089   { X86::VBROADCASTSSZ256rm,X86::VBROADCASTSSZ256rm,X86::VPBROADCASTDZ256rm },
7090   { X86::VBROADCASTSSZrr,   X86::VBROADCASTSSZrr,   X86::VPBROADCASTDZrr },
7091   { X86::VBROADCASTSSZrm,   X86::VBROADCASTSSZrm,   X86::VPBROADCASTDZrm },
7092   { X86::VMOVDDUPZ128rr,    X86::VMOVDDUPZ128rr,    X86::VPBROADCASTQZ128rr },
7093   { X86::VMOVDDUPZ128rm,    X86::VMOVDDUPZ128rm,    X86::VPBROADCASTQZ128rm },
7094   { X86::VBROADCASTSDZ256rr,X86::VBROADCASTSDZ256rr,X86::VPBROADCASTQZ256rr },
7095   { X86::VBROADCASTSDZ256rm,X86::VBROADCASTSDZ256rm,X86::VPBROADCASTQZ256rm },
7096   { X86::VBROADCASTSDZrr,   X86::VBROADCASTSDZrr,   X86::VPBROADCASTQZrr },
7097   { X86::VBROADCASTSDZrm,   X86::VBROADCASTSDZrm,   X86::VPBROADCASTQZrm },
7098   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
7099   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
7100   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
7101   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
7102   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
7103   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
7104   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
7105   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
7106   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
7107   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
7108   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
7109   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
7110   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
7111   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
7112   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
7113   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
7114   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
7115   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
7116   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
7117   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
7118   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
7119   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
7120   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
7121   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
7122   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
7123   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
7124   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
7125   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
7126   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
7127   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
7128   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
7129   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
7130   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
7131   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
7132   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
7133   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
7134   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
7135   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
7136   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
7137   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
7138   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
7139   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
7140   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
7141   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
7142   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
7143   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
7144   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
7145   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
7146   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
7147   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
7148   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
7149   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
7150   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
7151   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
7152   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
7153   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
7154   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
7155   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
7156   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
7157   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
7158   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
7159   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
7160   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
7161   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
7162   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
7163   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
7164   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
7165   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
7166   { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
7167   { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
7168 };
7169 
7170 static const uint16_t ReplaceableInstrsAVX2[][3] = {
7171   //PackedSingle       PackedDouble       PackedInt
7172   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
7173   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
7174   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
7175   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
7176   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
7177   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
7178   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
7179   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
7180   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
7181   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
7182   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7183   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7184   { X86::VMOVDDUPrm,     X86::VMOVDDUPrm,     X86::VPBROADCASTQrm},
7185   { X86::VMOVDDUPrr,     X86::VMOVDDUPrr,     X86::VPBROADCASTQrr},
7186   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7187   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7188   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7189   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
7190   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
7191   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
7192   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
7193   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
7194   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
7195   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
7196   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
7197   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
7198   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
7199   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
7200   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
7201   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
7202   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
7203 };
7204 
7205 static const uint16_t ReplaceableInstrsFP[][3] = {
7206   //PackedSingle         PackedDouble
7207   { X86::MOVLPSrm,       X86::MOVLPDrm,      X86::INSTRUCTION_LIST_END },
7208   { X86::MOVHPSrm,       X86::MOVHPDrm,      X86::INSTRUCTION_LIST_END },
7209   { X86::MOVHPSmr,       X86::MOVHPDmr,      X86::INSTRUCTION_LIST_END },
7210   { X86::VMOVLPSrm,      X86::VMOVLPDrm,     X86::INSTRUCTION_LIST_END },
7211   { X86::VMOVHPSrm,      X86::VMOVHPDrm,     X86::INSTRUCTION_LIST_END },
7212   { X86::VMOVHPSmr,      X86::VMOVHPDmr,     X86::INSTRUCTION_LIST_END },
7213   { X86::VMOVLPSZ128rm,  X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
7214   { X86::VMOVHPSZ128rm,  X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
7215   { X86::VMOVHPSZ128mr,  X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
7216 };
7217 
7218 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
7219   //PackedSingle       PackedDouble       PackedInt
7220   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7221   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7222   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
7223   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
7224 };
7225 
7226 static const uint16_t ReplaceableInstrsAVX512[][4] = {
7227   // Two integer columns for 64-bit and 32-bit elements.
7228   //PackedSingle        PackedDouble        PackedInt             PackedInt
7229   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
7230   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
7231   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
7232   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
7233   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
7234   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
7235   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
7236   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
7237   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
7238   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
7239   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
7240   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
7241   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
7242   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
7243   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
7244 };
7245 
7246 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7247   // Two integer columns for 64-bit and 32-bit elements.
7248   //PackedSingle        PackedDouble        PackedInt           PackedInt
7249   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7250   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7251   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7252   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7253   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7254   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7255   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7256   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7257   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7258   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7259   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7260   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7261   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7262   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7263   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7264   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7265   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
7266   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
7267   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
7268   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
7269   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
7270   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
7271   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
7272   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
7273 };
7274 
7275 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
7276   // Two integer columns for 64-bit and 32-bit elements.
7277   //PackedSingle          PackedDouble
7278   //PackedInt             PackedInt
7279   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
7280     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
7281   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
7282     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
7283   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
7284     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
7285   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
7286     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
7287   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
7288     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
7289   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
7290     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
7291   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
7292     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
7293   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
7294     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
7295   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
7296     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
7297   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
7298     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
7299   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
7300     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
7301   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
7302     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
7303   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
7304     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
7305   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
7306     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
7307   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
7308     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
7309   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
7310     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
7311   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
7312     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
7313   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
7314     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
7315   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
7316     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
7317   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
7318     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
7319   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
7320     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
7321   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
7322     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
7323   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
7324     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
7325   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
7326     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
7327   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
7328     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
7329   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
7330     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
7331   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
7332     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
7333   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
7334     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
7335   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
7336     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
7337   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
7338     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
7339   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
7340     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
7341   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
7342     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
7343   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
7344     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
7345   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
7346     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
7347   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
7348     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
7349   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
7350     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
7351   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
7352     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
7353   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
7354     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
7355   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
7356     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
7357   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
7358     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
7359   { X86::VORPSZrmk,       X86::VORPDZrmk,
7360     X86::VPORQZrmk,       X86::VPORDZrmk       },
7361   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
7362     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
7363   { X86::VORPSZrrk,       X86::VORPDZrrk,
7364     X86::VPORQZrrk,       X86::VPORDZrrk       },
7365   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
7366     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
7367   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
7368     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
7369   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
7370     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
7371   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
7372     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
7373   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
7374     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
7375   // Broadcast loads can be handled the same as masked operations to avoid
7376   // changing element size.
7377   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
7378     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
7379   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
7380     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
7381   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
7382     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
7383   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
7384     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
7385   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
7386     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
7387   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
7388     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
7389   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
7390     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
7391   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
7392     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
7393   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
7394     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
7395   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7396     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7397   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7398     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7399   { X86::VORPSZrmb,       X86::VORPDZrmb,
7400     X86::VPORQZrmb,       X86::VPORDZrmb       },
7401   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
7402     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
7403   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
7404     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
7405   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
7406     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
7407   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
7408     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
7409   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
7410     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
7411   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
7412     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
7413   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
7414     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
7415   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
7416     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
7417   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
7418     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
7419   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
7420     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
7421   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7422     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7423   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7424     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7425   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
7426     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
7427   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
7428     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
7429   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
7430     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
7431   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
7432     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
7433   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
7434     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
7435   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
7436     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
7437   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
7438     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
7439   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
7440     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
7441   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
7442     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
7443   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
7444     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
7445   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
7446     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
7447   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7448     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7449   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7450     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7451   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
7452     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
7453   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
7454     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
7455 };
7456 
7457 // NOTE: These should only be used by the custom domain methods.
7458 static const uint16_t ReplaceableBlendInstrs[][3] = {
7459   //PackedSingle             PackedDouble             PackedInt
7460   { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
7461   { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
7462   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
7463   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
7464   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
7465   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
7466 };
7467 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
7468   //PackedSingle             PackedDouble             PackedInt
7469   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
7470   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
7471   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
7472   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
7473 };
7474 
7475 // Special table for changing EVEX logic instructions to VEX.
7476 // TODO: Should we run EVEX->VEX earlier?
7477 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
7478   // Two integer columns for 64-bit and 32-bit elements.
7479   //PackedSingle     PackedDouble     PackedInt           PackedInt
7480   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7481   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7482   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7483   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7484   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7485   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7486   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7487   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7488   { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7489   { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7490   { X86::VANDPSYrm,  X86::VANDPDYrm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7491   { X86::VANDPSYrr,  X86::VANDPDYrr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7492   { X86::VORPSYrm,   X86::VORPDYrm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7493   { X86::VORPSYrr,   X86::VORPDYrr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7494   { X86::VXORPSYrm,  X86::VXORPDYrm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7495   { X86::VXORPSYrr,  X86::VXORPDYrr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7496 };
7497 
7498 // FIXME: Some shuffle and unpack instructions have equivalents in different
7499 // domains, but they require a bit more work than just switching opcodes.
7500 
7501 static const uint16_t *lookup(unsigned opcode, unsigned domain,
7502                               ArrayRef<uint16_t[3]> Table) {
7503   for (const uint16_t (&Row)[3] : Table)
7504     if (Row[domain-1] == opcode)
7505       return Row;
7506   return nullptr;
7507 }
7508 
7509 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
7510                                     ArrayRef<uint16_t[4]> Table) {
7511   // If this is the integer domain make sure to check both integer columns.
7512   for (const uint16_t (&Row)[4] : Table)
7513     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7514       return Row;
7515   return nullptr;
7516 }
7517 
7518 // Helper to attempt to widen/narrow blend masks.
7519 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
7520                             unsigned NewWidth, unsigned *pNewMask = nullptr) {
7521   assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
7522          "Illegal blend mask scale");
7523   unsigned NewMask = 0;
7524 
7525   if ((OldWidth % NewWidth) == 0) {
7526     unsigned Scale = OldWidth / NewWidth;
7527     unsigned SubMask = (1u << Scale) - 1;
7528     for (unsigned i = 0; i != NewWidth; ++i) {
7529       unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
7530       if (Sub == SubMask)
7531         NewMask |= (1u << i);
7532       else if (Sub != 0x0)
7533         return false;
7534     }
7535   } else {
7536     unsigned Scale = NewWidth / OldWidth;
7537     unsigned SubMask = (1u << Scale) - 1;
7538     for (unsigned i = 0; i != OldWidth; ++i) {
7539       if (OldMask & (1 << i)) {
7540         NewMask |= (SubMask << (i * Scale));
7541       }
7542     }
7543   }
7544 
7545   if (pNewMask)
7546     *pNewMask = NewMask;
7547   return true;
7548 }
7549 
7550 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
7551   unsigned Opcode = MI.getOpcode();
7552   unsigned NumOperands = MI.getDesc().getNumOperands();
7553 
7554   auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
7555     uint16_t validDomains = 0;
7556     if (MI.getOperand(NumOperands - 1).isImm()) {
7557       unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
7558       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
7559         validDomains |= 0x2; // PackedSingle
7560       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
7561         validDomains |= 0x4; // PackedDouble
7562       if (!Is256 || Subtarget.hasAVX2())
7563         validDomains |= 0x8; // PackedInt
7564     }
7565     return validDomains;
7566   };
7567 
7568   switch (Opcode) {
7569   case X86::BLENDPDrmi:
7570   case X86::BLENDPDrri:
7571   case X86::VBLENDPDrmi:
7572   case X86::VBLENDPDrri:
7573     return GetBlendDomains(2, false);
7574   case X86::VBLENDPDYrmi:
7575   case X86::VBLENDPDYrri:
7576     return GetBlendDomains(4, true);
7577   case X86::BLENDPSrmi:
7578   case X86::BLENDPSrri:
7579   case X86::VBLENDPSrmi:
7580   case X86::VBLENDPSrri:
7581   case X86::VPBLENDDrmi:
7582   case X86::VPBLENDDrri:
7583     return GetBlendDomains(4, false);
7584   case X86::VBLENDPSYrmi:
7585   case X86::VBLENDPSYrri:
7586   case X86::VPBLENDDYrmi:
7587   case X86::VPBLENDDYrri:
7588     return GetBlendDomains(8, true);
7589   case X86::PBLENDWrmi:
7590   case X86::PBLENDWrri:
7591   case X86::VPBLENDWrmi:
7592   case X86::VPBLENDWrri:
7593   // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
7594   case X86::VPBLENDWYrmi:
7595   case X86::VPBLENDWYrri:
7596     return GetBlendDomains(8, false);
7597   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7598   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7599   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7600   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7601   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7602   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7603   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7604   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7605   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7606   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7607   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7608   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7609   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7610   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7611   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7612   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm:
7613     // If we don't have DQI see if we can still switch from an EVEX integer
7614     // instruction to a VEX floating point instruction.
7615     if (Subtarget.hasDQI())
7616       return 0;
7617 
7618     if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
7619       return 0;
7620     if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
7621       return 0;
7622     // Register forms will have 3 operands. Memory form will have more.
7623     if (NumOperands == 3 &&
7624         RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
7625       return 0;
7626 
7627     // All domains are valid.
7628     return 0xe;
7629   case X86::MOVHLPSrr:
7630     // We can swap domains when both inputs are the same register.
7631     // FIXME: This doesn't catch all the cases we would like. If the input
7632     // register isn't KILLed by the instruction, the two address instruction
7633     // pass puts a COPY on one input. The other input uses the original
7634     // register. This prevents the same physical register from being used by
7635     // both inputs.
7636     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7637         MI.getOperand(0).getSubReg() == 0 &&
7638         MI.getOperand(1).getSubReg() == 0 &&
7639         MI.getOperand(2).getSubReg() == 0)
7640       return 0x6;
7641     return 0;
7642   case X86::SHUFPDrri:
7643     return 0x6;
7644   }
7645   return 0;
7646 }
7647 
7648 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
7649                                             unsigned Domain) const {
7650   assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
7651   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7652   assert(dom && "Not an SSE instruction");
7653 
7654   unsigned Opcode = MI.getOpcode();
7655   unsigned NumOperands = MI.getDesc().getNumOperands();
7656 
7657   auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
7658     if (MI.getOperand(NumOperands - 1).isImm()) {
7659       unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
7660       Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
7661       unsigned NewImm = Imm;
7662 
7663       const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
7664       if (!table)
7665         table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7666 
7667       if (Domain == 1) { // PackedSingle
7668         AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7669       } else if (Domain == 2) { // PackedDouble
7670         AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
7671       } else if (Domain == 3) { // PackedInt
7672         if (Subtarget.hasAVX2()) {
7673           // If we are already VPBLENDW use that, else use VPBLENDD.
7674           if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
7675             table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7676             AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7677           }
7678         } else {
7679           assert(!Is256 && "128-bit vector expected");
7680           AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
7681         }
7682       }
7683 
7684       assert(table && table[Domain - 1] && "Unknown domain op");
7685       MI.setDesc(get(table[Domain - 1]));
7686       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
7687     }
7688     return true;
7689   };
7690 
7691   switch (Opcode) {
7692   case X86::BLENDPDrmi:
7693   case X86::BLENDPDrri:
7694   case X86::VBLENDPDrmi:
7695   case X86::VBLENDPDrri:
7696     return SetBlendDomain(2, false);
7697   case X86::VBLENDPDYrmi:
7698   case X86::VBLENDPDYrri:
7699     return SetBlendDomain(4, true);
7700   case X86::BLENDPSrmi:
7701   case X86::BLENDPSrri:
7702   case X86::VBLENDPSrmi:
7703   case X86::VBLENDPSrri:
7704   case X86::VPBLENDDrmi:
7705   case X86::VPBLENDDrri:
7706     return SetBlendDomain(4, false);
7707   case X86::VBLENDPSYrmi:
7708   case X86::VBLENDPSYrri:
7709   case X86::VPBLENDDYrmi:
7710   case X86::VPBLENDDYrri:
7711     return SetBlendDomain(8, true);
7712   case X86::PBLENDWrmi:
7713   case X86::PBLENDWrri:
7714   case X86::VPBLENDWrmi:
7715   case X86::VPBLENDWrri:
7716     return SetBlendDomain(8, false);
7717   case X86::VPBLENDWYrmi:
7718   case X86::VPBLENDWYrri:
7719     return SetBlendDomain(16, true);
7720   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7721   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7722   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7723   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7724   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7725   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7726   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7727   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7728   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7729   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7730   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7731   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7732   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7733   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7734   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7735   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm: {
7736     // Without DQI, convert EVEX instructions to VEX instructions.
7737     if (Subtarget.hasDQI())
7738       return false;
7739 
7740     const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
7741                                          ReplaceableCustomAVX512LogicInstrs);
7742     assert(table && "Instruction not found in table?");
7743     // Don't change integer Q instructions to D instructions and
7744     // use D intructions if we started with a PS instruction.
7745     if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7746       Domain = 4;
7747     MI.setDesc(get(table[Domain - 1]));
7748     return true;
7749   }
7750   case X86::UNPCKHPDrr:
7751   case X86::MOVHLPSrr:
7752     // We just need to commute the instruction which will switch the domains.
7753     if (Domain != dom && Domain != 3 &&
7754         MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7755         MI.getOperand(0).getSubReg() == 0 &&
7756         MI.getOperand(1).getSubReg() == 0 &&
7757         MI.getOperand(2).getSubReg() == 0) {
7758       commuteInstruction(MI, false);
7759       return true;
7760     }
7761     // We must always return true for MOVHLPSrr.
7762     if (Opcode == X86::MOVHLPSrr)
7763       return true;
7764     break;
7765   case X86::SHUFPDrri: {
7766     if (Domain == 1) {
7767       unsigned Imm = MI.getOperand(3).getImm();
7768       unsigned NewImm = 0x44;
7769       if (Imm & 1) NewImm |= 0x0a;
7770       if (Imm & 2) NewImm |= 0xa0;
7771       MI.getOperand(3).setImm(NewImm);
7772       MI.setDesc(get(X86::SHUFPSrri));
7773     }
7774     return true;
7775   }
7776   }
7777   return false;
7778 }
7779 
7780 std::pair<uint16_t, uint16_t>
7781 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7782   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7783   unsigned opcode = MI.getOpcode();
7784   uint16_t validDomains = 0;
7785   if (domain) {
7786     // Attempt to match for custom instructions.
7787     validDomains = getExecutionDomainCustom(MI);
7788     if (validDomains)
7789       return std::make_pair(domain, validDomains);
7790 
7791     if (lookup(opcode, domain, ReplaceableInstrs)) {
7792       validDomains = 0xe;
7793     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
7794       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
7795     } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
7796       validDomains = 0x6;
7797     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
7798       // Insert/extract instructions should only effect domain if AVX2
7799       // is enabled.
7800       if (!Subtarget.hasAVX2())
7801         return std::make_pair(0, 0);
7802       validDomains = 0xe;
7803     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
7804       validDomains = 0xe;
7805     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
7806                                                   ReplaceableInstrsAVX512DQ)) {
7807       validDomains = 0xe;
7808     } else if (Subtarget.hasDQI()) {
7809       if (const uint16_t *table = lookupAVX512(opcode, domain,
7810                                              ReplaceableInstrsAVX512DQMasked)) {
7811         if (domain == 1 || (domain == 3 && table[3] == opcode))
7812           validDomains = 0xa;
7813         else
7814           validDomains = 0xc;
7815       }
7816     }
7817   }
7818   return std::make_pair(domain, validDomains);
7819 }
7820 
7821 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
7822   assert(Domain>0 && Domain<4 && "Invalid execution domain");
7823   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7824   assert(dom && "Not an SSE instruction");
7825 
7826   // Attempt to match for custom instructions.
7827   if (setExecutionDomainCustom(MI, Domain))
7828     return;
7829 
7830   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
7831   if (!table) { // try the other table
7832     assert((Subtarget.hasAVX2() || Domain < 3) &&
7833            "256-bit vector operations only available in AVX2");
7834     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
7835   }
7836   if (!table) { // try the FP table
7837     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
7838     assert((!table || Domain < 3) &&
7839            "Can only select PackedSingle or PackedDouble");
7840   }
7841   if (!table) { // try the other table
7842     assert(Subtarget.hasAVX2() &&
7843            "256-bit insert/extract only available in AVX2");
7844     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
7845   }
7846   if (!table) { // try the AVX512 table
7847     assert(Subtarget.hasAVX512() && "Requires AVX-512");
7848     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
7849     // Don't change integer Q instructions to D instructions.
7850     if (table && Domain == 3 && table[3] == MI.getOpcode())
7851       Domain = 4;
7852   }
7853   if (!table) { // try the AVX512DQ table
7854     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7855     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
7856     // Don't change integer Q instructions to D instructions and
7857     // use D instructions if we started with a PS instruction.
7858     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7859       Domain = 4;
7860   }
7861   if (!table) { // try the AVX512DQMasked table
7862     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7863     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
7864     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7865       Domain = 4;
7866   }
7867   assert(table && "Cannot change domain");
7868   MI.setDesc(get(table[Domain - 1]));
7869 }
7870 
7871 /// Return the noop instruction to use for a noop.
7872 MCInst X86InstrInfo::getNop() const {
7873   MCInst Nop;
7874   Nop.setOpcode(X86::NOOP);
7875   return Nop;
7876 }
7877 
7878 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7879   switch (opc) {
7880   default: return false;
7881   case X86::DIVPDrm:
7882   case X86::DIVPDrr:
7883   case X86::DIVPSrm:
7884   case X86::DIVPSrr:
7885   case X86::DIVSDrm:
7886   case X86::DIVSDrm_Int:
7887   case X86::DIVSDrr:
7888   case X86::DIVSDrr_Int:
7889   case X86::DIVSSrm:
7890   case X86::DIVSSrm_Int:
7891   case X86::DIVSSrr:
7892   case X86::DIVSSrr_Int:
7893   case X86::SQRTPDm:
7894   case X86::SQRTPDr:
7895   case X86::SQRTPSm:
7896   case X86::SQRTPSr:
7897   case X86::SQRTSDm:
7898   case X86::SQRTSDm_Int:
7899   case X86::SQRTSDr:
7900   case X86::SQRTSDr_Int:
7901   case X86::SQRTSSm:
7902   case X86::SQRTSSm_Int:
7903   case X86::SQRTSSr:
7904   case X86::SQRTSSr_Int:
7905   // AVX instructions with high latency
7906   case X86::VDIVPDrm:
7907   case X86::VDIVPDrr:
7908   case X86::VDIVPDYrm:
7909   case X86::VDIVPDYrr:
7910   case X86::VDIVPSrm:
7911   case X86::VDIVPSrr:
7912   case X86::VDIVPSYrm:
7913   case X86::VDIVPSYrr:
7914   case X86::VDIVSDrm:
7915   case X86::VDIVSDrm_Int:
7916   case X86::VDIVSDrr:
7917   case X86::VDIVSDrr_Int:
7918   case X86::VDIVSSrm:
7919   case X86::VDIVSSrm_Int:
7920   case X86::VDIVSSrr:
7921   case X86::VDIVSSrr_Int:
7922   case X86::VSQRTPDm:
7923   case X86::VSQRTPDr:
7924   case X86::VSQRTPDYm:
7925   case X86::VSQRTPDYr:
7926   case X86::VSQRTPSm:
7927   case X86::VSQRTPSr:
7928   case X86::VSQRTPSYm:
7929   case X86::VSQRTPSYr:
7930   case X86::VSQRTSDm:
7931   case X86::VSQRTSDm_Int:
7932   case X86::VSQRTSDr:
7933   case X86::VSQRTSDr_Int:
7934   case X86::VSQRTSSm:
7935   case X86::VSQRTSSm_Int:
7936   case X86::VSQRTSSr:
7937   case X86::VSQRTSSr_Int:
7938   // AVX512 instructions with high latency
7939   case X86::VDIVPDZ128rm:
7940   case X86::VDIVPDZ128rmb:
7941   case X86::VDIVPDZ128rmbk:
7942   case X86::VDIVPDZ128rmbkz:
7943   case X86::VDIVPDZ128rmk:
7944   case X86::VDIVPDZ128rmkz:
7945   case X86::VDIVPDZ128rr:
7946   case X86::VDIVPDZ128rrk:
7947   case X86::VDIVPDZ128rrkz:
7948   case X86::VDIVPDZ256rm:
7949   case X86::VDIVPDZ256rmb:
7950   case X86::VDIVPDZ256rmbk:
7951   case X86::VDIVPDZ256rmbkz:
7952   case X86::VDIVPDZ256rmk:
7953   case X86::VDIVPDZ256rmkz:
7954   case X86::VDIVPDZ256rr:
7955   case X86::VDIVPDZ256rrk:
7956   case X86::VDIVPDZ256rrkz:
7957   case X86::VDIVPDZrrb:
7958   case X86::VDIVPDZrrbk:
7959   case X86::VDIVPDZrrbkz:
7960   case X86::VDIVPDZrm:
7961   case X86::VDIVPDZrmb:
7962   case X86::VDIVPDZrmbk:
7963   case X86::VDIVPDZrmbkz:
7964   case X86::VDIVPDZrmk:
7965   case X86::VDIVPDZrmkz:
7966   case X86::VDIVPDZrr:
7967   case X86::VDIVPDZrrk:
7968   case X86::VDIVPDZrrkz:
7969   case X86::VDIVPSZ128rm:
7970   case X86::VDIVPSZ128rmb:
7971   case X86::VDIVPSZ128rmbk:
7972   case X86::VDIVPSZ128rmbkz:
7973   case X86::VDIVPSZ128rmk:
7974   case X86::VDIVPSZ128rmkz:
7975   case X86::VDIVPSZ128rr:
7976   case X86::VDIVPSZ128rrk:
7977   case X86::VDIVPSZ128rrkz:
7978   case X86::VDIVPSZ256rm:
7979   case X86::VDIVPSZ256rmb:
7980   case X86::VDIVPSZ256rmbk:
7981   case X86::VDIVPSZ256rmbkz:
7982   case X86::VDIVPSZ256rmk:
7983   case X86::VDIVPSZ256rmkz:
7984   case X86::VDIVPSZ256rr:
7985   case X86::VDIVPSZ256rrk:
7986   case X86::VDIVPSZ256rrkz:
7987   case X86::VDIVPSZrrb:
7988   case X86::VDIVPSZrrbk:
7989   case X86::VDIVPSZrrbkz:
7990   case X86::VDIVPSZrm:
7991   case X86::VDIVPSZrmb:
7992   case X86::VDIVPSZrmbk:
7993   case X86::VDIVPSZrmbkz:
7994   case X86::VDIVPSZrmk:
7995   case X86::VDIVPSZrmkz:
7996   case X86::VDIVPSZrr:
7997   case X86::VDIVPSZrrk:
7998   case X86::VDIVPSZrrkz:
7999   case X86::VDIVSDZrm:
8000   case X86::VDIVSDZrr:
8001   case X86::VDIVSDZrm_Int:
8002   case X86::VDIVSDZrm_Intk:
8003   case X86::VDIVSDZrm_Intkz:
8004   case X86::VDIVSDZrr_Int:
8005   case X86::VDIVSDZrr_Intk:
8006   case X86::VDIVSDZrr_Intkz:
8007   case X86::VDIVSDZrrb_Int:
8008   case X86::VDIVSDZrrb_Intk:
8009   case X86::VDIVSDZrrb_Intkz:
8010   case X86::VDIVSSZrm:
8011   case X86::VDIVSSZrr:
8012   case X86::VDIVSSZrm_Int:
8013   case X86::VDIVSSZrm_Intk:
8014   case X86::VDIVSSZrm_Intkz:
8015   case X86::VDIVSSZrr_Int:
8016   case X86::VDIVSSZrr_Intk:
8017   case X86::VDIVSSZrr_Intkz:
8018   case X86::VDIVSSZrrb_Int:
8019   case X86::VDIVSSZrrb_Intk:
8020   case X86::VDIVSSZrrb_Intkz:
8021   case X86::VSQRTPDZ128m:
8022   case X86::VSQRTPDZ128mb:
8023   case X86::VSQRTPDZ128mbk:
8024   case X86::VSQRTPDZ128mbkz:
8025   case X86::VSQRTPDZ128mk:
8026   case X86::VSQRTPDZ128mkz:
8027   case X86::VSQRTPDZ128r:
8028   case X86::VSQRTPDZ128rk:
8029   case X86::VSQRTPDZ128rkz:
8030   case X86::VSQRTPDZ256m:
8031   case X86::VSQRTPDZ256mb:
8032   case X86::VSQRTPDZ256mbk:
8033   case X86::VSQRTPDZ256mbkz:
8034   case X86::VSQRTPDZ256mk:
8035   case X86::VSQRTPDZ256mkz:
8036   case X86::VSQRTPDZ256r:
8037   case X86::VSQRTPDZ256rk:
8038   case X86::VSQRTPDZ256rkz:
8039   case X86::VSQRTPDZm:
8040   case X86::VSQRTPDZmb:
8041   case X86::VSQRTPDZmbk:
8042   case X86::VSQRTPDZmbkz:
8043   case X86::VSQRTPDZmk:
8044   case X86::VSQRTPDZmkz:
8045   case X86::VSQRTPDZr:
8046   case X86::VSQRTPDZrb:
8047   case X86::VSQRTPDZrbk:
8048   case X86::VSQRTPDZrbkz:
8049   case X86::VSQRTPDZrk:
8050   case X86::VSQRTPDZrkz:
8051   case X86::VSQRTPSZ128m:
8052   case X86::VSQRTPSZ128mb:
8053   case X86::VSQRTPSZ128mbk:
8054   case X86::VSQRTPSZ128mbkz:
8055   case X86::VSQRTPSZ128mk:
8056   case X86::VSQRTPSZ128mkz:
8057   case X86::VSQRTPSZ128r:
8058   case X86::VSQRTPSZ128rk:
8059   case X86::VSQRTPSZ128rkz:
8060   case X86::VSQRTPSZ256m:
8061   case X86::VSQRTPSZ256mb:
8062   case X86::VSQRTPSZ256mbk:
8063   case X86::VSQRTPSZ256mbkz:
8064   case X86::VSQRTPSZ256mk:
8065   case X86::VSQRTPSZ256mkz:
8066   case X86::VSQRTPSZ256r:
8067   case X86::VSQRTPSZ256rk:
8068   case X86::VSQRTPSZ256rkz:
8069   case X86::VSQRTPSZm:
8070   case X86::VSQRTPSZmb:
8071   case X86::VSQRTPSZmbk:
8072   case X86::VSQRTPSZmbkz:
8073   case X86::VSQRTPSZmk:
8074   case X86::VSQRTPSZmkz:
8075   case X86::VSQRTPSZr:
8076   case X86::VSQRTPSZrb:
8077   case X86::VSQRTPSZrbk:
8078   case X86::VSQRTPSZrbkz:
8079   case X86::VSQRTPSZrk:
8080   case X86::VSQRTPSZrkz:
8081   case X86::VSQRTSDZm:
8082   case X86::VSQRTSDZm_Int:
8083   case X86::VSQRTSDZm_Intk:
8084   case X86::VSQRTSDZm_Intkz:
8085   case X86::VSQRTSDZr:
8086   case X86::VSQRTSDZr_Int:
8087   case X86::VSQRTSDZr_Intk:
8088   case X86::VSQRTSDZr_Intkz:
8089   case X86::VSQRTSDZrb_Int:
8090   case X86::VSQRTSDZrb_Intk:
8091   case X86::VSQRTSDZrb_Intkz:
8092   case X86::VSQRTSSZm:
8093   case X86::VSQRTSSZm_Int:
8094   case X86::VSQRTSSZm_Intk:
8095   case X86::VSQRTSSZm_Intkz:
8096   case X86::VSQRTSSZr:
8097   case X86::VSQRTSSZr_Int:
8098   case X86::VSQRTSSZr_Intk:
8099   case X86::VSQRTSSZr_Intkz:
8100   case X86::VSQRTSSZrb_Int:
8101   case X86::VSQRTSSZrb_Intk:
8102   case X86::VSQRTSSZrb_Intkz:
8103 
8104   case X86::VGATHERDPDYrm:
8105   case X86::VGATHERDPDZ128rm:
8106   case X86::VGATHERDPDZ256rm:
8107   case X86::VGATHERDPDZrm:
8108   case X86::VGATHERDPDrm:
8109   case X86::VGATHERDPSYrm:
8110   case X86::VGATHERDPSZ128rm:
8111   case X86::VGATHERDPSZ256rm:
8112   case X86::VGATHERDPSZrm:
8113   case X86::VGATHERDPSrm:
8114   case X86::VGATHERPF0DPDm:
8115   case X86::VGATHERPF0DPSm:
8116   case X86::VGATHERPF0QPDm:
8117   case X86::VGATHERPF0QPSm:
8118   case X86::VGATHERPF1DPDm:
8119   case X86::VGATHERPF1DPSm:
8120   case X86::VGATHERPF1QPDm:
8121   case X86::VGATHERPF1QPSm:
8122   case X86::VGATHERQPDYrm:
8123   case X86::VGATHERQPDZ128rm:
8124   case X86::VGATHERQPDZ256rm:
8125   case X86::VGATHERQPDZrm:
8126   case X86::VGATHERQPDrm:
8127   case X86::VGATHERQPSYrm:
8128   case X86::VGATHERQPSZ128rm:
8129   case X86::VGATHERQPSZ256rm:
8130   case X86::VGATHERQPSZrm:
8131   case X86::VGATHERQPSrm:
8132   case X86::VPGATHERDDYrm:
8133   case X86::VPGATHERDDZ128rm:
8134   case X86::VPGATHERDDZ256rm:
8135   case X86::VPGATHERDDZrm:
8136   case X86::VPGATHERDDrm:
8137   case X86::VPGATHERDQYrm:
8138   case X86::VPGATHERDQZ128rm:
8139   case X86::VPGATHERDQZ256rm:
8140   case X86::VPGATHERDQZrm:
8141   case X86::VPGATHERDQrm:
8142   case X86::VPGATHERQDYrm:
8143   case X86::VPGATHERQDZ128rm:
8144   case X86::VPGATHERQDZ256rm:
8145   case X86::VPGATHERQDZrm:
8146   case X86::VPGATHERQDrm:
8147   case X86::VPGATHERQQYrm:
8148   case X86::VPGATHERQQZ128rm:
8149   case X86::VPGATHERQQZ256rm:
8150   case X86::VPGATHERQQZrm:
8151   case X86::VPGATHERQQrm:
8152   case X86::VSCATTERDPDZ128mr:
8153   case X86::VSCATTERDPDZ256mr:
8154   case X86::VSCATTERDPDZmr:
8155   case X86::VSCATTERDPSZ128mr:
8156   case X86::VSCATTERDPSZ256mr:
8157   case X86::VSCATTERDPSZmr:
8158   case X86::VSCATTERPF0DPDm:
8159   case X86::VSCATTERPF0DPSm:
8160   case X86::VSCATTERPF0QPDm:
8161   case X86::VSCATTERPF0QPSm:
8162   case X86::VSCATTERPF1DPDm:
8163   case X86::VSCATTERPF1DPSm:
8164   case X86::VSCATTERPF1QPDm:
8165   case X86::VSCATTERPF1QPSm:
8166   case X86::VSCATTERQPDZ128mr:
8167   case X86::VSCATTERQPDZ256mr:
8168   case X86::VSCATTERQPDZmr:
8169   case X86::VSCATTERQPSZ128mr:
8170   case X86::VSCATTERQPSZ256mr:
8171   case X86::VSCATTERQPSZmr:
8172   case X86::VPSCATTERDDZ128mr:
8173   case X86::VPSCATTERDDZ256mr:
8174   case X86::VPSCATTERDDZmr:
8175   case X86::VPSCATTERDQZ128mr:
8176   case X86::VPSCATTERDQZ256mr:
8177   case X86::VPSCATTERDQZmr:
8178   case X86::VPSCATTERQDZ128mr:
8179   case X86::VPSCATTERQDZ256mr:
8180   case X86::VPSCATTERQDZmr:
8181   case X86::VPSCATTERQQZ128mr:
8182   case X86::VPSCATTERQQZ256mr:
8183   case X86::VPSCATTERQQZmr:
8184     return true;
8185   }
8186 }
8187 
8188 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
8189                                          const MachineRegisterInfo *MRI,
8190                                          const MachineInstr &DefMI,
8191                                          unsigned DefIdx,
8192                                          const MachineInstr &UseMI,
8193                                          unsigned UseIdx) const {
8194   return isHighLatencyDef(DefMI.getOpcode());
8195 }
8196 
8197 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
8198                                            const MachineBasicBlock *MBB) const {
8199   assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
8200          Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
8201 
8202   // Integer binary math/logic instructions have a third source operand:
8203   // the EFLAGS register. That operand must be both defined here and never
8204   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
8205   // not change anything because rearranging the operands could affect other
8206   // instructions that depend on the exact status flags (zero, sign, etc.)
8207   // that are set by using these particular operands with this operation.
8208   const MachineOperand *FlagDef = Inst.findRegisterDefOperand(X86::EFLAGS);
8209   assert((Inst.getNumDefs() == 1 || FlagDef) &&
8210          "Implicit def isn't flags?");
8211   if (FlagDef && !FlagDef->isDead())
8212     return false;
8213 
8214   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
8215 }
8216 
8217 // TODO: There are many more machine instruction opcodes to match:
8218 //       1. Other data types (integer, vectors)
8219 //       2. Other math / logic operations (xor, or)
8220 //       3. Other forms of the same operation (intrinsics and other variants)
8221 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
8222   switch (Inst.getOpcode()) {
8223   case X86::AND8rr:
8224   case X86::AND16rr:
8225   case X86::AND32rr:
8226   case X86::AND64rr:
8227   case X86::OR8rr:
8228   case X86::OR16rr:
8229   case X86::OR32rr:
8230   case X86::OR64rr:
8231   case X86::XOR8rr:
8232   case X86::XOR16rr:
8233   case X86::XOR32rr:
8234   case X86::XOR64rr:
8235   case X86::IMUL16rr:
8236   case X86::IMUL32rr:
8237   case X86::IMUL64rr:
8238   case X86::PANDrr:
8239   case X86::PORrr:
8240   case X86::PXORrr:
8241   case X86::ANDPDrr:
8242   case X86::ANDPSrr:
8243   case X86::ORPDrr:
8244   case X86::ORPSrr:
8245   case X86::XORPDrr:
8246   case X86::XORPSrr:
8247   case X86::PADDBrr:
8248   case X86::PADDWrr:
8249   case X86::PADDDrr:
8250   case X86::PADDQrr:
8251   case X86::PMULLWrr:
8252   case X86::PMULLDrr:
8253   case X86::PMAXSBrr:
8254   case X86::PMAXSDrr:
8255   case X86::PMAXSWrr:
8256   case X86::PMAXUBrr:
8257   case X86::PMAXUDrr:
8258   case X86::PMAXUWrr:
8259   case X86::PMINSBrr:
8260   case X86::PMINSDrr:
8261   case X86::PMINSWrr:
8262   case X86::PMINUBrr:
8263   case X86::PMINUDrr:
8264   case X86::PMINUWrr:
8265   case X86::VPANDrr:
8266   case X86::VPANDYrr:
8267   case X86::VPANDDZ128rr:
8268   case X86::VPANDDZ256rr:
8269   case X86::VPANDDZrr:
8270   case X86::VPANDQZ128rr:
8271   case X86::VPANDQZ256rr:
8272   case X86::VPANDQZrr:
8273   case X86::VPORrr:
8274   case X86::VPORYrr:
8275   case X86::VPORDZ128rr:
8276   case X86::VPORDZ256rr:
8277   case X86::VPORDZrr:
8278   case X86::VPORQZ128rr:
8279   case X86::VPORQZ256rr:
8280   case X86::VPORQZrr:
8281   case X86::VPXORrr:
8282   case X86::VPXORYrr:
8283   case X86::VPXORDZ128rr:
8284   case X86::VPXORDZ256rr:
8285   case X86::VPXORDZrr:
8286   case X86::VPXORQZ128rr:
8287   case X86::VPXORQZ256rr:
8288   case X86::VPXORQZrr:
8289   case X86::VANDPDrr:
8290   case X86::VANDPSrr:
8291   case X86::VANDPDYrr:
8292   case X86::VANDPSYrr:
8293   case X86::VANDPDZ128rr:
8294   case X86::VANDPSZ128rr:
8295   case X86::VANDPDZ256rr:
8296   case X86::VANDPSZ256rr:
8297   case X86::VANDPDZrr:
8298   case X86::VANDPSZrr:
8299   case X86::VORPDrr:
8300   case X86::VORPSrr:
8301   case X86::VORPDYrr:
8302   case X86::VORPSYrr:
8303   case X86::VORPDZ128rr:
8304   case X86::VORPSZ128rr:
8305   case X86::VORPDZ256rr:
8306   case X86::VORPSZ256rr:
8307   case X86::VORPDZrr:
8308   case X86::VORPSZrr:
8309   case X86::VXORPDrr:
8310   case X86::VXORPSrr:
8311   case X86::VXORPDYrr:
8312   case X86::VXORPSYrr:
8313   case X86::VXORPDZ128rr:
8314   case X86::VXORPSZ128rr:
8315   case X86::VXORPDZ256rr:
8316   case X86::VXORPSZ256rr:
8317   case X86::VXORPDZrr:
8318   case X86::VXORPSZrr:
8319   case X86::KADDBrr:
8320   case X86::KADDWrr:
8321   case X86::KADDDrr:
8322   case X86::KADDQrr:
8323   case X86::KANDBrr:
8324   case X86::KANDWrr:
8325   case X86::KANDDrr:
8326   case X86::KANDQrr:
8327   case X86::KORBrr:
8328   case X86::KORWrr:
8329   case X86::KORDrr:
8330   case X86::KORQrr:
8331   case X86::KXORBrr:
8332   case X86::KXORWrr:
8333   case X86::KXORDrr:
8334   case X86::KXORQrr:
8335   case X86::VPADDBrr:
8336   case X86::VPADDWrr:
8337   case X86::VPADDDrr:
8338   case X86::VPADDQrr:
8339   case X86::VPADDBYrr:
8340   case X86::VPADDWYrr:
8341   case X86::VPADDDYrr:
8342   case X86::VPADDQYrr:
8343   case X86::VPADDBZ128rr:
8344   case X86::VPADDWZ128rr:
8345   case X86::VPADDDZ128rr:
8346   case X86::VPADDQZ128rr:
8347   case X86::VPADDBZ256rr:
8348   case X86::VPADDWZ256rr:
8349   case X86::VPADDDZ256rr:
8350   case X86::VPADDQZ256rr:
8351   case X86::VPADDBZrr:
8352   case X86::VPADDWZrr:
8353   case X86::VPADDDZrr:
8354   case X86::VPADDQZrr:
8355   case X86::VPMULLWrr:
8356   case X86::VPMULLWYrr:
8357   case X86::VPMULLWZ128rr:
8358   case X86::VPMULLWZ256rr:
8359   case X86::VPMULLWZrr:
8360   case X86::VPMULLDrr:
8361   case X86::VPMULLDYrr:
8362   case X86::VPMULLDZ128rr:
8363   case X86::VPMULLDZ256rr:
8364   case X86::VPMULLDZrr:
8365   case X86::VPMULLQZ128rr:
8366   case X86::VPMULLQZ256rr:
8367   case X86::VPMULLQZrr:
8368   case X86::VPMAXSBrr:
8369   case X86::VPMAXSBYrr:
8370   case X86::VPMAXSBZ128rr:
8371   case X86::VPMAXSBZ256rr:
8372   case X86::VPMAXSBZrr:
8373   case X86::VPMAXSDrr:
8374   case X86::VPMAXSDYrr:
8375   case X86::VPMAXSDZ128rr:
8376   case X86::VPMAXSDZ256rr:
8377   case X86::VPMAXSDZrr:
8378   case X86::VPMAXSQZ128rr:
8379   case X86::VPMAXSQZ256rr:
8380   case X86::VPMAXSQZrr:
8381   case X86::VPMAXSWrr:
8382   case X86::VPMAXSWYrr:
8383   case X86::VPMAXSWZ128rr:
8384   case X86::VPMAXSWZ256rr:
8385   case X86::VPMAXSWZrr:
8386   case X86::VPMAXUBrr:
8387   case X86::VPMAXUBYrr:
8388   case X86::VPMAXUBZ128rr:
8389   case X86::VPMAXUBZ256rr:
8390   case X86::VPMAXUBZrr:
8391   case X86::VPMAXUDrr:
8392   case X86::VPMAXUDYrr:
8393   case X86::VPMAXUDZ128rr:
8394   case X86::VPMAXUDZ256rr:
8395   case X86::VPMAXUDZrr:
8396   case X86::VPMAXUQZ128rr:
8397   case X86::VPMAXUQZ256rr:
8398   case X86::VPMAXUQZrr:
8399   case X86::VPMAXUWrr:
8400   case X86::VPMAXUWYrr:
8401   case X86::VPMAXUWZ128rr:
8402   case X86::VPMAXUWZ256rr:
8403   case X86::VPMAXUWZrr:
8404   case X86::VPMINSBrr:
8405   case X86::VPMINSBYrr:
8406   case X86::VPMINSBZ128rr:
8407   case X86::VPMINSBZ256rr:
8408   case X86::VPMINSBZrr:
8409   case X86::VPMINSDrr:
8410   case X86::VPMINSDYrr:
8411   case X86::VPMINSDZ128rr:
8412   case X86::VPMINSDZ256rr:
8413   case X86::VPMINSDZrr:
8414   case X86::VPMINSQZ128rr:
8415   case X86::VPMINSQZ256rr:
8416   case X86::VPMINSQZrr:
8417   case X86::VPMINSWrr:
8418   case X86::VPMINSWYrr:
8419   case X86::VPMINSWZ128rr:
8420   case X86::VPMINSWZ256rr:
8421   case X86::VPMINSWZrr:
8422   case X86::VPMINUBrr:
8423   case X86::VPMINUBYrr:
8424   case X86::VPMINUBZ128rr:
8425   case X86::VPMINUBZ256rr:
8426   case X86::VPMINUBZrr:
8427   case X86::VPMINUDrr:
8428   case X86::VPMINUDYrr:
8429   case X86::VPMINUDZ128rr:
8430   case X86::VPMINUDZ256rr:
8431   case X86::VPMINUDZrr:
8432   case X86::VPMINUQZ128rr:
8433   case X86::VPMINUQZ256rr:
8434   case X86::VPMINUQZrr:
8435   case X86::VPMINUWrr:
8436   case X86::VPMINUWYrr:
8437   case X86::VPMINUWZ128rr:
8438   case X86::VPMINUWZ256rr:
8439   case X86::VPMINUWZrr:
8440   // Normal min/max instructions are not commutative because of NaN and signed
8441   // zero semantics, but these are. Thus, there's no need to check for global
8442   // relaxed math; the instructions themselves have the properties we need.
8443   case X86::MAXCPDrr:
8444   case X86::MAXCPSrr:
8445   case X86::MAXCSDrr:
8446   case X86::MAXCSSrr:
8447   case X86::MINCPDrr:
8448   case X86::MINCPSrr:
8449   case X86::MINCSDrr:
8450   case X86::MINCSSrr:
8451   case X86::VMAXCPDrr:
8452   case X86::VMAXCPSrr:
8453   case X86::VMAXCPDYrr:
8454   case X86::VMAXCPSYrr:
8455   case X86::VMAXCPDZ128rr:
8456   case X86::VMAXCPSZ128rr:
8457   case X86::VMAXCPDZ256rr:
8458   case X86::VMAXCPSZ256rr:
8459   case X86::VMAXCPDZrr:
8460   case X86::VMAXCPSZrr:
8461   case X86::VMAXCSDrr:
8462   case X86::VMAXCSSrr:
8463   case X86::VMAXCSDZrr:
8464   case X86::VMAXCSSZrr:
8465   case X86::VMINCPDrr:
8466   case X86::VMINCPSrr:
8467   case X86::VMINCPDYrr:
8468   case X86::VMINCPSYrr:
8469   case X86::VMINCPDZ128rr:
8470   case X86::VMINCPSZ128rr:
8471   case X86::VMINCPDZ256rr:
8472   case X86::VMINCPSZ256rr:
8473   case X86::VMINCPDZrr:
8474   case X86::VMINCPSZrr:
8475   case X86::VMINCSDrr:
8476   case X86::VMINCSSrr:
8477   case X86::VMINCSDZrr:
8478   case X86::VMINCSSZrr:
8479   case X86::VMAXCPHZ128rr:
8480   case X86::VMAXCPHZ256rr:
8481   case X86::VMAXCPHZrr:
8482   case X86::VMAXCSHZrr:
8483   case X86::VMINCPHZ128rr:
8484   case X86::VMINCPHZ256rr:
8485   case X86::VMINCPHZrr:
8486   case X86::VMINCSHZrr:
8487     return true;
8488   case X86::ADDPDrr:
8489   case X86::ADDPSrr:
8490   case X86::ADDSDrr:
8491   case X86::ADDSSrr:
8492   case X86::MULPDrr:
8493   case X86::MULPSrr:
8494   case X86::MULSDrr:
8495   case X86::MULSSrr:
8496   case X86::VADDPDrr:
8497   case X86::VADDPSrr:
8498   case X86::VADDPDYrr:
8499   case X86::VADDPSYrr:
8500   case X86::VADDPDZ128rr:
8501   case X86::VADDPSZ128rr:
8502   case X86::VADDPDZ256rr:
8503   case X86::VADDPSZ256rr:
8504   case X86::VADDPDZrr:
8505   case X86::VADDPSZrr:
8506   case X86::VADDSDrr:
8507   case X86::VADDSSrr:
8508   case X86::VADDSDZrr:
8509   case X86::VADDSSZrr:
8510   case X86::VMULPDrr:
8511   case X86::VMULPSrr:
8512   case X86::VMULPDYrr:
8513   case X86::VMULPSYrr:
8514   case X86::VMULPDZ128rr:
8515   case X86::VMULPSZ128rr:
8516   case X86::VMULPDZ256rr:
8517   case X86::VMULPSZ256rr:
8518   case X86::VMULPDZrr:
8519   case X86::VMULPSZrr:
8520   case X86::VMULSDrr:
8521   case X86::VMULSSrr:
8522   case X86::VMULSDZrr:
8523   case X86::VMULSSZrr:
8524   case X86::VADDPHZ128rr:
8525   case X86::VADDPHZ256rr:
8526   case X86::VADDPHZrr:
8527   case X86::VADDSHZrr:
8528   case X86::VMULPHZ128rr:
8529   case X86::VMULPHZ256rr:
8530   case X86::VMULPHZrr:
8531   case X86::VMULSHZrr:
8532     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
8533            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
8534   default:
8535     return false;
8536   }
8537 }
8538 
8539 /// If \p DescribedReg overlaps with the MOVrr instruction's destination
8540 /// register then, if possible, describe the value in terms of the source
8541 /// register.
8542 static Optional<ParamLoadedValue>
8543 describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
8544                          const TargetRegisterInfo *TRI) {
8545   Register DestReg = MI.getOperand(0).getReg();
8546   Register SrcReg = MI.getOperand(1).getReg();
8547 
8548   auto Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8549 
8550   // If the described register is the destination, just return the source.
8551   if (DestReg == DescribedReg)
8552     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8553 
8554   // If the described register is a sub-register of the destination register,
8555   // then pick out the source register's corresponding sub-register.
8556   if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) {
8557     Register SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx);
8558     return ParamLoadedValue(MachineOperand::CreateReg(SrcSubReg, false), Expr);
8559   }
8560 
8561   // The remaining case to consider is when the described register is a
8562   // super-register of the destination register. MOV8rr and MOV16rr does not
8563   // write to any of the other bytes in the register, meaning that we'd have to
8564   // describe the value using a combination of the source register and the
8565   // non-overlapping bits in the described register, which is not currently
8566   // possible.
8567   if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
8568       !TRI->isSuperRegister(DestReg, DescribedReg))
8569     return None;
8570 
8571   assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
8572   return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8573 }
8574 
8575 Optional<ParamLoadedValue>
8576 X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
8577   const MachineOperand *Op = nullptr;
8578   DIExpression *Expr = nullptr;
8579 
8580   const TargetRegisterInfo *TRI = &getRegisterInfo();
8581 
8582   switch (MI.getOpcode()) {
8583   case X86::LEA32r:
8584   case X86::LEA64r:
8585   case X86::LEA64_32r: {
8586     // We may need to describe a 64-bit parameter with a 32-bit LEA.
8587     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8588       return None;
8589 
8590     // Operand 4 could be global address. For now we do not support
8591     // such situation.
8592     if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
8593       return None;
8594 
8595     const MachineOperand &Op1 = MI.getOperand(1);
8596     const MachineOperand &Op2 = MI.getOperand(3);
8597     assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
8598                            Register::isPhysicalRegister(Op2.getReg())));
8599 
8600     // Omit situations like:
8601     // %rsi = lea %rsi, 4, ...
8602     if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
8603         Op2.getReg() == MI.getOperand(0).getReg())
8604       return None;
8605     else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
8606               TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
8607              (Op2.getReg() != X86::NoRegister &&
8608               TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
8609       return None;
8610 
8611     int64_t Coef = MI.getOperand(2).getImm();
8612     int64_t Offset = MI.getOperand(4).getImm();
8613     SmallVector<uint64_t, 8> Ops;
8614 
8615     if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
8616       Op = &Op1;
8617     } else if (Op1.isFI())
8618       Op = &Op1;
8619 
8620     if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
8621       Ops.push_back(dwarf::DW_OP_constu);
8622       Ops.push_back(Coef + 1);
8623       Ops.push_back(dwarf::DW_OP_mul);
8624     } else {
8625       if (Op && Op2.getReg() != X86::NoRegister) {
8626         int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
8627         if (dwarfReg < 0)
8628           return None;
8629         else if (dwarfReg < 32) {
8630           Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
8631           Ops.push_back(0);
8632         } else {
8633           Ops.push_back(dwarf::DW_OP_bregx);
8634           Ops.push_back(dwarfReg);
8635           Ops.push_back(0);
8636         }
8637       } else if (!Op) {
8638         assert(Op2.getReg() != X86::NoRegister);
8639         Op = &Op2;
8640       }
8641 
8642       if (Coef > 1) {
8643         assert(Op2.getReg() != X86::NoRegister);
8644         Ops.push_back(dwarf::DW_OP_constu);
8645         Ops.push_back(Coef);
8646         Ops.push_back(dwarf::DW_OP_mul);
8647       }
8648 
8649       if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
8650           Op2.getReg() != X86::NoRegister) {
8651         Ops.push_back(dwarf::DW_OP_plus);
8652       }
8653     }
8654 
8655     DIExpression::appendOffset(Ops, Offset);
8656     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
8657 
8658     return ParamLoadedValue(*Op, Expr);;
8659   }
8660   case X86::MOV8ri:
8661   case X86::MOV16ri:
8662     // TODO: Handle MOV8ri and MOV16ri.
8663     return None;
8664   case X86::MOV32ri:
8665   case X86::MOV64ri:
8666   case X86::MOV64ri32:
8667     // MOV32ri may be used for producing zero-extended 32-bit immediates in
8668     // 64-bit parameters, so we need to consider super-registers.
8669     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8670       return None;
8671     return ParamLoadedValue(MI.getOperand(1), Expr);
8672   case X86::MOV8rr:
8673   case X86::MOV16rr:
8674   case X86::MOV32rr:
8675   case X86::MOV64rr:
8676     return describeMOVrrLoadedValue(MI, Reg, TRI);
8677   case X86::XOR32rr: {
8678     // 64-bit parameters are zero-materialized using XOR32rr, so also consider
8679     // super-registers.
8680     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8681       return None;
8682     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
8683       return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
8684     return None;
8685   }
8686   case X86::MOVSX64rr32: {
8687     // We may need to describe the lower 32 bits of the MOVSX; for example, in
8688     // cases like this:
8689     //
8690     //  $ebx = [...]
8691     //  $rdi = MOVSX64rr32 $ebx
8692     //  $esi = MOV32rr $edi
8693     if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg))
8694       return None;
8695 
8696     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8697 
8698     // If the described register is the destination register we need to
8699     // sign-extend the source register from 32 bits. The other case we handle
8700     // is when the described register is the 32-bit sub-register of the
8701     // destination register, in case we just need to return the source
8702     // register.
8703     if (Reg == MI.getOperand(0).getReg())
8704       Expr = DIExpression::appendExt(Expr, 32, 64, true);
8705     else
8706       assert(X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg) &&
8707              "Unhandled sub-register case for MOVSX64rr32");
8708 
8709     return ParamLoadedValue(MI.getOperand(1), Expr);
8710   }
8711   default:
8712     assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
8713     return TargetInstrInfo::describeLoadedValue(MI, Reg);
8714   }
8715 }
8716 
8717 /// This is an architecture-specific helper function of reassociateOps.
8718 /// Set special operand attributes for new instructions after reassociation.
8719 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
8720                                          MachineInstr &OldMI2,
8721                                          MachineInstr &NewMI1,
8722                                          MachineInstr &NewMI2) const {
8723   // Propagate FP flags from the original instructions.
8724   // But clear poison-generating flags because those may not be valid now.
8725   // TODO: There should be a helper function for copying only fast-math-flags.
8726   uint16_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
8727   NewMI1.setFlags(IntersectedFlags);
8728   NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
8729   NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
8730   NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
8731 
8732   NewMI2.setFlags(IntersectedFlags);
8733   NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
8734   NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
8735   NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
8736 
8737   // Integer instructions may define an implicit EFLAGS dest register operand.
8738   MachineOperand *OldFlagDef1 = OldMI1.findRegisterDefOperand(X86::EFLAGS);
8739   MachineOperand *OldFlagDef2 = OldMI2.findRegisterDefOperand(X86::EFLAGS);
8740 
8741   assert(!OldFlagDef1 == !OldFlagDef2 &&
8742          "Unexpected instruction type for reassociation");
8743 
8744   if (!OldFlagDef1 || !OldFlagDef2)
8745     return;
8746 
8747   assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
8748          "Must have dead EFLAGS operand in reassociable instruction");
8749 
8750   MachineOperand *NewFlagDef1 = NewMI1.findRegisterDefOperand(X86::EFLAGS);
8751   MachineOperand *NewFlagDef2 = NewMI2.findRegisterDefOperand(X86::EFLAGS);
8752 
8753   assert(NewFlagDef1 && NewFlagDef2 &&
8754          "Unexpected operand in reassociable instruction");
8755 
8756   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8757   // of this pass or other passes. The EFLAGS operands must be dead in these new
8758   // instructions because the EFLAGS operands in the original instructions must
8759   // be dead in order for reassociation to occur.
8760   NewFlagDef1->setIsDead();
8761   NewFlagDef2->setIsDead();
8762 }
8763 
8764 std::pair<unsigned, unsigned>
8765 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8766   return std::make_pair(TF, 0u);
8767 }
8768 
8769 ArrayRef<std::pair<unsigned, const char *>>
8770 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8771   using namespace X86II;
8772   static const std::pair<unsigned, const char *> TargetFlags[] = {
8773       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8774       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
8775       {MO_GOT, "x86-got"},
8776       {MO_GOTOFF, "x86-gotoff"},
8777       {MO_GOTPCREL, "x86-gotpcrel"},
8778       {MO_GOTPCREL_NORELAX, "x86-gotpcrel-norelax"},
8779       {MO_PLT, "x86-plt"},
8780       {MO_TLSGD, "x86-tlsgd"},
8781       {MO_TLSLD, "x86-tlsld"},
8782       {MO_TLSLDM, "x86-tlsldm"},
8783       {MO_GOTTPOFF, "x86-gottpoff"},
8784       {MO_INDNTPOFF, "x86-indntpoff"},
8785       {MO_TPOFF, "x86-tpoff"},
8786       {MO_DTPOFF, "x86-dtpoff"},
8787       {MO_NTPOFF, "x86-ntpoff"},
8788       {MO_GOTNTPOFF, "x86-gotntpoff"},
8789       {MO_DLLIMPORT, "x86-dllimport"},
8790       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
8791       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
8792       {MO_TLVP, "x86-tlvp"},
8793       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
8794       {MO_SECREL, "x86-secrel"},
8795       {MO_COFFSTUB, "x86-coffstub"}};
8796   return makeArrayRef(TargetFlags);
8797 }
8798 
8799 namespace {
8800   /// Create Global Base Reg pass. This initializes the PIC
8801   /// global base register for x86-32.
8802   struct CGBR : public MachineFunctionPass {
8803     static char ID;
8804     CGBR() : MachineFunctionPass(ID) {}
8805 
8806     bool runOnMachineFunction(MachineFunction &MF) override {
8807       const X86TargetMachine *TM =
8808         static_cast<const X86TargetMachine *>(&MF.getTarget());
8809       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
8810 
8811       // Don't do anything in the 64-bit small and kernel code models. They use
8812       // RIP-relative addressing for everything.
8813       if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
8814                             TM->getCodeModel() == CodeModel::Kernel))
8815         return false;
8816 
8817       // Only emit a global base reg in PIC mode.
8818       if (!TM->isPositionIndependent())
8819         return false;
8820 
8821       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8822       Register GlobalBaseReg = X86FI->getGlobalBaseReg();
8823 
8824       // If we didn't need a GlobalBaseReg, don't insert code.
8825       if (GlobalBaseReg == 0)
8826         return false;
8827 
8828       // Insert the set of GlobalBaseReg into the first MBB of the function
8829       MachineBasicBlock &FirstMBB = MF.front();
8830       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
8831       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
8832       MachineRegisterInfo &RegInfo = MF.getRegInfo();
8833       const X86InstrInfo *TII = STI.getInstrInfo();
8834 
8835       Register PC;
8836       if (STI.isPICStyleGOT())
8837         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
8838       else
8839         PC = GlobalBaseReg;
8840 
8841       if (STI.is64Bit()) {
8842         if (TM->getCodeModel() == CodeModel::Medium) {
8843           // In the medium code model, use a RIP-relative LEA to materialize the
8844           // GOT.
8845           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
8846               .addReg(X86::RIP)
8847               .addImm(0)
8848               .addReg(0)
8849               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
8850               .addReg(0);
8851         } else if (TM->getCodeModel() == CodeModel::Large) {
8852           // In the large code model, we are aiming for this code, though the
8853           // register allocation may vary:
8854           //   leaq .LN$pb(%rip), %rax
8855           //   movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
8856           //   addq %rcx, %rax
8857           // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
8858           Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8859           Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8860           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
8861               .addReg(X86::RIP)
8862               .addImm(0)
8863               .addReg(0)
8864               .addSym(MF.getPICBaseSymbol())
8865               .addReg(0);
8866           std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
8867           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
8868               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8869                                  X86II::MO_PIC_BASE_OFFSET);
8870           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
8871               .addReg(PBReg, RegState::Kill)
8872               .addReg(GOTReg, RegState::Kill);
8873         } else {
8874           llvm_unreachable("unexpected code model");
8875         }
8876       } else {
8877         // Operand of MovePCtoStack is completely ignored by asm printer. It's
8878         // only used in JIT code emission as displacement to pc.
8879         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
8880 
8881         // If we're using vanilla 'GOT' PIC style, we should use relative
8882         // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
8883         if (STI.isPICStyleGOT()) {
8884           // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
8885           // %some_register
8886           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
8887               .addReg(PC)
8888               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8889                                  X86II::MO_GOT_ABSOLUTE_ADDRESS);
8890         }
8891       }
8892 
8893       return true;
8894     }
8895 
8896     StringRef getPassName() const override {
8897       return "X86 PIC Global Base Reg Initialization";
8898     }
8899 
8900     void getAnalysisUsage(AnalysisUsage &AU) const override {
8901       AU.setPreservesCFG();
8902       MachineFunctionPass::getAnalysisUsage(AU);
8903     }
8904   };
8905 } // namespace
8906 
8907 char CGBR::ID = 0;
8908 FunctionPass*
8909 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
8910 
8911 namespace {
8912   struct LDTLSCleanup : public MachineFunctionPass {
8913     static char ID;
8914     LDTLSCleanup() : MachineFunctionPass(ID) {}
8915 
8916     bool runOnMachineFunction(MachineFunction &MF) override {
8917       if (skipFunction(MF.getFunction()))
8918         return false;
8919 
8920       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
8921       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8922         // No point folding accesses if there isn't at least two.
8923         return false;
8924       }
8925 
8926       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8927       return VisitNode(DT->getRootNode(), 0);
8928     }
8929 
8930     // Visit the dominator subtree rooted at Node in pre-order.
8931     // If TLSBaseAddrReg is non-null, then use that to replace any
8932     // TLS_base_addr instructions. Otherwise, create the register
8933     // when the first such instruction is seen, and then use it
8934     // as we encounter more instructions.
8935     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8936       MachineBasicBlock *BB = Node->getBlock();
8937       bool Changed = false;
8938 
8939       // Traverse the current block.
8940       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8941            ++I) {
8942         switch (I->getOpcode()) {
8943           case X86::TLS_base_addr32:
8944           case X86::TLS_base_addr64:
8945             if (TLSBaseAddrReg)
8946               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
8947             else
8948               I = SetRegister(*I, &TLSBaseAddrReg);
8949             Changed = true;
8950             break;
8951           default:
8952             break;
8953         }
8954       }
8955 
8956       // Visit the children of this block in the dominator tree.
8957       for (auto I = Node->begin(), E = Node->end(); I != E; ++I) {
8958         Changed |= VisitNode(*I, TLSBaseAddrReg);
8959       }
8960 
8961       return Changed;
8962     }
8963 
8964     // Replace the TLS_base_addr instruction I with a copy from
8965     // TLSBaseAddrReg, returning the new instruction.
8966     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
8967                                          unsigned TLSBaseAddrReg) {
8968       MachineFunction *MF = I.getParent()->getParent();
8969       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8970       const bool is64Bit = STI.is64Bit();
8971       const X86InstrInfo *TII = STI.getInstrInfo();
8972 
8973       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
8974       MachineInstr *Copy =
8975           BuildMI(*I.getParent(), I, I.getDebugLoc(),
8976                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8977               .addReg(TLSBaseAddrReg);
8978 
8979       // Erase the TLS_base_addr instruction.
8980       I.eraseFromParent();
8981 
8982       return Copy;
8983     }
8984 
8985     // Create a virtual register in *TLSBaseAddrReg, and populate it by
8986     // inserting a copy instruction after I. Returns the new instruction.
8987     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8988       MachineFunction *MF = I.getParent()->getParent();
8989       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8990       const bool is64Bit = STI.is64Bit();
8991       const X86InstrInfo *TII = STI.getInstrInfo();
8992 
8993       // Create a virtual register for the TLS base address.
8994       MachineRegisterInfo &RegInfo = MF->getRegInfo();
8995       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8996                                                       ? &X86::GR64RegClass
8997                                                       : &X86::GR32RegClass);
8998 
8999       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
9000       MachineInstr *Next = I.getNextNode();
9001       MachineInstr *Copy =
9002           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
9003                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
9004               .addReg(is64Bit ? X86::RAX : X86::EAX);
9005 
9006       return Copy;
9007     }
9008 
9009     StringRef getPassName() const override {
9010       return "Local Dynamic TLS Access Clean-up";
9011     }
9012 
9013     void getAnalysisUsage(AnalysisUsage &AU) const override {
9014       AU.setPreservesCFG();
9015       AU.addRequired<MachineDominatorTree>();
9016       MachineFunctionPass::getAnalysisUsage(AU);
9017     }
9018   };
9019 }
9020 
9021 char LDTLSCleanup::ID = 0;
9022 FunctionPass*
9023 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
9024 
9025 /// Constants defining how certain sequences should be outlined.
9026 ///
9027 /// \p MachineOutlinerDefault implies that the function is called with a call
9028 /// instruction, and a return must be emitted for the outlined function frame.
9029 ///
9030 /// That is,
9031 ///
9032 /// I1                                 OUTLINED_FUNCTION:
9033 /// I2 --> call OUTLINED_FUNCTION       I1
9034 /// I3                                  I2
9035 ///                                     I3
9036 ///                                     ret
9037 ///
9038 /// * Call construction overhead: 1 (call instruction)
9039 /// * Frame construction overhead: 1 (return instruction)
9040 ///
9041 /// \p MachineOutlinerTailCall implies that the function is being tail called.
9042 /// A jump is emitted instead of a call, and the return is already present in
9043 /// the outlined sequence. That is,
9044 ///
9045 /// I1                                 OUTLINED_FUNCTION:
9046 /// I2 --> jmp OUTLINED_FUNCTION       I1
9047 /// ret                                I2
9048 ///                                    ret
9049 ///
9050 /// * Call construction overhead: 1 (jump instruction)
9051 /// * Frame construction overhead: 0 (don't need to return)
9052 ///
9053 enum MachineOutlinerClass {
9054   MachineOutlinerDefault,
9055   MachineOutlinerTailCall
9056 };
9057 
9058 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
9059     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
9060   unsigned SequenceSize =
9061       std::accumulate(RepeatedSequenceLocs[0].front(),
9062                       std::next(RepeatedSequenceLocs[0].back()), 0,
9063                       [](unsigned Sum, const MachineInstr &MI) {
9064                         // FIXME: x86 doesn't implement getInstSizeInBytes, so
9065                         // we can't tell the cost.  Just assume each instruction
9066                         // is one byte.
9067                         if (MI.isDebugInstr() || MI.isKill())
9068                           return Sum;
9069                         return Sum + 1;
9070                       });
9071 
9072   // We check to see if CFI Instructions are present, and if they are
9073   // we find the number of CFI Instructions in the candidates.
9074   unsigned CFICount = 0;
9075   MachineBasicBlock::iterator MBBI = RepeatedSequenceLocs[0].front();
9076   for (unsigned Loc = RepeatedSequenceLocs[0].getStartIdx();
9077        Loc < RepeatedSequenceLocs[0].getEndIdx() + 1; Loc++) {
9078     if (MBBI->isCFIInstruction())
9079       CFICount++;
9080     MBBI++;
9081   }
9082 
9083   // We compare the number of found CFI Instructions to  the number of CFI
9084   // instructions in the parent function for each candidate.  We must check this
9085   // since if we outline one of the CFI instructions in a function, we have to
9086   // outline them all for correctness. If we do not, the address offsets will be
9087   // incorrect between the two sections of the program.
9088   for (outliner::Candidate &C : RepeatedSequenceLocs) {
9089     std::vector<MCCFIInstruction> CFIInstructions =
9090         C.getMF()->getFrameInstructions();
9091 
9092     if (CFICount > 0 && CFICount != CFIInstructions.size())
9093       return outliner::OutlinedFunction();
9094   }
9095 
9096   // FIXME: Use real size in bytes for call and ret instructions.
9097   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
9098     for (outliner::Candidate &C : RepeatedSequenceLocs)
9099       C.setCallInfo(MachineOutlinerTailCall, 1);
9100 
9101     return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
9102                                       0, // Number of bytes to emit frame.
9103                                       MachineOutlinerTailCall // Type of frame.
9104     );
9105   }
9106 
9107   if (CFICount > 0)
9108     return outliner::OutlinedFunction();
9109 
9110   for (outliner::Candidate &C : RepeatedSequenceLocs)
9111     C.setCallInfo(MachineOutlinerDefault, 1);
9112 
9113   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
9114                                     MachineOutlinerDefault);
9115 }
9116 
9117 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
9118                                            bool OutlineFromLinkOnceODRs) const {
9119   const Function &F = MF.getFunction();
9120 
9121   // Does the function use a red zone? If it does, then we can't risk messing
9122   // with the stack.
9123   if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
9124     // It could have a red zone. If it does, then we don't want to touch it.
9125     const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
9126     if (!X86FI || X86FI->getUsesRedZone())
9127       return false;
9128   }
9129 
9130   // If we *don't* want to outline from things that could potentially be deduped
9131   // then return false.
9132   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
9133       return false;
9134 
9135   // This function is viable for outlining, so return true.
9136   return true;
9137 }
9138 
9139 outliner::InstrType
9140 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  unsigned Flags) const {
9141   MachineInstr &MI = *MIT;
9142   // Don't allow debug values to impact outlining type.
9143   if (MI.isDebugInstr() || MI.isIndirectDebugValue())
9144     return outliner::InstrType::Invisible;
9145 
9146   // At this point, KILL instructions don't really tell us much so we can go
9147   // ahead and skip over them.
9148   if (MI.isKill())
9149     return outliner::InstrType::Invisible;
9150 
9151   // Is this a tail call? If yes, we can outline as a tail call.
9152   if (isTailCall(MI))
9153     return outliner::InstrType::Legal;
9154 
9155   // Is this the terminator of a basic block?
9156   if (MI.isTerminator() || MI.isReturn()) {
9157 
9158     // Does its parent have any successors in its MachineFunction?
9159     if (MI.getParent()->succ_empty())
9160       return outliner::InstrType::Legal;
9161 
9162     // It does, so we can't tail call it.
9163     return outliner::InstrType::Illegal;
9164   }
9165 
9166   // Don't outline anything that modifies or reads from the stack pointer.
9167   //
9168   // FIXME: There are instructions which are being manually built without
9169   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
9170   // able to remove the extra checks once those are fixed up. For example,
9171   // sometimes we might get something like %rax = POP64r 1. This won't be
9172   // caught by modifiesRegister or readsRegister even though the instruction
9173   // really ought to be formed so that modifiesRegister/readsRegister would
9174   // catch it.
9175   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
9176       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
9177       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
9178     return outliner::InstrType::Illegal;
9179 
9180   // Outlined calls change the instruction pointer, so don't read from it.
9181   if (MI.readsRegister(X86::RIP, &RI) ||
9182       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
9183       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
9184     return outliner::InstrType::Illegal;
9185 
9186   // Positions can't safely be outlined.
9187   if (MI.isPosition())
9188     return outliner::InstrType::Illegal;
9189 
9190   // Make sure none of the operands of this instruction do anything tricky.
9191   for (const MachineOperand &MOP : MI.operands())
9192     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
9193         MOP.isTargetIndex())
9194       return outliner::InstrType::Illegal;
9195 
9196   return outliner::InstrType::Legal;
9197 }
9198 
9199 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
9200                                           MachineFunction &MF,
9201                                           const outliner::OutlinedFunction &OF)
9202                                           const {
9203   // If we're a tail call, we already have a return, so don't do anything.
9204   if (OF.FrameConstructionID == MachineOutlinerTailCall)
9205     return;
9206 
9207   // We're a normal call, so our sequence doesn't have a return instruction.
9208   // Add it in.
9209   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RET64));
9210   MBB.insert(MBB.end(), retq);
9211 }
9212 
9213 MachineBasicBlock::iterator
9214 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
9215                                  MachineBasicBlock::iterator &It,
9216                                  MachineFunction &MF,
9217                                  outliner::Candidate &C) const {
9218   // Is it a tail call?
9219   if (C.CallConstructionID == MachineOutlinerTailCall) {
9220     // Yes, just insert a JMP.
9221     It = MBB.insert(It,
9222                   BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
9223                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9224   } else {
9225     // No, insert a call.
9226     It = MBB.insert(It,
9227                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
9228                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9229   }
9230 
9231   return It;
9232 }
9233 
9234 #define GET_INSTRINFO_HELPERS
9235 #include "X86GenInstrInfo.inc"
9236