1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LiveIntervals.h"
23 #include "llvm/CodeGen/LivePhysRegs.h"
24 #include "llvm/CodeGen/LiveVariables.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineDominators.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineModuleInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/StackMaps.h"
32 #include "llvm/IR/DebugInfoMetadata.h"
33 #include "llvm/IR/DerivedTypes.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/Target/TargetOptions.h"
43 
44 using namespace llvm;
45 
46 #define DEBUG_TYPE "x86-instr-info"
47 
48 #define GET_INSTRINFO_CTOR_DTOR
49 #include "X86GenInstrInfo.inc"
50 
51 static cl::opt<bool>
52     NoFusing("disable-spill-fusing",
53              cl::desc("Disable fusing of spill code into instructions"),
54              cl::Hidden);
55 static cl::opt<bool>
56 PrintFailedFusing("print-failed-fuse-candidates",
57                   cl::desc("Print instructions that the allocator wants to"
58                            " fuse, but the X86 backend currently can't"),
59                   cl::Hidden);
60 static cl::opt<bool>
61 ReMatPICStubLoad("remat-pic-stub-load",
62                  cl::desc("Re-materialize load from stub in PIC mode"),
63                  cl::init(false), cl::Hidden);
64 static cl::opt<unsigned>
65 PartialRegUpdateClearance("partial-reg-update-clearance",
66                           cl::desc("Clearance between two register writes "
67                                    "for inserting XOR to avoid partial "
68                                    "register update"),
69                           cl::init(64), cl::Hidden);
70 static cl::opt<unsigned>
71 UndefRegClearance("undef-reg-clearance",
72                   cl::desc("How many idle instructions we would like before "
73                            "certain undef register reads"),
74                   cl::init(128), cl::Hidden);
75 
76 
77 // Pin the vtable to this file.
78 void X86InstrInfo::anchor() {}
79 
80 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
81     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
82                                                : X86::ADJCALLSTACKDOWN32),
83                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
84                                                : X86::ADJCALLSTACKUP32),
85                       X86::CATCHRET,
86                       (STI.is64Bit() ? X86::RET64 : X86::RET32)),
87       Subtarget(STI), RI(STI.getTargetTriple()) {
88 }
89 
90 bool
91 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
92                                     Register &SrcReg, Register &DstReg,
93                                     unsigned &SubIdx) const {
94   switch (MI.getOpcode()) {
95   default: break;
96   case X86::MOVSX16rr8:
97   case X86::MOVZX16rr8:
98   case X86::MOVSX32rr8:
99   case X86::MOVZX32rr8:
100   case X86::MOVSX64rr8:
101     if (!Subtarget.is64Bit())
102       // It's not always legal to reference the low 8-bit of the larger
103       // register in 32-bit mode.
104       return false;
105     LLVM_FALLTHROUGH;
106   case X86::MOVSX32rr16:
107   case X86::MOVZX32rr16:
108   case X86::MOVSX64rr16:
109   case X86::MOVSX64rr32: {
110     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
111       // Be conservative.
112       return false;
113     SrcReg = MI.getOperand(1).getReg();
114     DstReg = MI.getOperand(0).getReg();
115     switch (MI.getOpcode()) {
116     default: llvm_unreachable("Unreachable!");
117     case X86::MOVSX16rr8:
118     case X86::MOVZX16rr8:
119     case X86::MOVSX32rr8:
120     case X86::MOVZX32rr8:
121     case X86::MOVSX64rr8:
122       SubIdx = X86::sub_8bit;
123       break;
124     case X86::MOVSX32rr16:
125     case X86::MOVZX32rr16:
126     case X86::MOVSX64rr16:
127       SubIdx = X86::sub_16bit;
128       break;
129     case X86::MOVSX64rr32:
130       SubIdx = X86::sub_32bit;
131       break;
132     }
133     return true;
134   }
135   }
136   return false;
137 }
138 
139 bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
140   if (MI.mayLoad() || MI.mayStore())
141     return false;
142 
143   // Some target-independent operations that trivially lower to data-invariant
144   // instructions.
145   if (MI.isCopyLike() || MI.isInsertSubreg())
146     return true;
147 
148   unsigned Opcode = MI.getOpcode();
149   using namespace X86;
150   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
151   // However, they set flags and are perhaps the most surprisingly constant
152   // time operations so we call them out here separately.
153   if (isIMUL(Opcode))
154     return true;
155   // Bit scanning and counting instructions that are somewhat surprisingly
156   // constant time as they scan across bits and do other fairly complex
157   // operations like popcnt, but are believed to be constant time on x86.
158   // However, these set flags.
159   if (isBSF(Opcode) || isBSR(Opcode) || isLZCNT(Opcode) || isPOPCNT(Opcode) ||
160       isTZCNT(Opcode))
161     return true;
162   // Bit manipulation instructions are effectively combinations of basic
163   // arithmetic ops, and should still execute in constant time. These also
164   // set flags.
165   if (isBLCFILL(Opcode) || isBLCI(Opcode) || isBLCIC(Opcode) ||
166       isBLCMSK(Opcode) || isBLCS(Opcode) || isBLSFILL(Opcode) ||
167       isBLSI(Opcode) || isBLSIC(Opcode) || isBLSMSK(Opcode) || isBLSR(Opcode) ||
168       isTZMSK(Opcode))
169     return true;
170   // Bit extracting and clearing instructions should execute in constant time,
171   // and set flags.
172   if (isBEXTR(Opcode) || isBZHI(Opcode))
173     return true;
174   // Shift and rotate.
175   if (isROL(Opcode) || isROR(Opcode) || isSAR(Opcode) || isSHL(Opcode) ||
176       isSHR(Opcode) || isSHLD(Opcode) || isSHRD(Opcode))
177     return true;
178   // Basic arithmetic is constant time on the input but does set flags.
179   if (isADC(Opcode) || isADD(Opcode) || isAND(Opcode) || isOR(Opcode) ||
180       isSBB(Opcode) || isSUB(Opcode) || isXOR(Opcode))
181     return true;
182   // Arithmetic with just 32-bit and 64-bit variants and no immediates.
183   if (isADCX(Opcode) || isADOX(Opcode) || isANDN(Opcode))
184     return true;
185   // Unary arithmetic operations.
186   if (isDEC(Opcode) || isINC(Opcode) || isNEG(Opcode))
187     return true;
188   // Unlike other arithmetic, NOT doesn't set EFLAGS.
189   if (isNOT(Opcode))
190     return true;
191   // Various move instructions used to zero or sign extend things. Note that we
192   // intentionally don't support the _NOREX variants as we can't handle that
193   // register constraint anyways.
194   if (isMOVSX(Opcode) || isMOVZX(Opcode) || isMOVSXD(Opcode) || isMOV(Opcode))
195     return true;
196   // Arithmetic instructions that are both constant time and don't set flags.
197   if (isRORX(Opcode) || isSARX(Opcode) || isSHLX(Opcode) || isSHRX(Opcode))
198     return true;
199   // LEA doesn't actually access memory, and its arithmetic is constant time.
200   if (isLEA(Opcode))
201     return true;
202   // By default, assume that the instruction is not data invariant.
203   return false;
204 }
205 
206 bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
207   switch (MI.getOpcode()) {
208   default:
209     // By default, assume that the load will immediately leak.
210     return false;
211 
212   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
213   // However, they set flags and are perhaps the most surprisingly constant
214   // time operations so we call them out here separately.
215   case X86::IMUL16rm:
216   case X86::IMUL16rmi8:
217   case X86::IMUL16rmi:
218   case X86::IMUL32rm:
219   case X86::IMUL32rmi8:
220   case X86::IMUL32rmi:
221   case X86::IMUL64rm:
222   case X86::IMUL64rmi32:
223   case X86::IMUL64rmi8:
224 
225   // Bit scanning and counting instructions that are somewhat surprisingly
226   // constant time as they scan across bits and do other fairly complex
227   // operations like popcnt, but are believed to be constant time on x86.
228   // However, these set flags.
229   case X86::BSF16rm:
230   case X86::BSF32rm:
231   case X86::BSF64rm:
232   case X86::BSR16rm:
233   case X86::BSR32rm:
234   case X86::BSR64rm:
235   case X86::LZCNT16rm:
236   case X86::LZCNT32rm:
237   case X86::LZCNT64rm:
238   case X86::POPCNT16rm:
239   case X86::POPCNT32rm:
240   case X86::POPCNT64rm:
241   case X86::TZCNT16rm:
242   case X86::TZCNT32rm:
243   case X86::TZCNT64rm:
244 
245   // Bit manipulation instructions are effectively combinations of basic
246   // arithmetic ops, and should still execute in constant time. These also
247   // set flags.
248   case X86::BLCFILL32rm:
249   case X86::BLCFILL64rm:
250   case X86::BLCI32rm:
251   case X86::BLCI64rm:
252   case X86::BLCIC32rm:
253   case X86::BLCIC64rm:
254   case X86::BLCMSK32rm:
255   case X86::BLCMSK64rm:
256   case X86::BLCS32rm:
257   case X86::BLCS64rm:
258   case X86::BLSFILL32rm:
259   case X86::BLSFILL64rm:
260   case X86::BLSI32rm:
261   case X86::BLSI64rm:
262   case X86::BLSIC32rm:
263   case X86::BLSIC64rm:
264   case X86::BLSMSK32rm:
265   case X86::BLSMSK64rm:
266   case X86::BLSR32rm:
267   case X86::BLSR64rm:
268   case X86::TZMSK32rm:
269   case X86::TZMSK64rm:
270 
271   // Bit extracting and clearing instructions should execute in constant time,
272   // and set flags.
273   case X86::BEXTR32rm:
274   case X86::BEXTR64rm:
275   case X86::BEXTRI32mi:
276   case X86::BEXTRI64mi:
277   case X86::BZHI32rm:
278   case X86::BZHI64rm:
279 
280   // Basic arithmetic is constant time on the input but does set flags.
281   case X86::ADC8rm:
282   case X86::ADC16rm:
283   case X86::ADC32rm:
284   case X86::ADC64rm:
285   case X86::ADCX32rm:
286   case X86::ADCX64rm:
287   case X86::ADD8rm:
288   case X86::ADD16rm:
289   case X86::ADD32rm:
290   case X86::ADD64rm:
291   case X86::ADOX32rm:
292   case X86::ADOX64rm:
293   case X86::AND8rm:
294   case X86::AND16rm:
295   case X86::AND32rm:
296   case X86::AND64rm:
297   case X86::ANDN32rm:
298   case X86::ANDN64rm:
299   case X86::OR8rm:
300   case X86::OR16rm:
301   case X86::OR32rm:
302   case X86::OR64rm:
303   case X86::SBB8rm:
304   case X86::SBB16rm:
305   case X86::SBB32rm:
306   case X86::SBB64rm:
307   case X86::SUB8rm:
308   case X86::SUB16rm:
309   case X86::SUB32rm:
310   case X86::SUB64rm:
311   case X86::XOR8rm:
312   case X86::XOR16rm:
313   case X86::XOR32rm:
314   case X86::XOR64rm:
315 
316   // Integer multiply w/o affecting flags is still believed to be constant
317   // time on x86. Called out separately as this is among the most surprising
318   // instructions to exhibit that behavior.
319   case X86::MULX32rm:
320   case X86::MULX64rm:
321 
322   // Arithmetic instructions that are both constant time and don't set flags.
323   case X86::RORX32mi:
324   case X86::RORX64mi:
325   case X86::SARX32rm:
326   case X86::SARX64rm:
327   case X86::SHLX32rm:
328   case X86::SHLX64rm:
329   case X86::SHRX32rm:
330   case X86::SHRX64rm:
331 
332   // Conversions are believed to be constant time and don't set flags.
333   case X86::CVTTSD2SI64rm:
334   case X86::VCVTTSD2SI64rm:
335   case X86::VCVTTSD2SI64Zrm:
336   case X86::CVTTSD2SIrm:
337   case X86::VCVTTSD2SIrm:
338   case X86::VCVTTSD2SIZrm:
339   case X86::CVTTSS2SI64rm:
340   case X86::VCVTTSS2SI64rm:
341   case X86::VCVTTSS2SI64Zrm:
342   case X86::CVTTSS2SIrm:
343   case X86::VCVTTSS2SIrm:
344   case X86::VCVTTSS2SIZrm:
345   case X86::CVTSI2SDrm:
346   case X86::VCVTSI2SDrm:
347   case X86::VCVTSI2SDZrm:
348   case X86::CVTSI2SSrm:
349   case X86::VCVTSI2SSrm:
350   case X86::VCVTSI2SSZrm:
351   case X86::CVTSI642SDrm:
352   case X86::VCVTSI642SDrm:
353   case X86::VCVTSI642SDZrm:
354   case X86::CVTSI642SSrm:
355   case X86::VCVTSI642SSrm:
356   case X86::VCVTSI642SSZrm:
357   case X86::CVTSS2SDrm:
358   case X86::VCVTSS2SDrm:
359   case X86::VCVTSS2SDZrm:
360   case X86::CVTSD2SSrm:
361   case X86::VCVTSD2SSrm:
362   case X86::VCVTSD2SSZrm:
363   // AVX512 added unsigned integer conversions.
364   case X86::VCVTTSD2USI64Zrm:
365   case X86::VCVTTSD2USIZrm:
366   case X86::VCVTTSS2USI64Zrm:
367   case X86::VCVTTSS2USIZrm:
368   case X86::VCVTUSI2SDZrm:
369   case X86::VCVTUSI642SDZrm:
370   case X86::VCVTUSI2SSZrm:
371   case X86::VCVTUSI642SSZrm:
372 
373   // Loads to register don't set flags.
374   case X86::MOV8rm:
375   case X86::MOV8rm_NOREX:
376   case X86::MOV16rm:
377   case X86::MOV32rm:
378   case X86::MOV64rm:
379   case X86::MOVSX16rm8:
380   case X86::MOVSX32rm16:
381   case X86::MOVSX32rm8:
382   case X86::MOVSX32rm8_NOREX:
383   case X86::MOVSX64rm16:
384   case X86::MOVSX64rm32:
385   case X86::MOVSX64rm8:
386   case X86::MOVZX16rm8:
387   case X86::MOVZX32rm16:
388   case X86::MOVZX32rm8:
389   case X86::MOVZX32rm8_NOREX:
390   case X86::MOVZX64rm16:
391   case X86::MOVZX64rm8:
392     return true;
393   }
394 }
395 
396 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
397   const MachineFunction *MF = MI.getParent()->getParent();
398   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
399 
400   if (isFrameInstr(MI)) {
401     int SPAdj = alignTo(getFrameSize(MI), TFI->getStackAlign());
402     SPAdj -= getFrameAdjustment(MI);
403     if (!isFrameSetup(MI))
404       SPAdj = -SPAdj;
405     return SPAdj;
406   }
407 
408   // To know whether a call adjusts the stack, we need information
409   // that is bound to the following ADJCALLSTACKUP pseudo.
410   // Look for the next ADJCALLSTACKUP that follows the call.
411   if (MI.isCall()) {
412     const MachineBasicBlock *MBB = MI.getParent();
413     auto I = ++MachineBasicBlock::const_iterator(MI);
414     for (auto E = MBB->end(); I != E; ++I) {
415       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
416           I->isCall())
417         break;
418     }
419 
420     // If we could not find a frame destroy opcode, then it has already
421     // been simplified, so we don't care.
422     if (I->getOpcode() != getCallFrameDestroyOpcode())
423       return 0;
424 
425     return -(I->getOperand(1).getImm());
426   }
427 
428   // Currently handle only PUSHes we can reasonably expect to see
429   // in call sequences
430   switch (MI.getOpcode()) {
431   default:
432     return 0;
433   case X86::PUSH32i8:
434   case X86::PUSH32r:
435   case X86::PUSH32rmm:
436   case X86::PUSH32rmr:
437   case X86::PUSHi32:
438     return 4;
439   case X86::PUSH64i8:
440   case X86::PUSH64r:
441   case X86::PUSH64rmm:
442   case X86::PUSH64rmr:
443   case X86::PUSH64i32:
444     return 8;
445   }
446 }
447 
448 /// Return true and the FrameIndex if the specified
449 /// operand and follow operands form a reference to the stack frame.
450 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
451                                   int &FrameIndex) const {
452   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
453       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
454       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
455       MI.getOperand(Op + X86::AddrDisp).isImm() &&
456       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
457       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
458       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
459     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
460     return true;
461   }
462   return false;
463 }
464 
465 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
466   switch (Opcode) {
467   default:
468     return false;
469   case X86::MOV8rm:
470   case X86::KMOVBkm:
471     MemBytes = 1;
472     return true;
473   case X86::MOV16rm:
474   case X86::KMOVWkm:
475   case X86::VMOVSHZrm:
476   case X86::VMOVSHZrm_alt:
477     MemBytes = 2;
478     return true;
479   case X86::MOV32rm:
480   case X86::MOVSSrm:
481   case X86::MOVSSrm_alt:
482   case X86::VMOVSSrm:
483   case X86::VMOVSSrm_alt:
484   case X86::VMOVSSZrm:
485   case X86::VMOVSSZrm_alt:
486   case X86::KMOVDkm:
487     MemBytes = 4;
488     return true;
489   case X86::MOV64rm:
490   case X86::LD_Fp64m:
491   case X86::MOVSDrm:
492   case X86::MOVSDrm_alt:
493   case X86::VMOVSDrm:
494   case X86::VMOVSDrm_alt:
495   case X86::VMOVSDZrm:
496   case X86::VMOVSDZrm_alt:
497   case X86::MMX_MOVD64rm:
498   case X86::MMX_MOVQ64rm:
499   case X86::KMOVQkm:
500     MemBytes = 8;
501     return true;
502   case X86::MOVAPSrm:
503   case X86::MOVUPSrm:
504   case X86::MOVAPDrm:
505   case X86::MOVUPDrm:
506   case X86::MOVDQArm:
507   case X86::MOVDQUrm:
508   case X86::VMOVAPSrm:
509   case X86::VMOVUPSrm:
510   case X86::VMOVAPDrm:
511   case X86::VMOVUPDrm:
512   case X86::VMOVDQArm:
513   case X86::VMOVDQUrm:
514   case X86::VMOVAPSZ128rm:
515   case X86::VMOVUPSZ128rm:
516   case X86::VMOVAPSZ128rm_NOVLX:
517   case X86::VMOVUPSZ128rm_NOVLX:
518   case X86::VMOVAPDZ128rm:
519   case X86::VMOVUPDZ128rm:
520   case X86::VMOVDQU8Z128rm:
521   case X86::VMOVDQU16Z128rm:
522   case X86::VMOVDQA32Z128rm:
523   case X86::VMOVDQU32Z128rm:
524   case X86::VMOVDQA64Z128rm:
525   case X86::VMOVDQU64Z128rm:
526     MemBytes = 16;
527     return true;
528   case X86::VMOVAPSYrm:
529   case X86::VMOVUPSYrm:
530   case X86::VMOVAPDYrm:
531   case X86::VMOVUPDYrm:
532   case X86::VMOVDQAYrm:
533   case X86::VMOVDQUYrm:
534   case X86::VMOVAPSZ256rm:
535   case X86::VMOVUPSZ256rm:
536   case X86::VMOVAPSZ256rm_NOVLX:
537   case X86::VMOVUPSZ256rm_NOVLX:
538   case X86::VMOVAPDZ256rm:
539   case X86::VMOVUPDZ256rm:
540   case X86::VMOVDQU8Z256rm:
541   case X86::VMOVDQU16Z256rm:
542   case X86::VMOVDQA32Z256rm:
543   case X86::VMOVDQU32Z256rm:
544   case X86::VMOVDQA64Z256rm:
545   case X86::VMOVDQU64Z256rm:
546     MemBytes = 32;
547     return true;
548   case X86::VMOVAPSZrm:
549   case X86::VMOVUPSZrm:
550   case X86::VMOVAPDZrm:
551   case X86::VMOVUPDZrm:
552   case X86::VMOVDQU8Zrm:
553   case X86::VMOVDQU16Zrm:
554   case X86::VMOVDQA32Zrm:
555   case X86::VMOVDQU32Zrm:
556   case X86::VMOVDQA64Zrm:
557   case X86::VMOVDQU64Zrm:
558     MemBytes = 64;
559     return true;
560   }
561 }
562 
563 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
564   switch (Opcode) {
565   default:
566     return false;
567   case X86::MOV8mr:
568   case X86::KMOVBmk:
569     MemBytes = 1;
570     return true;
571   case X86::MOV16mr:
572   case X86::KMOVWmk:
573   case X86::VMOVSHZmr:
574     MemBytes = 2;
575     return true;
576   case X86::MOV32mr:
577   case X86::MOVSSmr:
578   case X86::VMOVSSmr:
579   case X86::VMOVSSZmr:
580   case X86::KMOVDmk:
581     MemBytes = 4;
582     return true;
583   case X86::MOV64mr:
584   case X86::ST_FpP64m:
585   case X86::MOVSDmr:
586   case X86::VMOVSDmr:
587   case X86::VMOVSDZmr:
588   case X86::MMX_MOVD64mr:
589   case X86::MMX_MOVQ64mr:
590   case X86::MMX_MOVNTQmr:
591   case X86::KMOVQmk:
592     MemBytes = 8;
593     return true;
594   case X86::MOVAPSmr:
595   case X86::MOVUPSmr:
596   case X86::MOVAPDmr:
597   case X86::MOVUPDmr:
598   case X86::MOVDQAmr:
599   case X86::MOVDQUmr:
600   case X86::VMOVAPSmr:
601   case X86::VMOVUPSmr:
602   case X86::VMOVAPDmr:
603   case X86::VMOVUPDmr:
604   case X86::VMOVDQAmr:
605   case X86::VMOVDQUmr:
606   case X86::VMOVUPSZ128mr:
607   case X86::VMOVAPSZ128mr:
608   case X86::VMOVUPSZ128mr_NOVLX:
609   case X86::VMOVAPSZ128mr_NOVLX:
610   case X86::VMOVUPDZ128mr:
611   case X86::VMOVAPDZ128mr:
612   case X86::VMOVDQA32Z128mr:
613   case X86::VMOVDQU32Z128mr:
614   case X86::VMOVDQA64Z128mr:
615   case X86::VMOVDQU64Z128mr:
616   case X86::VMOVDQU8Z128mr:
617   case X86::VMOVDQU16Z128mr:
618     MemBytes = 16;
619     return true;
620   case X86::VMOVUPSYmr:
621   case X86::VMOVAPSYmr:
622   case X86::VMOVUPDYmr:
623   case X86::VMOVAPDYmr:
624   case X86::VMOVDQUYmr:
625   case X86::VMOVDQAYmr:
626   case X86::VMOVUPSZ256mr:
627   case X86::VMOVAPSZ256mr:
628   case X86::VMOVUPSZ256mr_NOVLX:
629   case X86::VMOVAPSZ256mr_NOVLX:
630   case X86::VMOVUPDZ256mr:
631   case X86::VMOVAPDZ256mr:
632   case X86::VMOVDQU8Z256mr:
633   case X86::VMOVDQU16Z256mr:
634   case X86::VMOVDQA32Z256mr:
635   case X86::VMOVDQU32Z256mr:
636   case X86::VMOVDQA64Z256mr:
637   case X86::VMOVDQU64Z256mr:
638     MemBytes = 32;
639     return true;
640   case X86::VMOVUPSZmr:
641   case X86::VMOVAPSZmr:
642   case X86::VMOVUPDZmr:
643   case X86::VMOVAPDZmr:
644   case X86::VMOVDQU8Zmr:
645   case X86::VMOVDQU16Zmr:
646   case X86::VMOVDQA32Zmr:
647   case X86::VMOVDQU32Zmr:
648   case X86::VMOVDQA64Zmr:
649   case X86::VMOVDQU64Zmr:
650     MemBytes = 64;
651     return true;
652   }
653   return false;
654 }
655 
656 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
657                                            int &FrameIndex) const {
658   unsigned Dummy;
659   return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
660 }
661 
662 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
663                                            int &FrameIndex,
664                                            unsigned &MemBytes) const {
665   if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
666     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
667       return MI.getOperand(0).getReg();
668   return 0;
669 }
670 
671 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
672                                                  int &FrameIndex) const {
673   unsigned Dummy;
674   if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
675     unsigned Reg;
676     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
677       return Reg;
678     // Check for post-frame index elimination operations
679     SmallVector<const MachineMemOperand *, 1> Accesses;
680     if (hasLoadFromStackSlot(MI, Accesses)) {
681       FrameIndex =
682           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
683               ->getFrameIndex();
684       return MI.getOperand(0).getReg();
685     }
686   }
687   return 0;
688 }
689 
690 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
691                                           int &FrameIndex) const {
692   unsigned Dummy;
693   return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
694 }
695 
696 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
697                                           int &FrameIndex,
698                                           unsigned &MemBytes) const {
699   if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
700     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
701         isFrameOperand(MI, 0, FrameIndex))
702       return MI.getOperand(X86::AddrNumOperands).getReg();
703   return 0;
704 }
705 
706 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
707                                                 int &FrameIndex) const {
708   unsigned Dummy;
709   if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
710     unsigned Reg;
711     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
712       return Reg;
713     // Check for post-frame index elimination operations
714     SmallVector<const MachineMemOperand *, 1> Accesses;
715     if (hasStoreToStackSlot(MI, Accesses)) {
716       FrameIndex =
717           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
718               ->getFrameIndex();
719       return MI.getOperand(X86::AddrNumOperands).getReg();
720     }
721   }
722   return 0;
723 }
724 
725 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
726 static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI) {
727   // Don't waste compile time scanning use-def chains of physregs.
728   if (!BaseReg.isVirtual())
729     return false;
730   bool isPICBase = false;
731   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
732          E = MRI.def_instr_end(); I != E; ++I) {
733     MachineInstr *DefMI = &*I;
734     if (DefMI->getOpcode() != X86::MOVPC32r)
735       return false;
736     assert(!isPICBase && "More than one PIC base?");
737     isPICBase = true;
738   }
739   return isPICBase;
740 }
741 
742 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
743                                                      AAResults *AA) const {
744   switch (MI.getOpcode()) {
745   default:
746     // This function should only be called for opcodes with the ReMaterializable
747     // flag set.
748     llvm_unreachable("Unknown rematerializable operation!");
749     break;
750 
751   case X86::LOAD_STACK_GUARD:
752   case X86::AVX1_SETALLONES:
753   case X86::AVX2_SETALLONES:
754   case X86::AVX512_128_SET0:
755   case X86::AVX512_256_SET0:
756   case X86::AVX512_512_SET0:
757   case X86::AVX512_512_SETALLONES:
758   case X86::AVX512_FsFLD0SD:
759   case X86::AVX512_FsFLD0SH:
760   case X86::AVX512_FsFLD0SS:
761   case X86::AVX512_FsFLD0F128:
762   case X86::AVX_SET0:
763   case X86::FsFLD0SD:
764   case X86::FsFLD0SS:
765   case X86::FsFLD0F128:
766   case X86::KSET0D:
767   case X86::KSET0Q:
768   case X86::KSET0W:
769   case X86::KSET1D:
770   case X86::KSET1Q:
771   case X86::KSET1W:
772   case X86::MMX_SET0:
773   case X86::MOV32ImmSExti8:
774   case X86::MOV32r0:
775   case X86::MOV32r1:
776   case X86::MOV32r_1:
777   case X86::MOV32ri64:
778   case X86::MOV64ImmSExti8:
779   case X86::V_SET0:
780   case X86::V_SETALLONES:
781   case X86::MOV16ri:
782   case X86::MOV32ri:
783   case X86::MOV64ri:
784   case X86::MOV64ri32:
785   case X86::MOV8ri:
786   case X86::PTILEZEROV:
787     return true;
788 
789   case X86::MOV8rm:
790   case X86::MOV8rm_NOREX:
791   case X86::MOV16rm:
792   case X86::MOV32rm:
793   case X86::MOV64rm:
794   case X86::MOVSSrm:
795   case X86::MOVSSrm_alt:
796   case X86::MOVSDrm:
797   case X86::MOVSDrm_alt:
798   case X86::MOVAPSrm:
799   case X86::MOVUPSrm:
800   case X86::MOVAPDrm:
801   case X86::MOVUPDrm:
802   case X86::MOVDQArm:
803   case X86::MOVDQUrm:
804   case X86::VMOVSSrm:
805   case X86::VMOVSSrm_alt:
806   case X86::VMOVSDrm:
807   case X86::VMOVSDrm_alt:
808   case X86::VMOVAPSrm:
809   case X86::VMOVUPSrm:
810   case X86::VMOVAPDrm:
811   case X86::VMOVUPDrm:
812   case X86::VMOVDQArm:
813   case X86::VMOVDQUrm:
814   case X86::VMOVAPSYrm:
815   case X86::VMOVUPSYrm:
816   case X86::VMOVAPDYrm:
817   case X86::VMOVUPDYrm:
818   case X86::VMOVDQAYrm:
819   case X86::VMOVDQUYrm:
820   case X86::MMX_MOVD64rm:
821   case X86::MMX_MOVQ64rm:
822   // AVX-512
823   case X86::VMOVSSZrm:
824   case X86::VMOVSSZrm_alt:
825   case X86::VMOVSDZrm:
826   case X86::VMOVSDZrm_alt:
827   case X86::VMOVSHZrm:
828   case X86::VMOVSHZrm_alt:
829   case X86::VMOVAPDZ128rm:
830   case X86::VMOVAPDZ256rm:
831   case X86::VMOVAPDZrm:
832   case X86::VMOVAPSZ128rm:
833   case X86::VMOVAPSZ256rm:
834   case X86::VMOVAPSZ128rm_NOVLX:
835   case X86::VMOVAPSZ256rm_NOVLX:
836   case X86::VMOVAPSZrm:
837   case X86::VMOVDQA32Z128rm:
838   case X86::VMOVDQA32Z256rm:
839   case X86::VMOVDQA32Zrm:
840   case X86::VMOVDQA64Z128rm:
841   case X86::VMOVDQA64Z256rm:
842   case X86::VMOVDQA64Zrm:
843   case X86::VMOVDQU16Z128rm:
844   case X86::VMOVDQU16Z256rm:
845   case X86::VMOVDQU16Zrm:
846   case X86::VMOVDQU32Z128rm:
847   case X86::VMOVDQU32Z256rm:
848   case X86::VMOVDQU32Zrm:
849   case X86::VMOVDQU64Z128rm:
850   case X86::VMOVDQU64Z256rm:
851   case X86::VMOVDQU64Zrm:
852   case X86::VMOVDQU8Z128rm:
853   case X86::VMOVDQU8Z256rm:
854   case X86::VMOVDQU8Zrm:
855   case X86::VMOVUPDZ128rm:
856   case X86::VMOVUPDZ256rm:
857   case X86::VMOVUPDZrm:
858   case X86::VMOVUPSZ128rm:
859   case X86::VMOVUPSZ256rm:
860   case X86::VMOVUPSZ128rm_NOVLX:
861   case X86::VMOVUPSZ256rm_NOVLX:
862   case X86::VMOVUPSZrm: {
863     // Loads from constant pools are trivially rematerializable.
864     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
865         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
866         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
867         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
868         MI.isDereferenceableInvariantLoad(AA)) {
869       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
870       if (BaseReg == 0 || BaseReg == X86::RIP)
871         return true;
872       // Allow re-materialization of PIC load.
873       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
874         return false;
875       const MachineFunction &MF = *MI.getParent()->getParent();
876       const MachineRegisterInfo &MRI = MF.getRegInfo();
877       return regIsPICBase(BaseReg, MRI);
878     }
879     return false;
880   }
881 
882   case X86::LEA32r:
883   case X86::LEA64r: {
884     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
885         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
886         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
887         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
888       // lea fi#, lea GV, etc. are all rematerializable.
889       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
890         return true;
891       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
892       if (BaseReg == 0)
893         return true;
894       // Allow re-materialization of lea PICBase + x.
895       const MachineFunction &MF = *MI.getParent()->getParent();
896       const MachineRegisterInfo &MRI = MF.getRegInfo();
897       return regIsPICBase(BaseReg, MRI);
898     }
899     return false;
900   }
901   }
902 }
903 
904 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
905                                  MachineBasicBlock::iterator I,
906                                  Register DestReg, unsigned SubIdx,
907                                  const MachineInstr &Orig,
908                                  const TargetRegisterInfo &TRI) const {
909   bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
910   if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
911                             MachineBasicBlock::LQR_Dead) {
912     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
913     // effects.
914     int Value;
915     switch (Orig.getOpcode()) {
916     case X86::MOV32r0:  Value = 0; break;
917     case X86::MOV32r1:  Value = 1; break;
918     case X86::MOV32r_1: Value = -1; break;
919     default:
920       llvm_unreachable("Unexpected instruction!");
921     }
922 
923     const DebugLoc &DL = Orig.getDebugLoc();
924     BuildMI(MBB, I, DL, get(X86::MOV32ri))
925         .add(Orig.getOperand(0))
926         .addImm(Value);
927   } else {
928     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
929     MBB.insert(I, MI);
930   }
931 
932   MachineInstr &NewMI = *std::prev(I);
933   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
934 }
935 
936 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
937 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
938   for (const MachineOperand &MO : MI.operands()) {
939     if (MO.isReg() && MO.isDef() &&
940         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
941       return true;
942     }
943   }
944   return false;
945 }
946 
947 /// Check whether the shift count for a machine operand is non-zero.
948 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
949                                               unsigned ShiftAmtOperandIdx) {
950   // The shift count is six bits with the REX.W prefix and five bits without.
951   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
952   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
953   return Imm & ShiftCountMask;
954 }
955 
956 /// Check whether the given shift count is appropriate
957 /// can be represented by a LEA instruction.
958 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
959   // Left shift instructions can be transformed into load-effective-address
960   // instructions if we can encode them appropriately.
961   // A LEA instruction utilizes a SIB byte to encode its scale factor.
962   // The SIB.scale field is two bits wide which means that we can encode any
963   // shift amount less than 4.
964   return ShAmt < 4 && ShAmt > 0;
965 }
966 
967 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
968                                   unsigned Opc, bool AllowSP, Register &NewSrc,
969                                   bool &isKill, MachineOperand &ImplicitOp,
970                                   LiveVariables *LV, LiveIntervals *LIS) const {
971   MachineFunction &MF = *MI.getParent()->getParent();
972   const TargetRegisterClass *RC;
973   if (AllowSP) {
974     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
975   } else {
976     RC = Opc != X86::LEA32r ?
977       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
978   }
979   Register SrcReg = Src.getReg();
980   isKill = MI.killsRegister(SrcReg);
981 
982   // For both LEA64 and LEA32 the register already has essentially the right
983   // type (32-bit or 64-bit) we may just need to forbid SP.
984   if (Opc != X86::LEA64_32r) {
985     NewSrc = SrcReg;
986     assert(!Src.isUndef() && "Undef op doesn't need optimization");
987 
988     if (NewSrc.isVirtual() && !MF.getRegInfo().constrainRegClass(NewSrc, RC))
989       return false;
990 
991     return true;
992   }
993 
994   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
995   // another we need to add 64-bit registers to the final MI.
996   if (SrcReg.isPhysical()) {
997     ImplicitOp = Src;
998     ImplicitOp.setImplicit();
999 
1000     NewSrc = getX86SubSuperRegister(SrcReg, 64);
1001     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1002   } else {
1003     // Virtual register of the wrong class, we have to create a temporary 64-bit
1004     // vreg to feed into the LEA.
1005     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1006     MachineInstr *Copy =
1007         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1008             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1009             .addReg(SrcReg, getKillRegState(isKill));
1010 
1011     // Which is obviously going to be dead after we're done with it.
1012     isKill = true;
1013 
1014     if (LV)
1015       LV->replaceKillInstruction(SrcReg, MI, *Copy);
1016 
1017     if (LIS) {
1018       SlotIndex CopyIdx = LIS->InsertMachineInstrInMaps(*Copy);
1019       SlotIndex Idx = LIS->getInstructionIndex(MI);
1020       LiveInterval &LI = LIS->getInterval(SrcReg);
1021       LiveRange::Segment *S = LI.getSegmentContaining(Idx);
1022       if (S->end.getBaseIndex() == Idx)
1023         S->end = CopyIdx.getRegSlot();
1024     }
1025   }
1026 
1027   // We've set all the parameters without issue.
1028   return true;
1029 }
1030 
1031 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1032                                                          MachineInstr &MI,
1033                                                          LiveVariables *LV,
1034                                                          LiveIntervals *LIS,
1035                                                          bool Is8BitOp) const {
1036   // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1037   MachineBasicBlock &MBB = *MI.getParent();
1038   MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
1039   assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1040               *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1041          "Unexpected type for LEA transform");
1042 
1043   // TODO: For a 32-bit target, we need to adjust the LEA variables with
1044   // something like this:
1045   //   Opcode = X86::LEA32r;
1046   //   InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1047   //   OutRegLEA =
1048   //       Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1049   //                : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1050   if (!Subtarget.is64Bit())
1051     return nullptr;
1052 
1053   unsigned Opcode = X86::LEA64_32r;
1054   Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1055   Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1056   Register InRegLEA2;
1057 
1058   // Build and insert into an implicit UNDEF value. This is OK because
1059   // we will be shifting and then extracting the lower 8/16-bits.
1060   // This has the potential to cause partial register stall. e.g.
1061   //   movw    (%rbp,%rcx,2), %dx
1062   //   leal    -65(%rdx), %esi
1063   // But testing has shown this *does* help performance in 64-bit mode (at
1064   // least on modern x86 machines).
1065   MachineBasicBlock::iterator MBBI = MI.getIterator();
1066   Register Dest = MI.getOperand(0).getReg();
1067   Register Src = MI.getOperand(1).getReg();
1068   Register Src2;
1069   bool IsDead = MI.getOperand(0).isDead();
1070   bool IsKill = MI.getOperand(1).isKill();
1071   unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1072   assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
1073   MachineInstr *ImpDef =
1074       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
1075   MachineInstr *InsMI =
1076       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1077           .addReg(InRegLEA, RegState::Define, SubReg)
1078           .addReg(Src, getKillRegState(IsKill));
1079   MachineInstr *ImpDef2 = nullptr;
1080   MachineInstr *InsMI2 = nullptr;
1081 
1082   MachineInstrBuilder MIB =
1083       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
1084   switch (MIOpc) {
1085   default: llvm_unreachable("Unreachable!");
1086   case X86::SHL8ri:
1087   case X86::SHL16ri: {
1088     unsigned ShAmt = MI.getOperand(2).getImm();
1089     MIB.addReg(0).addImm(1ULL << ShAmt)
1090        .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
1091     break;
1092   }
1093   case X86::INC8r:
1094   case X86::INC16r:
1095     addRegOffset(MIB, InRegLEA, true, 1);
1096     break;
1097   case X86::DEC8r:
1098   case X86::DEC16r:
1099     addRegOffset(MIB, InRegLEA, true, -1);
1100     break;
1101   case X86::ADD8ri:
1102   case X86::ADD8ri_DB:
1103   case X86::ADD16ri:
1104   case X86::ADD16ri8:
1105   case X86::ADD16ri_DB:
1106   case X86::ADD16ri8_DB:
1107     addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1108     break;
1109   case X86::ADD8rr:
1110   case X86::ADD8rr_DB:
1111   case X86::ADD16rr:
1112   case X86::ADD16rr_DB: {
1113     Src2 = MI.getOperand(2).getReg();
1114     bool IsKill2 = MI.getOperand(2).isKill();
1115     assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
1116     if (Src == Src2) {
1117       // ADD8rr/ADD16rr killed %reg1028, %reg1028
1118       // just a single insert_subreg.
1119       addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1120     } else {
1121       if (Subtarget.is64Bit())
1122         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1123       else
1124         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1125       // Build and insert into an implicit UNDEF value. This is OK because
1126       // we will be shifting and then extracting the lower 8/16-bits.
1127       ImpDef2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF),
1128                         InRegLEA2);
1129       InsMI2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1130                    .addReg(InRegLEA2, RegState::Define, SubReg)
1131                    .addReg(Src2, getKillRegState(IsKill2));
1132       addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1133     }
1134     if (LV && IsKill2 && InsMI2)
1135       LV->replaceKillInstruction(Src2, MI, *InsMI2);
1136     break;
1137   }
1138   }
1139 
1140   MachineInstr *NewMI = MIB;
1141   MachineInstr *ExtMI =
1142       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1143           .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
1144           .addReg(OutRegLEA, RegState::Kill, SubReg);
1145 
1146   if (LV) {
1147     // Update live variables.
1148     LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1149     LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
1150     if (IsKill)
1151       LV->replaceKillInstruction(Src, MI, *InsMI);
1152     if (IsDead)
1153       LV->replaceKillInstruction(Dest, MI, *ExtMI);
1154   }
1155 
1156   if (LIS) {
1157     LIS->InsertMachineInstrInMaps(*ImpDef);
1158     SlotIndex InsIdx = LIS->InsertMachineInstrInMaps(*InsMI);
1159     if (ImpDef2)
1160       LIS->InsertMachineInstrInMaps(*ImpDef2);
1161     SlotIndex Ins2Idx;
1162     if (InsMI2)
1163       Ins2Idx = LIS->InsertMachineInstrInMaps(*InsMI2);
1164     SlotIndex NewIdx = LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
1165     SlotIndex ExtIdx = LIS->InsertMachineInstrInMaps(*ExtMI);
1166     LIS->getInterval(InRegLEA);
1167     LIS->getInterval(OutRegLEA);
1168     if (InRegLEA2)
1169       LIS->getInterval(InRegLEA2);
1170 
1171     // Move the use of Src up to InsMI.
1172     LiveInterval &SrcLI = LIS->getInterval(Src);
1173     LiveRange::Segment *SrcSeg = SrcLI.getSegmentContaining(NewIdx);
1174     if (SrcSeg->end == NewIdx.getRegSlot())
1175       SrcSeg->end = InsIdx.getRegSlot();
1176 
1177     if (InsMI2) {
1178       // Move the use of Src2 up to InsMI2.
1179       LiveInterval &Src2LI = LIS->getInterval(Src2);
1180       LiveRange::Segment *Src2Seg = Src2LI.getSegmentContaining(NewIdx);
1181       if (Src2Seg->end == NewIdx.getRegSlot())
1182         Src2Seg->end = Ins2Idx.getRegSlot();
1183     }
1184 
1185     // Move the definition of Dest down to ExtMI.
1186     LiveInterval &DestLI = LIS->getInterval(Dest);
1187     LiveRange::Segment *DestSeg =
1188         DestLI.getSegmentContaining(NewIdx.getRegSlot());
1189     assert(DestSeg->start == NewIdx.getRegSlot() &&
1190            DestSeg->valno->def == NewIdx.getRegSlot());
1191     DestSeg->start = ExtIdx.getRegSlot();
1192     DestSeg->valno->def = ExtIdx.getRegSlot();
1193   }
1194 
1195   return ExtMI;
1196 }
1197 
1198 /// This method must be implemented by targets that
1199 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1200 /// may be able to convert a two-address instruction into a true
1201 /// three-address instruction on demand.  This allows the X86 target (for
1202 /// example) to convert ADD and SHL instructions into LEA instructions if they
1203 /// would require register copies due to two-addressness.
1204 ///
1205 /// This method returns a null pointer if the transformation cannot be
1206 /// performed, otherwise it returns the new instruction.
1207 ///
1208 MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
1209                                                   LiveVariables *LV,
1210                                                   LiveIntervals *LIS) const {
1211   // The following opcodes also sets the condition code register(s). Only
1212   // convert them to equivalent lea if the condition code register def's
1213   // are dead!
1214   if (hasLiveCondCodeDef(MI))
1215     return nullptr;
1216 
1217   MachineFunction &MF = *MI.getParent()->getParent();
1218   // All instructions input are two-addr instructions.  Get the known operands.
1219   const MachineOperand &Dest = MI.getOperand(0);
1220   const MachineOperand &Src = MI.getOperand(1);
1221 
1222   // Ideally, operations with undef should be folded before we get here, but we
1223   // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1224   // Without this, we have to forward undef state to new register operands to
1225   // avoid machine verifier errors.
1226   if (Src.isUndef())
1227     return nullptr;
1228   if (MI.getNumOperands() > 2)
1229     if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
1230       return nullptr;
1231 
1232   MachineInstr *NewMI = nullptr;
1233   Register SrcReg, SrcReg2;
1234   bool Is64Bit = Subtarget.is64Bit();
1235 
1236   bool Is8BitOp = false;
1237   unsigned MIOpc = MI.getOpcode();
1238   switch (MIOpc) {
1239   default: llvm_unreachable("Unreachable!");
1240   case X86::SHL64ri: {
1241     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1242     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1243     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1244 
1245     // LEA can't handle RSP.
1246     if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass(
1247                                         Src.getReg(), &X86::GR64_NOSPRegClass))
1248       return nullptr;
1249 
1250     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1251                 .add(Dest)
1252                 .addReg(0)
1253                 .addImm(1ULL << ShAmt)
1254                 .add(Src)
1255                 .addImm(0)
1256                 .addReg(0);
1257     break;
1258   }
1259   case X86::SHL32ri: {
1260     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1261     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1262     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1263 
1264     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1265 
1266     // LEA can't handle ESP.
1267     bool isKill;
1268     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1269     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1270                         ImplicitOp, LV, LIS))
1271       return nullptr;
1272 
1273     MachineInstrBuilder MIB =
1274         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1275             .add(Dest)
1276             .addReg(0)
1277             .addImm(1ULL << ShAmt)
1278             .addReg(SrcReg, getKillRegState(isKill))
1279             .addImm(0)
1280             .addReg(0);
1281     if (ImplicitOp.getReg() != 0)
1282       MIB.add(ImplicitOp);
1283     NewMI = MIB;
1284 
1285     break;
1286   }
1287   case X86::SHL8ri:
1288     Is8BitOp = true;
1289     LLVM_FALLTHROUGH;
1290   case X86::SHL16ri: {
1291     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1292     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1293     if (!isTruncatedShiftCountForLEA(ShAmt))
1294       return nullptr;
1295     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1296   }
1297   case X86::INC64r:
1298   case X86::INC32r: {
1299     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1300     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1301         (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1302     bool isKill;
1303     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1304     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1305                         ImplicitOp, LV, LIS))
1306       return nullptr;
1307 
1308     MachineInstrBuilder MIB =
1309         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1310             .add(Dest)
1311             .addReg(SrcReg, getKillRegState(isKill));
1312     if (ImplicitOp.getReg() != 0)
1313       MIB.add(ImplicitOp);
1314 
1315     NewMI = addOffset(MIB, 1);
1316     break;
1317   }
1318   case X86::DEC64r:
1319   case X86::DEC32r: {
1320     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1321     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1322         : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1323 
1324     bool isKill;
1325     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1326     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill,
1327                         ImplicitOp, LV, LIS))
1328       return nullptr;
1329 
1330     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1331                                   .add(Dest)
1332                                   .addReg(SrcReg, getKillRegState(isKill));
1333     if (ImplicitOp.getReg() != 0)
1334       MIB.add(ImplicitOp);
1335 
1336     NewMI = addOffset(MIB, -1);
1337 
1338     break;
1339   }
1340   case X86::DEC8r:
1341   case X86::INC8r:
1342     Is8BitOp = true;
1343     LLVM_FALLTHROUGH;
1344   case X86::DEC16r:
1345   case X86::INC16r:
1346     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1347   case X86::ADD64rr:
1348   case X86::ADD64rr_DB:
1349   case X86::ADD32rr:
1350   case X86::ADD32rr_DB: {
1351     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1352     unsigned Opc;
1353     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1354       Opc = X86::LEA64r;
1355     else
1356       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1357 
1358     const MachineOperand &Src2 = MI.getOperand(2);
1359     bool isKill2;
1360     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1361     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/false, SrcReg2, isKill2,
1362                         ImplicitOp2, LV, LIS))
1363       return nullptr;
1364 
1365     bool isKill;
1366     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1367     if (Src.getReg() == Src2.getReg()) {
1368       // Don't call classify LEAReg a second time on the same register, in case
1369       // the first call inserted a COPY from Src2 and marked it as killed.
1370       isKill = isKill2;
1371       SrcReg = SrcReg2;
1372     } else {
1373       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1374                           ImplicitOp, LV, LIS))
1375         return nullptr;
1376     }
1377 
1378     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1379     if (ImplicitOp.getReg() != 0)
1380       MIB.add(ImplicitOp);
1381     if (ImplicitOp2.getReg() != 0)
1382       MIB.add(ImplicitOp2);
1383 
1384     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1385     if (LV && Src2.isKill())
1386       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1387     break;
1388   }
1389   case X86::ADD8rr:
1390   case X86::ADD8rr_DB:
1391     Is8BitOp = true;
1392     LLVM_FALLTHROUGH;
1393   case X86::ADD16rr:
1394   case X86::ADD16rr_DB:
1395     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1396   case X86::ADD64ri32:
1397   case X86::ADD64ri8:
1398   case X86::ADD64ri32_DB:
1399   case X86::ADD64ri8_DB:
1400     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1401     NewMI = addOffset(
1402         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1403         MI.getOperand(2));
1404     break;
1405   case X86::ADD32ri:
1406   case X86::ADD32ri8:
1407   case X86::ADD32ri_DB:
1408   case X86::ADD32ri8_DB: {
1409     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1410     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1411 
1412     bool isKill;
1413     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1414     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1415                         ImplicitOp, LV, LIS))
1416       return nullptr;
1417 
1418     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1419                                   .add(Dest)
1420                                   .addReg(SrcReg, getKillRegState(isKill));
1421     if (ImplicitOp.getReg() != 0)
1422       MIB.add(ImplicitOp);
1423 
1424     NewMI = addOffset(MIB, MI.getOperand(2));
1425     break;
1426   }
1427   case X86::ADD8ri:
1428   case X86::ADD8ri_DB:
1429     Is8BitOp = true;
1430     LLVM_FALLTHROUGH;
1431   case X86::ADD16ri:
1432   case X86::ADD16ri8:
1433   case X86::ADD16ri_DB:
1434   case X86::ADD16ri8_DB:
1435     return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1436   case X86::SUB8ri:
1437   case X86::SUB16ri8:
1438   case X86::SUB16ri:
1439     /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1440     return nullptr;
1441   case X86::SUB32ri8:
1442   case X86::SUB32ri: {
1443     if (!MI.getOperand(2).isImm())
1444       return nullptr;
1445     int64_t Imm = MI.getOperand(2).getImm();
1446     if (!isInt<32>(-Imm))
1447       return nullptr;
1448 
1449     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1450     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1451 
1452     bool isKill;
1453     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1454     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill,
1455                         ImplicitOp, LV, LIS))
1456       return nullptr;
1457 
1458     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1459                                   .add(Dest)
1460                                   .addReg(SrcReg, getKillRegState(isKill));
1461     if (ImplicitOp.getReg() != 0)
1462       MIB.add(ImplicitOp);
1463 
1464     NewMI = addOffset(MIB, -Imm);
1465     break;
1466   }
1467 
1468   case X86::SUB64ri8:
1469   case X86::SUB64ri32: {
1470     if (!MI.getOperand(2).isImm())
1471       return nullptr;
1472     int64_t Imm = MI.getOperand(2).getImm();
1473     if (!isInt<32>(-Imm))
1474       return nullptr;
1475 
1476     assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1477 
1478     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1479                                       get(X86::LEA64r)).add(Dest).add(Src);
1480     NewMI = addOffset(MIB, -Imm);
1481     break;
1482   }
1483 
1484   case X86::VMOVDQU8Z128rmk:
1485   case X86::VMOVDQU8Z256rmk:
1486   case X86::VMOVDQU8Zrmk:
1487   case X86::VMOVDQU16Z128rmk:
1488   case X86::VMOVDQU16Z256rmk:
1489   case X86::VMOVDQU16Zrmk:
1490   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1491   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1492   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
1493   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1494   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1495   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
1496   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
1497   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
1498   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
1499   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
1500   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
1501   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk:
1502   case X86::VBROADCASTSDZ256rmk:
1503   case X86::VBROADCASTSDZrmk:
1504   case X86::VBROADCASTSSZ128rmk:
1505   case X86::VBROADCASTSSZ256rmk:
1506   case X86::VBROADCASTSSZrmk:
1507   case X86::VPBROADCASTDZ128rmk:
1508   case X86::VPBROADCASTDZ256rmk:
1509   case X86::VPBROADCASTDZrmk:
1510   case X86::VPBROADCASTQZ128rmk:
1511   case X86::VPBROADCASTQZ256rmk:
1512   case X86::VPBROADCASTQZrmk: {
1513     unsigned Opc;
1514     switch (MIOpc) {
1515     default: llvm_unreachable("Unreachable!");
1516     case X86::VMOVDQU8Z128rmk:     Opc = X86::VPBLENDMBZ128rmk; break;
1517     case X86::VMOVDQU8Z256rmk:     Opc = X86::VPBLENDMBZ256rmk; break;
1518     case X86::VMOVDQU8Zrmk:        Opc = X86::VPBLENDMBZrmk;    break;
1519     case X86::VMOVDQU16Z128rmk:    Opc = X86::VPBLENDMWZ128rmk; break;
1520     case X86::VMOVDQU16Z256rmk:    Opc = X86::VPBLENDMWZ256rmk; break;
1521     case X86::VMOVDQU16Zrmk:       Opc = X86::VPBLENDMWZrmk;    break;
1522     case X86::VMOVDQU32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1523     case X86::VMOVDQU32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1524     case X86::VMOVDQU32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1525     case X86::VMOVDQU64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1526     case X86::VMOVDQU64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1527     case X86::VMOVDQU64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1528     case X86::VMOVUPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1529     case X86::VMOVUPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1530     case X86::VMOVUPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1531     case X86::VMOVUPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1532     case X86::VMOVUPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1533     case X86::VMOVUPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1534     case X86::VMOVDQA32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1535     case X86::VMOVDQA32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1536     case X86::VMOVDQA32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1537     case X86::VMOVDQA64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1538     case X86::VMOVDQA64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1539     case X86::VMOVDQA64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1540     case X86::VMOVAPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1541     case X86::VMOVAPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1542     case X86::VMOVAPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1543     case X86::VMOVAPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1544     case X86::VMOVAPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1545     case X86::VMOVAPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1546     case X86::VBROADCASTSDZ256rmk: Opc = X86::VBLENDMPDZ256rmbk; break;
1547     case X86::VBROADCASTSDZrmk:    Opc = X86::VBLENDMPDZrmbk;    break;
1548     case X86::VBROADCASTSSZ128rmk: Opc = X86::VBLENDMPSZ128rmbk; break;
1549     case X86::VBROADCASTSSZ256rmk: Opc = X86::VBLENDMPSZ256rmbk; break;
1550     case X86::VBROADCASTSSZrmk:    Opc = X86::VBLENDMPSZrmbk;    break;
1551     case X86::VPBROADCASTDZ128rmk: Opc = X86::VPBLENDMDZ128rmbk; break;
1552     case X86::VPBROADCASTDZ256rmk: Opc = X86::VPBLENDMDZ256rmbk; break;
1553     case X86::VPBROADCASTDZrmk:    Opc = X86::VPBLENDMDZrmbk;    break;
1554     case X86::VPBROADCASTQZ128rmk: Opc = X86::VPBLENDMQZ128rmbk; break;
1555     case X86::VPBROADCASTQZ256rmk: Opc = X86::VPBLENDMQZ256rmbk; break;
1556     case X86::VPBROADCASTQZrmk:    Opc = X86::VPBLENDMQZrmbk;    break;
1557     }
1558 
1559     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1560               .add(Dest)
1561               .add(MI.getOperand(2))
1562               .add(Src)
1563               .add(MI.getOperand(3))
1564               .add(MI.getOperand(4))
1565               .add(MI.getOperand(5))
1566               .add(MI.getOperand(6))
1567               .add(MI.getOperand(7));
1568     break;
1569   }
1570 
1571   case X86::VMOVDQU8Z128rrk:
1572   case X86::VMOVDQU8Z256rrk:
1573   case X86::VMOVDQU8Zrrk:
1574   case X86::VMOVDQU16Z128rrk:
1575   case X86::VMOVDQU16Z256rrk:
1576   case X86::VMOVDQU16Zrrk:
1577   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1578   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1579   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
1580   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1581   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1582   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
1583   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
1584   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
1585   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
1586   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
1587   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
1588   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
1589     unsigned Opc;
1590     switch (MIOpc) {
1591     default: llvm_unreachable("Unreachable!");
1592     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
1593     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
1594     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
1595     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1596     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1597     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
1598     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1599     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1600     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1601     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1602     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1603     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1604     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1605     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1606     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1607     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1608     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1609     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1610     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1611     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1612     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1613     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1614     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1615     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1616     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1617     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1618     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1619     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1620     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1621     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1622     }
1623 
1624     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1625               .add(Dest)
1626               .add(MI.getOperand(2))
1627               .add(Src)
1628               .add(MI.getOperand(3));
1629     break;
1630   }
1631   }
1632 
1633   if (!NewMI) return nullptr;
1634 
1635   if (LV) {  // Update live variables
1636     if (Src.isKill())
1637       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1638     if (Dest.isDead())
1639       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1640   }
1641 
1642   MachineBasicBlock &MBB = *MI.getParent();
1643   MBB.insert(MI.getIterator(), NewMI); // Insert the new inst
1644 
1645   if (LIS) {
1646     LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
1647     if (SrcReg)
1648       LIS->getInterval(SrcReg);
1649     if (SrcReg2)
1650       LIS->getInterval(SrcReg2);
1651   }
1652 
1653   return NewMI;
1654 }
1655 
1656 /// This determines which of three possible cases of a three source commute
1657 /// the source indexes correspond to taking into account any mask operands.
1658 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1659 /// possible.
1660 /// Case 0 - Possible to commute the first and second operands.
1661 /// Case 1 - Possible to commute the first and third operands.
1662 /// Case 2 - Possible to commute the second and third operands.
1663 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1664                                        unsigned SrcOpIdx2) {
1665   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1666   if (SrcOpIdx1 > SrcOpIdx2)
1667     std::swap(SrcOpIdx1, SrcOpIdx2);
1668 
1669   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1670   if (X86II::isKMasked(TSFlags)) {
1671     Op2++;
1672     Op3++;
1673   }
1674 
1675   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1676     return 0;
1677   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1678     return 1;
1679   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1680     return 2;
1681   llvm_unreachable("Unknown three src commute case.");
1682 }
1683 
1684 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1685     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1686     const X86InstrFMA3Group &FMA3Group) const {
1687 
1688   unsigned Opc = MI.getOpcode();
1689 
1690   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1691   // analysis. The commute optimization is legal only if all users of FMA*_Int
1692   // use only the lowest element of the FMA*_Int instruction. Such analysis are
1693   // not implemented yet. So, just return 0 in that case.
1694   // When such analysis are available this place will be the right place for
1695   // calling it.
1696   assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1697          "Intrinsic instructions can't commute operand 1");
1698 
1699   // Determine which case this commute is or if it can't be done.
1700   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1701                                          SrcOpIdx2);
1702   assert(Case < 3 && "Unexpected case number!");
1703 
1704   // Define the FMA forms mapping array that helps to map input FMA form
1705   // to output FMA form to preserve the operation semantics after
1706   // commuting the operands.
1707   const unsigned Form132Index = 0;
1708   const unsigned Form213Index = 1;
1709   const unsigned Form231Index = 2;
1710   static const unsigned FormMapping[][3] = {
1711     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1712     // FMA132 A, C, b; ==> FMA231 C, A, b;
1713     // FMA213 B, A, c; ==> FMA213 A, B, c;
1714     // FMA231 C, A, b; ==> FMA132 A, C, b;
1715     { Form231Index, Form213Index, Form132Index },
1716     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1717     // FMA132 A, c, B; ==> FMA132 B, c, A;
1718     // FMA213 B, a, C; ==> FMA231 C, a, B;
1719     // FMA231 C, a, B; ==> FMA213 B, a, C;
1720     { Form132Index, Form231Index, Form213Index },
1721     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1722     // FMA132 a, C, B; ==> FMA213 a, B, C;
1723     // FMA213 b, A, C; ==> FMA132 b, C, A;
1724     // FMA231 c, A, B; ==> FMA231 c, B, A;
1725     { Form213Index, Form132Index, Form231Index }
1726   };
1727 
1728   unsigned FMAForms[3];
1729   FMAForms[0] = FMA3Group.get132Opcode();
1730   FMAForms[1] = FMA3Group.get213Opcode();
1731   FMAForms[2] = FMA3Group.get231Opcode();
1732 
1733   // Everything is ready, just adjust the FMA opcode and return it.
1734   for (unsigned FormIndex = 0; FormIndex < 3; FormIndex++)
1735     if (Opc == FMAForms[FormIndex])
1736       return FMAForms[FormMapping[Case][FormIndex]];
1737 
1738   llvm_unreachable("Illegal FMA3 format");
1739 }
1740 
1741 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1742                              unsigned SrcOpIdx2) {
1743   // Determine which case this commute is or if it can't be done.
1744   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1745                                          SrcOpIdx2);
1746   assert(Case < 3 && "Unexpected case value!");
1747 
1748   // For each case we need to swap two pairs of bits in the final immediate.
1749   static const uint8_t SwapMasks[3][4] = {
1750     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1751     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1752     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1753   };
1754 
1755   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1756   // Clear out the bits we are swapping.
1757   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1758                            SwapMasks[Case][2] | SwapMasks[Case][3]);
1759   // If the immediate had a bit of the pair set, then set the opposite bit.
1760   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1761   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1762   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1763   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1764   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1765 }
1766 
1767 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1768 // commuted.
1769 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1770 #define VPERM_CASES(Suffix) \
1771   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
1772   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
1773   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
1774   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
1775   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
1776   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
1777   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
1778   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
1779   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
1780   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
1781   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
1782   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
1783 
1784 #define VPERM_CASES_BROADCAST(Suffix) \
1785   VPERM_CASES(Suffix) \
1786   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
1787   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
1788   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
1789   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1790   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1791   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
1792 
1793   switch (Opcode) {
1794   default: return false;
1795   VPERM_CASES(B)
1796   VPERM_CASES_BROADCAST(D)
1797   VPERM_CASES_BROADCAST(PD)
1798   VPERM_CASES_BROADCAST(PS)
1799   VPERM_CASES_BROADCAST(Q)
1800   VPERM_CASES(W)
1801     return true;
1802   }
1803 #undef VPERM_CASES_BROADCAST
1804 #undef VPERM_CASES
1805 }
1806 
1807 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1808 // from the I opcode to the T opcode and vice versa.
1809 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1810 #define VPERM_CASES(Orig, New) \
1811   case X86::Orig##128rr:    return X86::New##128rr;   \
1812   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
1813   case X86::Orig##128rm:    return X86::New##128rm;   \
1814   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
1815   case X86::Orig##256rr:    return X86::New##256rr;   \
1816   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
1817   case X86::Orig##256rm:    return X86::New##256rm;   \
1818   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
1819   case X86::Orig##rr:       return X86::New##rr;      \
1820   case X86::Orig##rrkz:     return X86::New##rrkz;    \
1821   case X86::Orig##rm:       return X86::New##rm;      \
1822   case X86::Orig##rmkz:     return X86::New##rmkz;
1823 
1824 #define VPERM_CASES_BROADCAST(Orig, New) \
1825   VPERM_CASES(Orig, New) \
1826   case X86::Orig##128rmb:   return X86::New##128rmb;   \
1827   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1828   case X86::Orig##256rmb:   return X86::New##256rmb;   \
1829   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1830   case X86::Orig##rmb:      return X86::New##rmb;      \
1831   case X86::Orig##rmbkz:    return X86::New##rmbkz;
1832 
1833   switch (Opcode) {
1834   VPERM_CASES(VPERMI2B, VPERMT2B)
1835   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
1836   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1837   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1838   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
1839   VPERM_CASES(VPERMI2W, VPERMT2W)
1840   VPERM_CASES(VPERMT2B, VPERMI2B)
1841   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
1842   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1843   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1844   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
1845   VPERM_CASES(VPERMT2W, VPERMI2W)
1846   }
1847 
1848   llvm_unreachable("Unreachable!");
1849 #undef VPERM_CASES_BROADCAST
1850 #undef VPERM_CASES
1851 }
1852 
1853 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1854                                                    unsigned OpIdx1,
1855                                                    unsigned OpIdx2) const {
1856   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1857     if (NewMI)
1858       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1859     return MI;
1860   };
1861 
1862   switch (MI.getOpcode()) {
1863   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1864   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1865   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1866   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1867   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1868   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1869     unsigned Opc;
1870     unsigned Size;
1871     switch (MI.getOpcode()) {
1872     default: llvm_unreachable("Unreachable!");
1873     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1874     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1875     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1876     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1877     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1878     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1879     }
1880     unsigned Amt = MI.getOperand(3).getImm();
1881     auto &WorkingMI = cloneIfNew(MI);
1882     WorkingMI.setDesc(get(Opc));
1883     WorkingMI.getOperand(3).setImm(Size - Amt);
1884     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1885                                                    OpIdx1, OpIdx2);
1886   }
1887   case X86::PFSUBrr:
1888   case X86::PFSUBRrr: {
1889     // PFSUB  x, y: x = x - y
1890     // PFSUBR x, y: x = y - x
1891     unsigned Opc =
1892         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1893     auto &WorkingMI = cloneIfNew(MI);
1894     WorkingMI.setDesc(get(Opc));
1895     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1896                                                    OpIdx1, OpIdx2);
1897   }
1898   case X86::BLENDPDrri:
1899   case X86::BLENDPSrri:
1900   case X86::VBLENDPDrri:
1901   case X86::VBLENDPSrri:
1902     // If we're optimizing for size, try to use MOVSD/MOVSS.
1903     if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
1904       unsigned Mask, Opc;
1905       switch (MI.getOpcode()) {
1906       default: llvm_unreachable("Unreachable!");
1907       case X86::BLENDPDrri:  Opc = X86::MOVSDrr;  Mask = 0x03; break;
1908       case X86::BLENDPSrri:  Opc = X86::MOVSSrr;  Mask = 0x0F; break;
1909       case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1910       case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1911       }
1912       if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1913         auto &WorkingMI = cloneIfNew(MI);
1914         WorkingMI.setDesc(get(Opc));
1915         WorkingMI.removeOperand(3);
1916         return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1917                                                        /*NewMI=*/false,
1918                                                        OpIdx1, OpIdx2);
1919       }
1920     }
1921     LLVM_FALLTHROUGH;
1922   case X86::PBLENDWrri:
1923   case X86::VBLENDPDYrri:
1924   case X86::VBLENDPSYrri:
1925   case X86::VPBLENDDrri:
1926   case X86::VPBLENDWrri:
1927   case X86::VPBLENDDYrri:
1928   case X86::VPBLENDWYrri:{
1929     int8_t Mask;
1930     switch (MI.getOpcode()) {
1931     default: llvm_unreachable("Unreachable!");
1932     case X86::BLENDPDrri:    Mask = (int8_t)0x03; break;
1933     case X86::BLENDPSrri:    Mask = (int8_t)0x0F; break;
1934     case X86::PBLENDWrri:    Mask = (int8_t)0xFF; break;
1935     case X86::VBLENDPDrri:   Mask = (int8_t)0x03; break;
1936     case X86::VBLENDPSrri:   Mask = (int8_t)0x0F; break;
1937     case X86::VBLENDPDYrri:  Mask = (int8_t)0x0F; break;
1938     case X86::VBLENDPSYrri:  Mask = (int8_t)0xFF; break;
1939     case X86::VPBLENDDrri:   Mask = (int8_t)0x0F; break;
1940     case X86::VPBLENDWrri:   Mask = (int8_t)0xFF; break;
1941     case X86::VPBLENDDYrri:  Mask = (int8_t)0xFF; break;
1942     case X86::VPBLENDWYrri:  Mask = (int8_t)0xFF; break;
1943     }
1944     // Only the least significant bits of Imm are used.
1945     // Using int8_t to ensure it will be sign extended to the int64_t that
1946     // setImm takes in order to match isel behavior.
1947     int8_t Imm = MI.getOperand(3).getImm() & Mask;
1948     auto &WorkingMI = cloneIfNew(MI);
1949     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1950     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1951                                                    OpIdx1, OpIdx2);
1952   }
1953   case X86::INSERTPSrr:
1954   case X86::VINSERTPSrr:
1955   case X86::VINSERTPSZrr: {
1956     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
1957     unsigned ZMask = Imm & 15;
1958     unsigned DstIdx = (Imm >> 4) & 3;
1959     unsigned SrcIdx = (Imm >> 6) & 3;
1960 
1961     // We can commute insertps if we zero 2 of the elements, the insertion is
1962     // "inline" and we don't override the insertion with a zero.
1963     if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
1964         countPopulation(ZMask) == 2) {
1965       unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
1966       assert(AltIdx < 4 && "Illegal insertion index");
1967       unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
1968       auto &WorkingMI = cloneIfNew(MI);
1969       WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
1970       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1971                                                      OpIdx1, OpIdx2);
1972     }
1973     return nullptr;
1974   }
1975   case X86::MOVSDrr:
1976   case X86::MOVSSrr:
1977   case X86::VMOVSDrr:
1978   case X86::VMOVSSrr:{
1979     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1980     if (Subtarget.hasSSE41()) {
1981       unsigned Mask, Opc;
1982       switch (MI.getOpcode()) {
1983       default: llvm_unreachable("Unreachable!");
1984       case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
1985       case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
1986       case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1987       case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1988       }
1989 
1990       auto &WorkingMI = cloneIfNew(MI);
1991       WorkingMI.setDesc(get(Opc));
1992       WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1993       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1994                                                      OpIdx1, OpIdx2);
1995     }
1996 
1997     // Convert to SHUFPD.
1998     assert(MI.getOpcode() == X86::MOVSDrr &&
1999            "Can only commute MOVSDrr without SSE4.1");
2000 
2001     auto &WorkingMI = cloneIfNew(MI);
2002     WorkingMI.setDesc(get(X86::SHUFPDrri));
2003     WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2004     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2005                                                    OpIdx1, OpIdx2);
2006   }
2007   case X86::SHUFPDrri: {
2008     // Commute to MOVSD.
2009     assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
2010     auto &WorkingMI = cloneIfNew(MI);
2011     WorkingMI.setDesc(get(X86::MOVSDrr));
2012     WorkingMI.removeOperand(3);
2013     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2014                                                    OpIdx1, OpIdx2);
2015   }
2016   case X86::PCLMULQDQrr:
2017   case X86::VPCLMULQDQrr:
2018   case X86::VPCLMULQDQYrr:
2019   case X86::VPCLMULQDQZrr:
2020   case X86::VPCLMULQDQZ128rr:
2021   case X86::VPCLMULQDQZ256rr: {
2022     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2023     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2024     unsigned Imm = MI.getOperand(3).getImm();
2025     unsigned Src1Hi = Imm & 0x01;
2026     unsigned Src2Hi = Imm & 0x10;
2027     auto &WorkingMI = cloneIfNew(MI);
2028     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2029     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2030                                                    OpIdx1, OpIdx2);
2031   }
2032   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
2033   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
2034   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
2035   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
2036   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
2037   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
2038   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
2039   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
2040   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
2041   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
2042   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
2043   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
2044   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
2045   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
2046   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
2047   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
2048   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
2049   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
2050   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
2051   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
2052   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
2053   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
2054   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
2055   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
2056     // Flip comparison mode immediate (if necessary).
2057     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
2058     Imm = X86::getSwappedVPCMPImm(Imm);
2059     auto &WorkingMI = cloneIfNew(MI);
2060     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
2061     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2062                                                    OpIdx1, OpIdx2);
2063   }
2064   case X86::VPCOMBri: case X86::VPCOMUBri:
2065   case X86::VPCOMDri: case X86::VPCOMUDri:
2066   case X86::VPCOMQri: case X86::VPCOMUQri:
2067   case X86::VPCOMWri: case X86::VPCOMUWri: {
2068     // Flip comparison mode immediate (if necessary).
2069     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
2070     Imm = X86::getSwappedVPCOMImm(Imm);
2071     auto &WorkingMI = cloneIfNew(MI);
2072     WorkingMI.getOperand(3).setImm(Imm);
2073     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2074                                                    OpIdx1, OpIdx2);
2075   }
2076   case X86::VCMPSDZrr:
2077   case X86::VCMPSSZrr:
2078   case X86::VCMPPDZrri:
2079   case X86::VCMPPSZrri:
2080   case X86::VCMPSHZrr:
2081   case X86::VCMPPHZrri:
2082   case X86::VCMPPHZ128rri:
2083   case X86::VCMPPHZ256rri:
2084   case X86::VCMPPDZ128rri:
2085   case X86::VCMPPSZ128rri:
2086   case X86::VCMPPDZ256rri:
2087   case X86::VCMPPSZ256rri:
2088   case X86::VCMPPDZrrik:
2089   case X86::VCMPPSZrrik:
2090   case X86::VCMPPDZ128rrik:
2091   case X86::VCMPPSZ128rrik:
2092   case X86::VCMPPDZ256rrik:
2093   case X86::VCMPPSZ256rrik: {
2094     unsigned Imm =
2095                 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f;
2096     Imm = X86::getSwappedVCMPImm(Imm);
2097     auto &WorkingMI = cloneIfNew(MI);
2098     WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm);
2099     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2100                                                    OpIdx1, OpIdx2);
2101   }
2102   case X86::VPERM2F128rr:
2103   case X86::VPERM2I128rr: {
2104     // Flip permute source immediate.
2105     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2106     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2107     int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
2108     auto &WorkingMI = cloneIfNew(MI);
2109     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
2110     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2111                                                    OpIdx1, OpIdx2);
2112   }
2113   case X86::MOVHLPSrr:
2114   case X86::UNPCKHPDrr:
2115   case X86::VMOVHLPSrr:
2116   case X86::VUNPCKHPDrr:
2117   case X86::VMOVHLPSZrr:
2118   case X86::VUNPCKHPDZ128rr: {
2119     assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
2120 
2121     unsigned Opc = MI.getOpcode();
2122     switch (Opc) {
2123     default: llvm_unreachable("Unreachable!");
2124     case X86::MOVHLPSrr:       Opc = X86::UNPCKHPDrr;      break;
2125     case X86::UNPCKHPDrr:      Opc = X86::MOVHLPSrr;       break;
2126     case X86::VMOVHLPSrr:      Opc = X86::VUNPCKHPDrr;     break;
2127     case X86::VUNPCKHPDrr:     Opc = X86::VMOVHLPSrr;      break;
2128     case X86::VMOVHLPSZrr:     Opc = X86::VUNPCKHPDZ128rr; break;
2129     case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr;     break;
2130     }
2131     auto &WorkingMI = cloneIfNew(MI);
2132     WorkingMI.setDesc(get(Opc));
2133     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2134                                                    OpIdx1, OpIdx2);
2135   }
2136   case X86::CMOV16rr:  case X86::CMOV32rr:  case X86::CMOV64rr: {
2137     auto &WorkingMI = cloneIfNew(MI);
2138     unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2139     X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
2140     WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2141     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2142                                                    OpIdx1, OpIdx2);
2143   }
2144   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2145   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2146   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2147   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2148   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2149   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2150   case X86::VPTERNLOGDZrrik:
2151   case X86::VPTERNLOGDZ128rrik:
2152   case X86::VPTERNLOGDZ256rrik:
2153   case X86::VPTERNLOGQZrrik:
2154   case X86::VPTERNLOGQZ128rrik:
2155   case X86::VPTERNLOGQZ256rrik:
2156   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2157   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2158   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2159   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2160   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2161   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2162   case X86::VPTERNLOGDZ128rmbi:
2163   case X86::VPTERNLOGDZ256rmbi:
2164   case X86::VPTERNLOGDZrmbi:
2165   case X86::VPTERNLOGQZ128rmbi:
2166   case X86::VPTERNLOGQZ256rmbi:
2167   case X86::VPTERNLOGQZrmbi:
2168   case X86::VPTERNLOGDZ128rmbikz:
2169   case X86::VPTERNLOGDZ256rmbikz:
2170   case X86::VPTERNLOGDZrmbikz:
2171   case X86::VPTERNLOGQZ128rmbikz:
2172   case X86::VPTERNLOGQZ256rmbikz:
2173   case X86::VPTERNLOGQZrmbikz: {
2174     auto &WorkingMI = cloneIfNew(MI);
2175     commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
2176     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2177                                                    OpIdx1, OpIdx2);
2178   }
2179   default: {
2180     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
2181       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
2182       auto &WorkingMI = cloneIfNew(MI);
2183       WorkingMI.setDesc(get(Opc));
2184       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2185                                                      OpIdx1, OpIdx2);
2186     }
2187 
2188     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2189                                                       MI.getDesc().TSFlags);
2190     if (FMA3Group) {
2191       unsigned Opc =
2192         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
2193       auto &WorkingMI = cloneIfNew(MI);
2194       WorkingMI.setDesc(get(Opc));
2195       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2196                                                      OpIdx1, OpIdx2);
2197     }
2198 
2199     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2200   }
2201   }
2202 }
2203 
2204 bool
2205 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2206                                             unsigned &SrcOpIdx1,
2207                                             unsigned &SrcOpIdx2,
2208                                             bool IsIntrinsic) const {
2209   uint64_t TSFlags = MI.getDesc().TSFlags;
2210 
2211   unsigned FirstCommutableVecOp = 1;
2212   unsigned LastCommutableVecOp = 3;
2213   unsigned KMaskOp = -1U;
2214   if (X86II::isKMasked(TSFlags)) {
2215     // For k-zero-masked operations it is Ok to commute the first vector
2216     // operand. Unless this is an intrinsic instruction.
2217     // For regular k-masked operations a conservative choice is done as the
2218     // elements of the first vector operand, for which the corresponding bit
2219     // in the k-mask operand is set to 0, are copied to the result of the
2220     // instruction.
2221     // TODO/FIXME: The commute still may be legal if it is known that the
2222     // k-mask operand is set to either all ones or all zeroes.
2223     // It is also Ok to commute the 1st operand if all users of MI use only
2224     // the elements enabled by the k-mask operand. For example,
2225     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2226     //                                                     : v1[i];
2227     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2228     //                                  // Ok, to commute v1 in FMADD213PSZrk.
2229 
2230     // The k-mask operand has index = 2 for masked and zero-masked operations.
2231     KMaskOp = 2;
2232 
2233     // The operand with index = 1 is used as a source for those elements for
2234     // which the corresponding bit in the k-mask is set to 0.
2235     if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2236       FirstCommutableVecOp = 3;
2237 
2238     LastCommutableVecOp++;
2239   } else if (IsIntrinsic) {
2240     // Commuting the first operand of an intrinsic instruction isn't possible
2241     // unless we can prove that only the lowest element of the result is used.
2242     FirstCommutableVecOp = 2;
2243   }
2244 
2245   if (isMem(MI, LastCommutableVecOp))
2246     LastCommutableVecOp--;
2247 
2248   // Only the first RegOpsNum operands are commutable.
2249   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2250   // that the operand is not specified/fixed.
2251   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2252       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2253        SrcOpIdx1 == KMaskOp))
2254     return false;
2255   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2256       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2257        SrcOpIdx2 == KMaskOp))
2258     return false;
2259 
2260   // Look for two different register operands assumed to be commutable
2261   // regardless of the FMA opcode. The FMA opcode is adjusted later.
2262   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2263       SrcOpIdx2 == CommuteAnyOperandIndex) {
2264     unsigned CommutableOpIdx2 = SrcOpIdx2;
2265 
2266     // At least one of operands to be commuted is not specified and
2267     // this method is free to choose appropriate commutable operands.
2268     if (SrcOpIdx1 == SrcOpIdx2)
2269       // Both of operands are not fixed. By default set one of commutable
2270       // operands to the last register operand of the instruction.
2271       CommutableOpIdx2 = LastCommutableVecOp;
2272     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2273       // Only one of operands is not fixed.
2274       CommutableOpIdx2 = SrcOpIdx1;
2275 
2276     // CommutableOpIdx2 is well defined now. Let's choose another commutable
2277     // operand and assign its index to CommutableOpIdx1.
2278     Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
2279 
2280     unsigned CommutableOpIdx1;
2281     for (CommutableOpIdx1 = LastCommutableVecOp;
2282          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2283       // Just ignore and skip the k-mask operand.
2284       if (CommutableOpIdx1 == KMaskOp)
2285         continue;
2286 
2287       // The commuted operands must have different registers.
2288       // Otherwise, the commute transformation does not change anything and
2289       // is useless then.
2290       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
2291         break;
2292     }
2293 
2294     // No appropriate commutable operands were found.
2295     if (CommutableOpIdx1 < FirstCommutableVecOp)
2296       return false;
2297 
2298     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2299     // to return those values.
2300     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2301                               CommutableOpIdx1, CommutableOpIdx2))
2302       return false;
2303   }
2304 
2305   return true;
2306 }
2307 
2308 bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2309                                          unsigned &SrcOpIdx1,
2310                                          unsigned &SrcOpIdx2) const {
2311   const MCInstrDesc &Desc = MI.getDesc();
2312   if (!Desc.isCommutable())
2313     return false;
2314 
2315   switch (MI.getOpcode()) {
2316   case X86::CMPSDrr:
2317   case X86::CMPSSrr:
2318   case X86::CMPPDrri:
2319   case X86::CMPPSrri:
2320   case X86::VCMPSDrr:
2321   case X86::VCMPSSrr:
2322   case X86::VCMPPDrri:
2323   case X86::VCMPPSrri:
2324   case X86::VCMPPDYrri:
2325   case X86::VCMPPSYrri:
2326   case X86::VCMPSDZrr:
2327   case X86::VCMPSSZrr:
2328   case X86::VCMPPDZrri:
2329   case X86::VCMPPSZrri:
2330   case X86::VCMPSHZrr:
2331   case X86::VCMPPHZrri:
2332   case X86::VCMPPHZ128rri:
2333   case X86::VCMPPHZ256rri:
2334   case X86::VCMPPDZ128rri:
2335   case X86::VCMPPSZ128rri:
2336   case X86::VCMPPDZ256rri:
2337   case X86::VCMPPSZ256rri:
2338   case X86::VCMPPDZrrik:
2339   case X86::VCMPPSZrrik:
2340   case X86::VCMPPDZ128rrik:
2341   case X86::VCMPPSZ128rrik:
2342   case X86::VCMPPDZ256rrik:
2343   case X86::VCMPPSZ256rrik: {
2344     unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2345 
2346     // Float comparison can be safely commuted for
2347     // Ordered/Unordered/Equal/NotEqual tests
2348     unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2349     switch (Imm) {
2350     default:
2351       // EVEX versions can be commuted.
2352       if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2353         break;
2354       return false;
2355     case 0x00: // EQUAL
2356     case 0x03: // UNORDERED
2357     case 0x04: // NOT EQUAL
2358     case 0x07: // ORDERED
2359       break;
2360     }
2361 
2362     // The indices of the commutable operands are 1 and 2 (or 2 and 3
2363     // when masked).
2364     // Assign them to the returned operand indices here.
2365     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2366                                 2 + OpOffset);
2367   }
2368   case X86::MOVSSrr:
2369     // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2370     // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2371     // AVX implies sse4.1.
2372     if (Subtarget.hasSSE41())
2373       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2374     return false;
2375   case X86::SHUFPDrri:
2376     // We can commute this to MOVSD.
2377     if (MI.getOperand(3).getImm() == 0x02)
2378       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2379     return false;
2380   case X86::MOVHLPSrr:
2381   case X86::UNPCKHPDrr:
2382   case X86::VMOVHLPSrr:
2383   case X86::VUNPCKHPDrr:
2384   case X86::VMOVHLPSZrr:
2385   case X86::VUNPCKHPDZ128rr:
2386     if (Subtarget.hasSSE2())
2387       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2388     return false;
2389   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2390   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2391   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2392   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2393   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2394   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2395   case X86::VPTERNLOGDZrrik:
2396   case X86::VPTERNLOGDZ128rrik:
2397   case X86::VPTERNLOGDZ256rrik:
2398   case X86::VPTERNLOGQZrrik:
2399   case X86::VPTERNLOGQZ128rrik:
2400   case X86::VPTERNLOGQZ256rrik:
2401   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2402   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2403   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2404   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2405   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2406   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2407   case X86::VPTERNLOGDZ128rmbi:
2408   case X86::VPTERNLOGDZ256rmbi:
2409   case X86::VPTERNLOGDZrmbi:
2410   case X86::VPTERNLOGQZ128rmbi:
2411   case X86::VPTERNLOGQZ256rmbi:
2412   case X86::VPTERNLOGQZrmbi:
2413   case X86::VPTERNLOGDZ128rmbikz:
2414   case X86::VPTERNLOGDZ256rmbikz:
2415   case X86::VPTERNLOGDZrmbikz:
2416   case X86::VPTERNLOGQZ128rmbikz:
2417   case X86::VPTERNLOGQZ256rmbikz:
2418   case X86::VPTERNLOGQZrmbikz:
2419     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2420   case X86::VPDPWSSDYrr:
2421   case X86::VPDPWSSDrr:
2422   case X86::VPDPWSSDSYrr:
2423   case X86::VPDPWSSDSrr:
2424   case X86::VPDPWSSDZ128r:
2425   case X86::VPDPWSSDZ128rk:
2426   case X86::VPDPWSSDZ128rkz:
2427   case X86::VPDPWSSDZ256r:
2428   case X86::VPDPWSSDZ256rk:
2429   case X86::VPDPWSSDZ256rkz:
2430   case X86::VPDPWSSDZr:
2431   case X86::VPDPWSSDZrk:
2432   case X86::VPDPWSSDZrkz:
2433   case X86::VPDPWSSDSZ128r:
2434   case X86::VPDPWSSDSZ128rk:
2435   case X86::VPDPWSSDSZ128rkz:
2436   case X86::VPDPWSSDSZ256r:
2437   case X86::VPDPWSSDSZ256rk:
2438   case X86::VPDPWSSDSZ256rkz:
2439   case X86::VPDPWSSDSZr:
2440   case X86::VPDPWSSDSZrk:
2441   case X86::VPDPWSSDSZrkz:
2442   case X86::VPMADD52HUQZ128r:
2443   case X86::VPMADD52HUQZ128rk:
2444   case X86::VPMADD52HUQZ128rkz:
2445   case X86::VPMADD52HUQZ256r:
2446   case X86::VPMADD52HUQZ256rk:
2447   case X86::VPMADD52HUQZ256rkz:
2448   case X86::VPMADD52HUQZr:
2449   case X86::VPMADD52HUQZrk:
2450   case X86::VPMADD52HUQZrkz:
2451   case X86::VPMADD52LUQZ128r:
2452   case X86::VPMADD52LUQZ128rk:
2453   case X86::VPMADD52LUQZ128rkz:
2454   case X86::VPMADD52LUQZ256r:
2455   case X86::VPMADD52LUQZ256rk:
2456   case X86::VPMADD52LUQZ256rkz:
2457   case X86::VPMADD52LUQZr:
2458   case X86::VPMADD52LUQZrk:
2459   case X86::VPMADD52LUQZrkz:
2460   case X86::VFMADDCPHZr:
2461   case X86::VFMADDCPHZrk:
2462   case X86::VFMADDCPHZrkz:
2463   case X86::VFMADDCPHZ128r:
2464   case X86::VFMADDCPHZ128rk:
2465   case X86::VFMADDCPHZ128rkz:
2466   case X86::VFMADDCPHZ256r:
2467   case X86::VFMADDCPHZ256rk:
2468   case X86::VFMADDCPHZ256rkz:
2469   case X86::VFMADDCSHZr:
2470   case X86::VFMADDCSHZrk:
2471   case X86::VFMADDCSHZrkz: {
2472     unsigned CommutableOpIdx1 = 2;
2473     unsigned CommutableOpIdx2 = 3;
2474     if (X86II::isKMasked(Desc.TSFlags)) {
2475       // Skip the mask register.
2476       ++CommutableOpIdx1;
2477       ++CommutableOpIdx2;
2478     }
2479     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2480                               CommutableOpIdx1, CommutableOpIdx2))
2481       return false;
2482     if (!MI.getOperand(SrcOpIdx1).isReg() ||
2483         !MI.getOperand(SrcOpIdx2).isReg())
2484       // No idea.
2485       return false;
2486     return true;
2487   }
2488 
2489   default:
2490     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2491                                                       MI.getDesc().TSFlags);
2492     if (FMA3Group)
2493       return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2494                                            FMA3Group->isIntrinsic());
2495 
2496     // Handled masked instructions since we need to skip over the mask input
2497     // and the preserved input.
2498     if (X86II::isKMasked(Desc.TSFlags)) {
2499       // First assume that the first input is the mask operand and skip past it.
2500       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2501       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2502       // Check if the first input is tied. If there isn't one then we only
2503       // need to skip the mask operand which we did above.
2504       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2505                                              MCOI::TIED_TO) != -1)) {
2506         // If this is zero masking instruction with a tied operand, we need to
2507         // move the first index back to the first input since this must
2508         // be a 3 input instruction and we want the first two non-mask inputs.
2509         // Otherwise this is a 2 input instruction with a preserved input and
2510         // mask, so we need to move the indices to skip one more input.
2511         if (X86II::isKMergeMasked(Desc.TSFlags)) {
2512           ++CommutableOpIdx1;
2513           ++CommutableOpIdx2;
2514         } else {
2515           --CommutableOpIdx1;
2516         }
2517       }
2518 
2519       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2520                                 CommutableOpIdx1, CommutableOpIdx2))
2521         return false;
2522 
2523       if (!MI.getOperand(SrcOpIdx1).isReg() ||
2524           !MI.getOperand(SrcOpIdx2).isReg())
2525         // No idea.
2526         return false;
2527       return true;
2528     }
2529 
2530     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2531   }
2532   return false;
2533 }
2534 
2535 static bool isConvertibleLEA(MachineInstr *MI) {
2536   unsigned Opcode = MI->getOpcode();
2537   if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
2538       Opcode != X86::LEA64_32r)
2539     return false;
2540 
2541   const MachineOperand &Scale = MI->getOperand(1 + X86::AddrScaleAmt);
2542   const MachineOperand &Disp = MI->getOperand(1 + X86::AddrDisp);
2543   const MachineOperand &Segment = MI->getOperand(1 + X86::AddrSegmentReg);
2544 
2545   if (Segment.getReg() != 0 || !Disp.isImm() || Disp.getImm() != 0 ||
2546       Scale.getImm() > 1)
2547     return false;
2548 
2549   return true;
2550 }
2551 
2552 bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
2553   // Currently we're interested in following sequence only.
2554   //   r3 = lea r1, r2
2555   //   r5 = add r3, r4
2556   // Both r3 and r4 are killed in add, we hope the add instruction has the
2557   // operand order
2558   //   r5 = add r4, r3
2559   // So later in X86FixupLEAs the lea instruction can be rewritten as add.
2560   unsigned Opcode = MI.getOpcode();
2561   if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
2562     return false;
2563 
2564   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2565   Register Reg1 = MI.getOperand(1).getReg();
2566   Register Reg2 = MI.getOperand(2).getReg();
2567 
2568   // Check if Reg1 comes from LEA in the same MBB.
2569   if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg1)) {
2570     if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2571       Commute = true;
2572       return true;
2573     }
2574   }
2575 
2576   // Check if Reg2 comes from LEA in the same MBB.
2577   if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg2)) {
2578     if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2579       Commute = false;
2580       return true;
2581     }
2582   }
2583 
2584   return false;
2585 }
2586 
2587 int X86::getCondSrcNoFromDesc(const MCInstrDesc &MCID) {
2588   unsigned Opcode = MCID.getOpcode();
2589   if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isCMOVCC(Opcode)))
2590     return -1;
2591   // Assume that condition code is always the last use operand.
2592   unsigned NumUses = MCID.getNumOperands() - MCID.getNumDefs();
2593   return NumUses - 1;
2594 }
2595 
2596 X86::CondCode X86::getCondFromMI(const MachineInstr &MI) {
2597   const MCInstrDesc &MCID = MI.getDesc();
2598   int CondNo = getCondSrcNoFromDesc(MCID);
2599   if (CondNo < 0)
2600     return X86::COND_INVALID;
2601   CondNo += MCID.getNumDefs();
2602   return static_cast<X86::CondCode>(MI.getOperand(CondNo).getImm());
2603 }
2604 
2605 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2606   return X86::isJCC(MI.getOpcode()) ? X86::getCondFromMI(MI)
2607                                     : X86::COND_INVALID;
2608 }
2609 
2610 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2611   return X86::isSETCC(MI.getOpcode()) ? X86::getCondFromMI(MI)
2612                                       : X86::COND_INVALID;
2613 }
2614 
2615 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2616   return X86::isCMOVCC(MI.getOpcode()) ? X86::getCondFromMI(MI)
2617                                        : X86::COND_INVALID;
2618 }
2619 
2620 /// Return the inverse of the specified condition,
2621 /// e.g. turning COND_E to COND_NE.
2622 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2623   switch (CC) {
2624   default: llvm_unreachable("Illegal condition code!");
2625   case X86::COND_E:  return X86::COND_NE;
2626   case X86::COND_NE: return X86::COND_E;
2627   case X86::COND_L:  return X86::COND_GE;
2628   case X86::COND_LE: return X86::COND_G;
2629   case X86::COND_G:  return X86::COND_LE;
2630   case X86::COND_GE: return X86::COND_L;
2631   case X86::COND_B:  return X86::COND_AE;
2632   case X86::COND_BE: return X86::COND_A;
2633   case X86::COND_A:  return X86::COND_BE;
2634   case X86::COND_AE: return X86::COND_B;
2635   case X86::COND_S:  return X86::COND_NS;
2636   case X86::COND_NS: return X86::COND_S;
2637   case X86::COND_P:  return X86::COND_NP;
2638   case X86::COND_NP: return X86::COND_P;
2639   case X86::COND_O:  return X86::COND_NO;
2640   case X86::COND_NO: return X86::COND_O;
2641   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
2642   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2643   }
2644 }
2645 
2646 /// Assuming the flags are set by MI(a,b), return the condition code if we
2647 /// modify the instructions such that flags are set by MI(b,a).
2648 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2649   switch (CC) {
2650   default: return X86::COND_INVALID;
2651   case X86::COND_E:  return X86::COND_E;
2652   case X86::COND_NE: return X86::COND_NE;
2653   case X86::COND_L:  return X86::COND_G;
2654   case X86::COND_LE: return X86::COND_GE;
2655   case X86::COND_G:  return X86::COND_L;
2656   case X86::COND_GE: return X86::COND_LE;
2657   case X86::COND_B:  return X86::COND_A;
2658   case X86::COND_BE: return X86::COND_AE;
2659   case X86::COND_A:  return X86::COND_B;
2660   case X86::COND_AE: return X86::COND_BE;
2661   }
2662 }
2663 
2664 std::pair<X86::CondCode, bool>
2665 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2666   X86::CondCode CC = X86::COND_INVALID;
2667   bool NeedSwap = false;
2668   switch (Predicate) {
2669   default: break;
2670   // Floating-point Predicates
2671   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
2672   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
2673   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
2674   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
2675   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
2676   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
2677   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
2678   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
2679   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
2680   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
2681   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
2682   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
2683   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
2684   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2685 
2686   // Integer Predicates
2687   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
2688   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
2689   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
2690   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
2691   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
2692   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
2693   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
2694   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
2695   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
2696   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
2697   }
2698 
2699   return std::make_pair(CC, NeedSwap);
2700 }
2701 
2702 /// Return a cmov opcode for the given register size in bytes, and operand type.
2703 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2704   switch(RegBytes) {
2705   default: llvm_unreachable("Illegal register size!");
2706   case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2707   case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2708   case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr;
2709   }
2710 }
2711 
2712 /// Get the VPCMP immediate for the given condition.
2713 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2714   switch (CC) {
2715   default: llvm_unreachable("Unexpected SETCC condition");
2716   case ISD::SETNE:  return 4;
2717   case ISD::SETEQ:  return 0;
2718   case ISD::SETULT:
2719   case ISD::SETLT: return 1;
2720   case ISD::SETUGT:
2721   case ISD::SETGT: return 6;
2722   case ISD::SETUGE:
2723   case ISD::SETGE: return 5;
2724   case ISD::SETULE:
2725   case ISD::SETLE: return 2;
2726   }
2727 }
2728 
2729 /// Get the VPCMP immediate if the operands are swapped.
2730 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2731   switch (Imm) {
2732   default: llvm_unreachable("Unreachable!");
2733   case 0x01: Imm = 0x06; break; // LT  -> NLE
2734   case 0x02: Imm = 0x05; break; // LE  -> NLT
2735   case 0x05: Imm = 0x02; break; // NLT -> LE
2736   case 0x06: Imm = 0x01; break; // NLE -> LT
2737   case 0x00: // EQ
2738   case 0x03: // FALSE
2739   case 0x04: // NE
2740   case 0x07: // TRUE
2741     break;
2742   }
2743 
2744   return Imm;
2745 }
2746 
2747 /// Get the VPCOM immediate if the operands are swapped.
2748 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2749   switch (Imm) {
2750   default: llvm_unreachable("Unreachable!");
2751   case 0x00: Imm = 0x02; break; // LT -> GT
2752   case 0x01: Imm = 0x03; break; // LE -> GE
2753   case 0x02: Imm = 0x00; break; // GT -> LT
2754   case 0x03: Imm = 0x01; break; // GE -> LE
2755   case 0x04: // EQ
2756   case 0x05: // NE
2757   case 0x06: // FALSE
2758   case 0x07: // TRUE
2759     break;
2760   }
2761 
2762   return Imm;
2763 }
2764 
2765 /// Get the VCMP immediate if the operands are swapped.
2766 unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2767   // Only need the lower 2 bits to distinquish.
2768   switch (Imm & 0x3) {
2769   default: llvm_unreachable("Unreachable!");
2770   case 0x00: case 0x03:
2771     // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2772     break;
2773   case 0x01: case 0x02:
2774     // Need to toggle bits 3:0. Bit 4 stays the same.
2775     Imm ^= 0xf;
2776     break;
2777   }
2778 
2779   return Imm;
2780 }
2781 
2782 /// Return true if the Reg is X87 register.
2783 static bool isX87Reg(unsigned Reg) {
2784   return (Reg == X86::FPCW || Reg == X86::FPSW ||
2785           (Reg >= X86::ST0 && Reg <= X86::ST7));
2786 }
2787 
2788 /// check if the instruction is X87 instruction
2789 bool X86::isX87Instruction(MachineInstr &MI) {
2790   for (const MachineOperand &MO : MI.operands()) {
2791     if (!MO.isReg())
2792       continue;
2793     if (isX87Reg(MO.getReg()))
2794       return true;
2795   }
2796   return false;
2797 }
2798 
2799 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2800   switch (MI.getOpcode()) {
2801   case X86::TCRETURNdi:
2802   case X86::TCRETURNri:
2803   case X86::TCRETURNmi:
2804   case X86::TCRETURNdi64:
2805   case X86::TCRETURNri64:
2806   case X86::TCRETURNmi64:
2807     return true;
2808   default:
2809     return false;
2810   }
2811 }
2812 
2813 bool X86InstrInfo::canMakeTailCallConditional(
2814     SmallVectorImpl<MachineOperand> &BranchCond,
2815     const MachineInstr &TailCall) const {
2816   if (TailCall.getOpcode() != X86::TCRETURNdi &&
2817       TailCall.getOpcode() != X86::TCRETURNdi64) {
2818     // Only direct calls can be done with a conditional branch.
2819     return false;
2820   }
2821 
2822   const MachineFunction *MF = TailCall.getParent()->getParent();
2823   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2824     // Conditional tail calls confuse the Win64 unwinder.
2825     return false;
2826   }
2827 
2828   assert(BranchCond.size() == 1);
2829   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2830     // Can't make a conditional tail call with this condition.
2831     return false;
2832   }
2833 
2834   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2835   if (X86FI->getTCReturnAddrDelta() != 0 ||
2836       TailCall.getOperand(1).getImm() != 0) {
2837     // A conditional tail call cannot do any stack adjustment.
2838     return false;
2839   }
2840 
2841   return true;
2842 }
2843 
2844 void X86InstrInfo::replaceBranchWithTailCall(
2845     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2846     const MachineInstr &TailCall) const {
2847   assert(canMakeTailCallConditional(BranchCond, TailCall));
2848 
2849   MachineBasicBlock::iterator I = MBB.end();
2850   while (I != MBB.begin()) {
2851     --I;
2852     if (I->isDebugInstr())
2853       continue;
2854     if (!I->isBranch())
2855       assert(0 && "Can't find the branch to replace!");
2856 
2857     X86::CondCode CC = X86::getCondFromBranch(*I);
2858     assert(BranchCond.size() == 1);
2859     if (CC != BranchCond[0].getImm())
2860       continue;
2861 
2862     break;
2863   }
2864 
2865   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2866                                                          : X86::TCRETURNdi64cc;
2867 
2868   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2869   MIB->addOperand(TailCall.getOperand(0)); // Destination.
2870   MIB.addImm(0); // Stack offset (not used).
2871   MIB->addOperand(BranchCond[0]); // Condition.
2872   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2873 
2874   // Add implicit uses and defs of all live regs potentially clobbered by the
2875   // call. This way they still appear live across the call.
2876   LivePhysRegs LiveRegs(getRegisterInfo());
2877   LiveRegs.addLiveOuts(MBB);
2878   SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2879   LiveRegs.stepForward(*MIB, Clobbers);
2880   for (const auto &C : Clobbers) {
2881     MIB.addReg(C.first, RegState::Implicit);
2882     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2883   }
2884 
2885   I->eraseFromParent();
2886 }
2887 
2888 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2889 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2890 // fallthrough MBB cannot be identified.
2891 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2892                                             MachineBasicBlock *TBB) {
2893   // Look for non-EHPad successors other than TBB. If we find exactly one, it
2894   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2895   // and fallthrough MBB. If we find more than one, we cannot identify the
2896   // fallthrough MBB and should return nullptr.
2897   MachineBasicBlock *FallthroughBB = nullptr;
2898   for (MachineBasicBlock *Succ : MBB->successors()) {
2899     if (Succ->isEHPad() || (Succ == TBB && FallthroughBB))
2900       continue;
2901     // Return a nullptr if we found more than one fallthrough successor.
2902     if (FallthroughBB && FallthroughBB != TBB)
2903       return nullptr;
2904     FallthroughBB = Succ;
2905   }
2906   return FallthroughBB;
2907 }
2908 
2909 bool X86InstrInfo::AnalyzeBranchImpl(
2910     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2911     SmallVectorImpl<MachineOperand> &Cond,
2912     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2913 
2914   // Start from the bottom of the block and work up, examining the
2915   // terminator instructions.
2916   MachineBasicBlock::iterator I = MBB.end();
2917   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2918   while (I != MBB.begin()) {
2919     --I;
2920     if (I->isDebugInstr())
2921       continue;
2922 
2923     // Working from the bottom, when we see a non-terminator instruction, we're
2924     // done.
2925     if (!isUnpredicatedTerminator(*I))
2926       break;
2927 
2928     // A terminator that isn't a branch can't easily be handled by this
2929     // analysis.
2930     if (!I->isBranch())
2931       return true;
2932 
2933     // Handle unconditional branches.
2934     if (I->getOpcode() == X86::JMP_1) {
2935       UnCondBrIter = I;
2936 
2937       if (!AllowModify) {
2938         TBB = I->getOperand(0).getMBB();
2939         continue;
2940       }
2941 
2942       // If the block has any instructions after a JMP, delete them.
2943       while (std::next(I) != MBB.end())
2944         std::next(I)->eraseFromParent();
2945 
2946       Cond.clear();
2947       FBB = nullptr;
2948 
2949       // Delete the JMP if it's equivalent to a fall-through.
2950       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2951         TBB = nullptr;
2952         I->eraseFromParent();
2953         I = MBB.end();
2954         UnCondBrIter = MBB.end();
2955         continue;
2956       }
2957 
2958       // TBB is used to indicate the unconditional destination.
2959       TBB = I->getOperand(0).getMBB();
2960       continue;
2961     }
2962 
2963     // Handle conditional branches.
2964     X86::CondCode BranchCode = X86::getCondFromBranch(*I);
2965     if (BranchCode == X86::COND_INVALID)
2966       return true;  // Can't handle indirect branch.
2967 
2968     // In practice we should never have an undef eflags operand, if we do
2969     // abort here as we are not prepared to preserve the flag.
2970     if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
2971       return true;
2972 
2973     // Working from the bottom, handle the first conditional branch.
2974     if (Cond.empty()) {
2975       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2976       if (AllowModify && UnCondBrIter != MBB.end() &&
2977           MBB.isLayoutSuccessor(TargetBB)) {
2978         // If we can modify the code and it ends in something like:
2979         //
2980         //     jCC L1
2981         //     jmp L2
2982         //   L1:
2983         //     ...
2984         //   L2:
2985         //
2986         // Then we can change this to:
2987         //
2988         //     jnCC L2
2989         //   L1:
2990         //     ...
2991         //   L2:
2992         //
2993         // Which is a bit more efficient.
2994         // We conditionally jump to the fall-through block.
2995         BranchCode = GetOppositeBranchCondition(BranchCode);
2996         MachineBasicBlock::iterator OldInst = I;
2997 
2998         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
2999           .addMBB(UnCondBrIter->getOperand(0).getMBB())
3000           .addImm(BranchCode);
3001         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3002           .addMBB(TargetBB);
3003 
3004         OldInst->eraseFromParent();
3005         UnCondBrIter->eraseFromParent();
3006 
3007         // Restart the analysis.
3008         UnCondBrIter = MBB.end();
3009         I = MBB.end();
3010         continue;
3011       }
3012 
3013       FBB = TBB;
3014       TBB = I->getOperand(0).getMBB();
3015       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3016       CondBranches.push_back(&*I);
3017       continue;
3018     }
3019 
3020     // Handle subsequent conditional branches. Only handle the case where all
3021     // conditional branches branch to the same destination and their condition
3022     // opcodes fit one of the special multi-branch idioms.
3023     assert(Cond.size() == 1);
3024     assert(TBB);
3025 
3026     // If the conditions are the same, we can leave them alone.
3027     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3028     auto NewTBB = I->getOperand(0).getMBB();
3029     if (OldBranchCode == BranchCode && TBB == NewTBB)
3030       continue;
3031 
3032     // If they differ, see if they fit one of the known patterns. Theoretically,
3033     // we could handle more patterns here, but we shouldn't expect to see them
3034     // if instruction selection has done a reasonable job.
3035     if (TBB == NewTBB &&
3036                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3037                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3038       BranchCode = X86::COND_NE_OR_P;
3039     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3040                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3041       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
3042         return true;
3043 
3044       // X86::COND_E_AND_NP usually has two different branch destinations.
3045       //
3046       // JP B1
3047       // JE B2
3048       // JMP B1
3049       // B1:
3050       // B2:
3051       //
3052       // Here this condition branches to B2 only if NP && E. It has another
3053       // equivalent form:
3054       //
3055       // JNE B1
3056       // JNP B2
3057       // JMP B1
3058       // B1:
3059       // B2:
3060       //
3061       // Similarly it branches to B2 only if E && NP. That is why this condition
3062       // is named with COND_E_AND_NP.
3063       BranchCode = X86::COND_E_AND_NP;
3064     } else
3065       return true;
3066 
3067     // Update the MachineOperand.
3068     Cond[0].setImm(BranchCode);
3069     CondBranches.push_back(&*I);
3070   }
3071 
3072   return false;
3073 }
3074 
3075 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3076                                  MachineBasicBlock *&TBB,
3077                                  MachineBasicBlock *&FBB,
3078                                  SmallVectorImpl<MachineOperand> &Cond,
3079                                  bool AllowModify) const {
3080   SmallVector<MachineInstr *, 4> CondBranches;
3081   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3082 }
3083 
3084 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
3085                                           MachineBranchPredicate &MBP,
3086                                           bool AllowModify) const {
3087   using namespace std::placeholders;
3088 
3089   SmallVector<MachineOperand, 4> Cond;
3090   SmallVector<MachineInstr *, 4> CondBranches;
3091   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3092                         AllowModify))
3093     return true;
3094 
3095   if (Cond.size() != 1)
3096     return true;
3097 
3098   assert(MBP.TrueDest && "expected!");
3099 
3100   if (!MBP.FalseDest)
3101     MBP.FalseDest = MBB.getNextNode();
3102 
3103   const TargetRegisterInfo *TRI = &getRegisterInfo();
3104 
3105   MachineInstr *ConditionDef = nullptr;
3106   bool SingleUseCondition = true;
3107 
3108   for (MachineInstr &MI : llvm::drop_begin(llvm::reverse(MBB))) {
3109     if (MI.modifiesRegister(X86::EFLAGS, TRI)) {
3110       ConditionDef = &MI;
3111       break;
3112     }
3113 
3114     if (MI.readsRegister(X86::EFLAGS, TRI))
3115       SingleUseCondition = false;
3116   }
3117 
3118   if (!ConditionDef)
3119     return true;
3120 
3121   if (SingleUseCondition) {
3122     for (auto *Succ : MBB.successors())
3123       if (Succ->isLiveIn(X86::EFLAGS))
3124         SingleUseCondition = false;
3125   }
3126 
3127   MBP.ConditionDef = ConditionDef;
3128   MBP.SingleUseCondition = SingleUseCondition;
3129 
3130   // Currently we only recognize the simple pattern:
3131   //
3132   //   test %reg, %reg
3133   //   je %label
3134   //
3135   const unsigned TestOpcode =
3136       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3137 
3138   if (ConditionDef->getOpcode() == TestOpcode &&
3139       ConditionDef->getNumOperands() == 3 &&
3140       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3141       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3142     MBP.LHS = ConditionDef->getOperand(0);
3143     MBP.RHS = MachineOperand::CreateImm(0);
3144     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3145                         ? MachineBranchPredicate::PRED_NE
3146                         : MachineBranchPredicate::PRED_EQ;
3147     return false;
3148   }
3149 
3150   return true;
3151 }
3152 
3153 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
3154                                     int *BytesRemoved) const {
3155   assert(!BytesRemoved && "code size not handled");
3156 
3157   MachineBasicBlock::iterator I = MBB.end();
3158   unsigned Count = 0;
3159 
3160   while (I != MBB.begin()) {
3161     --I;
3162     if (I->isDebugInstr())
3163       continue;
3164     if (I->getOpcode() != X86::JMP_1 &&
3165         X86::getCondFromBranch(*I) == X86::COND_INVALID)
3166       break;
3167     // Remove the branch.
3168     I->eraseFromParent();
3169     I = MBB.end();
3170     ++Count;
3171   }
3172 
3173   return Count;
3174 }
3175 
3176 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
3177                                     MachineBasicBlock *TBB,
3178                                     MachineBasicBlock *FBB,
3179                                     ArrayRef<MachineOperand> Cond,
3180                                     const DebugLoc &DL,
3181                                     int *BytesAdded) const {
3182   // Shouldn't be a fall through.
3183   assert(TBB && "insertBranch must not be told to insert a fallthrough");
3184   assert((Cond.size() == 1 || Cond.size() == 0) &&
3185          "X86 branch conditions have one component!");
3186   assert(!BytesAdded && "code size not handled");
3187 
3188   if (Cond.empty()) {
3189     // Unconditional branch?
3190     assert(!FBB && "Unconditional branch with multiple successors!");
3191     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3192     return 1;
3193   }
3194 
3195   // If FBB is null, it is implied to be a fall-through block.
3196   bool FallThru = FBB == nullptr;
3197 
3198   // Conditional branch.
3199   unsigned Count = 0;
3200   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3201   switch (CC) {
3202   case X86::COND_NE_OR_P:
3203     // Synthesize NE_OR_P with two branches.
3204     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
3205     ++Count;
3206     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
3207     ++Count;
3208     break;
3209   case X86::COND_E_AND_NP:
3210     // Use the next block of MBB as FBB if it is null.
3211     if (FBB == nullptr) {
3212       FBB = getFallThroughMBB(&MBB, TBB);
3213       assert(FBB && "MBB cannot be the last block in function when the false "
3214                     "body is a fall-through.");
3215     }
3216     // Synthesize COND_E_AND_NP with two branches.
3217     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
3218     ++Count;
3219     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
3220     ++Count;
3221     break;
3222   default: {
3223     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
3224     ++Count;
3225   }
3226   }
3227   if (!FallThru) {
3228     // Two-way Conditional branch. Insert the second branch.
3229     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3230     ++Count;
3231   }
3232   return Count;
3233 }
3234 
3235 bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
3236                                    ArrayRef<MachineOperand> Cond,
3237                                    Register DstReg, Register TrueReg,
3238                                    Register FalseReg, int &CondCycles,
3239                                    int &TrueCycles, int &FalseCycles) const {
3240   // Not all subtargets have cmov instructions.
3241   if (!Subtarget.canUseCMOV())
3242     return false;
3243   if (Cond.size() != 1)
3244     return false;
3245   // We cannot do the composite conditions, at least not in SSA form.
3246   if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
3247     return false;
3248 
3249   // Check register classes.
3250   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3251   const TargetRegisterClass *RC =
3252     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3253   if (!RC)
3254     return false;
3255 
3256   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3257   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3258       X86::GR32RegClass.hasSubClassEq(RC) ||
3259       X86::GR64RegClass.hasSubClassEq(RC)) {
3260     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3261     // Bridge. Probably Ivy Bridge as well.
3262     CondCycles = 2;
3263     TrueCycles = 2;
3264     FalseCycles = 2;
3265     return true;
3266   }
3267 
3268   // Can't do vectors.
3269   return false;
3270 }
3271 
3272 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3273                                 MachineBasicBlock::iterator I,
3274                                 const DebugLoc &DL, Register DstReg,
3275                                 ArrayRef<MachineOperand> Cond, Register TrueReg,
3276                                 Register FalseReg) const {
3277   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3278   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3279   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
3280   assert(Cond.size() == 1 && "Invalid Cond array");
3281   unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
3282                                     false /*HasMemoryOperand*/);
3283   BuildMI(MBB, I, DL, get(Opc), DstReg)
3284       .addReg(FalseReg)
3285       .addReg(TrueReg)
3286       .addImm(Cond[0].getImm());
3287 }
3288 
3289 /// Test if the given register is a physical h register.
3290 static bool isHReg(unsigned Reg) {
3291   return X86::GR8_ABCD_HRegClass.contains(Reg);
3292 }
3293 
3294 // Try and copy between VR128/VR64 and GR64 registers.
3295 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3296                                         const X86Subtarget &Subtarget) {
3297   bool HasAVX = Subtarget.hasAVX();
3298   bool HasAVX512 = Subtarget.hasAVX512();
3299 
3300   // SrcReg(MaskReg) -> DestReg(GR64)
3301   // SrcReg(MaskReg) -> DestReg(GR32)
3302 
3303   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3304   if (X86::VK16RegClass.contains(SrcReg)) {
3305     if (X86::GR64RegClass.contains(DestReg)) {
3306       assert(Subtarget.hasBWI());
3307       return X86::KMOVQrk;
3308     }
3309     if (X86::GR32RegClass.contains(DestReg))
3310       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
3311   }
3312 
3313   // SrcReg(GR64) -> DestReg(MaskReg)
3314   // SrcReg(GR32) -> DestReg(MaskReg)
3315 
3316   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3317   if (X86::VK16RegClass.contains(DestReg)) {
3318     if (X86::GR64RegClass.contains(SrcReg)) {
3319       assert(Subtarget.hasBWI());
3320       return X86::KMOVQkr;
3321     }
3322     if (X86::GR32RegClass.contains(SrcReg))
3323       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
3324   }
3325 
3326 
3327   // SrcReg(VR128) -> DestReg(GR64)
3328   // SrcReg(VR64)  -> DestReg(GR64)
3329   // SrcReg(GR64)  -> DestReg(VR128)
3330   // SrcReg(GR64)  -> DestReg(VR64)
3331 
3332   if (X86::GR64RegClass.contains(DestReg)) {
3333     if (X86::VR128XRegClass.contains(SrcReg))
3334       // Copy from a VR128 register to a GR64 register.
3335       return HasAVX512 ? X86::VMOVPQIto64Zrr :
3336              HasAVX    ? X86::VMOVPQIto64rr  :
3337                          X86::MOVPQIto64rr;
3338     if (X86::VR64RegClass.contains(SrcReg))
3339       // Copy from a VR64 register to a GR64 register.
3340       return X86::MMX_MOVD64from64rr;
3341   } else if (X86::GR64RegClass.contains(SrcReg)) {
3342     // Copy from a GR64 register to a VR128 register.
3343     if (X86::VR128XRegClass.contains(DestReg))
3344       return HasAVX512 ? X86::VMOV64toPQIZrr :
3345              HasAVX    ? X86::VMOV64toPQIrr  :
3346                          X86::MOV64toPQIrr;
3347     // Copy from a GR64 register to a VR64 register.
3348     if (X86::VR64RegClass.contains(DestReg))
3349       return X86::MMX_MOVD64to64rr;
3350   }
3351 
3352   // SrcReg(VR128) -> DestReg(GR32)
3353   // SrcReg(GR32)  -> DestReg(VR128)
3354 
3355   if (X86::GR32RegClass.contains(DestReg) &&
3356       X86::VR128XRegClass.contains(SrcReg))
3357     // Copy from a VR128 register to a GR32 register.
3358     return HasAVX512 ? X86::VMOVPDI2DIZrr :
3359            HasAVX    ? X86::VMOVPDI2DIrr  :
3360                        X86::MOVPDI2DIrr;
3361 
3362   if (X86::VR128XRegClass.contains(DestReg) &&
3363       X86::GR32RegClass.contains(SrcReg))
3364     // Copy from a VR128 register to a VR128 register.
3365     return HasAVX512 ? X86::VMOVDI2PDIZrr :
3366            HasAVX    ? X86::VMOVDI2PDIrr  :
3367                        X86::MOVDI2PDIrr;
3368   return 0;
3369 }
3370 
3371 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3372                                MachineBasicBlock::iterator MI,
3373                                const DebugLoc &DL, MCRegister DestReg,
3374                                MCRegister SrcReg, bool KillSrc) const {
3375   // First deal with the normal symmetric copies.
3376   bool HasAVX = Subtarget.hasAVX();
3377   bool HasVLX = Subtarget.hasVLX();
3378   unsigned Opc = 0;
3379   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3380     Opc = X86::MOV64rr;
3381   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3382     Opc = X86::MOV32rr;
3383   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3384     Opc = X86::MOV16rr;
3385   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3386     // Copying to or from a physical H register on x86-64 requires a NOREX
3387     // move.  Otherwise use a normal move.
3388     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3389         Subtarget.is64Bit()) {
3390       Opc = X86::MOV8rr_NOREX;
3391       // Both operands must be encodable without an REX prefix.
3392       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3393              "8-bit H register can not be copied outside GR8_NOREX");
3394     } else
3395       Opc = X86::MOV8rr;
3396   }
3397   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3398     Opc = X86::MMX_MOVQ64rr;
3399   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3400     if (HasVLX)
3401       Opc = X86::VMOVAPSZ128rr;
3402     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3403       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3404     else {
3405       // If this an extended register and we don't have VLX we need to use a
3406       // 512-bit move.
3407       Opc = X86::VMOVAPSZrr;
3408       const TargetRegisterInfo *TRI = &getRegisterInfo();
3409       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3410                                          &X86::VR512RegClass);
3411       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3412                                         &X86::VR512RegClass);
3413     }
3414   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3415     if (HasVLX)
3416       Opc = X86::VMOVAPSZ256rr;
3417     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3418       Opc = X86::VMOVAPSYrr;
3419     else {
3420       // If this an extended register and we don't have VLX we need to use a
3421       // 512-bit move.
3422       Opc = X86::VMOVAPSZrr;
3423       const TargetRegisterInfo *TRI = &getRegisterInfo();
3424       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3425                                          &X86::VR512RegClass);
3426       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3427                                         &X86::VR512RegClass);
3428     }
3429   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3430     Opc = X86::VMOVAPSZrr;
3431   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3432   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3433     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3434   if (!Opc)
3435     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3436 
3437   if (Opc) {
3438     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3439       .addReg(SrcReg, getKillRegState(KillSrc));
3440     return;
3441   }
3442 
3443   if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3444     // FIXME: We use a fatal error here because historically LLVM has tried
3445     // lower some of these physreg copies and we want to ensure we get
3446     // reasonable bug reports if someone encounters a case no other testing
3447     // found. This path should be removed after the LLVM 7 release.
3448     report_fatal_error("Unable to copy EFLAGS physical register!");
3449   }
3450 
3451   LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3452                     << RI.getName(DestReg) << '\n');
3453   report_fatal_error("Cannot emit physreg copy instruction");
3454 }
3455 
3456 Optional<DestSourcePair>
3457 X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
3458   if (MI.isMoveReg())
3459     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
3460   return None;
3461 }
3462 
3463 static unsigned getLoadStoreRegOpcode(Register Reg,
3464                                       const TargetRegisterClass *RC,
3465                                       bool IsStackAligned,
3466                                       const X86Subtarget &STI, bool load) {
3467   bool HasAVX = STI.hasAVX();
3468   bool HasAVX512 = STI.hasAVX512();
3469   bool HasVLX = STI.hasVLX();
3470 
3471   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3472   default:
3473     llvm_unreachable("Unknown spill size");
3474   case 1:
3475     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3476     if (STI.is64Bit())
3477       // Copying to or from a physical H register on x86-64 requires a NOREX
3478       // move.  Otherwise use a normal move.
3479       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3480         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3481     return load ? X86::MOV8rm : X86::MOV8mr;
3482   case 2:
3483     if (X86::VK16RegClass.hasSubClassEq(RC))
3484       return load ? X86::KMOVWkm : X86::KMOVWmk;
3485     if (X86::FR16XRegClass.hasSubClassEq(RC)) {
3486       assert(STI.hasFP16());
3487       return load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
3488     }
3489     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3490     return load ? X86::MOV16rm : X86::MOV16mr;
3491   case 4:
3492     if (X86::GR32RegClass.hasSubClassEq(RC))
3493       return load ? X86::MOV32rm : X86::MOV32mr;
3494     if (X86::FR32XRegClass.hasSubClassEq(RC))
3495       return load ?
3496         (HasAVX512 ? X86::VMOVSSZrm_alt :
3497          HasAVX    ? X86::VMOVSSrm_alt :
3498                      X86::MOVSSrm_alt) :
3499         (HasAVX512 ? X86::VMOVSSZmr :
3500          HasAVX    ? X86::VMOVSSmr :
3501                      X86::MOVSSmr);
3502     if (X86::RFP32RegClass.hasSubClassEq(RC))
3503       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3504     if (X86::VK32RegClass.hasSubClassEq(RC)) {
3505       assert(STI.hasBWI() && "KMOVD requires BWI");
3506       return load ? X86::KMOVDkm : X86::KMOVDmk;
3507     }
3508     // All of these mask pair classes have the same spill size, the same kind
3509     // of kmov instructions can be used with all of them.
3510     if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3511         X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3512         X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3513         X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3514         X86::VK16PAIRRegClass.hasSubClassEq(RC))
3515       return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3516     llvm_unreachable("Unknown 4-byte regclass");
3517   case 8:
3518     if (X86::GR64RegClass.hasSubClassEq(RC))
3519       return load ? X86::MOV64rm : X86::MOV64mr;
3520     if (X86::FR64XRegClass.hasSubClassEq(RC))
3521       return load ?
3522         (HasAVX512 ? X86::VMOVSDZrm_alt :
3523          HasAVX    ? X86::VMOVSDrm_alt :
3524                      X86::MOVSDrm_alt) :
3525         (HasAVX512 ? X86::VMOVSDZmr :
3526          HasAVX    ? X86::VMOVSDmr :
3527                      X86::MOVSDmr);
3528     if (X86::VR64RegClass.hasSubClassEq(RC))
3529       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3530     if (X86::RFP64RegClass.hasSubClassEq(RC))
3531       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3532     if (X86::VK64RegClass.hasSubClassEq(RC)) {
3533       assert(STI.hasBWI() && "KMOVQ requires BWI");
3534       return load ? X86::KMOVQkm : X86::KMOVQmk;
3535     }
3536     llvm_unreachable("Unknown 8-byte regclass");
3537   case 10:
3538     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3539     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3540   case 16: {
3541     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3542       // If stack is realigned we can use aligned stores.
3543       if (IsStackAligned)
3544         return load ?
3545           (HasVLX    ? X86::VMOVAPSZ128rm :
3546            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3547            HasAVX    ? X86::VMOVAPSrm :
3548                        X86::MOVAPSrm):
3549           (HasVLX    ? X86::VMOVAPSZ128mr :
3550            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3551            HasAVX    ? X86::VMOVAPSmr :
3552                        X86::MOVAPSmr);
3553       else
3554         return load ?
3555           (HasVLX    ? X86::VMOVUPSZ128rm :
3556            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3557            HasAVX    ? X86::VMOVUPSrm :
3558                        X86::MOVUPSrm):
3559           (HasVLX    ? X86::VMOVUPSZ128mr :
3560            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3561            HasAVX    ? X86::VMOVUPSmr :
3562                        X86::MOVUPSmr);
3563     }
3564     llvm_unreachable("Unknown 16-byte regclass");
3565   }
3566   case 32:
3567     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3568     // If stack is realigned we can use aligned stores.
3569     if (IsStackAligned)
3570       return load ?
3571         (HasVLX    ? X86::VMOVAPSZ256rm :
3572          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3573                      X86::VMOVAPSYrm) :
3574         (HasVLX    ? X86::VMOVAPSZ256mr :
3575          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3576                      X86::VMOVAPSYmr);
3577     else
3578       return load ?
3579         (HasVLX    ? X86::VMOVUPSZ256rm :
3580          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3581                      X86::VMOVUPSYrm) :
3582         (HasVLX    ? X86::VMOVUPSZ256mr :
3583          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3584                      X86::VMOVUPSYmr);
3585   case 64:
3586     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3587     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3588     if (IsStackAligned)
3589       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3590     else
3591       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3592   }
3593 }
3594 
3595 Optional<ExtAddrMode>
3596 X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
3597                                       const TargetRegisterInfo *TRI) const {
3598   const MCInstrDesc &Desc = MemI.getDesc();
3599   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3600   if (MemRefBegin < 0)
3601     return None;
3602 
3603   MemRefBegin += X86II::getOperandBias(Desc);
3604 
3605   auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg);
3606   if (!BaseOp.isReg()) // Can be an MO_FrameIndex
3607     return None;
3608 
3609   const MachineOperand &DispMO = MemI.getOperand(MemRefBegin + X86::AddrDisp);
3610   // Displacement can be symbolic
3611   if (!DispMO.isImm())
3612     return None;
3613 
3614   ExtAddrMode AM;
3615   AM.BaseReg = BaseOp.getReg();
3616   AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg();
3617   AM.Scale = MemI.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm();
3618   AM.Displacement = DispMO.getImm();
3619   return AM;
3620 }
3621 
3622 bool X86InstrInfo::verifyInstruction(const MachineInstr &MI,
3623                                      StringRef &ErrInfo) const {
3624   Optional<ExtAddrMode> AMOrNone = getAddrModeFromMemoryOp(MI, nullptr);
3625   if (!AMOrNone)
3626     return true;
3627 
3628   ExtAddrMode AM = *AMOrNone;
3629 
3630   if (AM.ScaledReg != X86::NoRegister) {
3631     switch (AM.Scale) {
3632     case 1:
3633     case 2:
3634     case 4:
3635     case 8:
3636       break;
3637     default:
3638       ErrInfo = "Scale factor in address must be 1, 2, 4 or 8";
3639       return false;
3640     }
3641   }
3642   if (!isInt<32>(AM.Displacement)) {
3643     ErrInfo = "Displacement in address must fit into 32-bit signed "
3644               "integer";
3645     return false;
3646   }
3647 
3648   return true;
3649 }
3650 
3651 bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
3652                                            const Register Reg,
3653                                            int64_t &ImmVal) const {
3654   if (MI.getOpcode() != X86::MOV32ri && MI.getOpcode() != X86::MOV64ri)
3655     return false;
3656   // Mov Src can be a global address.
3657   if (!MI.getOperand(1).isImm() || MI.getOperand(0).getReg() != Reg)
3658     return false;
3659   ImmVal = MI.getOperand(1).getImm();
3660   return true;
3661 }
3662 
3663 bool X86InstrInfo::preservesZeroValueInReg(
3664     const MachineInstr *MI, const Register NullValueReg,
3665     const TargetRegisterInfo *TRI) const {
3666   if (!MI->modifiesRegister(NullValueReg, TRI))
3667     return true;
3668   switch (MI->getOpcode()) {
3669   // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
3670   // X.
3671   case X86::SHR64ri:
3672   case X86::SHR32ri:
3673   case X86::SHL64ri:
3674   case X86::SHL32ri:
3675     assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&
3676            "expected for shift opcode!");
3677     return MI->getOperand(0).getReg() == NullValueReg &&
3678            MI->getOperand(1).getReg() == NullValueReg;
3679   // Zero extend of a sub-reg of NullValueReg into itself does not change the
3680   // null value.
3681   case X86::MOV32rr:
3682     return llvm::all_of(MI->operands(), [&](const MachineOperand &MO) {
3683       return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
3684     });
3685   default:
3686     return false;
3687   }
3688   llvm_unreachable("Should be handled above!");
3689 }
3690 
3691 bool X86InstrInfo::getMemOperandsWithOffsetWidth(
3692     const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
3693     int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3694     const TargetRegisterInfo *TRI) const {
3695   const MCInstrDesc &Desc = MemOp.getDesc();
3696   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3697   if (MemRefBegin < 0)
3698     return false;
3699 
3700   MemRefBegin += X86II::getOperandBias(Desc);
3701 
3702   const MachineOperand *BaseOp =
3703       &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3704   if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3705     return false;
3706 
3707   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3708     return false;
3709 
3710   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3711       X86::NoRegister)
3712     return false;
3713 
3714   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3715 
3716   // Displacement can be symbolic
3717   if (!DispMO.isImm())
3718     return false;
3719 
3720   Offset = DispMO.getImm();
3721 
3722   if (!BaseOp->isReg())
3723     return false;
3724 
3725   OffsetIsScalable = false;
3726   // FIXME: Relying on memoperands() may not be right thing to do here. Check
3727   // with X86 maintainers, and fix it accordingly. For now, it is ok, since
3728   // there is no use of `Width` for X86 back-end at the moment.
3729   Width =
3730       !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0;
3731   BaseOps.push_back(BaseOp);
3732   return true;
3733 }
3734 
3735 static unsigned getStoreRegOpcode(Register SrcReg,
3736                                   const TargetRegisterClass *RC,
3737                                   bool IsStackAligned,
3738                                   const X86Subtarget &STI) {
3739   return getLoadStoreRegOpcode(SrcReg, RC, IsStackAligned, STI, false);
3740 }
3741 
3742 static unsigned getLoadRegOpcode(Register DestReg,
3743                                  const TargetRegisterClass *RC,
3744                                  bool IsStackAligned, const X86Subtarget &STI) {
3745   return getLoadStoreRegOpcode(DestReg, RC, IsStackAligned, STI, true);
3746 }
3747 
3748 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3749                                        MachineBasicBlock::iterator MI,
3750                                        Register SrcReg, bool isKill, int FrameIdx,
3751                                        const TargetRegisterClass *RC,
3752                                        const TargetRegisterInfo *TRI) const {
3753   const MachineFunction &MF = *MBB.getParent();
3754   const MachineFrameInfo &MFI = MF.getFrameInfo();
3755   assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3756          "Stack slot too small for store");
3757   if (RC->getID() == X86::TILERegClassID) {
3758     unsigned Opc = X86::TILESTORED;
3759     // tilestored %tmm, (%sp, %idx)
3760     MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3761     Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3762     BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3763     MachineInstr *NewMI =
3764         addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3765             .addReg(SrcReg, getKillRegState(isKill));
3766     MachineOperand &MO = NewMI->getOperand(2);
3767     MO.setReg(VirtReg);
3768     MO.setIsKill(true);
3769   } else {
3770     unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3771     bool isAligned =
3772         (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3773         (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3774     unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3775     addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3776         .addReg(SrcReg, getKillRegState(isKill));
3777   }
3778 }
3779 
3780 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3781                                         MachineBasicBlock::iterator MI,
3782                                         Register DestReg, int FrameIdx,
3783                                         const TargetRegisterClass *RC,
3784                                         const TargetRegisterInfo *TRI) const {
3785   if (RC->getID() == X86::TILERegClassID) {
3786     unsigned Opc = X86::TILELOADD;
3787     // tileloadd (%sp, %idx), %tmm
3788     MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3789     Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3790     MachineInstr *NewMI =
3791         BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3792     NewMI = addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3793                               FrameIdx);
3794     MachineOperand &MO = NewMI->getOperand(3);
3795     MO.setReg(VirtReg);
3796     MO.setIsKill(true);
3797   } else {
3798     const MachineFunction &MF = *MBB.getParent();
3799     const MachineFrameInfo &MFI = MF.getFrameInfo();
3800     unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3801     bool isAligned =
3802         (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3803         (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3804     unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3805     addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3806                       FrameIdx);
3807   }
3808 }
3809 
3810 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
3811                                   Register &SrcReg2, int64_t &CmpMask,
3812                                   int64_t &CmpValue) const {
3813   switch (MI.getOpcode()) {
3814   default: break;
3815   case X86::CMP64ri32:
3816   case X86::CMP64ri8:
3817   case X86::CMP32ri:
3818   case X86::CMP32ri8:
3819   case X86::CMP16ri:
3820   case X86::CMP16ri8:
3821   case X86::CMP8ri:
3822     SrcReg = MI.getOperand(0).getReg();
3823     SrcReg2 = 0;
3824     if (MI.getOperand(1).isImm()) {
3825       CmpMask = ~0;
3826       CmpValue = MI.getOperand(1).getImm();
3827     } else {
3828       CmpMask = CmpValue = 0;
3829     }
3830     return true;
3831   // A SUB can be used to perform comparison.
3832   case X86::SUB64rm:
3833   case X86::SUB32rm:
3834   case X86::SUB16rm:
3835   case X86::SUB8rm:
3836     SrcReg = MI.getOperand(1).getReg();
3837     SrcReg2 = 0;
3838     CmpMask = 0;
3839     CmpValue = 0;
3840     return true;
3841   case X86::SUB64rr:
3842   case X86::SUB32rr:
3843   case X86::SUB16rr:
3844   case X86::SUB8rr:
3845     SrcReg = MI.getOperand(1).getReg();
3846     SrcReg2 = MI.getOperand(2).getReg();
3847     CmpMask = 0;
3848     CmpValue = 0;
3849     return true;
3850   case X86::SUB64ri32:
3851   case X86::SUB64ri8:
3852   case X86::SUB32ri:
3853   case X86::SUB32ri8:
3854   case X86::SUB16ri:
3855   case X86::SUB16ri8:
3856   case X86::SUB8ri:
3857     SrcReg = MI.getOperand(1).getReg();
3858     SrcReg2 = 0;
3859     if (MI.getOperand(2).isImm()) {
3860       CmpMask = ~0;
3861       CmpValue = MI.getOperand(2).getImm();
3862     } else {
3863       CmpMask = CmpValue = 0;
3864     }
3865     return true;
3866   case X86::CMP64rr:
3867   case X86::CMP32rr:
3868   case X86::CMP16rr:
3869   case X86::CMP8rr:
3870     SrcReg = MI.getOperand(0).getReg();
3871     SrcReg2 = MI.getOperand(1).getReg();
3872     CmpMask = 0;
3873     CmpValue = 0;
3874     return true;
3875   case X86::TEST8rr:
3876   case X86::TEST16rr:
3877   case X86::TEST32rr:
3878   case X86::TEST64rr:
3879     SrcReg = MI.getOperand(0).getReg();
3880     if (MI.getOperand(1).getReg() != SrcReg)
3881       return false;
3882     // Compare against zero.
3883     SrcReg2 = 0;
3884     CmpMask = ~0;
3885     CmpValue = 0;
3886     return true;
3887   }
3888   return false;
3889 }
3890 
3891 bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
3892                                         Register SrcReg, Register SrcReg2,
3893                                         int64_t ImmMask, int64_t ImmValue,
3894                                         const MachineInstr &OI, bool *IsSwapped,
3895                                         int64_t *ImmDelta) const {
3896   switch (OI.getOpcode()) {
3897   case X86::CMP64rr:
3898   case X86::CMP32rr:
3899   case X86::CMP16rr:
3900   case X86::CMP8rr:
3901   case X86::SUB64rr:
3902   case X86::SUB32rr:
3903   case X86::SUB16rr:
3904   case X86::SUB8rr: {
3905     Register OISrcReg;
3906     Register OISrcReg2;
3907     int64_t OIMask;
3908     int64_t OIValue;
3909     if (!analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) ||
3910         OIMask != ImmMask || OIValue != ImmValue)
3911       return false;
3912     if (SrcReg == OISrcReg && SrcReg2 == OISrcReg2) {
3913       *IsSwapped = false;
3914       return true;
3915     }
3916     if (SrcReg == OISrcReg2 && SrcReg2 == OISrcReg) {
3917       *IsSwapped = true;
3918       return true;
3919     }
3920     return false;
3921   }
3922   case X86::CMP64ri32:
3923   case X86::CMP64ri8:
3924   case X86::CMP32ri:
3925   case X86::CMP32ri8:
3926   case X86::CMP16ri:
3927   case X86::CMP16ri8:
3928   case X86::CMP8ri:
3929   case X86::SUB64ri32:
3930   case X86::SUB64ri8:
3931   case X86::SUB32ri:
3932   case X86::SUB32ri8:
3933   case X86::SUB16ri:
3934   case X86::SUB16ri8:
3935   case X86::SUB8ri:
3936   case X86::TEST64rr:
3937   case X86::TEST32rr:
3938   case X86::TEST16rr:
3939   case X86::TEST8rr: {
3940     if (ImmMask != 0) {
3941       Register OISrcReg;
3942       Register OISrcReg2;
3943       int64_t OIMask;
3944       int64_t OIValue;
3945       if (analyzeCompare(OI, OISrcReg, OISrcReg2, OIMask, OIValue) &&
3946           SrcReg == OISrcReg && ImmMask == OIMask) {
3947         if (OIValue == ImmValue) {
3948           *ImmDelta = 0;
3949           return true;
3950         } else if (static_cast<uint64_t>(ImmValue) ==
3951                    static_cast<uint64_t>(OIValue) - 1) {
3952           *ImmDelta = -1;
3953           return true;
3954         } else if (static_cast<uint64_t>(ImmValue) ==
3955                    static_cast<uint64_t>(OIValue) + 1) {
3956           *ImmDelta = 1;
3957           return true;
3958         } else {
3959           return false;
3960         }
3961       }
3962     }
3963     return FlagI.isIdenticalTo(OI);
3964   }
3965   default:
3966     return false;
3967   }
3968 }
3969 
3970 /// Check whether the definition can be converted
3971 /// to remove a comparison against zero.
3972 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
3973                                     bool &ClearsOverflowFlag) {
3974   NoSignFlag = false;
3975   ClearsOverflowFlag = false;
3976 
3977   switch (MI.getOpcode()) {
3978   default: return false;
3979 
3980   // The shift instructions only modify ZF if their shift count is non-zero.
3981   // N.B.: The processor truncates the shift count depending on the encoding.
3982   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3983   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3984      return getTruncatedShiftCount(MI, 2) != 0;
3985 
3986   // Some left shift instructions can be turned into LEA instructions but only
3987   // if their flags aren't used. Avoid transforming such instructions.
3988   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3989     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3990     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3991     return ShAmt != 0;
3992   }
3993 
3994   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3995   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3996      return getTruncatedShiftCount(MI, 3) != 0;
3997 
3998   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3999   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
4000   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
4001   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
4002   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
4003   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
4004   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4005   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
4006   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
4007   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
4008   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
4009   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
4010   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
4011   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
4012   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
4013   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
4014   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
4015   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
4016   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
4017   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
4018   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
4019   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
4020   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4021   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
4022   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
4023   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
4024   case X86::LZCNT16rr: case X86::LZCNT16rm:
4025   case X86::LZCNT32rr: case X86::LZCNT32rm:
4026   case X86::LZCNT64rr: case X86::LZCNT64rm:
4027   case X86::POPCNT16rr:case X86::POPCNT16rm:
4028   case X86::POPCNT32rr:case X86::POPCNT32rm:
4029   case X86::POPCNT64rr:case X86::POPCNT64rm:
4030   case X86::TZCNT16rr: case X86::TZCNT16rm:
4031   case X86::TZCNT32rr: case X86::TZCNT32rm:
4032   case X86::TZCNT64rr: case X86::TZCNT64rm:
4033     return true;
4034   case X86::AND64ri32:   case X86::AND64ri8:  case X86::AND32ri:
4035   case X86::AND32ri8:    case X86::AND16ri:   case X86::AND16ri8:
4036   case X86::AND8ri:      case X86::AND64rr:   case X86::AND32rr:
4037   case X86::AND16rr:     case X86::AND8rr:    case X86::AND64rm:
4038   case X86::AND32rm:     case X86::AND16rm:   case X86::AND8rm:
4039   case X86::XOR64ri32:   case X86::XOR64ri8:  case X86::XOR32ri:
4040   case X86::XOR32ri8:    case X86::XOR16ri:   case X86::XOR16ri8:
4041   case X86::XOR8ri:      case X86::XOR64rr:   case X86::XOR32rr:
4042   case X86::XOR16rr:     case X86::XOR8rr:    case X86::XOR64rm:
4043   case X86::XOR32rm:     case X86::XOR16rm:   case X86::XOR8rm:
4044   case X86::OR64ri32:    case X86::OR64ri8:   case X86::OR32ri:
4045   case X86::OR32ri8:     case X86::OR16ri:    case X86::OR16ri8:
4046   case X86::OR8ri:       case X86::OR64rr:    case X86::OR32rr:
4047   case X86::OR16rr:      case X86::OR8rr:     case X86::OR64rm:
4048   case X86::OR32rm:      case X86::OR16rm:    case X86::OR8rm:
4049   case X86::ANDN32rr:    case X86::ANDN32rm:
4050   case X86::ANDN64rr:    case X86::ANDN64rm:
4051   case X86::BLSI32rr:    case X86::BLSI32rm:
4052   case X86::BLSI64rr:    case X86::BLSI64rm:
4053   case X86::BLSMSK32rr:  case X86::BLSMSK32rm:
4054   case X86::BLSMSK64rr:  case X86::BLSMSK64rm:
4055   case X86::BLSR32rr:    case X86::BLSR32rm:
4056   case X86::BLSR64rr:    case X86::BLSR64rm:
4057   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
4058   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
4059   case X86::BLCI32rr:    case X86::BLCI32rm:
4060   case X86::BLCI64rr:    case X86::BLCI64rm:
4061   case X86::BLCIC32rr:   case X86::BLCIC32rm:
4062   case X86::BLCIC64rr:   case X86::BLCIC64rm:
4063   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
4064   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
4065   case X86::BLCS32rr:    case X86::BLCS32rm:
4066   case X86::BLCS64rr:    case X86::BLCS64rm:
4067   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
4068   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
4069   case X86::BLSIC32rr:   case X86::BLSIC32rm:
4070   case X86::BLSIC64rr:   case X86::BLSIC64rm:
4071   case X86::BZHI32rr:    case X86::BZHI32rm:
4072   case X86::BZHI64rr:    case X86::BZHI64rm:
4073   case X86::T1MSKC32rr:  case X86::T1MSKC32rm:
4074   case X86::T1MSKC64rr:  case X86::T1MSKC64rm:
4075   case X86::TZMSK32rr:   case X86::TZMSK32rm:
4076   case X86::TZMSK64rr:   case X86::TZMSK64rm:
4077     // These instructions clear the overflow flag just like TEST.
4078     // FIXME: These are not the only instructions in this switch that clear the
4079     // overflow flag.
4080     ClearsOverflowFlag = true;
4081     return true;
4082   case X86::BEXTR32rr:   case X86::BEXTR64rr:
4083   case X86::BEXTR32rm:   case X86::BEXTR64rm:
4084   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
4085   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
4086     // BEXTR doesn't update the sign flag so we can't use it. It does clear
4087     // the overflow flag, but that's not useful without the sign flag.
4088     NoSignFlag = true;
4089     return true;
4090   }
4091 }
4092 
4093 /// Check whether the use can be converted to remove a comparison against zero.
4094 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
4095   switch (MI.getOpcode()) {
4096   default: return X86::COND_INVALID;
4097   case X86::NEG8r:
4098   case X86::NEG16r:
4099   case X86::NEG32r:
4100   case X86::NEG64r:
4101     return X86::COND_AE;
4102   case X86::LZCNT16rr:
4103   case X86::LZCNT32rr:
4104   case X86::LZCNT64rr:
4105     return X86::COND_B;
4106   case X86::POPCNT16rr:
4107   case X86::POPCNT32rr:
4108   case X86::POPCNT64rr:
4109     return X86::COND_E;
4110   case X86::TZCNT16rr:
4111   case X86::TZCNT32rr:
4112   case X86::TZCNT64rr:
4113     return X86::COND_B;
4114   case X86::BSF16rr:
4115   case X86::BSF32rr:
4116   case X86::BSF64rr:
4117   case X86::BSR16rr:
4118   case X86::BSR32rr:
4119   case X86::BSR64rr:
4120     return X86::COND_E;
4121   case X86::BLSI32rr:
4122   case X86::BLSI64rr:
4123     return X86::COND_AE;
4124   case X86::BLSR32rr:
4125   case X86::BLSR64rr:
4126   case X86::BLSMSK32rr:
4127   case X86::BLSMSK64rr:
4128     return X86::COND_B;
4129   // TODO: TBM instructions.
4130   }
4131 }
4132 
4133 /// Check if there exists an earlier instruction that
4134 /// operates on the same source operands and sets flags in the same way as
4135 /// Compare; remove Compare if possible.
4136 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
4137                                         Register SrcReg2, int64_t CmpMask,
4138                                         int64_t CmpValue,
4139                                         const MachineRegisterInfo *MRI) const {
4140   // Check whether we can replace SUB with CMP.
4141   switch (CmpInstr.getOpcode()) {
4142   default: break;
4143   case X86::SUB64ri32:
4144   case X86::SUB64ri8:
4145   case X86::SUB32ri:
4146   case X86::SUB32ri8:
4147   case X86::SUB16ri:
4148   case X86::SUB16ri8:
4149   case X86::SUB8ri:
4150   case X86::SUB64rm:
4151   case X86::SUB32rm:
4152   case X86::SUB16rm:
4153   case X86::SUB8rm:
4154   case X86::SUB64rr:
4155   case X86::SUB32rr:
4156   case X86::SUB16rr:
4157   case X86::SUB8rr: {
4158     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
4159       return false;
4160     // There is no use of the destination register, we can replace SUB with CMP.
4161     unsigned NewOpcode = 0;
4162     switch (CmpInstr.getOpcode()) {
4163     default: llvm_unreachable("Unreachable!");
4164     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4165     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4166     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4167     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4168     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4169     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4170     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4171     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4172     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4173     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4174     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4175     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4176     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4177     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4178     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4179     }
4180     CmpInstr.setDesc(get(NewOpcode));
4181     CmpInstr.removeOperand(0);
4182     // Mutating this instruction invalidates any debug data associated with it.
4183     CmpInstr.dropDebugNumber();
4184     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4185     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4186         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4187       return false;
4188   }
4189   }
4190 
4191   // The following code tries to remove the comparison by re-using EFLAGS
4192   // from earlier instructions.
4193 
4194   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
4195 
4196   // Transformation currently requires SSA values.
4197   if (SrcReg2.isPhysical())
4198     return false;
4199   MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg);
4200   assert(SrcRegDef && "Must have a definition (SSA)");
4201 
4202   MachineInstr *MI = nullptr;
4203   MachineInstr *Sub = nullptr;
4204   MachineInstr *Movr0Inst = nullptr;
4205   bool NoSignFlag = false;
4206   bool ClearsOverflowFlag = false;
4207   bool ShouldUpdateCC = false;
4208   bool IsSwapped = false;
4209   X86::CondCode NewCC = X86::COND_INVALID;
4210   int64_t ImmDelta = 0;
4211 
4212   // Search backward from CmpInstr for the next instruction defining EFLAGS.
4213   const TargetRegisterInfo *TRI = &getRegisterInfo();
4214   MachineBasicBlock &CmpMBB = *CmpInstr.getParent();
4215   MachineBasicBlock::reverse_iterator From =
4216       std::next(MachineBasicBlock::reverse_iterator(CmpInstr));
4217   for (MachineBasicBlock *MBB = &CmpMBB;;) {
4218     for (MachineInstr &Inst : make_range(From, MBB->rend())) {
4219       // Try to use EFLAGS from the instruction defining %SrcReg. Example:
4220       //     %eax = addl ...
4221       //     ...                // EFLAGS not changed
4222       //     testl %eax, %eax   // <-- can be removed
4223       if (&Inst == SrcRegDef) {
4224         if (IsCmpZero &&
4225             isDefConvertible(Inst, NoSignFlag, ClearsOverflowFlag)) {
4226           MI = &Inst;
4227           break;
4228         }
4229         // Cannot find other candidates before definition of SrcReg.
4230         return false;
4231       }
4232 
4233       if (Inst.modifiesRegister(X86::EFLAGS, TRI)) {
4234         // Try to use EFLAGS produced by an instruction reading %SrcReg.
4235         // Example:
4236         //      %eax = ...
4237         //      ...
4238         //      popcntl %eax
4239         //      ...                 // EFLAGS not changed
4240         //      testl %eax, %eax    // <-- can be removed
4241         if (IsCmpZero) {
4242           NewCC = isUseDefConvertible(Inst);
4243           if (NewCC != X86::COND_INVALID && Inst.getOperand(1).isReg() &&
4244               Inst.getOperand(1).getReg() == SrcReg) {
4245             ShouldUpdateCC = true;
4246             MI = &Inst;
4247             break;
4248           }
4249         }
4250 
4251         // Try to use EFLAGS from an instruction with similar flag results.
4252         // Example:
4253         //     sub x, y  or  cmp x, y
4254         //     ...           // EFLAGS not changed
4255         //     cmp x, y      // <-- can be removed
4256         if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask, CmpValue,
4257                                  Inst, &IsSwapped, &ImmDelta)) {
4258           Sub = &Inst;
4259           break;
4260         }
4261 
4262         // MOV32r0 is implemented with xor which clobbers condition code. It is
4263         // safe to move up, if the definition to EFLAGS is dead and earlier
4264         // instructions do not read or write EFLAGS.
4265         if (!Movr0Inst && Inst.getOpcode() == X86::MOV32r0 &&
4266             Inst.registerDefIsDead(X86::EFLAGS, TRI)) {
4267           Movr0Inst = &Inst;
4268           continue;
4269         }
4270 
4271         // Cannot do anything for any other EFLAG changes.
4272         return false;
4273       }
4274     }
4275 
4276     if (MI || Sub)
4277       break;
4278 
4279     // Reached begin of basic block. Continue in predecessor if there is
4280     // exactly one.
4281     if (MBB->pred_size() != 1)
4282       return false;
4283     MBB = *MBB->pred_begin();
4284     From = MBB->rbegin();
4285   }
4286 
4287   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4288   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4289   // If we are done with the basic block, we need to check whether EFLAGS is
4290   // live-out.
4291   bool FlagsMayLiveOut = true;
4292   SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
4293   MachineBasicBlock::iterator AfterCmpInstr =
4294       std::next(MachineBasicBlock::iterator(CmpInstr));
4295   for (MachineInstr &Instr : make_range(AfterCmpInstr, CmpMBB.end())) {
4296     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4297     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4298     // We should check the usage if this instruction uses and updates EFLAGS.
4299     if (!UseEFLAGS && ModifyEFLAGS) {
4300       // It is safe to remove CmpInstr if EFLAGS is updated again.
4301       FlagsMayLiveOut = false;
4302       break;
4303     }
4304     if (!UseEFLAGS && !ModifyEFLAGS)
4305       continue;
4306 
4307     // EFLAGS is used by this instruction.
4308     X86::CondCode OldCC = X86::COND_INVALID;
4309     if (MI || IsSwapped || ImmDelta != 0) {
4310       // We decode the condition code from opcode.
4311       if (Instr.isBranch())
4312         OldCC = X86::getCondFromBranch(Instr);
4313       else {
4314         OldCC = X86::getCondFromSETCC(Instr);
4315         if (OldCC == X86::COND_INVALID)
4316           OldCC = X86::getCondFromCMov(Instr);
4317       }
4318       if (OldCC == X86::COND_INVALID) return false;
4319     }
4320     X86::CondCode ReplacementCC = X86::COND_INVALID;
4321     if (MI) {
4322       switch (OldCC) {
4323       default: break;
4324       case X86::COND_A: case X86::COND_AE:
4325       case X86::COND_B: case X86::COND_BE:
4326         // CF is used, we can't perform this optimization.
4327         return false;
4328       case X86::COND_G: case X86::COND_GE:
4329       case X86::COND_L: case X86::COND_LE:
4330       case X86::COND_O: case X86::COND_NO:
4331         // If OF is used, the instruction needs to clear it like CmpZero does.
4332         if (!ClearsOverflowFlag)
4333           return false;
4334         break;
4335       case X86::COND_S: case X86::COND_NS:
4336         // If SF is used, but the instruction doesn't update the SF, then we
4337         // can't do the optimization.
4338         if (NoSignFlag)
4339           return false;
4340         break;
4341       }
4342 
4343       // If we're updating the condition code check if we have to reverse the
4344       // condition.
4345       if (ShouldUpdateCC)
4346         switch (OldCC) {
4347         default:
4348           return false;
4349         case X86::COND_E:
4350           ReplacementCC = NewCC;
4351           break;
4352         case X86::COND_NE:
4353           ReplacementCC = GetOppositeBranchCondition(NewCC);
4354           break;
4355         }
4356     } else if (IsSwapped) {
4357       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4358       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4359       // We swap the condition code and synthesize the new opcode.
4360       ReplacementCC = getSwappedCondition(OldCC);
4361       if (ReplacementCC == X86::COND_INVALID)
4362         return false;
4363       ShouldUpdateCC = true;
4364     } else if (ImmDelta != 0) {
4365       unsigned BitWidth = TRI->getRegSizeInBits(*MRI->getRegClass(SrcReg));
4366       // Shift amount for min/max constants to adjust for 8/16/32 instruction
4367       // sizes.
4368       switch (OldCC) {
4369       case X86::COND_L: // x <s (C + 1)  -->  x <=s C
4370         if (ImmDelta != 1 || APInt::getSignedMinValue(BitWidth) == CmpValue)
4371           return false;
4372         ReplacementCC = X86::COND_LE;
4373         break;
4374       case X86::COND_B: // x <u (C + 1)  -->  x <=u C
4375         if (ImmDelta != 1 || CmpValue == 0)
4376           return false;
4377         ReplacementCC = X86::COND_BE;
4378         break;
4379       case X86::COND_GE: // x >=s (C + 1)  -->  x >s C
4380         if (ImmDelta != 1 || APInt::getSignedMinValue(BitWidth) == CmpValue)
4381           return false;
4382         ReplacementCC = X86::COND_G;
4383         break;
4384       case X86::COND_AE: // x >=u (C + 1)  -->  x >u C
4385         if (ImmDelta != 1 || CmpValue == 0)
4386           return false;
4387         ReplacementCC = X86::COND_A;
4388         break;
4389       case X86::COND_G: // x >s (C - 1)  -->  x >=s C
4390         if (ImmDelta != -1 || APInt::getSignedMaxValue(BitWidth) == CmpValue)
4391           return false;
4392         ReplacementCC = X86::COND_GE;
4393         break;
4394       case X86::COND_A: // x >u (C - 1)  -->  x >=u C
4395         if (ImmDelta != -1 || APInt::getMaxValue(BitWidth) == CmpValue)
4396           return false;
4397         ReplacementCC = X86::COND_AE;
4398         break;
4399       case X86::COND_LE: // x <=s (C - 1)  -->  x <s C
4400         if (ImmDelta != -1 || APInt::getSignedMaxValue(BitWidth) == CmpValue)
4401           return false;
4402         ReplacementCC = X86::COND_L;
4403         break;
4404       case X86::COND_BE: // x <=u (C - 1)  -->  x <u C
4405         if (ImmDelta != -1 || APInt::getMaxValue(BitWidth) == CmpValue)
4406           return false;
4407         ReplacementCC = X86::COND_B;
4408         break;
4409       default:
4410         return false;
4411       }
4412       ShouldUpdateCC = true;
4413     }
4414 
4415     if (ShouldUpdateCC && ReplacementCC != OldCC) {
4416       // Push the MachineInstr to OpsToUpdate.
4417       // If it is safe to remove CmpInstr, the condition code of these
4418       // instructions will be modified.
4419       OpsToUpdate.push_back(std::make_pair(&Instr, ReplacementCC));
4420     }
4421     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4422       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4423       FlagsMayLiveOut = false;
4424       break;
4425     }
4426   }
4427 
4428   // If we have to update users but EFLAGS is live-out abort, since we cannot
4429   // easily find all of the users.
4430   if ((MI != nullptr || ShouldUpdateCC) && FlagsMayLiveOut) {
4431     for (MachineBasicBlock *Successor : CmpMBB.successors())
4432       if (Successor->isLiveIn(X86::EFLAGS))
4433         return false;
4434   }
4435 
4436   // The instruction to be updated is either Sub or MI.
4437   assert((MI == nullptr || Sub == nullptr) && "Should not have Sub and MI set");
4438   Sub = MI != nullptr ? MI : Sub;
4439   MachineBasicBlock *SubBB = Sub->getParent();
4440   // Move Movr0Inst to the appropriate place before Sub.
4441   if (Movr0Inst) {
4442     // Only move within the same block so we don't accidentally move to a
4443     // block with higher execution frequency.
4444     if (&CmpMBB != SubBB)
4445       return false;
4446     // Look backwards until we find a def that doesn't use the current EFLAGS.
4447     MachineBasicBlock::reverse_iterator InsertI = Sub,
4448                                         InsertE = Sub->getParent()->rend();
4449     for (; InsertI != InsertE; ++InsertI) {
4450       MachineInstr *Instr = &*InsertI;
4451       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4452           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4453         Movr0Inst->getParent()->remove(Movr0Inst);
4454         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4455                                    Movr0Inst);
4456         break;
4457       }
4458     }
4459     if (InsertI == InsertE)
4460       return false;
4461   }
4462 
4463   // Make sure Sub instruction defines EFLAGS and mark the def live.
4464   MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
4465   assert(FlagDef && "Unable to locate a def EFLAGS operand");
4466   FlagDef->setIsDead(false);
4467 
4468   CmpInstr.eraseFromParent();
4469 
4470   // Modify the condition code of instructions in OpsToUpdate.
4471   for (auto &Op : OpsToUpdate) {
4472     Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
4473         .setImm(Op.second);
4474   }
4475   // Add EFLAGS to block live-ins between CmpBB and block of flags producer.
4476   for (MachineBasicBlock *MBB = &CmpMBB; MBB != SubBB;
4477        MBB = *MBB->pred_begin()) {
4478     assert(MBB->pred_size() == 1 && "Expected exactly one predecessor");
4479     if (!MBB->isLiveIn(X86::EFLAGS))
4480       MBB->addLiveIn(X86::EFLAGS);
4481   }
4482   return true;
4483 }
4484 
4485 /// Try to remove the load by folding it to a register
4486 /// operand at the use. We fold the load instructions if load defines a virtual
4487 /// register, the virtual register is used once in the same BB, and the
4488 /// instructions in-between do not load or store, and have no side effects.
4489 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
4490                                               const MachineRegisterInfo *MRI,
4491                                               Register &FoldAsLoadDefReg,
4492                                               MachineInstr *&DefMI) const {
4493   // Check whether we can move DefMI here.
4494   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4495   assert(DefMI);
4496   bool SawStore = false;
4497   if (!DefMI->isSafeToMove(nullptr, SawStore))
4498     return nullptr;
4499 
4500   // Collect information about virtual register operands of MI.
4501   SmallVector<unsigned, 1> SrcOperandIds;
4502   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4503     MachineOperand &MO = MI.getOperand(i);
4504     if (!MO.isReg())
4505       continue;
4506     Register Reg = MO.getReg();
4507     if (Reg != FoldAsLoadDefReg)
4508       continue;
4509     // Do not fold if we have a subreg use or a def.
4510     if (MO.getSubReg() || MO.isDef())
4511       return nullptr;
4512     SrcOperandIds.push_back(i);
4513   }
4514   if (SrcOperandIds.empty())
4515     return nullptr;
4516 
4517   // Check whether we can fold the def into SrcOperandId.
4518   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
4519     FoldAsLoadDefReg = 0;
4520     return FoldMI;
4521   }
4522 
4523   return nullptr;
4524 }
4525 
4526 /// Expand a single-def pseudo instruction to a two-addr
4527 /// instruction with two undef reads of the register being defined.
4528 /// This is used for mapping:
4529 ///   %xmm4 = V_SET0
4530 /// to:
4531 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
4532 ///
4533 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4534                              const MCInstrDesc &Desc) {
4535   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4536   Register Reg = MIB.getReg(0);
4537   MIB->setDesc(Desc);
4538 
4539   // MachineInstr::addOperand() will insert explicit operands before any
4540   // implicit operands.
4541   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4542   // But we don't trust that.
4543   assert(MIB.getReg(1) == Reg &&
4544          MIB.getReg(2) == Reg && "Misplaced operand");
4545   return true;
4546 }
4547 
4548 /// Expand a single-def pseudo instruction to a two-addr
4549 /// instruction with two %k0 reads.
4550 /// This is used for mapping:
4551 ///   %k4 = K_SET1
4552 /// to:
4553 ///   %k4 = KXNORrr %k0, %k0
4554 static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
4555                             Register Reg) {
4556   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4557   MIB->setDesc(Desc);
4558   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4559   return true;
4560 }
4561 
4562 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
4563                           bool MinusOne) {
4564   MachineBasicBlock &MBB = *MIB->getParent();
4565   const DebugLoc &DL = MIB->getDebugLoc();
4566   Register Reg = MIB.getReg(0);
4567 
4568   // Insert the XOR.
4569   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
4570       .addReg(Reg, RegState::Undef)
4571       .addReg(Reg, RegState::Undef);
4572 
4573   // Turn the pseudo into an INC or DEC.
4574   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
4575   MIB.addReg(Reg);
4576 
4577   return true;
4578 }
4579 
4580 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
4581                                const TargetInstrInfo &TII,
4582                                const X86Subtarget &Subtarget) {
4583   MachineBasicBlock &MBB = *MIB->getParent();
4584   const DebugLoc &DL = MIB->getDebugLoc();
4585   int64_t Imm = MIB->getOperand(1).getImm();
4586   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
4587   MachineBasicBlock::iterator I = MIB.getInstr();
4588 
4589   int StackAdjustment;
4590 
4591   if (Subtarget.is64Bit()) {
4592     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
4593            MIB->getOpcode() == X86::MOV32ImmSExti8);
4594 
4595     // Can't use push/pop lowering if the function might write to the red zone.
4596     X86MachineFunctionInfo *X86FI =
4597         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
4598     if (X86FI->getUsesRedZone()) {
4599       MIB->setDesc(TII.get(MIB->getOpcode() ==
4600                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
4601       return true;
4602     }
4603 
4604     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4605     // widen the register if necessary.
4606     StackAdjustment = 8;
4607     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4608     MIB->setDesc(TII.get(X86::POP64r));
4609     MIB->getOperand(0)
4610         .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
4611   } else {
4612     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
4613     StackAdjustment = 4;
4614     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4615     MIB->setDesc(TII.get(X86::POP32r));
4616   }
4617   MIB->removeOperand(1);
4618   MIB->addImplicitDefUseOperands(*MBB.getParent());
4619 
4620   // Build CFI if necessary.
4621   MachineFunction &MF = *MBB.getParent();
4622   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4623   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4624   bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
4625   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4626   if (EmitCFI) {
4627     TFL->BuildCFI(MBB, I, DL,
4628         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4629     TFL->BuildCFI(MBB, std::next(I), DL,
4630         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4631   }
4632 
4633   return true;
4634 }
4635 
4636 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4637 // code sequence is needed for other targets.
4638 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4639                                  const TargetInstrInfo &TII) {
4640   MachineBasicBlock &MBB = *MIB->getParent();
4641   const DebugLoc &DL = MIB->getDebugLoc();
4642   Register Reg = MIB.getReg(0);
4643   const GlobalValue *GV =
4644       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4645   auto Flags = MachineMemOperand::MOLoad |
4646                MachineMemOperand::MODereferenceable |
4647                MachineMemOperand::MOInvariant;
4648   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4649       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, Align(8));
4650   MachineBasicBlock::iterator I = MIB.getInstr();
4651 
4652   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4653       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4654       .addMemOperand(MMO);
4655   MIB->setDebugLoc(DL);
4656   MIB->setDesc(TII.get(X86::MOV64rm));
4657   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4658 }
4659 
4660 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4661   MachineBasicBlock &MBB = *MIB->getParent();
4662   MachineFunction &MF = *MBB.getParent();
4663   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4664   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4665   unsigned XorOp =
4666       MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4667   MIB->setDesc(TII.get(XorOp));
4668   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4669   return true;
4670 }
4671 
4672 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4673 // but not VLX. If it uses an extended register we need to use an instruction
4674 // that loads the lower 128/256-bit, but is available with only AVX512F.
4675 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4676                             const TargetRegisterInfo *TRI,
4677                             const MCInstrDesc &LoadDesc,
4678                             const MCInstrDesc &BroadcastDesc,
4679                             unsigned SubIdx) {
4680   Register DestReg = MIB.getReg(0);
4681   // Check if DestReg is XMM16-31 or YMM16-31.
4682   if (TRI->getEncodingValue(DestReg) < 16) {
4683     // We can use a normal VEX encoded load.
4684     MIB->setDesc(LoadDesc);
4685   } else {
4686     // Use a 128/256-bit VBROADCAST instruction.
4687     MIB->setDesc(BroadcastDesc);
4688     // Change the destination to a 512-bit register.
4689     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4690     MIB->getOperand(0).setReg(DestReg);
4691   }
4692   return true;
4693 }
4694 
4695 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4696 // but not VLX. If it uses an extended register we need to use an instruction
4697 // that stores the lower 128/256-bit, but is available with only AVX512F.
4698 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4699                              const TargetRegisterInfo *TRI,
4700                              const MCInstrDesc &StoreDesc,
4701                              const MCInstrDesc &ExtractDesc,
4702                              unsigned SubIdx) {
4703   Register SrcReg = MIB.getReg(X86::AddrNumOperands);
4704   // Check if DestReg is XMM16-31 or YMM16-31.
4705   if (TRI->getEncodingValue(SrcReg) < 16) {
4706     // We can use a normal VEX encoded store.
4707     MIB->setDesc(StoreDesc);
4708   } else {
4709     // Use a VEXTRACTF instruction.
4710     MIB->setDesc(ExtractDesc);
4711     // Change the destination to a 512-bit register.
4712     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4713     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4714     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4715   }
4716 
4717   return true;
4718 }
4719 
4720 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4721   MIB->setDesc(Desc);
4722   int64_t ShiftAmt = MIB->getOperand(2).getImm();
4723   // Temporarily remove the immediate so we can add another source register.
4724   MIB->removeOperand(2);
4725   // Add the register. Don't copy the kill flag if there is one.
4726   MIB.addReg(MIB.getReg(1),
4727              getUndefRegState(MIB->getOperand(1).isUndef()));
4728   // Add back the immediate.
4729   MIB.addImm(ShiftAmt);
4730   return true;
4731 }
4732 
4733 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4734   bool HasAVX = Subtarget.hasAVX();
4735   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4736   switch (MI.getOpcode()) {
4737   case X86::MOV32r0:
4738     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4739   case X86::MOV32r1:
4740     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4741   case X86::MOV32r_1:
4742     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4743   case X86::MOV32ImmSExti8:
4744   case X86::MOV64ImmSExti8:
4745     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4746   case X86::SETB_C32r:
4747     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4748   case X86::SETB_C64r:
4749     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4750   case X86::MMX_SET0:
4751     return Expand2AddrUndef(MIB, get(X86::MMX_PXORrr));
4752   case X86::V_SET0:
4753   case X86::FsFLD0SS:
4754   case X86::FsFLD0SD:
4755   case X86::FsFLD0F128:
4756     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4757   case X86::AVX_SET0: {
4758     assert(HasAVX && "AVX not supported");
4759     const TargetRegisterInfo *TRI = &getRegisterInfo();
4760     Register SrcReg = MIB.getReg(0);
4761     Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4762     MIB->getOperand(0).setReg(XReg);
4763     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4764     MIB.addReg(SrcReg, RegState::ImplicitDefine);
4765     return true;
4766   }
4767   case X86::AVX512_128_SET0:
4768   case X86::AVX512_FsFLD0SH:
4769   case X86::AVX512_FsFLD0SS:
4770   case X86::AVX512_FsFLD0SD:
4771   case X86::AVX512_FsFLD0F128: {
4772     bool HasVLX = Subtarget.hasVLX();
4773     Register SrcReg = MIB.getReg(0);
4774     const TargetRegisterInfo *TRI = &getRegisterInfo();
4775     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4776       return Expand2AddrUndef(MIB,
4777                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4778     // Extended register without VLX. Use a larger XOR.
4779     SrcReg =
4780         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4781     MIB->getOperand(0).setReg(SrcReg);
4782     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4783   }
4784   case X86::AVX512_256_SET0:
4785   case X86::AVX512_512_SET0: {
4786     bool HasVLX = Subtarget.hasVLX();
4787     Register SrcReg = MIB.getReg(0);
4788     const TargetRegisterInfo *TRI = &getRegisterInfo();
4789     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4790       Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4791       MIB->getOperand(0).setReg(XReg);
4792       Expand2AddrUndef(MIB,
4793                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4794       MIB.addReg(SrcReg, RegState::ImplicitDefine);
4795       return true;
4796     }
4797     if (MI.getOpcode() == X86::AVX512_256_SET0) {
4798       // No VLX so we must reference a zmm.
4799       unsigned ZReg =
4800         TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4801       MIB->getOperand(0).setReg(ZReg);
4802     }
4803     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4804   }
4805   case X86::V_SETALLONES:
4806     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4807   case X86::AVX2_SETALLONES:
4808     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4809   case X86::AVX1_SETALLONES: {
4810     Register Reg = MIB.getReg(0);
4811     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4812     MIB->setDesc(get(X86::VCMPPSYrri));
4813     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4814     return true;
4815   }
4816   case X86::AVX512_512_SETALLONES: {
4817     Register Reg = MIB.getReg(0);
4818     MIB->setDesc(get(X86::VPTERNLOGDZrri));
4819     // VPTERNLOGD needs 3 register inputs and an immediate.
4820     // 0xff will return 1s for any input.
4821     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4822        .addReg(Reg, RegState::Undef).addImm(0xff);
4823     return true;
4824   }
4825   case X86::AVX512_512_SEXT_MASK_32:
4826   case X86::AVX512_512_SEXT_MASK_64: {
4827     Register Reg = MIB.getReg(0);
4828     Register MaskReg = MIB.getReg(1);
4829     unsigned MaskState = getRegState(MIB->getOperand(1));
4830     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4831                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4832     MI.removeOperand(1);
4833     MIB->setDesc(get(Opc));
4834     // VPTERNLOG needs 3 register inputs and an immediate.
4835     // 0xff will return 1s for any input.
4836     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4837        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4838     return true;
4839   }
4840   case X86::VMOVAPSZ128rm_NOVLX:
4841     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4842                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4843   case X86::VMOVUPSZ128rm_NOVLX:
4844     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4845                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4846   case X86::VMOVAPSZ256rm_NOVLX:
4847     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4848                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4849   case X86::VMOVUPSZ256rm_NOVLX:
4850     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4851                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4852   case X86::VMOVAPSZ128mr_NOVLX:
4853     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4854                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4855   case X86::VMOVUPSZ128mr_NOVLX:
4856     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4857                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4858   case X86::VMOVAPSZ256mr_NOVLX:
4859     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4860                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4861   case X86::VMOVUPSZ256mr_NOVLX:
4862     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4863                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4864   case X86::MOV32ri64: {
4865     Register Reg = MIB.getReg(0);
4866     Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4867     MI.setDesc(get(X86::MOV32ri));
4868     MIB->getOperand(0).setReg(Reg32);
4869     MIB.addReg(Reg, RegState::ImplicitDefine);
4870     return true;
4871   }
4872 
4873   // KNL does not recognize dependency-breaking idioms for mask registers,
4874   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4875   // Using %k0 as the undef input register is a performance heuristic based
4876   // on the assumption that %k0 is used less frequently than the other mask
4877   // registers, since it is not usable as a write mask.
4878   // FIXME: A more advanced approach would be to choose the best input mask
4879   // register based on context.
4880   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4881   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4882   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4883   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4884   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4885   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4886   case TargetOpcode::LOAD_STACK_GUARD:
4887     expandLoadStackGuard(MIB, *this);
4888     return true;
4889   case X86::XOR64_FP:
4890   case X86::XOR32_FP:
4891     return expandXorFP(MIB, *this);
4892   case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4893   case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4894   case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4895   case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4896   case X86::ADD8rr_DB:    MIB->setDesc(get(X86::OR8rr));    break;
4897   case X86::ADD16rr_DB:   MIB->setDesc(get(X86::OR16rr));   break;
4898   case X86::ADD32rr_DB:   MIB->setDesc(get(X86::OR32rr));   break;
4899   case X86::ADD64rr_DB:   MIB->setDesc(get(X86::OR64rr));   break;
4900   case X86::ADD8ri_DB:    MIB->setDesc(get(X86::OR8ri));    break;
4901   case X86::ADD16ri_DB:   MIB->setDesc(get(X86::OR16ri));   break;
4902   case X86::ADD32ri_DB:   MIB->setDesc(get(X86::OR32ri));   break;
4903   case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4904   case X86::ADD16ri8_DB:  MIB->setDesc(get(X86::OR16ri8));  break;
4905   case X86::ADD32ri8_DB:  MIB->setDesc(get(X86::OR32ri8));  break;
4906   case X86::ADD64ri8_DB:  MIB->setDesc(get(X86::OR64ri8));  break;
4907   }
4908   return false;
4909 }
4910 
4911 /// Return true for all instructions that only update
4912 /// the first 32 or 64-bits of the destination register and leave the rest
4913 /// unmodified. This can be used to avoid folding loads if the instructions
4914 /// only update part of the destination register, and the non-updated part is
4915 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4916 /// instructions breaks the partial register dependency and it can improve
4917 /// performance. e.g.:
4918 ///
4919 ///   movss (%rdi), %xmm0
4920 ///   cvtss2sd %xmm0, %xmm0
4921 ///
4922 /// Instead of
4923 ///   cvtss2sd (%rdi), %xmm0
4924 ///
4925 /// FIXME: This should be turned into a TSFlags.
4926 ///
4927 static bool hasPartialRegUpdate(unsigned Opcode,
4928                                 const X86Subtarget &Subtarget,
4929                                 bool ForLoadFold = false) {
4930   switch (Opcode) {
4931   case X86::CVTSI2SSrr:
4932   case X86::CVTSI2SSrm:
4933   case X86::CVTSI642SSrr:
4934   case X86::CVTSI642SSrm:
4935   case X86::CVTSI2SDrr:
4936   case X86::CVTSI2SDrm:
4937   case X86::CVTSI642SDrr:
4938   case X86::CVTSI642SDrm:
4939     // Load folding won't effect the undef register update since the input is
4940     // a GPR.
4941     return !ForLoadFold;
4942   case X86::CVTSD2SSrr:
4943   case X86::CVTSD2SSrm:
4944   case X86::CVTSS2SDrr:
4945   case X86::CVTSS2SDrm:
4946   case X86::MOVHPDrm:
4947   case X86::MOVHPSrm:
4948   case X86::MOVLPDrm:
4949   case X86::MOVLPSrm:
4950   case X86::RCPSSr:
4951   case X86::RCPSSm:
4952   case X86::RCPSSr_Int:
4953   case X86::RCPSSm_Int:
4954   case X86::ROUNDSDr:
4955   case X86::ROUNDSDm:
4956   case X86::ROUNDSSr:
4957   case X86::ROUNDSSm:
4958   case X86::RSQRTSSr:
4959   case X86::RSQRTSSm:
4960   case X86::RSQRTSSr_Int:
4961   case X86::RSQRTSSm_Int:
4962   case X86::SQRTSSr:
4963   case X86::SQRTSSm:
4964   case X86::SQRTSSr_Int:
4965   case X86::SQRTSSm_Int:
4966   case X86::SQRTSDr:
4967   case X86::SQRTSDm:
4968   case X86::SQRTSDr_Int:
4969   case X86::SQRTSDm_Int:
4970     return true;
4971   case X86::VFCMULCPHZ128rm:
4972   case X86::VFCMULCPHZ128rmb:
4973   case X86::VFCMULCPHZ128rmbkz:
4974   case X86::VFCMULCPHZ128rmkz:
4975   case X86::VFCMULCPHZ128rr:
4976   case X86::VFCMULCPHZ128rrkz:
4977   case X86::VFCMULCPHZ256rm:
4978   case X86::VFCMULCPHZ256rmb:
4979   case X86::VFCMULCPHZ256rmbkz:
4980   case X86::VFCMULCPHZ256rmkz:
4981   case X86::VFCMULCPHZ256rr:
4982   case X86::VFCMULCPHZ256rrkz:
4983   case X86::VFCMULCPHZrm:
4984   case X86::VFCMULCPHZrmb:
4985   case X86::VFCMULCPHZrmbkz:
4986   case X86::VFCMULCPHZrmkz:
4987   case X86::VFCMULCPHZrr:
4988   case X86::VFCMULCPHZrrb:
4989   case X86::VFCMULCPHZrrbkz:
4990   case X86::VFCMULCPHZrrkz:
4991   case X86::VFMULCPHZ128rm:
4992   case X86::VFMULCPHZ128rmb:
4993   case X86::VFMULCPHZ128rmbkz:
4994   case X86::VFMULCPHZ128rmkz:
4995   case X86::VFMULCPHZ128rr:
4996   case X86::VFMULCPHZ128rrkz:
4997   case X86::VFMULCPHZ256rm:
4998   case X86::VFMULCPHZ256rmb:
4999   case X86::VFMULCPHZ256rmbkz:
5000   case X86::VFMULCPHZ256rmkz:
5001   case X86::VFMULCPHZ256rr:
5002   case X86::VFMULCPHZ256rrkz:
5003   case X86::VFMULCPHZrm:
5004   case X86::VFMULCPHZrmb:
5005   case X86::VFMULCPHZrmbkz:
5006   case X86::VFMULCPHZrmkz:
5007   case X86::VFMULCPHZrr:
5008   case X86::VFMULCPHZrrb:
5009   case X86::VFMULCPHZrrbkz:
5010   case X86::VFMULCPHZrrkz:
5011   case X86::VFCMULCSHZrm:
5012   case X86::VFCMULCSHZrmkz:
5013   case X86::VFCMULCSHZrr:
5014   case X86::VFCMULCSHZrrb:
5015   case X86::VFCMULCSHZrrbkz:
5016   case X86::VFCMULCSHZrrkz:
5017   case X86::VFMULCSHZrm:
5018   case X86::VFMULCSHZrmkz:
5019   case X86::VFMULCSHZrr:
5020   case X86::VFMULCSHZrrb:
5021   case X86::VFMULCSHZrrbkz:
5022   case X86::VFMULCSHZrrkz:
5023     return Subtarget.hasMULCFalseDeps();
5024   case X86::VPERMDYrm:
5025   case X86::VPERMDYrr:
5026   case X86::VPERMQYmi:
5027   case X86::VPERMQYri:
5028   case X86::VPERMPSYrm:
5029   case X86::VPERMPSYrr:
5030   case X86::VPERMPDYmi:
5031   case X86::VPERMPDYri:
5032   case X86::VPERMDZ256rm:
5033   case X86::VPERMDZ256rmb:
5034   case X86::VPERMDZ256rmbkz:
5035   case X86::VPERMDZ256rmkz:
5036   case X86::VPERMDZ256rr:
5037   case X86::VPERMDZ256rrkz:
5038   case X86::VPERMDZrm:
5039   case X86::VPERMDZrmb:
5040   case X86::VPERMDZrmbkz:
5041   case X86::VPERMDZrmkz:
5042   case X86::VPERMDZrr:
5043   case X86::VPERMDZrrkz:
5044   case X86::VPERMQZ256mbi:
5045   case X86::VPERMQZ256mbikz:
5046   case X86::VPERMQZ256mi:
5047   case X86::VPERMQZ256mikz:
5048   case X86::VPERMQZ256ri:
5049   case X86::VPERMQZ256rikz:
5050   case X86::VPERMQZ256rm:
5051   case X86::VPERMQZ256rmb:
5052   case X86::VPERMQZ256rmbkz:
5053   case X86::VPERMQZ256rmkz:
5054   case X86::VPERMQZ256rr:
5055   case X86::VPERMQZ256rrkz:
5056   case X86::VPERMQZmbi:
5057   case X86::VPERMQZmbikz:
5058   case X86::VPERMQZmi:
5059   case X86::VPERMQZmikz:
5060   case X86::VPERMQZri:
5061   case X86::VPERMQZrikz:
5062   case X86::VPERMQZrm:
5063   case X86::VPERMQZrmb:
5064   case X86::VPERMQZrmbkz:
5065   case X86::VPERMQZrmkz:
5066   case X86::VPERMQZrr:
5067   case X86::VPERMQZrrkz:
5068   case X86::VPERMPSZ256rm:
5069   case X86::VPERMPSZ256rmb:
5070   case X86::VPERMPSZ256rmbkz:
5071   case X86::VPERMPSZ256rmkz:
5072   case X86::VPERMPSZ256rr:
5073   case X86::VPERMPSZ256rrkz:
5074   case X86::VPERMPSZrm:
5075   case X86::VPERMPSZrmb:
5076   case X86::VPERMPSZrmbkz:
5077   case X86::VPERMPSZrmkz:
5078   case X86::VPERMPSZrr:
5079   case X86::VPERMPSZrrkz:
5080   case X86::VPERMPDZ256mbi:
5081   case X86::VPERMPDZ256mbikz:
5082   case X86::VPERMPDZ256mi:
5083   case X86::VPERMPDZ256mikz:
5084   case X86::VPERMPDZ256ri:
5085   case X86::VPERMPDZ256rikz:
5086   case X86::VPERMPDZ256rm:
5087   case X86::VPERMPDZ256rmb:
5088   case X86::VPERMPDZ256rmbkz:
5089   case X86::VPERMPDZ256rmkz:
5090   case X86::VPERMPDZ256rr:
5091   case X86::VPERMPDZ256rrkz:
5092   case X86::VPERMPDZmbi:
5093   case X86::VPERMPDZmbikz:
5094   case X86::VPERMPDZmi:
5095   case X86::VPERMPDZmikz:
5096   case X86::VPERMPDZri:
5097   case X86::VPERMPDZrikz:
5098   case X86::VPERMPDZrm:
5099   case X86::VPERMPDZrmb:
5100   case X86::VPERMPDZrmbkz:
5101   case X86::VPERMPDZrmkz:
5102   case X86::VPERMPDZrr:
5103   case X86::VPERMPDZrrkz:
5104     return Subtarget.hasPERMFalseDeps();
5105   case X86::VRANGEPDZ128rmbi:
5106   case X86::VRANGEPDZ128rmbikz:
5107   case X86::VRANGEPDZ128rmi:
5108   case X86::VRANGEPDZ128rmikz:
5109   case X86::VRANGEPDZ128rri:
5110   case X86::VRANGEPDZ128rrikz:
5111   case X86::VRANGEPDZ256rmbi:
5112   case X86::VRANGEPDZ256rmbikz:
5113   case X86::VRANGEPDZ256rmi:
5114   case X86::VRANGEPDZ256rmikz:
5115   case X86::VRANGEPDZ256rri:
5116   case X86::VRANGEPDZ256rrikz:
5117   case X86::VRANGEPDZrmbi:
5118   case X86::VRANGEPDZrmbikz:
5119   case X86::VRANGEPDZrmi:
5120   case X86::VRANGEPDZrmikz:
5121   case X86::VRANGEPDZrri:
5122   case X86::VRANGEPDZrrib:
5123   case X86::VRANGEPDZrribkz:
5124   case X86::VRANGEPDZrrikz:
5125   case X86::VRANGEPSZ128rmbi:
5126   case X86::VRANGEPSZ128rmbikz:
5127   case X86::VRANGEPSZ128rmi:
5128   case X86::VRANGEPSZ128rmikz:
5129   case X86::VRANGEPSZ128rri:
5130   case X86::VRANGEPSZ128rrikz:
5131   case X86::VRANGEPSZ256rmbi:
5132   case X86::VRANGEPSZ256rmbikz:
5133   case X86::VRANGEPSZ256rmi:
5134   case X86::VRANGEPSZ256rmikz:
5135   case X86::VRANGEPSZ256rri:
5136   case X86::VRANGEPSZ256rrikz:
5137   case X86::VRANGEPSZrmbi:
5138   case X86::VRANGEPSZrmbikz:
5139   case X86::VRANGEPSZrmi:
5140   case X86::VRANGEPSZrmikz:
5141   case X86::VRANGEPSZrri:
5142   case X86::VRANGEPSZrrib:
5143   case X86::VRANGEPSZrribkz:
5144   case X86::VRANGEPSZrrikz:
5145   case X86::VRANGESDZrmi:
5146   case X86::VRANGESDZrmikz:
5147   case X86::VRANGESDZrri:
5148   case X86::VRANGESDZrrib:
5149   case X86::VRANGESDZrribkz:
5150   case X86::VRANGESDZrrikz:
5151   case X86::VRANGESSZrmi:
5152   case X86::VRANGESSZrmikz:
5153   case X86::VRANGESSZrri:
5154   case X86::VRANGESSZrrib:
5155   case X86::VRANGESSZrribkz:
5156   case X86::VRANGESSZrrikz:
5157     return Subtarget.hasRANGEFalseDeps();
5158   case X86::VGETMANTSSZrmi:
5159   case X86::VGETMANTSSZrmikz:
5160   case X86::VGETMANTSSZrri:
5161   case X86::VGETMANTSSZrrib:
5162   case X86::VGETMANTSSZrribkz:
5163   case X86::VGETMANTSSZrrikz:
5164   case X86::VGETMANTSDZrmi:
5165   case X86::VGETMANTSDZrmikz:
5166   case X86::VGETMANTSDZrri:
5167   case X86::VGETMANTSDZrrib:
5168   case X86::VGETMANTSDZrribkz:
5169   case X86::VGETMANTSDZrrikz:
5170   case X86::VGETMANTSHZrmi:
5171   case X86::VGETMANTSHZrmikz:
5172   case X86::VGETMANTSHZrri:
5173   case X86::VGETMANTSHZrrib:
5174   case X86::VGETMANTSHZrribkz:
5175   case X86::VGETMANTSHZrrikz:
5176   case X86::VGETMANTPSZ128rmbi:
5177   case X86::VGETMANTPSZ128rmbikz:
5178   case X86::VGETMANTPSZ128rmi:
5179   case X86::VGETMANTPSZ128rmikz:
5180   case X86::VGETMANTPSZ256rmbi:
5181   case X86::VGETMANTPSZ256rmbikz:
5182   case X86::VGETMANTPSZ256rmi:
5183   case X86::VGETMANTPSZ256rmikz:
5184   case X86::VGETMANTPSZrmbi:
5185   case X86::VGETMANTPSZrmbikz:
5186   case X86::VGETMANTPSZrmi:
5187   case X86::VGETMANTPSZrmikz:
5188   case X86::VGETMANTPDZ128rmbi:
5189   case X86::VGETMANTPDZ128rmbikz:
5190   case X86::VGETMANTPDZ128rmi:
5191   case X86::VGETMANTPDZ128rmikz:
5192   case X86::VGETMANTPDZ256rmbi:
5193   case X86::VGETMANTPDZ256rmbikz:
5194   case X86::VGETMANTPDZ256rmi:
5195   case X86::VGETMANTPDZ256rmikz:
5196   case X86::VGETMANTPDZrmbi:
5197   case X86::VGETMANTPDZrmbikz:
5198   case X86::VGETMANTPDZrmi:
5199   case X86::VGETMANTPDZrmikz:
5200     return Subtarget.hasGETMANTFalseDeps();
5201   case X86::VPMULLQZ128rm:
5202   case X86::VPMULLQZ128rmb:
5203   case X86::VPMULLQZ128rmbkz:
5204   case X86::VPMULLQZ128rmkz:
5205   case X86::VPMULLQZ128rr:
5206   case X86::VPMULLQZ128rrkz:
5207   case X86::VPMULLQZ256rm:
5208   case X86::VPMULLQZ256rmb:
5209   case X86::VPMULLQZ256rmbkz:
5210   case X86::VPMULLQZ256rmkz:
5211   case X86::VPMULLQZ256rr:
5212   case X86::VPMULLQZ256rrkz:
5213   case X86::VPMULLQZrm:
5214   case X86::VPMULLQZrmb:
5215   case X86::VPMULLQZrmbkz:
5216   case X86::VPMULLQZrmkz:
5217   case X86::VPMULLQZrr:
5218   case X86::VPMULLQZrrkz:
5219     return Subtarget.hasMULLQFalseDeps();
5220   // GPR
5221   case X86::POPCNT32rm:
5222   case X86::POPCNT32rr:
5223   case X86::POPCNT64rm:
5224   case X86::POPCNT64rr:
5225     return Subtarget.hasPOPCNTFalseDeps();
5226   case X86::LZCNT32rm:
5227   case X86::LZCNT32rr:
5228   case X86::LZCNT64rm:
5229   case X86::LZCNT64rr:
5230   case X86::TZCNT32rm:
5231   case X86::TZCNT32rr:
5232   case X86::TZCNT64rm:
5233   case X86::TZCNT64rr:
5234     return Subtarget.hasLZCNTFalseDeps();
5235   }
5236 
5237   return false;
5238 }
5239 
5240 /// Inform the BreakFalseDeps pass how many idle
5241 /// instructions we would like before a partial register update.
5242 unsigned X86InstrInfo::getPartialRegUpdateClearance(
5243     const MachineInstr &MI, unsigned OpNum,
5244     const TargetRegisterInfo *TRI) const {
5245   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
5246     return 0;
5247 
5248   // If MI is marked as reading Reg, the partial register update is wanted.
5249   const MachineOperand &MO = MI.getOperand(0);
5250   Register Reg = MO.getReg();
5251   if (Reg.isVirtual()) {
5252     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
5253       return 0;
5254   } else {
5255     if (MI.readsRegister(Reg, TRI))
5256       return 0;
5257   }
5258 
5259   // If any instructions in the clearance range are reading Reg, insert a
5260   // dependency breaking instruction, which is inexpensive and is likely to
5261   // be hidden in other instruction's cycles.
5262   return PartialRegUpdateClearance;
5263 }
5264 
5265 // Return true for any instruction the copies the high bits of the first source
5266 // operand into the unused high bits of the destination operand.
5267 // Also returns true for instructions that have two inputs where one may
5268 // be undef and we want it to use the same register as the other input.
5269 static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
5270                               bool ForLoadFold = false) {
5271   // Set the OpNum parameter to the first source operand.
5272   switch (Opcode) {
5273   case X86::MMX_PUNPCKHBWrr:
5274   case X86::MMX_PUNPCKHWDrr:
5275   case X86::MMX_PUNPCKHDQrr:
5276   case X86::MMX_PUNPCKLBWrr:
5277   case X86::MMX_PUNPCKLWDrr:
5278   case X86::MMX_PUNPCKLDQrr:
5279   case X86::MOVHLPSrr:
5280   case X86::PACKSSWBrr:
5281   case X86::PACKUSWBrr:
5282   case X86::PACKSSDWrr:
5283   case X86::PACKUSDWrr:
5284   case X86::PUNPCKHBWrr:
5285   case X86::PUNPCKLBWrr:
5286   case X86::PUNPCKHWDrr:
5287   case X86::PUNPCKLWDrr:
5288   case X86::PUNPCKHDQrr:
5289   case X86::PUNPCKLDQrr:
5290   case X86::PUNPCKHQDQrr:
5291   case X86::PUNPCKLQDQrr:
5292   case X86::SHUFPDrri:
5293   case X86::SHUFPSrri:
5294     // These instructions are sometimes used with an undef first or second
5295     // source. Return true here so BreakFalseDeps will assign this source to the
5296     // same register as the first source to avoid a false dependency.
5297     // Operand 1 of these instructions is tied so they're separate from their
5298     // VEX counterparts.
5299     return OpNum == 2 && !ForLoadFold;
5300 
5301   case X86::VMOVLHPSrr:
5302   case X86::VMOVLHPSZrr:
5303   case X86::VPACKSSWBrr:
5304   case X86::VPACKUSWBrr:
5305   case X86::VPACKSSDWrr:
5306   case X86::VPACKUSDWrr:
5307   case X86::VPACKSSWBZ128rr:
5308   case X86::VPACKUSWBZ128rr:
5309   case X86::VPACKSSDWZ128rr:
5310   case X86::VPACKUSDWZ128rr:
5311   case X86::VPERM2F128rr:
5312   case X86::VPERM2I128rr:
5313   case X86::VSHUFF32X4Z256rri:
5314   case X86::VSHUFF32X4Zrri:
5315   case X86::VSHUFF64X2Z256rri:
5316   case X86::VSHUFF64X2Zrri:
5317   case X86::VSHUFI32X4Z256rri:
5318   case X86::VSHUFI32X4Zrri:
5319   case X86::VSHUFI64X2Z256rri:
5320   case X86::VSHUFI64X2Zrri:
5321   case X86::VPUNPCKHBWrr:
5322   case X86::VPUNPCKLBWrr:
5323   case X86::VPUNPCKHBWYrr:
5324   case X86::VPUNPCKLBWYrr:
5325   case X86::VPUNPCKHBWZ128rr:
5326   case X86::VPUNPCKLBWZ128rr:
5327   case X86::VPUNPCKHBWZ256rr:
5328   case X86::VPUNPCKLBWZ256rr:
5329   case X86::VPUNPCKHBWZrr:
5330   case X86::VPUNPCKLBWZrr:
5331   case X86::VPUNPCKHWDrr:
5332   case X86::VPUNPCKLWDrr:
5333   case X86::VPUNPCKHWDYrr:
5334   case X86::VPUNPCKLWDYrr:
5335   case X86::VPUNPCKHWDZ128rr:
5336   case X86::VPUNPCKLWDZ128rr:
5337   case X86::VPUNPCKHWDZ256rr:
5338   case X86::VPUNPCKLWDZ256rr:
5339   case X86::VPUNPCKHWDZrr:
5340   case X86::VPUNPCKLWDZrr:
5341   case X86::VPUNPCKHDQrr:
5342   case X86::VPUNPCKLDQrr:
5343   case X86::VPUNPCKHDQYrr:
5344   case X86::VPUNPCKLDQYrr:
5345   case X86::VPUNPCKHDQZ128rr:
5346   case X86::VPUNPCKLDQZ128rr:
5347   case X86::VPUNPCKHDQZ256rr:
5348   case X86::VPUNPCKLDQZ256rr:
5349   case X86::VPUNPCKHDQZrr:
5350   case X86::VPUNPCKLDQZrr:
5351   case X86::VPUNPCKHQDQrr:
5352   case X86::VPUNPCKLQDQrr:
5353   case X86::VPUNPCKHQDQYrr:
5354   case X86::VPUNPCKLQDQYrr:
5355   case X86::VPUNPCKHQDQZ128rr:
5356   case X86::VPUNPCKLQDQZ128rr:
5357   case X86::VPUNPCKHQDQZ256rr:
5358   case X86::VPUNPCKLQDQZ256rr:
5359   case X86::VPUNPCKHQDQZrr:
5360   case X86::VPUNPCKLQDQZrr:
5361     // These instructions are sometimes used with an undef first or second
5362     // source. Return true here so BreakFalseDeps will assign this source to the
5363     // same register as the first source to avoid a false dependency.
5364     return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
5365 
5366   case X86::VCVTSI2SSrr:
5367   case X86::VCVTSI2SSrm:
5368   case X86::VCVTSI2SSrr_Int:
5369   case X86::VCVTSI2SSrm_Int:
5370   case X86::VCVTSI642SSrr:
5371   case X86::VCVTSI642SSrm:
5372   case X86::VCVTSI642SSrr_Int:
5373   case X86::VCVTSI642SSrm_Int:
5374   case X86::VCVTSI2SDrr:
5375   case X86::VCVTSI2SDrm:
5376   case X86::VCVTSI2SDrr_Int:
5377   case X86::VCVTSI2SDrm_Int:
5378   case X86::VCVTSI642SDrr:
5379   case X86::VCVTSI642SDrm:
5380   case X86::VCVTSI642SDrr_Int:
5381   case X86::VCVTSI642SDrm_Int:
5382   // AVX-512
5383   case X86::VCVTSI2SSZrr:
5384   case X86::VCVTSI2SSZrm:
5385   case X86::VCVTSI2SSZrr_Int:
5386   case X86::VCVTSI2SSZrrb_Int:
5387   case X86::VCVTSI2SSZrm_Int:
5388   case X86::VCVTSI642SSZrr:
5389   case X86::VCVTSI642SSZrm:
5390   case X86::VCVTSI642SSZrr_Int:
5391   case X86::VCVTSI642SSZrrb_Int:
5392   case X86::VCVTSI642SSZrm_Int:
5393   case X86::VCVTSI2SDZrr:
5394   case X86::VCVTSI2SDZrm:
5395   case X86::VCVTSI2SDZrr_Int:
5396   case X86::VCVTSI2SDZrm_Int:
5397   case X86::VCVTSI642SDZrr:
5398   case X86::VCVTSI642SDZrm:
5399   case X86::VCVTSI642SDZrr_Int:
5400   case X86::VCVTSI642SDZrrb_Int:
5401   case X86::VCVTSI642SDZrm_Int:
5402   case X86::VCVTUSI2SSZrr:
5403   case X86::VCVTUSI2SSZrm:
5404   case X86::VCVTUSI2SSZrr_Int:
5405   case X86::VCVTUSI2SSZrrb_Int:
5406   case X86::VCVTUSI2SSZrm_Int:
5407   case X86::VCVTUSI642SSZrr:
5408   case X86::VCVTUSI642SSZrm:
5409   case X86::VCVTUSI642SSZrr_Int:
5410   case X86::VCVTUSI642SSZrrb_Int:
5411   case X86::VCVTUSI642SSZrm_Int:
5412   case X86::VCVTUSI2SDZrr:
5413   case X86::VCVTUSI2SDZrm:
5414   case X86::VCVTUSI2SDZrr_Int:
5415   case X86::VCVTUSI2SDZrm_Int:
5416   case X86::VCVTUSI642SDZrr:
5417   case X86::VCVTUSI642SDZrm:
5418   case X86::VCVTUSI642SDZrr_Int:
5419   case X86::VCVTUSI642SDZrrb_Int:
5420   case X86::VCVTUSI642SDZrm_Int:
5421   case X86::VCVTSI2SHZrr:
5422   case X86::VCVTSI2SHZrm:
5423   case X86::VCVTSI2SHZrr_Int:
5424   case X86::VCVTSI2SHZrrb_Int:
5425   case X86::VCVTSI2SHZrm_Int:
5426   case X86::VCVTSI642SHZrr:
5427   case X86::VCVTSI642SHZrm:
5428   case X86::VCVTSI642SHZrr_Int:
5429   case X86::VCVTSI642SHZrrb_Int:
5430   case X86::VCVTSI642SHZrm_Int:
5431   case X86::VCVTUSI2SHZrr:
5432   case X86::VCVTUSI2SHZrm:
5433   case X86::VCVTUSI2SHZrr_Int:
5434   case X86::VCVTUSI2SHZrrb_Int:
5435   case X86::VCVTUSI2SHZrm_Int:
5436   case X86::VCVTUSI642SHZrr:
5437   case X86::VCVTUSI642SHZrm:
5438   case X86::VCVTUSI642SHZrr_Int:
5439   case X86::VCVTUSI642SHZrrb_Int:
5440   case X86::VCVTUSI642SHZrm_Int:
5441     // Load folding won't effect the undef register update since the input is
5442     // a GPR.
5443     return OpNum == 1 && !ForLoadFold;
5444   case X86::VCVTSD2SSrr:
5445   case X86::VCVTSD2SSrm:
5446   case X86::VCVTSD2SSrr_Int:
5447   case X86::VCVTSD2SSrm_Int:
5448   case X86::VCVTSS2SDrr:
5449   case X86::VCVTSS2SDrm:
5450   case X86::VCVTSS2SDrr_Int:
5451   case X86::VCVTSS2SDrm_Int:
5452   case X86::VRCPSSr:
5453   case X86::VRCPSSr_Int:
5454   case X86::VRCPSSm:
5455   case X86::VRCPSSm_Int:
5456   case X86::VROUNDSDr:
5457   case X86::VROUNDSDm:
5458   case X86::VROUNDSDr_Int:
5459   case X86::VROUNDSDm_Int:
5460   case X86::VROUNDSSr:
5461   case X86::VROUNDSSm:
5462   case X86::VROUNDSSr_Int:
5463   case X86::VROUNDSSm_Int:
5464   case X86::VRSQRTSSr:
5465   case X86::VRSQRTSSr_Int:
5466   case X86::VRSQRTSSm:
5467   case X86::VRSQRTSSm_Int:
5468   case X86::VSQRTSSr:
5469   case X86::VSQRTSSr_Int:
5470   case X86::VSQRTSSm:
5471   case X86::VSQRTSSm_Int:
5472   case X86::VSQRTSDr:
5473   case X86::VSQRTSDr_Int:
5474   case X86::VSQRTSDm:
5475   case X86::VSQRTSDm_Int:
5476   // AVX-512
5477   case X86::VCVTSD2SSZrr:
5478   case X86::VCVTSD2SSZrr_Int:
5479   case X86::VCVTSD2SSZrrb_Int:
5480   case X86::VCVTSD2SSZrm:
5481   case X86::VCVTSD2SSZrm_Int:
5482   case X86::VCVTSS2SDZrr:
5483   case X86::VCVTSS2SDZrr_Int:
5484   case X86::VCVTSS2SDZrrb_Int:
5485   case X86::VCVTSS2SDZrm:
5486   case X86::VCVTSS2SDZrm_Int:
5487   case X86::VGETEXPSDZr:
5488   case X86::VGETEXPSDZrb:
5489   case X86::VGETEXPSDZm:
5490   case X86::VGETEXPSSZr:
5491   case X86::VGETEXPSSZrb:
5492   case X86::VGETEXPSSZm:
5493   case X86::VGETMANTSDZrri:
5494   case X86::VGETMANTSDZrrib:
5495   case X86::VGETMANTSDZrmi:
5496   case X86::VGETMANTSSZrri:
5497   case X86::VGETMANTSSZrrib:
5498   case X86::VGETMANTSSZrmi:
5499   case X86::VRNDSCALESDZr:
5500   case X86::VRNDSCALESDZr_Int:
5501   case X86::VRNDSCALESDZrb_Int:
5502   case X86::VRNDSCALESDZm:
5503   case X86::VRNDSCALESDZm_Int:
5504   case X86::VRNDSCALESSZr:
5505   case X86::VRNDSCALESSZr_Int:
5506   case X86::VRNDSCALESSZrb_Int:
5507   case X86::VRNDSCALESSZm:
5508   case X86::VRNDSCALESSZm_Int:
5509   case X86::VRCP14SDZrr:
5510   case X86::VRCP14SDZrm:
5511   case X86::VRCP14SSZrr:
5512   case X86::VRCP14SSZrm:
5513   case X86::VRCPSHZrr:
5514   case X86::VRCPSHZrm:
5515   case X86::VRSQRTSHZrr:
5516   case X86::VRSQRTSHZrm:
5517   case X86::VREDUCESHZrmi:
5518   case X86::VREDUCESHZrri:
5519   case X86::VREDUCESHZrrib:
5520   case X86::VGETEXPSHZr:
5521   case X86::VGETEXPSHZrb:
5522   case X86::VGETEXPSHZm:
5523   case X86::VGETMANTSHZrri:
5524   case X86::VGETMANTSHZrrib:
5525   case X86::VGETMANTSHZrmi:
5526   case X86::VRNDSCALESHZr:
5527   case X86::VRNDSCALESHZr_Int:
5528   case X86::VRNDSCALESHZrb_Int:
5529   case X86::VRNDSCALESHZm:
5530   case X86::VRNDSCALESHZm_Int:
5531   case X86::VSQRTSHZr:
5532   case X86::VSQRTSHZr_Int:
5533   case X86::VSQRTSHZrb_Int:
5534   case X86::VSQRTSHZm:
5535   case X86::VSQRTSHZm_Int:
5536   case X86::VRCP28SDZr:
5537   case X86::VRCP28SDZrb:
5538   case X86::VRCP28SDZm:
5539   case X86::VRCP28SSZr:
5540   case X86::VRCP28SSZrb:
5541   case X86::VRCP28SSZm:
5542   case X86::VREDUCESSZrmi:
5543   case X86::VREDUCESSZrri:
5544   case X86::VREDUCESSZrrib:
5545   case X86::VRSQRT14SDZrr:
5546   case X86::VRSQRT14SDZrm:
5547   case X86::VRSQRT14SSZrr:
5548   case X86::VRSQRT14SSZrm:
5549   case X86::VRSQRT28SDZr:
5550   case X86::VRSQRT28SDZrb:
5551   case X86::VRSQRT28SDZm:
5552   case X86::VRSQRT28SSZr:
5553   case X86::VRSQRT28SSZrb:
5554   case X86::VRSQRT28SSZm:
5555   case X86::VSQRTSSZr:
5556   case X86::VSQRTSSZr_Int:
5557   case X86::VSQRTSSZrb_Int:
5558   case X86::VSQRTSSZm:
5559   case X86::VSQRTSSZm_Int:
5560   case X86::VSQRTSDZr:
5561   case X86::VSQRTSDZr_Int:
5562   case X86::VSQRTSDZrb_Int:
5563   case X86::VSQRTSDZm:
5564   case X86::VSQRTSDZm_Int:
5565   case X86::VCVTSD2SHZrr:
5566   case X86::VCVTSD2SHZrr_Int:
5567   case X86::VCVTSD2SHZrrb_Int:
5568   case X86::VCVTSD2SHZrm:
5569   case X86::VCVTSD2SHZrm_Int:
5570   case X86::VCVTSS2SHZrr:
5571   case X86::VCVTSS2SHZrr_Int:
5572   case X86::VCVTSS2SHZrrb_Int:
5573   case X86::VCVTSS2SHZrm:
5574   case X86::VCVTSS2SHZrm_Int:
5575   case X86::VCVTSH2SDZrr:
5576   case X86::VCVTSH2SDZrr_Int:
5577   case X86::VCVTSH2SDZrrb_Int:
5578   case X86::VCVTSH2SDZrm:
5579   case X86::VCVTSH2SDZrm_Int:
5580   case X86::VCVTSH2SSZrr:
5581   case X86::VCVTSH2SSZrr_Int:
5582   case X86::VCVTSH2SSZrrb_Int:
5583   case X86::VCVTSH2SSZrm:
5584   case X86::VCVTSH2SSZrm_Int:
5585     return OpNum == 1;
5586   case X86::VMOVSSZrrk:
5587   case X86::VMOVSDZrrk:
5588     return OpNum == 3 && !ForLoadFold;
5589   case X86::VMOVSSZrrkz:
5590   case X86::VMOVSDZrrkz:
5591     return OpNum == 2 && !ForLoadFold;
5592   }
5593 
5594   return false;
5595 }
5596 
5597 /// Inform the BreakFalseDeps pass how many idle instructions we would like
5598 /// before certain undef register reads.
5599 ///
5600 /// This catches the VCVTSI2SD family of instructions:
5601 ///
5602 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
5603 ///
5604 /// We should to be careful *not* to catch VXOR idioms which are presumably
5605 /// handled specially in the pipeline:
5606 ///
5607 /// vxorps undef %xmm1, undef %xmm1, %xmm1
5608 ///
5609 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5610 /// high bits that are passed-through are not live.
5611 unsigned
5612 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
5613                                    const TargetRegisterInfo *TRI) const {
5614   const MachineOperand &MO = MI.getOperand(OpNum);
5615   if (Register::isPhysicalRegister(MO.getReg()) &&
5616       hasUndefRegUpdate(MI.getOpcode(), OpNum))
5617     return UndefRegClearance;
5618 
5619   return 0;
5620 }
5621 
5622 void X86InstrInfo::breakPartialRegDependency(
5623     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5624   Register Reg = MI.getOperand(OpNum).getReg();
5625   // If MI kills this register, the false dependence is already broken.
5626   if (MI.killsRegister(Reg, TRI))
5627     return;
5628 
5629   if (X86::VR128RegClass.contains(Reg)) {
5630     // These instructions are all floating point domain, so xorps is the best
5631     // choice.
5632     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
5633     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
5634         .addReg(Reg, RegState::Undef)
5635         .addReg(Reg, RegState::Undef);
5636     MI.addRegisterKilled(Reg, TRI, true);
5637   } else if (X86::VR256RegClass.contains(Reg)) {
5638     // Use vxorps to clear the full ymm register.
5639     // It wants to read and write the xmm sub-register.
5640     Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5641     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
5642         .addReg(XReg, RegState::Undef)
5643         .addReg(XReg, RegState::Undef)
5644         .addReg(Reg, RegState::ImplicitDefine);
5645     MI.addRegisterKilled(Reg, TRI, true);
5646   } else if (X86::VR128XRegClass.contains(Reg)) {
5647     // Only handle VLX targets.
5648     if (!Subtarget.hasVLX())
5649       return;
5650     // Since vxorps requires AVX512DQ, vpxord should be the best choice.
5651     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VPXORDZ128rr), Reg)
5652         .addReg(Reg, RegState::Undef)
5653         .addReg(Reg, RegState::Undef);
5654     MI.addRegisterKilled(Reg, TRI, true);
5655   } else if (X86::VR256XRegClass.contains(Reg) ||
5656              X86::VR512RegClass.contains(Reg)) {
5657     // Only handle VLX targets.
5658     if (!Subtarget.hasVLX())
5659       return;
5660     // Use vpxord to clear the full ymm/zmm register.
5661     // It wants to read and write the xmm sub-register.
5662     Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5663     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VPXORDZ128rr), XReg)
5664         .addReg(XReg, RegState::Undef)
5665         .addReg(XReg, RegState::Undef)
5666         .addReg(Reg, RegState::ImplicitDefine);
5667     MI.addRegisterKilled(Reg, TRI, true);
5668   } else if (X86::GR64RegClass.contains(Reg)) {
5669     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
5670     // as well.
5671     Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
5672     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
5673         .addReg(XReg, RegState::Undef)
5674         .addReg(XReg, RegState::Undef)
5675         .addReg(Reg, RegState::ImplicitDefine);
5676     MI.addRegisterKilled(Reg, TRI, true);
5677   } else if (X86::GR32RegClass.contains(Reg)) {
5678     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
5679         .addReg(Reg, RegState::Undef)
5680         .addReg(Reg, RegState::Undef);
5681     MI.addRegisterKilled(Reg, TRI, true);
5682   }
5683 }
5684 
5685 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5686                         int PtrOffset = 0) {
5687   unsigned NumAddrOps = MOs.size();
5688 
5689   if (NumAddrOps < 4) {
5690     // FrameIndex only - add an immediate offset (whether its zero or not).
5691     for (unsigned i = 0; i != NumAddrOps; ++i)
5692       MIB.add(MOs[i]);
5693     addOffset(MIB, PtrOffset);
5694   } else {
5695     // General Memory Addressing - we need to add any offset to an existing
5696     // offset.
5697     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5698     for (unsigned i = 0; i != NumAddrOps; ++i) {
5699       const MachineOperand &MO = MOs[i];
5700       if (i == 3 && PtrOffset != 0) {
5701         MIB.addDisp(MO, PtrOffset);
5702       } else {
5703         MIB.add(MO);
5704       }
5705     }
5706   }
5707 }
5708 
5709 static void updateOperandRegConstraints(MachineFunction &MF,
5710                                         MachineInstr &NewMI,
5711                                         const TargetInstrInfo &TII) {
5712   MachineRegisterInfo &MRI = MF.getRegInfo();
5713   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
5714 
5715   for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
5716     MachineOperand &MO = NewMI.getOperand(Idx);
5717     // We only need to update constraints on virtual register operands.
5718     if (!MO.isReg())
5719       continue;
5720     Register Reg = MO.getReg();
5721     if (!Reg.isVirtual())
5722       continue;
5723 
5724     auto *NewRC = MRI.constrainRegClass(
5725         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
5726     if (!NewRC) {
5727       LLVM_DEBUG(
5728           dbgs() << "WARNING: Unable to update register constraint for operand "
5729                  << Idx << " of instruction:\n";
5730           NewMI.dump(); dbgs() << "\n");
5731     }
5732   }
5733 }
5734 
5735 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5736                                      ArrayRef<MachineOperand> MOs,
5737                                      MachineBasicBlock::iterator InsertPt,
5738                                      MachineInstr &MI,
5739                                      const TargetInstrInfo &TII) {
5740   // Create the base instruction with the memory operand as the first part.
5741   // Omit the implicit operands, something BuildMI can't do.
5742   MachineInstr *NewMI =
5743       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5744   MachineInstrBuilder MIB(MF, NewMI);
5745   addOperands(MIB, MOs);
5746 
5747   // Loop over the rest of the ri operands, converting them over.
5748   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5749   for (unsigned i = 0; i != NumOps; ++i) {
5750     MachineOperand &MO = MI.getOperand(i + 2);
5751     MIB.add(MO);
5752   }
5753   for (const MachineOperand &MO : llvm::drop_begin(MI.operands(), NumOps + 2))
5754     MIB.add(MO);
5755 
5756   updateOperandRegConstraints(MF, *NewMI, TII);
5757 
5758   MachineBasicBlock *MBB = InsertPt->getParent();
5759   MBB->insert(InsertPt, NewMI);
5760 
5761   return MIB;
5762 }
5763 
5764 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5765                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5766                               MachineBasicBlock::iterator InsertPt,
5767                               MachineInstr &MI, const TargetInstrInfo &TII,
5768                               int PtrOffset = 0) {
5769   // Omit the implicit operands, something BuildMI can't do.
5770   MachineInstr *NewMI =
5771       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5772   MachineInstrBuilder MIB(MF, NewMI);
5773 
5774   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5775     MachineOperand &MO = MI.getOperand(i);
5776     if (i == OpNo) {
5777       assert(MO.isReg() && "Expected to fold into reg operand!");
5778       addOperands(MIB, MOs, PtrOffset);
5779     } else {
5780       MIB.add(MO);
5781     }
5782   }
5783 
5784   updateOperandRegConstraints(MF, *NewMI, TII);
5785 
5786   // Copy the NoFPExcept flag from the instruction we're fusing.
5787   if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
5788     NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
5789 
5790   MachineBasicBlock *MBB = InsertPt->getParent();
5791   MBB->insert(InsertPt, NewMI);
5792 
5793   return MIB;
5794 }
5795 
5796 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5797                                 ArrayRef<MachineOperand> MOs,
5798                                 MachineBasicBlock::iterator InsertPt,
5799                                 MachineInstr &MI) {
5800   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5801                                     MI.getDebugLoc(), TII.get(Opcode));
5802   addOperands(MIB, MOs);
5803   return MIB.addImm(0);
5804 }
5805 
5806 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5807     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5808     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5809     unsigned Size, Align Alignment) const {
5810   switch (MI.getOpcode()) {
5811   case X86::INSERTPSrr:
5812   case X86::VINSERTPSrr:
5813   case X86::VINSERTPSZrr:
5814     // Attempt to convert the load of inserted vector into a fold load
5815     // of a single float.
5816     if (OpNum == 2) {
5817       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5818       unsigned ZMask = Imm & 15;
5819       unsigned DstIdx = (Imm >> 4) & 3;
5820       unsigned SrcIdx = (Imm >> 6) & 3;
5821 
5822       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5823       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5824       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5825       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(4)) {
5826         int PtrOffset = SrcIdx * 4;
5827         unsigned NewImm = (DstIdx << 4) | ZMask;
5828         unsigned NewOpCode =
5829             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5830             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
5831                                                     X86::INSERTPSrm;
5832         MachineInstr *NewMI =
5833             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5834         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5835         return NewMI;
5836       }
5837     }
5838     break;
5839   case X86::MOVHLPSrr:
5840   case X86::VMOVHLPSrr:
5841   case X86::VMOVHLPSZrr:
5842     // Move the upper 64-bits of the second operand to the lower 64-bits.
5843     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5844     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5845     if (OpNum == 2) {
5846       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5847       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5848       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5849       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
5850         unsigned NewOpCode =
5851             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5852             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
5853                                                    X86::MOVLPSrm;
5854         MachineInstr *NewMI =
5855             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5856         return NewMI;
5857       }
5858     }
5859     break;
5860   case X86::UNPCKLPDrr:
5861     // If we won't be able to fold this to the memory form of UNPCKL, use
5862     // MOVHPD instead. Done as custom because we can't have this in the load
5863     // table twice.
5864     if (OpNum == 2) {
5865       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5866       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5867       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5868       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
5869         MachineInstr *NewMI =
5870             FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
5871         return NewMI;
5872       }
5873     }
5874     break;
5875   }
5876 
5877   return nullptr;
5878 }
5879 
5880 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
5881                                                MachineInstr &MI) {
5882   if (!hasUndefRegUpdate(MI.getOpcode(), 1, /*ForLoadFold*/true) ||
5883       !MI.getOperand(1).isReg())
5884     return false;
5885 
5886   // The are two cases we need to handle depending on where in the pipeline
5887   // the folding attempt is being made.
5888   // -Register has the undef flag set.
5889   // -Register is produced by the IMPLICIT_DEF instruction.
5890 
5891   if (MI.getOperand(1).isUndef())
5892     return true;
5893 
5894   MachineRegisterInfo &RegInfo = MF.getRegInfo();
5895   MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
5896   return VRegDef && VRegDef->isImplicitDef();
5897 }
5898 
5899 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5900     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5901     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5902     unsigned Size, Align Alignment, bool AllowCommute) const {
5903   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
5904   bool isTwoAddrFold = false;
5905 
5906   // For CPUs that favor the register form of a call or push,
5907   // do not fold loads into calls or pushes, unless optimizing for size
5908   // aggressively.
5909   if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
5910       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5911        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5912        MI.getOpcode() == X86::PUSH64r))
5913     return nullptr;
5914 
5915   // Avoid partial and undef register update stalls unless optimizing for size.
5916   if (!MF.getFunction().hasOptSize() &&
5917       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5918        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5919     return nullptr;
5920 
5921   unsigned NumOps = MI.getDesc().getNumOperands();
5922   bool isTwoAddr =
5923       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5924 
5925   // FIXME: AsmPrinter doesn't know how to handle
5926   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5927   if (MI.getOpcode() == X86::ADD32ri &&
5928       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5929     return nullptr;
5930 
5931   // GOTTPOFF relocation loads can only be folded into add instructions.
5932   // FIXME: Need to exclude other relocations that only support specific
5933   // instructions.
5934   if (MOs.size() == X86::AddrNumOperands &&
5935       MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
5936       MI.getOpcode() != X86::ADD64rr)
5937     return nullptr;
5938 
5939   MachineInstr *NewMI = nullptr;
5940 
5941   // Attempt to fold any custom cases we have.
5942   if (MachineInstr *CustomMI = foldMemoryOperandCustom(
5943           MF, MI, OpNum, MOs, InsertPt, Size, Alignment))
5944     return CustomMI;
5945 
5946   const X86MemoryFoldTableEntry *I = nullptr;
5947 
5948   // Folding a memory location into the two-address part of a two-address
5949   // instruction is different than folding it other places.  It requires
5950   // replacing the *two* registers with the memory location.
5951   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5952       MI.getOperand(1).isReg() &&
5953       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5954     I = lookupTwoAddrFoldTable(MI.getOpcode());
5955     isTwoAddrFold = true;
5956   } else {
5957     if (OpNum == 0) {
5958       if (MI.getOpcode() == X86::MOV32r0) {
5959         NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5960         if (NewMI)
5961           return NewMI;
5962       }
5963     }
5964 
5965     I = lookupFoldTable(MI.getOpcode(), OpNum);
5966   }
5967 
5968   if (I != nullptr) {
5969     unsigned Opcode = I->DstOp;
5970     bool FoldedLoad =
5971         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_LOAD) || OpNum > 0;
5972     bool FoldedStore =
5973         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_STORE);
5974     MaybeAlign MinAlign =
5975         decodeMaybeAlign((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT);
5976     if (MinAlign && Alignment < *MinAlign)
5977       return nullptr;
5978     bool NarrowToMOV32rm = false;
5979     if (Size) {
5980       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5981       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
5982                                                   &RI, MF);
5983       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5984       // Check if it's safe to fold the load. If the size of the object is
5985       // narrower than the load width, then it's not.
5986       // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
5987       if (FoldedLoad && Size < RCSize) {
5988         // If this is a 64-bit load, but the spill slot is 32, then we can do
5989         // a 32-bit load which is implicitly zero-extended. This likely is
5990         // due to live interval analysis remat'ing a load from stack slot.
5991         if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5992           return nullptr;
5993         if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5994           return nullptr;
5995         Opcode = X86::MOV32rm;
5996         NarrowToMOV32rm = true;
5997       }
5998       // For stores, make sure the size of the object is equal to the size of
5999       // the store. If the object is larger, the extra bits would be garbage. If
6000       // the object is smaller we might overwrite another object or fault.
6001       if (FoldedStore && Size != RCSize)
6002         return nullptr;
6003     }
6004 
6005     if (isTwoAddrFold)
6006       NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
6007     else
6008       NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
6009 
6010     if (NarrowToMOV32rm) {
6011       // If this is the special case where we use a MOV32rm to load a 32-bit
6012       // value and zero-extend the top bits. Change the destination register
6013       // to a 32-bit one.
6014       Register DstReg = NewMI->getOperand(0).getReg();
6015       if (DstReg.isPhysical())
6016         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
6017       else
6018         NewMI->getOperand(0).setSubReg(X86::sub_32bit);
6019     }
6020     return NewMI;
6021   }
6022 
6023   // If the instruction and target operand are commutable, commute the
6024   // instruction and try again.
6025   if (AllowCommute) {
6026     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
6027     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
6028       bool HasDef = MI.getDesc().getNumDefs();
6029       Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
6030       Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
6031       Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
6032       bool Tied1 =
6033           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
6034       bool Tied2 =
6035           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
6036 
6037       // If either of the commutable operands are tied to the destination
6038       // then we can not commute + fold.
6039       if ((HasDef && Reg0 == Reg1 && Tied1) ||
6040           (HasDef && Reg0 == Reg2 && Tied2))
6041         return nullptr;
6042 
6043       MachineInstr *CommutedMI =
6044           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
6045       if (!CommutedMI) {
6046         // Unable to commute.
6047         return nullptr;
6048       }
6049       if (CommutedMI != &MI) {
6050         // New instruction. We can't fold from this.
6051         CommutedMI->eraseFromParent();
6052         return nullptr;
6053       }
6054 
6055       // Attempt to fold with the commuted version of the instruction.
6056       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, Size,
6057                                     Alignment, /*AllowCommute=*/false);
6058       if (NewMI)
6059         return NewMI;
6060 
6061       // Folding failed again - undo the commute before returning.
6062       MachineInstr *UncommutedMI =
6063           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
6064       if (!UncommutedMI) {
6065         // Unable to commute.
6066         return nullptr;
6067       }
6068       if (UncommutedMI != &MI) {
6069         // New instruction. It doesn't need to be kept.
6070         UncommutedMI->eraseFromParent();
6071         return nullptr;
6072       }
6073 
6074       // Return here to prevent duplicate fuse failure report.
6075       return nullptr;
6076     }
6077   }
6078 
6079   // No fusion
6080   if (PrintFailedFusing && !MI.isCopy())
6081     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
6082   return nullptr;
6083 }
6084 
6085 MachineInstr *
6086 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
6087                                     ArrayRef<unsigned> Ops,
6088                                     MachineBasicBlock::iterator InsertPt,
6089                                     int FrameIndex, LiveIntervals *LIS,
6090                                     VirtRegMap *VRM) const {
6091   // Check switch flag
6092   if (NoFusing)
6093     return nullptr;
6094 
6095   // Avoid partial and undef register update stalls unless optimizing for size.
6096   if (!MF.getFunction().hasOptSize() &&
6097       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
6098        shouldPreventUndefRegUpdateMemFold(MF, MI)))
6099     return nullptr;
6100 
6101   // Don't fold subreg spills, or reloads that use a high subreg.
6102   for (auto Op : Ops) {
6103     MachineOperand &MO = MI.getOperand(Op);
6104     auto SubReg = MO.getSubReg();
6105     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
6106       return nullptr;
6107   }
6108 
6109   const MachineFrameInfo &MFI = MF.getFrameInfo();
6110   unsigned Size = MFI.getObjectSize(FrameIndex);
6111   Align Alignment = MFI.getObjectAlign(FrameIndex);
6112   // If the function stack isn't realigned we don't want to fold instructions
6113   // that need increased alignment.
6114   if (!RI.hasStackRealignment(MF))
6115     Alignment =
6116         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlign());
6117   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6118     unsigned NewOpc = 0;
6119     unsigned RCSize = 0;
6120     switch (MI.getOpcode()) {
6121     default: return nullptr;
6122     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
6123     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6124     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6125     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
6126     }
6127     // Check if it's safe to fold the load. If the size of the object is
6128     // narrower than the load width, then it's not.
6129     if (Size < RCSize)
6130       return nullptr;
6131     // Change to CMPXXri r, 0 first.
6132     MI.setDesc(get(NewOpc));
6133     MI.getOperand(1).ChangeToImmediate(0);
6134   } else if (Ops.size() != 1)
6135     return nullptr;
6136 
6137   return foldMemoryOperandImpl(MF, MI, Ops[0],
6138                                MachineOperand::CreateFI(FrameIndex), InsertPt,
6139                                Size, Alignment, /*AllowCommute=*/true);
6140 }
6141 
6142 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6143 /// because the latter uses contents that wouldn't be defined in the folded
6144 /// version.  For instance, this transformation isn't legal:
6145 ///   movss (%rdi), %xmm0
6146 ///   addps %xmm0, %xmm0
6147 /// ->
6148 ///   addps (%rdi), %xmm0
6149 ///
6150 /// But this one is:
6151 ///   movss (%rdi), %xmm0
6152 ///   addss %xmm0, %xmm0
6153 /// ->
6154 ///   addss (%rdi), %xmm0
6155 ///
6156 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6157                                              const MachineInstr &UserMI,
6158                                              const MachineFunction &MF) {
6159   unsigned Opc = LoadMI.getOpcode();
6160   unsigned UserOpc = UserMI.getOpcode();
6161   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6162   const TargetRegisterClass *RC =
6163       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
6164   unsigned RegSize = TRI.getRegSizeInBits(*RC);
6165 
6166   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
6167        Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
6168        Opc == X86::VMOVSSZrm_alt) &&
6169       RegSize > 32) {
6170     // These instructions only load 32 bits, we can't fold them if the
6171     // destination register is wider than 32 bits (4 bytes), and its user
6172     // instruction isn't scalar (SS).
6173     switch (UserOpc) {
6174     case X86::CVTSS2SDrr_Int:
6175     case X86::VCVTSS2SDrr_Int:
6176     case X86::VCVTSS2SDZrr_Int:
6177     case X86::VCVTSS2SDZrr_Intk:
6178     case X86::VCVTSS2SDZrr_Intkz:
6179     case X86::CVTSS2SIrr_Int:     case X86::CVTSS2SI64rr_Int:
6180     case X86::VCVTSS2SIrr_Int:    case X86::VCVTSS2SI64rr_Int:
6181     case X86::VCVTSS2SIZrr_Int:   case X86::VCVTSS2SI64Zrr_Int:
6182     case X86::CVTTSS2SIrr_Int:    case X86::CVTTSS2SI64rr_Int:
6183     case X86::VCVTTSS2SIrr_Int:   case X86::VCVTTSS2SI64rr_Int:
6184     case X86::VCVTTSS2SIZrr_Int:  case X86::VCVTTSS2SI64Zrr_Int:
6185     case X86::VCVTSS2USIZrr_Int:  case X86::VCVTSS2USI64Zrr_Int:
6186     case X86::VCVTTSS2USIZrr_Int: case X86::VCVTTSS2USI64Zrr_Int:
6187     case X86::RCPSSr_Int:   case X86::VRCPSSr_Int:
6188     case X86::RSQRTSSr_Int: case X86::VRSQRTSSr_Int:
6189     case X86::ROUNDSSr_Int: case X86::VROUNDSSr_Int:
6190     case X86::COMISSrr_Int: case X86::VCOMISSrr_Int: case X86::VCOMISSZrr_Int:
6191     case X86::UCOMISSrr_Int:case X86::VUCOMISSrr_Int:case X86::VUCOMISSZrr_Int:
6192     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
6193     case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
6194     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
6195     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
6196     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
6197     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
6198     case X86::SQRTSSr_Int: case X86::VSQRTSSr_Int: case X86::VSQRTSSZr_Int:
6199     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
6200     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
6201     case X86::VCMPSSZrr_Intk:
6202     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
6203     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
6204     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
6205     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
6206     case X86::VSQRTSSZr_Intk: case X86::VSQRTSSZr_Intkz:
6207     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
6208     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
6209     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
6210     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
6211     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
6212     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
6213     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
6214     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
6215     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
6216     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
6217     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
6218     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
6219     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
6220     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
6221     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
6222     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
6223     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
6224     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
6225     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
6226     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
6227     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
6228     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
6229     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
6230     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
6231     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
6232     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
6233     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
6234     case X86::VFIXUPIMMSSZrri:
6235     case X86::VFIXUPIMMSSZrrik:
6236     case X86::VFIXUPIMMSSZrrikz:
6237     case X86::VFPCLASSSSZrr:
6238     case X86::VFPCLASSSSZrrk:
6239     case X86::VGETEXPSSZr:
6240     case X86::VGETEXPSSZrk:
6241     case X86::VGETEXPSSZrkz:
6242     case X86::VGETMANTSSZrri:
6243     case X86::VGETMANTSSZrrik:
6244     case X86::VGETMANTSSZrrikz:
6245     case X86::VRANGESSZrri:
6246     case X86::VRANGESSZrrik:
6247     case X86::VRANGESSZrrikz:
6248     case X86::VRCP14SSZrr:
6249     case X86::VRCP14SSZrrk:
6250     case X86::VRCP14SSZrrkz:
6251     case X86::VRCP28SSZr:
6252     case X86::VRCP28SSZrk:
6253     case X86::VRCP28SSZrkz:
6254     case X86::VREDUCESSZrri:
6255     case X86::VREDUCESSZrrik:
6256     case X86::VREDUCESSZrrikz:
6257     case X86::VRNDSCALESSZr_Int:
6258     case X86::VRNDSCALESSZr_Intk:
6259     case X86::VRNDSCALESSZr_Intkz:
6260     case X86::VRSQRT14SSZrr:
6261     case X86::VRSQRT14SSZrrk:
6262     case X86::VRSQRT14SSZrrkz:
6263     case X86::VRSQRT28SSZr:
6264     case X86::VRSQRT28SSZrk:
6265     case X86::VRSQRT28SSZrkz:
6266     case X86::VSCALEFSSZrr:
6267     case X86::VSCALEFSSZrrk:
6268     case X86::VSCALEFSSZrrkz:
6269       return false;
6270     default:
6271       return true;
6272     }
6273   }
6274 
6275   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
6276        Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
6277        Opc == X86::VMOVSDZrm_alt) &&
6278       RegSize > 64) {
6279     // These instructions only load 64 bits, we can't fold them if the
6280     // destination register is wider than 64 bits (8 bytes), and its user
6281     // instruction isn't scalar (SD).
6282     switch (UserOpc) {
6283     case X86::CVTSD2SSrr_Int:
6284     case X86::VCVTSD2SSrr_Int:
6285     case X86::VCVTSD2SSZrr_Int:
6286     case X86::VCVTSD2SSZrr_Intk:
6287     case X86::VCVTSD2SSZrr_Intkz:
6288     case X86::CVTSD2SIrr_Int:     case X86::CVTSD2SI64rr_Int:
6289     case X86::VCVTSD2SIrr_Int:    case X86::VCVTSD2SI64rr_Int:
6290     case X86::VCVTSD2SIZrr_Int:   case X86::VCVTSD2SI64Zrr_Int:
6291     case X86::CVTTSD2SIrr_Int:    case X86::CVTTSD2SI64rr_Int:
6292     case X86::VCVTTSD2SIrr_Int:   case X86::VCVTTSD2SI64rr_Int:
6293     case X86::VCVTTSD2SIZrr_Int:  case X86::VCVTTSD2SI64Zrr_Int:
6294     case X86::VCVTSD2USIZrr_Int:  case X86::VCVTSD2USI64Zrr_Int:
6295     case X86::VCVTTSD2USIZrr_Int: case X86::VCVTTSD2USI64Zrr_Int:
6296     case X86::ROUNDSDr_Int: case X86::VROUNDSDr_Int:
6297     case X86::COMISDrr_Int: case X86::VCOMISDrr_Int: case X86::VCOMISDZrr_Int:
6298     case X86::UCOMISDrr_Int:case X86::VUCOMISDrr_Int:case X86::VUCOMISDZrr_Int:
6299     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
6300     case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
6301     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
6302     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
6303     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
6304     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
6305     case X86::SQRTSDr_Int: case X86::VSQRTSDr_Int: case X86::VSQRTSDZr_Int:
6306     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
6307     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
6308     case X86::VCMPSDZrr_Intk:
6309     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
6310     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
6311     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
6312     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
6313     case X86::VSQRTSDZr_Intk: case X86::VSQRTSDZr_Intkz:
6314     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
6315     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
6316     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
6317     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
6318     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
6319     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
6320     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
6321     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
6322     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
6323     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
6324     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
6325     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
6326     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
6327     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
6328     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
6329     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
6330     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
6331     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
6332     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
6333     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
6334     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
6335     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
6336     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
6337     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
6338     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
6339     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
6340     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
6341     case X86::VFIXUPIMMSDZrri:
6342     case X86::VFIXUPIMMSDZrrik:
6343     case X86::VFIXUPIMMSDZrrikz:
6344     case X86::VFPCLASSSDZrr:
6345     case X86::VFPCLASSSDZrrk:
6346     case X86::VGETEXPSDZr:
6347     case X86::VGETEXPSDZrk:
6348     case X86::VGETEXPSDZrkz:
6349     case X86::VGETMANTSDZrri:
6350     case X86::VGETMANTSDZrrik:
6351     case X86::VGETMANTSDZrrikz:
6352     case X86::VRANGESDZrri:
6353     case X86::VRANGESDZrrik:
6354     case X86::VRANGESDZrrikz:
6355     case X86::VRCP14SDZrr:
6356     case X86::VRCP14SDZrrk:
6357     case X86::VRCP14SDZrrkz:
6358     case X86::VRCP28SDZr:
6359     case X86::VRCP28SDZrk:
6360     case X86::VRCP28SDZrkz:
6361     case X86::VREDUCESDZrri:
6362     case X86::VREDUCESDZrrik:
6363     case X86::VREDUCESDZrrikz:
6364     case X86::VRNDSCALESDZr_Int:
6365     case X86::VRNDSCALESDZr_Intk:
6366     case X86::VRNDSCALESDZr_Intkz:
6367     case X86::VRSQRT14SDZrr:
6368     case X86::VRSQRT14SDZrrk:
6369     case X86::VRSQRT14SDZrrkz:
6370     case X86::VRSQRT28SDZr:
6371     case X86::VRSQRT28SDZrk:
6372     case X86::VRSQRT28SDZrkz:
6373     case X86::VSCALEFSDZrr:
6374     case X86::VSCALEFSDZrrk:
6375     case X86::VSCALEFSDZrrkz:
6376       return false;
6377     default:
6378       return true;
6379     }
6380   }
6381 
6382   if ((Opc == X86::VMOVSHZrm || Opc == X86::VMOVSHZrm_alt) && RegSize > 16) {
6383     // These instructions only load 16 bits, we can't fold them if the
6384     // destination register is wider than 16 bits (2 bytes), and its user
6385     // instruction isn't scalar (SH).
6386     switch (UserOpc) {
6387     case X86::VADDSHZrr_Int:
6388     case X86::VCMPSHZrr_Int:
6389     case X86::VDIVSHZrr_Int:
6390     case X86::VMAXSHZrr_Int:
6391     case X86::VMINSHZrr_Int:
6392     case X86::VMULSHZrr_Int:
6393     case X86::VSUBSHZrr_Int:
6394     case X86::VADDSHZrr_Intk: case X86::VADDSHZrr_Intkz:
6395     case X86::VCMPSHZrr_Intk:
6396     case X86::VDIVSHZrr_Intk: case X86::VDIVSHZrr_Intkz:
6397     case X86::VMAXSHZrr_Intk: case X86::VMAXSHZrr_Intkz:
6398     case X86::VMINSHZrr_Intk: case X86::VMINSHZrr_Intkz:
6399     case X86::VMULSHZrr_Intk: case X86::VMULSHZrr_Intkz:
6400     case X86::VSUBSHZrr_Intk: case X86::VSUBSHZrr_Intkz:
6401     case X86::VFMADD132SHZr_Int: case X86::VFNMADD132SHZr_Int:
6402     case X86::VFMADD213SHZr_Int: case X86::VFNMADD213SHZr_Int:
6403     case X86::VFMADD231SHZr_Int: case X86::VFNMADD231SHZr_Int:
6404     case X86::VFMSUB132SHZr_Int: case X86::VFNMSUB132SHZr_Int:
6405     case X86::VFMSUB213SHZr_Int: case X86::VFNMSUB213SHZr_Int:
6406     case X86::VFMSUB231SHZr_Int: case X86::VFNMSUB231SHZr_Int:
6407     case X86::VFMADD132SHZr_Intk: case X86::VFNMADD132SHZr_Intk:
6408     case X86::VFMADD213SHZr_Intk: case X86::VFNMADD213SHZr_Intk:
6409     case X86::VFMADD231SHZr_Intk: case X86::VFNMADD231SHZr_Intk:
6410     case X86::VFMSUB132SHZr_Intk: case X86::VFNMSUB132SHZr_Intk:
6411     case X86::VFMSUB213SHZr_Intk: case X86::VFNMSUB213SHZr_Intk:
6412     case X86::VFMSUB231SHZr_Intk: case X86::VFNMSUB231SHZr_Intk:
6413     case X86::VFMADD132SHZr_Intkz: case X86::VFNMADD132SHZr_Intkz:
6414     case X86::VFMADD213SHZr_Intkz: case X86::VFNMADD213SHZr_Intkz:
6415     case X86::VFMADD231SHZr_Intkz: case X86::VFNMADD231SHZr_Intkz:
6416     case X86::VFMSUB132SHZr_Intkz: case X86::VFNMSUB132SHZr_Intkz:
6417     case X86::VFMSUB213SHZr_Intkz: case X86::VFNMSUB213SHZr_Intkz:
6418     case X86::VFMSUB231SHZr_Intkz: case X86::VFNMSUB231SHZr_Intkz:
6419       return false;
6420     default:
6421       return true;
6422     }
6423   }
6424 
6425   return false;
6426 }
6427 
6428 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6429     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6430     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
6431     LiveIntervals *LIS) const {
6432 
6433   // TODO: Support the case where LoadMI loads a wide register, but MI
6434   // only uses a subreg.
6435   for (auto Op : Ops) {
6436     if (MI.getOperand(Op).getSubReg())
6437       return nullptr;
6438   }
6439 
6440   // If loading from a FrameIndex, fold directly from the FrameIndex.
6441   unsigned NumOps = LoadMI.getDesc().getNumOperands();
6442   int FrameIndex;
6443   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6444     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6445       return nullptr;
6446     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
6447   }
6448 
6449   // Check switch flag
6450   if (NoFusing) return nullptr;
6451 
6452   // Avoid partial and undef register update stalls unless optimizing for size.
6453   if (!MF.getFunction().hasOptSize() &&
6454       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
6455        shouldPreventUndefRegUpdateMemFold(MF, MI)))
6456     return nullptr;
6457 
6458   // Determine the alignment of the load.
6459   Align Alignment;
6460   if (LoadMI.hasOneMemOperand())
6461     Alignment = (*LoadMI.memoperands_begin())->getAlign();
6462   else
6463     switch (LoadMI.getOpcode()) {
6464     case X86::AVX512_512_SET0:
6465     case X86::AVX512_512_SETALLONES:
6466       Alignment = Align(64);
6467       break;
6468     case X86::AVX2_SETALLONES:
6469     case X86::AVX1_SETALLONES:
6470     case X86::AVX_SET0:
6471     case X86::AVX512_256_SET0:
6472       Alignment = Align(32);
6473       break;
6474     case X86::V_SET0:
6475     case X86::V_SETALLONES:
6476     case X86::AVX512_128_SET0:
6477     case X86::FsFLD0F128:
6478     case X86::AVX512_FsFLD0F128:
6479       Alignment = Align(16);
6480       break;
6481     case X86::MMX_SET0:
6482     case X86::FsFLD0SD:
6483     case X86::AVX512_FsFLD0SD:
6484       Alignment = Align(8);
6485       break;
6486     case X86::FsFLD0SS:
6487     case X86::AVX512_FsFLD0SS:
6488       Alignment = Align(4);
6489       break;
6490     case X86::AVX512_FsFLD0SH:
6491       Alignment = Align(2);
6492       break;
6493     default:
6494       return nullptr;
6495     }
6496   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6497     unsigned NewOpc = 0;
6498     switch (MI.getOpcode()) {
6499     default: return nullptr;
6500     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6501     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6502     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6503     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6504     }
6505     // Change to CMPXXri r, 0 first.
6506     MI.setDesc(get(NewOpc));
6507     MI.getOperand(1).ChangeToImmediate(0);
6508   } else if (Ops.size() != 1)
6509     return nullptr;
6510 
6511   // Make sure the subregisters match.
6512   // Otherwise we risk changing the size of the load.
6513   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6514     return nullptr;
6515 
6516   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6517   switch (LoadMI.getOpcode()) {
6518   case X86::MMX_SET0:
6519   case X86::V_SET0:
6520   case X86::V_SETALLONES:
6521   case X86::AVX2_SETALLONES:
6522   case X86::AVX1_SETALLONES:
6523   case X86::AVX_SET0:
6524   case X86::AVX512_128_SET0:
6525   case X86::AVX512_256_SET0:
6526   case X86::AVX512_512_SET0:
6527   case X86::AVX512_512_SETALLONES:
6528   case X86::AVX512_FsFLD0SH:
6529   case X86::FsFLD0SD:
6530   case X86::AVX512_FsFLD0SD:
6531   case X86::FsFLD0SS:
6532   case X86::AVX512_FsFLD0SS:
6533   case X86::FsFLD0F128:
6534   case X86::AVX512_FsFLD0F128: {
6535     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6536     // Create a constant-pool entry and operands to load from it.
6537 
6538     // Medium and large mode can't fold loads this way.
6539     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6540         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6541       return nullptr;
6542 
6543     // x86-32 PIC requires a PIC base register for constant pools.
6544     unsigned PICBase = 0;
6545     // Since we're using Small or Kernel code model, we can always use
6546     // RIP-relative addressing for a smaller encoding.
6547     if (Subtarget.is64Bit()) {
6548       PICBase = X86::RIP;
6549     } else if (MF.getTarget().isPositionIndependent()) {
6550       // FIXME: PICBase = getGlobalBaseReg(&MF);
6551       // This doesn't work for several reasons.
6552       // 1. GlobalBaseReg may have been spilled.
6553       // 2. It may not be live at MI.
6554       return nullptr;
6555     }
6556 
6557     // Create a constant-pool entry.
6558     MachineConstantPool &MCP = *MF.getConstantPool();
6559     Type *Ty;
6560     unsigned Opc = LoadMI.getOpcode();
6561     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
6562       Ty = Type::getFloatTy(MF.getFunction().getContext());
6563     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
6564       Ty = Type::getDoubleTy(MF.getFunction().getContext());
6565     else if (Opc == X86::FsFLD0F128 || Opc == X86::AVX512_FsFLD0F128)
6566       Ty = Type::getFP128Ty(MF.getFunction().getContext());
6567     else if (Opc == X86::AVX512_FsFLD0SH)
6568       Ty = Type::getHalfTy(MF.getFunction().getContext());
6569     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
6570       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6571                                 16);
6572     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6573              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
6574       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6575                                 8);
6576     else if (Opc == X86::MMX_SET0)
6577       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6578                                 2);
6579     else
6580       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6581                                 4);
6582 
6583     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6584                       Opc == X86::AVX512_512_SETALLONES ||
6585                       Opc == X86::AVX1_SETALLONES);
6586     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6587                                     Constant::getNullValue(Ty);
6588     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6589 
6590     // Create operands to load from the constant pool entry.
6591     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6592     MOs.push_back(MachineOperand::CreateImm(1));
6593     MOs.push_back(MachineOperand::CreateReg(0, false));
6594     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6595     MOs.push_back(MachineOperand::CreateReg(0, false));
6596     break;
6597   }
6598   default: {
6599     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6600       return nullptr;
6601 
6602     // Folding a normal load. Just copy the load's address operands.
6603     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6604                LoadMI.operands_begin() + NumOps);
6605     break;
6606   }
6607   }
6608   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6609                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6610 }
6611 
6612 static SmallVector<MachineMemOperand *, 2>
6613 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6614   SmallVector<MachineMemOperand *, 2> LoadMMOs;
6615 
6616   for (MachineMemOperand *MMO : MMOs) {
6617     if (!MMO->isLoad())
6618       continue;
6619 
6620     if (!MMO->isStore()) {
6621       // Reuse the MMO.
6622       LoadMMOs.push_back(MMO);
6623     } else {
6624       // Clone the MMO and unset the store flag.
6625       LoadMMOs.push_back(MF.getMachineMemOperand(
6626           MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
6627     }
6628   }
6629 
6630   return LoadMMOs;
6631 }
6632 
6633 static SmallVector<MachineMemOperand *, 2>
6634 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6635   SmallVector<MachineMemOperand *, 2> StoreMMOs;
6636 
6637   for (MachineMemOperand *MMO : MMOs) {
6638     if (!MMO->isStore())
6639       continue;
6640 
6641     if (!MMO->isLoad()) {
6642       // Reuse the MMO.
6643       StoreMMOs.push_back(MMO);
6644     } else {
6645       // Clone the MMO and unset the load flag.
6646       StoreMMOs.push_back(MF.getMachineMemOperand(
6647           MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
6648     }
6649   }
6650 
6651   return StoreMMOs;
6652 }
6653 
6654 static unsigned getBroadcastOpcode(const X86MemoryFoldTableEntry *I,
6655                                    const TargetRegisterClass *RC,
6656                                    const X86Subtarget &STI) {
6657   assert(STI.hasAVX512() && "Expected at least AVX512!");
6658   unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
6659   assert((SpillSize == 64 || STI.hasVLX()) &&
6660          "Can't broadcast less than 64 bytes without AVX512VL!");
6661 
6662   switch (I->Flags & TB_BCAST_MASK) {
6663   default: llvm_unreachable("Unexpected broadcast type!");
6664   case TB_BCAST_D:
6665     switch (SpillSize) {
6666     default: llvm_unreachable("Unknown spill size");
6667     case 16: return X86::VPBROADCASTDZ128rm;
6668     case 32: return X86::VPBROADCASTDZ256rm;
6669     case 64: return X86::VPBROADCASTDZrm;
6670     }
6671     break;
6672   case TB_BCAST_Q:
6673     switch (SpillSize) {
6674     default: llvm_unreachable("Unknown spill size");
6675     case 16: return X86::VPBROADCASTQZ128rm;
6676     case 32: return X86::VPBROADCASTQZ256rm;
6677     case 64: return X86::VPBROADCASTQZrm;
6678     }
6679     break;
6680   case TB_BCAST_SS:
6681     switch (SpillSize) {
6682     default: llvm_unreachable("Unknown spill size");
6683     case 16: return X86::VBROADCASTSSZ128rm;
6684     case 32: return X86::VBROADCASTSSZ256rm;
6685     case 64: return X86::VBROADCASTSSZrm;
6686     }
6687     break;
6688   case TB_BCAST_SD:
6689     switch (SpillSize) {
6690     default: llvm_unreachable("Unknown spill size");
6691     case 16: return X86::VMOVDDUPZ128rm;
6692     case 32: return X86::VBROADCASTSDZ256rm;
6693     case 64: return X86::VBROADCASTSDZrm;
6694     }
6695     break;
6696   }
6697 }
6698 
6699 bool X86InstrInfo::unfoldMemoryOperand(
6700     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6701     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6702   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
6703   if (I == nullptr)
6704     return false;
6705   unsigned Opc = I->DstOp;
6706   unsigned Index = I->Flags & TB_INDEX_MASK;
6707   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6708   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6709   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6710   if (UnfoldLoad && !FoldedLoad)
6711     return false;
6712   UnfoldLoad &= FoldedLoad;
6713   if (UnfoldStore && !FoldedStore)
6714     return false;
6715   UnfoldStore &= FoldedStore;
6716 
6717   const MCInstrDesc &MCID = get(Opc);
6718 
6719   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6720   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6721   // TODO: Check if 32-byte or greater accesses are slow too?
6722   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
6723       Subtarget.isUnalignedMem16Slow())
6724     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6725     // conservatively assume the address is unaligned. That's bad for
6726     // performance.
6727     return false;
6728   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6729   SmallVector<MachineOperand,2> BeforeOps;
6730   SmallVector<MachineOperand,2> AfterOps;
6731   SmallVector<MachineOperand,4> ImpOps;
6732   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6733     MachineOperand &Op = MI.getOperand(i);
6734     if (i >= Index && i < Index + X86::AddrNumOperands)
6735       AddrOps.push_back(Op);
6736     else if (Op.isReg() && Op.isImplicit())
6737       ImpOps.push_back(Op);
6738     else if (i < Index)
6739       BeforeOps.push_back(Op);
6740     else if (i > Index)
6741       AfterOps.push_back(Op);
6742   }
6743 
6744   // Emit the load or broadcast instruction.
6745   if (UnfoldLoad) {
6746     auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
6747 
6748     unsigned Opc;
6749     if (FoldedBCast) {
6750       Opc = getBroadcastOpcode(I, RC, Subtarget);
6751     } else {
6752       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6753       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6754       Opc = getLoadRegOpcode(Reg, RC, isAligned, Subtarget);
6755     }
6756 
6757     DebugLoc DL;
6758     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
6759     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6760       MIB.add(AddrOps[i]);
6761     MIB.setMemRefs(MMOs);
6762     NewMIs.push_back(MIB);
6763 
6764     if (UnfoldStore) {
6765       // Address operands cannot be marked isKill.
6766       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6767         MachineOperand &MO = NewMIs[0]->getOperand(i);
6768         if (MO.isReg())
6769           MO.setIsKill(false);
6770       }
6771     }
6772   }
6773 
6774   // Emit the data processing instruction.
6775   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
6776   MachineInstrBuilder MIB(MF, DataMI);
6777 
6778   if (FoldedStore)
6779     MIB.addReg(Reg, RegState::Define);
6780   for (MachineOperand &BeforeOp : BeforeOps)
6781     MIB.add(BeforeOp);
6782   if (FoldedLoad)
6783     MIB.addReg(Reg);
6784   for (MachineOperand &AfterOp : AfterOps)
6785     MIB.add(AfterOp);
6786   for (MachineOperand &ImpOp : ImpOps) {
6787     MIB.addReg(ImpOp.getReg(),
6788                getDefRegState(ImpOp.isDef()) |
6789                RegState::Implicit |
6790                getKillRegState(ImpOp.isKill()) |
6791                getDeadRegState(ImpOp.isDead()) |
6792                getUndefRegState(ImpOp.isUndef()));
6793   }
6794   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6795   switch (DataMI->getOpcode()) {
6796   default: break;
6797   case X86::CMP64ri32:
6798   case X86::CMP64ri8:
6799   case X86::CMP32ri:
6800   case X86::CMP32ri8:
6801   case X86::CMP16ri:
6802   case X86::CMP16ri8:
6803   case X86::CMP8ri: {
6804     MachineOperand &MO0 = DataMI->getOperand(0);
6805     MachineOperand &MO1 = DataMI->getOperand(1);
6806     if (MO1.isImm() && MO1.getImm() == 0) {
6807       unsigned NewOpc;
6808       switch (DataMI->getOpcode()) {
6809       default: llvm_unreachable("Unreachable!");
6810       case X86::CMP64ri8:
6811       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6812       case X86::CMP32ri8:
6813       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6814       case X86::CMP16ri8:
6815       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6816       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6817       }
6818       DataMI->setDesc(get(NewOpc));
6819       MO1.ChangeToRegister(MO0.getReg(), false);
6820     }
6821   }
6822   }
6823   NewMIs.push_back(DataMI);
6824 
6825   // Emit the store instruction.
6826   if (UnfoldStore) {
6827     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6828     auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
6829     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16);
6830     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6831     unsigned Opc = getStoreRegOpcode(Reg, DstRC, isAligned, Subtarget);
6832     DebugLoc DL;
6833     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6834     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6835       MIB.add(AddrOps[i]);
6836     MIB.addReg(Reg, RegState::Kill);
6837     MIB.setMemRefs(MMOs);
6838     NewMIs.push_back(MIB);
6839   }
6840 
6841   return true;
6842 }
6843 
6844 bool
6845 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6846                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6847   if (!N->isMachineOpcode())
6848     return false;
6849 
6850   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
6851   if (I == nullptr)
6852     return false;
6853   unsigned Opc = I->DstOp;
6854   unsigned Index = I->Flags & TB_INDEX_MASK;
6855   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6856   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6857   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6858   const MCInstrDesc &MCID = get(Opc);
6859   MachineFunction &MF = DAG.getMachineFunction();
6860   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6861   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6862   unsigned NumDefs = MCID.NumDefs;
6863   std::vector<SDValue> AddrOps;
6864   std::vector<SDValue> BeforeOps;
6865   std::vector<SDValue> AfterOps;
6866   SDLoc dl(N);
6867   unsigned NumOps = N->getNumOperands();
6868   for (unsigned i = 0; i != NumOps-1; ++i) {
6869     SDValue Op = N->getOperand(i);
6870     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6871       AddrOps.push_back(Op);
6872     else if (i < Index-NumDefs)
6873       BeforeOps.push_back(Op);
6874     else if (i > Index-NumDefs)
6875       AfterOps.push_back(Op);
6876   }
6877   SDValue Chain = N->getOperand(NumOps-1);
6878   AddrOps.push_back(Chain);
6879 
6880   // Emit the load instruction.
6881   SDNode *Load = nullptr;
6882   if (FoldedLoad) {
6883     EVT VT = *TRI.legalclasstypes_begin(*RC);
6884     auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6885     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6886         Subtarget.isUnalignedMem16Slow())
6887       // Do not introduce a slow unaligned load.
6888       return false;
6889     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6890     // memory access is slow above.
6891 
6892     unsigned Opc;
6893     if (FoldedBCast) {
6894       Opc = getBroadcastOpcode(I, RC, Subtarget);
6895     } else {
6896       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6897       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6898       Opc = getLoadRegOpcode(0, RC, isAligned, Subtarget);
6899     }
6900 
6901     Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
6902     NewNodes.push_back(Load);
6903 
6904     // Preserve memory reference information.
6905     DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
6906   }
6907 
6908   // Emit the data processing instruction.
6909   std::vector<EVT> VTs;
6910   const TargetRegisterClass *DstRC = nullptr;
6911   if (MCID.getNumDefs() > 0) {
6912     DstRC = getRegClass(MCID, 0, &RI, MF);
6913     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
6914   }
6915   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6916     EVT VT = N->getValueType(i);
6917     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6918       VTs.push_back(VT);
6919   }
6920   if (Load)
6921     BeforeOps.push_back(SDValue(Load, 0));
6922   llvm::append_range(BeforeOps, AfterOps);
6923   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6924   switch (Opc) {
6925     default: break;
6926     case X86::CMP64ri32:
6927     case X86::CMP64ri8:
6928     case X86::CMP32ri:
6929     case X86::CMP32ri8:
6930     case X86::CMP16ri:
6931     case X86::CMP16ri8:
6932     case X86::CMP8ri:
6933       if (isNullConstant(BeforeOps[1])) {
6934         switch (Opc) {
6935           default: llvm_unreachable("Unreachable!");
6936           case X86::CMP64ri8:
6937           case X86::CMP64ri32: Opc = X86::TEST64rr; break;
6938           case X86::CMP32ri8:
6939           case X86::CMP32ri:   Opc = X86::TEST32rr; break;
6940           case X86::CMP16ri8:
6941           case X86::CMP16ri:   Opc = X86::TEST16rr; break;
6942           case X86::CMP8ri:    Opc = X86::TEST8rr; break;
6943         }
6944         BeforeOps[1] = BeforeOps[0];
6945       }
6946   }
6947   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6948   NewNodes.push_back(NewNode);
6949 
6950   // Emit the store instruction.
6951   if (FoldedStore) {
6952     AddrOps.pop_back();
6953     AddrOps.push_back(SDValue(NewNode, 0));
6954     AddrOps.push_back(Chain);
6955     auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6956     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6957         Subtarget.isUnalignedMem16Slow())
6958       // Do not introduce a slow unaligned store.
6959       return false;
6960     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6961     // memory access is slow above.
6962     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6963     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6964     SDNode *Store =
6965         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6966                            dl, MVT::Other, AddrOps);
6967     NewNodes.push_back(Store);
6968 
6969     // Preserve memory reference information.
6970     DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
6971   }
6972 
6973   return true;
6974 }
6975 
6976 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6977                                       bool UnfoldLoad, bool UnfoldStore,
6978                                       unsigned *LoadRegIndex) const {
6979   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
6980   if (I == nullptr)
6981     return 0;
6982   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6983   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6984   if (UnfoldLoad && !FoldedLoad)
6985     return 0;
6986   if (UnfoldStore && !FoldedStore)
6987     return 0;
6988   if (LoadRegIndex)
6989     *LoadRegIndex = I->Flags & TB_INDEX_MASK;
6990   return I->DstOp;
6991 }
6992 
6993 bool
6994 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6995                                      int64_t &Offset1, int64_t &Offset2) const {
6996   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6997     return false;
6998   unsigned Opc1 = Load1->getMachineOpcode();
6999   unsigned Opc2 = Load2->getMachineOpcode();
7000   switch (Opc1) {
7001   default: return false;
7002   case X86::MOV8rm:
7003   case X86::MOV16rm:
7004   case X86::MOV32rm:
7005   case X86::MOV64rm:
7006   case X86::LD_Fp32m:
7007   case X86::LD_Fp64m:
7008   case X86::LD_Fp80m:
7009   case X86::MOVSSrm:
7010   case X86::MOVSSrm_alt:
7011   case X86::MOVSDrm:
7012   case X86::MOVSDrm_alt:
7013   case X86::MMX_MOVD64rm:
7014   case X86::MMX_MOVQ64rm:
7015   case X86::MOVAPSrm:
7016   case X86::MOVUPSrm:
7017   case X86::MOVAPDrm:
7018   case X86::MOVUPDrm:
7019   case X86::MOVDQArm:
7020   case X86::MOVDQUrm:
7021   // AVX load instructions
7022   case X86::VMOVSSrm:
7023   case X86::VMOVSSrm_alt:
7024   case X86::VMOVSDrm:
7025   case X86::VMOVSDrm_alt:
7026   case X86::VMOVAPSrm:
7027   case X86::VMOVUPSrm:
7028   case X86::VMOVAPDrm:
7029   case X86::VMOVUPDrm:
7030   case X86::VMOVDQArm:
7031   case X86::VMOVDQUrm:
7032   case X86::VMOVAPSYrm:
7033   case X86::VMOVUPSYrm:
7034   case X86::VMOVAPDYrm:
7035   case X86::VMOVUPDYrm:
7036   case X86::VMOVDQAYrm:
7037   case X86::VMOVDQUYrm:
7038   // AVX512 load instructions
7039   case X86::VMOVSSZrm:
7040   case X86::VMOVSSZrm_alt:
7041   case X86::VMOVSDZrm:
7042   case X86::VMOVSDZrm_alt:
7043   case X86::VMOVAPSZ128rm:
7044   case X86::VMOVUPSZ128rm:
7045   case X86::VMOVAPSZ128rm_NOVLX:
7046   case X86::VMOVUPSZ128rm_NOVLX:
7047   case X86::VMOVAPDZ128rm:
7048   case X86::VMOVUPDZ128rm:
7049   case X86::VMOVDQU8Z128rm:
7050   case X86::VMOVDQU16Z128rm:
7051   case X86::VMOVDQA32Z128rm:
7052   case X86::VMOVDQU32Z128rm:
7053   case X86::VMOVDQA64Z128rm:
7054   case X86::VMOVDQU64Z128rm:
7055   case X86::VMOVAPSZ256rm:
7056   case X86::VMOVUPSZ256rm:
7057   case X86::VMOVAPSZ256rm_NOVLX:
7058   case X86::VMOVUPSZ256rm_NOVLX:
7059   case X86::VMOVAPDZ256rm:
7060   case X86::VMOVUPDZ256rm:
7061   case X86::VMOVDQU8Z256rm:
7062   case X86::VMOVDQU16Z256rm:
7063   case X86::VMOVDQA32Z256rm:
7064   case X86::VMOVDQU32Z256rm:
7065   case X86::VMOVDQA64Z256rm:
7066   case X86::VMOVDQU64Z256rm:
7067   case X86::VMOVAPSZrm:
7068   case X86::VMOVUPSZrm:
7069   case X86::VMOVAPDZrm:
7070   case X86::VMOVUPDZrm:
7071   case X86::VMOVDQU8Zrm:
7072   case X86::VMOVDQU16Zrm:
7073   case X86::VMOVDQA32Zrm:
7074   case X86::VMOVDQU32Zrm:
7075   case X86::VMOVDQA64Zrm:
7076   case X86::VMOVDQU64Zrm:
7077   case X86::KMOVBkm:
7078   case X86::KMOVWkm:
7079   case X86::KMOVDkm:
7080   case X86::KMOVQkm:
7081     break;
7082   }
7083   switch (Opc2) {
7084   default: return false;
7085   case X86::MOV8rm:
7086   case X86::MOV16rm:
7087   case X86::MOV32rm:
7088   case X86::MOV64rm:
7089   case X86::LD_Fp32m:
7090   case X86::LD_Fp64m:
7091   case X86::LD_Fp80m:
7092   case X86::MOVSSrm:
7093   case X86::MOVSSrm_alt:
7094   case X86::MOVSDrm:
7095   case X86::MOVSDrm_alt:
7096   case X86::MMX_MOVD64rm:
7097   case X86::MMX_MOVQ64rm:
7098   case X86::MOVAPSrm:
7099   case X86::MOVUPSrm:
7100   case X86::MOVAPDrm:
7101   case X86::MOVUPDrm:
7102   case X86::MOVDQArm:
7103   case X86::MOVDQUrm:
7104   // AVX load instructions
7105   case X86::VMOVSSrm:
7106   case X86::VMOVSSrm_alt:
7107   case X86::VMOVSDrm:
7108   case X86::VMOVSDrm_alt:
7109   case X86::VMOVAPSrm:
7110   case X86::VMOVUPSrm:
7111   case X86::VMOVAPDrm:
7112   case X86::VMOVUPDrm:
7113   case X86::VMOVDQArm:
7114   case X86::VMOVDQUrm:
7115   case X86::VMOVAPSYrm:
7116   case X86::VMOVUPSYrm:
7117   case X86::VMOVAPDYrm:
7118   case X86::VMOVUPDYrm:
7119   case X86::VMOVDQAYrm:
7120   case X86::VMOVDQUYrm:
7121   // AVX512 load instructions
7122   case X86::VMOVSSZrm:
7123   case X86::VMOVSSZrm_alt:
7124   case X86::VMOVSDZrm:
7125   case X86::VMOVSDZrm_alt:
7126   case X86::VMOVAPSZ128rm:
7127   case X86::VMOVUPSZ128rm:
7128   case X86::VMOVAPSZ128rm_NOVLX:
7129   case X86::VMOVUPSZ128rm_NOVLX:
7130   case X86::VMOVAPDZ128rm:
7131   case X86::VMOVUPDZ128rm:
7132   case X86::VMOVDQU8Z128rm:
7133   case X86::VMOVDQU16Z128rm:
7134   case X86::VMOVDQA32Z128rm:
7135   case X86::VMOVDQU32Z128rm:
7136   case X86::VMOVDQA64Z128rm:
7137   case X86::VMOVDQU64Z128rm:
7138   case X86::VMOVAPSZ256rm:
7139   case X86::VMOVUPSZ256rm:
7140   case X86::VMOVAPSZ256rm_NOVLX:
7141   case X86::VMOVUPSZ256rm_NOVLX:
7142   case X86::VMOVAPDZ256rm:
7143   case X86::VMOVUPDZ256rm:
7144   case X86::VMOVDQU8Z256rm:
7145   case X86::VMOVDQU16Z256rm:
7146   case X86::VMOVDQA32Z256rm:
7147   case X86::VMOVDQU32Z256rm:
7148   case X86::VMOVDQA64Z256rm:
7149   case X86::VMOVDQU64Z256rm:
7150   case X86::VMOVAPSZrm:
7151   case X86::VMOVUPSZrm:
7152   case X86::VMOVAPDZrm:
7153   case X86::VMOVUPDZrm:
7154   case X86::VMOVDQU8Zrm:
7155   case X86::VMOVDQU16Zrm:
7156   case X86::VMOVDQA32Zrm:
7157   case X86::VMOVDQU32Zrm:
7158   case X86::VMOVDQA64Zrm:
7159   case X86::VMOVDQU64Zrm:
7160   case X86::KMOVBkm:
7161   case X86::KMOVWkm:
7162   case X86::KMOVDkm:
7163   case X86::KMOVQkm:
7164     break;
7165   }
7166 
7167   // Lambda to check if both the loads have the same value for an operand index.
7168   auto HasSameOp = [&](int I) {
7169     return Load1->getOperand(I) == Load2->getOperand(I);
7170   };
7171 
7172   // All operands except the displacement should match.
7173   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
7174       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
7175     return false;
7176 
7177   // Chain Operand must be the same.
7178   if (!HasSameOp(5))
7179     return false;
7180 
7181   // Now let's examine if the displacements are constants.
7182   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
7183   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
7184   if (!Disp1 || !Disp2)
7185     return false;
7186 
7187   Offset1 = Disp1->getSExtValue();
7188   Offset2 = Disp2->getSExtValue();
7189   return true;
7190 }
7191 
7192 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
7193                                            int64_t Offset1, int64_t Offset2,
7194                                            unsigned NumLoads) const {
7195   assert(Offset2 > Offset1);
7196   if ((Offset2 - Offset1) / 8 > 64)
7197     return false;
7198 
7199   unsigned Opc1 = Load1->getMachineOpcode();
7200   unsigned Opc2 = Load2->getMachineOpcode();
7201   if (Opc1 != Opc2)
7202     return false;  // FIXME: overly conservative?
7203 
7204   switch (Opc1) {
7205   default: break;
7206   case X86::LD_Fp32m:
7207   case X86::LD_Fp64m:
7208   case X86::LD_Fp80m:
7209   case X86::MMX_MOVD64rm:
7210   case X86::MMX_MOVQ64rm:
7211     return false;
7212   }
7213 
7214   EVT VT = Load1->getValueType(0);
7215   switch (VT.getSimpleVT().SimpleTy) {
7216   default:
7217     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
7218     // have 16 of them to play with.
7219     if (Subtarget.is64Bit()) {
7220       if (NumLoads >= 3)
7221         return false;
7222     } else if (NumLoads) {
7223       return false;
7224     }
7225     break;
7226   case MVT::i8:
7227   case MVT::i16:
7228   case MVT::i32:
7229   case MVT::i64:
7230   case MVT::f32:
7231   case MVT::f64:
7232     if (NumLoads)
7233       return false;
7234     break;
7235   }
7236 
7237   return true;
7238 }
7239 
7240 bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
7241                                         const MachineBasicBlock *MBB,
7242                                         const MachineFunction &MF) const {
7243 
7244   // ENDBR instructions should not be scheduled around.
7245   unsigned Opcode = MI.getOpcode();
7246   if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32 ||
7247       Opcode == X86::LDTILECFG)
7248     return true;
7249 
7250   return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
7251 }
7252 
7253 bool X86InstrInfo::
7254 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
7255   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
7256   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
7257   Cond[0].setImm(GetOppositeBranchCondition(CC));
7258   return false;
7259 }
7260 
7261 bool X86InstrInfo::
7262 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
7263   // FIXME: Return false for x87 stack register classes for now. We can't
7264   // allow any loads of these registers before FpGet_ST0_80.
7265   return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
7266            RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
7267            RC == &X86::RFP80RegClass);
7268 }
7269 
7270 /// Return a virtual register initialized with the
7271 /// the global base register value. Output instructions required to
7272 /// initialize the register in the function entry block, if necessary.
7273 ///
7274 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
7275 ///
7276 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
7277   assert((!Subtarget.is64Bit() ||
7278           MF->getTarget().getCodeModel() == CodeModel::Medium ||
7279           MF->getTarget().getCodeModel() == CodeModel::Large) &&
7280          "X86-64 PIC uses RIP relative addressing");
7281 
7282   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
7283   Register GlobalBaseReg = X86FI->getGlobalBaseReg();
7284   if (GlobalBaseReg != 0)
7285     return GlobalBaseReg;
7286 
7287   // Create the register. The code to initialize it is inserted
7288   // later, by the CGBR pass (below).
7289   MachineRegisterInfo &RegInfo = MF->getRegInfo();
7290   GlobalBaseReg = RegInfo.createVirtualRegister(
7291       Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
7292   X86FI->setGlobalBaseReg(GlobalBaseReg);
7293   return GlobalBaseReg;
7294 }
7295 
7296 // These are the replaceable SSE instructions. Some of these have Int variants
7297 // that we don't include here. We don't want to replace instructions selected
7298 // by intrinsics.
7299 static const uint16_t ReplaceableInstrs[][3] = {
7300   //PackedSingle     PackedDouble    PackedInt
7301   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
7302   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
7303   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
7304   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
7305   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
7306   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
7307   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
7308   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
7309   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
7310   { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
7311   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
7312   { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
7313   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
7314   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
7315   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
7316   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
7317   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
7318   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
7319   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
7320   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
7321   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
7322   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
7323   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
7324   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
7325   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
7326   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
7327   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
7328   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
7329   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
7330   { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
7331   { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
7332   // AVX 128-bit support
7333   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
7334   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
7335   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
7336   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
7337   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
7338   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
7339   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
7340   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
7341   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
7342   { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
7343   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
7344   { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
7345   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7346   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
7347   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
7348   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
7349   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
7350   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
7351   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
7352   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
7353   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
7354   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
7355   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
7356   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
7357   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
7358   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
7359   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
7360   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
7361   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
7362   { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
7363   { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
7364   // AVX 256-bit support
7365   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
7366   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
7367   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
7368   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
7369   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
7370   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
7371   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
7372   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
7373   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
7374   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
7375   // AVX512 support
7376   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
7377   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7378   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
7379   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
7380   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
7381   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
7382   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
7383   { X86::VMOVSDZrm_alt,  X86::VMOVSDZrm_alt,  X86::VMOVQI2PQIZrm  },
7384   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
7385   { X86::VMOVSSZrm_alt,  X86::VMOVSSZrm_alt,  X86::VMOVDI2PDIZrm  },
7386   { X86::VBROADCASTSSZ128rr,X86::VBROADCASTSSZ128rr,X86::VPBROADCASTDZ128rr },
7387   { X86::VBROADCASTSSZ128rm,X86::VBROADCASTSSZ128rm,X86::VPBROADCASTDZ128rm },
7388   { X86::VBROADCASTSSZ256rr,X86::VBROADCASTSSZ256rr,X86::VPBROADCASTDZ256rr },
7389   { X86::VBROADCASTSSZ256rm,X86::VBROADCASTSSZ256rm,X86::VPBROADCASTDZ256rm },
7390   { X86::VBROADCASTSSZrr,   X86::VBROADCASTSSZrr,   X86::VPBROADCASTDZrr },
7391   { X86::VBROADCASTSSZrm,   X86::VBROADCASTSSZrm,   X86::VPBROADCASTDZrm },
7392   { X86::VMOVDDUPZ128rr,    X86::VMOVDDUPZ128rr,    X86::VPBROADCASTQZ128rr },
7393   { X86::VMOVDDUPZ128rm,    X86::VMOVDDUPZ128rm,    X86::VPBROADCASTQZ128rm },
7394   { X86::VBROADCASTSDZ256rr,X86::VBROADCASTSDZ256rr,X86::VPBROADCASTQZ256rr },
7395   { X86::VBROADCASTSDZ256rm,X86::VBROADCASTSDZ256rm,X86::VPBROADCASTQZ256rm },
7396   { X86::VBROADCASTSDZrr,   X86::VBROADCASTSDZrr,   X86::VPBROADCASTQZrr },
7397   { X86::VBROADCASTSDZrm,   X86::VBROADCASTSDZrm,   X86::VPBROADCASTQZrm },
7398   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
7399   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
7400   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
7401   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
7402   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
7403   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
7404   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
7405   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
7406   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
7407   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
7408   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
7409   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
7410   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
7411   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
7412   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
7413   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
7414   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
7415   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
7416   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
7417   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
7418   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
7419   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
7420   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
7421   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
7422   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
7423   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
7424   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
7425   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
7426   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
7427   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
7428   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
7429   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
7430   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
7431   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
7432   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
7433   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
7434   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
7435   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
7436   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
7437   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
7438   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
7439   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
7440   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
7441   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
7442   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
7443   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
7444   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
7445   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
7446   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
7447   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
7448   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
7449   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
7450   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
7451   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
7452   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
7453   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
7454   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
7455   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
7456   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
7457   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
7458   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
7459   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
7460   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
7461   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
7462   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
7463   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
7464   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
7465   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
7466   { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
7467   { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
7468 };
7469 
7470 static const uint16_t ReplaceableInstrsAVX2[][3] = {
7471   //PackedSingle       PackedDouble       PackedInt
7472   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
7473   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
7474   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
7475   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
7476   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
7477   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
7478   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
7479   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
7480   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
7481   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
7482   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7483   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7484   { X86::VMOVDDUPrm,     X86::VMOVDDUPrm,     X86::VPBROADCASTQrm},
7485   { X86::VMOVDDUPrr,     X86::VMOVDDUPrr,     X86::VPBROADCASTQrr},
7486   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7487   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7488   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7489   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
7490   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
7491   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
7492   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
7493   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
7494   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
7495   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
7496   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
7497   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
7498   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
7499   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
7500   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
7501   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
7502   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
7503 };
7504 
7505 static const uint16_t ReplaceableInstrsFP[][3] = {
7506   //PackedSingle         PackedDouble
7507   { X86::MOVLPSrm,       X86::MOVLPDrm,      X86::INSTRUCTION_LIST_END },
7508   { X86::MOVHPSrm,       X86::MOVHPDrm,      X86::INSTRUCTION_LIST_END },
7509   { X86::MOVHPSmr,       X86::MOVHPDmr,      X86::INSTRUCTION_LIST_END },
7510   { X86::VMOVLPSrm,      X86::VMOVLPDrm,     X86::INSTRUCTION_LIST_END },
7511   { X86::VMOVHPSrm,      X86::VMOVHPDrm,     X86::INSTRUCTION_LIST_END },
7512   { X86::VMOVHPSmr,      X86::VMOVHPDmr,     X86::INSTRUCTION_LIST_END },
7513   { X86::VMOVLPSZ128rm,  X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
7514   { X86::VMOVHPSZ128rm,  X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
7515   { X86::VMOVHPSZ128mr,  X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
7516 };
7517 
7518 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
7519   //PackedSingle       PackedDouble       PackedInt
7520   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7521   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7522   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
7523   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
7524 };
7525 
7526 static const uint16_t ReplaceableInstrsAVX512[][4] = {
7527   // Two integer columns for 64-bit and 32-bit elements.
7528   //PackedSingle        PackedDouble        PackedInt             PackedInt
7529   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
7530   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
7531   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
7532   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
7533   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
7534   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
7535   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
7536   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
7537   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
7538   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
7539   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
7540   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
7541   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
7542   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
7543   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
7544 };
7545 
7546 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7547   // Two integer columns for 64-bit and 32-bit elements.
7548   //PackedSingle        PackedDouble        PackedInt           PackedInt
7549   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7550   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7551   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7552   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7553   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7554   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7555   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7556   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7557   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7558   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7559   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7560   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7561   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7562   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7563   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7564   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7565   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
7566   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
7567   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
7568   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
7569   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
7570   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
7571   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
7572   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
7573 };
7574 
7575 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
7576   // Two integer columns for 64-bit and 32-bit elements.
7577   //PackedSingle          PackedDouble
7578   //PackedInt             PackedInt
7579   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
7580     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
7581   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
7582     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
7583   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
7584     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
7585   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
7586     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
7587   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
7588     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
7589   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
7590     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
7591   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
7592     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
7593   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
7594     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
7595   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
7596     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
7597   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
7598     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
7599   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
7600     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
7601   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
7602     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
7603   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
7604     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
7605   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
7606     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
7607   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
7608     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
7609   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
7610     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
7611   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
7612     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
7613   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
7614     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
7615   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
7616     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
7617   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
7618     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
7619   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
7620     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
7621   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
7622     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
7623   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
7624     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
7625   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
7626     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
7627   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
7628     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
7629   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
7630     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
7631   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
7632     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
7633   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
7634     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
7635   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
7636     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
7637   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
7638     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
7639   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
7640     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
7641   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
7642     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
7643   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
7644     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
7645   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
7646     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
7647   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
7648     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
7649   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
7650     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
7651   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
7652     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
7653   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
7654     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
7655   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
7656     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
7657   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
7658     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
7659   { X86::VORPSZrmk,       X86::VORPDZrmk,
7660     X86::VPORQZrmk,       X86::VPORDZrmk       },
7661   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
7662     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
7663   { X86::VORPSZrrk,       X86::VORPDZrrk,
7664     X86::VPORQZrrk,       X86::VPORDZrrk       },
7665   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
7666     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
7667   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
7668     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
7669   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
7670     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
7671   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
7672     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
7673   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
7674     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
7675   // Broadcast loads can be handled the same as masked operations to avoid
7676   // changing element size.
7677   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
7678     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
7679   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
7680     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
7681   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
7682     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
7683   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
7684     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
7685   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
7686     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
7687   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
7688     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
7689   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
7690     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
7691   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
7692     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
7693   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
7694     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
7695   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7696     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7697   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7698     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7699   { X86::VORPSZrmb,       X86::VORPDZrmb,
7700     X86::VPORQZrmb,       X86::VPORDZrmb       },
7701   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
7702     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
7703   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
7704     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
7705   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
7706     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
7707   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
7708     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
7709   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
7710     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
7711   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
7712     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
7713   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
7714     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
7715   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
7716     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
7717   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
7718     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
7719   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
7720     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
7721   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7722     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7723   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7724     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7725   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
7726     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
7727   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
7728     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
7729   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
7730     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
7731   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
7732     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
7733   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
7734     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
7735   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
7736     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
7737   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
7738     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
7739   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
7740     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
7741   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
7742     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
7743   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
7744     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
7745   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
7746     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
7747   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7748     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7749   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7750     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7751   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
7752     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
7753   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
7754     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
7755 };
7756 
7757 // NOTE: These should only be used by the custom domain methods.
7758 static const uint16_t ReplaceableBlendInstrs[][3] = {
7759   //PackedSingle             PackedDouble             PackedInt
7760   { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
7761   { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
7762   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
7763   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
7764   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
7765   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
7766 };
7767 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
7768   //PackedSingle             PackedDouble             PackedInt
7769   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
7770   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
7771   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
7772   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
7773 };
7774 
7775 // Special table for changing EVEX logic instructions to VEX.
7776 // TODO: Should we run EVEX->VEX earlier?
7777 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
7778   // Two integer columns for 64-bit and 32-bit elements.
7779   //PackedSingle     PackedDouble     PackedInt           PackedInt
7780   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7781   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7782   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7783   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7784   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7785   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7786   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7787   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7788   { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7789   { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7790   { X86::VANDPSYrm,  X86::VANDPDYrm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7791   { X86::VANDPSYrr,  X86::VANDPDYrr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7792   { X86::VORPSYrm,   X86::VORPDYrm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7793   { X86::VORPSYrr,   X86::VORPDYrr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7794   { X86::VXORPSYrm,  X86::VXORPDYrm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7795   { X86::VXORPSYrr,  X86::VXORPDYrr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7796 };
7797 
7798 // FIXME: Some shuffle and unpack instructions have equivalents in different
7799 // domains, but they require a bit more work than just switching opcodes.
7800 
7801 static const uint16_t *lookup(unsigned opcode, unsigned domain,
7802                               ArrayRef<uint16_t[3]> Table) {
7803   for (const uint16_t (&Row)[3] : Table)
7804     if (Row[domain-1] == opcode)
7805       return Row;
7806   return nullptr;
7807 }
7808 
7809 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
7810                                     ArrayRef<uint16_t[4]> Table) {
7811   // If this is the integer domain make sure to check both integer columns.
7812   for (const uint16_t (&Row)[4] : Table)
7813     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7814       return Row;
7815   return nullptr;
7816 }
7817 
7818 // Helper to attempt to widen/narrow blend masks.
7819 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
7820                             unsigned NewWidth, unsigned *pNewMask = nullptr) {
7821   assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
7822          "Illegal blend mask scale");
7823   unsigned NewMask = 0;
7824 
7825   if ((OldWidth % NewWidth) == 0) {
7826     unsigned Scale = OldWidth / NewWidth;
7827     unsigned SubMask = (1u << Scale) - 1;
7828     for (unsigned i = 0; i != NewWidth; ++i) {
7829       unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
7830       if (Sub == SubMask)
7831         NewMask |= (1u << i);
7832       else if (Sub != 0x0)
7833         return false;
7834     }
7835   } else {
7836     unsigned Scale = NewWidth / OldWidth;
7837     unsigned SubMask = (1u << Scale) - 1;
7838     for (unsigned i = 0; i != OldWidth; ++i) {
7839       if (OldMask & (1 << i)) {
7840         NewMask |= (SubMask << (i * Scale));
7841       }
7842     }
7843   }
7844 
7845   if (pNewMask)
7846     *pNewMask = NewMask;
7847   return true;
7848 }
7849 
7850 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
7851   unsigned Opcode = MI.getOpcode();
7852   unsigned NumOperands = MI.getDesc().getNumOperands();
7853 
7854   auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
7855     uint16_t validDomains = 0;
7856     if (MI.getOperand(NumOperands - 1).isImm()) {
7857       unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
7858       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
7859         validDomains |= 0x2; // PackedSingle
7860       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
7861         validDomains |= 0x4; // PackedDouble
7862       if (!Is256 || Subtarget.hasAVX2())
7863         validDomains |= 0x8; // PackedInt
7864     }
7865     return validDomains;
7866   };
7867 
7868   switch (Opcode) {
7869   case X86::BLENDPDrmi:
7870   case X86::BLENDPDrri:
7871   case X86::VBLENDPDrmi:
7872   case X86::VBLENDPDrri:
7873     return GetBlendDomains(2, false);
7874   case X86::VBLENDPDYrmi:
7875   case X86::VBLENDPDYrri:
7876     return GetBlendDomains(4, true);
7877   case X86::BLENDPSrmi:
7878   case X86::BLENDPSrri:
7879   case X86::VBLENDPSrmi:
7880   case X86::VBLENDPSrri:
7881   case X86::VPBLENDDrmi:
7882   case X86::VPBLENDDrri:
7883     return GetBlendDomains(4, false);
7884   case X86::VBLENDPSYrmi:
7885   case X86::VBLENDPSYrri:
7886   case X86::VPBLENDDYrmi:
7887   case X86::VPBLENDDYrri:
7888     return GetBlendDomains(8, true);
7889   case X86::PBLENDWrmi:
7890   case X86::PBLENDWrri:
7891   case X86::VPBLENDWrmi:
7892   case X86::VPBLENDWrri:
7893   // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
7894   case X86::VPBLENDWYrmi:
7895   case X86::VPBLENDWYrri:
7896     return GetBlendDomains(8, false);
7897   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7898   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7899   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7900   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7901   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7902   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7903   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7904   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7905   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7906   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7907   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7908   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7909   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7910   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7911   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7912   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm:
7913     // If we don't have DQI see if we can still switch from an EVEX integer
7914     // instruction to a VEX floating point instruction.
7915     if (Subtarget.hasDQI())
7916       return 0;
7917 
7918     if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
7919       return 0;
7920     if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
7921       return 0;
7922     // Register forms will have 3 operands. Memory form will have more.
7923     if (NumOperands == 3 &&
7924         RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
7925       return 0;
7926 
7927     // All domains are valid.
7928     return 0xe;
7929   case X86::MOVHLPSrr:
7930     // We can swap domains when both inputs are the same register.
7931     // FIXME: This doesn't catch all the cases we would like. If the input
7932     // register isn't KILLed by the instruction, the two address instruction
7933     // pass puts a COPY on one input. The other input uses the original
7934     // register. This prevents the same physical register from being used by
7935     // both inputs.
7936     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7937         MI.getOperand(0).getSubReg() == 0 &&
7938         MI.getOperand(1).getSubReg() == 0 &&
7939         MI.getOperand(2).getSubReg() == 0)
7940       return 0x6;
7941     return 0;
7942   case X86::SHUFPDrri:
7943     return 0x6;
7944   }
7945   return 0;
7946 }
7947 
7948 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
7949                                             unsigned Domain) const {
7950   assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
7951   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7952   assert(dom && "Not an SSE instruction");
7953 
7954   unsigned Opcode = MI.getOpcode();
7955   unsigned NumOperands = MI.getDesc().getNumOperands();
7956 
7957   auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
7958     if (MI.getOperand(NumOperands - 1).isImm()) {
7959       unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
7960       Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
7961       unsigned NewImm = Imm;
7962 
7963       const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
7964       if (!table)
7965         table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7966 
7967       if (Domain == 1) { // PackedSingle
7968         AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7969       } else if (Domain == 2) { // PackedDouble
7970         AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
7971       } else if (Domain == 3) { // PackedInt
7972         if (Subtarget.hasAVX2()) {
7973           // If we are already VPBLENDW use that, else use VPBLENDD.
7974           if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
7975             table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7976             AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7977           }
7978         } else {
7979           assert(!Is256 && "128-bit vector expected");
7980           AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
7981         }
7982       }
7983 
7984       assert(table && table[Domain - 1] && "Unknown domain op");
7985       MI.setDesc(get(table[Domain - 1]));
7986       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
7987     }
7988     return true;
7989   };
7990 
7991   switch (Opcode) {
7992   case X86::BLENDPDrmi:
7993   case X86::BLENDPDrri:
7994   case X86::VBLENDPDrmi:
7995   case X86::VBLENDPDrri:
7996     return SetBlendDomain(2, false);
7997   case X86::VBLENDPDYrmi:
7998   case X86::VBLENDPDYrri:
7999     return SetBlendDomain(4, true);
8000   case X86::BLENDPSrmi:
8001   case X86::BLENDPSrri:
8002   case X86::VBLENDPSrmi:
8003   case X86::VBLENDPSrri:
8004   case X86::VPBLENDDrmi:
8005   case X86::VPBLENDDrri:
8006     return SetBlendDomain(4, false);
8007   case X86::VBLENDPSYrmi:
8008   case X86::VBLENDPSYrri:
8009   case X86::VPBLENDDYrmi:
8010   case X86::VPBLENDDYrri:
8011     return SetBlendDomain(8, true);
8012   case X86::PBLENDWrmi:
8013   case X86::PBLENDWrri:
8014   case X86::VPBLENDWrmi:
8015   case X86::VPBLENDWrri:
8016     return SetBlendDomain(8, false);
8017   case X86::VPBLENDWYrmi:
8018   case X86::VPBLENDWYrri:
8019     return SetBlendDomain(16, true);
8020   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
8021   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
8022   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
8023   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
8024   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
8025   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
8026   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
8027   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
8028   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
8029   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
8030   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
8031   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
8032   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
8033   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
8034   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
8035   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm: {
8036     // Without DQI, convert EVEX instructions to VEX instructions.
8037     if (Subtarget.hasDQI())
8038       return false;
8039 
8040     const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
8041                                          ReplaceableCustomAVX512LogicInstrs);
8042     assert(table && "Instruction not found in table?");
8043     // Don't change integer Q instructions to D instructions and
8044     // use D intructions if we started with a PS instruction.
8045     if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
8046       Domain = 4;
8047     MI.setDesc(get(table[Domain - 1]));
8048     return true;
8049   }
8050   case X86::UNPCKHPDrr:
8051   case X86::MOVHLPSrr:
8052     // We just need to commute the instruction which will switch the domains.
8053     if (Domain != dom && Domain != 3 &&
8054         MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
8055         MI.getOperand(0).getSubReg() == 0 &&
8056         MI.getOperand(1).getSubReg() == 0 &&
8057         MI.getOperand(2).getSubReg() == 0) {
8058       commuteInstruction(MI, false);
8059       return true;
8060     }
8061     // We must always return true for MOVHLPSrr.
8062     if (Opcode == X86::MOVHLPSrr)
8063       return true;
8064     break;
8065   case X86::SHUFPDrri: {
8066     if (Domain == 1) {
8067       unsigned Imm = MI.getOperand(3).getImm();
8068       unsigned NewImm = 0x44;
8069       if (Imm & 1) NewImm |= 0x0a;
8070       if (Imm & 2) NewImm |= 0xa0;
8071       MI.getOperand(3).setImm(NewImm);
8072       MI.setDesc(get(X86::SHUFPSrri));
8073     }
8074     return true;
8075   }
8076   }
8077   return false;
8078 }
8079 
8080 std::pair<uint16_t, uint16_t>
8081 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
8082   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
8083   unsigned opcode = MI.getOpcode();
8084   uint16_t validDomains = 0;
8085   if (domain) {
8086     // Attempt to match for custom instructions.
8087     validDomains = getExecutionDomainCustom(MI);
8088     if (validDomains)
8089       return std::make_pair(domain, validDomains);
8090 
8091     if (lookup(opcode, domain, ReplaceableInstrs)) {
8092       validDomains = 0xe;
8093     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
8094       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
8095     } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
8096       validDomains = 0x6;
8097     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
8098       // Insert/extract instructions should only effect domain if AVX2
8099       // is enabled.
8100       if (!Subtarget.hasAVX2())
8101         return std::make_pair(0, 0);
8102       validDomains = 0xe;
8103     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
8104       validDomains = 0xe;
8105     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
8106                                                   ReplaceableInstrsAVX512DQ)) {
8107       validDomains = 0xe;
8108     } else if (Subtarget.hasDQI()) {
8109       if (const uint16_t *table = lookupAVX512(opcode, domain,
8110                                              ReplaceableInstrsAVX512DQMasked)) {
8111         if (domain == 1 || (domain == 3 && table[3] == opcode))
8112           validDomains = 0xa;
8113         else
8114           validDomains = 0xc;
8115       }
8116     }
8117   }
8118   return std::make_pair(domain, validDomains);
8119 }
8120 
8121 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
8122   assert(Domain>0 && Domain<4 && "Invalid execution domain");
8123   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
8124   assert(dom && "Not an SSE instruction");
8125 
8126   // Attempt to match for custom instructions.
8127   if (setExecutionDomainCustom(MI, Domain))
8128     return;
8129 
8130   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
8131   if (!table) { // try the other table
8132     assert((Subtarget.hasAVX2() || Domain < 3) &&
8133            "256-bit vector operations only available in AVX2");
8134     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
8135   }
8136   if (!table) { // try the FP table
8137     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
8138     assert((!table || Domain < 3) &&
8139            "Can only select PackedSingle or PackedDouble");
8140   }
8141   if (!table) { // try the other table
8142     assert(Subtarget.hasAVX2() &&
8143            "256-bit insert/extract only available in AVX2");
8144     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
8145   }
8146   if (!table) { // try the AVX512 table
8147     assert(Subtarget.hasAVX512() && "Requires AVX-512");
8148     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
8149     // Don't change integer Q instructions to D instructions.
8150     if (table && Domain == 3 && table[3] == MI.getOpcode())
8151       Domain = 4;
8152   }
8153   if (!table) { // try the AVX512DQ table
8154     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
8155     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
8156     // Don't change integer Q instructions to D instructions and
8157     // use D instructions if we started with a PS instruction.
8158     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
8159       Domain = 4;
8160   }
8161   if (!table) { // try the AVX512DQMasked table
8162     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
8163     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
8164     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
8165       Domain = 4;
8166   }
8167   assert(table && "Cannot change domain");
8168   MI.setDesc(get(table[Domain - 1]));
8169 }
8170 
8171 /// Return the noop instruction to use for a noop.
8172 MCInst X86InstrInfo::getNop() const {
8173   MCInst Nop;
8174   Nop.setOpcode(X86::NOOP);
8175   return Nop;
8176 }
8177 
8178 bool X86InstrInfo::isHighLatencyDef(int opc) const {
8179   switch (opc) {
8180   default: return false;
8181   case X86::DIVPDrm:
8182   case X86::DIVPDrr:
8183   case X86::DIVPSrm:
8184   case X86::DIVPSrr:
8185   case X86::DIVSDrm:
8186   case X86::DIVSDrm_Int:
8187   case X86::DIVSDrr:
8188   case X86::DIVSDrr_Int:
8189   case X86::DIVSSrm:
8190   case X86::DIVSSrm_Int:
8191   case X86::DIVSSrr:
8192   case X86::DIVSSrr_Int:
8193   case X86::SQRTPDm:
8194   case X86::SQRTPDr:
8195   case X86::SQRTPSm:
8196   case X86::SQRTPSr:
8197   case X86::SQRTSDm:
8198   case X86::SQRTSDm_Int:
8199   case X86::SQRTSDr:
8200   case X86::SQRTSDr_Int:
8201   case X86::SQRTSSm:
8202   case X86::SQRTSSm_Int:
8203   case X86::SQRTSSr:
8204   case X86::SQRTSSr_Int:
8205   // AVX instructions with high latency
8206   case X86::VDIVPDrm:
8207   case X86::VDIVPDrr:
8208   case X86::VDIVPDYrm:
8209   case X86::VDIVPDYrr:
8210   case X86::VDIVPSrm:
8211   case X86::VDIVPSrr:
8212   case X86::VDIVPSYrm:
8213   case X86::VDIVPSYrr:
8214   case X86::VDIVSDrm:
8215   case X86::VDIVSDrm_Int:
8216   case X86::VDIVSDrr:
8217   case X86::VDIVSDrr_Int:
8218   case X86::VDIVSSrm:
8219   case X86::VDIVSSrm_Int:
8220   case X86::VDIVSSrr:
8221   case X86::VDIVSSrr_Int:
8222   case X86::VSQRTPDm:
8223   case X86::VSQRTPDr:
8224   case X86::VSQRTPDYm:
8225   case X86::VSQRTPDYr:
8226   case X86::VSQRTPSm:
8227   case X86::VSQRTPSr:
8228   case X86::VSQRTPSYm:
8229   case X86::VSQRTPSYr:
8230   case X86::VSQRTSDm:
8231   case X86::VSQRTSDm_Int:
8232   case X86::VSQRTSDr:
8233   case X86::VSQRTSDr_Int:
8234   case X86::VSQRTSSm:
8235   case X86::VSQRTSSm_Int:
8236   case X86::VSQRTSSr:
8237   case X86::VSQRTSSr_Int:
8238   // AVX512 instructions with high latency
8239   case X86::VDIVPDZ128rm:
8240   case X86::VDIVPDZ128rmb:
8241   case X86::VDIVPDZ128rmbk:
8242   case X86::VDIVPDZ128rmbkz:
8243   case X86::VDIVPDZ128rmk:
8244   case X86::VDIVPDZ128rmkz:
8245   case X86::VDIVPDZ128rr:
8246   case X86::VDIVPDZ128rrk:
8247   case X86::VDIVPDZ128rrkz:
8248   case X86::VDIVPDZ256rm:
8249   case X86::VDIVPDZ256rmb:
8250   case X86::VDIVPDZ256rmbk:
8251   case X86::VDIVPDZ256rmbkz:
8252   case X86::VDIVPDZ256rmk:
8253   case X86::VDIVPDZ256rmkz:
8254   case X86::VDIVPDZ256rr:
8255   case X86::VDIVPDZ256rrk:
8256   case X86::VDIVPDZ256rrkz:
8257   case X86::VDIVPDZrrb:
8258   case X86::VDIVPDZrrbk:
8259   case X86::VDIVPDZrrbkz:
8260   case X86::VDIVPDZrm:
8261   case X86::VDIVPDZrmb:
8262   case X86::VDIVPDZrmbk:
8263   case X86::VDIVPDZrmbkz:
8264   case X86::VDIVPDZrmk:
8265   case X86::VDIVPDZrmkz:
8266   case X86::VDIVPDZrr:
8267   case X86::VDIVPDZrrk:
8268   case X86::VDIVPDZrrkz:
8269   case X86::VDIVPSZ128rm:
8270   case X86::VDIVPSZ128rmb:
8271   case X86::VDIVPSZ128rmbk:
8272   case X86::VDIVPSZ128rmbkz:
8273   case X86::VDIVPSZ128rmk:
8274   case X86::VDIVPSZ128rmkz:
8275   case X86::VDIVPSZ128rr:
8276   case X86::VDIVPSZ128rrk:
8277   case X86::VDIVPSZ128rrkz:
8278   case X86::VDIVPSZ256rm:
8279   case X86::VDIVPSZ256rmb:
8280   case X86::VDIVPSZ256rmbk:
8281   case X86::VDIVPSZ256rmbkz:
8282   case X86::VDIVPSZ256rmk:
8283   case X86::VDIVPSZ256rmkz:
8284   case X86::VDIVPSZ256rr:
8285   case X86::VDIVPSZ256rrk:
8286   case X86::VDIVPSZ256rrkz:
8287   case X86::VDIVPSZrrb:
8288   case X86::VDIVPSZrrbk:
8289   case X86::VDIVPSZrrbkz:
8290   case X86::VDIVPSZrm:
8291   case X86::VDIVPSZrmb:
8292   case X86::VDIVPSZrmbk:
8293   case X86::VDIVPSZrmbkz:
8294   case X86::VDIVPSZrmk:
8295   case X86::VDIVPSZrmkz:
8296   case X86::VDIVPSZrr:
8297   case X86::VDIVPSZrrk:
8298   case X86::VDIVPSZrrkz:
8299   case X86::VDIVSDZrm:
8300   case X86::VDIVSDZrr:
8301   case X86::VDIVSDZrm_Int:
8302   case X86::VDIVSDZrm_Intk:
8303   case X86::VDIVSDZrm_Intkz:
8304   case X86::VDIVSDZrr_Int:
8305   case X86::VDIVSDZrr_Intk:
8306   case X86::VDIVSDZrr_Intkz:
8307   case X86::VDIVSDZrrb_Int:
8308   case X86::VDIVSDZrrb_Intk:
8309   case X86::VDIVSDZrrb_Intkz:
8310   case X86::VDIVSSZrm:
8311   case X86::VDIVSSZrr:
8312   case X86::VDIVSSZrm_Int:
8313   case X86::VDIVSSZrm_Intk:
8314   case X86::VDIVSSZrm_Intkz:
8315   case X86::VDIVSSZrr_Int:
8316   case X86::VDIVSSZrr_Intk:
8317   case X86::VDIVSSZrr_Intkz:
8318   case X86::VDIVSSZrrb_Int:
8319   case X86::VDIVSSZrrb_Intk:
8320   case X86::VDIVSSZrrb_Intkz:
8321   case X86::VSQRTPDZ128m:
8322   case X86::VSQRTPDZ128mb:
8323   case X86::VSQRTPDZ128mbk:
8324   case X86::VSQRTPDZ128mbkz:
8325   case X86::VSQRTPDZ128mk:
8326   case X86::VSQRTPDZ128mkz:
8327   case X86::VSQRTPDZ128r:
8328   case X86::VSQRTPDZ128rk:
8329   case X86::VSQRTPDZ128rkz:
8330   case X86::VSQRTPDZ256m:
8331   case X86::VSQRTPDZ256mb:
8332   case X86::VSQRTPDZ256mbk:
8333   case X86::VSQRTPDZ256mbkz:
8334   case X86::VSQRTPDZ256mk:
8335   case X86::VSQRTPDZ256mkz:
8336   case X86::VSQRTPDZ256r:
8337   case X86::VSQRTPDZ256rk:
8338   case X86::VSQRTPDZ256rkz:
8339   case X86::VSQRTPDZm:
8340   case X86::VSQRTPDZmb:
8341   case X86::VSQRTPDZmbk:
8342   case X86::VSQRTPDZmbkz:
8343   case X86::VSQRTPDZmk:
8344   case X86::VSQRTPDZmkz:
8345   case X86::VSQRTPDZr:
8346   case X86::VSQRTPDZrb:
8347   case X86::VSQRTPDZrbk:
8348   case X86::VSQRTPDZrbkz:
8349   case X86::VSQRTPDZrk:
8350   case X86::VSQRTPDZrkz:
8351   case X86::VSQRTPSZ128m:
8352   case X86::VSQRTPSZ128mb:
8353   case X86::VSQRTPSZ128mbk:
8354   case X86::VSQRTPSZ128mbkz:
8355   case X86::VSQRTPSZ128mk:
8356   case X86::VSQRTPSZ128mkz:
8357   case X86::VSQRTPSZ128r:
8358   case X86::VSQRTPSZ128rk:
8359   case X86::VSQRTPSZ128rkz:
8360   case X86::VSQRTPSZ256m:
8361   case X86::VSQRTPSZ256mb:
8362   case X86::VSQRTPSZ256mbk:
8363   case X86::VSQRTPSZ256mbkz:
8364   case X86::VSQRTPSZ256mk:
8365   case X86::VSQRTPSZ256mkz:
8366   case X86::VSQRTPSZ256r:
8367   case X86::VSQRTPSZ256rk:
8368   case X86::VSQRTPSZ256rkz:
8369   case X86::VSQRTPSZm:
8370   case X86::VSQRTPSZmb:
8371   case X86::VSQRTPSZmbk:
8372   case X86::VSQRTPSZmbkz:
8373   case X86::VSQRTPSZmk:
8374   case X86::VSQRTPSZmkz:
8375   case X86::VSQRTPSZr:
8376   case X86::VSQRTPSZrb:
8377   case X86::VSQRTPSZrbk:
8378   case X86::VSQRTPSZrbkz:
8379   case X86::VSQRTPSZrk:
8380   case X86::VSQRTPSZrkz:
8381   case X86::VSQRTSDZm:
8382   case X86::VSQRTSDZm_Int:
8383   case X86::VSQRTSDZm_Intk:
8384   case X86::VSQRTSDZm_Intkz:
8385   case X86::VSQRTSDZr:
8386   case X86::VSQRTSDZr_Int:
8387   case X86::VSQRTSDZr_Intk:
8388   case X86::VSQRTSDZr_Intkz:
8389   case X86::VSQRTSDZrb_Int:
8390   case X86::VSQRTSDZrb_Intk:
8391   case X86::VSQRTSDZrb_Intkz:
8392   case X86::VSQRTSSZm:
8393   case X86::VSQRTSSZm_Int:
8394   case X86::VSQRTSSZm_Intk:
8395   case X86::VSQRTSSZm_Intkz:
8396   case X86::VSQRTSSZr:
8397   case X86::VSQRTSSZr_Int:
8398   case X86::VSQRTSSZr_Intk:
8399   case X86::VSQRTSSZr_Intkz:
8400   case X86::VSQRTSSZrb_Int:
8401   case X86::VSQRTSSZrb_Intk:
8402   case X86::VSQRTSSZrb_Intkz:
8403 
8404   case X86::VGATHERDPDYrm:
8405   case X86::VGATHERDPDZ128rm:
8406   case X86::VGATHERDPDZ256rm:
8407   case X86::VGATHERDPDZrm:
8408   case X86::VGATHERDPDrm:
8409   case X86::VGATHERDPSYrm:
8410   case X86::VGATHERDPSZ128rm:
8411   case X86::VGATHERDPSZ256rm:
8412   case X86::VGATHERDPSZrm:
8413   case X86::VGATHERDPSrm:
8414   case X86::VGATHERPF0DPDm:
8415   case X86::VGATHERPF0DPSm:
8416   case X86::VGATHERPF0QPDm:
8417   case X86::VGATHERPF0QPSm:
8418   case X86::VGATHERPF1DPDm:
8419   case X86::VGATHERPF1DPSm:
8420   case X86::VGATHERPF1QPDm:
8421   case X86::VGATHERPF1QPSm:
8422   case X86::VGATHERQPDYrm:
8423   case X86::VGATHERQPDZ128rm:
8424   case X86::VGATHERQPDZ256rm:
8425   case X86::VGATHERQPDZrm:
8426   case X86::VGATHERQPDrm:
8427   case X86::VGATHERQPSYrm:
8428   case X86::VGATHERQPSZ128rm:
8429   case X86::VGATHERQPSZ256rm:
8430   case X86::VGATHERQPSZrm:
8431   case X86::VGATHERQPSrm:
8432   case X86::VPGATHERDDYrm:
8433   case X86::VPGATHERDDZ128rm:
8434   case X86::VPGATHERDDZ256rm:
8435   case X86::VPGATHERDDZrm:
8436   case X86::VPGATHERDDrm:
8437   case X86::VPGATHERDQYrm:
8438   case X86::VPGATHERDQZ128rm:
8439   case X86::VPGATHERDQZ256rm:
8440   case X86::VPGATHERDQZrm:
8441   case X86::VPGATHERDQrm:
8442   case X86::VPGATHERQDYrm:
8443   case X86::VPGATHERQDZ128rm:
8444   case X86::VPGATHERQDZ256rm:
8445   case X86::VPGATHERQDZrm:
8446   case X86::VPGATHERQDrm:
8447   case X86::VPGATHERQQYrm:
8448   case X86::VPGATHERQQZ128rm:
8449   case X86::VPGATHERQQZ256rm:
8450   case X86::VPGATHERQQZrm:
8451   case X86::VPGATHERQQrm:
8452   case X86::VSCATTERDPDZ128mr:
8453   case X86::VSCATTERDPDZ256mr:
8454   case X86::VSCATTERDPDZmr:
8455   case X86::VSCATTERDPSZ128mr:
8456   case X86::VSCATTERDPSZ256mr:
8457   case X86::VSCATTERDPSZmr:
8458   case X86::VSCATTERPF0DPDm:
8459   case X86::VSCATTERPF0DPSm:
8460   case X86::VSCATTERPF0QPDm:
8461   case X86::VSCATTERPF0QPSm:
8462   case X86::VSCATTERPF1DPDm:
8463   case X86::VSCATTERPF1DPSm:
8464   case X86::VSCATTERPF1QPDm:
8465   case X86::VSCATTERPF1QPSm:
8466   case X86::VSCATTERQPDZ128mr:
8467   case X86::VSCATTERQPDZ256mr:
8468   case X86::VSCATTERQPDZmr:
8469   case X86::VSCATTERQPSZ128mr:
8470   case X86::VSCATTERQPSZ256mr:
8471   case X86::VSCATTERQPSZmr:
8472   case X86::VPSCATTERDDZ128mr:
8473   case X86::VPSCATTERDDZ256mr:
8474   case X86::VPSCATTERDDZmr:
8475   case X86::VPSCATTERDQZ128mr:
8476   case X86::VPSCATTERDQZ256mr:
8477   case X86::VPSCATTERDQZmr:
8478   case X86::VPSCATTERQDZ128mr:
8479   case X86::VPSCATTERQDZ256mr:
8480   case X86::VPSCATTERQDZmr:
8481   case X86::VPSCATTERQQZ128mr:
8482   case X86::VPSCATTERQQZ256mr:
8483   case X86::VPSCATTERQQZmr:
8484     return true;
8485   }
8486 }
8487 
8488 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
8489                                          const MachineRegisterInfo *MRI,
8490                                          const MachineInstr &DefMI,
8491                                          unsigned DefIdx,
8492                                          const MachineInstr &UseMI,
8493                                          unsigned UseIdx) const {
8494   return isHighLatencyDef(DefMI.getOpcode());
8495 }
8496 
8497 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
8498                                            const MachineBasicBlock *MBB) const {
8499   assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
8500          Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
8501 
8502   // Integer binary math/logic instructions have a third source operand:
8503   // the EFLAGS register. That operand must be both defined here and never
8504   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
8505   // not change anything because rearranging the operands could affect other
8506   // instructions that depend on the exact status flags (zero, sign, etc.)
8507   // that are set by using these particular operands with this operation.
8508   const MachineOperand *FlagDef = Inst.findRegisterDefOperand(X86::EFLAGS);
8509   assert((Inst.getNumDefs() == 1 || FlagDef) &&
8510          "Implicit def isn't flags?");
8511   if (FlagDef && !FlagDef->isDead())
8512     return false;
8513 
8514   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
8515 }
8516 
8517 // TODO: There are many more machine instruction opcodes to match:
8518 //       1. Other data types (integer, vectors)
8519 //       2. Other math / logic operations (xor, or)
8520 //       3. Other forms of the same operation (intrinsics and other variants)
8521 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
8522   switch (Inst.getOpcode()) {
8523   case X86::AND8rr:
8524   case X86::AND16rr:
8525   case X86::AND32rr:
8526   case X86::AND64rr:
8527   case X86::OR8rr:
8528   case X86::OR16rr:
8529   case X86::OR32rr:
8530   case X86::OR64rr:
8531   case X86::XOR8rr:
8532   case X86::XOR16rr:
8533   case X86::XOR32rr:
8534   case X86::XOR64rr:
8535   case X86::IMUL16rr:
8536   case X86::IMUL32rr:
8537   case X86::IMUL64rr:
8538   case X86::PANDrr:
8539   case X86::PORrr:
8540   case X86::PXORrr:
8541   case X86::ANDPDrr:
8542   case X86::ANDPSrr:
8543   case X86::ORPDrr:
8544   case X86::ORPSrr:
8545   case X86::XORPDrr:
8546   case X86::XORPSrr:
8547   case X86::PADDBrr:
8548   case X86::PADDWrr:
8549   case X86::PADDDrr:
8550   case X86::PADDQrr:
8551   case X86::PMULLWrr:
8552   case X86::PMULLDrr:
8553   case X86::PMAXSBrr:
8554   case X86::PMAXSDrr:
8555   case X86::PMAXSWrr:
8556   case X86::PMAXUBrr:
8557   case X86::PMAXUDrr:
8558   case X86::PMAXUWrr:
8559   case X86::PMINSBrr:
8560   case X86::PMINSDrr:
8561   case X86::PMINSWrr:
8562   case X86::PMINUBrr:
8563   case X86::PMINUDrr:
8564   case X86::PMINUWrr:
8565   case X86::VPANDrr:
8566   case X86::VPANDYrr:
8567   case X86::VPANDDZ128rr:
8568   case X86::VPANDDZ256rr:
8569   case X86::VPANDDZrr:
8570   case X86::VPANDQZ128rr:
8571   case X86::VPANDQZ256rr:
8572   case X86::VPANDQZrr:
8573   case X86::VPORrr:
8574   case X86::VPORYrr:
8575   case X86::VPORDZ128rr:
8576   case X86::VPORDZ256rr:
8577   case X86::VPORDZrr:
8578   case X86::VPORQZ128rr:
8579   case X86::VPORQZ256rr:
8580   case X86::VPORQZrr:
8581   case X86::VPXORrr:
8582   case X86::VPXORYrr:
8583   case X86::VPXORDZ128rr:
8584   case X86::VPXORDZ256rr:
8585   case X86::VPXORDZrr:
8586   case X86::VPXORQZ128rr:
8587   case X86::VPXORQZ256rr:
8588   case X86::VPXORQZrr:
8589   case X86::VANDPDrr:
8590   case X86::VANDPSrr:
8591   case X86::VANDPDYrr:
8592   case X86::VANDPSYrr:
8593   case X86::VANDPDZ128rr:
8594   case X86::VANDPSZ128rr:
8595   case X86::VANDPDZ256rr:
8596   case X86::VANDPSZ256rr:
8597   case X86::VANDPDZrr:
8598   case X86::VANDPSZrr:
8599   case X86::VORPDrr:
8600   case X86::VORPSrr:
8601   case X86::VORPDYrr:
8602   case X86::VORPSYrr:
8603   case X86::VORPDZ128rr:
8604   case X86::VORPSZ128rr:
8605   case X86::VORPDZ256rr:
8606   case X86::VORPSZ256rr:
8607   case X86::VORPDZrr:
8608   case X86::VORPSZrr:
8609   case X86::VXORPDrr:
8610   case X86::VXORPSrr:
8611   case X86::VXORPDYrr:
8612   case X86::VXORPSYrr:
8613   case X86::VXORPDZ128rr:
8614   case X86::VXORPSZ128rr:
8615   case X86::VXORPDZ256rr:
8616   case X86::VXORPSZ256rr:
8617   case X86::VXORPDZrr:
8618   case X86::VXORPSZrr:
8619   case X86::KADDBrr:
8620   case X86::KADDWrr:
8621   case X86::KADDDrr:
8622   case X86::KADDQrr:
8623   case X86::KANDBrr:
8624   case X86::KANDWrr:
8625   case X86::KANDDrr:
8626   case X86::KANDQrr:
8627   case X86::KORBrr:
8628   case X86::KORWrr:
8629   case X86::KORDrr:
8630   case X86::KORQrr:
8631   case X86::KXORBrr:
8632   case X86::KXORWrr:
8633   case X86::KXORDrr:
8634   case X86::KXORQrr:
8635   case X86::VPADDBrr:
8636   case X86::VPADDWrr:
8637   case X86::VPADDDrr:
8638   case X86::VPADDQrr:
8639   case X86::VPADDBYrr:
8640   case X86::VPADDWYrr:
8641   case X86::VPADDDYrr:
8642   case X86::VPADDQYrr:
8643   case X86::VPADDBZ128rr:
8644   case X86::VPADDWZ128rr:
8645   case X86::VPADDDZ128rr:
8646   case X86::VPADDQZ128rr:
8647   case X86::VPADDBZ256rr:
8648   case X86::VPADDWZ256rr:
8649   case X86::VPADDDZ256rr:
8650   case X86::VPADDQZ256rr:
8651   case X86::VPADDBZrr:
8652   case X86::VPADDWZrr:
8653   case X86::VPADDDZrr:
8654   case X86::VPADDQZrr:
8655   case X86::VPMULLWrr:
8656   case X86::VPMULLWYrr:
8657   case X86::VPMULLWZ128rr:
8658   case X86::VPMULLWZ256rr:
8659   case X86::VPMULLWZrr:
8660   case X86::VPMULLDrr:
8661   case X86::VPMULLDYrr:
8662   case X86::VPMULLDZ128rr:
8663   case X86::VPMULLDZ256rr:
8664   case X86::VPMULLDZrr:
8665   case X86::VPMULLQZ128rr:
8666   case X86::VPMULLQZ256rr:
8667   case X86::VPMULLQZrr:
8668   case X86::VPMAXSBrr:
8669   case X86::VPMAXSBYrr:
8670   case X86::VPMAXSBZ128rr:
8671   case X86::VPMAXSBZ256rr:
8672   case X86::VPMAXSBZrr:
8673   case X86::VPMAXSDrr:
8674   case X86::VPMAXSDYrr:
8675   case X86::VPMAXSDZ128rr:
8676   case X86::VPMAXSDZ256rr:
8677   case X86::VPMAXSDZrr:
8678   case X86::VPMAXSQZ128rr:
8679   case X86::VPMAXSQZ256rr:
8680   case X86::VPMAXSQZrr:
8681   case X86::VPMAXSWrr:
8682   case X86::VPMAXSWYrr:
8683   case X86::VPMAXSWZ128rr:
8684   case X86::VPMAXSWZ256rr:
8685   case X86::VPMAXSWZrr:
8686   case X86::VPMAXUBrr:
8687   case X86::VPMAXUBYrr:
8688   case X86::VPMAXUBZ128rr:
8689   case X86::VPMAXUBZ256rr:
8690   case X86::VPMAXUBZrr:
8691   case X86::VPMAXUDrr:
8692   case X86::VPMAXUDYrr:
8693   case X86::VPMAXUDZ128rr:
8694   case X86::VPMAXUDZ256rr:
8695   case X86::VPMAXUDZrr:
8696   case X86::VPMAXUQZ128rr:
8697   case X86::VPMAXUQZ256rr:
8698   case X86::VPMAXUQZrr:
8699   case X86::VPMAXUWrr:
8700   case X86::VPMAXUWYrr:
8701   case X86::VPMAXUWZ128rr:
8702   case X86::VPMAXUWZ256rr:
8703   case X86::VPMAXUWZrr:
8704   case X86::VPMINSBrr:
8705   case X86::VPMINSBYrr:
8706   case X86::VPMINSBZ128rr:
8707   case X86::VPMINSBZ256rr:
8708   case X86::VPMINSBZrr:
8709   case X86::VPMINSDrr:
8710   case X86::VPMINSDYrr:
8711   case X86::VPMINSDZ128rr:
8712   case X86::VPMINSDZ256rr:
8713   case X86::VPMINSDZrr:
8714   case X86::VPMINSQZ128rr:
8715   case X86::VPMINSQZ256rr:
8716   case X86::VPMINSQZrr:
8717   case X86::VPMINSWrr:
8718   case X86::VPMINSWYrr:
8719   case X86::VPMINSWZ128rr:
8720   case X86::VPMINSWZ256rr:
8721   case X86::VPMINSWZrr:
8722   case X86::VPMINUBrr:
8723   case X86::VPMINUBYrr:
8724   case X86::VPMINUBZ128rr:
8725   case X86::VPMINUBZ256rr:
8726   case X86::VPMINUBZrr:
8727   case X86::VPMINUDrr:
8728   case X86::VPMINUDYrr:
8729   case X86::VPMINUDZ128rr:
8730   case X86::VPMINUDZ256rr:
8731   case X86::VPMINUDZrr:
8732   case X86::VPMINUQZ128rr:
8733   case X86::VPMINUQZ256rr:
8734   case X86::VPMINUQZrr:
8735   case X86::VPMINUWrr:
8736   case X86::VPMINUWYrr:
8737   case X86::VPMINUWZ128rr:
8738   case X86::VPMINUWZ256rr:
8739   case X86::VPMINUWZrr:
8740   // Normal min/max instructions are not commutative because of NaN and signed
8741   // zero semantics, but these are. Thus, there's no need to check for global
8742   // relaxed math; the instructions themselves have the properties we need.
8743   case X86::MAXCPDrr:
8744   case X86::MAXCPSrr:
8745   case X86::MAXCSDrr:
8746   case X86::MAXCSSrr:
8747   case X86::MINCPDrr:
8748   case X86::MINCPSrr:
8749   case X86::MINCSDrr:
8750   case X86::MINCSSrr:
8751   case X86::VMAXCPDrr:
8752   case X86::VMAXCPSrr:
8753   case X86::VMAXCPDYrr:
8754   case X86::VMAXCPSYrr:
8755   case X86::VMAXCPDZ128rr:
8756   case X86::VMAXCPSZ128rr:
8757   case X86::VMAXCPDZ256rr:
8758   case X86::VMAXCPSZ256rr:
8759   case X86::VMAXCPDZrr:
8760   case X86::VMAXCPSZrr:
8761   case X86::VMAXCSDrr:
8762   case X86::VMAXCSSrr:
8763   case X86::VMAXCSDZrr:
8764   case X86::VMAXCSSZrr:
8765   case X86::VMINCPDrr:
8766   case X86::VMINCPSrr:
8767   case X86::VMINCPDYrr:
8768   case X86::VMINCPSYrr:
8769   case X86::VMINCPDZ128rr:
8770   case X86::VMINCPSZ128rr:
8771   case X86::VMINCPDZ256rr:
8772   case X86::VMINCPSZ256rr:
8773   case X86::VMINCPDZrr:
8774   case X86::VMINCPSZrr:
8775   case X86::VMINCSDrr:
8776   case X86::VMINCSSrr:
8777   case X86::VMINCSDZrr:
8778   case X86::VMINCSSZrr:
8779   case X86::VMAXCPHZ128rr:
8780   case X86::VMAXCPHZ256rr:
8781   case X86::VMAXCPHZrr:
8782   case X86::VMAXCSHZrr:
8783   case X86::VMINCPHZ128rr:
8784   case X86::VMINCPHZ256rr:
8785   case X86::VMINCPHZrr:
8786   case X86::VMINCSHZrr:
8787     return true;
8788   case X86::ADDPDrr:
8789   case X86::ADDPSrr:
8790   case X86::ADDSDrr:
8791   case X86::ADDSSrr:
8792   case X86::MULPDrr:
8793   case X86::MULPSrr:
8794   case X86::MULSDrr:
8795   case X86::MULSSrr:
8796   case X86::VADDPDrr:
8797   case X86::VADDPSrr:
8798   case X86::VADDPDYrr:
8799   case X86::VADDPSYrr:
8800   case X86::VADDPDZ128rr:
8801   case X86::VADDPSZ128rr:
8802   case X86::VADDPDZ256rr:
8803   case X86::VADDPSZ256rr:
8804   case X86::VADDPDZrr:
8805   case X86::VADDPSZrr:
8806   case X86::VADDSDrr:
8807   case X86::VADDSSrr:
8808   case X86::VADDSDZrr:
8809   case X86::VADDSSZrr:
8810   case X86::VMULPDrr:
8811   case X86::VMULPSrr:
8812   case X86::VMULPDYrr:
8813   case X86::VMULPSYrr:
8814   case X86::VMULPDZ128rr:
8815   case X86::VMULPSZ128rr:
8816   case X86::VMULPDZ256rr:
8817   case X86::VMULPSZ256rr:
8818   case X86::VMULPDZrr:
8819   case X86::VMULPSZrr:
8820   case X86::VMULSDrr:
8821   case X86::VMULSSrr:
8822   case X86::VMULSDZrr:
8823   case X86::VMULSSZrr:
8824   case X86::VADDPHZ128rr:
8825   case X86::VADDPHZ256rr:
8826   case X86::VADDPHZrr:
8827   case X86::VADDSHZrr:
8828   case X86::VMULPHZ128rr:
8829   case X86::VMULPHZ256rr:
8830   case X86::VMULPHZrr:
8831   case X86::VMULSHZrr:
8832     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
8833            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
8834   default:
8835     return false;
8836   }
8837 }
8838 
8839 /// If \p DescribedReg overlaps with the MOVrr instruction's destination
8840 /// register then, if possible, describe the value in terms of the source
8841 /// register.
8842 static Optional<ParamLoadedValue>
8843 describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
8844                          const TargetRegisterInfo *TRI) {
8845   Register DestReg = MI.getOperand(0).getReg();
8846   Register SrcReg = MI.getOperand(1).getReg();
8847 
8848   auto Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8849 
8850   // If the described register is the destination, just return the source.
8851   if (DestReg == DescribedReg)
8852     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8853 
8854   // If the described register is a sub-register of the destination register,
8855   // then pick out the source register's corresponding sub-register.
8856   if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) {
8857     Register SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx);
8858     return ParamLoadedValue(MachineOperand::CreateReg(SrcSubReg, false), Expr);
8859   }
8860 
8861   // The remaining case to consider is when the described register is a
8862   // super-register of the destination register. MOV8rr and MOV16rr does not
8863   // write to any of the other bytes in the register, meaning that we'd have to
8864   // describe the value using a combination of the source register and the
8865   // non-overlapping bits in the described register, which is not currently
8866   // possible.
8867   if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
8868       !TRI->isSuperRegister(DestReg, DescribedReg))
8869     return None;
8870 
8871   assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
8872   return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8873 }
8874 
8875 Optional<ParamLoadedValue>
8876 X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
8877   const MachineOperand *Op = nullptr;
8878   DIExpression *Expr = nullptr;
8879 
8880   const TargetRegisterInfo *TRI = &getRegisterInfo();
8881 
8882   switch (MI.getOpcode()) {
8883   case X86::LEA32r:
8884   case X86::LEA64r:
8885   case X86::LEA64_32r: {
8886     // We may need to describe a 64-bit parameter with a 32-bit LEA.
8887     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8888       return None;
8889 
8890     // Operand 4 could be global address. For now we do not support
8891     // such situation.
8892     if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
8893       return None;
8894 
8895     const MachineOperand &Op1 = MI.getOperand(1);
8896     const MachineOperand &Op2 = MI.getOperand(3);
8897     assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
8898                            Register::isPhysicalRegister(Op2.getReg())));
8899 
8900     // Omit situations like:
8901     // %rsi = lea %rsi, 4, ...
8902     if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
8903         Op2.getReg() == MI.getOperand(0).getReg())
8904       return None;
8905     else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
8906               TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
8907              (Op2.getReg() != X86::NoRegister &&
8908               TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
8909       return None;
8910 
8911     int64_t Coef = MI.getOperand(2).getImm();
8912     int64_t Offset = MI.getOperand(4).getImm();
8913     SmallVector<uint64_t, 8> Ops;
8914 
8915     if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
8916       Op = &Op1;
8917     } else if (Op1.isFI())
8918       Op = &Op1;
8919 
8920     if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
8921       Ops.push_back(dwarf::DW_OP_constu);
8922       Ops.push_back(Coef + 1);
8923       Ops.push_back(dwarf::DW_OP_mul);
8924     } else {
8925       if (Op && Op2.getReg() != X86::NoRegister) {
8926         int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
8927         if (dwarfReg < 0)
8928           return None;
8929         else if (dwarfReg < 32) {
8930           Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
8931           Ops.push_back(0);
8932         } else {
8933           Ops.push_back(dwarf::DW_OP_bregx);
8934           Ops.push_back(dwarfReg);
8935           Ops.push_back(0);
8936         }
8937       } else if (!Op) {
8938         assert(Op2.getReg() != X86::NoRegister);
8939         Op = &Op2;
8940       }
8941 
8942       if (Coef > 1) {
8943         assert(Op2.getReg() != X86::NoRegister);
8944         Ops.push_back(dwarf::DW_OP_constu);
8945         Ops.push_back(Coef);
8946         Ops.push_back(dwarf::DW_OP_mul);
8947       }
8948 
8949       if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
8950           Op2.getReg() != X86::NoRegister) {
8951         Ops.push_back(dwarf::DW_OP_plus);
8952       }
8953     }
8954 
8955     DIExpression::appendOffset(Ops, Offset);
8956     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
8957 
8958     return ParamLoadedValue(*Op, Expr);;
8959   }
8960   case X86::MOV8ri:
8961   case X86::MOV16ri:
8962     // TODO: Handle MOV8ri and MOV16ri.
8963     return None;
8964   case X86::MOV32ri:
8965   case X86::MOV64ri:
8966   case X86::MOV64ri32:
8967     // MOV32ri may be used for producing zero-extended 32-bit immediates in
8968     // 64-bit parameters, so we need to consider super-registers.
8969     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8970       return None;
8971     return ParamLoadedValue(MI.getOperand(1), Expr);
8972   case X86::MOV8rr:
8973   case X86::MOV16rr:
8974   case X86::MOV32rr:
8975   case X86::MOV64rr:
8976     return describeMOVrrLoadedValue(MI, Reg, TRI);
8977   case X86::XOR32rr: {
8978     // 64-bit parameters are zero-materialized using XOR32rr, so also consider
8979     // super-registers.
8980     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8981       return None;
8982     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
8983       return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
8984     return None;
8985   }
8986   case X86::MOVSX64rr32: {
8987     // We may need to describe the lower 32 bits of the MOVSX; for example, in
8988     // cases like this:
8989     //
8990     //  $ebx = [...]
8991     //  $rdi = MOVSX64rr32 $ebx
8992     //  $esi = MOV32rr $edi
8993     if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg))
8994       return None;
8995 
8996     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8997 
8998     // If the described register is the destination register we need to
8999     // sign-extend the source register from 32 bits. The other case we handle
9000     // is when the described register is the 32-bit sub-register of the
9001     // destination register, in case we just need to return the source
9002     // register.
9003     if (Reg == MI.getOperand(0).getReg())
9004       Expr = DIExpression::appendExt(Expr, 32, 64, true);
9005     else
9006       assert(X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg) &&
9007              "Unhandled sub-register case for MOVSX64rr32");
9008 
9009     return ParamLoadedValue(MI.getOperand(1), Expr);
9010   }
9011   default:
9012     assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
9013     return TargetInstrInfo::describeLoadedValue(MI, Reg);
9014   }
9015 }
9016 
9017 /// This is an architecture-specific helper function of reassociateOps.
9018 /// Set special operand attributes for new instructions after reassociation.
9019 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
9020                                          MachineInstr &OldMI2,
9021                                          MachineInstr &NewMI1,
9022                                          MachineInstr &NewMI2) const {
9023   // Propagate FP flags from the original instructions.
9024   // But clear poison-generating flags because those may not be valid now.
9025   // TODO: There should be a helper function for copying only fast-math-flags.
9026   uint16_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
9027   NewMI1.setFlags(IntersectedFlags);
9028   NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
9029   NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
9030   NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
9031 
9032   NewMI2.setFlags(IntersectedFlags);
9033   NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
9034   NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
9035   NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
9036 
9037   // Integer instructions may define an implicit EFLAGS dest register operand.
9038   MachineOperand *OldFlagDef1 = OldMI1.findRegisterDefOperand(X86::EFLAGS);
9039   MachineOperand *OldFlagDef2 = OldMI2.findRegisterDefOperand(X86::EFLAGS);
9040 
9041   assert(!OldFlagDef1 == !OldFlagDef2 &&
9042          "Unexpected instruction type for reassociation");
9043 
9044   if (!OldFlagDef1 || !OldFlagDef2)
9045     return;
9046 
9047   assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
9048          "Must have dead EFLAGS operand in reassociable instruction");
9049 
9050   MachineOperand *NewFlagDef1 = NewMI1.findRegisterDefOperand(X86::EFLAGS);
9051   MachineOperand *NewFlagDef2 = NewMI2.findRegisterDefOperand(X86::EFLAGS);
9052 
9053   assert(NewFlagDef1 && NewFlagDef2 &&
9054          "Unexpected operand in reassociable instruction");
9055 
9056   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
9057   // of this pass or other passes. The EFLAGS operands must be dead in these new
9058   // instructions because the EFLAGS operands in the original instructions must
9059   // be dead in order for reassociation to occur.
9060   NewFlagDef1->setIsDead();
9061   NewFlagDef2->setIsDead();
9062 }
9063 
9064 std::pair<unsigned, unsigned>
9065 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
9066   return std::make_pair(TF, 0u);
9067 }
9068 
9069 ArrayRef<std::pair<unsigned, const char *>>
9070 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
9071   using namespace X86II;
9072   static const std::pair<unsigned, const char *> TargetFlags[] = {
9073       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
9074       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
9075       {MO_GOT, "x86-got"},
9076       {MO_GOTOFF, "x86-gotoff"},
9077       {MO_GOTPCREL, "x86-gotpcrel"},
9078       {MO_GOTPCREL_NORELAX, "x86-gotpcrel-norelax"},
9079       {MO_PLT, "x86-plt"},
9080       {MO_TLSGD, "x86-tlsgd"},
9081       {MO_TLSLD, "x86-tlsld"},
9082       {MO_TLSLDM, "x86-tlsldm"},
9083       {MO_GOTTPOFF, "x86-gottpoff"},
9084       {MO_INDNTPOFF, "x86-indntpoff"},
9085       {MO_TPOFF, "x86-tpoff"},
9086       {MO_DTPOFF, "x86-dtpoff"},
9087       {MO_NTPOFF, "x86-ntpoff"},
9088       {MO_GOTNTPOFF, "x86-gotntpoff"},
9089       {MO_DLLIMPORT, "x86-dllimport"},
9090       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
9091       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
9092       {MO_TLVP, "x86-tlvp"},
9093       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
9094       {MO_SECREL, "x86-secrel"},
9095       {MO_COFFSTUB, "x86-coffstub"}};
9096   return makeArrayRef(TargetFlags);
9097 }
9098 
9099 namespace {
9100   /// Create Global Base Reg pass. This initializes the PIC
9101   /// global base register for x86-32.
9102   struct CGBR : public MachineFunctionPass {
9103     static char ID;
9104     CGBR() : MachineFunctionPass(ID) {}
9105 
9106     bool runOnMachineFunction(MachineFunction &MF) override {
9107       const X86TargetMachine *TM =
9108         static_cast<const X86TargetMachine *>(&MF.getTarget());
9109       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
9110 
9111       // Don't do anything in the 64-bit small and kernel code models. They use
9112       // RIP-relative addressing for everything.
9113       if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
9114                             TM->getCodeModel() == CodeModel::Kernel))
9115         return false;
9116 
9117       // Only emit a global base reg in PIC mode.
9118       if (!TM->isPositionIndependent())
9119         return false;
9120 
9121       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
9122       Register GlobalBaseReg = X86FI->getGlobalBaseReg();
9123 
9124       // If we didn't need a GlobalBaseReg, don't insert code.
9125       if (GlobalBaseReg == 0)
9126         return false;
9127 
9128       // Insert the set of GlobalBaseReg into the first MBB of the function
9129       MachineBasicBlock &FirstMBB = MF.front();
9130       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
9131       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
9132       MachineRegisterInfo &RegInfo = MF.getRegInfo();
9133       const X86InstrInfo *TII = STI.getInstrInfo();
9134 
9135       Register PC;
9136       if (STI.isPICStyleGOT())
9137         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
9138       else
9139         PC = GlobalBaseReg;
9140 
9141       if (STI.is64Bit()) {
9142         if (TM->getCodeModel() == CodeModel::Medium) {
9143           // In the medium code model, use a RIP-relative LEA to materialize the
9144           // GOT.
9145           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
9146               .addReg(X86::RIP)
9147               .addImm(0)
9148               .addReg(0)
9149               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
9150               .addReg(0);
9151         } else if (TM->getCodeModel() == CodeModel::Large) {
9152           // In the large code model, we are aiming for this code, though the
9153           // register allocation may vary:
9154           //   leaq .LN$pb(%rip), %rax
9155           //   movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
9156           //   addq %rcx, %rax
9157           // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
9158           Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
9159           Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
9160           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
9161               .addReg(X86::RIP)
9162               .addImm(0)
9163               .addReg(0)
9164               .addSym(MF.getPICBaseSymbol())
9165               .addReg(0);
9166           std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
9167           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
9168               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
9169                                  X86II::MO_PIC_BASE_OFFSET);
9170           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
9171               .addReg(PBReg, RegState::Kill)
9172               .addReg(GOTReg, RegState::Kill);
9173         } else {
9174           llvm_unreachable("unexpected code model");
9175         }
9176       } else {
9177         // Operand of MovePCtoStack is completely ignored by asm printer. It's
9178         // only used in JIT code emission as displacement to pc.
9179         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
9180 
9181         // If we're using vanilla 'GOT' PIC style, we should use relative
9182         // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
9183         if (STI.isPICStyleGOT()) {
9184           // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
9185           // %some_register
9186           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
9187               .addReg(PC)
9188               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
9189                                  X86II::MO_GOT_ABSOLUTE_ADDRESS);
9190         }
9191       }
9192 
9193       return true;
9194     }
9195 
9196     StringRef getPassName() const override {
9197       return "X86 PIC Global Base Reg Initialization";
9198     }
9199 
9200     void getAnalysisUsage(AnalysisUsage &AU) const override {
9201       AU.setPreservesCFG();
9202       MachineFunctionPass::getAnalysisUsage(AU);
9203     }
9204   };
9205 } // namespace
9206 
9207 char CGBR::ID = 0;
9208 FunctionPass*
9209 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
9210 
9211 namespace {
9212   struct LDTLSCleanup : public MachineFunctionPass {
9213     static char ID;
9214     LDTLSCleanup() : MachineFunctionPass(ID) {}
9215 
9216     bool runOnMachineFunction(MachineFunction &MF) override {
9217       if (skipFunction(MF.getFunction()))
9218         return false;
9219 
9220       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
9221       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
9222         // No point folding accesses if there isn't at least two.
9223         return false;
9224       }
9225 
9226       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
9227       return VisitNode(DT->getRootNode(), 0);
9228     }
9229 
9230     // Visit the dominator subtree rooted at Node in pre-order.
9231     // If TLSBaseAddrReg is non-null, then use that to replace any
9232     // TLS_base_addr instructions. Otherwise, create the register
9233     // when the first such instruction is seen, and then use it
9234     // as we encounter more instructions.
9235     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
9236       MachineBasicBlock *BB = Node->getBlock();
9237       bool Changed = false;
9238 
9239       // Traverse the current block.
9240       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
9241            ++I) {
9242         switch (I->getOpcode()) {
9243           case X86::TLS_base_addr32:
9244           case X86::TLS_base_addr64:
9245             if (TLSBaseAddrReg)
9246               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
9247             else
9248               I = SetRegister(*I, &TLSBaseAddrReg);
9249             Changed = true;
9250             break;
9251           default:
9252             break;
9253         }
9254       }
9255 
9256       // Visit the children of this block in the dominator tree.
9257       for (auto I = Node->begin(), E = Node->end(); I != E; ++I) {
9258         Changed |= VisitNode(*I, TLSBaseAddrReg);
9259       }
9260 
9261       return Changed;
9262     }
9263 
9264     // Replace the TLS_base_addr instruction I with a copy from
9265     // TLSBaseAddrReg, returning the new instruction.
9266     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
9267                                          unsigned TLSBaseAddrReg) {
9268       MachineFunction *MF = I.getParent()->getParent();
9269       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
9270       const bool is64Bit = STI.is64Bit();
9271       const X86InstrInfo *TII = STI.getInstrInfo();
9272 
9273       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
9274       MachineInstr *Copy =
9275           BuildMI(*I.getParent(), I, I.getDebugLoc(),
9276                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
9277               .addReg(TLSBaseAddrReg);
9278 
9279       // Erase the TLS_base_addr instruction.
9280       I.eraseFromParent();
9281 
9282       return Copy;
9283     }
9284 
9285     // Create a virtual register in *TLSBaseAddrReg, and populate it by
9286     // inserting a copy instruction after I. Returns the new instruction.
9287     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
9288       MachineFunction *MF = I.getParent()->getParent();
9289       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
9290       const bool is64Bit = STI.is64Bit();
9291       const X86InstrInfo *TII = STI.getInstrInfo();
9292 
9293       // Create a virtual register for the TLS base address.
9294       MachineRegisterInfo &RegInfo = MF->getRegInfo();
9295       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
9296                                                       ? &X86::GR64RegClass
9297                                                       : &X86::GR32RegClass);
9298 
9299       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
9300       MachineInstr *Next = I.getNextNode();
9301       MachineInstr *Copy =
9302           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
9303                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
9304               .addReg(is64Bit ? X86::RAX : X86::EAX);
9305 
9306       return Copy;
9307     }
9308 
9309     StringRef getPassName() const override {
9310       return "Local Dynamic TLS Access Clean-up";
9311     }
9312 
9313     void getAnalysisUsage(AnalysisUsage &AU) const override {
9314       AU.setPreservesCFG();
9315       AU.addRequired<MachineDominatorTree>();
9316       MachineFunctionPass::getAnalysisUsage(AU);
9317     }
9318   };
9319 }
9320 
9321 char LDTLSCleanup::ID = 0;
9322 FunctionPass*
9323 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
9324 
9325 /// Constants defining how certain sequences should be outlined.
9326 ///
9327 /// \p MachineOutlinerDefault implies that the function is called with a call
9328 /// instruction, and a return must be emitted for the outlined function frame.
9329 ///
9330 /// That is,
9331 ///
9332 /// I1                                 OUTLINED_FUNCTION:
9333 /// I2 --> call OUTLINED_FUNCTION       I1
9334 /// I3                                  I2
9335 ///                                     I3
9336 ///                                     ret
9337 ///
9338 /// * Call construction overhead: 1 (call instruction)
9339 /// * Frame construction overhead: 1 (return instruction)
9340 ///
9341 /// \p MachineOutlinerTailCall implies that the function is being tail called.
9342 /// A jump is emitted instead of a call, and the return is already present in
9343 /// the outlined sequence. That is,
9344 ///
9345 /// I1                                 OUTLINED_FUNCTION:
9346 /// I2 --> jmp OUTLINED_FUNCTION       I1
9347 /// ret                                I2
9348 ///                                    ret
9349 ///
9350 /// * Call construction overhead: 1 (jump instruction)
9351 /// * Frame construction overhead: 0 (don't need to return)
9352 ///
9353 enum MachineOutlinerClass {
9354   MachineOutlinerDefault,
9355   MachineOutlinerTailCall
9356 };
9357 
9358 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
9359     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
9360   unsigned SequenceSize =
9361       std::accumulate(RepeatedSequenceLocs[0].front(),
9362                       std::next(RepeatedSequenceLocs[0].back()), 0,
9363                       [](unsigned Sum, const MachineInstr &MI) {
9364                         // FIXME: x86 doesn't implement getInstSizeInBytes, so
9365                         // we can't tell the cost.  Just assume each instruction
9366                         // is one byte.
9367                         if (MI.isDebugInstr() || MI.isKill())
9368                           return Sum;
9369                         return Sum + 1;
9370                       });
9371 
9372   // We check to see if CFI Instructions are present, and if they are
9373   // we find the number of CFI Instructions in the candidates.
9374   unsigned CFICount = 0;
9375   MachineBasicBlock::iterator MBBI = RepeatedSequenceLocs[0].front();
9376   for (unsigned Loc = RepeatedSequenceLocs[0].getStartIdx();
9377        Loc < RepeatedSequenceLocs[0].getEndIdx() + 1; Loc++) {
9378     if (MBBI->isCFIInstruction())
9379       CFICount++;
9380     MBBI++;
9381   }
9382 
9383   // We compare the number of found CFI Instructions to  the number of CFI
9384   // instructions in the parent function for each candidate.  We must check this
9385   // since if we outline one of the CFI instructions in a function, we have to
9386   // outline them all for correctness. If we do not, the address offsets will be
9387   // incorrect between the two sections of the program.
9388   for (outliner::Candidate &C : RepeatedSequenceLocs) {
9389     std::vector<MCCFIInstruction> CFIInstructions =
9390         C.getMF()->getFrameInstructions();
9391 
9392     if (CFICount > 0 && CFICount != CFIInstructions.size())
9393       return outliner::OutlinedFunction();
9394   }
9395 
9396   // FIXME: Use real size in bytes for call and ret instructions.
9397   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
9398     for (outliner::Candidate &C : RepeatedSequenceLocs)
9399       C.setCallInfo(MachineOutlinerTailCall, 1);
9400 
9401     return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
9402                                       0, // Number of bytes to emit frame.
9403                                       MachineOutlinerTailCall // Type of frame.
9404     );
9405   }
9406 
9407   if (CFICount > 0)
9408     return outliner::OutlinedFunction();
9409 
9410   for (outliner::Candidate &C : RepeatedSequenceLocs)
9411     C.setCallInfo(MachineOutlinerDefault, 1);
9412 
9413   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
9414                                     MachineOutlinerDefault);
9415 }
9416 
9417 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
9418                                            bool OutlineFromLinkOnceODRs) const {
9419   const Function &F = MF.getFunction();
9420 
9421   // Does the function use a red zone? If it does, then we can't risk messing
9422   // with the stack.
9423   if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
9424     // It could have a red zone. If it does, then we don't want to touch it.
9425     const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
9426     if (!X86FI || X86FI->getUsesRedZone())
9427       return false;
9428   }
9429 
9430   // If we *don't* want to outline from things that could potentially be deduped
9431   // then return false.
9432   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
9433       return false;
9434 
9435   // This function is viable for outlining, so return true.
9436   return true;
9437 }
9438 
9439 outliner::InstrType
9440 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  unsigned Flags) const {
9441   MachineInstr &MI = *MIT;
9442   // Don't allow debug values to impact outlining type.
9443   if (MI.isDebugInstr() || MI.isIndirectDebugValue())
9444     return outliner::InstrType::Invisible;
9445 
9446   // At this point, KILL instructions don't really tell us much so we can go
9447   // ahead and skip over them.
9448   if (MI.isKill())
9449     return outliner::InstrType::Invisible;
9450 
9451   // Is this a tail call? If yes, we can outline as a tail call.
9452   if (isTailCall(MI))
9453     return outliner::InstrType::Legal;
9454 
9455   // Is this the terminator of a basic block?
9456   if (MI.isTerminator() || MI.isReturn()) {
9457 
9458     // Does its parent have any successors in its MachineFunction?
9459     if (MI.getParent()->succ_empty())
9460       return outliner::InstrType::Legal;
9461 
9462     // It does, so we can't tail call it.
9463     return outliner::InstrType::Illegal;
9464   }
9465 
9466   // Don't outline anything that modifies or reads from the stack pointer.
9467   //
9468   // FIXME: There are instructions which are being manually built without
9469   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
9470   // able to remove the extra checks once those are fixed up. For example,
9471   // sometimes we might get something like %rax = POP64r 1. This won't be
9472   // caught by modifiesRegister or readsRegister even though the instruction
9473   // really ought to be formed so that modifiesRegister/readsRegister would
9474   // catch it.
9475   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
9476       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
9477       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
9478     return outliner::InstrType::Illegal;
9479 
9480   // Outlined calls change the instruction pointer, so don't read from it.
9481   if (MI.readsRegister(X86::RIP, &RI) ||
9482       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
9483       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
9484     return outliner::InstrType::Illegal;
9485 
9486   // Positions can't safely be outlined.
9487   if (MI.isPosition())
9488     return outliner::InstrType::Illegal;
9489 
9490   // Make sure none of the operands of this instruction do anything tricky.
9491   for (const MachineOperand &MOP : MI.operands())
9492     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
9493         MOP.isTargetIndex())
9494       return outliner::InstrType::Illegal;
9495 
9496   return outliner::InstrType::Legal;
9497 }
9498 
9499 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
9500                                           MachineFunction &MF,
9501                                           const outliner::OutlinedFunction &OF)
9502                                           const {
9503   // If we're a tail call, we already have a return, so don't do anything.
9504   if (OF.FrameConstructionID == MachineOutlinerTailCall)
9505     return;
9506 
9507   // We're a normal call, so our sequence doesn't have a return instruction.
9508   // Add it in.
9509   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RET64));
9510   MBB.insert(MBB.end(), retq);
9511 }
9512 
9513 MachineBasicBlock::iterator
9514 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
9515                                  MachineBasicBlock::iterator &It,
9516                                  MachineFunction &MF,
9517                                  outliner::Candidate &C) const {
9518   // Is it a tail call?
9519   if (C.CallConstructionID == MachineOutlinerTailCall) {
9520     // Yes, just insert a JMP.
9521     It = MBB.insert(It,
9522                   BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
9523                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9524   } else {
9525     // No, insert a call.
9526     It = MBB.insert(It,
9527                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
9528                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9529   }
9530 
9531   return It;
9532 }
9533 
9534 #define GET_INSTRINFO_HELPERS
9535 #include "X86GenInstrInfo.inc"
9536