1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Target/TargetAsmInfo.h"
35 using namespace llvm;
36 
37 namespace {
38   cl::opt<bool>
39   NoFusing("disable-spill-fusing",
40            cl::desc("Disable fusing of spill code into instructions"));
41   cl::opt<bool>
42   PrintFailedFusing("print-failed-fuse-candidates",
43                     cl::desc("Print instructions that the allocator wants to"
44                              " fuse, but the X86 backend currently can't"),
45                     cl::Hidden);
46   cl::opt<bool>
47   ReMatPICStubLoad("remat-pic-stub-load",
48                    cl::desc("Re-materialize load from stub in PIC mode"),
49                    cl::init(false), cl::Hidden);
50 }
51 
52 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
53   : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
54     TM(tm), RI(tm, *this) {
55   SmallVector<unsigned,16> AmbEntries;
56   static const unsigned OpTbl2Addr[][2] = {
57     { X86::ADC32ri,     X86::ADC32mi },
58     { X86::ADC32ri8,    X86::ADC32mi8 },
59     { X86::ADC32rr,     X86::ADC32mr },
60     { X86::ADC64ri32,   X86::ADC64mi32 },
61     { X86::ADC64ri8,    X86::ADC64mi8 },
62     { X86::ADC64rr,     X86::ADC64mr },
63     { X86::ADD16ri,     X86::ADD16mi },
64     { X86::ADD16ri8,    X86::ADD16mi8 },
65     { X86::ADD16rr,     X86::ADD16mr },
66     { X86::ADD32ri,     X86::ADD32mi },
67     { X86::ADD32ri8,    X86::ADD32mi8 },
68     { X86::ADD32rr,     X86::ADD32mr },
69     { X86::ADD64ri32,   X86::ADD64mi32 },
70     { X86::ADD64ri8,    X86::ADD64mi8 },
71     { X86::ADD64rr,     X86::ADD64mr },
72     { X86::ADD8ri,      X86::ADD8mi },
73     { X86::ADD8rr,      X86::ADD8mr },
74     { X86::AND16ri,     X86::AND16mi },
75     { X86::AND16ri8,    X86::AND16mi8 },
76     { X86::AND16rr,     X86::AND16mr },
77     { X86::AND32ri,     X86::AND32mi },
78     { X86::AND32ri8,    X86::AND32mi8 },
79     { X86::AND32rr,     X86::AND32mr },
80     { X86::AND64ri32,   X86::AND64mi32 },
81     { X86::AND64ri8,    X86::AND64mi8 },
82     { X86::AND64rr,     X86::AND64mr },
83     { X86::AND8ri,      X86::AND8mi },
84     { X86::AND8rr,      X86::AND8mr },
85     { X86::DEC16r,      X86::DEC16m },
86     { X86::DEC32r,      X86::DEC32m },
87     { X86::DEC64_16r,   X86::DEC64_16m },
88     { X86::DEC64_32r,   X86::DEC64_32m },
89     { X86::DEC64r,      X86::DEC64m },
90     { X86::DEC8r,       X86::DEC8m },
91     { X86::INC16r,      X86::INC16m },
92     { X86::INC32r,      X86::INC32m },
93     { X86::INC64_16r,   X86::INC64_16m },
94     { X86::INC64_32r,   X86::INC64_32m },
95     { X86::INC64r,      X86::INC64m },
96     { X86::INC8r,       X86::INC8m },
97     { X86::NEG16r,      X86::NEG16m },
98     { X86::NEG32r,      X86::NEG32m },
99     { X86::NEG64r,      X86::NEG64m },
100     { X86::NEG8r,       X86::NEG8m },
101     { X86::NOT16r,      X86::NOT16m },
102     { X86::NOT32r,      X86::NOT32m },
103     { X86::NOT64r,      X86::NOT64m },
104     { X86::NOT8r,       X86::NOT8m },
105     { X86::OR16ri,      X86::OR16mi },
106     { X86::OR16ri8,     X86::OR16mi8 },
107     { X86::OR16rr,      X86::OR16mr },
108     { X86::OR32ri,      X86::OR32mi },
109     { X86::OR32ri8,     X86::OR32mi8 },
110     { X86::OR32rr,      X86::OR32mr },
111     { X86::OR64ri32,    X86::OR64mi32 },
112     { X86::OR64ri8,     X86::OR64mi8 },
113     { X86::OR64rr,      X86::OR64mr },
114     { X86::OR8ri,       X86::OR8mi },
115     { X86::OR8rr,       X86::OR8mr },
116     { X86::ROL16r1,     X86::ROL16m1 },
117     { X86::ROL16rCL,    X86::ROL16mCL },
118     { X86::ROL16ri,     X86::ROL16mi },
119     { X86::ROL32r1,     X86::ROL32m1 },
120     { X86::ROL32rCL,    X86::ROL32mCL },
121     { X86::ROL32ri,     X86::ROL32mi },
122     { X86::ROL64r1,     X86::ROL64m1 },
123     { X86::ROL64rCL,    X86::ROL64mCL },
124     { X86::ROL64ri,     X86::ROL64mi },
125     { X86::ROL8r1,      X86::ROL8m1 },
126     { X86::ROL8rCL,     X86::ROL8mCL },
127     { X86::ROL8ri,      X86::ROL8mi },
128     { X86::ROR16r1,     X86::ROR16m1 },
129     { X86::ROR16rCL,    X86::ROR16mCL },
130     { X86::ROR16ri,     X86::ROR16mi },
131     { X86::ROR32r1,     X86::ROR32m1 },
132     { X86::ROR32rCL,    X86::ROR32mCL },
133     { X86::ROR32ri,     X86::ROR32mi },
134     { X86::ROR64r1,     X86::ROR64m1 },
135     { X86::ROR64rCL,    X86::ROR64mCL },
136     { X86::ROR64ri,     X86::ROR64mi },
137     { X86::ROR8r1,      X86::ROR8m1 },
138     { X86::ROR8rCL,     X86::ROR8mCL },
139     { X86::ROR8ri,      X86::ROR8mi },
140     { X86::SAR16r1,     X86::SAR16m1 },
141     { X86::SAR16rCL,    X86::SAR16mCL },
142     { X86::SAR16ri,     X86::SAR16mi },
143     { X86::SAR32r1,     X86::SAR32m1 },
144     { X86::SAR32rCL,    X86::SAR32mCL },
145     { X86::SAR32ri,     X86::SAR32mi },
146     { X86::SAR64r1,     X86::SAR64m1 },
147     { X86::SAR64rCL,    X86::SAR64mCL },
148     { X86::SAR64ri,     X86::SAR64mi },
149     { X86::SAR8r1,      X86::SAR8m1 },
150     { X86::SAR8rCL,     X86::SAR8mCL },
151     { X86::SAR8ri,      X86::SAR8mi },
152     { X86::SBB32ri,     X86::SBB32mi },
153     { X86::SBB32ri8,    X86::SBB32mi8 },
154     { X86::SBB32rr,     X86::SBB32mr },
155     { X86::SBB64ri32,   X86::SBB64mi32 },
156     { X86::SBB64ri8,    X86::SBB64mi8 },
157     { X86::SBB64rr,     X86::SBB64mr },
158     { X86::SHL16rCL,    X86::SHL16mCL },
159     { X86::SHL16ri,     X86::SHL16mi },
160     { X86::SHL32rCL,    X86::SHL32mCL },
161     { X86::SHL32ri,     X86::SHL32mi },
162     { X86::SHL64rCL,    X86::SHL64mCL },
163     { X86::SHL64ri,     X86::SHL64mi },
164     { X86::SHL8rCL,     X86::SHL8mCL },
165     { X86::SHL8ri,      X86::SHL8mi },
166     { X86::SHLD16rrCL,  X86::SHLD16mrCL },
167     { X86::SHLD16rri8,  X86::SHLD16mri8 },
168     { X86::SHLD32rrCL,  X86::SHLD32mrCL },
169     { X86::SHLD32rri8,  X86::SHLD32mri8 },
170     { X86::SHLD64rrCL,  X86::SHLD64mrCL },
171     { X86::SHLD64rri8,  X86::SHLD64mri8 },
172     { X86::SHR16r1,     X86::SHR16m1 },
173     { X86::SHR16rCL,    X86::SHR16mCL },
174     { X86::SHR16ri,     X86::SHR16mi },
175     { X86::SHR32r1,     X86::SHR32m1 },
176     { X86::SHR32rCL,    X86::SHR32mCL },
177     { X86::SHR32ri,     X86::SHR32mi },
178     { X86::SHR64r1,     X86::SHR64m1 },
179     { X86::SHR64rCL,    X86::SHR64mCL },
180     { X86::SHR64ri,     X86::SHR64mi },
181     { X86::SHR8r1,      X86::SHR8m1 },
182     { X86::SHR8rCL,     X86::SHR8mCL },
183     { X86::SHR8ri,      X86::SHR8mi },
184     { X86::SHRD16rrCL,  X86::SHRD16mrCL },
185     { X86::SHRD16rri8,  X86::SHRD16mri8 },
186     { X86::SHRD32rrCL,  X86::SHRD32mrCL },
187     { X86::SHRD32rri8,  X86::SHRD32mri8 },
188     { X86::SHRD64rrCL,  X86::SHRD64mrCL },
189     { X86::SHRD64rri8,  X86::SHRD64mri8 },
190     { X86::SUB16ri,     X86::SUB16mi },
191     { X86::SUB16ri8,    X86::SUB16mi8 },
192     { X86::SUB16rr,     X86::SUB16mr },
193     { X86::SUB32ri,     X86::SUB32mi },
194     { X86::SUB32ri8,    X86::SUB32mi8 },
195     { X86::SUB32rr,     X86::SUB32mr },
196     { X86::SUB64ri32,   X86::SUB64mi32 },
197     { X86::SUB64ri8,    X86::SUB64mi8 },
198     { X86::SUB64rr,     X86::SUB64mr },
199     { X86::SUB8ri,      X86::SUB8mi },
200     { X86::SUB8rr,      X86::SUB8mr },
201     { X86::XOR16ri,     X86::XOR16mi },
202     { X86::XOR16ri8,    X86::XOR16mi8 },
203     { X86::XOR16rr,     X86::XOR16mr },
204     { X86::XOR32ri,     X86::XOR32mi },
205     { X86::XOR32ri8,    X86::XOR32mi8 },
206     { X86::XOR32rr,     X86::XOR32mr },
207     { X86::XOR64ri32,   X86::XOR64mi32 },
208     { X86::XOR64ri8,    X86::XOR64mi8 },
209     { X86::XOR64rr,     X86::XOR64mr },
210     { X86::XOR8ri,      X86::XOR8mi },
211     { X86::XOR8rr,      X86::XOR8mr }
212   };
213 
214   for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
215     unsigned RegOp = OpTbl2Addr[i][0];
216     unsigned MemOp = OpTbl2Addr[i][1];
217     if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
218                                                std::make_pair(MemOp,0))).second)
219       assert(false && "Duplicated entries?");
220     // Index 0, folded load and store, no alignment requirement.
221     unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
222     if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
223                                                 std::make_pair(RegOp,
224                                                               AuxInfo))).second)
225       AmbEntries.push_back(MemOp);
226   }
227 
228   // If the third value is 1, then it's folding either a load or a store.
229   static const unsigned OpTbl0[][4] = {
230     { X86::BT16ri8,     X86::BT16mi8, 1, 0 },
231     { X86::BT32ri8,     X86::BT32mi8, 1, 0 },
232     { X86::BT64ri8,     X86::BT64mi8, 1, 0 },
233     { X86::CALL32r,     X86::CALL32m, 1, 0 },
234     { X86::CALL64r,     X86::CALL64m, 1, 0 },
235     { X86::CMP16ri,     X86::CMP16mi, 1, 0 },
236     { X86::CMP16ri8,    X86::CMP16mi8, 1, 0 },
237     { X86::CMP16rr,     X86::CMP16mr, 1, 0 },
238     { X86::CMP32ri,     X86::CMP32mi, 1, 0 },
239     { X86::CMP32ri8,    X86::CMP32mi8, 1, 0 },
240     { X86::CMP32rr,     X86::CMP32mr, 1, 0 },
241     { X86::CMP64ri32,   X86::CMP64mi32, 1, 0 },
242     { X86::CMP64ri8,    X86::CMP64mi8, 1, 0 },
243     { X86::CMP64rr,     X86::CMP64mr, 1, 0 },
244     { X86::CMP8ri,      X86::CMP8mi, 1, 0 },
245     { X86::CMP8rr,      X86::CMP8mr, 1, 0 },
246     { X86::DIV16r,      X86::DIV16m, 1, 0 },
247     { X86::DIV32r,      X86::DIV32m, 1, 0 },
248     { X86::DIV64r,      X86::DIV64m, 1, 0 },
249     { X86::DIV8r,       X86::DIV8m, 1, 0 },
250     { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
251     { X86::FsMOVAPDrr,  X86::MOVSDmr, 0, 0 },
252     { X86::FsMOVAPSrr,  X86::MOVSSmr, 0, 0 },
253     { X86::IDIV16r,     X86::IDIV16m, 1, 0 },
254     { X86::IDIV32r,     X86::IDIV32m, 1, 0 },
255     { X86::IDIV64r,     X86::IDIV64m, 1, 0 },
256     { X86::IDIV8r,      X86::IDIV8m, 1, 0 },
257     { X86::IMUL16r,     X86::IMUL16m, 1, 0 },
258     { X86::IMUL32r,     X86::IMUL32m, 1, 0 },
259     { X86::IMUL64r,     X86::IMUL64m, 1, 0 },
260     { X86::IMUL8r,      X86::IMUL8m, 1, 0 },
261     { X86::JMP32r,      X86::JMP32m, 1, 0 },
262     { X86::JMP64r,      X86::JMP64m, 1, 0 },
263     { X86::MOV16ri,     X86::MOV16mi, 0, 0 },
264     { X86::MOV16rr,     X86::MOV16mr, 0, 0 },
265     { X86::MOV32ri,     X86::MOV32mi, 0, 0 },
266     { X86::MOV32rr,     X86::MOV32mr, 0, 0 },
267     { X86::MOV64ri32,   X86::MOV64mi32, 0, 0 },
268     { X86::MOV64rr,     X86::MOV64mr, 0, 0 },
269     { X86::MOV8ri,      X86::MOV8mi, 0, 0 },
270     { X86::MOV8rr,      X86::MOV8mr, 0, 0 },
271     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
272     { X86::MOVAPDrr,    X86::MOVAPDmr, 0, 16 },
273     { X86::MOVAPSrr,    X86::MOVAPSmr, 0, 16 },
274     { X86::MOVDQArr,    X86::MOVDQAmr, 0, 16 },
275     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
276     { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
277     { X86::MOVPS2SSrr,  X86::MOVPS2SSmr, 0, 0 },
278     { X86::MOVSDrr,     X86::MOVSDmr, 0, 0 },
279     { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
280     { X86::MOVSS2DIrr,  X86::MOVSS2DImr, 0, 0 },
281     { X86::MOVSSrr,     X86::MOVSSmr, 0, 0 },
282     { X86::MOVUPDrr,    X86::MOVUPDmr, 0, 0 },
283     { X86::MOVUPSrr,    X86::MOVUPSmr, 0, 0 },
284     { X86::MUL16r,      X86::MUL16m, 1, 0 },
285     { X86::MUL32r,      X86::MUL32m, 1, 0 },
286     { X86::MUL64r,      X86::MUL64m, 1, 0 },
287     { X86::MUL8r,       X86::MUL8m, 1, 0 },
288     { X86::SETAEr,      X86::SETAEm, 0, 0 },
289     { X86::SETAr,       X86::SETAm, 0, 0 },
290     { X86::SETBEr,      X86::SETBEm, 0, 0 },
291     { X86::SETBr,       X86::SETBm, 0, 0 },
292     { X86::SETEr,       X86::SETEm, 0, 0 },
293     { X86::SETGEr,      X86::SETGEm, 0, 0 },
294     { X86::SETGr,       X86::SETGm, 0, 0 },
295     { X86::SETLEr,      X86::SETLEm, 0, 0 },
296     { X86::SETLr,       X86::SETLm, 0, 0 },
297     { X86::SETNEr,      X86::SETNEm, 0, 0 },
298     { X86::SETNOr,      X86::SETNOm, 0, 0 },
299     { X86::SETNPr,      X86::SETNPm, 0, 0 },
300     { X86::SETNSr,      X86::SETNSm, 0, 0 },
301     { X86::SETOr,       X86::SETOm, 0, 0 },
302     { X86::SETPr,       X86::SETPm, 0, 0 },
303     { X86::SETSr,       X86::SETSm, 0, 0 },
304     { X86::TAILJMPr,    X86::TAILJMPm, 1, 0 },
305     { X86::TEST16ri,    X86::TEST16mi, 1, 0 },
306     { X86::TEST32ri,    X86::TEST32mi, 1, 0 },
307     { X86::TEST64ri32,  X86::TEST64mi32, 1, 0 },
308     { X86::TEST8ri,     X86::TEST8mi, 1, 0 }
309   };
310 
311   for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
312     unsigned RegOp = OpTbl0[i][0];
313     unsigned MemOp = OpTbl0[i][1];
314     unsigned Align = OpTbl0[i][3];
315     if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
316                                            std::make_pair(MemOp,Align))).second)
317       assert(false && "Duplicated entries?");
318     unsigned FoldedLoad = OpTbl0[i][2];
319     // Index 0, folded load or store.
320     unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
321     if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
322       if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
323                                      std::make_pair(RegOp, AuxInfo))).second)
324         AmbEntries.push_back(MemOp);
325   }
326 
327   static const unsigned OpTbl1[][3] = {
328     { X86::CMP16rr,         X86::CMP16rm, 0 },
329     { X86::CMP32rr,         X86::CMP32rm, 0 },
330     { X86::CMP64rr,         X86::CMP64rm, 0 },
331     { X86::CMP8rr,          X86::CMP8rm, 0 },
332     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm, 0 },
333     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm, 0 },
334     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm, 0 },
335     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm, 0 },
336     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm, 0 },
337     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm, 0 },
338     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm, 0 },
339     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm, 0 },
340     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm, 0 },
341     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm, 0 },
342     { X86::FsMOVAPDrr,      X86::MOVSDrm, 0 },
343     { X86::FsMOVAPSrr,      X86::MOVSSrm, 0 },
344     { X86::IMUL16rri,       X86::IMUL16rmi, 0 },
345     { X86::IMUL16rri8,      X86::IMUL16rmi8, 0 },
346     { X86::IMUL32rri,       X86::IMUL32rmi, 0 },
347     { X86::IMUL32rri8,      X86::IMUL32rmi8, 0 },
348     { X86::IMUL64rri32,     X86::IMUL64rmi32, 0 },
349     { X86::IMUL64rri8,      X86::IMUL64rmi8, 0 },
350     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm, 0 },
351     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm, 0 },
352     { X86::Int_COMISDrr,    X86::Int_COMISDrm, 0 },
353     { X86::Int_COMISSrr,    X86::Int_COMISSrm, 0 },
354     { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm, 16 },
355     { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm, 16 },
356     { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm, 16 },
357     { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm, 16 },
358     { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm, 16 },
359     { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm, 0 },
360     { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
361     { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm, 0 },
362     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm, 0 },
363     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
364     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm, 0 },
365     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
366     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm, 0 },
367     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm, 0 },
368     { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
369     { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm, 0 },
370     { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
371     { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
372     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
373     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
374     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
375     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
376     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm, 0 },
377     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm, 0 },
378     { X86::MOV16rr,         X86::MOV16rm, 0 },
379     { X86::MOV32rr,         X86::MOV32rm, 0 },
380     { X86::MOV64rr,         X86::MOV64rm, 0 },
381     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm, 0 },
382     { X86::MOV64toSDrr,     X86::MOV64toSDrm, 0 },
383     { X86::MOV8rr,          X86::MOV8rm, 0 },
384     { X86::MOVAPDrr,        X86::MOVAPDrm, 16 },
385     { X86::MOVAPSrr,        X86::MOVAPSrm, 16 },
386     { X86::MOVDDUPrr,       X86::MOVDDUPrm, 0 },
387     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm, 0 },
388     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm, 0 },
389     { X86::MOVDQArr,        X86::MOVDQArm, 16 },
390     { X86::MOVSD2PDrr,      X86::MOVSD2PDrm, 0 },
391     { X86::MOVSDrr,         X86::MOVSDrm, 0 },
392     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm, 16 },
393     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm, 16 },
394     { X86::MOVSS2PSrr,      X86::MOVSS2PSrm, 0 },
395     { X86::MOVSSrr,         X86::MOVSSrm, 0 },
396     { X86::MOVSX16rr8,      X86::MOVSX16rm8, 0 },
397     { X86::MOVSX32rr16,     X86::MOVSX32rm16, 0 },
398     { X86::MOVSX32rr8,      X86::MOVSX32rm8, 0 },
399     { X86::MOVSX64rr16,     X86::MOVSX64rm16, 0 },
400     { X86::MOVSX64rr32,     X86::MOVSX64rm32, 0 },
401     { X86::MOVSX64rr8,      X86::MOVSX64rm8, 0 },
402     { X86::MOVUPDrr,        X86::MOVUPDrm, 16 },
403     { X86::MOVUPSrr,        X86::MOVUPSrm, 16 },
404     { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm, 0 },
405     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm, 0 },
406     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
407     { X86::MOVZX16rr8,      X86::MOVZX16rm8, 0 },
408     { X86::MOVZX32rr16,     X86::MOVZX32rm16, 0 },
409     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
410     { X86::MOVZX32rr8,      X86::MOVZX32rm8, 0 },
411     { X86::MOVZX64rr16,     X86::MOVZX64rm16, 0 },
412     { X86::MOVZX64rr32,     X86::MOVZX64rm32, 0 },
413     { X86::MOVZX64rr8,      X86::MOVZX64rm8, 0 },
414     { X86::PSHUFDri,        X86::PSHUFDmi, 16 },
415     { X86::PSHUFHWri,       X86::PSHUFHWmi, 16 },
416     { X86::PSHUFLWri,       X86::PSHUFLWmi, 16 },
417     { X86::RCPPSr,          X86::RCPPSm, 16 },
418     { X86::RCPPSr_Int,      X86::RCPPSm_Int, 16 },
419     { X86::RSQRTPSr,        X86::RSQRTPSm, 16 },
420     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int, 16 },
421     { X86::RSQRTSSr,        X86::RSQRTSSm, 0 },
422     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int, 0 },
423     { X86::SQRTPDr,         X86::SQRTPDm, 16 },
424     { X86::SQRTPDr_Int,     X86::SQRTPDm_Int, 16 },
425     { X86::SQRTPSr,         X86::SQRTPSm, 16 },
426     { X86::SQRTPSr_Int,     X86::SQRTPSm_Int, 16 },
427     { X86::SQRTSDr,         X86::SQRTSDm, 0 },
428     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int, 0 },
429     { X86::SQRTSSr,         X86::SQRTSSm, 0 },
430     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int, 0 },
431     { X86::TEST16rr,        X86::TEST16rm, 0 },
432     { X86::TEST32rr,        X86::TEST32rm, 0 },
433     { X86::TEST64rr,        X86::TEST64rm, 0 },
434     { X86::TEST8rr,         X86::TEST8rm, 0 },
435     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
436     { X86::UCOMISDrr,       X86::UCOMISDrm, 0 },
437     { X86::UCOMISSrr,       X86::UCOMISSrm, 0 }
438   };
439 
440   for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
441     unsigned RegOp = OpTbl1[i][0];
442     unsigned MemOp = OpTbl1[i][1];
443     unsigned Align = OpTbl1[i][2];
444     if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
445                                            std::make_pair(MemOp,Align))).second)
446       assert(false && "Duplicated entries?");
447     // Index 1, folded load
448     unsigned AuxInfo = 1 | (1 << 4);
449     if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
450       if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
451                                      std::make_pair(RegOp, AuxInfo))).second)
452         AmbEntries.push_back(MemOp);
453   }
454 
455   static const unsigned OpTbl2[][3] = {
456     { X86::ADC32rr,         X86::ADC32rm, 0 },
457     { X86::ADC64rr,         X86::ADC64rm, 0 },
458     { X86::ADD16rr,         X86::ADD16rm, 0 },
459     { X86::ADD32rr,         X86::ADD32rm, 0 },
460     { X86::ADD64rr,         X86::ADD64rm, 0 },
461     { X86::ADD8rr,          X86::ADD8rm, 0 },
462     { X86::ADDPDrr,         X86::ADDPDrm, 16 },
463     { X86::ADDPSrr,         X86::ADDPSrm, 16 },
464     { X86::ADDSDrr,         X86::ADDSDrm, 0 },
465     { X86::ADDSSrr,         X86::ADDSSrm, 0 },
466     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm, 16 },
467     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm, 16 },
468     { X86::AND16rr,         X86::AND16rm, 0 },
469     { X86::AND32rr,         X86::AND32rm, 0 },
470     { X86::AND64rr,         X86::AND64rm, 0 },
471     { X86::AND8rr,          X86::AND8rm, 0 },
472     { X86::ANDNPDrr,        X86::ANDNPDrm, 16 },
473     { X86::ANDNPSrr,        X86::ANDNPSrm, 16 },
474     { X86::ANDPDrr,         X86::ANDPDrm, 16 },
475     { X86::ANDPSrr,         X86::ANDPSrm, 16 },
476     { X86::CMOVA16rr,       X86::CMOVA16rm, 0 },
477     { X86::CMOVA32rr,       X86::CMOVA32rm, 0 },
478     { X86::CMOVA64rr,       X86::CMOVA64rm, 0 },
479     { X86::CMOVAE16rr,      X86::CMOVAE16rm, 0 },
480     { X86::CMOVAE32rr,      X86::CMOVAE32rm, 0 },
481     { X86::CMOVAE64rr,      X86::CMOVAE64rm, 0 },
482     { X86::CMOVB16rr,       X86::CMOVB16rm, 0 },
483     { X86::CMOVB32rr,       X86::CMOVB32rm, 0 },
484     { X86::CMOVB64rr,       X86::CMOVB64rm, 0 },
485     { X86::CMOVBE16rr,      X86::CMOVBE16rm, 0 },
486     { X86::CMOVBE32rr,      X86::CMOVBE32rm, 0 },
487     { X86::CMOVBE64rr,      X86::CMOVBE64rm, 0 },
488     { X86::CMOVE16rr,       X86::CMOVE16rm, 0 },
489     { X86::CMOVE32rr,       X86::CMOVE32rm, 0 },
490     { X86::CMOVE64rr,       X86::CMOVE64rm, 0 },
491     { X86::CMOVG16rr,       X86::CMOVG16rm, 0 },
492     { X86::CMOVG32rr,       X86::CMOVG32rm, 0 },
493     { X86::CMOVG64rr,       X86::CMOVG64rm, 0 },
494     { X86::CMOVGE16rr,      X86::CMOVGE16rm, 0 },
495     { X86::CMOVGE32rr,      X86::CMOVGE32rm, 0 },
496     { X86::CMOVGE64rr,      X86::CMOVGE64rm, 0 },
497     { X86::CMOVL16rr,       X86::CMOVL16rm, 0 },
498     { X86::CMOVL32rr,       X86::CMOVL32rm, 0 },
499     { X86::CMOVL64rr,       X86::CMOVL64rm, 0 },
500     { X86::CMOVLE16rr,      X86::CMOVLE16rm, 0 },
501     { X86::CMOVLE32rr,      X86::CMOVLE32rm, 0 },
502     { X86::CMOVLE64rr,      X86::CMOVLE64rm, 0 },
503     { X86::CMOVNE16rr,      X86::CMOVNE16rm, 0 },
504     { X86::CMOVNE32rr,      X86::CMOVNE32rm, 0 },
505     { X86::CMOVNE64rr,      X86::CMOVNE64rm, 0 },
506     { X86::CMOVNO16rr,      X86::CMOVNO16rm, 0 },
507     { X86::CMOVNO32rr,      X86::CMOVNO32rm, 0 },
508     { X86::CMOVNO64rr,      X86::CMOVNO64rm, 0 },
509     { X86::CMOVNP16rr,      X86::CMOVNP16rm, 0 },
510     { X86::CMOVNP32rr,      X86::CMOVNP32rm, 0 },
511     { X86::CMOVNP64rr,      X86::CMOVNP64rm, 0 },
512     { X86::CMOVNS16rr,      X86::CMOVNS16rm, 0 },
513     { X86::CMOVNS32rr,      X86::CMOVNS32rm, 0 },
514     { X86::CMOVNS64rr,      X86::CMOVNS64rm, 0 },
515     { X86::CMOVO16rr,       X86::CMOVO16rm, 0 },
516     { X86::CMOVO32rr,       X86::CMOVO32rm, 0 },
517     { X86::CMOVO64rr,       X86::CMOVO64rm, 0 },
518     { X86::CMOVP16rr,       X86::CMOVP16rm, 0 },
519     { X86::CMOVP32rr,       X86::CMOVP32rm, 0 },
520     { X86::CMOVP64rr,       X86::CMOVP64rm, 0 },
521     { X86::CMOVS16rr,       X86::CMOVS16rm, 0 },
522     { X86::CMOVS32rr,       X86::CMOVS32rm, 0 },
523     { X86::CMOVS64rr,       X86::CMOVS64rm, 0 },
524     { X86::CMPPDrri,        X86::CMPPDrmi, 16 },
525     { X86::CMPPSrri,        X86::CMPPSrmi, 16 },
526     { X86::CMPSDrr,         X86::CMPSDrm, 0 },
527     { X86::CMPSSrr,         X86::CMPSSrm, 0 },
528     { X86::DIVPDrr,         X86::DIVPDrm, 16 },
529     { X86::DIVPSrr,         X86::DIVPSrm, 16 },
530     { X86::DIVSDrr,         X86::DIVSDrm, 0 },
531     { X86::DIVSSrr,         X86::DIVSSrm, 0 },
532     { X86::FsANDNPDrr,      X86::FsANDNPDrm, 16 },
533     { X86::FsANDNPSrr,      X86::FsANDNPSrm, 16 },
534     { X86::FsANDPDrr,       X86::FsANDPDrm, 16 },
535     { X86::FsANDPSrr,       X86::FsANDPSrm, 16 },
536     { X86::FsORPDrr,        X86::FsORPDrm, 16 },
537     { X86::FsORPSrr,        X86::FsORPSrm, 16 },
538     { X86::FsXORPDrr,       X86::FsXORPDrm, 16 },
539     { X86::FsXORPSrr,       X86::FsXORPSrm, 16 },
540     { X86::HADDPDrr,        X86::HADDPDrm, 16 },
541     { X86::HADDPSrr,        X86::HADDPSrm, 16 },
542     { X86::HSUBPDrr,        X86::HSUBPDrm, 16 },
543     { X86::HSUBPSrr,        X86::HSUBPSrm, 16 },
544     { X86::IMUL16rr,        X86::IMUL16rm, 0 },
545     { X86::IMUL32rr,        X86::IMUL32rm, 0 },
546     { X86::IMUL64rr,        X86::IMUL64rm, 0 },
547     { X86::MAXPDrr,         X86::MAXPDrm, 16 },
548     { X86::MAXPDrr_Int,     X86::MAXPDrm_Int, 16 },
549     { X86::MAXPSrr,         X86::MAXPSrm, 16 },
550     { X86::MAXPSrr_Int,     X86::MAXPSrm_Int, 16 },
551     { X86::MAXSDrr,         X86::MAXSDrm, 0 },
552     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int, 0 },
553     { X86::MAXSSrr,         X86::MAXSSrm, 0 },
554     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int, 0 },
555     { X86::MINPDrr,         X86::MINPDrm, 16 },
556     { X86::MINPDrr_Int,     X86::MINPDrm_Int, 16 },
557     { X86::MINPSrr,         X86::MINPSrm, 16 },
558     { X86::MINPSrr_Int,     X86::MINPSrm_Int, 16 },
559     { X86::MINSDrr,         X86::MINSDrm, 0 },
560     { X86::MINSDrr_Int,     X86::MINSDrm_Int, 0 },
561     { X86::MINSSrr,         X86::MINSSrm, 0 },
562     { X86::MINSSrr_Int,     X86::MINSSrm_Int, 0 },
563     { X86::MULPDrr,         X86::MULPDrm, 16 },
564     { X86::MULPSrr,         X86::MULPSrm, 16 },
565     { X86::MULSDrr,         X86::MULSDrm, 0 },
566     { X86::MULSSrr,         X86::MULSSrm, 0 },
567     { X86::OR16rr,          X86::OR16rm, 0 },
568     { X86::OR32rr,          X86::OR32rm, 0 },
569     { X86::OR64rr,          X86::OR64rm, 0 },
570     { X86::OR8rr,           X86::OR8rm, 0 },
571     { X86::ORPDrr,          X86::ORPDrm, 16 },
572     { X86::ORPSrr,          X86::ORPSrm, 16 },
573     { X86::PACKSSDWrr,      X86::PACKSSDWrm, 16 },
574     { X86::PACKSSWBrr,      X86::PACKSSWBrm, 16 },
575     { X86::PACKUSWBrr,      X86::PACKUSWBrm, 16 },
576     { X86::PADDBrr,         X86::PADDBrm, 16 },
577     { X86::PADDDrr,         X86::PADDDrm, 16 },
578     { X86::PADDQrr,         X86::PADDQrm, 16 },
579     { X86::PADDSBrr,        X86::PADDSBrm, 16 },
580     { X86::PADDSWrr,        X86::PADDSWrm, 16 },
581     { X86::PADDWrr,         X86::PADDWrm, 16 },
582     { X86::PANDNrr,         X86::PANDNrm, 16 },
583     { X86::PANDrr,          X86::PANDrm, 16 },
584     { X86::PAVGBrr,         X86::PAVGBrm, 16 },
585     { X86::PAVGWrr,         X86::PAVGWrm, 16 },
586     { X86::PCMPEQBrr,       X86::PCMPEQBrm, 16 },
587     { X86::PCMPEQDrr,       X86::PCMPEQDrm, 16 },
588     { X86::PCMPEQWrr,       X86::PCMPEQWrm, 16 },
589     { X86::PCMPGTBrr,       X86::PCMPGTBrm, 16 },
590     { X86::PCMPGTDrr,       X86::PCMPGTDrm, 16 },
591     { X86::PCMPGTWrr,       X86::PCMPGTWrm, 16 },
592     { X86::PINSRWrri,       X86::PINSRWrmi, 16 },
593     { X86::PMADDWDrr,       X86::PMADDWDrm, 16 },
594     { X86::PMAXSWrr,        X86::PMAXSWrm, 16 },
595     { X86::PMAXUBrr,        X86::PMAXUBrm, 16 },
596     { X86::PMINSWrr,        X86::PMINSWrm, 16 },
597     { X86::PMINUBrr,        X86::PMINUBrm, 16 },
598     { X86::PMULDQrr,        X86::PMULDQrm, 16 },
599     { X86::PMULHUWrr,       X86::PMULHUWrm, 16 },
600     { X86::PMULHWrr,        X86::PMULHWrm, 16 },
601     { X86::PMULLDrr,        X86::PMULLDrm, 16 },
602     { X86::PMULLDrr_int,    X86::PMULLDrm_int, 16 },
603     { X86::PMULLWrr,        X86::PMULLWrm, 16 },
604     { X86::PMULUDQrr,       X86::PMULUDQrm, 16 },
605     { X86::PORrr,           X86::PORrm, 16 },
606     { X86::PSADBWrr,        X86::PSADBWrm, 16 },
607     { X86::PSLLDrr,         X86::PSLLDrm, 16 },
608     { X86::PSLLQrr,         X86::PSLLQrm, 16 },
609     { X86::PSLLWrr,         X86::PSLLWrm, 16 },
610     { X86::PSRADrr,         X86::PSRADrm, 16 },
611     { X86::PSRAWrr,         X86::PSRAWrm, 16 },
612     { X86::PSRLDrr,         X86::PSRLDrm, 16 },
613     { X86::PSRLQrr,         X86::PSRLQrm, 16 },
614     { X86::PSRLWrr,         X86::PSRLWrm, 16 },
615     { X86::PSUBBrr,         X86::PSUBBrm, 16 },
616     { X86::PSUBDrr,         X86::PSUBDrm, 16 },
617     { X86::PSUBSBrr,        X86::PSUBSBrm, 16 },
618     { X86::PSUBSWrr,        X86::PSUBSWrm, 16 },
619     { X86::PSUBWrr,         X86::PSUBWrm, 16 },
620     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm, 16 },
621     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm, 16 },
622     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm, 16 },
623     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm, 16 },
624     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm, 16 },
625     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm, 16 },
626     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm, 16 },
627     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm, 16 },
628     { X86::PXORrr,          X86::PXORrm, 16 },
629     { X86::SBB32rr,         X86::SBB32rm, 0 },
630     { X86::SBB64rr,         X86::SBB64rm, 0 },
631     { X86::SHUFPDrri,       X86::SHUFPDrmi, 16 },
632     { X86::SHUFPSrri,       X86::SHUFPSrmi, 16 },
633     { X86::SUB16rr,         X86::SUB16rm, 0 },
634     { X86::SUB32rr,         X86::SUB32rm, 0 },
635     { X86::SUB64rr,         X86::SUB64rm, 0 },
636     { X86::SUB8rr,          X86::SUB8rm, 0 },
637     { X86::SUBPDrr,         X86::SUBPDrm, 16 },
638     { X86::SUBPSrr,         X86::SUBPSrm, 16 },
639     { X86::SUBSDrr,         X86::SUBSDrm, 0 },
640     { X86::SUBSSrr,         X86::SUBSSrm, 0 },
641     // FIXME: TEST*rr -> swapped operand of TEST*mr.
642     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm, 16 },
643     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm, 16 },
644     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm, 16 },
645     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm, 16 },
646     { X86::XOR16rr,         X86::XOR16rm, 0 },
647     { X86::XOR32rr,         X86::XOR32rm, 0 },
648     { X86::XOR64rr,         X86::XOR64rm, 0 },
649     { X86::XOR8rr,          X86::XOR8rm, 0 },
650     { X86::XORPDrr,         X86::XORPDrm, 16 },
651     { X86::XORPSrr,         X86::XORPSrm, 16 }
652   };
653 
654   for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
655     unsigned RegOp = OpTbl2[i][0];
656     unsigned MemOp = OpTbl2[i][1];
657     unsigned Align = OpTbl2[i][2];
658     if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
659                                            std::make_pair(MemOp,Align))).second)
660       assert(false && "Duplicated entries?");
661     // Index 2, folded load
662     unsigned AuxInfo = 2 | (1 << 4);
663     if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
664                                    std::make_pair(RegOp, AuxInfo))).second)
665       AmbEntries.push_back(MemOp);
666   }
667 
668   // Remove ambiguous entries.
669   assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
670 }
671 
672 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
673                                unsigned &SrcReg, unsigned &DstReg,
674                                unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
675   switch (MI.getOpcode()) {
676   default:
677     return false;
678   case X86::MOV8rr:
679   case X86::MOV8rr_NOREX:
680   case X86::MOV16rr:
681   case X86::MOV32rr:
682   case X86::MOV64rr:
683   case X86::MOVSSrr:
684   case X86::MOVSDrr:
685 
686   // FP Stack register class copies
687   case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
688   case X86::MOV_Fp3264: case X86::MOV_Fp3280:
689   case X86::MOV_Fp6432: case X86::MOV_Fp8032:
690 
691   case X86::FsMOVAPSrr:
692   case X86::FsMOVAPDrr:
693   case X86::MOVAPSrr:
694   case X86::MOVAPDrr:
695   case X86::MOVDQArr:
696   case X86::MOVSS2PSrr:
697   case X86::MOVSD2PDrr:
698   case X86::MOVPS2SSrr:
699   case X86::MOVPD2SDrr:
700   case X86::MMX_MOVQ64rr:
701     assert(MI.getNumOperands() >= 2 &&
702            MI.getOperand(0).isReg() &&
703            MI.getOperand(1).isReg() &&
704            "invalid register-register move instruction");
705     SrcReg = MI.getOperand(1).getReg();
706     DstReg = MI.getOperand(0).getReg();
707     SrcSubIdx = MI.getOperand(1).getSubReg();
708     DstSubIdx = MI.getOperand(0).getSubReg();
709     return true;
710   }
711 }
712 
713 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
714                                            int &FrameIndex) const {
715   switch (MI->getOpcode()) {
716   default: break;
717   case X86::MOV8rm:
718   case X86::MOV16rm:
719   case X86::MOV32rm:
720   case X86::MOV64rm:
721   case X86::LD_Fp64m:
722   case X86::MOVSSrm:
723   case X86::MOVSDrm:
724   case X86::MOVAPSrm:
725   case X86::MOVAPDrm:
726   case X86::MOVDQArm:
727   case X86::MMX_MOVD64rm:
728   case X86::MMX_MOVQ64rm:
729     if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
730         MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
731         MI->getOperand(2).getImm() == 1 &&
732         MI->getOperand(3).getReg() == 0 &&
733         MI->getOperand(4).getImm() == 0) {
734       FrameIndex = MI->getOperand(1).getIndex();
735       return MI->getOperand(0).getReg();
736     }
737     break;
738   }
739   return 0;
740 }
741 
742 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
743                                           int &FrameIndex) const {
744   switch (MI->getOpcode()) {
745   default: break;
746   case X86::MOV8mr:
747   case X86::MOV16mr:
748   case X86::MOV32mr:
749   case X86::MOV64mr:
750   case X86::ST_FpP64m:
751   case X86::MOVSSmr:
752   case X86::MOVSDmr:
753   case X86::MOVAPSmr:
754   case X86::MOVAPDmr:
755   case X86::MOVDQAmr:
756   case X86::MMX_MOVD64mr:
757   case X86::MMX_MOVQ64mr:
758   case X86::MMX_MOVNTQmr:
759     if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
760         MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
761         MI->getOperand(1).getImm() == 1 &&
762         MI->getOperand(2).getReg() == 0 &&
763         MI->getOperand(3).getImm() == 0) {
764       FrameIndex = MI->getOperand(0).getIndex();
765       return MI->getOperand(X86AddrNumOperands).getReg();
766     }
767     break;
768   }
769   return 0;
770 }
771 
772 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
773 /// X86::MOVPC32r.
774 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
775   bool isPICBase = false;
776   for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
777          E = MRI.def_end(); I != E; ++I) {
778     MachineInstr *DefMI = I.getOperand().getParent();
779     if (DefMI->getOpcode() != X86::MOVPC32r)
780       return false;
781     assert(!isPICBase && "More than one PIC base?");
782     isPICBase = true;
783   }
784   return isPICBase;
785 }
786 
787 /// CanRematLoadWithDispOperand - Return true if a load with the specified
788 /// operand is a candidate for remat: for this to be true we need to know that
789 /// the load will always return the same value, even if moved.
790 static bool CanRematLoadWithDispOperand(const MachineOperand &MO,
791                                         X86TargetMachine &TM) {
792   // Loads from constant pool entries can be remat'd.
793   if (MO.isCPI()) return true;
794 
795   // We can remat globals in some cases.
796   if (MO.isGlobal()) {
797     // If this is a load of a stub, not of the global, we can remat it.  This
798     // access will always return the address of the global.
799     if (isGlobalStubReference(MO.getTargetFlags()))
800       return true;
801 
802     // If the global itself is constant, we can remat the load.
803     if (GlobalVariable *GV = dyn_cast<GlobalVariable>(MO.getGlobal()))
804       if (GV->isConstant())
805         return true;
806   }
807   return false;
808 }
809 
810 bool
811 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
812   switch (MI->getOpcode()) {
813   default: break;
814     case X86::MOV8rm:
815     case X86::MOV16rm:
816     case X86::MOV32rm:
817     case X86::MOV64rm:
818     case X86::LD_Fp64m:
819     case X86::MOVSSrm:
820     case X86::MOVSDrm:
821     case X86::MOVAPSrm:
822     case X86::MOVAPDrm:
823     case X86::MOVDQArm:
824     case X86::MMX_MOVD64rm:
825     case X86::MMX_MOVQ64rm: {
826       // Loads from constant pools are trivially rematerializable.
827       if (MI->getOperand(1).isReg() &&
828           MI->getOperand(2).isImm() &&
829           MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
830           CanRematLoadWithDispOperand(MI->getOperand(4), TM)) {
831         unsigned BaseReg = MI->getOperand(1).getReg();
832         if (BaseReg == 0 || BaseReg == X86::RIP)
833           return true;
834         // Allow re-materialization of PIC load.
835         if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
836           return false;
837         const MachineFunction &MF = *MI->getParent()->getParent();
838         const MachineRegisterInfo &MRI = MF.getRegInfo();
839         bool isPICBase = false;
840         for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
841                E = MRI.def_end(); I != E; ++I) {
842           MachineInstr *DefMI = I.getOperand().getParent();
843           if (DefMI->getOpcode() != X86::MOVPC32r)
844             return false;
845           assert(!isPICBase && "More than one PIC base?");
846           isPICBase = true;
847         }
848         return isPICBase;
849       }
850       return false;
851     }
852 
853      case X86::LEA32r:
854      case X86::LEA64r: {
855        if (MI->getOperand(2).isImm() &&
856            MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
857            !MI->getOperand(4).isReg()) {
858          // lea fi#, lea GV, etc. are all rematerializable.
859          if (!MI->getOperand(1).isReg())
860            return true;
861          unsigned BaseReg = MI->getOperand(1).getReg();
862          if (BaseReg == 0)
863            return true;
864          // Allow re-materialization of lea PICBase + x.
865          const MachineFunction &MF = *MI->getParent()->getParent();
866          const MachineRegisterInfo &MRI = MF.getRegInfo();
867          return regIsPICBase(BaseReg, MRI);
868        }
869        return false;
870      }
871   }
872 
873   // All other instructions marked M_REMATERIALIZABLE are always trivially
874   // rematerializable.
875   return true;
876 }
877 
878 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
879 /// would clobber the EFLAGS condition register. Note the result may be
880 /// conservative. If it cannot definitely determine the safety after visiting
881 /// two instructions it assumes it's not safe.
882 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
883                                   MachineBasicBlock::iterator I) {
884   // It's always safe to clobber EFLAGS at the end of a block.
885   if (I == MBB.end())
886     return true;
887 
888   // For compile time consideration, if we are not able to determine the
889   // safety after visiting 2 instructions, we will assume it's not safe.
890   for (unsigned i = 0; i < 2; ++i) {
891     bool SeenDef = false;
892     for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
893       MachineOperand &MO = I->getOperand(j);
894       if (!MO.isReg())
895         continue;
896       if (MO.getReg() == X86::EFLAGS) {
897         if (MO.isUse())
898           return false;
899         SeenDef = true;
900       }
901     }
902 
903     if (SeenDef)
904       // This instruction defines EFLAGS, no need to look any further.
905       return true;
906     ++I;
907 
908     // If we make it to the end of the block, it's safe to clobber EFLAGS.
909     if (I == MBB.end())
910       return true;
911   }
912 
913   // Conservative answer.
914   return false;
915 }
916 
917 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
918                                  MachineBasicBlock::iterator I,
919                                  unsigned DestReg, unsigned SubIdx,
920                                  const MachineInstr *Orig) const {
921   DebugLoc DL = DebugLoc::getUnknownLoc();
922   if (I != MBB.end()) DL = I->getDebugLoc();
923 
924   if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
925     DestReg = RI.getSubReg(DestReg, SubIdx);
926     SubIdx = 0;
927   }
928 
929   // MOV32r0 etc. are implemented with xor which clobbers condition code.
930   // Re-materialize them as movri instructions to avoid side effects.
931   bool Clone = true;
932   unsigned Opc = Orig->getOpcode();
933   switch (Opc) {
934   default: break;
935   case X86::MOV8r0:
936   case X86::MOV16r0:
937   case X86::MOV32r0: {
938     if (!isSafeToClobberEFLAGS(MBB, I)) {
939       switch (Opc) {
940       default: break;
941       case X86::MOV8r0:  Opc = X86::MOV8ri;  break;
942       case X86::MOV16r0: Opc = X86::MOV16ri; break;
943       case X86::MOV32r0: Opc = X86::MOV32ri; break;
944       }
945       Clone = false;
946     }
947     break;
948   }
949   }
950 
951   if (Clone) {
952     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
953     MI->getOperand(0).setReg(DestReg);
954     MBB.insert(I, MI);
955   } else {
956     BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
957   }
958 
959   MachineInstr *NewMI = prior(I);
960   NewMI->getOperand(0).setSubReg(SubIdx);
961 }
962 
963 /// isInvariantLoad - Return true if the specified instruction (which is marked
964 /// mayLoad) is loading from a location whose value is invariant across the
965 /// function.  For example, loading a value from the constant pool or from
966 /// from the argument area of a function if it does not change.  This should
967 /// only return true of *all* loads the instruction does are invariant (if it
968 /// does multiple loads).
969 bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const {
970   // This code cares about loads from three cases: constant pool entries,
971   // invariant argument slots, and global stubs.  In order to handle these cases
972   // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
973   // operand and base our analysis on it.  This is safe because the address of
974   // none of these three cases is ever used as anything other than a load base
975   // and X86 doesn't have any instructions that load from multiple places.
976 
977   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
978     const MachineOperand &MO = MI->getOperand(i);
979     // Loads from constant pools are trivially invariant.
980     if (MO.isCPI())
981       return true;
982 
983     if (MO.isGlobal())
984       return isGlobalStubReference(MO.getTargetFlags());
985 
986     // If this is a load from an invariant stack slot, the load is a constant.
987     if (MO.isFI()) {
988       const MachineFrameInfo &MFI =
989         *MI->getParent()->getParent()->getFrameInfo();
990       int Idx = MO.getIndex();
991       return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
992     }
993   }
994 
995   // All other instances of these instructions are presumed to have other
996   // issues.
997   return false;
998 }
999 
1000 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1001 /// is not marked dead.
1002 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1003   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1004     MachineOperand &MO = MI->getOperand(i);
1005     if (MO.isReg() && MO.isDef() &&
1006         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1007       return true;
1008     }
1009   }
1010   return false;
1011 }
1012 
1013 /// convertToThreeAddress - This method must be implemented by targets that
1014 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1015 /// may be able to convert a two-address instruction into a true
1016 /// three-address instruction on demand.  This allows the X86 target (for
1017 /// example) to convert ADD and SHL instructions into LEA instructions if they
1018 /// would require register copies due to two-addressness.
1019 ///
1020 /// This method returns a null pointer if the transformation cannot be
1021 /// performed, otherwise it returns the new instruction.
1022 ///
1023 MachineInstr *
1024 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1025                                     MachineBasicBlock::iterator &MBBI,
1026                                     LiveVariables *LV) const {
1027   MachineInstr *MI = MBBI;
1028   MachineFunction &MF = *MI->getParent()->getParent();
1029   // All instructions input are two-addr instructions.  Get the known operands.
1030   unsigned Dest = MI->getOperand(0).getReg();
1031   unsigned Src = MI->getOperand(1).getReg();
1032   bool isDead = MI->getOperand(0).isDead();
1033   bool isKill = MI->getOperand(1).isKill();
1034 
1035   MachineInstr *NewMI = NULL;
1036   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
1037   // we have better subtarget support, enable the 16-bit LEA generation here.
1038   bool DisableLEA16 = true;
1039 
1040   unsigned MIOpc = MI->getOpcode();
1041   switch (MIOpc) {
1042   case X86::SHUFPSrri: {
1043     assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1044     if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1045 
1046     unsigned B = MI->getOperand(1).getReg();
1047     unsigned C = MI->getOperand(2).getReg();
1048     if (B != C) return 0;
1049     unsigned A = MI->getOperand(0).getReg();
1050     unsigned M = MI->getOperand(3).getImm();
1051     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1052       .addReg(A, RegState::Define | getDeadRegState(isDead))
1053       .addReg(B, getKillRegState(isKill)).addImm(M);
1054     break;
1055   }
1056   case X86::SHL64ri: {
1057     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1058     // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1059     // the flags produced by a shift yet, so this is safe.
1060     unsigned ShAmt = MI->getOperand(2).getImm();
1061     if (ShAmt == 0 || ShAmt >= 4) return 0;
1062 
1063     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1064       .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1065       .addReg(0).addImm(1 << ShAmt)
1066       .addReg(Src, getKillRegState(isKill))
1067       .addImm(0);
1068     break;
1069   }
1070   case X86::SHL32ri: {
1071     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1072     // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1073     // the flags produced by a shift yet, so this is safe.
1074     unsigned ShAmt = MI->getOperand(2).getImm();
1075     if (ShAmt == 0 || ShAmt >= 4) return 0;
1076 
1077     unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1078       X86::LEA64_32r : X86::LEA32r;
1079     NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1080       .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1081       .addReg(0).addImm(1 << ShAmt)
1082       .addReg(Src, getKillRegState(isKill)).addImm(0);
1083     break;
1084   }
1085   case X86::SHL16ri: {
1086     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1087     // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1088     // the flags produced by a shift yet, so this is safe.
1089     unsigned ShAmt = MI->getOperand(2).getImm();
1090     if (ShAmt == 0 || ShAmt >= 4) return 0;
1091 
1092     if (DisableLEA16) {
1093       // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1094       MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1095       unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1096         ? X86::LEA64_32r : X86::LEA32r;
1097       unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1098       unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1099 
1100       // Build and insert into an implicit UNDEF value. This is OK because
1101       // well be shifting and then extracting the lower 16-bits.
1102       BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1103       MachineInstr *InsMI =
1104         BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1105         .addReg(leaInReg)
1106         .addReg(Src, getKillRegState(isKill))
1107         .addImm(X86::SUBREG_16BIT);
1108 
1109       NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
1110         .addReg(0).addImm(1 << ShAmt)
1111         .addReg(leaInReg, RegState::Kill)
1112         .addImm(0);
1113 
1114       MachineInstr *ExtMI =
1115         BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1116         .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1117         .addReg(leaOutReg, RegState::Kill)
1118         .addImm(X86::SUBREG_16BIT);
1119 
1120       if (LV) {
1121         // Update live variables
1122         LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1123         LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1124         if (isKill)
1125           LV->replaceKillInstruction(Src, MI, InsMI);
1126         if (isDead)
1127           LV->replaceKillInstruction(Dest, MI, ExtMI);
1128       }
1129       return ExtMI;
1130     } else {
1131       NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1132         .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1133         .addReg(0).addImm(1 << ShAmt)
1134         .addReg(Src, getKillRegState(isKill))
1135         .addImm(0);
1136     }
1137     break;
1138   }
1139   default: {
1140     // The following opcodes also sets the condition code register(s). Only
1141     // convert them to equivalent lea if the condition code register def's
1142     // are dead!
1143     if (hasLiveCondCodeDef(MI))
1144       return 0;
1145 
1146     bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1147     switch (MIOpc) {
1148     default: return 0;
1149     case X86::INC64r:
1150     case X86::INC32r:
1151     case X86::INC64_32r: {
1152       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1153       unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1154         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1155       NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1156                               .addReg(Dest, RegState::Define |
1157                                       getDeadRegState(isDead)),
1158                               Src, isKill, 1);
1159       break;
1160     }
1161     case X86::INC16r:
1162     case X86::INC64_16r:
1163       if (DisableLEA16) return 0;
1164       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1165       NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1166                            .addReg(Dest, RegState::Define |
1167                                    getDeadRegState(isDead)),
1168                            Src, isKill, 1);
1169       break;
1170     case X86::DEC64r:
1171     case X86::DEC32r:
1172     case X86::DEC64_32r: {
1173       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1174       unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1175         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1176       NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1177                               .addReg(Dest, RegState::Define |
1178                                       getDeadRegState(isDead)),
1179                               Src, isKill, -1);
1180       break;
1181     }
1182     case X86::DEC16r:
1183     case X86::DEC64_16r:
1184       if (DisableLEA16) return 0;
1185       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1186       NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1187                            .addReg(Dest, RegState::Define |
1188                                    getDeadRegState(isDead)),
1189                            Src, isKill, -1);
1190       break;
1191     case X86::ADD64rr:
1192     case X86::ADD32rr: {
1193       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1194       unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1195         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1196       unsigned Src2 = MI->getOperand(2).getReg();
1197       bool isKill2 = MI->getOperand(2).isKill();
1198       NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1199                         .addReg(Dest, RegState::Define |
1200                                 getDeadRegState(isDead)),
1201                         Src, isKill, Src2, isKill2);
1202       if (LV && isKill2)
1203         LV->replaceKillInstruction(Src2, MI, NewMI);
1204       break;
1205     }
1206     case X86::ADD16rr: {
1207       if (DisableLEA16) return 0;
1208       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1209       unsigned Src2 = MI->getOperand(2).getReg();
1210       bool isKill2 = MI->getOperand(2).isKill();
1211       NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1212                         .addReg(Dest, RegState::Define |
1213                                 getDeadRegState(isDead)),
1214                         Src, isKill, Src2, isKill2);
1215       if (LV && isKill2)
1216         LV->replaceKillInstruction(Src2, MI, NewMI);
1217       break;
1218     }
1219     case X86::ADD64ri32:
1220     case X86::ADD64ri8:
1221       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1222       if (MI->getOperand(2).isImm())
1223         NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1224                                 .addReg(Dest, RegState::Define |
1225                                         getDeadRegState(isDead)),
1226                                 Src, isKill, MI->getOperand(2).getImm());
1227       break;
1228     case X86::ADD32ri:
1229     case X86::ADD32ri8:
1230       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1231       if (MI->getOperand(2).isImm()) {
1232         unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1233         NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1234                                 .addReg(Dest, RegState::Define |
1235                                         getDeadRegState(isDead)),
1236                                 Src, isKill, MI->getOperand(2).getImm());
1237       }
1238       break;
1239     case X86::ADD16ri:
1240     case X86::ADD16ri8:
1241       if (DisableLEA16) return 0;
1242       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1243       if (MI->getOperand(2).isImm())
1244         NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1245                              .addReg(Dest, RegState::Define |
1246                                      getDeadRegState(isDead)),
1247                              Src, isKill, MI->getOperand(2).getImm());
1248       break;
1249     case X86::SHL16ri:
1250       if (DisableLEA16) return 0;
1251     case X86::SHL32ri:
1252     case X86::SHL64ri: {
1253       assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
1254              "Unknown shl instruction!");
1255       unsigned ShAmt = MI->getOperand(2).getImm();
1256       if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1257         X86AddressMode AM;
1258         AM.Scale = 1 << ShAmt;
1259         AM.IndexReg = Src;
1260         unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1261           : (MIOpc == X86::SHL32ri
1262              ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1263         NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1264                                .addReg(Dest, RegState::Define |
1265                                        getDeadRegState(isDead)), AM);
1266         if (isKill)
1267           NewMI->getOperand(3).setIsKill(true);
1268       }
1269       break;
1270     }
1271     }
1272   }
1273   }
1274 
1275   if (!NewMI) return 0;
1276 
1277   if (LV) {  // Update live variables
1278     if (isKill)
1279       LV->replaceKillInstruction(Src, MI, NewMI);
1280     if (isDead)
1281       LV->replaceKillInstruction(Dest, MI, NewMI);
1282   }
1283 
1284   MFI->insert(MBBI, NewMI);          // Insert the new inst
1285   return NewMI;
1286 }
1287 
1288 /// commuteInstruction - We have a few instructions that must be hacked on to
1289 /// commute them.
1290 ///
1291 MachineInstr *
1292 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1293   switch (MI->getOpcode()) {
1294   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1295   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1296   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1297   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1298   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1299   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1300     unsigned Opc;
1301     unsigned Size;
1302     switch (MI->getOpcode()) {
1303     default: llvm_unreachable("Unreachable!");
1304     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1305     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1306     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1307     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1308     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1309     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1310     }
1311     unsigned Amt = MI->getOperand(3).getImm();
1312     if (NewMI) {
1313       MachineFunction &MF = *MI->getParent()->getParent();
1314       MI = MF.CloneMachineInstr(MI);
1315       NewMI = false;
1316     }
1317     MI->setDesc(get(Opc));
1318     MI->getOperand(3).setImm(Size-Amt);
1319     return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1320   }
1321   case X86::CMOVB16rr:
1322   case X86::CMOVB32rr:
1323   case X86::CMOVB64rr:
1324   case X86::CMOVAE16rr:
1325   case X86::CMOVAE32rr:
1326   case X86::CMOVAE64rr:
1327   case X86::CMOVE16rr:
1328   case X86::CMOVE32rr:
1329   case X86::CMOVE64rr:
1330   case X86::CMOVNE16rr:
1331   case X86::CMOVNE32rr:
1332   case X86::CMOVNE64rr:
1333   case X86::CMOVBE16rr:
1334   case X86::CMOVBE32rr:
1335   case X86::CMOVBE64rr:
1336   case X86::CMOVA16rr:
1337   case X86::CMOVA32rr:
1338   case X86::CMOVA64rr:
1339   case X86::CMOVL16rr:
1340   case X86::CMOVL32rr:
1341   case X86::CMOVL64rr:
1342   case X86::CMOVGE16rr:
1343   case X86::CMOVGE32rr:
1344   case X86::CMOVGE64rr:
1345   case X86::CMOVLE16rr:
1346   case X86::CMOVLE32rr:
1347   case X86::CMOVLE64rr:
1348   case X86::CMOVG16rr:
1349   case X86::CMOVG32rr:
1350   case X86::CMOVG64rr:
1351   case X86::CMOVS16rr:
1352   case X86::CMOVS32rr:
1353   case X86::CMOVS64rr:
1354   case X86::CMOVNS16rr:
1355   case X86::CMOVNS32rr:
1356   case X86::CMOVNS64rr:
1357   case X86::CMOVP16rr:
1358   case X86::CMOVP32rr:
1359   case X86::CMOVP64rr:
1360   case X86::CMOVNP16rr:
1361   case X86::CMOVNP32rr:
1362   case X86::CMOVNP64rr:
1363   case X86::CMOVO16rr:
1364   case X86::CMOVO32rr:
1365   case X86::CMOVO64rr:
1366   case X86::CMOVNO16rr:
1367   case X86::CMOVNO32rr:
1368   case X86::CMOVNO64rr: {
1369     unsigned Opc = 0;
1370     switch (MI->getOpcode()) {
1371     default: break;
1372     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
1373     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
1374     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
1375     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1376     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1377     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1378     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
1379     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
1380     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
1381     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1382     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1383     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1384     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1385     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1386     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1387     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
1388     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
1389     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
1390     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
1391     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
1392     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
1393     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1394     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1395     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1396     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1397     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1398     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1399     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
1400     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
1401     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
1402     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
1403     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
1404     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
1405     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1406     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1407     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1408     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
1409     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
1410     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
1411     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1412     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1413     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1414     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
1415     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
1416     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
1417     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1418     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1419     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1420     }
1421     if (NewMI) {
1422       MachineFunction &MF = *MI->getParent()->getParent();
1423       MI = MF.CloneMachineInstr(MI);
1424       NewMI = false;
1425     }
1426     MI->setDesc(get(Opc));
1427     // Fallthrough intended.
1428   }
1429   default:
1430     return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1431   }
1432 }
1433 
1434 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1435   switch (BrOpc) {
1436   default: return X86::COND_INVALID;
1437   case X86::JE:  return X86::COND_E;
1438   case X86::JNE: return X86::COND_NE;
1439   case X86::JL:  return X86::COND_L;
1440   case X86::JLE: return X86::COND_LE;
1441   case X86::JG:  return X86::COND_G;
1442   case X86::JGE: return X86::COND_GE;
1443   case X86::JB:  return X86::COND_B;
1444   case X86::JBE: return X86::COND_BE;
1445   case X86::JA:  return X86::COND_A;
1446   case X86::JAE: return X86::COND_AE;
1447   case X86::JS:  return X86::COND_S;
1448   case X86::JNS: return X86::COND_NS;
1449   case X86::JP:  return X86::COND_P;
1450   case X86::JNP: return X86::COND_NP;
1451   case X86::JO:  return X86::COND_O;
1452   case X86::JNO: return X86::COND_NO;
1453   }
1454 }
1455 
1456 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1457   switch (CC) {
1458   default: llvm_unreachable("Illegal condition code!");
1459   case X86::COND_E:  return X86::JE;
1460   case X86::COND_NE: return X86::JNE;
1461   case X86::COND_L:  return X86::JL;
1462   case X86::COND_LE: return X86::JLE;
1463   case X86::COND_G:  return X86::JG;
1464   case X86::COND_GE: return X86::JGE;
1465   case X86::COND_B:  return X86::JB;
1466   case X86::COND_BE: return X86::JBE;
1467   case X86::COND_A:  return X86::JA;
1468   case X86::COND_AE: return X86::JAE;
1469   case X86::COND_S:  return X86::JS;
1470   case X86::COND_NS: return X86::JNS;
1471   case X86::COND_P:  return X86::JP;
1472   case X86::COND_NP: return X86::JNP;
1473   case X86::COND_O:  return X86::JO;
1474   case X86::COND_NO: return X86::JNO;
1475   }
1476 }
1477 
1478 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1479 /// e.g. turning COND_E to COND_NE.
1480 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1481   switch (CC) {
1482   default: llvm_unreachable("Illegal condition code!");
1483   case X86::COND_E:  return X86::COND_NE;
1484   case X86::COND_NE: return X86::COND_E;
1485   case X86::COND_L:  return X86::COND_GE;
1486   case X86::COND_LE: return X86::COND_G;
1487   case X86::COND_G:  return X86::COND_LE;
1488   case X86::COND_GE: return X86::COND_L;
1489   case X86::COND_B:  return X86::COND_AE;
1490   case X86::COND_BE: return X86::COND_A;
1491   case X86::COND_A:  return X86::COND_BE;
1492   case X86::COND_AE: return X86::COND_B;
1493   case X86::COND_S:  return X86::COND_NS;
1494   case X86::COND_NS: return X86::COND_S;
1495   case X86::COND_P:  return X86::COND_NP;
1496   case X86::COND_NP: return X86::COND_P;
1497   case X86::COND_O:  return X86::COND_NO;
1498   case X86::COND_NO: return X86::COND_O;
1499   }
1500 }
1501 
1502 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1503   const TargetInstrDesc &TID = MI->getDesc();
1504   if (!TID.isTerminator()) return false;
1505 
1506   // Conditional branch is a special case.
1507   if (TID.isBranch() && !TID.isBarrier())
1508     return true;
1509   if (!TID.isPredicable())
1510     return true;
1511   return !isPredicated(MI);
1512 }
1513 
1514 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1515 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1516                                                const X86InstrInfo &TII) {
1517   if (MI->getOpcode() == X86::FP_REG_KILL)
1518     return false;
1519   return TII.isUnpredicatedTerminator(MI);
1520 }
1521 
1522 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1523                                  MachineBasicBlock *&TBB,
1524                                  MachineBasicBlock *&FBB,
1525                                  SmallVectorImpl<MachineOperand> &Cond,
1526                                  bool AllowModify) const {
1527   // Start from the bottom of the block and work up, examining the
1528   // terminator instructions.
1529   MachineBasicBlock::iterator I = MBB.end();
1530   while (I != MBB.begin()) {
1531     --I;
1532     // Working from the bottom, when we see a non-terminator
1533     // instruction, we're done.
1534     if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1535       break;
1536     // A terminator that isn't a branch can't easily be handled
1537     // by this analysis.
1538     if (!I->getDesc().isBranch())
1539       return true;
1540     // Handle unconditional branches.
1541     if (I->getOpcode() == X86::JMP) {
1542       if (!AllowModify) {
1543         TBB = I->getOperand(0).getMBB();
1544         continue;
1545       }
1546 
1547       // If the block has any instructions after a JMP, delete them.
1548       while (next(I) != MBB.end())
1549         next(I)->eraseFromParent();
1550       Cond.clear();
1551       FBB = 0;
1552       // Delete the JMP if it's equivalent to a fall-through.
1553       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1554         TBB = 0;
1555         I->eraseFromParent();
1556         I = MBB.end();
1557         continue;
1558       }
1559       // TBB is used to indicate the unconditinal destination.
1560       TBB = I->getOperand(0).getMBB();
1561       continue;
1562     }
1563     // Handle conditional branches.
1564     X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1565     if (BranchCode == X86::COND_INVALID)
1566       return true;  // Can't handle indirect branch.
1567     // Working from the bottom, handle the first conditional branch.
1568     if (Cond.empty()) {
1569       FBB = TBB;
1570       TBB = I->getOperand(0).getMBB();
1571       Cond.push_back(MachineOperand::CreateImm(BranchCode));
1572       continue;
1573     }
1574     // Handle subsequent conditional branches. Only handle the case
1575     // where all conditional branches branch to the same destination
1576     // and their condition opcodes fit one of the special
1577     // multi-branch idioms.
1578     assert(Cond.size() == 1);
1579     assert(TBB);
1580     // Only handle the case where all conditional branches branch to
1581     // the same destination.
1582     if (TBB != I->getOperand(0).getMBB())
1583       return true;
1584     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1585     // If the conditions are the same, we can leave them alone.
1586     if (OldBranchCode == BranchCode)
1587       continue;
1588     // If they differ, see if they fit one of the known patterns.
1589     // Theoretically we could handle more patterns here, but
1590     // we shouldn't expect to see them if instruction selection
1591     // has done a reasonable job.
1592     if ((OldBranchCode == X86::COND_NP &&
1593          BranchCode == X86::COND_E) ||
1594         (OldBranchCode == X86::COND_E &&
1595          BranchCode == X86::COND_NP))
1596       BranchCode = X86::COND_NP_OR_E;
1597     else if ((OldBranchCode == X86::COND_P &&
1598               BranchCode == X86::COND_NE) ||
1599              (OldBranchCode == X86::COND_NE &&
1600               BranchCode == X86::COND_P))
1601       BranchCode = X86::COND_NE_OR_P;
1602     else
1603       return true;
1604     // Update the MachineOperand.
1605     Cond[0].setImm(BranchCode);
1606   }
1607 
1608   return false;
1609 }
1610 
1611 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1612   MachineBasicBlock::iterator I = MBB.end();
1613   unsigned Count = 0;
1614 
1615   while (I != MBB.begin()) {
1616     --I;
1617     if (I->getOpcode() != X86::JMP &&
1618         GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1619       break;
1620     // Remove the branch.
1621     I->eraseFromParent();
1622     I = MBB.end();
1623     ++Count;
1624   }
1625 
1626   return Count;
1627 }
1628 
1629 unsigned
1630 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1631                            MachineBasicBlock *FBB,
1632                            const SmallVectorImpl<MachineOperand> &Cond) const {
1633   // FIXME this should probably have a DebugLoc operand
1634   DebugLoc dl = DebugLoc::getUnknownLoc();
1635   // Shouldn't be a fall through.
1636   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1637   assert((Cond.size() == 1 || Cond.size() == 0) &&
1638          "X86 branch conditions have one component!");
1639 
1640   if (Cond.empty()) {
1641     // Unconditional branch?
1642     assert(!FBB && "Unconditional branch with multiple successors!");
1643     BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
1644     return 1;
1645   }
1646 
1647   // Conditional branch.
1648   unsigned Count = 0;
1649   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1650   switch (CC) {
1651   case X86::COND_NP_OR_E:
1652     // Synthesize NP_OR_E with two branches.
1653     BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
1654     ++Count;
1655     BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
1656     ++Count;
1657     break;
1658   case X86::COND_NE_OR_P:
1659     // Synthesize NE_OR_P with two branches.
1660     BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
1661     ++Count;
1662     BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
1663     ++Count;
1664     break;
1665   default: {
1666     unsigned Opc = GetCondBranchFromCond(CC);
1667     BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1668     ++Count;
1669   }
1670   }
1671   if (FBB) {
1672     // Two-way Conditional branch. Insert the second branch.
1673     BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
1674     ++Count;
1675   }
1676   return Count;
1677 }
1678 
1679 /// isHReg - Test if the given register is a physical h register.
1680 static bool isHReg(unsigned Reg) {
1681   return X86::GR8_ABCD_HRegClass.contains(Reg);
1682 }
1683 
1684 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1685                                 MachineBasicBlock::iterator MI,
1686                                 unsigned DestReg, unsigned SrcReg,
1687                                 const TargetRegisterClass *DestRC,
1688                                 const TargetRegisterClass *SrcRC) const {
1689   DebugLoc DL = DebugLoc::getUnknownLoc();
1690   if (MI != MBB.end()) DL = MI->getDebugLoc();
1691 
1692   // Determine if DstRC and SrcRC have a common superclass in common.
1693   const TargetRegisterClass *CommonRC = DestRC;
1694   if (DestRC == SrcRC)
1695     /* Source and destination have the same register class. */;
1696   else if (CommonRC->hasSuperClass(SrcRC))
1697     CommonRC = SrcRC;
1698   else if (!DestRC->hasSubClass(SrcRC)) {
1699     // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1700     // but we want to copy then as GR64.
1701     if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1702         DestRC->hasSuperClass(&X86::GR64RegClass))
1703       CommonRC = &X86::GR64RegClass;
1704     else
1705       CommonRC = 0;
1706   }
1707 
1708   if (CommonRC) {
1709     unsigned Opc;
1710     if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1711       Opc = X86::MOV64rr;
1712     } else if (CommonRC == &X86::GR32RegClass ||
1713                CommonRC == &X86::GR32_NOSPRegClass) {
1714       Opc = X86::MOV32rr;
1715     } else if (CommonRC == &X86::GR16RegClass) {
1716       Opc = X86::MOV16rr;
1717     } else if (CommonRC == &X86::GR8RegClass) {
1718       // Copying to or from a physical H register on x86-64 requires a NOREX
1719       // move.  Otherwise use a normal move.
1720       if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1721           TM.getSubtarget<X86Subtarget>().is64Bit())
1722         Opc = X86::MOV8rr_NOREX;
1723       else
1724         Opc = X86::MOV8rr;
1725     } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1726       Opc = X86::MOV64rr;
1727     } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1728       Opc = X86::MOV32rr;
1729     } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1730       Opc = X86::MOV16rr;
1731     } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1732       Opc = X86::MOV8rr;
1733     } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1734       if (TM.getSubtarget<X86Subtarget>().is64Bit())
1735         Opc = X86::MOV8rr_NOREX;
1736       else
1737         Opc = X86::MOV8rr;
1738     } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1739                CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1740       Opc = X86::MOV64rr;
1741     } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1742       Opc = X86::MOV32rr;
1743     } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1744       Opc = X86::MOV16rr;
1745     } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1746       Opc = X86::MOV8rr;
1747     } else if (CommonRC == &X86::RFP32RegClass) {
1748       Opc = X86::MOV_Fp3232;
1749     } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1750       Opc = X86::MOV_Fp6464;
1751     } else if (CommonRC == &X86::RFP80RegClass) {
1752       Opc = X86::MOV_Fp8080;
1753     } else if (CommonRC == &X86::FR32RegClass) {
1754       Opc = X86::FsMOVAPSrr;
1755     } else if (CommonRC == &X86::FR64RegClass) {
1756       Opc = X86::FsMOVAPDrr;
1757     } else if (CommonRC == &X86::VR128RegClass) {
1758       Opc = X86::MOVAPSrr;
1759     } else if (CommonRC == &X86::VR64RegClass) {
1760       Opc = X86::MMX_MOVQ64rr;
1761     } else {
1762       return false;
1763     }
1764     BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1765     return true;
1766   }
1767 
1768   // Moving EFLAGS to / from another register requires a push and a pop.
1769   if (SrcRC == &X86::CCRRegClass) {
1770     if (SrcReg != X86::EFLAGS)
1771       return false;
1772     if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1773       BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
1774       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1775       return true;
1776     } else if (DestRC == &X86::GR32RegClass ||
1777                DestRC == &X86::GR32_NOSPRegClass) {
1778       BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1779       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1780       return true;
1781     }
1782   } else if (DestRC == &X86::CCRRegClass) {
1783     if (DestReg != X86::EFLAGS)
1784       return false;
1785     if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1786       BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1787       BuildMI(MBB, MI, DL, get(X86::POPFQ));
1788       return true;
1789     } else if (SrcRC == &X86::GR32RegClass ||
1790                DestRC == &X86::GR32_NOSPRegClass) {
1791       BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1792       BuildMI(MBB, MI, DL, get(X86::POPFD));
1793       return true;
1794     }
1795   }
1796 
1797   // Moving from ST(0) turns into FpGET_ST0_32 etc.
1798   if (SrcRC == &X86::RSTRegClass) {
1799     // Copying from ST(0)/ST(1).
1800     if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1801       // Can only copy from ST(0)/ST(1) right now
1802       return false;
1803     bool isST0 = SrcReg == X86::ST0;
1804     unsigned Opc;
1805     if (DestRC == &X86::RFP32RegClass)
1806       Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1807     else if (DestRC == &X86::RFP64RegClass)
1808       Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1809     else {
1810       if (DestRC != &X86::RFP80RegClass)
1811         return false;
1812       Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1813     }
1814     BuildMI(MBB, MI, DL, get(Opc), DestReg);
1815     return true;
1816   }
1817 
1818   // Moving to ST(0) turns into FpSET_ST0_32 etc.
1819   if (DestRC == &X86::RSTRegClass) {
1820     // Copying to ST(0) / ST(1).
1821     if (DestReg != X86::ST0 && DestReg != X86::ST1)
1822       // Can only copy to TOS right now
1823       return false;
1824     bool isST0 = DestReg == X86::ST0;
1825     unsigned Opc;
1826     if (SrcRC == &X86::RFP32RegClass)
1827       Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1828     else if (SrcRC == &X86::RFP64RegClass)
1829       Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1830     else {
1831       if (SrcRC != &X86::RFP80RegClass)
1832         return false;
1833       Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1834     }
1835     BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1836     return true;
1837   }
1838 
1839   // Not yet supported!
1840   return false;
1841 }
1842 
1843 static unsigned getStoreRegOpcode(unsigned SrcReg,
1844                                   const TargetRegisterClass *RC,
1845                                   bool isStackAligned,
1846                                   TargetMachine &TM) {
1847   unsigned Opc = 0;
1848   if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1849     Opc = X86::MOV64mr;
1850   } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1851     Opc = X86::MOV32mr;
1852   } else if (RC == &X86::GR16RegClass) {
1853     Opc = X86::MOV16mr;
1854   } else if (RC == &X86::GR8RegClass) {
1855     // Copying to or from a physical H register on x86-64 requires a NOREX
1856     // move.  Otherwise use a normal move.
1857     if (isHReg(SrcReg) &&
1858         TM.getSubtarget<X86Subtarget>().is64Bit())
1859       Opc = X86::MOV8mr_NOREX;
1860     else
1861       Opc = X86::MOV8mr;
1862   } else if (RC == &X86::GR64_ABCDRegClass) {
1863     Opc = X86::MOV64mr;
1864   } else if (RC == &X86::GR32_ABCDRegClass) {
1865     Opc = X86::MOV32mr;
1866   } else if (RC == &X86::GR16_ABCDRegClass) {
1867     Opc = X86::MOV16mr;
1868   } else if (RC == &X86::GR8_ABCD_LRegClass) {
1869     Opc = X86::MOV8mr;
1870   } else if (RC == &X86::GR8_ABCD_HRegClass) {
1871     if (TM.getSubtarget<X86Subtarget>().is64Bit())
1872       Opc = X86::MOV8mr_NOREX;
1873     else
1874       Opc = X86::MOV8mr;
1875   } else if (RC == &X86::GR64_NOREXRegClass ||
1876              RC == &X86::GR64_NOREX_NOSPRegClass) {
1877     Opc = X86::MOV64mr;
1878   } else if (RC == &X86::GR32_NOREXRegClass) {
1879     Opc = X86::MOV32mr;
1880   } else if (RC == &X86::GR16_NOREXRegClass) {
1881     Opc = X86::MOV16mr;
1882   } else if (RC == &X86::GR8_NOREXRegClass) {
1883     Opc = X86::MOV8mr;
1884   } else if (RC == &X86::RFP80RegClass) {
1885     Opc = X86::ST_FpP80m;   // pops
1886   } else if (RC == &X86::RFP64RegClass) {
1887     Opc = X86::ST_Fp64m;
1888   } else if (RC == &X86::RFP32RegClass) {
1889     Opc = X86::ST_Fp32m;
1890   } else if (RC == &X86::FR32RegClass) {
1891     Opc = X86::MOVSSmr;
1892   } else if (RC == &X86::FR64RegClass) {
1893     Opc = X86::MOVSDmr;
1894   } else if (RC == &X86::VR128RegClass) {
1895     // If stack is realigned we can use aligned stores.
1896     Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1897   } else if (RC == &X86::VR64RegClass) {
1898     Opc = X86::MMX_MOVQ64mr;
1899   } else {
1900     llvm_unreachable("Unknown regclass");
1901   }
1902 
1903   return Opc;
1904 }
1905 
1906 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1907                                        MachineBasicBlock::iterator MI,
1908                                        unsigned SrcReg, bool isKill, int FrameIdx,
1909                                        const TargetRegisterClass *RC) const {
1910   const MachineFunction &MF = *MBB.getParent();
1911   bool isAligned = (RI.getStackAlignment() >= 16) ||
1912     RI.needsStackRealignment(MF);
1913   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1914   DebugLoc DL = DebugLoc::getUnknownLoc();
1915   if (MI != MBB.end()) DL = MI->getDebugLoc();
1916   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
1917     .addReg(SrcReg, getKillRegState(isKill));
1918 }
1919 
1920 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1921                                   bool isKill,
1922                                   SmallVectorImpl<MachineOperand> &Addr,
1923                                   const TargetRegisterClass *RC,
1924                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
1925   bool isAligned = (RI.getStackAlignment() >= 16) ||
1926     RI.needsStackRealignment(MF);
1927   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1928   DebugLoc DL = DebugLoc::getUnknownLoc();
1929   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
1930   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1931     MIB.addOperand(Addr[i]);
1932   MIB.addReg(SrcReg, getKillRegState(isKill));
1933   NewMIs.push_back(MIB);
1934 }
1935 
1936 static unsigned getLoadRegOpcode(unsigned DestReg,
1937                                  const TargetRegisterClass *RC,
1938                                  bool isStackAligned,
1939                                  const TargetMachine &TM) {
1940   unsigned Opc = 0;
1941   if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1942     Opc = X86::MOV64rm;
1943   } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1944     Opc = X86::MOV32rm;
1945   } else if (RC == &X86::GR16RegClass) {
1946     Opc = X86::MOV16rm;
1947   } else if (RC == &X86::GR8RegClass) {
1948     // Copying to or from a physical H register on x86-64 requires a NOREX
1949     // move.  Otherwise use a normal move.
1950     if (isHReg(DestReg) &&
1951         TM.getSubtarget<X86Subtarget>().is64Bit())
1952       Opc = X86::MOV8rm_NOREX;
1953     else
1954       Opc = X86::MOV8rm;
1955   } else if (RC == &X86::GR64_ABCDRegClass) {
1956     Opc = X86::MOV64rm;
1957   } else if (RC == &X86::GR32_ABCDRegClass) {
1958     Opc = X86::MOV32rm;
1959   } else if (RC == &X86::GR16_ABCDRegClass) {
1960     Opc = X86::MOV16rm;
1961   } else if (RC == &X86::GR8_ABCD_LRegClass) {
1962     Opc = X86::MOV8rm;
1963   } else if (RC == &X86::GR8_ABCD_HRegClass) {
1964     if (TM.getSubtarget<X86Subtarget>().is64Bit())
1965       Opc = X86::MOV8rm_NOREX;
1966     else
1967       Opc = X86::MOV8rm;
1968   } else if (RC == &X86::GR64_NOREXRegClass ||
1969              RC == &X86::GR64_NOREX_NOSPRegClass) {
1970     Opc = X86::MOV64rm;
1971   } else if (RC == &X86::GR32_NOREXRegClass) {
1972     Opc = X86::MOV32rm;
1973   } else if (RC == &X86::GR16_NOREXRegClass) {
1974     Opc = X86::MOV16rm;
1975   } else if (RC == &X86::GR8_NOREXRegClass) {
1976     Opc = X86::MOV8rm;
1977   } else if (RC == &X86::RFP80RegClass) {
1978     Opc = X86::LD_Fp80m;
1979   } else if (RC == &X86::RFP64RegClass) {
1980     Opc = X86::LD_Fp64m;
1981   } else if (RC == &X86::RFP32RegClass) {
1982     Opc = X86::LD_Fp32m;
1983   } else if (RC == &X86::FR32RegClass) {
1984     Opc = X86::MOVSSrm;
1985   } else if (RC == &X86::FR64RegClass) {
1986     Opc = X86::MOVSDrm;
1987   } else if (RC == &X86::VR128RegClass) {
1988     // If stack is realigned we can use aligned loads.
1989     Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
1990   } else if (RC == &X86::VR64RegClass) {
1991     Opc = X86::MMX_MOVQ64rm;
1992   } else {
1993     llvm_unreachable("Unknown regclass");
1994   }
1995 
1996   return Opc;
1997 }
1998 
1999 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2000                                         MachineBasicBlock::iterator MI,
2001                                         unsigned DestReg, int FrameIdx,
2002                                         const TargetRegisterClass *RC) const{
2003   const MachineFunction &MF = *MBB.getParent();
2004   bool isAligned = (RI.getStackAlignment() >= 16) ||
2005     RI.needsStackRealignment(MF);
2006   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2007   DebugLoc DL = DebugLoc::getUnknownLoc();
2008   if (MI != MBB.end()) DL = MI->getDebugLoc();
2009   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2010 }
2011 
2012 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2013                                  SmallVectorImpl<MachineOperand> &Addr,
2014                                  const TargetRegisterClass *RC,
2015                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
2016   bool isAligned = (RI.getStackAlignment() >= 16) ||
2017     RI.needsStackRealignment(MF);
2018   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2019   DebugLoc DL = DebugLoc::getUnknownLoc();
2020   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2021   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2022     MIB.addOperand(Addr[i]);
2023   NewMIs.push_back(MIB);
2024 }
2025 
2026 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2027                                              MachineBasicBlock::iterator MI,
2028                                 const std::vector<CalleeSavedInfo> &CSI) const {
2029   if (CSI.empty())
2030     return false;
2031 
2032   DebugLoc DL = DebugLoc::getUnknownLoc();
2033   if (MI != MBB.end()) DL = MI->getDebugLoc();
2034 
2035   bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2036   unsigned SlotSize = is64Bit ? 8 : 4;
2037 
2038   MachineFunction &MF = *MBB.getParent();
2039   unsigned FPReg = RI.getFrameRegister(MF);
2040   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2041   unsigned CalleeFrameSize = 0;
2042 
2043   unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2044   for (unsigned i = CSI.size(); i != 0; --i) {
2045     unsigned Reg = CSI[i-1].getReg();
2046     const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2047     // Add the callee-saved register as live-in. It's killed at the spill.
2048     MBB.addLiveIn(Reg);
2049     if (Reg == FPReg)
2050       // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2051       continue;
2052     if (RegClass != &X86::VR128RegClass) {
2053       CalleeFrameSize += SlotSize;
2054       BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2055     } else {
2056       storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2057     }
2058   }
2059 
2060   X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2061   return true;
2062 }
2063 
2064 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2065                                                MachineBasicBlock::iterator MI,
2066                                 const std::vector<CalleeSavedInfo> &CSI) const {
2067   if (CSI.empty())
2068     return false;
2069 
2070   DebugLoc DL = DebugLoc::getUnknownLoc();
2071   if (MI != MBB.end()) DL = MI->getDebugLoc();
2072 
2073   MachineFunction &MF = *MBB.getParent();
2074   unsigned FPReg = RI.getFrameRegister(MF);
2075   bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2076   unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2077   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2078     unsigned Reg = CSI[i].getReg();
2079     if (Reg == FPReg)
2080       // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2081       continue;
2082     const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2083     if (RegClass != &X86::VR128RegClass) {
2084       BuildMI(MBB, MI, DL, get(Opc), Reg);
2085     } else {
2086       loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2087     }
2088   }
2089   return true;
2090 }
2091 
2092 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2093                                      const SmallVectorImpl<MachineOperand> &MOs,
2094                                      MachineInstr *MI,
2095                                      const TargetInstrInfo &TII) {
2096   // Create the base instruction with the memory operand as the first part.
2097   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2098                                               MI->getDebugLoc(), true);
2099   MachineInstrBuilder MIB(NewMI);
2100   unsigned NumAddrOps = MOs.size();
2101   for (unsigned i = 0; i != NumAddrOps; ++i)
2102     MIB.addOperand(MOs[i]);
2103   if (NumAddrOps < 4)  // FrameIndex only
2104     addOffset(MIB, 0);
2105 
2106   // Loop over the rest of the ri operands, converting them over.
2107   unsigned NumOps = MI->getDesc().getNumOperands()-2;
2108   for (unsigned i = 0; i != NumOps; ++i) {
2109     MachineOperand &MO = MI->getOperand(i+2);
2110     MIB.addOperand(MO);
2111   }
2112   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2113     MachineOperand &MO = MI->getOperand(i);
2114     MIB.addOperand(MO);
2115   }
2116   return MIB;
2117 }
2118 
2119 static MachineInstr *FuseInst(MachineFunction &MF,
2120                               unsigned Opcode, unsigned OpNo,
2121                               const SmallVectorImpl<MachineOperand> &MOs,
2122                               MachineInstr *MI, const TargetInstrInfo &TII) {
2123   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2124                                               MI->getDebugLoc(), true);
2125   MachineInstrBuilder MIB(NewMI);
2126 
2127   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2128     MachineOperand &MO = MI->getOperand(i);
2129     if (i == OpNo) {
2130       assert(MO.isReg() && "Expected to fold into reg operand!");
2131       unsigned NumAddrOps = MOs.size();
2132       for (unsigned i = 0; i != NumAddrOps; ++i)
2133         MIB.addOperand(MOs[i]);
2134       if (NumAddrOps < 4)  // FrameIndex only
2135         addOffset(MIB, 0);
2136     } else {
2137       MIB.addOperand(MO);
2138     }
2139   }
2140   return MIB;
2141 }
2142 
2143 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2144                                 const SmallVectorImpl<MachineOperand> &MOs,
2145                                 MachineInstr *MI) {
2146   MachineFunction &MF = *MI->getParent()->getParent();
2147   MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2148 
2149   unsigned NumAddrOps = MOs.size();
2150   for (unsigned i = 0; i != NumAddrOps; ++i)
2151     MIB.addOperand(MOs[i]);
2152   if (NumAddrOps < 4)  // FrameIndex only
2153     addOffset(MIB, 0);
2154   return MIB.addImm(0);
2155 }
2156 
2157 MachineInstr*
2158 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2159                                     MachineInstr *MI, unsigned i,
2160                                     const SmallVectorImpl<MachineOperand> &MOs,
2161                                     unsigned Align) const {
2162   const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2163   bool isTwoAddrFold = false;
2164   unsigned NumOps = MI->getDesc().getNumOperands();
2165   bool isTwoAddr = NumOps > 1 &&
2166     MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2167 
2168   MachineInstr *NewMI = NULL;
2169   // Folding a memory location into the two-address part of a two-address
2170   // instruction is different than folding it other places.  It requires
2171   // replacing the *two* registers with the memory location.
2172   if (isTwoAddr && NumOps >= 2 && i < 2 &&
2173       MI->getOperand(0).isReg() &&
2174       MI->getOperand(1).isReg() &&
2175       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2176     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2177     isTwoAddrFold = true;
2178   } else if (i == 0) { // If operand 0
2179     if (MI->getOpcode() == X86::MOV16r0)
2180       NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2181     else if (MI->getOpcode() == X86::MOV32r0)
2182       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2183     else if (MI->getOpcode() == X86::MOV8r0)
2184       NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2185     if (NewMI)
2186       return NewMI;
2187 
2188     OpcodeTablePtr = &RegOp2MemOpTable0;
2189   } else if (i == 1) {
2190     OpcodeTablePtr = &RegOp2MemOpTable1;
2191   } else if (i == 2) {
2192     OpcodeTablePtr = &RegOp2MemOpTable2;
2193   }
2194 
2195   // If table selected...
2196   if (OpcodeTablePtr) {
2197     // Find the Opcode to fuse
2198     DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2199       OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2200     if (I != OpcodeTablePtr->end()) {
2201       unsigned MinAlign = I->second.second;
2202       if (Align < MinAlign)
2203         return NULL;
2204       if (isTwoAddrFold)
2205         NewMI = FuseTwoAddrInst(MF, I->second.first, MOs, MI, *this);
2206       else
2207         NewMI = FuseInst(MF, I->second.first, i, MOs, MI, *this);
2208       return NewMI;
2209     }
2210   }
2211 
2212   // No fusion
2213   if (PrintFailedFusing)
2214     cerr << "We failed to fuse operand " << i << " in " << *MI;
2215   return NULL;
2216 }
2217 
2218 
2219 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2220                                                   MachineInstr *MI,
2221                                            const SmallVectorImpl<unsigned> &Ops,
2222                                                   int FrameIndex) const {
2223   // Check switch flag
2224   if (NoFusing) return NULL;
2225 
2226   const MachineFrameInfo *MFI = MF.getFrameInfo();
2227   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2228   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2229     unsigned NewOpc = 0;
2230     switch (MI->getOpcode()) {
2231     default: return NULL;
2232     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
2233     case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2234     case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2235     case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2236     }
2237     // Change to CMPXXri r, 0 first.
2238     MI->setDesc(get(NewOpc));
2239     MI->getOperand(1).ChangeToImmediate(0);
2240   } else if (Ops.size() != 1)
2241     return NULL;
2242 
2243   SmallVector<MachineOperand,4> MOs;
2244   MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2245   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Alignment);
2246 }
2247 
2248 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2249                                                   MachineInstr *MI,
2250                                            const SmallVectorImpl<unsigned> &Ops,
2251                                                   MachineInstr *LoadMI) const {
2252   // Check switch flag
2253   if (NoFusing) return NULL;
2254 
2255   // Determine the alignment of the load.
2256   unsigned Alignment = 0;
2257   if (LoadMI->hasOneMemOperand())
2258     Alignment = LoadMI->memoperands_begin()->getAlignment();
2259   else if (LoadMI->getOpcode() == X86::V_SET0 ||
2260            LoadMI->getOpcode() == X86::V_SETALLONES)
2261     Alignment = 16;
2262   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2263     unsigned NewOpc = 0;
2264     switch (MI->getOpcode()) {
2265     default: return NULL;
2266     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
2267     case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2268     case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2269     case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2270     }
2271     // Change to CMPXXri r, 0 first.
2272     MI->setDesc(get(NewOpc));
2273     MI->getOperand(1).ChangeToImmediate(0);
2274   } else if (Ops.size() != 1)
2275     return NULL;
2276 
2277   SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2278   if (LoadMI->getOpcode() == X86::V_SET0 ||
2279       LoadMI->getOpcode() == X86::V_SETALLONES) {
2280     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2281     // Create a constant-pool entry and operands to load from it.
2282 
2283     // x86-32 PIC requires a PIC base register for constant pools.
2284     unsigned PICBase = 0;
2285     if (TM.getRelocationModel() == Reloc::PIC_) {
2286       if (TM.getSubtarget<X86Subtarget>().is64Bit())
2287         PICBase = X86::RIP;
2288       else
2289         // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2290         // This doesn't work for several reasons.
2291         // 1. GlobalBaseReg may have been spilled.
2292         // 2. It may not be live at MI.
2293         return false;
2294     }
2295 
2296     // Create a v4i32 constant-pool entry.
2297     MachineConstantPool &MCP = *MF.getConstantPool();
2298     const VectorType *Ty = VectorType::get(Type::Int32Ty, 4);
2299     Constant *C = LoadMI->getOpcode() == X86::V_SET0 ?
2300                     Constant::getNullValue(Ty) :
2301                     Constant::getAllOnesValue(Ty);
2302     unsigned CPI = MCP.getConstantPoolIndex(C, 16);
2303 
2304     // Create operands to load from the constant pool entry.
2305     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2306     MOs.push_back(MachineOperand::CreateImm(1));
2307     MOs.push_back(MachineOperand::CreateReg(0, false));
2308     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2309     MOs.push_back(MachineOperand::CreateReg(0, false));
2310   } else {
2311     // Folding a normal load. Just copy the load's address operands.
2312     unsigned NumOps = LoadMI->getDesc().getNumOperands();
2313     for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2314       MOs.push_back(LoadMI->getOperand(i));
2315   }
2316   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Alignment);
2317 }
2318 
2319 
2320 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2321                                   const SmallVectorImpl<unsigned> &Ops) const {
2322   // Check switch flag
2323   if (NoFusing) return 0;
2324 
2325   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2326     switch (MI->getOpcode()) {
2327     default: return false;
2328     case X86::TEST8rr:
2329     case X86::TEST16rr:
2330     case X86::TEST32rr:
2331     case X86::TEST64rr:
2332       return true;
2333     }
2334   }
2335 
2336   if (Ops.size() != 1)
2337     return false;
2338 
2339   unsigned OpNum = Ops[0];
2340   unsigned Opc = MI->getOpcode();
2341   unsigned NumOps = MI->getDesc().getNumOperands();
2342   bool isTwoAddr = NumOps > 1 &&
2343     MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2344 
2345   // Folding a memory location into the two-address part of a two-address
2346   // instruction is different than folding it other places.  It requires
2347   // replacing the *two* registers with the memory location.
2348   const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2349   if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2350     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2351   } else if (OpNum == 0) { // If operand 0
2352     switch (Opc) {
2353     case X86::MOV8r0:
2354     case X86::MOV16r0:
2355     case X86::MOV32r0:
2356       return true;
2357     default: break;
2358     }
2359     OpcodeTablePtr = &RegOp2MemOpTable0;
2360   } else if (OpNum == 1) {
2361     OpcodeTablePtr = &RegOp2MemOpTable1;
2362   } else if (OpNum == 2) {
2363     OpcodeTablePtr = &RegOp2MemOpTable2;
2364   }
2365 
2366   if (OpcodeTablePtr) {
2367     // Find the Opcode to fuse
2368     DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2369       OpcodeTablePtr->find((unsigned*)Opc);
2370     if (I != OpcodeTablePtr->end())
2371       return true;
2372   }
2373   return false;
2374 }
2375 
2376 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2377                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2378                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2379   DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2380     MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2381   if (I == MemOp2RegOpTable.end())
2382     return false;
2383   DebugLoc dl = MI->getDebugLoc();
2384   unsigned Opc = I->second.first;
2385   unsigned Index = I->second.second & 0xf;
2386   bool FoldedLoad = I->second.second & (1 << 4);
2387   bool FoldedStore = I->second.second & (1 << 5);
2388   if (UnfoldLoad && !FoldedLoad)
2389     return false;
2390   UnfoldLoad &= FoldedLoad;
2391   if (UnfoldStore && !FoldedStore)
2392     return false;
2393   UnfoldStore &= FoldedStore;
2394 
2395   const TargetInstrDesc &TID = get(Opc);
2396   const TargetOperandInfo &TOI = TID.OpInfo[Index];
2397   const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2398   SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2399   SmallVector<MachineOperand,2> BeforeOps;
2400   SmallVector<MachineOperand,2> AfterOps;
2401   SmallVector<MachineOperand,4> ImpOps;
2402   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2403     MachineOperand &Op = MI->getOperand(i);
2404     if (i >= Index && i < Index + X86AddrNumOperands)
2405       AddrOps.push_back(Op);
2406     else if (Op.isReg() && Op.isImplicit())
2407       ImpOps.push_back(Op);
2408     else if (i < Index)
2409       BeforeOps.push_back(Op);
2410     else if (i > Index)
2411       AfterOps.push_back(Op);
2412   }
2413 
2414   // Emit the load instruction.
2415   if (UnfoldLoad) {
2416     loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
2417     if (UnfoldStore) {
2418       // Address operands cannot be marked isKill.
2419       for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2420         MachineOperand &MO = NewMIs[0]->getOperand(i);
2421         if (MO.isReg())
2422           MO.setIsKill(false);
2423       }
2424     }
2425   }
2426 
2427   // Emit the data processing instruction.
2428   MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2429   MachineInstrBuilder MIB(DataMI);
2430 
2431   if (FoldedStore)
2432     MIB.addReg(Reg, RegState::Define);
2433   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2434     MIB.addOperand(BeforeOps[i]);
2435   if (FoldedLoad)
2436     MIB.addReg(Reg);
2437   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2438     MIB.addOperand(AfterOps[i]);
2439   for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2440     MachineOperand &MO = ImpOps[i];
2441     MIB.addReg(MO.getReg(),
2442                getDefRegState(MO.isDef()) |
2443                RegState::Implicit |
2444                getKillRegState(MO.isKill()) |
2445                getDeadRegState(MO.isDead()) |
2446                getUndefRegState(MO.isUndef()));
2447   }
2448   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2449   unsigned NewOpc = 0;
2450   switch (DataMI->getOpcode()) {
2451   default: break;
2452   case X86::CMP64ri32:
2453   case X86::CMP32ri:
2454   case X86::CMP16ri:
2455   case X86::CMP8ri: {
2456     MachineOperand &MO0 = DataMI->getOperand(0);
2457     MachineOperand &MO1 = DataMI->getOperand(1);
2458     if (MO1.getImm() == 0) {
2459       switch (DataMI->getOpcode()) {
2460       default: break;
2461       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2462       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
2463       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
2464       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
2465       }
2466       DataMI->setDesc(get(NewOpc));
2467       MO1.ChangeToRegister(MO0.getReg(), false);
2468     }
2469   }
2470   }
2471   NewMIs.push_back(DataMI);
2472 
2473   // Emit the store instruction.
2474   if (UnfoldStore) {
2475     const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2476     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
2477   }
2478 
2479   return true;
2480 }
2481 
2482 bool
2483 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2484                                   SmallVectorImpl<SDNode*> &NewNodes) const {
2485   if (!N->isMachineOpcode())
2486     return false;
2487 
2488   DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2489     MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2490   if (I == MemOp2RegOpTable.end())
2491     return false;
2492   unsigned Opc = I->second.first;
2493   unsigned Index = I->second.second & 0xf;
2494   bool FoldedLoad = I->second.second & (1 << 4);
2495   bool FoldedStore = I->second.second & (1 << 5);
2496   const TargetInstrDesc &TID = get(Opc);
2497   const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2498   unsigned NumDefs = TID.NumDefs;
2499   std::vector<SDValue> AddrOps;
2500   std::vector<SDValue> BeforeOps;
2501   std::vector<SDValue> AfterOps;
2502   DebugLoc dl = N->getDebugLoc();
2503   unsigned NumOps = N->getNumOperands();
2504   for (unsigned i = 0; i != NumOps-1; ++i) {
2505     SDValue Op = N->getOperand(i);
2506     if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2507       AddrOps.push_back(Op);
2508     else if (i < Index-NumDefs)
2509       BeforeOps.push_back(Op);
2510     else if (i > Index-NumDefs)
2511       AfterOps.push_back(Op);
2512   }
2513   SDValue Chain = N->getOperand(NumOps-1);
2514   AddrOps.push_back(Chain);
2515 
2516   // Emit the load instruction.
2517   SDNode *Load = 0;
2518   const MachineFunction &MF = DAG.getMachineFunction();
2519   if (FoldedLoad) {
2520     MVT VT = *RC->vt_begin();
2521     bool isAligned = (RI.getStackAlignment() >= 16) ||
2522       RI.needsStackRealignment(MF);
2523     Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2524                              VT, MVT::Other, &AddrOps[0], AddrOps.size());
2525     NewNodes.push_back(Load);
2526   }
2527 
2528   // Emit the data processing instruction.
2529   std::vector<MVT> VTs;
2530   const TargetRegisterClass *DstRC = 0;
2531   if (TID.getNumDefs() > 0) {
2532     DstRC = TID.OpInfo[0].getRegClass(&RI);
2533     VTs.push_back(*DstRC->vt_begin());
2534   }
2535   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2536     MVT VT = N->getValueType(i);
2537     if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2538       VTs.push_back(VT);
2539   }
2540   if (Load)
2541     BeforeOps.push_back(SDValue(Load, 0));
2542   std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2543   SDNode *NewNode= DAG.getTargetNode(Opc, dl, VTs, &BeforeOps[0],
2544                                      BeforeOps.size());
2545   NewNodes.push_back(NewNode);
2546 
2547   // Emit the store instruction.
2548   if (FoldedStore) {
2549     AddrOps.pop_back();
2550     AddrOps.push_back(SDValue(NewNode, 0));
2551     AddrOps.push_back(Chain);
2552     bool isAligned = (RI.getStackAlignment() >= 16) ||
2553       RI.needsStackRealignment(MF);
2554     SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC,
2555                                                         isAligned, TM),
2556                                       dl, MVT::Other,
2557                                       &AddrOps[0], AddrOps.size());
2558     NewNodes.push_back(Store);
2559   }
2560 
2561   return true;
2562 }
2563 
2564 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2565                                       bool UnfoldLoad, bool UnfoldStore) const {
2566   DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2567     MemOp2RegOpTable.find((unsigned*)Opc);
2568   if (I == MemOp2RegOpTable.end())
2569     return 0;
2570   bool FoldedLoad = I->second.second & (1 << 4);
2571   bool FoldedStore = I->second.second & (1 << 5);
2572   if (UnfoldLoad && !FoldedLoad)
2573     return 0;
2574   if (UnfoldStore && !FoldedStore)
2575     return 0;
2576   return I->second.first;
2577 }
2578 
2579 bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
2580   if (MBB.empty()) return false;
2581 
2582   switch (MBB.back().getOpcode()) {
2583   case X86::TCRETURNri:
2584   case X86::TCRETURNdi:
2585   case X86::RET:     // Return.
2586   case X86::RETI:
2587   case X86::TAILJMPd:
2588   case X86::TAILJMPr:
2589   case X86::TAILJMPm:
2590   case X86::JMP:     // Uncond branch.
2591   case X86::JMP32r:  // Indirect branch.
2592   case X86::JMP64r:  // Indirect branch (64-bit).
2593   case X86::JMP32m:  // Indirect branch through mem.
2594   case X86::JMP64m:  // Indirect branch through mem (64-bit).
2595     return true;
2596   default: return false;
2597   }
2598 }
2599 
2600 bool X86InstrInfo::
2601 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2602   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2603   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2604   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2605     return true;
2606   Cond[0].setImm(GetOppositeBranchCondition(CC));
2607   return false;
2608 }
2609 
2610 bool X86InstrInfo::
2611 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2612   // FIXME: Return false for x87 stack register classes for now. We can't
2613   // allow any loads of these registers before FpGet_ST0_80.
2614   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2615            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2616 }
2617 
2618 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2619   switch (Desc->TSFlags & X86II::ImmMask) {
2620   case X86II::Imm8:   return 1;
2621   case X86II::Imm16:  return 2;
2622   case X86II::Imm32:  return 4;
2623   case X86II::Imm64:  return 8;
2624   default: llvm_unreachable("Immediate size not set!");
2625     return 0;
2626   }
2627 }
2628 
2629 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2630 /// e.g. r8, xmm8, etc.
2631 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2632   if (!MO.isReg()) return false;
2633   switch (MO.getReg()) {
2634   default: break;
2635   case X86::R8:    case X86::R9:    case X86::R10:   case X86::R11:
2636   case X86::R12:   case X86::R13:   case X86::R14:   case X86::R15:
2637   case X86::R8D:   case X86::R9D:   case X86::R10D:  case X86::R11D:
2638   case X86::R12D:  case X86::R13D:  case X86::R14D:  case X86::R15D:
2639   case X86::R8W:   case X86::R9W:   case X86::R10W:  case X86::R11W:
2640   case X86::R12W:  case X86::R13W:  case X86::R14W:  case X86::R15W:
2641   case X86::R8B:   case X86::R9B:   case X86::R10B:  case X86::R11B:
2642   case X86::R12B:  case X86::R13B:  case X86::R14B:  case X86::R15B:
2643   case X86::XMM8:  case X86::XMM9:  case X86::XMM10: case X86::XMM11:
2644   case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2645     return true;
2646   }
2647   return false;
2648 }
2649 
2650 
2651 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2652 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2653 /// size, and 3) use of X86-64 extended registers.
2654 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2655   unsigned REX = 0;
2656   const TargetInstrDesc &Desc = MI.getDesc();
2657 
2658   // Pseudo instructions do not need REX prefix byte.
2659   if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2660     return 0;
2661   if (Desc.TSFlags & X86II::REX_W)
2662     REX |= 1 << 3;
2663 
2664   unsigned NumOps = Desc.getNumOperands();
2665   if (NumOps) {
2666     bool isTwoAddr = NumOps > 1 &&
2667       Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2668 
2669     // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2670     unsigned i = isTwoAddr ? 1 : 0;
2671     for (unsigned e = NumOps; i != e; ++i) {
2672       const MachineOperand& MO = MI.getOperand(i);
2673       if (MO.isReg()) {
2674         unsigned Reg = MO.getReg();
2675         if (isX86_64NonExtLowByteReg(Reg))
2676           REX |= 0x40;
2677       }
2678     }
2679 
2680     switch (Desc.TSFlags & X86II::FormMask) {
2681     case X86II::MRMInitReg:
2682       if (isX86_64ExtendedReg(MI.getOperand(0)))
2683         REX |= (1 << 0) | (1 << 2);
2684       break;
2685     case X86II::MRMSrcReg: {
2686       if (isX86_64ExtendedReg(MI.getOperand(0)))
2687         REX |= 1 << 2;
2688       i = isTwoAddr ? 2 : 1;
2689       for (unsigned e = NumOps; i != e; ++i) {
2690         const MachineOperand& MO = MI.getOperand(i);
2691         if (isX86_64ExtendedReg(MO))
2692           REX |= 1 << 0;
2693       }
2694       break;
2695     }
2696     case X86II::MRMSrcMem: {
2697       if (isX86_64ExtendedReg(MI.getOperand(0)))
2698         REX |= 1 << 2;
2699       unsigned Bit = 0;
2700       i = isTwoAddr ? 2 : 1;
2701       for (; i != NumOps; ++i) {
2702         const MachineOperand& MO = MI.getOperand(i);
2703         if (MO.isReg()) {
2704           if (isX86_64ExtendedReg(MO))
2705             REX |= 1 << Bit;
2706           Bit++;
2707         }
2708       }
2709       break;
2710     }
2711     case X86II::MRM0m: case X86II::MRM1m:
2712     case X86II::MRM2m: case X86II::MRM3m:
2713     case X86II::MRM4m: case X86II::MRM5m:
2714     case X86II::MRM6m: case X86II::MRM7m:
2715     case X86II::MRMDestMem: {
2716       unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
2717       i = isTwoAddr ? 1 : 0;
2718       if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2719         REX |= 1 << 2;
2720       unsigned Bit = 0;
2721       for (; i != e; ++i) {
2722         const MachineOperand& MO = MI.getOperand(i);
2723         if (MO.isReg()) {
2724           if (isX86_64ExtendedReg(MO))
2725             REX |= 1 << Bit;
2726           Bit++;
2727         }
2728       }
2729       break;
2730     }
2731     default: {
2732       if (isX86_64ExtendedReg(MI.getOperand(0)))
2733         REX |= 1 << 0;
2734       i = isTwoAddr ? 2 : 1;
2735       for (unsigned e = NumOps; i != e; ++i) {
2736         const MachineOperand& MO = MI.getOperand(i);
2737         if (isX86_64ExtendedReg(MO))
2738           REX |= 1 << 2;
2739       }
2740       break;
2741     }
2742     }
2743   }
2744   return REX;
2745 }
2746 
2747 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2748 /// relative block address instruction
2749 ///
2750 static unsigned sizePCRelativeBlockAddress() {
2751   return 4;
2752 }
2753 
2754 /// sizeGlobalAddress - Give the size of the emission of this global address
2755 ///
2756 static unsigned sizeGlobalAddress(bool dword) {
2757   return dword ? 8 : 4;
2758 }
2759 
2760 /// sizeConstPoolAddress - Give the size of the emission of this constant
2761 /// pool address
2762 ///
2763 static unsigned sizeConstPoolAddress(bool dword) {
2764   return dword ? 8 : 4;
2765 }
2766 
2767 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2768 /// symbol
2769 ///
2770 static unsigned sizeExternalSymbolAddress(bool dword) {
2771   return dword ? 8 : 4;
2772 }
2773 
2774 /// sizeJumpTableAddress - Give the size of the emission of this jump
2775 /// table address
2776 ///
2777 static unsigned sizeJumpTableAddress(bool dword) {
2778   return dword ? 8 : 4;
2779 }
2780 
2781 static unsigned sizeConstant(unsigned Size) {
2782   return Size;
2783 }
2784 
2785 static unsigned sizeRegModRMByte(){
2786   return 1;
2787 }
2788 
2789 static unsigned sizeSIBByte(){
2790   return 1;
2791 }
2792 
2793 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2794   unsigned FinalSize = 0;
2795   // If this is a simple integer displacement that doesn't require a relocation.
2796   if (!RelocOp) {
2797     FinalSize += sizeConstant(4);
2798     return FinalSize;
2799   }
2800 
2801   // Otherwise, this is something that requires a relocation.
2802   if (RelocOp->isGlobal()) {
2803     FinalSize += sizeGlobalAddress(false);
2804   } else if (RelocOp->isCPI()) {
2805     FinalSize += sizeConstPoolAddress(false);
2806   } else if (RelocOp->isJTI()) {
2807     FinalSize += sizeJumpTableAddress(false);
2808   } else {
2809     llvm_unreachable("Unknown value to relocate!");
2810   }
2811   return FinalSize;
2812 }
2813 
2814 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2815                                     bool IsPIC, bool Is64BitMode) {
2816   const MachineOperand &Op3 = MI.getOperand(Op+3);
2817   int DispVal = 0;
2818   const MachineOperand *DispForReloc = 0;
2819   unsigned FinalSize = 0;
2820 
2821   // Figure out what sort of displacement we have to handle here.
2822   if (Op3.isGlobal()) {
2823     DispForReloc = &Op3;
2824   } else if (Op3.isCPI()) {
2825     if (Is64BitMode || IsPIC) {
2826       DispForReloc = &Op3;
2827     } else {
2828       DispVal = 1;
2829     }
2830   } else if (Op3.isJTI()) {
2831     if (Is64BitMode || IsPIC) {
2832       DispForReloc = &Op3;
2833     } else {
2834       DispVal = 1;
2835     }
2836   } else {
2837     DispVal = 1;
2838   }
2839 
2840   const MachineOperand &Base     = MI.getOperand(Op);
2841   const MachineOperand &IndexReg = MI.getOperand(Op+2);
2842 
2843   unsigned BaseReg = Base.getReg();
2844 
2845   // Is a SIB byte needed?
2846   if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
2847       IndexReg.getReg() == 0 &&
2848       (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2849     if (BaseReg == 0) {  // Just a displacement?
2850       // Emit special case [disp32] encoding
2851       ++FinalSize;
2852       FinalSize += getDisplacementFieldSize(DispForReloc);
2853     } else {
2854       unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2855       if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2856         // Emit simple indirect register encoding... [EAX] f.e.
2857         ++FinalSize;
2858       // Be pessimistic and assume it's a disp32, not a disp8
2859       } else {
2860         // Emit the most general non-SIB encoding: [REG+disp32]
2861         ++FinalSize;
2862         FinalSize += getDisplacementFieldSize(DispForReloc);
2863       }
2864     }
2865 
2866   } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
2867     assert(IndexReg.getReg() != X86::ESP &&
2868            IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2869 
2870     bool ForceDisp32 = false;
2871     if (BaseReg == 0 || DispForReloc) {
2872       // Emit the normal disp32 encoding.
2873       ++FinalSize;
2874       ForceDisp32 = true;
2875     } else {
2876       ++FinalSize;
2877     }
2878 
2879     FinalSize += sizeSIBByte();
2880 
2881     // Do we need to output a displacement?
2882     if (DispVal != 0 || ForceDisp32) {
2883       FinalSize += getDisplacementFieldSize(DispForReloc);
2884     }
2885   }
2886   return FinalSize;
2887 }
2888 
2889 
2890 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2891                                     const TargetInstrDesc *Desc,
2892                                     bool IsPIC, bool Is64BitMode) {
2893 
2894   unsigned Opcode = Desc->Opcode;
2895   unsigned FinalSize = 0;
2896 
2897   // Emit the lock opcode prefix as needed.
2898   if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2899 
2900   // Emit segment override opcode prefix as needed.
2901   switch (Desc->TSFlags & X86II::SegOvrMask) {
2902   case X86II::FS:
2903   case X86II::GS:
2904    ++FinalSize;
2905    break;
2906   default: llvm_unreachable("Invalid segment!");
2907   case 0: break;  // No segment override!
2908   }
2909 
2910   // Emit the repeat opcode prefix as needed.
2911   if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2912 
2913   // Emit the operand size opcode prefix as needed.
2914   if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2915 
2916   // Emit the address size opcode prefix as needed.
2917   if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2918 
2919   bool Need0FPrefix = false;
2920   switch (Desc->TSFlags & X86II::Op0Mask) {
2921   case X86II::TB:  // Two-byte opcode prefix
2922   case X86II::T8:  // 0F 38
2923   case X86II::TA:  // 0F 3A
2924     Need0FPrefix = true;
2925     break;
2926   case X86II::REP: break; // already handled.
2927   case X86II::XS:   // F3 0F
2928     ++FinalSize;
2929     Need0FPrefix = true;
2930     break;
2931   case X86II::XD:   // F2 0F
2932     ++FinalSize;
2933     Need0FPrefix = true;
2934     break;
2935   case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
2936   case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
2937     ++FinalSize;
2938     break; // Two-byte opcode prefix
2939   default: llvm_unreachable("Invalid prefix!");
2940   case 0: break;  // No prefix!
2941   }
2942 
2943   if (Is64BitMode) {
2944     // REX prefix
2945     unsigned REX = X86InstrInfo::determineREX(MI);
2946     if (REX)
2947       ++FinalSize;
2948   }
2949 
2950   // 0x0F escape code must be emitted just before the opcode.
2951   if (Need0FPrefix)
2952     ++FinalSize;
2953 
2954   switch (Desc->TSFlags & X86II::Op0Mask) {
2955   case X86II::T8:  // 0F 38
2956     ++FinalSize;
2957     break;
2958   case X86II::TA:  // 0F 3A
2959     ++FinalSize;
2960     break;
2961   }
2962 
2963   // If this is a two-address instruction, skip one of the register operands.
2964   unsigned NumOps = Desc->getNumOperands();
2965   unsigned CurOp = 0;
2966   if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
2967     CurOp++;
2968   else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
2969     // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
2970     --NumOps;
2971 
2972   switch (Desc->TSFlags & X86II::FormMask) {
2973   default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
2974   case X86II::Pseudo:
2975     // Remember the current PC offset, this is the PIC relocation
2976     // base address.
2977     switch (Opcode) {
2978     default:
2979       break;
2980     case TargetInstrInfo::INLINEASM: {
2981       const MachineFunction *MF = MI.getParent()->getParent();
2982       const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
2983       FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
2984                                           *MF->getTarget().getTargetAsmInfo());
2985       break;
2986     }
2987     case TargetInstrInfo::DBG_LABEL:
2988     case TargetInstrInfo::EH_LABEL:
2989       break;
2990     case TargetInstrInfo::IMPLICIT_DEF:
2991     case TargetInstrInfo::DECLARE:
2992     case X86::DWARF_LOC:
2993     case X86::FP_REG_KILL:
2994       break;
2995     case X86::MOVPC32r: {
2996       // This emits the "call" portion of this pseudo instruction.
2997       ++FinalSize;
2998       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2999       break;
3000     }
3001     }
3002     CurOp = NumOps;
3003     break;
3004   case X86II::RawFrm:
3005     ++FinalSize;
3006 
3007     if (CurOp != NumOps) {
3008       const MachineOperand &MO = MI.getOperand(CurOp++);
3009       if (MO.isMBB()) {
3010         FinalSize += sizePCRelativeBlockAddress();
3011       } else if (MO.isGlobal()) {
3012         FinalSize += sizeGlobalAddress(false);
3013       } else if (MO.isSymbol()) {
3014         FinalSize += sizeExternalSymbolAddress(false);
3015       } else if (MO.isImm()) {
3016         FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3017       } else {
3018         llvm_unreachable("Unknown RawFrm operand!");
3019       }
3020     }
3021     break;
3022 
3023   case X86II::AddRegFrm:
3024     ++FinalSize;
3025     ++CurOp;
3026 
3027     if (CurOp != NumOps) {
3028       const MachineOperand &MO1 = MI.getOperand(CurOp++);
3029       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3030       if (MO1.isImm())
3031         FinalSize += sizeConstant(Size);
3032       else {
3033         bool dword = false;
3034         if (Opcode == X86::MOV64ri)
3035           dword = true;
3036         if (MO1.isGlobal()) {
3037           FinalSize += sizeGlobalAddress(dword);
3038         } else if (MO1.isSymbol())
3039           FinalSize += sizeExternalSymbolAddress(dword);
3040         else if (MO1.isCPI())
3041           FinalSize += sizeConstPoolAddress(dword);
3042         else if (MO1.isJTI())
3043           FinalSize += sizeJumpTableAddress(dword);
3044       }
3045     }
3046     break;
3047 
3048   case X86II::MRMDestReg: {
3049     ++FinalSize;
3050     FinalSize += sizeRegModRMByte();
3051     CurOp += 2;
3052     if (CurOp != NumOps) {
3053       ++CurOp;
3054       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3055     }
3056     break;
3057   }
3058   case X86II::MRMDestMem: {
3059     ++FinalSize;
3060     FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3061     CurOp +=  X86AddrNumOperands + 1;
3062     if (CurOp != NumOps) {
3063       ++CurOp;
3064       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3065     }
3066     break;
3067   }
3068 
3069   case X86II::MRMSrcReg:
3070     ++FinalSize;
3071     FinalSize += sizeRegModRMByte();
3072     CurOp += 2;
3073     if (CurOp != NumOps) {
3074       ++CurOp;
3075       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3076     }
3077     break;
3078 
3079   case X86II::MRMSrcMem: {
3080     int AddrOperands;
3081     if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3082         Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3083       AddrOperands = X86AddrNumOperands - 1; // No segment register
3084     else
3085       AddrOperands = X86AddrNumOperands;
3086 
3087     ++FinalSize;
3088     FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3089     CurOp += AddrOperands + 1;
3090     if (CurOp != NumOps) {
3091       ++CurOp;
3092       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3093     }
3094     break;
3095   }
3096 
3097   case X86II::MRM0r: case X86II::MRM1r:
3098   case X86II::MRM2r: case X86II::MRM3r:
3099   case X86II::MRM4r: case X86II::MRM5r:
3100   case X86II::MRM6r: case X86II::MRM7r:
3101     ++FinalSize;
3102     if (Desc->getOpcode() == X86::LFENCE ||
3103         Desc->getOpcode() == X86::MFENCE) {
3104       // Special handling of lfence and mfence;
3105       FinalSize += sizeRegModRMByte();
3106     } else if (Desc->getOpcode() == X86::MONITOR ||
3107                Desc->getOpcode() == X86::MWAIT) {
3108       // Special handling of monitor and mwait.
3109       FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3110     } else {
3111       ++CurOp;
3112       FinalSize += sizeRegModRMByte();
3113     }
3114 
3115     if (CurOp != NumOps) {
3116       const MachineOperand &MO1 = MI.getOperand(CurOp++);
3117       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3118       if (MO1.isImm())
3119         FinalSize += sizeConstant(Size);
3120       else {
3121         bool dword = false;
3122         if (Opcode == X86::MOV64ri32)
3123           dword = true;
3124         if (MO1.isGlobal()) {
3125           FinalSize += sizeGlobalAddress(dword);
3126         } else if (MO1.isSymbol())
3127           FinalSize += sizeExternalSymbolAddress(dword);
3128         else if (MO1.isCPI())
3129           FinalSize += sizeConstPoolAddress(dword);
3130         else if (MO1.isJTI())
3131           FinalSize += sizeJumpTableAddress(dword);
3132       }
3133     }
3134     break;
3135 
3136   case X86II::MRM0m: case X86II::MRM1m:
3137   case X86II::MRM2m: case X86II::MRM3m:
3138   case X86II::MRM4m: case X86II::MRM5m:
3139   case X86II::MRM6m: case X86II::MRM7m: {
3140 
3141     ++FinalSize;
3142     FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3143     CurOp += X86AddrNumOperands;
3144 
3145     if (CurOp != NumOps) {
3146       const MachineOperand &MO = MI.getOperand(CurOp++);
3147       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3148       if (MO.isImm())
3149         FinalSize += sizeConstant(Size);
3150       else {
3151         bool dword = false;
3152         if (Opcode == X86::MOV64mi32)
3153           dword = true;
3154         if (MO.isGlobal()) {
3155           FinalSize += sizeGlobalAddress(dword);
3156         } else if (MO.isSymbol())
3157           FinalSize += sizeExternalSymbolAddress(dword);
3158         else if (MO.isCPI())
3159           FinalSize += sizeConstPoolAddress(dword);
3160         else if (MO.isJTI())
3161           FinalSize += sizeJumpTableAddress(dword);
3162       }
3163     }
3164     break;
3165   }
3166 
3167   case X86II::MRMInitReg:
3168     ++FinalSize;
3169     // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3170     FinalSize += sizeRegModRMByte();
3171     ++CurOp;
3172     break;
3173   }
3174 
3175   if (!Desc->isVariadic() && CurOp != NumOps) {
3176     std::string msg;
3177     raw_string_ostream Msg(msg);
3178     Msg << "Cannot determine size: " << MI;
3179     llvm_report_error(Msg.str());
3180   }
3181 
3182 
3183   return FinalSize;
3184 }
3185 
3186 
3187 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3188   const TargetInstrDesc &Desc = MI->getDesc();
3189   bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3190   bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3191   unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3192   if (Desc.getOpcode() == X86::MOVPC32r)
3193     Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3194   return Size;
3195 }
3196 
3197 /// getGlobalBaseReg - Return a virtual register initialized with the
3198 /// the global base register value. Output instructions required to
3199 /// initialize the register in the function entry block, if necessary.
3200 ///
3201 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3202   assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3203          "X86-64 PIC uses RIP relative addressing");
3204 
3205   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3206   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3207   if (GlobalBaseReg != 0)
3208     return GlobalBaseReg;
3209 
3210   // Insert the set of GlobalBaseReg into the first MBB of the function
3211   MachineBasicBlock &FirstMBB = MF->front();
3212   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3213   DebugLoc DL = DebugLoc::getUnknownLoc();
3214   if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
3215   MachineRegisterInfo &RegInfo = MF->getRegInfo();
3216   unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3217 
3218   const TargetInstrInfo *TII = TM.getInstrInfo();
3219   // Operand of MovePCtoStack is completely ignored by asm printer. It's
3220   // only used in JIT code emission as displacement to pc.
3221   BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3222 
3223   // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3224   // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3225   if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3226     GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3227     // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3228     BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3229       .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 0,
3230                                     X86II::MO_GOT_ABSOLUTE_ADDRESS);
3231   } else {
3232     GlobalBaseReg = PC;
3233   }
3234 
3235   X86FI->setGlobalBaseReg(GlobalBaseReg);
3236   return GlobalBaseReg;
3237 }
3238