1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "x86-instr-info"
45 
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
48 
49 static cl::opt<bool>
50 NoFusing("disable-spill-fusing",
51          cl::desc("Disable fusing of spill code into instructions"));
52 static cl::opt<bool>
53 PrintFailedFusing("print-failed-fuse-candidates",
54                   cl::desc("Print instructions that the allocator wants to"
55                            " fuse, but the X86 backend currently can't"),
56                   cl::Hidden);
57 static cl::opt<bool>
58 ReMatPICStubLoad("remat-pic-stub-load",
59                  cl::desc("Re-materialize load from stub in PIC mode"),
60                  cl::init(false), cl::Hidden);
61 
62 enum {
63   // Select which memory operand is being unfolded.
64   // (stored in bits 0 - 3)
65   TB_INDEX_0    = 0,
66   TB_INDEX_1    = 1,
67   TB_INDEX_2    = 2,
68   TB_INDEX_3    = 3,
69   TB_INDEX_4    = 4,
70   TB_INDEX_MASK = 0xf,
71 
72   // Do not insert the reverse map (MemOp -> RegOp) into the table.
73   // This may be needed because there is a many -> one mapping.
74   TB_NO_REVERSE   = 1 << 4,
75 
76   // Do not insert the forward map (RegOp -> MemOp) into the table.
77   // This is needed for Native Client, which prohibits branch
78   // instructions from using a memory operand.
79   TB_NO_FORWARD   = 1 << 5,
80 
81   TB_FOLDED_LOAD  = 1 << 6,
82   TB_FOLDED_STORE = 1 << 7,
83 
84   // Minimum alignment required for load/store.
85   // Used for RegOp->MemOp conversion.
86   // (stored in bits 8 - 15)
87   TB_ALIGN_SHIFT = 8,
88   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
89   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
90   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
91   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
92   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
93 };
94 
95 struct X86MemoryFoldTableEntry {
96   uint16_t RegOp;
97   uint16_t MemOp;
98   uint16_t Flags;
99 };
100 
101 // Pin the vtable to this file.
102 void X86InstrInfo::anchor() {}
103 
104 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
105     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
106                                                : X86::ADJCALLSTACKDOWN32),
107                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
108                                                : X86::ADJCALLSTACKUP32),
109                       X86::CATCHRET),
110       Subtarget(STI), RI(STI.getTargetTriple()) {
111 
112   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
113     { X86::ADC32ri,     X86::ADC32mi,    0 },
114     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
115     { X86::ADC32rr,     X86::ADC32mr,    0 },
116     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
117     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
118     { X86::ADC64rr,     X86::ADC64mr,    0 },
119     { X86::ADD16ri,     X86::ADD16mi,    0 },
120     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
121     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
122     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
123     { X86::ADD16rr,     X86::ADD16mr,    0 },
124     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
125     { X86::ADD32ri,     X86::ADD32mi,    0 },
126     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
127     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
128     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
129     { X86::ADD32rr,     X86::ADD32mr,    0 },
130     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
131     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
132     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
133     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
134     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
135     { X86::ADD64rr,     X86::ADD64mr,    0 },
136     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
137     { X86::ADD8ri,      X86::ADD8mi,     0 },
138     { X86::ADD8rr,      X86::ADD8mr,     0 },
139     { X86::AND16ri,     X86::AND16mi,    0 },
140     { X86::AND16ri8,    X86::AND16mi8,   0 },
141     { X86::AND16rr,     X86::AND16mr,    0 },
142     { X86::AND32ri,     X86::AND32mi,    0 },
143     { X86::AND32ri8,    X86::AND32mi8,   0 },
144     { X86::AND32rr,     X86::AND32mr,    0 },
145     { X86::AND64ri32,   X86::AND64mi32,  0 },
146     { X86::AND64ri8,    X86::AND64mi8,   0 },
147     { X86::AND64rr,     X86::AND64mr,    0 },
148     { X86::AND8ri,      X86::AND8mi,     0 },
149     { X86::AND8rr,      X86::AND8mr,     0 },
150     { X86::DEC16r,      X86::DEC16m,     0 },
151     { X86::DEC32r,      X86::DEC32m,     0 },
152     { X86::DEC64r,      X86::DEC64m,     0 },
153     { X86::DEC8r,       X86::DEC8m,      0 },
154     { X86::INC16r,      X86::INC16m,     0 },
155     { X86::INC32r,      X86::INC32m,     0 },
156     { X86::INC64r,      X86::INC64m,     0 },
157     { X86::INC8r,       X86::INC8m,      0 },
158     { X86::NEG16r,      X86::NEG16m,     0 },
159     { X86::NEG32r,      X86::NEG32m,     0 },
160     { X86::NEG64r,      X86::NEG64m,     0 },
161     { X86::NEG8r,       X86::NEG8m,      0 },
162     { X86::NOT16r,      X86::NOT16m,     0 },
163     { X86::NOT32r,      X86::NOT32m,     0 },
164     { X86::NOT64r,      X86::NOT64m,     0 },
165     { X86::NOT8r,       X86::NOT8m,      0 },
166     { X86::OR16ri,      X86::OR16mi,     0 },
167     { X86::OR16ri8,     X86::OR16mi8,    0 },
168     { X86::OR16rr,      X86::OR16mr,     0 },
169     { X86::OR32ri,      X86::OR32mi,     0 },
170     { X86::OR32ri8,     X86::OR32mi8,    0 },
171     { X86::OR32rr,      X86::OR32mr,     0 },
172     { X86::OR64ri32,    X86::OR64mi32,   0 },
173     { X86::OR64ri8,     X86::OR64mi8,    0 },
174     { X86::OR64rr,      X86::OR64mr,     0 },
175     { X86::OR8ri,       X86::OR8mi,      0 },
176     { X86::OR8rr,       X86::OR8mr,      0 },
177     { X86::ROL16r1,     X86::ROL16m1,    0 },
178     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
179     { X86::ROL16ri,     X86::ROL16mi,    0 },
180     { X86::ROL32r1,     X86::ROL32m1,    0 },
181     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
182     { X86::ROL32ri,     X86::ROL32mi,    0 },
183     { X86::ROL64r1,     X86::ROL64m1,    0 },
184     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
185     { X86::ROL64ri,     X86::ROL64mi,    0 },
186     { X86::ROL8r1,      X86::ROL8m1,     0 },
187     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
188     { X86::ROL8ri,      X86::ROL8mi,     0 },
189     { X86::ROR16r1,     X86::ROR16m1,    0 },
190     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
191     { X86::ROR16ri,     X86::ROR16mi,    0 },
192     { X86::ROR32r1,     X86::ROR32m1,    0 },
193     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
194     { X86::ROR32ri,     X86::ROR32mi,    0 },
195     { X86::ROR64r1,     X86::ROR64m1,    0 },
196     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
197     { X86::ROR64ri,     X86::ROR64mi,    0 },
198     { X86::ROR8r1,      X86::ROR8m1,     0 },
199     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
200     { X86::ROR8ri,      X86::ROR8mi,     0 },
201     { X86::SAR16r1,     X86::SAR16m1,    0 },
202     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
203     { X86::SAR16ri,     X86::SAR16mi,    0 },
204     { X86::SAR32r1,     X86::SAR32m1,    0 },
205     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
206     { X86::SAR32ri,     X86::SAR32mi,    0 },
207     { X86::SAR64r1,     X86::SAR64m1,    0 },
208     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
209     { X86::SAR64ri,     X86::SAR64mi,    0 },
210     { X86::SAR8r1,      X86::SAR8m1,     0 },
211     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
212     { X86::SAR8ri,      X86::SAR8mi,     0 },
213     { X86::SBB32ri,     X86::SBB32mi,    0 },
214     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
215     { X86::SBB32rr,     X86::SBB32mr,    0 },
216     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
217     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
218     { X86::SBB64rr,     X86::SBB64mr,    0 },
219     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
220     { X86::SHL16ri,     X86::SHL16mi,    0 },
221     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
222     { X86::SHL32ri,     X86::SHL32mi,    0 },
223     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
224     { X86::SHL64ri,     X86::SHL64mi,    0 },
225     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
226     { X86::SHL8ri,      X86::SHL8mi,     0 },
227     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
228     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
229     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
230     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
231     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
232     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
233     { X86::SHR16r1,     X86::SHR16m1,    0 },
234     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
235     { X86::SHR16ri,     X86::SHR16mi,    0 },
236     { X86::SHR32r1,     X86::SHR32m1,    0 },
237     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
238     { X86::SHR32ri,     X86::SHR32mi,    0 },
239     { X86::SHR64r1,     X86::SHR64m1,    0 },
240     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
241     { X86::SHR64ri,     X86::SHR64mi,    0 },
242     { X86::SHR8r1,      X86::SHR8m1,     0 },
243     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
244     { X86::SHR8ri,      X86::SHR8mi,     0 },
245     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
246     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
247     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
248     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
249     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
250     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
251     { X86::SUB16ri,     X86::SUB16mi,    0 },
252     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
253     { X86::SUB16rr,     X86::SUB16mr,    0 },
254     { X86::SUB32ri,     X86::SUB32mi,    0 },
255     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
256     { X86::SUB32rr,     X86::SUB32mr,    0 },
257     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
258     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
259     { X86::SUB64rr,     X86::SUB64mr,    0 },
260     { X86::SUB8ri,      X86::SUB8mi,     0 },
261     { X86::SUB8rr,      X86::SUB8mr,     0 },
262     { X86::XOR16ri,     X86::XOR16mi,    0 },
263     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
264     { X86::XOR16rr,     X86::XOR16mr,    0 },
265     { X86::XOR32ri,     X86::XOR32mi,    0 },
266     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
267     { X86::XOR32rr,     X86::XOR32mr,    0 },
268     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
269     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
270     { X86::XOR64rr,     X86::XOR64mr,    0 },
271     { X86::XOR8ri,      X86::XOR8mi,     0 },
272     { X86::XOR8rr,      X86::XOR8mr,     0 }
273   };
274 
275   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
276     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
277                   Entry.RegOp, Entry.MemOp,
278                   // Index 0, folded load and store, no alignment requirement.
279                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
280   }
281 
282   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
283     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
284     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
285     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
286     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
287     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
288     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
289     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
290     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
291     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
292     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
293     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
294     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
295     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
296     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
297     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
298     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
299     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
300     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
301     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
302     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
303     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
304     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
305     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
306     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
307     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
308     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
309     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
310     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
311     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
312     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
313     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
314     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
315     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
316     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
317     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
318     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
319     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
320     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
321     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
322     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
326     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
327     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
328     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
329     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
330     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
331     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
332     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
333     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
334     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
335     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
336     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
337     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
338     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
339     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
340     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
341     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
342     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
343     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
344     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
345     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
346     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
347     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
348     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
349     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
350     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
351     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
352     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
353     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
354     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
355     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
356     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
357     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
358     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
359     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
360     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
361     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
362     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
363     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
364 
365     // AVX 128-bit versions of foldable instructions
366     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
367     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
368     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
369     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
370     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
371     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
372     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
373     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
374     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
375     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
376     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
377     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
378     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
379 
380     // AVX 256-bit foldable instructions
381     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
382     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
383     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
384     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
385     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
386     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
387 
388     // AVX-512 foldable instructions
389     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
390     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
391     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
392     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
393     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
394     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
395     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
396     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
397     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
398     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
399     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
400 
401     // AVX-512 foldable instructions (256-bit versions)
402     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
403     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
404     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
405     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
406     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
407     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
408     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
409     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
410     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
411     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
412 
413     // AVX-512 foldable instructions (128-bit versions)
414     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
415     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
416     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
417     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
418     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
419     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
420     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
421     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
422     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
423     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
424 
425     // F16C foldable instructions
426     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
427     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
428   };
429 
430   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
431     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
432                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
433   }
434 
435   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
436     { X86::BSF16rr,         X86::BSF16rm,             0 },
437     { X86::BSF32rr,         X86::BSF32rm,             0 },
438     { X86::BSF64rr,         X86::BSF64rm,             0 },
439     { X86::BSR16rr,         X86::BSR16rm,             0 },
440     { X86::BSR32rr,         X86::BSR32rm,             0 },
441     { X86::BSR64rr,         X86::BSR64rm,             0 },
442     { X86::CMP16rr,         X86::CMP16rm,             0 },
443     { X86::CMP32rr,         X86::CMP32rm,             0 },
444     { X86::CMP64rr,         X86::CMP64rm,             0 },
445     { X86::CMP8rr,          X86::CMP8rm,              0 },
446     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
447     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
448     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
449     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
450     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
451     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
452     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
453     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
454     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
455     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
456     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
457     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
458     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
459     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
460     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
461     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
462     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
463     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
464     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
465     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
466     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
467     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
468     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
469     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
470     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
471     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
472     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
473     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
474     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
475     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
476     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
477     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
478     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
479     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
480     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
481     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
482     { X86::MOV16rr,         X86::MOV16rm,             0 },
483     { X86::MOV32rr,         X86::MOV32rm,             0 },
484     { X86::MOV64rr,         X86::MOV64rm,             0 },
485     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
486     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
487     { X86::MOV8rr,          X86::MOV8rm,              0 },
488     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
489     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
490     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
491     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
492     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
493     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
494     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
495     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
496     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
497     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
498     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
499     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
500     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
501     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
502     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
503     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
504     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
505     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
506     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
507     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
508     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
509     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
510     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
511     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
512     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
513     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
514     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
515     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
516     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
517     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
518     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
519     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
520     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
521     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
522     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
523     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
524     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
525     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
526     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
527     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
528     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
529     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
530     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
531     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
532     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
533     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
534     { X86::RCPSSr,          X86::RCPSSm,              0 },
535     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          0 },
536     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
537     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
538     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
539     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
540     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
541     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
542     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
543     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
544     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
545     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
546     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
547     { X86::TEST16rr,        X86::TEST16rm,            0 },
548     { X86::TEST32rr,        X86::TEST32rm,            0 },
549     { X86::TEST64rr,        X86::TEST64rm,            0 },
550     { X86::TEST8rr,         X86::TEST8rm,             0 },
551     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
552     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
553     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
554 
555     // MMX version of foldable instructions
556     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
557     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
558     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
559     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
560     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
561     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
562     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
563     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
564     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
565     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
566 
567     // 3DNow! version of foldable instructions
568     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
569     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
570     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
571     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
572     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
573     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
574     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
575 
576     // AVX 128-bit versions of foldable instructions
577     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
578     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
579     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
580     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
581     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
582     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
583     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
584     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
585     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
586     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
587     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
588     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
589     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
590     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
591     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
592     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
593     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
594     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
595     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
596     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
597     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
598     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
599     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
600     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
601     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
602     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
603     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
604     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
605     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
606     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
607     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
608     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
609     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
610     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
611     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
612     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
613     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
614     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
615     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
616     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
617     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
618     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
619     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
620     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
621     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
622     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
623     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
624     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
625     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
626     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
627     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
628     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
629     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
630     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
631     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
632     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
633     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
634     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
635     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
636     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
637     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
638     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
639     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
640     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
641     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
642     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
643     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
644     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
645     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
646     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
647     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
648     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
649     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
650 
651     // AVX 256-bit foldable instructions
652     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
653     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
654     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
655     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
656     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
657     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
658     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
659     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
660     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
661     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
662     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
663     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
664     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
665     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
666     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
667     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
668     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
669     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
670     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
671     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
672     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
673     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
674     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
675     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
676     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
677     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
678     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
679 
680     // AVX2 foldable instructions
681 
682     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
683     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
684     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
685     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
686     // so they don't need an equivalent limitation.
687     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
688     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
689     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
690     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
691     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
692     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
693     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      0 },
694     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     0 },
695     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      0 },
696     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     0 },
697     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      0 },
698     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     0 },
699     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      0 },
700     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     0 },
701     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
702     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
703     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        0 },
704     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        0 },
705     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
706     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
707     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
708     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        0 },
709     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        0 },
710     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        0 },
711     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
712     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
713     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
714     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        0 },
715     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
716     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
717     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
718 
719     // XOP foldable instructions
720     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
721     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
722     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
723     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
724     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
725     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
726     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
727     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
728     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
729     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
730     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
731     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
732     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
733     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
734     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
735     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
736     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
737     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
738     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
739     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
740     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
741     { X86::VPROTBri,           X86::VPROTBmi,         0 },
742     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
743     { X86::VPROTDri,           X86::VPROTDmi,         0 },
744     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
745     { X86::VPROTQri,           X86::VPROTQmi,         0 },
746     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
747     { X86::VPROTWri,           X86::VPROTWmi,         0 },
748     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
749     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
750     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
751     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
752     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
753     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
754     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
755     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
756     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
757 
758     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
759     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
760     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
761     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
762     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
763     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
764     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
765     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
766     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
767     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
768     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
769     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
770     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
771     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
772     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
773     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
774     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
775     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
776     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
777     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
778     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
779     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
780     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
781     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
782     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
783     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
784     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
785     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
786     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
787     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
788     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
789     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
790     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
791     { X86::RORX32ri,        X86::RORX32mi,            0 },
792     { X86::RORX64ri,        X86::RORX64mi,            0 },
793     { X86::SARX32rr,        X86::SARX32rm,            0 },
794     { X86::SARX64rr,        X86::SARX64rm,            0 },
795     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
796     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
797     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
798     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
799     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
800     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
801     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
802     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
803     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
804     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
805     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
806 
807     // AVX-512 foldable instructions
808     { X86::VMOV64toPQIZrr,   X86::VMOVQI2PQIZrm,      0 },
809     { X86::VMOVDI2SSZrr,     X86::VMOVDI2SSZrm,       0 },
810     { X86::VMOVAPDZrr,       X86::VMOVAPDZrm,         TB_ALIGN_64 },
811     { X86::VMOVAPSZrr,       X86::VMOVAPSZrm,         TB_ALIGN_64 },
812     { X86::VMOVDQA32Zrr,     X86::VMOVDQA32Zrm,       TB_ALIGN_64 },
813     { X86::VMOVDQA64Zrr,     X86::VMOVDQA64Zrm,       TB_ALIGN_64 },
814     { X86::VMOVDQU8Zrr,      X86::VMOVDQU8Zrm,        0 },
815     { X86::VMOVDQU16Zrr,     X86::VMOVDQU16Zrm,       0 },
816     { X86::VMOVDQU32Zrr,     X86::VMOVDQU32Zrm,       0 },
817     { X86::VMOVDQU64Zrr,     X86::VMOVDQU64Zrm,       0 },
818     { X86::VMOVUPDZrr,       X86::VMOVUPDZrm,         0 },
819     { X86::VMOVUPSZrr,       X86::VMOVUPSZrm,         0 },
820     { X86::VPABSDZrr,        X86::VPABSDZrm,          0 },
821     { X86::VPABSQZrr,        X86::VPABSQZrm,          0 },
822     { X86::VBROADCASTSSZr,   X86::VBROADCASTSSZm,     TB_NO_REVERSE },
823     { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm,     TB_NO_REVERSE },
824     { X86::VBROADCASTSDZr,   X86::VBROADCASTSDZm,     TB_NO_REVERSE },
825     { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm,     TB_NO_REVERSE },
826 
827     // AVX-512 foldable instructions (256-bit versions)
828     { X86::VMOVAPDZ256rr,        X86::VMOVAPDZ256rm,        TB_ALIGN_32 },
829     { X86::VMOVAPSZ256rr,        X86::VMOVAPSZ256rm,        TB_ALIGN_32 },
830     { X86::VMOVDQA32Z256rr,      X86::VMOVDQA32Z256rm,      TB_ALIGN_32 },
831     { X86::VMOVDQA64Z256rr,      X86::VMOVDQA64Z256rm,      TB_ALIGN_32 },
832     { X86::VMOVDQU8Z256rr,       X86::VMOVDQU8Z256rm,       0 },
833     { X86::VMOVDQU16Z256rr,      X86::VMOVDQU16Z256rm,      0 },
834     { X86::VMOVDQU32Z256rr,      X86::VMOVDQU32Z256rm,      0 },
835     { X86::VMOVDQU64Z256rr,      X86::VMOVDQU64Z256rm,      0 },
836     { X86::VMOVUPDZ256rr,        X86::VMOVUPDZ256rm,        0 },
837     { X86::VMOVUPSZ256rr,        X86::VMOVUPSZ256rm,        0 },
838     { X86::VBROADCASTSSZ256r,    X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
839     { X86::VBROADCASTSSZ256r_s,  X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
840     { X86::VBROADCASTSDZ256r,    X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
841     { X86::VBROADCASTSDZ256r_s,  X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
842 
843     // AVX-512 foldable instructions (128-bit versions)
844     { X86::VMOVAPDZ128rr,        X86::VMOVAPDZ128rm,        TB_ALIGN_16 },
845     { X86::VMOVAPSZ128rr,        X86::VMOVAPSZ128rm,        TB_ALIGN_16 },
846     { X86::VMOVDQA32Z128rr,      X86::VMOVDQA32Z128rm,      TB_ALIGN_16 },
847     { X86::VMOVDQA64Z128rr,      X86::VMOVDQA64Z128rm,      TB_ALIGN_16 },
848     { X86::VMOVDQU8Z128rr,       X86::VMOVDQU8Z128rm,       0 },
849     { X86::VMOVDQU16Z128rr,      X86::VMOVDQU16Z128rm,      0 },
850     { X86::VMOVDQU32Z128rr,      X86::VMOVDQU32Z128rm,      0 },
851     { X86::VMOVDQU64Z128rr,      X86::VMOVDQU64Z128rm,      0 },
852     { X86::VMOVUPDZ128rr,        X86::VMOVUPDZ128rm,        0 },
853     { X86::VMOVUPSZ128rr,        X86::VMOVUPSZ128rm,        0 },
854     { X86::VBROADCASTSSZ128r,    X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
855     { X86::VBROADCASTSSZ128r_s,  X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
856     // F16C foldable instructions
857     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
858     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
859 
860     // AES foldable instructions
861     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
862     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
863     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
864     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
865   };
866 
867   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
868     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
869                   Entry.RegOp, Entry.MemOp,
870                   // Index 1, folded load
871                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
872   }
873 
874   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
875     { X86::ADC32rr,         X86::ADC32rm,       0 },
876     { X86::ADC64rr,         X86::ADC64rm,       0 },
877     { X86::ADD16rr,         X86::ADD16rm,       0 },
878     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
879     { X86::ADD32rr,         X86::ADD32rm,       0 },
880     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
881     { X86::ADD64rr,         X86::ADD64rm,       0 },
882     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
883     { X86::ADD8rr,          X86::ADD8rm,        0 },
884     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
885     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
886     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
887     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
888     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
889     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
890     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
891     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
892     { X86::AND16rr,         X86::AND16rm,       0 },
893     { X86::AND32rr,         X86::AND32rm,       0 },
894     { X86::AND64rr,         X86::AND64rm,       0 },
895     { X86::AND8rr,          X86::AND8rm,        0 },
896     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
897     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
898     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
899     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
900     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
901     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
902     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
903     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
904     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
905     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
906     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
907     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
908     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
909     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
910     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
911     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
912     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
913     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
914     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
915     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
916     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
917     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
918     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
919     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
920     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
921     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
922     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
923     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
924     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
925     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
926     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
927     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
928     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
929     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
930     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
931     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
932     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
933     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
934     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
935     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
936     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
937     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
938     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
939     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
940     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
941     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
942     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
943     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
944     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
945     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
946     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
947     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
948     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
949     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
950     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
951     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
952     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
953     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
954     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
955     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
956     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
957     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
958     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
959     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
960     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
961     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
962     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
963     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
964     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
965     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
966 
967     // Do not fold Fs* scalar logical op loads because there are no scalar
968     // load variants for these instructions. When folded, the load is required
969     // to be 128-bits, so the load size would not match.
970 
971     { X86::FvANDNPDrr,      X86::FvANDNPDrm,    TB_ALIGN_16 },
972     { X86::FvANDNPSrr,      X86::FvANDNPSrm,    TB_ALIGN_16 },
973     { X86::FvANDPDrr,       X86::FvANDPDrm,     TB_ALIGN_16 },
974     { X86::FvANDPSrr,       X86::FvANDPSrm,     TB_ALIGN_16 },
975     { X86::FvORPDrr,        X86::FvORPDrm,      TB_ALIGN_16 },
976     { X86::FvORPSrr,        X86::FvORPSrm,      TB_ALIGN_16 },
977     { X86::FvXORPDrr,       X86::FvXORPDrm,     TB_ALIGN_16 },
978     { X86::FvXORPSrr,       X86::FvXORPSrm,     TB_ALIGN_16 },
979     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
980     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
981     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
982     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
983     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
984     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
985     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
986     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
987     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
988     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
989     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
990     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
991     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
992     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
993     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
994     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
995     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
996     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
997     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
998     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
999     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
1000     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
1001     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
1002     { X86::MINSDrr,         X86::MINSDrm,       0 },
1003     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
1004     { X86::MINSSrr,         X86::MINSSrm,       0 },
1005     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
1006     { X86::MOVLHPSrr,       X86::MOVHPSrm,      TB_NO_REVERSE },
1007     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1008     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1009     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1010     { X86::MULSDrr,         X86::MULSDrm,       0 },
1011     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
1012     { X86::MULSSrr,         X86::MULSSrm,       0 },
1013     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
1014     { X86::OR16rr,          X86::OR16rm,        0 },
1015     { X86::OR32rr,          X86::OR32rm,        0 },
1016     { X86::OR64rr,          X86::OR64rm,        0 },
1017     { X86::OR8rr,           X86::OR8rm,         0 },
1018     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1019     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1020     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1021     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1022     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1023     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1024     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1025     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1026     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1027     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1028     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1029     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1030     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1031     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1032     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
1033     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1034     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1035     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1036     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1037     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1038     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1039     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1040     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1041     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1042     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1043     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1044     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1045     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1046     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1047     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1048     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1049     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1050     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1051     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1052     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1053     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1054     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1055     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1056     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1057     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1058     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
1059     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1060     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1061     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1062     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1063     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1064     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1065     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1066     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1067     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1068     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1069     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1070     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1071     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1072     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1073     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
1074     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1075     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1076     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1077     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1078     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1079     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1080     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1081     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1082     { X86::PSIGNBrr128,     X86::PSIGNBrm128,   TB_ALIGN_16 },
1083     { X86::PSIGNWrr128,     X86::PSIGNWrm128,   TB_ALIGN_16 },
1084     { X86::PSIGNDrr128,     X86::PSIGNDrm128,   TB_ALIGN_16 },
1085     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1086     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1087     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1088     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1089     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1090     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1091     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1092     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1093     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1094     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1095     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1096     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1097     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1098     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1099     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1100     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1101     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1102     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1103     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1104     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1105     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1106     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1107     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1108     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1109     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1110     { X86::ROUNDSDr,        X86::ROUNDSDm,      0 },
1111     { X86::ROUNDSSr,        X86::ROUNDSSm,      0 },
1112     { X86::SBB32rr,         X86::SBB32rm,       0 },
1113     { X86::SBB64rr,         X86::SBB64rm,       0 },
1114     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1115     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1116     { X86::SUB16rr,         X86::SUB16rm,       0 },
1117     { X86::SUB32rr,         X86::SUB32rm,       0 },
1118     { X86::SUB64rr,         X86::SUB64rm,       0 },
1119     { X86::SUB8rr,          X86::SUB8rm,        0 },
1120     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1121     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1122     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1123     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1124     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1125     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1126     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1127     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1128     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1129     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1130     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1131     { X86::XOR16rr,         X86::XOR16rm,       0 },
1132     { X86::XOR32rr,         X86::XOR32rm,       0 },
1133     { X86::XOR64rr,         X86::XOR64rm,       0 },
1134     { X86::XOR8rr,          X86::XOR8rm,        0 },
1135     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1136     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1137 
1138     // MMX version of foldable instructions
1139     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1140     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1141     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1142     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1143     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1144     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1145     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1146     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1147     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1148     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1149     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1150     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1151     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1152     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1153     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1154     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1155     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1156     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1157     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1158     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1159     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1160     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1161     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1162     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1163     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1164     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1165     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1166     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1167     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1168     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1169     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1170     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1171     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1172     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1173     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1174     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1175     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1176     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1177     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1178     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1179     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1180     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1181     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1182     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1183     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1184     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1185     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1186     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1187     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1188     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1189     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1190     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1191     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1192     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1193     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1194     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1195     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1196     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1197     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1198     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1199     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1200     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1201     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1202     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1203     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1204     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1205     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1206     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1207     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1208     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1209 
1210     // 3DNow! version of foldable instructions
1211     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1212     { X86::PFACCrr,           X86::PFACCrm,           0 },
1213     { X86::PFADDrr,           X86::PFADDrm,           0 },
1214     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1215     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1216     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1217     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1218     { X86::PFMINrr,           X86::PFMINrm,           0 },
1219     { X86::PFMULrr,           X86::PFMULrm,           0 },
1220     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1221     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1222     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1223     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1224     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1225     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1226     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1227     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1228 
1229     // AVX 128-bit versions of foldable instructions
1230     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1231     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1232     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1233     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1234     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1235     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1236     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1237     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1238     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1239     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1240     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1241     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1242     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1243     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        0 },
1244     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1245     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      0 },
1246     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1247     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       0 },
1248     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1249     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       0 },
1250     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1251     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1252     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1253     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1254     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1255     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1256     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1257     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1258     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1259     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1260     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1261     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1262     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1263     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1264     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1265     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1266     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1267     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1268     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1269     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1270     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1271     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1272     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1273     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1274     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1275     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1276     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1277     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1278     // Do not fold VFs* loads because there are no scalar load variants for
1279     // these instructions. When folded, the load is required to be 128-bits, so
1280     // the load size would not match.
1281     { X86::VFvANDNPDrr,       X86::VFvANDNPDrm,        0 },
1282     { X86::VFvANDNPSrr,       X86::VFvANDNPSrm,        0 },
1283     { X86::VFvANDPDrr,        X86::VFvANDPDrm,         0 },
1284     { X86::VFvANDPSrr,        X86::VFvANDPSrm,         0 },
1285     { X86::VFvORPDrr,         X86::VFvORPDrm,          0 },
1286     { X86::VFvORPSrr,         X86::VFvORPSrm,          0 },
1287     { X86::VFvXORPDrr,        X86::VFvXORPDrm,         0 },
1288     { X86::VFvXORPSrr,        X86::VFvXORPSrm,         0 },
1289     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1290     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1291     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1292     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1293     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1294     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1295     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1296     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1297     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1298     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1299     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1300     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1301     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1302     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1303     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1304     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1305     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1306     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1307     { X86::VMOVLHPSrr,        X86::VMOVHPSrm,          TB_NO_REVERSE },
1308     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1309     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1310     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1311     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1312     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1313     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1314     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1315     { X86::VORPDrr,           X86::VORPDrm,            0 },
1316     { X86::VORPSrr,           X86::VORPSrm,            0 },
1317     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1318     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1319     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1320     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1321     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1322     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1323     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1324     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1325     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1326     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1327     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1328     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1329     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
1330     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1331     { X86::VPANDrr,           X86::VPANDrm,            0 },
1332     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1333     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1334     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1335     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1336     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1337     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1338     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1339     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1340     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1341     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1342     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1343     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1344     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1345     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1346     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1347     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1348     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1349     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1350     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1351     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1352     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1353     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1354     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1355     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1356     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1357     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1358     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1359     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1360     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1361     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1362     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1363     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1364     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1365     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1366     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1367     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1368     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1369     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1370     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1371     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1372     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1373     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1374     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1375     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1376     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1377     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1378     { X86::VPORrr,            X86::VPORrm,             0 },
1379     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1380     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1381     { X86::VPSIGNBrr128,      X86::VPSIGNBrm128,       0 },
1382     { X86::VPSIGNWrr128,      X86::VPSIGNWrm128,       0 },
1383     { X86::VPSIGNDrr128,      X86::VPSIGNDrm128,       0 },
1384     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1385     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1386     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1387     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1388     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1389     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1390     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1391     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1392     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1393     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1394     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1395     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1396     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1397     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1398     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1399     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1400     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1401     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1402     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1403     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1404     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1405     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1406     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1407     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1408     { X86::VPXORrr,           X86::VPXORrm,            0 },
1409     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1410     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1411     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1412     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1413     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1414     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1415     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1416     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1417     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1418     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1419     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1420     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1421     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1422     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1423     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1424     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1425 
1426     // AVX 256-bit foldable instructions
1427     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1428     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1429     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1430     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1431     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1432     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1433     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1434     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1435     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1436     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1437     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1438     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1439     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1440     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1441     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1442     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1443     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1444     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1445     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1446     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1447     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1448     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1449     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1450     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1451     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1452     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1453     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1454     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1455     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1456     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1457     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1458     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1459     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1460     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1461     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1462     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1463     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1464     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1465     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1466     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1467     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1468     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1469     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1470 
1471     // AVX2 foldable instructions
1472     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1473     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1474     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1475     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1476     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1477     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1478     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1479     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1480     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1481     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1482     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1483     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1484     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1485     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1486     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1487     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1488     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1489     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1490     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1491     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1492     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1493     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1494     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1495     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1496     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1497     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1498     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1499     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1500     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1501     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1502     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1503     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1504     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1505     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1506     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1507     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1508     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1509     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1510     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1511     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1512     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1513     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1514     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1515     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1516     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1517     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1518     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1519     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1520     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1521     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1522     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1523     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1524     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1525     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1526     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1527     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1528     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1529     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1530     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1531     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1532     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1533     { X86::VPORYrr,           X86::VPORYrm,            0 },
1534     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1535     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1536     { X86::VPSIGNBYrr256,     X86::VPSIGNBYrm256,      0 },
1537     { X86::VPSIGNWYrr256,     X86::VPSIGNWYrm256,      0 },
1538     { X86::VPSIGNDYrr256,     X86::VPSIGNDYrm256,      0 },
1539     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1540     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1541     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1542     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1543     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1544     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1545     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1546     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1547     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1548     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1549     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1550     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1551     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1552     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1553     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1554     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1555     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1556     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1557     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1558     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1559     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1560     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1561     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1562     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1563     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1564     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1565     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1566     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1567     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1568     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1569     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1570     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1571     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1572     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1573     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1574 
1575     // FMA4 foldable patterns
1576     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1577     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1578     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1579     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1580     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_NONE },
1581     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_NONE },
1582     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1583     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1584     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1585     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1586     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_NONE },
1587     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_NONE },
1588     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1589     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1590     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1591     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1592     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_NONE },
1593     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_NONE },
1594     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1595     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1596     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1597     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1598     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_NONE },
1599     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_NONE },
1600     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1601     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1602     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_NONE },
1603     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_NONE },
1604     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1605     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1606     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_NONE },
1607     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_NONE },
1608 
1609     // XOP foldable instructions
1610     { X86::VPCMOVrrr,         X86::VPCMOVrmr,           0 },
1611     { X86::VPCMOVrrrY,        X86::VPCMOVrmrY,          0 },
1612     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1613     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1614     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1615     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1616     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1617     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1618     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1619     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1620     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1621     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1622     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1623     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1624     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1625     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1626     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1627     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1628     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1629     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1630     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1631     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1632     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1633     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1634     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1635     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1636     { X86::VPPERMrrr,         X86::VPPERMrmr,           0 },
1637     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1638     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1639     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1640     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1641     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1642     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1643     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1644     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1645     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1646     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1647     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1648     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1649 
1650     // BMI/BMI2 foldable instructions
1651     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1652     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1653     { X86::MULX32rr,          X86::MULX32rm,            0 },
1654     { X86::MULX64rr,          X86::MULX64rm,            0 },
1655     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1656     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1657     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1658     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1659 
1660     // ADX foldable instructions
1661     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1662     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1663     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1664     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1665 
1666     // AVX-512 foldable instructions
1667     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1668     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1669     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1670     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1671     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1672     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1673     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1674     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1675     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1676     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1677     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1678     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1679     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1680     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1681     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1682     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1683     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1684     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1685     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1686     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1687     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1688     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1689     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1690     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1691     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1692     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1693     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1694     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1695     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1696     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1697     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1698     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1699     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1700     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1701     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1702     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1703     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1704     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1705     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1706 
1707     // AVX-512{F,VL} foldable instructions
1708     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1709     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1710     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1711 
1712     // AVX-512{F,VL} foldable instructions
1713     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1714     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1715     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1716     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1717 
1718     // AES foldable instructions
1719     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1720     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1721     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1722     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1723     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
1724     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
1725     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
1726     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
1727 
1728     // SHA foldable instructions
1729     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1730     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1731     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1732     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1733     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1734     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1735     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
1736   };
1737 
1738   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
1739     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1740                   Entry.RegOp, Entry.MemOp,
1741                   // Index 2, folded load
1742                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1743   }
1744 
1745   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1746     // FMA foldable instructions
1747     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1748     { X86::VFMADDSSr231r_Int,     X86::VFMADDSSr231m_Int,     TB_ALIGN_NONE },
1749     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1750     { X86::VFMADDSDr231r_Int,     X86::VFMADDSDr231m_Int,     TB_ALIGN_NONE },
1751     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1752     { X86::VFMADDSSr132r_Int,     X86::VFMADDSSr132m_Int,     TB_ALIGN_NONE },
1753     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1754     { X86::VFMADDSDr132r_Int,     X86::VFMADDSDr132m_Int,     TB_ALIGN_NONE },
1755     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1756     { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     TB_ALIGN_NONE },
1757     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1758     { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     TB_ALIGN_NONE },
1759 
1760     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1761     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1762     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1763     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1764     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1765     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1766     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1767     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1768     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1769     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1770     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1771     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1772 
1773     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1774     { X86::VFNMADDSSr231r_Int,    X86::VFNMADDSSr231m_Int,    TB_ALIGN_NONE },
1775     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1776     { X86::VFNMADDSDr231r_Int,    X86::VFNMADDSDr231m_Int,    TB_ALIGN_NONE },
1777     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1778     { X86::VFNMADDSSr132r_Int,    X86::VFNMADDSSr132m_Int,    TB_ALIGN_NONE },
1779     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1780     { X86::VFNMADDSDr132r_Int,    X86::VFNMADDSDr132m_Int,    TB_ALIGN_NONE },
1781     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1782     { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    TB_ALIGN_NONE },
1783     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1784     { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    TB_ALIGN_NONE },
1785 
1786     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1787     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1788     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1789     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1790     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1791     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1792     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1793     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1794     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1795     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1796     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1797     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1798 
1799     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1800     { X86::VFMSUBSSr231r_Int,     X86::VFMSUBSSr231m_Int,     TB_ALIGN_NONE },
1801     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1802     { X86::VFMSUBSDr231r_Int,     X86::VFMSUBSDr231m_Int,     TB_ALIGN_NONE },
1803     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1804     { X86::VFMSUBSSr132r_Int,     X86::VFMSUBSSr132m_Int,     TB_ALIGN_NONE },
1805     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1806     { X86::VFMSUBSDr132r_Int,     X86::VFMSUBSDr132m_Int,     TB_ALIGN_NONE },
1807     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1808     { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     TB_ALIGN_NONE },
1809     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1810     { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     TB_ALIGN_NONE },
1811 
1812     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1813     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1814     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1815     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1816     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1817     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1818     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1819     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1820     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1821     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1822     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1823     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1824 
1825     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1826     { X86::VFNMSUBSSr231r_Int,    X86::VFNMSUBSSr231m_Int,    TB_ALIGN_NONE },
1827     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1828     { X86::VFNMSUBSDr231r_Int,    X86::VFNMSUBSDr231m_Int,    TB_ALIGN_NONE },
1829     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1830     { X86::VFNMSUBSSr132r_Int,    X86::VFNMSUBSSr132m_Int,    TB_ALIGN_NONE },
1831     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1832     { X86::VFNMSUBSDr132r_Int,    X86::VFNMSUBSDr132m_Int,    TB_ALIGN_NONE },
1833     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1834     { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    TB_ALIGN_NONE },
1835     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1836     { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    TB_ALIGN_NONE },
1837 
1838     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1839     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1840     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1841     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1842     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1843     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1844     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1845     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1846     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1847     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1848     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1849     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1850 
1851     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1852     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1853     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1854     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1855     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1856     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1857     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1858     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1859     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1860     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1861     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1862     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1863 
1864     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1865     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1866     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1867     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1868     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1869     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1870     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1871     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1872     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1873     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1874     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1875     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1876 
1877     // FMA4 foldable patterns
1878     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
1879     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
1880     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
1881     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
1882     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_NONE },
1883     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_NONE },
1884     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
1885     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
1886     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
1887     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
1888     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_NONE },
1889     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_NONE },
1890     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
1891     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
1892     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
1893     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
1894     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_NONE },
1895     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_NONE },
1896     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
1897     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
1898     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
1899     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
1900     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_NONE },
1901     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_NONE },
1902     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
1903     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
1904     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_NONE },
1905     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_NONE },
1906     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
1907     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
1908     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_NONE },
1909     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_NONE },
1910 
1911     // XOP foldable instructions
1912     { X86::VPCMOVrrr,             X86::VPCMOVrrm,             0 },
1913     { X86::VPCMOVrrrY,            X86::VPCMOVrrmY,            0 },
1914     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
1915     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
1916     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
1917     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
1918     { X86::VPPERMrrr,             X86::VPPERMrrm,             0 },
1919 
1920     // AVX-512 VPERMI instructions with 3 source operands.
1921     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1922     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1923     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1924     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1925     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1926     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1927     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1928     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1929     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1930     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1931     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1932     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1933     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
1934      // AVX-512 arithmetic instructions
1935     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
1936     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
1937     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
1938     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
1939     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
1940     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
1941     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
1942     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
1943     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
1944     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
1945     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
1946     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
1947     // AVX-512{F,VL} arithmetic instructions 256-bit
1948     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
1949     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
1950     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
1951     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
1952     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
1953     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
1954     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
1955     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
1956     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
1957     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
1958     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
1959     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
1960     // AVX-512{F,VL} arithmetic instructions 128-bit
1961     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
1962     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
1963     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
1964     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
1965     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
1966     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
1967     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
1968     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
1969     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
1970     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
1971     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
1972     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
1973   };
1974 
1975   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
1976     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1977                   Entry.RegOp, Entry.MemOp,
1978                   // Index 3, folded load
1979                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1980   }
1981 
1982   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
1983      // AVX-512 foldable instructions
1984     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
1985     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
1986     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
1987     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
1988     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
1989     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
1990     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
1991     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
1992     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
1993     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
1994     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
1995     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
1996     // AVX-512{F,VL} foldable instructions 256-bit
1997     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
1998     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
1999     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
2000     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
2001     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
2002     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
2003     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
2004     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
2005     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
2006     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
2007     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
2008     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
2009     // AVX-512{F,VL} foldable instructions 128-bit
2010     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
2011     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
2012     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
2013     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
2014     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
2015     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
2016     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
2017     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
2018     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
2019     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
2020     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
2021     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
2022   };
2023 
2024   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
2025     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2026                   Entry.RegOp, Entry.MemOp,
2027                   // Index 4, folded load
2028                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
2029   }
2030 }
2031 
2032 void
2033 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2034                             MemOp2RegOpTableType &M2RTable,
2035                             uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
2036     if ((Flags & TB_NO_FORWARD) == 0) {
2037       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2038       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2039     }
2040     if ((Flags & TB_NO_REVERSE) == 0) {
2041       assert(!M2RTable.count(MemOp) &&
2042            "Duplicated entries in unfolding maps?");
2043       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2044     }
2045 }
2046 
2047 bool
2048 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2049                                     unsigned &SrcReg, unsigned &DstReg,
2050                                     unsigned &SubIdx) const {
2051   switch (MI.getOpcode()) {
2052   default: break;
2053   case X86::MOVSX16rr8:
2054   case X86::MOVZX16rr8:
2055   case X86::MOVSX32rr8:
2056   case X86::MOVZX32rr8:
2057   case X86::MOVSX64rr8:
2058     if (!Subtarget.is64Bit())
2059       // It's not always legal to reference the low 8-bit of the larger
2060       // register in 32-bit mode.
2061       return false;
2062   case X86::MOVSX32rr16:
2063   case X86::MOVZX32rr16:
2064   case X86::MOVSX64rr16:
2065   case X86::MOVSX64rr32: {
2066     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2067       // Be conservative.
2068       return false;
2069     SrcReg = MI.getOperand(1).getReg();
2070     DstReg = MI.getOperand(0).getReg();
2071     switch (MI.getOpcode()) {
2072     default: llvm_unreachable("Unreachable!");
2073     case X86::MOVSX16rr8:
2074     case X86::MOVZX16rr8:
2075     case X86::MOVSX32rr8:
2076     case X86::MOVZX32rr8:
2077     case X86::MOVSX64rr8:
2078       SubIdx = X86::sub_8bit;
2079       break;
2080     case X86::MOVSX32rr16:
2081     case X86::MOVZX32rr16:
2082     case X86::MOVSX64rr16:
2083       SubIdx = X86::sub_16bit;
2084       break;
2085     case X86::MOVSX64rr32:
2086       SubIdx = X86::sub_32bit;
2087       break;
2088     }
2089     return true;
2090   }
2091   }
2092   return false;
2093 }
2094 
2095 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
2096   const MachineFunction *MF = MI->getParent()->getParent();
2097   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2098 
2099   if (MI->getOpcode() == getCallFrameSetupOpcode() ||
2100       MI->getOpcode() == getCallFrameDestroyOpcode()) {
2101     unsigned StackAlign = TFI->getStackAlignment();
2102     int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
2103                  StackAlign;
2104 
2105     SPAdj -= MI->getOperand(1).getImm();
2106 
2107     if (MI->getOpcode() == getCallFrameSetupOpcode())
2108       return SPAdj;
2109     else
2110       return -SPAdj;
2111   }
2112 
2113   // To know whether a call adjusts the stack, we need information
2114   // that is bound to the following ADJCALLSTACKUP pseudo.
2115   // Look for the next ADJCALLSTACKUP that follows the call.
2116   if (MI->isCall()) {
2117     const MachineBasicBlock* MBB = MI->getParent();
2118     auto I = ++MachineBasicBlock::const_iterator(MI);
2119     for (auto E = MBB->end(); I != E; ++I) {
2120       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2121           I->isCall())
2122         break;
2123     }
2124 
2125     // If we could not find a frame destroy opcode, then it has already
2126     // been simplified, so we don't care.
2127     if (I->getOpcode() != getCallFrameDestroyOpcode())
2128       return 0;
2129 
2130     return -(I->getOperand(1).getImm());
2131   }
2132 
2133   // Currently handle only PUSHes we can reasonably expect to see
2134   // in call sequences
2135   switch (MI->getOpcode()) {
2136   default:
2137     return 0;
2138   case X86::PUSH32i8:
2139   case X86::PUSH32r:
2140   case X86::PUSH32rmm:
2141   case X86::PUSH32rmr:
2142   case X86::PUSHi32:
2143     return 4;
2144   case X86::PUSH64i8:
2145   case X86::PUSH64r:
2146   case X86::PUSH64rmm:
2147   case X86::PUSH64rmr:
2148   case X86::PUSH64i32:
2149     return 8;
2150   }
2151 }
2152 
2153 /// Return true and the FrameIndex if the specified
2154 /// operand and follow operands form a reference to the stack frame.
2155 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2156                                   int &FrameIndex) const {
2157   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2158       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2159       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2160       MI->getOperand(Op+X86::AddrDisp).isImm() &&
2161       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2162       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2163       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2164     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
2165     return true;
2166   }
2167   return false;
2168 }
2169 
2170 static bool isFrameLoadOpcode(int Opcode) {
2171   switch (Opcode) {
2172   default:
2173     return false;
2174   case X86::MOV8rm:
2175   case X86::MOV16rm:
2176   case X86::MOV32rm:
2177   case X86::MOV64rm:
2178   case X86::LD_Fp64m:
2179   case X86::MOVSSrm:
2180   case X86::MOVSDrm:
2181   case X86::MOVAPSrm:
2182   case X86::MOVAPDrm:
2183   case X86::MOVDQArm:
2184   case X86::VMOVSSrm:
2185   case X86::VMOVSDrm:
2186   case X86::VMOVAPSrm:
2187   case X86::VMOVAPDrm:
2188   case X86::VMOVDQArm:
2189   case X86::VMOVUPSYrm:
2190   case X86::VMOVAPSYrm:
2191   case X86::VMOVUPDYrm:
2192   case X86::VMOVAPDYrm:
2193   case X86::VMOVDQUYrm:
2194   case X86::VMOVDQAYrm:
2195   case X86::MMX_MOVD64rm:
2196   case X86::MMX_MOVQ64rm:
2197   case X86::VMOVAPSZrm:
2198   case X86::VMOVUPSZrm:
2199     return true;
2200   }
2201 }
2202 
2203 static bool isFrameStoreOpcode(int Opcode) {
2204   switch (Opcode) {
2205   default: break;
2206   case X86::MOV8mr:
2207   case X86::MOV16mr:
2208   case X86::MOV32mr:
2209   case X86::MOV64mr:
2210   case X86::ST_FpP64m:
2211   case X86::MOVSSmr:
2212   case X86::MOVSDmr:
2213   case X86::MOVAPSmr:
2214   case X86::MOVAPDmr:
2215   case X86::MOVDQAmr:
2216   case X86::VMOVSSmr:
2217   case X86::VMOVSDmr:
2218   case X86::VMOVAPSmr:
2219   case X86::VMOVAPDmr:
2220   case X86::VMOVDQAmr:
2221   case X86::VMOVUPSYmr:
2222   case X86::VMOVAPSYmr:
2223   case X86::VMOVUPDYmr:
2224   case X86::VMOVAPDYmr:
2225   case X86::VMOVDQUYmr:
2226   case X86::VMOVDQAYmr:
2227   case X86::VMOVUPSZmr:
2228   case X86::VMOVAPSZmr:
2229   case X86::MMX_MOVD64mr:
2230   case X86::MMX_MOVQ64mr:
2231   case X86::MMX_MOVNTQmr:
2232     return true;
2233   }
2234   return false;
2235 }
2236 
2237 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
2238                                            int &FrameIndex) const {
2239   if (isFrameLoadOpcode(MI->getOpcode()))
2240     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2241       return MI->getOperand(0).getReg();
2242   return 0;
2243 }
2244 
2245 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
2246                                                  int &FrameIndex) const {
2247   if (isFrameLoadOpcode(MI->getOpcode())) {
2248     unsigned Reg;
2249     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2250       return Reg;
2251     // Check for post-frame index elimination operations
2252     const MachineMemOperand *Dummy;
2253     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2254   }
2255   return 0;
2256 }
2257 
2258 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
2259                                           int &FrameIndex) const {
2260   if (isFrameStoreOpcode(MI->getOpcode()))
2261     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2262         isFrameOperand(MI, 0, FrameIndex))
2263       return MI->getOperand(X86::AddrNumOperands).getReg();
2264   return 0;
2265 }
2266 
2267 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2268                                                 int &FrameIndex) const {
2269   if (isFrameStoreOpcode(MI->getOpcode())) {
2270     unsigned Reg;
2271     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2272       return Reg;
2273     // Check for post-frame index elimination operations
2274     const MachineMemOperand *Dummy;
2275     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2276   }
2277   return 0;
2278 }
2279 
2280 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2281 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2282   // Don't waste compile time scanning use-def chains of physregs.
2283   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2284     return false;
2285   bool isPICBase = false;
2286   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2287          E = MRI.def_instr_end(); I != E; ++I) {
2288     MachineInstr *DefMI = &*I;
2289     if (DefMI->getOpcode() != X86::MOVPC32r)
2290       return false;
2291     assert(!isPICBase && "More than one PIC base?");
2292     isPICBase = true;
2293   }
2294   return isPICBase;
2295 }
2296 
2297 bool
2298 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2299                                                 AliasAnalysis *AA) const {
2300   switch (MI->getOpcode()) {
2301   default: break;
2302   case X86::MOV8rm:
2303   case X86::MOV16rm:
2304   case X86::MOV32rm:
2305   case X86::MOV64rm:
2306   case X86::LD_Fp64m:
2307   case X86::MOVSSrm:
2308   case X86::MOVSDrm:
2309   case X86::MOVAPSrm:
2310   case X86::MOVUPSrm:
2311   case X86::MOVAPDrm:
2312   case X86::MOVDQArm:
2313   case X86::MOVDQUrm:
2314   case X86::VMOVSSrm:
2315   case X86::VMOVSDrm:
2316   case X86::VMOVAPSrm:
2317   case X86::VMOVUPSrm:
2318   case X86::VMOVAPDrm:
2319   case X86::VMOVDQArm:
2320   case X86::VMOVDQUrm:
2321   case X86::VMOVAPSYrm:
2322   case X86::VMOVUPSYrm:
2323   case X86::VMOVAPDYrm:
2324   case X86::VMOVDQAYrm:
2325   case X86::VMOVDQUYrm:
2326   case X86::MMX_MOVD64rm:
2327   case X86::MMX_MOVQ64rm:
2328   case X86::FsVMOVAPSrm:
2329   case X86::FsVMOVAPDrm:
2330   case X86::FsMOVAPSrm:
2331   case X86::FsMOVAPDrm:
2332   // AVX-512
2333   case X86::VMOVAPDZ128rm:
2334   case X86::VMOVAPDZ256rm:
2335   case X86::VMOVAPDZrm:
2336   case X86::VMOVAPSZ128rm:
2337   case X86::VMOVAPSZ256rm:
2338   case X86::VMOVAPSZrm:
2339   case X86::VMOVDQA32Z128rm:
2340   case X86::VMOVDQA32Z256rm:
2341   case X86::VMOVDQA32Zrm:
2342   case X86::VMOVDQA64Z128rm:
2343   case X86::VMOVDQA64Z256rm:
2344   case X86::VMOVDQA64Zrm:
2345   case X86::VMOVDQU16Z128rm:
2346   case X86::VMOVDQU16Z256rm:
2347   case X86::VMOVDQU16Zrm:
2348   case X86::VMOVDQU32Z128rm:
2349   case X86::VMOVDQU32Z256rm:
2350   case X86::VMOVDQU32Zrm:
2351   case X86::VMOVDQU64Z128rm:
2352   case X86::VMOVDQU64Z256rm:
2353   case X86::VMOVDQU64Zrm:
2354   case X86::VMOVDQU8Z128rm:
2355   case X86::VMOVDQU8Z256rm:
2356   case X86::VMOVDQU8Zrm:
2357   case X86::VMOVUPSZ128rm:
2358   case X86::VMOVUPSZ256rm:
2359   case X86::VMOVUPSZrm: {
2360     // Loads from constant pools are trivially rematerializable.
2361     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2362         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2363         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2364         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2365         MI->isInvariantLoad(AA)) {
2366       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2367       if (BaseReg == 0 || BaseReg == X86::RIP)
2368         return true;
2369       // Allow re-materialization of PIC load.
2370       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
2371         return false;
2372       const MachineFunction &MF = *MI->getParent()->getParent();
2373       const MachineRegisterInfo &MRI = MF.getRegInfo();
2374       return regIsPICBase(BaseReg, MRI);
2375     }
2376     return false;
2377   }
2378 
2379   case X86::LEA32r:
2380   case X86::LEA64r: {
2381     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2382         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2383         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2384         !MI->getOperand(1+X86::AddrDisp).isReg()) {
2385       // lea fi#, lea GV, etc. are all rematerializable.
2386       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
2387         return true;
2388       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2389       if (BaseReg == 0)
2390         return true;
2391       // Allow re-materialization of lea PICBase + x.
2392       const MachineFunction &MF = *MI->getParent()->getParent();
2393       const MachineRegisterInfo &MRI = MF.getRegInfo();
2394       return regIsPICBase(BaseReg, MRI);
2395     }
2396     return false;
2397   }
2398   }
2399 
2400   // All other instructions marked M_REMATERIALIZABLE are always trivially
2401   // rematerializable.
2402   return true;
2403 }
2404 
2405 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2406                                          MachineBasicBlock::iterator I) const {
2407   MachineBasicBlock::iterator E = MBB.end();
2408 
2409   // For compile time consideration, if we are not able to determine the
2410   // safety after visiting 4 instructions in each direction, we will assume
2411   // it's not safe.
2412   MachineBasicBlock::iterator Iter = I;
2413   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2414     bool SeenDef = false;
2415     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2416       MachineOperand &MO = Iter->getOperand(j);
2417       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2418         SeenDef = true;
2419       if (!MO.isReg())
2420         continue;
2421       if (MO.getReg() == X86::EFLAGS) {
2422         if (MO.isUse())
2423           return false;
2424         SeenDef = true;
2425       }
2426     }
2427 
2428     if (SeenDef)
2429       // This instruction defines EFLAGS, no need to look any further.
2430       return true;
2431     ++Iter;
2432     // Skip over DBG_VALUE.
2433     while (Iter != E && Iter->isDebugValue())
2434       ++Iter;
2435   }
2436 
2437   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2438   // live in.
2439   if (Iter == E) {
2440     for (MachineBasicBlock *S : MBB.successors())
2441       if (S->isLiveIn(X86::EFLAGS))
2442         return false;
2443     return true;
2444   }
2445 
2446   MachineBasicBlock::iterator B = MBB.begin();
2447   Iter = I;
2448   for (unsigned i = 0; i < 4; ++i) {
2449     // If we make it to the beginning of the block, it's safe to clobber
2450     // EFLAGS iff EFLAGS is not live-in.
2451     if (Iter == B)
2452       return !MBB.isLiveIn(X86::EFLAGS);
2453 
2454     --Iter;
2455     // Skip over DBG_VALUE.
2456     while (Iter != B && Iter->isDebugValue())
2457       --Iter;
2458 
2459     bool SawKill = false;
2460     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2461       MachineOperand &MO = Iter->getOperand(j);
2462       // A register mask may clobber EFLAGS, but we should still look for a
2463       // live EFLAGS def.
2464       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2465         SawKill = true;
2466       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2467         if (MO.isDef()) return MO.isDead();
2468         if (MO.isKill()) SawKill = true;
2469       }
2470     }
2471 
2472     if (SawKill)
2473       // This instruction kills EFLAGS and doesn't redefine it, so
2474       // there's no need to look further.
2475       return true;
2476   }
2477 
2478   // Conservative answer.
2479   return false;
2480 }
2481 
2482 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2483                                  MachineBasicBlock::iterator I,
2484                                  unsigned DestReg, unsigned SubIdx,
2485                                  const MachineInstr *Orig,
2486                                  const TargetRegisterInfo &TRI) const {
2487   bool ClobbersEFLAGS = false;
2488   for (const MachineOperand &MO : Orig->operands()) {
2489     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2490       ClobbersEFLAGS = true;
2491       break;
2492     }
2493   }
2494 
2495   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2496     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2497     // effects.
2498     int Value;
2499     switch (Orig->getOpcode()) {
2500     case X86::MOV32r0:  Value = 0; break;
2501     case X86::MOV32r1:  Value = 1; break;
2502     case X86::MOV32r_1: Value = -1; break;
2503     default:
2504       llvm_unreachable("Unexpected instruction!");
2505     }
2506 
2507     DebugLoc DL = Orig->getDebugLoc();
2508     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2509       .addImm(Value);
2510   } else {
2511     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2512     MBB.insert(I, MI);
2513   }
2514 
2515   MachineInstr *NewMI = std::prev(I);
2516   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2517 }
2518 
2519 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2520 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr *MI) const {
2521   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2522     MachineOperand &MO = MI->getOperand(i);
2523     if (MO.isReg() && MO.isDef() &&
2524         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2525       return true;
2526     }
2527   }
2528   return false;
2529 }
2530 
2531 /// Check whether the shift count for a machine operand is non-zero.
2532 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2533                                               unsigned ShiftAmtOperandIdx) {
2534   // The shift count is six bits with the REX.W prefix and five bits without.
2535   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2536   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2537   return Imm & ShiftCountMask;
2538 }
2539 
2540 /// Check whether the given shift count is appropriate
2541 /// can be represented by a LEA instruction.
2542 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2543   // Left shift instructions can be transformed into load-effective-address
2544   // instructions if we can encode them appropriately.
2545   // A LEA instruction utilizes a SIB byte to encode its scale factor.
2546   // The SIB.scale field is two bits wide which means that we can encode any
2547   // shift amount less than 4.
2548   return ShAmt < 4 && ShAmt > 0;
2549 }
2550 
2551 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2552                                   unsigned Opc, bool AllowSP,
2553                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
2554                                   MachineOperand &ImplicitOp) const {
2555   MachineFunction &MF = *MI->getParent()->getParent();
2556   const TargetRegisterClass *RC;
2557   if (AllowSP) {
2558     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2559   } else {
2560     RC = Opc != X86::LEA32r ?
2561       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2562   }
2563   unsigned SrcReg = Src.getReg();
2564 
2565   // For both LEA64 and LEA32 the register already has essentially the right
2566   // type (32-bit or 64-bit) we may just need to forbid SP.
2567   if (Opc != X86::LEA64_32r) {
2568     NewSrc = SrcReg;
2569     isKill = Src.isKill();
2570     isUndef = Src.isUndef();
2571 
2572     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2573         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2574       return false;
2575 
2576     return true;
2577   }
2578 
2579   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2580   // another we need to add 64-bit registers to the final MI.
2581   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2582     ImplicitOp = Src;
2583     ImplicitOp.setImplicit();
2584 
2585     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
2586     MachineBasicBlock::LivenessQueryResult LQR =
2587       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2588 
2589     switch (LQR) {
2590     case MachineBasicBlock::LQR_Unknown:
2591       // We can't give sane liveness flags to the instruction, abandon LEA
2592       // formation.
2593       return false;
2594     case MachineBasicBlock::LQR_Live:
2595       isKill = MI->killsRegister(SrcReg);
2596       isUndef = false;
2597       break;
2598     default:
2599       // The physreg itself is dead, so we have to use it as an <undef>.
2600       isKill = false;
2601       isUndef = true;
2602       break;
2603     }
2604   } else {
2605     // Virtual register of the wrong class, we have to create a temporary 64-bit
2606     // vreg to feed into the LEA.
2607     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2608     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2609             get(TargetOpcode::COPY))
2610       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2611         .addOperand(Src);
2612 
2613     // Which is obviously going to be dead after we're done with it.
2614     isKill = true;
2615     isUndef = false;
2616   }
2617 
2618   // We've set all the parameters without issue.
2619   return true;
2620 }
2621 
2622 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2623 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2624 /// truncating back down to a 16-bit subregister.
2625 MachineInstr *
2626 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2627                                            MachineFunction::iterator &MFI,
2628                                            MachineBasicBlock::iterator &MBBI,
2629                                            LiveVariables *LV) const {
2630   MachineInstr *MI = MBBI;
2631   unsigned Dest = MI->getOperand(0).getReg();
2632   unsigned Src = MI->getOperand(1).getReg();
2633   bool isDead = MI->getOperand(0).isDead();
2634   bool isKill = MI->getOperand(1).isKill();
2635 
2636   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2637   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2638   unsigned Opc, leaInReg;
2639   if (Subtarget.is64Bit()) {
2640     Opc = X86::LEA64_32r;
2641     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2642   } else {
2643     Opc = X86::LEA32r;
2644     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2645   }
2646 
2647   // Build and insert into an implicit UNDEF value. This is OK because
2648   // well be shifting and then extracting the lower 16-bits.
2649   // This has the potential to cause partial register stall. e.g.
2650   //   movw    (%rbp,%rcx,2), %dx
2651   //   leal    -65(%rdx), %esi
2652   // But testing has shown this *does* help performance in 64-bit mode (at
2653   // least on modern x86 machines).
2654   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2655   MachineInstr *InsMI =
2656     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2657     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2658     .addReg(Src, getKillRegState(isKill));
2659 
2660   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2661                                     get(Opc), leaOutReg);
2662   switch (MIOpc) {
2663   default: llvm_unreachable("Unreachable!");
2664   case X86::SHL16ri: {
2665     unsigned ShAmt = MI->getOperand(2).getImm();
2666     MIB.addReg(0).addImm(1ULL << ShAmt)
2667        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2668     break;
2669   }
2670   case X86::INC16r:
2671     addRegOffset(MIB, leaInReg, true, 1);
2672     break;
2673   case X86::DEC16r:
2674     addRegOffset(MIB, leaInReg, true, -1);
2675     break;
2676   case X86::ADD16ri:
2677   case X86::ADD16ri8:
2678   case X86::ADD16ri_DB:
2679   case X86::ADD16ri8_DB:
2680     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2681     break;
2682   case X86::ADD16rr:
2683   case X86::ADD16rr_DB: {
2684     unsigned Src2 = MI->getOperand(2).getReg();
2685     bool isKill2 = MI->getOperand(2).isKill();
2686     unsigned leaInReg2 = 0;
2687     MachineInstr *InsMI2 = nullptr;
2688     if (Src == Src2) {
2689       // ADD16rr %reg1028<kill>, %reg1028
2690       // just a single insert_subreg.
2691       addRegReg(MIB, leaInReg, true, leaInReg, false);
2692     } else {
2693       if (Subtarget.is64Bit())
2694         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2695       else
2696         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2697       // Build and insert into an implicit UNDEF value. This is OK because
2698       // well be shifting and then extracting the lower 16-bits.
2699       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2700       InsMI2 =
2701         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2702         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2703         .addReg(Src2, getKillRegState(isKill2));
2704       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2705     }
2706     if (LV && isKill2 && InsMI2)
2707       LV->replaceKillInstruction(Src2, MI, InsMI2);
2708     break;
2709   }
2710   }
2711 
2712   MachineInstr *NewMI = MIB;
2713   MachineInstr *ExtMI =
2714     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2715     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2716     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2717 
2718   if (LV) {
2719     // Update live variables
2720     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2721     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2722     if (isKill)
2723       LV->replaceKillInstruction(Src, MI, InsMI);
2724     if (isDead)
2725       LV->replaceKillInstruction(Dest, MI, ExtMI);
2726   }
2727 
2728   return ExtMI;
2729 }
2730 
2731 /// This method must be implemented by targets that
2732 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2733 /// may be able to convert a two-address instruction into a true
2734 /// three-address instruction on demand.  This allows the X86 target (for
2735 /// example) to convert ADD and SHL instructions into LEA instructions if they
2736 /// would require register copies due to two-addressness.
2737 ///
2738 /// This method returns a null pointer if the transformation cannot be
2739 /// performed, otherwise it returns the new instruction.
2740 ///
2741 MachineInstr *
2742 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2743                                     MachineBasicBlock::iterator &MBBI,
2744                                     LiveVariables *LV) const {
2745   MachineInstr *MI = MBBI;
2746 
2747   // The following opcodes also sets the condition code register(s). Only
2748   // convert them to equivalent lea if the condition code register def's
2749   // are dead!
2750   if (hasLiveCondCodeDef(MI))
2751     return nullptr;
2752 
2753   MachineFunction &MF = *MI->getParent()->getParent();
2754   // All instructions input are two-addr instructions.  Get the known operands.
2755   const MachineOperand &Dest = MI->getOperand(0);
2756   const MachineOperand &Src = MI->getOperand(1);
2757 
2758   MachineInstr *NewMI = nullptr;
2759   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2760   // we have better subtarget support, enable the 16-bit LEA generation here.
2761   // 16-bit LEA is also slow on Core2.
2762   bool DisableLEA16 = true;
2763   bool is64Bit = Subtarget.is64Bit();
2764 
2765   unsigned MIOpc = MI->getOpcode();
2766   switch (MIOpc) {
2767   default: return nullptr;
2768   case X86::SHL64ri: {
2769     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2770     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2771     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2772 
2773     // LEA can't handle RSP.
2774     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2775         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2776                                            &X86::GR64_NOSPRegClass))
2777       return nullptr;
2778 
2779     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2780       .addOperand(Dest)
2781       .addReg(0).addImm(1ULL << ShAmt).addOperand(Src).addImm(0).addReg(0);
2782     break;
2783   }
2784   case X86::SHL32ri: {
2785     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2786     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2787     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2788 
2789     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2790 
2791     // LEA can't handle ESP.
2792     bool isKill, isUndef;
2793     unsigned SrcReg;
2794     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2795     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2796                         SrcReg, isKill, isUndef, ImplicitOp))
2797       return nullptr;
2798 
2799     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2800       .addOperand(Dest)
2801       .addReg(0).addImm(1ULL << ShAmt)
2802       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2803       .addImm(0).addReg(0);
2804     if (ImplicitOp.getReg() != 0)
2805       MIB.addOperand(ImplicitOp);
2806     NewMI = MIB;
2807 
2808     break;
2809   }
2810   case X86::SHL16ri: {
2811     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2812     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2813     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2814 
2815     if (DisableLEA16)
2816       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2817     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2818       .addOperand(Dest)
2819       .addReg(0).addImm(1ULL << ShAmt).addOperand(Src).addImm(0).addReg(0);
2820     break;
2821   }
2822   case X86::INC64r:
2823   case X86::INC32r: {
2824     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2825     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2826       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2827     bool isKill, isUndef;
2828     unsigned SrcReg;
2829     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2830     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2831                         SrcReg, isKill, isUndef, ImplicitOp))
2832       return nullptr;
2833 
2834     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2835         .addOperand(Dest)
2836         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2837     if (ImplicitOp.getReg() != 0)
2838       MIB.addOperand(ImplicitOp);
2839 
2840     NewMI = addOffset(MIB, 1);
2841     break;
2842   }
2843   case X86::INC16r:
2844     if (DisableLEA16)
2845       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2846                      : nullptr;
2847     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2848     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2849                       .addOperand(Dest).addOperand(Src), 1);
2850     break;
2851   case X86::DEC64r:
2852   case X86::DEC32r: {
2853     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2854     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2855       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2856 
2857     bool isKill, isUndef;
2858     unsigned SrcReg;
2859     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2860     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2861                         SrcReg, isKill, isUndef, ImplicitOp))
2862       return nullptr;
2863 
2864     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2865         .addOperand(Dest)
2866         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2867     if (ImplicitOp.getReg() != 0)
2868       MIB.addOperand(ImplicitOp);
2869 
2870     NewMI = addOffset(MIB, -1);
2871 
2872     break;
2873   }
2874   case X86::DEC16r:
2875     if (DisableLEA16)
2876       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2877                      : nullptr;
2878     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2879     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2880                       .addOperand(Dest).addOperand(Src), -1);
2881     break;
2882   case X86::ADD64rr:
2883   case X86::ADD64rr_DB:
2884   case X86::ADD32rr:
2885   case X86::ADD32rr_DB: {
2886     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2887     unsigned Opc;
2888     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2889       Opc = X86::LEA64r;
2890     else
2891       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2892 
2893     bool isKill, isUndef;
2894     unsigned SrcReg;
2895     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2896     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2897                         SrcReg, isKill, isUndef, ImplicitOp))
2898       return nullptr;
2899 
2900     const MachineOperand &Src2 = MI->getOperand(2);
2901     bool isKill2, isUndef2;
2902     unsigned SrcReg2;
2903     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2904     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2905                         SrcReg2, isKill2, isUndef2, ImplicitOp2))
2906       return nullptr;
2907 
2908     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2909       .addOperand(Dest);
2910     if (ImplicitOp.getReg() != 0)
2911       MIB.addOperand(ImplicitOp);
2912     if (ImplicitOp2.getReg() != 0)
2913       MIB.addOperand(ImplicitOp2);
2914 
2915     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2916 
2917     // Preserve undefness of the operands.
2918     NewMI->getOperand(1).setIsUndef(isUndef);
2919     NewMI->getOperand(3).setIsUndef(isUndef2);
2920 
2921     if (LV && Src2.isKill())
2922       LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2923     break;
2924   }
2925   case X86::ADD16rr:
2926   case X86::ADD16rr_DB: {
2927     if (DisableLEA16)
2928       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2929                      : nullptr;
2930     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2931     unsigned Src2 = MI->getOperand(2).getReg();
2932     bool isKill2 = MI->getOperand(2).isKill();
2933     NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2934                       .addOperand(Dest),
2935                       Src.getReg(), Src.isKill(), Src2, isKill2);
2936 
2937     // Preserve undefness of the operands.
2938     bool isUndef = MI->getOperand(1).isUndef();
2939     bool isUndef2 = MI->getOperand(2).isUndef();
2940     NewMI->getOperand(1).setIsUndef(isUndef);
2941     NewMI->getOperand(3).setIsUndef(isUndef2);
2942 
2943     if (LV && isKill2)
2944       LV->replaceKillInstruction(Src2, MI, NewMI);
2945     break;
2946   }
2947   case X86::ADD64ri32:
2948   case X86::ADD64ri8:
2949   case X86::ADD64ri32_DB:
2950   case X86::ADD64ri8_DB:
2951     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2952     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2953                       .addOperand(Dest).addOperand(Src),
2954                       MI->getOperand(2).getImm());
2955     break;
2956   case X86::ADD32ri:
2957   case X86::ADD32ri8:
2958   case X86::ADD32ri_DB:
2959   case X86::ADD32ri8_DB: {
2960     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2961     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2962 
2963     bool isKill, isUndef;
2964     unsigned SrcReg;
2965     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2966     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2967                         SrcReg, isKill, isUndef, ImplicitOp))
2968       return nullptr;
2969 
2970     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2971         .addOperand(Dest)
2972         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2973     if (ImplicitOp.getReg() != 0)
2974       MIB.addOperand(ImplicitOp);
2975 
2976     NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2977     break;
2978   }
2979   case X86::ADD16ri:
2980   case X86::ADD16ri8:
2981   case X86::ADD16ri_DB:
2982   case X86::ADD16ri8_DB:
2983     if (DisableLEA16)
2984       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2985                      : nullptr;
2986     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2987     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2988                       .addOperand(Dest).addOperand(Src),
2989                       MI->getOperand(2).getImm());
2990     break;
2991   }
2992 
2993   if (!NewMI) return nullptr;
2994 
2995   if (LV) {  // Update live variables
2996     if (Src.isKill())
2997       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2998     if (Dest.isDead())
2999       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
3000   }
3001 
3002   MFI->insert(MBBI, NewMI);          // Insert the new inst
3003   return NewMI;
3004 }
3005 
3006 /// Returns true if the given instruction opcode is FMA3.
3007 /// Otherwise, returns false.
3008 /// The second parameter is optional and is used as the second return from
3009 /// the function. It is set to true if the given instruction has FMA3 opcode
3010 /// that is used for lowering of scalar FMA intrinsics, and it is set to false
3011 /// otherwise.
3012 static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
3013   if (IsIntrinsic)
3014     *IsIntrinsic = false;
3015 
3016   switch (Opcode) {
3017     case X86::VFMADDSDr132r:      case X86::VFMADDSDr132m:
3018     case X86::VFMADDSSr132r:      case X86::VFMADDSSr132m:
3019     case X86::VFMSUBSDr132r:      case X86::VFMSUBSDr132m:
3020     case X86::VFMSUBSSr132r:      case X86::VFMSUBSSr132m:
3021     case X86::VFNMADDSDr132r:     case X86::VFNMADDSDr132m:
3022     case X86::VFNMADDSSr132r:     case X86::VFNMADDSSr132m:
3023     case X86::VFNMSUBSDr132r:     case X86::VFNMSUBSDr132m:
3024     case X86::VFNMSUBSSr132r:     case X86::VFNMSUBSSr132m:
3025 
3026     case X86::VFMADDSDr213r:      case X86::VFMADDSDr213m:
3027     case X86::VFMADDSSr213r:      case X86::VFMADDSSr213m:
3028     case X86::VFMSUBSDr213r:      case X86::VFMSUBSDr213m:
3029     case X86::VFMSUBSSr213r:      case X86::VFMSUBSSr213m:
3030     case X86::VFNMADDSDr213r:     case X86::VFNMADDSDr213m:
3031     case X86::VFNMADDSSr213r:     case X86::VFNMADDSSr213m:
3032     case X86::VFNMSUBSDr213r:     case X86::VFNMSUBSDr213m:
3033     case X86::VFNMSUBSSr213r:     case X86::VFNMSUBSSr213m:
3034 
3035     case X86::VFMADDSDr231r:      case X86::VFMADDSDr231m:
3036     case X86::VFMADDSSr231r:      case X86::VFMADDSSr231m:
3037     case X86::VFMSUBSDr231r:      case X86::VFMSUBSDr231m:
3038     case X86::VFMSUBSSr231r:      case X86::VFMSUBSSr231m:
3039     case X86::VFNMADDSDr231r:     case X86::VFNMADDSDr231m:
3040     case X86::VFNMADDSSr231r:     case X86::VFNMADDSSr231m:
3041     case X86::VFNMSUBSDr231r:     case X86::VFNMSUBSDr231m:
3042     case X86::VFNMSUBSSr231r:     case X86::VFNMSUBSSr231m:
3043 
3044     case X86::VFMADDSUBPDr132r:   case X86::VFMADDSUBPDr132m:
3045     case X86::VFMADDSUBPSr132r:   case X86::VFMADDSUBPSr132m:
3046     case X86::VFMSUBADDPDr132r:   case X86::VFMSUBADDPDr132m:
3047     case X86::VFMSUBADDPSr132r:   case X86::VFMSUBADDPSr132m:
3048     case X86::VFMADDSUBPDr132rY:  case X86::VFMADDSUBPDr132mY:
3049     case X86::VFMADDSUBPSr132rY:  case X86::VFMADDSUBPSr132mY:
3050     case X86::VFMSUBADDPDr132rY:  case X86::VFMSUBADDPDr132mY:
3051     case X86::VFMSUBADDPSr132rY:  case X86::VFMSUBADDPSr132mY:
3052 
3053     case X86::VFMADDPDr132r:      case X86::VFMADDPDr132m:
3054     case X86::VFMADDPSr132r:      case X86::VFMADDPSr132m:
3055     case X86::VFMSUBPDr132r:      case X86::VFMSUBPDr132m:
3056     case X86::VFMSUBPSr132r:      case X86::VFMSUBPSr132m:
3057     case X86::VFNMADDPDr132r:     case X86::VFNMADDPDr132m:
3058     case X86::VFNMADDPSr132r:     case X86::VFNMADDPSr132m:
3059     case X86::VFNMSUBPDr132r:     case X86::VFNMSUBPDr132m:
3060     case X86::VFNMSUBPSr132r:     case X86::VFNMSUBPSr132m:
3061     case X86::VFMADDPDr132rY:     case X86::VFMADDPDr132mY:
3062     case X86::VFMADDPSr132rY:     case X86::VFMADDPSr132mY:
3063     case X86::VFMSUBPDr132rY:     case X86::VFMSUBPDr132mY:
3064     case X86::VFMSUBPSr132rY:     case X86::VFMSUBPSr132mY:
3065     case X86::VFNMADDPDr132rY:    case X86::VFNMADDPDr132mY:
3066     case X86::VFNMADDPSr132rY:    case X86::VFNMADDPSr132mY:
3067     case X86::VFNMSUBPDr132rY:    case X86::VFNMSUBPDr132mY:
3068     case X86::VFNMSUBPSr132rY:    case X86::VFNMSUBPSr132mY:
3069 
3070     case X86::VFMADDSUBPDr213r:   case X86::VFMADDSUBPDr213m:
3071     case X86::VFMADDSUBPSr213r:   case X86::VFMADDSUBPSr213m:
3072     case X86::VFMSUBADDPDr213r:   case X86::VFMSUBADDPDr213m:
3073     case X86::VFMSUBADDPSr213r:   case X86::VFMSUBADDPSr213m:
3074     case X86::VFMADDSUBPDr213rY:  case X86::VFMADDSUBPDr213mY:
3075     case X86::VFMADDSUBPSr213rY:  case X86::VFMADDSUBPSr213mY:
3076     case X86::VFMSUBADDPDr213rY:  case X86::VFMSUBADDPDr213mY:
3077     case X86::VFMSUBADDPSr213rY:  case X86::VFMSUBADDPSr213mY:
3078 
3079     case X86::VFMADDPDr213r:      case X86::VFMADDPDr213m:
3080     case X86::VFMADDPSr213r:      case X86::VFMADDPSr213m:
3081     case X86::VFMSUBPDr213r:      case X86::VFMSUBPDr213m:
3082     case X86::VFMSUBPSr213r:      case X86::VFMSUBPSr213m:
3083     case X86::VFNMADDPDr213r:     case X86::VFNMADDPDr213m:
3084     case X86::VFNMADDPSr213r:     case X86::VFNMADDPSr213m:
3085     case X86::VFNMSUBPDr213r:     case X86::VFNMSUBPDr213m:
3086     case X86::VFNMSUBPSr213r:     case X86::VFNMSUBPSr213m:
3087     case X86::VFMADDPDr213rY:     case X86::VFMADDPDr213mY:
3088     case X86::VFMADDPSr213rY:     case X86::VFMADDPSr213mY:
3089     case X86::VFMSUBPDr213rY:     case X86::VFMSUBPDr213mY:
3090     case X86::VFMSUBPSr213rY:     case X86::VFMSUBPSr213mY:
3091     case X86::VFNMADDPDr213rY:    case X86::VFNMADDPDr213mY:
3092     case X86::VFNMADDPSr213rY:    case X86::VFNMADDPSr213mY:
3093     case X86::VFNMSUBPDr213rY:    case X86::VFNMSUBPDr213mY:
3094     case X86::VFNMSUBPSr213rY:    case X86::VFNMSUBPSr213mY:
3095 
3096     case X86::VFMADDSUBPDr231r:   case X86::VFMADDSUBPDr231m:
3097     case X86::VFMADDSUBPSr231r:   case X86::VFMADDSUBPSr231m:
3098     case X86::VFMSUBADDPDr231r:   case X86::VFMSUBADDPDr231m:
3099     case X86::VFMSUBADDPSr231r:   case X86::VFMSUBADDPSr231m:
3100     case X86::VFMADDSUBPDr231rY:  case X86::VFMADDSUBPDr231mY:
3101     case X86::VFMADDSUBPSr231rY:  case X86::VFMADDSUBPSr231mY:
3102     case X86::VFMSUBADDPDr231rY:  case X86::VFMSUBADDPDr231mY:
3103     case X86::VFMSUBADDPSr231rY:  case X86::VFMSUBADDPSr231mY:
3104 
3105     case X86::VFMADDPDr231r:      case X86::VFMADDPDr231m:
3106     case X86::VFMADDPSr231r:      case X86::VFMADDPSr231m:
3107     case X86::VFMSUBPDr231r:      case X86::VFMSUBPDr231m:
3108     case X86::VFMSUBPSr231r:      case X86::VFMSUBPSr231m:
3109     case X86::VFNMADDPDr231r:     case X86::VFNMADDPDr231m:
3110     case X86::VFNMADDPSr231r:     case X86::VFNMADDPSr231m:
3111     case X86::VFNMSUBPDr231r:     case X86::VFNMSUBPDr231m:
3112     case X86::VFNMSUBPSr231r:     case X86::VFNMSUBPSr231m:
3113     case X86::VFMADDPDr231rY:     case X86::VFMADDPDr231mY:
3114     case X86::VFMADDPSr231rY:     case X86::VFMADDPSr231mY:
3115     case X86::VFMSUBPDr231rY:     case X86::VFMSUBPDr231mY:
3116     case X86::VFMSUBPSr231rY:     case X86::VFMSUBPSr231mY:
3117     case X86::VFNMADDPDr231rY:    case X86::VFNMADDPDr231mY:
3118     case X86::VFNMADDPSr231rY:    case X86::VFNMADDPSr231mY:
3119     case X86::VFNMSUBPDr231rY:    case X86::VFNMSUBPDr231mY:
3120     case X86::VFNMSUBPSr231rY:    case X86::VFNMSUBPSr231mY:
3121       return true;
3122 
3123     case X86::VFMADDSDr132r_Int:  case X86::VFMADDSDr132m_Int:
3124     case X86::VFMADDSSr132r_Int:  case X86::VFMADDSSr132m_Int:
3125     case X86::VFMSUBSDr132r_Int:  case X86::VFMSUBSDr132m_Int:
3126     case X86::VFMSUBSSr132r_Int:  case X86::VFMSUBSSr132m_Int:
3127     case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int:
3128     case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int:
3129     case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int:
3130     case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int:
3131 
3132     case X86::VFMADDSDr213r_Int:  case X86::VFMADDSDr213m_Int:
3133     case X86::VFMADDSSr213r_Int:  case X86::VFMADDSSr213m_Int:
3134     case X86::VFMSUBSDr213r_Int:  case X86::VFMSUBSDr213m_Int:
3135     case X86::VFMSUBSSr213r_Int:  case X86::VFMSUBSSr213m_Int:
3136     case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int:
3137     case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int:
3138     case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int:
3139     case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int:
3140 
3141     case X86::VFMADDSDr231r_Int:  case X86::VFMADDSDr231m_Int:
3142     case X86::VFMADDSSr231r_Int:  case X86::VFMADDSSr231m_Int:
3143     case X86::VFMSUBSDr231r_Int:  case X86::VFMSUBSDr231m_Int:
3144     case X86::VFMSUBSSr231r_Int:  case X86::VFMSUBSSr231m_Int:
3145     case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int:
3146     case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
3147     case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
3148     case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
3149       if (IsIntrinsic)
3150         *IsIntrinsic = true;
3151       return true;
3152     default:
3153       return false;
3154   }
3155   llvm_unreachable("Opcode not handled by the switch");
3156 }
3157 
3158 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr *MI,
3159                                                    bool NewMI,
3160                                                    unsigned OpIdx1,
3161                                                    unsigned OpIdx2) const {
3162   switch (MI->getOpcode()) {
3163   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3164   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
3165   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
3166   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3167   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3168   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
3169     unsigned Opc;
3170     unsigned Size;
3171     switch (MI->getOpcode()) {
3172     default: llvm_unreachable("Unreachable!");
3173     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3174     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3175     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3176     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
3177     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3178     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
3179     }
3180     unsigned Amt = MI->getOperand(3).getImm();
3181     if (NewMI) {
3182       MachineFunction &MF = *MI->getParent()->getParent();
3183       MI = MF.CloneMachineInstr(MI);
3184       NewMI = false;
3185     }
3186     MI->setDesc(get(Opc));
3187     MI->getOperand(3).setImm(Size-Amt);
3188     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3189   }
3190   case X86::BLENDPDrri:
3191   case X86::BLENDPSrri:
3192   case X86::PBLENDWrri:
3193   case X86::VBLENDPDrri:
3194   case X86::VBLENDPSrri:
3195   case X86::VBLENDPDYrri:
3196   case X86::VBLENDPSYrri:
3197   case X86::VPBLENDDrri:
3198   case X86::VPBLENDWrri:
3199   case X86::VPBLENDDYrri:
3200   case X86::VPBLENDWYrri:{
3201     unsigned Mask;
3202     switch (MI->getOpcode()) {
3203     default: llvm_unreachable("Unreachable!");
3204     case X86::BLENDPDrri:    Mask = 0x03; break;
3205     case X86::BLENDPSrri:    Mask = 0x0F; break;
3206     case X86::PBLENDWrri:    Mask = 0xFF; break;
3207     case X86::VBLENDPDrri:   Mask = 0x03; break;
3208     case X86::VBLENDPSrri:   Mask = 0x0F; break;
3209     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
3210     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
3211     case X86::VPBLENDDrri:   Mask = 0x0F; break;
3212     case X86::VPBLENDWrri:   Mask = 0xFF; break;
3213     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
3214     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
3215     }
3216     // Only the least significant bits of Imm are used.
3217     unsigned Imm = MI->getOperand(3).getImm() & Mask;
3218     if (NewMI) {
3219       MachineFunction &MF = *MI->getParent()->getParent();
3220       MI = MF.CloneMachineInstr(MI);
3221       NewMI = false;
3222     }
3223     MI->getOperand(3).setImm(Mask ^ Imm);
3224     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3225   }
3226   case X86::PCLMULQDQrr:
3227   case X86::VPCLMULQDQrr:{
3228     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3229     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3230     unsigned Imm = MI->getOperand(3).getImm();
3231     unsigned Src1Hi = Imm & 0x01;
3232     unsigned Src2Hi = Imm & 0x10;
3233     if (NewMI) {
3234       MachineFunction &MF = *MI->getParent()->getParent();
3235       MI = MF.CloneMachineInstr(MI);
3236       NewMI = false;
3237     }
3238     MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3239     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3240   }
3241   case X86::CMPPDrri:
3242   case X86::CMPPSrri:
3243   case X86::VCMPPDrri:
3244   case X86::VCMPPSrri:
3245   case X86::VCMPPDYrri:
3246   case X86::VCMPPSYrri: {
3247     // Float comparison can be safely commuted for
3248     // Ordered/Unordered/Equal/NotEqual tests
3249     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3250     switch (Imm) {
3251     case 0x00: // EQUAL
3252     case 0x03: // UNORDERED
3253     case 0x04: // NOT EQUAL
3254     case 0x07: // ORDERED
3255       if (NewMI) {
3256         MachineFunction &MF = *MI->getParent()->getParent();
3257         MI = MF.CloneMachineInstr(MI);
3258         NewMI = false;
3259       }
3260       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3261     default:
3262       return nullptr;
3263     }
3264   }
3265   case X86::VPCOMBri: case X86::VPCOMUBri:
3266   case X86::VPCOMDri: case X86::VPCOMUDri:
3267   case X86::VPCOMQri: case X86::VPCOMUQri:
3268   case X86::VPCOMWri: case X86::VPCOMUWri: {
3269     // Flip comparison mode immediate (if necessary).
3270     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3271     switch (Imm) {
3272     case 0x00: Imm = 0x02; break; // LT -> GT
3273     case 0x01: Imm = 0x03; break; // LE -> GE
3274     case 0x02: Imm = 0x00; break; // GT -> LT
3275     case 0x03: Imm = 0x01; break; // GE -> LE
3276     case 0x04: // EQ
3277     case 0x05: // NE
3278     case 0x06: // FALSE
3279     case 0x07: // TRUE
3280     default:
3281       break;
3282     }
3283     if (NewMI) {
3284       MachineFunction &MF = *MI->getParent()->getParent();
3285       MI = MF.CloneMachineInstr(MI);
3286       NewMI = false;
3287     }
3288     MI->getOperand(3).setImm(Imm);
3289     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3290   }
3291   case X86::VPERM2F128rr:
3292   case X86::VPERM2I128rr: {
3293     // Flip permute source immediate.
3294     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3295     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
3296     unsigned Imm = MI->getOperand(3).getImm() & 0xFF;
3297     if (NewMI) {
3298       MachineFunction &MF = *MI->getParent()->getParent();
3299       MI = MF.CloneMachineInstr(MI);
3300       NewMI = false;
3301     }
3302     MI->getOperand(3).setImm(Imm ^ 0x22);
3303     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3304   }
3305   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
3306   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3307   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
3308   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3309   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3310   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
3311   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
3312   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3313   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3314   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
3315   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
3316   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3317   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
3318   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3319   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
3320   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3321     unsigned Opc;
3322     switch (MI->getOpcode()) {
3323     default: llvm_unreachable("Unreachable!");
3324     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
3325     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
3326     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
3327     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3328     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3329     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3330     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
3331     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
3332     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
3333     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3334     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3335     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
3336     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3337     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3338     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3339     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
3340     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
3341     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
3342     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
3343     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
3344     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
3345     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3346     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3347     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3348     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3349     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3350     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3351     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
3352     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
3353     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
3354     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
3355     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
3356     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
3357     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3358     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3359     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3360     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
3361     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
3362     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
3363     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3364     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3365     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3366     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
3367     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
3368     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
3369     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3370     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3371     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3372     }
3373     if (NewMI) {
3374       MachineFunction &MF = *MI->getParent()->getParent();
3375       MI = MF.CloneMachineInstr(MI);
3376       NewMI = false;
3377     }
3378     MI->setDesc(get(Opc));
3379     // Fallthrough intended.
3380   }
3381   default:
3382     if (isFMA3(MI->getOpcode())) {
3383       unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
3384       if (Opc == 0)
3385         return nullptr;
3386       if (NewMI) {
3387         MachineFunction &MF = *MI->getParent()->getParent();
3388         MI = MF.CloneMachineInstr(MI);
3389         NewMI = false;
3390       }
3391       MI->setDesc(get(Opc));
3392     }
3393     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3394   }
3395 }
3396 
3397 bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr *MI,
3398                                              unsigned &SrcOpIdx1,
3399                                              unsigned &SrcOpIdx2) const {
3400 
3401   unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3402 
3403   // Only the first RegOpsNum operands are commutable.
3404   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3405   // that the operand is not specified/fixed.
3406   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3407       (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3408     return false;
3409   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3410       (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3411     return false;
3412 
3413   // Look for two different register operands assumed to be commutable
3414   // regardless of the FMA opcode. The FMA opcode is adjusted later.
3415   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3416       SrcOpIdx2 == CommuteAnyOperandIndex) {
3417     unsigned CommutableOpIdx1 = SrcOpIdx1;
3418     unsigned CommutableOpIdx2 = SrcOpIdx2;
3419 
3420     // At least one of operands to be commuted is not specified and
3421     // this method is free to choose appropriate commutable operands.
3422     if (SrcOpIdx1 == SrcOpIdx2)
3423       // Both of operands are not fixed. By default set one of commutable
3424       // operands to the last register operand of the instruction.
3425       CommutableOpIdx2 = RegOpsNum;
3426     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3427       // Only one of operands is not fixed.
3428       CommutableOpIdx2 = SrcOpIdx1;
3429 
3430     // CommutableOpIdx2 is well defined now. Let's choose another commutable
3431     // operand and assign its index to CommutableOpIdx1.
3432     unsigned Op2Reg = MI->getOperand(CommutableOpIdx2).getReg();
3433     for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3434       // The commuted operands must have different registers.
3435       // Otherwise, the commute transformation does not change anything and
3436       // is useless then.
3437       if (Op2Reg != MI->getOperand(CommutableOpIdx1).getReg())
3438         break;
3439     }
3440 
3441     // No appropriate commutable operands were found.
3442     if (CommutableOpIdx1 == 0)
3443       return false;
3444 
3445     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3446     // to return those values.
3447     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3448                               CommutableOpIdx1, CommutableOpIdx2))
3449       return false;
3450   }
3451 
3452   // Check if we can adjust the opcode to preserve the semantics when
3453   // commute the register operands.
3454   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
3455 }
3456 
3457 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(MachineInstr *MI,
3458                                                       unsigned SrcOpIdx1,
3459                                                       unsigned SrcOpIdx2) const {
3460   unsigned Opc = MI->getOpcode();
3461 
3462   // Define the array that holds FMA opcodes in groups
3463   // of 3 opcodes(132, 213, 231) in each group.
3464   static const uint16_t RegularOpcodeGroups[][3] = {
3465     { X86::VFMADDSSr132r,   X86::VFMADDSSr213r,   X86::VFMADDSSr231r  },
3466     { X86::VFMADDSDr132r,   X86::VFMADDSDr213r,   X86::VFMADDSDr231r  },
3467     { X86::VFMADDPSr132r,   X86::VFMADDPSr213r,   X86::VFMADDPSr231r  },
3468     { X86::VFMADDPDr132r,   X86::VFMADDPDr213r,   X86::VFMADDPDr231r  },
3469     { X86::VFMADDPSr132rY,  X86::VFMADDPSr213rY,  X86::VFMADDPSr231rY },
3470     { X86::VFMADDPDr132rY,  X86::VFMADDPDr213rY,  X86::VFMADDPDr231rY },
3471     { X86::VFMADDSSr132m,   X86::VFMADDSSr213m,   X86::VFMADDSSr231m  },
3472     { X86::VFMADDSDr132m,   X86::VFMADDSDr213m,   X86::VFMADDSDr231m  },
3473     { X86::VFMADDPSr132m,   X86::VFMADDPSr213m,   X86::VFMADDPSr231m  },
3474     { X86::VFMADDPDr132m,   X86::VFMADDPDr213m,   X86::VFMADDPDr231m  },
3475     { X86::VFMADDPSr132mY,  X86::VFMADDPSr213mY,  X86::VFMADDPSr231mY },
3476     { X86::VFMADDPDr132mY,  X86::VFMADDPDr213mY,  X86::VFMADDPDr231mY },
3477 
3478     { X86::VFMSUBSSr132r,   X86::VFMSUBSSr213r,   X86::VFMSUBSSr231r  },
3479     { X86::VFMSUBSDr132r,   X86::VFMSUBSDr213r,   X86::VFMSUBSDr231r  },
3480     { X86::VFMSUBPSr132r,   X86::VFMSUBPSr213r,   X86::VFMSUBPSr231r  },
3481     { X86::VFMSUBPDr132r,   X86::VFMSUBPDr213r,   X86::VFMSUBPDr231r  },
3482     { X86::VFMSUBPSr132rY,  X86::VFMSUBPSr213rY,  X86::VFMSUBPSr231rY },
3483     { X86::VFMSUBPDr132rY,  X86::VFMSUBPDr213rY,  X86::VFMSUBPDr231rY },
3484     { X86::VFMSUBSSr132m,   X86::VFMSUBSSr213m,   X86::VFMSUBSSr231m  },
3485     { X86::VFMSUBSDr132m,   X86::VFMSUBSDr213m,   X86::VFMSUBSDr231m  },
3486     { X86::VFMSUBPSr132m,   X86::VFMSUBPSr213m,   X86::VFMSUBPSr231m  },
3487     { X86::VFMSUBPDr132m,   X86::VFMSUBPDr213m,   X86::VFMSUBPDr231m  },
3488     { X86::VFMSUBPSr132mY,  X86::VFMSUBPSr213mY,  X86::VFMSUBPSr231mY },
3489     { X86::VFMSUBPDr132mY,  X86::VFMSUBPDr213mY,  X86::VFMSUBPDr231mY },
3490 
3491     { X86::VFNMADDSSr132r,  X86::VFNMADDSSr213r,  X86::VFNMADDSSr231r  },
3492     { X86::VFNMADDSDr132r,  X86::VFNMADDSDr213r,  X86::VFNMADDSDr231r  },
3493     { X86::VFNMADDPSr132r,  X86::VFNMADDPSr213r,  X86::VFNMADDPSr231r  },
3494     { X86::VFNMADDPDr132r,  X86::VFNMADDPDr213r,  X86::VFNMADDPDr231r  },
3495     { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
3496     { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
3497     { X86::VFNMADDSSr132m,  X86::VFNMADDSSr213m,  X86::VFNMADDSSr231m  },
3498     { X86::VFNMADDSDr132m,  X86::VFNMADDSDr213m,  X86::VFNMADDSDr231m  },
3499     { X86::VFNMADDPSr132m,  X86::VFNMADDPSr213m,  X86::VFNMADDPSr231m  },
3500     { X86::VFNMADDPDr132m,  X86::VFNMADDPDr213m,  X86::VFNMADDPDr231m  },
3501     { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
3502     { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
3503 
3504     { X86::VFNMSUBSSr132r,  X86::VFNMSUBSSr213r,  X86::VFNMSUBSSr231r  },
3505     { X86::VFNMSUBSDr132r,  X86::VFNMSUBSDr213r,  X86::VFNMSUBSDr231r  },
3506     { X86::VFNMSUBPSr132r,  X86::VFNMSUBPSr213r,  X86::VFNMSUBPSr231r  },
3507     { X86::VFNMSUBPDr132r,  X86::VFNMSUBPDr213r,  X86::VFNMSUBPDr231r  },
3508     { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
3509     { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
3510     { X86::VFNMSUBSSr132m,  X86::VFNMSUBSSr213m,  X86::VFNMSUBSSr231m  },
3511     { X86::VFNMSUBSDr132m,  X86::VFNMSUBSDr213m,  X86::VFNMSUBSDr231m  },
3512     { X86::VFNMSUBPSr132m,  X86::VFNMSUBPSr213m,  X86::VFNMSUBPSr231m  },
3513     { X86::VFNMSUBPDr132m,  X86::VFNMSUBPDr213m,  X86::VFNMSUBPDr231m  },
3514     { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
3515     { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
3516 
3517     { X86::VFMADDSUBPSr132r,  X86::VFMADDSUBPSr213r,  X86::VFMADDSUBPSr231r  },
3518     { X86::VFMADDSUBPDr132r,  X86::VFMADDSUBPDr213r,  X86::VFMADDSUBPDr231r  },
3519     { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
3520     { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
3521     { X86::VFMADDSUBPSr132m,  X86::VFMADDSUBPSr213m,  X86::VFMADDSUBPSr231m  },
3522     { X86::VFMADDSUBPDr132m,  X86::VFMADDSUBPDr213m,  X86::VFMADDSUBPDr231m  },
3523     { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
3524     { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
3525 
3526     { X86::VFMSUBADDPSr132r,  X86::VFMSUBADDPSr213r,  X86::VFMSUBADDPSr231r  },
3527     { X86::VFMSUBADDPDr132r,  X86::VFMSUBADDPDr213r,  X86::VFMSUBADDPDr231r  },
3528     { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
3529     { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
3530     { X86::VFMSUBADDPSr132m,  X86::VFMSUBADDPSr213m,  X86::VFMSUBADDPSr231m  },
3531     { X86::VFMSUBADDPDr132m,  X86::VFMSUBADDPDr213m,  X86::VFMSUBADDPDr231m  },
3532     { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
3533     { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
3534   };
3535 
3536   // Define the array that holds FMA*_Int opcodes in groups
3537   // of 3 opcodes(132, 213, 231) in each group.
3538   static const uint16_t IntrinOpcodeGroups[][3] = {
3539     { X86::VFMADDSSr132r_Int,  X86::VFMADDSSr213r_Int,  X86::VFMADDSSr231r_Int },
3540     { X86::VFMADDSDr132r_Int,  X86::VFMADDSDr213r_Int,  X86::VFMADDSDr231r_Int },
3541     { X86::VFMADDSSr132m_Int,  X86::VFMADDSSr213m_Int,  X86::VFMADDSSr231m_Int },
3542     { X86::VFMADDSDr132m_Int,  X86::VFMADDSDr213m_Int,  X86::VFMADDSDr231m_Int },
3543 
3544     { X86::VFMSUBSSr132r_Int,  X86::VFMSUBSSr213r_Int,  X86::VFMSUBSSr231r_Int },
3545     { X86::VFMSUBSDr132r_Int,  X86::VFMSUBSDr213r_Int,  X86::VFMSUBSDr231r_Int },
3546     { X86::VFMSUBSSr132m_Int,  X86::VFMSUBSSr213m_Int,  X86::VFMSUBSSr231m_Int },
3547     { X86::VFMSUBSDr132m_Int,  X86::VFMSUBSDr213m_Int,  X86::VFMSUBSDr231m_Int },
3548 
3549     { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
3550     { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
3551     { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
3552     { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
3553 
3554     { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
3555     { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
3556     { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
3557     { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
3558   };
3559 
3560   const unsigned Form132Index = 0;
3561   const unsigned Form213Index = 1;
3562   const unsigned Form231Index = 2;
3563   const unsigned FormsNum = 3;
3564 
3565   bool IsIntrinOpcode;
3566   isFMA3(Opc, &IsIntrinOpcode);
3567 
3568   size_t GroupsNum;
3569   const uint16_t (*OpcodeGroups)[3];
3570   if (IsIntrinOpcode) {
3571     GroupsNum = array_lengthof(IntrinOpcodeGroups);
3572     OpcodeGroups = IntrinOpcodeGroups;
3573   } else {
3574     GroupsNum = array_lengthof(RegularOpcodeGroups);
3575     OpcodeGroups = RegularOpcodeGroups;
3576   }
3577 
3578   const uint16_t *FoundOpcodesGroup = nullptr;
3579   size_t FormIndex;
3580 
3581   // Look for the input opcode in the corresponding opcodes table.
3582   for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
3583          ++GroupIndex) {
3584     for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
3585       if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
3586         FoundOpcodesGroup = OpcodeGroups[GroupIndex];
3587         break;
3588       }
3589     }
3590   }
3591 
3592   // The input opcode does not match with any of the opcodes from the tables.
3593   // The unsupported FMA opcode must be added to one of the two opcode groups
3594   // defined above.
3595   assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
3596 
3597   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3598   if (SrcOpIdx1 > SrcOpIdx2)
3599     std::swap(SrcOpIdx1, SrcOpIdx2);
3600 
3601   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3602   // analysis. The commute optimization is legal only if all users of FMA*_Int
3603   // use only the lowest element of the FMA*_Int instruction. Such analysis are
3604   // not implemented yet. So, just return 0 in that case.
3605   // When such analysis are available this place will be the right place for
3606   // calling it.
3607   if (IsIntrinOpcode && SrcOpIdx1 == 1)
3608     return 0;
3609 
3610   unsigned Case;
3611   if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
3612     Case = 0;
3613   else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3614     Case = 1;
3615   else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3616     Case = 2;
3617   else
3618     return 0;
3619 
3620   // Define the FMA forms mapping array that helps to map input FMA form
3621   // to output FMA form to preserve the operation semantics after
3622   // commuting the operands.
3623   static const unsigned FormMapping[][3] = {
3624     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3625     // FMA132 A, C, b; ==> FMA231 C, A, b;
3626     // FMA213 B, A, c; ==> FMA213 A, B, c;
3627     // FMA231 C, A, b; ==> FMA132 A, C, b;
3628     { Form231Index, Form213Index, Form132Index },
3629     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3630     // FMA132 A, c, B; ==> FMA132 B, c, A;
3631     // FMA213 B, a, C; ==> FMA231 C, a, B;
3632     // FMA231 C, a, B; ==> FMA213 B, a, C;
3633     { Form132Index, Form231Index, Form213Index },
3634     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3635     // FMA132 a, C, B; ==> FMA213 a, B, C;
3636     // FMA213 b, A, C; ==> FMA132 b, C, A;
3637     // FMA231 c, A, B; ==> FMA231 c, B, A;
3638     { Form213Index, Form132Index, Form231Index }
3639   };
3640 
3641   // Everything is ready, just adjust the FMA opcode and return it.
3642   FormIndex = FormMapping[Case][FormIndex];
3643   return FoundOpcodesGroup[FormIndex];
3644 }
3645 
3646 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI,
3647                                          unsigned &SrcOpIdx1,
3648                                          unsigned &SrcOpIdx2) const {
3649   switch (MI->getOpcode()) {
3650     case X86::CMPPDrri:
3651     case X86::CMPPSrri:
3652     case X86::VCMPPDrri:
3653     case X86::VCMPPSrri:
3654     case X86::VCMPPDYrri:
3655     case X86::VCMPPSYrri: {
3656       // Float comparison can be safely commuted for
3657       // Ordered/Unordered/Equal/NotEqual tests
3658       unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3659       switch (Imm) {
3660         case 0x00: // EQUAL
3661         case 0x03: // UNORDERED
3662         case 0x04: // NOT EQUAL
3663         case 0x07: // ORDERED
3664           // The indices of the commutable operands are 1 and 2.
3665           // Assign them to the returned operand indices here.
3666           return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
3667       }
3668       return false;
3669     }
3670     default:
3671       if (isFMA3(MI->getOpcode()))
3672         return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3673       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3674   }
3675   return false;
3676 }
3677 
3678 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
3679   switch (BrOpc) {
3680   default: return X86::COND_INVALID;
3681   case X86::JE_1:  return X86::COND_E;
3682   case X86::JNE_1: return X86::COND_NE;
3683   case X86::JL_1:  return X86::COND_L;
3684   case X86::JLE_1: return X86::COND_LE;
3685   case X86::JG_1:  return X86::COND_G;
3686   case X86::JGE_1: return X86::COND_GE;
3687   case X86::JB_1:  return X86::COND_B;
3688   case X86::JBE_1: return X86::COND_BE;
3689   case X86::JA_1:  return X86::COND_A;
3690   case X86::JAE_1: return X86::COND_AE;
3691   case X86::JS_1:  return X86::COND_S;
3692   case X86::JNS_1: return X86::COND_NS;
3693   case X86::JP_1:  return X86::COND_P;
3694   case X86::JNP_1: return X86::COND_NP;
3695   case X86::JO_1:  return X86::COND_O;
3696   case X86::JNO_1: return X86::COND_NO;
3697   }
3698 }
3699 
3700 /// Return condition code of a SET opcode.
3701 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3702   switch (Opc) {
3703   default: return X86::COND_INVALID;
3704   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
3705   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3706   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
3707   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3708   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
3709   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
3710   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3711   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
3712   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3713   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3714   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3715   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3716   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3717   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
3718   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
3719   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
3720   }
3721 }
3722 
3723 /// Return condition code of a CMov opcode.
3724 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
3725   switch (Opc) {
3726   default: return X86::COND_INVALID;
3727   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
3728   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
3729     return X86::COND_A;
3730   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3731   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3732     return X86::COND_AE;
3733   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
3734   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
3735     return X86::COND_B;
3736   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3737   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3738     return X86::COND_BE;
3739   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
3740   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
3741     return X86::COND_E;
3742   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
3743   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
3744     return X86::COND_G;
3745   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3746   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3747     return X86::COND_GE;
3748   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
3749   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
3750     return X86::COND_L;
3751   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3752   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3753     return X86::COND_LE;
3754   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3755   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3756     return X86::COND_NE;
3757   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3758   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3759     return X86::COND_NO;
3760   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3761   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3762     return X86::COND_NP;
3763   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3764   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3765     return X86::COND_NS;
3766   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
3767   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
3768     return X86::COND_O;
3769   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
3770   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
3771     return X86::COND_P;
3772   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
3773   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
3774     return X86::COND_S;
3775   }
3776 }
3777 
3778 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3779   switch (CC) {
3780   default: llvm_unreachable("Illegal condition code!");
3781   case X86::COND_E:  return X86::JE_1;
3782   case X86::COND_NE: return X86::JNE_1;
3783   case X86::COND_L:  return X86::JL_1;
3784   case X86::COND_LE: return X86::JLE_1;
3785   case X86::COND_G:  return X86::JG_1;
3786   case X86::COND_GE: return X86::JGE_1;
3787   case X86::COND_B:  return X86::JB_1;
3788   case X86::COND_BE: return X86::JBE_1;
3789   case X86::COND_A:  return X86::JA_1;
3790   case X86::COND_AE: return X86::JAE_1;
3791   case X86::COND_S:  return X86::JS_1;
3792   case X86::COND_NS: return X86::JNS_1;
3793   case X86::COND_P:  return X86::JP_1;
3794   case X86::COND_NP: return X86::JNP_1;
3795   case X86::COND_O:  return X86::JO_1;
3796   case X86::COND_NO: return X86::JNO_1;
3797   }
3798 }
3799 
3800 /// Return the inverse of the specified condition,
3801 /// e.g. turning COND_E to COND_NE.
3802 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3803   switch (CC) {
3804   default: llvm_unreachable("Illegal condition code!");
3805   case X86::COND_E:  return X86::COND_NE;
3806   case X86::COND_NE: return X86::COND_E;
3807   case X86::COND_L:  return X86::COND_GE;
3808   case X86::COND_LE: return X86::COND_G;
3809   case X86::COND_G:  return X86::COND_LE;
3810   case X86::COND_GE: return X86::COND_L;
3811   case X86::COND_B:  return X86::COND_AE;
3812   case X86::COND_BE: return X86::COND_A;
3813   case X86::COND_A:  return X86::COND_BE;
3814   case X86::COND_AE: return X86::COND_B;
3815   case X86::COND_S:  return X86::COND_NS;
3816   case X86::COND_NS: return X86::COND_S;
3817   case X86::COND_P:  return X86::COND_NP;
3818   case X86::COND_NP: return X86::COND_P;
3819   case X86::COND_O:  return X86::COND_NO;
3820   case X86::COND_NO: return X86::COND_O;
3821   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
3822   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
3823   }
3824 }
3825 
3826 /// Assuming the flags are set by MI(a,b), return the condition code if we
3827 /// modify the instructions such that flags are set by MI(b,a).
3828 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3829   switch (CC) {
3830   default: return X86::COND_INVALID;
3831   case X86::COND_E:  return X86::COND_E;
3832   case X86::COND_NE: return X86::COND_NE;
3833   case X86::COND_L:  return X86::COND_G;
3834   case X86::COND_LE: return X86::COND_GE;
3835   case X86::COND_G:  return X86::COND_L;
3836   case X86::COND_GE: return X86::COND_LE;
3837   case X86::COND_B:  return X86::COND_A;
3838   case X86::COND_BE: return X86::COND_AE;
3839   case X86::COND_A:  return X86::COND_B;
3840   case X86::COND_AE: return X86::COND_BE;
3841   }
3842 }
3843 
3844 /// Return a set opcode for the given condition and
3845 /// whether it has memory operand.
3846 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
3847   static const uint16_t Opc[16][2] = {
3848     { X86::SETAr,  X86::SETAm  },
3849     { X86::SETAEr, X86::SETAEm },
3850     { X86::SETBr,  X86::SETBm  },
3851     { X86::SETBEr, X86::SETBEm },
3852     { X86::SETEr,  X86::SETEm  },
3853     { X86::SETGr,  X86::SETGm  },
3854     { X86::SETGEr, X86::SETGEm },
3855     { X86::SETLr,  X86::SETLm  },
3856     { X86::SETLEr, X86::SETLEm },
3857     { X86::SETNEr, X86::SETNEm },
3858     { X86::SETNOr, X86::SETNOm },
3859     { X86::SETNPr, X86::SETNPm },
3860     { X86::SETNSr, X86::SETNSm },
3861     { X86::SETOr,  X86::SETOm  },
3862     { X86::SETPr,  X86::SETPm  },
3863     { X86::SETSr,  X86::SETSm  }
3864   };
3865 
3866   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
3867   return Opc[CC][HasMemoryOperand ? 1 : 0];
3868 }
3869 
3870 /// Return a cmov opcode for the given condition,
3871 /// register size in bytes, and operand type.
3872 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3873                               bool HasMemoryOperand) {
3874   static const uint16_t Opc[32][3] = {
3875     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
3876     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3877     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
3878     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3879     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
3880     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
3881     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3882     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
3883     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3884     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3885     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3886     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3887     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3888     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
3889     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
3890     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
3891     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
3892     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3893     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
3894     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3895     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
3896     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
3897     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3898     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
3899     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3900     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3901     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3902     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3903     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3904     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
3905     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
3906     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
3907   };
3908 
3909   assert(CC < 16 && "Can only handle standard cond codes");
3910   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
3911   switch(RegBytes) {
3912   default: llvm_unreachable("Illegal register size!");
3913   case 2: return Opc[Idx][0];
3914   case 4: return Opc[Idx][1];
3915   case 8: return Opc[Idx][2];
3916   }
3917 }
3918 
3919 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
3920   if (!MI.isTerminator()) return false;
3921 
3922   // Conditional branch is a special case.
3923   if (MI.isBranch() && !MI.isBarrier())
3924     return true;
3925   if (!MI.isPredicable())
3926     return true;
3927   return !isPredicated(MI);
3928 }
3929 
3930 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
3931 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
3932 // fallthrough MBB cannot be identified.
3933 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3934                                             MachineBasicBlock *TBB) {
3935   // Look for non-EHPad successors other than TBB. If we find exactly one, it
3936   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
3937   // and fallthrough MBB. If we find more than one, we cannot identify the
3938   // fallthrough MBB and should return nullptr.
3939   MachineBasicBlock *FallthroughBB = nullptr;
3940   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
3941     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
3942       continue;
3943     // Return a nullptr if we found more than one fallthrough successor.
3944     if (FallthroughBB && FallthroughBB != TBB)
3945       return nullptr;
3946     FallthroughBB = *SI;
3947   }
3948   return FallthroughBB;
3949 }
3950 
3951 bool X86InstrInfo::AnalyzeBranchImpl(
3952     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3953     SmallVectorImpl<MachineOperand> &Cond,
3954     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3955 
3956   // Start from the bottom of the block and work up, examining the
3957   // terminator instructions.
3958   MachineBasicBlock::iterator I = MBB.end();
3959   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3960   while (I != MBB.begin()) {
3961     --I;
3962     if (I->isDebugValue())
3963       continue;
3964 
3965     // Working from the bottom, when we see a non-terminator instruction, we're
3966     // done.
3967     if (!isUnpredicatedTerminator(*I))
3968       break;
3969 
3970     // A terminator that isn't a branch can't easily be handled by this
3971     // analysis.
3972     if (!I->isBranch())
3973       return true;
3974 
3975     // Handle unconditional branches.
3976     if (I->getOpcode() == X86::JMP_1) {
3977       UnCondBrIter = I;
3978 
3979       if (!AllowModify) {
3980         TBB = I->getOperand(0).getMBB();
3981         continue;
3982       }
3983 
3984       // If the block has any instructions after a JMP, delete them.
3985       while (std::next(I) != MBB.end())
3986         std::next(I)->eraseFromParent();
3987 
3988       Cond.clear();
3989       FBB = nullptr;
3990 
3991       // Delete the JMP if it's equivalent to a fall-through.
3992       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3993         TBB = nullptr;
3994         I->eraseFromParent();
3995         I = MBB.end();
3996         UnCondBrIter = MBB.end();
3997         continue;
3998       }
3999 
4000       // TBB is used to indicate the unconditional destination.
4001       TBB = I->getOperand(0).getMBB();
4002       continue;
4003     }
4004 
4005     // Handle conditional branches.
4006     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
4007     if (BranchCode == X86::COND_INVALID)
4008       return true;  // Can't handle indirect branch.
4009 
4010     // Working from the bottom, handle the first conditional branch.
4011     if (Cond.empty()) {
4012       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4013       if (AllowModify && UnCondBrIter != MBB.end() &&
4014           MBB.isLayoutSuccessor(TargetBB)) {
4015         // If we can modify the code and it ends in something like:
4016         //
4017         //     jCC L1
4018         //     jmp L2
4019         //   L1:
4020         //     ...
4021         //   L2:
4022         //
4023         // Then we can change this to:
4024         //
4025         //     jnCC L2
4026         //   L1:
4027         //     ...
4028         //   L2:
4029         //
4030         // Which is a bit more efficient.
4031         // We conditionally jump to the fall-through block.
4032         BranchCode = GetOppositeBranchCondition(BranchCode);
4033         unsigned JNCC = GetCondBranchFromCond(BranchCode);
4034         MachineBasicBlock::iterator OldInst = I;
4035 
4036         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
4037           .addMBB(UnCondBrIter->getOperand(0).getMBB());
4038         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
4039           .addMBB(TargetBB);
4040 
4041         OldInst->eraseFromParent();
4042         UnCondBrIter->eraseFromParent();
4043 
4044         // Restart the analysis.
4045         UnCondBrIter = MBB.end();
4046         I = MBB.end();
4047         continue;
4048       }
4049 
4050       FBB = TBB;
4051       TBB = I->getOperand(0).getMBB();
4052       Cond.push_back(MachineOperand::CreateImm(BranchCode));
4053       CondBranches.push_back(I);
4054       continue;
4055     }
4056 
4057     // Handle subsequent conditional branches. Only handle the case where all
4058     // conditional branches branch to the same destination and their condition
4059     // opcodes fit one of the special multi-branch idioms.
4060     assert(Cond.size() == 1);
4061     assert(TBB);
4062 
4063     // If the conditions are the same, we can leave them alone.
4064     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
4065     auto NewTBB = I->getOperand(0).getMBB();
4066     if (OldBranchCode == BranchCode && TBB == NewTBB)
4067       continue;
4068 
4069     // If they differ, see if they fit one of the known patterns. Theoretically,
4070     // we could handle more patterns here, but we shouldn't expect to see them
4071     // if instruction selection has done a reasonable job.
4072     if (TBB == NewTBB &&
4073                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4074                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
4075       BranchCode = X86::COND_NE_OR_P;
4076     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4077                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4078       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4079         return true;
4080 
4081       // X86::COND_E_AND_NP usually has two different branch destinations.
4082       //
4083       // JP B1
4084       // JE B2
4085       // JMP B1
4086       // B1:
4087       // B2:
4088       //
4089       // Here this condition branches to B2 only if NP && E. It has another
4090       // equivalent form:
4091       //
4092       // JNE B1
4093       // JNP B2
4094       // JMP B1
4095       // B1:
4096       // B2:
4097       //
4098       // Similarly it branches to B2 only if E && NP. That is why this condition
4099       // is named with COND_E_AND_NP.
4100       BranchCode = X86::COND_E_AND_NP;
4101     } else
4102       return true;
4103 
4104     // Update the MachineOperand.
4105     Cond[0].setImm(BranchCode);
4106     CondBranches.push_back(I);
4107   }
4108 
4109   return false;
4110 }
4111 
4112 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
4113                                  MachineBasicBlock *&TBB,
4114                                  MachineBasicBlock *&FBB,
4115                                  SmallVectorImpl<MachineOperand> &Cond,
4116                                  bool AllowModify) const {
4117   SmallVector<MachineInstr *, 4> CondBranches;
4118   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4119 }
4120 
4121 bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB,
4122                                           MachineBranchPredicate &MBP,
4123                                           bool AllowModify) const {
4124   using namespace std::placeholders;
4125 
4126   SmallVector<MachineOperand, 4> Cond;
4127   SmallVector<MachineInstr *, 4> CondBranches;
4128   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4129                         AllowModify))
4130     return true;
4131 
4132   if (Cond.size() != 1)
4133     return true;
4134 
4135   assert(MBP.TrueDest && "expected!");
4136 
4137   if (!MBP.FalseDest)
4138     MBP.FalseDest = MBB.getNextNode();
4139 
4140   const TargetRegisterInfo *TRI = &getRegisterInfo();
4141 
4142   MachineInstr *ConditionDef = nullptr;
4143   bool SingleUseCondition = true;
4144 
4145   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4146     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4147       ConditionDef = &*I;
4148       break;
4149     }
4150 
4151     if (I->readsRegister(X86::EFLAGS, TRI))
4152       SingleUseCondition = false;
4153   }
4154 
4155   if (!ConditionDef)
4156     return true;
4157 
4158   if (SingleUseCondition) {
4159     for (auto *Succ : MBB.successors())
4160       if (Succ->isLiveIn(X86::EFLAGS))
4161         SingleUseCondition = false;
4162   }
4163 
4164   MBP.ConditionDef = ConditionDef;
4165   MBP.SingleUseCondition = SingleUseCondition;
4166 
4167   // Currently we only recognize the simple pattern:
4168   //
4169   //   test %reg, %reg
4170   //   je %label
4171   //
4172   const unsigned TestOpcode =
4173       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4174 
4175   if (ConditionDef->getOpcode() == TestOpcode &&
4176       ConditionDef->getNumOperands() == 3 &&
4177       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4178       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4179     MBP.LHS = ConditionDef->getOperand(0);
4180     MBP.RHS = MachineOperand::CreateImm(0);
4181     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4182                         ? MachineBranchPredicate::PRED_NE
4183                         : MachineBranchPredicate::PRED_EQ;
4184     return false;
4185   }
4186 
4187   return true;
4188 }
4189 
4190 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
4191   MachineBasicBlock::iterator I = MBB.end();
4192   unsigned Count = 0;
4193 
4194   while (I != MBB.begin()) {
4195     --I;
4196     if (I->isDebugValue())
4197       continue;
4198     if (I->getOpcode() != X86::JMP_1 &&
4199         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
4200       break;
4201     // Remove the branch.
4202     I->eraseFromParent();
4203     I = MBB.end();
4204     ++Count;
4205   }
4206 
4207   return Count;
4208 }
4209 
4210 unsigned
4211 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
4212                            MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
4213                            DebugLoc DL) const {
4214   // Shouldn't be a fall through.
4215   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
4216   assert((Cond.size() == 1 || Cond.size() == 0) &&
4217          "X86 branch conditions have one component!");
4218 
4219   if (Cond.empty()) {
4220     // Unconditional branch?
4221     assert(!FBB && "Unconditional branch with multiple successors!");
4222     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
4223     return 1;
4224   }
4225 
4226   // If FBB is null, it is implied to be a fall-through block.
4227   bool FallThru = FBB == nullptr;
4228 
4229   // Conditional branch.
4230   unsigned Count = 0;
4231   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4232   switch (CC) {
4233   case X86::COND_NE_OR_P:
4234     // Synthesize NE_OR_P with two branches.
4235     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
4236     ++Count;
4237     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
4238     ++Count;
4239     break;
4240   case X86::COND_E_AND_NP:
4241     // Use the next block of MBB as FBB if it is null.
4242     if (FBB == nullptr) {
4243       FBB = getFallThroughMBB(&MBB, TBB);
4244       assert(FBB && "MBB cannot be the last block in function when the false "
4245                     "body is a fall-through.");
4246     }
4247     // Synthesize COND_E_AND_NP with two branches.
4248     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4249     ++Count;
4250     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4251     ++Count;
4252     break;
4253   default: {
4254     unsigned Opc = GetCondBranchFromCond(CC);
4255     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
4256     ++Count;
4257   }
4258   }
4259   if (!FallThru) {
4260     // Two-way Conditional branch. Insert the second branch.
4261     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
4262     ++Count;
4263   }
4264   return Count;
4265 }
4266 
4267 bool X86InstrInfo::
4268 canInsertSelect(const MachineBasicBlock &MBB,
4269                 ArrayRef<MachineOperand> Cond,
4270                 unsigned TrueReg, unsigned FalseReg,
4271                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4272   // Not all subtargets have cmov instructions.
4273   if (!Subtarget.hasCMov())
4274     return false;
4275   if (Cond.size() != 1)
4276     return false;
4277   // We cannot do the composite conditions, at least not in SSA form.
4278   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4279     return false;
4280 
4281   // Check register classes.
4282   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4283   const TargetRegisterClass *RC =
4284     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4285   if (!RC)
4286     return false;
4287 
4288   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4289   if (X86::GR16RegClass.hasSubClassEq(RC) ||
4290       X86::GR32RegClass.hasSubClassEq(RC) ||
4291       X86::GR64RegClass.hasSubClassEq(RC)) {
4292     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4293     // Bridge. Probably Ivy Bridge as well.
4294     CondCycles = 2;
4295     TrueCycles = 2;
4296     FalseCycles = 2;
4297     return true;
4298   }
4299 
4300   // Can't do vectors.
4301   return false;
4302 }
4303 
4304 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4305                                 MachineBasicBlock::iterator I, DebugLoc DL,
4306                                 unsigned DstReg, ArrayRef<MachineOperand> Cond,
4307                                 unsigned TrueReg, unsigned FalseReg) const {
4308    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4309    assert(Cond.size() == 1 && "Invalid Cond array");
4310    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4311                                   MRI.getRegClass(DstReg)->getSize(),
4312                                   false/*HasMemoryOperand*/);
4313    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
4314 }
4315 
4316 /// Test if the given register is a physical h register.
4317 static bool isHReg(unsigned Reg) {
4318   return X86::GR8_ABCD_HRegClass.contains(Reg);
4319 }
4320 
4321 // Try and copy between VR128/VR64 and GR64 registers.
4322 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
4323                                         const X86Subtarget &Subtarget) {
4324 
4325   // SrcReg(VR128) -> DestReg(GR64)
4326   // SrcReg(VR64)  -> DestReg(GR64)
4327   // SrcReg(GR64)  -> DestReg(VR128)
4328   // SrcReg(GR64)  -> DestReg(VR64)
4329 
4330   bool HasAVX = Subtarget.hasAVX();
4331   bool HasAVX512 = Subtarget.hasAVX512();
4332   if (X86::GR64RegClass.contains(DestReg)) {
4333     if (X86::VR128XRegClass.contains(SrcReg))
4334       // Copy from a VR128 register to a GR64 register.
4335       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
4336                                                X86::MOVPQIto64rr);
4337     if (X86::VR64RegClass.contains(SrcReg))
4338       // Copy from a VR64 register to a GR64 register.
4339       return X86::MMX_MOVD64from64rr;
4340   } else if (X86::GR64RegClass.contains(SrcReg)) {
4341     // Copy from a GR64 register to a VR128 register.
4342     if (X86::VR128XRegClass.contains(DestReg))
4343       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
4344                                                X86::MOV64toPQIrr);
4345     // Copy from a GR64 register to a VR64 register.
4346     if (X86::VR64RegClass.contains(DestReg))
4347       return X86::MMX_MOVD64to64rr;
4348   }
4349 
4350   // SrcReg(FR32) -> DestReg(GR32)
4351   // SrcReg(GR32) -> DestReg(FR32)
4352 
4353   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
4354     // Copy from a FR32 register to a GR32 register.
4355     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
4356 
4357   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4358     // Copy from a GR32 register to a FR32 register.
4359     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
4360   return 0;
4361 }
4362 
4363 static bool isMaskRegClass(const TargetRegisterClass *RC) {
4364   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4365   return X86::VK16RegClass.hasSubClassEq(RC);
4366 }
4367 
4368 static bool MaskRegClassContains(unsigned Reg) {
4369   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4370   return X86::VK16RegClass.contains(Reg);
4371 }
4372 
4373 static bool GRRegClassContains(unsigned Reg) {
4374   return X86::GR64RegClass.contains(Reg) ||
4375          X86::GR32RegClass.contains(Reg) ||
4376          X86::GR16RegClass.contains(Reg) ||
4377          X86::GR8RegClass.contains(Reg);
4378 }
4379 static
4380 unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4381   if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
4382     DestReg = getX86SubSuperRegister(DestReg, 32);
4383     return X86::KMOVBrk;
4384   }
4385   if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
4386     SrcReg = getX86SubSuperRegister(SrcReg, 32);
4387     return X86::KMOVBkr;
4388   }
4389   return 0;
4390 }
4391 
4392 static
4393 unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4394   if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4395     return X86::KMOVQkk;
4396   if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4397     return X86::KMOVDrk;
4398   if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4399     return X86::KMOVQrk;
4400   if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4401     return X86::KMOVDkr;
4402   if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4403     return X86::KMOVQkr;
4404   return 0;
4405 }
4406 
4407 static
4408 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4409                                   const X86Subtarget &Subtarget)
4410 {
4411   if (Subtarget.hasDQI())
4412     if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4413       return Opc;
4414   if (Subtarget.hasBWI())
4415     if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4416       return Opc;
4417   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
4418       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
4419       X86::VR512RegClass.contains(DestReg, SrcReg)) {
4420      DestReg = get512BitSuperRegister(DestReg);
4421      SrcReg = get512BitSuperRegister(SrcReg);
4422      return X86::VMOVAPSZrr;
4423   }
4424   if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
4425     return X86::KMOVWkk;
4426   if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
4427     SrcReg = getX86SubSuperRegister(SrcReg, 32);
4428     return X86::KMOVWkr;
4429   }
4430   if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
4431     DestReg = getX86SubSuperRegister(DestReg, 32);
4432     return X86::KMOVWrk;
4433   }
4434   return 0;
4435 }
4436 
4437 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4438                                MachineBasicBlock::iterator MI, DebugLoc DL,
4439                                unsigned DestReg, unsigned SrcReg,
4440                                bool KillSrc) const {
4441   // First deal with the normal symmetric copies.
4442   bool HasAVX = Subtarget.hasAVX();
4443   bool HasAVX512 = Subtarget.hasAVX512();
4444   unsigned Opc = 0;
4445   if (X86::GR64RegClass.contains(DestReg, SrcReg))
4446     Opc = X86::MOV64rr;
4447   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4448     Opc = X86::MOV32rr;
4449   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4450     Opc = X86::MOV16rr;
4451   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4452     // Copying to or from a physical H register on x86-64 requires a NOREX
4453     // move.  Otherwise use a normal move.
4454     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
4455         Subtarget.is64Bit()) {
4456       Opc = X86::MOV8rr_NOREX;
4457       // Both operands must be encodable without an REX prefix.
4458       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4459              "8-bit H register can not be copied outside GR8_NOREX");
4460     } else
4461       Opc = X86::MOV8rr;
4462   }
4463   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4464     Opc = X86::MMX_MOVQ64rr;
4465   else if (HasAVX512)
4466     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
4467   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
4468     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4469   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4470     Opc = X86::VMOVAPSYrr;
4471   if (!Opc)
4472     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4473 
4474   if (Opc) {
4475     BuildMI(MBB, MI, DL, get(Opc), DestReg)
4476       .addReg(SrcReg, getKillRegState(KillSrc));
4477     return;
4478   }
4479 
4480   bool FromEFLAGS = SrcReg == X86::EFLAGS;
4481   bool ToEFLAGS = DestReg == X86::EFLAGS;
4482   int Reg = FromEFLAGS ? DestReg : SrcReg;
4483   bool is32 = X86::GR32RegClass.contains(Reg);
4484   bool is64 = X86::GR64RegClass.contains(Reg);
4485 
4486   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
4487     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4488     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4489     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4490     int Pop = is64 ? X86::POP64r : X86::POP32r;
4491     int PopF = is64 ? X86::POPF64 : X86::POPF32;
4492     int AX = is64 ? X86::RAX : X86::EAX;
4493 
4494     if (!Subtarget.hasLAHFSAHF()) {
4495       assert(Subtarget.is64Bit() &&
4496              "Not having LAHF/SAHF only happens on 64-bit.");
4497       // Moving EFLAGS to / from another register requires a push and a pop.
4498       // Notice that we have to adjust the stack if we don't want to clobber the
4499       // first frame index. See X86FrameLowering.cpp - usesTheStack.
4500       if (FromEFLAGS) {
4501         BuildMI(MBB, MI, DL, get(PushF));
4502         BuildMI(MBB, MI, DL, get(Pop), DestReg);
4503       }
4504       if (ToEFLAGS) {
4505         BuildMI(MBB, MI, DL, get(Push))
4506             .addReg(SrcReg, getKillRegState(KillSrc));
4507         BuildMI(MBB, MI, DL, get(PopF));
4508       }
4509       return;
4510     }
4511 
4512     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4513     // inefficient. Instead:
4514     //   - Save the overflow flag OF into AL using SETO, and restore it using a
4515     //     signed 8-bit addition of AL and INT8_MAX.
4516     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4517     //     using LAHF/SAHF.
4518     //   - When RAX/EAX is live and isn't the destination register, make sure it
4519     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4520     //     the flags.
4521     // This approach is ~2.25x faster than using PUSHF/POPF.
4522     //
4523     // This is still somewhat inefficient because we don't know which flags are
4524     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4525     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4526     //
4527     // PUSHF/POPF is also potentially incorrect because it affects other flags
4528     // such as TF/IF/DF, which LLVM doesn't model.
4529     //
4530     // Notice that we have to adjust the stack if we don't want to clobber the
4531     // first frame index.
4532     // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
4533 
4534     const TargetRegisterInfo *TRI = &getRegisterInfo();
4535     MachineBasicBlock::LivenessQueryResult LQR =
4536         MBB.computeRegisterLiveness(TRI, AX, MI);
4537     // We do not want to save and restore AX if we do not have to.
4538     // Moreover, if we do so whereas AX is dead, we would need to set
4539     // an undef flag on the use of AX, otherwise the verifier will
4540     // complain that we read an undef value.
4541     // We do not want to change the behavior of the machine verifier
4542     // as this is usually wrong to read an undef value.
4543     if (MachineBasicBlock::LQR_Unknown == LQR) {
4544       LivePhysRegs LPR(TRI);
4545       LPR.addLiveOuts(MBB);
4546       MachineBasicBlock::iterator I = MBB.end();
4547       while (I != MI) {
4548         --I;
4549         LPR.stepBackward(*I);
4550       }
4551       // AX contains the top most register in the aliasing hierarchy.
4552       // It may not be live, but one of its aliases may be.
4553       for (MCRegAliasIterator AI(AX, TRI, true);
4554            AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
4555         LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
4556                                 : MachineBasicBlock::LQR_Dead;
4557     }
4558     bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4559     if (!AXDead)
4560       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
4561     if (FromEFLAGS) {
4562       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4563       BuildMI(MBB, MI, DL, get(X86::LAHF));
4564       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
4565     }
4566     if (ToEFLAGS) {
4567       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4568       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4569           .addReg(X86::AL)
4570           .addImm(INT8_MAX);
4571       BuildMI(MBB, MI, DL, get(X86::SAHF));
4572     }
4573     if (!AXDead)
4574       BuildMI(MBB, MI, DL, get(Pop), AX);
4575     return;
4576   }
4577 
4578   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4579                << " to " << RI.getName(DestReg) << '\n');
4580   llvm_unreachable("Cannot emit physreg copy instruction");
4581 }
4582 
4583 static unsigned getLoadStoreMaskRegOpcode(const TargetRegisterClass *RC,
4584                                           bool load) {
4585   switch (RC->getSize()) {
4586   default:
4587     llvm_unreachable("Unknown spill size");
4588   case 2:
4589     return load ? X86::KMOVWkm : X86::KMOVWmk;
4590   case 4:
4591     return load ? X86::KMOVDkm : X86::KMOVDmk;
4592   case 8:
4593     return load ? X86::KMOVQkm : X86::KMOVQmk;
4594   }
4595 }
4596 
4597 static unsigned getLoadStoreRegOpcode(unsigned Reg,
4598                                       const TargetRegisterClass *RC,
4599                                       bool isStackAligned,
4600                                       const X86Subtarget &STI,
4601                                       bool load) {
4602   if (STI.hasAVX512()) {
4603     if (isMaskRegClass(RC))
4604       return getLoadStoreMaskRegOpcode(RC, load);
4605     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
4606       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
4607     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
4608       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
4609     if (X86::VR512RegClass.hasSubClassEq(RC))
4610       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4611   }
4612 
4613   bool HasAVX = STI.hasAVX();
4614   switch (RC->getSize()) {
4615   default:
4616     llvm_unreachable("Unknown spill size");
4617   case 1:
4618     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
4619     if (STI.is64Bit())
4620       // Copying to or from a physical H register on x86-64 requires a NOREX
4621       // move.  Otherwise use a normal move.
4622       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4623         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4624     return load ? X86::MOV8rm : X86::MOV8mr;
4625   case 2:
4626     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4627     return load ? X86::MOV16rm : X86::MOV16mr;
4628   case 4:
4629     if (X86::GR32RegClass.hasSubClassEq(RC))
4630       return load ? X86::MOV32rm : X86::MOV32mr;
4631     if (X86::FR32RegClass.hasSubClassEq(RC))
4632       return load ?
4633         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4634         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
4635     if (X86::RFP32RegClass.hasSubClassEq(RC))
4636       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4637     llvm_unreachable("Unknown 4-byte regclass");
4638   case 8:
4639     if (X86::GR64RegClass.hasSubClassEq(RC))
4640       return load ? X86::MOV64rm : X86::MOV64mr;
4641     if (X86::FR64RegClass.hasSubClassEq(RC))
4642       return load ?
4643         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4644         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
4645     if (X86::VR64RegClass.hasSubClassEq(RC))
4646       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4647     if (X86::RFP64RegClass.hasSubClassEq(RC))
4648       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4649     llvm_unreachable("Unknown 8-byte regclass");
4650   case 10:
4651     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
4652     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
4653   case 16: {
4654     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4655             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
4656     // If stack is realigned we can use aligned stores.
4657     if (X86::VR128RegClass.hasSubClassEq(RC)) {
4658       if (isStackAligned)
4659         return load ? (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm)
4660                     : (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4661       else
4662         return load ? (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm)
4663                     : (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4664     }
4665     assert(STI.hasVLX() && "Using extended register requires VLX");
4666     if (isStackAligned)
4667       return load ? X86::VMOVAPSZ128rm : X86::VMOVAPSZ128mr;
4668     else
4669       return load ? X86::VMOVUPSZ128rm : X86::VMOVUPSZ128mr;
4670   }
4671   case 32:
4672     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4673             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
4674     // If stack is realigned we can use aligned stores.
4675     if (X86::VR256RegClass.hasSubClassEq(RC)) {
4676       if (isStackAligned)
4677         return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4678       else
4679         return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
4680     }
4681     assert(STI.hasVLX() && "Using extended register requires VLX");
4682     if (isStackAligned)
4683       return load ? X86::VMOVAPSZ256rm : X86::VMOVAPSZ256mr;
4684     else
4685       return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr;
4686   case 64:
4687     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4688     assert(STI.hasVLX() && "Using 512-bit register requires AVX512");
4689     if (isStackAligned)
4690       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4691     else
4692       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4693   }
4694 }
4695 
4696 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
4697                                          int64_t &Offset,
4698                                          const TargetRegisterInfo *TRI) const {
4699   const MCInstrDesc &Desc = MemOp->getDesc();
4700   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
4701   if (MemRefBegin < 0)
4702     return false;
4703 
4704   MemRefBegin += X86II::getOperandBias(Desc);
4705 
4706   MachineOperand &BaseMO = MemOp->getOperand(MemRefBegin + X86::AddrBaseReg);
4707   if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4708     return false;
4709 
4710   BaseReg = BaseMO.getReg();
4711   if (MemOp->getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4712     return false;
4713 
4714   if (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
4715       X86::NoRegister)
4716     return false;
4717 
4718   const MachineOperand &DispMO = MemOp->getOperand(MemRefBegin + X86::AddrDisp);
4719 
4720   // Displacement can be symbolic
4721   if (!DispMO.isImm())
4722     return false;
4723 
4724   Offset = DispMO.getImm();
4725 
4726   return (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4727           X86::NoRegister);
4728 }
4729 
4730 static unsigned getStoreRegOpcode(unsigned SrcReg,
4731                                   const TargetRegisterClass *RC,
4732                                   bool isStackAligned,
4733                                   const X86Subtarget &STI) {
4734   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
4735 }
4736 
4737 
4738 static unsigned getLoadRegOpcode(unsigned DestReg,
4739                                  const TargetRegisterClass *RC,
4740                                  bool isStackAligned,
4741                                  const X86Subtarget &STI) {
4742   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
4743 }
4744 
4745 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4746                                        MachineBasicBlock::iterator MI,
4747                                        unsigned SrcReg, bool isKill, int FrameIdx,
4748                                        const TargetRegisterClass *RC,
4749                                        const TargetRegisterInfo *TRI) const {
4750   const MachineFunction &MF = *MBB.getParent();
4751   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4752          "Stack slot too small for store");
4753   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4754   bool isAligned =
4755       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4756       RI.canRealignStack(MF);
4757   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4758   DebugLoc DL = MBB.findDebugLoc(MI);
4759   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
4760     .addReg(SrcReg, getKillRegState(isKill));
4761 }
4762 
4763 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4764                                   bool isKill,
4765                                   SmallVectorImpl<MachineOperand> &Addr,
4766                                   const TargetRegisterClass *RC,
4767                                   MachineInstr::mmo_iterator MMOBegin,
4768                                   MachineInstr::mmo_iterator MMOEnd,
4769                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
4770   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4771   bool isAligned = MMOBegin != MMOEnd &&
4772                    (*MMOBegin)->getAlignment() >= Alignment;
4773   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4774   DebugLoc DL;
4775   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
4776   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4777     MIB.addOperand(Addr[i]);
4778   MIB.addReg(SrcReg, getKillRegState(isKill));
4779   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4780   NewMIs.push_back(MIB);
4781 }
4782 
4783 
4784 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4785                                         MachineBasicBlock::iterator MI,
4786                                         unsigned DestReg, int FrameIdx,
4787                                         const TargetRegisterClass *RC,
4788                                         const TargetRegisterInfo *TRI) const {
4789   const MachineFunction &MF = *MBB.getParent();
4790   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4791   bool isAligned =
4792       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4793       RI.canRealignStack(MF);
4794   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4795   DebugLoc DL = MBB.findDebugLoc(MI);
4796   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
4797 }
4798 
4799 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
4800                                  SmallVectorImpl<MachineOperand> &Addr,
4801                                  const TargetRegisterClass *RC,
4802                                  MachineInstr::mmo_iterator MMOBegin,
4803                                  MachineInstr::mmo_iterator MMOEnd,
4804                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
4805   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4806   bool isAligned = MMOBegin != MMOEnd &&
4807                    (*MMOBegin)->getAlignment() >= Alignment;
4808   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4809   DebugLoc DL;
4810   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
4811   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4812     MIB.addOperand(Addr[i]);
4813   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4814   NewMIs.push_back(MIB);
4815 }
4816 
4817 bool X86InstrInfo::
4818 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
4819                int &CmpMask, int &CmpValue) const {
4820   switch (MI->getOpcode()) {
4821   default: break;
4822   case X86::CMP64ri32:
4823   case X86::CMP64ri8:
4824   case X86::CMP32ri:
4825   case X86::CMP32ri8:
4826   case X86::CMP16ri:
4827   case X86::CMP16ri8:
4828   case X86::CMP8ri:
4829     SrcReg = MI->getOperand(0).getReg();
4830     SrcReg2 = 0;
4831     CmpMask = ~0;
4832     CmpValue = MI->getOperand(1).getImm();
4833     return true;
4834   // A SUB can be used to perform comparison.
4835   case X86::SUB64rm:
4836   case X86::SUB32rm:
4837   case X86::SUB16rm:
4838   case X86::SUB8rm:
4839     SrcReg = MI->getOperand(1).getReg();
4840     SrcReg2 = 0;
4841     CmpMask = ~0;
4842     CmpValue = 0;
4843     return true;
4844   case X86::SUB64rr:
4845   case X86::SUB32rr:
4846   case X86::SUB16rr:
4847   case X86::SUB8rr:
4848     SrcReg = MI->getOperand(1).getReg();
4849     SrcReg2 = MI->getOperand(2).getReg();
4850     CmpMask = ~0;
4851     CmpValue = 0;
4852     return true;
4853   case X86::SUB64ri32:
4854   case X86::SUB64ri8:
4855   case X86::SUB32ri:
4856   case X86::SUB32ri8:
4857   case X86::SUB16ri:
4858   case X86::SUB16ri8:
4859   case X86::SUB8ri:
4860     SrcReg = MI->getOperand(1).getReg();
4861     SrcReg2 = 0;
4862     CmpMask = ~0;
4863     CmpValue = MI->getOperand(2).getImm();
4864     return true;
4865   case X86::CMP64rr:
4866   case X86::CMP32rr:
4867   case X86::CMP16rr:
4868   case X86::CMP8rr:
4869     SrcReg = MI->getOperand(0).getReg();
4870     SrcReg2 = MI->getOperand(1).getReg();
4871     CmpMask = ~0;
4872     CmpValue = 0;
4873     return true;
4874   case X86::TEST8rr:
4875   case X86::TEST16rr:
4876   case X86::TEST32rr:
4877   case X86::TEST64rr:
4878     SrcReg = MI->getOperand(0).getReg();
4879     if (MI->getOperand(1).getReg() != SrcReg) return false;
4880     // Compare against zero.
4881     SrcReg2 = 0;
4882     CmpMask = ~0;
4883     CmpValue = 0;
4884     return true;
4885   }
4886   return false;
4887 }
4888 
4889 /// Check whether the first instruction, whose only
4890 /// purpose is to update flags, can be made redundant.
4891 /// CMPrr can be made redundant by SUBrr if the operands are the same.
4892 /// This function can be extended later on.
4893 /// SrcReg, SrcRegs: register operands for FlagI.
4894 /// ImmValue: immediate for FlagI if it takes an immediate.
4895 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4896                                         unsigned SrcReg2, int ImmValue,
4897                                         MachineInstr *OI) {
4898   if (((FlagI->getOpcode() == X86::CMP64rr &&
4899         OI->getOpcode() == X86::SUB64rr) ||
4900        (FlagI->getOpcode() == X86::CMP32rr &&
4901         OI->getOpcode() == X86::SUB32rr)||
4902        (FlagI->getOpcode() == X86::CMP16rr &&
4903         OI->getOpcode() == X86::SUB16rr)||
4904        (FlagI->getOpcode() == X86::CMP8rr &&
4905         OI->getOpcode() == X86::SUB8rr)) &&
4906       ((OI->getOperand(1).getReg() == SrcReg &&
4907         OI->getOperand(2).getReg() == SrcReg2) ||
4908        (OI->getOperand(1).getReg() == SrcReg2 &&
4909         OI->getOperand(2).getReg() == SrcReg)))
4910     return true;
4911 
4912   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4913         OI->getOpcode() == X86::SUB64ri32) ||
4914        (FlagI->getOpcode() == X86::CMP64ri8 &&
4915         OI->getOpcode() == X86::SUB64ri8) ||
4916        (FlagI->getOpcode() == X86::CMP32ri &&
4917         OI->getOpcode() == X86::SUB32ri) ||
4918        (FlagI->getOpcode() == X86::CMP32ri8 &&
4919         OI->getOpcode() == X86::SUB32ri8) ||
4920        (FlagI->getOpcode() == X86::CMP16ri &&
4921         OI->getOpcode() == X86::SUB16ri) ||
4922        (FlagI->getOpcode() == X86::CMP16ri8 &&
4923         OI->getOpcode() == X86::SUB16ri8) ||
4924        (FlagI->getOpcode() == X86::CMP8ri &&
4925         OI->getOpcode() == X86::SUB8ri)) &&
4926       OI->getOperand(1).getReg() == SrcReg &&
4927       OI->getOperand(2).getImm() == ImmValue)
4928     return true;
4929   return false;
4930 }
4931 
4932 /// Check whether the definition can be converted
4933 /// to remove a comparison against zero.
4934 inline static bool isDefConvertible(MachineInstr *MI) {
4935   switch (MI->getOpcode()) {
4936   default: return false;
4937 
4938   // The shift instructions only modify ZF if their shift count is non-zero.
4939   // N.B.: The processor truncates the shift count depending on the encoding.
4940   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
4941   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
4942      return getTruncatedShiftCount(MI, 2) != 0;
4943 
4944   // Some left shift instructions can be turned into LEA instructions but only
4945   // if their flags aren't used. Avoid transforming such instructions.
4946   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
4947     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4948     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4949     return ShAmt != 0;
4950   }
4951 
4952   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4953   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4954      return getTruncatedShiftCount(MI, 3) != 0;
4955 
4956   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4957   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
4958   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
4959   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
4960   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
4961   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
4962   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4963   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
4964   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
4965   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
4966   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
4967   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
4968   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4969   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
4970   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
4971   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
4972   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
4973   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4974   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
4975   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
4976   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
4977   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
4978   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
4979   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
4980   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
4981   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
4982   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
4983   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4984   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
4985   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
4986   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
4987   case X86::ADC32ri:   case X86::ADC32ri8:
4988   case X86::ADC32rr:   case X86::ADC64ri32:
4989   case X86::ADC64ri8:  case X86::ADC64rr:
4990   case X86::SBB32ri:   case X86::SBB32ri8:
4991   case X86::SBB32rr:   case X86::SBB64ri32:
4992   case X86::SBB64ri8:  case X86::SBB64rr:
4993   case X86::ANDN32rr:  case X86::ANDN32rm:
4994   case X86::ANDN64rr:  case X86::ANDN64rm:
4995   case X86::BEXTR32rr: case X86::BEXTR64rr:
4996   case X86::BEXTR32rm: case X86::BEXTR64rm:
4997   case X86::BLSI32rr:  case X86::BLSI32rm:
4998   case X86::BLSI64rr:  case X86::BLSI64rm:
4999   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
5000   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
5001   case X86::BLSR32rr:  case X86::BLSR32rm:
5002   case X86::BLSR64rr:  case X86::BLSR64rm:
5003   case X86::BZHI32rr:  case X86::BZHI32rm:
5004   case X86::BZHI64rr:  case X86::BZHI64rm:
5005   case X86::LZCNT16rr: case X86::LZCNT16rm:
5006   case X86::LZCNT32rr: case X86::LZCNT32rm:
5007   case X86::LZCNT64rr: case X86::LZCNT64rm:
5008   case X86::POPCNT16rr:case X86::POPCNT16rm:
5009   case X86::POPCNT32rr:case X86::POPCNT32rm:
5010   case X86::POPCNT64rr:case X86::POPCNT64rm:
5011   case X86::TZCNT16rr: case X86::TZCNT16rm:
5012   case X86::TZCNT32rr: case X86::TZCNT32rm:
5013   case X86::TZCNT64rr: case X86::TZCNT64rm:
5014     return true;
5015   }
5016 }
5017 
5018 /// Check whether the use can be converted to remove a comparison against zero.
5019 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
5020   switch (MI->getOpcode()) {
5021   default: return X86::COND_INVALID;
5022   case X86::LZCNT16rr: case X86::LZCNT16rm:
5023   case X86::LZCNT32rr: case X86::LZCNT32rm:
5024   case X86::LZCNT64rr: case X86::LZCNT64rm:
5025     return X86::COND_B;
5026   case X86::POPCNT16rr:case X86::POPCNT16rm:
5027   case X86::POPCNT32rr:case X86::POPCNT32rm:
5028   case X86::POPCNT64rr:case X86::POPCNT64rm:
5029     return X86::COND_E;
5030   case X86::TZCNT16rr: case X86::TZCNT16rm:
5031   case X86::TZCNT32rr: case X86::TZCNT32rm:
5032   case X86::TZCNT64rr: case X86::TZCNT64rm:
5033     return X86::COND_B;
5034   }
5035 }
5036 
5037 /// Check if there exists an earlier instruction that
5038 /// operates on the same source operands and sets flags in the same way as
5039 /// Compare; remove Compare if possible.
5040 bool X86InstrInfo::
5041 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
5042                      int CmpMask, int CmpValue,
5043                      const MachineRegisterInfo *MRI) const {
5044   // Check whether we can replace SUB with CMP.
5045   unsigned NewOpcode = 0;
5046   switch (CmpInstr->getOpcode()) {
5047   default: break;
5048   case X86::SUB64ri32:
5049   case X86::SUB64ri8:
5050   case X86::SUB32ri:
5051   case X86::SUB32ri8:
5052   case X86::SUB16ri:
5053   case X86::SUB16ri8:
5054   case X86::SUB8ri:
5055   case X86::SUB64rm:
5056   case X86::SUB32rm:
5057   case X86::SUB16rm:
5058   case X86::SUB8rm:
5059   case X86::SUB64rr:
5060   case X86::SUB32rr:
5061   case X86::SUB16rr:
5062   case X86::SUB8rr: {
5063     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
5064       return false;
5065     // There is no use of the destination register, we can replace SUB with CMP.
5066     switch (CmpInstr->getOpcode()) {
5067     default: llvm_unreachable("Unreachable!");
5068     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
5069     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
5070     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
5071     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
5072     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
5073     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
5074     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
5075     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
5076     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5077     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
5078     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
5079     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
5080     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
5081     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
5082     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
5083     }
5084     CmpInstr->setDesc(get(NewOpcode));
5085     CmpInstr->RemoveOperand(0);
5086     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5087     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5088         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5089       return false;
5090   }
5091   }
5092 
5093   // Get the unique definition of SrcReg.
5094   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5095   if (!MI) return false;
5096 
5097   // CmpInstr is the first instruction of the BB.
5098   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5099 
5100   // If we are comparing against zero, check whether we can use MI to update
5101   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5102   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
5103   if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
5104     return false;
5105 
5106   // If we have a use of the source register between the def and our compare
5107   // instruction we can eliminate the compare iff the use sets EFLAGS in the
5108   // right way.
5109   bool ShouldUpdateCC = false;
5110   X86::CondCode NewCC = X86::COND_INVALID;
5111   if (IsCmpZero && !isDefConvertible(MI)) {
5112     // Scan forward from the use until we hit the use we're looking for or the
5113     // compare instruction.
5114     for (MachineBasicBlock::iterator J = MI;; ++J) {
5115       // Do we have a convertible instruction?
5116       NewCC = isUseDefConvertible(J);
5117       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5118           J->getOperand(1).getReg() == SrcReg) {
5119         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5120         ShouldUpdateCC = true; // Update CC later on.
5121         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5122         // with the new def.
5123         MI = Def = J;
5124         break;
5125       }
5126 
5127       if (J == I)
5128         return false;
5129     }
5130   }
5131 
5132   // We are searching for an earlier instruction that can make CmpInstr
5133   // redundant and that instruction will be saved in Sub.
5134   MachineInstr *Sub = nullptr;
5135   const TargetRegisterInfo *TRI = &getRegisterInfo();
5136 
5137   // We iterate backward, starting from the instruction before CmpInstr and
5138   // stop when reaching the definition of a source register or done with the BB.
5139   // RI points to the instruction before CmpInstr.
5140   // If the definition is in this basic block, RE points to the definition;
5141   // otherwise, RE is the rend of the basic block.
5142   MachineBasicBlock::reverse_iterator
5143       RI = MachineBasicBlock::reverse_iterator(I),
5144       RE = CmpInstr->getParent() == MI->getParent() ?
5145            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
5146            CmpInstr->getParent()->rend();
5147   MachineInstr *Movr0Inst = nullptr;
5148   for (; RI != RE; ++RI) {
5149     MachineInstr *Instr = &*RI;
5150     // Check whether CmpInstr can be made redundant by the current instruction.
5151     if (!IsCmpZero &&
5152         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
5153       Sub = Instr;
5154       break;
5155     }
5156 
5157     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
5158         Instr->readsRegister(X86::EFLAGS, TRI)) {
5159       // This instruction modifies or uses EFLAGS.
5160 
5161       // MOV32r0 etc. are implemented with xor which clobbers condition code.
5162       // They are safe to move up, if the definition to EFLAGS is dead and
5163       // earlier instructions do not read or write EFLAGS.
5164       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
5165           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
5166         Movr0Inst = Instr;
5167         continue;
5168       }
5169 
5170       // We can't remove CmpInstr.
5171       return false;
5172     }
5173   }
5174 
5175   // Return false if no candidates exist.
5176   if (!IsCmpZero && !Sub)
5177     return false;
5178 
5179   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5180                     Sub->getOperand(2).getReg() == SrcReg);
5181 
5182   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
5183   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5184   // If we are done with the basic block, we need to check whether EFLAGS is
5185   // live-out.
5186   bool IsSafe = false;
5187   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
5188   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
5189   for (++I; I != E; ++I) {
5190     const MachineInstr &Instr = *I;
5191     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5192     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5193     // We should check the usage if this instruction uses and updates EFLAGS.
5194     if (!UseEFLAGS && ModifyEFLAGS) {
5195       // It is safe to remove CmpInstr if EFLAGS is updated again.
5196       IsSafe = true;
5197       break;
5198     }
5199     if (!UseEFLAGS && !ModifyEFLAGS)
5200       continue;
5201 
5202     // EFLAGS is used by this instruction.
5203     X86::CondCode OldCC = X86::COND_INVALID;
5204     bool OpcIsSET = false;
5205     if (IsCmpZero || IsSwapped) {
5206       // We decode the condition code from opcode.
5207       if (Instr.isBranch())
5208         OldCC = getCondFromBranchOpc(Instr.getOpcode());
5209       else {
5210         OldCC = getCondFromSETOpc(Instr.getOpcode());
5211         if (OldCC != X86::COND_INVALID)
5212           OpcIsSET = true;
5213         else
5214           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
5215       }
5216       if (OldCC == X86::COND_INVALID) return false;
5217     }
5218     if (IsCmpZero) {
5219       switch (OldCC) {
5220       default: break;
5221       case X86::COND_A: case X86::COND_AE:
5222       case X86::COND_B: case X86::COND_BE:
5223       case X86::COND_G: case X86::COND_GE:
5224       case X86::COND_L: case X86::COND_LE:
5225       case X86::COND_O: case X86::COND_NO:
5226         // CF and OF are used, we can't perform this optimization.
5227         return false;
5228       }
5229 
5230       // If we're updating the condition code check if we have to reverse the
5231       // condition.
5232       if (ShouldUpdateCC)
5233         switch (OldCC) {
5234         default:
5235           return false;
5236         case X86::COND_E:
5237           break;
5238         case X86::COND_NE:
5239           NewCC = GetOppositeBranchCondition(NewCC);
5240           break;
5241         }
5242     } else if (IsSwapped) {
5243       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5244       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5245       // We swap the condition code and synthesize the new opcode.
5246       NewCC = getSwappedCondition(OldCC);
5247       if (NewCC == X86::COND_INVALID) return false;
5248     }
5249 
5250     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
5251       // Synthesize the new opcode.
5252       bool HasMemoryOperand = Instr.hasOneMemOperand();
5253       unsigned NewOpc;
5254       if (Instr.isBranch())
5255         NewOpc = GetCondBranchFromCond(NewCC);
5256       else if(OpcIsSET)
5257         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5258       else {
5259         unsigned DstReg = Instr.getOperand(0).getReg();
5260         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5261                                  HasMemoryOperand);
5262       }
5263 
5264       // Push the MachineInstr to OpsToUpdate.
5265       // If it is safe to remove CmpInstr, the condition code of these
5266       // instructions will be modified.
5267       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5268     }
5269     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5270       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
5271       IsSafe = true;
5272       break;
5273     }
5274   }
5275 
5276   // If EFLAGS is not killed nor re-defined, we should check whether it is
5277   // live-out. If it is live-out, do not optimize.
5278   if ((IsCmpZero || IsSwapped) && !IsSafe) {
5279     MachineBasicBlock *MBB = CmpInstr->getParent();
5280     for (MachineBasicBlock *Successor : MBB->successors())
5281       if (Successor->isLiveIn(X86::EFLAGS))
5282         return false;
5283   }
5284 
5285   // The instruction to be updated is either Sub or MI.
5286   Sub = IsCmpZero ? MI : Sub;
5287   // Move Movr0Inst to the appropriate place before Sub.
5288   if (Movr0Inst) {
5289     // Look backwards until we find a def that doesn't use the current EFLAGS.
5290     Def = Sub;
5291     MachineBasicBlock::reverse_iterator
5292       InsertI = MachineBasicBlock::reverse_iterator(++Def),
5293                 InsertE = Sub->getParent()->rend();
5294     for (; InsertI != InsertE; ++InsertI) {
5295       MachineInstr *Instr = &*InsertI;
5296       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5297           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5298         Sub->getParent()->remove(Movr0Inst);
5299         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5300                                    Movr0Inst);
5301         break;
5302       }
5303     }
5304     if (InsertI == InsertE)
5305       return false;
5306   }
5307 
5308   // Make sure Sub instruction defines EFLAGS and mark the def live.
5309   unsigned i = 0, e = Sub->getNumOperands();
5310   for (; i != e; ++i) {
5311     MachineOperand &MO = Sub->getOperand(i);
5312     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5313       MO.setIsDead(false);
5314       break;
5315     }
5316   }
5317   assert(i != e && "Unable to locate a def EFLAGS operand");
5318 
5319   CmpInstr->eraseFromParent();
5320 
5321   // Modify the condition code of instructions in OpsToUpdate.
5322   for (auto &Op : OpsToUpdate)
5323     Op.first->setDesc(get(Op.second));
5324   return true;
5325 }
5326 
5327 /// Try to remove the load by folding it to a register
5328 /// operand at the use. We fold the load instructions if load defines a virtual
5329 /// register, the virtual register is used once in the same BB, and the
5330 /// instructions in-between do not load or store, and have no side effects.
5331 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
5332                                               const MachineRegisterInfo *MRI,
5333                                               unsigned &FoldAsLoadDefReg,
5334                                               MachineInstr *&DefMI) const {
5335   if (FoldAsLoadDefReg == 0)
5336     return nullptr;
5337   // To be conservative, if there exists another load, clear the load candidate.
5338   if (MI->mayLoad()) {
5339     FoldAsLoadDefReg = 0;
5340     return nullptr;
5341   }
5342 
5343   // Check whether we can move DefMI here.
5344   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5345   assert(DefMI);
5346   bool SawStore = false;
5347   if (!DefMI->isSafeToMove(nullptr, SawStore))
5348     return nullptr;
5349 
5350   // Collect information about virtual register operands of MI.
5351   unsigned SrcOperandId = 0;
5352   bool FoundSrcOperand = false;
5353   for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
5354     MachineOperand &MO = MI->getOperand(i);
5355     if (!MO.isReg())
5356       continue;
5357     unsigned Reg = MO.getReg();
5358     if (Reg != FoldAsLoadDefReg)
5359       continue;
5360     // Do not fold if we have a subreg use or a def or multiple uses.
5361     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
5362       return nullptr;
5363 
5364     SrcOperandId = i;
5365     FoundSrcOperand = true;
5366   }
5367   if (!FoundSrcOperand)
5368     return nullptr;
5369 
5370   // Check whether we can fold the def into SrcOperandId.
5371   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI)) {
5372     FoldAsLoadDefReg = 0;
5373     return FoldMI;
5374   }
5375 
5376   return nullptr;
5377 }
5378 
5379 /// Expand a single-def pseudo instruction to a two-addr
5380 /// instruction with two undef reads of the register being defined.
5381 /// This is used for mapping:
5382 ///   %xmm4 = V_SET0
5383 /// to:
5384 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5385 ///
5386 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5387                              const MCInstrDesc &Desc) {
5388   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5389   unsigned Reg = MIB->getOperand(0).getReg();
5390   MIB->setDesc(Desc);
5391 
5392   // MachineInstr::addOperand() will insert explicit operands before any
5393   // implicit operands.
5394   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5395   // But we don't trust that.
5396   assert(MIB->getOperand(1).getReg() == Reg &&
5397          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
5398   return true;
5399 }
5400 
5401 /// Expand a single-def pseudo instruction to a two-addr
5402 /// instruction with two %k0 reads.
5403 /// This is used for mapping:
5404 ///   %k4 = K_SET1
5405 /// to:
5406 ///   %k4 = KXNORrr %k0, %k0
5407 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5408                             const MCInstrDesc &Desc, unsigned Reg) {
5409   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5410   MIB->setDesc(Desc);
5411   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5412   return true;
5413 }
5414 
5415 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5416                           bool MinusOne) {
5417   MachineBasicBlock &MBB = *MIB->getParent();
5418   DebugLoc DL = MIB->getDebugLoc();
5419   unsigned Reg = MIB->getOperand(0).getReg();
5420 
5421   // Insert the XOR.
5422   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5423       .addReg(Reg, RegState::Undef)
5424       .addReg(Reg, RegState::Undef);
5425 
5426   // Turn the pseudo into an INC or DEC.
5427   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5428   MIB.addReg(Reg);
5429 
5430   return true;
5431 }
5432 
5433 bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5434   MachineBasicBlock &MBB = *MIB->getParent();
5435   DebugLoc DL = MIB->getDebugLoc();
5436   int64_t Imm = MIB->getOperand(1).getImm();
5437   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5438   MachineBasicBlock::iterator I = MIB.getInstr();
5439 
5440   int StackAdjustment;
5441 
5442   if (Subtarget.is64Bit()) {
5443     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5444            MIB->getOpcode() == X86::MOV32ImmSExti8);
5445 
5446     // Can't use push/pop lowering if the function might write to the red zone.
5447     X86MachineFunctionInfo *X86FI =
5448         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5449     if (X86FI->getUsesRedZone()) {
5450       MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5451                                                                : X86::MOV64ri));
5452       return true;
5453     }
5454 
5455     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5456     // widen the register if necessary.
5457     StackAdjustment = 8;
5458     BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5459     MIB->setDesc(get(X86::POP64r));
5460     MIB->getOperand(0)
5461         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5462   } else {
5463     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5464     StackAdjustment = 4;
5465     BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5466     MIB->setDesc(get(X86::POP32r));
5467   }
5468 
5469   // Build CFI if necessary.
5470   MachineFunction &MF = *MBB.getParent();
5471   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5472   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5473   bool NeedsDwarfCFI =
5474       !IsWin64Prologue &&
5475       (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5476   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5477   if (EmitCFI) {
5478     TFL->BuildCFI(MBB, I, DL,
5479         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5480     TFL->BuildCFI(MBB, std::next(I), DL,
5481         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5482   }
5483 
5484   return true;
5485 }
5486 
5487 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5488 // code sequence is needed for other targets.
5489 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5490                                  const TargetInstrInfo &TII) {
5491   MachineBasicBlock &MBB = *MIB->getParent();
5492   DebugLoc DL = MIB->getDebugLoc();
5493   unsigned Reg = MIB->getOperand(0).getReg();
5494   const GlobalValue *GV =
5495       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
5496   unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
5497   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
5498       MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8);
5499   MachineBasicBlock::iterator I = MIB.getInstr();
5500 
5501   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5502       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5503       .addMemOperand(MMO);
5504   MIB->setDebugLoc(DL);
5505   MIB->setDesc(TII.get(X86::MOV64rm));
5506   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5507 }
5508 
5509 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
5510   bool HasAVX = Subtarget.hasAVX();
5511   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
5512   switch (MI->getOpcode()) {
5513   case X86::MOV32r0:
5514     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
5515   case X86::MOV32r1:
5516     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5517   case X86::MOV32r_1:
5518     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
5519   case X86::MOV32ImmSExti8:
5520   case X86::MOV64ImmSExti8:
5521     return ExpandMOVImmSExti8(MIB);
5522   case X86::SETB_C8r:
5523     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
5524   case X86::SETB_C16r:
5525     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
5526   case X86::SETB_C32r:
5527     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
5528   case X86::SETB_C64r:
5529     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
5530   case X86::V_SET0:
5531   case X86::FsFLD0SS:
5532   case X86::FsFLD0SD:
5533     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
5534   case X86::AVX_SET0:
5535     assert(HasAVX && "AVX not supported");
5536     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
5537   case X86::AVX512_128_SET0:
5538     return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
5539   case X86::AVX512_256_SET0:
5540     return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
5541   case X86::AVX512_512_SET0:
5542     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
5543   case X86::V_SETALLONES:
5544     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
5545   case X86::AVX2_SETALLONES:
5546     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
5547   case X86::TEST8ri_NOREX:
5548     MI->setDesc(get(X86::TEST8ri));
5549     return true;
5550   case X86::MOV32ri64:
5551     MI->setDesc(get(X86::MOV32ri));
5552     return true;
5553 
5554   // KNL does not recognize dependency-breaking idioms for mask registers,
5555   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5556   // Using %k0 as the undef input register is a performance heuristic based
5557   // on the assumption that %k0 is used less frequently than the other mask
5558   // registers, since it is not usable as a write mask.
5559   // FIXME: A more advanced approach would be to choose the best input mask
5560   // register based on context.
5561   case X86::KSET0B:
5562   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5563   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5564   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
5565   case X86::KSET1B:
5566   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5567   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5568   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
5569   case TargetOpcode::LOAD_STACK_GUARD:
5570     expandLoadStackGuard(MIB, *this);
5571     return true;
5572   }
5573   return false;
5574 }
5575 
5576 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5577                         int PtrOffset = 0) {
5578   unsigned NumAddrOps = MOs.size();
5579 
5580   if (NumAddrOps < 4) {
5581     // FrameIndex only - add an immediate offset (whether its zero or not).
5582     for (unsigned i = 0; i != NumAddrOps; ++i)
5583       MIB.addOperand(MOs[i]);
5584     addOffset(MIB, PtrOffset);
5585   } else {
5586     // General Memory Addressing - we need to add any offset to an existing
5587     // offset.
5588     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5589     for (unsigned i = 0; i != NumAddrOps; ++i) {
5590       const MachineOperand &MO = MOs[i];
5591       if (i == 3 && PtrOffset != 0) {
5592         MIB.addDisp(MO, PtrOffset);
5593       } else {
5594         MIB.addOperand(MO);
5595       }
5596     }
5597   }
5598 }
5599 
5600 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5601                                      ArrayRef<MachineOperand> MOs,
5602                                      MachineBasicBlock::iterator InsertPt,
5603                                      MachineInstr *MI,
5604                                      const TargetInstrInfo &TII) {
5605   // Create the base instruction with the memory operand as the first part.
5606   // Omit the implicit operands, something BuildMI can't do.
5607   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5608                                               MI->getDebugLoc(), true);
5609   MachineInstrBuilder MIB(MF, NewMI);
5610   addOperands(MIB, MOs);
5611 
5612   // Loop over the rest of the ri operands, converting them over.
5613   unsigned NumOps = MI->getDesc().getNumOperands()-2;
5614   for (unsigned i = 0; i != NumOps; ++i) {
5615     MachineOperand &MO = MI->getOperand(i+2);
5616     MIB.addOperand(MO);
5617   }
5618   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
5619     MachineOperand &MO = MI->getOperand(i);
5620     MIB.addOperand(MO);
5621   }
5622 
5623   MachineBasicBlock *MBB = InsertPt->getParent();
5624   MBB->insert(InsertPt, NewMI);
5625 
5626   return MIB;
5627 }
5628 
5629 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5630                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5631                               MachineBasicBlock::iterator InsertPt,
5632                               MachineInstr *MI, const TargetInstrInfo &TII,
5633                               int PtrOffset = 0) {
5634   // Omit the implicit operands, something BuildMI can't do.
5635   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5636                                               MI->getDebugLoc(), true);
5637   MachineInstrBuilder MIB(MF, NewMI);
5638 
5639   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5640     MachineOperand &MO = MI->getOperand(i);
5641     if (i == OpNo) {
5642       assert(MO.isReg() && "Expected to fold into reg operand!");
5643       addOperands(MIB, MOs, PtrOffset);
5644     } else {
5645       MIB.addOperand(MO);
5646     }
5647   }
5648 
5649   MachineBasicBlock *MBB = InsertPt->getParent();
5650   MBB->insert(InsertPt, NewMI);
5651 
5652   return MIB;
5653 }
5654 
5655 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5656                                 ArrayRef<MachineOperand> MOs,
5657                                 MachineBasicBlock::iterator InsertPt,
5658                                 MachineInstr *MI) {
5659   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5660                                     MI->getDebugLoc(), TII.get(Opcode));
5661   addOperands(MIB, MOs);
5662   return MIB.addImm(0);
5663 }
5664 
5665 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5666     MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5667     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5668     unsigned Size, unsigned Align) const {
5669   switch (MI->getOpcode()) {
5670   case X86::INSERTPSrr:
5671   case X86::VINSERTPSrr:
5672     // Attempt to convert the load of inserted vector into a fold load
5673     // of a single float.
5674     if (OpNum == 2) {
5675       unsigned Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
5676       unsigned ZMask = Imm & 15;
5677       unsigned DstIdx = (Imm >> 4) & 3;
5678       unsigned SrcIdx = (Imm >> 6) & 3;
5679 
5680       unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5681       if (Size <= RCSize && 4 <= Align) {
5682         int PtrOffset = SrcIdx * 4;
5683         unsigned NewImm = (DstIdx << 4) | ZMask;
5684         unsigned NewOpCode =
5685             (MI->getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
5686                                                  : X86::INSERTPSrm);
5687         MachineInstr *NewMI =
5688             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5689         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5690         return NewMI;
5691       }
5692     }
5693     break;
5694   case X86::MOVHLPSrr:
5695   case X86::VMOVHLPSrr:
5696     // Move the upper 64-bits of the second operand to the lower 64-bits.
5697     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5698     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5699     if (OpNum == 2) {
5700       unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5701       if (Size <= RCSize && 8 <= Align) {
5702         unsigned NewOpCode =
5703             (MI->getOpcode() == X86::VMOVHLPSrr ? X86::VMOVLPSrm
5704                                                 : X86::MOVLPSrm);
5705         MachineInstr *NewMI =
5706             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5707         return NewMI;
5708       }
5709     }
5710     break;
5711   };
5712 
5713   return nullptr;
5714 }
5715 
5716 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5717     MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5718     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5719     unsigned Size, unsigned Align, bool AllowCommute) const {
5720   const DenseMap<unsigned,
5721                  std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
5722   bool isCallRegIndirect = Subtarget.callRegIndirect();
5723   bool isTwoAddrFold = false;
5724 
5725   // For CPUs that favor the register form of a call or push,
5726   // do not fold loads into calls or pushes, unless optimizing for size
5727   // aggressively.
5728   if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
5729       (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r ||
5730        MI->getOpcode() == X86::PUSH16r || MI->getOpcode() == X86::PUSH32r ||
5731        MI->getOpcode() == X86::PUSH64r))
5732     return nullptr;
5733 
5734   unsigned NumOps = MI->getDesc().getNumOperands();
5735   bool isTwoAddr = NumOps > 1 &&
5736     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5737 
5738   // FIXME: AsmPrinter doesn't know how to handle
5739   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5740   if (MI->getOpcode() == X86::ADD32ri &&
5741       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5742     return nullptr;
5743 
5744   MachineInstr *NewMI = nullptr;
5745 
5746   // Attempt to fold any custom cases we have.
5747   if (MachineInstr *CustomMI =
5748           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
5749     return CustomMI;
5750 
5751   // Folding a memory location into the two-address part of a two-address
5752   // instruction is different than folding it other places.  It requires
5753   // replacing the *two* registers with the memory location.
5754   if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
5755       MI->getOperand(0).isReg() &&
5756       MI->getOperand(1).isReg() &&
5757       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
5758     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5759     isTwoAddrFold = true;
5760   } else if (OpNum == 0) {
5761     if (MI->getOpcode() == X86::MOV32r0) {
5762       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5763       if (NewMI)
5764         return NewMI;
5765     }
5766 
5767     OpcodeTablePtr = &RegOp2MemOpTable0;
5768   } else if (OpNum == 1) {
5769     OpcodeTablePtr = &RegOp2MemOpTable1;
5770   } else if (OpNum == 2) {
5771     OpcodeTablePtr = &RegOp2MemOpTable2;
5772   } else if (OpNum == 3) {
5773     OpcodeTablePtr = &RegOp2MemOpTable3;
5774   } else if (OpNum == 4) {
5775     OpcodeTablePtr = &RegOp2MemOpTable4;
5776   }
5777 
5778   // If table selected...
5779   if (OpcodeTablePtr) {
5780     // Find the Opcode to fuse
5781     auto I = OpcodeTablePtr->find(MI->getOpcode());
5782     if (I != OpcodeTablePtr->end()) {
5783       unsigned Opcode = I->second.first;
5784       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
5785       if (Align < MinAlign)
5786         return nullptr;
5787       bool NarrowToMOV32rm = false;
5788       if (Size) {
5789         unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5790         if (Size < RCSize) {
5791           // Check if it's safe to fold the load. If the size of the object is
5792           // narrower than the load width, then it's not.
5793           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5794             return nullptr;
5795           // If this is a 64-bit load, but the spill slot is 32, then we can do
5796           // a 32-bit load which is implicitly zero-extended. This likely is
5797           // due to live interval analysis remat'ing a load from stack slot.
5798           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
5799             return nullptr;
5800           Opcode = X86::MOV32rm;
5801           NarrowToMOV32rm = true;
5802         }
5803       }
5804 
5805       if (isTwoAddrFold)
5806         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5807       else
5808         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5809 
5810       if (NarrowToMOV32rm) {
5811         // If this is the special case where we use a MOV32rm to load a 32-bit
5812         // value and zero-extend the top bits. Change the destination register
5813         // to a 32-bit one.
5814         unsigned DstReg = NewMI->getOperand(0).getReg();
5815         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
5816           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5817         else
5818           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5819       }
5820       return NewMI;
5821     }
5822   }
5823 
5824   // If the instruction and target operand are commutable, commute the
5825   // instruction and try again.
5826   if (AllowCommute) {
5827     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5828     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5829       bool HasDef = MI->getDesc().getNumDefs();
5830       unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
5831       unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
5832       unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
5833       bool Tied1 =
5834           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5835       bool Tied2 =
5836           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5837 
5838       // If either of the commutable operands are tied to the destination
5839       // then we can not commute + fold.
5840       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5841           (HasDef && Reg0 == Reg2 && Tied2))
5842         return nullptr;
5843 
5844       MachineInstr *CommutedMI =
5845           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5846       if (!CommutedMI) {
5847         // Unable to commute.
5848         return nullptr;
5849       }
5850       if (CommutedMI != MI) {
5851         // New instruction. We can't fold from this.
5852         CommutedMI->eraseFromParent();
5853         return nullptr;
5854       }
5855 
5856       // Attempt to fold with the commuted version of the instruction.
5857       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5858                                     Size, Align, /*AllowCommute=*/false);
5859       if (NewMI)
5860         return NewMI;
5861 
5862       // Folding failed again - undo the commute before returning.
5863       MachineInstr *UncommutedMI =
5864           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5865       if (!UncommutedMI) {
5866         // Unable to commute.
5867         return nullptr;
5868       }
5869       if (UncommutedMI != MI) {
5870         // New instruction. It doesn't need to be kept.
5871         UncommutedMI->eraseFromParent();
5872         return nullptr;
5873       }
5874 
5875       // Return here to prevent duplicate fuse failure report.
5876       return nullptr;
5877     }
5878   }
5879 
5880   // No fusion
5881   if (PrintFailedFusing && !MI->isCopy())
5882     dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
5883   return nullptr;
5884 }
5885 
5886 /// Return true for all instructions that only update
5887 /// the first 32 or 64-bits of the destination register and leave the rest
5888 /// unmodified. This can be used to avoid folding loads if the instructions
5889 /// only update part of the destination register, and the non-updated part is
5890 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5891 /// instructions breaks the partial register dependency and it can improve
5892 /// performance. e.g.:
5893 ///
5894 ///   movss (%rdi), %xmm0
5895 ///   cvtss2sd %xmm0, %xmm0
5896 ///
5897 /// Instead of
5898 ///   cvtss2sd (%rdi), %xmm0
5899 ///
5900 /// FIXME: This should be turned into a TSFlags.
5901 ///
5902 static bool hasPartialRegUpdate(unsigned Opcode) {
5903   switch (Opcode) {
5904   case X86::CVTSI2SSrr:
5905   case X86::CVTSI2SSrm:
5906   case X86::CVTSI2SS64rr:
5907   case X86::CVTSI2SS64rm:
5908   case X86::CVTSI2SDrr:
5909   case X86::CVTSI2SDrm:
5910   case X86::CVTSI2SD64rr:
5911   case X86::CVTSI2SD64rm:
5912   case X86::CVTSD2SSrr:
5913   case X86::CVTSD2SSrm:
5914   case X86::Int_CVTSD2SSrr:
5915   case X86::Int_CVTSD2SSrm:
5916   case X86::CVTSS2SDrr:
5917   case X86::CVTSS2SDrm:
5918   case X86::Int_CVTSS2SDrr:
5919   case X86::Int_CVTSS2SDrm:
5920   case X86::MOVHPDrm:
5921   case X86::MOVHPSrm:
5922   case X86::MOVLPDrm:
5923   case X86::MOVLPSrm:
5924   case X86::RCPSSr:
5925   case X86::RCPSSm:
5926   case X86::RCPSSr_Int:
5927   case X86::RCPSSm_Int:
5928   case X86::ROUNDSDr:
5929   case X86::ROUNDSDm:
5930   case X86::ROUNDSDr_Int:
5931   case X86::ROUNDSSr:
5932   case X86::ROUNDSSm:
5933   case X86::ROUNDSSr_Int:
5934   case X86::RSQRTSSr:
5935   case X86::RSQRTSSm:
5936   case X86::RSQRTSSr_Int:
5937   case X86::RSQRTSSm_Int:
5938   case X86::SQRTSSr:
5939   case X86::SQRTSSm:
5940   case X86::SQRTSSr_Int:
5941   case X86::SQRTSSm_Int:
5942   case X86::SQRTSDr:
5943   case X86::SQRTSDm:
5944   case X86::SQRTSDr_Int:
5945   case X86::SQRTSDm_Int:
5946     return true;
5947   }
5948 
5949   return false;
5950 }
5951 
5952 /// Inform the ExeDepsFix pass how many idle
5953 /// instructions we would like before a partial register update.
5954 unsigned X86InstrInfo::
5955 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
5956                              const TargetRegisterInfo *TRI) const {
5957   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
5958     return 0;
5959 
5960   // If MI is marked as reading Reg, the partial register update is wanted.
5961   const MachineOperand &MO = MI->getOperand(0);
5962   unsigned Reg = MO.getReg();
5963   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
5964     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
5965       return 0;
5966   } else {
5967     if (MI->readsRegister(Reg, TRI))
5968       return 0;
5969   }
5970 
5971   // If any of the preceding 16 instructions are reading Reg, insert a
5972   // dependency breaking instruction.  The magic number is based on a few
5973   // Nehalem experiments.
5974   return 16;
5975 }
5976 
5977 // Return true for any instruction the copies the high bits of the first source
5978 // operand into the unused high bits of the destination operand.
5979 static bool hasUndefRegUpdate(unsigned Opcode) {
5980   switch (Opcode) {
5981   case X86::VCVTSI2SSrr:
5982   case X86::VCVTSI2SSrm:
5983   case X86::Int_VCVTSI2SSrr:
5984   case X86::Int_VCVTSI2SSrm:
5985   case X86::VCVTSI2SS64rr:
5986   case X86::VCVTSI2SS64rm:
5987   case X86::Int_VCVTSI2SS64rr:
5988   case X86::Int_VCVTSI2SS64rm:
5989   case X86::VCVTSI2SDrr:
5990   case X86::VCVTSI2SDrm:
5991   case X86::Int_VCVTSI2SDrr:
5992   case X86::Int_VCVTSI2SDrm:
5993   case X86::VCVTSI2SD64rr:
5994   case X86::VCVTSI2SD64rm:
5995   case X86::Int_VCVTSI2SD64rr:
5996   case X86::Int_VCVTSI2SD64rm:
5997   case X86::VCVTSD2SSrr:
5998   case X86::VCVTSD2SSrm:
5999   case X86::Int_VCVTSD2SSrr:
6000   case X86::Int_VCVTSD2SSrm:
6001   case X86::VCVTSS2SDrr:
6002   case X86::VCVTSS2SDrm:
6003   case X86::Int_VCVTSS2SDrr:
6004   case X86::Int_VCVTSS2SDrm:
6005   case X86::VRCPSSr:
6006   case X86::VRCPSSm:
6007   case X86::VRCPSSm_Int:
6008   case X86::VROUNDSDr:
6009   case X86::VROUNDSDm:
6010   case X86::VROUNDSDr_Int:
6011   case X86::VROUNDSSr:
6012   case X86::VROUNDSSm:
6013   case X86::VROUNDSSr_Int:
6014   case X86::VRSQRTSSr:
6015   case X86::VRSQRTSSm:
6016   case X86::VRSQRTSSm_Int:
6017   case X86::VSQRTSSr:
6018   case X86::VSQRTSSm:
6019   case X86::VSQRTSSm_Int:
6020   case X86::VSQRTSDr:
6021   case X86::VSQRTSDm:
6022   case X86::VSQRTSDm_Int:
6023     // AVX-512
6024   case X86::VCVTSD2SSZrr:
6025   case X86::VCVTSD2SSZrm:
6026   case X86::VCVTSS2SDZrr:
6027   case X86::VCVTSS2SDZrm:
6028     return true;
6029   }
6030 
6031   return false;
6032 }
6033 
6034 /// Inform the ExeDepsFix pass how many idle instructions we would like before
6035 /// certain undef register reads.
6036 ///
6037 /// This catches the VCVTSI2SD family of instructions:
6038 ///
6039 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6040 ///
6041 /// We should to be careful *not* to catch VXOR idioms which are presumably
6042 /// handled specially in the pipeline:
6043 ///
6044 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6045 ///
6046 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6047 /// high bits that are passed-through are not live.
6048 unsigned X86InstrInfo::
6049 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
6050                      const TargetRegisterInfo *TRI) const {
6051   if (!hasUndefRegUpdate(MI->getOpcode()))
6052     return 0;
6053 
6054   // Set the OpNum parameter to the first source operand.
6055   OpNum = 1;
6056 
6057   const MachineOperand &MO = MI->getOperand(OpNum);
6058   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
6059     // Use the same magic number as getPartialRegUpdateClearance.
6060     return 16;
6061   }
6062   return 0;
6063 }
6064 
6065 void X86InstrInfo::
6066 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
6067                           const TargetRegisterInfo *TRI) const {
6068   unsigned Reg = MI->getOperand(OpNum).getReg();
6069   // If MI kills this register, the false dependence is already broken.
6070   if (MI->killsRegister(Reg, TRI))
6071     return;
6072 
6073   if (X86::VR128RegClass.contains(Reg)) {
6074     // These instructions are all floating point domain, so xorps is the best
6075     // choice.
6076     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
6077     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
6078       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
6079     MI->addRegisterKilled(Reg, TRI, true);
6080   } else if (X86::VR256RegClass.contains(Reg)) {
6081     // Use vxorps to clear the full ymm register.
6082     // It wants to read and write the xmm sub-register.
6083     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
6084     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
6085       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
6086       .addReg(Reg, RegState::ImplicitDefine);
6087     MI->addRegisterKilled(Reg, TRI, true);
6088   }
6089 }
6090 
6091 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6092     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
6093     MachineBasicBlock::iterator InsertPt, int FrameIndex,
6094     LiveIntervals *LIS) const {
6095   // Check switch flag
6096   if (NoFusing)
6097     return nullptr;
6098 
6099   // Unless optimizing for size, don't fold to avoid partial
6100   // register update stalls
6101   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
6102     return nullptr;
6103 
6104   const MachineFrameInfo *MFI = MF.getFrameInfo();
6105   unsigned Size = MFI->getObjectSize(FrameIndex);
6106   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
6107   // If the function stack isn't realigned we don't want to fold instructions
6108   // that need increased alignment.
6109   if (!RI.needsStackRealignment(MF))
6110     Alignment =
6111         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
6112   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6113     unsigned NewOpc = 0;
6114     unsigned RCSize = 0;
6115     switch (MI->getOpcode()) {
6116     default: return nullptr;
6117     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
6118     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6119     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6120     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
6121     }
6122     // Check if it's safe to fold the load. If the size of the object is
6123     // narrower than the load width, then it's not.
6124     if (Size < RCSize)
6125       return nullptr;
6126     // Change to CMPXXri r, 0 first.
6127     MI->setDesc(get(NewOpc));
6128     MI->getOperand(1).ChangeToImmediate(0);
6129   } else if (Ops.size() != 1)
6130     return nullptr;
6131 
6132   return foldMemoryOperandImpl(MF, MI, Ops[0],
6133                                MachineOperand::CreateFI(FrameIndex), InsertPt,
6134                                Size, Alignment, /*AllowCommute=*/true);
6135 }
6136 
6137 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6138 /// because the latter uses contents that wouldn't be defined in the folded
6139 /// version.  For instance, this transformation isn't legal:
6140 ///   movss (%rdi), %xmm0
6141 ///   addps %xmm0, %xmm0
6142 /// ->
6143 ///   addps (%rdi), %xmm0
6144 ///
6145 /// But this one is:
6146 ///   movss (%rdi), %xmm0
6147 ///   addss %xmm0, %xmm0
6148 /// ->
6149 ///   addss (%rdi), %xmm0
6150 ///
6151 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6152                                              const MachineInstr &UserMI,
6153                                              const MachineFunction &MF) {
6154   unsigned Opc = LoadMI.getOpcode();
6155   unsigned UserOpc = UserMI.getOpcode();
6156   unsigned RegSize =
6157       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6158 
6159   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
6160     // These instructions only load 32 bits, we can't fold them if the
6161     // destination register is wider than 32 bits (4 bytes), and its user
6162     // instruction isn't scalar (SS).
6163     switch (UserOpc) {
6164     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
6165     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
6166     case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
6167     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
6168     case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int:
6169     case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int:
6170     case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int:
6171     case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int:
6172     case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int:
6173     case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int:
6174       return false;
6175     default:
6176       return true;
6177     }
6178   }
6179 
6180   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
6181     // These instructions only load 64 bits, we can't fold them if the
6182     // destination register is wider than 64 bits (8 bytes), and its user
6183     // instruction isn't scalar (SD).
6184     switch (UserOpc) {
6185     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
6186     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
6187     case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
6188     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
6189     case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int:
6190     case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int:
6191     case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int:
6192     case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int:
6193     case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int:
6194     case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int:
6195       return false;
6196     default:
6197       return true;
6198     }
6199   }
6200 
6201   return false;
6202 }
6203 
6204 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6205     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
6206     MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI,
6207     LiveIntervals *LIS) const {
6208   // If loading from a FrameIndex, fold directly from the FrameIndex.
6209   unsigned NumOps = LoadMI->getDesc().getNumOperands();
6210   int FrameIndex;
6211   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6212     if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
6213       return nullptr;
6214     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
6215   }
6216 
6217   // Check switch flag
6218   if (NoFusing) return nullptr;
6219 
6220   // Avoid partial register update stalls unless optimizing for size.
6221   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
6222     return nullptr;
6223 
6224   // Determine the alignment of the load.
6225   unsigned Alignment = 0;
6226   if (LoadMI->hasOneMemOperand())
6227     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
6228   else
6229     switch (LoadMI->getOpcode()) {
6230     case X86::AVX2_SETALLONES:
6231     case X86::AVX_SET0:
6232       Alignment = 32;
6233       break;
6234     case X86::V_SET0:
6235     case X86::V_SETALLONES:
6236       Alignment = 16;
6237       break;
6238     case X86::FsFLD0SD:
6239       Alignment = 8;
6240       break;
6241     case X86::FsFLD0SS:
6242       Alignment = 4;
6243       break;
6244     default:
6245       return nullptr;
6246     }
6247   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6248     unsigned NewOpc = 0;
6249     switch (MI->getOpcode()) {
6250     default: return nullptr;
6251     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6252     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6253     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6254     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6255     }
6256     // Change to CMPXXri r, 0 first.
6257     MI->setDesc(get(NewOpc));
6258     MI->getOperand(1).ChangeToImmediate(0);
6259   } else if (Ops.size() != 1)
6260     return nullptr;
6261 
6262   // Make sure the subregisters match.
6263   // Otherwise we risk changing the size of the load.
6264   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
6265     return nullptr;
6266 
6267   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6268   switch (LoadMI->getOpcode()) {
6269   case X86::V_SET0:
6270   case X86::V_SETALLONES:
6271   case X86::AVX2_SETALLONES:
6272   case X86::AVX_SET0:
6273   case X86::FsFLD0SD:
6274   case X86::FsFLD0SS: {
6275     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6276     // Create a constant-pool entry and operands to load from it.
6277 
6278     // Medium and large mode can't fold loads this way.
6279     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6280         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6281       return nullptr;
6282 
6283     // x86-32 PIC requires a PIC base register for constant pools.
6284     unsigned PICBase = 0;
6285     if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
6286       if (Subtarget.is64Bit())
6287         PICBase = X86::RIP;
6288       else
6289         // FIXME: PICBase = getGlobalBaseReg(&MF);
6290         // This doesn't work for several reasons.
6291         // 1. GlobalBaseReg may have been spilled.
6292         // 2. It may not be live at MI.
6293         return nullptr;
6294     }
6295 
6296     // Create a constant-pool entry.
6297     MachineConstantPool &MCP = *MF.getConstantPool();
6298     Type *Ty;
6299     unsigned Opc = LoadMI->getOpcode();
6300     if (Opc == X86::FsFLD0SS)
6301       Ty = Type::getFloatTy(MF.getFunction()->getContext());
6302     else if (Opc == X86::FsFLD0SD)
6303       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
6304     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
6305       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
6306     else
6307       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
6308 
6309     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
6310     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6311                                     Constant::getNullValue(Ty);
6312     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6313 
6314     // Create operands to load from the constant pool entry.
6315     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6316     MOs.push_back(MachineOperand::CreateImm(1));
6317     MOs.push_back(MachineOperand::CreateReg(0, false));
6318     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6319     MOs.push_back(MachineOperand::CreateReg(0, false));
6320     break;
6321   }
6322   default: {
6323     if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
6324       return nullptr;
6325 
6326     // Folding a normal load. Just copy the load's address operands.
6327     MOs.append(LoadMI->operands_begin() + NumOps - X86::AddrNumOperands,
6328                LoadMI->operands_begin() + NumOps);
6329     break;
6330   }
6331   }
6332   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6333                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6334 }
6335 
6336 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
6337                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
6338                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
6339   auto I = MemOp2RegOpTable.find(MI->getOpcode());
6340   if (I == MemOp2RegOpTable.end())
6341     return false;
6342   unsigned Opc = I->second.first;
6343   unsigned Index = I->second.second & TB_INDEX_MASK;
6344   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6345   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6346   if (UnfoldLoad && !FoldedLoad)
6347     return false;
6348   UnfoldLoad &= FoldedLoad;
6349   if (UnfoldStore && !FoldedStore)
6350     return false;
6351   UnfoldStore &= FoldedStore;
6352 
6353   const MCInstrDesc &MCID = get(Opc);
6354   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6355   // TODO: Check if 32-byte or greater accesses are slow too?
6356   if (!MI->hasOneMemOperand() &&
6357       RC == &X86::VR128RegClass &&
6358       Subtarget.isUnalignedMem16Slow())
6359     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6360     // conservatively assume the address is unaligned. That's bad for
6361     // performance.
6362     return false;
6363   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6364   SmallVector<MachineOperand,2> BeforeOps;
6365   SmallVector<MachineOperand,2> AfterOps;
6366   SmallVector<MachineOperand,4> ImpOps;
6367   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
6368     MachineOperand &Op = MI->getOperand(i);
6369     if (i >= Index && i < Index + X86::AddrNumOperands)
6370       AddrOps.push_back(Op);
6371     else if (Op.isReg() && Op.isImplicit())
6372       ImpOps.push_back(Op);
6373     else if (i < Index)
6374       BeforeOps.push_back(Op);
6375     else if (i > Index)
6376       AfterOps.push_back(Op);
6377   }
6378 
6379   // Emit the load instruction.
6380   if (UnfoldLoad) {
6381     std::pair<MachineInstr::mmo_iterator,
6382               MachineInstr::mmo_iterator> MMOs =
6383       MF.extractLoadMemRefs(MI->memoperands_begin(),
6384                             MI->memoperands_end());
6385     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
6386     if (UnfoldStore) {
6387       // Address operands cannot be marked isKill.
6388       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6389         MachineOperand &MO = NewMIs[0]->getOperand(i);
6390         if (MO.isReg())
6391           MO.setIsKill(false);
6392       }
6393     }
6394   }
6395 
6396   // Emit the data processing instruction.
6397   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
6398   MachineInstrBuilder MIB(MF, DataMI);
6399 
6400   if (FoldedStore)
6401     MIB.addReg(Reg, RegState::Define);
6402   for (MachineOperand &BeforeOp : BeforeOps)
6403     MIB.addOperand(BeforeOp);
6404   if (FoldedLoad)
6405     MIB.addReg(Reg);
6406   for (MachineOperand &AfterOp : AfterOps)
6407     MIB.addOperand(AfterOp);
6408   for (MachineOperand &ImpOp : ImpOps) {
6409     MIB.addReg(ImpOp.getReg(),
6410                getDefRegState(ImpOp.isDef()) |
6411                RegState::Implicit |
6412                getKillRegState(ImpOp.isKill()) |
6413                getDeadRegState(ImpOp.isDead()) |
6414                getUndefRegState(ImpOp.isUndef()));
6415   }
6416   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6417   switch (DataMI->getOpcode()) {
6418   default: break;
6419   case X86::CMP64ri32:
6420   case X86::CMP64ri8:
6421   case X86::CMP32ri:
6422   case X86::CMP32ri8:
6423   case X86::CMP16ri:
6424   case X86::CMP16ri8:
6425   case X86::CMP8ri: {
6426     MachineOperand &MO0 = DataMI->getOperand(0);
6427     MachineOperand &MO1 = DataMI->getOperand(1);
6428     if (MO1.getImm() == 0) {
6429       unsigned NewOpc;
6430       switch (DataMI->getOpcode()) {
6431       default: llvm_unreachable("Unreachable!");
6432       case X86::CMP64ri8:
6433       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6434       case X86::CMP32ri8:
6435       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6436       case X86::CMP16ri8:
6437       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6438       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6439       }
6440       DataMI->setDesc(get(NewOpc));
6441       MO1.ChangeToRegister(MO0.getReg(), false);
6442     }
6443   }
6444   }
6445   NewMIs.push_back(DataMI);
6446 
6447   // Emit the store instruction.
6448   if (UnfoldStore) {
6449     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6450     std::pair<MachineInstr::mmo_iterator,
6451               MachineInstr::mmo_iterator> MMOs =
6452       MF.extractStoreMemRefs(MI->memoperands_begin(),
6453                              MI->memoperands_end());
6454     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
6455   }
6456 
6457   return true;
6458 }
6459 
6460 bool
6461 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6462                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6463   if (!N->isMachineOpcode())
6464     return false;
6465 
6466   auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
6467   if (I == MemOp2RegOpTable.end())
6468     return false;
6469   unsigned Opc = I->second.first;
6470   unsigned Index = I->second.second & TB_INDEX_MASK;
6471   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6472   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6473   const MCInstrDesc &MCID = get(Opc);
6474   MachineFunction &MF = DAG.getMachineFunction();
6475   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6476   unsigned NumDefs = MCID.NumDefs;
6477   std::vector<SDValue> AddrOps;
6478   std::vector<SDValue> BeforeOps;
6479   std::vector<SDValue> AfterOps;
6480   SDLoc dl(N);
6481   unsigned NumOps = N->getNumOperands();
6482   for (unsigned i = 0; i != NumOps-1; ++i) {
6483     SDValue Op = N->getOperand(i);
6484     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6485       AddrOps.push_back(Op);
6486     else if (i < Index-NumDefs)
6487       BeforeOps.push_back(Op);
6488     else if (i > Index-NumDefs)
6489       AfterOps.push_back(Op);
6490   }
6491   SDValue Chain = N->getOperand(NumOps-1);
6492   AddrOps.push_back(Chain);
6493 
6494   // Emit the load instruction.
6495   SDNode *Load = nullptr;
6496   if (FoldedLoad) {
6497     EVT VT = *RC->vt_begin();
6498     std::pair<MachineInstr::mmo_iterator,
6499               MachineInstr::mmo_iterator> MMOs =
6500       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6501                             cast<MachineSDNode>(N)->memoperands_end());
6502     if (!(*MMOs.first) &&
6503         RC == &X86::VR128RegClass &&
6504         Subtarget.isUnalignedMem16Slow())
6505       // Do not introduce a slow unaligned load.
6506       return false;
6507     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6508     // memory access is slow above.
6509     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6510     bool isAligned = (*MMOs.first) &&
6511                      (*MMOs.first)->getAlignment() >= Alignment;
6512     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
6513                               VT, MVT::Other, AddrOps);
6514     NewNodes.push_back(Load);
6515 
6516     // Preserve memory reference information.
6517     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
6518   }
6519 
6520   // Emit the data processing instruction.
6521   std::vector<EVT> VTs;
6522   const TargetRegisterClass *DstRC = nullptr;
6523   if (MCID.getNumDefs() > 0) {
6524     DstRC = getRegClass(MCID, 0, &RI, MF);
6525     VTs.push_back(*DstRC->vt_begin());
6526   }
6527   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6528     EVT VT = N->getValueType(i);
6529     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6530       VTs.push_back(VT);
6531   }
6532   if (Load)
6533     BeforeOps.push_back(SDValue(Load, 0));
6534   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
6535   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6536   NewNodes.push_back(NewNode);
6537 
6538   // Emit the store instruction.
6539   if (FoldedStore) {
6540     AddrOps.pop_back();
6541     AddrOps.push_back(SDValue(NewNode, 0));
6542     AddrOps.push_back(Chain);
6543     std::pair<MachineInstr::mmo_iterator,
6544               MachineInstr::mmo_iterator> MMOs =
6545       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6546                              cast<MachineSDNode>(N)->memoperands_end());
6547     if (!(*MMOs.first) &&
6548         RC == &X86::VR128RegClass &&
6549         Subtarget.isUnalignedMem16Slow())
6550       // Do not introduce a slow unaligned store.
6551       return false;
6552     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6553     // memory access is slow above.
6554     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6555     bool isAligned = (*MMOs.first) &&
6556                      (*MMOs.first)->getAlignment() >= Alignment;
6557     SDNode *Store =
6558         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6559                            dl, MVT::Other, AddrOps);
6560     NewNodes.push_back(Store);
6561 
6562     // Preserve memory reference information.
6563     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
6564   }
6565 
6566   return true;
6567 }
6568 
6569 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6570                                       bool UnfoldLoad, bool UnfoldStore,
6571                                       unsigned *LoadRegIndex) const {
6572   auto I = MemOp2RegOpTable.find(Opc);
6573   if (I == MemOp2RegOpTable.end())
6574     return 0;
6575   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6576   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6577   if (UnfoldLoad && !FoldedLoad)
6578     return 0;
6579   if (UnfoldStore && !FoldedStore)
6580     return 0;
6581   if (LoadRegIndex)
6582     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
6583   return I->second.first;
6584 }
6585 
6586 bool
6587 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6588                                      int64_t &Offset1, int64_t &Offset2) const {
6589   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6590     return false;
6591   unsigned Opc1 = Load1->getMachineOpcode();
6592   unsigned Opc2 = Load2->getMachineOpcode();
6593   switch (Opc1) {
6594   default: return false;
6595   case X86::MOV8rm:
6596   case X86::MOV16rm:
6597   case X86::MOV32rm:
6598   case X86::MOV64rm:
6599   case X86::LD_Fp32m:
6600   case X86::LD_Fp64m:
6601   case X86::LD_Fp80m:
6602   case X86::MOVSSrm:
6603   case X86::MOVSDrm:
6604   case X86::MMX_MOVD64rm:
6605   case X86::MMX_MOVQ64rm:
6606   case X86::FsMOVAPSrm:
6607   case X86::FsMOVAPDrm:
6608   case X86::MOVAPSrm:
6609   case X86::MOVUPSrm:
6610   case X86::MOVAPDrm:
6611   case X86::MOVDQArm:
6612   case X86::MOVDQUrm:
6613   // AVX load instructions
6614   case X86::VMOVSSrm:
6615   case X86::VMOVSDrm:
6616   case X86::FsVMOVAPSrm:
6617   case X86::FsVMOVAPDrm:
6618   case X86::VMOVAPSrm:
6619   case X86::VMOVUPSrm:
6620   case X86::VMOVAPDrm:
6621   case X86::VMOVDQArm:
6622   case X86::VMOVDQUrm:
6623   case X86::VMOVAPSYrm:
6624   case X86::VMOVUPSYrm:
6625   case X86::VMOVAPDYrm:
6626   case X86::VMOVDQAYrm:
6627   case X86::VMOVDQUYrm:
6628     break;
6629   }
6630   switch (Opc2) {
6631   default: return false;
6632   case X86::MOV8rm:
6633   case X86::MOV16rm:
6634   case X86::MOV32rm:
6635   case X86::MOV64rm:
6636   case X86::LD_Fp32m:
6637   case X86::LD_Fp64m:
6638   case X86::LD_Fp80m:
6639   case X86::MOVSSrm:
6640   case X86::MOVSDrm:
6641   case X86::MMX_MOVD64rm:
6642   case X86::MMX_MOVQ64rm:
6643   case X86::FsMOVAPSrm:
6644   case X86::FsMOVAPDrm:
6645   case X86::MOVAPSrm:
6646   case X86::MOVUPSrm:
6647   case X86::MOVAPDrm:
6648   case X86::MOVDQArm:
6649   case X86::MOVDQUrm:
6650   // AVX load instructions
6651   case X86::VMOVSSrm:
6652   case X86::VMOVSDrm:
6653   case X86::FsVMOVAPSrm:
6654   case X86::FsVMOVAPDrm:
6655   case X86::VMOVAPSrm:
6656   case X86::VMOVUPSrm:
6657   case X86::VMOVAPDrm:
6658   case X86::VMOVDQArm:
6659   case X86::VMOVDQUrm:
6660   case X86::VMOVAPSYrm:
6661   case X86::VMOVUPSYrm:
6662   case X86::VMOVAPDYrm:
6663   case X86::VMOVDQAYrm:
6664   case X86::VMOVDQUYrm:
6665     break;
6666   }
6667 
6668   // Check if chain operands and base addresses match.
6669   if (Load1->getOperand(0) != Load2->getOperand(0) ||
6670       Load1->getOperand(5) != Load2->getOperand(5))
6671     return false;
6672   // Segment operands should match as well.
6673   if (Load1->getOperand(4) != Load2->getOperand(4))
6674     return false;
6675   // Scale should be 1, Index should be Reg0.
6676   if (Load1->getOperand(1) == Load2->getOperand(1) &&
6677       Load1->getOperand(2) == Load2->getOperand(2)) {
6678     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6679       return false;
6680 
6681     // Now let's examine the displacements.
6682     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6683         isa<ConstantSDNode>(Load2->getOperand(3))) {
6684       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6685       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6686       return true;
6687     }
6688   }
6689   return false;
6690 }
6691 
6692 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6693                                            int64_t Offset1, int64_t Offset2,
6694                                            unsigned NumLoads) const {
6695   assert(Offset2 > Offset1);
6696   if ((Offset2 - Offset1) / 8 > 64)
6697     return false;
6698 
6699   unsigned Opc1 = Load1->getMachineOpcode();
6700   unsigned Opc2 = Load2->getMachineOpcode();
6701   if (Opc1 != Opc2)
6702     return false;  // FIXME: overly conservative?
6703 
6704   switch (Opc1) {
6705   default: break;
6706   case X86::LD_Fp32m:
6707   case X86::LD_Fp64m:
6708   case X86::LD_Fp80m:
6709   case X86::MMX_MOVD64rm:
6710   case X86::MMX_MOVQ64rm:
6711     return false;
6712   }
6713 
6714   EVT VT = Load1->getValueType(0);
6715   switch (VT.getSimpleVT().SimpleTy) {
6716   default:
6717     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6718     // have 16 of them to play with.
6719     if (Subtarget.is64Bit()) {
6720       if (NumLoads >= 3)
6721         return false;
6722     } else if (NumLoads) {
6723       return false;
6724     }
6725     break;
6726   case MVT::i8:
6727   case MVT::i16:
6728   case MVT::i32:
6729   case MVT::i64:
6730   case MVT::f32:
6731   case MVT::f64:
6732     if (NumLoads)
6733       return false;
6734     break;
6735   }
6736 
6737   return true;
6738 }
6739 
6740 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
6741                                           MachineInstr *Second) const {
6742   // Check if this processor supports macro-fusion. Since this is a minor
6743   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6744   // proxy for SandyBridge+.
6745   if (!Subtarget.hasAVX())
6746     return false;
6747 
6748   enum {
6749     FuseTest,
6750     FuseCmp,
6751     FuseInc
6752   } FuseKind;
6753 
6754   switch(Second->getOpcode()) {
6755   default:
6756     return false;
6757   case X86::JE_1:
6758   case X86::JNE_1:
6759   case X86::JL_1:
6760   case X86::JLE_1:
6761   case X86::JG_1:
6762   case X86::JGE_1:
6763     FuseKind = FuseInc;
6764     break;
6765   case X86::JB_1:
6766   case X86::JBE_1:
6767   case X86::JA_1:
6768   case X86::JAE_1:
6769     FuseKind = FuseCmp;
6770     break;
6771   case X86::JS_1:
6772   case X86::JNS_1:
6773   case X86::JP_1:
6774   case X86::JNP_1:
6775   case X86::JO_1:
6776   case X86::JNO_1:
6777     FuseKind = FuseTest;
6778     break;
6779   }
6780   switch (First->getOpcode()) {
6781   default:
6782     return false;
6783   case X86::TEST8rr:
6784   case X86::TEST16rr:
6785   case X86::TEST32rr:
6786   case X86::TEST64rr:
6787   case X86::TEST8ri:
6788   case X86::TEST16ri:
6789   case X86::TEST32ri:
6790   case X86::TEST32i32:
6791   case X86::TEST64i32:
6792   case X86::TEST64ri32:
6793   case X86::TEST8rm:
6794   case X86::TEST16rm:
6795   case X86::TEST32rm:
6796   case X86::TEST64rm:
6797   case X86::TEST8ri_NOREX:
6798   case X86::AND16i16:
6799   case X86::AND16ri:
6800   case X86::AND16ri8:
6801   case X86::AND16rm:
6802   case X86::AND16rr:
6803   case X86::AND32i32:
6804   case X86::AND32ri:
6805   case X86::AND32ri8:
6806   case X86::AND32rm:
6807   case X86::AND32rr:
6808   case X86::AND64i32:
6809   case X86::AND64ri32:
6810   case X86::AND64ri8:
6811   case X86::AND64rm:
6812   case X86::AND64rr:
6813   case X86::AND8i8:
6814   case X86::AND8ri:
6815   case X86::AND8rm:
6816   case X86::AND8rr:
6817     return true;
6818   case X86::CMP16i16:
6819   case X86::CMP16ri:
6820   case X86::CMP16ri8:
6821   case X86::CMP16rm:
6822   case X86::CMP16rr:
6823   case X86::CMP32i32:
6824   case X86::CMP32ri:
6825   case X86::CMP32ri8:
6826   case X86::CMP32rm:
6827   case X86::CMP32rr:
6828   case X86::CMP64i32:
6829   case X86::CMP64ri32:
6830   case X86::CMP64ri8:
6831   case X86::CMP64rm:
6832   case X86::CMP64rr:
6833   case X86::CMP8i8:
6834   case X86::CMP8ri:
6835   case X86::CMP8rm:
6836   case X86::CMP8rr:
6837   case X86::ADD16i16:
6838   case X86::ADD16ri:
6839   case X86::ADD16ri8:
6840   case X86::ADD16ri8_DB:
6841   case X86::ADD16ri_DB:
6842   case X86::ADD16rm:
6843   case X86::ADD16rr:
6844   case X86::ADD16rr_DB:
6845   case X86::ADD32i32:
6846   case X86::ADD32ri:
6847   case X86::ADD32ri8:
6848   case X86::ADD32ri8_DB:
6849   case X86::ADD32ri_DB:
6850   case X86::ADD32rm:
6851   case X86::ADD32rr:
6852   case X86::ADD32rr_DB:
6853   case X86::ADD64i32:
6854   case X86::ADD64ri32:
6855   case X86::ADD64ri32_DB:
6856   case X86::ADD64ri8:
6857   case X86::ADD64ri8_DB:
6858   case X86::ADD64rm:
6859   case X86::ADD64rr:
6860   case X86::ADD64rr_DB:
6861   case X86::ADD8i8:
6862   case X86::ADD8mi:
6863   case X86::ADD8mr:
6864   case X86::ADD8ri:
6865   case X86::ADD8rm:
6866   case X86::ADD8rr:
6867   case X86::SUB16i16:
6868   case X86::SUB16ri:
6869   case X86::SUB16ri8:
6870   case X86::SUB16rm:
6871   case X86::SUB16rr:
6872   case X86::SUB32i32:
6873   case X86::SUB32ri:
6874   case X86::SUB32ri8:
6875   case X86::SUB32rm:
6876   case X86::SUB32rr:
6877   case X86::SUB64i32:
6878   case X86::SUB64ri32:
6879   case X86::SUB64ri8:
6880   case X86::SUB64rm:
6881   case X86::SUB64rr:
6882   case X86::SUB8i8:
6883   case X86::SUB8ri:
6884   case X86::SUB8rm:
6885   case X86::SUB8rr:
6886     return FuseKind == FuseCmp || FuseKind == FuseInc;
6887   case X86::INC16r:
6888   case X86::INC32r:
6889   case X86::INC64r:
6890   case X86::INC8r:
6891   case X86::DEC16r:
6892   case X86::DEC32r:
6893   case X86::DEC64r:
6894   case X86::DEC8r:
6895     return FuseKind == FuseInc;
6896   }
6897 }
6898 
6899 bool X86InstrInfo::
6900 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6901   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6902   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6903   Cond[0].setImm(GetOppositeBranchCondition(CC));
6904   return false;
6905 }
6906 
6907 bool X86InstrInfo::
6908 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6909   // FIXME: Return false for x87 stack register classes for now. We can't
6910   // allow any loads of these registers before FpGet_ST0_80.
6911   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6912            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
6913 }
6914 
6915 /// Return a virtual register initialized with the
6916 /// the global base register value. Output instructions required to
6917 /// initialize the register in the function entry block, if necessary.
6918 ///
6919 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6920 ///
6921 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6922   assert(!Subtarget.is64Bit() &&
6923          "X86-64 PIC uses RIP relative addressing");
6924 
6925   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6926   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6927   if (GlobalBaseReg != 0)
6928     return GlobalBaseReg;
6929 
6930   // Create the register. The code to initialize it is inserted
6931   // later, by the CGBR pass (below).
6932   MachineRegisterInfo &RegInfo = MF->getRegInfo();
6933   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
6934   X86FI->setGlobalBaseReg(GlobalBaseReg);
6935   return GlobalBaseReg;
6936 }
6937 
6938 // These are the replaceable SSE instructions. Some of these have Int variants
6939 // that we don't include here. We don't want to replace instructions selected
6940 // by intrinsics.
6941 static const uint16_t ReplaceableInstrs[][3] = {
6942   //PackedSingle     PackedDouble    PackedInt
6943   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
6944   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
6945   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
6946   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
6947   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
6948   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr  },
6949   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
6950   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
6951   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
6952   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
6953   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
6954   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
6955   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
6956   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
6957   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
6958   // AVX 128-bit support
6959   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
6960   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
6961   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
6962   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
6963   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
6964   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr  },
6965   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6966   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
6967   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
6968   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
6969   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
6970   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
6971   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
6972   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
6973   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
6974   // AVX 256-bit support
6975   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
6976   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
6977   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
6978   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
6979   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
6980   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
6981 };
6982 
6983 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6984   //PackedSingle       PackedDouble       PackedInt
6985   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
6986   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
6987   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
6988   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
6989   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
6990   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
6991   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
6992   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
6993   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6994   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6995   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
6996   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
6997   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
6998   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
6999   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7000   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7001   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7002   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7003   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7004   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
7005 };
7006 
7007 // FIXME: Some shuffle and unpack instructions have equivalents in different
7008 // domains, but they require a bit more work than just switching opcodes.
7009 
7010 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
7011   for (const uint16_t (&Row)[3] : ReplaceableInstrs)
7012     if (Row[domain-1] == opcode)
7013       return Row;
7014   return nullptr;
7015 }
7016 
7017 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
7018   for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
7019     if (Row[domain-1] == opcode)
7020       return Row;
7021   return nullptr;
7022 }
7023 
7024 std::pair<uint16_t, uint16_t>
7025 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
7026   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7027   bool hasAVX2 = Subtarget.hasAVX2();
7028   uint16_t validDomains = 0;
7029   if (domain && lookup(MI->getOpcode(), domain))
7030     validDomains = 0xe;
7031   else if (domain && lookupAVX2(MI->getOpcode(), domain))
7032     validDomains = hasAVX2 ? 0xe : 0x6;
7033   return std::make_pair(domain, validDomains);
7034 }
7035 
7036 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
7037   assert(Domain>0 && Domain<4 && "Invalid execution domain");
7038   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7039   assert(dom && "Not an SSE instruction");
7040   const uint16_t *table = lookup(MI->getOpcode(), dom);
7041   if (!table) { // try the other table
7042     assert((Subtarget.hasAVX2() || Domain < 3) &&
7043            "256-bit vector operations only available in AVX2");
7044     table = lookupAVX2(MI->getOpcode(), dom);
7045   }
7046   assert(table && "Cannot change domain");
7047   MI->setDesc(get(table[Domain-1]));
7048 }
7049 
7050 /// Return the noop instruction to use for a noop.
7051 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7052   NopInst.setOpcode(X86::NOOP);
7053 }
7054 
7055 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
7056 // In particular, getJumpInstrTableEntryBound must always return an upper bound
7057 // on the encoding lengths of the instructions generated by
7058 // getUnconditionalBranch and getTrap.
7059 void X86InstrInfo::getUnconditionalBranch(
7060     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
7061   Branch.setOpcode(X86::JMP_1);
7062   Branch.addOperand(MCOperand::createExpr(BranchTarget));
7063 }
7064 
7065 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
7066 // In particular, getJumpInstrTableEntryBound must always return an upper bound
7067 // on the encoding lengths of the instructions generated by
7068 // getUnconditionalBranch and getTrap.
7069 void X86InstrInfo::getTrap(MCInst &MI) const {
7070   MI.setOpcode(X86::TRAP);
7071 }
7072 
7073 // See getTrap and getUnconditionalBranch for conditions on the value returned
7074 // by this function.
7075 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7076   // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7077   // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7078   return 5;
7079 }
7080 
7081 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7082   switch (opc) {
7083   default: return false;
7084   case X86::DIVSDrm:
7085   case X86::DIVSDrm_Int:
7086   case X86::DIVSDrr:
7087   case X86::DIVSDrr_Int:
7088   case X86::DIVSSrm:
7089   case X86::DIVSSrm_Int:
7090   case X86::DIVSSrr:
7091   case X86::DIVSSrr_Int:
7092   case X86::SQRTPDm:
7093   case X86::SQRTPDr:
7094   case X86::SQRTPSm:
7095   case X86::SQRTPSr:
7096   case X86::SQRTSDm:
7097   case X86::SQRTSDm_Int:
7098   case X86::SQRTSDr:
7099   case X86::SQRTSDr_Int:
7100   case X86::SQRTSSm:
7101   case X86::SQRTSSm_Int:
7102   case X86::SQRTSSr:
7103   case X86::SQRTSSr_Int:
7104   // AVX instructions with high latency
7105   case X86::VDIVSDrm:
7106   case X86::VDIVSDrm_Int:
7107   case X86::VDIVSDrr:
7108   case X86::VDIVSDrr_Int:
7109   case X86::VDIVSSrm:
7110   case X86::VDIVSSrm_Int:
7111   case X86::VDIVSSrr:
7112   case X86::VDIVSSrr_Int:
7113   case X86::VSQRTPDm:
7114   case X86::VSQRTPDr:
7115   case X86::VSQRTPSm:
7116   case X86::VSQRTPSr:
7117   case X86::VSQRTSDm:
7118   case X86::VSQRTSDm_Int:
7119   case X86::VSQRTSDr:
7120   case X86::VSQRTSSm:
7121   case X86::VSQRTSSm_Int:
7122   case X86::VSQRTSSr:
7123   case X86::VSQRTPDZm:
7124   case X86::VSQRTPDZr:
7125   case X86::VSQRTPSZm:
7126   case X86::VSQRTPSZr:
7127   case X86::VSQRTSDZm:
7128   case X86::VSQRTSDZm_Int:
7129   case X86::VSQRTSDZr:
7130   case X86::VSQRTSSZm_Int:
7131   case X86::VSQRTSSZr:
7132   case X86::VSQRTSSZm:
7133   case X86::VDIVSDZrm:
7134   case X86::VDIVSDZrr:
7135   case X86::VDIVSSZrm:
7136   case X86::VDIVSSZrr:
7137 
7138   case X86::VGATHERQPSZrm:
7139   case X86::VGATHERQPDZrm:
7140   case X86::VGATHERDPDZrm:
7141   case X86::VGATHERDPSZrm:
7142   case X86::VPGATHERQDZrm:
7143   case X86::VPGATHERQQZrm:
7144   case X86::VPGATHERDDZrm:
7145   case X86::VPGATHERDQZrm:
7146   case X86::VSCATTERQPDZmr:
7147   case X86::VSCATTERQPSZmr:
7148   case X86::VSCATTERDPDZmr:
7149   case X86::VSCATTERDPSZmr:
7150   case X86::VPSCATTERQDZmr:
7151   case X86::VPSCATTERQQZmr:
7152   case X86::VPSCATTERDDZmr:
7153   case X86::VPSCATTERDQZmr:
7154     return true;
7155   }
7156 }
7157 
7158 bool X86InstrInfo::
7159 hasHighOperandLatency(const TargetSchedModel &SchedModel,
7160                       const MachineRegisterInfo *MRI,
7161                       const MachineInstr *DefMI, unsigned DefIdx,
7162                       const MachineInstr *UseMI, unsigned UseIdx) const {
7163   return isHighLatencyDef(DefMI->getOpcode());
7164 }
7165 
7166 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7167                                            const MachineBasicBlock *MBB) const {
7168   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7169          "Reassociation needs binary operators");
7170 
7171   // Integer binary math/logic instructions have a third source operand:
7172   // the EFLAGS register. That operand must be both defined here and never
7173   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7174   // not change anything because rearranging the operands could affect other
7175   // instructions that depend on the exact status flags (zero, sign, etc.)
7176   // that are set by using these particular operands with this operation.
7177   if (Inst.getNumOperands() == 4) {
7178     assert(Inst.getOperand(3).isReg() &&
7179            Inst.getOperand(3).getReg() == X86::EFLAGS &&
7180            "Unexpected operand in reassociable instruction");
7181     if (!Inst.getOperand(3).isDead())
7182       return false;
7183   }
7184 
7185   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7186 }
7187 
7188 // TODO: There are many more machine instruction opcodes to match:
7189 //       1. Other data types (integer, vectors)
7190 //       2. Other math / logic operations (xor, or)
7191 //       3. Other forms of the same operation (intrinsics and other variants)
7192 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7193   switch (Inst.getOpcode()) {
7194   case X86::AND8rr:
7195   case X86::AND16rr:
7196   case X86::AND32rr:
7197   case X86::AND64rr:
7198   case X86::OR8rr:
7199   case X86::OR16rr:
7200   case X86::OR32rr:
7201   case X86::OR64rr:
7202   case X86::XOR8rr:
7203   case X86::XOR16rr:
7204   case X86::XOR32rr:
7205   case X86::XOR64rr:
7206   case X86::IMUL16rr:
7207   case X86::IMUL32rr:
7208   case X86::IMUL64rr:
7209   case X86::PANDrr:
7210   case X86::PORrr:
7211   case X86::PXORrr:
7212   case X86::VPANDrr:
7213   case X86::VPANDYrr:
7214   case X86::VPORrr:
7215   case X86::VPORYrr:
7216   case X86::VPXORrr:
7217   case X86::VPXORYrr:
7218   // Normal min/max instructions are not commutative because of NaN and signed
7219   // zero semantics, but these are. Thus, there's no need to check for global
7220   // relaxed math; the instructions themselves have the properties we need.
7221   case X86::MAXCPDrr:
7222   case X86::MAXCPSrr:
7223   case X86::MAXCSDrr:
7224   case X86::MAXCSSrr:
7225   case X86::MINCPDrr:
7226   case X86::MINCPSrr:
7227   case X86::MINCSDrr:
7228   case X86::MINCSSrr:
7229   case X86::VMAXCPDrr:
7230   case X86::VMAXCPSrr:
7231   case X86::VMAXCPDYrr:
7232   case X86::VMAXCPSYrr:
7233   case X86::VMAXCSDrr:
7234   case X86::VMAXCSSrr:
7235   case X86::VMINCPDrr:
7236   case X86::VMINCPSrr:
7237   case X86::VMINCPDYrr:
7238   case X86::VMINCPSYrr:
7239   case X86::VMINCSDrr:
7240   case X86::VMINCSSrr:
7241     return true;
7242   case X86::ADDPDrr:
7243   case X86::ADDPSrr:
7244   case X86::ADDSDrr:
7245   case X86::ADDSSrr:
7246   case X86::MULPDrr:
7247   case X86::MULPSrr:
7248   case X86::MULSDrr:
7249   case X86::MULSSrr:
7250   case X86::VADDPDrr:
7251   case X86::VADDPSrr:
7252   case X86::VADDPDYrr:
7253   case X86::VADDPSYrr:
7254   case X86::VADDSDrr:
7255   case X86::VADDSSrr:
7256   case X86::VMULPDrr:
7257   case X86::VMULPSrr:
7258   case X86::VMULPDYrr:
7259   case X86::VMULPSYrr:
7260   case X86::VMULSDrr:
7261   case X86::VMULSSrr:
7262     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7263   default:
7264     return false;
7265   }
7266 }
7267 
7268 /// This is an architecture-specific helper function of reassociateOps.
7269 /// Set special operand attributes for new instructions after reassociation.
7270 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7271                                          MachineInstr &OldMI2,
7272                                          MachineInstr &NewMI1,
7273                                          MachineInstr &NewMI2) const {
7274   // Integer instructions define an implicit EFLAGS source register operand as
7275   // the third source (fourth total) operand.
7276   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7277     return;
7278 
7279   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7280          "Unexpected instruction type for reassociation");
7281 
7282   MachineOperand &OldOp1 = OldMI1.getOperand(3);
7283   MachineOperand &OldOp2 = OldMI2.getOperand(3);
7284   MachineOperand &NewOp1 = NewMI1.getOperand(3);
7285   MachineOperand &NewOp2 = NewMI2.getOperand(3);
7286 
7287   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7288          "Must have dead EFLAGS operand in reassociable instruction");
7289   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7290          "Must have dead EFLAGS operand in reassociable instruction");
7291 
7292   (void)OldOp1;
7293   (void)OldOp2;
7294 
7295   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7296          "Unexpected operand in reassociable instruction");
7297   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7298          "Unexpected operand in reassociable instruction");
7299 
7300   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7301   // of this pass or other passes. The EFLAGS operands must be dead in these new
7302   // instructions because the EFLAGS operands in the original instructions must
7303   // be dead in order for reassociation to occur.
7304   NewOp1.setIsDead();
7305   NewOp2.setIsDead();
7306 }
7307 
7308 std::pair<unsigned, unsigned>
7309 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7310   return std::make_pair(TF, 0u);
7311 }
7312 
7313 ArrayRef<std::pair<unsigned, const char *>>
7314 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7315   using namespace X86II;
7316   static const std::pair<unsigned, const char *> TargetFlags[] = {
7317       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7318       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7319       {MO_GOT, "x86-got"},
7320       {MO_GOTOFF, "x86-gotoff"},
7321       {MO_GOTPCREL, "x86-gotpcrel"},
7322       {MO_PLT, "x86-plt"},
7323       {MO_TLSGD, "x86-tlsgd"},
7324       {MO_TLSLD, "x86-tlsld"},
7325       {MO_TLSLDM, "x86-tlsldm"},
7326       {MO_GOTTPOFF, "x86-gottpoff"},
7327       {MO_INDNTPOFF, "x86-indntpoff"},
7328       {MO_TPOFF, "x86-tpoff"},
7329       {MO_DTPOFF, "x86-dtpoff"},
7330       {MO_NTPOFF, "x86-ntpoff"},
7331       {MO_GOTNTPOFF, "x86-gotntpoff"},
7332       {MO_DLLIMPORT, "x86-dllimport"},
7333       {MO_DARWIN_STUB, "x86-darwin-stub"},
7334       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7335       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7336       {MO_TLVP, "x86-tlvp"},
7337       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7338       {MO_SECREL, "x86-secrel"}};
7339   return makeArrayRef(TargetFlags);
7340 }
7341 
7342 namespace {
7343   /// Create Global Base Reg pass. This initializes the PIC
7344   /// global base register for x86-32.
7345   struct CGBR : public MachineFunctionPass {
7346     static char ID;
7347     CGBR() : MachineFunctionPass(ID) {}
7348 
7349     bool runOnMachineFunction(MachineFunction &MF) override {
7350       const X86TargetMachine *TM =
7351         static_cast<const X86TargetMachine *>(&MF.getTarget());
7352       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7353 
7354       // Don't do anything if this is 64-bit as 64-bit PIC
7355       // uses RIP relative addressing.
7356       if (STI.is64Bit())
7357         return false;
7358 
7359       // Only emit a global base reg in PIC mode.
7360       if (TM->getRelocationModel() != Reloc::PIC_)
7361         return false;
7362 
7363       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7364       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7365 
7366       // If we didn't need a GlobalBaseReg, don't insert code.
7367       if (GlobalBaseReg == 0)
7368         return false;
7369 
7370       // Insert the set of GlobalBaseReg into the first MBB of the function
7371       MachineBasicBlock &FirstMBB = MF.front();
7372       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7373       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7374       MachineRegisterInfo &RegInfo = MF.getRegInfo();
7375       const X86InstrInfo *TII = STI.getInstrInfo();
7376 
7377       unsigned PC;
7378       if (STI.isPICStyleGOT())
7379         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7380       else
7381         PC = GlobalBaseReg;
7382 
7383       // Operand of MovePCtoStack is completely ignored by asm printer. It's
7384       // only used in JIT code emission as displacement to pc.
7385       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7386 
7387       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
7388       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7389       if (STI.isPICStyleGOT()) {
7390         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
7391         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7392           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7393                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
7394       }
7395 
7396       return true;
7397     }
7398 
7399     const char *getPassName() const override {
7400       return "X86 PIC Global Base Reg Initialization";
7401     }
7402 
7403     void getAnalysisUsage(AnalysisUsage &AU) const override {
7404       AU.setPreservesCFG();
7405       MachineFunctionPass::getAnalysisUsage(AU);
7406     }
7407   };
7408 }
7409 
7410 char CGBR::ID = 0;
7411 FunctionPass*
7412 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
7413 
7414 namespace {
7415   struct LDTLSCleanup : public MachineFunctionPass {
7416     static char ID;
7417     LDTLSCleanup() : MachineFunctionPass(ID) {}
7418 
7419     bool runOnMachineFunction(MachineFunction &MF) override {
7420       if (skipFunction(*MF.getFunction()))
7421         return false;
7422 
7423       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
7424       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7425         // No point folding accesses if there isn't at least two.
7426         return false;
7427       }
7428 
7429       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7430       return VisitNode(DT->getRootNode(), 0);
7431     }
7432 
7433     // Visit the dominator subtree rooted at Node in pre-order.
7434     // If TLSBaseAddrReg is non-null, then use that to replace any
7435     // TLS_base_addr instructions. Otherwise, create the register
7436     // when the first such instruction is seen, and then use it
7437     // as we encounter more instructions.
7438     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7439       MachineBasicBlock *BB = Node->getBlock();
7440       bool Changed = false;
7441 
7442       // Traverse the current block.
7443       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7444            ++I) {
7445         switch (I->getOpcode()) {
7446           case X86::TLS_base_addr32:
7447           case X86::TLS_base_addr64:
7448             if (TLSBaseAddrReg)
7449               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
7450             else
7451               I = SetRegister(I, &TLSBaseAddrReg);
7452             Changed = true;
7453             break;
7454           default:
7455             break;
7456         }
7457       }
7458 
7459       // Visit the children of this block in the dominator tree.
7460       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7461            I != E; ++I) {
7462         Changed |= VisitNode(*I, TLSBaseAddrReg);
7463       }
7464 
7465       return Changed;
7466     }
7467 
7468     // Replace the TLS_base_addr instruction I with a copy from
7469     // TLSBaseAddrReg, returning the new instruction.
7470     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
7471                                          unsigned TLSBaseAddrReg) {
7472       MachineFunction *MF = I->getParent()->getParent();
7473       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7474       const bool is64Bit = STI.is64Bit();
7475       const X86InstrInfo *TII = STI.getInstrInfo();
7476 
7477       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7478       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
7479                                    TII->get(TargetOpcode::COPY),
7480                                    is64Bit ? X86::RAX : X86::EAX)
7481                                    .addReg(TLSBaseAddrReg);
7482 
7483       // Erase the TLS_base_addr instruction.
7484       I->eraseFromParent();
7485 
7486       return Copy;
7487     }
7488 
7489     // Create a virtal register in *TLSBaseAddrReg, and populate it by
7490     // inserting a copy instruction after I. Returns the new instruction.
7491     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
7492       MachineFunction *MF = I->getParent()->getParent();
7493       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7494       const bool is64Bit = STI.is64Bit();
7495       const X86InstrInfo *TII = STI.getInstrInfo();
7496 
7497       // Create a virtual register for the TLS base address.
7498       MachineRegisterInfo &RegInfo = MF->getRegInfo();
7499       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7500                                                       ? &X86::GR64RegClass
7501                                                       : &X86::GR32RegClass);
7502 
7503       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7504       MachineInstr *Next = I->getNextNode();
7505       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
7506                                    TII->get(TargetOpcode::COPY),
7507                                    *TLSBaseAddrReg)
7508                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
7509 
7510       return Copy;
7511     }
7512 
7513     const char *getPassName() const override {
7514       return "Local Dynamic TLS Access Clean-up";
7515     }
7516 
7517     void getAnalysisUsage(AnalysisUsage &AU) const override {
7518       AU.setPreservesCFG();
7519       AU.addRequired<MachineDominatorTree>();
7520       MachineFunctionPass::getAnalysisUsage(AU);
7521     }
7522   };
7523 }
7524 
7525 char LDTLSCleanup::ID = 0;
7526 FunctionPass*
7527 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
7528