1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LivePhysRegs.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DebugInfoMetadata.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "x86-instr-info"
46 
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "X86GenInstrInfo.inc"
49 
50 static cl::opt<bool>
51     NoFusing("disable-spill-fusing",
52              cl::desc("Disable fusing of spill code into instructions"),
53              cl::Hidden);
54 static cl::opt<bool>
55 PrintFailedFusing("print-failed-fuse-candidates",
56                   cl::desc("Print instructions that the allocator wants to"
57                            " fuse, but the X86 backend currently can't"),
58                   cl::Hidden);
59 static cl::opt<bool>
60 ReMatPICStubLoad("remat-pic-stub-load",
61                  cl::desc("Re-materialize load from stub in PIC mode"),
62                  cl::init(false), cl::Hidden);
63 static cl::opt<unsigned>
64 PartialRegUpdateClearance("partial-reg-update-clearance",
65                           cl::desc("Clearance between two register writes "
66                                    "for inserting XOR to avoid partial "
67                                    "register update"),
68                           cl::init(64), cl::Hidden);
69 static cl::opt<unsigned>
70 UndefRegClearance("undef-reg-clearance",
71                   cl::desc("How many idle instructions we would like before "
72                            "certain undef register reads"),
73                   cl::init(128), cl::Hidden);
74 
75 
76 // Pin the vtable to this file.
77 void X86InstrInfo::anchor() {}
78 
79 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81                                                : X86::ADJCALLSTACKDOWN32),
82                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83                                                : X86::ADJCALLSTACKUP32),
84                       X86::CATCHRET,
85                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86       Subtarget(STI), RI(STI.getTargetTriple()) {
87 }
88 
89 bool
90 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91                                     Register &SrcReg, Register &DstReg,
92                                     unsigned &SubIdx) const {
93   switch (MI.getOpcode()) {
94   default: break;
95   case X86::MOVSX16rr8:
96   case X86::MOVZX16rr8:
97   case X86::MOVSX32rr8:
98   case X86::MOVZX32rr8:
99   case X86::MOVSX64rr8:
100     if (!Subtarget.is64Bit())
101       // It's not always legal to reference the low 8-bit of the larger
102       // register in 32-bit mode.
103       return false;
104     LLVM_FALLTHROUGH;
105   case X86::MOVSX32rr16:
106   case X86::MOVZX32rr16:
107   case X86::MOVSX64rr16:
108   case X86::MOVSX64rr32: {
109     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110       // Be conservative.
111       return false;
112     SrcReg = MI.getOperand(1).getReg();
113     DstReg = MI.getOperand(0).getReg();
114     switch (MI.getOpcode()) {
115     default: llvm_unreachable("Unreachable!");
116     case X86::MOVSX16rr8:
117     case X86::MOVZX16rr8:
118     case X86::MOVSX32rr8:
119     case X86::MOVZX32rr8:
120     case X86::MOVSX64rr8:
121       SubIdx = X86::sub_8bit;
122       break;
123     case X86::MOVSX32rr16:
124     case X86::MOVZX32rr16:
125     case X86::MOVSX64rr16:
126       SubIdx = X86::sub_16bit;
127       break;
128     case X86::MOVSX64rr32:
129       SubIdx = X86::sub_32bit;
130       break;
131     }
132     return true;
133   }
134   }
135   return false;
136 }
137 
138 bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
139   switch (MI.getOpcode()) {
140   default:
141     // By default, assume that the instruction is not data invariant.
142     return false;
143 
144     // Some target-independent operations that trivially lower to data-invariant
145     // instructions.
146   case TargetOpcode::COPY:
147   case TargetOpcode::INSERT_SUBREG:
148   case TargetOpcode::SUBREG_TO_REG:
149     return true;
150 
151   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
152   // However, they set flags and are perhaps the most surprisingly constant
153   // time operations so we call them out here separately.
154   case X86::IMUL16rr:
155   case X86::IMUL16rri8:
156   case X86::IMUL16rri:
157   case X86::IMUL32rr:
158   case X86::IMUL32rri8:
159   case X86::IMUL32rri:
160   case X86::IMUL64rr:
161   case X86::IMUL64rri32:
162   case X86::IMUL64rri8:
163 
164   // Bit scanning and counting instructions that are somewhat surprisingly
165   // constant time as they scan across bits and do other fairly complex
166   // operations like popcnt, but are believed to be constant time on x86.
167   // However, these set flags.
168   case X86::BSF16rr:
169   case X86::BSF32rr:
170   case X86::BSF64rr:
171   case X86::BSR16rr:
172   case X86::BSR32rr:
173   case X86::BSR64rr:
174   case X86::LZCNT16rr:
175   case X86::LZCNT32rr:
176   case X86::LZCNT64rr:
177   case X86::POPCNT16rr:
178   case X86::POPCNT32rr:
179   case X86::POPCNT64rr:
180   case X86::TZCNT16rr:
181   case X86::TZCNT32rr:
182   case X86::TZCNT64rr:
183 
184   // Bit manipulation instructions are effectively combinations of basic
185   // arithmetic ops, and should still execute in constant time. These also
186   // set flags.
187   case X86::BLCFILL32rr:
188   case X86::BLCFILL64rr:
189   case X86::BLCI32rr:
190   case X86::BLCI64rr:
191   case X86::BLCIC32rr:
192   case X86::BLCIC64rr:
193   case X86::BLCMSK32rr:
194   case X86::BLCMSK64rr:
195   case X86::BLCS32rr:
196   case X86::BLCS64rr:
197   case X86::BLSFILL32rr:
198   case X86::BLSFILL64rr:
199   case X86::BLSI32rr:
200   case X86::BLSI64rr:
201   case X86::BLSIC32rr:
202   case X86::BLSIC64rr:
203   case X86::BLSMSK32rr:
204   case X86::BLSMSK64rr:
205   case X86::BLSR32rr:
206   case X86::BLSR64rr:
207   case X86::TZMSK32rr:
208   case X86::TZMSK64rr:
209 
210   // Bit extracting and clearing instructions should execute in constant time,
211   // and set flags.
212   case X86::BEXTR32rr:
213   case X86::BEXTR64rr:
214   case X86::BEXTRI32ri:
215   case X86::BEXTRI64ri:
216   case X86::BZHI32rr:
217   case X86::BZHI64rr:
218 
219   // Shift and rotate.
220   case X86::ROL8r1:
221   case X86::ROL16r1:
222   case X86::ROL32r1:
223   case X86::ROL64r1:
224   case X86::ROL8rCL:
225   case X86::ROL16rCL:
226   case X86::ROL32rCL:
227   case X86::ROL64rCL:
228   case X86::ROL8ri:
229   case X86::ROL16ri:
230   case X86::ROL32ri:
231   case X86::ROL64ri:
232   case X86::ROR8r1:
233   case X86::ROR16r1:
234   case X86::ROR32r1:
235   case X86::ROR64r1:
236   case X86::ROR8rCL:
237   case X86::ROR16rCL:
238   case X86::ROR32rCL:
239   case X86::ROR64rCL:
240   case X86::ROR8ri:
241   case X86::ROR16ri:
242   case X86::ROR32ri:
243   case X86::ROR64ri:
244   case X86::SAR8r1:
245   case X86::SAR16r1:
246   case X86::SAR32r1:
247   case X86::SAR64r1:
248   case X86::SAR8rCL:
249   case X86::SAR16rCL:
250   case X86::SAR32rCL:
251   case X86::SAR64rCL:
252   case X86::SAR8ri:
253   case X86::SAR16ri:
254   case X86::SAR32ri:
255   case X86::SAR64ri:
256   case X86::SHL8r1:
257   case X86::SHL16r1:
258   case X86::SHL32r1:
259   case X86::SHL64r1:
260   case X86::SHL8rCL:
261   case X86::SHL16rCL:
262   case X86::SHL32rCL:
263   case X86::SHL64rCL:
264   case X86::SHL8ri:
265   case X86::SHL16ri:
266   case X86::SHL32ri:
267   case X86::SHL64ri:
268   case X86::SHR8r1:
269   case X86::SHR16r1:
270   case X86::SHR32r1:
271   case X86::SHR64r1:
272   case X86::SHR8rCL:
273   case X86::SHR16rCL:
274   case X86::SHR32rCL:
275   case X86::SHR64rCL:
276   case X86::SHR8ri:
277   case X86::SHR16ri:
278   case X86::SHR32ri:
279   case X86::SHR64ri:
280   case X86::SHLD16rrCL:
281   case X86::SHLD32rrCL:
282   case X86::SHLD64rrCL:
283   case X86::SHLD16rri8:
284   case X86::SHLD32rri8:
285   case X86::SHLD64rri8:
286   case X86::SHRD16rrCL:
287   case X86::SHRD32rrCL:
288   case X86::SHRD64rrCL:
289   case X86::SHRD16rri8:
290   case X86::SHRD32rri8:
291   case X86::SHRD64rri8:
292 
293   // Basic arithmetic is constant time on the input but does set flags.
294   case X86::ADC8rr:
295   case X86::ADC8ri:
296   case X86::ADC16rr:
297   case X86::ADC16ri:
298   case X86::ADC16ri8:
299   case X86::ADC32rr:
300   case X86::ADC32ri:
301   case X86::ADC32ri8:
302   case X86::ADC64rr:
303   case X86::ADC64ri8:
304   case X86::ADC64ri32:
305   case X86::ADD8rr:
306   case X86::ADD8ri:
307   case X86::ADD16rr:
308   case X86::ADD16ri:
309   case X86::ADD16ri8:
310   case X86::ADD32rr:
311   case X86::ADD32ri:
312   case X86::ADD32ri8:
313   case X86::ADD64rr:
314   case X86::ADD64ri8:
315   case X86::ADD64ri32:
316   case X86::AND8rr:
317   case X86::AND8ri:
318   case X86::AND16rr:
319   case X86::AND16ri:
320   case X86::AND16ri8:
321   case X86::AND32rr:
322   case X86::AND32ri:
323   case X86::AND32ri8:
324   case X86::AND64rr:
325   case X86::AND64ri8:
326   case X86::AND64ri32:
327   case X86::OR8rr:
328   case X86::OR8ri:
329   case X86::OR16rr:
330   case X86::OR16ri:
331   case X86::OR16ri8:
332   case X86::OR32rr:
333   case X86::OR32ri:
334   case X86::OR32ri8:
335   case X86::OR64rr:
336   case X86::OR64ri8:
337   case X86::OR64ri32:
338   case X86::SBB8rr:
339   case X86::SBB8ri:
340   case X86::SBB16rr:
341   case X86::SBB16ri:
342   case X86::SBB16ri8:
343   case X86::SBB32rr:
344   case X86::SBB32ri:
345   case X86::SBB32ri8:
346   case X86::SBB64rr:
347   case X86::SBB64ri8:
348   case X86::SBB64ri32:
349   case X86::SUB8rr:
350   case X86::SUB8ri:
351   case X86::SUB16rr:
352   case X86::SUB16ri:
353   case X86::SUB16ri8:
354   case X86::SUB32rr:
355   case X86::SUB32ri:
356   case X86::SUB32ri8:
357   case X86::SUB64rr:
358   case X86::SUB64ri8:
359   case X86::SUB64ri32:
360   case X86::XOR8rr:
361   case X86::XOR8ri:
362   case X86::XOR16rr:
363   case X86::XOR16ri:
364   case X86::XOR16ri8:
365   case X86::XOR32rr:
366   case X86::XOR32ri:
367   case X86::XOR32ri8:
368   case X86::XOR64rr:
369   case X86::XOR64ri8:
370   case X86::XOR64ri32:
371   // Arithmetic with just 32-bit and 64-bit variants and no immediates.
372   case X86::ADCX32rr:
373   case X86::ADCX64rr:
374   case X86::ADOX32rr:
375   case X86::ADOX64rr:
376   case X86::ANDN32rr:
377   case X86::ANDN64rr:
378   // Unary arithmetic operations.
379   case X86::DEC8r:
380   case X86::DEC16r:
381   case X86::DEC32r:
382   case X86::DEC64r:
383   case X86::INC8r:
384   case X86::INC16r:
385   case X86::INC32r:
386   case X86::INC64r:
387   case X86::NEG8r:
388   case X86::NEG16r:
389   case X86::NEG32r:
390   case X86::NEG64r:
391 
392   // Unlike other arithmetic, NOT doesn't set EFLAGS.
393   case X86::NOT8r:
394   case X86::NOT16r:
395   case X86::NOT32r:
396   case X86::NOT64r:
397 
398   // Various move instructions used to zero or sign extend things. Note that we
399   // intentionally don't support the _NOREX variants as we can't handle that
400   // register constraint anyways.
401   case X86::MOVSX16rr8:
402   case X86::MOVSX32rr8:
403   case X86::MOVSX32rr16:
404   case X86::MOVSX64rr8:
405   case X86::MOVSX64rr16:
406   case X86::MOVSX64rr32:
407   case X86::MOVZX16rr8:
408   case X86::MOVZX32rr8:
409   case X86::MOVZX32rr16:
410   case X86::MOVZX64rr8:
411   case X86::MOVZX64rr16:
412   case X86::MOV32rr:
413 
414   // Arithmetic instructions that are both constant time and don't set flags.
415   case X86::RORX32ri:
416   case X86::RORX64ri:
417   case X86::SARX32rr:
418   case X86::SARX64rr:
419   case X86::SHLX32rr:
420   case X86::SHLX64rr:
421   case X86::SHRX32rr:
422   case X86::SHRX64rr:
423 
424   // LEA doesn't actually access memory, and its arithmetic is constant time.
425   case X86::LEA16r:
426   case X86::LEA32r:
427   case X86::LEA64_32r:
428   case X86::LEA64r:
429     return true;
430   }
431 }
432 
433 bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
434   switch (MI.getOpcode()) {
435   default:
436     // By default, assume that the load will immediately leak.
437     return false;
438 
439   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
440   // However, they set flags and are perhaps the most surprisingly constant
441   // time operations so we call them out here separately.
442   case X86::IMUL16rm:
443   case X86::IMUL16rmi8:
444   case X86::IMUL16rmi:
445   case X86::IMUL32rm:
446   case X86::IMUL32rmi8:
447   case X86::IMUL32rmi:
448   case X86::IMUL64rm:
449   case X86::IMUL64rmi32:
450   case X86::IMUL64rmi8:
451 
452   // Bit scanning and counting instructions that are somewhat surprisingly
453   // constant time as they scan across bits and do other fairly complex
454   // operations like popcnt, but are believed to be constant time on x86.
455   // However, these set flags.
456   case X86::BSF16rm:
457   case X86::BSF32rm:
458   case X86::BSF64rm:
459   case X86::BSR16rm:
460   case X86::BSR32rm:
461   case X86::BSR64rm:
462   case X86::LZCNT16rm:
463   case X86::LZCNT32rm:
464   case X86::LZCNT64rm:
465   case X86::POPCNT16rm:
466   case X86::POPCNT32rm:
467   case X86::POPCNT64rm:
468   case X86::TZCNT16rm:
469   case X86::TZCNT32rm:
470   case X86::TZCNT64rm:
471 
472   // Bit manipulation instructions are effectively combinations of basic
473   // arithmetic ops, and should still execute in constant time. These also
474   // set flags.
475   case X86::BLCFILL32rm:
476   case X86::BLCFILL64rm:
477   case X86::BLCI32rm:
478   case X86::BLCI64rm:
479   case X86::BLCIC32rm:
480   case X86::BLCIC64rm:
481   case X86::BLCMSK32rm:
482   case X86::BLCMSK64rm:
483   case X86::BLCS32rm:
484   case X86::BLCS64rm:
485   case X86::BLSFILL32rm:
486   case X86::BLSFILL64rm:
487   case X86::BLSI32rm:
488   case X86::BLSI64rm:
489   case X86::BLSIC32rm:
490   case X86::BLSIC64rm:
491   case X86::BLSMSK32rm:
492   case X86::BLSMSK64rm:
493   case X86::BLSR32rm:
494   case X86::BLSR64rm:
495   case X86::TZMSK32rm:
496   case X86::TZMSK64rm:
497 
498   // Bit extracting and clearing instructions should execute in constant time,
499   // and set flags.
500   case X86::BEXTR32rm:
501   case X86::BEXTR64rm:
502   case X86::BEXTRI32mi:
503   case X86::BEXTRI64mi:
504   case X86::BZHI32rm:
505   case X86::BZHI64rm:
506 
507   // Basic arithmetic is constant time on the input but does set flags.
508   case X86::ADC8rm:
509   case X86::ADC16rm:
510   case X86::ADC32rm:
511   case X86::ADC64rm:
512   case X86::ADCX32rm:
513   case X86::ADCX64rm:
514   case X86::ADD8rm:
515   case X86::ADD16rm:
516   case X86::ADD32rm:
517   case X86::ADD64rm:
518   case X86::ADOX32rm:
519   case X86::ADOX64rm:
520   case X86::AND8rm:
521   case X86::AND16rm:
522   case X86::AND32rm:
523   case X86::AND64rm:
524   case X86::ANDN32rm:
525   case X86::ANDN64rm:
526   case X86::OR8rm:
527   case X86::OR16rm:
528   case X86::OR32rm:
529   case X86::OR64rm:
530   case X86::SBB8rm:
531   case X86::SBB16rm:
532   case X86::SBB32rm:
533   case X86::SBB64rm:
534   case X86::SUB8rm:
535   case X86::SUB16rm:
536   case X86::SUB32rm:
537   case X86::SUB64rm:
538   case X86::XOR8rm:
539   case X86::XOR16rm:
540   case X86::XOR32rm:
541   case X86::XOR64rm:
542 
543   // Integer multiply w/o affecting flags is still believed to be constant
544   // time on x86. Called out separately as this is among the most surprising
545   // instructions to exhibit that behavior.
546   case X86::MULX32rm:
547   case X86::MULX64rm:
548 
549   // Arithmetic instructions that are both constant time and don't set flags.
550   case X86::RORX32mi:
551   case X86::RORX64mi:
552   case X86::SARX32rm:
553   case X86::SARX64rm:
554   case X86::SHLX32rm:
555   case X86::SHLX64rm:
556   case X86::SHRX32rm:
557   case X86::SHRX64rm:
558 
559   // Conversions are believed to be constant time and don't set flags.
560   case X86::CVTTSD2SI64rm:
561   case X86::VCVTTSD2SI64rm:
562   case X86::VCVTTSD2SI64Zrm:
563   case X86::CVTTSD2SIrm:
564   case X86::VCVTTSD2SIrm:
565   case X86::VCVTTSD2SIZrm:
566   case X86::CVTTSS2SI64rm:
567   case X86::VCVTTSS2SI64rm:
568   case X86::VCVTTSS2SI64Zrm:
569   case X86::CVTTSS2SIrm:
570   case X86::VCVTTSS2SIrm:
571   case X86::VCVTTSS2SIZrm:
572   case X86::CVTSI2SDrm:
573   case X86::VCVTSI2SDrm:
574   case X86::VCVTSI2SDZrm:
575   case X86::CVTSI2SSrm:
576   case X86::VCVTSI2SSrm:
577   case X86::VCVTSI2SSZrm:
578   case X86::CVTSI642SDrm:
579   case X86::VCVTSI642SDrm:
580   case X86::VCVTSI642SDZrm:
581   case X86::CVTSI642SSrm:
582   case X86::VCVTSI642SSrm:
583   case X86::VCVTSI642SSZrm:
584   case X86::CVTSS2SDrm:
585   case X86::VCVTSS2SDrm:
586   case X86::VCVTSS2SDZrm:
587   case X86::CVTSD2SSrm:
588   case X86::VCVTSD2SSrm:
589   case X86::VCVTSD2SSZrm:
590   // AVX512 added unsigned integer conversions.
591   case X86::VCVTTSD2USI64Zrm:
592   case X86::VCVTTSD2USIZrm:
593   case X86::VCVTTSS2USI64Zrm:
594   case X86::VCVTTSS2USIZrm:
595   case X86::VCVTUSI2SDZrm:
596   case X86::VCVTUSI642SDZrm:
597   case X86::VCVTUSI2SSZrm:
598   case X86::VCVTUSI642SSZrm:
599 
600   // Loads to register don't set flags.
601   case X86::MOV8rm:
602   case X86::MOV8rm_NOREX:
603   case X86::MOV16rm:
604   case X86::MOV32rm:
605   case X86::MOV64rm:
606   case X86::MOVSX16rm8:
607   case X86::MOVSX32rm16:
608   case X86::MOVSX32rm8:
609   case X86::MOVSX32rm8_NOREX:
610   case X86::MOVSX64rm16:
611   case X86::MOVSX64rm32:
612   case X86::MOVSX64rm8:
613   case X86::MOVZX16rm8:
614   case X86::MOVZX32rm16:
615   case X86::MOVZX32rm8:
616   case X86::MOVZX32rm8_NOREX:
617   case X86::MOVZX64rm16:
618   case X86::MOVZX64rm8:
619     return true;
620   }
621 }
622 
623 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
624   const MachineFunction *MF = MI.getParent()->getParent();
625   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
626 
627   if (isFrameInstr(MI)) {
628     int SPAdj = alignTo(getFrameSize(MI), TFI->getStackAlign());
629     SPAdj -= getFrameAdjustment(MI);
630     if (!isFrameSetup(MI))
631       SPAdj = -SPAdj;
632     return SPAdj;
633   }
634 
635   // To know whether a call adjusts the stack, we need information
636   // that is bound to the following ADJCALLSTACKUP pseudo.
637   // Look for the next ADJCALLSTACKUP that follows the call.
638   if (MI.isCall()) {
639     const MachineBasicBlock *MBB = MI.getParent();
640     auto I = ++MachineBasicBlock::const_iterator(MI);
641     for (auto E = MBB->end(); I != E; ++I) {
642       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
643           I->isCall())
644         break;
645     }
646 
647     // If we could not find a frame destroy opcode, then it has already
648     // been simplified, so we don't care.
649     if (I->getOpcode() != getCallFrameDestroyOpcode())
650       return 0;
651 
652     return -(I->getOperand(1).getImm());
653   }
654 
655   // Currently handle only PUSHes we can reasonably expect to see
656   // in call sequences
657   switch (MI.getOpcode()) {
658   default:
659     return 0;
660   case X86::PUSH32i8:
661   case X86::PUSH32r:
662   case X86::PUSH32rmm:
663   case X86::PUSH32rmr:
664   case X86::PUSHi32:
665     return 4;
666   case X86::PUSH64i8:
667   case X86::PUSH64r:
668   case X86::PUSH64rmm:
669   case X86::PUSH64rmr:
670   case X86::PUSH64i32:
671     return 8;
672   }
673 }
674 
675 /// Return true and the FrameIndex if the specified
676 /// operand and follow operands form a reference to the stack frame.
677 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
678                                   int &FrameIndex) const {
679   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
680       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
681       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
682       MI.getOperand(Op + X86::AddrDisp).isImm() &&
683       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
684       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
685       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
686     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
687     return true;
688   }
689   return false;
690 }
691 
692 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
693   switch (Opcode) {
694   default:
695     return false;
696   case X86::MOV8rm:
697   case X86::KMOVBkm:
698     MemBytes = 1;
699     return true;
700   case X86::MOV16rm:
701   case X86::KMOVWkm:
702   case X86::VMOVSHZrm:
703   case X86::VMOVSHZrm_alt:
704     MemBytes = 2;
705     return true;
706   case X86::MOV32rm:
707   case X86::MOVSSrm:
708   case X86::MOVSSrm_alt:
709   case X86::VMOVSSrm:
710   case X86::VMOVSSrm_alt:
711   case X86::VMOVSSZrm:
712   case X86::VMOVSSZrm_alt:
713   case X86::KMOVDkm:
714     MemBytes = 4;
715     return true;
716   case X86::MOV64rm:
717   case X86::LD_Fp64m:
718   case X86::MOVSDrm:
719   case X86::MOVSDrm_alt:
720   case X86::VMOVSDrm:
721   case X86::VMOVSDrm_alt:
722   case X86::VMOVSDZrm:
723   case X86::VMOVSDZrm_alt:
724   case X86::MMX_MOVD64rm:
725   case X86::MMX_MOVQ64rm:
726   case X86::KMOVQkm:
727     MemBytes = 8;
728     return true;
729   case X86::MOVAPSrm:
730   case X86::MOVUPSrm:
731   case X86::MOVAPDrm:
732   case X86::MOVUPDrm:
733   case X86::MOVDQArm:
734   case X86::MOVDQUrm:
735   case X86::VMOVAPSrm:
736   case X86::VMOVUPSrm:
737   case X86::VMOVAPDrm:
738   case X86::VMOVUPDrm:
739   case X86::VMOVDQArm:
740   case X86::VMOVDQUrm:
741   case X86::VMOVAPSZ128rm:
742   case X86::VMOVUPSZ128rm:
743   case X86::VMOVAPSZ128rm_NOVLX:
744   case X86::VMOVUPSZ128rm_NOVLX:
745   case X86::VMOVAPDZ128rm:
746   case X86::VMOVUPDZ128rm:
747   case X86::VMOVDQU8Z128rm:
748   case X86::VMOVDQU16Z128rm:
749   case X86::VMOVDQA32Z128rm:
750   case X86::VMOVDQU32Z128rm:
751   case X86::VMOVDQA64Z128rm:
752   case X86::VMOVDQU64Z128rm:
753     MemBytes = 16;
754     return true;
755   case X86::VMOVAPSYrm:
756   case X86::VMOVUPSYrm:
757   case X86::VMOVAPDYrm:
758   case X86::VMOVUPDYrm:
759   case X86::VMOVDQAYrm:
760   case X86::VMOVDQUYrm:
761   case X86::VMOVAPSZ256rm:
762   case X86::VMOVUPSZ256rm:
763   case X86::VMOVAPSZ256rm_NOVLX:
764   case X86::VMOVUPSZ256rm_NOVLX:
765   case X86::VMOVAPDZ256rm:
766   case X86::VMOVUPDZ256rm:
767   case X86::VMOVDQU8Z256rm:
768   case X86::VMOVDQU16Z256rm:
769   case X86::VMOVDQA32Z256rm:
770   case X86::VMOVDQU32Z256rm:
771   case X86::VMOVDQA64Z256rm:
772   case X86::VMOVDQU64Z256rm:
773     MemBytes = 32;
774     return true;
775   case X86::VMOVAPSZrm:
776   case X86::VMOVUPSZrm:
777   case X86::VMOVAPDZrm:
778   case X86::VMOVUPDZrm:
779   case X86::VMOVDQU8Zrm:
780   case X86::VMOVDQU16Zrm:
781   case X86::VMOVDQA32Zrm:
782   case X86::VMOVDQU32Zrm:
783   case X86::VMOVDQA64Zrm:
784   case X86::VMOVDQU64Zrm:
785     MemBytes = 64;
786     return true;
787   }
788 }
789 
790 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
791   switch (Opcode) {
792   default:
793     return false;
794   case X86::MOV8mr:
795   case X86::KMOVBmk:
796     MemBytes = 1;
797     return true;
798   case X86::MOV16mr:
799   case X86::KMOVWmk:
800   case X86::VMOVSHZmr:
801     MemBytes = 2;
802     return true;
803   case X86::MOV32mr:
804   case X86::MOVSSmr:
805   case X86::VMOVSSmr:
806   case X86::VMOVSSZmr:
807   case X86::KMOVDmk:
808     MemBytes = 4;
809     return true;
810   case X86::MOV64mr:
811   case X86::ST_FpP64m:
812   case X86::MOVSDmr:
813   case X86::VMOVSDmr:
814   case X86::VMOVSDZmr:
815   case X86::MMX_MOVD64mr:
816   case X86::MMX_MOVQ64mr:
817   case X86::MMX_MOVNTQmr:
818   case X86::KMOVQmk:
819     MemBytes = 8;
820     return true;
821   case X86::MOVAPSmr:
822   case X86::MOVUPSmr:
823   case X86::MOVAPDmr:
824   case X86::MOVUPDmr:
825   case X86::MOVDQAmr:
826   case X86::MOVDQUmr:
827   case X86::VMOVAPSmr:
828   case X86::VMOVUPSmr:
829   case X86::VMOVAPDmr:
830   case X86::VMOVUPDmr:
831   case X86::VMOVDQAmr:
832   case X86::VMOVDQUmr:
833   case X86::VMOVUPSZ128mr:
834   case X86::VMOVAPSZ128mr:
835   case X86::VMOVUPSZ128mr_NOVLX:
836   case X86::VMOVAPSZ128mr_NOVLX:
837   case X86::VMOVUPDZ128mr:
838   case X86::VMOVAPDZ128mr:
839   case X86::VMOVDQA32Z128mr:
840   case X86::VMOVDQU32Z128mr:
841   case X86::VMOVDQA64Z128mr:
842   case X86::VMOVDQU64Z128mr:
843   case X86::VMOVDQU8Z128mr:
844   case X86::VMOVDQU16Z128mr:
845     MemBytes = 16;
846     return true;
847   case X86::VMOVUPSYmr:
848   case X86::VMOVAPSYmr:
849   case X86::VMOVUPDYmr:
850   case X86::VMOVAPDYmr:
851   case X86::VMOVDQUYmr:
852   case X86::VMOVDQAYmr:
853   case X86::VMOVUPSZ256mr:
854   case X86::VMOVAPSZ256mr:
855   case X86::VMOVUPSZ256mr_NOVLX:
856   case X86::VMOVAPSZ256mr_NOVLX:
857   case X86::VMOVUPDZ256mr:
858   case X86::VMOVAPDZ256mr:
859   case X86::VMOVDQU8Z256mr:
860   case X86::VMOVDQU16Z256mr:
861   case X86::VMOVDQA32Z256mr:
862   case X86::VMOVDQU32Z256mr:
863   case X86::VMOVDQA64Z256mr:
864   case X86::VMOVDQU64Z256mr:
865     MemBytes = 32;
866     return true;
867   case X86::VMOVUPSZmr:
868   case X86::VMOVAPSZmr:
869   case X86::VMOVUPDZmr:
870   case X86::VMOVAPDZmr:
871   case X86::VMOVDQU8Zmr:
872   case X86::VMOVDQU16Zmr:
873   case X86::VMOVDQA32Zmr:
874   case X86::VMOVDQU32Zmr:
875   case X86::VMOVDQA64Zmr:
876   case X86::VMOVDQU64Zmr:
877     MemBytes = 64;
878     return true;
879   }
880   return false;
881 }
882 
883 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
884                                            int &FrameIndex) const {
885   unsigned Dummy;
886   return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
887 }
888 
889 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
890                                            int &FrameIndex,
891                                            unsigned &MemBytes) const {
892   if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
893     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
894       return MI.getOperand(0).getReg();
895   return 0;
896 }
897 
898 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
899                                                  int &FrameIndex) const {
900   unsigned Dummy;
901   if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
902     unsigned Reg;
903     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
904       return Reg;
905     // Check for post-frame index elimination operations
906     SmallVector<const MachineMemOperand *, 1> Accesses;
907     if (hasLoadFromStackSlot(MI, Accesses)) {
908       FrameIndex =
909           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
910               ->getFrameIndex();
911       return MI.getOperand(0).getReg();
912     }
913   }
914   return 0;
915 }
916 
917 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
918                                           int &FrameIndex) const {
919   unsigned Dummy;
920   return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
921 }
922 
923 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
924                                           int &FrameIndex,
925                                           unsigned &MemBytes) const {
926   if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
927     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
928         isFrameOperand(MI, 0, FrameIndex))
929       return MI.getOperand(X86::AddrNumOperands).getReg();
930   return 0;
931 }
932 
933 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
934                                                 int &FrameIndex) const {
935   unsigned Dummy;
936   if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
937     unsigned Reg;
938     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
939       return Reg;
940     // Check for post-frame index elimination operations
941     SmallVector<const MachineMemOperand *, 1> Accesses;
942     if (hasStoreToStackSlot(MI, Accesses)) {
943       FrameIndex =
944           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
945               ->getFrameIndex();
946       return MI.getOperand(X86::AddrNumOperands).getReg();
947     }
948   }
949   return 0;
950 }
951 
952 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
953 static bool regIsPICBase(Register BaseReg, const MachineRegisterInfo &MRI) {
954   // Don't waste compile time scanning use-def chains of physregs.
955   if (!BaseReg.isVirtual())
956     return false;
957   bool isPICBase = false;
958   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
959          E = MRI.def_instr_end(); I != E; ++I) {
960     MachineInstr *DefMI = &*I;
961     if (DefMI->getOpcode() != X86::MOVPC32r)
962       return false;
963     assert(!isPICBase && "More than one PIC base?");
964     isPICBase = true;
965   }
966   return isPICBase;
967 }
968 
969 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
970                                                      AAResults *AA) const {
971   switch (MI.getOpcode()) {
972   default:
973     // This function should only be called for opcodes with the ReMaterializable
974     // flag set.
975     llvm_unreachable("Unknown rematerializable operation!");
976     break;
977 
978   case X86::LOAD_STACK_GUARD:
979   case X86::AVX1_SETALLONES:
980   case X86::AVX2_SETALLONES:
981   case X86::AVX512_128_SET0:
982   case X86::AVX512_256_SET0:
983   case X86::AVX512_512_SET0:
984   case X86::AVX512_512_SETALLONES:
985   case X86::AVX512_FsFLD0SD:
986   case X86::AVX512_FsFLD0SH:
987   case X86::AVX512_FsFLD0SS:
988   case X86::AVX512_FsFLD0F128:
989   case X86::AVX_SET0:
990   case X86::FsFLD0SD:
991   case X86::FsFLD0SS:
992   case X86::FsFLD0F128:
993   case X86::KSET0D:
994   case X86::KSET0Q:
995   case X86::KSET0W:
996   case X86::KSET1D:
997   case X86::KSET1Q:
998   case X86::KSET1W:
999   case X86::MMX_SET0:
1000   case X86::MOV32ImmSExti8:
1001   case X86::MOV32r0:
1002   case X86::MOV32r1:
1003   case X86::MOV32r_1:
1004   case X86::MOV32ri64:
1005   case X86::MOV64ImmSExti8:
1006   case X86::V_SET0:
1007   case X86::V_SETALLONES:
1008   case X86::MOV16ri:
1009   case X86::MOV32ri:
1010   case X86::MOV64ri:
1011   case X86::MOV64ri32:
1012   case X86::MOV8ri:
1013   case X86::PTILEZEROV:
1014     return true;
1015 
1016   case X86::MOV8rm:
1017   case X86::MOV8rm_NOREX:
1018   case X86::MOV16rm:
1019   case X86::MOV32rm:
1020   case X86::MOV64rm:
1021   case X86::MOVSSrm:
1022   case X86::MOVSSrm_alt:
1023   case X86::MOVSDrm:
1024   case X86::MOVSDrm_alt:
1025   case X86::MOVAPSrm:
1026   case X86::MOVUPSrm:
1027   case X86::MOVAPDrm:
1028   case X86::MOVUPDrm:
1029   case X86::MOVDQArm:
1030   case X86::MOVDQUrm:
1031   case X86::VMOVSSrm:
1032   case X86::VMOVSSrm_alt:
1033   case X86::VMOVSDrm:
1034   case X86::VMOVSDrm_alt:
1035   case X86::VMOVAPSrm:
1036   case X86::VMOVUPSrm:
1037   case X86::VMOVAPDrm:
1038   case X86::VMOVUPDrm:
1039   case X86::VMOVDQArm:
1040   case X86::VMOVDQUrm:
1041   case X86::VMOVAPSYrm:
1042   case X86::VMOVUPSYrm:
1043   case X86::VMOVAPDYrm:
1044   case X86::VMOVUPDYrm:
1045   case X86::VMOVDQAYrm:
1046   case X86::VMOVDQUYrm:
1047   case X86::MMX_MOVD64rm:
1048   case X86::MMX_MOVQ64rm:
1049   // AVX-512
1050   case X86::VMOVSSZrm:
1051   case X86::VMOVSSZrm_alt:
1052   case X86::VMOVSDZrm:
1053   case X86::VMOVSDZrm_alt:
1054   case X86::VMOVSHZrm:
1055   case X86::VMOVSHZrm_alt:
1056   case X86::VMOVAPDZ128rm:
1057   case X86::VMOVAPDZ256rm:
1058   case X86::VMOVAPDZrm:
1059   case X86::VMOVAPSZ128rm:
1060   case X86::VMOVAPSZ256rm:
1061   case X86::VMOVAPSZ128rm_NOVLX:
1062   case X86::VMOVAPSZ256rm_NOVLX:
1063   case X86::VMOVAPSZrm:
1064   case X86::VMOVDQA32Z128rm:
1065   case X86::VMOVDQA32Z256rm:
1066   case X86::VMOVDQA32Zrm:
1067   case X86::VMOVDQA64Z128rm:
1068   case X86::VMOVDQA64Z256rm:
1069   case X86::VMOVDQA64Zrm:
1070   case X86::VMOVDQU16Z128rm:
1071   case X86::VMOVDQU16Z256rm:
1072   case X86::VMOVDQU16Zrm:
1073   case X86::VMOVDQU32Z128rm:
1074   case X86::VMOVDQU32Z256rm:
1075   case X86::VMOVDQU32Zrm:
1076   case X86::VMOVDQU64Z128rm:
1077   case X86::VMOVDQU64Z256rm:
1078   case X86::VMOVDQU64Zrm:
1079   case X86::VMOVDQU8Z128rm:
1080   case X86::VMOVDQU8Z256rm:
1081   case X86::VMOVDQU8Zrm:
1082   case X86::VMOVUPDZ128rm:
1083   case X86::VMOVUPDZ256rm:
1084   case X86::VMOVUPDZrm:
1085   case X86::VMOVUPSZ128rm:
1086   case X86::VMOVUPSZ256rm:
1087   case X86::VMOVUPSZ128rm_NOVLX:
1088   case X86::VMOVUPSZ256rm_NOVLX:
1089   case X86::VMOVUPSZrm: {
1090     // Loads from constant pools are trivially rematerializable.
1091     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
1092         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1093         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1094         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1095         MI.isDereferenceableInvariantLoad(AA)) {
1096       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1097       if (BaseReg == 0 || BaseReg == X86::RIP)
1098         return true;
1099       // Allow re-materialization of PIC load.
1100       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
1101         return false;
1102       const MachineFunction &MF = *MI.getParent()->getParent();
1103       const MachineRegisterInfo &MRI = MF.getRegInfo();
1104       return regIsPICBase(BaseReg, MRI);
1105     }
1106     return false;
1107   }
1108 
1109   case X86::LEA32r:
1110   case X86::LEA64r: {
1111     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1112         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1113         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1114         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
1115       // lea fi#, lea GV, etc. are all rematerializable.
1116       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
1117         return true;
1118       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1119       if (BaseReg == 0)
1120         return true;
1121       // Allow re-materialization of lea PICBase + x.
1122       const MachineFunction &MF = *MI.getParent()->getParent();
1123       const MachineRegisterInfo &MRI = MF.getRegInfo();
1124       return regIsPICBase(BaseReg, MRI);
1125     }
1126     return false;
1127   }
1128   }
1129 }
1130 
1131 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1132                                  MachineBasicBlock::iterator I,
1133                                  Register DestReg, unsigned SubIdx,
1134                                  const MachineInstr &Orig,
1135                                  const TargetRegisterInfo &TRI) const {
1136   bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
1137   if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
1138                             MachineBasicBlock::LQR_Dead) {
1139     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
1140     // effects.
1141     int Value;
1142     switch (Orig.getOpcode()) {
1143     case X86::MOV32r0:  Value = 0; break;
1144     case X86::MOV32r1:  Value = 1; break;
1145     case X86::MOV32r_1: Value = -1; break;
1146     default:
1147       llvm_unreachable("Unexpected instruction!");
1148     }
1149 
1150     const DebugLoc &DL = Orig.getDebugLoc();
1151     BuildMI(MBB, I, DL, get(X86::MOV32ri))
1152         .add(Orig.getOperand(0))
1153         .addImm(Value);
1154   } else {
1155     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1156     MBB.insert(I, MI);
1157   }
1158 
1159   MachineInstr &NewMI = *std::prev(I);
1160   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1161 }
1162 
1163 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
1164 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
1165   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1166     MachineOperand &MO = MI.getOperand(i);
1167     if (MO.isReg() && MO.isDef() &&
1168         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1169       return true;
1170     }
1171   }
1172   return false;
1173 }
1174 
1175 /// Check whether the shift count for a machine operand is non-zero.
1176 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
1177                                               unsigned ShiftAmtOperandIdx) {
1178   // The shift count is six bits with the REX.W prefix and five bits without.
1179   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1180   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
1181   return Imm & ShiftCountMask;
1182 }
1183 
1184 /// Check whether the given shift count is appropriate
1185 /// can be represented by a LEA instruction.
1186 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1187   // Left shift instructions can be transformed into load-effective-address
1188   // instructions if we can encode them appropriately.
1189   // A LEA instruction utilizes a SIB byte to encode its scale factor.
1190   // The SIB.scale field is two bits wide which means that we can encode any
1191   // shift amount less than 4.
1192   return ShAmt < 4 && ShAmt > 0;
1193 }
1194 
1195 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
1196                                   unsigned Opc, bool AllowSP, Register &NewSrc,
1197                                   bool &isKill, MachineOperand &ImplicitOp,
1198                                   LiveVariables *LV) const {
1199   MachineFunction &MF = *MI.getParent()->getParent();
1200   const TargetRegisterClass *RC;
1201   if (AllowSP) {
1202     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1203   } else {
1204     RC = Opc != X86::LEA32r ?
1205       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1206   }
1207   Register SrcReg = Src.getReg();
1208 
1209   // For both LEA64 and LEA32 the register already has essentially the right
1210   // type (32-bit or 64-bit) we may just need to forbid SP.
1211   if (Opc != X86::LEA64_32r) {
1212     NewSrc = SrcReg;
1213     isKill = Src.isKill();
1214     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1215 
1216     if (NewSrc.isVirtual() && !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1217       return false;
1218 
1219     return true;
1220   }
1221 
1222   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1223   // another we need to add 64-bit registers to the final MI.
1224   if (SrcReg.isPhysical()) {
1225     ImplicitOp = Src;
1226     ImplicitOp.setImplicit();
1227 
1228     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
1229     isKill = Src.isKill();
1230     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1231   } else {
1232     // Virtual register of the wrong class, we have to create a temporary 64-bit
1233     // vreg to feed into the LEA.
1234     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1235     MachineInstr *Copy =
1236         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1237             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1238             .add(Src);
1239 
1240     // Which is obviously going to be dead after we're done with it.
1241     isKill = true;
1242 
1243     if (LV)
1244       LV->replaceKillInstruction(SrcReg, MI, *Copy);
1245   }
1246 
1247   // We've set all the parameters without issue.
1248   return true;
1249 }
1250 
1251 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1252                                                          MachineInstr &MI,
1253                                                          LiveVariables *LV,
1254                                                          bool Is8BitOp) const {
1255   // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1256   MachineBasicBlock &MBB = *MI.getParent();
1257   MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
1258   assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1259               *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1260          "Unexpected type for LEA transform");
1261 
1262   // TODO: For a 32-bit target, we need to adjust the LEA variables with
1263   // something like this:
1264   //   Opcode = X86::LEA32r;
1265   //   InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1266   //   OutRegLEA =
1267   //       Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1268   //                : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1269   if (!Subtarget.is64Bit())
1270     return nullptr;
1271 
1272   unsigned Opcode = X86::LEA64_32r;
1273   Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1274   Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1275 
1276   // Build and insert into an implicit UNDEF value. This is OK because
1277   // we will be shifting and then extracting the lower 8/16-bits.
1278   // This has the potential to cause partial register stall. e.g.
1279   //   movw    (%rbp,%rcx,2), %dx
1280   //   leal    -65(%rdx), %esi
1281   // But testing has shown this *does* help performance in 64-bit mode (at
1282   // least on modern x86 machines).
1283   MachineBasicBlock::iterator MBBI = MI.getIterator();
1284   Register Dest = MI.getOperand(0).getReg();
1285   Register Src = MI.getOperand(1).getReg();
1286   bool IsDead = MI.getOperand(0).isDead();
1287   bool IsKill = MI.getOperand(1).isKill();
1288   unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1289   assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
1290   BuildMI(MBB, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
1291   MachineInstr *InsMI =
1292       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1293           .addReg(InRegLEA, RegState::Define, SubReg)
1294           .addReg(Src, getKillRegState(IsKill));
1295 
1296   MachineInstrBuilder MIB =
1297       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
1298   switch (MIOpc) {
1299   default: llvm_unreachable("Unreachable!");
1300   case X86::SHL8ri:
1301   case X86::SHL16ri: {
1302     unsigned ShAmt = MI.getOperand(2).getImm();
1303     MIB.addReg(0).addImm(1ULL << ShAmt)
1304        .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
1305     break;
1306   }
1307   case X86::INC8r:
1308   case X86::INC16r:
1309     addRegOffset(MIB, InRegLEA, true, 1);
1310     break;
1311   case X86::DEC8r:
1312   case X86::DEC16r:
1313     addRegOffset(MIB, InRegLEA, true, -1);
1314     break;
1315   case X86::ADD8ri:
1316   case X86::ADD8ri_DB:
1317   case X86::ADD16ri:
1318   case X86::ADD16ri8:
1319   case X86::ADD16ri_DB:
1320   case X86::ADD16ri8_DB:
1321     addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1322     break;
1323   case X86::ADD8rr:
1324   case X86::ADD8rr_DB:
1325   case X86::ADD16rr:
1326   case X86::ADD16rr_DB: {
1327     Register Src2 = MI.getOperand(2).getReg();
1328     bool IsKill2 = MI.getOperand(2).isKill();
1329     assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
1330     unsigned InRegLEA2 = 0;
1331     MachineInstr *InsMI2 = nullptr;
1332     if (Src == Src2) {
1333       // ADD8rr/ADD16rr killed %reg1028, %reg1028
1334       // just a single insert_subreg.
1335       addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1336     } else {
1337       if (Subtarget.is64Bit())
1338         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1339       else
1340         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1341       // Build and insert into an implicit UNDEF value. This is OK because
1342       // we will be shifting and then extracting the lower 8/16-bits.
1343       BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
1344       InsMI2 = BuildMI(MBB, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1345                    .addReg(InRegLEA2, RegState::Define, SubReg)
1346                    .addReg(Src2, getKillRegState(IsKill2));
1347       addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1348     }
1349     if (LV && IsKill2 && InsMI2)
1350       LV->replaceKillInstruction(Src2, MI, *InsMI2);
1351     break;
1352   }
1353   }
1354 
1355   MachineInstr *NewMI = MIB;
1356   MachineInstr *ExtMI =
1357       BuildMI(MBB, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1358           .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
1359           .addReg(OutRegLEA, RegState::Kill, SubReg);
1360 
1361   if (LV) {
1362     // Update live variables.
1363     LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1364     LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
1365     if (IsKill)
1366       LV->replaceKillInstruction(Src, MI, *InsMI);
1367     if (IsDead)
1368       LV->replaceKillInstruction(Dest, MI, *ExtMI);
1369   }
1370 
1371   return ExtMI;
1372 }
1373 
1374 /// This method must be implemented by targets that
1375 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1376 /// may be able to convert a two-address instruction into a true
1377 /// three-address instruction on demand.  This allows the X86 target (for
1378 /// example) to convert ADD and SHL instructions into LEA instructions if they
1379 /// would require register copies due to two-addressness.
1380 ///
1381 /// This method returns a null pointer if the transformation cannot be
1382 /// performed, otherwise it returns the new instruction.
1383 ///
1384 MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
1385                                                   LiveVariables *LV) const {
1386   // The following opcodes also sets the condition code register(s). Only
1387   // convert them to equivalent lea if the condition code register def's
1388   // are dead!
1389   if (hasLiveCondCodeDef(MI))
1390     return nullptr;
1391 
1392   MachineFunction &MF = *MI.getParent()->getParent();
1393   // All instructions input are two-addr instructions.  Get the known operands.
1394   const MachineOperand &Dest = MI.getOperand(0);
1395   const MachineOperand &Src = MI.getOperand(1);
1396 
1397   // Ideally, operations with undef should be folded before we get here, but we
1398   // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1399   // Without this, we have to forward undef state to new register operands to
1400   // avoid machine verifier errors.
1401   if (Src.isUndef())
1402     return nullptr;
1403   if (MI.getNumOperands() > 2)
1404     if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
1405       return nullptr;
1406 
1407   MachineInstr *NewMI = nullptr;
1408   bool Is64Bit = Subtarget.is64Bit();
1409 
1410   bool Is8BitOp = false;
1411   unsigned MIOpc = MI.getOpcode();
1412   switch (MIOpc) {
1413   default: llvm_unreachable("Unreachable!");
1414   case X86::SHL64ri: {
1415     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1416     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1417     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1418 
1419     // LEA can't handle RSP.
1420     if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass(
1421                                         Src.getReg(), &X86::GR64_NOSPRegClass))
1422       return nullptr;
1423 
1424     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1425                 .add(Dest)
1426                 .addReg(0)
1427                 .addImm(1ULL << ShAmt)
1428                 .add(Src)
1429                 .addImm(0)
1430                 .addReg(0);
1431     break;
1432   }
1433   case X86::SHL32ri: {
1434     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1435     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1436     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1437 
1438     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1439 
1440     // LEA can't handle ESP.
1441     bool isKill;
1442     Register SrcReg;
1443     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1444     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
1445                         SrcReg, isKill, ImplicitOp, LV))
1446       return nullptr;
1447 
1448     MachineInstrBuilder MIB =
1449         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1450             .add(Dest)
1451             .addReg(0)
1452             .addImm(1ULL << ShAmt)
1453             .addReg(SrcReg, getKillRegState(isKill))
1454             .addImm(0)
1455             .addReg(0);
1456     if (ImplicitOp.getReg() != 0)
1457       MIB.add(ImplicitOp);
1458     NewMI = MIB;
1459 
1460     break;
1461   }
1462   case X86::SHL8ri:
1463     Is8BitOp = true;
1464     LLVM_FALLTHROUGH;
1465   case X86::SHL16ri: {
1466     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1467     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1468     if (!isTruncatedShiftCountForLEA(ShAmt))
1469       return nullptr;
1470     return convertToThreeAddressWithLEA(MIOpc, MI, LV, Is8BitOp);
1471   }
1472   case X86::INC64r:
1473   case X86::INC32r: {
1474     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1475     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1476         (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1477     bool isKill;
1478     Register SrcReg;
1479     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1480     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1481                         ImplicitOp, LV))
1482       return nullptr;
1483 
1484     MachineInstrBuilder MIB =
1485         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1486             .add(Dest)
1487             .addReg(SrcReg, getKillRegState(isKill));
1488     if (ImplicitOp.getReg() != 0)
1489       MIB.add(ImplicitOp);
1490 
1491     NewMI = addOffset(MIB, 1);
1492     break;
1493   }
1494   case X86::DEC64r:
1495   case X86::DEC32r: {
1496     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1497     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1498         : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1499 
1500     bool isKill;
1501     Register SrcReg;
1502     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1503     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1504                         ImplicitOp, LV))
1505       return nullptr;
1506 
1507     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1508                                   .add(Dest)
1509                                   .addReg(SrcReg, getKillRegState(isKill));
1510     if (ImplicitOp.getReg() != 0)
1511       MIB.add(ImplicitOp);
1512 
1513     NewMI = addOffset(MIB, -1);
1514 
1515     break;
1516   }
1517   case X86::DEC8r:
1518   case X86::INC8r:
1519     Is8BitOp = true;
1520     LLVM_FALLTHROUGH;
1521   case X86::DEC16r:
1522   case X86::INC16r:
1523     return convertToThreeAddressWithLEA(MIOpc, MI, LV, Is8BitOp);
1524   case X86::ADD64rr:
1525   case X86::ADD64rr_DB:
1526   case X86::ADD32rr:
1527   case X86::ADD32rr_DB: {
1528     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1529     unsigned Opc;
1530     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1531       Opc = X86::LEA64r;
1532     else
1533       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1534 
1535     bool isKill;
1536     Register SrcReg;
1537     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1538     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1539                         SrcReg, isKill, ImplicitOp, LV))
1540       return nullptr;
1541 
1542     const MachineOperand &Src2 = MI.getOperand(2);
1543     bool isKill2;
1544     Register SrcReg2;
1545     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1546     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1547                         SrcReg2, isKill2, ImplicitOp2, LV))
1548       return nullptr;
1549 
1550     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1551     if (ImplicitOp.getReg() != 0)
1552       MIB.add(ImplicitOp);
1553     if (ImplicitOp2.getReg() != 0)
1554       MIB.add(ImplicitOp2);
1555 
1556     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1557     if (LV && Src2.isKill())
1558       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1559     break;
1560   }
1561   case X86::ADD8rr:
1562   case X86::ADD8rr_DB:
1563     Is8BitOp = true;
1564     LLVM_FALLTHROUGH;
1565   case X86::ADD16rr:
1566   case X86::ADD16rr_DB:
1567     return convertToThreeAddressWithLEA(MIOpc, MI, LV, Is8BitOp);
1568   case X86::ADD64ri32:
1569   case X86::ADD64ri8:
1570   case X86::ADD64ri32_DB:
1571   case X86::ADD64ri8_DB:
1572     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1573     NewMI = addOffset(
1574         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1575         MI.getOperand(2));
1576     break;
1577   case X86::ADD32ri:
1578   case X86::ADD32ri8:
1579   case X86::ADD32ri_DB:
1580   case X86::ADD32ri8_DB: {
1581     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1582     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1583 
1584     bool isKill;
1585     Register SrcReg;
1586     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1587     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1588                         SrcReg, isKill, ImplicitOp, LV))
1589       return nullptr;
1590 
1591     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1592                                   .add(Dest)
1593                                   .addReg(SrcReg, getKillRegState(isKill));
1594     if (ImplicitOp.getReg() != 0)
1595       MIB.add(ImplicitOp);
1596 
1597     NewMI = addOffset(MIB, MI.getOperand(2));
1598     break;
1599   }
1600   case X86::ADD8ri:
1601   case X86::ADD8ri_DB:
1602     Is8BitOp = true;
1603     LLVM_FALLTHROUGH;
1604   case X86::ADD16ri:
1605   case X86::ADD16ri8:
1606   case X86::ADD16ri_DB:
1607   case X86::ADD16ri8_DB:
1608     return convertToThreeAddressWithLEA(MIOpc, MI, LV, Is8BitOp);
1609   case X86::SUB8ri:
1610   case X86::SUB16ri8:
1611   case X86::SUB16ri:
1612     /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1613     return nullptr;
1614   case X86::SUB32ri8:
1615   case X86::SUB32ri: {
1616     if (!MI.getOperand(2).isImm())
1617       return nullptr;
1618     int64_t Imm = MI.getOperand(2).getImm();
1619     if (!isInt<32>(-Imm))
1620       return nullptr;
1621 
1622     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1623     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1624 
1625     bool isKill;
1626     Register SrcReg;
1627     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1628     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1629                         SrcReg, isKill, ImplicitOp, LV))
1630       return nullptr;
1631 
1632     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1633                                   .add(Dest)
1634                                   .addReg(SrcReg, getKillRegState(isKill));
1635     if (ImplicitOp.getReg() != 0)
1636       MIB.add(ImplicitOp);
1637 
1638     NewMI = addOffset(MIB, -Imm);
1639     break;
1640   }
1641 
1642   case X86::SUB64ri8:
1643   case X86::SUB64ri32: {
1644     if (!MI.getOperand(2).isImm())
1645       return nullptr;
1646     int64_t Imm = MI.getOperand(2).getImm();
1647     if (!isInt<32>(-Imm))
1648       return nullptr;
1649 
1650     assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1651 
1652     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1653                                       get(X86::LEA64r)).add(Dest).add(Src);
1654     NewMI = addOffset(MIB, -Imm);
1655     break;
1656   }
1657 
1658   case X86::VMOVDQU8Z128rmk:
1659   case X86::VMOVDQU8Z256rmk:
1660   case X86::VMOVDQU8Zrmk:
1661   case X86::VMOVDQU16Z128rmk:
1662   case X86::VMOVDQU16Z256rmk:
1663   case X86::VMOVDQU16Zrmk:
1664   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1665   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1666   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
1667   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1668   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1669   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
1670   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
1671   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
1672   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
1673   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
1674   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
1675   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk:
1676   case X86::VBROADCASTSDZ256rmk:
1677   case X86::VBROADCASTSDZrmk:
1678   case X86::VBROADCASTSSZ128rmk:
1679   case X86::VBROADCASTSSZ256rmk:
1680   case X86::VBROADCASTSSZrmk:
1681   case X86::VPBROADCASTDZ128rmk:
1682   case X86::VPBROADCASTDZ256rmk:
1683   case X86::VPBROADCASTDZrmk:
1684   case X86::VPBROADCASTQZ128rmk:
1685   case X86::VPBROADCASTQZ256rmk:
1686   case X86::VPBROADCASTQZrmk: {
1687     unsigned Opc;
1688     switch (MIOpc) {
1689     default: llvm_unreachable("Unreachable!");
1690     case X86::VMOVDQU8Z128rmk:     Opc = X86::VPBLENDMBZ128rmk; break;
1691     case X86::VMOVDQU8Z256rmk:     Opc = X86::VPBLENDMBZ256rmk; break;
1692     case X86::VMOVDQU8Zrmk:        Opc = X86::VPBLENDMBZrmk;    break;
1693     case X86::VMOVDQU16Z128rmk:    Opc = X86::VPBLENDMWZ128rmk; break;
1694     case X86::VMOVDQU16Z256rmk:    Opc = X86::VPBLENDMWZ256rmk; break;
1695     case X86::VMOVDQU16Zrmk:       Opc = X86::VPBLENDMWZrmk;    break;
1696     case X86::VMOVDQU32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1697     case X86::VMOVDQU32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1698     case X86::VMOVDQU32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1699     case X86::VMOVDQU64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1700     case X86::VMOVDQU64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1701     case X86::VMOVDQU64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1702     case X86::VMOVUPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1703     case X86::VMOVUPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1704     case X86::VMOVUPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1705     case X86::VMOVUPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1706     case X86::VMOVUPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1707     case X86::VMOVUPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1708     case X86::VMOVDQA32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1709     case X86::VMOVDQA32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1710     case X86::VMOVDQA32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1711     case X86::VMOVDQA64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1712     case X86::VMOVDQA64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1713     case X86::VMOVDQA64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1714     case X86::VMOVAPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1715     case X86::VMOVAPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1716     case X86::VMOVAPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1717     case X86::VMOVAPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1718     case X86::VMOVAPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1719     case X86::VMOVAPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1720     case X86::VBROADCASTSDZ256rmk: Opc = X86::VBLENDMPDZ256rmbk; break;
1721     case X86::VBROADCASTSDZrmk:    Opc = X86::VBLENDMPDZrmbk;    break;
1722     case X86::VBROADCASTSSZ128rmk: Opc = X86::VBLENDMPSZ128rmbk; break;
1723     case X86::VBROADCASTSSZ256rmk: Opc = X86::VBLENDMPSZ256rmbk; break;
1724     case X86::VBROADCASTSSZrmk:    Opc = X86::VBLENDMPSZrmbk;    break;
1725     case X86::VPBROADCASTDZ128rmk: Opc = X86::VPBLENDMDZ128rmbk; break;
1726     case X86::VPBROADCASTDZ256rmk: Opc = X86::VPBLENDMDZ256rmbk; break;
1727     case X86::VPBROADCASTDZrmk:    Opc = X86::VPBLENDMDZrmbk;    break;
1728     case X86::VPBROADCASTQZ128rmk: Opc = X86::VPBLENDMQZ128rmbk; break;
1729     case X86::VPBROADCASTQZ256rmk: Opc = X86::VPBLENDMQZ256rmbk; break;
1730     case X86::VPBROADCASTQZrmk:    Opc = X86::VPBLENDMQZrmbk;    break;
1731     }
1732 
1733     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1734               .add(Dest)
1735               .add(MI.getOperand(2))
1736               .add(Src)
1737               .add(MI.getOperand(3))
1738               .add(MI.getOperand(4))
1739               .add(MI.getOperand(5))
1740               .add(MI.getOperand(6))
1741               .add(MI.getOperand(7));
1742     break;
1743   }
1744 
1745   case X86::VMOVDQU8Z128rrk:
1746   case X86::VMOVDQU8Z256rrk:
1747   case X86::VMOVDQU8Zrrk:
1748   case X86::VMOVDQU16Z128rrk:
1749   case X86::VMOVDQU16Z256rrk:
1750   case X86::VMOVDQU16Zrrk:
1751   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1752   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1753   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
1754   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1755   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1756   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
1757   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
1758   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
1759   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
1760   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
1761   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
1762   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
1763     unsigned Opc;
1764     switch (MIOpc) {
1765     default: llvm_unreachable("Unreachable!");
1766     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
1767     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
1768     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
1769     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1770     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1771     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
1772     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1773     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1774     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1775     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1776     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1777     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1778     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1779     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1780     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1781     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1782     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1783     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1784     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1785     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1786     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1787     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1788     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1789     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1790     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1791     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1792     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1793     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1794     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1795     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1796     }
1797 
1798     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1799               .add(Dest)
1800               .add(MI.getOperand(2))
1801               .add(Src)
1802               .add(MI.getOperand(3));
1803     break;
1804   }
1805   }
1806 
1807   if (!NewMI) return nullptr;
1808 
1809   if (LV) {  // Update live variables
1810     if (Src.isKill())
1811       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1812     if (Dest.isDead())
1813       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1814   }
1815 
1816   MachineBasicBlock &MBB = *MI.getParent();
1817   MBB.insert(MI.getIterator(), NewMI); // Insert the new inst
1818   return NewMI;
1819 }
1820 
1821 /// This determines which of three possible cases of a three source commute
1822 /// the source indexes correspond to taking into account any mask operands.
1823 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1824 /// possible.
1825 /// Case 0 - Possible to commute the first and second operands.
1826 /// Case 1 - Possible to commute the first and third operands.
1827 /// Case 2 - Possible to commute the second and third operands.
1828 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1829                                        unsigned SrcOpIdx2) {
1830   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1831   if (SrcOpIdx1 > SrcOpIdx2)
1832     std::swap(SrcOpIdx1, SrcOpIdx2);
1833 
1834   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1835   if (X86II::isKMasked(TSFlags)) {
1836     Op2++;
1837     Op3++;
1838   }
1839 
1840   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1841     return 0;
1842   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1843     return 1;
1844   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1845     return 2;
1846   llvm_unreachable("Unknown three src commute case.");
1847 }
1848 
1849 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1850     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1851     const X86InstrFMA3Group &FMA3Group) const {
1852 
1853   unsigned Opc = MI.getOpcode();
1854 
1855   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1856   // analysis. The commute optimization is legal only if all users of FMA*_Int
1857   // use only the lowest element of the FMA*_Int instruction. Such analysis are
1858   // not implemented yet. So, just return 0 in that case.
1859   // When such analysis are available this place will be the right place for
1860   // calling it.
1861   assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1862          "Intrinsic instructions can't commute operand 1");
1863 
1864   // Determine which case this commute is or if it can't be done.
1865   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1866                                          SrcOpIdx2);
1867   assert(Case < 3 && "Unexpected case number!");
1868 
1869   // Define the FMA forms mapping array that helps to map input FMA form
1870   // to output FMA form to preserve the operation semantics after
1871   // commuting the operands.
1872   const unsigned Form132Index = 0;
1873   const unsigned Form213Index = 1;
1874   const unsigned Form231Index = 2;
1875   static const unsigned FormMapping[][3] = {
1876     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1877     // FMA132 A, C, b; ==> FMA231 C, A, b;
1878     // FMA213 B, A, c; ==> FMA213 A, B, c;
1879     // FMA231 C, A, b; ==> FMA132 A, C, b;
1880     { Form231Index, Form213Index, Form132Index },
1881     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1882     // FMA132 A, c, B; ==> FMA132 B, c, A;
1883     // FMA213 B, a, C; ==> FMA231 C, a, B;
1884     // FMA231 C, a, B; ==> FMA213 B, a, C;
1885     { Form132Index, Form231Index, Form213Index },
1886     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1887     // FMA132 a, C, B; ==> FMA213 a, B, C;
1888     // FMA213 b, A, C; ==> FMA132 b, C, A;
1889     // FMA231 c, A, B; ==> FMA231 c, B, A;
1890     { Form213Index, Form132Index, Form231Index }
1891   };
1892 
1893   unsigned FMAForms[3];
1894   FMAForms[0] = FMA3Group.get132Opcode();
1895   FMAForms[1] = FMA3Group.get213Opcode();
1896   FMAForms[2] = FMA3Group.get231Opcode();
1897   unsigned FormIndex;
1898   for (FormIndex = 0; FormIndex < 3; FormIndex++)
1899     if (Opc == FMAForms[FormIndex])
1900       break;
1901 
1902   // Everything is ready, just adjust the FMA opcode and return it.
1903   FormIndex = FormMapping[Case][FormIndex];
1904   return FMAForms[FormIndex];
1905 }
1906 
1907 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1908                              unsigned SrcOpIdx2) {
1909   // Determine which case this commute is or if it can't be done.
1910   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1911                                          SrcOpIdx2);
1912   assert(Case < 3 && "Unexpected case value!");
1913 
1914   // For each case we need to swap two pairs of bits in the final immediate.
1915   static const uint8_t SwapMasks[3][4] = {
1916     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1917     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1918     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1919   };
1920 
1921   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1922   // Clear out the bits we are swapping.
1923   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1924                            SwapMasks[Case][2] | SwapMasks[Case][3]);
1925   // If the immediate had a bit of the pair set, then set the opposite bit.
1926   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1927   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1928   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1929   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1930   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1931 }
1932 
1933 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1934 // commuted.
1935 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1936 #define VPERM_CASES(Suffix) \
1937   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
1938   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
1939   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
1940   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
1941   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
1942   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
1943   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
1944   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
1945   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
1946   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
1947   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
1948   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
1949 
1950 #define VPERM_CASES_BROADCAST(Suffix) \
1951   VPERM_CASES(Suffix) \
1952   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
1953   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
1954   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
1955   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1956   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1957   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
1958 
1959   switch (Opcode) {
1960   default: return false;
1961   VPERM_CASES(B)
1962   VPERM_CASES_BROADCAST(D)
1963   VPERM_CASES_BROADCAST(PD)
1964   VPERM_CASES_BROADCAST(PS)
1965   VPERM_CASES_BROADCAST(Q)
1966   VPERM_CASES(W)
1967     return true;
1968   }
1969 #undef VPERM_CASES_BROADCAST
1970 #undef VPERM_CASES
1971 }
1972 
1973 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1974 // from the I opcode to the T opcode and vice versa.
1975 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1976 #define VPERM_CASES(Orig, New) \
1977   case X86::Orig##128rr:    return X86::New##128rr;   \
1978   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
1979   case X86::Orig##128rm:    return X86::New##128rm;   \
1980   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
1981   case X86::Orig##256rr:    return X86::New##256rr;   \
1982   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
1983   case X86::Orig##256rm:    return X86::New##256rm;   \
1984   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
1985   case X86::Orig##rr:       return X86::New##rr;      \
1986   case X86::Orig##rrkz:     return X86::New##rrkz;    \
1987   case X86::Orig##rm:       return X86::New##rm;      \
1988   case X86::Orig##rmkz:     return X86::New##rmkz;
1989 
1990 #define VPERM_CASES_BROADCAST(Orig, New) \
1991   VPERM_CASES(Orig, New) \
1992   case X86::Orig##128rmb:   return X86::New##128rmb;   \
1993   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1994   case X86::Orig##256rmb:   return X86::New##256rmb;   \
1995   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1996   case X86::Orig##rmb:      return X86::New##rmb;      \
1997   case X86::Orig##rmbkz:    return X86::New##rmbkz;
1998 
1999   switch (Opcode) {
2000   VPERM_CASES(VPERMI2B, VPERMT2B)
2001   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
2002   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
2003   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
2004   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
2005   VPERM_CASES(VPERMI2W, VPERMT2W)
2006   VPERM_CASES(VPERMT2B, VPERMI2B)
2007   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
2008   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
2009   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
2010   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
2011   VPERM_CASES(VPERMT2W, VPERMI2W)
2012   }
2013 
2014   llvm_unreachable("Unreachable!");
2015 #undef VPERM_CASES_BROADCAST
2016 #undef VPERM_CASES
2017 }
2018 
2019 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2020                                                    unsigned OpIdx1,
2021                                                    unsigned OpIdx2) const {
2022   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
2023     if (NewMI)
2024       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
2025     return MI;
2026   };
2027 
2028   switch (MI.getOpcode()) {
2029   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2030   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2031   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2032   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2033   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2034   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2035     unsigned Opc;
2036     unsigned Size;
2037     switch (MI.getOpcode()) {
2038     default: llvm_unreachable("Unreachable!");
2039     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2040     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2041     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2042     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2043     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2044     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2045     }
2046     unsigned Amt = MI.getOperand(3).getImm();
2047     auto &WorkingMI = cloneIfNew(MI);
2048     WorkingMI.setDesc(get(Opc));
2049     WorkingMI.getOperand(3).setImm(Size - Amt);
2050     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2051                                                    OpIdx1, OpIdx2);
2052   }
2053   case X86::PFSUBrr:
2054   case X86::PFSUBRrr: {
2055     // PFSUB  x, y: x = x - y
2056     // PFSUBR x, y: x = y - x
2057     unsigned Opc =
2058         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
2059     auto &WorkingMI = cloneIfNew(MI);
2060     WorkingMI.setDesc(get(Opc));
2061     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2062                                                    OpIdx1, OpIdx2);
2063   }
2064   case X86::BLENDPDrri:
2065   case X86::BLENDPSrri:
2066   case X86::VBLENDPDrri:
2067   case X86::VBLENDPSrri:
2068     // If we're optimizing for size, try to use MOVSD/MOVSS.
2069     if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
2070       unsigned Mask, Opc;
2071       switch (MI.getOpcode()) {
2072       default: llvm_unreachable("Unreachable!");
2073       case X86::BLENDPDrri:  Opc = X86::MOVSDrr;  Mask = 0x03; break;
2074       case X86::BLENDPSrri:  Opc = X86::MOVSSrr;  Mask = 0x0F; break;
2075       case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
2076       case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
2077       }
2078       if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
2079         auto &WorkingMI = cloneIfNew(MI);
2080         WorkingMI.setDesc(get(Opc));
2081         WorkingMI.RemoveOperand(3);
2082         return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
2083                                                        /*NewMI=*/false,
2084                                                        OpIdx1, OpIdx2);
2085       }
2086     }
2087     LLVM_FALLTHROUGH;
2088   case X86::PBLENDWrri:
2089   case X86::VBLENDPDYrri:
2090   case X86::VBLENDPSYrri:
2091   case X86::VPBLENDDrri:
2092   case X86::VPBLENDWrri:
2093   case X86::VPBLENDDYrri:
2094   case X86::VPBLENDWYrri:{
2095     int8_t Mask;
2096     switch (MI.getOpcode()) {
2097     default: llvm_unreachable("Unreachable!");
2098     case X86::BLENDPDrri:    Mask = (int8_t)0x03; break;
2099     case X86::BLENDPSrri:    Mask = (int8_t)0x0F; break;
2100     case X86::PBLENDWrri:    Mask = (int8_t)0xFF; break;
2101     case X86::VBLENDPDrri:   Mask = (int8_t)0x03; break;
2102     case X86::VBLENDPSrri:   Mask = (int8_t)0x0F; break;
2103     case X86::VBLENDPDYrri:  Mask = (int8_t)0x0F; break;
2104     case X86::VBLENDPSYrri:  Mask = (int8_t)0xFF; break;
2105     case X86::VPBLENDDrri:   Mask = (int8_t)0x0F; break;
2106     case X86::VPBLENDWrri:   Mask = (int8_t)0xFF; break;
2107     case X86::VPBLENDDYrri:  Mask = (int8_t)0xFF; break;
2108     case X86::VPBLENDWYrri:  Mask = (int8_t)0xFF; break;
2109     }
2110     // Only the least significant bits of Imm are used.
2111     // Using int8_t to ensure it will be sign extended to the int64_t that
2112     // setImm takes in order to match isel behavior.
2113     int8_t Imm = MI.getOperand(3).getImm() & Mask;
2114     auto &WorkingMI = cloneIfNew(MI);
2115     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
2116     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2117                                                    OpIdx1, OpIdx2);
2118   }
2119   case X86::INSERTPSrr:
2120   case X86::VINSERTPSrr:
2121   case X86::VINSERTPSZrr: {
2122     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
2123     unsigned ZMask = Imm & 15;
2124     unsigned DstIdx = (Imm >> 4) & 3;
2125     unsigned SrcIdx = (Imm >> 6) & 3;
2126 
2127     // We can commute insertps if we zero 2 of the elements, the insertion is
2128     // "inline" and we don't override the insertion with a zero.
2129     if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2130         countPopulation(ZMask) == 2) {
2131       unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
2132       assert(AltIdx < 4 && "Illegal insertion index");
2133       unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2134       auto &WorkingMI = cloneIfNew(MI);
2135       WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
2136       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2137                                                      OpIdx1, OpIdx2);
2138     }
2139     return nullptr;
2140   }
2141   case X86::MOVSDrr:
2142   case X86::MOVSSrr:
2143   case X86::VMOVSDrr:
2144   case X86::VMOVSSrr:{
2145     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
2146     if (Subtarget.hasSSE41()) {
2147       unsigned Mask, Opc;
2148       switch (MI.getOpcode()) {
2149       default: llvm_unreachable("Unreachable!");
2150       case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
2151       case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
2152       case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
2153       case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
2154       }
2155 
2156       auto &WorkingMI = cloneIfNew(MI);
2157       WorkingMI.setDesc(get(Opc));
2158       WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
2159       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2160                                                      OpIdx1, OpIdx2);
2161     }
2162 
2163     // Convert to SHUFPD.
2164     assert(MI.getOpcode() == X86::MOVSDrr &&
2165            "Can only commute MOVSDrr without SSE4.1");
2166 
2167     auto &WorkingMI = cloneIfNew(MI);
2168     WorkingMI.setDesc(get(X86::SHUFPDrri));
2169     WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2170     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2171                                                    OpIdx1, OpIdx2);
2172   }
2173   case X86::SHUFPDrri: {
2174     // Commute to MOVSD.
2175     assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
2176     auto &WorkingMI = cloneIfNew(MI);
2177     WorkingMI.setDesc(get(X86::MOVSDrr));
2178     WorkingMI.RemoveOperand(3);
2179     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2180                                                    OpIdx1, OpIdx2);
2181   }
2182   case X86::PCLMULQDQrr:
2183   case X86::VPCLMULQDQrr:
2184   case X86::VPCLMULQDQYrr:
2185   case X86::VPCLMULQDQZrr:
2186   case X86::VPCLMULQDQZ128rr:
2187   case X86::VPCLMULQDQZ256rr: {
2188     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2189     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2190     unsigned Imm = MI.getOperand(3).getImm();
2191     unsigned Src1Hi = Imm & 0x01;
2192     unsigned Src2Hi = Imm & 0x10;
2193     auto &WorkingMI = cloneIfNew(MI);
2194     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2195     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2196                                                    OpIdx1, OpIdx2);
2197   }
2198   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
2199   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
2200   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
2201   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
2202   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
2203   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
2204   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
2205   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
2206   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
2207   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
2208   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
2209   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
2210   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
2211   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
2212   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
2213   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
2214   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
2215   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
2216   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
2217   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
2218   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
2219   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
2220   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
2221   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
2222     // Flip comparison mode immediate (if necessary).
2223     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
2224     Imm = X86::getSwappedVPCMPImm(Imm);
2225     auto &WorkingMI = cloneIfNew(MI);
2226     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
2227     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2228                                                    OpIdx1, OpIdx2);
2229   }
2230   case X86::VPCOMBri: case X86::VPCOMUBri:
2231   case X86::VPCOMDri: case X86::VPCOMUDri:
2232   case X86::VPCOMQri: case X86::VPCOMUQri:
2233   case X86::VPCOMWri: case X86::VPCOMUWri: {
2234     // Flip comparison mode immediate (if necessary).
2235     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
2236     Imm = X86::getSwappedVPCOMImm(Imm);
2237     auto &WorkingMI = cloneIfNew(MI);
2238     WorkingMI.getOperand(3).setImm(Imm);
2239     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2240                                                    OpIdx1, OpIdx2);
2241   }
2242   case X86::VCMPSDZrr:
2243   case X86::VCMPSSZrr:
2244   case X86::VCMPPDZrri:
2245   case X86::VCMPPSZrri:
2246   case X86::VCMPSHZrr:
2247   case X86::VCMPPHZrri:
2248   case X86::VCMPPHZ128rri:
2249   case X86::VCMPPHZ256rri:
2250   case X86::VCMPPDZ128rri:
2251   case X86::VCMPPSZ128rri:
2252   case X86::VCMPPDZ256rri:
2253   case X86::VCMPPSZ256rri:
2254   case X86::VCMPPDZrrik:
2255   case X86::VCMPPSZrrik:
2256   case X86::VCMPPDZ128rrik:
2257   case X86::VCMPPSZ128rrik:
2258   case X86::VCMPPDZ256rrik:
2259   case X86::VCMPPSZ256rrik: {
2260     unsigned Imm =
2261                 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f;
2262     Imm = X86::getSwappedVCMPImm(Imm);
2263     auto &WorkingMI = cloneIfNew(MI);
2264     WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm);
2265     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2266                                                    OpIdx1, OpIdx2);
2267   }
2268   case X86::VPERM2F128rr:
2269   case X86::VPERM2I128rr: {
2270     // Flip permute source immediate.
2271     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2272     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2273     int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
2274     auto &WorkingMI = cloneIfNew(MI);
2275     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
2276     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2277                                                    OpIdx1, OpIdx2);
2278   }
2279   case X86::MOVHLPSrr:
2280   case X86::UNPCKHPDrr:
2281   case X86::VMOVHLPSrr:
2282   case X86::VUNPCKHPDrr:
2283   case X86::VMOVHLPSZrr:
2284   case X86::VUNPCKHPDZ128rr: {
2285     assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
2286 
2287     unsigned Opc = MI.getOpcode();
2288     switch (Opc) {
2289     default: llvm_unreachable("Unreachable!");
2290     case X86::MOVHLPSrr:       Opc = X86::UNPCKHPDrr;      break;
2291     case X86::UNPCKHPDrr:      Opc = X86::MOVHLPSrr;       break;
2292     case X86::VMOVHLPSrr:      Opc = X86::VUNPCKHPDrr;     break;
2293     case X86::VUNPCKHPDrr:     Opc = X86::VMOVHLPSrr;      break;
2294     case X86::VMOVHLPSZrr:     Opc = X86::VUNPCKHPDZ128rr; break;
2295     case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr;     break;
2296     }
2297     auto &WorkingMI = cloneIfNew(MI);
2298     WorkingMI.setDesc(get(Opc));
2299     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2300                                                    OpIdx1, OpIdx2);
2301   }
2302   case X86::CMOV16rr:  case X86::CMOV32rr:  case X86::CMOV64rr: {
2303     auto &WorkingMI = cloneIfNew(MI);
2304     unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2305     X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
2306     WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2307     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2308                                                    OpIdx1, OpIdx2);
2309   }
2310   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2311   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2312   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2313   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2314   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2315   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2316   case X86::VPTERNLOGDZrrik:
2317   case X86::VPTERNLOGDZ128rrik:
2318   case X86::VPTERNLOGDZ256rrik:
2319   case X86::VPTERNLOGQZrrik:
2320   case X86::VPTERNLOGQZ128rrik:
2321   case X86::VPTERNLOGQZ256rrik:
2322   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2323   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2324   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2325   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2326   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2327   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2328   case X86::VPTERNLOGDZ128rmbi:
2329   case X86::VPTERNLOGDZ256rmbi:
2330   case X86::VPTERNLOGDZrmbi:
2331   case X86::VPTERNLOGQZ128rmbi:
2332   case X86::VPTERNLOGQZ256rmbi:
2333   case X86::VPTERNLOGQZrmbi:
2334   case X86::VPTERNLOGDZ128rmbikz:
2335   case X86::VPTERNLOGDZ256rmbikz:
2336   case X86::VPTERNLOGDZrmbikz:
2337   case X86::VPTERNLOGQZ128rmbikz:
2338   case X86::VPTERNLOGQZ256rmbikz:
2339   case X86::VPTERNLOGQZrmbikz: {
2340     auto &WorkingMI = cloneIfNew(MI);
2341     commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
2342     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2343                                                    OpIdx1, OpIdx2);
2344   }
2345   default: {
2346     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
2347       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
2348       auto &WorkingMI = cloneIfNew(MI);
2349       WorkingMI.setDesc(get(Opc));
2350       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2351                                                      OpIdx1, OpIdx2);
2352     }
2353 
2354     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2355                                                       MI.getDesc().TSFlags);
2356     if (FMA3Group) {
2357       unsigned Opc =
2358         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
2359       auto &WorkingMI = cloneIfNew(MI);
2360       WorkingMI.setDesc(get(Opc));
2361       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2362                                                      OpIdx1, OpIdx2);
2363     }
2364 
2365     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2366   }
2367   }
2368 }
2369 
2370 bool
2371 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2372                                             unsigned &SrcOpIdx1,
2373                                             unsigned &SrcOpIdx2,
2374                                             bool IsIntrinsic) const {
2375   uint64_t TSFlags = MI.getDesc().TSFlags;
2376 
2377   unsigned FirstCommutableVecOp = 1;
2378   unsigned LastCommutableVecOp = 3;
2379   unsigned KMaskOp = -1U;
2380   if (X86II::isKMasked(TSFlags)) {
2381     // For k-zero-masked operations it is Ok to commute the first vector
2382     // operand. Unless this is an intrinsic instruction.
2383     // For regular k-masked operations a conservative choice is done as the
2384     // elements of the first vector operand, for which the corresponding bit
2385     // in the k-mask operand is set to 0, are copied to the result of the
2386     // instruction.
2387     // TODO/FIXME: The commute still may be legal if it is known that the
2388     // k-mask operand is set to either all ones or all zeroes.
2389     // It is also Ok to commute the 1st operand if all users of MI use only
2390     // the elements enabled by the k-mask operand. For example,
2391     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2392     //                                                     : v1[i];
2393     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2394     //                                  // Ok, to commute v1 in FMADD213PSZrk.
2395 
2396     // The k-mask operand has index = 2 for masked and zero-masked operations.
2397     KMaskOp = 2;
2398 
2399     // The operand with index = 1 is used as a source for those elements for
2400     // which the corresponding bit in the k-mask is set to 0.
2401     if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2402       FirstCommutableVecOp = 3;
2403 
2404     LastCommutableVecOp++;
2405   } else if (IsIntrinsic) {
2406     // Commuting the first operand of an intrinsic instruction isn't possible
2407     // unless we can prove that only the lowest element of the result is used.
2408     FirstCommutableVecOp = 2;
2409   }
2410 
2411   if (isMem(MI, LastCommutableVecOp))
2412     LastCommutableVecOp--;
2413 
2414   // Only the first RegOpsNum operands are commutable.
2415   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2416   // that the operand is not specified/fixed.
2417   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2418       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2419        SrcOpIdx1 == KMaskOp))
2420     return false;
2421   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2422       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2423        SrcOpIdx2 == KMaskOp))
2424     return false;
2425 
2426   // Look for two different register operands assumed to be commutable
2427   // regardless of the FMA opcode. The FMA opcode is adjusted later.
2428   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2429       SrcOpIdx2 == CommuteAnyOperandIndex) {
2430     unsigned CommutableOpIdx2 = SrcOpIdx2;
2431 
2432     // At least one of operands to be commuted is not specified and
2433     // this method is free to choose appropriate commutable operands.
2434     if (SrcOpIdx1 == SrcOpIdx2)
2435       // Both of operands are not fixed. By default set one of commutable
2436       // operands to the last register operand of the instruction.
2437       CommutableOpIdx2 = LastCommutableVecOp;
2438     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2439       // Only one of operands is not fixed.
2440       CommutableOpIdx2 = SrcOpIdx1;
2441 
2442     // CommutableOpIdx2 is well defined now. Let's choose another commutable
2443     // operand and assign its index to CommutableOpIdx1.
2444     Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
2445 
2446     unsigned CommutableOpIdx1;
2447     for (CommutableOpIdx1 = LastCommutableVecOp;
2448          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2449       // Just ignore and skip the k-mask operand.
2450       if (CommutableOpIdx1 == KMaskOp)
2451         continue;
2452 
2453       // The commuted operands must have different registers.
2454       // Otherwise, the commute transformation does not change anything and
2455       // is useless then.
2456       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
2457         break;
2458     }
2459 
2460     // No appropriate commutable operands were found.
2461     if (CommutableOpIdx1 < FirstCommutableVecOp)
2462       return false;
2463 
2464     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2465     // to return those values.
2466     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2467                               CommutableOpIdx1, CommutableOpIdx2))
2468       return false;
2469   }
2470 
2471   return true;
2472 }
2473 
2474 bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2475                                          unsigned &SrcOpIdx1,
2476                                          unsigned &SrcOpIdx2) const {
2477   const MCInstrDesc &Desc = MI.getDesc();
2478   if (!Desc.isCommutable())
2479     return false;
2480 
2481   switch (MI.getOpcode()) {
2482   case X86::CMPSDrr:
2483   case X86::CMPSSrr:
2484   case X86::CMPPDrri:
2485   case X86::CMPPSrri:
2486   case X86::VCMPSDrr:
2487   case X86::VCMPSSrr:
2488   case X86::VCMPPDrri:
2489   case X86::VCMPPSrri:
2490   case X86::VCMPPDYrri:
2491   case X86::VCMPPSYrri:
2492   case X86::VCMPSDZrr:
2493   case X86::VCMPSSZrr:
2494   case X86::VCMPPDZrri:
2495   case X86::VCMPPSZrri:
2496   case X86::VCMPSHZrr:
2497   case X86::VCMPPHZrri:
2498   case X86::VCMPPHZ128rri:
2499   case X86::VCMPPHZ256rri:
2500   case X86::VCMPPDZ128rri:
2501   case X86::VCMPPSZ128rri:
2502   case X86::VCMPPDZ256rri:
2503   case X86::VCMPPSZ256rri:
2504   case X86::VCMPPDZrrik:
2505   case X86::VCMPPSZrrik:
2506   case X86::VCMPPDZ128rrik:
2507   case X86::VCMPPSZ128rrik:
2508   case X86::VCMPPDZ256rrik:
2509   case X86::VCMPPSZ256rrik: {
2510     unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2511 
2512     // Float comparison can be safely commuted for
2513     // Ordered/Unordered/Equal/NotEqual tests
2514     unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2515     switch (Imm) {
2516     default:
2517       // EVEX versions can be commuted.
2518       if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2519         break;
2520       return false;
2521     case 0x00: // EQUAL
2522     case 0x03: // UNORDERED
2523     case 0x04: // NOT EQUAL
2524     case 0x07: // ORDERED
2525       break;
2526     }
2527 
2528     // The indices of the commutable operands are 1 and 2 (or 2 and 3
2529     // when masked).
2530     // Assign them to the returned operand indices here.
2531     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2532                                 2 + OpOffset);
2533   }
2534   case X86::MOVSSrr:
2535     // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2536     // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2537     // AVX implies sse4.1.
2538     if (Subtarget.hasSSE41())
2539       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2540     return false;
2541   case X86::SHUFPDrri:
2542     // We can commute this to MOVSD.
2543     if (MI.getOperand(3).getImm() == 0x02)
2544       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2545     return false;
2546   case X86::MOVHLPSrr:
2547   case X86::UNPCKHPDrr:
2548   case X86::VMOVHLPSrr:
2549   case X86::VUNPCKHPDrr:
2550   case X86::VMOVHLPSZrr:
2551   case X86::VUNPCKHPDZ128rr:
2552     if (Subtarget.hasSSE2())
2553       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2554     return false;
2555   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2556   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2557   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2558   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2559   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2560   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2561   case X86::VPTERNLOGDZrrik:
2562   case X86::VPTERNLOGDZ128rrik:
2563   case X86::VPTERNLOGDZ256rrik:
2564   case X86::VPTERNLOGQZrrik:
2565   case X86::VPTERNLOGQZ128rrik:
2566   case X86::VPTERNLOGQZ256rrik:
2567   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2568   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2569   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2570   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2571   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2572   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2573   case X86::VPTERNLOGDZ128rmbi:
2574   case X86::VPTERNLOGDZ256rmbi:
2575   case X86::VPTERNLOGDZrmbi:
2576   case X86::VPTERNLOGQZ128rmbi:
2577   case X86::VPTERNLOGQZ256rmbi:
2578   case X86::VPTERNLOGQZrmbi:
2579   case X86::VPTERNLOGDZ128rmbikz:
2580   case X86::VPTERNLOGDZ256rmbikz:
2581   case X86::VPTERNLOGDZrmbikz:
2582   case X86::VPTERNLOGQZ128rmbikz:
2583   case X86::VPTERNLOGQZ256rmbikz:
2584   case X86::VPTERNLOGQZrmbikz:
2585     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2586   case X86::VPDPWSSDYrr:
2587   case X86::VPDPWSSDrr:
2588   case X86::VPDPWSSDSYrr:
2589   case X86::VPDPWSSDSrr:
2590   case X86::VPDPWSSDZ128r:
2591   case X86::VPDPWSSDZ128rk:
2592   case X86::VPDPWSSDZ128rkz:
2593   case X86::VPDPWSSDZ256r:
2594   case X86::VPDPWSSDZ256rk:
2595   case X86::VPDPWSSDZ256rkz:
2596   case X86::VPDPWSSDZr:
2597   case X86::VPDPWSSDZrk:
2598   case X86::VPDPWSSDZrkz:
2599   case X86::VPDPWSSDSZ128r:
2600   case X86::VPDPWSSDSZ128rk:
2601   case X86::VPDPWSSDSZ128rkz:
2602   case X86::VPDPWSSDSZ256r:
2603   case X86::VPDPWSSDSZ256rk:
2604   case X86::VPDPWSSDSZ256rkz:
2605   case X86::VPDPWSSDSZr:
2606   case X86::VPDPWSSDSZrk:
2607   case X86::VPDPWSSDSZrkz:
2608   case X86::VPMADD52HUQZ128r:
2609   case X86::VPMADD52HUQZ128rk:
2610   case X86::VPMADD52HUQZ128rkz:
2611   case X86::VPMADD52HUQZ256r:
2612   case X86::VPMADD52HUQZ256rk:
2613   case X86::VPMADD52HUQZ256rkz:
2614   case X86::VPMADD52HUQZr:
2615   case X86::VPMADD52HUQZrk:
2616   case X86::VPMADD52HUQZrkz:
2617   case X86::VPMADD52LUQZ128r:
2618   case X86::VPMADD52LUQZ128rk:
2619   case X86::VPMADD52LUQZ128rkz:
2620   case X86::VPMADD52LUQZ256r:
2621   case X86::VPMADD52LUQZ256rk:
2622   case X86::VPMADD52LUQZ256rkz:
2623   case X86::VPMADD52LUQZr:
2624   case X86::VPMADD52LUQZrk:
2625   case X86::VPMADD52LUQZrkz:
2626   case X86::VFMADDCPHZr:
2627   case X86::VFMADDCPHZrk:
2628   case X86::VFMADDCPHZrkz:
2629   case X86::VFMADDCPHZ128r:
2630   case X86::VFMADDCPHZ128rk:
2631   case X86::VFMADDCPHZ128rkz:
2632   case X86::VFMADDCPHZ256r:
2633   case X86::VFMADDCPHZ256rk:
2634   case X86::VFMADDCPHZ256rkz:
2635   case X86::VFMADDCSHZr:
2636   case X86::VFMADDCSHZrk:
2637   case X86::VFMADDCSHZrkz: {
2638     unsigned CommutableOpIdx1 = 2;
2639     unsigned CommutableOpIdx2 = 3;
2640     if (X86II::isKMasked(Desc.TSFlags)) {
2641       // Skip the mask register.
2642       ++CommutableOpIdx1;
2643       ++CommutableOpIdx2;
2644     }
2645     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2646                               CommutableOpIdx1, CommutableOpIdx2))
2647       return false;
2648     if (!MI.getOperand(SrcOpIdx1).isReg() ||
2649         !MI.getOperand(SrcOpIdx2).isReg())
2650       // No idea.
2651       return false;
2652     return true;
2653   }
2654 
2655   default:
2656     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2657                                                       MI.getDesc().TSFlags);
2658     if (FMA3Group)
2659       return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2660                                            FMA3Group->isIntrinsic());
2661 
2662     // Handled masked instructions since we need to skip over the mask input
2663     // and the preserved input.
2664     if (X86II::isKMasked(Desc.TSFlags)) {
2665       // First assume that the first input is the mask operand and skip past it.
2666       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2667       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2668       // Check if the first input is tied. If there isn't one then we only
2669       // need to skip the mask operand which we did above.
2670       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2671                                              MCOI::TIED_TO) != -1)) {
2672         // If this is zero masking instruction with a tied operand, we need to
2673         // move the first index back to the first input since this must
2674         // be a 3 input instruction and we want the first two non-mask inputs.
2675         // Otherwise this is a 2 input instruction with a preserved input and
2676         // mask, so we need to move the indices to skip one more input.
2677         if (X86II::isKMergeMasked(Desc.TSFlags)) {
2678           ++CommutableOpIdx1;
2679           ++CommutableOpIdx2;
2680         } else {
2681           --CommutableOpIdx1;
2682         }
2683       }
2684 
2685       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2686                                 CommutableOpIdx1, CommutableOpIdx2))
2687         return false;
2688 
2689       if (!MI.getOperand(SrcOpIdx1).isReg() ||
2690           !MI.getOperand(SrcOpIdx2).isReg())
2691         // No idea.
2692         return false;
2693       return true;
2694     }
2695 
2696     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2697   }
2698   return false;
2699 }
2700 
2701 static bool isConvertibleLEA(MachineInstr *MI) {
2702   unsigned Opcode = MI->getOpcode();
2703   if (Opcode != X86::LEA32r && Opcode != X86::LEA64r &&
2704       Opcode != X86::LEA64_32r)
2705     return false;
2706 
2707   const MachineOperand &Scale = MI->getOperand(1 + X86::AddrScaleAmt);
2708   const MachineOperand &Disp = MI->getOperand(1 + X86::AddrDisp);
2709   const MachineOperand &Segment = MI->getOperand(1 + X86::AddrSegmentReg);
2710 
2711   if (Segment.getReg() != 0 || !Disp.isImm() || Disp.getImm() != 0 ||
2712       Scale.getImm() > 1)
2713     return false;
2714 
2715   return true;
2716 }
2717 
2718 bool X86InstrInfo::hasCommutePreference(MachineInstr &MI, bool &Commute) const {
2719   // Currently we're interested in following sequence only.
2720   //   r3 = lea r1, r2
2721   //   r5 = add r3, r4
2722   // Both r3 and r4 are killed in add, we hope the add instruction has the
2723   // operand order
2724   //   r5 = add r4, r3
2725   // So later in X86FixupLEAs the lea instruction can be rewritten as add.
2726   unsigned Opcode = MI.getOpcode();
2727   if (Opcode != X86::ADD32rr && Opcode != X86::ADD64rr)
2728     return false;
2729 
2730   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2731   Register Reg1 = MI.getOperand(1).getReg();
2732   Register Reg2 = MI.getOperand(2).getReg();
2733 
2734   // Check if Reg1 comes from LEA in the same MBB.
2735   if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg1)) {
2736     if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2737       Commute = true;
2738       return true;
2739     }
2740   }
2741 
2742   // Check if Reg2 comes from LEA in the same MBB.
2743   if (MachineInstr *Inst = MRI.getUniqueVRegDef(Reg2)) {
2744     if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
2745       Commute = false;
2746       return true;
2747     }
2748   }
2749 
2750   return false;
2751 }
2752 
2753 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2754   switch (MI.getOpcode()) {
2755   default: return X86::COND_INVALID;
2756   case X86::JCC_1:
2757     return static_cast<X86::CondCode>(
2758         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2759   }
2760 }
2761 
2762 /// Return condition code of a SETCC opcode.
2763 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2764   switch (MI.getOpcode()) {
2765   default: return X86::COND_INVALID;
2766   case X86::SETCCr: case X86::SETCCm:
2767     return static_cast<X86::CondCode>(
2768         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2769   }
2770 }
2771 
2772 /// Return condition code of a CMov opcode.
2773 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2774   switch (MI.getOpcode()) {
2775   default: return X86::COND_INVALID;
2776   case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2777   case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2778     return static_cast<X86::CondCode>(
2779         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2780   }
2781 }
2782 
2783 /// Return the inverse of the specified condition,
2784 /// e.g. turning COND_E to COND_NE.
2785 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2786   switch (CC) {
2787   default: llvm_unreachable("Illegal condition code!");
2788   case X86::COND_E:  return X86::COND_NE;
2789   case X86::COND_NE: return X86::COND_E;
2790   case X86::COND_L:  return X86::COND_GE;
2791   case X86::COND_LE: return X86::COND_G;
2792   case X86::COND_G:  return X86::COND_LE;
2793   case X86::COND_GE: return X86::COND_L;
2794   case X86::COND_B:  return X86::COND_AE;
2795   case X86::COND_BE: return X86::COND_A;
2796   case X86::COND_A:  return X86::COND_BE;
2797   case X86::COND_AE: return X86::COND_B;
2798   case X86::COND_S:  return X86::COND_NS;
2799   case X86::COND_NS: return X86::COND_S;
2800   case X86::COND_P:  return X86::COND_NP;
2801   case X86::COND_NP: return X86::COND_P;
2802   case X86::COND_O:  return X86::COND_NO;
2803   case X86::COND_NO: return X86::COND_O;
2804   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
2805   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2806   }
2807 }
2808 
2809 /// Assuming the flags are set by MI(a,b), return the condition code if we
2810 /// modify the instructions such that flags are set by MI(b,a).
2811 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2812   switch (CC) {
2813   default: return X86::COND_INVALID;
2814   case X86::COND_E:  return X86::COND_E;
2815   case X86::COND_NE: return X86::COND_NE;
2816   case X86::COND_L:  return X86::COND_G;
2817   case X86::COND_LE: return X86::COND_GE;
2818   case X86::COND_G:  return X86::COND_L;
2819   case X86::COND_GE: return X86::COND_LE;
2820   case X86::COND_B:  return X86::COND_A;
2821   case X86::COND_BE: return X86::COND_AE;
2822   case X86::COND_A:  return X86::COND_B;
2823   case X86::COND_AE: return X86::COND_BE;
2824   }
2825 }
2826 
2827 std::pair<X86::CondCode, bool>
2828 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2829   X86::CondCode CC = X86::COND_INVALID;
2830   bool NeedSwap = false;
2831   switch (Predicate) {
2832   default: break;
2833   // Floating-point Predicates
2834   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
2835   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
2836   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
2837   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
2838   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
2839   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
2840   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
2841   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
2842   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
2843   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
2844   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
2845   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
2846   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
2847   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2848 
2849   // Integer Predicates
2850   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
2851   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
2852   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
2853   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
2854   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
2855   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
2856   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
2857   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
2858   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
2859   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
2860   }
2861 
2862   return std::make_pair(CC, NeedSwap);
2863 }
2864 
2865 /// Return a setcc opcode based on whether it has memory operand.
2866 unsigned X86::getSETOpc(bool HasMemoryOperand) {
2867   return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2868 }
2869 
2870 /// Return a cmov opcode for the given register size in bytes, and operand type.
2871 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2872   switch(RegBytes) {
2873   default: llvm_unreachable("Illegal register size!");
2874   case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2875   case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2876   case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr;
2877   }
2878 }
2879 
2880 /// Get the VPCMP immediate for the given condition.
2881 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2882   switch (CC) {
2883   default: llvm_unreachable("Unexpected SETCC condition");
2884   case ISD::SETNE:  return 4;
2885   case ISD::SETEQ:  return 0;
2886   case ISD::SETULT:
2887   case ISD::SETLT: return 1;
2888   case ISD::SETUGT:
2889   case ISD::SETGT: return 6;
2890   case ISD::SETUGE:
2891   case ISD::SETGE: return 5;
2892   case ISD::SETULE:
2893   case ISD::SETLE: return 2;
2894   }
2895 }
2896 
2897 /// Get the VPCMP immediate if the operands are swapped.
2898 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2899   switch (Imm) {
2900   default: llvm_unreachable("Unreachable!");
2901   case 0x01: Imm = 0x06; break; // LT  -> NLE
2902   case 0x02: Imm = 0x05; break; // LE  -> NLT
2903   case 0x05: Imm = 0x02; break; // NLT -> LE
2904   case 0x06: Imm = 0x01; break; // NLE -> LT
2905   case 0x00: // EQ
2906   case 0x03: // FALSE
2907   case 0x04: // NE
2908   case 0x07: // TRUE
2909     break;
2910   }
2911 
2912   return Imm;
2913 }
2914 
2915 /// Get the VPCOM immediate if the operands are swapped.
2916 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2917   switch (Imm) {
2918   default: llvm_unreachable("Unreachable!");
2919   case 0x00: Imm = 0x02; break; // LT -> GT
2920   case 0x01: Imm = 0x03; break; // LE -> GE
2921   case 0x02: Imm = 0x00; break; // GT -> LT
2922   case 0x03: Imm = 0x01; break; // GE -> LE
2923   case 0x04: // EQ
2924   case 0x05: // NE
2925   case 0x06: // FALSE
2926   case 0x07: // TRUE
2927     break;
2928   }
2929 
2930   return Imm;
2931 }
2932 
2933 /// Get the VCMP immediate if the operands are swapped.
2934 unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2935   // Only need the lower 2 bits to distinquish.
2936   switch (Imm & 0x3) {
2937   default: llvm_unreachable("Unreachable!");
2938   case 0x00: case 0x03:
2939     // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2940     break;
2941   case 0x01: case 0x02:
2942     // Need to toggle bits 3:0. Bit 4 stays the same.
2943     Imm ^= 0xf;
2944     break;
2945   }
2946 
2947   return Imm;
2948 }
2949 
2950 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2951   switch (MI.getOpcode()) {
2952   case X86::TCRETURNdi:
2953   case X86::TCRETURNri:
2954   case X86::TCRETURNmi:
2955   case X86::TCRETURNdi64:
2956   case X86::TCRETURNri64:
2957   case X86::TCRETURNmi64:
2958     return true;
2959   default:
2960     return false;
2961   }
2962 }
2963 
2964 bool X86InstrInfo::canMakeTailCallConditional(
2965     SmallVectorImpl<MachineOperand> &BranchCond,
2966     const MachineInstr &TailCall) const {
2967   if (TailCall.getOpcode() != X86::TCRETURNdi &&
2968       TailCall.getOpcode() != X86::TCRETURNdi64) {
2969     // Only direct calls can be done with a conditional branch.
2970     return false;
2971   }
2972 
2973   const MachineFunction *MF = TailCall.getParent()->getParent();
2974   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2975     // Conditional tail calls confuse the Win64 unwinder.
2976     return false;
2977   }
2978 
2979   assert(BranchCond.size() == 1);
2980   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2981     // Can't make a conditional tail call with this condition.
2982     return false;
2983   }
2984 
2985   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2986   if (X86FI->getTCReturnAddrDelta() != 0 ||
2987       TailCall.getOperand(1).getImm() != 0) {
2988     // A conditional tail call cannot do any stack adjustment.
2989     return false;
2990   }
2991 
2992   return true;
2993 }
2994 
2995 void X86InstrInfo::replaceBranchWithTailCall(
2996     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2997     const MachineInstr &TailCall) const {
2998   assert(canMakeTailCallConditional(BranchCond, TailCall));
2999 
3000   MachineBasicBlock::iterator I = MBB.end();
3001   while (I != MBB.begin()) {
3002     --I;
3003     if (I->isDebugInstr())
3004       continue;
3005     if (!I->isBranch())
3006       assert(0 && "Can't find the branch to replace!");
3007 
3008     X86::CondCode CC = X86::getCondFromBranch(*I);
3009     assert(BranchCond.size() == 1);
3010     if (CC != BranchCond[0].getImm())
3011       continue;
3012 
3013     break;
3014   }
3015 
3016   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
3017                                                          : X86::TCRETURNdi64cc;
3018 
3019   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
3020   MIB->addOperand(TailCall.getOperand(0)); // Destination.
3021   MIB.addImm(0); // Stack offset (not used).
3022   MIB->addOperand(BranchCond[0]); // Condition.
3023   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
3024 
3025   // Add implicit uses and defs of all live regs potentially clobbered by the
3026   // call. This way they still appear live across the call.
3027   LivePhysRegs LiveRegs(getRegisterInfo());
3028   LiveRegs.addLiveOuts(MBB);
3029   SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
3030   LiveRegs.stepForward(*MIB, Clobbers);
3031   for (const auto &C : Clobbers) {
3032     MIB.addReg(C.first, RegState::Implicit);
3033     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
3034   }
3035 
3036   I->eraseFromParent();
3037 }
3038 
3039 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
3040 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
3041 // fallthrough MBB cannot be identified.
3042 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3043                                             MachineBasicBlock *TBB) {
3044   // Look for non-EHPad successors other than TBB. If we find exactly one, it
3045   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
3046   // and fallthrough MBB. If we find more than one, we cannot identify the
3047   // fallthrough MBB and should return nullptr.
3048   MachineBasicBlock *FallthroughBB = nullptr;
3049   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
3050     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
3051       continue;
3052     // Return a nullptr if we found more than one fallthrough successor.
3053     if (FallthroughBB && FallthroughBB != TBB)
3054       return nullptr;
3055     FallthroughBB = *SI;
3056   }
3057   return FallthroughBB;
3058 }
3059 
3060 bool X86InstrInfo::AnalyzeBranchImpl(
3061     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3062     SmallVectorImpl<MachineOperand> &Cond,
3063     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3064 
3065   // Start from the bottom of the block and work up, examining the
3066   // terminator instructions.
3067   MachineBasicBlock::iterator I = MBB.end();
3068   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3069   while (I != MBB.begin()) {
3070     --I;
3071     if (I->isDebugInstr())
3072       continue;
3073 
3074     // Working from the bottom, when we see a non-terminator instruction, we're
3075     // done.
3076     if (!isUnpredicatedTerminator(*I))
3077       break;
3078 
3079     // A terminator that isn't a branch can't easily be handled by this
3080     // analysis.
3081     if (!I->isBranch())
3082       return true;
3083 
3084     // Handle unconditional branches.
3085     if (I->getOpcode() == X86::JMP_1) {
3086       UnCondBrIter = I;
3087 
3088       if (!AllowModify) {
3089         TBB = I->getOperand(0).getMBB();
3090         continue;
3091       }
3092 
3093       // If the block has any instructions after a JMP, delete them.
3094       while (std::next(I) != MBB.end())
3095         std::next(I)->eraseFromParent();
3096 
3097       Cond.clear();
3098       FBB = nullptr;
3099 
3100       // Delete the JMP if it's equivalent to a fall-through.
3101       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3102         TBB = nullptr;
3103         I->eraseFromParent();
3104         I = MBB.end();
3105         UnCondBrIter = MBB.end();
3106         continue;
3107       }
3108 
3109       // TBB is used to indicate the unconditional destination.
3110       TBB = I->getOperand(0).getMBB();
3111       continue;
3112     }
3113 
3114     // Handle conditional branches.
3115     X86::CondCode BranchCode = X86::getCondFromBranch(*I);
3116     if (BranchCode == X86::COND_INVALID)
3117       return true;  // Can't handle indirect branch.
3118 
3119     // In practice we should never have an undef eflags operand, if we do
3120     // abort here as we are not prepared to preserve the flag.
3121     if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
3122       return true;
3123 
3124     // Working from the bottom, handle the first conditional branch.
3125     if (Cond.empty()) {
3126       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3127       if (AllowModify && UnCondBrIter != MBB.end() &&
3128           MBB.isLayoutSuccessor(TargetBB)) {
3129         // If we can modify the code and it ends in something like:
3130         //
3131         //     jCC L1
3132         //     jmp L2
3133         //   L1:
3134         //     ...
3135         //   L2:
3136         //
3137         // Then we can change this to:
3138         //
3139         //     jnCC L2
3140         //   L1:
3141         //     ...
3142         //   L2:
3143         //
3144         // Which is a bit more efficient.
3145         // We conditionally jump to the fall-through block.
3146         BranchCode = GetOppositeBranchCondition(BranchCode);
3147         MachineBasicBlock::iterator OldInst = I;
3148 
3149         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
3150           .addMBB(UnCondBrIter->getOperand(0).getMBB())
3151           .addImm(BranchCode);
3152         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3153           .addMBB(TargetBB);
3154 
3155         OldInst->eraseFromParent();
3156         UnCondBrIter->eraseFromParent();
3157 
3158         // Restart the analysis.
3159         UnCondBrIter = MBB.end();
3160         I = MBB.end();
3161         continue;
3162       }
3163 
3164       FBB = TBB;
3165       TBB = I->getOperand(0).getMBB();
3166       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3167       CondBranches.push_back(&*I);
3168       continue;
3169     }
3170 
3171     // Handle subsequent conditional branches. Only handle the case where all
3172     // conditional branches branch to the same destination and their condition
3173     // opcodes fit one of the special multi-branch idioms.
3174     assert(Cond.size() == 1);
3175     assert(TBB);
3176 
3177     // If the conditions are the same, we can leave them alone.
3178     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3179     auto NewTBB = I->getOperand(0).getMBB();
3180     if (OldBranchCode == BranchCode && TBB == NewTBB)
3181       continue;
3182 
3183     // If they differ, see if they fit one of the known patterns. Theoretically,
3184     // we could handle more patterns here, but we shouldn't expect to see them
3185     // if instruction selection has done a reasonable job.
3186     if (TBB == NewTBB &&
3187                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3188                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3189       BranchCode = X86::COND_NE_OR_P;
3190     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3191                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3192       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
3193         return true;
3194 
3195       // X86::COND_E_AND_NP usually has two different branch destinations.
3196       //
3197       // JP B1
3198       // JE B2
3199       // JMP B1
3200       // B1:
3201       // B2:
3202       //
3203       // Here this condition branches to B2 only if NP && E. It has another
3204       // equivalent form:
3205       //
3206       // JNE B1
3207       // JNP B2
3208       // JMP B1
3209       // B1:
3210       // B2:
3211       //
3212       // Similarly it branches to B2 only if E && NP. That is why this condition
3213       // is named with COND_E_AND_NP.
3214       BranchCode = X86::COND_E_AND_NP;
3215     } else
3216       return true;
3217 
3218     // Update the MachineOperand.
3219     Cond[0].setImm(BranchCode);
3220     CondBranches.push_back(&*I);
3221   }
3222 
3223   return false;
3224 }
3225 
3226 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3227                                  MachineBasicBlock *&TBB,
3228                                  MachineBasicBlock *&FBB,
3229                                  SmallVectorImpl<MachineOperand> &Cond,
3230                                  bool AllowModify) const {
3231   SmallVector<MachineInstr *, 4> CondBranches;
3232   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3233 }
3234 
3235 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
3236                                           MachineBranchPredicate &MBP,
3237                                           bool AllowModify) const {
3238   using namespace std::placeholders;
3239 
3240   SmallVector<MachineOperand, 4> Cond;
3241   SmallVector<MachineInstr *, 4> CondBranches;
3242   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3243                         AllowModify))
3244     return true;
3245 
3246   if (Cond.size() != 1)
3247     return true;
3248 
3249   assert(MBP.TrueDest && "expected!");
3250 
3251   if (!MBP.FalseDest)
3252     MBP.FalseDest = MBB.getNextNode();
3253 
3254   const TargetRegisterInfo *TRI = &getRegisterInfo();
3255 
3256   MachineInstr *ConditionDef = nullptr;
3257   bool SingleUseCondition = true;
3258 
3259   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
3260     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
3261       ConditionDef = &*I;
3262       break;
3263     }
3264 
3265     if (I->readsRegister(X86::EFLAGS, TRI))
3266       SingleUseCondition = false;
3267   }
3268 
3269   if (!ConditionDef)
3270     return true;
3271 
3272   if (SingleUseCondition) {
3273     for (auto *Succ : MBB.successors())
3274       if (Succ->isLiveIn(X86::EFLAGS))
3275         SingleUseCondition = false;
3276   }
3277 
3278   MBP.ConditionDef = ConditionDef;
3279   MBP.SingleUseCondition = SingleUseCondition;
3280 
3281   // Currently we only recognize the simple pattern:
3282   //
3283   //   test %reg, %reg
3284   //   je %label
3285   //
3286   const unsigned TestOpcode =
3287       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3288 
3289   if (ConditionDef->getOpcode() == TestOpcode &&
3290       ConditionDef->getNumOperands() == 3 &&
3291       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3292       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3293     MBP.LHS = ConditionDef->getOperand(0);
3294     MBP.RHS = MachineOperand::CreateImm(0);
3295     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3296                         ? MachineBranchPredicate::PRED_NE
3297                         : MachineBranchPredicate::PRED_EQ;
3298     return false;
3299   }
3300 
3301   return true;
3302 }
3303 
3304 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
3305                                     int *BytesRemoved) const {
3306   assert(!BytesRemoved && "code size not handled");
3307 
3308   MachineBasicBlock::iterator I = MBB.end();
3309   unsigned Count = 0;
3310 
3311   while (I != MBB.begin()) {
3312     --I;
3313     if (I->isDebugInstr())
3314       continue;
3315     if (I->getOpcode() != X86::JMP_1 &&
3316         X86::getCondFromBranch(*I) == X86::COND_INVALID)
3317       break;
3318     // Remove the branch.
3319     I->eraseFromParent();
3320     I = MBB.end();
3321     ++Count;
3322   }
3323 
3324   return Count;
3325 }
3326 
3327 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
3328                                     MachineBasicBlock *TBB,
3329                                     MachineBasicBlock *FBB,
3330                                     ArrayRef<MachineOperand> Cond,
3331                                     const DebugLoc &DL,
3332                                     int *BytesAdded) const {
3333   // Shouldn't be a fall through.
3334   assert(TBB && "insertBranch must not be told to insert a fallthrough");
3335   assert((Cond.size() == 1 || Cond.size() == 0) &&
3336          "X86 branch conditions have one component!");
3337   assert(!BytesAdded && "code size not handled");
3338 
3339   if (Cond.empty()) {
3340     // Unconditional branch?
3341     assert(!FBB && "Unconditional branch with multiple successors!");
3342     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3343     return 1;
3344   }
3345 
3346   // If FBB is null, it is implied to be a fall-through block.
3347   bool FallThru = FBB == nullptr;
3348 
3349   // Conditional branch.
3350   unsigned Count = 0;
3351   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3352   switch (CC) {
3353   case X86::COND_NE_OR_P:
3354     // Synthesize NE_OR_P with two branches.
3355     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
3356     ++Count;
3357     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
3358     ++Count;
3359     break;
3360   case X86::COND_E_AND_NP:
3361     // Use the next block of MBB as FBB if it is null.
3362     if (FBB == nullptr) {
3363       FBB = getFallThroughMBB(&MBB, TBB);
3364       assert(FBB && "MBB cannot be the last block in function when the false "
3365                     "body is a fall-through.");
3366     }
3367     // Synthesize COND_E_AND_NP with two branches.
3368     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
3369     ++Count;
3370     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
3371     ++Count;
3372     break;
3373   default: {
3374     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
3375     ++Count;
3376   }
3377   }
3378   if (!FallThru) {
3379     // Two-way Conditional branch. Insert the second branch.
3380     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3381     ++Count;
3382   }
3383   return Count;
3384 }
3385 
3386 bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
3387                                    ArrayRef<MachineOperand> Cond,
3388                                    Register DstReg, Register TrueReg,
3389                                    Register FalseReg, int &CondCycles,
3390                                    int &TrueCycles, int &FalseCycles) const {
3391   // Not all subtargets have cmov instructions.
3392   if (!Subtarget.hasCMov())
3393     return false;
3394   if (Cond.size() != 1)
3395     return false;
3396   // We cannot do the composite conditions, at least not in SSA form.
3397   if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
3398     return false;
3399 
3400   // Check register classes.
3401   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3402   const TargetRegisterClass *RC =
3403     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3404   if (!RC)
3405     return false;
3406 
3407   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3408   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3409       X86::GR32RegClass.hasSubClassEq(RC) ||
3410       X86::GR64RegClass.hasSubClassEq(RC)) {
3411     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3412     // Bridge. Probably Ivy Bridge as well.
3413     CondCycles = 2;
3414     TrueCycles = 2;
3415     FalseCycles = 2;
3416     return true;
3417   }
3418 
3419   // Can't do vectors.
3420   return false;
3421 }
3422 
3423 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3424                                 MachineBasicBlock::iterator I,
3425                                 const DebugLoc &DL, Register DstReg,
3426                                 ArrayRef<MachineOperand> Cond, Register TrueReg,
3427                                 Register FalseReg) const {
3428   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3429   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3430   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
3431   assert(Cond.size() == 1 && "Invalid Cond array");
3432   unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
3433                                     false /*HasMemoryOperand*/);
3434   BuildMI(MBB, I, DL, get(Opc), DstReg)
3435       .addReg(FalseReg)
3436       .addReg(TrueReg)
3437       .addImm(Cond[0].getImm());
3438 }
3439 
3440 /// Test if the given register is a physical h register.
3441 static bool isHReg(unsigned Reg) {
3442   return X86::GR8_ABCD_HRegClass.contains(Reg);
3443 }
3444 
3445 // Try and copy between VR128/VR64 and GR64 registers.
3446 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3447                                         const X86Subtarget &Subtarget) {
3448   bool HasAVX = Subtarget.hasAVX();
3449   bool HasAVX512 = Subtarget.hasAVX512();
3450 
3451   // SrcReg(MaskReg) -> DestReg(GR64)
3452   // SrcReg(MaskReg) -> DestReg(GR32)
3453 
3454   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3455   if (X86::VK16RegClass.contains(SrcReg)) {
3456     if (X86::GR64RegClass.contains(DestReg)) {
3457       assert(Subtarget.hasBWI());
3458       return X86::KMOVQrk;
3459     }
3460     if (X86::GR32RegClass.contains(DestReg))
3461       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
3462   }
3463 
3464   // SrcReg(GR64) -> DestReg(MaskReg)
3465   // SrcReg(GR32) -> DestReg(MaskReg)
3466 
3467   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3468   if (X86::VK16RegClass.contains(DestReg)) {
3469     if (X86::GR64RegClass.contains(SrcReg)) {
3470       assert(Subtarget.hasBWI());
3471       return X86::KMOVQkr;
3472     }
3473     if (X86::GR32RegClass.contains(SrcReg))
3474       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
3475   }
3476 
3477 
3478   // SrcReg(VR128) -> DestReg(GR64)
3479   // SrcReg(VR64)  -> DestReg(GR64)
3480   // SrcReg(GR64)  -> DestReg(VR128)
3481   // SrcReg(GR64)  -> DestReg(VR64)
3482 
3483   if (X86::GR64RegClass.contains(DestReg)) {
3484     if (X86::VR128XRegClass.contains(SrcReg))
3485       // Copy from a VR128 register to a GR64 register.
3486       return HasAVX512 ? X86::VMOVPQIto64Zrr :
3487              HasAVX    ? X86::VMOVPQIto64rr  :
3488                          X86::MOVPQIto64rr;
3489     if (X86::VR64RegClass.contains(SrcReg))
3490       // Copy from a VR64 register to a GR64 register.
3491       return X86::MMX_MOVD64from64rr;
3492   } else if (X86::GR64RegClass.contains(SrcReg)) {
3493     // Copy from a GR64 register to a VR128 register.
3494     if (X86::VR128XRegClass.contains(DestReg))
3495       return HasAVX512 ? X86::VMOV64toPQIZrr :
3496              HasAVX    ? X86::VMOV64toPQIrr  :
3497                          X86::MOV64toPQIrr;
3498     // Copy from a GR64 register to a VR64 register.
3499     if (X86::VR64RegClass.contains(DestReg))
3500       return X86::MMX_MOVD64to64rr;
3501   }
3502 
3503   // SrcReg(VR128) -> DestReg(GR32)
3504   // SrcReg(GR32)  -> DestReg(VR128)
3505 
3506   if (X86::GR32RegClass.contains(DestReg) &&
3507       X86::VR128XRegClass.contains(SrcReg))
3508     // Copy from a VR128 register to a GR32 register.
3509     return HasAVX512 ? X86::VMOVPDI2DIZrr :
3510            HasAVX    ? X86::VMOVPDI2DIrr  :
3511                        X86::MOVPDI2DIrr;
3512 
3513   if (X86::VR128XRegClass.contains(DestReg) &&
3514       X86::GR32RegClass.contains(SrcReg))
3515     // Copy from a VR128 register to a VR128 register.
3516     return HasAVX512 ? X86::VMOVDI2PDIZrr :
3517            HasAVX    ? X86::VMOVDI2PDIrr  :
3518                        X86::MOVDI2PDIrr;
3519   return 0;
3520 }
3521 
3522 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3523                                MachineBasicBlock::iterator MI,
3524                                const DebugLoc &DL, MCRegister DestReg,
3525                                MCRegister SrcReg, bool KillSrc) const {
3526   // First deal with the normal symmetric copies.
3527   bool HasAVX = Subtarget.hasAVX();
3528   bool HasVLX = Subtarget.hasVLX();
3529   unsigned Opc = 0;
3530   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3531     Opc = X86::MOV64rr;
3532   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3533     Opc = X86::MOV32rr;
3534   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3535     Opc = X86::MOV16rr;
3536   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3537     // Copying to or from a physical H register on x86-64 requires a NOREX
3538     // move.  Otherwise use a normal move.
3539     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3540         Subtarget.is64Bit()) {
3541       Opc = X86::MOV8rr_NOREX;
3542       // Both operands must be encodable without an REX prefix.
3543       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3544              "8-bit H register can not be copied outside GR8_NOREX");
3545     } else
3546       Opc = X86::MOV8rr;
3547   }
3548   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3549     Opc = X86::MMX_MOVQ64rr;
3550   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3551     if (HasVLX)
3552       Opc = X86::VMOVAPSZ128rr;
3553     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3554       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3555     else {
3556       // If this an extended register and we don't have VLX we need to use a
3557       // 512-bit move.
3558       Opc = X86::VMOVAPSZrr;
3559       const TargetRegisterInfo *TRI = &getRegisterInfo();
3560       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3561                                          &X86::VR512RegClass);
3562       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3563                                         &X86::VR512RegClass);
3564     }
3565   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3566     if (HasVLX)
3567       Opc = X86::VMOVAPSZ256rr;
3568     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3569       Opc = X86::VMOVAPSYrr;
3570     else {
3571       // If this an extended register and we don't have VLX we need to use a
3572       // 512-bit move.
3573       Opc = X86::VMOVAPSZrr;
3574       const TargetRegisterInfo *TRI = &getRegisterInfo();
3575       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3576                                          &X86::VR512RegClass);
3577       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3578                                         &X86::VR512RegClass);
3579     }
3580   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3581     Opc = X86::VMOVAPSZrr;
3582   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3583   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3584     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3585   if (!Opc)
3586     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3587 
3588   if (Opc) {
3589     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3590       .addReg(SrcReg, getKillRegState(KillSrc));
3591     return;
3592   }
3593 
3594   if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3595     // FIXME: We use a fatal error here because historically LLVM has tried
3596     // lower some of these physreg copies and we want to ensure we get
3597     // reasonable bug reports if someone encounters a case no other testing
3598     // found. This path should be removed after the LLVM 7 release.
3599     report_fatal_error("Unable to copy EFLAGS physical register!");
3600   }
3601 
3602   LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3603                     << RI.getName(DestReg) << '\n');
3604   report_fatal_error("Cannot emit physreg copy instruction");
3605 }
3606 
3607 Optional<DestSourcePair>
3608 X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
3609   if (MI.isMoveReg())
3610     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
3611   return None;
3612 }
3613 
3614 static unsigned getLoadStoreRegOpcode(Register Reg,
3615                                       const TargetRegisterClass *RC,
3616                                       bool IsStackAligned,
3617                                       const X86Subtarget &STI, bool load) {
3618   bool HasAVX = STI.hasAVX();
3619   bool HasAVX512 = STI.hasAVX512();
3620   bool HasVLX = STI.hasVLX();
3621 
3622   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3623   default:
3624     llvm_unreachable("Unknown spill size");
3625   case 1:
3626     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3627     if (STI.is64Bit())
3628       // Copying to or from a physical H register on x86-64 requires a NOREX
3629       // move.  Otherwise use a normal move.
3630       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3631         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3632     return load ? X86::MOV8rm : X86::MOV8mr;
3633   case 2:
3634     if (X86::VK16RegClass.hasSubClassEq(RC))
3635       return load ? X86::KMOVWkm : X86::KMOVWmk;
3636     if (X86::FR16XRegClass.hasSubClassEq(RC)) {
3637       assert(STI.hasFP16());
3638       return load ? X86::VMOVSHZrm_alt : X86::VMOVSHZmr;
3639     }
3640     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3641     return load ? X86::MOV16rm : X86::MOV16mr;
3642   case 4:
3643     if (X86::GR32RegClass.hasSubClassEq(RC))
3644       return load ? X86::MOV32rm : X86::MOV32mr;
3645     if (X86::FR32XRegClass.hasSubClassEq(RC))
3646       return load ?
3647         (HasAVX512 ? X86::VMOVSSZrm_alt :
3648          HasAVX    ? X86::VMOVSSrm_alt :
3649                      X86::MOVSSrm_alt) :
3650         (HasAVX512 ? X86::VMOVSSZmr :
3651          HasAVX    ? X86::VMOVSSmr :
3652                      X86::MOVSSmr);
3653     if (X86::RFP32RegClass.hasSubClassEq(RC))
3654       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3655     if (X86::VK32RegClass.hasSubClassEq(RC)) {
3656       assert(STI.hasBWI() && "KMOVD requires BWI");
3657       return load ? X86::KMOVDkm : X86::KMOVDmk;
3658     }
3659     // All of these mask pair classes have the same spill size, the same kind
3660     // of kmov instructions can be used with all of them.
3661     if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3662         X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3663         X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3664         X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3665         X86::VK16PAIRRegClass.hasSubClassEq(RC))
3666       return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3667     llvm_unreachable("Unknown 4-byte regclass");
3668   case 8:
3669     if (X86::GR64RegClass.hasSubClassEq(RC))
3670       return load ? X86::MOV64rm : X86::MOV64mr;
3671     if (X86::FR64XRegClass.hasSubClassEq(RC))
3672       return load ?
3673         (HasAVX512 ? X86::VMOVSDZrm_alt :
3674          HasAVX    ? X86::VMOVSDrm_alt :
3675                      X86::MOVSDrm_alt) :
3676         (HasAVX512 ? X86::VMOVSDZmr :
3677          HasAVX    ? X86::VMOVSDmr :
3678                      X86::MOVSDmr);
3679     if (X86::VR64RegClass.hasSubClassEq(RC))
3680       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3681     if (X86::RFP64RegClass.hasSubClassEq(RC))
3682       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3683     if (X86::VK64RegClass.hasSubClassEq(RC)) {
3684       assert(STI.hasBWI() && "KMOVQ requires BWI");
3685       return load ? X86::KMOVQkm : X86::KMOVQmk;
3686     }
3687     llvm_unreachable("Unknown 8-byte regclass");
3688   case 10:
3689     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3690     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3691   case 16: {
3692     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3693       // If stack is realigned we can use aligned stores.
3694       if (IsStackAligned)
3695         return load ?
3696           (HasVLX    ? X86::VMOVAPSZ128rm :
3697            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3698            HasAVX    ? X86::VMOVAPSrm :
3699                        X86::MOVAPSrm):
3700           (HasVLX    ? X86::VMOVAPSZ128mr :
3701            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3702            HasAVX    ? X86::VMOVAPSmr :
3703                        X86::MOVAPSmr);
3704       else
3705         return load ?
3706           (HasVLX    ? X86::VMOVUPSZ128rm :
3707            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3708            HasAVX    ? X86::VMOVUPSrm :
3709                        X86::MOVUPSrm):
3710           (HasVLX    ? X86::VMOVUPSZ128mr :
3711            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3712            HasAVX    ? X86::VMOVUPSmr :
3713                        X86::MOVUPSmr);
3714     }
3715     if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3716       if (STI.is64Bit())
3717         return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3718       else
3719         return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3720     }
3721     llvm_unreachable("Unknown 16-byte regclass");
3722   }
3723   case 32:
3724     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3725     // If stack is realigned we can use aligned stores.
3726     if (IsStackAligned)
3727       return load ?
3728         (HasVLX    ? X86::VMOVAPSZ256rm :
3729          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3730                      X86::VMOVAPSYrm) :
3731         (HasVLX    ? X86::VMOVAPSZ256mr :
3732          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3733                      X86::VMOVAPSYmr);
3734     else
3735       return load ?
3736         (HasVLX    ? X86::VMOVUPSZ256rm :
3737          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3738                      X86::VMOVUPSYrm) :
3739         (HasVLX    ? X86::VMOVUPSZ256mr :
3740          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3741                      X86::VMOVUPSYmr);
3742   case 64:
3743     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3744     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3745     if (IsStackAligned)
3746       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3747     else
3748       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3749   }
3750 }
3751 
3752 Optional<ExtAddrMode>
3753 X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
3754                                       const TargetRegisterInfo *TRI) const {
3755   const MCInstrDesc &Desc = MemI.getDesc();
3756   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3757   if (MemRefBegin < 0)
3758     return None;
3759 
3760   MemRefBegin += X86II::getOperandBias(Desc);
3761 
3762   auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg);
3763   if (!BaseOp.isReg()) // Can be an MO_FrameIndex
3764     return None;
3765 
3766   const MachineOperand &DispMO = MemI.getOperand(MemRefBegin + X86::AddrDisp);
3767   // Displacement can be symbolic
3768   if (!DispMO.isImm())
3769     return None;
3770 
3771   ExtAddrMode AM;
3772   AM.BaseReg = BaseOp.getReg();
3773   AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg();
3774   AM.Scale = MemI.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm();
3775   AM.Displacement = DispMO.getImm();
3776   return AM;
3777 }
3778 
3779 bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
3780                                            const Register Reg,
3781                                            int64_t &ImmVal) const {
3782   if (MI.getOpcode() != X86::MOV32ri && MI.getOpcode() != X86::MOV64ri)
3783     return false;
3784   // Mov Src can be a global address.
3785   if (!MI.getOperand(1).isImm() || MI.getOperand(0).getReg() != Reg)
3786     return false;
3787   ImmVal = MI.getOperand(1).getImm();
3788   return true;
3789 }
3790 
3791 bool X86InstrInfo::preservesZeroValueInReg(
3792     const MachineInstr *MI, const Register NullValueReg,
3793     const TargetRegisterInfo *TRI) const {
3794   if (!MI->modifiesRegister(NullValueReg, TRI))
3795     return true;
3796   switch (MI->getOpcode()) {
3797   // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
3798   // X.
3799   case X86::SHR64ri:
3800   case X86::SHR32ri:
3801   case X86::SHL64ri:
3802   case X86::SHL32ri:
3803     assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&
3804            "expected for shift opcode!");
3805     return MI->getOperand(0).getReg() == NullValueReg &&
3806            MI->getOperand(1).getReg() == NullValueReg;
3807   // Zero extend of a sub-reg of NullValueReg into itself does not change the
3808   // null value.
3809   case X86::MOV32rr:
3810     return llvm::all_of(MI->operands(), [&](const MachineOperand &MO) {
3811       return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
3812     });
3813   default:
3814     return false;
3815   }
3816   llvm_unreachable("Should be handled above!");
3817 }
3818 
3819 bool X86InstrInfo::getMemOperandsWithOffsetWidth(
3820     const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
3821     int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3822     const TargetRegisterInfo *TRI) const {
3823   const MCInstrDesc &Desc = MemOp.getDesc();
3824   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3825   if (MemRefBegin < 0)
3826     return false;
3827 
3828   MemRefBegin += X86II::getOperandBias(Desc);
3829 
3830   const MachineOperand *BaseOp =
3831       &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3832   if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3833     return false;
3834 
3835   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3836     return false;
3837 
3838   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3839       X86::NoRegister)
3840     return false;
3841 
3842   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3843 
3844   // Displacement can be symbolic
3845   if (!DispMO.isImm())
3846     return false;
3847 
3848   Offset = DispMO.getImm();
3849 
3850   if (!BaseOp->isReg())
3851     return false;
3852 
3853   OffsetIsScalable = false;
3854   // FIXME: Relying on memoperands() may not be right thing to do here. Check
3855   // with X86 maintainers, and fix it accordingly. For now, it is ok, since
3856   // there is no use of `Width` for X86 back-end at the moment.
3857   Width =
3858       !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0;
3859   BaseOps.push_back(BaseOp);
3860   return true;
3861 }
3862 
3863 static unsigned getStoreRegOpcode(Register SrcReg,
3864                                   const TargetRegisterClass *RC,
3865                                   bool IsStackAligned,
3866                                   const X86Subtarget &STI) {
3867   return getLoadStoreRegOpcode(SrcReg, RC, IsStackAligned, STI, false);
3868 }
3869 
3870 static unsigned getLoadRegOpcode(Register DestReg,
3871                                  const TargetRegisterClass *RC,
3872                                  bool IsStackAligned, const X86Subtarget &STI) {
3873   return getLoadStoreRegOpcode(DestReg, RC, IsStackAligned, STI, true);
3874 }
3875 
3876 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3877                                        MachineBasicBlock::iterator MI,
3878                                        Register SrcReg, bool isKill, int FrameIdx,
3879                                        const TargetRegisterClass *RC,
3880                                        const TargetRegisterInfo *TRI) const {
3881   const MachineFunction &MF = *MBB.getParent();
3882   const MachineFrameInfo &MFI = MF.getFrameInfo();
3883   assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3884          "Stack slot too small for store");
3885   if (RC->getID() == X86::TILERegClassID) {
3886     unsigned Opc = X86::TILESTORED;
3887     // tilestored %tmm, (%sp, %idx)
3888     MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3889     Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3890     BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3891     MachineInstr *NewMI =
3892         addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3893             .addReg(SrcReg, getKillRegState(isKill));
3894     MachineOperand &MO = NewMI->getOperand(2);
3895     MO.setReg(VirtReg);
3896     MO.setIsKill(true);
3897   } else {
3898     unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3899     bool isAligned =
3900         (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3901         (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3902     unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3903     addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3904         .addReg(SrcReg, getKillRegState(isKill));
3905   }
3906 }
3907 
3908 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3909                                         MachineBasicBlock::iterator MI,
3910                                         Register DestReg, int FrameIdx,
3911                                         const TargetRegisterClass *RC,
3912                                         const TargetRegisterInfo *TRI) const {
3913   if (RC->getID() == X86::TILERegClassID) {
3914     unsigned Opc = X86::TILELOADD;
3915     // tileloadd (%sp, %idx), %tmm
3916     MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
3917     Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3918     MachineInstr *NewMI =
3919         BuildMI(MBB, MI, DebugLoc(), get(X86::MOV64ri), VirtReg).addImm(64);
3920     NewMI = addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3921                               FrameIdx);
3922     MachineOperand &MO = NewMI->getOperand(3);
3923     MO.setReg(VirtReg);
3924     MO.setIsKill(true);
3925   } else {
3926     const MachineFunction &MF = *MBB.getParent();
3927     const MachineFrameInfo &MFI = MF.getFrameInfo();
3928     unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3929     bool isAligned =
3930         (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3931         (RI.canRealignStack(MF) && !MFI.isFixedObjectIndex(FrameIdx));
3932     unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3933     addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg),
3934                       FrameIdx);
3935   }
3936 }
3937 
3938 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
3939                                   Register &SrcReg2, int64_t &CmpMask,
3940                                   int64_t &CmpValue) const {
3941   switch (MI.getOpcode()) {
3942   default: break;
3943   case X86::CMP64ri32:
3944   case X86::CMP64ri8:
3945   case X86::CMP32ri:
3946   case X86::CMP32ri8:
3947   case X86::CMP16ri:
3948   case X86::CMP16ri8:
3949   case X86::CMP8ri:
3950     SrcReg = MI.getOperand(0).getReg();
3951     SrcReg2 = 0;
3952     if (MI.getOperand(1).isImm()) {
3953       CmpMask = ~0;
3954       CmpValue = MI.getOperand(1).getImm();
3955     } else {
3956       CmpMask = CmpValue = 0;
3957     }
3958     return true;
3959   // A SUB can be used to perform comparison.
3960   case X86::SUB64rm:
3961   case X86::SUB32rm:
3962   case X86::SUB16rm:
3963   case X86::SUB8rm:
3964     SrcReg = MI.getOperand(1).getReg();
3965     SrcReg2 = 0;
3966     CmpMask = 0;
3967     CmpValue = 0;
3968     return true;
3969   case X86::SUB64rr:
3970   case X86::SUB32rr:
3971   case X86::SUB16rr:
3972   case X86::SUB8rr:
3973     SrcReg = MI.getOperand(1).getReg();
3974     SrcReg2 = MI.getOperand(2).getReg();
3975     CmpMask = 0;
3976     CmpValue = 0;
3977     return true;
3978   case X86::SUB64ri32:
3979   case X86::SUB64ri8:
3980   case X86::SUB32ri:
3981   case X86::SUB32ri8:
3982   case X86::SUB16ri:
3983   case X86::SUB16ri8:
3984   case X86::SUB8ri:
3985     SrcReg = MI.getOperand(1).getReg();
3986     SrcReg2 = 0;
3987     if (MI.getOperand(2).isImm()) {
3988       CmpMask = ~0;
3989       CmpValue = MI.getOperand(2).getImm();
3990     } else {
3991       CmpMask = CmpValue = 0;
3992     }
3993     return true;
3994   case X86::CMP64rr:
3995   case X86::CMP32rr:
3996   case X86::CMP16rr:
3997   case X86::CMP8rr:
3998     SrcReg = MI.getOperand(0).getReg();
3999     SrcReg2 = MI.getOperand(1).getReg();
4000     CmpMask = 0;
4001     CmpValue = 0;
4002     return true;
4003   case X86::TEST8rr:
4004   case X86::TEST16rr:
4005   case X86::TEST32rr:
4006   case X86::TEST64rr:
4007     SrcReg = MI.getOperand(0).getReg();
4008     if (MI.getOperand(1).getReg() != SrcReg)
4009       return false;
4010     // Compare against zero.
4011     SrcReg2 = 0;
4012     CmpMask = ~0;
4013     CmpValue = 0;
4014     return true;
4015   }
4016   return false;
4017 }
4018 
4019 /// Check whether the first instruction, whose only
4020 /// purpose is to update flags, can be made redundant.
4021 /// CMPrr can be made redundant by SUBrr if the operands are the same.
4022 /// This function can be extended later on.
4023 /// SrcReg, SrcRegs: register operands for FlagI.
4024 /// ImmValue: immediate for FlagI if it takes an immediate.
4025 inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
4026                                         Register SrcReg, Register SrcReg2,
4027                                         int64_t ImmMask, int64_t ImmValue,
4028                                         const MachineInstr &OI) {
4029   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
4030        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
4031        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
4032        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
4033       ((OI.getOperand(1).getReg() == SrcReg &&
4034         OI.getOperand(2).getReg() == SrcReg2) ||
4035        (OI.getOperand(1).getReg() == SrcReg2 &&
4036         OI.getOperand(2).getReg() == SrcReg)))
4037     return true;
4038 
4039   if (ImmMask != 0 &&
4040       ((FlagI.getOpcode() == X86::CMP64ri32 &&
4041         OI.getOpcode() == X86::SUB64ri32) ||
4042        (FlagI.getOpcode() == X86::CMP64ri8 &&
4043         OI.getOpcode() == X86::SUB64ri8) ||
4044        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
4045        (FlagI.getOpcode() == X86::CMP32ri8 &&
4046         OI.getOpcode() == X86::SUB32ri8) ||
4047        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
4048        (FlagI.getOpcode() == X86::CMP16ri8 &&
4049         OI.getOpcode() == X86::SUB16ri8) ||
4050        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
4051       OI.getOperand(1).getReg() == SrcReg &&
4052       OI.getOperand(2).getImm() == ImmValue)
4053     return true;
4054   return false;
4055 }
4056 
4057 /// Check whether the definition can be converted
4058 /// to remove a comparison against zero.
4059 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
4060                                     bool &ClearsOverflowFlag) {
4061   NoSignFlag = false;
4062   ClearsOverflowFlag = false;
4063 
4064   switch (MI.getOpcode()) {
4065   default: return false;
4066 
4067   // The shift instructions only modify ZF if their shift count is non-zero.
4068   // N.B.: The processor truncates the shift count depending on the encoding.
4069   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
4070   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
4071      return getTruncatedShiftCount(MI, 2) != 0;
4072 
4073   // Some left shift instructions can be turned into LEA instructions but only
4074   // if their flags aren't used. Avoid transforming such instructions.
4075   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
4076     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4077     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4078     return ShAmt != 0;
4079   }
4080 
4081   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4082   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4083      return getTruncatedShiftCount(MI, 3) != 0;
4084 
4085   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4086   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
4087   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
4088   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
4089   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
4090   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
4091   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4092   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
4093   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
4094   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
4095   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
4096   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
4097   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
4098   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
4099   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
4100   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
4101   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
4102   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
4103   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
4104   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
4105   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
4106   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
4107   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4108   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
4109   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
4110   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
4111   case X86::LZCNT16rr: case X86::LZCNT16rm:
4112   case X86::LZCNT32rr: case X86::LZCNT32rm:
4113   case X86::LZCNT64rr: case X86::LZCNT64rm:
4114   case X86::POPCNT16rr:case X86::POPCNT16rm:
4115   case X86::POPCNT32rr:case X86::POPCNT32rm:
4116   case X86::POPCNT64rr:case X86::POPCNT64rm:
4117   case X86::TZCNT16rr: case X86::TZCNT16rm:
4118   case X86::TZCNT32rr: case X86::TZCNT32rm:
4119   case X86::TZCNT64rr: case X86::TZCNT64rm:
4120     return true;
4121   case X86::AND64ri32:   case X86::AND64ri8:  case X86::AND32ri:
4122   case X86::AND32ri8:    case X86::AND16ri:   case X86::AND16ri8:
4123   case X86::AND8ri:      case X86::AND64rr:   case X86::AND32rr:
4124   case X86::AND16rr:     case X86::AND8rr:    case X86::AND64rm:
4125   case X86::AND32rm:     case X86::AND16rm:   case X86::AND8rm:
4126   case X86::XOR64ri32:   case X86::XOR64ri8:  case X86::XOR32ri:
4127   case X86::XOR32ri8:    case X86::XOR16ri:   case X86::XOR16ri8:
4128   case X86::XOR8ri:      case X86::XOR64rr:   case X86::XOR32rr:
4129   case X86::XOR16rr:     case X86::XOR8rr:    case X86::XOR64rm:
4130   case X86::XOR32rm:     case X86::XOR16rm:   case X86::XOR8rm:
4131   case X86::OR64ri32:    case X86::OR64ri8:   case X86::OR32ri:
4132   case X86::OR32ri8:     case X86::OR16ri:    case X86::OR16ri8:
4133   case X86::OR8ri:       case X86::OR64rr:    case X86::OR32rr:
4134   case X86::OR16rr:      case X86::OR8rr:     case X86::OR64rm:
4135   case X86::OR32rm:      case X86::OR16rm:    case X86::OR8rm:
4136   case X86::ANDN32rr:    case X86::ANDN32rm:
4137   case X86::ANDN64rr:    case X86::ANDN64rm:
4138   case X86::BLSI32rr:    case X86::BLSI32rm:
4139   case X86::BLSI64rr:    case X86::BLSI64rm:
4140   case X86::BLSMSK32rr:  case X86::BLSMSK32rm:
4141   case X86::BLSMSK64rr:  case X86::BLSMSK64rm:
4142   case X86::BLSR32rr:    case X86::BLSR32rm:
4143   case X86::BLSR64rr:    case X86::BLSR64rm:
4144   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
4145   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
4146   case X86::BLCI32rr:    case X86::BLCI32rm:
4147   case X86::BLCI64rr:    case X86::BLCI64rm:
4148   case X86::BLCIC32rr:   case X86::BLCIC32rm:
4149   case X86::BLCIC64rr:   case X86::BLCIC64rm:
4150   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
4151   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
4152   case X86::BLCS32rr:    case X86::BLCS32rm:
4153   case X86::BLCS64rr:    case X86::BLCS64rm:
4154   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
4155   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
4156   case X86::BLSIC32rr:   case X86::BLSIC32rm:
4157   case X86::BLSIC64rr:   case X86::BLSIC64rm:
4158   case X86::BZHI32rr:    case X86::BZHI32rm:
4159   case X86::BZHI64rr:    case X86::BZHI64rm:
4160   case X86::T1MSKC32rr:  case X86::T1MSKC32rm:
4161   case X86::T1MSKC64rr:  case X86::T1MSKC64rm:
4162   case X86::TZMSK32rr:   case X86::TZMSK32rm:
4163   case X86::TZMSK64rr:   case X86::TZMSK64rm:
4164     // These instructions clear the overflow flag just like TEST.
4165     // FIXME: These are not the only instructions in this switch that clear the
4166     // overflow flag.
4167     ClearsOverflowFlag = true;
4168     return true;
4169   case X86::BEXTR32rr:   case X86::BEXTR64rr:
4170   case X86::BEXTR32rm:   case X86::BEXTR64rm:
4171   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
4172   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
4173     // BEXTR doesn't update the sign flag so we can't use it. It does clear
4174     // the overflow flag, but that's not useful without the sign flag.
4175     NoSignFlag = true;
4176     return true;
4177   }
4178 }
4179 
4180 /// Check whether the use can be converted to remove a comparison against zero.
4181 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
4182   switch (MI.getOpcode()) {
4183   default: return X86::COND_INVALID;
4184   case X86::NEG8r:
4185   case X86::NEG16r:
4186   case X86::NEG32r:
4187   case X86::NEG64r:
4188     return X86::COND_AE;
4189   case X86::LZCNT16rr:
4190   case X86::LZCNT32rr:
4191   case X86::LZCNT64rr:
4192     return X86::COND_B;
4193   case X86::POPCNT16rr:
4194   case X86::POPCNT32rr:
4195   case X86::POPCNT64rr:
4196     return X86::COND_E;
4197   case X86::TZCNT16rr:
4198   case X86::TZCNT32rr:
4199   case X86::TZCNT64rr:
4200     return X86::COND_B;
4201   case X86::BSF16rr:
4202   case X86::BSF32rr:
4203   case X86::BSF64rr:
4204   case X86::BSR16rr:
4205   case X86::BSR32rr:
4206   case X86::BSR64rr:
4207     return X86::COND_E;
4208   case X86::BLSI32rr:
4209   case X86::BLSI64rr:
4210     return X86::COND_AE;
4211   case X86::BLSR32rr:
4212   case X86::BLSR64rr:
4213   case X86::BLSMSK32rr:
4214   case X86::BLSMSK64rr:
4215     return X86::COND_B;
4216   // TODO: TBM instructions.
4217   }
4218 }
4219 
4220 /// Check if there exists an earlier instruction that
4221 /// operates on the same source operands and sets flags in the same way as
4222 /// Compare; remove Compare if possible.
4223 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
4224                                         Register SrcReg2, int64_t CmpMask,
4225                                         int64_t CmpValue,
4226                                         const MachineRegisterInfo *MRI) const {
4227   // Check whether we can replace SUB with CMP.
4228   switch (CmpInstr.getOpcode()) {
4229   default: break;
4230   case X86::SUB64ri32:
4231   case X86::SUB64ri8:
4232   case X86::SUB32ri:
4233   case X86::SUB32ri8:
4234   case X86::SUB16ri:
4235   case X86::SUB16ri8:
4236   case X86::SUB8ri:
4237   case X86::SUB64rm:
4238   case X86::SUB32rm:
4239   case X86::SUB16rm:
4240   case X86::SUB8rm:
4241   case X86::SUB64rr:
4242   case X86::SUB32rr:
4243   case X86::SUB16rr:
4244   case X86::SUB8rr: {
4245     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
4246       return false;
4247     // There is no use of the destination register, we can replace SUB with CMP.
4248     unsigned NewOpcode = 0;
4249     switch (CmpInstr.getOpcode()) {
4250     default: llvm_unreachable("Unreachable!");
4251     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4252     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4253     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4254     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4255     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4256     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4257     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4258     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4259     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4260     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4261     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4262     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4263     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4264     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4265     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4266     }
4267     CmpInstr.setDesc(get(NewOpcode));
4268     CmpInstr.RemoveOperand(0);
4269     // Mutating this instruction invalidates any debug data associated with it.
4270     CmpInstr.dropDebugNumber();
4271     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4272     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4273         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4274       return false;
4275   }
4276   }
4277 
4278   // Get the unique definition of SrcReg.
4279   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4280   if (!MI) return false;
4281 
4282   // CmpInstr is the first instruction of the BB.
4283   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4284 
4285   // If we are comparing against zero, check whether we can use MI to update
4286   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4287   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
4288   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
4289     return false;
4290 
4291   // If we have a use of the source register between the def and our compare
4292   // instruction we can eliminate the compare iff the use sets EFLAGS in the
4293   // right way.
4294   bool ShouldUpdateCC = false;
4295   bool NoSignFlag = false;
4296   bool ClearsOverflowFlag = false;
4297   X86::CondCode NewCC = X86::COND_INVALID;
4298   if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag, ClearsOverflowFlag)) {
4299     // Scan forward from the use until we hit the use we're looking for or the
4300     // compare instruction.
4301     for (MachineBasicBlock::iterator J = MI;; ++J) {
4302       // Do we have a convertible instruction?
4303       NewCC = isUseDefConvertible(*J);
4304       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4305           J->getOperand(1).getReg() == SrcReg) {
4306         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4307         ShouldUpdateCC = true; // Update CC later on.
4308         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4309         // with the new def.
4310         Def = J;
4311         MI = &*Def;
4312         break;
4313       }
4314 
4315       if (J == I)
4316         return false;
4317     }
4318   }
4319 
4320   // We are searching for an earlier instruction that can make CmpInstr
4321   // redundant and that instruction will be saved in Sub.
4322   MachineInstr *Sub = nullptr;
4323   const TargetRegisterInfo *TRI = &getRegisterInfo();
4324 
4325   // We iterate backward, starting from the instruction before CmpInstr and
4326   // stop when reaching the definition of a source register or done with the BB.
4327   // RI points to the instruction before CmpInstr.
4328   // If the definition is in this basic block, RE points to the definition;
4329   // otherwise, RE is the rend of the basic block.
4330   MachineBasicBlock::reverse_iterator
4331       RI = ++I.getReverse(),
4332       RE = CmpInstr.getParent() == MI->getParent()
4333                ? Def.getReverse() /* points to MI */
4334                : CmpInstr.getParent()->rend();
4335   MachineInstr *Movr0Inst = nullptr;
4336   for (; RI != RE; ++RI) {
4337     MachineInstr &Instr = *RI;
4338     // Check whether CmpInstr can be made redundant by the current instruction.
4339     if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
4340                                            CmpValue, Instr)) {
4341       Sub = &Instr;
4342       break;
4343     }
4344 
4345     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
4346         Instr.readsRegister(X86::EFLAGS, TRI)) {
4347       // This instruction modifies or uses EFLAGS.
4348 
4349       // MOV32r0 etc. are implemented with xor which clobbers condition code.
4350       // They are safe to move up, if the definition to EFLAGS is dead and
4351       // earlier instructions do not read or write EFLAGS.
4352       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
4353           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
4354         Movr0Inst = &Instr;
4355         continue;
4356       }
4357 
4358       // We can't remove CmpInstr.
4359       return false;
4360     }
4361   }
4362 
4363   // Return false if no candidates exist.
4364   if (!IsCmpZero && !Sub)
4365     return false;
4366 
4367   bool IsSwapped =
4368       (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
4369        Sub->getOperand(2).getReg() == SrcReg);
4370 
4371   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4372   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4373   // If we are done with the basic block, we need to check whether EFLAGS is
4374   // live-out.
4375   bool IsSafe = false;
4376   SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
4377   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
4378   for (++I; I != E; ++I) {
4379     const MachineInstr &Instr = *I;
4380     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4381     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4382     // We should check the usage if this instruction uses and updates EFLAGS.
4383     if (!UseEFLAGS && ModifyEFLAGS) {
4384       // It is safe to remove CmpInstr if EFLAGS is updated again.
4385       IsSafe = true;
4386       break;
4387     }
4388     if (!UseEFLAGS && !ModifyEFLAGS)
4389       continue;
4390 
4391     // EFLAGS is used by this instruction.
4392     X86::CondCode OldCC = X86::COND_INVALID;
4393     if (IsCmpZero || IsSwapped) {
4394       // We decode the condition code from opcode.
4395       if (Instr.isBranch())
4396         OldCC = X86::getCondFromBranch(Instr);
4397       else {
4398         OldCC = X86::getCondFromSETCC(Instr);
4399         if (OldCC == X86::COND_INVALID)
4400           OldCC = X86::getCondFromCMov(Instr);
4401       }
4402       if (OldCC == X86::COND_INVALID) return false;
4403     }
4404     X86::CondCode ReplacementCC = X86::COND_INVALID;
4405     if (IsCmpZero) {
4406       switch (OldCC) {
4407       default: break;
4408       case X86::COND_A: case X86::COND_AE:
4409       case X86::COND_B: case X86::COND_BE:
4410         // CF is used, we can't perform this optimization.
4411         return false;
4412       case X86::COND_G: case X86::COND_GE:
4413       case X86::COND_L: case X86::COND_LE:
4414       case X86::COND_O: case X86::COND_NO:
4415         // If OF is used, the instruction needs to clear it like CmpZero does.
4416         if (!ClearsOverflowFlag)
4417           return false;
4418         break;
4419       case X86::COND_S: case X86::COND_NS:
4420         // If SF is used, but the instruction doesn't update the SF, then we
4421         // can't do the optimization.
4422         if (NoSignFlag)
4423           return false;
4424         break;
4425       }
4426 
4427       // If we're updating the condition code check if we have to reverse the
4428       // condition.
4429       if (ShouldUpdateCC)
4430         switch (OldCC) {
4431         default:
4432           return false;
4433         case X86::COND_E:
4434           ReplacementCC = NewCC;
4435           break;
4436         case X86::COND_NE:
4437           ReplacementCC = GetOppositeBranchCondition(NewCC);
4438           break;
4439         }
4440     } else if (IsSwapped) {
4441       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4442       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4443       // We swap the condition code and synthesize the new opcode.
4444       ReplacementCC = getSwappedCondition(OldCC);
4445       if (ReplacementCC == X86::COND_INVALID) return false;
4446     }
4447 
4448     if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
4449       // Push the MachineInstr to OpsToUpdate.
4450       // If it is safe to remove CmpInstr, the condition code of these
4451       // instructions will be modified.
4452       OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
4453     }
4454     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4455       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4456       IsSafe = true;
4457       break;
4458     }
4459   }
4460 
4461   // If EFLAGS is not killed nor re-defined, we should check whether it is
4462   // live-out. If it is live-out, do not optimize.
4463   if ((IsCmpZero || IsSwapped) && !IsSafe) {
4464     MachineBasicBlock *MBB = CmpInstr.getParent();
4465     for (MachineBasicBlock *Successor : MBB->successors())
4466       if (Successor->isLiveIn(X86::EFLAGS))
4467         return false;
4468   }
4469 
4470   // The instruction to be updated is either Sub or MI.
4471   Sub = IsCmpZero ? MI : Sub;
4472   // Move Movr0Inst to the appropriate place before Sub.
4473   if (Movr0Inst) {
4474     // Look backwards until we find a def that doesn't use the current EFLAGS.
4475     Def = Sub;
4476     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
4477                                         InsertE = Sub->getParent()->rend();
4478     for (; InsertI != InsertE; ++InsertI) {
4479       MachineInstr *Instr = &*InsertI;
4480       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4481           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4482         Sub->getParent()->remove(Movr0Inst);
4483         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4484                                    Movr0Inst);
4485         break;
4486       }
4487     }
4488     if (InsertI == InsertE)
4489       return false;
4490   }
4491 
4492   // Make sure Sub instruction defines EFLAGS and mark the def live.
4493   MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
4494   assert(FlagDef && "Unable to locate a def EFLAGS operand");
4495   FlagDef->setIsDead(false);
4496 
4497   CmpInstr.eraseFromParent();
4498 
4499   // Modify the condition code of instructions in OpsToUpdate.
4500   for (auto &Op : OpsToUpdate) {
4501     Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
4502         .setImm(Op.second);
4503   }
4504   return true;
4505 }
4506 
4507 /// Try to remove the load by folding it to a register
4508 /// operand at the use. We fold the load instructions if load defines a virtual
4509 /// register, the virtual register is used once in the same BB, and the
4510 /// instructions in-between do not load or store, and have no side effects.
4511 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
4512                                               const MachineRegisterInfo *MRI,
4513                                               Register &FoldAsLoadDefReg,
4514                                               MachineInstr *&DefMI) const {
4515   // Check whether we can move DefMI here.
4516   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4517   assert(DefMI);
4518   bool SawStore = false;
4519   if (!DefMI->isSafeToMove(nullptr, SawStore))
4520     return nullptr;
4521 
4522   // Collect information about virtual register operands of MI.
4523   SmallVector<unsigned, 1> SrcOperandIds;
4524   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4525     MachineOperand &MO = MI.getOperand(i);
4526     if (!MO.isReg())
4527       continue;
4528     Register Reg = MO.getReg();
4529     if (Reg != FoldAsLoadDefReg)
4530       continue;
4531     // Do not fold if we have a subreg use or a def.
4532     if (MO.getSubReg() || MO.isDef())
4533       return nullptr;
4534     SrcOperandIds.push_back(i);
4535   }
4536   if (SrcOperandIds.empty())
4537     return nullptr;
4538 
4539   // Check whether we can fold the def into SrcOperandId.
4540   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
4541     FoldAsLoadDefReg = 0;
4542     return FoldMI;
4543   }
4544 
4545   return nullptr;
4546 }
4547 
4548 /// Expand a single-def pseudo instruction to a two-addr
4549 /// instruction with two undef reads of the register being defined.
4550 /// This is used for mapping:
4551 ///   %xmm4 = V_SET0
4552 /// to:
4553 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
4554 ///
4555 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4556                              const MCInstrDesc &Desc) {
4557   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4558   Register Reg = MIB.getReg(0);
4559   MIB->setDesc(Desc);
4560 
4561   // MachineInstr::addOperand() will insert explicit operands before any
4562   // implicit operands.
4563   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4564   // But we don't trust that.
4565   assert(MIB.getReg(1) == Reg &&
4566          MIB.getReg(2) == Reg && "Misplaced operand");
4567   return true;
4568 }
4569 
4570 /// Expand a single-def pseudo instruction to a two-addr
4571 /// instruction with two %k0 reads.
4572 /// This is used for mapping:
4573 ///   %k4 = K_SET1
4574 /// to:
4575 ///   %k4 = KXNORrr %k0, %k0
4576 static bool Expand2AddrKreg(MachineInstrBuilder &MIB, const MCInstrDesc &Desc,
4577                             Register Reg) {
4578   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4579   MIB->setDesc(Desc);
4580   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4581   return true;
4582 }
4583 
4584 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
4585                           bool MinusOne) {
4586   MachineBasicBlock &MBB = *MIB->getParent();
4587   const DebugLoc &DL = MIB->getDebugLoc();
4588   Register Reg = MIB.getReg(0);
4589 
4590   // Insert the XOR.
4591   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
4592       .addReg(Reg, RegState::Undef)
4593       .addReg(Reg, RegState::Undef);
4594 
4595   // Turn the pseudo into an INC or DEC.
4596   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
4597   MIB.addReg(Reg);
4598 
4599   return true;
4600 }
4601 
4602 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
4603                                const TargetInstrInfo &TII,
4604                                const X86Subtarget &Subtarget) {
4605   MachineBasicBlock &MBB = *MIB->getParent();
4606   const DebugLoc &DL = MIB->getDebugLoc();
4607   int64_t Imm = MIB->getOperand(1).getImm();
4608   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
4609   MachineBasicBlock::iterator I = MIB.getInstr();
4610 
4611   int StackAdjustment;
4612 
4613   if (Subtarget.is64Bit()) {
4614     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
4615            MIB->getOpcode() == X86::MOV32ImmSExti8);
4616 
4617     // Can't use push/pop lowering if the function might write to the red zone.
4618     X86MachineFunctionInfo *X86FI =
4619         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
4620     if (X86FI->getUsesRedZone()) {
4621       MIB->setDesc(TII.get(MIB->getOpcode() ==
4622                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
4623       return true;
4624     }
4625 
4626     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4627     // widen the register if necessary.
4628     StackAdjustment = 8;
4629     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4630     MIB->setDesc(TII.get(X86::POP64r));
4631     MIB->getOperand(0)
4632         .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
4633   } else {
4634     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
4635     StackAdjustment = 4;
4636     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4637     MIB->setDesc(TII.get(X86::POP32r));
4638   }
4639   MIB->RemoveOperand(1);
4640   MIB->addImplicitDefUseOperands(*MBB.getParent());
4641 
4642   // Build CFI if necessary.
4643   MachineFunction &MF = *MBB.getParent();
4644   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4645   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4646   bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
4647   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4648   if (EmitCFI) {
4649     TFL->BuildCFI(MBB, I, DL,
4650         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4651     TFL->BuildCFI(MBB, std::next(I), DL,
4652         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4653   }
4654 
4655   return true;
4656 }
4657 
4658 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4659 // code sequence is needed for other targets.
4660 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4661                                  const TargetInstrInfo &TII) {
4662   MachineBasicBlock &MBB = *MIB->getParent();
4663   const DebugLoc &DL = MIB->getDebugLoc();
4664   Register Reg = MIB.getReg(0);
4665   const GlobalValue *GV =
4666       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4667   auto Flags = MachineMemOperand::MOLoad |
4668                MachineMemOperand::MODereferenceable |
4669                MachineMemOperand::MOInvariant;
4670   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4671       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, Align(8));
4672   MachineBasicBlock::iterator I = MIB.getInstr();
4673 
4674   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4675       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4676       .addMemOperand(MMO);
4677   MIB->setDebugLoc(DL);
4678   MIB->setDesc(TII.get(X86::MOV64rm));
4679   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4680 }
4681 
4682 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4683   MachineBasicBlock &MBB = *MIB->getParent();
4684   MachineFunction &MF = *MBB.getParent();
4685   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4686   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4687   unsigned XorOp =
4688       MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4689   MIB->setDesc(TII.get(XorOp));
4690   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4691   return true;
4692 }
4693 
4694 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4695 // but not VLX. If it uses an extended register we need to use an instruction
4696 // that loads the lower 128/256-bit, but is available with only AVX512F.
4697 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4698                             const TargetRegisterInfo *TRI,
4699                             const MCInstrDesc &LoadDesc,
4700                             const MCInstrDesc &BroadcastDesc,
4701                             unsigned SubIdx) {
4702   Register DestReg = MIB.getReg(0);
4703   // Check if DestReg is XMM16-31 or YMM16-31.
4704   if (TRI->getEncodingValue(DestReg) < 16) {
4705     // We can use a normal VEX encoded load.
4706     MIB->setDesc(LoadDesc);
4707   } else {
4708     // Use a 128/256-bit VBROADCAST instruction.
4709     MIB->setDesc(BroadcastDesc);
4710     // Change the destination to a 512-bit register.
4711     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4712     MIB->getOperand(0).setReg(DestReg);
4713   }
4714   return true;
4715 }
4716 
4717 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4718 // but not VLX. If it uses an extended register we need to use an instruction
4719 // that stores the lower 128/256-bit, but is available with only AVX512F.
4720 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4721                              const TargetRegisterInfo *TRI,
4722                              const MCInstrDesc &StoreDesc,
4723                              const MCInstrDesc &ExtractDesc,
4724                              unsigned SubIdx) {
4725   Register SrcReg = MIB.getReg(X86::AddrNumOperands);
4726   // Check if DestReg is XMM16-31 or YMM16-31.
4727   if (TRI->getEncodingValue(SrcReg) < 16) {
4728     // We can use a normal VEX encoded store.
4729     MIB->setDesc(StoreDesc);
4730   } else {
4731     // Use a VEXTRACTF instruction.
4732     MIB->setDesc(ExtractDesc);
4733     // Change the destination to a 512-bit register.
4734     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4735     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4736     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4737   }
4738 
4739   return true;
4740 }
4741 
4742 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4743   MIB->setDesc(Desc);
4744   int64_t ShiftAmt = MIB->getOperand(2).getImm();
4745   // Temporarily remove the immediate so we can add another source register.
4746   MIB->RemoveOperand(2);
4747   // Add the register. Don't copy the kill flag if there is one.
4748   MIB.addReg(MIB.getReg(1),
4749              getUndefRegState(MIB->getOperand(1).isUndef()));
4750   // Add back the immediate.
4751   MIB.addImm(ShiftAmt);
4752   return true;
4753 }
4754 
4755 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4756   bool HasAVX = Subtarget.hasAVX();
4757   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4758   switch (MI.getOpcode()) {
4759   case X86::MOV32r0:
4760     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4761   case X86::MOV32r1:
4762     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4763   case X86::MOV32r_1:
4764     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4765   case X86::MOV32ImmSExti8:
4766   case X86::MOV64ImmSExti8:
4767     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4768   case X86::SETB_C32r:
4769     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4770   case X86::SETB_C64r:
4771     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4772   case X86::MMX_SET0:
4773     return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4774   case X86::V_SET0:
4775   case X86::FsFLD0SS:
4776   case X86::FsFLD0SD:
4777   case X86::FsFLD0F128:
4778     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4779   case X86::AVX_SET0: {
4780     assert(HasAVX && "AVX not supported");
4781     const TargetRegisterInfo *TRI = &getRegisterInfo();
4782     Register SrcReg = MIB.getReg(0);
4783     Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4784     MIB->getOperand(0).setReg(XReg);
4785     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4786     MIB.addReg(SrcReg, RegState::ImplicitDefine);
4787     return true;
4788   }
4789   case X86::AVX512_128_SET0:
4790   case X86::AVX512_FsFLD0SH:
4791   case X86::AVX512_FsFLD0SS:
4792   case X86::AVX512_FsFLD0SD:
4793   case X86::AVX512_FsFLD0F128: {
4794     bool HasVLX = Subtarget.hasVLX();
4795     Register SrcReg = MIB.getReg(0);
4796     const TargetRegisterInfo *TRI = &getRegisterInfo();
4797     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4798       return Expand2AddrUndef(MIB,
4799                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4800     // Extended register without VLX. Use a larger XOR.
4801     SrcReg =
4802         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4803     MIB->getOperand(0).setReg(SrcReg);
4804     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4805   }
4806   case X86::AVX512_256_SET0:
4807   case X86::AVX512_512_SET0: {
4808     bool HasVLX = Subtarget.hasVLX();
4809     Register SrcReg = MIB.getReg(0);
4810     const TargetRegisterInfo *TRI = &getRegisterInfo();
4811     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4812       Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4813       MIB->getOperand(0).setReg(XReg);
4814       Expand2AddrUndef(MIB,
4815                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4816       MIB.addReg(SrcReg, RegState::ImplicitDefine);
4817       return true;
4818     }
4819     if (MI.getOpcode() == X86::AVX512_256_SET0) {
4820       // No VLX so we must reference a zmm.
4821       unsigned ZReg =
4822         TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4823       MIB->getOperand(0).setReg(ZReg);
4824     }
4825     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4826   }
4827   case X86::V_SETALLONES:
4828     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4829   case X86::AVX2_SETALLONES:
4830     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4831   case X86::AVX1_SETALLONES: {
4832     Register Reg = MIB.getReg(0);
4833     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4834     MIB->setDesc(get(X86::VCMPPSYrri));
4835     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4836     return true;
4837   }
4838   case X86::AVX512_512_SETALLONES: {
4839     Register Reg = MIB.getReg(0);
4840     MIB->setDesc(get(X86::VPTERNLOGDZrri));
4841     // VPTERNLOGD needs 3 register inputs and an immediate.
4842     // 0xff will return 1s for any input.
4843     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4844        .addReg(Reg, RegState::Undef).addImm(0xff);
4845     return true;
4846   }
4847   case X86::AVX512_512_SEXT_MASK_32:
4848   case X86::AVX512_512_SEXT_MASK_64: {
4849     Register Reg = MIB.getReg(0);
4850     Register MaskReg = MIB.getReg(1);
4851     unsigned MaskState = getRegState(MIB->getOperand(1));
4852     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4853                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4854     MI.RemoveOperand(1);
4855     MIB->setDesc(get(Opc));
4856     // VPTERNLOG needs 3 register inputs and an immediate.
4857     // 0xff will return 1s for any input.
4858     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4859        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4860     return true;
4861   }
4862   case X86::VMOVAPSZ128rm_NOVLX:
4863     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4864                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4865   case X86::VMOVUPSZ128rm_NOVLX:
4866     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4867                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4868   case X86::VMOVAPSZ256rm_NOVLX:
4869     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4870                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4871   case X86::VMOVUPSZ256rm_NOVLX:
4872     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4873                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4874   case X86::VMOVAPSZ128mr_NOVLX:
4875     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4876                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4877   case X86::VMOVUPSZ128mr_NOVLX:
4878     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4879                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4880   case X86::VMOVAPSZ256mr_NOVLX:
4881     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4882                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4883   case X86::VMOVUPSZ256mr_NOVLX:
4884     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4885                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4886   case X86::MOV32ri64: {
4887     Register Reg = MIB.getReg(0);
4888     Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4889     MI.setDesc(get(X86::MOV32ri));
4890     MIB->getOperand(0).setReg(Reg32);
4891     MIB.addReg(Reg, RegState::ImplicitDefine);
4892     return true;
4893   }
4894 
4895   // KNL does not recognize dependency-breaking idioms for mask registers,
4896   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4897   // Using %k0 as the undef input register is a performance heuristic based
4898   // on the assumption that %k0 is used less frequently than the other mask
4899   // registers, since it is not usable as a write mask.
4900   // FIXME: A more advanced approach would be to choose the best input mask
4901   // register based on context.
4902   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4903   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4904   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4905   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4906   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4907   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4908   case TargetOpcode::LOAD_STACK_GUARD:
4909     expandLoadStackGuard(MIB, *this);
4910     return true;
4911   case X86::XOR64_FP:
4912   case X86::XOR32_FP:
4913     return expandXorFP(MIB, *this);
4914   case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4915   case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4916   case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4917   case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4918   case X86::ADD8rr_DB:    MIB->setDesc(get(X86::OR8rr));    break;
4919   case X86::ADD16rr_DB:   MIB->setDesc(get(X86::OR16rr));   break;
4920   case X86::ADD32rr_DB:   MIB->setDesc(get(X86::OR32rr));   break;
4921   case X86::ADD64rr_DB:   MIB->setDesc(get(X86::OR64rr));   break;
4922   case X86::ADD8ri_DB:    MIB->setDesc(get(X86::OR8ri));    break;
4923   case X86::ADD16ri_DB:   MIB->setDesc(get(X86::OR16ri));   break;
4924   case X86::ADD32ri_DB:   MIB->setDesc(get(X86::OR32ri));   break;
4925   case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4926   case X86::ADD16ri8_DB:  MIB->setDesc(get(X86::OR16ri8));  break;
4927   case X86::ADD32ri8_DB:  MIB->setDesc(get(X86::OR32ri8));  break;
4928   case X86::ADD64ri8_DB:  MIB->setDesc(get(X86::OR64ri8));  break;
4929   }
4930   return false;
4931 }
4932 
4933 /// Return true for all instructions that only update
4934 /// the first 32 or 64-bits of the destination register and leave the rest
4935 /// unmodified. This can be used to avoid folding loads if the instructions
4936 /// only update part of the destination register, and the non-updated part is
4937 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4938 /// instructions breaks the partial register dependency and it can improve
4939 /// performance. e.g.:
4940 ///
4941 ///   movss (%rdi), %xmm0
4942 ///   cvtss2sd %xmm0, %xmm0
4943 ///
4944 /// Instead of
4945 ///   cvtss2sd (%rdi), %xmm0
4946 ///
4947 /// FIXME: This should be turned into a TSFlags.
4948 ///
4949 static bool hasPartialRegUpdate(unsigned Opcode,
4950                                 const X86Subtarget &Subtarget,
4951                                 bool ForLoadFold = false) {
4952   switch (Opcode) {
4953   case X86::CVTSI2SSrr:
4954   case X86::CVTSI2SSrm:
4955   case X86::CVTSI642SSrr:
4956   case X86::CVTSI642SSrm:
4957   case X86::CVTSI2SDrr:
4958   case X86::CVTSI2SDrm:
4959   case X86::CVTSI642SDrr:
4960   case X86::CVTSI642SDrm:
4961     // Load folding won't effect the undef register update since the input is
4962     // a GPR.
4963     return !ForLoadFold;
4964   case X86::CVTSD2SSrr:
4965   case X86::CVTSD2SSrm:
4966   case X86::CVTSS2SDrr:
4967   case X86::CVTSS2SDrm:
4968   case X86::MOVHPDrm:
4969   case X86::MOVHPSrm:
4970   case X86::MOVLPDrm:
4971   case X86::MOVLPSrm:
4972   case X86::RCPSSr:
4973   case X86::RCPSSm:
4974   case X86::RCPSSr_Int:
4975   case X86::RCPSSm_Int:
4976   case X86::ROUNDSDr:
4977   case X86::ROUNDSDm:
4978   case X86::ROUNDSSr:
4979   case X86::ROUNDSSm:
4980   case X86::RSQRTSSr:
4981   case X86::RSQRTSSm:
4982   case X86::RSQRTSSr_Int:
4983   case X86::RSQRTSSm_Int:
4984   case X86::SQRTSSr:
4985   case X86::SQRTSSm:
4986   case X86::SQRTSSr_Int:
4987   case X86::SQRTSSm_Int:
4988   case X86::SQRTSDr:
4989   case X86::SQRTSDm:
4990   case X86::SQRTSDr_Int:
4991   case X86::SQRTSDm_Int:
4992     return true;
4993   // GPR
4994   case X86::POPCNT32rm:
4995   case X86::POPCNT32rr:
4996   case X86::POPCNT64rm:
4997   case X86::POPCNT64rr:
4998     return Subtarget.hasPOPCNTFalseDeps();
4999   case X86::LZCNT32rm:
5000   case X86::LZCNT32rr:
5001   case X86::LZCNT64rm:
5002   case X86::LZCNT64rr:
5003   case X86::TZCNT32rm:
5004   case X86::TZCNT32rr:
5005   case X86::TZCNT64rm:
5006   case X86::TZCNT64rr:
5007     return Subtarget.hasLZCNTFalseDeps();
5008   }
5009 
5010   return false;
5011 }
5012 
5013 /// Inform the BreakFalseDeps pass how many idle
5014 /// instructions we would like before a partial register update.
5015 unsigned X86InstrInfo::getPartialRegUpdateClearance(
5016     const MachineInstr &MI, unsigned OpNum,
5017     const TargetRegisterInfo *TRI) const {
5018   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
5019     return 0;
5020 
5021   // If MI is marked as reading Reg, the partial register update is wanted.
5022   const MachineOperand &MO = MI.getOperand(0);
5023   Register Reg = MO.getReg();
5024   if (Reg.isVirtual()) {
5025     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
5026       return 0;
5027   } else {
5028     if (MI.readsRegister(Reg, TRI))
5029       return 0;
5030   }
5031 
5032   // If any instructions in the clearance range are reading Reg, insert a
5033   // dependency breaking instruction, which is inexpensive and is likely to
5034   // be hidden in other instruction's cycles.
5035   return PartialRegUpdateClearance;
5036 }
5037 
5038 // Return true for any instruction the copies the high bits of the first source
5039 // operand into the unused high bits of the destination operand.
5040 // Also returns true for instructions that have two inputs where one may
5041 // be undef and we want it to use the same register as the other input.
5042 static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
5043                               bool ForLoadFold = false) {
5044   // Set the OpNum parameter to the first source operand.
5045   switch (Opcode) {
5046   case X86::MMX_PUNPCKHBWirr:
5047   case X86::MMX_PUNPCKHWDirr:
5048   case X86::MMX_PUNPCKHDQirr:
5049   case X86::MMX_PUNPCKLBWirr:
5050   case X86::MMX_PUNPCKLWDirr:
5051   case X86::MMX_PUNPCKLDQirr:
5052   case X86::MOVHLPSrr:
5053   case X86::PACKSSWBrr:
5054   case X86::PACKUSWBrr:
5055   case X86::PACKSSDWrr:
5056   case X86::PACKUSDWrr:
5057   case X86::PUNPCKHBWrr:
5058   case X86::PUNPCKLBWrr:
5059   case X86::PUNPCKHWDrr:
5060   case X86::PUNPCKLWDrr:
5061   case X86::PUNPCKHDQrr:
5062   case X86::PUNPCKLDQrr:
5063   case X86::PUNPCKHQDQrr:
5064   case X86::PUNPCKLQDQrr:
5065   case X86::SHUFPDrri:
5066   case X86::SHUFPSrri:
5067     // These instructions are sometimes used with an undef first or second
5068     // source. Return true here so BreakFalseDeps will assign this source to the
5069     // same register as the first source to avoid a false dependency.
5070     // Operand 1 of these instructions is tied so they're separate from their
5071     // VEX counterparts.
5072     return OpNum == 2 && !ForLoadFold;
5073 
5074   case X86::VMOVLHPSrr:
5075   case X86::VMOVLHPSZrr:
5076   case X86::VPACKSSWBrr:
5077   case X86::VPACKUSWBrr:
5078   case X86::VPACKSSDWrr:
5079   case X86::VPACKUSDWrr:
5080   case X86::VPACKSSWBZ128rr:
5081   case X86::VPACKUSWBZ128rr:
5082   case X86::VPACKSSDWZ128rr:
5083   case X86::VPACKUSDWZ128rr:
5084   case X86::VPERM2F128rr:
5085   case X86::VPERM2I128rr:
5086   case X86::VSHUFF32X4Z256rri:
5087   case X86::VSHUFF32X4Zrri:
5088   case X86::VSHUFF64X2Z256rri:
5089   case X86::VSHUFF64X2Zrri:
5090   case X86::VSHUFI32X4Z256rri:
5091   case X86::VSHUFI32X4Zrri:
5092   case X86::VSHUFI64X2Z256rri:
5093   case X86::VSHUFI64X2Zrri:
5094   case X86::VPUNPCKHBWrr:
5095   case X86::VPUNPCKLBWrr:
5096   case X86::VPUNPCKHBWYrr:
5097   case X86::VPUNPCKLBWYrr:
5098   case X86::VPUNPCKHBWZ128rr:
5099   case X86::VPUNPCKLBWZ128rr:
5100   case X86::VPUNPCKHBWZ256rr:
5101   case X86::VPUNPCKLBWZ256rr:
5102   case X86::VPUNPCKHBWZrr:
5103   case X86::VPUNPCKLBWZrr:
5104   case X86::VPUNPCKHWDrr:
5105   case X86::VPUNPCKLWDrr:
5106   case X86::VPUNPCKHWDYrr:
5107   case X86::VPUNPCKLWDYrr:
5108   case X86::VPUNPCKHWDZ128rr:
5109   case X86::VPUNPCKLWDZ128rr:
5110   case X86::VPUNPCKHWDZ256rr:
5111   case X86::VPUNPCKLWDZ256rr:
5112   case X86::VPUNPCKHWDZrr:
5113   case X86::VPUNPCKLWDZrr:
5114   case X86::VPUNPCKHDQrr:
5115   case X86::VPUNPCKLDQrr:
5116   case X86::VPUNPCKHDQYrr:
5117   case X86::VPUNPCKLDQYrr:
5118   case X86::VPUNPCKHDQZ128rr:
5119   case X86::VPUNPCKLDQZ128rr:
5120   case X86::VPUNPCKHDQZ256rr:
5121   case X86::VPUNPCKLDQZ256rr:
5122   case X86::VPUNPCKHDQZrr:
5123   case X86::VPUNPCKLDQZrr:
5124   case X86::VPUNPCKHQDQrr:
5125   case X86::VPUNPCKLQDQrr:
5126   case X86::VPUNPCKHQDQYrr:
5127   case X86::VPUNPCKLQDQYrr:
5128   case X86::VPUNPCKHQDQZ128rr:
5129   case X86::VPUNPCKLQDQZ128rr:
5130   case X86::VPUNPCKHQDQZ256rr:
5131   case X86::VPUNPCKLQDQZ256rr:
5132   case X86::VPUNPCKHQDQZrr:
5133   case X86::VPUNPCKLQDQZrr:
5134     // These instructions are sometimes used with an undef first or second
5135     // source. Return true here so BreakFalseDeps will assign this source to the
5136     // same register as the first source to avoid a false dependency.
5137     return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
5138 
5139   case X86::VCVTSI2SSrr:
5140   case X86::VCVTSI2SSrm:
5141   case X86::VCVTSI2SSrr_Int:
5142   case X86::VCVTSI2SSrm_Int:
5143   case X86::VCVTSI642SSrr:
5144   case X86::VCVTSI642SSrm:
5145   case X86::VCVTSI642SSrr_Int:
5146   case X86::VCVTSI642SSrm_Int:
5147   case X86::VCVTSI2SDrr:
5148   case X86::VCVTSI2SDrm:
5149   case X86::VCVTSI2SDrr_Int:
5150   case X86::VCVTSI2SDrm_Int:
5151   case X86::VCVTSI642SDrr:
5152   case X86::VCVTSI642SDrm:
5153   case X86::VCVTSI642SDrr_Int:
5154   case X86::VCVTSI642SDrm_Int:
5155   // AVX-512
5156   case X86::VCVTSI2SSZrr:
5157   case X86::VCVTSI2SSZrm:
5158   case X86::VCVTSI2SSZrr_Int:
5159   case X86::VCVTSI2SSZrrb_Int:
5160   case X86::VCVTSI2SSZrm_Int:
5161   case X86::VCVTSI642SSZrr:
5162   case X86::VCVTSI642SSZrm:
5163   case X86::VCVTSI642SSZrr_Int:
5164   case X86::VCVTSI642SSZrrb_Int:
5165   case X86::VCVTSI642SSZrm_Int:
5166   case X86::VCVTSI2SDZrr:
5167   case X86::VCVTSI2SDZrm:
5168   case X86::VCVTSI2SDZrr_Int:
5169   case X86::VCVTSI2SDZrm_Int:
5170   case X86::VCVTSI642SDZrr:
5171   case X86::VCVTSI642SDZrm:
5172   case X86::VCVTSI642SDZrr_Int:
5173   case X86::VCVTSI642SDZrrb_Int:
5174   case X86::VCVTSI642SDZrm_Int:
5175   case X86::VCVTUSI2SSZrr:
5176   case X86::VCVTUSI2SSZrm:
5177   case X86::VCVTUSI2SSZrr_Int:
5178   case X86::VCVTUSI2SSZrrb_Int:
5179   case X86::VCVTUSI2SSZrm_Int:
5180   case X86::VCVTUSI642SSZrr:
5181   case X86::VCVTUSI642SSZrm:
5182   case X86::VCVTUSI642SSZrr_Int:
5183   case X86::VCVTUSI642SSZrrb_Int:
5184   case X86::VCVTUSI642SSZrm_Int:
5185   case X86::VCVTUSI2SDZrr:
5186   case X86::VCVTUSI2SDZrm:
5187   case X86::VCVTUSI2SDZrr_Int:
5188   case X86::VCVTUSI2SDZrm_Int:
5189   case X86::VCVTUSI642SDZrr:
5190   case X86::VCVTUSI642SDZrm:
5191   case X86::VCVTUSI642SDZrr_Int:
5192   case X86::VCVTUSI642SDZrrb_Int:
5193   case X86::VCVTUSI642SDZrm_Int:
5194   case X86::VCVTSI2SHZrr:
5195   case X86::VCVTSI2SHZrm:
5196   case X86::VCVTSI2SHZrr_Int:
5197   case X86::VCVTSI2SHZrrb_Int:
5198   case X86::VCVTSI2SHZrm_Int:
5199   case X86::VCVTSI642SHZrr:
5200   case X86::VCVTSI642SHZrm:
5201   case X86::VCVTSI642SHZrr_Int:
5202   case X86::VCVTSI642SHZrrb_Int:
5203   case X86::VCVTSI642SHZrm_Int:
5204   case X86::VCVTUSI2SHZrr:
5205   case X86::VCVTUSI2SHZrm:
5206   case X86::VCVTUSI2SHZrr_Int:
5207   case X86::VCVTUSI2SHZrrb_Int:
5208   case X86::VCVTUSI2SHZrm_Int:
5209   case X86::VCVTUSI642SHZrr:
5210   case X86::VCVTUSI642SHZrm:
5211   case X86::VCVTUSI642SHZrr_Int:
5212   case X86::VCVTUSI642SHZrrb_Int:
5213   case X86::VCVTUSI642SHZrm_Int:
5214     // Load folding won't effect the undef register update since the input is
5215     // a GPR.
5216     return OpNum == 1 && !ForLoadFold;
5217   case X86::VCVTSD2SSrr:
5218   case X86::VCVTSD2SSrm:
5219   case X86::VCVTSD2SSrr_Int:
5220   case X86::VCVTSD2SSrm_Int:
5221   case X86::VCVTSS2SDrr:
5222   case X86::VCVTSS2SDrm:
5223   case X86::VCVTSS2SDrr_Int:
5224   case X86::VCVTSS2SDrm_Int:
5225   case X86::VRCPSSr:
5226   case X86::VRCPSSr_Int:
5227   case X86::VRCPSSm:
5228   case X86::VRCPSSm_Int:
5229   case X86::VROUNDSDr:
5230   case X86::VROUNDSDm:
5231   case X86::VROUNDSDr_Int:
5232   case X86::VROUNDSDm_Int:
5233   case X86::VROUNDSSr:
5234   case X86::VROUNDSSm:
5235   case X86::VROUNDSSr_Int:
5236   case X86::VROUNDSSm_Int:
5237   case X86::VRSQRTSSr:
5238   case X86::VRSQRTSSr_Int:
5239   case X86::VRSQRTSSm:
5240   case X86::VRSQRTSSm_Int:
5241   case X86::VSQRTSSr:
5242   case X86::VSQRTSSr_Int:
5243   case X86::VSQRTSSm:
5244   case X86::VSQRTSSm_Int:
5245   case X86::VSQRTSDr:
5246   case X86::VSQRTSDr_Int:
5247   case X86::VSQRTSDm:
5248   case X86::VSQRTSDm_Int:
5249   // AVX-512
5250   case X86::VCVTSD2SSZrr:
5251   case X86::VCVTSD2SSZrr_Int:
5252   case X86::VCVTSD2SSZrrb_Int:
5253   case X86::VCVTSD2SSZrm:
5254   case X86::VCVTSD2SSZrm_Int:
5255   case X86::VCVTSS2SDZrr:
5256   case X86::VCVTSS2SDZrr_Int:
5257   case X86::VCVTSS2SDZrrb_Int:
5258   case X86::VCVTSS2SDZrm:
5259   case X86::VCVTSS2SDZrm_Int:
5260   case X86::VGETEXPSDZr:
5261   case X86::VGETEXPSDZrb:
5262   case X86::VGETEXPSDZm:
5263   case X86::VGETEXPSSZr:
5264   case X86::VGETEXPSSZrb:
5265   case X86::VGETEXPSSZm:
5266   case X86::VGETMANTSDZrri:
5267   case X86::VGETMANTSDZrrib:
5268   case X86::VGETMANTSDZrmi:
5269   case X86::VGETMANTSSZrri:
5270   case X86::VGETMANTSSZrrib:
5271   case X86::VGETMANTSSZrmi:
5272   case X86::VRNDSCALESDZr:
5273   case X86::VRNDSCALESDZr_Int:
5274   case X86::VRNDSCALESDZrb_Int:
5275   case X86::VRNDSCALESDZm:
5276   case X86::VRNDSCALESDZm_Int:
5277   case X86::VRNDSCALESSZr:
5278   case X86::VRNDSCALESSZr_Int:
5279   case X86::VRNDSCALESSZrb_Int:
5280   case X86::VRNDSCALESSZm:
5281   case X86::VRNDSCALESSZm_Int:
5282   case X86::VRCP14SDZrr:
5283   case X86::VRCP14SDZrm:
5284   case X86::VRCP14SSZrr:
5285   case X86::VRCP14SSZrm:
5286   case X86::VRCPSHZrr:
5287   case X86::VRCPSHZrm:
5288   case X86::VRSQRTSHZrr:
5289   case X86::VRSQRTSHZrm:
5290   case X86::VREDUCESHZrmi:
5291   case X86::VREDUCESHZrri:
5292   case X86::VREDUCESHZrrib:
5293   case X86::VGETEXPSHZr:
5294   case X86::VGETEXPSHZrb:
5295   case X86::VGETEXPSHZm:
5296   case X86::VGETMANTSHZrri:
5297   case X86::VGETMANTSHZrrib:
5298   case X86::VGETMANTSHZrmi:
5299   case X86::VRNDSCALESHZr:
5300   case X86::VRNDSCALESHZr_Int:
5301   case X86::VRNDSCALESHZrb_Int:
5302   case X86::VRNDSCALESHZm:
5303   case X86::VRNDSCALESHZm_Int:
5304   case X86::VSQRTSHZr:
5305   case X86::VSQRTSHZr_Int:
5306   case X86::VSQRTSHZrb_Int:
5307   case X86::VSQRTSHZm:
5308   case X86::VSQRTSHZm_Int:
5309   case X86::VRCP28SDZr:
5310   case X86::VRCP28SDZrb:
5311   case X86::VRCP28SDZm:
5312   case X86::VRCP28SSZr:
5313   case X86::VRCP28SSZrb:
5314   case X86::VRCP28SSZm:
5315   case X86::VREDUCESSZrmi:
5316   case X86::VREDUCESSZrri:
5317   case X86::VREDUCESSZrrib:
5318   case X86::VRSQRT14SDZrr:
5319   case X86::VRSQRT14SDZrm:
5320   case X86::VRSQRT14SSZrr:
5321   case X86::VRSQRT14SSZrm:
5322   case X86::VRSQRT28SDZr:
5323   case X86::VRSQRT28SDZrb:
5324   case X86::VRSQRT28SDZm:
5325   case X86::VRSQRT28SSZr:
5326   case X86::VRSQRT28SSZrb:
5327   case X86::VRSQRT28SSZm:
5328   case X86::VSQRTSSZr:
5329   case X86::VSQRTSSZr_Int:
5330   case X86::VSQRTSSZrb_Int:
5331   case X86::VSQRTSSZm:
5332   case X86::VSQRTSSZm_Int:
5333   case X86::VSQRTSDZr:
5334   case X86::VSQRTSDZr_Int:
5335   case X86::VSQRTSDZrb_Int:
5336   case X86::VSQRTSDZm:
5337   case X86::VSQRTSDZm_Int:
5338   case X86::VCVTSD2SHZrr:
5339   case X86::VCVTSD2SHZrr_Int:
5340   case X86::VCVTSD2SHZrrb_Int:
5341   case X86::VCVTSD2SHZrm:
5342   case X86::VCVTSD2SHZrm_Int:
5343   case X86::VCVTSS2SHZrr:
5344   case X86::VCVTSS2SHZrr_Int:
5345   case X86::VCVTSS2SHZrrb_Int:
5346   case X86::VCVTSS2SHZrm:
5347   case X86::VCVTSS2SHZrm_Int:
5348   case X86::VCVTSH2SDZrr:
5349   case X86::VCVTSH2SDZrr_Int:
5350   case X86::VCVTSH2SDZrrb_Int:
5351   case X86::VCVTSH2SDZrm:
5352   case X86::VCVTSH2SDZrm_Int:
5353   case X86::VCVTSH2SSZrr:
5354   case X86::VCVTSH2SSZrr_Int:
5355   case X86::VCVTSH2SSZrrb_Int:
5356   case X86::VCVTSH2SSZrm:
5357   case X86::VCVTSH2SSZrm_Int:
5358     return OpNum == 1;
5359   case X86::VMOVSSZrrk:
5360   case X86::VMOVSDZrrk:
5361     return OpNum == 3 && !ForLoadFold;
5362   case X86::VMOVSSZrrkz:
5363   case X86::VMOVSDZrrkz:
5364     return OpNum == 2 && !ForLoadFold;
5365   }
5366 
5367   return false;
5368 }
5369 
5370 /// Inform the BreakFalseDeps pass how many idle instructions we would like
5371 /// before certain undef register reads.
5372 ///
5373 /// This catches the VCVTSI2SD family of instructions:
5374 ///
5375 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
5376 ///
5377 /// We should to be careful *not* to catch VXOR idioms which are presumably
5378 /// handled specially in the pipeline:
5379 ///
5380 /// vxorps undef %xmm1, undef %xmm1, %xmm1
5381 ///
5382 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5383 /// high bits that are passed-through are not live.
5384 unsigned
5385 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
5386                                    const TargetRegisterInfo *TRI) const {
5387   const MachineOperand &MO = MI.getOperand(OpNum);
5388   if (Register::isPhysicalRegister(MO.getReg()) &&
5389       hasUndefRegUpdate(MI.getOpcode(), OpNum))
5390     return UndefRegClearance;
5391 
5392   return 0;
5393 }
5394 
5395 void X86InstrInfo::breakPartialRegDependency(
5396     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5397   Register Reg = MI.getOperand(OpNum).getReg();
5398   // If MI kills this register, the false dependence is already broken.
5399   if (MI.killsRegister(Reg, TRI))
5400     return;
5401 
5402   if (X86::VR128RegClass.contains(Reg)) {
5403     // These instructions are all floating point domain, so xorps is the best
5404     // choice.
5405     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
5406     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
5407         .addReg(Reg, RegState::Undef)
5408         .addReg(Reg, RegState::Undef);
5409     MI.addRegisterKilled(Reg, TRI, true);
5410   } else if (X86::VR256RegClass.contains(Reg)) {
5411     // Use vxorps to clear the full ymm register.
5412     // It wants to read and write the xmm sub-register.
5413     Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5414     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
5415         .addReg(XReg, RegState::Undef)
5416         .addReg(XReg, RegState::Undef)
5417         .addReg(Reg, RegState::ImplicitDefine);
5418     MI.addRegisterKilled(Reg, TRI, true);
5419   } else if (X86::GR64RegClass.contains(Reg)) {
5420     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
5421     // as well.
5422     Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
5423     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
5424         .addReg(XReg, RegState::Undef)
5425         .addReg(XReg, RegState::Undef)
5426         .addReg(Reg, RegState::ImplicitDefine);
5427     MI.addRegisterKilled(Reg, TRI, true);
5428   } else if (X86::GR32RegClass.contains(Reg)) {
5429     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
5430         .addReg(Reg, RegState::Undef)
5431         .addReg(Reg, RegState::Undef);
5432     MI.addRegisterKilled(Reg, TRI, true);
5433   }
5434 }
5435 
5436 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5437                         int PtrOffset = 0) {
5438   unsigned NumAddrOps = MOs.size();
5439 
5440   if (NumAddrOps < 4) {
5441     // FrameIndex only - add an immediate offset (whether its zero or not).
5442     for (unsigned i = 0; i != NumAddrOps; ++i)
5443       MIB.add(MOs[i]);
5444     addOffset(MIB, PtrOffset);
5445   } else {
5446     // General Memory Addressing - we need to add any offset to an existing
5447     // offset.
5448     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5449     for (unsigned i = 0; i != NumAddrOps; ++i) {
5450       const MachineOperand &MO = MOs[i];
5451       if (i == 3 && PtrOffset != 0) {
5452         MIB.addDisp(MO, PtrOffset);
5453       } else {
5454         MIB.add(MO);
5455       }
5456     }
5457   }
5458 }
5459 
5460 static void updateOperandRegConstraints(MachineFunction &MF,
5461                                         MachineInstr &NewMI,
5462                                         const TargetInstrInfo &TII) {
5463   MachineRegisterInfo &MRI = MF.getRegInfo();
5464   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
5465 
5466   for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
5467     MachineOperand &MO = NewMI.getOperand(Idx);
5468     // We only need to update constraints on virtual register operands.
5469     if (!MO.isReg())
5470       continue;
5471     Register Reg = MO.getReg();
5472     if (!Reg.isVirtual())
5473       continue;
5474 
5475     auto *NewRC = MRI.constrainRegClass(
5476         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
5477     if (!NewRC) {
5478       LLVM_DEBUG(
5479           dbgs() << "WARNING: Unable to update register constraint for operand "
5480                  << Idx << " of instruction:\n";
5481           NewMI.dump(); dbgs() << "\n");
5482     }
5483   }
5484 }
5485 
5486 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5487                                      ArrayRef<MachineOperand> MOs,
5488                                      MachineBasicBlock::iterator InsertPt,
5489                                      MachineInstr &MI,
5490                                      const TargetInstrInfo &TII) {
5491   // Create the base instruction with the memory operand as the first part.
5492   // Omit the implicit operands, something BuildMI can't do.
5493   MachineInstr *NewMI =
5494       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5495   MachineInstrBuilder MIB(MF, NewMI);
5496   addOperands(MIB, MOs);
5497 
5498   // Loop over the rest of the ri operands, converting them over.
5499   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5500   for (unsigned i = 0; i != NumOps; ++i) {
5501     MachineOperand &MO = MI.getOperand(i + 2);
5502     MIB.add(MO);
5503   }
5504   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5505     MachineOperand &MO = MI.getOperand(i);
5506     MIB.add(MO);
5507   }
5508 
5509   updateOperandRegConstraints(MF, *NewMI, TII);
5510 
5511   MachineBasicBlock *MBB = InsertPt->getParent();
5512   MBB->insert(InsertPt, NewMI);
5513 
5514   return MIB;
5515 }
5516 
5517 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5518                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5519                               MachineBasicBlock::iterator InsertPt,
5520                               MachineInstr &MI, const TargetInstrInfo &TII,
5521                               int PtrOffset = 0) {
5522   // Omit the implicit operands, something BuildMI can't do.
5523   MachineInstr *NewMI =
5524       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5525   MachineInstrBuilder MIB(MF, NewMI);
5526 
5527   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5528     MachineOperand &MO = MI.getOperand(i);
5529     if (i == OpNo) {
5530       assert(MO.isReg() && "Expected to fold into reg operand!");
5531       addOperands(MIB, MOs, PtrOffset);
5532     } else {
5533       MIB.add(MO);
5534     }
5535   }
5536 
5537   updateOperandRegConstraints(MF, *NewMI, TII);
5538 
5539   // Copy the NoFPExcept flag from the instruction we're fusing.
5540   if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
5541     NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
5542 
5543   MachineBasicBlock *MBB = InsertPt->getParent();
5544   MBB->insert(InsertPt, NewMI);
5545 
5546   return MIB;
5547 }
5548 
5549 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5550                                 ArrayRef<MachineOperand> MOs,
5551                                 MachineBasicBlock::iterator InsertPt,
5552                                 MachineInstr &MI) {
5553   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5554                                     MI.getDebugLoc(), TII.get(Opcode));
5555   addOperands(MIB, MOs);
5556   return MIB.addImm(0);
5557 }
5558 
5559 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5560     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5561     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5562     unsigned Size, Align Alignment) const {
5563   switch (MI.getOpcode()) {
5564   case X86::INSERTPSrr:
5565   case X86::VINSERTPSrr:
5566   case X86::VINSERTPSZrr:
5567     // Attempt to convert the load of inserted vector into a fold load
5568     // of a single float.
5569     if (OpNum == 2) {
5570       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5571       unsigned ZMask = Imm & 15;
5572       unsigned DstIdx = (Imm >> 4) & 3;
5573       unsigned SrcIdx = (Imm >> 6) & 3;
5574 
5575       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5576       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5577       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5578       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(4)) {
5579         int PtrOffset = SrcIdx * 4;
5580         unsigned NewImm = (DstIdx << 4) | ZMask;
5581         unsigned NewOpCode =
5582             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5583             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
5584                                                     X86::INSERTPSrm;
5585         MachineInstr *NewMI =
5586             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5587         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5588         return NewMI;
5589       }
5590     }
5591     break;
5592   case X86::MOVHLPSrr:
5593   case X86::VMOVHLPSrr:
5594   case X86::VMOVHLPSZrr:
5595     // Move the upper 64-bits of the second operand to the lower 64-bits.
5596     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5597     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5598     if (OpNum == 2) {
5599       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5600       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5601       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5602       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
5603         unsigned NewOpCode =
5604             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5605             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
5606                                                    X86::MOVLPSrm;
5607         MachineInstr *NewMI =
5608             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5609         return NewMI;
5610       }
5611     }
5612     break;
5613   case X86::UNPCKLPDrr:
5614     // If we won't be able to fold this to the memory form of UNPCKL, use
5615     // MOVHPD instead. Done as custom because we can't have this in the load
5616     // table twice.
5617     if (OpNum == 2) {
5618       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5619       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5620       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5621       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
5622         MachineInstr *NewMI =
5623             FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
5624         return NewMI;
5625       }
5626     }
5627     break;
5628   }
5629 
5630   return nullptr;
5631 }
5632 
5633 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
5634                                                MachineInstr &MI) {
5635   if (!hasUndefRegUpdate(MI.getOpcode(), 1, /*ForLoadFold*/true) ||
5636       !MI.getOperand(1).isReg())
5637     return false;
5638 
5639   // The are two cases we need to handle depending on where in the pipeline
5640   // the folding attempt is being made.
5641   // -Register has the undef flag set.
5642   // -Register is produced by the IMPLICIT_DEF instruction.
5643 
5644   if (MI.getOperand(1).isUndef())
5645     return true;
5646 
5647   MachineRegisterInfo &RegInfo = MF.getRegInfo();
5648   MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
5649   return VRegDef && VRegDef->isImplicitDef();
5650 }
5651 
5652 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5653     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5654     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5655     unsigned Size, Align Alignment, bool AllowCommute) const {
5656   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
5657   bool isTwoAddrFold = false;
5658 
5659   // For CPUs that favor the register form of a call or push,
5660   // do not fold loads into calls or pushes, unless optimizing for size
5661   // aggressively.
5662   if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
5663       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5664        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5665        MI.getOpcode() == X86::PUSH64r))
5666     return nullptr;
5667 
5668   // Avoid partial and undef register update stalls unless optimizing for size.
5669   if (!MF.getFunction().hasOptSize() &&
5670       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5671        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5672     return nullptr;
5673 
5674   unsigned NumOps = MI.getDesc().getNumOperands();
5675   bool isTwoAddr =
5676       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5677 
5678   // FIXME: AsmPrinter doesn't know how to handle
5679   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5680   if (MI.getOpcode() == X86::ADD32ri &&
5681       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5682     return nullptr;
5683 
5684   // GOTTPOFF relocation loads can only be folded into add instructions.
5685   // FIXME: Need to exclude other relocations that only support specific
5686   // instructions.
5687   if (MOs.size() == X86::AddrNumOperands &&
5688       MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
5689       MI.getOpcode() != X86::ADD64rr)
5690     return nullptr;
5691 
5692   MachineInstr *NewMI = nullptr;
5693 
5694   // Attempt to fold any custom cases we have.
5695   if (MachineInstr *CustomMI = foldMemoryOperandCustom(
5696           MF, MI, OpNum, MOs, InsertPt, Size, Alignment))
5697     return CustomMI;
5698 
5699   const X86MemoryFoldTableEntry *I = nullptr;
5700 
5701   // Folding a memory location into the two-address part of a two-address
5702   // instruction is different than folding it other places.  It requires
5703   // replacing the *two* registers with the memory location.
5704   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5705       MI.getOperand(1).isReg() &&
5706       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5707     I = lookupTwoAddrFoldTable(MI.getOpcode());
5708     isTwoAddrFold = true;
5709   } else {
5710     if (OpNum == 0) {
5711       if (MI.getOpcode() == X86::MOV32r0) {
5712         NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5713         if (NewMI)
5714           return NewMI;
5715       }
5716     }
5717 
5718     I = lookupFoldTable(MI.getOpcode(), OpNum);
5719   }
5720 
5721   if (I != nullptr) {
5722     unsigned Opcode = I->DstOp;
5723     bool FoldedLoad =
5724         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_LOAD) || OpNum > 0;
5725     bool FoldedStore =
5726         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_STORE);
5727     MaybeAlign MinAlign =
5728         decodeMaybeAlign((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT);
5729     if (MinAlign && Alignment < *MinAlign)
5730       return nullptr;
5731     bool NarrowToMOV32rm = false;
5732     if (Size) {
5733       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5734       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
5735                                                   &RI, MF);
5736       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5737       // Check if it's safe to fold the load. If the size of the object is
5738       // narrower than the load width, then it's not.
5739       // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
5740       if (FoldedLoad && Size < RCSize) {
5741         // If this is a 64-bit load, but the spill slot is 32, then we can do
5742         // a 32-bit load which is implicitly zero-extended. This likely is
5743         // due to live interval analysis remat'ing a load from stack slot.
5744         if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5745           return nullptr;
5746         if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5747           return nullptr;
5748         Opcode = X86::MOV32rm;
5749         NarrowToMOV32rm = true;
5750       }
5751       // For stores, make sure the size of the object is equal to the size of
5752       // the store. If the object is larger, the extra bits would be garbage. If
5753       // the object is smaller we might overwrite another object or fault.
5754       if (FoldedStore && Size != RCSize)
5755         return nullptr;
5756     }
5757 
5758     if (isTwoAddrFold)
5759       NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5760     else
5761       NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5762 
5763     if (NarrowToMOV32rm) {
5764       // If this is the special case where we use a MOV32rm to load a 32-bit
5765       // value and zero-extend the top bits. Change the destination register
5766       // to a 32-bit one.
5767       Register DstReg = NewMI->getOperand(0).getReg();
5768       if (DstReg.isPhysical())
5769         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5770       else
5771         NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5772     }
5773     return NewMI;
5774   }
5775 
5776   // If the instruction and target operand are commutable, commute the
5777   // instruction and try again.
5778   if (AllowCommute) {
5779     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5780     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5781       bool HasDef = MI.getDesc().getNumDefs();
5782       Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
5783       Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5784       Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5785       bool Tied1 =
5786           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5787       bool Tied2 =
5788           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5789 
5790       // If either of the commutable operands are tied to the destination
5791       // then we can not commute + fold.
5792       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5793           (HasDef && Reg0 == Reg2 && Tied2))
5794         return nullptr;
5795 
5796       MachineInstr *CommutedMI =
5797           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5798       if (!CommutedMI) {
5799         // Unable to commute.
5800         return nullptr;
5801       }
5802       if (CommutedMI != &MI) {
5803         // New instruction. We can't fold from this.
5804         CommutedMI->eraseFromParent();
5805         return nullptr;
5806       }
5807 
5808       // Attempt to fold with the commuted version of the instruction.
5809       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, Size,
5810                                     Alignment, /*AllowCommute=*/false);
5811       if (NewMI)
5812         return NewMI;
5813 
5814       // Folding failed again - undo the commute before returning.
5815       MachineInstr *UncommutedMI =
5816           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5817       if (!UncommutedMI) {
5818         // Unable to commute.
5819         return nullptr;
5820       }
5821       if (UncommutedMI != &MI) {
5822         // New instruction. It doesn't need to be kept.
5823         UncommutedMI->eraseFromParent();
5824         return nullptr;
5825       }
5826 
5827       // Return here to prevent duplicate fuse failure report.
5828       return nullptr;
5829     }
5830   }
5831 
5832   // No fusion
5833   if (PrintFailedFusing && !MI.isCopy())
5834     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
5835   return nullptr;
5836 }
5837 
5838 MachineInstr *
5839 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
5840                                     ArrayRef<unsigned> Ops,
5841                                     MachineBasicBlock::iterator InsertPt,
5842                                     int FrameIndex, LiveIntervals *LIS,
5843                                     VirtRegMap *VRM) const {
5844   // Check switch flag
5845   if (NoFusing)
5846     return nullptr;
5847 
5848   // Avoid partial and undef register update stalls unless optimizing for size.
5849   if (!MF.getFunction().hasOptSize() &&
5850       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5851        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5852     return nullptr;
5853 
5854   // Don't fold subreg spills, or reloads that use a high subreg.
5855   for (auto Op : Ops) {
5856     MachineOperand &MO = MI.getOperand(Op);
5857     auto SubReg = MO.getSubReg();
5858     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
5859       return nullptr;
5860   }
5861 
5862   const MachineFrameInfo &MFI = MF.getFrameInfo();
5863   unsigned Size = MFI.getObjectSize(FrameIndex);
5864   Align Alignment = MFI.getObjectAlign(FrameIndex);
5865   // If the function stack isn't realigned we don't want to fold instructions
5866   // that need increased alignment.
5867   if (!RI.hasStackRealignment(MF))
5868     Alignment =
5869         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlign());
5870   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5871     unsigned NewOpc = 0;
5872     unsigned RCSize = 0;
5873     switch (MI.getOpcode()) {
5874     default: return nullptr;
5875     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5876     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5877     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5878     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5879     }
5880     // Check if it's safe to fold the load. If the size of the object is
5881     // narrower than the load width, then it's not.
5882     if (Size < RCSize)
5883       return nullptr;
5884     // Change to CMPXXri r, 0 first.
5885     MI.setDesc(get(NewOpc));
5886     MI.getOperand(1).ChangeToImmediate(0);
5887   } else if (Ops.size() != 1)
5888     return nullptr;
5889 
5890   return foldMemoryOperandImpl(MF, MI, Ops[0],
5891                                MachineOperand::CreateFI(FrameIndex), InsertPt,
5892                                Size, Alignment, /*AllowCommute=*/true);
5893 }
5894 
5895 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5896 /// because the latter uses contents that wouldn't be defined in the folded
5897 /// version.  For instance, this transformation isn't legal:
5898 ///   movss (%rdi), %xmm0
5899 ///   addps %xmm0, %xmm0
5900 /// ->
5901 ///   addps (%rdi), %xmm0
5902 ///
5903 /// But this one is:
5904 ///   movss (%rdi), %xmm0
5905 ///   addss %xmm0, %xmm0
5906 /// ->
5907 ///   addss (%rdi), %xmm0
5908 ///
5909 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5910                                              const MachineInstr &UserMI,
5911                                              const MachineFunction &MF) {
5912   unsigned Opc = LoadMI.getOpcode();
5913   unsigned UserOpc = UserMI.getOpcode();
5914   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5915   const TargetRegisterClass *RC =
5916       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5917   unsigned RegSize = TRI.getRegSizeInBits(*RC);
5918 
5919   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
5920        Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
5921        Opc == X86::VMOVSSZrm_alt) &&
5922       RegSize > 32) {
5923     // These instructions only load 32 bits, we can't fold them if the
5924     // destination register is wider than 32 bits (4 bytes), and its user
5925     // instruction isn't scalar (SS).
5926     switch (UserOpc) {
5927     case X86::CVTSS2SDrr_Int:
5928     case X86::VCVTSS2SDrr_Int:
5929     case X86::VCVTSS2SDZrr_Int:
5930     case X86::VCVTSS2SDZrr_Intk:
5931     case X86::VCVTSS2SDZrr_Intkz:
5932     case X86::CVTSS2SIrr_Int:     case X86::CVTSS2SI64rr_Int:
5933     case X86::VCVTSS2SIrr_Int:    case X86::VCVTSS2SI64rr_Int:
5934     case X86::VCVTSS2SIZrr_Int:   case X86::VCVTSS2SI64Zrr_Int:
5935     case X86::CVTTSS2SIrr_Int:    case X86::CVTTSS2SI64rr_Int:
5936     case X86::VCVTTSS2SIrr_Int:   case X86::VCVTTSS2SI64rr_Int:
5937     case X86::VCVTTSS2SIZrr_Int:  case X86::VCVTTSS2SI64Zrr_Int:
5938     case X86::VCVTSS2USIZrr_Int:  case X86::VCVTSS2USI64Zrr_Int:
5939     case X86::VCVTTSS2USIZrr_Int: case X86::VCVTTSS2USI64Zrr_Int:
5940     case X86::RCPSSr_Int:   case X86::VRCPSSr_Int:
5941     case X86::RSQRTSSr_Int: case X86::VRSQRTSSr_Int:
5942     case X86::ROUNDSSr_Int: case X86::VROUNDSSr_Int:
5943     case X86::COMISSrr_Int: case X86::VCOMISSrr_Int: case X86::VCOMISSZrr_Int:
5944     case X86::UCOMISSrr_Int:case X86::VUCOMISSrr_Int:case X86::VUCOMISSZrr_Int:
5945     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5946     case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5947     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5948     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5949     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5950     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5951     case X86::SQRTSSr_Int: case X86::VSQRTSSr_Int: case X86::VSQRTSSZr_Int:
5952     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5953     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5954     case X86::VCMPSSZrr_Intk:
5955     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5956     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5957     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5958     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5959     case X86::VSQRTSSZr_Intk: case X86::VSQRTSSZr_Intkz:
5960     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5961     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
5962     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
5963     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
5964     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
5965     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
5966     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
5967     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
5968     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
5969     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5970     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5971     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5972     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5973     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5974     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5975     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5976     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5977     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5978     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5979     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5980     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5981     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5982     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5983     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5984     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5985     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5986     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5987     case X86::VFIXUPIMMSSZrri:
5988     case X86::VFIXUPIMMSSZrrik:
5989     case X86::VFIXUPIMMSSZrrikz:
5990     case X86::VFPCLASSSSZrr:
5991     case X86::VFPCLASSSSZrrk:
5992     case X86::VGETEXPSSZr:
5993     case X86::VGETEXPSSZrk:
5994     case X86::VGETEXPSSZrkz:
5995     case X86::VGETMANTSSZrri:
5996     case X86::VGETMANTSSZrrik:
5997     case X86::VGETMANTSSZrrikz:
5998     case X86::VRANGESSZrri:
5999     case X86::VRANGESSZrrik:
6000     case X86::VRANGESSZrrikz:
6001     case X86::VRCP14SSZrr:
6002     case X86::VRCP14SSZrrk:
6003     case X86::VRCP14SSZrrkz:
6004     case X86::VRCP28SSZr:
6005     case X86::VRCP28SSZrk:
6006     case X86::VRCP28SSZrkz:
6007     case X86::VREDUCESSZrri:
6008     case X86::VREDUCESSZrrik:
6009     case X86::VREDUCESSZrrikz:
6010     case X86::VRNDSCALESSZr_Int:
6011     case X86::VRNDSCALESSZr_Intk:
6012     case X86::VRNDSCALESSZr_Intkz:
6013     case X86::VRSQRT14SSZrr:
6014     case X86::VRSQRT14SSZrrk:
6015     case X86::VRSQRT14SSZrrkz:
6016     case X86::VRSQRT28SSZr:
6017     case X86::VRSQRT28SSZrk:
6018     case X86::VRSQRT28SSZrkz:
6019     case X86::VSCALEFSSZrr:
6020     case X86::VSCALEFSSZrrk:
6021     case X86::VSCALEFSSZrrkz:
6022       return false;
6023     default:
6024       return true;
6025     }
6026   }
6027 
6028   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
6029        Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
6030        Opc == X86::VMOVSDZrm_alt) &&
6031       RegSize > 64) {
6032     // These instructions only load 64 bits, we can't fold them if the
6033     // destination register is wider than 64 bits (8 bytes), and its user
6034     // instruction isn't scalar (SD).
6035     switch (UserOpc) {
6036     case X86::CVTSD2SSrr_Int:
6037     case X86::VCVTSD2SSrr_Int:
6038     case X86::VCVTSD2SSZrr_Int:
6039     case X86::VCVTSD2SSZrr_Intk:
6040     case X86::VCVTSD2SSZrr_Intkz:
6041     case X86::CVTSD2SIrr_Int:     case X86::CVTSD2SI64rr_Int:
6042     case X86::VCVTSD2SIrr_Int:    case X86::VCVTSD2SI64rr_Int:
6043     case X86::VCVTSD2SIZrr_Int:   case X86::VCVTSD2SI64Zrr_Int:
6044     case X86::CVTTSD2SIrr_Int:    case X86::CVTTSD2SI64rr_Int:
6045     case X86::VCVTTSD2SIrr_Int:   case X86::VCVTTSD2SI64rr_Int:
6046     case X86::VCVTTSD2SIZrr_Int:  case X86::VCVTTSD2SI64Zrr_Int:
6047     case X86::VCVTSD2USIZrr_Int:  case X86::VCVTSD2USI64Zrr_Int:
6048     case X86::VCVTTSD2USIZrr_Int: case X86::VCVTTSD2USI64Zrr_Int:
6049     case X86::ROUNDSDr_Int: case X86::VROUNDSDr_Int:
6050     case X86::COMISDrr_Int: case X86::VCOMISDrr_Int: case X86::VCOMISDZrr_Int:
6051     case X86::UCOMISDrr_Int:case X86::VUCOMISDrr_Int:case X86::VUCOMISDZrr_Int:
6052     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
6053     case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
6054     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
6055     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
6056     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
6057     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
6058     case X86::SQRTSDr_Int: case X86::VSQRTSDr_Int: case X86::VSQRTSDZr_Int:
6059     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
6060     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
6061     case X86::VCMPSDZrr_Intk:
6062     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
6063     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
6064     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
6065     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
6066     case X86::VSQRTSDZr_Intk: case X86::VSQRTSDZr_Intkz:
6067     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
6068     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
6069     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
6070     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
6071     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
6072     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
6073     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
6074     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
6075     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
6076     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
6077     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
6078     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
6079     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
6080     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
6081     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
6082     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
6083     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
6084     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
6085     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
6086     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
6087     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
6088     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
6089     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
6090     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
6091     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
6092     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
6093     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
6094     case X86::VFIXUPIMMSDZrri:
6095     case X86::VFIXUPIMMSDZrrik:
6096     case X86::VFIXUPIMMSDZrrikz:
6097     case X86::VFPCLASSSDZrr:
6098     case X86::VFPCLASSSDZrrk:
6099     case X86::VGETEXPSDZr:
6100     case X86::VGETEXPSDZrk:
6101     case X86::VGETEXPSDZrkz:
6102     case X86::VGETMANTSDZrri:
6103     case X86::VGETMANTSDZrrik:
6104     case X86::VGETMANTSDZrrikz:
6105     case X86::VRANGESDZrri:
6106     case X86::VRANGESDZrrik:
6107     case X86::VRANGESDZrrikz:
6108     case X86::VRCP14SDZrr:
6109     case X86::VRCP14SDZrrk:
6110     case X86::VRCP14SDZrrkz:
6111     case X86::VRCP28SDZr:
6112     case X86::VRCP28SDZrk:
6113     case X86::VRCP28SDZrkz:
6114     case X86::VREDUCESDZrri:
6115     case X86::VREDUCESDZrrik:
6116     case X86::VREDUCESDZrrikz:
6117     case X86::VRNDSCALESDZr_Int:
6118     case X86::VRNDSCALESDZr_Intk:
6119     case X86::VRNDSCALESDZr_Intkz:
6120     case X86::VRSQRT14SDZrr:
6121     case X86::VRSQRT14SDZrrk:
6122     case X86::VRSQRT14SDZrrkz:
6123     case X86::VRSQRT28SDZr:
6124     case X86::VRSQRT28SDZrk:
6125     case X86::VRSQRT28SDZrkz:
6126     case X86::VSCALEFSDZrr:
6127     case X86::VSCALEFSDZrrk:
6128     case X86::VSCALEFSDZrrkz:
6129       return false;
6130     default:
6131       return true;
6132     }
6133   }
6134 
6135   if ((Opc == X86::VMOVSHZrm || Opc == X86::VMOVSHZrm_alt) && RegSize > 16) {
6136     // These instructions only load 16 bits, we can't fold them if the
6137     // destination register is wider than 16 bits (2 bytes), and its user
6138     // instruction isn't scalar (SH).
6139     switch (UserOpc) {
6140     case X86::VADDSHZrr_Int:
6141     case X86::VCMPSHZrr_Int:
6142     case X86::VDIVSHZrr_Int:
6143     case X86::VMAXSHZrr_Int:
6144     case X86::VMINSHZrr_Int:
6145     case X86::VMULSHZrr_Int:
6146     case X86::VSUBSHZrr_Int:
6147     case X86::VADDSHZrr_Intk: case X86::VADDSHZrr_Intkz:
6148     case X86::VCMPSHZrr_Intk:
6149     case X86::VDIVSHZrr_Intk: case X86::VDIVSHZrr_Intkz:
6150     case X86::VMAXSHZrr_Intk: case X86::VMAXSHZrr_Intkz:
6151     case X86::VMINSHZrr_Intk: case X86::VMINSHZrr_Intkz:
6152     case X86::VMULSHZrr_Intk: case X86::VMULSHZrr_Intkz:
6153     case X86::VSUBSHZrr_Intk: case X86::VSUBSHZrr_Intkz:
6154     case X86::VFMADD132SHZr_Int: case X86::VFNMADD132SHZr_Int:
6155     case X86::VFMADD213SHZr_Int: case X86::VFNMADD213SHZr_Int:
6156     case X86::VFMADD231SHZr_Int: case X86::VFNMADD231SHZr_Int:
6157     case X86::VFMSUB132SHZr_Int: case X86::VFNMSUB132SHZr_Int:
6158     case X86::VFMSUB213SHZr_Int: case X86::VFNMSUB213SHZr_Int:
6159     case X86::VFMSUB231SHZr_Int: case X86::VFNMSUB231SHZr_Int:
6160     case X86::VFMADD132SHZr_Intk: case X86::VFNMADD132SHZr_Intk:
6161     case X86::VFMADD213SHZr_Intk: case X86::VFNMADD213SHZr_Intk:
6162     case X86::VFMADD231SHZr_Intk: case X86::VFNMADD231SHZr_Intk:
6163     case X86::VFMSUB132SHZr_Intk: case X86::VFNMSUB132SHZr_Intk:
6164     case X86::VFMSUB213SHZr_Intk: case X86::VFNMSUB213SHZr_Intk:
6165     case X86::VFMSUB231SHZr_Intk: case X86::VFNMSUB231SHZr_Intk:
6166     case X86::VFMADD132SHZr_Intkz: case X86::VFNMADD132SHZr_Intkz:
6167     case X86::VFMADD213SHZr_Intkz: case X86::VFNMADD213SHZr_Intkz:
6168     case X86::VFMADD231SHZr_Intkz: case X86::VFNMADD231SHZr_Intkz:
6169     case X86::VFMSUB132SHZr_Intkz: case X86::VFNMSUB132SHZr_Intkz:
6170     case X86::VFMSUB213SHZr_Intkz: case X86::VFNMSUB213SHZr_Intkz:
6171     case X86::VFMSUB231SHZr_Intkz: case X86::VFNMSUB231SHZr_Intkz:
6172       return false;
6173     default:
6174       return true;
6175     }
6176   }
6177 
6178   return false;
6179 }
6180 
6181 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6182     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6183     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
6184     LiveIntervals *LIS) const {
6185 
6186   // TODO: Support the case where LoadMI loads a wide register, but MI
6187   // only uses a subreg.
6188   for (auto Op : Ops) {
6189     if (MI.getOperand(Op).getSubReg())
6190       return nullptr;
6191   }
6192 
6193   // If loading from a FrameIndex, fold directly from the FrameIndex.
6194   unsigned NumOps = LoadMI.getDesc().getNumOperands();
6195   int FrameIndex;
6196   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6197     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6198       return nullptr;
6199     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
6200   }
6201 
6202   // Check switch flag
6203   if (NoFusing) return nullptr;
6204 
6205   // Avoid partial and undef register update stalls unless optimizing for size.
6206   if (!MF.getFunction().hasOptSize() &&
6207       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
6208        shouldPreventUndefRegUpdateMemFold(MF, MI)))
6209     return nullptr;
6210 
6211   // Determine the alignment of the load.
6212   Align Alignment;
6213   if (LoadMI.hasOneMemOperand())
6214     Alignment = (*LoadMI.memoperands_begin())->getAlign();
6215   else
6216     switch (LoadMI.getOpcode()) {
6217     case X86::AVX512_512_SET0:
6218     case X86::AVX512_512_SETALLONES:
6219       Alignment = Align(64);
6220       break;
6221     case X86::AVX2_SETALLONES:
6222     case X86::AVX1_SETALLONES:
6223     case X86::AVX_SET0:
6224     case X86::AVX512_256_SET0:
6225       Alignment = Align(32);
6226       break;
6227     case X86::V_SET0:
6228     case X86::V_SETALLONES:
6229     case X86::AVX512_128_SET0:
6230     case X86::FsFLD0F128:
6231     case X86::AVX512_FsFLD0F128:
6232       Alignment = Align(16);
6233       break;
6234     case X86::MMX_SET0:
6235     case X86::FsFLD0SD:
6236     case X86::AVX512_FsFLD0SD:
6237       Alignment = Align(8);
6238       break;
6239     case X86::FsFLD0SS:
6240     case X86::AVX512_FsFLD0SS:
6241       Alignment = Align(4);
6242       break;
6243     case X86::AVX512_FsFLD0SH:
6244       Alignment = Align(2);
6245       break;
6246     default:
6247       return nullptr;
6248     }
6249   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6250     unsigned NewOpc = 0;
6251     switch (MI.getOpcode()) {
6252     default: return nullptr;
6253     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6254     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6255     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6256     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6257     }
6258     // Change to CMPXXri r, 0 first.
6259     MI.setDesc(get(NewOpc));
6260     MI.getOperand(1).ChangeToImmediate(0);
6261   } else if (Ops.size() != 1)
6262     return nullptr;
6263 
6264   // Make sure the subregisters match.
6265   // Otherwise we risk changing the size of the load.
6266   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6267     return nullptr;
6268 
6269   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6270   switch (LoadMI.getOpcode()) {
6271   case X86::MMX_SET0:
6272   case X86::V_SET0:
6273   case X86::V_SETALLONES:
6274   case X86::AVX2_SETALLONES:
6275   case X86::AVX1_SETALLONES:
6276   case X86::AVX_SET0:
6277   case X86::AVX512_128_SET0:
6278   case X86::AVX512_256_SET0:
6279   case X86::AVX512_512_SET0:
6280   case X86::AVX512_512_SETALLONES:
6281   case X86::AVX512_FsFLD0SH:
6282   case X86::FsFLD0SD:
6283   case X86::AVX512_FsFLD0SD:
6284   case X86::FsFLD0SS:
6285   case X86::AVX512_FsFLD0SS:
6286   case X86::FsFLD0F128:
6287   case X86::AVX512_FsFLD0F128: {
6288     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6289     // Create a constant-pool entry and operands to load from it.
6290 
6291     // Medium and large mode can't fold loads this way.
6292     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6293         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6294       return nullptr;
6295 
6296     // x86-32 PIC requires a PIC base register for constant pools.
6297     unsigned PICBase = 0;
6298     // Since we're using Small or Kernel code model, we can always use
6299     // RIP-relative addressing for a smaller encoding.
6300     if (Subtarget.is64Bit()) {
6301       PICBase = X86::RIP;
6302     } else if (MF.getTarget().isPositionIndependent()) {
6303       // FIXME: PICBase = getGlobalBaseReg(&MF);
6304       // This doesn't work for several reasons.
6305       // 1. GlobalBaseReg may have been spilled.
6306       // 2. It may not be live at MI.
6307       return nullptr;
6308     }
6309 
6310     // Create a constant-pool entry.
6311     MachineConstantPool &MCP = *MF.getConstantPool();
6312     Type *Ty;
6313     unsigned Opc = LoadMI.getOpcode();
6314     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
6315       Ty = Type::getFloatTy(MF.getFunction().getContext());
6316     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
6317       Ty = Type::getDoubleTy(MF.getFunction().getContext());
6318     else if (Opc == X86::FsFLD0F128 || Opc == X86::AVX512_FsFLD0F128)
6319       Ty = Type::getFP128Ty(MF.getFunction().getContext());
6320     else if (Opc == X86::AVX512_FsFLD0SH)
6321       Ty = Type::getHalfTy(MF.getFunction().getContext());
6322     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
6323       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6324                                 16);
6325     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6326              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
6327       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6328                                 8);
6329     else if (Opc == X86::MMX_SET0)
6330       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6331                                 2);
6332     else
6333       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6334                                 4);
6335 
6336     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6337                       Opc == X86::AVX512_512_SETALLONES ||
6338                       Opc == X86::AVX1_SETALLONES);
6339     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6340                                     Constant::getNullValue(Ty);
6341     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6342 
6343     // Create operands to load from the constant pool entry.
6344     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6345     MOs.push_back(MachineOperand::CreateImm(1));
6346     MOs.push_back(MachineOperand::CreateReg(0, false));
6347     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6348     MOs.push_back(MachineOperand::CreateReg(0, false));
6349     break;
6350   }
6351   default: {
6352     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6353       return nullptr;
6354 
6355     // Folding a normal load. Just copy the load's address operands.
6356     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6357                LoadMI.operands_begin() + NumOps);
6358     break;
6359   }
6360   }
6361   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6362                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6363 }
6364 
6365 static SmallVector<MachineMemOperand *, 2>
6366 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6367   SmallVector<MachineMemOperand *, 2> LoadMMOs;
6368 
6369   for (MachineMemOperand *MMO : MMOs) {
6370     if (!MMO->isLoad())
6371       continue;
6372 
6373     if (!MMO->isStore()) {
6374       // Reuse the MMO.
6375       LoadMMOs.push_back(MMO);
6376     } else {
6377       // Clone the MMO and unset the store flag.
6378       LoadMMOs.push_back(MF.getMachineMemOperand(
6379           MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
6380     }
6381   }
6382 
6383   return LoadMMOs;
6384 }
6385 
6386 static SmallVector<MachineMemOperand *, 2>
6387 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6388   SmallVector<MachineMemOperand *, 2> StoreMMOs;
6389 
6390   for (MachineMemOperand *MMO : MMOs) {
6391     if (!MMO->isStore())
6392       continue;
6393 
6394     if (!MMO->isLoad()) {
6395       // Reuse the MMO.
6396       StoreMMOs.push_back(MMO);
6397     } else {
6398       // Clone the MMO and unset the load flag.
6399       StoreMMOs.push_back(MF.getMachineMemOperand(
6400           MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
6401     }
6402   }
6403 
6404   return StoreMMOs;
6405 }
6406 
6407 static unsigned getBroadcastOpcode(const X86MemoryFoldTableEntry *I,
6408                                    const TargetRegisterClass *RC,
6409                                    const X86Subtarget &STI) {
6410   assert(STI.hasAVX512() && "Expected at least AVX512!");
6411   unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
6412   assert((SpillSize == 64 || STI.hasVLX()) &&
6413          "Can't broadcast less than 64 bytes without AVX512VL!");
6414 
6415   switch (I->Flags & TB_BCAST_MASK) {
6416   default: llvm_unreachable("Unexpected broadcast type!");
6417   case TB_BCAST_D:
6418     switch (SpillSize) {
6419     default: llvm_unreachable("Unknown spill size");
6420     case 16: return X86::VPBROADCASTDZ128rm;
6421     case 32: return X86::VPBROADCASTDZ256rm;
6422     case 64: return X86::VPBROADCASTDZrm;
6423     }
6424     break;
6425   case TB_BCAST_Q:
6426     switch (SpillSize) {
6427     default: llvm_unreachable("Unknown spill size");
6428     case 16: return X86::VPBROADCASTQZ128rm;
6429     case 32: return X86::VPBROADCASTQZ256rm;
6430     case 64: return X86::VPBROADCASTQZrm;
6431     }
6432     break;
6433   case TB_BCAST_SS:
6434     switch (SpillSize) {
6435     default: llvm_unreachable("Unknown spill size");
6436     case 16: return X86::VBROADCASTSSZ128rm;
6437     case 32: return X86::VBROADCASTSSZ256rm;
6438     case 64: return X86::VBROADCASTSSZrm;
6439     }
6440     break;
6441   case TB_BCAST_SD:
6442     switch (SpillSize) {
6443     default: llvm_unreachable("Unknown spill size");
6444     case 16: return X86::VMOVDDUPZ128rm;
6445     case 32: return X86::VBROADCASTSDZ256rm;
6446     case 64: return X86::VBROADCASTSDZrm;
6447     }
6448     break;
6449   }
6450 }
6451 
6452 bool X86InstrInfo::unfoldMemoryOperand(
6453     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6454     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6455   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
6456   if (I == nullptr)
6457     return false;
6458   unsigned Opc = I->DstOp;
6459   unsigned Index = I->Flags & TB_INDEX_MASK;
6460   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6461   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6462   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6463   if (UnfoldLoad && !FoldedLoad)
6464     return false;
6465   UnfoldLoad &= FoldedLoad;
6466   if (UnfoldStore && !FoldedStore)
6467     return false;
6468   UnfoldStore &= FoldedStore;
6469 
6470   const MCInstrDesc &MCID = get(Opc);
6471 
6472   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6473   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6474   // TODO: Check if 32-byte or greater accesses are slow too?
6475   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
6476       Subtarget.isUnalignedMem16Slow())
6477     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6478     // conservatively assume the address is unaligned. That's bad for
6479     // performance.
6480     return false;
6481   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6482   SmallVector<MachineOperand,2> BeforeOps;
6483   SmallVector<MachineOperand,2> AfterOps;
6484   SmallVector<MachineOperand,4> ImpOps;
6485   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6486     MachineOperand &Op = MI.getOperand(i);
6487     if (i >= Index && i < Index + X86::AddrNumOperands)
6488       AddrOps.push_back(Op);
6489     else if (Op.isReg() && Op.isImplicit())
6490       ImpOps.push_back(Op);
6491     else if (i < Index)
6492       BeforeOps.push_back(Op);
6493     else if (i > Index)
6494       AfterOps.push_back(Op);
6495   }
6496 
6497   // Emit the load or broadcast instruction.
6498   if (UnfoldLoad) {
6499     auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
6500 
6501     unsigned Opc;
6502     if (FoldedBCast) {
6503       Opc = getBroadcastOpcode(I, RC, Subtarget);
6504     } else {
6505       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6506       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6507       Opc = getLoadRegOpcode(Reg, RC, isAligned, Subtarget);
6508     }
6509 
6510     DebugLoc DL;
6511     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
6512     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6513       MIB.add(AddrOps[i]);
6514     MIB.setMemRefs(MMOs);
6515     NewMIs.push_back(MIB);
6516 
6517     if (UnfoldStore) {
6518       // Address operands cannot be marked isKill.
6519       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6520         MachineOperand &MO = NewMIs[0]->getOperand(i);
6521         if (MO.isReg())
6522           MO.setIsKill(false);
6523       }
6524     }
6525   }
6526 
6527   // Emit the data processing instruction.
6528   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
6529   MachineInstrBuilder MIB(MF, DataMI);
6530 
6531   if (FoldedStore)
6532     MIB.addReg(Reg, RegState::Define);
6533   for (MachineOperand &BeforeOp : BeforeOps)
6534     MIB.add(BeforeOp);
6535   if (FoldedLoad)
6536     MIB.addReg(Reg);
6537   for (MachineOperand &AfterOp : AfterOps)
6538     MIB.add(AfterOp);
6539   for (MachineOperand &ImpOp : ImpOps) {
6540     MIB.addReg(ImpOp.getReg(),
6541                getDefRegState(ImpOp.isDef()) |
6542                RegState::Implicit |
6543                getKillRegState(ImpOp.isKill()) |
6544                getDeadRegState(ImpOp.isDead()) |
6545                getUndefRegState(ImpOp.isUndef()));
6546   }
6547   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6548   switch (DataMI->getOpcode()) {
6549   default: break;
6550   case X86::CMP64ri32:
6551   case X86::CMP64ri8:
6552   case X86::CMP32ri:
6553   case X86::CMP32ri8:
6554   case X86::CMP16ri:
6555   case X86::CMP16ri8:
6556   case X86::CMP8ri: {
6557     MachineOperand &MO0 = DataMI->getOperand(0);
6558     MachineOperand &MO1 = DataMI->getOperand(1);
6559     if (MO1.isImm() && MO1.getImm() == 0) {
6560       unsigned NewOpc;
6561       switch (DataMI->getOpcode()) {
6562       default: llvm_unreachable("Unreachable!");
6563       case X86::CMP64ri8:
6564       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6565       case X86::CMP32ri8:
6566       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6567       case X86::CMP16ri8:
6568       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6569       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6570       }
6571       DataMI->setDesc(get(NewOpc));
6572       MO1.ChangeToRegister(MO0.getReg(), false);
6573     }
6574   }
6575   }
6576   NewMIs.push_back(DataMI);
6577 
6578   // Emit the store instruction.
6579   if (UnfoldStore) {
6580     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6581     auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
6582     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16);
6583     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6584     unsigned Opc = getStoreRegOpcode(Reg, DstRC, isAligned, Subtarget);
6585     DebugLoc DL;
6586     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6587     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6588       MIB.add(AddrOps[i]);
6589     MIB.addReg(Reg, RegState::Kill);
6590     MIB.setMemRefs(MMOs);
6591     NewMIs.push_back(MIB);
6592   }
6593 
6594   return true;
6595 }
6596 
6597 bool
6598 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6599                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6600   if (!N->isMachineOpcode())
6601     return false;
6602 
6603   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
6604   if (I == nullptr)
6605     return false;
6606   unsigned Opc = I->DstOp;
6607   unsigned Index = I->Flags & TB_INDEX_MASK;
6608   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6609   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6610   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6611   const MCInstrDesc &MCID = get(Opc);
6612   MachineFunction &MF = DAG.getMachineFunction();
6613   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6614   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6615   unsigned NumDefs = MCID.NumDefs;
6616   std::vector<SDValue> AddrOps;
6617   std::vector<SDValue> BeforeOps;
6618   std::vector<SDValue> AfterOps;
6619   SDLoc dl(N);
6620   unsigned NumOps = N->getNumOperands();
6621   for (unsigned i = 0; i != NumOps-1; ++i) {
6622     SDValue Op = N->getOperand(i);
6623     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6624       AddrOps.push_back(Op);
6625     else if (i < Index-NumDefs)
6626       BeforeOps.push_back(Op);
6627     else if (i > Index-NumDefs)
6628       AfterOps.push_back(Op);
6629   }
6630   SDValue Chain = N->getOperand(NumOps-1);
6631   AddrOps.push_back(Chain);
6632 
6633   // Emit the load instruction.
6634   SDNode *Load = nullptr;
6635   if (FoldedLoad) {
6636     EVT VT = *TRI.legalclasstypes_begin(*RC);
6637     auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6638     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6639         Subtarget.isUnalignedMem16Slow())
6640       // Do not introduce a slow unaligned load.
6641       return false;
6642     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6643     // memory access is slow above.
6644 
6645     unsigned Opc;
6646     if (FoldedBCast) {
6647       Opc = getBroadcastOpcode(I, RC, Subtarget);
6648     } else {
6649       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6650       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6651       Opc = getLoadRegOpcode(0, RC, isAligned, Subtarget);
6652     }
6653 
6654     Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
6655     NewNodes.push_back(Load);
6656 
6657     // Preserve memory reference information.
6658     DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
6659   }
6660 
6661   // Emit the data processing instruction.
6662   std::vector<EVT> VTs;
6663   const TargetRegisterClass *DstRC = nullptr;
6664   if (MCID.getNumDefs() > 0) {
6665     DstRC = getRegClass(MCID, 0, &RI, MF);
6666     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
6667   }
6668   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6669     EVT VT = N->getValueType(i);
6670     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6671       VTs.push_back(VT);
6672   }
6673   if (Load)
6674     BeforeOps.push_back(SDValue(Load, 0));
6675   llvm::append_range(BeforeOps, AfterOps);
6676   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6677   switch (Opc) {
6678     default: break;
6679     case X86::CMP64ri32:
6680     case X86::CMP64ri8:
6681     case X86::CMP32ri:
6682     case X86::CMP32ri8:
6683     case X86::CMP16ri:
6684     case X86::CMP16ri8:
6685     case X86::CMP8ri:
6686       if (isNullConstant(BeforeOps[1])) {
6687         switch (Opc) {
6688           default: llvm_unreachable("Unreachable!");
6689           case X86::CMP64ri8:
6690           case X86::CMP64ri32: Opc = X86::TEST64rr; break;
6691           case X86::CMP32ri8:
6692           case X86::CMP32ri:   Opc = X86::TEST32rr; break;
6693           case X86::CMP16ri8:
6694           case X86::CMP16ri:   Opc = X86::TEST16rr; break;
6695           case X86::CMP8ri:    Opc = X86::TEST8rr; break;
6696         }
6697         BeforeOps[1] = BeforeOps[0];
6698       }
6699   }
6700   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6701   NewNodes.push_back(NewNode);
6702 
6703   // Emit the store instruction.
6704   if (FoldedStore) {
6705     AddrOps.pop_back();
6706     AddrOps.push_back(SDValue(NewNode, 0));
6707     AddrOps.push_back(Chain);
6708     auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6709     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6710         Subtarget.isUnalignedMem16Slow())
6711       // Do not introduce a slow unaligned store.
6712       return false;
6713     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6714     // memory access is slow above.
6715     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6716     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6717     SDNode *Store =
6718         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6719                            dl, MVT::Other, AddrOps);
6720     NewNodes.push_back(Store);
6721 
6722     // Preserve memory reference information.
6723     DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
6724   }
6725 
6726   return true;
6727 }
6728 
6729 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6730                                       bool UnfoldLoad, bool UnfoldStore,
6731                                       unsigned *LoadRegIndex) const {
6732   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
6733   if (I == nullptr)
6734     return 0;
6735   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6736   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6737   if (UnfoldLoad && !FoldedLoad)
6738     return 0;
6739   if (UnfoldStore && !FoldedStore)
6740     return 0;
6741   if (LoadRegIndex)
6742     *LoadRegIndex = I->Flags & TB_INDEX_MASK;
6743   return I->DstOp;
6744 }
6745 
6746 bool
6747 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6748                                      int64_t &Offset1, int64_t &Offset2) const {
6749   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6750     return false;
6751   unsigned Opc1 = Load1->getMachineOpcode();
6752   unsigned Opc2 = Load2->getMachineOpcode();
6753   switch (Opc1) {
6754   default: return false;
6755   case X86::MOV8rm:
6756   case X86::MOV16rm:
6757   case X86::MOV32rm:
6758   case X86::MOV64rm:
6759   case X86::LD_Fp32m:
6760   case X86::LD_Fp64m:
6761   case X86::LD_Fp80m:
6762   case X86::MOVSSrm:
6763   case X86::MOVSSrm_alt:
6764   case X86::MOVSDrm:
6765   case X86::MOVSDrm_alt:
6766   case X86::MMX_MOVD64rm:
6767   case X86::MMX_MOVQ64rm:
6768   case X86::MOVAPSrm:
6769   case X86::MOVUPSrm:
6770   case X86::MOVAPDrm:
6771   case X86::MOVUPDrm:
6772   case X86::MOVDQArm:
6773   case X86::MOVDQUrm:
6774   // AVX load instructions
6775   case X86::VMOVSSrm:
6776   case X86::VMOVSSrm_alt:
6777   case X86::VMOVSDrm:
6778   case X86::VMOVSDrm_alt:
6779   case X86::VMOVAPSrm:
6780   case X86::VMOVUPSrm:
6781   case X86::VMOVAPDrm:
6782   case X86::VMOVUPDrm:
6783   case X86::VMOVDQArm:
6784   case X86::VMOVDQUrm:
6785   case X86::VMOVAPSYrm:
6786   case X86::VMOVUPSYrm:
6787   case X86::VMOVAPDYrm:
6788   case X86::VMOVUPDYrm:
6789   case X86::VMOVDQAYrm:
6790   case X86::VMOVDQUYrm:
6791   // AVX512 load instructions
6792   case X86::VMOVSSZrm:
6793   case X86::VMOVSSZrm_alt:
6794   case X86::VMOVSDZrm:
6795   case X86::VMOVSDZrm_alt:
6796   case X86::VMOVAPSZ128rm:
6797   case X86::VMOVUPSZ128rm:
6798   case X86::VMOVAPSZ128rm_NOVLX:
6799   case X86::VMOVUPSZ128rm_NOVLX:
6800   case X86::VMOVAPDZ128rm:
6801   case X86::VMOVUPDZ128rm:
6802   case X86::VMOVDQU8Z128rm:
6803   case X86::VMOVDQU16Z128rm:
6804   case X86::VMOVDQA32Z128rm:
6805   case X86::VMOVDQU32Z128rm:
6806   case X86::VMOVDQA64Z128rm:
6807   case X86::VMOVDQU64Z128rm:
6808   case X86::VMOVAPSZ256rm:
6809   case X86::VMOVUPSZ256rm:
6810   case X86::VMOVAPSZ256rm_NOVLX:
6811   case X86::VMOVUPSZ256rm_NOVLX:
6812   case X86::VMOVAPDZ256rm:
6813   case X86::VMOVUPDZ256rm:
6814   case X86::VMOVDQU8Z256rm:
6815   case X86::VMOVDQU16Z256rm:
6816   case X86::VMOVDQA32Z256rm:
6817   case X86::VMOVDQU32Z256rm:
6818   case X86::VMOVDQA64Z256rm:
6819   case X86::VMOVDQU64Z256rm:
6820   case X86::VMOVAPSZrm:
6821   case X86::VMOVUPSZrm:
6822   case X86::VMOVAPDZrm:
6823   case X86::VMOVUPDZrm:
6824   case X86::VMOVDQU8Zrm:
6825   case X86::VMOVDQU16Zrm:
6826   case X86::VMOVDQA32Zrm:
6827   case X86::VMOVDQU32Zrm:
6828   case X86::VMOVDQA64Zrm:
6829   case X86::VMOVDQU64Zrm:
6830   case X86::KMOVBkm:
6831   case X86::KMOVWkm:
6832   case X86::KMOVDkm:
6833   case X86::KMOVQkm:
6834     break;
6835   }
6836   switch (Opc2) {
6837   default: return false;
6838   case X86::MOV8rm:
6839   case X86::MOV16rm:
6840   case X86::MOV32rm:
6841   case X86::MOV64rm:
6842   case X86::LD_Fp32m:
6843   case X86::LD_Fp64m:
6844   case X86::LD_Fp80m:
6845   case X86::MOVSSrm:
6846   case X86::MOVSSrm_alt:
6847   case X86::MOVSDrm:
6848   case X86::MOVSDrm_alt:
6849   case X86::MMX_MOVD64rm:
6850   case X86::MMX_MOVQ64rm:
6851   case X86::MOVAPSrm:
6852   case X86::MOVUPSrm:
6853   case X86::MOVAPDrm:
6854   case X86::MOVUPDrm:
6855   case X86::MOVDQArm:
6856   case X86::MOVDQUrm:
6857   // AVX load instructions
6858   case X86::VMOVSSrm:
6859   case X86::VMOVSSrm_alt:
6860   case X86::VMOVSDrm:
6861   case X86::VMOVSDrm_alt:
6862   case X86::VMOVAPSrm:
6863   case X86::VMOVUPSrm:
6864   case X86::VMOVAPDrm:
6865   case X86::VMOVUPDrm:
6866   case X86::VMOVDQArm:
6867   case X86::VMOVDQUrm:
6868   case X86::VMOVAPSYrm:
6869   case X86::VMOVUPSYrm:
6870   case X86::VMOVAPDYrm:
6871   case X86::VMOVUPDYrm:
6872   case X86::VMOVDQAYrm:
6873   case X86::VMOVDQUYrm:
6874   // AVX512 load instructions
6875   case X86::VMOVSSZrm:
6876   case X86::VMOVSSZrm_alt:
6877   case X86::VMOVSDZrm:
6878   case X86::VMOVSDZrm_alt:
6879   case X86::VMOVAPSZ128rm:
6880   case X86::VMOVUPSZ128rm:
6881   case X86::VMOVAPSZ128rm_NOVLX:
6882   case X86::VMOVUPSZ128rm_NOVLX:
6883   case X86::VMOVAPDZ128rm:
6884   case X86::VMOVUPDZ128rm:
6885   case X86::VMOVDQU8Z128rm:
6886   case X86::VMOVDQU16Z128rm:
6887   case X86::VMOVDQA32Z128rm:
6888   case X86::VMOVDQU32Z128rm:
6889   case X86::VMOVDQA64Z128rm:
6890   case X86::VMOVDQU64Z128rm:
6891   case X86::VMOVAPSZ256rm:
6892   case X86::VMOVUPSZ256rm:
6893   case X86::VMOVAPSZ256rm_NOVLX:
6894   case X86::VMOVUPSZ256rm_NOVLX:
6895   case X86::VMOVAPDZ256rm:
6896   case X86::VMOVUPDZ256rm:
6897   case X86::VMOVDQU8Z256rm:
6898   case X86::VMOVDQU16Z256rm:
6899   case X86::VMOVDQA32Z256rm:
6900   case X86::VMOVDQU32Z256rm:
6901   case X86::VMOVDQA64Z256rm:
6902   case X86::VMOVDQU64Z256rm:
6903   case X86::VMOVAPSZrm:
6904   case X86::VMOVUPSZrm:
6905   case X86::VMOVAPDZrm:
6906   case X86::VMOVUPDZrm:
6907   case X86::VMOVDQU8Zrm:
6908   case X86::VMOVDQU16Zrm:
6909   case X86::VMOVDQA32Zrm:
6910   case X86::VMOVDQU32Zrm:
6911   case X86::VMOVDQA64Zrm:
6912   case X86::VMOVDQU64Zrm:
6913   case X86::KMOVBkm:
6914   case X86::KMOVWkm:
6915   case X86::KMOVDkm:
6916   case X86::KMOVQkm:
6917     break;
6918   }
6919 
6920   // Lambda to check if both the loads have the same value for an operand index.
6921   auto HasSameOp = [&](int I) {
6922     return Load1->getOperand(I) == Load2->getOperand(I);
6923   };
6924 
6925   // All operands except the displacement should match.
6926   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
6927       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
6928     return false;
6929 
6930   // Chain Operand must be the same.
6931   if (!HasSameOp(5))
6932     return false;
6933 
6934   // Now let's examine if the displacements are constants.
6935   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
6936   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
6937   if (!Disp1 || !Disp2)
6938     return false;
6939 
6940   Offset1 = Disp1->getSExtValue();
6941   Offset2 = Disp2->getSExtValue();
6942   return true;
6943 }
6944 
6945 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6946                                            int64_t Offset1, int64_t Offset2,
6947                                            unsigned NumLoads) const {
6948   assert(Offset2 > Offset1);
6949   if ((Offset2 - Offset1) / 8 > 64)
6950     return false;
6951 
6952   unsigned Opc1 = Load1->getMachineOpcode();
6953   unsigned Opc2 = Load2->getMachineOpcode();
6954   if (Opc1 != Opc2)
6955     return false;  // FIXME: overly conservative?
6956 
6957   switch (Opc1) {
6958   default: break;
6959   case X86::LD_Fp32m:
6960   case X86::LD_Fp64m:
6961   case X86::LD_Fp80m:
6962   case X86::MMX_MOVD64rm:
6963   case X86::MMX_MOVQ64rm:
6964     return false;
6965   }
6966 
6967   EVT VT = Load1->getValueType(0);
6968   switch (VT.getSimpleVT().SimpleTy) {
6969   default:
6970     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6971     // have 16 of them to play with.
6972     if (Subtarget.is64Bit()) {
6973       if (NumLoads >= 3)
6974         return false;
6975     } else if (NumLoads) {
6976       return false;
6977     }
6978     break;
6979   case MVT::i8:
6980   case MVT::i16:
6981   case MVT::i32:
6982   case MVT::i64:
6983   case MVT::f32:
6984   case MVT::f64:
6985     if (NumLoads)
6986       return false;
6987     break;
6988   }
6989 
6990   return true;
6991 }
6992 
6993 bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
6994                                         const MachineBasicBlock *MBB,
6995                                         const MachineFunction &MF) const {
6996 
6997   // ENDBR instructions should not be scheduled around.
6998   unsigned Opcode = MI.getOpcode();
6999   if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32 ||
7000       Opcode == X86::LDTILECFG)
7001     return true;
7002 
7003   return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
7004 }
7005 
7006 bool X86InstrInfo::
7007 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
7008   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
7009   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
7010   Cond[0].setImm(GetOppositeBranchCondition(CC));
7011   return false;
7012 }
7013 
7014 bool X86InstrInfo::
7015 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
7016   // FIXME: Return false for x87 stack register classes for now. We can't
7017   // allow any loads of these registers before FpGet_ST0_80.
7018   return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
7019            RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
7020            RC == &X86::RFP80RegClass);
7021 }
7022 
7023 /// Return a virtual register initialized with the
7024 /// the global base register value. Output instructions required to
7025 /// initialize the register in the function entry block, if necessary.
7026 ///
7027 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
7028 ///
7029 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
7030   assert((!Subtarget.is64Bit() ||
7031           MF->getTarget().getCodeModel() == CodeModel::Medium ||
7032           MF->getTarget().getCodeModel() == CodeModel::Large) &&
7033          "X86-64 PIC uses RIP relative addressing");
7034 
7035   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
7036   Register GlobalBaseReg = X86FI->getGlobalBaseReg();
7037   if (GlobalBaseReg != 0)
7038     return GlobalBaseReg;
7039 
7040   // Create the register. The code to initialize it is inserted
7041   // later, by the CGBR pass (below).
7042   MachineRegisterInfo &RegInfo = MF->getRegInfo();
7043   GlobalBaseReg = RegInfo.createVirtualRegister(
7044       Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
7045   X86FI->setGlobalBaseReg(GlobalBaseReg);
7046   return GlobalBaseReg;
7047 }
7048 
7049 // These are the replaceable SSE instructions. Some of these have Int variants
7050 // that we don't include here. We don't want to replace instructions selected
7051 // by intrinsics.
7052 static const uint16_t ReplaceableInstrs[][3] = {
7053   //PackedSingle     PackedDouble    PackedInt
7054   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
7055   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
7056   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
7057   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
7058   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
7059   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
7060   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
7061   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
7062   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
7063   { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
7064   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
7065   { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
7066   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
7067   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
7068   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
7069   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
7070   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
7071   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
7072   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
7073   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
7074   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
7075   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
7076   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
7077   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
7078   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
7079   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
7080   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
7081   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
7082   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
7083   { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
7084   { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
7085   // AVX 128-bit support
7086   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
7087   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
7088   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
7089   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
7090   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
7091   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
7092   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
7093   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
7094   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
7095   { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
7096   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
7097   { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
7098   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7099   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
7100   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
7101   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
7102   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
7103   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
7104   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
7105   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
7106   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
7107   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
7108   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
7109   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
7110   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
7111   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
7112   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
7113   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
7114   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
7115   { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
7116   { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
7117   // AVX 256-bit support
7118   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
7119   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
7120   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
7121   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
7122   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
7123   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
7124   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
7125   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
7126   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
7127   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
7128   // AVX512 support
7129   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
7130   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7131   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
7132   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
7133   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
7134   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
7135   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
7136   { X86::VMOVSDZrm_alt,  X86::VMOVSDZrm_alt,  X86::VMOVQI2PQIZrm  },
7137   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
7138   { X86::VMOVSSZrm_alt,  X86::VMOVSSZrm_alt,  X86::VMOVDI2PDIZrm  },
7139   { X86::VBROADCASTSSZ128rr,X86::VBROADCASTSSZ128rr,X86::VPBROADCASTDZ128rr },
7140   { X86::VBROADCASTSSZ128rm,X86::VBROADCASTSSZ128rm,X86::VPBROADCASTDZ128rm },
7141   { X86::VBROADCASTSSZ256rr,X86::VBROADCASTSSZ256rr,X86::VPBROADCASTDZ256rr },
7142   { X86::VBROADCASTSSZ256rm,X86::VBROADCASTSSZ256rm,X86::VPBROADCASTDZ256rm },
7143   { X86::VBROADCASTSSZrr,   X86::VBROADCASTSSZrr,   X86::VPBROADCASTDZrr },
7144   { X86::VBROADCASTSSZrm,   X86::VBROADCASTSSZrm,   X86::VPBROADCASTDZrm },
7145   { X86::VMOVDDUPZ128rr,    X86::VMOVDDUPZ128rr,    X86::VPBROADCASTQZ128rr },
7146   { X86::VMOVDDUPZ128rm,    X86::VMOVDDUPZ128rm,    X86::VPBROADCASTQZ128rm },
7147   { X86::VBROADCASTSDZ256rr,X86::VBROADCASTSDZ256rr,X86::VPBROADCASTQZ256rr },
7148   { X86::VBROADCASTSDZ256rm,X86::VBROADCASTSDZ256rm,X86::VPBROADCASTQZ256rm },
7149   { X86::VBROADCASTSDZrr,   X86::VBROADCASTSDZrr,   X86::VPBROADCASTQZrr },
7150   { X86::VBROADCASTSDZrm,   X86::VBROADCASTSDZrm,   X86::VPBROADCASTQZrm },
7151   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
7152   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
7153   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
7154   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
7155   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
7156   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
7157   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
7158   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
7159   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
7160   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
7161   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
7162   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
7163   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
7164   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
7165   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
7166   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
7167   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
7168   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
7169   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
7170   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
7171   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
7172   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
7173   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
7174   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
7175   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
7176   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
7177   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
7178   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
7179   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
7180   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
7181   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
7182   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
7183   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
7184   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
7185   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
7186   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
7187   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
7188   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
7189   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
7190   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
7191   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
7192   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
7193   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
7194   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
7195   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
7196   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
7197   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
7198   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
7199   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
7200   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
7201   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
7202   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
7203   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
7204   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
7205   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
7206   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
7207   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
7208   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
7209   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
7210   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
7211   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
7212   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
7213   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
7214   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
7215   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
7216   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
7217   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
7218   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
7219   { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
7220   { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
7221 };
7222 
7223 static const uint16_t ReplaceableInstrsAVX2[][3] = {
7224   //PackedSingle       PackedDouble       PackedInt
7225   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
7226   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
7227   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
7228   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
7229   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
7230   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
7231   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
7232   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
7233   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
7234   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
7235   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7236   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7237   { X86::VMOVDDUPrm,     X86::VMOVDDUPrm,     X86::VPBROADCASTQrm},
7238   { X86::VMOVDDUPrr,     X86::VMOVDDUPrr,     X86::VPBROADCASTQrr},
7239   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7240   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7241   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7242   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
7243   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
7244   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
7245   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
7246   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
7247   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
7248   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
7249   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
7250   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
7251   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
7252   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
7253   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
7254   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
7255   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
7256 };
7257 
7258 static const uint16_t ReplaceableInstrsFP[][3] = {
7259   //PackedSingle         PackedDouble
7260   { X86::MOVLPSrm,       X86::MOVLPDrm,      X86::INSTRUCTION_LIST_END },
7261   { X86::MOVHPSrm,       X86::MOVHPDrm,      X86::INSTRUCTION_LIST_END },
7262   { X86::MOVHPSmr,       X86::MOVHPDmr,      X86::INSTRUCTION_LIST_END },
7263   { X86::VMOVLPSrm,      X86::VMOVLPDrm,     X86::INSTRUCTION_LIST_END },
7264   { X86::VMOVHPSrm,      X86::VMOVHPDrm,     X86::INSTRUCTION_LIST_END },
7265   { X86::VMOVHPSmr,      X86::VMOVHPDmr,     X86::INSTRUCTION_LIST_END },
7266   { X86::VMOVLPSZ128rm,  X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
7267   { X86::VMOVHPSZ128rm,  X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
7268   { X86::VMOVHPSZ128mr,  X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
7269 };
7270 
7271 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
7272   //PackedSingle       PackedDouble       PackedInt
7273   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7274   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7275   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
7276   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
7277 };
7278 
7279 static const uint16_t ReplaceableInstrsAVX512[][4] = {
7280   // Two integer columns for 64-bit and 32-bit elements.
7281   //PackedSingle        PackedDouble        PackedInt             PackedInt
7282   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
7283   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
7284   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
7285   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
7286   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
7287   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
7288   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
7289   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
7290   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
7291   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
7292   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
7293   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
7294   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
7295   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
7296   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
7297 };
7298 
7299 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7300   // Two integer columns for 64-bit and 32-bit elements.
7301   //PackedSingle        PackedDouble        PackedInt           PackedInt
7302   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7303   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7304   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7305   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7306   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7307   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7308   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7309   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7310   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7311   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7312   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7313   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7314   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7315   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7316   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7317   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7318   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
7319   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
7320   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
7321   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
7322   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
7323   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
7324   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
7325   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
7326 };
7327 
7328 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
7329   // Two integer columns for 64-bit and 32-bit elements.
7330   //PackedSingle          PackedDouble
7331   //PackedInt             PackedInt
7332   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
7333     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
7334   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
7335     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
7336   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
7337     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
7338   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
7339     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
7340   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
7341     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
7342   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
7343     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
7344   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
7345     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
7346   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
7347     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
7348   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
7349     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
7350   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
7351     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
7352   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
7353     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
7354   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
7355     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
7356   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
7357     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
7358   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
7359     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
7360   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
7361     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
7362   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
7363     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
7364   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
7365     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
7366   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
7367     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
7368   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
7369     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
7370   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
7371     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
7372   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
7373     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
7374   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
7375     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
7376   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
7377     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
7378   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
7379     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
7380   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
7381     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
7382   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
7383     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
7384   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
7385     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
7386   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
7387     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
7388   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
7389     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
7390   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
7391     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
7392   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
7393     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
7394   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
7395     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
7396   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
7397     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
7398   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
7399     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
7400   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
7401     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
7402   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
7403     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
7404   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
7405     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
7406   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
7407     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
7408   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
7409     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
7410   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
7411     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
7412   { X86::VORPSZrmk,       X86::VORPDZrmk,
7413     X86::VPORQZrmk,       X86::VPORDZrmk       },
7414   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
7415     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
7416   { X86::VORPSZrrk,       X86::VORPDZrrk,
7417     X86::VPORQZrrk,       X86::VPORDZrrk       },
7418   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
7419     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
7420   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
7421     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
7422   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
7423     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
7424   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
7425     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
7426   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
7427     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
7428   // Broadcast loads can be handled the same as masked operations to avoid
7429   // changing element size.
7430   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
7431     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
7432   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
7433     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
7434   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
7435     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
7436   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
7437     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
7438   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
7439     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
7440   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
7441     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
7442   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
7443     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
7444   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
7445     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
7446   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
7447     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
7448   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7449     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7450   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7451     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7452   { X86::VORPSZrmb,       X86::VORPDZrmb,
7453     X86::VPORQZrmb,       X86::VPORDZrmb       },
7454   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
7455     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
7456   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
7457     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
7458   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
7459     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
7460   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
7461     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
7462   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
7463     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
7464   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
7465     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
7466   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
7467     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
7468   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
7469     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
7470   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
7471     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
7472   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
7473     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
7474   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7475     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7476   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7477     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7478   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
7479     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
7480   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
7481     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
7482   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
7483     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
7484   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
7485     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
7486   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
7487     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
7488   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
7489     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
7490   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
7491     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
7492   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
7493     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
7494   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
7495     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
7496   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
7497     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
7498   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
7499     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
7500   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7501     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7502   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7503     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7504   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
7505     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
7506   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
7507     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
7508 };
7509 
7510 // NOTE: These should only be used by the custom domain methods.
7511 static const uint16_t ReplaceableBlendInstrs[][3] = {
7512   //PackedSingle             PackedDouble             PackedInt
7513   { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
7514   { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
7515   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
7516   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
7517   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
7518   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
7519 };
7520 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
7521   //PackedSingle             PackedDouble             PackedInt
7522   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
7523   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
7524   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
7525   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
7526 };
7527 
7528 // Special table for changing EVEX logic instructions to VEX.
7529 // TODO: Should we run EVEX->VEX earlier?
7530 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
7531   // Two integer columns for 64-bit and 32-bit elements.
7532   //PackedSingle     PackedDouble     PackedInt           PackedInt
7533   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7534   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7535   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7536   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7537   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7538   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7539   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7540   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7541   { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7542   { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7543   { X86::VANDPSYrm,  X86::VANDPDYrm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7544   { X86::VANDPSYrr,  X86::VANDPDYrr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7545   { X86::VORPSYrm,   X86::VORPDYrm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7546   { X86::VORPSYrr,   X86::VORPDYrr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7547   { X86::VXORPSYrm,  X86::VXORPDYrm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7548   { X86::VXORPSYrr,  X86::VXORPDYrr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7549 };
7550 
7551 // FIXME: Some shuffle and unpack instructions have equivalents in different
7552 // domains, but they require a bit more work than just switching opcodes.
7553 
7554 static const uint16_t *lookup(unsigned opcode, unsigned domain,
7555                               ArrayRef<uint16_t[3]> Table) {
7556   for (const uint16_t (&Row)[3] : Table)
7557     if (Row[domain-1] == opcode)
7558       return Row;
7559   return nullptr;
7560 }
7561 
7562 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
7563                                     ArrayRef<uint16_t[4]> Table) {
7564   // If this is the integer domain make sure to check both integer columns.
7565   for (const uint16_t (&Row)[4] : Table)
7566     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7567       return Row;
7568   return nullptr;
7569 }
7570 
7571 // Helper to attempt to widen/narrow blend masks.
7572 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
7573                             unsigned NewWidth, unsigned *pNewMask = nullptr) {
7574   assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
7575          "Illegal blend mask scale");
7576   unsigned NewMask = 0;
7577 
7578   if ((OldWidth % NewWidth) == 0) {
7579     unsigned Scale = OldWidth / NewWidth;
7580     unsigned SubMask = (1u << Scale) - 1;
7581     for (unsigned i = 0; i != NewWidth; ++i) {
7582       unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
7583       if (Sub == SubMask)
7584         NewMask |= (1u << i);
7585       else if (Sub != 0x0)
7586         return false;
7587     }
7588   } else {
7589     unsigned Scale = NewWidth / OldWidth;
7590     unsigned SubMask = (1u << Scale) - 1;
7591     for (unsigned i = 0; i != OldWidth; ++i) {
7592       if (OldMask & (1 << i)) {
7593         NewMask |= (SubMask << (i * Scale));
7594       }
7595     }
7596   }
7597 
7598   if (pNewMask)
7599     *pNewMask = NewMask;
7600   return true;
7601 }
7602 
7603 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
7604   unsigned Opcode = MI.getOpcode();
7605   unsigned NumOperands = MI.getDesc().getNumOperands();
7606 
7607   auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
7608     uint16_t validDomains = 0;
7609     if (MI.getOperand(NumOperands - 1).isImm()) {
7610       unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
7611       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
7612         validDomains |= 0x2; // PackedSingle
7613       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
7614         validDomains |= 0x4; // PackedDouble
7615       if (!Is256 || Subtarget.hasAVX2())
7616         validDomains |= 0x8; // PackedInt
7617     }
7618     return validDomains;
7619   };
7620 
7621   switch (Opcode) {
7622   case X86::BLENDPDrmi:
7623   case X86::BLENDPDrri:
7624   case X86::VBLENDPDrmi:
7625   case X86::VBLENDPDrri:
7626     return GetBlendDomains(2, false);
7627   case X86::VBLENDPDYrmi:
7628   case X86::VBLENDPDYrri:
7629     return GetBlendDomains(4, true);
7630   case X86::BLENDPSrmi:
7631   case X86::BLENDPSrri:
7632   case X86::VBLENDPSrmi:
7633   case X86::VBLENDPSrri:
7634   case X86::VPBLENDDrmi:
7635   case X86::VPBLENDDrri:
7636     return GetBlendDomains(4, false);
7637   case X86::VBLENDPSYrmi:
7638   case X86::VBLENDPSYrri:
7639   case X86::VPBLENDDYrmi:
7640   case X86::VPBLENDDYrri:
7641     return GetBlendDomains(8, true);
7642   case X86::PBLENDWrmi:
7643   case X86::PBLENDWrri:
7644   case X86::VPBLENDWrmi:
7645   case X86::VPBLENDWrri:
7646   // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
7647   case X86::VPBLENDWYrmi:
7648   case X86::VPBLENDWYrri:
7649     return GetBlendDomains(8, false);
7650   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7651   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7652   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7653   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7654   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7655   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7656   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7657   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7658   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7659   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7660   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7661   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7662   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7663   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7664   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7665   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm:
7666     // If we don't have DQI see if we can still switch from an EVEX integer
7667     // instruction to a VEX floating point instruction.
7668     if (Subtarget.hasDQI())
7669       return 0;
7670 
7671     if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
7672       return 0;
7673     if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
7674       return 0;
7675     // Register forms will have 3 operands. Memory form will have more.
7676     if (NumOperands == 3 &&
7677         RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
7678       return 0;
7679 
7680     // All domains are valid.
7681     return 0xe;
7682   case X86::MOVHLPSrr:
7683     // We can swap domains when both inputs are the same register.
7684     // FIXME: This doesn't catch all the cases we would like. If the input
7685     // register isn't KILLed by the instruction, the two address instruction
7686     // pass puts a COPY on one input. The other input uses the original
7687     // register. This prevents the same physical register from being used by
7688     // both inputs.
7689     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7690         MI.getOperand(0).getSubReg() == 0 &&
7691         MI.getOperand(1).getSubReg() == 0 &&
7692         MI.getOperand(2).getSubReg() == 0)
7693       return 0x6;
7694     return 0;
7695   case X86::SHUFPDrri:
7696     return 0x6;
7697   }
7698   return 0;
7699 }
7700 
7701 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
7702                                             unsigned Domain) const {
7703   assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
7704   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7705   assert(dom && "Not an SSE instruction");
7706 
7707   unsigned Opcode = MI.getOpcode();
7708   unsigned NumOperands = MI.getDesc().getNumOperands();
7709 
7710   auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
7711     if (MI.getOperand(NumOperands - 1).isImm()) {
7712       unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
7713       Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
7714       unsigned NewImm = Imm;
7715 
7716       const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
7717       if (!table)
7718         table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7719 
7720       if (Domain == 1) { // PackedSingle
7721         AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7722       } else if (Domain == 2) { // PackedDouble
7723         AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
7724       } else if (Domain == 3) { // PackedInt
7725         if (Subtarget.hasAVX2()) {
7726           // If we are already VPBLENDW use that, else use VPBLENDD.
7727           if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
7728             table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7729             AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7730           }
7731         } else {
7732           assert(!Is256 && "128-bit vector expected");
7733           AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
7734         }
7735       }
7736 
7737       assert(table && table[Domain - 1] && "Unknown domain op");
7738       MI.setDesc(get(table[Domain - 1]));
7739       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
7740     }
7741     return true;
7742   };
7743 
7744   switch (Opcode) {
7745   case X86::BLENDPDrmi:
7746   case X86::BLENDPDrri:
7747   case X86::VBLENDPDrmi:
7748   case X86::VBLENDPDrri:
7749     return SetBlendDomain(2, false);
7750   case X86::VBLENDPDYrmi:
7751   case X86::VBLENDPDYrri:
7752     return SetBlendDomain(4, true);
7753   case X86::BLENDPSrmi:
7754   case X86::BLENDPSrri:
7755   case X86::VBLENDPSrmi:
7756   case X86::VBLENDPSrri:
7757   case X86::VPBLENDDrmi:
7758   case X86::VPBLENDDrri:
7759     return SetBlendDomain(4, false);
7760   case X86::VBLENDPSYrmi:
7761   case X86::VBLENDPSYrri:
7762   case X86::VPBLENDDYrmi:
7763   case X86::VPBLENDDYrri:
7764     return SetBlendDomain(8, true);
7765   case X86::PBLENDWrmi:
7766   case X86::PBLENDWrri:
7767   case X86::VPBLENDWrmi:
7768   case X86::VPBLENDWrri:
7769     return SetBlendDomain(8, false);
7770   case X86::VPBLENDWYrmi:
7771   case X86::VPBLENDWYrri:
7772     return SetBlendDomain(16, true);
7773   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7774   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7775   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7776   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7777   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7778   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7779   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7780   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7781   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7782   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7783   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7784   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7785   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7786   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7787   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7788   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm: {
7789     // Without DQI, convert EVEX instructions to VEX instructions.
7790     if (Subtarget.hasDQI())
7791       return false;
7792 
7793     const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
7794                                          ReplaceableCustomAVX512LogicInstrs);
7795     assert(table && "Instruction not found in table?");
7796     // Don't change integer Q instructions to D instructions and
7797     // use D intructions if we started with a PS instruction.
7798     if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7799       Domain = 4;
7800     MI.setDesc(get(table[Domain - 1]));
7801     return true;
7802   }
7803   case X86::UNPCKHPDrr:
7804   case X86::MOVHLPSrr:
7805     // We just need to commute the instruction which will switch the domains.
7806     if (Domain != dom && Domain != 3 &&
7807         MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7808         MI.getOperand(0).getSubReg() == 0 &&
7809         MI.getOperand(1).getSubReg() == 0 &&
7810         MI.getOperand(2).getSubReg() == 0) {
7811       commuteInstruction(MI, false);
7812       return true;
7813     }
7814     // We must always return true for MOVHLPSrr.
7815     if (Opcode == X86::MOVHLPSrr)
7816       return true;
7817     break;
7818   case X86::SHUFPDrri: {
7819     if (Domain == 1) {
7820       unsigned Imm = MI.getOperand(3).getImm();
7821       unsigned NewImm = 0x44;
7822       if (Imm & 1) NewImm |= 0x0a;
7823       if (Imm & 2) NewImm |= 0xa0;
7824       MI.getOperand(3).setImm(NewImm);
7825       MI.setDesc(get(X86::SHUFPSrri));
7826     }
7827     return true;
7828   }
7829   }
7830   return false;
7831 }
7832 
7833 std::pair<uint16_t, uint16_t>
7834 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7835   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7836   unsigned opcode = MI.getOpcode();
7837   uint16_t validDomains = 0;
7838   if (domain) {
7839     // Attempt to match for custom instructions.
7840     validDomains = getExecutionDomainCustom(MI);
7841     if (validDomains)
7842       return std::make_pair(domain, validDomains);
7843 
7844     if (lookup(opcode, domain, ReplaceableInstrs)) {
7845       validDomains = 0xe;
7846     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
7847       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
7848     } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
7849       validDomains = 0x6;
7850     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
7851       // Insert/extract instructions should only effect domain if AVX2
7852       // is enabled.
7853       if (!Subtarget.hasAVX2())
7854         return std::make_pair(0, 0);
7855       validDomains = 0xe;
7856     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
7857       validDomains = 0xe;
7858     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
7859                                                   ReplaceableInstrsAVX512DQ)) {
7860       validDomains = 0xe;
7861     } else if (Subtarget.hasDQI()) {
7862       if (const uint16_t *table = lookupAVX512(opcode, domain,
7863                                              ReplaceableInstrsAVX512DQMasked)) {
7864         if (domain == 1 || (domain == 3 && table[3] == opcode))
7865           validDomains = 0xa;
7866         else
7867           validDomains = 0xc;
7868       }
7869     }
7870   }
7871   return std::make_pair(domain, validDomains);
7872 }
7873 
7874 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
7875   assert(Domain>0 && Domain<4 && "Invalid execution domain");
7876   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7877   assert(dom && "Not an SSE instruction");
7878 
7879   // Attempt to match for custom instructions.
7880   if (setExecutionDomainCustom(MI, Domain))
7881     return;
7882 
7883   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
7884   if (!table) { // try the other table
7885     assert((Subtarget.hasAVX2() || Domain < 3) &&
7886            "256-bit vector operations only available in AVX2");
7887     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
7888   }
7889   if (!table) { // try the FP table
7890     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
7891     assert((!table || Domain < 3) &&
7892            "Can only select PackedSingle or PackedDouble");
7893   }
7894   if (!table) { // try the other table
7895     assert(Subtarget.hasAVX2() &&
7896            "256-bit insert/extract only available in AVX2");
7897     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
7898   }
7899   if (!table) { // try the AVX512 table
7900     assert(Subtarget.hasAVX512() && "Requires AVX-512");
7901     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
7902     // Don't change integer Q instructions to D instructions.
7903     if (table && Domain == 3 && table[3] == MI.getOpcode())
7904       Domain = 4;
7905   }
7906   if (!table) { // try the AVX512DQ table
7907     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7908     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
7909     // Don't change integer Q instructions to D instructions and
7910     // use D instructions if we started with a PS instruction.
7911     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7912       Domain = 4;
7913   }
7914   if (!table) { // try the AVX512DQMasked table
7915     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7916     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
7917     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7918       Domain = 4;
7919   }
7920   assert(table && "Cannot change domain");
7921   MI.setDesc(get(table[Domain - 1]));
7922 }
7923 
7924 /// Return the noop instruction to use for a noop.
7925 MCInst X86InstrInfo::getNop() const {
7926   MCInst Nop;
7927   Nop.setOpcode(X86::NOOP);
7928   return Nop;
7929 }
7930 
7931 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7932   switch (opc) {
7933   default: return false;
7934   case X86::DIVPDrm:
7935   case X86::DIVPDrr:
7936   case X86::DIVPSrm:
7937   case X86::DIVPSrr:
7938   case X86::DIVSDrm:
7939   case X86::DIVSDrm_Int:
7940   case X86::DIVSDrr:
7941   case X86::DIVSDrr_Int:
7942   case X86::DIVSSrm:
7943   case X86::DIVSSrm_Int:
7944   case X86::DIVSSrr:
7945   case X86::DIVSSrr_Int:
7946   case X86::SQRTPDm:
7947   case X86::SQRTPDr:
7948   case X86::SQRTPSm:
7949   case X86::SQRTPSr:
7950   case X86::SQRTSDm:
7951   case X86::SQRTSDm_Int:
7952   case X86::SQRTSDr:
7953   case X86::SQRTSDr_Int:
7954   case X86::SQRTSSm:
7955   case X86::SQRTSSm_Int:
7956   case X86::SQRTSSr:
7957   case X86::SQRTSSr_Int:
7958   // AVX instructions with high latency
7959   case X86::VDIVPDrm:
7960   case X86::VDIVPDrr:
7961   case X86::VDIVPDYrm:
7962   case X86::VDIVPDYrr:
7963   case X86::VDIVPSrm:
7964   case X86::VDIVPSrr:
7965   case X86::VDIVPSYrm:
7966   case X86::VDIVPSYrr:
7967   case X86::VDIVSDrm:
7968   case X86::VDIVSDrm_Int:
7969   case X86::VDIVSDrr:
7970   case X86::VDIVSDrr_Int:
7971   case X86::VDIVSSrm:
7972   case X86::VDIVSSrm_Int:
7973   case X86::VDIVSSrr:
7974   case X86::VDIVSSrr_Int:
7975   case X86::VSQRTPDm:
7976   case X86::VSQRTPDr:
7977   case X86::VSQRTPDYm:
7978   case X86::VSQRTPDYr:
7979   case X86::VSQRTPSm:
7980   case X86::VSQRTPSr:
7981   case X86::VSQRTPSYm:
7982   case X86::VSQRTPSYr:
7983   case X86::VSQRTSDm:
7984   case X86::VSQRTSDm_Int:
7985   case X86::VSQRTSDr:
7986   case X86::VSQRTSDr_Int:
7987   case X86::VSQRTSSm:
7988   case X86::VSQRTSSm_Int:
7989   case X86::VSQRTSSr:
7990   case X86::VSQRTSSr_Int:
7991   // AVX512 instructions with high latency
7992   case X86::VDIVPDZ128rm:
7993   case X86::VDIVPDZ128rmb:
7994   case X86::VDIVPDZ128rmbk:
7995   case X86::VDIVPDZ128rmbkz:
7996   case X86::VDIVPDZ128rmk:
7997   case X86::VDIVPDZ128rmkz:
7998   case X86::VDIVPDZ128rr:
7999   case X86::VDIVPDZ128rrk:
8000   case X86::VDIVPDZ128rrkz:
8001   case X86::VDIVPDZ256rm:
8002   case X86::VDIVPDZ256rmb:
8003   case X86::VDIVPDZ256rmbk:
8004   case X86::VDIVPDZ256rmbkz:
8005   case X86::VDIVPDZ256rmk:
8006   case X86::VDIVPDZ256rmkz:
8007   case X86::VDIVPDZ256rr:
8008   case X86::VDIVPDZ256rrk:
8009   case X86::VDIVPDZ256rrkz:
8010   case X86::VDIVPDZrrb:
8011   case X86::VDIVPDZrrbk:
8012   case X86::VDIVPDZrrbkz:
8013   case X86::VDIVPDZrm:
8014   case X86::VDIVPDZrmb:
8015   case X86::VDIVPDZrmbk:
8016   case X86::VDIVPDZrmbkz:
8017   case X86::VDIVPDZrmk:
8018   case X86::VDIVPDZrmkz:
8019   case X86::VDIVPDZrr:
8020   case X86::VDIVPDZrrk:
8021   case X86::VDIVPDZrrkz:
8022   case X86::VDIVPSZ128rm:
8023   case X86::VDIVPSZ128rmb:
8024   case X86::VDIVPSZ128rmbk:
8025   case X86::VDIVPSZ128rmbkz:
8026   case X86::VDIVPSZ128rmk:
8027   case X86::VDIVPSZ128rmkz:
8028   case X86::VDIVPSZ128rr:
8029   case X86::VDIVPSZ128rrk:
8030   case X86::VDIVPSZ128rrkz:
8031   case X86::VDIVPSZ256rm:
8032   case X86::VDIVPSZ256rmb:
8033   case X86::VDIVPSZ256rmbk:
8034   case X86::VDIVPSZ256rmbkz:
8035   case X86::VDIVPSZ256rmk:
8036   case X86::VDIVPSZ256rmkz:
8037   case X86::VDIVPSZ256rr:
8038   case X86::VDIVPSZ256rrk:
8039   case X86::VDIVPSZ256rrkz:
8040   case X86::VDIVPSZrrb:
8041   case X86::VDIVPSZrrbk:
8042   case X86::VDIVPSZrrbkz:
8043   case X86::VDIVPSZrm:
8044   case X86::VDIVPSZrmb:
8045   case X86::VDIVPSZrmbk:
8046   case X86::VDIVPSZrmbkz:
8047   case X86::VDIVPSZrmk:
8048   case X86::VDIVPSZrmkz:
8049   case X86::VDIVPSZrr:
8050   case X86::VDIVPSZrrk:
8051   case X86::VDIVPSZrrkz:
8052   case X86::VDIVSDZrm:
8053   case X86::VDIVSDZrr:
8054   case X86::VDIVSDZrm_Int:
8055   case X86::VDIVSDZrm_Intk:
8056   case X86::VDIVSDZrm_Intkz:
8057   case X86::VDIVSDZrr_Int:
8058   case X86::VDIVSDZrr_Intk:
8059   case X86::VDIVSDZrr_Intkz:
8060   case X86::VDIVSDZrrb_Int:
8061   case X86::VDIVSDZrrb_Intk:
8062   case X86::VDIVSDZrrb_Intkz:
8063   case X86::VDIVSSZrm:
8064   case X86::VDIVSSZrr:
8065   case X86::VDIVSSZrm_Int:
8066   case X86::VDIVSSZrm_Intk:
8067   case X86::VDIVSSZrm_Intkz:
8068   case X86::VDIVSSZrr_Int:
8069   case X86::VDIVSSZrr_Intk:
8070   case X86::VDIVSSZrr_Intkz:
8071   case X86::VDIVSSZrrb_Int:
8072   case X86::VDIVSSZrrb_Intk:
8073   case X86::VDIVSSZrrb_Intkz:
8074   case X86::VSQRTPDZ128m:
8075   case X86::VSQRTPDZ128mb:
8076   case X86::VSQRTPDZ128mbk:
8077   case X86::VSQRTPDZ128mbkz:
8078   case X86::VSQRTPDZ128mk:
8079   case X86::VSQRTPDZ128mkz:
8080   case X86::VSQRTPDZ128r:
8081   case X86::VSQRTPDZ128rk:
8082   case X86::VSQRTPDZ128rkz:
8083   case X86::VSQRTPDZ256m:
8084   case X86::VSQRTPDZ256mb:
8085   case X86::VSQRTPDZ256mbk:
8086   case X86::VSQRTPDZ256mbkz:
8087   case X86::VSQRTPDZ256mk:
8088   case X86::VSQRTPDZ256mkz:
8089   case X86::VSQRTPDZ256r:
8090   case X86::VSQRTPDZ256rk:
8091   case X86::VSQRTPDZ256rkz:
8092   case X86::VSQRTPDZm:
8093   case X86::VSQRTPDZmb:
8094   case X86::VSQRTPDZmbk:
8095   case X86::VSQRTPDZmbkz:
8096   case X86::VSQRTPDZmk:
8097   case X86::VSQRTPDZmkz:
8098   case X86::VSQRTPDZr:
8099   case X86::VSQRTPDZrb:
8100   case X86::VSQRTPDZrbk:
8101   case X86::VSQRTPDZrbkz:
8102   case X86::VSQRTPDZrk:
8103   case X86::VSQRTPDZrkz:
8104   case X86::VSQRTPSZ128m:
8105   case X86::VSQRTPSZ128mb:
8106   case X86::VSQRTPSZ128mbk:
8107   case X86::VSQRTPSZ128mbkz:
8108   case X86::VSQRTPSZ128mk:
8109   case X86::VSQRTPSZ128mkz:
8110   case X86::VSQRTPSZ128r:
8111   case X86::VSQRTPSZ128rk:
8112   case X86::VSQRTPSZ128rkz:
8113   case X86::VSQRTPSZ256m:
8114   case X86::VSQRTPSZ256mb:
8115   case X86::VSQRTPSZ256mbk:
8116   case X86::VSQRTPSZ256mbkz:
8117   case X86::VSQRTPSZ256mk:
8118   case X86::VSQRTPSZ256mkz:
8119   case X86::VSQRTPSZ256r:
8120   case X86::VSQRTPSZ256rk:
8121   case X86::VSQRTPSZ256rkz:
8122   case X86::VSQRTPSZm:
8123   case X86::VSQRTPSZmb:
8124   case X86::VSQRTPSZmbk:
8125   case X86::VSQRTPSZmbkz:
8126   case X86::VSQRTPSZmk:
8127   case X86::VSQRTPSZmkz:
8128   case X86::VSQRTPSZr:
8129   case X86::VSQRTPSZrb:
8130   case X86::VSQRTPSZrbk:
8131   case X86::VSQRTPSZrbkz:
8132   case X86::VSQRTPSZrk:
8133   case X86::VSQRTPSZrkz:
8134   case X86::VSQRTSDZm:
8135   case X86::VSQRTSDZm_Int:
8136   case X86::VSQRTSDZm_Intk:
8137   case X86::VSQRTSDZm_Intkz:
8138   case X86::VSQRTSDZr:
8139   case X86::VSQRTSDZr_Int:
8140   case X86::VSQRTSDZr_Intk:
8141   case X86::VSQRTSDZr_Intkz:
8142   case X86::VSQRTSDZrb_Int:
8143   case X86::VSQRTSDZrb_Intk:
8144   case X86::VSQRTSDZrb_Intkz:
8145   case X86::VSQRTSSZm:
8146   case X86::VSQRTSSZm_Int:
8147   case X86::VSQRTSSZm_Intk:
8148   case X86::VSQRTSSZm_Intkz:
8149   case X86::VSQRTSSZr:
8150   case X86::VSQRTSSZr_Int:
8151   case X86::VSQRTSSZr_Intk:
8152   case X86::VSQRTSSZr_Intkz:
8153   case X86::VSQRTSSZrb_Int:
8154   case X86::VSQRTSSZrb_Intk:
8155   case X86::VSQRTSSZrb_Intkz:
8156 
8157   case X86::VGATHERDPDYrm:
8158   case X86::VGATHERDPDZ128rm:
8159   case X86::VGATHERDPDZ256rm:
8160   case X86::VGATHERDPDZrm:
8161   case X86::VGATHERDPDrm:
8162   case X86::VGATHERDPSYrm:
8163   case X86::VGATHERDPSZ128rm:
8164   case X86::VGATHERDPSZ256rm:
8165   case X86::VGATHERDPSZrm:
8166   case X86::VGATHERDPSrm:
8167   case X86::VGATHERPF0DPDm:
8168   case X86::VGATHERPF0DPSm:
8169   case X86::VGATHERPF0QPDm:
8170   case X86::VGATHERPF0QPSm:
8171   case X86::VGATHERPF1DPDm:
8172   case X86::VGATHERPF1DPSm:
8173   case X86::VGATHERPF1QPDm:
8174   case X86::VGATHERPF1QPSm:
8175   case X86::VGATHERQPDYrm:
8176   case X86::VGATHERQPDZ128rm:
8177   case X86::VGATHERQPDZ256rm:
8178   case X86::VGATHERQPDZrm:
8179   case X86::VGATHERQPDrm:
8180   case X86::VGATHERQPSYrm:
8181   case X86::VGATHERQPSZ128rm:
8182   case X86::VGATHERQPSZ256rm:
8183   case X86::VGATHERQPSZrm:
8184   case X86::VGATHERQPSrm:
8185   case X86::VPGATHERDDYrm:
8186   case X86::VPGATHERDDZ128rm:
8187   case X86::VPGATHERDDZ256rm:
8188   case X86::VPGATHERDDZrm:
8189   case X86::VPGATHERDDrm:
8190   case X86::VPGATHERDQYrm:
8191   case X86::VPGATHERDQZ128rm:
8192   case X86::VPGATHERDQZ256rm:
8193   case X86::VPGATHERDQZrm:
8194   case X86::VPGATHERDQrm:
8195   case X86::VPGATHERQDYrm:
8196   case X86::VPGATHERQDZ128rm:
8197   case X86::VPGATHERQDZ256rm:
8198   case X86::VPGATHERQDZrm:
8199   case X86::VPGATHERQDrm:
8200   case X86::VPGATHERQQYrm:
8201   case X86::VPGATHERQQZ128rm:
8202   case X86::VPGATHERQQZ256rm:
8203   case X86::VPGATHERQQZrm:
8204   case X86::VPGATHERQQrm:
8205   case X86::VSCATTERDPDZ128mr:
8206   case X86::VSCATTERDPDZ256mr:
8207   case X86::VSCATTERDPDZmr:
8208   case X86::VSCATTERDPSZ128mr:
8209   case X86::VSCATTERDPSZ256mr:
8210   case X86::VSCATTERDPSZmr:
8211   case X86::VSCATTERPF0DPDm:
8212   case X86::VSCATTERPF0DPSm:
8213   case X86::VSCATTERPF0QPDm:
8214   case X86::VSCATTERPF0QPSm:
8215   case X86::VSCATTERPF1DPDm:
8216   case X86::VSCATTERPF1DPSm:
8217   case X86::VSCATTERPF1QPDm:
8218   case X86::VSCATTERPF1QPSm:
8219   case X86::VSCATTERQPDZ128mr:
8220   case X86::VSCATTERQPDZ256mr:
8221   case X86::VSCATTERQPDZmr:
8222   case X86::VSCATTERQPSZ128mr:
8223   case X86::VSCATTERQPSZ256mr:
8224   case X86::VSCATTERQPSZmr:
8225   case X86::VPSCATTERDDZ128mr:
8226   case X86::VPSCATTERDDZ256mr:
8227   case X86::VPSCATTERDDZmr:
8228   case X86::VPSCATTERDQZ128mr:
8229   case X86::VPSCATTERDQZ256mr:
8230   case X86::VPSCATTERDQZmr:
8231   case X86::VPSCATTERQDZ128mr:
8232   case X86::VPSCATTERQDZ256mr:
8233   case X86::VPSCATTERQDZmr:
8234   case X86::VPSCATTERQQZ128mr:
8235   case X86::VPSCATTERQQZ256mr:
8236   case X86::VPSCATTERQQZmr:
8237     return true;
8238   }
8239 }
8240 
8241 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
8242                                          const MachineRegisterInfo *MRI,
8243                                          const MachineInstr &DefMI,
8244                                          unsigned DefIdx,
8245                                          const MachineInstr &UseMI,
8246                                          unsigned UseIdx) const {
8247   return isHighLatencyDef(DefMI.getOpcode());
8248 }
8249 
8250 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
8251                                            const MachineBasicBlock *MBB) const {
8252   assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
8253          Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
8254 
8255   // Integer binary math/logic instructions have a third source operand:
8256   // the EFLAGS register. That operand must be both defined here and never
8257   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
8258   // not change anything because rearranging the operands could affect other
8259   // instructions that depend on the exact status flags (zero, sign, etc.)
8260   // that are set by using these particular operands with this operation.
8261   const MachineOperand *FlagDef = Inst.findRegisterDefOperand(X86::EFLAGS);
8262   assert((Inst.getNumDefs() == 1 || FlagDef) &&
8263          "Implicit def isn't flags?");
8264   if (FlagDef && !FlagDef->isDead())
8265     return false;
8266 
8267   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
8268 }
8269 
8270 // TODO: There are many more machine instruction opcodes to match:
8271 //       1. Other data types (integer, vectors)
8272 //       2. Other math / logic operations (xor, or)
8273 //       3. Other forms of the same operation (intrinsics and other variants)
8274 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
8275   switch (Inst.getOpcode()) {
8276   case X86::AND8rr:
8277   case X86::AND16rr:
8278   case X86::AND32rr:
8279   case X86::AND64rr:
8280   case X86::OR8rr:
8281   case X86::OR16rr:
8282   case X86::OR32rr:
8283   case X86::OR64rr:
8284   case X86::XOR8rr:
8285   case X86::XOR16rr:
8286   case X86::XOR32rr:
8287   case X86::XOR64rr:
8288   case X86::IMUL16rr:
8289   case X86::IMUL32rr:
8290   case X86::IMUL64rr:
8291   case X86::PANDrr:
8292   case X86::PORrr:
8293   case X86::PXORrr:
8294   case X86::ANDPDrr:
8295   case X86::ANDPSrr:
8296   case X86::ORPDrr:
8297   case X86::ORPSrr:
8298   case X86::XORPDrr:
8299   case X86::XORPSrr:
8300   case X86::PADDBrr:
8301   case X86::PADDWrr:
8302   case X86::PADDDrr:
8303   case X86::PADDQrr:
8304   case X86::PMULLWrr:
8305   case X86::PMULLDrr:
8306   case X86::PMAXSBrr:
8307   case X86::PMAXSDrr:
8308   case X86::PMAXSWrr:
8309   case X86::PMAXUBrr:
8310   case X86::PMAXUDrr:
8311   case X86::PMAXUWrr:
8312   case X86::PMINSBrr:
8313   case X86::PMINSDrr:
8314   case X86::PMINSWrr:
8315   case X86::PMINUBrr:
8316   case X86::PMINUDrr:
8317   case X86::PMINUWrr:
8318   case X86::VPANDrr:
8319   case X86::VPANDYrr:
8320   case X86::VPANDDZ128rr:
8321   case X86::VPANDDZ256rr:
8322   case X86::VPANDDZrr:
8323   case X86::VPANDQZ128rr:
8324   case X86::VPANDQZ256rr:
8325   case X86::VPANDQZrr:
8326   case X86::VPORrr:
8327   case X86::VPORYrr:
8328   case X86::VPORDZ128rr:
8329   case X86::VPORDZ256rr:
8330   case X86::VPORDZrr:
8331   case X86::VPORQZ128rr:
8332   case X86::VPORQZ256rr:
8333   case X86::VPORQZrr:
8334   case X86::VPXORrr:
8335   case X86::VPXORYrr:
8336   case X86::VPXORDZ128rr:
8337   case X86::VPXORDZ256rr:
8338   case X86::VPXORDZrr:
8339   case X86::VPXORQZ128rr:
8340   case X86::VPXORQZ256rr:
8341   case X86::VPXORQZrr:
8342   case X86::VANDPDrr:
8343   case X86::VANDPSrr:
8344   case X86::VANDPDYrr:
8345   case X86::VANDPSYrr:
8346   case X86::VANDPDZ128rr:
8347   case X86::VANDPSZ128rr:
8348   case X86::VANDPDZ256rr:
8349   case X86::VANDPSZ256rr:
8350   case X86::VANDPDZrr:
8351   case X86::VANDPSZrr:
8352   case X86::VORPDrr:
8353   case X86::VORPSrr:
8354   case X86::VORPDYrr:
8355   case X86::VORPSYrr:
8356   case X86::VORPDZ128rr:
8357   case X86::VORPSZ128rr:
8358   case X86::VORPDZ256rr:
8359   case X86::VORPSZ256rr:
8360   case X86::VORPDZrr:
8361   case X86::VORPSZrr:
8362   case X86::VXORPDrr:
8363   case X86::VXORPSrr:
8364   case X86::VXORPDYrr:
8365   case X86::VXORPSYrr:
8366   case X86::VXORPDZ128rr:
8367   case X86::VXORPSZ128rr:
8368   case X86::VXORPDZ256rr:
8369   case X86::VXORPSZ256rr:
8370   case X86::VXORPDZrr:
8371   case X86::VXORPSZrr:
8372   case X86::KADDBrr:
8373   case X86::KADDWrr:
8374   case X86::KADDDrr:
8375   case X86::KADDQrr:
8376   case X86::KANDBrr:
8377   case X86::KANDWrr:
8378   case X86::KANDDrr:
8379   case X86::KANDQrr:
8380   case X86::KORBrr:
8381   case X86::KORWrr:
8382   case X86::KORDrr:
8383   case X86::KORQrr:
8384   case X86::KXORBrr:
8385   case X86::KXORWrr:
8386   case X86::KXORDrr:
8387   case X86::KXORQrr:
8388   case X86::VPADDBrr:
8389   case X86::VPADDWrr:
8390   case X86::VPADDDrr:
8391   case X86::VPADDQrr:
8392   case X86::VPADDBYrr:
8393   case X86::VPADDWYrr:
8394   case X86::VPADDDYrr:
8395   case X86::VPADDQYrr:
8396   case X86::VPADDBZ128rr:
8397   case X86::VPADDWZ128rr:
8398   case X86::VPADDDZ128rr:
8399   case X86::VPADDQZ128rr:
8400   case X86::VPADDBZ256rr:
8401   case X86::VPADDWZ256rr:
8402   case X86::VPADDDZ256rr:
8403   case X86::VPADDQZ256rr:
8404   case X86::VPADDBZrr:
8405   case X86::VPADDWZrr:
8406   case X86::VPADDDZrr:
8407   case X86::VPADDQZrr:
8408   case X86::VPMULLWrr:
8409   case X86::VPMULLWYrr:
8410   case X86::VPMULLWZ128rr:
8411   case X86::VPMULLWZ256rr:
8412   case X86::VPMULLWZrr:
8413   case X86::VPMULLDrr:
8414   case X86::VPMULLDYrr:
8415   case X86::VPMULLDZ128rr:
8416   case X86::VPMULLDZ256rr:
8417   case X86::VPMULLDZrr:
8418   case X86::VPMULLQZ128rr:
8419   case X86::VPMULLQZ256rr:
8420   case X86::VPMULLQZrr:
8421   case X86::VPMAXSBrr:
8422   case X86::VPMAXSBYrr:
8423   case X86::VPMAXSBZ128rr:
8424   case X86::VPMAXSBZ256rr:
8425   case X86::VPMAXSBZrr:
8426   case X86::VPMAXSDrr:
8427   case X86::VPMAXSDYrr:
8428   case X86::VPMAXSDZ128rr:
8429   case X86::VPMAXSDZ256rr:
8430   case X86::VPMAXSDZrr:
8431   case X86::VPMAXSQZ128rr:
8432   case X86::VPMAXSQZ256rr:
8433   case X86::VPMAXSQZrr:
8434   case X86::VPMAXSWrr:
8435   case X86::VPMAXSWYrr:
8436   case X86::VPMAXSWZ128rr:
8437   case X86::VPMAXSWZ256rr:
8438   case X86::VPMAXSWZrr:
8439   case X86::VPMAXUBrr:
8440   case X86::VPMAXUBYrr:
8441   case X86::VPMAXUBZ128rr:
8442   case X86::VPMAXUBZ256rr:
8443   case X86::VPMAXUBZrr:
8444   case X86::VPMAXUDrr:
8445   case X86::VPMAXUDYrr:
8446   case X86::VPMAXUDZ128rr:
8447   case X86::VPMAXUDZ256rr:
8448   case X86::VPMAXUDZrr:
8449   case X86::VPMAXUQZ128rr:
8450   case X86::VPMAXUQZ256rr:
8451   case X86::VPMAXUQZrr:
8452   case X86::VPMAXUWrr:
8453   case X86::VPMAXUWYrr:
8454   case X86::VPMAXUWZ128rr:
8455   case X86::VPMAXUWZ256rr:
8456   case X86::VPMAXUWZrr:
8457   case X86::VPMINSBrr:
8458   case X86::VPMINSBYrr:
8459   case X86::VPMINSBZ128rr:
8460   case X86::VPMINSBZ256rr:
8461   case X86::VPMINSBZrr:
8462   case X86::VPMINSDrr:
8463   case X86::VPMINSDYrr:
8464   case X86::VPMINSDZ128rr:
8465   case X86::VPMINSDZ256rr:
8466   case X86::VPMINSDZrr:
8467   case X86::VPMINSQZ128rr:
8468   case X86::VPMINSQZ256rr:
8469   case X86::VPMINSQZrr:
8470   case X86::VPMINSWrr:
8471   case X86::VPMINSWYrr:
8472   case X86::VPMINSWZ128rr:
8473   case X86::VPMINSWZ256rr:
8474   case X86::VPMINSWZrr:
8475   case X86::VPMINUBrr:
8476   case X86::VPMINUBYrr:
8477   case X86::VPMINUBZ128rr:
8478   case X86::VPMINUBZ256rr:
8479   case X86::VPMINUBZrr:
8480   case X86::VPMINUDrr:
8481   case X86::VPMINUDYrr:
8482   case X86::VPMINUDZ128rr:
8483   case X86::VPMINUDZ256rr:
8484   case X86::VPMINUDZrr:
8485   case X86::VPMINUQZ128rr:
8486   case X86::VPMINUQZ256rr:
8487   case X86::VPMINUQZrr:
8488   case X86::VPMINUWrr:
8489   case X86::VPMINUWYrr:
8490   case X86::VPMINUWZ128rr:
8491   case X86::VPMINUWZ256rr:
8492   case X86::VPMINUWZrr:
8493   // Normal min/max instructions are not commutative because of NaN and signed
8494   // zero semantics, but these are. Thus, there's no need to check for global
8495   // relaxed math; the instructions themselves have the properties we need.
8496   case X86::MAXCPDrr:
8497   case X86::MAXCPSrr:
8498   case X86::MAXCSDrr:
8499   case X86::MAXCSSrr:
8500   case X86::MINCPDrr:
8501   case X86::MINCPSrr:
8502   case X86::MINCSDrr:
8503   case X86::MINCSSrr:
8504   case X86::VMAXCPDrr:
8505   case X86::VMAXCPSrr:
8506   case X86::VMAXCPDYrr:
8507   case X86::VMAXCPSYrr:
8508   case X86::VMAXCPDZ128rr:
8509   case X86::VMAXCPSZ128rr:
8510   case X86::VMAXCPDZ256rr:
8511   case X86::VMAXCPSZ256rr:
8512   case X86::VMAXCPDZrr:
8513   case X86::VMAXCPSZrr:
8514   case X86::VMAXCSDrr:
8515   case X86::VMAXCSSrr:
8516   case X86::VMAXCSDZrr:
8517   case X86::VMAXCSSZrr:
8518   case X86::VMINCPDrr:
8519   case X86::VMINCPSrr:
8520   case X86::VMINCPDYrr:
8521   case X86::VMINCPSYrr:
8522   case X86::VMINCPDZ128rr:
8523   case X86::VMINCPSZ128rr:
8524   case X86::VMINCPDZ256rr:
8525   case X86::VMINCPSZ256rr:
8526   case X86::VMINCPDZrr:
8527   case X86::VMINCPSZrr:
8528   case X86::VMINCSDrr:
8529   case X86::VMINCSSrr:
8530   case X86::VMINCSDZrr:
8531   case X86::VMINCSSZrr:
8532   case X86::VMAXCPHZ128rr:
8533   case X86::VMAXCPHZ256rr:
8534   case X86::VMAXCPHZrr:
8535   case X86::VMAXCSHZrr:
8536   case X86::VMINCPHZ128rr:
8537   case X86::VMINCPHZ256rr:
8538   case X86::VMINCPHZrr:
8539   case X86::VMINCSHZrr:
8540     return true;
8541   case X86::ADDPDrr:
8542   case X86::ADDPSrr:
8543   case X86::ADDSDrr:
8544   case X86::ADDSSrr:
8545   case X86::MULPDrr:
8546   case X86::MULPSrr:
8547   case X86::MULSDrr:
8548   case X86::MULSSrr:
8549   case X86::VADDPDrr:
8550   case X86::VADDPSrr:
8551   case X86::VADDPDYrr:
8552   case X86::VADDPSYrr:
8553   case X86::VADDPDZ128rr:
8554   case X86::VADDPSZ128rr:
8555   case X86::VADDPDZ256rr:
8556   case X86::VADDPSZ256rr:
8557   case X86::VADDPDZrr:
8558   case X86::VADDPSZrr:
8559   case X86::VADDSDrr:
8560   case X86::VADDSSrr:
8561   case X86::VADDSDZrr:
8562   case X86::VADDSSZrr:
8563   case X86::VMULPDrr:
8564   case X86::VMULPSrr:
8565   case X86::VMULPDYrr:
8566   case X86::VMULPSYrr:
8567   case X86::VMULPDZ128rr:
8568   case X86::VMULPSZ128rr:
8569   case X86::VMULPDZ256rr:
8570   case X86::VMULPSZ256rr:
8571   case X86::VMULPDZrr:
8572   case X86::VMULPSZrr:
8573   case X86::VMULSDrr:
8574   case X86::VMULSSrr:
8575   case X86::VMULSDZrr:
8576   case X86::VMULSSZrr:
8577   case X86::VADDPHZ128rr:
8578   case X86::VADDPHZ256rr:
8579   case X86::VADDPHZrr:
8580   case X86::VADDSHZrr:
8581   case X86::VMULPHZ128rr:
8582   case X86::VMULPHZ256rr:
8583   case X86::VMULPHZrr:
8584   case X86::VMULSHZrr:
8585     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
8586            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
8587   default:
8588     return false;
8589   }
8590 }
8591 
8592 /// If \p DescribedReg overlaps with the MOVrr instruction's destination
8593 /// register then, if possible, describe the value in terms of the source
8594 /// register.
8595 static Optional<ParamLoadedValue>
8596 describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
8597                          const TargetRegisterInfo *TRI) {
8598   Register DestReg = MI.getOperand(0).getReg();
8599   Register SrcReg = MI.getOperand(1).getReg();
8600 
8601   auto Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8602 
8603   // If the described register is the destination, just return the source.
8604   if (DestReg == DescribedReg)
8605     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8606 
8607   // If the described register is a sub-register of the destination register,
8608   // then pick out the source register's corresponding sub-register.
8609   if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) {
8610     Register SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx);
8611     return ParamLoadedValue(MachineOperand::CreateReg(SrcSubReg, false), Expr);
8612   }
8613 
8614   // The remaining case to consider is when the described register is a
8615   // super-register of the destination register. MOV8rr and MOV16rr does not
8616   // write to any of the other bytes in the register, meaning that we'd have to
8617   // describe the value using a combination of the source register and the
8618   // non-overlapping bits in the described register, which is not currently
8619   // possible.
8620   if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
8621       !TRI->isSuperRegister(DestReg, DescribedReg))
8622     return None;
8623 
8624   assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
8625   return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8626 }
8627 
8628 Optional<ParamLoadedValue>
8629 X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
8630   const MachineOperand *Op = nullptr;
8631   DIExpression *Expr = nullptr;
8632 
8633   const TargetRegisterInfo *TRI = &getRegisterInfo();
8634 
8635   switch (MI.getOpcode()) {
8636   case X86::LEA32r:
8637   case X86::LEA64r:
8638   case X86::LEA64_32r: {
8639     // We may need to describe a 64-bit parameter with a 32-bit LEA.
8640     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8641       return None;
8642 
8643     // Operand 4 could be global address. For now we do not support
8644     // such situation.
8645     if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
8646       return None;
8647 
8648     const MachineOperand &Op1 = MI.getOperand(1);
8649     const MachineOperand &Op2 = MI.getOperand(3);
8650     assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
8651                            Register::isPhysicalRegister(Op2.getReg())));
8652 
8653     // Omit situations like:
8654     // %rsi = lea %rsi, 4, ...
8655     if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
8656         Op2.getReg() == MI.getOperand(0).getReg())
8657       return None;
8658     else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
8659               TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
8660              (Op2.getReg() != X86::NoRegister &&
8661               TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
8662       return None;
8663 
8664     int64_t Coef = MI.getOperand(2).getImm();
8665     int64_t Offset = MI.getOperand(4).getImm();
8666     SmallVector<uint64_t, 8> Ops;
8667 
8668     if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
8669       Op = &Op1;
8670     } else if (Op1.isFI())
8671       Op = &Op1;
8672 
8673     if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
8674       Ops.push_back(dwarf::DW_OP_constu);
8675       Ops.push_back(Coef + 1);
8676       Ops.push_back(dwarf::DW_OP_mul);
8677     } else {
8678       if (Op && Op2.getReg() != X86::NoRegister) {
8679         int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
8680         if (dwarfReg < 0)
8681           return None;
8682         else if (dwarfReg < 32) {
8683           Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
8684           Ops.push_back(0);
8685         } else {
8686           Ops.push_back(dwarf::DW_OP_bregx);
8687           Ops.push_back(dwarfReg);
8688           Ops.push_back(0);
8689         }
8690       } else if (!Op) {
8691         assert(Op2.getReg() != X86::NoRegister);
8692         Op = &Op2;
8693       }
8694 
8695       if (Coef > 1) {
8696         assert(Op2.getReg() != X86::NoRegister);
8697         Ops.push_back(dwarf::DW_OP_constu);
8698         Ops.push_back(Coef);
8699         Ops.push_back(dwarf::DW_OP_mul);
8700       }
8701 
8702       if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
8703           Op2.getReg() != X86::NoRegister) {
8704         Ops.push_back(dwarf::DW_OP_plus);
8705       }
8706     }
8707 
8708     DIExpression::appendOffset(Ops, Offset);
8709     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
8710 
8711     return ParamLoadedValue(*Op, Expr);;
8712   }
8713   case X86::MOV8ri:
8714   case X86::MOV16ri:
8715     // TODO: Handle MOV8ri and MOV16ri.
8716     return None;
8717   case X86::MOV32ri:
8718   case X86::MOV64ri:
8719   case X86::MOV64ri32:
8720     // MOV32ri may be used for producing zero-extended 32-bit immediates in
8721     // 64-bit parameters, so we need to consider super-registers.
8722     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8723       return None;
8724     return ParamLoadedValue(MI.getOperand(1), Expr);
8725   case X86::MOV8rr:
8726   case X86::MOV16rr:
8727   case X86::MOV32rr:
8728   case X86::MOV64rr:
8729     return describeMOVrrLoadedValue(MI, Reg, TRI);
8730   case X86::XOR32rr: {
8731     // 64-bit parameters are zero-materialized using XOR32rr, so also consider
8732     // super-registers.
8733     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8734       return None;
8735     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
8736       return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
8737     return None;
8738   }
8739   case X86::MOVSX64rr32: {
8740     // We may need to describe the lower 32 bits of the MOVSX; for example, in
8741     // cases like this:
8742     //
8743     //  $ebx = [...]
8744     //  $rdi = MOVSX64rr32 $ebx
8745     //  $esi = MOV32rr $edi
8746     if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg))
8747       return None;
8748 
8749     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8750 
8751     // If the described register is the destination register we need to
8752     // sign-extend the source register from 32 bits. The other case we handle
8753     // is when the described register is the 32-bit sub-register of the
8754     // destination register, in case we just need to return the source
8755     // register.
8756     if (Reg == MI.getOperand(0).getReg())
8757       Expr = DIExpression::appendExt(Expr, 32, 64, true);
8758     else
8759       assert(X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg) &&
8760              "Unhandled sub-register case for MOVSX64rr32");
8761 
8762     return ParamLoadedValue(MI.getOperand(1), Expr);
8763   }
8764   default:
8765     assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
8766     return TargetInstrInfo::describeLoadedValue(MI, Reg);
8767   }
8768 }
8769 
8770 /// This is an architecture-specific helper function of reassociateOps.
8771 /// Set special operand attributes for new instructions after reassociation.
8772 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
8773                                          MachineInstr &OldMI2,
8774                                          MachineInstr &NewMI1,
8775                                          MachineInstr &NewMI2) const {
8776   // Propagate FP flags from the original instructions.
8777   // But clear poison-generating flags because those may not be valid now.
8778   // TODO: There should be a helper function for copying only fast-math-flags.
8779   uint16_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
8780   NewMI1.setFlags(IntersectedFlags);
8781   NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
8782   NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
8783   NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
8784 
8785   NewMI2.setFlags(IntersectedFlags);
8786   NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
8787   NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
8788   NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
8789 
8790   // Integer instructions may define an implicit EFLAGS dest register operand.
8791   MachineOperand *OldFlagDef1 = OldMI1.findRegisterDefOperand(X86::EFLAGS);
8792   MachineOperand *OldFlagDef2 = OldMI2.findRegisterDefOperand(X86::EFLAGS);
8793 
8794   assert(!OldFlagDef1 == !OldFlagDef2 &&
8795          "Unexpected instruction type for reassociation");
8796 
8797   if (!OldFlagDef1 || !OldFlagDef2)
8798     return;
8799 
8800   assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
8801          "Must have dead EFLAGS operand in reassociable instruction");
8802 
8803   MachineOperand *NewFlagDef1 = NewMI1.findRegisterDefOperand(X86::EFLAGS);
8804   MachineOperand *NewFlagDef2 = NewMI2.findRegisterDefOperand(X86::EFLAGS);
8805 
8806   assert(NewFlagDef1 && NewFlagDef2 &&
8807          "Unexpected operand in reassociable instruction");
8808 
8809   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8810   // of this pass or other passes. The EFLAGS operands must be dead in these new
8811   // instructions because the EFLAGS operands in the original instructions must
8812   // be dead in order for reassociation to occur.
8813   NewFlagDef1->setIsDead();
8814   NewFlagDef2->setIsDead();
8815 }
8816 
8817 std::pair<unsigned, unsigned>
8818 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8819   return std::make_pair(TF, 0u);
8820 }
8821 
8822 ArrayRef<std::pair<unsigned, const char *>>
8823 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8824   using namespace X86II;
8825   static const std::pair<unsigned, const char *> TargetFlags[] = {
8826       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8827       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
8828       {MO_GOT, "x86-got"},
8829       {MO_GOTOFF, "x86-gotoff"},
8830       {MO_GOTPCREL, "x86-gotpcrel"},
8831       {MO_PLT, "x86-plt"},
8832       {MO_TLSGD, "x86-tlsgd"},
8833       {MO_TLSLD, "x86-tlsld"},
8834       {MO_TLSLDM, "x86-tlsldm"},
8835       {MO_GOTTPOFF, "x86-gottpoff"},
8836       {MO_INDNTPOFF, "x86-indntpoff"},
8837       {MO_TPOFF, "x86-tpoff"},
8838       {MO_DTPOFF, "x86-dtpoff"},
8839       {MO_NTPOFF, "x86-ntpoff"},
8840       {MO_GOTNTPOFF, "x86-gotntpoff"},
8841       {MO_DLLIMPORT, "x86-dllimport"},
8842       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
8843       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
8844       {MO_TLVP, "x86-tlvp"},
8845       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
8846       {MO_SECREL, "x86-secrel"},
8847       {MO_COFFSTUB, "x86-coffstub"}};
8848   return makeArrayRef(TargetFlags);
8849 }
8850 
8851 namespace {
8852   /// Create Global Base Reg pass. This initializes the PIC
8853   /// global base register for x86-32.
8854   struct CGBR : public MachineFunctionPass {
8855     static char ID;
8856     CGBR() : MachineFunctionPass(ID) {}
8857 
8858     bool runOnMachineFunction(MachineFunction &MF) override {
8859       const X86TargetMachine *TM =
8860         static_cast<const X86TargetMachine *>(&MF.getTarget());
8861       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
8862 
8863       // Don't do anything in the 64-bit small and kernel code models. They use
8864       // RIP-relative addressing for everything.
8865       if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
8866                             TM->getCodeModel() == CodeModel::Kernel))
8867         return false;
8868 
8869       // Only emit a global base reg in PIC mode.
8870       if (!TM->isPositionIndependent())
8871         return false;
8872 
8873       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8874       Register GlobalBaseReg = X86FI->getGlobalBaseReg();
8875 
8876       // If we didn't need a GlobalBaseReg, don't insert code.
8877       if (GlobalBaseReg == 0)
8878         return false;
8879 
8880       // Insert the set of GlobalBaseReg into the first MBB of the function
8881       MachineBasicBlock &FirstMBB = MF.front();
8882       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
8883       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
8884       MachineRegisterInfo &RegInfo = MF.getRegInfo();
8885       const X86InstrInfo *TII = STI.getInstrInfo();
8886 
8887       Register PC;
8888       if (STI.isPICStyleGOT())
8889         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
8890       else
8891         PC = GlobalBaseReg;
8892 
8893       if (STI.is64Bit()) {
8894         if (TM->getCodeModel() == CodeModel::Medium) {
8895           // In the medium code model, use a RIP-relative LEA to materialize the
8896           // GOT.
8897           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
8898               .addReg(X86::RIP)
8899               .addImm(0)
8900               .addReg(0)
8901               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
8902               .addReg(0);
8903         } else if (TM->getCodeModel() == CodeModel::Large) {
8904           // In the large code model, we are aiming for this code, though the
8905           // register allocation may vary:
8906           //   leaq .LN$pb(%rip), %rax
8907           //   movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
8908           //   addq %rcx, %rax
8909           // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
8910           Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8911           Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8912           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
8913               .addReg(X86::RIP)
8914               .addImm(0)
8915               .addReg(0)
8916               .addSym(MF.getPICBaseSymbol())
8917               .addReg(0);
8918           std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
8919           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
8920               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8921                                  X86II::MO_PIC_BASE_OFFSET);
8922           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
8923               .addReg(PBReg, RegState::Kill)
8924               .addReg(GOTReg, RegState::Kill);
8925         } else {
8926           llvm_unreachable("unexpected code model");
8927         }
8928       } else {
8929         // Operand of MovePCtoStack is completely ignored by asm printer. It's
8930         // only used in JIT code emission as displacement to pc.
8931         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
8932 
8933         // If we're using vanilla 'GOT' PIC style, we should use relative
8934         // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
8935         if (STI.isPICStyleGOT()) {
8936           // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
8937           // %some_register
8938           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
8939               .addReg(PC)
8940               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8941                                  X86II::MO_GOT_ABSOLUTE_ADDRESS);
8942         }
8943       }
8944 
8945       return true;
8946     }
8947 
8948     StringRef getPassName() const override {
8949       return "X86 PIC Global Base Reg Initialization";
8950     }
8951 
8952     void getAnalysisUsage(AnalysisUsage &AU) const override {
8953       AU.setPreservesCFG();
8954       MachineFunctionPass::getAnalysisUsage(AU);
8955     }
8956   };
8957 } // namespace
8958 
8959 char CGBR::ID = 0;
8960 FunctionPass*
8961 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
8962 
8963 namespace {
8964   struct LDTLSCleanup : public MachineFunctionPass {
8965     static char ID;
8966     LDTLSCleanup() : MachineFunctionPass(ID) {}
8967 
8968     bool runOnMachineFunction(MachineFunction &MF) override {
8969       if (skipFunction(MF.getFunction()))
8970         return false;
8971 
8972       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
8973       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8974         // No point folding accesses if there isn't at least two.
8975         return false;
8976       }
8977 
8978       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8979       return VisitNode(DT->getRootNode(), 0);
8980     }
8981 
8982     // Visit the dominator subtree rooted at Node in pre-order.
8983     // If TLSBaseAddrReg is non-null, then use that to replace any
8984     // TLS_base_addr instructions. Otherwise, create the register
8985     // when the first such instruction is seen, and then use it
8986     // as we encounter more instructions.
8987     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8988       MachineBasicBlock *BB = Node->getBlock();
8989       bool Changed = false;
8990 
8991       // Traverse the current block.
8992       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8993            ++I) {
8994         switch (I->getOpcode()) {
8995           case X86::TLS_base_addr32:
8996           case X86::TLS_base_addr64:
8997             if (TLSBaseAddrReg)
8998               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
8999             else
9000               I = SetRegister(*I, &TLSBaseAddrReg);
9001             Changed = true;
9002             break;
9003           default:
9004             break;
9005         }
9006       }
9007 
9008       // Visit the children of this block in the dominator tree.
9009       for (auto I = Node->begin(), E = Node->end(); I != E; ++I) {
9010         Changed |= VisitNode(*I, TLSBaseAddrReg);
9011       }
9012 
9013       return Changed;
9014     }
9015 
9016     // Replace the TLS_base_addr instruction I with a copy from
9017     // TLSBaseAddrReg, returning the new instruction.
9018     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
9019                                          unsigned TLSBaseAddrReg) {
9020       MachineFunction *MF = I.getParent()->getParent();
9021       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
9022       const bool is64Bit = STI.is64Bit();
9023       const X86InstrInfo *TII = STI.getInstrInfo();
9024 
9025       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
9026       MachineInstr *Copy =
9027           BuildMI(*I.getParent(), I, I.getDebugLoc(),
9028                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
9029               .addReg(TLSBaseAddrReg);
9030 
9031       // Erase the TLS_base_addr instruction.
9032       I.eraseFromParent();
9033 
9034       return Copy;
9035     }
9036 
9037     // Create a virtual register in *TLSBaseAddrReg, and populate it by
9038     // inserting a copy instruction after I. Returns the new instruction.
9039     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
9040       MachineFunction *MF = I.getParent()->getParent();
9041       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
9042       const bool is64Bit = STI.is64Bit();
9043       const X86InstrInfo *TII = STI.getInstrInfo();
9044 
9045       // Create a virtual register for the TLS base address.
9046       MachineRegisterInfo &RegInfo = MF->getRegInfo();
9047       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
9048                                                       ? &X86::GR64RegClass
9049                                                       : &X86::GR32RegClass);
9050 
9051       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
9052       MachineInstr *Next = I.getNextNode();
9053       MachineInstr *Copy =
9054           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
9055                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
9056               .addReg(is64Bit ? X86::RAX : X86::EAX);
9057 
9058       return Copy;
9059     }
9060 
9061     StringRef getPassName() const override {
9062       return "Local Dynamic TLS Access Clean-up";
9063     }
9064 
9065     void getAnalysisUsage(AnalysisUsage &AU) const override {
9066       AU.setPreservesCFG();
9067       AU.addRequired<MachineDominatorTree>();
9068       MachineFunctionPass::getAnalysisUsage(AU);
9069     }
9070   };
9071 }
9072 
9073 char LDTLSCleanup::ID = 0;
9074 FunctionPass*
9075 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
9076 
9077 /// Constants defining how certain sequences should be outlined.
9078 ///
9079 /// \p MachineOutlinerDefault implies that the function is called with a call
9080 /// instruction, and a return must be emitted for the outlined function frame.
9081 ///
9082 /// That is,
9083 ///
9084 /// I1                                 OUTLINED_FUNCTION:
9085 /// I2 --> call OUTLINED_FUNCTION       I1
9086 /// I3                                  I2
9087 ///                                     I3
9088 ///                                     ret
9089 ///
9090 /// * Call construction overhead: 1 (call instruction)
9091 /// * Frame construction overhead: 1 (return instruction)
9092 ///
9093 /// \p MachineOutlinerTailCall implies that the function is being tail called.
9094 /// A jump is emitted instead of a call, and the return is already present in
9095 /// the outlined sequence. That is,
9096 ///
9097 /// I1                                 OUTLINED_FUNCTION:
9098 /// I2 --> jmp OUTLINED_FUNCTION       I1
9099 /// ret                                I2
9100 ///                                    ret
9101 ///
9102 /// * Call construction overhead: 1 (jump instruction)
9103 /// * Frame construction overhead: 0 (don't need to return)
9104 ///
9105 enum MachineOutlinerClass {
9106   MachineOutlinerDefault,
9107   MachineOutlinerTailCall
9108 };
9109 
9110 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
9111     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
9112   unsigned SequenceSize =
9113       std::accumulate(RepeatedSequenceLocs[0].front(),
9114                       std::next(RepeatedSequenceLocs[0].back()), 0,
9115                       [](unsigned Sum, const MachineInstr &MI) {
9116                         // FIXME: x86 doesn't implement getInstSizeInBytes, so
9117                         // we can't tell the cost.  Just assume each instruction
9118                         // is one byte.
9119                         if (MI.isDebugInstr() || MI.isKill())
9120                           return Sum;
9121                         return Sum + 1;
9122                       });
9123 
9124   // We check to see if CFI Instructions are present, and if they are
9125   // we find the number of CFI Instructions in the candidates.
9126   unsigned CFICount = 0;
9127   MachineBasicBlock::iterator MBBI = RepeatedSequenceLocs[0].front();
9128   for (unsigned Loc = RepeatedSequenceLocs[0].getStartIdx();
9129        Loc < RepeatedSequenceLocs[0].getEndIdx() + 1; Loc++) {
9130     const std::vector<MCCFIInstruction> &CFIInstructions =
9131         RepeatedSequenceLocs[0].getMF()->getFrameInstructions();
9132     if (MBBI->isCFIInstruction()) {
9133       unsigned CFIIndex = MBBI->getOperand(0).getCFIIndex();
9134       MCCFIInstruction CFI = CFIInstructions[CFIIndex];
9135       CFICount++;
9136     }
9137     MBBI++;
9138   }
9139 
9140   // We compare the number of found CFI Instructions to  the number of CFI
9141   // instructions in the parent function for each candidate.  We must check this
9142   // since if we outline one of the CFI instructions in a function, we have to
9143   // outline them all for correctness. If we do not, the address offsets will be
9144   // incorrect between the two sections of the program.
9145   for (outliner::Candidate &C : RepeatedSequenceLocs) {
9146     std::vector<MCCFIInstruction> CFIInstructions =
9147         C.getMF()->getFrameInstructions();
9148 
9149     if (CFICount > 0 && CFICount != CFIInstructions.size())
9150       return outliner::OutlinedFunction();
9151   }
9152 
9153   // FIXME: Use real size in bytes for call and ret instructions.
9154   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
9155     for (outliner::Candidate &C : RepeatedSequenceLocs)
9156       C.setCallInfo(MachineOutlinerTailCall, 1);
9157 
9158     return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
9159                                       0, // Number of bytes to emit frame.
9160                                       MachineOutlinerTailCall // Type of frame.
9161     );
9162   }
9163 
9164   if (CFICount > 0)
9165     return outliner::OutlinedFunction();
9166 
9167   for (outliner::Candidate &C : RepeatedSequenceLocs)
9168     C.setCallInfo(MachineOutlinerDefault, 1);
9169 
9170   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
9171                                     MachineOutlinerDefault);
9172 }
9173 
9174 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
9175                                            bool OutlineFromLinkOnceODRs) const {
9176   const Function &F = MF.getFunction();
9177 
9178   // Does the function use a red zone? If it does, then we can't risk messing
9179   // with the stack.
9180   if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
9181     // It could have a red zone. If it does, then we don't want to touch it.
9182     const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
9183     if (!X86FI || X86FI->getUsesRedZone())
9184       return false;
9185   }
9186 
9187   // If we *don't* want to outline from things that could potentially be deduped
9188   // then return false.
9189   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
9190       return false;
9191 
9192   // This function is viable for outlining, so return true.
9193   return true;
9194 }
9195 
9196 outliner::InstrType
9197 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  unsigned Flags) const {
9198   MachineInstr &MI = *MIT;
9199   // Don't allow debug values to impact outlining type.
9200   if (MI.isDebugInstr() || MI.isIndirectDebugValue())
9201     return outliner::InstrType::Invisible;
9202 
9203   // At this point, KILL instructions don't really tell us much so we can go
9204   // ahead and skip over them.
9205   if (MI.isKill())
9206     return outliner::InstrType::Invisible;
9207 
9208   // Is this a tail call? If yes, we can outline as a tail call.
9209   if (isTailCall(MI))
9210     return outliner::InstrType::Legal;
9211 
9212   // Is this the terminator of a basic block?
9213   if (MI.isTerminator() || MI.isReturn()) {
9214 
9215     // Does its parent have any successors in its MachineFunction?
9216     if (MI.getParent()->succ_empty())
9217       return outliner::InstrType::Legal;
9218 
9219     // It does, so we can't tail call it.
9220     return outliner::InstrType::Illegal;
9221   }
9222 
9223   // Don't outline anything that modifies or reads from the stack pointer.
9224   //
9225   // FIXME: There are instructions which are being manually built without
9226   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
9227   // able to remove the extra checks once those are fixed up. For example,
9228   // sometimes we might get something like %rax = POP64r 1. This won't be
9229   // caught by modifiesRegister or readsRegister even though the instruction
9230   // really ought to be formed so that modifiesRegister/readsRegister would
9231   // catch it.
9232   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
9233       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
9234       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
9235     return outliner::InstrType::Illegal;
9236 
9237   // Outlined calls change the instruction pointer, so don't read from it.
9238   if (MI.readsRegister(X86::RIP, &RI) ||
9239       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
9240       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
9241     return outliner::InstrType::Illegal;
9242 
9243   // Positions can't safely be outlined.
9244   if (MI.isPosition())
9245     return outliner::InstrType::Illegal;
9246 
9247   // Make sure none of the operands of this instruction do anything tricky.
9248   for (const MachineOperand &MOP : MI.operands())
9249     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
9250         MOP.isTargetIndex())
9251       return outliner::InstrType::Illegal;
9252 
9253   return outliner::InstrType::Legal;
9254 }
9255 
9256 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
9257                                           MachineFunction &MF,
9258                                           const outliner::OutlinedFunction &OF)
9259                                           const {
9260   // If we're a tail call, we already have a return, so don't do anything.
9261   if (OF.FrameConstructionID == MachineOutlinerTailCall)
9262     return;
9263 
9264   // We're a normal call, so our sequence doesn't have a return instruction.
9265   // Add it in.
9266   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
9267   MBB.insert(MBB.end(), retq);
9268 }
9269 
9270 MachineBasicBlock::iterator
9271 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
9272                                  MachineBasicBlock::iterator &It,
9273                                  MachineFunction &MF,
9274                                  const outliner::Candidate &C) const {
9275   // Is it a tail call?
9276   if (C.CallConstructionID == MachineOutlinerTailCall) {
9277     // Yes, just insert a JMP.
9278     It = MBB.insert(It,
9279                   BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
9280                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9281   } else {
9282     // No, insert a call.
9283     It = MBB.insert(It,
9284                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
9285                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9286   }
9287 
9288   return It;
9289 }
9290 
9291 #define GET_INSTRINFO_HELPERS
9292 #include "X86GenInstrInfo.inc"
9293