1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include <limits>
37 
38 #define GET_INSTRINFO_CTOR
39 #include "X86GenInstrInfo.inc"
40 
41 using namespace llvm;
42 
43 static cl::opt<bool>
44 NoFusing("disable-spill-fusing",
45          cl::desc("Disable fusing of spill code into instructions"));
46 static cl::opt<bool>
47 PrintFailedFusing("print-failed-fuse-candidates",
48                   cl::desc("Print instructions that the allocator wants to"
49                            " fuse, but the X86 backend currently can't"),
50                   cl::Hidden);
51 static cl::opt<bool>
52 ReMatPICStubLoad("remat-pic-stub-load",
53                  cl::desc("Re-materialize load from stub in PIC mode"),
54                  cl::init(false), cl::Hidden);
55 
56 enum {
57   // Select which memory operand is being unfolded.
58   // (stored in bits 0 - 3)
59   TB_INDEX_0    = 0,
60   TB_INDEX_1    = 1,
61   TB_INDEX_2    = 2,
62   TB_INDEX_3    = 3,
63   TB_INDEX_MASK = 0xf,
64 
65   // Do not insert the reverse map (MemOp -> RegOp) into the table.
66   // This may be needed because there is a many -> one mapping.
67   TB_NO_REVERSE   = 1 << 4,
68 
69   // Do not insert the forward map (RegOp -> MemOp) into the table.
70   // This is needed for Native Client, which prohibits branch
71   // instructions from using a memory operand.
72   TB_NO_FORWARD   = 1 << 5,
73 
74   TB_FOLDED_LOAD  = 1 << 6,
75   TB_FOLDED_STORE = 1 << 7,
76 
77   // Minimum alignment required for load/store.
78   // Used for RegOp->MemOp conversion.
79   // (stored in bits 8 - 15)
80   TB_ALIGN_SHIFT = 8,
81   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
82   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
83   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
84   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
85   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
86 };
87 
88 struct X86OpTblEntry {
89   uint16_t RegOp;
90   uint16_t MemOp;
91   uint16_t Flags;
92 };
93 
94 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
95   : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
96                      ? X86::ADJCALLSTACKDOWN64
97                      : X86::ADJCALLSTACKDOWN32),
98                     (tm.getSubtarget<X86Subtarget>().is64Bit()
99                      ? X86::ADJCALLSTACKUP64
100                      : X86::ADJCALLSTACKUP32)),
101     TM(tm), RI(tm) {
102 
103   static const X86OpTblEntry OpTbl2Addr[] = {
104     { X86::ADC32ri,     X86::ADC32mi,    0 },
105     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
106     { X86::ADC32rr,     X86::ADC32mr,    0 },
107     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
108     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
109     { X86::ADC64rr,     X86::ADC64mr,    0 },
110     { X86::ADD16ri,     X86::ADD16mi,    0 },
111     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
112     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
113     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
114     { X86::ADD16rr,     X86::ADD16mr,    0 },
115     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
116     { X86::ADD32ri,     X86::ADD32mi,    0 },
117     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
118     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
119     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
120     { X86::ADD32rr,     X86::ADD32mr,    0 },
121     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
122     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
123     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
124     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
125     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
126     { X86::ADD64rr,     X86::ADD64mr,    0 },
127     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
128     { X86::ADD8ri,      X86::ADD8mi,     0 },
129     { X86::ADD8rr,      X86::ADD8mr,     0 },
130     { X86::AND16ri,     X86::AND16mi,    0 },
131     { X86::AND16ri8,    X86::AND16mi8,   0 },
132     { X86::AND16rr,     X86::AND16mr,    0 },
133     { X86::AND32ri,     X86::AND32mi,    0 },
134     { X86::AND32ri8,    X86::AND32mi8,   0 },
135     { X86::AND32rr,     X86::AND32mr,    0 },
136     { X86::AND64ri32,   X86::AND64mi32,  0 },
137     { X86::AND64ri8,    X86::AND64mi8,   0 },
138     { X86::AND64rr,     X86::AND64mr,    0 },
139     { X86::AND8ri,      X86::AND8mi,     0 },
140     { X86::AND8rr,      X86::AND8mr,     0 },
141     { X86::DEC16r,      X86::DEC16m,     0 },
142     { X86::DEC32r,      X86::DEC32m,     0 },
143     { X86::DEC64_16r,   X86::DEC64_16m,  0 },
144     { X86::DEC64_32r,   X86::DEC64_32m,  0 },
145     { X86::DEC64r,      X86::DEC64m,     0 },
146     { X86::DEC8r,       X86::DEC8m,      0 },
147     { X86::INC16r,      X86::INC16m,     0 },
148     { X86::INC32r,      X86::INC32m,     0 },
149     { X86::INC64_16r,   X86::INC64_16m,  0 },
150     { X86::INC64_32r,   X86::INC64_32m,  0 },
151     { X86::INC64r,      X86::INC64m,     0 },
152     { X86::INC8r,       X86::INC8m,      0 },
153     { X86::NEG16r,      X86::NEG16m,     0 },
154     { X86::NEG32r,      X86::NEG32m,     0 },
155     { X86::NEG64r,      X86::NEG64m,     0 },
156     { X86::NEG8r,       X86::NEG8m,      0 },
157     { X86::NOT16r,      X86::NOT16m,     0 },
158     { X86::NOT32r,      X86::NOT32m,     0 },
159     { X86::NOT64r,      X86::NOT64m,     0 },
160     { X86::NOT8r,       X86::NOT8m,      0 },
161     { X86::OR16ri,      X86::OR16mi,     0 },
162     { X86::OR16ri8,     X86::OR16mi8,    0 },
163     { X86::OR16rr,      X86::OR16mr,     0 },
164     { X86::OR32ri,      X86::OR32mi,     0 },
165     { X86::OR32ri8,     X86::OR32mi8,    0 },
166     { X86::OR32rr,      X86::OR32mr,     0 },
167     { X86::OR64ri32,    X86::OR64mi32,   0 },
168     { X86::OR64ri8,     X86::OR64mi8,    0 },
169     { X86::OR64rr,      X86::OR64mr,     0 },
170     { X86::OR8ri,       X86::OR8mi,      0 },
171     { X86::OR8rr,       X86::OR8mr,      0 },
172     { X86::ROL16r1,     X86::ROL16m1,    0 },
173     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
174     { X86::ROL16ri,     X86::ROL16mi,    0 },
175     { X86::ROL32r1,     X86::ROL32m1,    0 },
176     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
177     { X86::ROL32ri,     X86::ROL32mi,    0 },
178     { X86::ROL64r1,     X86::ROL64m1,    0 },
179     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
180     { X86::ROL64ri,     X86::ROL64mi,    0 },
181     { X86::ROL8r1,      X86::ROL8m1,     0 },
182     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
183     { X86::ROL8ri,      X86::ROL8mi,     0 },
184     { X86::ROR16r1,     X86::ROR16m1,    0 },
185     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
186     { X86::ROR16ri,     X86::ROR16mi,    0 },
187     { X86::ROR32r1,     X86::ROR32m1,    0 },
188     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
189     { X86::ROR32ri,     X86::ROR32mi,    0 },
190     { X86::ROR64r1,     X86::ROR64m1,    0 },
191     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
192     { X86::ROR64ri,     X86::ROR64mi,    0 },
193     { X86::ROR8r1,      X86::ROR8m1,     0 },
194     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
195     { X86::ROR8ri,      X86::ROR8mi,     0 },
196     { X86::SAR16r1,     X86::SAR16m1,    0 },
197     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
198     { X86::SAR16ri,     X86::SAR16mi,    0 },
199     { X86::SAR32r1,     X86::SAR32m1,    0 },
200     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
201     { X86::SAR32ri,     X86::SAR32mi,    0 },
202     { X86::SAR64r1,     X86::SAR64m1,    0 },
203     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
204     { X86::SAR64ri,     X86::SAR64mi,    0 },
205     { X86::SAR8r1,      X86::SAR8m1,     0 },
206     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
207     { X86::SAR8ri,      X86::SAR8mi,     0 },
208     { X86::SBB32ri,     X86::SBB32mi,    0 },
209     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
210     { X86::SBB32rr,     X86::SBB32mr,    0 },
211     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
212     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
213     { X86::SBB64rr,     X86::SBB64mr,    0 },
214     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
215     { X86::SHL16ri,     X86::SHL16mi,    0 },
216     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
217     { X86::SHL32ri,     X86::SHL32mi,    0 },
218     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
219     { X86::SHL64ri,     X86::SHL64mi,    0 },
220     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
221     { X86::SHL8ri,      X86::SHL8mi,     0 },
222     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
223     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
224     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
225     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
226     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
227     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
228     { X86::SHR16r1,     X86::SHR16m1,    0 },
229     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
230     { X86::SHR16ri,     X86::SHR16mi,    0 },
231     { X86::SHR32r1,     X86::SHR32m1,    0 },
232     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
233     { X86::SHR32ri,     X86::SHR32mi,    0 },
234     { X86::SHR64r1,     X86::SHR64m1,    0 },
235     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
236     { X86::SHR64ri,     X86::SHR64mi,    0 },
237     { X86::SHR8r1,      X86::SHR8m1,     0 },
238     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
239     { X86::SHR8ri,      X86::SHR8mi,     0 },
240     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
241     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
242     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
243     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
244     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
245     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
246     { X86::SUB16ri,     X86::SUB16mi,    0 },
247     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
248     { X86::SUB16rr,     X86::SUB16mr,    0 },
249     { X86::SUB32ri,     X86::SUB32mi,    0 },
250     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
251     { X86::SUB32rr,     X86::SUB32mr,    0 },
252     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
253     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
254     { X86::SUB64rr,     X86::SUB64mr,    0 },
255     { X86::SUB8ri,      X86::SUB8mi,     0 },
256     { X86::SUB8rr,      X86::SUB8mr,     0 },
257     { X86::XOR16ri,     X86::XOR16mi,    0 },
258     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
259     { X86::XOR16rr,     X86::XOR16mr,    0 },
260     { X86::XOR32ri,     X86::XOR32mi,    0 },
261     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
262     { X86::XOR32rr,     X86::XOR32mr,    0 },
263     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
264     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
265     { X86::XOR64rr,     X86::XOR64mr,    0 },
266     { X86::XOR8ri,      X86::XOR8mi,     0 },
267     { X86::XOR8rr,      X86::XOR8mr,     0 }
268   };
269 
270   for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
271     unsigned RegOp = OpTbl2Addr[i].RegOp;
272     unsigned MemOp = OpTbl2Addr[i].MemOp;
273     unsigned Flags = OpTbl2Addr[i].Flags;
274     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
275                   RegOp, MemOp,
276                   // Index 0, folded load and store, no alignment requirement.
277                   Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
278   }
279 
280   static const X86OpTblEntry OpTbl0[] = {
281     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
282     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
283     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
284     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
285     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
286     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
287     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
288     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
289     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
290     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
291     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
292     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
293     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
294     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
295     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
296     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
297     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
298     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
299     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
300     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
301     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
302     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
303     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
304     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
305     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
306     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
307     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
308     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
309     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
310     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
311     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
312     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
313     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
314     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
315     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
316     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
317     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
318     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
319     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
320     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
321     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
322     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
323     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
325     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
326     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
327     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
328     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
329     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
330     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
331     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
332     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
333     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
334     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
335     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
336     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
337     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
338     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
339     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
340     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
341     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
342     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
343     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
344     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
345     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
346     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
347     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
348     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
349     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
350     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
351     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
352     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
353     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
354     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
355     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
356     // AVX 128-bit versions of foldable instructions
357     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
358     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
359     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
360     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
361     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
362     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
363     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
364     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
365     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
366     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
367     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
368     // AVX 256-bit foldable instructions
369     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
370     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
371     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
372     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
373     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
374     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
375     // AVX-512 foldable instructions
376     { X86::VMOVPDI2DIZrr,X86::VMOVPDI2DIZmr,  TB_FOLDED_STORE }
377   };
378 
379   for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
380     unsigned RegOp      = OpTbl0[i].RegOp;
381     unsigned MemOp      = OpTbl0[i].MemOp;
382     unsigned Flags      = OpTbl0[i].Flags;
383     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
384                   RegOp, MemOp, TB_INDEX_0 | Flags);
385   }
386 
387   static const X86OpTblEntry OpTbl1[] = {
388     { X86::CMP16rr,         X86::CMP16rm,             0 },
389     { X86::CMP32rr,         X86::CMP32rm,             0 },
390     { X86::CMP64rr,         X86::CMP64rm,             0 },
391     { X86::CMP8rr,          X86::CMP8rm,              0 },
392     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
393     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
394     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
395     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
396     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
397     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
398     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
399     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
400     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
401     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
402     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
403     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
404     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
405     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
406     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
407     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
408     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
409     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
410     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
411     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
412     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
413     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
414     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
415     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
416     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
417     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
418     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
419     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
420     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
421     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
422     { X86::MOV16rr,         X86::MOV16rm,             0 },
423     { X86::MOV32rr,         X86::MOV32rm,             0 },
424     { X86::MOV64rr,         X86::MOV64rm,             0 },
425     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
426     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
427     { X86::MOV8rr,          X86::MOV8rm,              0 },
428     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
429     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
430     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
431     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
432     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
433     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
434     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
435     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
436     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
437     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
438     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
439     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
440     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
441     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
442     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
443     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
444     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
445     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
446     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
447     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
448     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
449     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
450     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
451     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
452     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
453     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
454     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
455     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
456     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
457     { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
458     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
459     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
460     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
461     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
462     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
463     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
464     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
465     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
466     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
467     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
468     { X86::TEST16rr,        X86::TEST16rm,            0 },
469     { X86::TEST32rr,        X86::TEST32rm,            0 },
470     { X86::TEST64rr,        X86::TEST64rm,            0 },
471     { X86::TEST8rr,         X86::TEST8rm,             0 },
472     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
473     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
474     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
475     // AVX 128-bit versions of foldable instructions
476     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
477     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
478     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
479     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
480     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
481     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
482     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
483     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
484     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
485     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
486     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
487     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
488     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
489     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
490     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
491     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
492     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
493     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
494     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
495     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
496     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
497     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
498     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
499     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
500     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
501     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
502     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
503     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
504     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
505     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
506     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
507     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
508     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
509     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
510     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
511     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
512     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
513     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
514     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
515     { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
516     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
517     { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
518     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
519     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
520     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
521     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
522     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
523 
524     // AVX 256-bit foldable instructions
525     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
526     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
527     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
528     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
529     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
530     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
531     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
532 
533     // AVX2 foldable instructions
534     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
535     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
536     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
537     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
538     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
539     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
540     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
541     { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
542     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
543     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
544     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
545     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
546     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
547 
548     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
549     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
550     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
551     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
552     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
553     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
554     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
555     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
556     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
557     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
558     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
559     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
560     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
561     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
562     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
563     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
564     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
565     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
566     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
567     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
568     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
569     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
570     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
571     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
572     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
573     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
574     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
575     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
576     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
577     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
578     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
579     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
580     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
581     { X86::RORX32ri,        X86::RORX32mi,            0 },
582     { X86::RORX64ri,        X86::RORX64mi,            0 },
583     { X86::SARX32rr,        X86::SARX32rm,            0 },
584     { X86::SARX64rr,        X86::SARX64rm,            0 },
585     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
586     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
587     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
588     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
589     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
590     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
591     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
592     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
593     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
594     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
595     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
596 
597     // AVX-512 foldable instructions
598     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
599     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
600     { X86::VMOVDQA32rr,     X86::VMOVDQA32rm,         TB_ALIGN_64 },
601     { X86::VMOVDQA64rr,     X86::VMOVDQA64rm,         TB_ALIGN_64 },
602     { X86::VMOVDQU32rr,     X86::VMOVDQU32rm,         0 },
603     { X86::VMOVDQU64rr,     X86::VMOVDQU64rm,         0 },
604 
605     // AES foldable instructions
606     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
607     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
608     { X86::VAESIMCrr,             X86::VAESIMCrm,             TB_ALIGN_16 },
609     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 },
610   };
611 
612   for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
613     unsigned RegOp = OpTbl1[i].RegOp;
614     unsigned MemOp = OpTbl1[i].MemOp;
615     unsigned Flags = OpTbl1[i].Flags;
616     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
617                   RegOp, MemOp,
618                   // Index 1, folded load
619                   Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
620   }
621 
622   static const X86OpTblEntry OpTbl2[] = {
623     { X86::ADC32rr,         X86::ADC32rm,       0 },
624     { X86::ADC64rr,         X86::ADC64rm,       0 },
625     { X86::ADD16rr,         X86::ADD16rm,       0 },
626     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
627     { X86::ADD32rr,         X86::ADD32rm,       0 },
628     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
629     { X86::ADD64rr,         X86::ADD64rm,       0 },
630     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
631     { X86::ADD8rr,          X86::ADD8rm,        0 },
632     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
633     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
634     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
635     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
636     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
637     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
638     { X86::AND16rr,         X86::AND16rm,       0 },
639     { X86::AND32rr,         X86::AND32rm,       0 },
640     { X86::AND64rr,         X86::AND64rm,       0 },
641     { X86::AND8rr,          X86::AND8rm,        0 },
642     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
643     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
644     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
645     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
646     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
647     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
648     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
649     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
650     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
651     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
652     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
653     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
654     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
655     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
656     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
657     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
658     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
659     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
660     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
661     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
662     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
663     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
664     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
665     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
666     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
667     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
668     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
669     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
670     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
671     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
672     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
673     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
674     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
675     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
676     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
677     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
678     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
679     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
680     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
681     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
682     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
683     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
684     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
685     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
686     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
687     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
688     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
689     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
690     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
691     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
692     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
693     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
694     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
695     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
696     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
697     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
698     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
699     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
700     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
701     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
702     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
703     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
704     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
705     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
706     { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
707     { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
708     { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
709     { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
710     { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
711     { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
712     { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
713     { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
714     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
715     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
716     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
717     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
718     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
719     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
720     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
721     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
722     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
723     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
724     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
725     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
726     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
727     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
728     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
729     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
730     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
731     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
732     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
733     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
734     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
735     { X86::MINSDrr,         X86::MINSDrm,       0 },
736     { X86::MINSSrr,         X86::MINSSrm,       0 },
737     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
738     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
739     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
740     { X86::MULSDrr,         X86::MULSDrm,       0 },
741     { X86::MULSSrr,         X86::MULSSrm,       0 },
742     { X86::OR16rr,          X86::OR16rm,        0 },
743     { X86::OR32rr,          X86::OR32rm,        0 },
744     { X86::OR64rr,          X86::OR64rm,        0 },
745     { X86::OR8rr,           X86::OR8rm,         0 },
746     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
747     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
748     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
749     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
750     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
751     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
752     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
753     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
754     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
755     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
756     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
757     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
758     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
759     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
760     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
761     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
762     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
763     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
764     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
765     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
766     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
767     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
768     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
769     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
770     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
771     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
772     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
773     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
774     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
775     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
776     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
777     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
778     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
779     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
780     { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
781     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
782     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
783     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
784     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
785     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
786     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
787     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
788     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
789     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
790     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
791     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
792     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
793     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
794     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
795     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
796     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
797     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
798     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
799     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
800     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
801     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
802     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
803     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
804     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
805     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
806     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
807     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
808     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
809     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
810     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
811     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
812     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
813     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
814     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
815     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
816     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
817     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
818     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
819     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
820     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
821     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
822     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
823     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
824     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
825     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
826     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
827     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
828     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
829     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
830     { X86::SBB32rr,         X86::SBB32rm,       0 },
831     { X86::SBB64rr,         X86::SBB64rm,       0 },
832     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
833     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
834     { X86::SUB16rr,         X86::SUB16rm,       0 },
835     { X86::SUB32rr,         X86::SUB32rm,       0 },
836     { X86::SUB64rr,         X86::SUB64rm,       0 },
837     { X86::SUB8rr,          X86::SUB8rm,        0 },
838     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
839     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
840     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
841     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
842     // FIXME: TEST*rr -> swapped operand of TEST*mr.
843     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
844     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
845     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
846     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
847     { X86::XOR16rr,         X86::XOR16rm,       0 },
848     { X86::XOR32rr,         X86::XOR32rm,       0 },
849     { X86::XOR64rr,         X86::XOR64rm,       0 },
850     { X86::XOR8rr,          X86::XOR8rm,        0 },
851     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
852     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
853     // AVX 128-bit versions of foldable instructions
854     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
855     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
856     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
857     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
858     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
859     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
860     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
861     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
862     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
863     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
864     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
865     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
866     { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQXrm,      0 },
867     { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       0 },
868     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
869     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
870     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
871     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
872     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
873     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
874     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
875     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
876     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
877     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
878     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
879     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
880     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
881     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
882     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
883     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
884     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
885     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
886     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
887     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
888     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
889     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
890     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
891     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
892     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
893     { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
894     { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
895     { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
896     { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
897     { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
898     { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
899     { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
900     { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
901     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
902     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
903     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
904     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
905     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
906     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
907     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
908     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
909     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
910     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
911     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
912     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
913     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
914     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
915     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
916     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
917     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
918     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
919     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
920     { X86::VORPDrr,           X86::VORPDrm,            0 },
921     { X86::VORPSrr,           X86::VORPSrm,            0 },
922     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
923     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
924     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
925     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
926     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
927     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
928     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
929     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
930     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
931     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
932     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
933     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
934     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
935     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
936     { X86::VPANDrr,           X86::VPANDrm,            0 },
937     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
938     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
939     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
940     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
941     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
942     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
943     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
944     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
945     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
946     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
947     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
948     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
949     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
950     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
951     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
952     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
953     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
954     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
955     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
956     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
957     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
958     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
959     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
960     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
961     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
962     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
963     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
964     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
965     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
966     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
967     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
968     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
969     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
970     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
971     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
972     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
973     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
974     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
975     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
976     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
977     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
978     { X86::VPORrr,            X86::VPORrm,             0 },
979     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
980     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
981     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
982     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
983     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
984     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
985     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
986     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
987     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
988     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
989     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
990     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
991     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
992     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
993     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
994     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
995     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
996     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
997     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
998     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
999     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1000     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1001     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1002     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1003     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1004     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1005     { X86::VPXORrr,           X86::VPXORrm,            0 },
1006     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1007     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1008     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1009     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1010     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1011     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1012     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1013     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1014     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1015     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1016     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1017     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1018     // AVX 256-bit foldable instructions
1019     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1020     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1021     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1022     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1023     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1024     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1025     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1026     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1027     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1028     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1029     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1030     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1031     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1032     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1033     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1034     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1035     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1036     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1037     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1038     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1039     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1040     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1041     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1042     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1043     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1044     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1045     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1046     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1047     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1048     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1049     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1050     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1051     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1052     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1053     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1054     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1055     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1056     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1057     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1058     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1059     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1060     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1061     // AVX2 foldable instructions
1062     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1063     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1064     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1065     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1066     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1067     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1068     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1069     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1070     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1071     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1072     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1073     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1074     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1075     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1076     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1077     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1078     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1079     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1080     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1081     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1082     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1083     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1084     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1085     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1086     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1087     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1088     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1089     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1090     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1091     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1092     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1093     { X86::VPERMPDYri,        X86::VPERMPDYmi,         0 },
1094     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1095     { X86::VPERMQYri,         X86::VPERMQYmi,          0 },
1096     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1097     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1098     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1099     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1100     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1101     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1102     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1103     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1104     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1105     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1106     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1107     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1108     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1109     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1110     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1111     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1112     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1113     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1114     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1115     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1116     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1117     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1118     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1119     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1120     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1121     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1122     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1123     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1124     { X86::VPORYrr,           X86::VPORYrm,            0 },
1125     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1126     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1127     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1128     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1129     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1130     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1131     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1132     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1133     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1134     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1135     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1136     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1137     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1138     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1139     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1140     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1141     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1142     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1143     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1144     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1145     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1146     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1147     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1148     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1149     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1150     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1151     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1152     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1153     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1154     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1155     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1156     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1157     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1158     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1159     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1160     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1161     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1162     // FIXME: add AVX 256-bit foldable instructions
1163 
1164     // FMA4 foldable patterns
1165     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0           },
1166     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0           },
1167     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_16 },
1168     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_16 },
1169     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_32 },
1170     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_32 },
1171     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0           },
1172     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0           },
1173     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_16 },
1174     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_16 },
1175     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_32 },
1176     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_32 },
1177     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0           },
1178     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0           },
1179     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_16 },
1180     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_16 },
1181     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_32 },
1182     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_32 },
1183     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0           },
1184     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0           },
1185     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_16 },
1186     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_16 },
1187     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_32 },
1188     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_32 },
1189     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_16 },
1190     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_16 },
1191     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_32 },
1192     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_32 },
1193     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_16 },
1194     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_16 },
1195     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_32 },
1196     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_32 },
1197 
1198     // BMI/BMI2 foldable instructions
1199     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1200     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1201     { X86::MULX32rr,          X86::MULX32rm,            0 },
1202     { X86::MULX64rr,          X86::MULX64rm,            0 },
1203     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1204     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1205     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1206     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1207 
1208     // AVX-512 foldable instructions
1209     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1210     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1211     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1212     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1213     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1214     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1215     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1216     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1217     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1218     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1219     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1220     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1221     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1222     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1223     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1224     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1225     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1226     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1227     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1228     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1229     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1230     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1231     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1232     { X86::VALIGNQrri,        X86::VALIGNQrmi,          0 },
1233     { X86::VALIGNDrri,        X86::VALIGNDrmi,          0 },
1234 
1235     // AES foldable instructions
1236     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1237     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1238     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1239     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1240     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       TB_ALIGN_16 },
1241     { X86::VAESDECrr,         X86::VAESDECrm,           TB_ALIGN_16 },
1242     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       TB_ALIGN_16 },
1243     { X86::VAESENCrr,         X86::VAESENCrm,           TB_ALIGN_16 },
1244 
1245     // SHA foldable instructions
1246     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1247     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1248     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1249     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1250     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1251     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1252     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 },
1253   };
1254 
1255   for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1256     unsigned RegOp = OpTbl2[i].RegOp;
1257     unsigned MemOp = OpTbl2[i].MemOp;
1258     unsigned Flags = OpTbl2[i].Flags;
1259     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1260                   RegOp, MemOp,
1261                   // Index 2, folded load
1262                   Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1263   }
1264 
1265   static const X86OpTblEntry OpTbl3[] = {
1266     // FMA foldable instructions
1267     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         0 },
1268     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         0 },
1269     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         0 },
1270     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         0 },
1271     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         0 },
1272     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         0 },
1273     { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     0 },
1274     { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     0 },
1275 
1276     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_16 },
1277     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_16 },
1278     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_16 },
1279     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_16 },
1280     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_16 },
1281     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_16 },
1282     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_32 },
1283     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_32 },
1284     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_32 },
1285     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_32 },
1286     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_32 },
1287     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_32 },
1288 
1289     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        0 },
1290     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        0 },
1291     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        0 },
1292     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        0 },
1293     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        0 },
1294     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        0 },
1295     { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    0 },
1296     { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    0 },
1297 
1298     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_16 },
1299     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_16 },
1300     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_16 },
1301     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_16 },
1302     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_16 },
1303     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_16 },
1304     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_32 },
1305     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_32 },
1306     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_32 },
1307     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_32 },
1308     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_32 },
1309     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_32 },
1310 
1311     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         0 },
1312     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         0 },
1313     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         0 },
1314     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         0 },
1315     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         0 },
1316     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         0 },
1317     { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     0 },
1318     { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     0 },
1319 
1320     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_16 },
1321     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_16 },
1322     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_16 },
1323     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_16 },
1324     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_16 },
1325     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_16 },
1326     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_32 },
1327     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_32 },
1328     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_32 },
1329     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_32 },
1330     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_32 },
1331     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_32 },
1332 
1333     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        0 },
1334     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        0 },
1335     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        0 },
1336     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        0 },
1337     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        0 },
1338     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        0 },
1339     { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    0 },
1340     { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    0 },
1341 
1342     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_16 },
1343     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_16 },
1344     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_16 },
1345     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_16 },
1346     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_16 },
1347     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_16 },
1348     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_32 },
1349     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_32 },
1350     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_32 },
1351     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_32 },
1352     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_32 },
1353     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_32 },
1354 
1355     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_16 },
1356     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_16 },
1357     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_16 },
1358     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_16 },
1359     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_16 },
1360     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_16 },
1361     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_32 },
1362     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_32 },
1363     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_32 },
1364     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_32 },
1365     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_32 },
1366     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_32 },
1367 
1368     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_16 },
1369     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_16 },
1370     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_16 },
1371     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_16 },
1372     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_16 },
1373     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_16 },
1374     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_32 },
1375     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_32 },
1376     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_32 },
1377     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_32 },
1378     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_32 },
1379     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_32 },
1380 
1381     // FMA4 foldable patterns
1382     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1383     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1384     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1385     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1386     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1387     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1388     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1389     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1390     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1391     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1392     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1393     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1394     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1395     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1396     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1397     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1398     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1399     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1400     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1401     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1402     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1403     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1404     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1405     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1406     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1407     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1408     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1409     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1410     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1411     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1412     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1413     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1414     // AVX-512 VPERMI instructions with 3 source operands.
1415     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1416     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1417     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1418     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1419   };
1420 
1421   for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1422     unsigned RegOp = OpTbl3[i].RegOp;
1423     unsigned MemOp = OpTbl3[i].MemOp;
1424     unsigned Flags = OpTbl3[i].Flags;
1425     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1426                   RegOp, MemOp,
1427                   // Index 3, folded load
1428                   Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1429   }
1430 
1431 }
1432 
1433 void
1434 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1435                             MemOp2RegOpTableType &M2RTable,
1436                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
1437     if ((Flags & TB_NO_FORWARD) == 0) {
1438       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1439       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1440     }
1441     if ((Flags & TB_NO_REVERSE) == 0) {
1442       assert(!M2RTable.count(MemOp) &&
1443            "Duplicated entries in unfolding maps?");
1444       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1445     }
1446 }
1447 
1448 bool
1449 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1450                                     unsigned &SrcReg, unsigned &DstReg,
1451                                     unsigned &SubIdx) const {
1452   switch (MI.getOpcode()) {
1453   default: break;
1454   case X86::MOVSX16rr8:
1455   case X86::MOVZX16rr8:
1456   case X86::MOVSX32rr8:
1457   case X86::MOVZX32rr8:
1458   case X86::MOVSX64rr8:
1459     if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1460       // It's not always legal to reference the low 8-bit of the larger
1461       // register in 32-bit mode.
1462       return false;
1463   case X86::MOVSX32rr16:
1464   case X86::MOVZX32rr16:
1465   case X86::MOVSX64rr16:
1466   case X86::MOVSX64rr32: {
1467     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1468       // Be conservative.
1469       return false;
1470     SrcReg = MI.getOperand(1).getReg();
1471     DstReg = MI.getOperand(0).getReg();
1472     switch (MI.getOpcode()) {
1473     default: llvm_unreachable("Unreachable!");
1474     case X86::MOVSX16rr8:
1475     case X86::MOVZX16rr8:
1476     case X86::MOVSX32rr8:
1477     case X86::MOVZX32rr8:
1478     case X86::MOVSX64rr8:
1479       SubIdx = X86::sub_8bit;
1480       break;
1481     case X86::MOVSX32rr16:
1482     case X86::MOVZX32rr16:
1483     case X86::MOVSX64rr16:
1484       SubIdx = X86::sub_16bit;
1485       break;
1486     case X86::MOVSX64rr32:
1487       SubIdx = X86::sub_32bit;
1488       break;
1489     }
1490     return true;
1491   }
1492   }
1493   return false;
1494 }
1495 
1496 /// isFrameOperand - Return true and the FrameIndex if the specified
1497 /// operand and follow operands form a reference to the stack frame.
1498 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1499                                   int &FrameIndex) const {
1500   if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1501       MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1502       MI->getOperand(Op+1).getImm() == 1 &&
1503       MI->getOperand(Op+2).getReg() == 0 &&
1504       MI->getOperand(Op+3).getImm() == 0) {
1505     FrameIndex = MI->getOperand(Op).getIndex();
1506     return true;
1507   }
1508   return false;
1509 }
1510 
1511 static bool isFrameLoadOpcode(int Opcode) {
1512   switch (Opcode) {
1513   default:
1514     return false;
1515   case X86::MOV8rm:
1516   case X86::MOV16rm:
1517   case X86::MOV32rm:
1518   case X86::MOV64rm:
1519   case X86::LD_Fp64m:
1520   case X86::MOVSSrm:
1521   case X86::MOVSDrm:
1522   case X86::MOVAPSrm:
1523   case X86::MOVAPDrm:
1524   case X86::MOVDQArm:
1525   case X86::VMOVSSrm:
1526   case X86::VMOVSDrm:
1527   case X86::VMOVAPSrm:
1528   case X86::VMOVAPDrm:
1529   case X86::VMOVDQArm:
1530   case X86::VMOVAPSYrm:
1531   case X86::VMOVAPDYrm:
1532   case X86::VMOVDQAYrm:
1533   case X86::MMX_MOVD64rm:
1534   case X86::MMX_MOVQ64rm:
1535   case X86::VMOVDQA32rm:
1536   case X86::VMOVDQA64rm:
1537     return true;
1538   }
1539 }
1540 
1541 static bool isFrameStoreOpcode(int Opcode) {
1542   switch (Opcode) {
1543   default: break;
1544   case X86::MOV8mr:
1545   case X86::MOV16mr:
1546   case X86::MOV32mr:
1547   case X86::MOV64mr:
1548   case X86::ST_FpP64m:
1549   case X86::MOVSSmr:
1550   case X86::MOVSDmr:
1551   case X86::MOVAPSmr:
1552   case X86::MOVAPDmr:
1553   case X86::MOVDQAmr:
1554   case X86::VMOVSSmr:
1555   case X86::VMOVSDmr:
1556   case X86::VMOVAPSmr:
1557   case X86::VMOVAPDmr:
1558   case X86::VMOVDQAmr:
1559   case X86::VMOVAPSYmr:
1560   case X86::VMOVAPDYmr:
1561   case X86::VMOVDQAYmr:
1562   case X86::MMX_MOVD64mr:
1563   case X86::MMX_MOVQ64mr:
1564   case X86::MMX_MOVNTQmr:
1565     return true;
1566   }
1567   return false;
1568 }
1569 
1570 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1571                                            int &FrameIndex) const {
1572   if (isFrameLoadOpcode(MI->getOpcode()))
1573     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1574       return MI->getOperand(0).getReg();
1575   return 0;
1576 }
1577 
1578 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1579                                                  int &FrameIndex) const {
1580   if (isFrameLoadOpcode(MI->getOpcode())) {
1581     unsigned Reg;
1582     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1583       return Reg;
1584     // Check for post-frame index elimination operations
1585     const MachineMemOperand *Dummy;
1586     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1587   }
1588   return 0;
1589 }
1590 
1591 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1592                                           int &FrameIndex) const {
1593   if (isFrameStoreOpcode(MI->getOpcode()))
1594     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1595         isFrameOperand(MI, 0, FrameIndex))
1596       return MI->getOperand(X86::AddrNumOperands).getReg();
1597   return 0;
1598 }
1599 
1600 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1601                                                 int &FrameIndex) const {
1602   if (isFrameStoreOpcode(MI->getOpcode())) {
1603     unsigned Reg;
1604     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1605       return Reg;
1606     // Check for post-frame index elimination operations
1607     const MachineMemOperand *Dummy;
1608     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1609   }
1610   return 0;
1611 }
1612 
1613 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1614 /// X86::MOVPC32r.
1615 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1616   // Don't waste compile time scanning use-def chains of physregs.
1617   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1618     return false;
1619   bool isPICBase = false;
1620   for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1621          E = MRI.def_end(); I != E; ++I) {
1622     MachineInstr *DefMI = I.getOperand().getParent();
1623     if (DefMI->getOpcode() != X86::MOVPC32r)
1624       return false;
1625     assert(!isPICBase && "More than one PIC base?");
1626     isPICBase = true;
1627   }
1628   return isPICBase;
1629 }
1630 
1631 bool
1632 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1633                                                 AliasAnalysis *AA) const {
1634   switch (MI->getOpcode()) {
1635   default: break;
1636   case X86::MOV8rm:
1637   case X86::MOV16rm:
1638   case X86::MOV32rm:
1639   case X86::MOV64rm:
1640   case X86::LD_Fp64m:
1641   case X86::MOVSSrm:
1642   case X86::MOVSDrm:
1643   case X86::MOVAPSrm:
1644   case X86::MOVUPSrm:
1645   case X86::MOVAPDrm:
1646   case X86::MOVDQArm:
1647   case X86::MOVDQUrm:
1648   case X86::VMOVSSrm:
1649   case X86::VMOVSDrm:
1650   case X86::VMOVAPSrm:
1651   case X86::VMOVUPSrm:
1652   case X86::VMOVAPDrm:
1653   case X86::VMOVDQArm:
1654   case X86::VMOVDQUrm:
1655   case X86::VMOVAPSYrm:
1656   case X86::VMOVUPSYrm:
1657   case X86::VMOVAPDYrm:
1658   case X86::VMOVDQAYrm:
1659   case X86::VMOVDQUYrm:
1660   case X86::MMX_MOVD64rm:
1661   case X86::MMX_MOVQ64rm:
1662   case X86::FsVMOVAPSrm:
1663   case X86::FsVMOVAPDrm:
1664   case X86::FsMOVAPSrm:
1665   case X86::FsMOVAPDrm: {
1666     // Loads from constant pools are trivially rematerializable.
1667     if (MI->getOperand(1).isReg() &&
1668         MI->getOperand(2).isImm() &&
1669         MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1670         MI->isInvariantLoad(AA)) {
1671       unsigned BaseReg = MI->getOperand(1).getReg();
1672       if (BaseReg == 0 || BaseReg == X86::RIP)
1673         return true;
1674       // Allow re-materialization of PIC load.
1675       if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1676         return false;
1677       const MachineFunction &MF = *MI->getParent()->getParent();
1678       const MachineRegisterInfo &MRI = MF.getRegInfo();
1679       return regIsPICBase(BaseReg, MRI);
1680     }
1681     return false;
1682   }
1683 
1684   case X86::LEA32r:
1685   case X86::LEA64r: {
1686     if (MI->getOperand(2).isImm() &&
1687         MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1688         !MI->getOperand(4).isReg()) {
1689       // lea fi#, lea GV, etc. are all rematerializable.
1690       if (!MI->getOperand(1).isReg())
1691         return true;
1692       unsigned BaseReg = MI->getOperand(1).getReg();
1693       if (BaseReg == 0)
1694         return true;
1695       // Allow re-materialization of lea PICBase + x.
1696       const MachineFunction &MF = *MI->getParent()->getParent();
1697       const MachineRegisterInfo &MRI = MF.getRegInfo();
1698       return regIsPICBase(BaseReg, MRI);
1699     }
1700     return false;
1701   }
1702   }
1703 
1704   // All other instructions marked M_REMATERIALIZABLE are always trivially
1705   // rematerializable.
1706   return true;
1707 }
1708 
1709 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1710 /// would clobber the EFLAGS condition register. Note the result may be
1711 /// conservative. If it cannot definitely determine the safety after visiting
1712 /// a few instructions in each direction it assumes it's not safe.
1713 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1714                                   MachineBasicBlock::iterator I) {
1715   MachineBasicBlock::iterator E = MBB.end();
1716 
1717   // For compile time consideration, if we are not able to determine the
1718   // safety after visiting 4 instructions in each direction, we will assume
1719   // it's not safe.
1720   MachineBasicBlock::iterator Iter = I;
1721   for (unsigned i = 0; Iter != E && i < 4; ++i) {
1722     bool SeenDef = false;
1723     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1724       MachineOperand &MO = Iter->getOperand(j);
1725       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1726         SeenDef = true;
1727       if (!MO.isReg())
1728         continue;
1729       if (MO.getReg() == X86::EFLAGS) {
1730         if (MO.isUse())
1731           return false;
1732         SeenDef = true;
1733       }
1734     }
1735 
1736     if (SeenDef)
1737       // This instruction defines EFLAGS, no need to look any further.
1738       return true;
1739     ++Iter;
1740     // Skip over DBG_VALUE.
1741     while (Iter != E && Iter->isDebugValue())
1742       ++Iter;
1743   }
1744 
1745   // It is safe to clobber EFLAGS at the end of a block of no successor has it
1746   // live in.
1747   if (Iter == E) {
1748     for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1749            SE = MBB.succ_end(); SI != SE; ++SI)
1750       if ((*SI)->isLiveIn(X86::EFLAGS))
1751         return false;
1752     return true;
1753   }
1754 
1755   MachineBasicBlock::iterator B = MBB.begin();
1756   Iter = I;
1757   for (unsigned i = 0; i < 4; ++i) {
1758     // If we make it to the beginning of the block, it's safe to clobber
1759     // EFLAGS iff EFLAGS is not live-in.
1760     if (Iter == B)
1761       return !MBB.isLiveIn(X86::EFLAGS);
1762 
1763     --Iter;
1764     // Skip over DBG_VALUE.
1765     while (Iter != B && Iter->isDebugValue())
1766       --Iter;
1767 
1768     bool SawKill = false;
1769     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1770       MachineOperand &MO = Iter->getOperand(j);
1771       // A register mask may clobber EFLAGS, but we should still look for a
1772       // live EFLAGS def.
1773       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1774         SawKill = true;
1775       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1776         if (MO.isDef()) return MO.isDead();
1777         if (MO.isKill()) SawKill = true;
1778       }
1779     }
1780 
1781     if (SawKill)
1782       // This instruction kills EFLAGS and doesn't redefine it, so
1783       // there's no need to look further.
1784       return true;
1785   }
1786 
1787   // Conservative answer.
1788   return false;
1789 }
1790 
1791 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1792                                  MachineBasicBlock::iterator I,
1793                                  unsigned DestReg, unsigned SubIdx,
1794                                  const MachineInstr *Orig,
1795                                  const TargetRegisterInfo &TRI) const {
1796   // MOV32r0 is implemented with a xor which clobbers condition code.
1797   // Re-materialize it as movri instructions to avoid side effects.
1798   unsigned Opc = Orig->getOpcode();
1799   if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
1800     DebugLoc DL = Orig->getDebugLoc();
1801     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
1802       .addImm(0);
1803   } else {
1804     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1805     MBB.insert(I, MI);
1806   }
1807 
1808   MachineInstr *NewMI = prior(I);
1809   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1810 }
1811 
1812 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1813 /// is not marked dead.
1814 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1815   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1816     MachineOperand &MO = MI->getOperand(i);
1817     if (MO.isReg() && MO.isDef() &&
1818         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1819       return true;
1820     }
1821   }
1822   return false;
1823 }
1824 
1825 /// getTruncatedShiftCount - check whether the shift count for a machine operand
1826 /// is non-zero.
1827 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
1828                                               unsigned ShiftAmtOperandIdx) {
1829   // The shift count is six bits with the REX.W prefix and five bits without.
1830   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1831   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
1832   return Imm & ShiftCountMask;
1833 }
1834 
1835 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
1836 /// can be represented by a LEA instruction.
1837 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1838   // Left shift instructions can be transformed into load-effective-address
1839   // instructions if we can encode them appropriately.
1840   // A LEA instruction utilizes a SIB byte to encode it's scale factor.
1841   // The SIB.scale field is two bits wide which means that we can encode any
1842   // shift amount less than 4.
1843   return ShAmt < 4 && ShAmt > 0;
1844 }
1845 
1846 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
1847                                   unsigned Opc, bool AllowSP,
1848                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
1849                                   MachineOperand &ImplicitOp) const {
1850   MachineFunction &MF = *MI->getParent()->getParent();
1851   const TargetRegisterClass *RC;
1852   if (AllowSP) {
1853     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1854   } else {
1855     RC = Opc != X86::LEA32r ?
1856       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1857   }
1858   unsigned SrcReg = Src.getReg();
1859 
1860   // For both LEA64 and LEA32 the register already has essentially the right
1861   // type (32-bit or 64-bit) we may just need to forbid SP.
1862   if (Opc != X86::LEA64_32r) {
1863     NewSrc = SrcReg;
1864     isKill = Src.isKill();
1865     isUndef = Src.isUndef();
1866 
1867     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
1868         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1869       return false;
1870 
1871     return true;
1872   }
1873 
1874   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1875   // another we need to add 64-bit registers to the final MI.
1876   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1877     ImplicitOp = Src;
1878     ImplicitOp.setImplicit();
1879 
1880     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
1881     MachineBasicBlock::LivenessQueryResult LQR =
1882       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
1883 
1884     switch (LQR) {
1885     case MachineBasicBlock::LQR_Unknown:
1886       // We can't give sane liveness flags to the instruction, abandon LEA
1887       // formation.
1888       return false;
1889     case MachineBasicBlock::LQR_Live:
1890       isKill = MI->killsRegister(SrcReg);
1891       isUndef = false;
1892       break;
1893     default:
1894       // The physreg itself is dead, so we have to use it as an <undef>.
1895       isKill = false;
1896       isUndef = true;
1897       break;
1898     }
1899   } else {
1900     // Virtual register of the wrong class, we have to create a temporary 64-bit
1901     // vreg to feed into the LEA.
1902     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1903     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1904             get(TargetOpcode::COPY))
1905       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1906         .addOperand(Src);
1907 
1908     // Which is obviously going to be dead after we're done with it.
1909     isKill = true;
1910     isUndef = false;
1911   }
1912 
1913   // We've set all the parameters without issue.
1914   return true;
1915 }
1916 
1917 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1918 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1919 /// to a 32-bit superregister and then truncating back down to a 16-bit
1920 /// subregister.
1921 MachineInstr *
1922 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1923                                            MachineFunction::iterator &MFI,
1924                                            MachineBasicBlock::iterator &MBBI,
1925                                            LiveVariables *LV) const {
1926   MachineInstr *MI = MBBI;
1927   unsigned Dest = MI->getOperand(0).getReg();
1928   unsigned Src = MI->getOperand(1).getReg();
1929   bool isDead = MI->getOperand(0).isDead();
1930   bool isKill = MI->getOperand(1).isKill();
1931 
1932   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1933   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1934   unsigned Opc, leaInReg;
1935   if (TM.getSubtarget<X86Subtarget>().is64Bit()) {
1936     Opc = X86::LEA64_32r;
1937     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1938   } else {
1939     Opc = X86::LEA32r;
1940     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1941   }
1942 
1943   // Build and insert into an implicit UNDEF value. This is OK because
1944   // well be shifting and then extracting the lower 16-bits.
1945   // This has the potential to cause partial register stall. e.g.
1946   //   movw    (%rbp,%rcx,2), %dx
1947   //   leal    -65(%rdx), %esi
1948   // But testing has shown this *does* help performance in 64-bit mode (at
1949   // least on modern x86 machines).
1950   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1951   MachineInstr *InsMI =
1952     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1953     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1954     .addReg(Src, getKillRegState(isKill));
1955 
1956   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1957                                     get(Opc), leaOutReg);
1958   switch (MIOpc) {
1959   default: llvm_unreachable("Unreachable!");
1960   case X86::SHL16ri: {
1961     unsigned ShAmt = MI->getOperand(2).getImm();
1962     MIB.addReg(0).addImm(1 << ShAmt)
1963        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1964     break;
1965   }
1966   case X86::INC16r:
1967   case X86::INC64_16r:
1968     addRegOffset(MIB, leaInReg, true, 1);
1969     break;
1970   case X86::DEC16r:
1971   case X86::DEC64_16r:
1972     addRegOffset(MIB, leaInReg, true, -1);
1973     break;
1974   case X86::ADD16ri:
1975   case X86::ADD16ri8:
1976   case X86::ADD16ri_DB:
1977   case X86::ADD16ri8_DB:
1978     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1979     break;
1980   case X86::ADD16rr:
1981   case X86::ADD16rr_DB: {
1982     unsigned Src2 = MI->getOperand(2).getReg();
1983     bool isKill2 = MI->getOperand(2).isKill();
1984     unsigned leaInReg2 = 0;
1985     MachineInstr *InsMI2 = 0;
1986     if (Src == Src2) {
1987       // ADD16rr %reg1028<kill>, %reg1028
1988       // just a single insert_subreg.
1989       addRegReg(MIB, leaInReg, true, leaInReg, false);
1990     } else {
1991       if (TM.getSubtarget<X86Subtarget>().is64Bit())
1992         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1993       else
1994         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1995       // Build and insert into an implicit UNDEF value. This is OK because
1996       // well be shifting and then extracting the lower 16-bits.
1997       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1998       InsMI2 =
1999         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2000         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2001         .addReg(Src2, getKillRegState(isKill2));
2002       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2003     }
2004     if (LV && isKill2 && InsMI2)
2005       LV->replaceKillInstruction(Src2, MI, InsMI2);
2006     break;
2007   }
2008   }
2009 
2010   MachineInstr *NewMI = MIB;
2011   MachineInstr *ExtMI =
2012     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2013     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2014     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2015 
2016   if (LV) {
2017     // Update live variables
2018     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2019     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2020     if (isKill)
2021       LV->replaceKillInstruction(Src, MI, InsMI);
2022     if (isDead)
2023       LV->replaceKillInstruction(Dest, MI, ExtMI);
2024   }
2025 
2026   return ExtMI;
2027 }
2028 
2029 /// convertToThreeAddress - This method must be implemented by targets that
2030 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2031 /// may be able to convert a two-address instruction into a true
2032 /// three-address instruction on demand.  This allows the X86 target (for
2033 /// example) to convert ADD and SHL instructions into LEA instructions if they
2034 /// would require register copies due to two-addressness.
2035 ///
2036 /// This method returns a null pointer if the transformation cannot be
2037 /// performed, otherwise it returns the new instruction.
2038 ///
2039 MachineInstr *
2040 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2041                                     MachineBasicBlock::iterator &MBBI,
2042                                     LiveVariables *LV) const {
2043   MachineInstr *MI = MBBI;
2044 
2045   // The following opcodes also sets the condition code register(s). Only
2046   // convert them to equivalent lea if the condition code register def's
2047   // are dead!
2048   if (hasLiveCondCodeDef(MI))
2049     return 0;
2050 
2051   MachineFunction &MF = *MI->getParent()->getParent();
2052   // All instructions input are two-addr instructions.  Get the known operands.
2053   const MachineOperand &Dest = MI->getOperand(0);
2054   const MachineOperand &Src = MI->getOperand(1);
2055 
2056   MachineInstr *NewMI = NULL;
2057   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2058   // we have better subtarget support, enable the 16-bit LEA generation here.
2059   // 16-bit LEA is also slow on Core2.
2060   bool DisableLEA16 = true;
2061   bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2062 
2063   unsigned MIOpc = MI->getOpcode();
2064   switch (MIOpc) {
2065   case X86::SHUFPSrri: {
2066     assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
2067     if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
2068 
2069     unsigned B = MI->getOperand(1).getReg();
2070     unsigned C = MI->getOperand(2).getReg();
2071     if (B != C) return 0;
2072     unsigned M = MI->getOperand(3).getImm();
2073     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2074       .addOperand(Dest).addOperand(Src).addImm(M);
2075     break;
2076   }
2077   case X86::SHUFPDrri: {
2078     assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
2079     if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
2080 
2081     unsigned B = MI->getOperand(1).getReg();
2082     unsigned C = MI->getOperand(2).getReg();
2083     if (B != C) return 0;
2084     unsigned M = MI->getOperand(3).getImm();
2085 
2086     // Convert to PSHUFD mask.
2087     M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
2088 
2089     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2090       .addOperand(Dest).addOperand(Src).addImm(M);
2091     break;
2092   }
2093   case X86::SHL64ri: {
2094     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2095     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2096     if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2097 
2098     // LEA can't handle RSP.
2099     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2100         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2101                                            &X86::GR64_NOSPRegClass))
2102       return 0;
2103 
2104     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2105       .addOperand(Dest)
2106       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2107     break;
2108   }
2109   case X86::SHL32ri: {
2110     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2111     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2112     if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2113 
2114     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2115 
2116     // LEA can't handle ESP.
2117     bool isKill, isUndef;
2118     unsigned SrcReg;
2119     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2120     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2121                         SrcReg, isKill, isUndef, ImplicitOp))
2122       return 0;
2123 
2124     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2125       .addOperand(Dest)
2126       .addReg(0).addImm(1 << ShAmt)
2127       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2128       .addImm(0).addReg(0);
2129     if (ImplicitOp.getReg() != 0)
2130       MIB.addOperand(ImplicitOp);
2131     NewMI = MIB;
2132 
2133     break;
2134   }
2135   case X86::SHL16ri: {
2136     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2137     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2138     if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2139 
2140     if (DisableLEA16)
2141       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2142     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2143       .addOperand(Dest)
2144       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2145     break;
2146   }
2147   default: {
2148 
2149     switch (MIOpc) {
2150     default: return 0;
2151     case X86::INC64r:
2152     case X86::INC32r:
2153     case X86::INC64_32r: {
2154       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2155       unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2156         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2157       bool isKill, isUndef;
2158       unsigned SrcReg;
2159       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2160       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2161                           SrcReg, isKill, isUndef, ImplicitOp))
2162         return 0;
2163 
2164       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2165           .addOperand(Dest)
2166           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2167       if (ImplicitOp.getReg() != 0)
2168         MIB.addOperand(ImplicitOp);
2169 
2170       NewMI = addOffset(MIB, 1);
2171       break;
2172     }
2173     case X86::INC16r:
2174     case X86::INC64_16r:
2175       if (DisableLEA16)
2176         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2177       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2178       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2179                         .addOperand(Dest).addOperand(Src), 1);
2180       break;
2181     case X86::DEC64r:
2182     case X86::DEC32r:
2183     case X86::DEC64_32r: {
2184       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2185       unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2186         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2187 
2188       bool isKill, isUndef;
2189       unsigned SrcReg;
2190       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2191       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2192                           SrcReg, isKill, isUndef, ImplicitOp))
2193         return 0;
2194 
2195       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2196           .addOperand(Dest)
2197           .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2198       if (ImplicitOp.getReg() != 0)
2199         MIB.addOperand(ImplicitOp);
2200 
2201       NewMI = addOffset(MIB, -1);
2202 
2203       break;
2204     }
2205     case X86::DEC16r:
2206     case X86::DEC64_16r:
2207       if (DisableLEA16)
2208         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2209       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2210       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2211                         .addOperand(Dest).addOperand(Src), -1);
2212       break;
2213     case X86::ADD64rr:
2214     case X86::ADD64rr_DB:
2215     case X86::ADD32rr:
2216     case X86::ADD32rr_DB: {
2217       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2218       unsigned Opc;
2219       if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2220         Opc = X86::LEA64r;
2221       else
2222         Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2223 
2224       bool isKill, isUndef;
2225       unsigned SrcReg;
2226       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2227       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2228                           SrcReg, isKill, isUndef, ImplicitOp))
2229         return 0;
2230 
2231       const MachineOperand &Src2 = MI->getOperand(2);
2232       bool isKill2, isUndef2;
2233       unsigned SrcReg2;
2234       MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2235       if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2236                           SrcReg2, isKill2, isUndef2, ImplicitOp2))
2237         return 0;
2238 
2239       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2240         .addOperand(Dest);
2241       if (ImplicitOp.getReg() != 0)
2242         MIB.addOperand(ImplicitOp);
2243       if (ImplicitOp2.getReg() != 0)
2244         MIB.addOperand(ImplicitOp2);
2245 
2246       NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2247 
2248       // Preserve undefness of the operands.
2249       NewMI->getOperand(1).setIsUndef(isUndef);
2250       NewMI->getOperand(3).setIsUndef(isUndef2);
2251 
2252       if (LV && Src2.isKill())
2253         LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2254       break;
2255     }
2256     case X86::ADD16rr:
2257     case X86::ADD16rr_DB: {
2258       if (DisableLEA16)
2259         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2260       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2261       unsigned Src2 = MI->getOperand(2).getReg();
2262       bool isKill2 = MI->getOperand(2).isKill();
2263       NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2264                         .addOperand(Dest),
2265                         Src.getReg(), Src.isKill(), Src2, isKill2);
2266 
2267       // Preserve undefness of the operands.
2268       bool isUndef = MI->getOperand(1).isUndef();
2269       bool isUndef2 = MI->getOperand(2).isUndef();
2270       NewMI->getOperand(1).setIsUndef(isUndef);
2271       NewMI->getOperand(3).setIsUndef(isUndef2);
2272 
2273       if (LV && isKill2)
2274         LV->replaceKillInstruction(Src2, MI, NewMI);
2275       break;
2276     }
2277     case X86::ADD64ri32:
2278     case X86::ADD64ri8:
2279     case X86::ADD64ri32_DB:
2280     case X86::ADD64ri8_DB:
2281       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2282       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2283                         .addOperand(Dest).addOperand(Src),
2284                         MI->getOperand(2).getImm());
2285       break;
2286     case X86::ADD32ri:
2287     case X86::ADD32ri8:
2288     case X86::ADD32ri_DB:
2289     case X86::ADD32ri8_DB: {
2290       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2291       unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2292 
2293       bool isKill, isUndef;
2294       unsigned SrcReg;
2295       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2296       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2297                           SrcReg, isKill, isUndef, ImplicitOp))
2298         return 0;
2299 
2300       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2301           .addOperand(Dest)
2302           .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2303       if (ImplicitOp.getReg() != 0)
2304         MIB.addOperand(ImplicitOp);
2305 
2306       NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2307       break;
2308     }
2309     case X86::ADD16ri:
2310     case X86::ADD16ri8:
2311     case X86::ADD16ri_DB:
2312     case X86::ADD16ri8_DB:
2313       if (DisableLEA16)
2314         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2315       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2316       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2317                         .addOperand(Dest).addOperand(Src),
2318                         MI->getOperand(2).getImm());
2319       break;
2320     }
2321   }
2322   }
2323 
2324   if (!NewMI) return 0;
2325 
2326   if (LV) {  // Update live variables
2327     if (Src.isKill())
2328       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2329     if (Dest.isDead())
2330       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2331   }
2332 
2333   MFI->insert(MBBI, NewMI);          // Insert the new inst
2334   return NewMI;
2335 }
2336 
2337 /// commuteInstruction - We have a few instructions that must be hacked on to
2338 /// commute them.
2339 ///
2340 MachineInstr *
2341 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2342   switch (MI->getOpcode()) {
2343   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2344   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2345   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2346   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2347   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2348   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2349     unsigned Opc;
2350     unsigned Size;
2351     switch (MI->getOpcode()) {
2352     default: llvm_unreachable("Unreachable!");
2353     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2354     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2355     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2356     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2357     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2358     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2359     }
2360     unsigned Amt = MI->getOperand(3).getImm();
2361     if (NewMI) {
2362       MachineFunction &MF = *MI->getParent()->getParent();
2363       MI = MF.CloneMachineInstr(MI);
2364       NewMI = false;
2365     }
2366     MI->setDesc(get(Opc));
2367     MI->getOperand(3).setImm(Size-Amt);
2368     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2369   }
2370   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
2371   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2372   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
2373   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2374   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2375   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
2376   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
2377   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2378   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2379   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
2380   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
2381   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2382   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
2383   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2384   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
2385   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2386     unsigned Opc;
2387     switch (MI->getOpcode()) {
2388     default: llvm_unreachable("Unreachable!");
2389     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2390     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2391     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2392     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2393     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2394     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2395     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2396     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2397     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2398     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2399     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2400     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2401     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2402     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2403     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2404     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2405     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2406     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2407     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2408     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2409     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2410     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2411     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2412     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2413     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2414     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2415     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2416     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2417     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2418     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2419     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2420     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2421     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2422     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2423     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2424     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2425     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2426     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2427     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2428     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2429     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2430     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2431     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2432     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2433     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2434     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2435     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2436     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2437     }
2438     if (NewMI) {
2439       MachineFunction &MF = *MI->getParent()->getParent();
2440       MI = MF.CloneMachineInstr(MI);
2441       NewMI = false;
2442     }
2443     MI->setDesc(get(Opc));
2444     // Fallthrough intended.
2445   }
2446   default:
2447     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2448   }
2449 }
2450 
2451 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2452   switch (BrOpc) {
2453   default: return X86::COND_INVALID;
2454   case X86::JE_4:  return X86::COND_E;
2455   case X86::JNE_4: return X86::COND_NE;
2456   case X86::JL_4:  return X86::COND_L;
2457   case X86::JLE_4: return X86::COND_LE;
2458   case X86::JG_4:  return X86::COND_G;
2459   case X86::JGE_4: return X86::COND_GE;
2460   case X86::JB_4:  return X86::COND_B;
2461   case X86::JBE_4: return X86::COND_BE;
2462   case X86::JA_4:  return X86::COND_A;
2463   case X86::JAE_4: return X86::COND_AE;
2464   case X86::JS_4:  return X86::COND_S;
2465   case X86::JNS_4: return X86::COND_NS;
2466   case X86::JP_4:  return X86::COND_P;
2467   case X86::JNP_4: return X86::COND_NP;
2468   case X86::JO_4:  return X86::COND_O;
2469   case X86::JNO_4: return X86::COND_NO;
2470   }
2471 }
2472 
2473 /// getCondFromSETOpc - return condition code of a SET opcode.
2474 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2475   switch (Opc) {
2476   default: return X86::COND_INVALID;
2477   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
2478   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2479   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
2480   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2481   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
2482   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
2483   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2484   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
2485   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2486   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2487   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2488   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2489   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2490   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
2491   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
2492   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
2493   }
2494 }
2495 
2496 /// getCondFromCmovOpc - return condition code of a CMov opcode.
2497 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2498   switch (Opc) {
2499   default: return X86::COND_INVALID;
2500   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
2501   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
2502     return X86::COND_A;
2503   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2504   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2505     return X86::COND_AE;
2506   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
2507   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
2508     return X86::COND_B;
2509   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2510   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2511     return X86::COND_BE;
2512   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
2513   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
2514     return X86::COND_E;
2515   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
2516   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
2517     return X86::COND_G;
2518   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2519   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2520     return X86::COND_GE;
2521   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
2522   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
2523     return X86::COND_L;
2524   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2525   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2526     return X86::COND_LE;
2527   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2528   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2529     return X86::COND_NE;
2530   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2531   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2532     return X86::COND_NO;
2533   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2534   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2535     return X86::COND_NP;
2536   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2537   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2538     return X86::COND_NS;
2539   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
2540   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
2541     return X86::COND_O;
2542   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
2543   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
2544     return X86::COND_P;
2545   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
2546   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
2547     return X86::COND_S;
2548   }
2549 }
2550 
2551 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2552   switch (CC) {
2553   default: llvm_unreachable("Illegal condition code!");
2554   case X86::COND_E:  return X86::JE_4;
2555   case X86::COND_NE: return X86::JNE_4;
2556   case X86::COND_L:  return X86::JL_4;
2557   case X86::COND_LE: return X86::JLE_4;
2558   case X86::COND_G:  return X86::JG_4;
2559   case X86::COND_GE: return X86::JGE_4;
2560   case X86::COND_B:  return X86::JB_4;
2561   case X86::COND_BE: return X86::JBE_4;
2562   case X86::COND_A:  return X86::JA_4;
2563   case X86::COND_AE: return X86::JAE_4;
2564   case X86::COND_S:  return X86::JS_4;
2565   case X86::COND_NS: return X86::JNS_4;
2566   case X86::COND_P:  return X86::JP_4;
2567   case X86::COND_NP: return X86::JNP_4;
2568   case X86::COND_O:  return X86::JO_4;
2569   case X86::COND_NO: return X86::JNO_4;
2570   }
2571 }
2572 
2573 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2574 /// e.g. turning COND_E to COND_NE.
2575 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2576   switch (CC) {
2577   default: llvm_unreachable("Illegal condition code!");
2578   case X86::COND_E:  return X86::COND_NE;
2579   case X86::COND_NE: return X86::COND_E;
2580   case X86::COND_L:  return X86::COND_GE;
2581   case X86::COND_LE: return X86::COND_G;
2582   case X86::COND_G:  return X86::COND_LE;
2583   case X86::COND_GE: return X86::COND_L;
2584   case X86::COND_B:  return X86::COND_AE;
2585   case X86::COND_BE: return X86::COND_A;
2586   case X86::COND_A:  return X86::COND_BE;
2587   case X86::COND_AE: return X86::COND_B;
2588   case X86::COND_S:  return X86::COND_NS;
2589   case X86::COND_NS: return X86::COND_S;
2590   case X86::COND_P:  return X86::COND_NP;
2591   case X86::COND_NP: return X86::COND_P;
2592   case X86::COND_O:  return X86::COND_NO;
2593   case X86::COND_NO: return X86::COND_O;
2594   }
2595 }
2596 
2597 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2598 /// the condition code if we modify the instructions such that flags are
2599 /// set by MI(b,a).
2600 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2601   switch (CC) {
2602   default: return X86::COND_INVALID;
2603   case X86::COND_E:  return X86::COND_E;
2604   case X86::COND_NE: return X86::COND_NE;
2605   case X86::COND_L:  return X86::COND_G;
2606   case X86::COND_LE: return X86::COND_GE;
2607   case X86::COND_G:  return X86::COND_L;
2608   case X86::COND_GE: return X86::COND_LE;
2609   case X86::COND_B:  return X86::COND_A;
2610   case X86::COND_BE: return X86::COND_AE;
2611   case X86::COND_A:  return X86::COND_B;
2612   case X86::COND_AE: return X86::COND_BE;
2613   }
2614 }
2615 
2616 /// getSETFromCond - Return a set opcode for the given condition and
2617 /// whether it has memory operand.
2618 static unsigned getSETFromCond(X86::CondCode CC,
2619                                bool HasMemoryOperand) {
2620   static const uint16_t Opc[16][2] = {
2621     { X86::SETAr,  X86::SETAm  },
2622     { X86::SETAEr, X86::SETAEm },
2623     { X86::SETBr,  X86::SETBm  },
2624     { X86::SETBEr, X86::SETBEm },
2625     { X86::SETEr,  X86::SETEm  },
2626     { X86::SETGr,  X86::SETGm  },
2627     { X86::SETGEr, X86::SETGEm },
2628     { X86::SETLr,  X86::SETLm  },
2629     { X86::SETLEr, X86::SETLEm },
2630     { X86::SETNEr, X86::SETNEm },
2631     { X86::SETNOr, X86::SETNOm },
2632     { X86::SETNPr, X86::SETNPm },
2633     { X86::SETNSr, X86::SETNSm },
2634     { X86::SETOr,  X86::SETOm  },
2635     { X86::SETPr,  X86::SETPm  },
2636     { X86::SETSr,  X86::SETSm  }
2637   };
2638 
2639   assert(CC < 16 && "Can only handle standard cond codes");
2640   return Opc[CC][HasMemoryOperand ? 1 : 0];
2641 }
2642 
2643 /// getCMovFromCond - Return a cmov opcode for the given condition,
2644 /// register size in bytes, and operand type.
2645 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes,
2646                                 bool HasMemoryOperand) {
2647   static const uint16_t Opc[32][3] = {
2648     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
2649     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2650     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
2651     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2652     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
2653     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
2654     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2655     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
2656     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2657     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2658     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2659     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2660     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2661     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
2662     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
2663     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
2664     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
2665     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2666     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
2667     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2668     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
2669     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
2670     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2671     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
2672     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2673     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2674     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2675     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2676     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2677     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
2678     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
2679     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
2680   };
2681 
2682   assert(CC < 16 && "Can only handle standard cond codes");
2683   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2684   switch(RegBytes) {
2685   default: llvm_unreachable("Illegal register size!");
2686   case 2: return Opc[Idx][0];
2687   case 4: return Opc[Idx][1];
2688   case 8: return Opc[Idx][2];
2689   }
2690 }
2691 
2692 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2693   if (!MI->isTerminator()) return false;
2694 
2695   // Conditional branch is a special case.
2696   if (MI->isBranch() && !MI->isBarrier())
2697     return true;
2698   if (!MI->isPredicable())
2699     return true;
2700   return !isPredicated(MI);
2701 }
2702 
2703 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2704                                  MachineBasicBlock *&TBB,
2705                                  MachineBasicBlock *&FBB,
2706                                  SmallVectorImpl<MachineOperand> &Cond,
2707                                  bool AllowModify) const {
2708   // Start from the bottom of the block and work up, examining the
2709   // terminator instructions.
2710   MachineBasicBlock::iterator I = MBB.end();
2711   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2712   while (I != MBB.begin()) {
2713     --I;
2714     if (I->isDebugValue())
2715       continue;
2716 
2717     // Working from the bottom, when we see a non-terminator instruction, we're
2718     // done.
2719     if (!isUnpredicatedTerminator(I))
2720       break;
2721 
2722     // A terminator that isn't a branch can't easily be handled by this
2723     // analysis.
2724     if (!I->isBranch())
2725       return true;
2726 
2727     // Handle unconditional branches.
2728     if (I->getOpcode() == X86::JMP_4) {
2729       UnCondBrIter = I;
2730 
2731       if (!AllowModify) {
2732         TBB = I->getOperand(0).getMBB();
2733         continue;
2734       }
2735 
2736       // If the block has any instructions after a JMP, delete them.
2737       while (llvm::next(I) != MBB.end())
2738         llvm::next(I)->eraseFromParent();
2739 
2740       Cond.clear();
2741       FBB = 0;
2742 
2743       // Delete the JMP if it's equivalent to a fall-through.
2744       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2745         TBB = 0;
2746         I->eraseFromParent();
2747         I = MBB.end();
2748         UnCondBrIter = MBB.end();
2749         continue;
2750       }
2751 
2752       // TBB is used to indicate the unconditional destination.
2753       TBB = I->getOperand(0).getMBB();
2754       continue;
2755     }
2756 
2757     // Handle conditional branches.
2758     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2759     if (BranchCode == X86::COND_INVALID)
2760       return true;  // Can't handle indirect branch.
2761 
2762     // Working from the bottom, handle the first conditional branch.
2763     if (Cond.empty()) {
2764       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2765       if (AllowModify && UnCondBrIter != MBB.end() &&
2766           MBB.isLayoutSuccessor(TargetBB)) {
2767         // If we can modify the code and it ends in something like:
2768         //
2769         //     jCC L1
2770         //     jmp L2
2771         //   L1:
2772         //     ...
2773         //   L2:
2774         //
2775         // Then we can change this to:
2776         //
2777         //     jnCC L2
2778         //   L1:
2779         //     ...
2780         //   L2:
2781         //
2782         // Which is a bit more efficient.
2783         // We conditionally jump to the fall-through block.
2784         BranchCode = GetOppositeBranchCondition(BranchCode);
2785         unsigned JNCC = GetCondBranchFromCond(BranchCode);
2786         MachineBasicBlock::iterator OldInst = I;
2787 
2788         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2789           .addMBB(UnCondBrIter->getOperand(0).getMBB());
2790         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2791           .addMBB(TargetBB);
2792 
2793         OldInst->eraseFromParent();
2794         UnCondBrIter->eraseFromParent();
2795 
2796         // Restart the analysis.
2797         UnCondBrIter = MBB.end();
2798         I = MBB.end();
2799         continue;
2800       }
2801 
2802       FBB = TBB;
2803       TBB = I->getOperand(0).getMBB();
2804       Cond.push_back(MachineOperand::CreateImm(BranchCode));
2805       continue;
2806     }
2807 
2808     // Handle subsequent conditional branches. Only handle the case where all
2809     // conditional branches branch to the same destination and their condition
2810     // opcodes fit one of the special multi-branch idioms.
2811     assert(Cond.size() == 1);
2812     assert(TBB);
2813 
2814     // Only handle the case where all conditional branches branch to the same
2815     // destination.
2816     if (TBB != I->getOperand(0).getMBB())
2817       return true;
2818 
2819     // If the conditions are the same, we can leave them alone.
2820     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2821     if (OldBranchCode == BranchCode)
2822       continue;
2823 
2824     // If they differ, see if they fit one of the known patterns. Theoretically,
2825     // we could handle more patterns here, but we shouldn't expect to see them
2826     // if instruction selection has done a reasonable job.
2827     if ((OldBranchCode == X86::COND_NP &&
2828          BranchCode == X86::COND_E) ||
2829         (OldBranchCode == X86::COND_E &&
2830          BranchCode == X86::COND_NP))
2831       BranchCode = X86::COND_NP_OR_E;
2832     else if ((OldBranchCode == X86::COND_P &&
2833               BranchCode == X86::COND_NE) ||
2834              (OldBranchCode == X86::COND_NE &&
2835               BranchCode == X86::COND_P))
2836       BranchCode = X86::COND_NE_OR_P;
2837     else
2838       return true;
2839 
2840     // Update the MachineOperand.
2841     Cond[0].setImm(BranchCode);
2842   }
2843 
2844   return false;
2845 }
2846 
2847 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2848   MachineBasicBlock::iterator I = MBB.end();
2849   unsigned Count = 0;
2850 
2851   while (I != MBB.begin()) {
2852     --I;
2853     if (I->isDebugValue())
2854       continue;
2855     if (I->getOpcode() != X86::JMP_4 &&
2856         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2857       break;
2858     // Remove the branch.
2859     I->eraseFromParent();
2860     I = MBB.end();
2861     ++Count;
2862   }
2863 
2864   return Count;
2865 }
2866 
2867 unsigned
2868 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2869                            MachineBasicBlock *FBB,
2870                            const SmallVectorImpl<MachineOperand> &Cond,
2871                            DebugLoc DL) const {
2872   // Shouldn't be a fall through.
2873   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2874   assert((Cond.size() == 1 || Cond.size() == 0) &&
2875          "X86 branch conditions have one component!");
2876 
2877   if (Cond.empty()) {
2878     // Unconditional branch?
2879     assert(!FBB && "Unconditional branch with multiple successors!");
2880     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2881     return 1;
2882   }
2883 
2884   // Conditional branch.
2885   unsigned Count = 0;
2886   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2887   switch (CC) {
2888   case X86::COND_NP_OR_E:
2889     // Synthesize NP_OR_E with two branches.
2890     BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2891     ++Count;
2892     BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2893     ++Count;
2894     break;
2895   case X86::COND_NE_OR_P:
2896     // Synthesize NE_OR_P with two branches.
2897     BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2898     ++Count;
2899     BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2900     ++Count;
2901     break;
2902   default: {
2903     unsigned Opc = GetCondBranchFromCond(CC);
2904     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2905     ++Count;
2906   }
2907   }
2908   if (FBB) {
2909     // Two-way Conditional branch. Insert the second branch.
2910     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2911     ++Count;
2912   }
2913   return Count;
2914 }
2915 
2916 bool X86InstrInfo::
2917 canInsertSelect(const MachineBasicBlock &MBB,
2918                 const SmallVectorImpl<MachineOperand> &Cond,
2919                 unsigned TrueReg, unsigned FalseReg,
2920                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2921   // Not all subtargets have cmov instructions.
2922   if (!TM.getSubtarget<X86Subtarget>().hasCMov())
2923     return false;
2924   if (Cond.size() != 1)
2925     return false;
2926   // We cannot do the composite conditions, at least not in SSA form.
2927   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2928     return false;
2929 
2930   // Check register classes.
2931   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2932   const TargetRegisterClass *RC =
2933     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2934   if (!RC)
2935     return false;
2936 
2937   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2938   if (X86::GR16RegClass.hasSubClassEq(RC) ||
2939       X86::GR32RegClass.hasSubClassEq(RC) ||
2940       X86::GR64RegClass.hasSubClassEq(RC)) {
2941     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2942     // Bridge. Probably Ivy Bridge as well.
2943     CondCycles = 2;
2944     TrueCycles = 2;
2945     FalseCycles = 2;
2946     return true;
2947   }
2948 
2949   // Can't do vectors.
2950   return false;
2951 }
2952 
2953 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2954                                 MachineBasicBlock::iterator I, DebugLoc DL,
2955                                 unsigned DstReg,
2956                                 const SmallVectorImpl<MachineOperand> &Cond,
2957                                 unsigned TrueReg, unsigned FalseReg) const {
2958    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2959    assert(Cond.size() == 1 && "Invalid Cond array");
2960    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
2961                                   MRI.getRegClass(DstReg)->getSize(),
2962                                   false/*HasMemoryOperand*/);
2963    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
2964 }
2965 
2966 /// isHReg - Test if the given register is a physical h register.
2967 static bool isHReg(unsigned Reg) {
2968   return X86::GR8_ABCD_HRegClass.contains(Reg);
2969 }
2970 
2971 // Try and copy between VR128/VR64 and GR64 registers.
2972 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2973                                         const X86Subtarget& Subtarget) {
2974 
2975 
2976   // SrcReg(VR128) -> DestReg(GR64)
2977   // SrcReg(VR64)  -> DestReg(GR64)
2978   // SrcReg(GR64)  -> DestReg(VR128)
2979   // SrcReg(GR64)  -> DestReg(VR64)
2980 
2981   bool HasAVX = Subtarget.hasAVX();
2982   bool HasAVX512 = Subtarget.hasAVX512();
2983   if (X86::GR64RegClass.contains(DestReg)) {
2984     if (X86::VR128XRegClass.contains(SrcReg))
2985       // Copy from a VR128 register to a GR64 register.
2986       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
2987                                                X86::MOVPQIto64rr);
2988     if (X86::VR64RegClass.contains(SrcReg))
2989       // Copy from a VR64 register to a GR64 register.
2990       return X86::MOVSDto64rr;
2991   } else if (X86::GR64RegClass.contains(SrcReg)) {
2992     // Copy from a GR64 register to a VR128 register.
2993     if (X86::VR128XRegClass.contains(DestReg))
2994       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
2995                                                X86::MOV64toPQIrr);
2996     // Copy from a GR64 register to a VR64 register.
2997     if (X86::VR64RegClass.contains(DestReg))
2998       return X86::MOV64toSDrr;
2999   }
3000 
3001   // SrcReg(FR32) -> DestReg(GR32)
3002   // SrcReg(GR32) -> DestReg(FR32)
3003 
3004   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3005     // Copy from a FR32 register to a GR32 register.
3006     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3007 
3008   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3009     // Copy from a GR32 register to a FR32 register.
3010     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3011   return 0;
3012 }
3013 
3014 static
3015 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3016   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3017       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3018       X86::VR512RegClass.contains(DestReg, SrcReg)) {
3019      DestReg = get512BitSuperRegister(DestReg);
3020      SrcReg = get512BitSuperRegister(SrcReg);
3021      return X86::VMOVAPSZrr;
3022   }
3023   if ((X86::VK8RegClass.contains(DestReg) ||
3024        X86::VK16RegClass.contains(DestReg)) &&
3025       (X86::VK8RegClass.contains(SrcReg) ||
3026        X86::VK16RegClass.contains(SrcReg)))
3027     return X86::KMOVWkk;
3028   return 0;
3029 }
3030 
3031 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3032                                MachineBasicBlock::iterator MI, DebugLoc DL,
3033                                unsigned DestReg, unsigned SrcReg,
3034                                bool KillSrc) const {
3035   // First deal with the normal symmetric copies.
3036   bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3037   bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
3038   unsigned Opc = 0;
3039   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3040     Opc = X86::MOV64rr;
3041   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3042     Opc = X86::MOV32rr;
3043   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3044     Opc = X86::MOV16rr;
3045   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3046     // Copying to or from a physical H register on x86-64 requires a NOREX
3047     // move.  Otherwise use a normal move.
3048     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3049         TM.getSubtarget<X86Subtarget>().is64Bit()) {
3050       Opc = X86::MOV8rr_NOREX;
3051       // Both operands must be encodable without an REX prefix.
3052       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3053              "8-bit H register can not be copied outside GR8_NOREX");
3054     } else
3055       Opc = X86::MOV8rr;
3056   }
3057   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3058     Opc = X86::MMX_MOVQ64rr;
3059   else if (HasAVX512)
3060     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3061   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3062     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3063   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3064     Opc = X86::VMOVAPSYrr;
3065   if (!Opc)
3066     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, TM.getSubtarget<X86Subtarget>());
3067 
3068   if (Opc) {
3069     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3070       .addReg(SrcReg, getKillRegState(KillSrc));
3071     return;
3072   }
3073 
3074   // Moving EFLAGS to / from another register requires a push and a pop.
3075   // Notice that we have to adjust the stack if we don't want to clobber the
3076   // first frame index. See X86FrameLowering.cpp - colobbersTheStack.
3077   if (SrcReg == X86::EFLAGS) {
3078     if (X86::GR64RegClass.contains(DestReg)) {
3079       BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3080       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3081       return;
3082     }
3083     if (X86::GR32RegClass.contains(DestReg)) {
3084       BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3085       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3086       return;
3087     }
3088   }
3089   if (DestReg == X86::EFLAGS) {
3090     if (X86::GR64RegClass.contains(SrcReg)) {
3091       BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3092         .addReg(SrcReg, getKillRegState(KillSrc));
3093       BuildMI(MBB, MI, DL, get(X86::POPF64));
3094       return;
3095     }
3096     if (X86::GR32RegClass.contains(SrcReg)) {
3097       BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3098         .addReg(SrcReg, getKillRegState(KillSrc));
3099       BuildMI(MBB, MI, DL, get(X86::POPF32));
3100       return;
3101     }
3102   }
3103 
3104   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3105                << " to " << RI.getName(DestReg) << '\n');
3106   llvm_unreachable("Cannot emit physreg copy instruction");
3107 }
3108 
3109 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3110                                       const TargetRegisterClass *RC,
3111                                       bool isStackAligned,
3112                                       const TargetMachine &TM,
3113                                       bool load) {
3114   if (TM.getSubtarget<X86Subtarget>().hasAVX512()) {
3115     if (X86::VK8RegClass.hasSubClassEq(RC)  ||
3116       X86::VK16RegClass.hasSubClassEq(RC))
3117       return load ? X86::KMOVWkm : X86::KMOVWmk;
3118     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3119       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3120     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3121       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3122     if (X86::VR512RegClass.hasSubClassEq(RC))
3123       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3124   }
3125 
3126   bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3127   switch (RC->getSize()) {
3128   default:
3129     llvm_unreachable("Unknown spill size");
3130   case 1:
3131     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3132     if (TM.getSubtarget<X86Subtarget>().is64Bit())
3133       // Copying to or from a physical H register on x86-64 requires a NOREX
3134       // move.  Otherwise use a normal move.
3135       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3136         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3137     return load ? X86::MOV8rm : X86::MOV8mr;
3138   case 2:
3139     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3140     return load ? X86::MOV16rm : X86::MOV16mr;
3141   case 4:
3142     if (X86::GR32RegClass.hasSubClassEq(RC))
3143       return load ? X86::MOV32rm : X86::MOV32mr;
3144     if (X86::FR32RegClass.hasSubClassEq(RC))
3145       return load ?
3146         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3147         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3148     if (X86::RFP32RegClass.hasSubClassEq(RC))
3149       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3150     llvm_unreachable("Unknown 4-byte regclass");
3151   case 8:
3152     if (X86::GR64RegClass.hasSubClassEq(RC))
3153       return load ? X86::MOV64rm : X86::MOV64mr;
3154     if (X86::FR64RegClass.hasSubClassEq(RC))
3155       return load ?
3156         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3157         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3158     if (X86::VR64RegClass.hasSubClassEq(RC))
3159       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3160     if (X86::RFP64RegClass.hasSubClassEq(RC))
3161       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3162     llvm_unreachable("Unknown 8-byte regclass");
3163   case 10:
3164     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3165     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3166   case 16: {
3167     assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
3168     // If stack is realigned we can use aligned stores.
3169     if (isStackAligned)
3170       return load ?
3171         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3172         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3173     else
3174       return load ?
3175         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3176         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3177   }
3178   case 32:
3179     assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3180     // If stack is realigned we can use aligned stores.
3181     if (isStackAligned)
3182       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3183     else
3184       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3185   case 64:
3186     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3187     if (isStackAligned)
3188       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3189     else
3190       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3191   }
3192 }
3193 
3194 static unsigned getStoreRegOpcode(unsigned SrcReg,
3195                                   const TargetRegisterClass *RC,
3196                                   bool isStackAligned,
3197                                   TargetMachine &TM) {
3198   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
3199 }
3200 
3201 
3202 static unsigned getLoadRegOpcode(unsigned DestReg,
3203                                  const TargetRegisterClass *RC,
3204                                  bool isStackAligned,
3205                                  const TargetMachine &TM) {
3206   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
3207 }
3208 
3209 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3210                                        MachineBasicBlock::iterator MI,
3211                                        unsigned SrcReg, bool isKill, int FrameIdx,
3212                                        const TargetRegisterClass *RC,
3213                                        const TargetRegisterInfo *TRI) const {
3214   const MachineFunction &MF = *MBB.getParent();
3215   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3216          "Stack slot too small for store");
3217   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3218   bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
3219     RI.canRealignStack(MF);
3220   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
3221   DebugLoc DL = MBB.findDebugLoc(MI);
3222   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3223     .addReg(SrcReg, getKillRegState(isKill));
3224 }
3225 
3226 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3227                                   bool isKill,
3228                                   SmallVectorImpl<MachineOperand> &Addr,
3229                                   const TargetRegisterClass *RC,
3230                                   MachineInstr::mmo_iterator MMOBegin,
3231                                   MachineInstr::mmo_iterator MMOEnd,
3232                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
3233   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3234   bool isAligned = MMOBegin != MMOEnd &&
3235                    (*MMOBegin)->getAlignment() >= Alignment;
3236   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
3237   DebugLoc DL;
3238   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3239   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3240     MIB.addOperand(Addr[i]);
3241   MIB.addReg(SrcReg, getKillRegState(isKill));
3242   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3243   NewMIs.push_back(MIB);
3244 }
3245 
3246 
3247 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3248                                         MachineBasicBlock::iterator MI,
3249                                         unsigned DestReg, int FrameIdx,
3250                                         const TargetRegisterClass *RC,
3251                                         const TargetRegisterInfo *TRI) const {
3252   const MachineFunction &MF = *MBB.getParent();
3253   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3254   bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
3255     RI.canRealignStack(MF);
3256   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
3257   DebugLoc DL = MBB.findDebugLoc(MI);
3258   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
3259 }
3260 
3261 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
3262                                  SmallVectorImpl<MachineOperand> &Addr,
3263                                  const TargetRegisterClass *RC,
3264                                  MachineInstr::mmo_iterator MMOBegin,
3265                                  MachineInstr::mmo_iterator MMOEnd,
3266                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
3267   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3268   bool isAligned = MMOBegin != MMOEnd &&
3269                    (*MMOBegin)->getAlignment() >= Alignment;
3270   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
3271   DebugLoc DL;
3272   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3273   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3274     MIB.addOperand(Addr[i]);
3275   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3276   NewMIs.push_back(MIB);
3277 }
3278 
3279 bool X86InstrInfo::
3280 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3281                int &CmpMask, int &CmpValue) const {
3282   switch (MI->getOpcode()) {
3283   default: break;
3284   case X86::CMP64ri32:
3285   case X86::CMP64ri8:
3286   case X86::CMP32ri:
3287   case X86::CMP32ri8:
3288   case X86::CMP16ri:
3289   case X86::CMP16ri8:
3290   case X86::CMP8ri:
3291     SrcReg = MI->getOperand(0).getReg();
3292     SrcReg2 = 0;
3293     CmpMask = ~0;
3294     CmpValue = MI->getOperand(1).getImm();
3295     return true;
3296   // A SUB can be used to perform comparison.
3297   case X86::SUB64rm:
3298   case X86::SUB32rm:
3299   case X86::SUB16rm:
3300   case X86::SUB8rm:
3301     SrcReg = MI->getOperand(1).getReg();
3302     SrcReg2 = 0;
3303     CmpMask = ~0;
3304     CmpValue = 0;
3305     return true;
3306   case X86::SUB64rr:
3307   case X86::SUB32rr:
3308   case X86::SUB16rr:
3309   case X86::SUB8rr:
3310     SrcReg = MI->getOperand(1).getReg();
3311     SrcReg2 = MI->getOperand(2).getReg();
3312     CmpMask = ~0;
3313     CmpValue = 0;
3314     return true;
3315   case X86::SUB64ri32:
3316   case X86::SUB64ri8:
3317   case X86::SUB32ri:
3318   case X86::SUB32ri8:
3319   case X86::SUB16ri:
3320   case X86::SUB16ri8:
3321   case X86::SUB8ri:
3322     SrcReg = MI->getOperand(1).getReg();
3323     SrcReg2 = 0;
3324     CmpMask = ~0;
3325     CmpValue = MI->getOperand(2).getImm();
3326     return true;
3327   case X86::CMP64rr:
3328   case X86::CMP32rr:
3329   case X86::CMP16rr:
3330   case X86::CMP8rr:
3331     SrcReg = MI->getOperand(0).getReg();
3332     SrcReg2 = MI->getOperand(1).getReg();
3333     CmpMask = ~0;
3334     CmpValue = 0;
3335     return true;
3336   case X86::TEST8rr:
3337   case X86::TEST16rr:
3338   case X86::TEST32rr:
3339   case X86::TEST64rr:
3340     SrcReg = MI->getOperand(0).getReg();
3341     if (MI->getOperand(1).getReg() != SrcReg) return false;
3342     // Compare against zero.
3343     SrcReg2 = 0;
3344     CmpMask = ~0;
3345     CmpValue = 0;
3346     return true;
3347   }
3348   return false;
3349 }
3350 
3351 /// isRedundantFlagInstr - check whether the first instruction, whose only
3352 /// purpose is to update flags, can be made redundant.
3353 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3354 /// This function can be extended later on.
3355 /// SrcReg, SrcRegs: register operands for FlagI.
3356 /// ImmValue: immediate for FlagI if it takes an immediate.
3357 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3358                                         unsigned SrcReg2, int ImmValue,
3359                                         MachineInstr *OI) {
3360   if (((FlagI->getOpcode() == X86::CMP64rr &&
3361         OI->getOpcode() == X86::SUB64rr) ||
3362        (FlagI->getOpcode() == X86::CMP32rr &&
3363         OI->getOpcode() == X86::SUB32rr)||
3364        (FlagI->getOpcode() == X86::CMP16rr &&
3365         OI->getOpcode() == X86::SUB16rr)||
3366        (FlagI->getOpcode() == X86::CMP8rr &&
3367         OI->getOpcode() == X86::SUB8rr)) &&
3368       ((OI->getOperand(1).getReg() == SrcReg &&
3369         OI->getOperand(2).getReg() == SrcReg2) ||
3370        (OI->getOperand(1).getReg() == SrcReg2 &&
3371         OI->getOperand(2).getReg() == SrcReg)))
3372     return true;
3373 
3374   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3375         OI->getOpcode() == X86::SUB64ri32) ||
3376        (FlagI->getOpcode() == X86::CMP64ri8 &&
3377         OI->getOpcode() == X86::SUB64ri8) ||
3378        (FlagI->getOpcode() == X86::CMP32ri &&
3379         OI->getOpcode() == X86::SUB32ri) ||
3380        (FlagI->getOpcode() == X86::CMP32ri8 &&
3381         OI->getOpcode() == X86::SUB32ri8) ||
3382        (FlagI->getOpcode() == X86::CMP16ri &&
3383         OI->getOpcode() == X86::SUB16ri) ||
3384        (FlagI->getOpcode() == X86::CMP16ri8 &&
3385         OI->getOpcode() == X86::SUB16ri8) ||
3386        (FlagI->getOpcode() == X86::CMP8ri &&
3387         OI->getOpcode() == X86::SUB8ri)) &&
3388       OI->getOperand(1).getReg() == SrcReg &&
3389       OI->getOperand(2).getImm() == ImmValue)
3390     return true;
3391   return false;
3392 }
3393 
3394 /// isDefConvertible - check whether the definition can be converted
3395 /// to remove a comparison against zero.
3396 inline static bool isDefConvertible(MachineInstr *MI) {
3397   switch (MI->getOpcode()) {
3398   default: return false;
3399 
3400   // The shift instructions only modify ZF if their shift count is non-zero.
3401   // N.B.: The processor truncates the shift count depending on the encoding.
3402   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3403   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3404      return getTruncatedShiftCount(MI, 2) != 0;
3405 
3406   // Some left shift instructions can be turned into LEA instructions but only
3407   // if their flags aren't used. Avoid transforming such instructions.
3408   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3409     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3410     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3411     return ShAmt != 0;
3412   }
3413 
3414   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3415   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3416      return getTruncatedShiftCount(MI, 3) != 0;
3417 
3418   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3419   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3420   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3421   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3422   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3423   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3424   case X86::DEC64_32r: case X86::DEC64_16r:
3425   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3426   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3427   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3428   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3429   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3430   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3431   case X86::INC64_32r: case X86::INC64_16r:
3432   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3433   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3434   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3435   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3436   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3437   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3438   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3439   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3440   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3441   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3442   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3443   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3444   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3445   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3446   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3447   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
3448   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
3449   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
3450   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
3451   case X86::ADC32ri:   case X86::ADC32ri8:
3452   case X86::ADC32rr:   case X86::ADC64ri32:
3453   case X86::ADC64ri8:  case X86::ADC64rr:
3454   case X86::SBB32ri:   case X86::SBB32ri8:
3455   case X86::SBB32rr:   case X86::SBB64ri32:
3456   case X86::SBB64ri8:  case X86::SBB64rr:
3457   case X86::ANDN32rr:  case X86::ANDN32rm:
3458   case X86::ANDN64rr:  case X86::ANDN64rm:
3459   case X86::BEXTR32rr: case X86::BEXTR64rr:
3460   case X86::BEXTR32rm: case X86::BEXTR64rm:
3461   case X86::BLSI32rr:  case X86::BLSI32rm:
3462   case X86::BLSI64rr:  case X86::BLSI64rm:
3463   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3464   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3465   case X86::BLSR32rr:  case X86::BLSR32rm:
3466   case X86::BLSR64rr:  case X86::BLSR64rm:
3467   case X86::BZHI32rr:  case X86::BZHI32rm:
3468   case X86::BZHI64rr:  case X86::BZHI64rm:
3469   case X86::LZCNT16rr: case X86::LZCNT16rm:
3470   case X86::LZCNT32rr: case X86::LZCNT32rm:
3471   case X86::LZCNT64rr: case X86::LZCNT64rm:
3472   case X86::POPCNT16rr:case X86::POPCNT16rm:
3473   case X86::POPCNT32rr:case X86::POPCNT32rm:
3474   case X86::POPCNT64rr:case X86::POPCNT64rm:
3475   case X86::TZCNT16rr: case X86::TZCNT16rm:
3476   case X86::TZCNT32rr: case X86::TZCNT32rm:
3477   case X86::TZCNT64rr: case X86::TZCNT64rm:
3478     return true;
3479   }
3480 }
3481 
3482 /// optimizeCompareInstr - Check if there exists an earlier instruction that
3483 /// operates on the same source operands and sets flags in the same way as
3484 /// Compare; remove Compare if possible.
3485 bool X86InstrInfo::
3486 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3487                      int CmpMask, int CmpValue,
3488                      const MachineRegisterInfo *MRI) const {
3489   // Check whether we can replace SUB with CMP.
3490   unsigned NewOpcode = 0;
3491   switch (CmpInstr->getOpcode()) {
3492   default: break;
3493   case X86::SUB64ri32:
3494   case X86::SUB64ri8:
3495   case X86::SUB32ri:
3496   case X86::SUB32ri8:
3497   case X86::SUB16ri:
3498   case X86::SUB16ri8:
3499   case X86::SUB8ri:
3500   case X86::SUB64rm:
3501   case X86::SUB32rm:
3502   case X86::SUB16rm:
3503   case X86::SUB8rm:
3504   case X86::SUB64rr:
3505   case X86::SUB32rr:
3506   case X86::SUB16rr:
3507   case X86::SUB8rr: {
3508     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3509       return false;
3510     // There is no use of the destination register, we can replace SUB with CMP.
3511     switch (CmpInstr->getOpcode()) {
3512     default: llvm_unreachable("Unreachable!");
3513     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
3514     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
3515     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
3516     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
3517     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
3518     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
3519     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
3520     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
3521     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3522     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
3523     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
3524     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
3525     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
3526     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
3527     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
3528     }
3529     CmpInstr->setDesc(get(NewOpcode));
3530     CmpInstr->RemoveOperand(0);
3531     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3532     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3533         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3534       return false;
3535   }
3536   }
3537 
3538   // Get the unique definition of SrcReg.
3539   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3540   if (!MI) return false;
3541 
3542   // CmpInstr is the first instruction of the BB.
3543   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3544 
3545   // If we are comparing against zero, check whether we can use MI to update
3546   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3547   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
3548   if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() ||
3549       !isDefConvertible(MI)))
3550     return false;
3551 
3552   // We are searching for an earlier instruction that can make CmpInstr
3553   // redundant and that instruction will be saved in Sub.
3554   MachineInstr *Sub = NULL;
3555   const TargetRegisterInfo *TRI = &getRegisterInfo();
3556 
3557   // We iterate backward, starting from the instruction before CmpInstr and
3558   // stop when reaching the definition of a source register or done with the BB.
3559   // RI points to the instruction before CmpInstr.
3560   // If the definition is in this basic block, RE points to the definition;
3561   // otherwise, RE is the rend of the basic block.
3562   MachineBasicBlock::reverse_iterator
3563       RI = MachineBasicBlock::reverse_iterator(I),
3564       RE = CmpInstr->getParent() == MI->getParent() ?
3565            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3566            CmpInstr->getParent()->rend();
3567   MachineInstr *Movr0Inst = 0;
3568   for (; RI != RE; ++RI) {
3569     MachineInstr *Instr = &*RI;
3570     // Check whether CmpInstr can be made redundant by the current instruction.
3571     if (!IsCmpZero &&
3572         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
3573       Sub = Instr;
3574       break;
3575     }
3576 
3577     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3578         Instr->readsRegister(X86::EFLAGS, TRI)) {
3579       // This instruction modifies or uses EFLAGS.
3580 
3581       // MOV32r0 etc. are implemented with xor which clobbers condition code.
3582       // They are safe to move up, if the definition to EFLAGS is dead and
3583       // earlier instructions do not read or write EFLAGS.
3584       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
3585           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3586         Movr0Inst = Instr;
3587         continue;
3588       }
3589 
3590       // We can't remove CmpInstr.
3591       return false;
3592     }
3593   }
3594 
3595   // Return false if no candidates exist.
3596   if (!IsCmpZero && !Sub)
3597     return false;
3598 
3599   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3600                     Sub->getOperand(2).getReg() == SrcReg);
3601 
3602   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3603   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3604   // If we are done with the basic block, we need to check whether EFLAGS is
3605   // live-out.
3606   bool IsSafe = false;
3607   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3608   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3609   for (++I; I != E; ++I) {
3610     const MachineInstr &Instr = *I;
3611     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3612     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3613     // We should check the usage if this instruction uses and updates EFLAGS.
3614     if (!UseEFLAGS && ModifyEFLAGS) {
3615       // It is safe to remove CmpInstr if EFLAGS is updated again.
3616       IsSafe = true;
3617       break;
3618     }
3619     if (!UseEFLAGS && !ModifyEFLAGS)
3620       continue;
3621 
3622     // EFLAGS is used by this instruction.
3623     X86::CondCode OldCC;
3624     bool OpcIsSET = false;
3625     if (IsCmpZero || IsSwapped) {
3626       // We decode the condition code from opcode.
3627       if (Instr.isBranch())
3628         OldCC = getCondFromBranchOpc(Instr.getOpcode());
3629       else {
3630         OldCC = getCondFromSETOpc(Instr.getOpcode());
3631         if (OldCC != X86::COND_INVALID)
3632           OpcIsSET = true;
3633         else
3634           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3635       }
3636       if (OldCC == X86::COND_INVALID) return false;
3637     }
3638     if (IsCmpZero) {
3639       switch (OldCC) {
3640       default: break;
3641       case X86::COND_A: case X86::COND_AE:
3642       case X86::COND_B: case X86::COND_BE:
3643       case X86::COND_G: case X86::COND_GE:
3644       case X86::COND_L: case X86::COND_LE:
3645       case X86::COND_O: case X86::COND_NO:
3646         // CF and OF are used, we can't perform this optimization.
3647         return false;
3648       }
3649     } else if (IsSwapped) {
3650       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3651       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3652       // We swap the condition code and synthesize the new opcode.
3653       X86::CondCode NewCC = getSwappedCondition(OldCC);
3654       if (NewCC == X86::COND_INVALID) return false;
3655 
3656       // Synthesize the new opcode.
3657       bool HasMemoryOperand = Instr.hasOneMemOperand();
3658       unsigned NewOpc;
3659       if (Instr.isBranch())
3660         NewOpc = GetCondBranchFromCond(NewCC);
3661       else if(OpcIsSET)
3662         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3663       else {
3664         unsigned DstReg = Instr.getOperand(0).getReg();
3665         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3666                                  HasMemoryOperand);
3667       }
3668 
3669       // Push the MachineInstr to OpsToUpdate.
3670       // If it is safe to remove CmpInstr, the condition code of these
3671       // instructions will be modified.
3672       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3673     }
3674     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3675       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3676       IsSafe = true;
3677       break;
3678     }
3679   }
3680 
3681   // If EFLAGS is not killed nor re-defined, we should check whether it is
3682   // live-out. If it is live-out, do not optimize.
3683   if ((IsCmpZero || IsSwapped) && !IsSafe) {
3684     MachineBasicBlock *MBB = CmpInstr->getParent();
3685     for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
3686              SE = MBB->succ_end(); SI != SE; ++SI)
3687       if ((*SI)->isLiveIn(X86::EFLAGS))
3688         return false;
3689   }
3690 
3691   // The instruction to be updated is either Sub or MI.
3692   Sub = IsCmpZero ? MI : Sub;
3693   // Move Movr0Inst to the appropriate place before Sub.
3694   if (Movr0Inst) {
3695     // Look backwards until we find a def that doesn't use the current EFLAGS.
3696     Def = Sub;
3697     MachineBasicBlock::reverse_iterator
3698       InsertI = MachineBasicBlock::reverse_iterator(++Def),
3699                 InsertE = Sub->getParent()->rend();
3700     for (; InsertI != InsertE; ++InsertI) {
3701       MachineInstr *Instr = &*InsertI;
3702       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3703           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3704         Sub->getParent()->remove(Movr0Inst);
3705         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3706                                    Movr0Inst);
3707         break;
3708       }
3709     }
3710     if (InsertI == InsertE)
3711       return false;
3712   }
3713 
3714   // Make sure Sub instruction defines EFLAGS and mark the def live.
3715   unsigned i = 0, e = Sub->getNumOperands();
3716   for (; i != e; ++i) {
3717     MachineOperand &MO = Sub->getOperand(i);
3718     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3719       MO.setIsDead(false);
3720       break;
3721     }
3722   }
3723   assert(i != e && "Unable to locate a def EFLAGS operand");
3724 
3725   CmpInstr->eraseFromParent();
3726 
3727   // Modify the condition code of instructions in OpsToUpdate.
3728   for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
3729     OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
3730   return true;
3731 }
3732 
3733 /// optimizeLoadInstr - Try to remove the load by folding it to a register
3734 /// operand at the use. We fold the load instructions if load defines a virtual
3735 /// register, the virtual register is used once in the same BB, and the
3736 /// instructions in-between do not load or store, and have no side effects.
3737 MachineInstr* X86InstrInfo::
3738 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,
3739                   unsigned &FoldAsLoadDefReg,
3740                   MachineInstr *&DefMI) const {
3741   if (FoldAsLoadDefReg == 0)
3742     return 0;
3743   // To be conservative, if there exists another load, clear the load candidate.
3744   if (MI->mayLoad()) {
3745     FoldAsLoadDefReg = 0;
3746     return 0;
3747   }
3748 
3749   // Check whether we can move DefMI here.
3750   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3751   assert(DefMI);
3752   bool SawStore = false;
3753   if (!DefMI->isSafeToMove(this, 0, SawStore))
3754     return 0;
3755 
3756   // We try to commute MI if possible.
3757   unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1;
3758   for (unsigned Idx = 0; Idx < IdxEnd; Idx++) {
3759     // Collect information about virtual register operands of MI.
3760     unsigned SrcOperandId = 0;
3761     bool FoundSrcOperand = false;
3762     for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
3763       MachineOperand &MO = MI->getOperand(i);
3764       if (!MO.isReg())
3765         continue;
3766       unsigned Reg = MO.getReg();
3767       if (Reg != FoldAsLoadDefReg)
3768         continue;
3769       // Do not fold if we have a subreg use or a def or multiple uses.
3770       if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
3771         return 0;
3772 
3773       SrcOperandId = i;
3774       FoundSrcOperand = true;
3775     }
3776     if (!FoundSrcOperand) return 0;
3777 
3778     // Check whether we can fold the def into SrcOperandId.
3779     SmallVector<unsigned, 8> Ops;
3780     Ops.push_back(SrcOperandId);
3781     MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
3782     if (FoldMI) {
3783       FoldAsLoadDefReg = 0;
3784       return FoldMI;
3785     }
3786 
3787     if (Idx == 1) {
3788       // MI was changed but it didn't help, commute it back!
3789       commuteInstruction(MI, false);
3790       return 0;
3791     }
3792 
3793     // Check whether we can commute MI and enable folding.
3794     if (MI->isCommutable()) {
3795       MachineInstr *NewMI = commuteInstruction(MI, false);
3796       // Unable to commute.
3797       if (!NewMI) return 0;
3798       if (NewMI != MI) {
3799         // New instruction. It doesn't need to be kept.
3800         NewMI->eraseFromParent();
3801         return 0;
3802       }
3803     }
3804   }
3805   return 0;
3806 }
3807 
3808 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
3809 /// instruction with two undef reads of the register being defined.  This is
3810 /// used for mapping:
3811 ///   %xmm4 = V_SET0
3812 /// to:
3813 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
3814 ///
3815 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3816                              const MCInstrDesc &Desc) {
3817   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3818   unsigned Reg = MIB->getOperand(0).getReg();
3819   MIB->setDesc(Desc);
3820 
3821   // MachineInstr::addOperand() will insert explicit operands before any
3822   // implicit operands.
3823   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3824   // But we don't trust that.
3825   assert(MIB->getOperand(1).getReg() == Reg &&
3826          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3827   return true;
3828 }
3829 
3830 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
3831   bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3832   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
3833   switch (MI->getOpcode()) {
3834   case X86::SETB_C8r:
3835     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
3836   case X86::SETB_C16r:
3837     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
3838   case X86::SETB_C32r:
3839     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
3840   case X86::SETB_C64r:
3841     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
3842   case X86::V_SET0:
3843   case X86::FsFLD0SS:
3844   case X86::FsFLD0SD:
3845     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
3846   case X86::AVX_SET0:
3847     assert(HasAVX && "AVX not supported");
3848     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
3849   case X86::AVX512_512_SET0:
3850     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
3851   case X86::V_SETALLONES:
3852     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
3853   case X86::AVX2_SETALLONES:
3854     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
3855   case X86::TEST8ri_NOREX:
3856     MI->setDesc(get(X86::TEST8ri));
3857     return true;
3858   case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
3859   case X86::KSET1B:
3860   case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
3861   }
3862   return false;
3863 }
3864 
3865 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
3866                                      const SmallVectorImpl<MachineOperand> &MOs,
3867                                      MachineInstr *MI,
3868                                      const TargetInstrInfo &TII) {
3869   // Create the base instruction with the memory operand as the first part.
3870   // Omit the implicit operands, something BuildMI can't do.
3871   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3872                                               MI->getDebugLoc(), true);
3873   MachineInstrBuilder MIB(MF, NewMI);
3874   unsigned NumAddrOps = MOs.size();
3875   for (unsigned i = 0; i != NumAddrOps; ++i)
3876     MIB.addOperand(MOs[i]);
3877   if (NumAddrOps < 4)  // FrameIndex only
3878     addOffset(MIB, 0);
3879 
3880   // Loop over the rest of the ri operands, converting them over.
3881   unsigned NumOps = MI->getDesc().getNumOperands()-2;
3882   for (unsigned i = 0; i != NumOps; ++i) {
3883     MachineOperand &MO = MI->getOperand(i+2);
3884     MIB.addOperand(MO);
3885   }
3886   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
3887     MachineOperand &MO = MI->getOperand(i);
3888     MIB.addOperand(MO);
3889   }
3890   return MIB;
3891 }
3892 
3893 static MachineInstr *FuseInst(MachineFunction &MF,
3894                               unsigned Opcode, unsigned OpNo,
3895                               const SmallVectorImpl<MachineOperand> &MOs,
3896                               MachineInstr *MI, const TargetInstrInfo &TII) {
3897   // Omit the implicit operands, something BuildMI can't do.
3898   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3899                                               MI->getDebugLoc(), true);
3900   MachineInstrBuilder MIB(MF, NewMI);
3901 
3902   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3903     MachineOperand &MO = MI->getOperand(i);
3904     if (i == OpNo) {
3905       assert(MO.isReg() && "Expected to fold into reg operand!");
3906       unsigned NumAddrOps = MOs.size();
3907       for (unsigned i = 0; i != NumAddrOps; ++i)
3908         MIB.addOperand(MOs[i]);
3909       if (NumAddrOps < 4)  // FrameIndex only
3910         addOffset(MIB, 0);
3911     } else {
3912       MIB.addOperand(MO);
3913     }
3914   }
3915   return MIB;
3916 }
3917 
3918 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
3919                                 const SmallVectorImpl<MachineOperand> &MOs,
3920                                 MachineInstr *MI) {
3921   MachineFunction &MF = *MI->getParent()->getParent();
3922   MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
3923 
3924   unsigned NumAddrOps = MOs.size();
3925   for (unsigned i = 0; i != NumAddrOps; ++i)
3926     MIB.addOperand(MOs[i]);
3927   if (NumAddrOps < 4)  // FrameIndex only
3928     addOffset(MIB, 0);
3929   return MIB.addImm(0);
3930 }
3931 
3932 MachineInstr*
3933 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3934                                     MachineInstr *MI, unsigned i,
3935                                     const SmallVectorImpl<MachineOperand> &MOs,
3936                                     unsigned Size, unsigned Align) const {
3937   const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
3938   bool isCallRegIndirect = TM.getSubtarget<X86Subtarget>().callRegIndirect();
3939   bool isTwoAddrFold = false;
3940 
3941   // Atom favors register form of call. So, we do not fold loads into calls
3942   // when X86Subtarget is Atom.
3943   if (isCallRegIndirect &&
3944     (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
3945     return NULL;
3946   }
3947 
3948   unsigned NumOps = MI->getDesc().getNumOperands();
3949   bool isTwoAddr = NumOps > 1 &&
3950     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3951 
3952   // FIXME: AsmPrinter doesn't know how to handle
3953   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3954   if (MI->getOpcode() == X86::ADD32ri &&
3955       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3956     return NULL;
3957 
3958   MachineInstr *NewMI = NULL;
3959   // Folding a memory location into the two-address part of a two-address
3960   // instruction is different than folding it other places.  It requires
3961   // replacing the *two* registers with the memory location.
3962   if (isTwoAddr && NumOps >= 2 && i < 2 &&
3963       MI->getOperand(0).isReg() &&
3964       MI->getOperand(1).isReg() &&
3965       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
3966     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3967     isTwoAddrFold = true;
3968   } else if (i == 0) { // If operand 0
3969     if (MI->getOpcode() == X86::MOV32r0) {
3970       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
3971       if (NewMI)
3972         return NewMI;
3973     }
3974 
3975     OpcodeTablePtr = &RegOp2MemOpTable0;
3976   } else if (i == 1) {
3977     OpcodeTablePtr = &RegOp2MemOpTable1;
3978   } else if (i == 2) {
3979     OpcodeTablePtr = &RegOp2MemOpTable2;
3980   } else if (i == 3) {
3981     OpcodeTablePtr = &RegOp2MemOpTable3;
3982   }
3983 
3984   // If table selected...
3985   if (OpcodeTablePtr) {
3986     // Find the Opcode to fuse
3987     DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3988       OpcodeTablePtr->find(MI->getOpcode());
3989     if (I != OpcodeTablePtr->end()) {
3990       unsigned Opcode = I->second.first;
3991       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
3992       if (Align < MinAlign)
3993         return NULL;
3994       bool NarrowToMOV32rm = false;
3995       if (Size) {
3996         unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
3997         if (Size < RCSize) {
3998           // Check if it's safe to fold the load. If the size of the object is
3999           // narrower than the load width, then it's not.
4000           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4001             return NULL;
4002           // If this is a 64-bit load, but the spill slot is 32, then we can do
4003           // a 32-bit load which is implicitly zero-extended. This likely is due
4004           // to liveintervalanalysis remat'ing a load from stack slot.
4005           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4006             return NULL;
4007           Opcode = X86::MOV32rm;
4008           NarrowToMOV32rm = true;
4009         }
4010       }
4011 
4012       if (isTwoAddrFold)
4013         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
4014       else
4015         NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
4016 
4017       if (NarrowToMOV32rm) {
4018         // If this is the special case where we use a MOV32rm to load a 32-bit
4019         // value and zero-extend the top bits. Change the destination register
4020         // to a 32-bit one.
4021         unsigned DstReg = NewMI->getOperand(0).getReg();
4022         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4023           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
4024                                                    X86::sub_32bit));
4025         else
4026           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4027       }
4028       return NewMI;
4029     }
4030   }
4031 
4032   // No fusion
4033   if (PrintFailedFusing && !MI->isCopy())
4034     dbgs() << "We failed to fuse operand " << i << " in " << *MI;
4035   return NULL;
4036 }
4037 
4038 /// hasPartialRegUpdate - Return true for all instructions that only update
4039 /// the first 32 or 64-bits of the destination register and leave the rest
4040 /// unmodified. This can be used to avoid folding loads if the instructions
4041 /// only update part of the destination register, and the non-updated part is
4042 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4043 /// instructions breaks the partial register dependency and it can improve
4044 /// performance. e.g.:
4045 ///
4046 ///   movss (%rdi), %xmm0
4047 ///   cvtss2sd %xmm0, %xmm0
4048 ///
4049 /// Instead of
4050 ///   cvtss2sd (%rdi), %xmm0
4051 ///
4052 /// FIXME: This should be turned into a TSFlags.
4053 ///
4054 static bool hasPartialRegUpdate(unsigned Opcode) {
4055   switch (Opcode) {
4056   case X86::CVTSI2SSrr:
4057   case X86::CVTSI2SS64rr:
4058   case X86::CVTSI2SDrr:
4059   case X86::CVTSI2SD64rr:
4060   case X86::CVTSD2SSrr:
4061   case X86::Int_CVTSD2SSrr:
4062   case X86::CVTSS2SDrr:
4063   case X86::Int_CVTSS2SDrr:
4064   case X86::RCPSSr:
4065   case X86::RCPSSr_Int:
4066   case X86::ROUNDSDr:
4067   case X86::ROUNDSDr_Int:
4068   case X86::ROUNDSSr:
4069   case X86::ROUNDSSr_Int:
4070   case X86::RSQRTSSr:
4071   case X86::RSQRTSSr_Int:
4072   case X86::SQRTSSr:
4073   case X86::SQRTSSr_Int:
4074     return true;
4075   }
4076 
4077   return false;
4078 }
4079 
4080 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4081 /// instructions we would like before a partial register update.
4082 unsigned X86InstrInfo::
4083 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4084                              const TargetRegisterInfo *TRI) const {
4085   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4086     return 0;
4087 
4088   // If MI is marked as reading Reg, the partial register update is wanted.
4089   const MachineOperand &MO = MI->getOperand(0);
4090   unsigned Reg = MO.getReg();
4091   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4092     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4093       return 0;
4094   } else {
4095     if (MI->readsRegister(Reg, TRI))
4096       return 0;
4097   }
4098 
4099   // If any of the preceding 16 instructions are reading Reg, insert a
4100   // dependency breaking instruction.  The magic number is based on a few
4101   // Nehalem experiments.
4102   return 16;
4103 }
4104 
4105 // Return true for any instruction the copies the high bits of the first source
4106 // operand into the unused high bits of the destination operand.
4107 static bool hasUndefRegUpdate(unsigned Opcode) {
4108   switch (Opcode) {
4109   case X86::VCVTSI2SSrr:
4110   case X86::Int_VCVTSI2SSrr:
4111   case X86::VCVTSI2SS64rr:
4112   case X86::Int_VCVTSI2SS64rr:
4113   case X86::VCVTSI2SDrr:
4114   case X86::Int_VCVTSI2SDrr:
4115   case X86::VCVTSI2SD64rr:
4116   case X86::Int_VCVTSI2SD64rr:
4117   case X86::VCVTSD2SSrr:
4118   case X86::Int_VCVTSD2SSrr:
4119   case X86::VCVTSS2SDrr:
4120   case X86::Int_VCVTSS2SDrr:
4121   case X86::VRCPSSr:
4122   case X86::VROUNDSDr:
4123   case X86::VROUNDSDr_Int:
4124   case X86::VROUNDSSr:
4125   case X86::VROUNDSSr_Int:
4126   case X86::VRSQRTSSr:
4127   case X86::VSQRTSSr:
4128 
4129   // AVX-512
4130   case X86::VCVTSD2SSZrr:
4131   case X86::VCVTSS2SDZrr:
4132     return true;
4133   }
4134 
4135   return false;
4136 }
4137 
4138 /// Inform the ExeDepsFix pass how many idle instructions we would like before
4139 /// certain undef register reads.
4140 ///
4141 /// This catches the VCVTSI2SD family of instructions:
4142 ///
4143 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4144 ///
4145 /// We should to be careful *not* to catch VXOR idioms which are presumably
4146 /// handled specially in the pipeline:
4147 ///
4148 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4149 ///
4150 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4151 /// high bits that are passed-through are not live.
4152 unsigned X86InstrInfo::
4153 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4154                      const TargetRegisterInfo *TRI) const {
4155   if (!hasUndefRegUpdate(MI->getOpcode()))
4156     return 0;
4157 
4158   // Set the OpNum parameter to the first source operand.
4159   OpNum = 1;
4160 
4161   const MachineOperand &MO = MI->getOperand(OpNum);
4162   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4163     // Use the same magic number as getPartialRegUpdateClearance.
4164     return 16;
4165   }
4166   return 0;
4167 }
4168 
4169 void X86InstrInfo::
4170 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4171                           const TargetRegisterInfo *TRI) const {
4172   unsigned Reg = MI->getOperand(OpNum).getReg();
4173   // If MI kills this register, the false dependence is already broken.
4174   if (MI->killsRegister(Reg, TRI))
4175     return;
4176   if (X86::VR128RegClass.contains(Reg)) {
4177     // These instructions are all floating point domain, so xorps is the best
4178     // choice.
4179     bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
4180     unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4181     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4182       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4183   } else if (X86::VR256RegClass.contains(Reg)) {
4184     // Use vxorps to clear the full ymm register.
4185     // It wants to read and write the xmm sub-register.
4186     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4187     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4188       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4189       .addReg(Reg, RegState::ImplicitDefine);
4190   } else
4191     return;
4192   MI->addRegisterKilled(Reg, TRI, true);
4193 }
4194 
4195 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4196                                                   MachineInstr *MI,
4197                                            const SmallVectorImpl<unsigned> &Ops,
4198                                                   int FrameIndex) const {
4199   // Check switch flag
4200   if (NoFusing) return NULL;
4201 
4202   // Unless optimizing for size, don't fold to avoid partial
4203   // register update stalls
4204   if (!MF.getFunction()->getAttributes().
4205         hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4206       hasPartialRegUpdate(MI->getOpcode()))
4207     return 0;
4208 
4209   const MachineFrameInfo *MFI = MF.getFrameInfo();
4210   unsigned Size = MFI->getObjectSize(FrameIndex);
4211   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
4212   // If the function stack isn't realigned we don't want to fold instructions
4213   // that need increased alignment.
4214   if (!RI.needsStackRealignment(MF))
4215     Alignment = std::min(Alignment, TM.getFrameLowering()->getStackAlignment());
4216   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4217     unsigned NewOpc = 0;
4218     unsigned RCSize = 0;
4219     switch (MI->getOpcode()) {
4220     default: return NULL;
4221     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
4222     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4223     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4224     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4225     }
4226     // Check if it's safe to fold the load. If the size of the object is
4227     // narrower than the load width, then it's not.
4228     if (Size < RCSize)
4229       return NULL;
4230     // Change to CMPXXri r, 0 first.
4231     MI->setDesc(get(NewOpc));
4232     MI->getOperand(1).ChangeToImmediate(0);
4233   } else if (Ops.size() != 1)
4234     return NULL;
4235 
4236   SmallVector<MachineOperand,4> MOs;
4237   MOs.push_back(MachineOperand::CreateFI(FrameIndex));
4238   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
4239 }
4240 
4241 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4242                                                   MachineInstr *MI,
4243                                            const SmallVectorImpl<unsigned> &Ops,
4244                                                   MachineInstr *LoadMI) const {
4245   // Check switch flag
4246   if (NoFusing) return NULL;
4247 
4248   // Unless optimizing for size, don't fold to avoid partial
4249   // register update stalls
4250   if (!MF.getFunction()->getAttributes().
4251         hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4252       hasPartialRegUpdate(MI->getOpcode()))
4253     return 0;
4254 
4255   // Determine the alignment of the load.
4256   unsigned Alignment = 0;
4257   if (LoadMI->hasOneMemOperand())
4258     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
4259   else
4260     switch (LoadMI->getOpcode()) {
4261     case X86::AVX2_SETALLONES:
4262     case X86::AVX_SET0:
4263       Alignment = 32;
4264       break;
4265     case X86::V_SET0:
4266     case X86::V_SETALLONES:
4267       Alignment = 16;
4268       break;
4269     case X86::FsFLD0SD:
4270       Alignment = 8;
4271       break;
4272     case X86::FsFLD0SS:
4273       Alignment = 4;
4274       break;
4275     default:
4276       return 0;
4277     }
4278   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4279     unsigned NewOpc = 0;
4280     switch (MI->getOpcode()) {
4281     default: return NULL;
4282     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
4283     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4284     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4285     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
4286     }
4287     // Change to CMPXXri r, 0 first.
4288     MI->setDesc(get(NewOpc));
4289     MI->getOperand(1).ChangeToImmediate(0);
4290   } else if (Ops.size() != 1)
4291     return NULL;
4292 
4293   // Make sure the subregisters match.
4294   // Otherwise we risk changing the size of the load.
4295   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
4296     return NULL;
4297 
4298   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
4299   switch (LoadMI->getOpcode()) {
4300   case X86::V_SET0:
4301   case X86::V_SETALLONES:
4302   case X86::AVX2_SETALLONES:
4303   case X86::AVX_SET0:
4304   case X86::FsFLD0SD:
4305   case X86::FsFLD0SS: {
4306     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
4307     // Create a constant-pool entry and operands to load from it.
4308 
4309     // Medium and large mode can't fold loads this way.
4310     if (TM.getCodeModel() != CodeModel::Small &&
4311         TM.getCodeModel() != CodeModel::Kernel)
4312       return NULL;
4313 
4314     // x86-32 PIC requires a PIC base register for constant pools.
4315     unsigned PICBase = 0;
4316     if (TM.getRelocationModel() == Reloc::PIC_) {
4317       if (TM.getSubtarget<X86Subtarget>().is64Bit())
4318         PICBase = X86::RIP;
4319       else
4320         // FIXME: PICBase = getGlobalBaseReg(&MF);
4321         // This doesn't work for several reasons.
4322         // 1. GlobalBaseReg may have been spilled.
4323         // 2. It may not be live at MI.
4324         return NULL;
4325     }
4326 
4327     // Create a constant-pool entry.
4328     MachineConstantPool &MCP = *MF.getConstantPool();
4329     Type *Ty;
4330     unsigned Opc = LoadMI->getOpcode();
4331     if (Opc == X86::FsFLD0SS)
4332       Ty = Type::getFloatTy(MF.getFunction()->getContext());
4333     else if (Opc == X86::FsFLD0SD)
4334       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
4335     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
4336       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
4337     else
4338       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
4339 
4340     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
4341     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4342                                     Constant::getNullValue(Ty);
4343     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
4344 
4345     // Create operands to load from the constant pool entry.
4346     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4347     MOs.push_back(MachineOperand::CreateImm(1));
4348     MOs.push_back(MachineOperand::CreateReg(0, false));
4349     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
4350     MOs.push_back(MachineOperand::CreateReg(0, false));
4351     break;
4352   }
4353   default: {
4354     if ((LoadMI->getOpcode() == X86::MOVSSrm ||
4355          LoadMI->getOpcode() == X86::VMOVSSrm) &&
4356         MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4357           > 4)
4358       // These instructions only load 32 bits, we can't fold them if the
4359       // destination register is wider than 32 bits (4 bytes).
4360       return NULL;
4361     if ((LoadMI->getOpcode() == X86::MOVSDrm ||
4362          LoadMI->getOpcode() == X86::VMOVSDrm) &&
4363         MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4364           > 8)
4365       // These instructions only load 64 bits, we can't fold them if the
4366       // destination register is wider than 64 bits (8 bytes).
4367       return NULL;
4368 
4369     // Folding a normal load. Just copy the load's address operands.
4370     unsigned NumOps = LoadMI->getDesc().getNumOperands();
4371     for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
4372       MOs.push_back(LoadMI->getOperand(i));
4373     break;
4374   }
4375   }
4376   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
4377 }
4378 
4379 
4380 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4381                                   const SmallVectorImpl<unsigned> &Ops) const {
4382   // Check switch flag
4383   if (NoFusing) return 0;
4384 
4385   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4386     switch (MI->getOpcode()) {
4387     default: return false;
4388     case X86::TEST8rr:
4389     case X86::TEST16rr:
4390     case X86::TEST32rr:
4391     case X86::TEST64rr:
4392       return true;
4393     case X86::ADD32ri:
4394       // FIXME: AsmPrinter doesn't know how to handle
4395       // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4396       if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4397         return false;
4398       break;
4399     }
4400   }
4401 
4402   if (Ops.size() != 1)
4403     return false;
4404 
4405   unsigned OpNum = Ops[0];
4406   unsigned Opc = MI->getOpcode();
4407   unsigned NumOps = MI->getDesc().getNumOperands();
4408   bool isTwoAddr = NumOps > 1 &&
4409     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4410 
4411   // Folding a memory location into the two-address part of a two-address
4412   // instruction is different than folding it other places.  It requires
4413   // replacing the *two* registers with the memory location.
4414   const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
4415   if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
4416     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4417   } else if (OpNum == 0) { // If operand 0
4418     if (Opc == X86::MOV32r0)
4419       return true;
4420 
4421     OpcodeTablePtr = &RegOp2MemOpTable0;
4422   } else if (OpNum == 1) {
4423     OpcodeTablePtr = &RegOp2MemOpTable1;
4424   } else if (OpNum == 2) {
4425     OpcodeTablePtr = &RegOp2MemOpTable2;
4426   } else if (OpNum == 3) {
4427     OpcodeTablePtr = &RegOp2MemOpTable3;
4428   }
4429 
4430   if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4431     return true;
4432   return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
4433 }
4434 
4435 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4436                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
4437                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4438   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4439     MemOp2RegOpTable.find(MI->getOpcode());
4440   if (I == MemOp2RegOpTable.end())
4441     return false;
4442   unsigned Opc = I->second.first;
4443   unsigned Index = I->second.second & TB_INDEX_MASK;
4444   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4445   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4446   if (UnfoldLoad && !FoldedLoad)
4447     return false;
4448   UnfoldLoad &= FoldedLoad;
4449   if (UnfoldStore && !FoldedStore)
4450     return false;
4451   UnfoldStore &= FoldedStore;
4452 
4453   const MCInstrDesc &MCID = get(Opc);
4454   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4455   if (!MI->hasOneMemOperand() &&
4456       RC == &X86::VR128RegClass &&
4457       !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4458     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4459     // conservatively assume the address is unaligned. That's bad for
4460     // performance.
4461     return false;
4462   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
4463   SmallVector<MachineOperand,2> BeforeOps;
4464   SmallVector<MachineOperand,2> AfterOps;
4465   SmallVector<MachineOperand,4> ImpOps;
4466   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4467     MachineOperand &Op = MI->getOperand(i);
4468     if (i >= Index && i < Index + X86::AddrNumOperands)
4469       AddrOps.push_back(Op);
4470     else if (Op.isReg() && Op.isImplicit())
4471       ImpOps.push_back(Op);
4472     else if (i < Index)
4473       BeforeOps.push_back(Op);
4474     else if (i > Index)
4475       AfterOps.push_back(Op);
4476   }
4477 
4478   // Emit the load instruction.
4479   if (UnfoldLoad) {
4480     std::pair<MachineInstr::mmo_iterator,
4481               MachineInstr::mmo_iterator> MMOs =
4482       MF.extractLoadMemRefs(MI->memoperands_begin(),
4483                             MI->memoperands_end());
4484     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
4485     if (UnfoldStore) {
4486       // Address operands cannot be marked isKill.
4487       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
4488         MachineOperand &MO = NewMIs[0]->getOperand(i);
4489         if (MO.isReg())
4490           MO.setIsKill(false);
4491       }
4492     }
4493   }
4494 
4495   // Emit the data processing instruction.
4496   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
4497   MachineInstrBuilder MIB(MF, DataMI);
4498 
4499   if (FoldedStore)
4500     MIB.addReg(Reg, RegState::Define);
4501   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
4502     MIB.addOperand(BeforeOps[i]);
4503   if (FoldedLoad)
4504     MIB.addReg(Reg);
4505   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
4506     MIB.addOperand(AfterOps[i]);
4507   for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
4508     MachineOperand &MO = ImpOps[i];
4509     MIB.addReg(MO.getReg(),
4510                getDefRegState(MO.isDef()) |
4511                RegState::Implicit |
4512                getKillRegState(MO.isKill()) |
4513                getDeadRegState(MO.isDead()) |
4514                getUndefRegState(MO.isUndef()));
4515   }
4516   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
4517   switch (DataMI->getOpcode()) {
4518   default: break;
4519   case X86::CMP64ri32:
4520   case X86::CMP64ri8:
4521   case X86::CMP32ri:
4522   case X86::CMP32ri8:
4523   case X86::CMP16ri:
4524   case X86::CMP16ri8:
4525   case X86::CMP8ri: {
4526     MachineOperand &MO0 = DataMI->getOperand(0);
4527     MachineOperand &MO1 = DataMI->getOperand(1);
4528     if (MO1.getImm() == 0) {
4529       unsigned NewOpc;
4530       switch (DataMI->getOpcode()) {
4531       default: llvm_unreachable("Unreachable!");
4532       case X86::CMP64ri8:
4533       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
4534       case X86::CMP32ri8:
4535       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
4536       case X86::CMP16ri8:
4537       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
4538       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
4539       }
4540       DataMI->setDesc(get(NewOpc));
4541       MO1.ChangeToRegister(MO0.getReg(), false);
4542     }
4543   }
4544   }
4545   NewMIs.push_back(DataMI);
4546 
4547   // Emit the store instruction.
4548   if (UnfoldStore) {
4549     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
4550     std::pair<MachineInstr::mmo_iterator,
4551               MachineInstr::mmo_iterator> MMOs =
4552       MF.extractStoreMemRefs(MI->memoperands_begin(),
4553                              MI->memoperands_end());
4554     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
4555   }
4556 
4557   return true;
4558 }
4559 
4560 bool
4561 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
4562                                   SmallVectorImpl<SDNode*> &NewNodes) const {
4563   if (!N->isMachineOpcode())
4564     return false;
4565 
4566   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4567     MemOp2RegOpTable.find(N->getMachineOpcode());
4568   if (I == MemOp2RegOpTable.end())
4569     return false;
4570   unsigned Opc = I->second.first;
4571   unsigned Index = I->second.second & TB_INDEX_MASK;
4572   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4573   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4574   const MCInstrDesc &MCID = get(Opc);
4575   MachineFunction &MF = DAG.getMachineFunction();
4576   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4577   unsigned NumDefs = MCID.NumDefs;
4578   std::vector<SDValue> AddrOps;
4579   std::vector<SDValue> BeforeOps;
4580   std::vector<SDValue> AfterOps;
4581   SDLoc dl(N);
4582   unsigned NumOps = N->getNumOperands();
4583   for (unsigned i = 0; i != NumOps-1; ++i) {
4584     SDValue Op = N->getOperand(i);
4585     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
4586       AddrOps.push_back(Op);
4587     else if (i < Index-NumDefs)
4588       BeforeOps.push_back(Op);
4589     else if (i > Index-NumDefs)
4590       AfterOps.push_back(Op);
4591   }
4592   SDValue Chain = N->getOperand(NumOps-1);
4593   AddrOps.push_back(Chain);
4594 
4595   // Emit the load instruction.
4596   SDNode *Load = 0;
4597   if (FoldedLoad) {
4598     EVT VT = *RC->vt_begin();
4599     std::pair<MachineInstr::mmo_iterator,
4600               MachineInstr::mmo_iterator> MMOs =
4601       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4602                             cast<MachineSDNode>(N)->memoperands_end());
4603     if (!(*MMOs.first) &&
4604         RC == &X86::VR128RegClass &&
4605         !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4606       // Do not introduce a slow unaligned load.
4607       return false;
4608     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4609     bool isAligned = (*MMOs.first) &&
4610                      (*MMOs.first)->getAlignment() >= Alignment;
4611     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
4612                               VT, MVT::Other, AddrOps);
4613     NewNodes.push_back(Load);
4614 
4615     // Preserve memory reference information.
4616     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4617   }
4618 
4619   // Emit the data processing instruction.
4620   std::vector<EVT> VTs;
4621   const TargetRegisterClass *DstRC = 0;
4622   if (MCID.getNumDefs() > 0) {
4623     DstRC = getRegClass(MCID, 0, &RI, MF);
4624     VTs.push_back(*DstRC->vt_begin());
4625   }
4626   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
4627     EVT VT = N->getValueType(i);
4628     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
4629       VTs.push_back(VT);
4630   }
4631   if (Load)
4632     BeforeOps.push_back(SDValue(Load, 0));
4633   std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
4634   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
4635   NewNodes.push_back(NewNode);
4636 
4637   // Emit the store instruction.
4638   if (FoldedStore) {
4639     AddrOps.pop_back();
4640     AddrOps.push_back(SDValue(NewNode, 0));
4641     AddrOps.push_back(Chain);
4642     std::pair<MachineInstr::mmo_iterator,
4643               MachineInstr::mmo_iterator> MMOs =
4644       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4645                              cast<MachineSDNode>(N)->memoperands_end());
4646     if (!(*MMOs.first) &&
4647         RC == &X86::VR128RegClass &&
4648         !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4649       // Do not introduce a slow unaligned store.
4650       return false;
4651     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4652     bool isAligned = (*MMOs.first) &&
4653                      (*MMOs.first)->getAlignment() >= Alignment;
4654     SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
4655                                                          isAligned, TM),
4656                                        dl, MVT::Other, AddrOps);
4657     NewNodes.push_back(Store);
4658 
4659     // Preserve memory reference information.
4660     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4661   }
4662 
4663   return true;
4664 }
4665 
4666 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
4667                                       bool UnfoldLoad, bool UnfoldStore,
4668                                       unsigned *LoadRegIndex) const {
4669   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4670     MemOp2RegOpTable.find(Opc);
4671   if (I == MemOp2RegOpTable.end())
4672     return 0;
4673   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4674   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4675   if (UnfoldLoad && !FoldedLoad)
4676     return 0;
4677   if (UnfoldStore && !FoldedStore)
4678     return 0;
4679   if (LoadRegIndex)
4680     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
4681   return I->second.first;
4682 }
4683 
4684 bool
4685 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
4686                                      int64_t &Offset1, int64_t &Offset2) const {
4687   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
4688     return false;
4689   unsigned Opc1 = Load1->getMachineOpcode();
4690   unsigned Opc2 = Load2->getMachineOpcode();
4691   switch (Opc1) {
4692   default: return false;
4693   case X86::MOV8rm:
4694   case X86::MOV16rm:
4695   case X86::MOV32rm:
4696   case X86::MOV64rm:
4697   case X86::LD_Fp32m:
4698   case X86::LD_Fp64m:
4699   case X86::LD_Fp80m:
4700   case X86::MOVSSrm:
4701   case X86::MOVSDrm:
4702   case X86::MMX_MOVD64rm:
4703   case X86::MMX_MOVQ64rm:
4704   case X86::FsMOVAPSrm:
4705   case X86::FsMOVAPDrm:
4706   case X86::MOVAPSrm:
4707   case X86::MOVUPSrm:
4708   case X86::MOVAPDrm:
4709   case X86::MOVDQArm:
4710   case X86::MOVDQUrm:
4711   // AVX load instructions
4712   case X86::VMOVSSrm:
4713   case X86::VMOVSDrm:
4714   case X86::FsVMOVAPSrm:
4715   case X86::FsVMOVAPDrm:
4716   case X86::VMOVAPSrm:
4717   case X86::VMOVUPSrm:
4718   case X86::VMOVAPDrm:
4719   case X86::VMOVDQArm:
4720   case X86::VMOVDQUrm:
4721   case X86::VMOVAPSYrm:
4722   case X86::VMOVUPSYrm:
4723   case X86::VMOVAPDYrm:
4724   case X86::VMOVDQAYrm:
4725   case X86::VMOVDQUYrm:
4726     break;
4727   }
4728   switch (Opc2) {
4729   default: return false;
4730   case X86::MOV8rm:
4731   case X86::MOV16rm:
4732   case X86::MOV32rm:
4733   case X86::MOV64rm:
4734   case X86::LD_Fp32m:
4735   case X86::LD_Fp64m:
4736   case X86::LD_Fp80m:
4737   case X86::MOVSSrm:
4738   case X86::MOVSDrm:
4739   case X86::MMX_MOVD64rm:
4740   case X86::MMX_MOVQ64rm:
4741   case X86::FsMOVAPSrm:
4742   case X86::FsMOVAPDrm:
4743   case X86::MOVAPSrm:
4744   case X86::MOVUPSrm:
4745   case X86::MOVAPDrm:
4746   case X86::MOVDQArm:
4747   case X86::MOVDQUrm:
4748   // AVX load instructions
4749   case X86::VMOVSSrm:
4750   case X86::VMOVSDrm:
4751   case X86::FsVMOVAPSrm:
4752   case X86::FsVMOVAPDrm:
4753   case X86::VMOVAPSrm:
4754   case X86::VMOVUPSrm:
4755   case X86::VMOVAPDrm:
4756   case X86::VMOVDQArm:
4757   case X86::VMOVDQUrm:
4758   case X86::VMOVAPSYrm:
4759   case X86::VMOVUPSYrm:
4760   case X86::VMOVAPDYrm:
4761   case X86::VMOVDQAYrm:
4762   case X86::VMOVDQUYrm:
4763     break;
4764   }
4765 
4766   // Check if chain operands and base addresses match.
4767   if (Load1->getOperand(0) != Load2->getOperand(0) ||
4768       Load1->getOperand(5) != Load2->getOperand(5))
4769     return false;
4770   // Segment operands should match as well.
4771   if (Load1->getOperand(4) != Load2->getOperand(4))
4772     return false;
4773   // Scale should be 1, Index should be Reg0.
4774   if (Load1->getOperand(1) == Load2->getOperand(1) &&
4775       Load1->getOperand(2) == Load2->getOperand(2)) {
4776     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
4777       return false;
4778 
4779     // Now let's examine the displacements.
4780     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
4781         isa<ConstantSDNode>(Load2->getOperand(3))) {
4782       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
4783       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
4784       return true;
4785     }
4786   }
4787   return false;
4788 }
4789 
4790 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
4791                                            int64_t Offset1, int64_t Offset2,
4792                                            unsigned NumLoads) const {
4793   assert(Offset2 > Offset1);
4794   if ((Offset2 - Offset1) / 8 > 64)
4795     return false;
4796 
4797   unsigned Opc1 = Load1->getMachineOpcode();
4798   unsigned Opc2 = Load2->getMachineOpcode();
4799   if (Opc1 != Opc2)
4800     return false;  // FIXME: overly conservative?
4801 
4802   switch (Opc1) {
4803   default: break;
4804   case X86::LD_Fp32m:
4805   case X86::LD_Fp64m:
4806   case X86::LD_Fp80m:
4807   case X86::MMX_MOVD64rm:
4808   case X86::MMX_MOVQ64rm:
4809     return false;
4810   }
4811 
4812   EVT VT = Load1->getValueType(0);
4813   switch (VT.getSimpleVT().SimpleTy) {
4814   default:
4815     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
4816     // have 16 of them to play with.
4817     if (TM.getSubtargetImpl()->is64Bit()) {
4818       if (NumLoads >= 3)
4819         return false;
4820     } else if (NumLoads) {
4821       return false;
4822     }
4823     break;
4824   case MVT::i8:
4825   case MVT::i16:
4826   case MVT::i32:
4827   case MVT::i64:
4828   case MVT::f32:
4829   case MVT::f64:
4830     if (NumLoads)
4831       return false;
4832     break;
4833   }
4834 
4835   return true;
4836 }
4837 
4838 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
4839                                           MachineInstr *Second) const {
4840   // Check if this processor supports macro-fusion. Since this is a minor
4841   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
4842   // proxy for SandyBridge+.
4843   if (!TM.getSubtarget<X86Subtarget>().hasAVX())
4844     return false;
4845 
4846   enum {
4847     FuseTest,
4848     FuseCmp,
4849     FuseInc
4850   } FuseKind;
4851 
4852   switch(Second->getOpcode()) {
4853   default:
4854     return false;
4855   case X86::JE_4:
4856   case X86::JNE_4:
4857   case X86::JL_4:
4858   case X86::JLE_4:
4859   case X86::JG_4:
4860   case X86::JGE_4:
4861     FuseKind = FuseInc;
4862     break;
4863   case X86::JB_4:
4864   case X86::JBE_4:
4865   case X86::JA_4:
4866   case X86::JAE_4:
4867     FuseKind = FuseCmp;
4868     break;
4869   case X86::JS_4:
4870   case X86::JNS_4:
4871   case X86::JP_4:
4872   case X86::JNP_4:
4873   case X86::JO_4:
4874   case X86::JNO_4:
4875     FuseKind = FuseTest;
4876     break;
4877   }
4878   switch (First->getOpcode()) {
4879   default:
4880     return false;
4881   case X86::TEST8rr:
4882   case X86::TEST16rr:
4883   case X86::TEST32rr:
4884   case X86::TEST64rr:
4885   case X86::TEST8ri:
4886   case X86::TEST16ri:
4887   case X86::TEST32ri:
4888   case X86::TEST32i32:
4889   case X86::TEST64i32:
4890   case X86::TEST64ri32:
4891   case X86::TEST8rm:
4892   case X86::TEST16rm:
4893   case X86::TEST32rm:
4894   case X86::TEST64rm:
4895   case X86::AND16i16:
4896   case X86::AND16ri:
4897   case X86::AND16ri8:
4898   case X86::AND16rm:
4899   case X86::AND16rr:
4900   case X86::AND32i32:
4901   case X86::AND32ri:
4902   case X86::AND32ri8:
4903   case X86::AND32rm:
4904   case X86::AND32rr:
4905   case X86::AND64i32:
4906   case X86::AND64ri32:
4907   case X86::AND64ri8:
4908   case X86::AND64rm:
4909   case X86::AND64rr:
4910   case X86::AND8i8:
4911   case X86::AND8ri:
4912   case X86::AND8rm:
4913   case X86::AND8rr:
4914     return true;
4915   case X86::CMP16i16:
4916   case X86::CMP16ri:
4917   case X86::CMP16ri8:
4918   case X86::CMP16rm:
4919   case X86::CMP16rr:
4920   case X86::CMP32i32:
4921   case X86::CMP32ri:
4922   case X86::CMP32ri8:
4923   case X86::CMP32rm:
4924   case X86::CMP32rr:
4925   case X86::CMP64i32:
4926   case X86::CMP64ri32:
4927   case X86::CMP64ri8:
4928   case X86::CMP64rm:
4929   case X86::CMP64rr:
4930   case X86::CMP8i8:
4931   case X86::CMP8ri:
4932   case X86::CMP8rm:
4933   case X86::CMP8rr:
4934   case X86::ADD16i16:
4935   case X86::ADD16ri:
4936   case X86::ADD16ri8:
4937   case X86::ADD16ri8_DB:
4938   case X86::ADD16ri_DB:
4939   case X86::ADD16rm:
4940   case X86::ADD16rr:
4941   case X86::ADD16rr_DB:
4942   case X86::ADD32i32:
4943   case X86::ADD32ri:
4944   case X86::ADD32ri8:
4945   case X86::ADD32ri8_DB:
4946   case X86::ADD32ri_DB:
4947   case X86::ADD32rm:
4948   case X86::ADD32rr:
4949   case X86::ADD32rr_DB:
4950   case X86::ADD64i32:
4951   case X86::ADD64ri32:
4952   case X86::ADD64ri32_DB:
4953   case X86::ADD64ri8:
4954   case X86::ADD64ri8_DB:
4955   case X86::ADD64rm:
4956   case X86::ADD64rr:
4957   case X86::ADD64rr_DB:
4958   case X86::ADD8i8:
4959   case X86::ADD8mi:
4960   case X86::ADD8mr:
4961   case X86::ADD8ri:
4962   case X86::ADD8rm:
4963   case X86::ADD8rr:
4964   case X86::SUB16i16:
4965   case X86::SUB16ri:
4966   case X86::SUB16ri8:
4967   case X86::SUB16rm:
4968   case X86::SUB16rr:
4969   case X86::SUB32i32:
4970   case X86::SUB32ri:
4971   case X86::SUB32ri8:
4972   case X86::SUB32rm:
4973   case X86::SUB32rr:
4974   case X86::SUB64i32:
4975   case X86::SUB64ri32:
4976   case X86::SUB64ri8:
4977   case X86::SUB64rm:
4978   case X86::SUB64rr:
4979   case X86::SUB8i8:
4980   case X86::SUB8ri:
4981   case X86::SUB8rm:
4982   case X86::SUB8rr:
4983     return FuseKind == FuseCmp || FuseKind == FuseInc;
4984   case X86::INC16r:
4985   case X86::INC32r:
4986   case X86::INC64_16r:
4987   case X86::INC64_32r:
4988   case X86::INC64r:
4989   case X86::INC8r:
4990   case X86::DEC16r:
4991   case X86::DEC32r:
4992   case X86::DEC64_16r:
4993   case X86::DEC64_32r:
4994   case X86::DEC64r:
4995   case X86::DEC8r:
4996     return FuseKind == FuseInc;
4997   }
4998 }
4999 
5000 bool X86InstrInfo::
5001 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5002   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5003   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5004   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5005     return true;
5006   Cond[0].setImm(GetOppositeBranchCondition(CC));
5007   return false;
5008 }
5009 
5010 bool X86InstrInfo::
5011 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5012   // FIXME: Return false for x87 stack register classes for now. We can't
5013   // allow any loads of these registers before FpGet_ST0_80.
5014   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5015            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
5016 }
5017 
5018 /// getGlobalBaseReg - Return a virtual register initialized with the
5019 /// the global base register value. Output instructions required to
5020 /// initialize the register in the function entry block, if necessary.
5021 ///
5022 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5023 ///
5024 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5025   assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
5026          "X86-64 PIC uses RIP relative addressing");
5027 
5028   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5029   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5030   if (GlobalBaseReg != 0)
5031     return GlobalBaseReg;
5032 
5033   // Create the register. The code to initialize it is inserted
5034   // later, by the CGBR pass (below).
5035   MachineRegisterInfo &RegInfo = MF->getRegInfo();
5036   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
5037   X86FI->setGlobalBaseReg(GlobalBaseReg);
5038   return GlobalBaseReg;
5039 }
5040 
5041 // These are the replaceable SSE instructions. Some of these have Int variants
5042 // that we don't include here. We don't want to replace instructions selected
5043 // by intrinsics.
5044 static const uint16_t ReplaceableInstrs[][3] = {
5045   //PackedSingle     PackedDouble    PackedInt
5046   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
5047   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
5048   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
5049   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
5050   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
5051   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
5052   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
5053   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
5054   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
5055   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
5056   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
5057   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
5058   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
5059   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
5060   // AVX 128-bit support
5061   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
5062   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
5063   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
5064   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
5065   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
5066   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5067   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
5068   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
5069   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
5070   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
5071   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
5072   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
5073   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
5074   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
5075   // AVX 256-bit support
5076   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
5077   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
5078   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
5079   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
5080   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
5081   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
5082 };
5083 
5084 static const uint16_t ReplaceableInstrsAVX2[][3] = {
5085   //PackedSingle       PackedDouble       PackedInt
5086   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
5087   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
5088   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
5089   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
5090   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
5091   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
5092   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
5093   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
5094   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5095   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5096   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
5097   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
5098   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
5099   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr }
5100 };
5101 
5102 // FIXME: Some shuffle and unpack instructions have equivalents in different
5103 // domains, but they require a bit more work than just switching opcodes.
5104 
5105 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
5106   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
5107     if (ReplaceableInstrs[i][domain-1] == opcode)
5108       return ReplaceableInstrs[i];
5109   return 0;
5110 }
5111 
5112 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
5113   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5114     if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5115       return ReplaceableInstrsAVX2[i];
5116   return 0;
5117 }
5118 
5119 std::pair<uint16_t, uint16_t>
5120 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
5121   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5122   bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
5123   uint16_t validDomains = 0;
5124   if (domain && lookup(MI->getOpcode(), domain))
5125     validDomains = 0xe;
5126   else if (domain && lookupAVX2(MI->getOpcode(), domain))
5127     validDomains = hasAVX2 ? 0xe : 0x6;
5128   return std::make_pair(domain, validDomains);
5129 }
5130 
5131 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
5132   assert(Domain>0 && Domain<4 && "Invalid execution domain");
5133   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5134   assert(dom && "Not an SSE instruction");
5135   const uint16_t *table = lookup(MI->getOpcode(), dom);
5136   if (!table) { // try the other table
5137     assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
5138            "256-bit vector operations only available in AVX2");
5139     table = lookupAVX2(MI->getOpcode(), dom);
5140   }
5141   assert(table && "Cannot change domain");
5142   MI->setDesc(get(table[Domain-1]));
5143 }
5144 
5145 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5146 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5147   NopInst.setOpcode(X86::NOOP);
5148 }
5149 
5150 bool X86InstrInfo::isHighLatencyDef(int opc) const {
5151   switch (opc) {
5152   default: return false;
5153   case X86::DIVSDrm:
5154   case X86::DIVSDrm_Int:
5155   case X86::DIVSDrr:
5156   case X86::DIVSDrr_Int:
5157   case X86::DIVSSrm:
5158   case X86::DIVSSrm_Int:
5159   case X86::DIVSSrr:
5160   case X86::DIVSSrr_Int:
5161   case X86::SQRTPDm:
5162   case X86::SQRTPDr:
5163   case X86::SQRTPSm:
5164   case X86::SQRTPSr:
5165   case X86::SQRTSDm:
5166   case X86::SQRTSDm_Int:
5167   case X86::SQRTSDr:
5168   case X86::SQRTSDr_Int:
5169   case X86::SQRTSSm:
5170   case X86::SQRTSSm_Int:
5171   case X86::SQRTSSr:
5172   case X86::SQRTSSr_Int:
5173   // AVX instructions with high latency
5174   case X86::VDIVSDrm:
5175   case X86::VDIVSDrm_Int:
5176   case X86::VDIVSDrr:
5177   case X86::VDIVSDrr_Int:
5178   case X86::VDIVSSrm:
5179   case X86::VDIVSSrm_Int:
5180   case X86::VDIVSSrr:
5181   case X86::VDIVSSrr_Int:
5182   case X86::VSQRTPDm:
5183   case X86::VSQRTPDr:
5184   case X86::VSQRTPSm:
5185   case X86::VSQRTPSr:
5186   case X86::VSQRTSDm:
5187   case X86::VSQRTSDm_Int:
5188   case X86::VSQRTSDr:
5189   case X86::VSQRTSSm:
5190   case X86::VSQRTSSm_Int:
5191   case X86::VSQRTSSr:
5192   case X86::VSQRTPDZrm:
5193   case X86::VSQRTPDZrr:
5194   case X86::VSQRTPSZrm:
5195   case X86::VSQRTPSZrr:
5196   case X86::VSQRTSDZm:
5197   case X86::VSQRTSDZm_Int:
5198   case X86::VSQRTSDZr:
5199   case X86::VSQRTSSZm_Int:
5200   case X86::VSQRTSSZr:
5201   case X86::VSQRTSSZm:
5202   case X86::VDIVSDZrm:
5203   case X86::VDIVSDZrr:
5204   case X86::VDIVSSZrm:
5205   case X86::VDIVSSZrr:
5206 
5207   case X86::VGATHERQPSZrm:
5208   case X86::VGATHERQPDZrm:
5209   case X86::VGATHERDPDZrm:
5210   case X86::VGATHERDPSZrm:
5211   case X86::VPGATHERQDZrm:
5212   case X86::VPGATHERQQZrm:
5213   case X86::VPGATHERDDZrm:
5214   case X86::VPGATHERDQZrm:
5215   case X86::VSCATTERQPDZmr:
5216   case X86::VSCATTERQPSZmr:
5217   case X86::VSCATTERDPDZmr:
5218   case X86::VSCATTERDPSZmr:
5219   case X86::VPSCATTERQDZmr:
5220   case X86::VPSCATTERQQZmr:
5221   case X86::VPSCATTERDDZmr:
5222   case X86::VPSCATTERDQZmr:
5223     return true;
5224   }
5225 }
5226 
5227 bool X86InstrInfo::
5228 hasHighOperandLatency(const InstrItineraryData *ItinData,
5229                       const MachineRegisterInfo *MRI,
5230                       const MachineInstr *DefMI, unsigned DefIdx,
5231                       const MachineInstr *UseMI, unsigned UseIdx) const {
5232   return isHighLatencyDef(DefMI->getOpcode());
5233 }
5234 
5235 namespace {
5236   /// CGBR - Create Global Base Reg pass. This initializes the PIC
5237   /// global base register for x86-32.
5238   struct CGBR : public MachineFunctionPass {
5239     static char ID;
5240     CGBR() : MachineFunctionPass(ID) {}
5241 
5242     virtual bool runOnMachineFunction(MachineFunction &MF) {
5243       const X86TargetMachine *TM =
5244         static_cast<const X86TargetMachine *>(&MF.getTarget());
5245 
5246       assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
5247              "X86-64 PIC uses RIP relative addressing");
5248 
5249       // Only emit a global base reg in PIC mode.
5250       if (TM->getRelocationModel() != Reloc::PIC_)
5251         return false;
5252 
5253       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
5254       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5255 
5256       // If we didn't need a GlobalBaseReg, don't insert code.
5257       if (GlobalBaseReg == 0)
5258         return false;
5259 
5260       // Insert the set of GlobalBaseReg into the first MBB of the function
5261       MachineBasicBlock &FirstMBB = MF.front();
5262       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
5263       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
5264       MachineRegisterInfo &RegInfo = MF.getRegInfo();
5265       const X86InstrInfo *TII = TM->getInstrInfo();
5266 
5267       unsigned PC;
5268       if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
5269         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
5270       else
5271         PC = GlobalBaseReg;
5272 
5273       // Operand of MovePCtoStack is completely ignored by asm printer. It's
5274       // only used in JIT code emission as displacement to pc.
5275       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
5276 
5277       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
5278       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
5279       if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
5280         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
5281         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5282           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
5283                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
5284       }
5285 
5286       return true;
5287     }
5288 
5289     virtual const char *getPassName() const {
5290       return "X86 PIC Global Base Reg Initialization";
5291     }
5292 
5293     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
5294       AU.setPreservesCFG();
5295       MachineFunctionPass::getAnalysisUsage(AU);
5296     }
5297   };
5298 }
5299 
5300 char CGBR::ID = 0;
5301 FunctionPass*
5302 llvm::createGlobalBaseRegPass() { return new CGBR(); }
5303 
5304 namespace {
5305   struct LDTLSCleanup : public MachineFunctionPass {
5306     static char ID;
5307     LDTLSCleanup() : MachineFunctionPass(ID) {}
5308 
5309     virtual bool runOnMachineFunction(MachineFunction &MF) {
5310       X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
5311       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
5312         // No point folding accesses if there isn't at least two.
5313         return false;
5314       }
5315 
5316       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
5317       return VisitNode(DT->getRootNode(), 0);
5318     }
5319 
5320     // Visit the dominator subtree rooted at Node in pre-order.
5321     // If TLSBaseAddrReg is non-null, then use that to replace any
5322     // TLS_base_addr instructions. Otherwise, create the register
5323     // when the first such instruction is seen, and then use it
5324     // as we encounter more instructions.
5325     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
5326       MachineBasicBlock *BB = Node->getBlock();
5327       bool Changed = false;
5328 
5329       // Traverse the current block.
5330       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
5331            ++I) {
5332         switch (I->getOpcode()) {
5333           case X86::TLS_base_addr32:
5334           case X86::TLS_base_addr64:
5335             if (TLSBaseAddrReg)
5336               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
5337             else
5338               I = SetRegister(I, &TLSBaseAddrReg);
5339             Changed = true;
5340             break;
5341           default:
5342             break;
5343         }
5344       }
5345 
5346       // Visit the children of this block in the dominator tree.
5347       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
5348            I != E; ++I) {
5349         Changed |= VisitNode(*I, TLSBaseAddrReg);
5350       }
5351 
5352       return Changed;
5353     }
5354 
5355     // Replace the TLS_base_addr instruction I with a copy from
5356     // TLSBaseAddrReg, returning the new instruction.
5357     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
5358                                          unsigned TLSBaseAddrReg) {
5359       MachineFunction *MF = I->getParent()->getParent();
5360       const X86TargetMachine *TM =
5361           static_cast<const X86TargetMachine *>(&MF->getTarget());
5362       const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5363       const X86InstrInfo *TII = TM->getInstrInfo();
5364 
5365       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5366       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
5367                                    TII->get(TargetOpcode::COPY),
5368                                    is64Bit ? X86::RAX : X86::EAX)
5369                                    .addReg(TLSBaseAddrReg);
5370 
5371       // Erase the TLS_base_addr instruction.
5372       I->eraseFromParent();
5373 
5374       return Copy;
5375     }
5376 
5377     // Create a virtal register in *TLSBaseAddrReg, and populate it by
5378     // inserting a copy instruction after I. Returns the new instruction.
5379     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
5380       MachineFunction *MF = I->getParent()->getParent();
5381       const X86TargetMachine *TM =
5382           static_cast<const X86TargetMachine *>(&MF->getTarget());
5383       const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5384       const X86InstrInfo *TII = TM->getInstrInfo();
5385 
5386       // Create a virtual register for the TLS base address.
5387       MachineRegisterInfo &RegInfo = MF->getRegInfo();
5388       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
5389                                                       ? &X86::GR64RegClass
5390                                                       : &X86::GR32RegClass);
5391 
5392       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
5393       MachineInstr *Next = I->getNextNode();
5394       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
5395                                    TII->get(TargetOpcode::COPY),
5396                                    *TLSBaseAddrReg)
5397                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
5398 
5399       return Copy;
5400     }
5401 
5402     virtual const char *getPassName() const {
5403       return "Local Dynamic TLS Access Clean-up";
5404     }
5405 
5406     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
5407       AU.setPreservesCFG();
5408       AU.addRequired<MachineDominatorTree>();
5409       MachineFunctionPass::getAnalysisUsage(AU);
5410     }
5411   };
5412 }
5413 
5414 char LDTLSCleanup::ID = 0;
5415 FunctionPass*
5416 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
5417