1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include <limits>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "x86-instr-info"
44 
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "X86GenInstrInfo.inc"
47 
48 static cl::opt<bool>
49 NoFusing("disable-spill-fusing",
50          cl::desc("Disable fusing of spill code into instructions"));
51 static cl::opt<bool>
52 PrintFailedFusing("print-failed-fuse-candidates",
53                   cl::desc("Print instructions that the allocator wants to"
54                            " fuse, but the X86 backend currently can't"),
55                   cl::Hidden);
56 static cl::opt<bool>
57 ReMatPICStubLoad("remat-pic-stub-load",
58                  cl::desc("Re-materialize load from stub in PIC mode"),
59                  cl::init(false), cl::Hidden);
60 
61 enum {
62   // Select which memory operand is being unfolded.
63   // (stored in bits 0 - 3)
64   TB_INDEX_0    = 0,
65   TB_INDEX_1    = 1,
66   TB_INDEX_2    = 2,
67   TB_INDEX_3    = 3,
68   TB_INDEX_MASK = 0xf,
69 
70   // Do not insert the reverse map (MemOp -> RegOp) into the table.
71   // This may be needed because there is a many -> one mapping.
72   TB_NO_REVERSE   = 1 << 4,
73 
74   // Do not insert the forward map (RegOp -> MemOp) into the table.
75   // This is needed for Native Client, which prohibits branch
76   // instructions from using a memory operand.
77   TB_NO_FORWARD   = 1 << 5,
78 
79   TB_FOLDED_LOAD  = 1 << 6,
80   TB_FOLDED_STORE = 1 << 7,
81 
82   // Minimum alignment required for load/store.
83   // Used for RegOp->MemOp conversion.
84   // (stored in bits 8 - 15)
85   TB_ALIGN_SHIFT = 8,
86   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
87   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
88   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
89   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
90   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
91 };
92 
93 struct X86OpTblEntry {
94   uint16_t RegOp;
95   uint16_t MemOp;
96   uint16_t Flags;
97 };
98 
99 // Pin the vtable to this file.
100 void X86InstrInfo::anchor() {}
101 
102 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
103     : X86GenInstrInfo(
104           (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
105           (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
106       Subtarget(STI), RI(STI) {
107 
108   static const X86OpTblEntry OpTbl2Addr[] = {
109     { X86::ADC32ri,     X86::ADC32mi,    0 },
110     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
111     { X86::ADC32rr,     X86::ADC32mr,    0 },
112     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
113     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
114     { X86::ADC64rr,     X86::ADC64mr,    0 },
115     { X86::ADD16ri,     X86::ADD16mi,    0 },
116     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
117     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
118     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
119     { X86::ADD16rr,     X86::ADD16mr,    0 },
120     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
121     { X86::ADD32ri,     X86::ADD32mi,    0 },
122     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
123     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
124     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
125     { X86::ADD32rr,     X86::ADD32mr,    0 },
126     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
127     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
128     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
129     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
130     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
131     { X86::ADD64rr,     X86::ADD64mr,    0 },
132     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
133     { X86::ADD8ri,      X86::ADD8mi,     0 },
134     { X86::ADD8rr,      X86::ADD8mr,     0 },
135     { X86::AND16ri,     X86::AND16mi,    0 },
136     { X86::AND16ri8,    X86::AND16mi8,   0 },
137     { X86::AND16rr,     X86::AND16mr,    0 },
138     { X86::AND32ri,     X86::AND32mi,    0 },
139     { X86::AND32ri8,    X86::AND32mi8,   0 },
140     { X86::AND32rr,     X86::AND32mr,    0 },
141     { X86::AND64ri32,   X86::AND64mi32,  0 },
142     { X86::AND64ri8,    X86::AND64mi8,   0 },
143     { X86::AND64rr,     X86::AND64mr,    0 },
144     { X86::AND8ri,      X86::AND8mi,     0 },
145     { X86::AND8rr,      X86::AND8mr,     0 },
146     { X86::DEC16r,      X86::DEC16m,     0 },
147     { X86::DEC32r,      X86::DEC32m,     0 },
148     { X86::DEC64_16r,   X86::DEC64_16m,  0 },
149     { X86::DEC64_32r,   X86::DEC64_32m,  0 },
150     { X86::DEC64r,      X86::DEC64m,     0 },
151     { X86::DEC8r,       X86::DEC8m,      0 },
152     { X86::INC16r,      X86::INC16m,     0 },
153     { X86::INC32r,      X86::INC32m,     0 },
154     { X86::INC64_16r,   X86::INC64_16m,  0 },
155     { X86::INC64_32r,   X86::INC64_32m,  0 },
156     { X86::INC64r,      X86::INC64m,     0 },
157     { X86::INC8r,       X86::INC8m,      0 },
158     { X86::NEG16r,      X86::NEG16m,     0 },
159     { X86::NEG32r,      X86::NEG32m,     0 },
160     { X86::NEG64r,      X86::NEG64m,     0 },
161     { X86::NEG8r,       X86::NEG8m,      0 },
162     { X86::NOT16r,      X86::NOT16m,     0 },
163     { X86::NOT32r,      X86::NOT32m,     0 },
164     { X86::NOT64r,      X86::NOT64m,     0 },
165     { X86::NOT8r,       X86::NOT8m,      0 },
166     { X86::OR16ri,      X86::OR16mi,     0 },
167     { X86::OR16ri8,     X86::OR16mi8,    0 },
168     { X86::OR16rr,      X86::OR16mr,     0 },
169     { X86::OR32ri,      X86::OR32mi,     0 },
170     { X86::OR32ri8,     X86::OR32mi8,    0 },
171     { X86::OR32rr,      X86::OR32mr,     0 },
172     { X86::OR64ri32,    X86::OR64mi32,   0 },
173     { X86::OR64ri8,     X86::OR64mi8,    0 },
174     { X86::OR64rr,      X86::OR64mr,     0 },
175     { X86::OR8ri,       X86::OR8mi,      0 },
176     { X86::OR8rr,       X86::OR8mr,      0 },
177     { X86::ROL16r1,     X86::ROL16m1,    0 },
178     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
179     { X86::ROL16ri,     X86::ROL16mi,    0 },
180     { X86::ROL32r1,     X86::ROL32m1,    0 },
181     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
182     { X86::ROL32ri,     X86::ROL32mi,    0 },
183     { X86::ROL64r1,     X86::ROL64m1,    0 },
184     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
185     { X86::ROL64ri,     X86::ROL64mi,    0 },
186     { X86::ROL8r1,      X86::ROL8m1,     0 },
187     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
188     { X86::ROL8ri,      X86::ROL8mi,     0 },
189     { X86::ROR16r1,     X86::ROR16m1,    0 },
190     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
191     { X86::ROR16ri,     X86::ROR16mi,    0 },
192     { X86::ROR32r1,     X86::ROR32m1,    0 },
193     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
194     { X86::ROR32ri,     X86::ROR32mi,    0 },
195     { X86::ROR64r1,     X86::ROR64m1,    0 },
196     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
197     { X86::ROR64ri,     X86::ROR64mi,    0 },
198     { X86::ROR8r1,      X86::ROR8m1,     0 },
199     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
200     { X86::ROR8ri,      X86::ROR8mi,     0 },
201     { X86::SAR16r1,     X86::SAR16m1,    0 },
202     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
203     { X86::SAR16ri,     X86::SAR16mi,    0 },
204     { X86::SAR32r1,     X86::SAR32m1,    0 },
205     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
206     { X86::SAR32ri,     X86::SAR32mi,    0 },
207     { X86::SAR64r1,     X86::SAR64m1,    0 },
208     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
209     { X86::SAR64ri,     X86::SAR64mi,    0 },
210     { X86::SAR8r1,      X86::SAR8m1,     0 },
211     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
212     { X86::SAR8ri,      X86::SAR8mi,     0 },
213     { X86::SBB32ri,     X86::SBB32mi,    0 },
214     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
215     { X86::SBB32rr,     X86::SBB32mr,    0 },
216     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
217     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
218     { X86::SBB64rr,     X86::SBB64mr,    0 },
219     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
220     { X86::SHL16ri,     X86::SHL16mi,    0 },
221     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
222     { X86::SHL32ri,     X86::SHL32mi,    0 },
223     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
224     { X86::SHL64ri,     X86::SHL64mi,    0 },
225     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
226     { X86::SHL8ri,      X86::SHL8mi,     0 },
227     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
228     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
229     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
230     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
231     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
232     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
233     { X86::SHR16r1,     X86::SHR16m1,    0 },
234     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
235     { X86::SHR16ri,     X86::SHR16mi,    0 },
236     { X86::SHR32r1,     X86::SHR32m1,    0 },
237     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
238     { X86::SHR32ri,     X86::SHR32mi,    0 },
239     { X86::SHR64r1,     X86::SHR64m1,    0 },
240     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
241     { X86::SHR64ri,     X86::SHR64mi,    0 },
242     { X86::SHR8r1,      X86::SHR8m1,     0 },
243     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
244     { X86::SHR8ri,      X86::SHR8mi,     0 },
245     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
246     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
247     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
248     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
249     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
250     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
251     { X86::SUB16ri,     X86::SUB16mi,    0 },
252     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
253     { X86::SUB16rr,     X86::SUB16mr,    0 },
254     { X86::SUB32ri,     X86::SUB32mi,    0 },
255     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
256     { X86::SUB32rr,     X86::SUB32mr,    0 },
257     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
258     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
259     { X86::SUB64rr,     X86::SUB64mr,    0 },
260     { X86::SUB8ri,      X86::SUB8mi,     0 },
261     { X86::SUB8rr,      X86::SUB8mr,     0 },
262     { X86::XOR16ri,     X86::XOR16mi,    0 },
263     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
264     { X86::XOR16rr,     X86::XOR16mr,    0 },
265     { X86::XOR32ri,     X86::XOR32mi,    0 },
266     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
267     { X86::XOR32rr,     X86::XOR32mr,    0 },
268     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
269     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
270     { X86::XOR64rr,     X86::XOR64mr,    0 },
271     { X86::XOR8ri,      X86::XOR8mi,     0 },
272     { X86::XOR8rr,      X86::XOR8mr,     0 }
273   };
274 
275   for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
276     unsigned RegOp = OpTbl2Addr[i].RegOp;
277     unsigned MemOp = OpTbl2Addr[i].MemOp;
278     unsigned Flags = OpTbl2Addr[i].Flags;
279     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
280                   RegOp, MemOp,
281                   // Index 0, folded load and store, no alignment requirement.
282                   Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
283   }
284 
285   static const X86OpTblEntry OpTbl0[] = {
286     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
287     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
288     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
289     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
290     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
291     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
292     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
293     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
294     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
295     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
296     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
297     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
298     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
299     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
300     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
301     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
302     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
303     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
304     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
305     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
306     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
307     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
308     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
309     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
310     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
311     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
312     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
313     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
314     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
315     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
316     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
317     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
318     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
319     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
320     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
321     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
322     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
323     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
324     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
325     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
326     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
327     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
328     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
329     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
330     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
331     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
332     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
333     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
334     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
335     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
336     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
337     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
338     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
339     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
340     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
341     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
342     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
343     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
344     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
345     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
346     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
347     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
348     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
349     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
350     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
351     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
352     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
353     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
354     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
355     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
356     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
357     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
358     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
359     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
360     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
361     // AVX 128-bit versions of foldable instructions
362     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
363     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
364     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
365     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
366     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
367     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
368     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
369     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
370     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
371     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
372     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
373     // AVX 256-bit foldable instructions
374     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
375     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
376     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
377     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
378     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
379     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
380     // AVX-512 foldable instructions
381     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
382     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
383     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
384     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
385     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
386     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
387     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
388     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
389     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
390     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
391     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
392     // AVX-512 foldable instructions (256-bit versions)
393     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
394     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
395     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
396     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
397     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
398     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
399     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
400     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
401     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
402     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
403     // AVX-512 foldable instructions (128-bit versions)
404     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
405     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
406     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
407     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
408     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
409     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
410     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
411     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
412     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
413     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE }
414   };
415 
416   for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
417     unsigned RegOp      = OpTbl0[i].RegOp;
418     unsigned MemOp      = OpTbl0[i].MemOp;
419     unsigned Flags      = OpTbl0[i].Flags;
420     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
421                   RegOp, MemOp, TB_INDEX_0 | Flags);
422   }
423 
424   static const X86OpTblEntry OpTbl1[] = {
425     { X86::CMP16rr,         X86::CMP16rm,             0 },
426     { X86::CMP32rr,         X86::CMP32rm,             0 },
427     { X86::CMP64rr,         X86::CMP64rm,             0 },
428     { X86::CMP8rr,          X86::CMP8rm,              0 },
429     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
430     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
431     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
432     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
433     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
434     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
435     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
436     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
437     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
438     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
439     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
440     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
441     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
442     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
443     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
444     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
445     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
446     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
447     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
448     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
449     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
450     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
451     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
452     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
453     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
454     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
455     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
456     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
457     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
458     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
459     { X86::MOV16rr,         X86::MOV16rm,             0 },
460     { X86::MOV32rr,         X86::MOV32rm,             0 },
461     { X86::MOV64rr,         X86::MOV64rm,             0 },
462     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
463     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
464     { X86::MOV8rr,          X86::MOV8rm,              0 },
465     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
466     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
467     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
468     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
469     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
470     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
471     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
472     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
473     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
474     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
475     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
476     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
477     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
478     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
479     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
480     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
481     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
482     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
483     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
484     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
485     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
486     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
487     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
488     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
489     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
490     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
491     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
492     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
493     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
494     { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
495     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
496     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
497     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
498     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
499     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
500     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
501     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
502     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
503     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
504     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
505     { X86::TEST16rr,        X86::TEST16rm,            0 },
506     { X86::TEST32rr,        X86::TEST32rm,            0 },
507     { X86::TEST64rr,        X86::TEST64rm,            0 },
508     { X86::TEST8rr,         X86::TEST8rm,             0 },
509     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
510     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
511     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
512     // AVX 128-bit versions of foldable instructions
513     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
514     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
515     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
516     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
517     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
518     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
519     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
520     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
521     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
522     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
523     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
524     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
525     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
526     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
527     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
528     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
529     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
530     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
531     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
532     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
533     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
534     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
535     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
536     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
537     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
538     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
539     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
540     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
541     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
542     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
543     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
544     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
545     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
546     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
547     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
548     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
549     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
550     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
551     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
552     { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
553     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
554     { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
555     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
556     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
557     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
558     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
559     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
560 
561     // AVX 256-bit foldable instructions
562     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
563     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
564     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
565     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
566     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
567     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
568     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
569     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
570     { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
571     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
572     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
573     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
574     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
575     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
576 
577     // AVX2 foldable instructions
578     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
579     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
580     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
581     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
582     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
583     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
584 
585     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
586     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
587     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
588     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
589     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
590     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
591     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
592     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
593     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
594     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
595     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
596     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
597     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
598     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
599     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
600     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
601     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
602     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
603     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
604     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
605     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
606     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
607     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
608     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
609     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
610     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
611     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
612     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
613     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
614     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
615     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
616     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
617     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
618     { X86::RORX32ri,        X86::RORX32mi,            0 },
619     { X86::RORX64ri,        X86::RORX64mi,            0 },
620     { X86::SARX32rr,        X86::SARX32rm,            0 },
621     { X86::SARX64rr,        X86::SARX64rm,            0 },
622     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
623     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
624     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
625     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
626     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
627     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
628     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
629     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
630     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
631     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
632     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
633 
634     // AVX-512 foldable instructions
635     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
636     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
637     { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
638     { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
639     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
640     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
641     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zrm,         0 },
642     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zrm,        0 },
643     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
644     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
645     { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
646     { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
647     { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
648     { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
649     // AVX-512 foldable instructions (256-bit versions)
650     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256rm,          TB_ALIGN_32 },
651     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256rm,          TB_ALIGN_32 },
652     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256rm,        TB_ALIGN_32 },
653     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256rm,        TB_ALIGN_32 },
654     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256rm,         0 },
655     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256rm,        0 },
656     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256rm,        0 },
657     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256rm,        0 },
658     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256rm,          0 },
659     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256rm,          0 },
660     // AVX-512 foldable instructions (256-bit versions)
661     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128rm,          TB_ALIGN_16 },
662     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128rm,          TB_ALIGN_16 },
663     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128rm,        TB_ALIGN_16 },
664     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128rm,        TB_ALIGN_16 },
665     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128rm,         0 },
666     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128rm,        0 },
667     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128rm,        0 },
668     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128rm,        0 },
669     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128rm,          0 },
670     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128rm,          0 },
671 
672     // AES foldable instructions
673     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
674     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
675     { X86::VAESIMCrr,             X86::VAESIMCrm,             TB_ALIGN_16 },
676     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 }
677   };
678 
679   for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
680     unsigned RegOp = OpTbl1[i].RegOp;
681     unsigned MemOp = OpTbl1[i].MemOp;
682     unsigned Flags = OpTbl1[i].Flags;
683     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
684                   RegOp, MemOp,
685                   // Index 1, folded load
686                   Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
687   }
688 
689   static const X86OpTblEntry OpTbl2[] = {
690     { X86::ADC32rr,         X86::ADC32rm,       0 },
691     { X86::ADC64rr,         X86::ADC64rm,       0 },
692     { X86::ADD16rr,         X86::ADD16rm,       0 },
693     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
694     { X86::ADD32rr,         X86::ADD32rm,       0 },
695     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
696     { X86::ADD64rr,         X86::ADD64rm,       0 },
697     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
698     { X86::ADD8rr,          X86::ADD8rm,        0 },
699     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
700     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
701     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
702     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
703     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
704     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
705     { X86::AND16rr,         X86::AND16rm,       0 },
706     { X86::AND32rr,         X86::AND32rm,       0 },
707     { X86::AND64rr,         X86::AND64rm,       0 },
708     { X86::AND8rr,          X86::AND8rm,        0 },
709     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
710     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
711     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
712     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
713     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
714     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
715     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
716     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
717     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
718     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
719     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
720     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
721     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
722     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
723     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
724     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
725     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
726     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
727     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
728     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
729     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
730     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
731     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
732     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
733     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
734     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
735     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
736     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
737     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
738     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
739     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
740     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
741     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
742     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
743     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
744     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
745     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
746     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
747     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
748     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
749     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
750     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
751     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
752     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
753     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
754     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
755     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
756     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
757     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
758     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
759     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
760     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
761     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
762     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
763     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
764     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
765     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
766     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
767     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
768     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
769     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
770     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
771     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
772     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
773     { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
774     { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
775     { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
776     { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
777     { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
778     { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
779     { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
780     { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
781     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
782     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
783     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
784     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
785     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
786     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
787     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
788     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
789     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
790     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
791     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
792     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
793     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
794     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
795     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
796     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
797     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
798     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
799     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
800     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
801     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
802     { X86::MINSDrr,         X86::MINSDrm,       0 },
803     { X86::MINSSrr,         X86::MINSSrm,       0 },
804     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
805     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
806     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
807     { X86::MULSDrr,         X86::MULSDrm,       0 },
808     { X86::MULSSrr,         X86::MULSSrm,       0 },
809     { X86::OR16rr,          X86::OR16rm,        0 },
810     { X86::OR32rr,          X86::OR32rm,        0 },
811     { X86::OR64rr,          X86::OR64rm,        0 },
812     { X86::OR8rr,           X86::OR8rm,         0 },
813     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
814     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
815     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
816     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
817     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
818     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
819     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
820     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
821     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
822     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
823     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
824     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
825     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
826     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
827     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
828     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
829     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
830     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
831     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
832     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
833     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
834     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
835     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
836     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
837     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
838     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
839     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
840     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
841     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
842     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
843     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
844     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
845     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
846     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
847     { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
848     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
849     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
850     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
851     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
852     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
853     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
854     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
855     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
856     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
857     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
858     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
859     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
860     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
861     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
862     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
863     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
864     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
865     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
866     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
867     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
868     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
869     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
870     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
871     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
872     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
873     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
874     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
875     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
876     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
877     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
878     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
879     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
880     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
881     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
882     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
883     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
884     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
885     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
886     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
887     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
888     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
889     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
890     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
891     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
892     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
893     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
894     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
895     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
896     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
897     { X86::SBB32rr,         X86::SBB32rm,       0 },
898     { X86::SBB64rr,         X86::SBB64rm,       0 },
899     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
900     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
901     { X86::SUB16rr,         X86::SUB16rm,       0 },
902     { X86::SUB32rr,         X86::SUB32rm,       0 },
903     { X86::SUB64rr,         X86::SUB64rm,       0 },
904     { X86::SUB8rr,          X86::SUB8rm,        0 },
905     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
906     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
907     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
908     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
909     // FIXME: TEST*rr -> swapped operand of TEST*mr.
910     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
911     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
912     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
913     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
914     { X86::XOR16rr,         X86::XOR16rm,       0 },
915     { X86::XOR32rr,         X86::XOR32rm,       0 },
916     { X86::XOR64rr,         X86::XOR64rm,       0 },
917     { X86::XOR8rr,          X86::XOR8rm,        0 },
918     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
919     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
920     // AVX 128-bit versions of foldable instructions
921     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
922     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
923     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
924     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
925     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
926     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
927     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
928     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
929     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
930     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
931     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
932     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
933     { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQXrm,      0 },
934     { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       0 },
935     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
936     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
937     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
938     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
939     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
940     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
941     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
942     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
943     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
944     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
945     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
946     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
947     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
948     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
949     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
950     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
951     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
952     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
953     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
954     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
955     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
956     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
957     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
958     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
959     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
960     { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
961     { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
962     { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
963     { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
964     { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
965     { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
966     { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
967     { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
968     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
969     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
970     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
971     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
972     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
973     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
974     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
975     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
976     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
977     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
978     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
979     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
980     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
981     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
982     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
983     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
984     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
985     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
986     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
987     { X86::VORPDrr,           X86::VORPDrm,            0 },
988     { X86::VORPSrr,           X86::VORPSrm,            0 },
989     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
990     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
991     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
992     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
993     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
994     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
995     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
996     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
997     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
998     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
999     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1000     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1001     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
1002     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1003     { X86::VPANDrr,           X86::VPANDrm,            0 },
1004     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1005     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1006     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1007     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1008     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1009     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1010     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1011     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1012     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1013     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1014     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1015     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1016     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1017     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1018     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1019     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1020     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1021     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1022     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1023     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1024     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1025     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1026     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1027     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1028     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1029     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1030     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1031     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1032     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1033     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1034     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1035     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1036     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1037     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1038     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1039     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1040     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1041     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1042     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1043     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1044     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1045     { X86::VPORrr,            X86::VPORrm,             0 },
1046     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1047     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1048     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
1049     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
1050     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
1051     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1052     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1053     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1054     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1055     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1056     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1057     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1058     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1059     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1060     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1061     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1062     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1063     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1064     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1065     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1066     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1067     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1068     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1069     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1070     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1071     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1072     { X86::VPXORrr,           X86::VPXORrm,            0 },
1073     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1074     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1075     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1076     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1077     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1078     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1079     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1080     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1081     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1082     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1083     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1084     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1085     // AVX 256-bit foldable instructions
1086     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1087     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1088     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1089     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1090     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1091     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1092     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1093     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1094     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1095     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1096     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1097     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1098     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1099     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1100     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1101     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1102     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1103     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1104     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1105     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1106     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1107     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1108     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1109     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1110     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1111     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1112     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1113     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1114     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1115     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1116     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1117     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1118     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1119     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1120     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1121     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1122     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1123     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1124     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1125     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1126     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1127     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1128     // AVX2 foldable instructions
1129     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1130     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1131     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1132     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1133     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1134     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1135     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1136     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1137     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1138     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1139     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1140     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1141     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1142     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1143     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1144     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1145     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1146     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1147     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1148     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1149     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1150     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1151     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1152     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1153     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1154     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1155     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1156     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1157     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1158     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1159     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1160     { X86::VPERMPDYri,        X86::VPERMPDYmi,         0 },
1161     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1162     { X86::VPERMQYri,         X86::VPERMQYmi,          0 },
1163     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1164     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1165     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1166     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1167     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1168     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1169     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1170     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1171     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1172     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1173     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1174     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1175     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1176     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1177     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1178     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1179     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1180     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1181     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1182     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1183     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1184     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1185     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1186     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1187     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1188     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1189     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1190     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1191     { X86::VPORYrr,           X86::VPORYrm,            0 },
1192     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1193     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1194     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1195     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1196     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1197     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1198     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1199     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1200     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1201     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1202     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1203     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1204     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1205     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1206     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1207     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1208     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1209     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1210     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1211     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1212     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1213     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1214     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1215     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1216     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1217     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1218     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1219     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1220     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1221     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1222     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1223     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1224     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1225     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1226     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1227     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1228     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1229     // FIXME: add AVX 256-bit foldable instructions
1230 
1231     // FMA4 foldable patterns
1232     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0           },
1233     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0           },
1234     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_16 },
1235     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_16 },
1236     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_32 },
1237     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_32 },
1238     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0           },
1239     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0           },
1240     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_16 },
1241     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_16 },
1242     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_32 },
1243     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_32 },
1244     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0           },
1245     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0           },
1246     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_16 },
1247     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_16 },
1248     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_32 },
1249     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_32 },
1250     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0           },
1251     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0           },
1252     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_16 },
1253     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_16 },
1254     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_32 },
1255     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_32 },
1256     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_16 },
1257     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_16 },
1258     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_32 },
1259     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_32 },
1260     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_16 },
1261     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_16 },
1262     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_32 },
1263     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_32 },
1264 
1265     // BMI/BMI2 foldable instructions
1266     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1267     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1268     { X86::MULX32rr,          X86::MULX32rm,            0 },
1269     { X86::MULX64rr,          X86::MULX64rm,            0 },
1270     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1271     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1272     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1273     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1274 
1275     // AVX-512 foldable instructions
1276     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1277     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1278     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1279     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1280     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1281     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1282     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1283     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1284     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1285     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1286     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1287     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1288     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1289     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1290     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1291     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1292     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1293     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1294     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1295     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1296     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1297     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1298     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1299     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1300     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1301     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1302     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1303     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1304     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1305     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1306     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1307     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1308     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1309     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1310     { X86::VALIGNQrri,        X86::VALIGNQrmi,          0 },
1311     { X86::VALIGNDrri,        X86::VALIGNDrmi,          0 },
1312     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1313 
1314     // AES foldable instructions
1315     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1316     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1317     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1318     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1319     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       TB_ALIGN_16 },
1320     { X86::VAESDECrr,         X86::VAESDECrm,           TB_ALIGN_16 },
1321     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       TB_ALIGN_16 },
1322     { X86::VAESENCrr,         X86::VAESENCrm,           TB_ALIGN_16 },
1323 
1324     // SHA foldable instructions
1325     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1326     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1327     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1328     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1329     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1330     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1331     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 },
1332   };
1333 
1334   for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1335     unsigned RegOp = OpTbl2[i].RegOp;
1336     unsigned MemOp = OpTbl2[i].MemOp;
1337     unsigned Flags = OpTbl2[i].Flags;
1338     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1339                   RegOp, MemOp,
1340                   // Index 2, folded load
1341                   Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1342   }
1343 
1344   static const X86OpTblEntry OpTbl3[] = {
1345     // FMA foldable instructions
1346     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1347     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1348     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1349     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1350     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1351     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1352 
1353     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1354     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1355     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1356     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1357     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1358     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1359     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1360     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1361     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1362     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1363     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1364     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1365 
1366     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1367     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1368     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1369     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1370     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1371     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1372 
1373     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1374     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1375     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1376     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1377     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1378     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1379     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1380     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1381     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1382     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1383     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1384     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1385 
1386     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1387     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1388     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1389     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1390     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1391     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1392 
1393     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1394     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1395     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1396     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1397     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1398     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1399     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1400     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1401     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1402     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1403     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1404     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1405 
1406     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1407     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1408     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1409     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1410     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1411     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1412 
1413     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1414     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1415     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1416     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1417     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1418     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1419     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1420     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1421     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1422     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1423     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1424     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1425 
1426     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1427     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1428     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1429     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1430     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1431     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1432     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1433     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1434     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1435     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1436     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1437     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1438 
1439     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1440     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1441     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1442     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1443     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1444     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1445     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1446     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1447     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1448     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1449     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1450     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1451 
1452     // FMA4 foldable patterns
1453     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1454     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1455     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1456     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1457     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1458     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1459     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1460     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1461     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1462     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1463     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1464     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1465     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1466     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1467     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1468     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1469     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1470     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1471     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1472     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1473     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1474     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1475     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1476     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1477     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1478     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1479     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1480     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1481     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1482     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1483     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1484     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1485     // AVX-512 VPERMI instructions with 3 source operands.
1486     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1487     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1488     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1489     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1490     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1491     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1492     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1493     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 }
1494   };
1495 
1496   for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1497     unsigned RegOp = OpTbl3[i].RegOp;
1498     unsigned MemOp = OpTbl3[i].MemOp;
1499     unsigned Flags = OpTbl3[i].Flags;
1500     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1501                   RegOp, MemOp,
1502                   // Index 3, folded load
1503                   Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1504   }
1505 
1506 }
1507 
1508 void
1509 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1510                             MemOp2RegOpTableType &M2RTable,
1511                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
1512     if ((Flags & TB_NO_FORWARD) == 0) {
1513       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1514       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1515     }
1516     if ((Flags & TB_NO_REVERSE) == 0) {
1517       assert(!M2RTable.count(MemOp) &&
1518            "Duplicated entries in unfolding maps?");
1519       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1520     }
1521 }
1522 
1523 bool
1524 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1525                                     unsigned &SrcReg, unsigned &DstReg,
1526                                     unsigned &SubIdx) const {
1527   switch (MI.getOpcode()) {
1528   default: break;
1529   case X86::MOVSX16rr8:
1530   case X86::MOVZX16rr8:
1531   case X86::MOVSX32rr8:
1532   case X86::MOVZX32rr8:
1533   case X86::MOVSX64rr8:
1534     if (!Subtarget.is64Bit())
1535       // It's not always legal to reference the low 8-bit of the larger
1536       // register in 32-bit mode.
1537       return false;
1538   case X86::MOVSX32rr16:
1539   case X86::MOVZX32rr16:
1540   case X86::MOVSX64rr16:
1541   case X86::MOVSX64rr32: {
1542     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1543       // Be conservative.
1544       return false;
1545     SrcReg = MI.getOperand(1).getReg();
1546     DstReg = MI.getOperand(0).getReg();
1547     switch (MI.getOpcode()) {
1548     default: llvm_unreachable("Unreachable!");
1549     case X86::MOVSX16rr8:
1550     case X86::MOVZX16rr8:
1551     case X86::MOVSX32rr8:
1552     case X86::MOVZX32rr8:
1553     case X86::MOVSX64rr8:
1554       SubIdx = X86::sub_8bit;
1555       break;
1556     case X86::MOVSX32rr16:
1557     case X86::MOVZX32rr16:
1558     case X86::MOVSX64rr16:
1559       SubIdx = X86::sub_16bit;
1560       break;
1561     case X86::MOVSX64rr32:
1562       SubIdx = X86::sub_32bit;
1563       break;
1564     }
1565     return true;
1566   }
1567   }
1568   return false;
1569 }
1570 
1571 /// isFrameOperand - Return true and the FrameIndex if the specified
1572 /// operand and follow operands form a reference to the stack frame.
1573 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1574                                   int &FrameIndex) const {
1575   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
1576       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
1577       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
1578       MI->getOperand(Op+X86::AddrDisp).isImm() &&
1579       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
1580       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
1581       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
1582     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
1583     return true;
1584   }
1585   return false;
1586 }
1587 
1588 static bool isFrameLoadOpcode(int Opcode) {
1589   switch (Opcode) {
1590   default:
1591     return false;
1592   case X86::MOV8rm:
1593   case X86::MOV16rm:
1594   case X86::MOV32rm:
1595   case X86::MOV64rm:
1596   case X86::LD_Fp64m:
1597   case X86::MOVSSrm:
1598   case X86::MOVSDrm:
1599   case X86::MOVAPSrm:
1600   case X86::MOVAPDrm:
1601   case X86::MOVDQArm:
1602   case X86::VMOVSSrm:
1603   case X86::VMOVSDrm:
1604   case X86::VMOVAPSrm:
1605   case X86::VMOVAPDrm:
1606   case X86::VMOVDQArm:
1607   case X86::VMOVAPSYrm:
1608   case X86::VMOVAPDYrm:
1609   case X86::VMOVDQAYrm:
1610   case X86::MMX_MOVD64rm:
1611   case X86::MMX_MOVQ64rm:
1612   case X86::VMOVAPSZrm:
1613   case X86::VMOVUPSZrm:
1614     return true;
1615   }
1616 }
1617 
1618 static bool isFrameStoreOpcode(int Opcode) {
1619   switch (Opcode) {
1620   default: break;
1621   case X86::MOV8mr:
1622   case X86::MOV16mr:
1623   case X86::MOV32mr:
1624   case X86::MOV64mr:
1625   case X86::ST_FpP64m:
1626   case X86::MOVSSmr:
1627   case X86::MOVSDmr:
1628   case X86::MOVAPSmr:
1629   case X86::MOVAPDmr:
1630   case X86::MOVDQAmr:
1631   case X86::VMOVSSmr:
1632   case X86::VMOVSDmr:
1633   case X86::VMOVAPSmr:
1634   case X86::VMOVAPDmr:
1635   case X86::VMOVDQAmr:
1636   case X86::VMOVAPSYmr:
1637   case X86::VMOVAPDYmr:
1638   case X86::VMOVDQAYmr:
1639   case X86::VMOVUPSZmr:
1640   case X86::VMOVAPSZmr:
1641   case X86::MMX_MOVD64mr:
1642   case X86::MMX_MOVQ64mr:
1643   case X86::MMX_MOVNTQmr:
1644     return true;
1645   }
1646   return false;
1647 }
1648 
1649 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1650                                            int &FrameIndex) const {
1651   if (isFrameLoadOpcode(MI->getOpcode()))
1652     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1653       return MI->getOperand(0).getReg();
1654   return 0;
1655 }
1656 
1657 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1658                                                  int &FrameIndex) const {
1659   if (isFrameLoadOpcode(MI->getOpcode())) {
1660     unsigned Reg;
1661     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1662       return Reg;
1663     // Check for post-frame index elimination operations
1664     const MachineMemOperand *Dummy;
1665     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1666   }
1667   return 0;
1668 }
1669 
1670 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1671                                           int &FrameIndex) const {
1672   if (isFrameStoreOpcode(MI->getOpcode()))
1673     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1674         isFrameOperand(MI, 0, FrameIndex))
1675       return MI->getOperand(X86::AddrNumOperands).getReg();
1676   return 0;
1677 }
1678 
1679 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1680                                                 int &FrameIndex) const {
1681   if (isFrameStoreOpcode(MI->getOpcode())) {
1682     unsigned Reg;
1683     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1684       return Reg;
1685     // Check for post-frame index elimination operations
1686     const MachineMemOperand *Dummy;
1687     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1688   }
1689   return 0;
1690 }
1691 
1692 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1693 /// X86::MOVPC32r.
1694 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1695   // Don't waste compile time scanning use-def chains of physregs.
1696   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1697     return false;
1698   bool isPICBase = false;
1699   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
1700          E = MRI.def_instr_end(); I != E; ++I) {
1701     MachineInstr *DefMI = &*I;
1702     if (DefMI->getOpcode() != X86::MOVPC32r)
1703       return false;
1704     assert(!isPICBase && "More than one PIC base?");
1705     isPICBase = true;
1706   }
1707   return isPICBase;
1708 }
1709 
1710 bool
1711 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1712                                                 AliasAnalysis *AA) const {
1713   switch (MI->getOpcode()) {
1714   default: break;
1715   case X86::MOV8rm:
1716   case X86::MOV16rm:
1717   case X86::MOV32rm:
1718   case X86::MOV64rm:
1719   case X86::LD_Fp64m:
1720   case X86::MOVSSrm:
1721   case X86::MOVSDrm:
1722   case X86::MOVAPSrm:
1723   case X86::MOVUPSrm:
1724   case X86::MOVAPDrm:
1725   case X86::MOVDQArm:
1726   case X86::MOVDQUrm:
1727   case X86::VMOVSSrm:
1728   case X86::VMOVSDrm:
1729   case X86::VMOVAPSrm:
1730   case X86::VMOVUPSrm:
1731   case X86::VMOVAPDrm:
1732   case X86::VMOVDQArm:
1733   case X86::VMOVDQUrm:
1734   case X86::VMOVAPSYrm:
1735   case X86::VMOVUPSYrm:
1736   case X86::VMOVAPDYrm:
1737   case X86::VMOVDQAYrm:
1738   case X86::VMOVDQUYrm:
1739   case X86::MMX_MOVD64rm:
1740   case X86::MMX_MOVQ64rm:
1741   case X86::FsVMOVAPSrm:
1742   case X86::FsVMOVAPDrm:
1743   case X86::FsMOVAPSrm:
1744   case X86::FsMOVAPDrm: {
1745     // Loads from constant pools are trivially rematerializable.
1746     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
1747         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1748         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1749         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1750         MI->isInvariantLoad(AA)) {
1751       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1752       if (BaseReg == 0 || BaseReg == X86::RIP)
1753         return true;
1754       // Allow re-materialization of PIC load.
1755       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
1756         return false;
1757       const MachineFunction &MF = *MI->getParent()->getParent();
1758       const MachineRegisterInfo &MRI = MF.getRegInfo();
1759       return regIsPICBase(BaseReg, MRI);
1760     }
1761     return false;
1762   }
1763 
1764   case X86::LEA32r:
1765   case X86::LEA64r: {
1766     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1767         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1768         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1769         !MI->getOperand(1+X86::AddrDisp).isReg()) {
1770       // lea fi#, lea GV, etc. are all rematerializable.
1771       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
1772         return true;
1773       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1774       if (BaseReg == 0)
1775         return true;
1776       // Allow re-materialization of lea PICBase + x.
1777       const MachineFunction &MF = *MI->getParent()->getParent();
1778       const MachineRegisterInfo &MRI = MF.getRegInfo();
1779       return regIsPICBase(BaseReg, MRI);
1780     }
1781     return false;
1782   }
1783   }
1784 
1785   // All other instructions marked M_REMATERIALIZABLE are always trivially
1786   // rematerializable.
1787   return true;
1788 }
1789 
1790 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1791                                          MachineBasicBlock::iterator I) const {
1792   MachineBasicBlock::iterator E = MBB.end();
1793 
1794   // For compile time consideration, if we are not able to determine the
1795   // safety after visiting 4 instructions in each direction, we will assume
1796   // it's not safe.
1797   MachineBasicBlock::iterator Iter = I;
1798   for (unsigned i = 0; Iter != E && i < 4; ++i) {
1799     bool SeenDef = false;
1800     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1801       MachineOperand &MO = Iter->getOperand(j);
1802       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1803         SeenDef = true;
1804       if (!MO.isReg())
1805         continue;
1806       if (MO.getReg() == X86::EFLAGS) {
1807         if (MO.isUse())
1808           return false;
1809         SeenDef = true;
1810       }
1811     }
1812 
1813     if (SeenDef)
1814       // This instruction defines EFLAGS, no need to look any further.
1815       return true;
1816     ++Iter;
1817     // Skip over DBG_VALUE.
1818     while (Iter != E && Iter->isDebugValue())
1819       ++Iter;
1820   }
1821 
1822   // It is safe to clobber EFLAGS at the end of a block of no successor has it
1823   // live in.
1824   if (Iter == E) {
1825     for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1826            SE = MBB.succ_end(); SI != SE; ++SI)
1827       if ((*SI)->isLiveIn(X86::EFLAGS))
1828         return false;
1829     return true;
1830   }
1831 
1832   MachineBasicBlock::iterator B = MBB.begin();
1833   Iter = I;
1834   for (unsigned i = 0; i < 4; ++i) {
1835     // If we make it to the beginning of the block, it's safe to clobber
1836     // EFLAGS iff EFLAGS is not live-in.
1837     if (Iter == B)
1838       return !MBB.isLiveIn(X86::EFLAGS);
1839 
1840     --Iter;
1841     // Skip over DBG_VALUE.
1842     while (Iter != B && Iter->isDebugValue())
1843       --Iter;
1844 
1845     bool SawKill = false;
1846     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1847       MachineOperand &MO = Iter->getOperand(j);
1848       // A register mask may clobber EFLAGS, but we should still look for a
1849       // live EFLAGS def.
1850       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1851         SawKill = true;
1852       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1853         if (MO.isDef()) return MO.isDead();
1854         if (MO.isKill()) SawKill = true;
1855       }
1856     }
1857 
1858     if (SawKill)
1859       // This instruction kills EFLAGS and doesn't redefine it, so
1860       // there's no need to look further.
1861       return true;
1862   }
1863 
1864   // Conservative answer.
1865   return false;
1866 }
1867 
1868 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1869                                  MachineBasicBlock::iterator I,
1870                                  unsigned DestReg, unsigned SubIdx,
1871                                  const MachineInstr *Orig,
1872                                  const TargetRegisterInfo &TRI) const {
1873   // MOV32r0 is implemented with a xor which clobbers condition code.
1874   // Re-materialize it as movri instructions to avoid side effects.
1875   unsigned Opc = Orig->getOpcode();
1876   if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
1877     DebugLoc DL = Orig->getDebugLoc();
1878     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
1879       .addImm(0);
1880   } else {
1881     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1882     MBB.insert(I, MI);
1883   }
1884 
1885   MachineInstr *NewMI = std::prev(I);
1886   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1887 }
1888 
1889 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1890 /// is not marked dead.
1891 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1892   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1893     MachineOperand &MO = MI->getOperand(i);
1894     if (MO.isReg() && MO.isDef() &&
1895         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1896       return true;
1897     }
1898   }
1899   return false;
1900 }
1901 
1902 /// getTruncatedShiftCount - check whether the shift count for a machine operand
1903 /// is non-zero.
1904 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
1905                                               unsigned ShiftAmtOperandIdx) {
1906   // The shift count is six bits with the REX.W prefix and five bits without.
1907   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1908   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
1909   return Imm & ShiftCountMask;
1910 }
1911 
1912 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
1913 /// can be represented by a LEA instruction.
1914 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1915   // Left shift instructions can be transformed into load-effective-address
1916   // instructions if we can encode them appropriately.
1917   // A LEA instruction utilizes a SIB byte to encode it's scale factor.
1918   // The SIB.scale field is two bits wide which means that we can encode any
1919   // shift amount less than 4.
1920   return ShAmt < 4 && ShAmt > 0;
1921 }
1922 
1923 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
1924                                   unsigned Opc, bool AllowSP,
1925                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
1926                                   MachineOperand &ImplicitOp) const {
1927   MachineFunction &MF = *MI->getParent()->getParent();
1928   const TargetRegisterClass *RC;
1929   if (AllowSP) {
1930     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1931   } else {
1932     RC = Opc != X86::LEA32r ?
1933       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1934   }
1935   unsigned SrcReg = Src.getReg();
1936 
1937   // For both LEA64 and LEA32 the register already has essentially the right
1938   // type (32-bit or 64-bit) we may just need to forbid SP.
1939   if (Opc != X86::LEA64_32r) {
1940     NewSrc = SrcReg;
1941     isKill = Src.isKill();
1942     isUndef = Src.isUndef();
1943 
1944     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
1945         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1946       return false;
1947 
1948     return true;
1949   }
1950 
1951   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1952   // another we need to add 64-bit registers to the final MI.
1953   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1954     ImplicitOp = Src;
1955     ImplicitOp.setImplicit();
1956 
1957     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
1958     MachineBasicBlock::LivenessQueryResult LQR =
1959       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
1960 
1961     switch (LQR) {
1962     case MachineBasicBlock::LQR_Unknown:
1963       // We can't give sane liveness flags to the instruction, abandon LEA
1964       // formation.
1965       return false;
1966     case MachineBasicBlock::LQR_Live:
1967       isKill = MI->killsRegister(SrcReg);
1968       isUndef = false;
1969       break;
1970     default:
1971       // The physreg itself is dead, so we have to use it as an <undef>.
1972       isKill = false;
1973       isUndef = true;
1974       break;
1975     }
1976   } else {
1977     // Virtual register of the wrong class, we have to create a temporary 64-bit
1978     // vreg to feed into the LEA.
1979     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1980     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1981             get(TargetOpcode::COPY))
1982       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1983         .addOperand(Src);
1984 
1985     // Which is obviously going to be dead after we're done with it.
1986     isKill = true;
1987     isUndef = false;
1988   }
1989 
1990   // We've set all the parameters without issue.
1991   return true;
1992 }
1993 
1994 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1995 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1996 /// to a 32-bit superregister and then truncating back down to a 16-bit
1997 /// subregister.
1998 MachineInstr *
1999 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2000                                            MachineFunction::iterator &MFI,
2001                                            MachineBasicBlock::iterator &MBBI,
2002                                            LiveVariables *LV) const {
2003   MachineInstr *MI = MBBI;
2004   unsigned Dest = MI->getOperand(0).getReg();
2005   unsigned Src = MI->getOperand(1).getReg();
2006   bool isDead = MI->getOperand(0).isDead();
2007   bool isKill = MI->getOperand(1).isKill();
2008 
2009   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2010   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2011   unsigned Opc, leaInReg;
2012   if (Subtarget.is64Bit()) {
2013     Opc = X86::LEA64_32r;
2014     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2015   } else {
2016     Opc = X86::LEA32r;
2017     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2018   }
2019 
2020   // Build and insert into an implicit UNDEF value. This is OK because
2021   // well be shifting and then extracting the lower 16-bits.
2022   // This has the potential to cause partial register stall. e.g.
2023   //   movw    (%rbp,%rcx,2), %dx
2024   //   leal    -65(%rdx), %esi
2025   // But testing has shown this *does* help performance in 64-bit mode (at
2026   // least on modern x86 machines).
2027   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2028   MachineInstr *InsMI =
2029     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2030     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2031     .addReg(Src, getKillRegState(isKill));
2032 
2033   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2034                                     get(Opc), leaOutReg);
2035   switch (MIOpc) {
2036   default: llvm_unreachable("Unreachable!");
2037   case X86::SHL16ri: {
2038     unsigned ShAmt = MI->getOperand(2).getImm();
2039     MIB.addReg(0).addImm(1 << ShAmt)
2040        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2041     break;
2042   }
2043   case X86::INC16r:
2044   case X86::INC64_16r:
2045     addRegOffset(MIB, leaInReg, true, 1);
2046     break;
2047   case X86::DEC16r:
2048   case X86::DEC64_16r:
2049     addRegOffset(MIB, leaInReg, true, -1);
2050     break;
2051   case X86::ADD16ri:
2052   case X86::ADD16ri8:
2053   case X86::ADD16ri_DB:
2054   case X86::ADD16ri8_DB:
2055     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2056     break;
2057   case X86::ADD16rr:
2058   case X86::ADD16rr_DB: {
2059     unsigned Src2 = MI->getOperand(2).getReg();
2060     bool isKill2 = MI->getOperand(2).isKill();
2061     unsigned leaInReg2 = 0;
2062     MachineInstr *InsMI2 = nullptr;
2063     if (Src == Src2) {
2064       // ADD16rr %reg1028<kill>, %reg1028
2065       // just a single insert_subreg.
2066       addRegReg(MIB, leaInReg, true, leaInReg, false);
2067     } else {
2068       if (Subtarget.is64Bit())
2069         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2070       else
2071         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2072       // Build and insert into an implicit UNDEF value. This is OK because
2073       // well be shifting and then extracting the lower 16-bits.
2074       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2075       InsMI2 =
2076         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2077         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2078         .addReg(Src2, getKillRegState(isKill2));
2079       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2080     }
2081     if (LV && isKill2 && InsMI2)
2082       LV->replaceKillInstruction(Src2, MI, InsMI2);
2083     break;
2084   }
2085   }
2086 
2087   MachineInstr *NewMI = MIB;
2088   MachineInstr *ExtMI =
2089     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2090     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2091     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2092 
2093   if (LV) {
2094     // Update live variables
2095     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2096     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2097     if (isKill)
2098       LV->replaceKillInstruction(Src, MI, InsMI);
2099     if (isDead)
2100       LV->replaceKillInstruction(Dest, MI, ExtMI);
2101   }
2102 
2103   return ExtMI;
2104 }
2105 
2106 /// convertToThreeAddress - This method must be implemented by targets that
2107 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2108 /// may be able to convert a two-address instruction into a true
2109 /// three-address instruction on demand.  This allows the X86 target (for
2110 /// example) to convert ADD and SHL instructions into LEA instructions if they
2111 /// would require register copies due to two-addressness.
2112 ///
2113 /// This method returns a null pointer if the transformation cannot be
2114 /// performed, otherwise it returns the new instruction.
2115 ///
2116 MachineInstr *
2117 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2118                                     MachineBasicBlock::iterator &MBBI,
2119                                     LiveVariables *LV) const {
2120   MachineInstr *MI = MBBI;
2121 
2122   // The following opcodes also sets the condition code register(s). Only
2123   // convert them to equivalent lea if the condition code register def's
2124   // are dead!
2125   if (hasLiveCondCodeDef(MI))
2126     return nullptr;
2127 
2128   MachineFunction &MF = *MI->getParent()->getParent();
2129   // All instructions input are two-addr instructions.  Get the known operands.
2130   const MachineOperand &Dest = MI->getOperand(0);
2131   const MachineOperand &Src = MI->getOperand(1);
2132 
2133   MachineInstr *NewMI = nullptr;
2134   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2135   // we have better subtarget support, enable the 16-bit LEA generation here.
2136   // 16-bit LEA is also slow on Core2.
2137   bool DisableLEA16 = true;
2138   bool is64Bit = Subtarget.is64Bit();
2139 
2140   unsigned MIOpc = MI->getOpcode();
2141   switch (MIOpc) {
2142   case X86::SHL64ri: {
2143     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2144     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2145     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2146 
2147     // LEA can't handle RSP.
2148     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2149         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2150                                            &X86::GR64_NOSPRegClass))
2151       return nullptr;
2152 
2153     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2154       .addOperand(Dest)
2155       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2156     break;
2157   }
2158   case X86::SHL32ri: {
2159     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2160     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2161     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2162 
2163     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2164 
2165     // LEA can't handle ESP.
2166     bool isKill, isUndef;
2167     unsigned SrcReg;
2168     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2169     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2170                         SrcReg, isKill, isUndef, ImplicitOp))
2171       return nullptr;
2172 
2173     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2174       .addOperand(Dest)
2175       .addReg(0).addImm(1 << ShAmt)
2176       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2177       .addImm(0).addReg(0);
2178     if (ImplicitOp.getReg() != 0)
2179       MIB.addOperand(ImplicitOp);
2180     NewMI = MIB;
2181 
2182     break;
2183   }
2184   case X86::SHL16ri: {
2185     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2186     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2187     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2188 
2189     if (DisableLEA16)
2190       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2191     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2192       .addOperand(Dest)
2193       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2194     break;
2195   }
2196   default: {
2197 
2198     switch (MIOpc) {
2199     default: return nullptr;
2200     case X86::INC64r:
2201     case X86::INC32r:
2202     case X86::INC64_32r: {
2203       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2204       unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2205         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2206       bool isKill, isUndef;
2207       unsigned SrcReg;
2208       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2209       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2210                           SrcReg, isKill, isUndef, ImplicitOp))
2211         return nullptr;
2212 
2213       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2214           .addOperand(Dest)
2215           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2216       if (ImplicitOp.getReg() != 0)
2217         MIB.addOperand(ImplicitOp);
2218 
2219       NewMI = addOffset(MIB, 1);
2220       break;
2221     }
2222     case X86::INC16r:
2223     case X86::INC64_16r:
2224       if (DisableLEA16)
2225         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2226                        : nullptr;
2227       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2228       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2229                         .addOperand(Dest).addOperand(Src), 1);
2230       break;
2231     case X86::DEC64r:
2232     case X86::DEC32r:
2233     case X86::DEC64_32r: {
2234       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2235       unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2236         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2237 
2238       bool isKill, isUndef;
2239       unsigned SrcReg;
2240       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2241       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2242                           SrcReg, isKill, isUndef, ImplicitOp))
2243         return nullptr;
2244 
2245       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2246           .addOperand(Dest)
2247           .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2248       if (ImplicitOp.getReg() != 0)
2249         MIB.addOperand(ImplicitOp);
2250 
2251       NewMI = addOffset(MIB, -1);
2252 
2253       break;
2254     }
2255     case X86::DEC16r:
2256     case X86::DEC64_16r:
2257       if (DisableLEA16)
2258         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2259                        : nullptr;
2260       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2261       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2262                         .addOperand(Dest).addOperand(Src), -1);
2263       break;
2264     case X86::ADD64rr:
2265     case X86::ADD64rr_DB:
2266     case X86::ADD32rr:
2267     case X86::ADD32rr_DB: {
2268       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2269       unsigned Opc;
2270       if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2271         Opc = X86::LEA64r;
2272       else
2273         Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2274 
2275       bool isKill, isUndef;
2276       unsigned SrcReg;
2277       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2278       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2279                           SrcReg, isKill, isUndef, ImplicitOp))
2280         return nullptr;
2281 
2282       const MachineOperand &Src2 = MI->getOperand(2);
2283       bool isKill2, isUndef2;
2284       unsigned SrcReg2;
2285       MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2286       if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2287                           SrcReg2, isKill2, isUndef2, ImplicitOp2))
2288         return nullptr;
2289 
2290       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2291         .addOperand(Dest);
2292       if (ImplicitOp.getReg() != 0)
2293         MIB.addOperand(ImplicitOp);
2294       if (ImplicitOp2.getReg() != 0)
2295         MIB.addOperand(ImplicitOp2);
2296 
2297       NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2298 
2299       // Preserve undefness of the operands.
2300       NewMI->getOperand(1).setIsUndef(isUndef);
2301       NewMI->getOperand(3).setIsUndef(isUndef2);
2302 
2303       if (LV && Src2.isKill())
2304         LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2305       break;
2306     }
2307     case X86::ADD16rr:
2308     case X86::ADD16rr_DB: {
2309       if (DisableLEA16)
2310         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2311                        : nullptr;
2312       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2313       unsigned Src2 = MI->getOperand(2).getReg();
2314       bool isKill2 = MI->getOperand(2).isKill();
2315       NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2316                         .addOperand(Dest),
2317                         Src.getReg(), Src.isKill(), Src2, isKill2);
2318 
2319       // Preserve undefness of the operands.
2320       bool isUndef = MI->getOperand(1).isUndef();
2321       bool isUndef2 = MI->getOperand(2).isUndef();
2322       NewMI->getOperand(1).setIsUndef(isUndef);
2323       NewMI->getOperand(3).setIsUndef(isUndef2);
2324 
2325       if (LV && isKill2)
2326         LV->replaceKillInstruction(Src2, MI, NewMI);
2327       break;
2328     }
2329     case X86::ADD64ri32:
2330     case X86::ADD64ri8:
2331     case X86::ADD64ri32_DB:
2332     case X86::ADD64ri8_DB:
2333       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2334       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2335                         .addOperand(Dest).addOperand(Src),
2336                         MI->getOperand(2).getImm());
2337       break;
2338     case X86::ADD32ri:
2339     case X86::ADD32ri8:
2340     case X86::ADD32ri_DB:
2341     case X86::ADD32ri8_DB: {
2342       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2343       unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2344 
2345       bool isKill, isUndef;
2346       unsigned SrcReg;
2347       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2348       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2349                           SrcReg, isKill, isUndef, ImplicitOp))
2350         return nullptr;
2351 
2352       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2353           .addOperand(Dest)
2354           .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2355       if (ImplicitOp.getReg() != 0)
2356         MIB.addOperand(ImplicitOp);
2357 
2358       NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2359       break;
2360     }
2361     case X86::ADD16ri:
2362     case X86::ADD16ri8:
2363     case X86::ADD16ri_DB:
2364     case X86::ADD16ri8_DB:
2365       if (DisableLEA16)
2366         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2367                        : nullptr;
2368       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2369       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2370                         .addOperand(Dest).addOperand(Src),
2371                         MI->getOperand(2).getImm());
2372       break;
2373     }
2374   }
2375   }
2376 
2377   if (!NewMI) return nullptr;
2378 
2379   if (LV) {  // Update live variables
2380     if (Src.isKill())
2381       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2382     if (Dest.isDead())
2383       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2384   }
2385 
2386   MFI->insert(MBBI, NewMI);          // Insert the new inst
2387   return NewMI;
2388 }
2389 
2390 /// commuteInstruction - We have a few instructions that must be hacked on to
2391 /// commute them.
2392 ///
2393 MachineInstr *
2394 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2395   switch (MI->getOpcode()) {
2396   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2397   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2398   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2399   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2400   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2401   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2402     unsigned Opc;
2403     unsigned Size;
2404     switch (MI->getOpcode()) {
2405     default: llvm_unreachable("Unreachable!");
2406     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2407     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2408     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2409     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2410     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2411     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2412     }
2413     unsigned Amt = MI->getOperand(3).getImm();
2414     if (NewMI) {
2415       MachineFunction &MF = *MI->getParent()->getParent();
2416       MI = MF.CloneMachineInstr(MI);
2417       NewMI = false;
2418     }
2419     MI->setDesc(get(Opc));
2420     MI->getOperand(3).setImm(Size-Amt);
2421     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2422   }
2423   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
2424   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2425   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
2426   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2427   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2428   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
2429   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
2430   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2431   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2432   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
2433   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
2434   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2435   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
2436   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2437   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
2438   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2439     unsigned Opc;
2440     switch (MI->getOpcode()) {
2441     default: llvm_unreachable("Unreachable!");
2442     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2443     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2444     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2445     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2446     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2447     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2448     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2449     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2450     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2451     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2452     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2453     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2454     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2455     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2456     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2457     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2458     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2459     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2460     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2461     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2462     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2463     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2464     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2465     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2466     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2467     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2468     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2469     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2470     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2471     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2472     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2473     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2474     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2475     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2476     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2477     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2478     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2479     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2480     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2481     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2482     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2483     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2484     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2485     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2486     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2487     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2488     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2489     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2490     }
2491     if (NewMI) {
2492       MachineFunction &MF = *MI->getParent()->getParent();
2493       MI = MF.CloneMachineInstr(MI);
2494       NewMI = false;
2495     }
2496     MI->setDesc(get(Opc));
2497     // Fallthrough intended.
2498   }
2499   default:
2500     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2501   }
2502 }
2503 
2504 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
2505                                          unsigned &SrcOpIdx2) const {
2506   switch (MI->getOpcode()) {
2507     case X86::VFMADDPDr231r:
2508     case X86::VFMADDPSr231r:
2509     case X86::VFMADDSDr231r:
2510     case X86::VFMADDSSr231r:
2511     case X86::VFMSUBPDr231r:
2512     case X86::VFMSUBPSr231r:
2513     case X86::VFMSUBSDr231r:
2514     case X86::VFMSUBSSr231r:
2515     case X86::VFNMADDPDr231r:
2516     case X86::VFNMADDPSr231r:
2517     case X86::VFNMADDSDr231r:
2518     case X86::VFNMADDSSr231r:
2519     case X86::VFNMSUBPDr231r:
2520     case X86::VFNMSUBPSr231r:
2521     case X86::VFNMSUBSDr231r:
2522     case X86::VFNMSUBSSr231r:
2523     case X86::VFMADDPDr231rY:
2524     case X86::VFMADDPSr231rY:
2525     case X86::VFMSUBPDr231rY:
2526     case X86::VFMSUBPSr231rY:
2527     case X86::VFNMADDPDr231rY:
2528     case X86::VFNMADDPSr231rY:
2529     case X86::VFNMSUBPDr231rY:
2530     case X86::VFNMSUBPSr231rY:
2531       SrcOpIdx1 = 2;
2532       SrcOpIdx2 = 3;
2533       return true;
2534     default:
2535       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2536   }
2537 }
2538 
2539 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2540   switch (BrOpc) {
2541   default: return X86::COND_INVALID;
2542   case X86::JE_4:  return X86::COND_E;
2543   case X86::JNE_4: return X86::COND_NE;
2544   case X86::JL_4:  return X86::COND_L;
2545   case X86::JLE_4: return X86::COND_LE;
2546   case X86::JG_4:  return X86::COND_G;
2547   case X86::JGE_4: return X86::COND_GE;
2548   case X86::JB_4:  return X86::COND_B;
2549   case X86::JBE_4: return X86::COND_BE;
2550   case X86::JA_4:  return X86::COND_A;
2551   case X86::JAE_4: return X86::COND_AE;
2552   case X86::JS_4:  return X86::COND_S;
2553   case X86::JNS_4: return X86::COND_NS;
2554   case X86::JP_4:  return X86::COND_P;
2555   case X86::JNP_4: return X86::COND_NP;
2556   case X86::JO_4:  return X86::COND_O;
2557   case X86::JNO_4: return X86::COND_NO;
2558   }
2559 }
2560 
2561 /// getCondFromSETOpc - return condition code of a SET opcode.
2562 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2563   switch (Opc) {
2564   default: return X86::COND_INVALID;
2565   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
2566   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2567   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
2568   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2569   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
2570   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
2571   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2572   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
2573   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2574   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2575   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2576   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2577   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2578   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
2579   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
2580   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
2581   }
2582 }
2583 
2584 /// getCondFromCmovOpc - return condition code of a CMov opcode.
2585 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2586   switch (Opc) {
2587   default: return X86::COND_INVALID;
2588   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
2589   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
2590     return X86::COND_A;
2591   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2592   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2593     return X86::COND_AE;
2594   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
2595   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
2596     return X86::COND_B;
2597   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2598   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2599     return X86::COND_BE;
2600   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
2601   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
2602     return X86::COND_E;
2603   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
2604   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
2605     return X86::COND_G;
2606   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2607   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2608     return X86::COND_GE;
2609   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
2610   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
2611     return X86::COND_L;
2612   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2613   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2614     return X86::COND_LE;
2615   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2616   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2617     return X86::COND_NE;
2618   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2619   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2620     return X86::COND_NO;
2621   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2622   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2623     return X86::COND_NP;
2624   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2625   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2626     return X86::COND_NS;
2627   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
2628   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
2629     return X86::COND_O;
2630   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
2631   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
2632     return X86::COND_P;
2633   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
2634   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
2635     return X86::COND_S;
2636   }
2637 }
2638 
2639 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2640   switch (CC) {
2641   default: llvm_unreachable("Illegal condition code!");
2642   case X86::COND_E:  return X86::JE_4;
2643   case X86::COND_NE: return X86::JNE_4;
2644   case X86::COND_L:  return X86::JL_4;
2645   case X86::COND_LE: return X86::JLE_4;
2646   case X86::COND_G:  return X86::JG_4;
2647   case X86::COND_GE: return X86::JGE_4;
2648   case X86::COND_B:  return X86::JB_4;
2649   case X86::COND_BE: return X86::JBE_4;
2650   case X86::COND_A:  return X86::JA_4;
2651   case X86::COND_AE: return X86::JAE_4;
2652   case X86::COND_S:  return X86::JS_4;
2653   case X86::COND_NS: return X86::JNS_4;
2654   case X86::COND_P:  return X86::JP_4;
2655   case X86::COND_NP: return X86::JNP_4;
2656   case X86::COND_O:  return X86::JO_4;
2657   case X86::COND_NO: return X86::JNO_4;
2658   }
2659 }
2660 
2661 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2662 /// e.g. turning COND_E to COND_NE.
2663 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2664   switch (CC) {
2665   default: llvm_unreachable("Illegal condition code!");
2666   case X86::COND_E:  return X86::COND_NE;
2667   case X86::COND_NE: return X86::COND_E;
2668   case X86::COND_L:  return X86::COND_GE;
2669   case X86::COND_LE: return X86::COND_G;
2670   case X86::COND_G:  return X86::COND_LE;
2671   case X86::COND_GE: return X86::COND_L;
2672   case X86::COND_B:  return X86::COND_AE;
2673   case X86::COND_BE: return X86::COND_A;
2674   case X86::COND_A:  return X86::COND_BE;
2675   case X86::COND_AE: return X86::COND_B;
2676   case X86::COND_S:  return X86::COND_NS;
2677   case X86::COND_NS: return X86::COND_S;
2678   case X86::COND_P:  return X86::COND_NP;
2679   case X86::COND_NP: return X86::COND_P;
2680   case X86::COND_O:  return X86::COND_NO;
2681   case X86::COND_NO: return X86::COND_O;
2682   }
2683 }
2684 
2685 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2686 /// the condition code if we modify the instructions such that flags are
2687 /// set by MI(b,a).
2688 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2689   switch (CC) {
2690   default: return X86::COND_INVALID;
2691   case X86::COND_E:  return X86::COND_E;
2692   case X86::COND_NE: return X86::COND_NE;
2693   case X86::COND_L:  return X86::COND_G;
2694   case X86::COND_LE: return X86::COND_GE;
2695   case X86::COND_G:  return X86::COND_L;
2696   case X86::COND_GE: return X86::COND_LE;
2697   case X86::COND_B:  return X86::COND_A;
2698   case X86::COND_BE: return X86::COND_AE;
2699   case X86::COND_A:  return X86::COND_B;
2700   case X86::COND_AE: return X86::COND_BE;
2701   }
2702 }
2703 
2704 /// getSETFromCond - Return a set opcode for the given condition and
2705 /// whether it has memory operand.
2706 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
2707   static const uint16_t Opc[16][2] = {
2708     { X86::SETAr,  X86::SETAm  },
2709     { X86::SETAEr, X86::SETAEm },
2710     { X86::SETBr,  X86::SETBm  },
2711     { X86::SETBEr, X86::SETBEm },
2712     { X86::SETEr,  X86::SETEm  },
2713     { X86::SETGr,  X86::SETGm  },
2714     { X86::SETGEr, X86::SETGEm },
2715     { X86::SETLr,  X86::SETLm  },
2716     { X86::SETLEr, X86::SETLEm },
2717     { X86::SETNEr, X86::SETNEm },
2718     { X86::SETNOr, X86::SETNOm },
2719     { X86::SETNPr, X86::SETNPm },
2720     { X86::SETNSr, X86::SETNSm },
2721     { X86::SETOr,  X86::SETOm  },
2722     { X86::SETPr,  X86::SETPm  },
2723     { X86::SETSr,  X86::SETSm  }
2724   };
2725 
2726   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
2727   return Opc[CC][HasMemoryOperand ? 1 : 0];
2728 }
2729 
2730 /// getCMovFromCond - Return a cmov opcode for the given condition,
2731 /// register size in bytes, and operand type.
2732 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
2733                               bool HasMemoryOperand) {
2734   static const uint16_t Opc[32][3] = {
2735     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
2736     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2737     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
2738     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2739     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
2740     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
2741     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2742     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
2743     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2744     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2745     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2746     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2747     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2748     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
2749     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
2750     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
2751     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
2752     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2753     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
2754     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2755     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
2756     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
2757     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2758     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
2759     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2760     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2761     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2762     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2763     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2764     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
2765     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
2766     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
2767   };
2768 
2769   assert(CC < 16 && "Can only handle standard cond codes");
2770   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2771   switch(RegBytes) {
2772   default: llvm_unreachable("Illegal register size!");
2773   case 2: return Opc[Idx][0];
2774   case 4: return Opc[Idx][1];
2775   case 8: return Opc[Idx][2];
2776   }
2777 }
2778 
2779 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2780   if (!MI->isTerminator()) return false;
2781 
2782   // Conditional branch is a special case.
2783   if (MI->isBranch() && !MI->isBarrier())
2784     return true;
2785   if (!MI->isPredicable())
2786     return true;
2787   return !isPredicated(MI);
2788 }
2789 
2790 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2791                                  MachineBasicBlock *&TBB,
2792                                  MachineBasicBlock *&FBB,
2793                                  SmallVectorImpl<MachineOperand> &Cond,
2794                                  bool AllowModify) const {
2795   // Start from the bottom of the block and work up, examining the
2796   // terminator instructions.
2797   MachineBasicBlock::iterator I = MBB.end();
2798   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2799   while (I != MBB.begin()) {
2800     --I;
2801     if (I->isDebugValue())
2802       continue;
2803 
2804     // Working from the bottom, when we see a non-terminator instruction, we're
2805     // done.
2806     if (!isUnpredicatedTerminator(I))
2807       break;
2808 
2809     // A terminator that isn't a branch can't easily be handled by this
2810     // analysis.
2811     if (!I->isBranch())
2812       return true;
2813 
2814     // Handle unconditional branches.
2815     if (I->getOpcode() == X86::JMP_4) {
2816       UnCondBrIter = I;
2817 
2818       if (!AllowModify) {
2819         TBB = I->getOperand(0).getMBB();
2820         continue;
2821       }
2822 
2823       // If the block has any instructions after a JMP, delete them.
2824       while (std::next(I) != MBB.end())
2825         std::next(I)->eraseFromParent();
2826 
2827       Cond.clear();
2828       FBB = nullptr;
2829 
2830       // Delete the JMP if it's equivalent to a fall-through.
2831       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2832         TBB = nullptr;
2833         I->eraseFromParent();
2834         I = MBB.end();
2835         UnCondBrIter = MBB.end();
2836         continue;
2837       }
2838 
2839       // TBB is used to indicate the unconditional destination.
2840       TBB = I->getOperand(0).getMBB();
2841       continue;
2842     }
2843 
2844     // Handle conditional branches.
2845     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2846     if (BranchCode == X86::COND_INVALID)
2847       return true;  // Can't handle indirect branch.
2848 
2849     // Working from the bottom, handle the first conditional branch.
2850     if (Cond.empty()) {
2851       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2852       if (AllowModify && UnCondBrIter != MBB.end() &&
2853           MBB.isLayoutSuccessor(TargetBB)) {
2854         // If we can modify the code and it ends in something like:
2855         //
2856         //     jCC L1
2857         //     jmp L2
2858         //   L1:
2859         //     ...
2860         //   L2:
2861         //
2862         // Then we can change this to:
2863         //
2864         //     jnCC L2
2865         //   L1:
2866         //     ...
2867         //   L2:
2868         //
2869         // Which is a bit more efficient.
2870         // We conditionally jump to the fall-through block.
2871         BranchCode = GetOppositeBranchCondition(BranchCode);
2872         unsigned JNCC = GetCondBranchFromCond(BranchCode);
2873         MachineBasicBlock::iterator OldInst = I;
2874 
2875         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2876           .addMBB(UnCondBrIter->getOperand(0).getMBB());
2877         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2878           .addMBB(TargetBB);
2879 
2880         OldInst->eraseFromParent();
2881         UnCondBrIter->eraseFromParent();
2882 
2883         // Restart the analysis.
2884         UnCondBrIter = MBB.end();
2885         I = MBB.end();
2886         continue;
2887       }
2888 
2889       FBB = TBB;
2890       TBB = I->getOperand(0).getMBB();
2891       Cond.push_back(MachineOperand::CreateImm(BranchCode));
2892       continue;
2893     }
2894 
2895     // Handle subsequent conditional branches. Only handle the case where all
2896     // conditional branches branch to the same destination and their condition
2897     // opcodes fit one of the special multi-branch idioms.
2898     assert(Cond.size() == 1);
2899     assert(TBB);
2900 
2901     // Only handle the case where all conditional branches branch to the same
2902     // destination.
2903     if (TBB != I->getOperand(0).getMBB())
2904       return true;
2905 
2906     // If the conditions are the same, we can leave them alone.
2907     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2908     if (OldBranchCode == BranchCode)
2909       continue;
2910 
2911     // If they differ, see if they fit one of the known patterns. Theoretically,
2912     // we could handle more patterns here, but we shouldn't expect to see them
2913     // if instruction selection has done a reasonable job.
2914     if ((OldBranchCode == X86::COND_NP &&
2915          BranchCode == X86::COND_E) ||
2916         (OldBranchCode == X86::COND_E &&
2917          BranchCode == X86::COND_NP))
2918       BranchCode = X86::COND_NP_OR_E;
2919     else if ((OldBranchCode == X86::COND_P &&
2920               BranchCode == X86::COND_NE) ||
2921              (OldBranchCode == X86::COND_NE &&
2922               BranchCode == X86::COND_P))
2923       BranchCode = X86::COND_NE_OR_P;
2924     else
2925       return true;
2926 
2927     // Update the MachineOperand.
2928     Cond[0].setImm(BranchCode);
2929   }
2930 
2931   return false;
2932 }
2933 
2934 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2935   MachineBasicBlock::iterator I = MBB.end();
2936   unsigned Count = 0;
2937 
2938   while (I != MBB.begin()) {
2939     --I;
2940     if (I->isDebugValue())
2941       continue;
2942     if (I->getOpcode() != X86::JMP_4 &&
2943         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2944       break;
2945     // Remove the branch.
2946     I->eraseFromParent();
2947     I = MBB.end();
2948     ++Count;
2949   }
2950 
2951   return Count;
2952 }
2953 
2954 unsigned
2955 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2956                            MachineBasicBlock *FBB,
2957                            const SmallVectorImpl<MachineOperand> &Cond,
2958                            DebugLoc DL) const {
2959   // Shouldn't be a fall through.
2960   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2961   assert((Cond.size() == 1 || Cond.size() == 0) &&
2962          "X86 branch conditions have one component!");
2963 
2964   if (Cond.empty()) {
2965     // Unconditional branch?
2966     assert(!FBB && "Unconditional branch with multiple successors!");
2967     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2968     return 1;
2969   }
2970 
2971   // Conditional branch.
2972   unsigned Count = 0;
2973   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2974   switch (CC) {
2975   case X86::COND_NP_OR_E:
2976     // Synthesize NP_OR_E with two branches.
2977     BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2978     ++Count;
2979     BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2980     ++Count;
2981     break;
2982   case X86::COND_NE_OR_P:
2983     // Synthesize NE_OR_P with two branches.
2984     BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2985     ++Count;
2986     BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2987     ++Count;
2988     break;
2989   default: {
2990     unsigned Opc = GetCondBranchFromCond(CC);
2991     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2992     ++Count;
2993   }
2994   }
2995   if (FBB) {
2996     // Two-way Conditional branch. Insert the second branch.
2997     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2998     ++Count;
2999   }
3000   return Count;
3001 }
3002 
3003 bool X86InstrInfo::
3004 canInsertSelect(const MachineBasicBlock &MBB,
3005                 const SmallVectorImpl<MachineOperand> &Cond,
3006                 unsigned TrueReg, unsigned FalseReg,
3007                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3008   // Not all subtargets have cmov instructions.
3009   if (!Subtarget.hasCMov())
3010     return false;
3011   if (Cond.size() != 1)
3012     return false;
3013   // We cannot do the composite conditions, at least not in SSA form.
3014   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3015     return false;
3016 
3017   // Check register classes.
3018   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3019   const TargetRegisterClass *RC =
3020     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3021   if (!RC)
3022     return false;
3023 
3024   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3025   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3026       X86::GR32RegClass.hasSubClassEq(RC) ||
3027       X86::GR64RegClass.hasSubClassEq(RC)) {
3028     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3029     // Bridge. Probably Ivy Bridge as well.
3030     CondCycles = 2;
3031     TrueCycles = 2;
3032     FalseCycles = 2;
3033     return true;
3034   }
3035 
3036   // Can't do vectors.
3037   return false;
3038 }
3039 
3040 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3041                                 MachineBasicBlock::iterator I, DebugLoc DL,
3042                                 unsigned DstReg,
3043                                 const SmallVectorImpl<MachineOperand> &Cond,
3044                                 unsigned TrueReg, unsigned FalseReg) const {
3045    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3046    assert(Cond.size() == 1 && "Invalid Cond array");
3047    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
3048                                   MRI.getRegClass(DstReg)->getSize(),
3049                                   false/*HasMemoryOperand*/);
3050    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3051 }
3052 
3053 /// isHReg - Test if the given register is a physical h register.
3054 static bool isHReg(unsigned Reg) {
3055   return X86::GR8_ABCD_HRegClass.contains(Reg);
3056 }
3057 
3058 // Try and copy between VR128/VR64 and GR64 registers.
3059 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3060                                         const X86Subtarget &Subtarget) {
3061 
3062   // SrcReg(VR128) -> DestReg(GR64)
3063   // SrcReg(VR64)  -> DestReg(GR64)
3064   // SrcReg(GR64)  -> DestReg(VR128)
3065   // SrcReg(GR64)  -> DestReg(VR64)
3066 
3067   bool HasAVX = Subtarget.hasAVX();
3068   bool HasAVX512 = Subtarget.hasAVX512();
3069   if (X86::GR64RegClass.contains(DestReg)) {
3070     if (X86::VR128XRegClass.contains(SrcReg))
3071       // Copy from a VR128 register to a GR64 register.
3072       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3073                                                X86::MOVPQIto64rr);
3074     if (X86::VR64RegClass.contains(SrcReg))
3075       // Copy from a VR64 register to a GR64 register.
3076       return X86::MOVSDto64rr;
3077   } else if (X86::GR64RegClass.contains(SrcReg)) {
3078     // Copy from a GR64 register to a VR128 register.
3079     if (X86::VR128XRegClass.contains(DestReg))
3080       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3081                                                X86::MOV64toPQIrr);
3082     // Copy from a GR64 register to a VR64 register.
3083     if (X86::VR64RegClass.contains(DestReg))
3084       return X86::MOV64toSDrr;
3085   }
3086 
3087   // SrcReg(FR32) -> DestReg(GR32)
3088   // SrcReg(GR32) -> DestReg(FR32)
3089 
3090   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3091     // Copy from a FR32 register to a GR32 register.
3092     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3093 
3094   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3095     // Copy from a GR32 register to a FR32 register.
3096     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3097   return 0;
3098 }
3099 
3100 inline static bool MaskRegClassContains(unsigned Reg) {
3101   return X86::VK8RegClass.contains(Reg) ||
3102          X86::VK16RegClass.contains(Reg) ||
3103          X86::VK32RegClass.contains(Reg) ||
3104          X86::VK64RegClass.contains(Reg) ||
3105          X86::VK1RegClass.contains(Reg);
3106 }
3107 static
3108 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3109   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3110       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3111       X86::VR512RegClass.contains(DestReg, SrcReg)) {
3112      DestReg = get512BitSuperRegister(DestReg);
3113      SrcReg = get512BitSuperRegister(SrcReg);
3114      return X86::VMOVAPSZrr;
3115   }
3116   if (MaskRegClassContains(DestReg) &&
3117       MaskRegClassContains(SrcReg))
3118     return X86::KMOVWkk;
3119   if (MaskRegClassContains(DestReg) &&
3120       (X86::GR32RegClass.contains(SrcReg) ||
3121        X86::GR16RegClass.contains(SrcReg) ||
3122        X86::GR8RegClass.contains(SrcReg))) {
3123     SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3124     return X86::KMOVWkr;
3125   }
3126   if ((X86::GR32RegClass.contains(DestReg) ||
3127        X86::GR16RegClass.contains(DestReg) ||
3128        X86::GR8RegClass.contains(DestReg)) &&
3129        MaskRegClassContains(SrcReg)) {
3130     DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3131     return X86::KMOVWrk;
3132   }
3133   return 0;
3134 }
3135 
3136 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3137                                MachineBasicBlock::iterator MI, DebugLoc DL,
3138                                unsigned DestReg, unsigned SrcReg,
3139                                bool KillSrc) const {
3140   // First deal with the normal symmetric copies.
3141   bool HasAVX = Subtarget.hasAVX();
3142   bool HasAVX512 = Subtarget.hasAVX512();
3143   unsigned Opc = 0;
3144   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3145     Opc = X86::MOV64rr;
3146   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3147     Opc = X86::MOV32rr;
3148   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3149     Opc = X86::MOV16rr;
3150   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3151     // Copying to or from a physical H register on x86-64 requires a NOREX
3152     // move.  Otherwise use a normal move.
3153     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3154         Subtarget.is64Bit()) {
3155       Opc = X86::MOV8rr_NOREX;
3156       // Both operands must be encodable without an REX prefix.
3157       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3158              "8-bit H register can not be copied outside GR8_NOREX");
3159     } else
3160       Opc = X86::MOV8rr;
3161   }
3162   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3163     Opc = X86::MMX_MOVQ64rr;
3164   else if (HasAVX512)
3165     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3166   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3167     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3168   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3169     Opc = X86::VMOVAPSYrr;
3170   if (!Opc)
3171     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3172 
3173   if (Opc) {
3174     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3175       .addReg(SrcReg, getKillRegState(KillSrc));
3176     return;
3177   }
3178 
3179   // Moving EFLAGS to / from another register requires a push and a pop.
3180   // Notice that we have to adjust the stack if we don't want to clobber the
3181   // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
3182   if (SrcReg == X86::EFLAGS) {
3183     if (X86::GR64RegClass.contains(DestReg)) {
3184       BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3185       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3186       return;
3187     }
3188     if (X86::GR32RegClass.contains(DestReg)) {
3189       BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3190       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3191       return;
3192     }
3193   }
3194   if (DestReg == X86::EFLAGS) {
3195     if (X86::GR64RegClass.contains(SrcReg)) {
3196       BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3197         .addReg(SrcReg, getKillRegState(KillSrc));
3198       BuildMI(MBB, MI, DL, get(X86::POPF64));
3199       return;
3200     }
3201     if (X86::GR32RegClass.contains(SrcReg)) {
3202       BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3203         .addReg(SrcReg, getKillRegState(KillSrc));
3204       BuildMI(MBB, MI, DL, get(X86::POPF32));
3205       return;
3206     }
3207   }
3208 
3209   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3210                << " to " << RI.getName(DestReg) << '\n');
3211   llvm_unreachable("Cannot emit physreg copy instruction");
3212 }
3213 
3214 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3215                                       const TargetRegisterClass *RC,
3216                                       bool isStackAligned,
3217                                       const X86Subtarget &STI,
3218                                       bool load) {
3219   if (STI.hasAVX512()) {
3220     if (X86::VK8RegClass.hasSubClassEq(RC)  ||
3221       X86::VK16RegClass.hasSubClassEq(RC))
3222       return load ? X86::KMOVWkm : X86::KMOVWmk;
3223     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3224       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3225     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3226       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3227     if (X86::VR512RegClass.hasSubClassEq(RC))
3228       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3229   }
3230 
3231   bool HasAVX = STI.hasAVX();
3232   switch (RC->getSize()) {
3233   default:
3234     llvm_unreachable("Unknown spill size");
3235   case 1:
3236     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3237     if (STI.is64Bit())
3238       // Copying to or from a physical H register on x86-64 requires a NOREX
3239       // move.  Otherwise use a normal move.
3240       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3241         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3242     return load ? X86::MOV8rm : X86::MOV8mr;
3243   case 2:
3244     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3245     return load ? X86::MOV16rm : X86::MOV16mr;
3246   case 4:
3247     if (X86::GR32RegClass.hasSubClassEq(RC))
3248       return load ? X86::MOV32rm : X86::MOV32mr;
3249     if (X86::FR32RegClass.hasSubClassEq(RC))
3250       return load ?
3251         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3252         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3253     if (X86::RFP32RegClass.hasSubClassEq(RC))
3254       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3255     llvm_unreachable("Unknown 4-byte regclass");
3256   case 8:
3257     if (X86::GR64RegClass.hasSubClassEq(RC))
3258       return load ? X86::MOV64rm : X86::MOV64mr;
3259     if (X86::FR64RegClass.hasSubClassEq(RC))
3260       return load ?
3261         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3262         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3263     if (X86::VR64RegClass.hasSubClassEq(RC))
3264       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3265     if (X86::RFP64RegClass.hasSubClassEq(RC))
3266       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3267     llvm_unreachable("Unknown 8-byte regclass");
3268   case 10:
3269     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3270     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3271   case 16: {
3272     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3273             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
3274     // If stack is realigned we can use aligned stores.
3275     if (isStackAligned)
3276       return load ?
3277         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3278         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3279     else
3280       return load ?
3281         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3282         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3283   }
3284   case 32:
3285     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3286             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
3287     // If stack is realigned we can use aligned stores.
3288     if (isStackAligned)
3289       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3290     else
3291       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3292   case 64:
3293     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3294     if (isStackAligned)
3295       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3296     else
3297       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3298   }
3299 }
3300 
3301 static unsigned getStoreRegOpcode(unsigned SrcReg,
3302                                   const TargetRegisterClass *RC,
3303                                   bool isStackAligned,
3304                                   const X86Subtarget &STI) {
3305   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3306 }
3307 
3308 
3309 static unsigned getLoadRegOpcode(unsigned DestReg,
3310                                  const TargetRegisterClass *RC,
3311                                  bool isStackAligned,
3312                                  const X86Subtarget &STI) {
3313   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3314 }
3315 
3316 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3317                                        MachineBasicBlock::iterator MI,
3318                                        unsigned SrcReg, bool isKill, int FrameIdx,
3319                                        const TargetRegisterClass *RC,
3320                                        const TargetRegisterInfo *TRI) const {
3321   const MachineFunction &MF = *MBB.getParent();
3322   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3323          "Stack slot too small for store");
3324   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3325   bool isAligned = (MF.getTarget()
3326                         .getSubtargetImpl()
3327                         ->getFrameLowering()
3328                         ->getStackAlignment() >= Alignment) ||
3329                    RI.canRealignStack(MF);
3330   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3331   DebugLoc DL = MBB.findDebugLoc(MI);
3332   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3333     .addReg(SrcReg, getKillRegState(isKill));
3334 }
3335 
3336 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3337                                   bool isKill,
3338                                   SmallVectorImpl<MachineOperand> &Addr,
3339                                   const TargetRegisterClass *RC,
3340                                   MachineInstr::mmo_iterator MMOBegin,
3341                                   MachineInstr::mmo_iterator MMOEnd,
3342                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
3343   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3344   bool isAligned = MMOBegin != MMOEnd &&
3345                    (*MMOBegin)->getAlignment() >= Alignment;
3346   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3347   DebugLoc DL;
3348   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3349   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3350     MIB.addOperand(Addr[i]);
3351   MIB.addReg(SrcReg, getKillRegState(isKill));
3352   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3353   NewMIs.push_back(MIB);
3354 }
3355 
3356 
3357 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3358                                         MachineBasicBlock::iterator MI,
3359                                         unsigned DestReg, int FrameIdx,
3360                                         const TargetRegisterClass *RC,
3361                                         const TargetRegisterInfo *TRI) const {
3362   const MachineFunction &MF = *MBB.getParent();
3363   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3364   bool isAligned = (MF.getTarget()
3365                         .getSubtargetImpl()
3366                         ->getFrameLowering()
3367                         ->getStackAlignment() >= Alignment) ||
3368                    RI.canRealignStack(MF);
3369   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3370   DebugLoc DL = MBB.findDebugLoc(MI);
3371   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
3372 }
3373 
3374 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
3375                                  SmallVectorImpl<MachineOperand> &Addr,
3376                                  const TargetRegisterClass *RC,
3377                                  MachineInstr::mmo_iterator MMOBegin,
3378                                  MachineInstr::mmo_iterator MMOEnd,
3379                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
3380   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3381   bool isAligned = MMOBegin != MMOEnd &&
3382                    (*MMOBegin)->getAlignment() >= Alignment;
3383   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3384   DebugLoc DL;
3385   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3386   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3387     MIB.addOperand(Addr[i]);
3388   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3389   NewMIs.push_back(MIB);
3390 }
3391 
3392 bool X86InstrInfo::
3393 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3394                int &CmpMask, int &CmpValue) const {
3395   switch (MI->getOpcode()) {
3396   default: break;
3397   case X86::CMP64ri32:
3398   case X86::CMP64ri8:
3399   case X86::CMP32ri:
3400   case X86::CMP32ri8:
3401   case X86::CMP16ri:
3402   case X86::CMP16ri8:
3403   case X86::CMP8ri:
3404     SrcReg = MI->getOperand(0).getReg();
3405     SrcReg2 = 0;
3406     CmpMask = ~0;
3407     CmpValue = MI->getOperand(1).getImm();
3408     return true;
3409   // A SUB can be used to perform comparison.
3410   case X86::SUB64rm:
3411   case X86::SUB32rm:
3412   case X86::SUB16rm:
3413   case X86::SUB8rm:
3414     SrcReg = MI->getOperand(1).getReg();
3415     SrcReg2 = 0;
3416     CmpMask = ~0;
3417     CmpValue = 0;
3418     return true;
3419   case X86::SUB64rr:
3420   case X86::SUB32rr:
3421   case X86::SUB16rr:
3422   case X86::SUB8rr:
3423     SrcReg = MI->getOperand(1).getReg();
3424     SrcReg2 = MI->getOperand(2).getReg();
3425     CmpMask = ~0;
3426     CmpValue = 0;
3427     return true;
3428   case X86::SUB64ri32:
3429   case X86::SUB64ri8:
3430   case X86::SUB32ri:
3431   case X86::SUB32ri8:
3432   case X86::SUB16ri:
3433   case X86::SUB16ri8:
3434   case X86::SUB8ri:
3435     SrcReg = MI->getOperand(1).getReg();
3436     SrcReg2 = 0;
3437     CmpMask = ~0;
3438     CmpValue = MI->getOperand(2).getImm();
3439     return true;
3440   case X86::CMP64rr:
3441   case X86::CMP32rr:
3442   case X86::CMP16rr:
3443   case X86::CMP8rr:
3444     SrcReg = MI->getOperand(0).getReg();
3445     SrcReg2 = MI->getOperand(1).getReg();
3446     CmpMask = ~0;
3447     CmpValue = 0;
3448     return true;
3449   case X86::TEST8rr:
3450   case X86::TEST16rr:
3451   case X86::TEST32rr:
3452   case X86::TEST64rr:
3453     SrcReg = MI->getOperand(0).getReg();
3454     if (MI->getOperand(1).getReg() != SrcReg) return false;
3455     // Compare against zero.
3456     SrcReg2 = 0;
3457     CmpMask = ~0;
3458     CmpValue = 0;
3459     return true;
3460   }
3461   return false;
3462 }
3463 
3464 /// isRedundantFlagInstr - check whether the first instruction, whose only
3465 /// purpose is to update flags, can be made redundant.
3466 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3467 /// This function can be extended later on.
3468 /// SrcReg, SrcRegs: register operands for FlagI.
3469 /// ImmValue: immediate for FlagI if it takes an immediate.
3470 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3471                                         unsigned SrcReg2, int ImmValue,
3472                                         MachineInstr *OI) {
3473   if (((FlagI->getOpcode() == X86::CMP64rr &&
3474         OI->getOpcode() == X86::SUB64rr) ||
3475        (FlagI->getOpcode() == X86::CMP32rr &&
3476         OI->getOpcode() == X86::SUB32rr)||
3477        (FlagI->getOpcode() == X86::CMP16rr &&
3478         OI->getOpcode() == X86::SUB16rr)||
3479        (FlagI->getOpcode() == X86::CMP8rr &&
3480         OI->getOpcode() == X86::SUB8rr)) &&
3481       ((OI->getOperand(1).getReg() == SrcReg &&
3482         OI->getOperand(2).getReg() == SrcReg2) ||
3483        (OI->getOperand(1).getReg() == SrcReg2 &&
3484         OI->getOperand(2).getReg() == SrcReg)))
3485     return true;
3486 
3487   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3488         OI->getOpcode() == X86::SUB64ri32) ||
3489        (FlagI->getOpcode() == X86::CMP64ri8 &&
3490         OI->getOpcode() == X86::SUB64ri8) ||
3491        (FlagI->getOpcode() == X86::CMP32ri &&
3492         OI->getOpcode() == X86::SUB32ri) ||
3493        (FlagI->getOpcode() == X86::CMP32ri8 &&
3494         OI->getOpcode() == X86::SUB32ri8) ||
3495        (FlagI->getOpcode() == X86::CMP16ri &&
3496         OI->getOpcode() == X86::SUB16ri) ||
3497        (FlagI->getOpcode() == X86::CMP16ri8 &&
3498         OI->getOpcode() == X86::SUB16ri8) ||
3499        (FlagI->getOpcode() == X86::CMP8ri &&
3500         OI->getOpcode() == X86::SUB8ri)) &&
3501       OI->getOperand(1).getReg() == SrcReg &&
3502       OI->getOperand(2).getImm() == ImmValue)
3503     return true;
3504   return false;
3505 }
3506 
3507 /// isDefConvertible - check whether the definition can be converted
3508 /// to remove a comparison against zero.
3509 inline static bool isDefConvertible(MachineInstr *MI) {
3510   switch (MI->getOpcode()) {
3511   default: return false;
3512 
3513   // The shift instructions only modify ZF if their shift count is non-zero.
3514   // N.B.: The processor truncates the shift count depending on the encoding.
3515   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3516   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3517      return getTruncatedShiftCount(MI, 2) != 0;
3518 
3519   // Some left shift instructions can be turned into LEA instructions but only
3520   // if their flags aren't used. Avoid transforming such instructions.
3521   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3522     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3523     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3524     return ShAmt != 0;
3525   }
3526 
3527   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3528   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3529      return getTruncatedShiftCount(MI, 3) != 0;
3530 
3531   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3532   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3533   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3534   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3535   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3536   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3537   case X86::DEC64_32r: case X86::DEC64_16r:
3538   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3539   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3540   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3541   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3542   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3543   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3544   case X86::INC64_32r: case X86::INC64_16r:
3545   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3546   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3547   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3548   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3549   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3550   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3551   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3552   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3553   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3554   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3555   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3556   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3557   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3558   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3559   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3560   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
3561   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
3562   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
3563   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
3564   case X86::ADC32ri:   case X86::ADC32ri8:
3565   case X86::ADC32rr:   case X86::ADC64ri32:
3566   case X86::ADC64ri8:  case X86::ADC64rr:
3567   case X86::SBB32ri:   case X86::SBB32ri8:
3568   case X86::SBB32rr:   case X86::SBB64ri32:
3569   case X86::SBB64ri8:  case X86::SBB64rr:
3570   case X86::ANDN32rr:  case X86::ANDN32rm:
3571   case X86::ANDN64rr:  case X86::ANDN64rm:
3572   case X86::BEXTR32rr: case X86::BEXTR64rr:
3573   case X86::BEXTR32rm: case X86::BEXTR64rm:
3574   case X86::BLSI32rr:  case X86::BLSI32rm:
3575   case X86::BLSI64rr:  case X86::BLSI64rm:
3576   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3577   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3578   case X86::BLSR32rr:  case X86::BLSR32rm:
3579   case X86::BLSR64rr:  case X86::BLSR64rm:
3580   case X86::BZHI32rr:  case X86::BZHI32rm:
3581   case X86::BZHI64rr:  case X86::BZHI64rm:
3582   case X86::LZCNT16rr: case X86::LZCNT16rm:
3583   case X86::LZCNT32rr: case X86::LZCNT32rm:
3584   case X86::LZCNT64rr: case X86::LZCNT64rm:
3585   case X86::POPCNT16rr:case X86::POPCNT16rm:
3586   case X86::POPCNT32rr:case X86::POPCNT32rm:
3587   case X86::POPCNT64rr:case X86::POPCNT64rm:
3588   case X86::TZCNT16rr: case X86::TZCNT16rm:
3589   case X86::TZCNT32rr: case X86::TZCNT32rm:
3590   case X86::TZCNT64rr: case X86::TZCNT64rm:
3591     return true;
3592   }
3593 }
3594 
3595 /// isUseDefConvertible - check whether the use can be converted
3596 /// to remove a comparison against zero.
3597 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
3598   switch (MI->getOpcode()) {
3599   default: return X86::COND_INVALID;
3600   case X86::LZCNT16rr: case X86::LZCNT16rm:
3601   case X86::LZCNT32rr: case X86::LZCNT32rm:
3602   case X86::LZCNT64rr: case X86::LZCNT64rm:
3603     return X86::COND_B;
3604   case X86::POPCNT16rr:case X86::POPCNT16rm:
3605   case X86::POPCNT32rr:case X86::POPCNT32rm:
3606   case X86::POPCNT64rr:case X86::POPCNT64rm:
3607     return X86::COND_E;
3608   case X86::TZCNT16rr: case X86::TZCNT16rm:
3609   case X86::TZCNT32rr: case X86::TZCNT32rm:
3610   case X86::TZCNT64rr: case X86::TZCNT64rm:
3611     return X86::COND_B;
3612   }
3613 }
3614 
3615 /// optimizeCompareInstr - Check if there exists an earlier instruction that
3616 /// operates on the same source operands and sets flags in the same way as
3617 /// Compare; remove Compare if possible.
3618 bool X86InstrInfo::
3619 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3620                      int CmpMask, int CmpValue,
3621                      const MachineRegisterInfo *MRI) const {
3622   // Check whether we can replace SUB with CMP.
3623   unsigned NewOpcode = 0;
3624   switch (CmpInstr->getOpcode()) {
3625   default: break;
3626   case X86::SUB64ri32:
3627   case X86::SUB64ri8:
3628   case X86::SUB32ri:
3629   case X86::SUB32ri8:
3630   case X86::SUB16ri:
3631   case X86::SUB16ri8:
3632   case X86::SUB8ri:
3633   case X86::SUB64rm:
3634   case X86::SUB32rm:
3635   case X86::SUB16rm:
3636   case X86::SUB8rm:
3637   case X86::SUB64rr:
3638   case X86::SUB32rr:
3639   case X86::SUB16rr:
3640   case X86::SUB8rr: {
3641     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3642       return false;
3643     // There is no use of the destination register, we can replace SUB with CMP.
3644     switch (CmpInstr->getOpcode()) {
3645     default: llvm_unreachable("Unreachable!");
3646     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
3647     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
3648     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
3649     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
3650     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
3651     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
3652     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
3653     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
3654     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3655     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
3656     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
3657     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
3658     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
3659     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
3660     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
3661     }
3662     CmpInstr->setDesc(get(NewOpcode));
3663     CmpInstr->RemoveOperand(0);
3664     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3665     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3666         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3667       return false;
3668   }
3669   }
3670 
3671   // Get the unique definition of SrcReg.
3672   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3673   if (!MI) return false;
3674 
3675   // CmpInstr is the first instruction of the BB.
3676   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3677 
3678   // If we are comparing against zero, check whether we can use MI to update
3679   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3680   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
3681   if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
3682     return false;
3683 
3684   // If we have a use of the source register between the def and our compare
3685   // instruction we can eliminate the compare iff the use sets EFLAGS in the
3686   // right way.
3687   bool ShouldUpdateCC = false;
3688   X86::CondCode NewCC = X86::COND_INVALID;
3689   if (IsCmpZero && !isDefConvertible(MI)) {
3690     // Scan forward from the use until we hit the use we're looking for or the
3691     // compare instruction.
3692     for (MachineBasicBlock::iterator J = MI;; ++J) {
3693       // Do we have a convertible instruction?
3694       NewCC = isUseDefConvertible(J);
3695       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3696           J->getOperand(1).getReg() == SrcReg) {
3697         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3698         ShouldUpdateCC = true; // Update CC later on.
3699         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3700         // with the new def.
3701         MI = Def = J;
3702         break;
3703       }
3704 
3705       if (J == I)
3706         return false;
3707     }
3708   }
3709 
3710   // We are searching for an earlier instruction that can make CmpInstr
3711   // redundant and that instruction will be saved in Sub.
3712   MachineInstr *Sub = nullptr;
3713   const TargetRegisterInfo *TRI = &getRegisterInfo();
3714 
3715   // We iterate backward, starting from the instruction before CmpInstr and
3716   // stop when reaching the definition of a source register or done with the BB.
3717   // RI points to the instruction before CmpInstr.
3718   // If the definition is in this basic block, RE points to the definition;
3719   // otherwise, RE is the rend of the basic block.
3720   MachineBasicBlock::reverse_iterator
3721       RI = MachineBasicBlock::reverse_iterator(I),
3722       RE = CmpInstr->getParent() == MI->getParent() ?
3723            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3724            CmpInstr->getParent()->rend();
3725   MachineInstr *Movr0Inst = nullptr;
3726   for (; RI != RE; ++RI) {
3727     MachineInstr *Instr = &*RI;
3728     // Check whether CmpInstr can be made redundant by the current instruction.
3729     if (!IsCmpZero &&
3730         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
3731       Sub = Instr;
3732       break;
3733     }
3734 
3735     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3736         Instr->readsRegister(X86::EFLAGS, TRI)) {
3737       // This instruction modifies or uses EFLAGS.
3738 
3739       // MOV32r0 etc. are implemented with xor which clobbers condition code.
3740       // They are safe to move up, if the definition to EFLAGS is dead and
3741       // earlier instructions do not read or write EFLAGS.
3742       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
3743           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3744         Movr0Inst = Instr;
3745         continue;
3746       }
3747 
3748       // We can't remove CmpInstr.
3749       return false;
3750     }
3751   }
3752 
3753   // Return false if no candidates exist.
3754   if (!IsCmpZero && !Sub)
3755     return false;
3756 
3757   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3758                     Sub->getOperand(2).getReg() == SrcReg);
3759 
3760   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3761   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3762   // If we are done with the basic block, we need to check whether EFLAGS is
3763   // live-out.
3764   bool IsSafe = false;
3765   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3766   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3767   for (++I; I != E; ++I) {
3768     const MachineInstr &Instr = *I;
3769     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3770     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3771     // We should check the usage if this instruction uses and updates EFLAGS.
3772     if (!UseEFLAGS && ModifyEFLAGS) {
3773       // It is safe to remove CmpInstr if EFLAGS is updated again.
3774       IsSafe = true;
3775       break;
3776     }
3777     if (!UseEFLAGS && !ModifyEFLAGS)
3778       continue;
3779 
3780     // EFLAGS is used by this instruction.
3781     X86::CondCode OldCC = X86::COND_INVALID;
3782     bool OpcIsSET = false;
3783     if (IsCmpZero || IsSwapped) {
3784       // We decode the condition code from opcode.
3785       if (Instr.isBranch())
3786         OldCC = getCondFromBranchOpc(Instr.getOpcode());
3787       else {
3788         OldCC = getCondFromSETOpc(Instr.getOpcode());
3789         if (OldCC != X86::COND_INVALID)
3790           OpcIsSET = true;
3791         else
3792           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3793       }
3794       if (OldCC == X86::COND_INVALID) return false;
3795     }
3796     if (IsCmpZero) {
3797       switch (OldCC) {
3798       default: break;
3799       case X86::COND_A: case X86::COND_AE:
3800       case X86::COND_B: case X86::COND_BE:
3801       case X86::COND_G: case X86::COND_GE:
3802       case X86::COND_L: case X86::COND_LE:
3803       case X86::COND_O: case X86::COND_NO:
3804         // CF and OF are used, we can't perform this optimization.
3805         return false;
3806       }
3807 
3808       // If we're updating the condition code check if we have to reverse the
3809       // condition.
3810       if (ShouldUpdateCC)
3811         switch (OldCC) {
3812         default:
3813           return false;
3814         case X86::COND_E:
3815           break;
3816         case X86::COND_NE:
3817           NewCC = GetOppositeBranchCondition(NewCC);
3818           break;
3819         }
3820     } else if (IsSwapped) {
3821       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3822       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3823       // We swap the condition code and synthesize the new opcode.
3824       NewCC = getSwappedCondition(OldCC);
3825       if (NewCC == X86::COND_INVALID) return false;
3826     }
3827 
3828     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
3829       // Synthesize the new opcode.
3830       bool HasMemoryOperand = Instr.hasOneMemOperand();
3831       unsigned NewOpc;
3832       if (Instr.isBranch())
3833         NewOpc = GetCondBranchFromCond(NewCC);
3834       else if(OpcIsSET)
3835         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3836       else {
3837         unsigned DstReg = Instr.getOperand(0).getReg();
3838         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3839                                  HasMemoryOperand);
3840       }
3841 
3842       // Push the MachineInstr to OpsToUpdate.
3843       // If it is safe to remove CmpInstr, the condition code of these
3844       // instructions will be modified.
3845       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3846     }
3847     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3848       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3849       IsSafe = true;
3850       break;
3851     }
3852   }
3853 
3854   // If EFLAGS is not killed nor re-defined, we should check whether it is
3855   // live-out. If it is live-out, do not optimize.
3856   if ((IsCmpZero || IsSwapped) && !IsSafe) {
3857     MachineBasicBlock *MBB = CmpInstr->getParent();
3858     for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
3859              SE = MBB->succ_end(); SI != SE; ++SI)
3860       if ((*SI)->isLiveIn(X86::EFLAGS))
3861         return false;
3862   }
3863 
3864   // The instruction to be updated is either Sub or MI.
3865   Sub = IsCmpZero ? MI : Sub;
3866   // Move Movr0Inst to the appropriate place before Sub.
3867   if (Movr0Inst) {
3868     // Look backwards until we find a def that doesn't use the current EFLAGS.
3869     Def = Sub;
3870     MachineBasicBlock::reverse_iterator
3871       InsertI = MachineBasicBlock::reverse_iterator(++Def),
3872                 InsertE = Sub->getParent()->rend();
3873     for (; InsertI != InsertE; ++InsertI) {
3874       MachineInstr *Instr = &*InsertI;
3875       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3876           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3877         Sub->getParent()->remove(Movr0Inst);
3878         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3879                                    Movr0Inst);
3880         break;
3881       }
3882     }
3883     if (InsertI == InsertE)
3884       return false;
3885   }
3886 
3887   // Make sure Sub instruction defines EFLAGS and mark the def live.
3888   unsigned i = 0, e = Sub->getNumOperands();
3889   for (; i != e; ++i) {
3890     MachineOperand &MO = Sub->getOperand(i);
3891     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3892       MO.setIsDead(false);
3893       break;
3894     }
3895   }
3896   assert(i != e && "Unable to locate a def EFLAGS operand");
3897 
3898   CmpInstr->eraseFromParent();
3899 
3900   // Modify the condition code of instructions in OpsToUpdate.
3901   for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
3902     OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
3903   return true;
3904 }
3905 
3906 /// optimizeLoadInstr - Try to remove the load by folding it to a register
3907 /// operand at the use. We fold the load instructions if load defines a virtual
3908 /// register, the virtual register is used once in the same BB, and the
3909 /// instructions in-between do not load or store, and have no side effects.
3910 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
3911                                               const MachineRegisterInfo *MRI,
3912                                               unsigned &FoldAsLoadDefReg,
3913                                               MachineInstr *&DefMI) const {
3914   if (FoldAsLoadDefReg == 0)
3915     return nullptr;
3916   // To be conservative, if there exists another load, clear the load candidate.
3917   if (MI->mayLoad()) {
3918     FoldAsLoadDefReg = 0;
3919     return nullptr;
3920   }
3921 
3922   // Check whether we can move DefMI here.
3923   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3924   assert(DefMI);
3925   bool SawStore = false;
3926   if (!DefMI->isSafeToMove(this, nullptr, SawStore))
3927     return nullptr;
3928 
3929   // Collect information about virtual register operands of MI.
3930   unsigned SrcOperandId = 0;
3931   bool FoundSrcOperand = false;
3932   for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
3933     MachineOperand &MO = MI->getOperand(i);
3934     if (!MO.isReg())
3935       continue;
3936     unsigned Reg = MO.getReg();
3937     if (Reg != FoldAsLoadDefReg)
3938       continue;
3939     // Do not fold if we have a subreg use or a def or multiple uses.
3940     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
3941       return nullptr;
3942 
3943     SrcOperandId = i;
3944     FoundSrcOperand = true;
3945   }
3946   if (!FoundSrcOperand)
3947     return nullptr;
3948 
3949   // Check whether we can fold the def into SrcOperandId.
3950   SmallVector<unsigned, 8> Ops;
3951   Ops.push_back(SrcOperandId);
3952   MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
3953   if (FoldMI) {
3954     FoldAsLoadDefReg = 0;
3955     return FoldMI;
3956   }
3957 
3958   return nullptr;
3959 }
3960 
3961 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
3962 /// instruction with two undef reads of the register being defined.  This is
3963 /// used for mapping:
3964 ///   %xmm4 = V_SET0
3965 /// to:
3966 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
3967 ///
3968 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3969                              const MCInstrDesc &Desc) {
3970   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3971   unsigned Reg = MIB->getOperand(0).getReg();
3972   MIB->setDesc(Desc);
3973 
3974   // MachineInstr::addOperand() will insert explicit operands before any
3975   // implicit operands.
3976   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3977   // But we don't trust that.
3978   assert(MIB->getOperand(1).getReg() == Reg &&
3979          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3980   return true;
3981 }
3982 
3983 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
3984 // code sequence is needed for other targets.
3985 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
3986                                  const TargetInstrInfo &TII) {
3987   MachineBasicBlock &MBB = *MIB->getParent();
3988   DebugLoc DL = MIB->getDebugLoc();
3989   unsigned Reg = MIB->getOperand(0).getReg();
3990   const GlobalValue *GV =
3991       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
3992   unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
3993   MachineMemOperand *MMO = MBB.getParent()->
3994       getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8);
3995   MachineBasicBlock::iterator I = MIB;
3996 
3997   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
3998       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
3999       .addMemOperand(MMO);
4000   MIB->setDebugLoc(DL);
4001   MIB->setDesc(TII.get(X86::MOV64rm));
4002   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4003 }
4004 
4005 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
4006   bool HasAVX = Subtarget.hasAVX();
4007   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4008   switch (MI->getOpcode()) {
4009   case X86::MOV32r0:
4010     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4011   case X86::SETB_C8r:
4012     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4013   case X86::SETB_C16r:
4014     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4015   case X86::SETB_C32r:
4016     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4017   case X86::SETB_C64r:
4018     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4019   case X86::V_SET0:
4020   case X86::FsFLD0SS:
4021   case X86::FsFLD0SD:
4022     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4023   case X86::AVX_SET0:
4024     assert(HasAVX && "AVX not supported");
4025     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
4026   case X86::AVX512_512_SET0:
4027     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4028   case X86::V_SETALLONES:
4029     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4030   case X86::AVX2_SETALLONES:
4031     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4032   case X86::TEST8ri_NOREX:
4033     MI->setDesc(get(X86::TEST8ri));
4034     return true;
4035   case X86::KSET0B:
4036   case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4037   case X86::KSET1B:
4038   case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
4039   case TargetOpcode::LOAD_STACK_GUARD:
4040     expandLoadStackGuard(MIB, *this);
4041     return true;
4042   }
4043   return false;
4044 }
4045 
4046 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4047                                      const SmallVectorImpl<MachineOperand> &MOs,
4048                                      MachineInstr *MI,
4049                                      const TargetInstrInfo &TII) {
4050   // Create the base instruction with the memory operand as the first part.
4051   // Omit the implicit operands, something BuildMI can't do.
4052   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4053                                               MI->getDebugLoc(), true);
4054   MachineInstrBuilder MIB(MF, NewMI);
4055   unsigned NumAddrOps = MOs.size();
4056   for (unsigned i = 0; i != NumAddrOps; ++i)
4057     MIB.addOperand(MOs[i]);
4058   if (NumAddrOps < 4)  // FrameIndex only
4059     addOffset(MIB, 0);
4060 
4061   // Loop over the rest of the ri operands, converting them over.
4062   unsigned NumOps = MI->getDesc().getNumOperands()-2;
4063   for (unsigned i = 0; i != NumOps; ++i) {
4064     MachineOperand &MO = MI->getOperand(i+2);
4065     MIB.addOperand(MO);
4066   }
4067   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4068     MachineOperand &MO = MI->getOperand(i);
4069     MIB.addOperand(MO);
4070   }
4071   return MIB;
4072 }
4073 
4074 static MachineInstr *FuseInst(MachineFunction &MF,
4075                               unsigned Opcode, unsigned OpNo,
4076                               const SmallVectorImpl<MachineOperand> &MOs,
4077                               MachineInstr *MI, const TargetInstrInfo &TII) {
4078   // Omit the implicit operands, something BuildMI can't do.
4079   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4080                                               MI->getDebugLoc(), true);
4081   MachineInstrBuilder MIB(MF, NewMI);
4082 
4083   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4084     MachineOperand &MO = MI->getOperand(i);
4085     if (i == OpNo) {
4086       assert(MO.isReg() && "Expected to fold into reg operand!");
4087       unsigned NumAddrOps = MOs.size();
4088       for (unsigned i = 0; i != NumAddrOps; ++i)
4089         MIB.addOperand(MOs[i]);
4090       if (NumAddrOps < 4)  // FrameIndex only
4091         addOffset(MIB, 0);
4092     } else {
4093       MIB.addOperand(MO);
4094     }
4095   }
4096   return MIB;
4097 }
4098 
4099 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4100                                 const SmallVectorImpl<MachineOperand> &MOs,
4101                                 MachineInstr *MI) {
4102   MachineFunction &MF = *MI->getParent()->getParent();
4103   MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
4104 
4105   unsigned NumAddrOps = MOs.size();
4106   for (unsigned i = 0; i != NumAddrOps; ++i)
4107     MIB.addOperand(MOs[i]);
4108   if (NumAddrOps < 4)  // FrameIndex only
4109     addOffset(MIB, 0);
4110   return MIB.addImm(0);
4111 }
4112 
4113 MachineInstr*
4114 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4115                                     MachineInstr *MI, unsigned i,
4116                                     const SmallVectorImpl<MachineOperand> &MOs,
4117                                     unsigned Size, unsigned Align,
4118                                     bool AllowCommute) const {
4119   const DenseMap<unsigned,
4120                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4121   bool isCallRegIndirect = Subtarget.callRegIndirect();
4122   bool isTwoAddrFold = false;
4123 
4124   // Atom favors register form of call. So, we do not fold loads into calls
4125   // when X86Subtarget is Atom.
4126   if (isCallRegIndirect &&
4127     (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
4128     return nullptr;
4129   }
4130 
4131   unsigned NumOps = MI->getDesc().getNumOperands();
4132   bool isTwoAddr = NumOps > 1 &&
4133     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4134 
4135   // FIXME: AsmPrinter doesn't know how to handle
4136   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4137   if (MI->getOpcode() == X86::ADD32ri &&
4138       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4139     return nullptr;
4140 
4141   MachineInstr *NewMI = nullptr;
4142   // Folding a memory location into the two-address part of a two-address
4143   // instruction is different than folding it other places.  It requires
4144   // replacing the *two* registers with the memory location.
4145   if (isTwoAddr && NumOps >= 2 && i < 2 &&
4146       MI->getOperand(0).isReg() &&
4147       MI->getOperand(1).isReg() &&
4148       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
4149     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4150     isTwoAddrFold = true;
4151   } else if (i == 0) { // If operand 0
4152     if (MI->getOpcode() == X86::MOV32r0) {
4153       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4154       if (NewMI)
4155         return NewMI;
4156     }
4157 
4158     OpcodeTablePtr = &RegOp2MemOpTable0;
4159   } else if (i == 1) {
4160     OpcodeTablePtr = &RegOp2MemOpTable1;
4161   } else if (i == 2) {
4162     OpcodeTablePtr = &RegOp2MemOpTable2;
4163   } else if (i == 3) {
4164     OpcodeTablePtr = &RegOp2MemOpTable3;
4165   }
4166 
4167   // If table selected...
4168   if (OpcodeTablePtr) {
4169     // Find the Opcode to fuse
4170     DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4171       OpcodeTablePtr->find(MI->getOpcode());
4172     if (I != OpcodeTablePtr->end()) {
4173       unsigned Opcode = I->second.first;
4174       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4175       if (Align < MinAlign)
4176         return nullptr;
4177       bool NarrowToMOV32rm = false;
4178       if (Size) {
4179         unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
4180         if (Size < RCSize) {
4181           // Check if it's safe to fold the load. If the size of the object is
4182           // narrower than the load width, then it's not.
4183           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4184             return nullptr;
4185           // If this is a 64-bit load, but the spill slot is 32, then we can do
4186           // a 32-bit load which is implicitly zero-extended. This likely is
4187           // due to live interval analysis remat'ing a load from stack slot.
4188           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4189             return nullptr;
4190           Opcode = X86::MOV32rm;
4191           NarrowToMOV32rm = true;
4192         }
4193       }
4194 
4195       if (isTwoAddrFold)
4196         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
4197       else
4198         NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
4199 
4200       if (NarrowToMOV32rm) {
4201         // If this is the special case where we use a MOV32rm to load a 32-bit
4202         // value and zero-extend the top bits. Change the destination register
4203         // to a 32-bit one.
4204         unsigned DstReg = NewMI->getOperand(0).getReg();
4205         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4206           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4207         else
4208           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4209       }
4210       return NewMI;
4211     }
4212   }
4213 
4214   // If the instruction and target operand are commutable, commute the
4215   // instruction and try again.
4216   if (AllowCommute) {
4217     unsigned OriginalOpIdx = i, CommuteOpIdx1, CommuteOpIdx2;
4218     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4219       bool HasDef = MI->getDesc().getNumDefs();
4220       unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
4221       unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
4222       unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
4223       bool Tied0 =
4224           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4225       bool Tied1 =
4226           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4227 
4228       // If either of the commutable operands are tied to the destination
4229       // then we can not commute + fold.
4230       if ((HasDef && Reg0 == Reg1 && Tied0) ||
4231           (HasDef && Reg0 == Reg2 && Tied1))
4232         return nullptr;
4233 
4234       if ((CommuteOpIdx1 == OriginalOpIdx) ||
4235           (CommuteOpIdx2 == OriginalOpIdx)) {
4236         MachineInstr *CommutedMI = commuteInstruction(MI, false);
4237         if (!CommutedMI) {
4238           // Unable to commute.
4239           return nullptr;
4240         }
4241         if (CommutedMI != MI) {
4242           // New instruction. We can't fold from this.
4243           CommutedMI->eraseFromParent();
4244           return nullptr;
4245         }
4246 
4247         // Attempt to fold with the commuted version of the instruction.
4248         unsigned CommuteOp =
4249             (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1);
4250         NewMI = foldMemoryOperandImpl(MF, MI, CommuteOp, MOs, Size, Align,
4251                                       /*AllowCommute=*/false);
4252         if (NewMI)
4253           return NewMI;
4254 
4255         // Folding failed again - undo the commute before returning.
4256         MachineInstr *UncommutedMI = commuteInstruction(MI, false);
4257         if (!UncommutedMI) {
4258           // Unable to commute.
4259           return nullptr;
4260         }
4261         if (UncommutedMI != MI) {
4262           // New instruction. It doesn't need to be kept.
4263           UncommutedMI->eraseFromParent();
4264           return nullptr;
4265         }
4266 
4267         // Return here to prevent duplicate fuse failure report.
4268         return nullptr;
4269       }
4270     }
4271   }
4272 
4273   // No fusion
4274   if (PrintFailedFusing && !MI->isCopy())
4275     dbgs() << "We failed to fuse operand " << i << " in " << *MI;
4276   return nullptr;
4277 }
4278 
4279 /// hasPartialRegUpdate - Return true for all instructions that only update
4280 /// the first 32 or 64-bits of the destination register and leave the rest
4281 /// unmodified. This can be used to avoid folding loads if the instructions
4282 /// only update part of the destination register, and the non-updated part is
4283 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4284 /// instructions breaks the partial register dependency and it can improve
4285 /// performance. e.g.:
4286 ///
4287 ///   movss (%rdi), %xmm0
4288 ///   cvtss2sd %xmm0, %xmm0
4289 ///
4290 /// Instead of
4291 ///   cvtss2sd (%rdi), %xmm0
4292 ///
4293 /// FIXME: This should be turned into a TSFlags.
4294 ///
4295 static bool hasPartialRegUpdate(unsigned Opcode) {
4296   switch (Opcode) {
4297   case X86::CVTSI2SSrr:
4298   case X86::CVTSI2SS64rr:
4299   case X86::CVTSI2SDrr:
4300   case X86::CVTSI2SD64rr:
4301   case X86::CVTSD2SSrr:
4302   case X86::Int_CVTSD2SSrr:
4303   case X86::CVTSS2SDrr:
4304   case X86::Int_CVTSS2SDrr:
4305   case X86::RCPSSr:
4306   case X86::RCPSSr_Int:
4307   case X86::ROUNDSDr:
4308   case X86::ROUNDSDr_Int:
4309   case X86::ROUNDSSr:
4310   case X86::ROUNDSSr_Int:
4311   case X86::RSQRTSSr:
4312   case X86::RSQRTSSr_Int:
4313   case X86::SQRTSSr:
4314   case X86::SQRTSSr_Int:
4315     return true;
4316   }
4317 
4318   return false;
4319 }
4320 
4321 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4322 /// instructions we would like before a partial register update.
4323 unsigned X86InstrInfo::
4324 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4325                              const TargetRegisterInfo *TRI) const {
4326   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4327     return 0;
4328 
4329   // If MI is marked as reading Reg, the partial register update is wanted.
4330   const MachineOperand &MO = MI->getOperand(0);
4331   unsigned Reg = MO.getReg();
4332   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4333     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4334       return 0;
4335   } else {
4336     if (MI->readsRegister(Reg, TRI))
4337       return 0;
4338   }
4339 
4340   // If any of the preceding 16 instructions are reading Reg, insert a
4341   // dependency breaking instruction.  The magic number is based on a few
4342   // Nehalem experiments.
4343   return 16;
4344 }
4345 
4346 // Return true for any instruction the copies the high bits of the first source
4347 // operand into the unused high bits of the destination operand.
4348 static bool hasUndefRegUpdate(unsigned Opcode) {
4349   switch (Opcode) {
4350   case X86::VCVTSI2SSrr:
4351   case X86::Int_VCVTSI2SSrr:
4352   case X86::VCVTSI2SS64rr:
4353   case X86::Int_VCVTSI2SS64rr:
4354   case X86::VCVTSI2SDrr:
4355   case X86::Int_VCVTSI2SDrr:
4356   case X86::VCVTSI2SD64rr:
4357   case X86::Int_VCVTSI2SD64rr:
4358   case X86::VCVTSD2SSrr:
4359   case X86::Int_VCVTSD2SSrr:
4360   case X86::VCVTSS2SDrr:
4361   case X86::Int_VCVTSS2SDrr:
4362   case X86::VRCPSSr:
4363   case X86::VROUNDSDr:
4364   case X86::VROUNDSDr_Int:
4365   case X86::VROUNDSSr:
4366   case X86::VROUNDSSr_Int:
4367   case X86::VRSQRTSSr:
4368   case X86::VSQRTSSr:
4369 
4370   // AVX-512
4371   case X86::VCVTSD2SSZrr:
4372   case X86::VCVTSS2SDZrr:
4373     return true;
4374   }
4375 
4376   return false;
4377 }
4378 
4379 /// Inform the ExeDepsFix pass how many idle instructions we would like before
4380 /// certain undef register reads.
4381 ///
4382 /// This catches the VCVTSI2SD family of instructions:
4383 ///
4384 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4385 ///
4386 /// We should to be careful *not* to catch VXOR idioms which are presumably
4387 /// handled specially in the pipeline:
4388 ///
4389 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4390 ///
4391 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4392 /// high bits that are passed-through are not live.
4393 unsigned X86InstrInfo::
4394 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4395                      const TargetRegisterInfo *TRI) const {
4396   if (!hasUndefRegUpdate(MI->getOpcode()))
4397     return 0;
4398 
4399   // Set the OpNum parameter to the first source operand.
4400   OpNum = 1;
4401 
4402   const MachineOperand &MO = MI->getOperand(OpNum);
4403   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4404     // Use the same magic number as getPartialRegUpdateClearance.
4405     return 16;
4406   }
4407   return 0;
4408 }
4409 
4410 void X86InstrInfo::
4411 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4412                           const TargetRegisterInfo *TRI) const {
4413   unsigned Reg = MI->getOperand(OpNum).getReg();
4414   // If MI kills this register, the false dependence is already broken.
4415   if (MI->killsRegister(Reg, TRI))
4416     return;
4417   if (X86::VR128RegClass.contains(Reg)) {
4418     // These instructions are all floating point domain, so xorps is the best
4419     // choice.
4420     bool HasAVX = Subtarget.hasAVX();
4421     unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4422     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4423       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4424   } else if (X86::VR256RegClass.contains(Reg)) {
4425     // Use vxorps to clear the full ymm register.
4426     // It wants to read and write the xmm sub-register.
4427     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4428     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4429       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4430       .addReg(Reg, RegState::ImplicitDefine);
4431   } else
4432     return;
4433   MI->addRegisterKilled(Reg, TRI, true);
4434 }
4435 
4436 MachineInstr*
4437 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4438                                     const SmallVectorImpl<unsigned> &Ops,
4439                                     int FrameIndex) const {
4440   // Check switch flag
4441   if (NoFusing) return nullptr;
4442 
4443   // Unless optimizing for size, don't fold to avoid partial
4444   // register update stalls
4445   if (!MF.getFunction()->getAttributes().
4446         hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4447       hasPartialRegUpdate(MI->getOpcode()))
4448     return nullptr;
4449 
4450   const MachineFrameInfo *MFI = MF.getFrameInfo();
4451   unsigned Size = MFI->getObjectSize(FrameIndex);
4452   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
4453   // If the function stack isn't realigned we don't want to fold instructions
4454   // that need increased alignment.
4455   if (!RI.needsStackRealignment(MF))
4456     Alignment = std::min(Alignment, MF.getTarget()
4457                                         .getSubtargetImpl()
4458                                         ->getFrameLowering()
4459                                         ->getStackAlignment());
4460   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4461     unsigned NewOpc = 0;
4462     unsigned RCSize = 0;
4463     switch (MI->getOpcode()) {
4464     default: return nullptr;
4465     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
4466     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4467     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4468     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4469     }
4470     // Check if it's safe to fold the load. If the size of the object is
4471     // narrower than the load width, then it's not.
4472     if (Size < RCSize)
4473       return nullptr;
4474     // Change to CMPXXri r, 0 first.
4475     MI->setDesc(get(NewOpc));
4476     MI->getOperand(1).ChangeToImmediate(0);
4477   } else if (Ops.size() != 1)
4478     return nullptr;
4479 
4480   SmallVector<MachineOperand,4> MOs;
4481   MOs.push_back(MachineOperand::CreateFI(FrameIndex));
4482   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
4483                                Size, Alignment, /*AllowCommute=*/true);
4484 }
4485 
4486 static bool isPartialRegisterLoad(const MachineInstr &LoadMI,
4487                                   const MachineFunction &MF) {
4488   unsigned Opc = LoadMI.getOpcode();
4489   unsigned RegSize =
4490       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
4491 
4492   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
4493     // These instructions only load 32 bits, we can't fold them if the
4494     // destination register is wider than 32 bits (4 bytes).
4495     return true;
4496 
4497   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
4498     // These instructions only load 64 bits, we can't fold them if the
4499     // destination register is wider than 64 bits (8 bytes).
4500     return true;
4501 
4502   return false;
4503 }
4504 
4505 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4506                                                   MachineInstr *MI,
4507                                            const SmallVectorImpl<unsigned> &Ops,
4508                                                   MachineInstr *LoadMI) const {
4509   // If loading from a FrameIndex, fold directly from the FrameIndex.
4510   unsigned NumOps = LoadMI->getDesc().getNumOperands();
4511   int FrameIndex;
4512   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
4513     if (isPartialRegisterLoad(*LoadMI, MF))
4514       return nullptr;
4515     return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
4516   }
4517 
4518   // Check switch flag
4519   if (NoFusing) return nullptr;
4520 
4521   // Unless optimizing for size, don't fold to avoid partial
4522   // register update stalls
4523   if (!MF.getFunction()->getAttributes().
4524         hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4525       hasPartialRegUpdate(MI->getOpcode()))
4526     return nullptr;
4527 
4528   // Determine the alignment of the load.
4529   unsigned Alignment = 0;
4530   if (LoadMI->hasOneMemOperand())
4531     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
4532   else
4533     switch (LoadMI->getOpcode()) {
4534     case X86::AVX2_SETALLONES:
4535     case X86::AVX_SET0:
4536       Alignment = 32;
4537       break;
4538     case X86::V_SET0:
4539     case X86::V_SETALLONES:
4540       Alignment = 16;
4541       break;
4542     case X86::FsFLD0SD:
4543       Alignment = 8;
4544       break;
4545     case X86::FsFLD0SS:
4546       Alignment = 4;
4547       break;
4548     default:
4549       return nullptr;
4550     }
4551   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4552     unsigned NewOpc = 0;
4553     switch (MI->getOpcode()) {
4554     default: return nullptr;
4555     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
4556     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4557     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4558     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
4559     }
4560     // Change to CMPXXri r, 0 first.
4561     MI->setDesc(get(NewOpc));
4562     MI->getOperand(1).ChangeToImmediate(0);
4563   } else if (Ops.size() != 1)
4564     return nullptr;
4565 
4566   // Make sure the subregisters match.
4567   // Otherwise we risk changing the size of the load.
4568   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
4569     return nullptr;
4570 
4571   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
4572   switch (LoadMI->getOpcode()) {
4573   case X86::V_SET0:
4574   case X86::V_SETALLONES:
4575   case X86::AVX2_SETALLONES:
4576   case X86::AVX_SET0:
4577   case X86::FsFLD0SD:
4578   case X86::FsFLD0SS: {
4579     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
4580     // Create a constant-pool entry and operands to load from it.
4581 
4582     // Medium and large mode can't fold loads this way.
4583     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
4584         MF.getTarget().getCodeModel() != CodeModel::Kernel)
4585       return nullptr;
4586 
4587     // x86-32 PIC requires a PIC base register for constant pools.
4588     unsigned PICBase = 0;
4589     if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
4590       if (Subtarget.is64Bit())
4591         PICBase = X86::RIP;
4592       else
4593         // FIXME: PICBase = getGlobalBaseReg(&MF);
4594         // This doesn't work for several reasons.
4595         // 1. GlobalBaseReg may have been spilled.
4596         // 2. It may not be live at MI.
4597         return nullptr;
4598     }
4599 
4600     // Create a constant-pool entry.
4601     MachineConstantPool &MCP = *MF.getConstantPool();
4602     Type *Ty;
4603     unsigned Opc = LoadMI->getOpcode();
4604     if (Opc == X86::FsFLD0SS)
4605       Ty = Type::getFloatTy(MF.getFunction()->getContext());
4606     else if (Opc == X86::FsFLD0SD)
4607       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
4608     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
4609       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
4610     else
4611       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
4612 
4613     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
4614     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4615                                     Constant::getNullValue(Ty);
4616     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
4617 
4618     // Create operands to load from the constant pool entry.
4619     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4620     MOs.push_back(MachineOperand::CreateImm(1));
4621     MOs.push_back(MachineOperand::CreateReg(0, false));
4622     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
4623     MOs.push_back(MachineOperand::CreateReg(0, false));
4624     break;
4625   }
4626   default: {
4627     if (isPartialRegisterLoad(*LoadMI, MF))
4628       return nullptr;
4629 
4630     // Folding a normal load. Just copy the load's address operands.
4631     for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
4632       MOs.push_back(LoadMI->getOperand(i));
4633     break;
4634   }
4635   }
4636   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
4637                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
4638 }
4639 
4640 
4641 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4642                                   const SmallVectorImpl<unsigned> &Ops) const {
4643   // Check switch flag
4644   if (NoFusing) return 0;
4645 
4646   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4647     switch (MI->getOpcode()) {
4648     default: return false;
4649     case X86::TEST8rr:
4650     case X86::TEST16rr:
4651     case X86::TEST32rr:
4652     case X86::TEST64rr:
4653       return true;
4654     case X86::ADD32ri:
4655       // FIXME: AsmPrinter doesn't know how to handle
4656       // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4657       if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4658         return false;
4659       break;
4660     }
4661   }
4662 
4663   if (Ops.size() != 1)
4664     return false;
4665 
4666   unsigned OpNum = Ops[0];
4667   unsigned Opc = MI->getOpcode();
4668   unsigned NumOps = MI->getDesc().getNumOperands();
4669   bool isTwoAddr = NumOps > 1 &&
4670     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4671 
4672   // Folding a memory location into the two-address part of a two-address
4673   // instruction is different than folding it other places.  It requires
4674   // replacing the *two* registers with the memory location.
4675   const DenseMap<unsigned,
4676                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4677   if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
4678     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4679   } else if (OpNum == 0) { // If operand 0
4680     if (Opc == X86::MOV32r0)
4681       return true;
4682 
4683     OpcodeTablePtr = &RegOp2MemOpTable0;
4684   } else if (OpNum == 1) {
4685     OpcodeTablePtr = &RegOp2MemOpTable1;
4686   } else if (OpNum == 2) {
4687     OpcodeTablePtr = &RegOp2MemOpTable2;
4688   } else if (OpNum == 3) {
4689     OpcodeTablePtr = &RegOp2MemOpTable3;
4690   }
4691 
4692   if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4693     return true;
4694   return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
4695 }
4696 
4697 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4698                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
4699                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4700   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4701     MemOp2RegOpTable.find(MI->getOpcode());
4702   if (I == MemOp2RegOpTable.end())
4703     return false;
4704   unsigned Opc = I->second.first;
4705   unsigned Index = I->second.second & TB_INDEX_MASK;
4706   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4707   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4708   if (UnfoldLoad && !FoldedLoad)
4709     return false;
4710   UnfoldLoad &= FoldedLoad;
4711   if (UnfoldStore && !FoldedStore)
4712     return false;
4713   UnfoldStore &= FoldedStore;
4714 
4715   const MCInstrDesc &MCID = get(Opc);
4716   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4717   if (!MI->hasOneMemOperand() &&
4718       RC == &X86::VR128RegClass &&
4719       !Subtarget.isUnalignedMemAccessFast())
4720     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4721     // conservatively assume the address is unaligned. That's bad for
4722     // performance.
4723     return false;
4724   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
4725   SmallVector<MachineOperand,2> BeforeOps;
4726   SmallVector<MachineOperand,2> AfterOps;
4727   SmallVector<MachineOperand,4> ImpOps;
4728   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4729     MachineOperand &Op = MI->getOperand(i);
4730     if (i >= Index && i < Index + X86::AddrNumOperands)
4731       AddrOps.push_back(Op);
4732     else if (Op.isReg() && Op.isImplicit())
4733       ImpOps.push_back(Op);
4734     else if (i < Index)
4735       BeforeOps.push_back(Op);
4736     else if (i > Index)
4737       AfterOps.push_back(Op);
4738   }
4739 
4740   // Emit the load instruction.
4741   if (UnfoldLoad) {
4742     std::pair<MachineInstr::mmo_iterator,
4743               MachineInstr::mmo_iterator> MMOs =
4744       MF.extractLoadMemRefs(MI->memoperands_begin(),
4745                             MI->memoperands_end());
4746     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
4747     if (UnfoldStore) {
4748       // Address operands cannot be marked isKill.
4749       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
4750         MachineOperand &MO = NewMIs[0]->getOperand(i);
4751         if (MO.isReg())
4752           MO.setIsKill(false);
4753       }
4754     }
4755   }
4756 
4757   // Emit the data processing instruction.
4758   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
4759   MachineInstrBuilder MIB(MF, DataMI);
4760 
4761   if (FoldedStore)
4762     MIB.addReg(Reg, RegState::Define);
4763   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
4764     MIB.addOperand(BeforeOps[i]);
4765   if (FoldedLoad)
4766     MIB.addReg(Reg);
4767   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
4768     MIB.addOperand(AfterOps[i]);
4769   for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
4770     MachineOperand &MO = ImpOps[i];
4771     MIB.addReg(MO.getReg(),
4772                getDefRegState(MO.isDef()) |
4773                RegState::Implicit |
4774                getKillRegState(MO.isKill()) |
4775                getDeadRegState(MO.isDead()) |
4776                getUndefRegState(MO.isUndef()));
4777   }
4778   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
4779   switch (DataMI->getOpcode()) {
4780   default: break;
4781   case X86::CMP64ri32:
4782   case X86::CMP64ri8:
4783   case X86::CMP32ri:
4784   case X86::CMP32ri8:
4785   case X86::CMP16ri:
4786   case X86::CMP16ri8:
4787   case X86::CMP8ri: {
4788     MachineOperand &MO0 = DataMI->getOperand(0);
4789     MachineOperand &MO1 = DataMI->getOperand(1);
4790     if (MO1.getImm() == 0) {
4791       unsigned NewOpc;
4792       switch (DataMI->getOpcode()) {
4793       default: llvm_unreachable("Unreachable!");
4794       case X86::CMP64ri8:
4795       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
4796       case X86::CMP32ri8:
4797       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
4798       case X86::CMP16ri8:
4799       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
4800       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
4801       }
4802       DataMI->setDesc(get(NewOpc));
4803       MO1.ChangeToRegister(MO0.getReg(), false);
4804     }
4805   }
4806   }
4807   NewMIs.push_back(DataMI);
4808 
4809   // Emit the store instruction.
4810   if (UnfoldStore) {
4811     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
4812     std::pair<MachineInstr::mmo_iterator,
4813               MachineInstr::mmo_iterator> MMOs =
4814       MF.extractStoreMemRefs(MI->memoperands_begin(),
4815                              MI->memoperands_end());
4816     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
4817   }
4818 
4819   return true;
4820 }
4821 
4822 bool
4823 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
4824                                   SmallVectorImpl<SDNode*> &NewNodes) const {
4825   if (!N->isMachineOpcode())
4826     return false;
4827 
4828   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4829     MemOp2RegOpTable.find(N->getMachineOpcode());
4830   if (I == MemOp2RegOpTable.end())
4831     return false;
4832   unsigned Opc = I->second.first;
4833   unsigned Index = I->second.second & TB_INDEX_MASK;
4834   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4835   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4836   const MCInstrDesc &MCID = get(Opc);
4837   MachineFunction &MF = DAG.getMachineFunction();
4838   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4839   unsigned NumDefs = MCID.NumDefs;
4840   std::vector<SDValue> AddrOps;
4841   std::vector<SDValue> BeforeOps;
4842   std::vector<SDValue> AfterOps;
4843   SDLoc dl(N);
4844   unsigned NumOps = N->getNumOperands();
4845   for (unsigned i = 0; i != NumOps-1; ++i) {
4846     SDValue Op = N->getOperand(i);
4847     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
4848       AddrOps.push_back(Op);
4849     else if (i < Index-NumDefs)
4850       BeforeOps.push_back(Op);
4851     else if (i > Index-NumDefs)
4852       AfterOps.push_back(Op);
4853   }
4854   SDValue Chain = N->getOperand(NumOps-1);
4855   AddrOps.push_back(Chain);
4856 
4857   // Emit the load instruction.
4858   SDNode *Load = nullptr;
4859   if (FoldedLoad) {
4860     EVT VT = *RC->vt_begin();
4861     std::pair<MachineInstr::mmo_iterator,
4862               MachineInstr::mmo_iterator> MMOs =
4863       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4864                             cast<MachineSDNode>(N)->memoperands_end());
4865     if (!(*MMOs.first) &&
4866         RC == &X86::VR128RegClass &&
4867         !Subtarget.isUnalignedMemAccessFast())
4868       // Do not introduce a slow unaligned load.
4869       return false;
4870     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4871     bool isAligned = (*MMOs.first) &&
4872                      (*MMOs.first)->getAlignment() >= Alignment;
4873     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
4874                               VT, MVT::Other, AddrOps);
4875     NewNodes.push_back(Load);
4876 
4877     // Preserve memory reference information.
4878     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4879   }
4880 
4881   // Emit the data processing instruction.
4882   std::vector<EVT> VTs;
4883   const TargetRegisterClass *DstRC = nullptr;
4884   if (MCID.getNumDefs() > 0) {
4885     DstRC = getRegClass(MCID, 0, &RI, MF);
4886     VTs.push_back(*DstRC->vt_begin());
4887   }
4888   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
4889     EVT VT = N->getValueType(i);
4890     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
4891       VTs.push_back(VT);
4892   }
4893   if (Load)
4894     BeforeOps.push_back(SDValue(Load, 0));
4895   std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
4896   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
4897   NewNodes.push_back(NewNode);
4898 
4899   // Emit the store instruction.
4900   if (FoldedStore) {
4901     AddrOps.pop_back();
4902     AddrOps.push_back(SDValue(NewNode, 0));
4903     AddrOps.push_back(Chain);
4904     std::pair<MachineInstr::mmo_iterator,
4905               MachineInstr::mmo_iterator> MMOs =
4906       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4907                              cast<MachineSDNode>(N)->memoperands_end());
4908     if (!(*MMOs.first) &&
4909         RC == &X86::VR128RegClass &&
4910         !Subtarget.isUnalignedMemAccessFast())
4911       // Do not introduce a slow unaligned store.
4912       return false;
4913     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4914     bool isAligned = (*MMOs.first) &&
4915                      (*MMOs.first)->getAlignment() >= Alignment;
4916     SDNode *Store =
4917         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
4918                            dl, MVT::Other, AddrOps);
4919     NewNodes.push_back(Store);
4920 
4921     // Preserve memory reference information.
4922     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4923   }
4924 
4925   return true;
4926 }
4927 
4928 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
4929                                       bool UnfoldLoad, bool UnfoldStore,
4930                                       unsigned *LoadRegIndex) const {
4931   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4932     MemOp2RegOpTable.find(Opc);
4933   if (I == MemOp2RegOpTable.end())
4934     return 0;
4935   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4936   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4937   if (UnfoldLoad && !FoldedLoad)
4938     return 0;
4939   if (UnfoldStore && !FoldedStore)
4940     return 0;
4941   if (LoadRegIndex)
4942     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
4943   return I->second.first;
4944 }
4945 
4946 bool
4947 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
4948                                      int64_t &Offset1, int64_t &Offset2) const {
4949   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
4950     return false;
4951   unsigned Opc1 = Load1->getMachineOpcode();
4952   unsigned Opc2 = Load2->getMachineOpcode();
4953   switch (Opc1) {
4954   default: return false;
4955   case X86::MOV8rm:
4956   case X86::MOV16rm:
4957   case X86::MOV32rm:
4958   case X86::MOV64rm:
4959   case X86::LD_Fp32m:
4960   case X86::LD_Fp64m:
4961   case X86::LD_Fp80m:
4962   case X86::MOVSSrm:
4963   case X86::MOVSDrm:
4964   case X86::MMX_MOVD64rm:
4965   case X86::MMX_MOVQ64rm:
4966   case X86::FsMOVAPSrm:
4967   case X86::FsMOVAPDrm:
4968   case X86::MOVAPSrm:
4969   case X86::MOVUPSrm:
4970   case X86::MOVAPDrm:
4971   case X86::MOVDQArm:
4972   case X86::MOVDQUrm:
4973   // AVX load instructions
4974   case X86::VMOVSSrm:
4975   case X86::VMOVSDrm:
4976   case X86::FsVMOVAPSrm:
4977   case X86::FsVMOVAPDrm:
4978   case X86::VMOVAPSrm:
4979   case X86::VMOVUPSrm:
4980   case X86::VMOVAPDrm:
4981   case X86::VMOVDQArm:
4982   case X86::VMOVDQUrm:
4983   case X86::VMOVAPSYrm:
4984   case X86::VMOVUPSYrm:
4985   case X86::VMOVAPDYrm:
4986   case X86::VMOVDQAYrm:
4987   case X86::VMOVDQUYrm:
4988     break;
4989   }
4990   switch (Opc2) {
4991   default: return false;
4992   case X86::MOV8rm:
4993   case X86::MOV16rm:
4994   case X86::MOV32rm:
4995   case X86::MOV64rm:
4996   case X86::LD_Fp32m:
4997   case X86::LD_Fp64m:
4998   case X86::LD_Fp80m:
4999   case X86::MOVSSrm:
5000   case X86::MOVSDrm:
5001   case X86::MMX_MOVD64rm:
5002   case X86::MMX_MOVQ64rm:
5003   case X86::FsMOVAPSrm:
5004   case X86::FsMOVAPDrm:
5005   case X86::MOVAPSrm:
5006   case X86::MOVUPSrm:
5007   case X86::MOVAPDrm:
5008   case X86::MOVDQArm:
5009   case X86::MOVDQUrm:
5010   // AVX load instructions
5011   case X86::VMOVSSrm:
5012   case X86::VMOVSDrm:
5013   case X86::FsVMOVAPSrm:
5014   case X86::FsVMOVAPDrm:
5015   case X86::VMOVAPSrm:
5016   case X86::VMOVUPSrm:
5017   case X86::VMOVAPDrm:
5018   case X86::VMOVDQArm:
5019   case X86::VMOVDQUrm:
5020   case X86::VMOVAPSYrm:
5021   case X86::VMOVUPSYrm:
5022   case X86::VMOVAPDYrm:
5023   case X86::VMOVDQAYrm:
5024   case X86::VMOVDQUYrm:
5025     break;
5026   }
5027 
5028   // Check if chain operands and base addresses match.
5029   if (Load1->getOperand(0) != Load2->getOperand(0) ||
5030       Load1->getOperand(5) != Load2->getOperand(5))
5031     return false;
5032   // Segment operands should match as well.
5033   if (Load1->getOperand(4) != Load2->getOperand(4))
5034     return false;
5035   // Scale should be 1, Index should be Reg0.
5036   if (Load1->getOperand(1) == Load2->getOperand(1) &&
5037       Load1->getOperand(2) == Load2->getOperand(2)) {
5038     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5039       return false;
5040 
5041     // Now let's examine the displacements.
5042     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5043         isa<ConstantSDNode>(Load2->getOperand(3))) {
5044       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5045       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5046       return true;
5047     }
5048   }
5049   return false;
5050 }
5051 
5052 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5053                                            int64_t Offset1, int64_t Offset2,
5054                                            unsigned NumLoads) const {
5055   assert(Offset2 > Offset1);
5056   if ((Offset2 - Offset1) / 8 > 64)
5057     return false;
5058 
5059   unsigned Opc1 = Load1->getMachineOpcode();
5060   unsigned Opc2 = Load2->getMachineOpcode();
5061   if (Opc1 != Opc2)
5062     return false;  // FIXME: overly conservative?
5063 
5064   switch (Opc1) {
5065   default: break;
5066   case X86::LD_Fp32m:
5067   case X86::LD_Fp64m:
5068   case X86::LD_Fp80m:
5069   case X86::MMX_MOVD64rm:
5070   case X86::MMX_MOVQ64rm:
5071     return false;
5072   }
5073 
5074   EVT VT = Load1->getValueType(0);
5075   switch (VT.getSimpleVT().SimpleTy) {
5076   default:
5077     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5078     // have 16 of them to play with.
5079     if (Subtarget.is64Bit()) {
5080       if (NumLoads >= 3)
5081         return false;
5082     } else if (NumLoads) {
5083       return false;
5084     }
5085     break;
5086   case MVT::i8:
5087   case MVT::i16:
5088   case MVT::i32:
5089   case MVT::i64:
5090   case MVT::f32:
5091   case MVT::f64:
5092     if (NumLoads)
5093       return false;
5094     break;
5095   }
5096 
5097   return true;
5098 }
5099 
5100 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5101                                           MachineInstr *Second) const {
5102   // Check if this processor supports macro-fusion. Since this is a minor
5103   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5104   // proxy for SandyBridge+.
5105   if (!Subtarget.hasAVX())
5106     return false;
5107 
5108   enum {
5109     FuseTest,
5110     FuseCmp,
5111     FuseInc
5112   } FuseKind;
5113 
5114   switch(Second->getOpcode()) {
5115   default:
5116     return false;
5117   case X86::JE_4:
5118   case X86::JNE_4:
5119   case X86::JL_4:
5120   case X86::JLE_4:
5121   case X86::JG_4:
5122   case X86::JGE_4:
5123     FuseKind = FuseInc;
5124     break;
5125   case X86::JB_4:
5126   case X86::JBE_4:
5127   case X86::JA_4:
5128   case X86::JAE_4:
5129     FuseKind = FuseCmp;
5130     break;
5131   case X86::JS_4:
5132   case X86::JNS_4:
5133   case X86::JP_4:
5134   case X86::JNP_4:
5135   case X86::JO_4:
5136   case X86::JNO_4:
5137     FuseKind = FuseTest;
5138     break;
5139   }
5140   switch (First->getOpcode()) {
5141   default:
5142     return false;
5143   case X86::TEST8rr:
5144   case X86::TEST16rr:
5145   case X86::TEST32rr:
5146   case X86::TEST64rr:
5147   case X86::TEST8ri:
5148   case X86::TEST16ri:
5149   case X86::TEST32ri:
5150   case X86::TEST32i32:
5151   case X86::TEST64i32:
5152   case X86::TEST64ri32:
5153   case X86::TEST8rm:
5154   case X86::TEST16rm:
5155   case X86::TEST32rm:
5156   case X86::TEST64rm:
5157   case X86::TEST8ri_NOREX:
5158   case X86::AND16i16:
5159   case X86::AND16ri:
5160   case X86::AND16ri8:
5161   case X86::AND16rm:
5162   case X86::AND16rr:
5163   case X86::AND32i32:
5164   case X86::AND32ri:
5165   case X86::AND32ri8:
5166   case X86::AND32rm:
5167   case X86::AND32rr:
5168   case X86::AND64i32:
5169   case X86::AND64ri32:
5170   case X86::AND64ri8:
5171   case X86::AND64rm:
5172   case X86::AND64rr:
5173   case X86::AND8i8:
5174   case X86::AND8ri:
5175   case X86::AND8rm:
5176   case X86::AND8rr:
5177     return true;
5178   case X86::CMP16i16:
5179   case X86::CMP16ri:
5180   case X86::CMP16ri8:
5181   case X86::CMP16rm:
5182   case X86::CMP16rr:
5183   case X86::CMP32i32:
5184   case X86::CMP32ri:
5185   case X86::CMP32ri8:
5186   case X86::CMP32rm:
5187   case X86::CMP32rr:
5188   case X86::CMP64i32:
5189   case X86::CMP64ri32:
5190   case X86::CMP64ri8:
5191   case X86::CMP64rm:
5192   case X86::CMP64rr:
5193   case X86::CMP8i8:
5194   case X86::CMP8ri:
5195   case X86::CMP8rm:
5196   case X86::CMP8rr:
5197   case X86::ADD16i16:
5198   case X86::ADD16ri:
5199   case X86::ADD16ri8:
5200   case X86::ADD16ri8_DB:
5201   case X86::ADD16ri_DB:
5202   case X86::ADD16rm:
5203   case X86::ADD16rr:
5204   case X86::ADD16rr_DB:
5205   case X86::ADD32i32:
5206   case X86::ADD32ri:
5207   case X86::ADD32ri8:
5208   case X86::ADD32ri8_DB:
5209   case X86::ADD32ri_DB:
5210   case X86::ADD32rm:
5211   case X86::ADD32rr:
5212   case X86::ADD32rr_DB:
5213   case X86::ADD64i32:
5214   case X86::ADD64ri32:
5215   case X86::ADD64ri32_DB:
5216   case X86::ADD64ri8:
5217   case X86::ADD64ri8_DB:
5218   case X86::ADD64rm:
5219   case X86::ADD64rr:
5220   case X86::ADD64rr_DB:
5221   case X86::ADD8i8:
5222   case X86::ADD8mi:
5223   case X86::ADD8mr:
5224   case X86::ADD8ri:
5225   case X86::ADD8rm:
5226   case X86::ADD8rr:
5227   case X86::SUB16i16:
5228   case X86::SUB16ri:
5229   case X86::SUB16ri8:
5230   case X86::SUB16rm:
5231   case X86::SUB16rr:
5232   case X86::SUB32i32:
5233   case X86::SUB32ri:
5234   case X86::SUB32ri8:
5235   case X86::SUB32rm:
5236   case X86::SUB32rr:
5237   case X86::SUB64i32:
5238   case X86::SUB64ri32:
5239   case X86::SUB64ri8:
5240   case X86::SUB64rm:
5241   case X86::SUB64rr:
5242   case X86::SUB8i8:
5243   case X86::SUB8ri:
5244   case X86::SUB8rm:
5245   case X86::SUB8rr:
5246     return FuseKind == FuseCmp || FuseKind == FuseInc;
5247   case X86::INC16r:
5248   case X86::INC32r:
5249   case X86::INC64_16r:
5250   case X86::INC64_32r:
5251   case X86::INC64r:
5252   case X86::INC8r:
5253   case X86::DEC16r:
5254   case X86::DEC32r:
5255   case X86::DEC64_16r:
5256   case X86::DEC64_32r:
5257   case X86::DEC64r:
5258   case X86::DEC8r:
5259     return FuseKind == FuseInc;
5260   }
5261 }
5262 
5263 bool X86InstrInfo::
5264 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5265   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5266   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5267   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5268     return true;
5269   Cond[0].setImm(GetOppositeBranchCondition(CC));
5270   return false;
5271 }
5272 
5273 bool X86InstrInfo::
5274 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5275   // FIXME: Return false for x87 stack register classes for now. We can't
5276   // allow any loads of these registers before FpGet_ST0_80.
5277   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5278            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
5279 }
5280 
5281 /// getGlobalBaseReg - Return a virtual register initialized with the
5282 /// the global base register value. Output instructions required to
5283 /// initialize the register in the function entry block, if necessary.
5284 ///
5285 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5286 ///
5287 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5288   assert(!Subtarget.is64Bit() &&
5289          "X86-64 PIC uses RIP relative addressing");
5290 
5291   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5292   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5293   if (GlobalBaseReg != 0)
5294     return GlobalBaseReg;
5295 
5296   // Create the register. The code to initialize it is inserted
5297   // later, by the CGBR pass (below).
5298   MachineRegisterInfo &RegInfo = MF->getRegInfo();
5299   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
5300   X86FI->setGlobalBaseReg(GlobalBaseReg);
5301   return GlobalBaseReg;
5302 }
5303 
5304 // These are the replaceable SSE instructions. Some of these have Int variants
5305 // that we don't include here. We don't want to replace instructions selected
5306 // by intrinsics.
5307 static const uint16_t ReplaceableInstrs[][3] = {
5308   //PackedSingle     PackedDouble    PackedInt
5309   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
5310   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
5311   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
5312   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
5313   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
5314   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
5315   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
5316   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
5317   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
5318   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
5319   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
5320   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
5321   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
5322   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
5323   // AVX 128-bit support
5324   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
5325   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
5326   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
5327   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
5328   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
5329   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5330   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
5331   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
5332   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
5333   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
5334   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
5335   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
5336   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
5337   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
5338   // AVX 256-bit support
5339   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
5340   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
5341   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
5342   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
5343   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
5344   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
5345 };
5346 
5347 static const uint16_t ReplaceableInstrsAVX2[][3] = {
5348   //PackedSingle       PackedDouble       PackedInt
5349   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
5350   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
5351   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
5352   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
5353   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
5354   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
5355   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
5356   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
5357   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5358   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5359   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
5360   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
5361   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
5362   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
5363   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5364   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5365   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5366   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5367   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5368   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
5369 };
5370 
5371 // FIXME: Some shuffle and unpack instructions have equivalents in different
5372 // domains, but they require a bit more work than just switching opcodes.
5373 
5374 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
5375   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
5376     if (ReplaceableInstrs[i][domain-1] == opcode)
5377       return ReplaceableInstrs[i];
5378   return nullptr;
5379 }
5380 
5381 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
5382   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5383     if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5384       return ReplaceableInstrsAVX2[i];
5385   return nullptr;
5386 }
5387 
5388 std::pair<uint16_t, uint16_t>
5389 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
5390   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5391   bool hasAVX2 = Subtarget.hasAVX2();
5392   uint16_t validDomains = 0;
5393   if (domain && lookup(MI->getOpcode(), domain))
5394     validDomains = 0xe;
5395   else if (domain && lookupAVX2(MI->getOpcode(), domain))
5396     validDomains = hasAVX2 ? 0xe : 0x6;
5397   return std::make_pair(domain, validDomains);
5398 }
5399 
5400 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
5401   assert(Domain>0 && Domain<4 && "Invalid execution domain");
5402   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5403   assert(dom && "Not an SSE instruction");
5404   const uint16_t *table = lookup(MI->getOpcode(), dom);
5405   if (!table) { // try the other table
5406     assert((Subtarget.hasAVX2() || Domain < 3) &&
5407            "256-bit vector operations only available in AVX2");
5408     table = lookupAVX2(MI->getOpcode(), dom);
5409   }
5410   assert(table && "Cannot change domain");
5411   MI->setDesc(get(table[Domain-1]));
5412 }
5413 
5414 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5415 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5416   NopInst.setOpcode(X86::NOOP);
5417 }
5418 
5419 void X86InstrInfo::getUnconditionalBranch(
5420     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
5421   Branch.setOpcode(X86::JMP_4);
5422   Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
5423 }
5424 
5425 void X86InstrInfo::getTrap(MCInst &MI) const {
5426   MI.setOpcode(X86::TRAP);
5427 }
5428 
5429 bool X86InstrInfo::isHighLatencyDef(int opc) const {
5430   switch (opc) {
5431   default: return false;
5432   case X86::DIVSDrm:
5433   case X86::DIVSDrm_Int:
5434   case X86::DIVSDrr:
5435   case X86::DIVSDrr_Int:
5436   case X86::DIVSSrm:
5437   case X86::DIVSSrm_Int:
5438   case X86::DIVSSrr:
5439   case X86::DIVSSrr_Int:
5440   case X86::SQRTPDm:
5441   case X86::SQRTPDr:
5442   case X86::SQRTPSm:
5443   case X86::SQRTPSr:
5444   case X86::SQRTSDm:
5445   case X86::SQRTSDm_Int:
5446   case X86::SQRTSDr:
5447   case X86::SQRTSDr_Int:
5448   case X86::SQRTSSm:
5449   case X86::SQRTSSm_Int:
5450   case X86::SQRTSSr:
5451   case X86::SQRTSSr_Int:
5452   // AVX instructions with high latency
5453   case X86::VDIVSDrm:
5454   case X86::VDIVSDrm_Int:
5455   case X86::VDIVSDrr:
5456   case X86::VDIVSDrr_Int:
5457   case X86::VDIVSSrm:
5458   case X86::VDIVSSrm_Int:
5459   case X86::VDIVSSrr:
5460   case X86::VDIVSSrr_Int:
5461   case X86::VSQRTPDm:
5462   case X86::VSQRTPDr:
5463   case X86::VSQRTPSm:
5464   case X86::VSQRTPSr:
5465   case X86::VSQRTSDm:
5466   case X86::VSQRTSDm_Int:
5467   case X86::VSQRTSDr:
5468   case X86::VSQRTSSm:
5469   case X86::VSQRTSSm_Int:
5470   case X86::VSQRTSSr:
5471   case X86::VSQRTPDZm:
5472   case X86::VSQRTPDZr:
5473   case X86::VSQRTPSZm:
5474   case X86::VSQRTPSZr:
5475   case X86::VSQRTSDZm:
5476   case X86::VSQRTSDZm_Int:
5477   case X86::VSQRTSDZr:
5478   case X86::VSQRTSSZm_Int:
5479   case X86::VSQRTSSZr:
5480   case X86::VSQRTSSZm:
5481   case X86::VDIVSDZrm:
5482   case X86::VDIVSDZrr:
5483   case X86::VDIVSSZrm:
5484   case X86::VDIVSSZrr:
5485 
5486   case X86::VGATHERQPSZrm:
5487   case X86::VGATHERQPDZrm:
5488   case X86::VGATHERDPDZrm:
5489   case X86::VGATHERDPSZrm:
5490   case X86::VPGATHERQDZrm:
5491   case X86::VPGATHERQQZrm:
5492   case X86::VPGATHERDDZrm:
5493   case X86::VPGATHERDQZrm:
5494   case X86::VSCATTERQPDZmr:
5495   case X86::VSCATTERQPSZmr:
5496   case X86::VSCATTERDPDZmr:
5497   case X86::VSCATTERDPSZmr:
5498   case X86::VPSCATTERQDZmr:
5499   case X86::VPSCATTERQQZmr:
5500   case X86::VPSCATTERDDZmr:
5501   case X86::VPSCATTERDQZmr:
5502     return true;
5503   }
5504 }
5505 
5506 bool X86InstrInfo::
5507 hasHighOperandLatency(const InstrItineraryData *ItinData,
5508                       const MachineRegisterInfo *MRI,
5509                       const MachineInstr *DefMI, unsigned DefIdx,
5510                       const MachineInstr *UseMI, unsigned UseIdx) const {
5511   return isHighLatencyDef(DefMI->getOpcode());
5512 }
5513 
5514 namespace {
5515   /// CGBR - Create Global Base Reg pass. This initializes the PIC
5516   /// global base register for x86-32.
5517   struct CGBR : public MachineFunctionPass {
5518     static char ID;
5519     CGBR() : MachineFunctionPass(ID) {}
5520 
5521     bool runOnMachineFunction(MachineFunction &MF) override {
5522       const X86TargetMachine *TM =
5523         static_cast<const X86TargetMachine *>(&MF.getTarget());
5524 
5525       // Don't do anything if this is 64-bit as 64-bit PIC
5526       // uses RIP relative addressing.
5527       if (TM->getSubtarget<X86Subtarget>().is64Bit())
5528         return false;
5529 
5530       // Only emit a global base reg in PIC mode.
5531       if (TM->getRelocationModel() != Reloc::PIC_)
5532         return false;
5533 
5534       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
5535       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5536 
5537       // If we didn't need a GlobalBaseReg, don't insert code.
5538       if (GlobalBaseReg == 0)
5539         return false;
5540 
5541       // Insert the set of GlobalBaseReg into the first MBB of the function
5542       MachineBasicBlock &FirstMBB = MF.front();
5543       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
5544       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
5545       MachineRegisterInfo &RegInfo = MF.getRegInfo();
5546       const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5547 
5548       unsigned PC;
5549       if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
5550         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
5551       else
5552         PC = GlobalBaseReg;
5553 
5554       // Operand of MovePCtoStack is completely ignored by asm printer. It's
5555       // only used in JIT code emission as displacement to pc.
5556       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
5557 
5558       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
5559       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
5560       if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
5561         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
5562         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5563           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
5564                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
5565       }
5566 
5567       return true;
5568     }
5569 
5570     const char *getPassName() const override {
5571       return "X86 PIC Global Base Reg Initialization";
5572     }
5573 
5574     void getAnalysisUsage(AnalysisUsage &AU) const override {
5575       AU.setPreservesCFG();
5576       MachineFunctionPass::getAnalysisUsage(AU);
5577     }
5578   };
5579 }
5580 
5581 char CGBR::ID = 0;
5582 FunctionPass*
5583 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
5584 
5585 namespace {
5586   struct LDTLSCleanup : public MachineFunctionPass {
5587     static char ID;
5588     LDTLSCleanup() : MachineFunctionPass(ID) {}
5589 
5590     bool runOnMachineFunction(MachineFunction &MF) override {
5591       X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
5592       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
5593         // No point folding accesses if there isn't at least two.
5594         return false;
5595       }
5596 
5597       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
5598       return VisitNode(DT->getRootNode(), 0);
5599     }
5600 
5601     // Visit the dominator subtree rooted at Node in pre-order.
5602     // If TLSBaseAddrReg is non-null, then use that to replace any
5603     // TLS_base_addr instructions. Otherwise, create the register
5604     // when the first such instruction is seen, and then use it
5605     // as we encounter more instructions.
5606     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
5607       MachineBasicBlock *BB = Node->getBlock();
5608       bool Changed = false;
5609 
5610       // Traverse the current block.
5611       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
5612            ++I) {
5613         switch (I->getOpcode()) {
5614           case X86::TLS_base_addr32:
5615           case X86::TLS_base_addr64:
5616             if (TLSBaseAddrReg)
5617               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
5618             else
5619               I = SetRegister(I, &TLSBaseAddrReg);
5620             Changed = true;
5621             break;
5622           default:
5623             break;
5624         }
5625       }
5626 
5627       // Visit the children of this block in the dominator tree.
5628       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
5629            I != E; ++I) {
5630         Changed |= VisitNode(*I, TLSBaseAddrReg);
5631       }
5632 
5633       return Changed;
5634     }
5635 
5636     // Replace the TLS_base_addr instruction I with a copy from
5637     // TLSBaseAddrReg, returning the new instruction.
5638     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
5639                                          unsigned TLSBaseAddrReg) {
5640       MachineFunction *MF = I->getParent()->getParent();
5641       const X86TargetMachine *TM =
5642           static_cast<const X86TargetMachine *>(&MF->getTarget());
5643       const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5644       const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5645 
5646       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5647       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
5648                                    TII->get(TargetOpcode::COPY),
5649                                    is64Bit ? X86::RAX : X86::EAX)
5650                                    .addReg(TLSBaseAddrReg);
5651 
5652       // Erase the TLS_base_addr instruction.
5653       I->eraseFromParent();
5654 
5655       return Copy;
5656     }
5657 
5658     // Create a virtal register in *TLSBaseAddrReg, and populate it by
5659     // inserting a copy instruction after I. Returns the new instruction.
5660     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
5661       MachineFunction *MF = I->getParent()->getParent();
5662       const X86TargetMachine *TM =
5663           static_cast<const X86TargetMachine *>(&MF->getTarget());
5664       const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5665       const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5666 
5667       // Create a virtual register for the TLS base address.
5668       MachineRegisterInfo &RegInfo = MF->getRegInfo();
5669       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
5670                                                       ? &X86::GR64RegClass
5671                                                       : &X86::GR32RegClass);
5672 
5673       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
5674       MachineInstr *Next = I->getNextNode();
5675       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
5676                                    TII->get(TargetOpcode::COPY),
5677                                    *TLSBaseAddrReg)
5678                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
5679 
5680       return Copy;
5681     }
5682 
5683     const char *getPassName() const override {
5684       return "Local Dynamic TLS Access Clean-up";
5685     }
5686 
5687     void getAnalysisUsage(AnalysisUsage &AU) const override {
5688       AU.setPreservesCFG();
5689       AU.addRequired<MachineDominatorTree>();
5690       MachineFunctionPass::getAnalysisUsage(AU);
5691     }
5692   };
5693 }
5694 
5695 char LDTLSCleanup::ID = 0;
5696 FunctionPass*
5697 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
5698