1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include <limits>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "x86-instr-info"
44 
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "X86GenInstrInfo.inc"
47 
48 static cl::opt<bool>
49 NoFusing("disable-spill-fusing",
50          cl::desc("Disable fusing of spill code into instructions"));
51 static cl::opt<bool>
52 PrintFailedFusing("print-failed-fuse-candidates",
53                   cl::desc("Print instructions that the allocator wants to"
54                            " fuse, but the X86 backend currently can't"),
55                   cl::Hidden);
56 static cl::opt<bool>
57 ReMatPICStubLoad("remat-pic-stub-load",
58                  cl::desc("Re-materialize load from stub in PIC mode"),
59                  cl::init(false), cl::Hidden);
60 
61 enum {
62   // Select which memory operand is being unfolded.
63   // (stored in bits 0 - 3)
64   TB_INDEX_0    = 0,
65   TB_INDEX_1    = 1,
66   TB_INDEX_2    = 2,
67   TB_INDEX_3    = 3,
68   TB_INDEX_MASK = 0xf,
69 
70   // Do not insert the reverse map (MemOp -> RegOp) into the table.
71   // This may be needed because there is a many -> one mapping.
72   TB_NO_REVERSE   = 1 << 4,
73 
74   // Do not insert the forward map (RegOp -> MemOp) into the table.
75   // This is needed for Native Client, which prohibits branch
76   // instructions from using a memory operand.
77   TB_NO_FORWARD   = 1 << 5,
78 
79   TB_FOLDED_LOAD  = 1 << 6,
80   TB_FOLDED_STORE = 1 << 7,
81 
82   // Minimum alignment required for load/store.
83   // Used for RegOp->MemOp conversion.
84   // (stored in bits 8 - 15)
85   TB_ALIGN_SHIFT = 8,
86   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
87   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
88   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
89   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
90   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
91 };
92 
93 struct X86OpTblEntry {
94   uint16_t RegOp;
95   uint16_t MemOp;
96   uint16_t Flags;
97 };
98 
99 // Pin the vtable to this file.
100 void X86InstrInfo::anchor() {}
101 
102 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
103     : X86GenInstrInfo(
104           (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
105           (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
106       Subtarget(STI), RI(STI) {
107 
108   static const X86OpTblEntry OpTbl2Addr[] = {
109     { X86::ADC32ri,     X86::ADC32mi,    0 },
110     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
111     { X86::ADC32rr,     X86::ADC32mr,    0 },
112     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
113     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
114     { X86::ADC64rr,     X86::ADC64mr,    0 },
115     { X86::ADD16ri,     X86::ADD16mi,    0 },
116     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
117     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
118     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
119     { X86::ADD16rr,     X86::ADD16mr,    0 },
120     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
121     { X86::ADD32ri,     X86::ADD32mi,    0 },
122     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
123     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
124     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
125     { X86::ADD32rr,     X86::ADD32mr,    0 },
126     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
127     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
128     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
129     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
130     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
131     { X86::ADD64rr,     X86::ADD64mr,    0 },
132     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
133     { X86::ADD8ri,      X86::ADD8mi,     0 },
134     { X86::ADD8rr,      X86::ADD8mr,     0 },
135     { X86::AND16ri,     X86::AND16mi,    0 },
136     { X86::AND16ri8,    X86::AND16mi8,   0 },
137     { X86::AND16rr,     X86::AND16mr,    0 },
138     { X86::AND32ri,     X86::AND32mi,    0 },
139     { X86::AND32ri8,    X86::AND32mi8,   0 },
140     { X86::AND32rr,     X86::AND32mr,    0 },
141     { X86::AND64ri32,   X86::AND64mi32,  0 },
142     { X86::AND64ri8,    X86::AND64mi8,   0 },
143     { X86::AND64rr,     X86::AND64mr,    0 },
144     { X86::AND8ri,      X86::AND8mi,     0 },
145     { X86::AND8rr,      X86::AND8mr,     0 },
146     { X86::DEC16r,      X86::DEC16m,     0 },
147     { X86::DEC32r,      X86::DEC32m,     0 },
148     { X86::DEC64_16r,   X86::DEC64_16m,  0 },
149     { X86::DEC64_32r,   X86::DEC64_32m,  0 },
150     { X86::DEC64r,      X86::DEC64m,     0 },
151     { X86::DEC8r,       X86::DEC8m,      0 },
152     { X86::INC16r,      X86::INC16m,     0 },
153     { X86::INC32r,      X86::INC32m,     0 },
154     { X86::INC64_16r,   X86::INC64_16m,  0 },
155     { X86::INC64_32r,   X86::INC64_32m,  0 },
156     { X86::INC64r,      X86::INC64m,     0 },
157     { X86::INC8r,       X86::INC8m,      0 },
158     { X86::NEG16r,      X86::NEG16m,     0 },
159     { X86::NEG32r,      X86::NEG32m,     0 },
160     { X86::NEG64r,      X86::NEG64m,     0 },
161     { X86::NEG8r,       X86::NEG8m,      0 },
162     { X86::NOT16r,      X86::NOT16m,     0 },
163     { X86::NOT32r,      X86::NOT32m,     0 },
164     { X86::NOT64r,      X86::NOT64m,     0 },
165     { X86::NOT8r,       X86::NOT8m,      0 },
166     { X86::OR16ri,      X86::OR16mi,     0 },
167     { X86::OR16ri8,     X86::OR16mi8,    0 },
168     { X86::OR16rr,      X86::OR16mr,     0 },
169     { X86::OR32ri,      X86::OR32mi,     0 },
170     { X86::OR32ri8,     X86::OR32mi8,    0 },
171     { X86::OR32rr,      X86::OR32mr,     0 },
172     { X86::OR64ri32,    X86::OR64mi32,   0 },
173     { X86::OR64ri8,     X86::OR64mi8,    0 },
174     { X86::OR64rr,      X86::OR64mr,     0 },
175     { X86::OR8ri,       X86::OR8mi,      0 },
176     { X86::OR8rr,       X86::OR8mr,      0 },
177     { X86::ROL16r1,     X86::ROL16m1,    0 },
178     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
179     { X86::ROL16ri,     X86::ROL16mi,    0 },
180     { X86::ROL32r1,     X86::ROL32m1,    0 },
181     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
182     { X86::ROL32ri,     X86::ROL32mi,    0 },
183     { X86::ROL64r1,     X86::ROL64m1,    0 },
184     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
185     { X86::ROL64ri,     X86::ROL64mi,    0 },
186     { X86::ROL8r1,      X86::ROL8m1,     0 },
187     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
188     { X86::ROL8ri,      X86::ROL8mi,     0 },
189     { X86::ROR16r1,     X86::ROR16m1,    0 },
190     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
191     { X86::ROR16ri,     X86::ROR16mi,    0 },
192     { X86::ROR32r1,     X86::ROR32m1,    0 },
193     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
194     { X86::ROR32ri,     X86::ROR32mi,    0 },
195     { X86::ROR64r1,     X86::ROR64m1,    0 },
196     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
197     { X86::ROR64ri,     X86::ROR64mi,    0 },
198     { X86::ROR8r1,      X86::ROR8m1,     0 },
199     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
200     { X86::ROR8ri,      X86::ROR8mi,     0 },
201     { X86::SAR16r1,     X86::SAR16m1,    0 },
202     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
203     { X86::SAR16ri,     X86::SAR16mi,    0 },
204     { X86::SAR32r1,     X86::SAR32m1,    0 },
205     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
206     { X86::SAR32ri,     X86::SAR32mi,    0 },
207     { X86::SAR64r1,     X86::SAR64m1,    0 },
208     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
209     { X86::SAR64ri,     X86::SAR64mi,    0 },
210     { X86::SAR8r1,      X86::SAR8m1,     0 },
211     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
212     { X86::SAR8ri,      X86::SAR8mi,     0 },
213     { X86::SBB32ri,     X86::SBB32mi,    0 },
214     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
215     { X86::SBB32rr,     X86::SBB32mr,    0 },
216     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
217     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
218     { X86::SBB64rr,     X86::SBB64mr,    0 },
219     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
220     { X86::SHL16ri,     X86::SHL16mi,    0 },
221     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
222     { X86::SHL32ri,     X86::SHL32mi,    0 },
223     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
224     { X86::SHL64ri,     X86::SHL64mi,    0 },
225     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
226     { X86::SHL8ri,      X86::SHL8mi,     0 },
227     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
228     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
229     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
230     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
231     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
232     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
233     { X86::SHR16r1,     X86::SHR16m1,    0 },
234     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
235     { X86::SHR16ri,     X86::SHR16mi,    0 },
236     { X86::SHR32r1,     X86::SHR32m1,    0 },
237     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
238     { X86::SHR32ri,     X86::SHR32mi,    0 },
239     { X86::SHR64r1,     X86::SHR64m1,    0 },
240     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
241     { X86::SHR64ri,     X86::SHR64mi,    0 },
242     { X86::SHR8r1,      X86::SHR8m1,     0 },
243     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
244     { X86::SHR8ri,      X86::SHR8mi,     0 },
245     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
246     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
247     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
248     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
249     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
250     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
251     { X86::SUB16ri,     X86::SUB16mi,    0 },
252     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
253     { X86::SUB16rr,     X86::SUB16mr,    0 },
254     { X86::SUB32ri,     X86::SUB32mi,    0 },
255     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
256     { X86::SUB32rr,     X86::SUB32mr,    0 },
257     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
258     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
259     { X86::SUB64rr,     X86::SUB64mr,    0 },
260     { X86::SUB8ri,      X86::SUB8mi,     0 },
261     { X86::SUB8rr,      X86::SUB8mr,     0 },
262     { X86::XOR16ri,     X86::XOR16mi,    0 },
263     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
264     { X86::XOR16rr,     X86::XOR16mr,    0 },
265     { X86::XOR32ri,     X86::XOR32mi,    0 },
266     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
267     { X86::XOR32rr,     X86::XOR32mr,    0 },
268     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
269     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
270     { X86::XOR64rr,     X86::XOR64mr,    0 },
271     { X86::XOR8ri,      X86::XOR8mi,     0 },
272     { X86::XOR8rr,      X86::XOR8mr,     0 }
273   };
274 
275   for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
276     unsigned RegOp = OpTbl2Addr[i].RegOp;
277     unsigned MemOp = OpTbl2Addr[i].MemOp;
278     unsigned Flags = OpTbl2Addr[i].Flags;
279     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
280                   RegOp, MemOp,
281                   // Index 0, folded load and store, no alignment requirement.
282                   Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
283   }
284 
285   static const X86OpTblEntry OpTbl0[] = {
286     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
287     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
288     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
289     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
290     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
291     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
292     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
293     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
294     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
295     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
296     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
297     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
298     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
299     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
300     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
301     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
302     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
303     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
304     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
305     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
306     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
307     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
308     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
309     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
310     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
311     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
312     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
313     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
314     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
315     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
316     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
317     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
318     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
319     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
320     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
321     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
322     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
323     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
324     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
325     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
326     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
327     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
328     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
329     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
330     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
331     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
332     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
333     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
334     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
335     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
336     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
337     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
338     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
339     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
340     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
341     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
342     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
343     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
344     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
345     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
346     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
347     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
348     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
349     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
350     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
351     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
352     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
353     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
354     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
355     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
356     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
357     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
358     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
359     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
360     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
361     // AVX 128-bit versions of foldable instructions
362     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
363     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
364     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
365     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
366     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
367     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
368     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
369     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
370     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
371     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
372     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
373     // AVX 256-bit foldable instructions
374     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
375     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
376     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
377     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
378     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
379     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
380     // AVX-512 foldable instructions
381     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
382     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
383     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
384     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
385     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
386     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
387     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
388     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
389     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
390     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
391     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
392     // AVX-512 foldable instructions (256-bit versions)
393     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
394     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
395     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
396     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
397     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
398     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
399     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
400     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
401     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
402     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
403     // AVX-512 foldable instructions (128-bit versions)
404     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
405     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
406     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
407     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
408     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
409     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
410     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
411     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
412     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
413     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE }
414   };
415 
416   for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
417     unsigned RegOp      = OpTbl0[i].RegOp;
418     unsigned MemOp      = OpTbl0[i].MemOp;
419     unsigned Flags      = OpTbl0[i].Flags;
420     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
421                   RegOp, MemOp, TB_INDEX_0 | Flags);
422   }
423 
424   static const X86OpTblEntry OpTbl1[] = {
425     { X86::CMP16rr,         X86::CMP16rm,             0 },
426     { X86::CMP32rr,         X86::CMP32rm,             0 },
427     { X86::CMP64rr,         X86::CMP64rm,             0 },
428     { X86::CMP8rr,          X86::CMP8rm,              0 },
429     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
430     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
431     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
432     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
433     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
434     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
435     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
436     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
437     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
438     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
439     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
440     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
441     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
442     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
443     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
444     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
445     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
446     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
447     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
448     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
449     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
450     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
451     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
452     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
453     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
454     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
455     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
456     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
457     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
458     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
459     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
460     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
461     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
462     { X86::MOV16rr,         X86::MOV16rm,             0 },
463     { X86::MOV32rr,         X86::MOV32rm,             0 },
464     { X86::MOV64rr,         X86::MOV64rm,             0 },
465     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
466     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
467     { X86::MOV8rr,          X86::MOV8rm,              0 },
468     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
469     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
470     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
471     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
472     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
473     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
474     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
475     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
476     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
477     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
478     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
479     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
480     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
481     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
482     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
483     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
484     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
485     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
486     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
487     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
488     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
489     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
490     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
491     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
492     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
493     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
494     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
495     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
496     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
497     { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
498     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
499     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
500     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
501     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
502     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
503     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
504     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
505     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
506     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
507     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
508     { X86::TEST16rr,        X86::TEST16rm,            0 },
509     { X86::TEST32rr,        X86::TEST32rm,            0 },
510     { X86::TEST64rr,        X86::TEST64rm,            0 },
511     { X86::TEST8rr,         X86::TEST8rm,             0 },
512     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
513     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
514     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
515     // AVX 128-bit versions of foldable instructions
516     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
517     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
518     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
519     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
520     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
521     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
522     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
523     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
524     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
525     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
526     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
527     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
528     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
529     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
530     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
531     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
532     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
533     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
534     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
535     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
536     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
537     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
538     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
539     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
540     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
541     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
542     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
543     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
544     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
545     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
546     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
547     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
548     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
549     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
550     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
551     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
552     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
553     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
554     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
555     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
556     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
557     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
558     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
559     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
560     { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
561     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
562     { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
563     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
564     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
565     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
566     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
567     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
568 
569     // AVX 256-bit foldable instructions
570     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
571     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
572     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
573     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
574     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
575     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
576     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
577     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
578     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
579     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
580     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
581     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
582     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
583     { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
584     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
585     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
586     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
587     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
588     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
589 
590     // AVX2 foldable instructions
591     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
592     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
593     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
594     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
595     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
596     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
597 
598     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
599     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
600     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
601     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
602     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
603     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
604     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
605     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
606     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
607     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
608     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
609     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
610     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
611     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
612     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
613     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
614     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
615     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
616     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
617     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
618     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
619     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
620     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
621     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
622     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
623     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
624     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
625     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
626     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
627     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
628     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
629     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
630     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
631     { X86::RORX32ri,        X86::RORX32mi,            0 },
632     { X86::RORX64ri,        X86::RORX64mi,            0 },
633     { X86::SARX32rr,        X86::SARX32rm,            0 },
634     { X86::SARX64rr,        X86::SARX64rm,            0 },
635     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
636     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
637     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
638     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
639     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
640     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
641     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
642     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
643     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
644     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
645     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
646 
647     // AVX-512 foldable instructions
648     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
649     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
650     { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
651     { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
652     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
653     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
654     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zrm,         0 },
655     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zrm,        0 },
656     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
657     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
658     { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
659     { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
660     { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
661     { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
662     { X86::VBROADCASTSSZr,  X86::VBROADCASTSSZm,      TB_NO_REVERSE },
663     { X86::VBROADCASTSDZr,  X86::VBROADCASTSDZm,      TB_NO_REVERSE },
664     // AVX-512 foldable instructions (256-bit versions)
665     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256rm,          TB_ALIGN_32 },
666     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256rm,          TB_ALIGN_32 },
667     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256rm,        TB_ALIGN_32 },
668     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256rm,        TB_ALIGN_32 },
669     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256rm,         0 },
670     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256rm,        0 },
671     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256rm,        0 },
672     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256rm,        0 },
673     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256rm,          0 },
674     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256rm,          0 },
675     { X86::VBROADCASTSSZ256r,  X86::VBROADCASTSSZ256m,      TB_NO_REVERSE },
676     { X86::VBROADCASTSDZ256r,  X86::VBROADCASTSDZ256m,      TB_NO_REVERSE },
677     // AVX-512 foldable instructions (256-bit versions)
678     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128rm,          TB_ALIGN_16 },
679     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128rm,          TB_ALIGN_16 },
680     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128rm,        TB_ALIGN_16 },
681     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128rm,        TB_ALIGN_16 },
682     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128rm,         0 },
683     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128rm,        0 },
684     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128rm,        0 },
685     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128rm,        0 },
686     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128rm,          0 },
687     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128rm,          0 },
688     { X86::VBROADCASTSSZ128r,  X86::VBROADCASTSSZ128m,      TB_NO_REVERSE },
689 
690     // AES foldable instructions
691     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
692     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
693     { X86::VAESIMCrr,             X86::VAESIMCrm,             TB_ALIGN_16 },
694     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 }
695   };
696 
697   for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
698     unsigned RegOp = OpTbl1[i].RegOp;
699     unsigned MemOp = OpTbl1[i].MemOp;
700     unsigned Flags = OpTbl1[i].Flags;
701     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
702                   RegOp, MemOp,
703                   // Index 1, folded load
704                   Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
705   }
706 
707   static const X86OpTblEntry OpTbl2[] = {
708     { X86::ADC32rr,         X86::ADC32rm,       0 },
709     { X86::ADC64rr,         X86::ADC64rm,       0 },
710     { X86::ADD16rr,         X86::ADD16rm,       0 },
711     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
712     { X86::ADD32rr,         X86::ADD32rm,       0 },
713     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
714     { X86::ADD64rr,         X86::ADD64rm,       0 },
715     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
716     { X86::ADD8rr,          X86::ADD8rm,        0 },
717     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
718     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
719     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
720     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
721     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
722     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
723     { X86::AND16rr,         X86::AND16rm,       0 },
724     { X86::AND32rr,         X86::AND32rm,       0 },
725     { X86::AND64rr,         X86::AND64rm,       0 },
726     { X86::AND8rr,          X86::AND8rm,        0 },
727     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
728     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
729     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
730     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
731     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
732     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
733     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
734     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
735     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
736     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
737     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
738     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
739     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
740     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
741     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
742     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
743     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
744     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
745     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
746     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
747     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
748     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
749     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
750     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
751     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
752     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
753     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
754     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
755     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
756     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
757     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
758     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
759     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
760     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
761     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
762     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
763     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
764     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
765     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
766     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
767     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
768     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
769     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
770     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
771     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
772     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
773     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
774     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
775     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
776     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
777     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
778     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
779     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
780     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
781     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
782     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
783     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
784     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
785     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
786     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
787     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
788     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
789     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
790     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
791     { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
792     { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
793     { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
794     { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
795     { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
796     { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
797     { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
798     { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
799     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
800     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
801     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
802     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
803     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
804     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
805     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
806     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
807     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
808     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
809     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
810     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
811     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
812     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
813     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
814     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
815     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
816     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
817     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
818     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
819     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
820     { X86::MINSDrr,         X86::MINSDrm,       0 },
821     { X86::MINSSrr,         X86::MINSSrm,       0 },
822     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
823     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
824     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
825     { X86::MULSDrr,         X86::MULSDrm,       0 },
826     { X86::MULSSrr,         X86::MULSSrm,       0 },
827     { X86::OR16rr,          X86::OR16rm,        0 },
828     { X86::OR32rr,          X86::OR32rm,        0 },
829     { X86::OR64rr,          X86::OR64rm,        0 },
830     { X86::OR8rr,           X86::OR8rm,         0 },
831     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
832     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
833     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
834     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
835     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
836     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
837     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
838     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
839     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
840     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
841     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
842     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
843     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
844     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
845     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
846     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
847     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
848     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
849     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
850     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
851     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
852     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
853     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
854     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
855     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
856     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
857     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
858     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
859     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
860     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
861     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
862     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
863     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
864     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
865     { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
866     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
867     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
868     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
869     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
870     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
871     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
872     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
873     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
874     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
875     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
876     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
877     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
878     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
879     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
880     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
881     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
882     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
883     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
884     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
885     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
886     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
887     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
888     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
889     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
890     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
891     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
892     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
893     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
894     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
895     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
896     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
897     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
898     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
899     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
900     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
901     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
902     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
903     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
904     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
905     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
906     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
907     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
908     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
909     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
910     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
911     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
912     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
913     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
914     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
915     { X86::SBB32rr,         X86::SBB32rm,       0 },
916     { X86::SBB64rr,         X86::SBB64rm,       0 },
917     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
918     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
919     { X86::SUB16rr,         X86::SUB16rm,       0 },
920     { X86::SUB32rr,         X86::SUB32rm,       0 },
921     { X86::SUB64rr,         X86::SUB64rm,       0 },
922     { X86::SUB8rr,          X86::SUB8rm,        0 },
923     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
924     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
925     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
926     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
927     // FIXME: TEST*rr -> swapped operand of TEST*mr.
928     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
929     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
930     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
931     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
932     { X86::XOR16rr,         X86::XOR16rm,       0 },
933     { X86::XOR32rr,         X86::XOR32rm,       0 },
934     { X86::XOR64rr,         X86::XOR64rm,       0 },
935     { X86::XOR8rr,          X86::XOR8rm,        0 },
936     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
937     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
938     // AVX 128-bit versions of foldable instructions
939     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
940     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
941     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
942     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
943     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
944     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
945     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
946     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
947     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
948     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
949     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
950     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
951     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
952     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
953     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
954     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
955     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
956     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
957     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
958     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
959     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
960     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
961     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
962     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
963     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
964     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
965     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
966     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
967     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
968     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
969     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
970     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
971     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
972     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
973     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
974     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
975     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
976     { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
977     { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
978     { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
979     { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
980     { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
981     { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
982     { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
983     { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
984     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
985     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
986     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
987     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
988     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
989     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
990     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
991     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
992     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
993     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
994     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
995     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
996     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
997     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
998     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
999     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1000     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1001     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1002     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1003     { X86::VORPDrr,           X86::VORPDrm,            0 },
1004     { X86::VORPSrr,           X86::VORPSrm,            0 },
1005     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1006     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1007     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1008     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1009     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1010     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1011     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1012     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1013     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1014     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1015     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1016     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1017     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
1018     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1019     { X86::VPANDrr,           X86::VPANDrm,            0 },
1020     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1021     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1022     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1023     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1024     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1025     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1026     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1027     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1028     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1029     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1030     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1031     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1032     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1033     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1034     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1035     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1036     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1037     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1038     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1039     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1040     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1041     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1042     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1043     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1044     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1045     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1046     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1047     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1048     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1049     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1050     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1051     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1052     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1053     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1054     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1055     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1056     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1057     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1058     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1059     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1060     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1061     { X86::VPORrr,            X86::VPORrm,             0 },
1062     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1063     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1064     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
1065     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
1066     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
1067     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1068     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1069     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1070     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1071     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1072     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1073     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1074     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1075     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1076     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1077     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1078     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1079     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1080     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1081     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1082     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1083     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1084     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1085     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1086     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1087     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1088     { X86::VPXORrr,           X86::VPXORrm,            0 },
1089     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1090     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1091     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1092     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1093     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1094     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1095     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1096     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1097     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1098     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1099     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1100     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1101     // AVX 256-bit foldable instructions
1102     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1103     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1104     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1105     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1106     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1107     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1108     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1109     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1110     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1111     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1112     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1113     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1114     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1115     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1116     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1117     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1118     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1119     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1120     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1121     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1122     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1123     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1124     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1125     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1126     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1127     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1128     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1129     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1130     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1131     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1132     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1133     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1134     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1135     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1136     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1137     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1138     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1139     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1140     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1141     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1142     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1143     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1144     // AVX2 foldable instructions
1145     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1146     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1147     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1148     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1149     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1150     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1151     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1152     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1153     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1154     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1155     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1156     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1157     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1158     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1159     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1160     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1161     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1162     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1163     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1164     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1165     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1166     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1167     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1168     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1169     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1170     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1171     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1172     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1173     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1174     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1175     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1176     { X86::VPERMPDYri,        X86::VPERMPDYmi,         0 },
1177     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1178     { X86::VPERMQYri,         X86::VPERMQYmi,          0 },
1179     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1180     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1181     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1182     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1183     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1184     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1185     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1186     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1187     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1188     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1189     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1190     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1191     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1192     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1193     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1194     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1195     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1196     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1197     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1198     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1199     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1200     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1201     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1202     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1203     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1204     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1205     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1206     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1207     { X86::VPORYrr,           X86::VPORYrm,            0 },
1208     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1209     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1210     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1211     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1212     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1213     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1214     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1215     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1216     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1217     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1218     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1219     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1220     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1221     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1222     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1223     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1224     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1225     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1226     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1227     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1228     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1229     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1230     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1231     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1232     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1233     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1234     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1235     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1236     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1237     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1238     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1239     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1240     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1241     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1242     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1243     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1244     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1245     // FIXME: add AVX 256-bit foldable instructions
1246 
1247     // FMA4 foldable patterns
1248     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0           },
1249     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0           },
1250     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_16 },
1251     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_16 },
1252     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_32 },
1253     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_32 },
1254     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0           },
1255     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0           },
1256     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_16 },
1257     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_16 },
1258     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_32 },
1259     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_32 },
1260     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0           },
1261     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0           },
1262     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_16 },
1263     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_16 },
1264     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_32 },
1265     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_32 },
1266     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0           },
1267     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0           },
1268     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_16 },
1269     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_16 },
1270     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_32 },
1271     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_32 },
1272     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_16 },
1273     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_16 },
1274     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_32 },
1275     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_32 },
1276     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_16 },
1277     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_16 },
1278     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_32 },
1279     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_32 },
1280 
1281     // BMI/BMI2 foldable instructions
1282     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1283     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1284     { X86::MULX32rr,          X86::MULX32rm,            0 },
1285     { X86::MULX64rr,          X86::MULX64rm,            0 },
1286     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1287     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1288     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1289     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1290 
1291     // AVX-512 foldable instructions
1292     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1293     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1294     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1295     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1296     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1297     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1298     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1299     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1300     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1301     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1302     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1303     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1304     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1305     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1306     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1307     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1308     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1309     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1310     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1311     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1312     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1313     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1314     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1315     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1316     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1317     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1318     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1319     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1320     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1321     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1322     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1323     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1324     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1325     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1326     { X86::VALIGNQrri,        X86::VALIGNQrmi,          0 },
1327     { X86::VALIGNDrri,        X86::VALIGNDrmi,          0 },
1328     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1329     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1330     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1331 
1332     // AVX-512{F,VL} foldable instructions
1333     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1334     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1335     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1336 
1337     // AES foldable instructions
1338     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1339     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1340     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1341     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1342     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       TB_ALIGN_16 },
1343     { X86::VAESDECrr,         X86::VAESDECrm,           TB_ALIGN_16 },
1344     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       TB_ALIGN_16 },
1345     { X86::VAESENCrr,         X86::VAESENCrm,           TB_ALIGN_16 },
1346 
1347     // SHA foldable instructions
1348     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1349     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1350     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1351     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1352     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1353     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1354     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 },
1355   };
1356 
1357   for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1358     unsigned RegOp = OpTbl2[i].RegOp;
1359     unsigned MemOp = OpTbl2[i].MemOp;
1360     unsigned Flags = OpTbl2[i].Flags;
1361     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1362                   RegOp, MemOp,
1363                   // Index 2, folded load
1364                   Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1365   }
1366 
1367   static const X86OpTblEntry OpTbl3[] = {
1368     // FMA foldable instructions
1369     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1370     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1371     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1372     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1373     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1374     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1375 
1376     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1377     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1378     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1379     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1380     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1381     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1382     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1383     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1384     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1385     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1386     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1387     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1388 
1389     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1390     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1391     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1392     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1393     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1394     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1395 
1396     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1397     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1398     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1399     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1400     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1401     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1402     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1403     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1404     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1405     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1406     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1407     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1408 
1409     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1410     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1411     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1412     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1413     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1414     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1415 
1416     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1417     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1418     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1419     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1420     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1421     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1422     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1423     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1424     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1425     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1426     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1427     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1428 
1429     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1430     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1431     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1432     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1433     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1434     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1435 
1436     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1437     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1438     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1439     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1440     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1441     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1442     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1443     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1444     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1445     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1446     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1447     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1448 
1449     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1450     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1451     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1452     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1453     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1454     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1455     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1456     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1457     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1458     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1459     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1460     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1461 
1462     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1463     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1464     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1465     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1466     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1467     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1468     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1469     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1470     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1471     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1472     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1473     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1474 
1475     // FMA4 foldable patterns
1476     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1477     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1478     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1479     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1480     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1481     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1482     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1483     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1484     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1485     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1486     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1487     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1488     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1489     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1490     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1491     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1492     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1493     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1494     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1495     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1496     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1497     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1498     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1499     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1500     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1501     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1502     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1503     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1504     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1505     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1506     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1507     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1508     // AVX-512 VPERMI instructions with 3 source operands.
1509     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1510     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1511     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1512     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1513     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1514     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1515     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1516     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1517     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1518     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1519     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1520     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1521     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE }
1522   };
1523 
1524   for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1525     unsigned RegOp = OpTbl3[i].RegOp;
1526     unsigned MemOp = OpTbl3[i].MemOp;
1527     unsigned Flags = OpTbl3[i].Flags;
1528     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1529                   RegOp, MemOp,
1530                   // Index 3, folded load
1531                   Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1532   }
1533 
1534 }
1535 
1536 void
1537 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1538                             MemOp2RegOpTableType &M2RTable,
1539                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
1540     if ((Flags & TB_NO_FORWARD) == 0) {
1541       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1542       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1543     }
1544     if ((Flags & TB_NO_REVERSE) == 0) {
1545       assert(!M2RTable.count(MemOp) &&
1546            "Duplicated entries in unfolding maps?");
1547       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1548     }
1549 }
1550 
1551 bool
1552 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1553                                     unsigned &SrcReg, unsigned &DstReg,
1554                                     unsigned &SubIdx) const {
1555   switch (MI.getOpcode()) {
1556   default: break;
1557   case X86::MOVSX16rr8:
1558   case X86::MOVZX16rr8:
1559   case X86::MOVSX32rr8:
1560   case X86::MOVZX32rr8:
1561   case X86::MOVSX64rr8:
1562     if (!Subtarget.is64Bit())
1563       // It's not always legal to reference the low 8-bit of the larger
1564       // register in 32-bit mode.
1565       return false;
1566   case X86::MOVSX32rr16:
1567   case X86::MOVZX32rr16:
1568   case X86::MOVSX64rr16:
1569   case X86::MOVSX64rr32: {
1570     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1571       // Be conservative.
1572       return false;
1573     SrcReg = MI.getOperand(1).getReg();
1574     DstReg = MI.getOperand(0).getReg();
1575     switch (MI.getOpcode()) {
1576     default: llvm_unreachable("Unreachable!");
1577     case X86::MOVSX16rr8:
1578     case X86::MOVZX16rr8:
1579     case X86::MOVSX32rr8:
1580     case X86::MOVZX32rr8:
1581     case X86::MOVSX64rr8:
1582       SubIdx = X86::sub_8bit;
1583       break;
1584     case X86::MOVSX32rr16:
1585     case X86::MOVZX32rr16:
1586     case X86::MOVSX64rr16:
1587       SubIdx = X86::sub_16bit;
1588       break;
1589     case X86::MOVSX64rr32:
1590       SubIdx = X86::sub_32bit;
1591       break;
1592     }
1593     return true;
1594   }
1595   }
1596   return false;
1597 }
1598 
1599 /// isFrameOperand - Return true and the FrameIndex if the specified
1600 /// operand and follow operands form a reference to the stack frame.
1601 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1602                                   int &FrameIndex) const {
1603   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
1604       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
1605       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
1606       MI->getOperand(Op+X86::AddrDisp).isImm() &&
1607       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
1608       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
1609       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
1610     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
1611     return true;
1612   }
1613   return false;
1614 }
1615 
1616 static bool isFrameLoadOpcode(int Opcode) {
1617   switch (Opcode) {
1618   default:
1619     return false;
1620   case X86::MOV8rm:
1621   case X86::MOV16rm:
1622   case X86::MOV32rm:
1623   case X86::MOV64rm:
1624   case X86::LD_Fp64m:
1625   case X86::MOVSSrm:
1626   case X86::MOVSDrm:
1627   case X86::MOVAPSrm:
1628   case X86::MOVAPDrm:
1629   case X86::MOVDQArm:
1630   case X86::VMOVSSrm:
1631   case X86::VMOVSDrm:
1632   case X86::VMOVAPSrm:
1633   case X86::VMOVAPDrm:
1634   case X86::VMOVDQArm:
1635   case X86::VMOVUPSYrm:
1636   case X86::VMOVAPSYrm:
1637   case X86::VMOVUPDYrm:
1638   case X86::VMOVAPDYrm:
1639   case X86::VMOVDQUYrm:
1640   case X86::VMOVDQAYrm:
1641   case X86::MMX_MOVD64rm:
1642   case X86::MMX_MOVQ64rm:
1643   case X86::VMOVAPSZrm:
1644   case X86::VMOVUPSZrm:
1645     return true;
1646   }
1647 }
1648 
1649 static bool isFrameStoreOpcode(int Opcode) {
1650   switch (Opcode) {
1651   default: break;
1652   case X86::MOV8mr:
1653   case X86::MOV16mr:
1654   case X86::MOV32mr:
1655   case X86::MOV64mr:
1656   case X86::ST_FpP64m:
1657   case X86::MOVSSmr:
1658   case X86::MOVSDmr:
1659   case X86::MOVAPSmr:
1660   case X86::MOVAPDmr:
1661   case X86::MOVDQAmr:
1662   case X86::VMOVSSmr:
1663   case X86::VMOVSDmr:
1664   case X86::VMOVAPSmr:
1665   case X86::VMOVAPDmr:
1666   case X86::VMOVDQAmr:
1667   case X86::VMOVUPSYmr:
1668   case X86::VMOVAPSYmr:
1669   case X86::VMOVUPDYmr:
1670   case X86::VMOVAPDYmr:
1671   case X86::VMOVDQUYmr:
1672   case X86::VMOVDQAYmr:
1673   case X86::VMOVUPSZmr:
1674   case X86::VMOVAPSZmr:
1675   case X86::MMX_MOVD64mr:
1676   case X86::MMX_MOVQ64mr:
1677   case X86::MMX_MOVNTQmr:
1678     return true;
1679   }
1680   return false;
1681 }
1682 
1683 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1684                                            int &FrameIndex) const {
1685   if (isFrameLoadOpcode(MI->getOpcode()))
1686     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1687       return MI->getOperand(0).getReg();
1688   return 0;
1689 }
1690 
1691 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1692                                                  int &FrameIndex) const {
1693   if (isFrameLoadOpcode(MI->getOpcode())) {
1694     unsigned Reg;
1695     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1696       return Reg;
1697     // Check for post-frame index elimination operations
1698     const MachineMemOperand *Dummy;
1699     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1700   }
1701   return 0;
1702 }
1703 
1704 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1705                                           int &FrameIndex) const {
1706   if (isFrameStoreOpcode(MI->getOpcode()))
1707     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1708         isFrameOperand(MI, 0, FrameIndex))
1709       return MI->getOperand(X86::AddrNumOperands).getReg();
1710   return 0;
1711 }
1712 
1713 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1714                                                 int &FrameIndex) const {
1715   if (isFrameStoreOpcode(MI->getOpcode())) {
1716     unsigned Reg;
1717     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1718       return Reg;
1719     // Check for post-frame index elimination operations
1720     const MachineMemOperand *Dummy;
1721     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1722   }
1723   return 0;
1724 }
1725 
1726 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1727 /// X86::MOVPC32r.
1728 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1729   // Don't waste compile time scanning use-def chains of physregs.
1730   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1731     return false;
1732   bool isPICBase = false;
1733   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
1734          E = MRI.def_instr_end(); I != E; ++I) {
1735     MachineInstr *DefMI = &*I;
1736     if (DefMI->getOpcode() != X86::MOVPC32r)
1737       return false;
1738     assert(!isPICBase && "More than one PIC base?");
1739     isPICBase = true;
1740   }
1741   return isPICBase;
1742 }
1743 
1744 bool
1745 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1746                                                 AliasAnalysis *AA) const {
1747   switch (MI->getOpcode()) {
1748   default: break;
1749   case X86::MOV8rm:
1750   case X86::MOV16rm:
1751   case X86::MOV32rm:
1752   case X86::MOV64rm:
1753   case X86::LD_Fp64m:
1754   case X86::MOVSSrm:
1755   case X86::MOVSDrm:
1756   case X86::MOVAPSrm:
1757   case X86::MOVUPSrm:
1758   case X86::MOVAPDrm:
1759   case X86::MOVDQArm:
1760   case X86::MOVDQUrm:
1761   case X86::VMOVSSrm:
1762   case X86::VMOVSDrm:
1763   case X86::VMOVAPSrm:
1764   case X86::VMOVUPSrm:
1765   case X86::VMOVAPDrm:
1766   case X86::VMOVDQArm:
1767   case X86::VMOVDQUrm:
1768   case X86::VMOVAPSYrm:
1769   case X86::VMOVUPSYrm:
1770   case X86::VMOVAPDYrm:
1771   case X86::VMOVDQAYrm:
1772   case X86::VMOVDQUYrm:
1773   case X86::MMX_MOVD64rm:
1774   case X86::MMX_MOVQ64rm:
1775   case X86::FsVMOVAPSrm:
1776   case X86::FsVMOVAPDrm:
1777   case X86::FsMOVAPSrm:
1778   case X86::FsMOVAPDrm: {
1779     // Loads from constant pools are trivially rematerializable.
1780     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
1781         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1782         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1783         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1784         MI->isInvariantLoad(AA)) {
1785       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1786       if (BaseReg == 0 || BaseReg == X86::RIP)
1787         return true;
1788       // Allow re-materialization of PIC load.
1789       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
1790         return false;
1791       const MachineFunction &MF = *MI->getParent()->getParent();
1792       const MachineRegisterInfo &MRI = MF.getRegInfo();
1793       return regIsPICBase(BaseReg, MRI);
1794     }
1795     return false;
1796   }
1797 
1798   case X86::LEA32r:
1799   case X86::LEA64r: {
1800     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
1801         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
1802         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
1803         !MI->getOperand(1+X86::AddrDisp).isReg()) {
1804       // lea fi#, lea GV, etc. are all rematerializable.
1805       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
1806         return true;
1807       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
1808       if (BaseReg == 0)
1809         return true;
1810       // Allow re-materialization of lea PICBase + x.
1811       const MachineFunction &MF = *MI->getParent()->getParent();
1812       const MachineRegisterInfo &MRI = MF.getRegInfo();
1813       return regIsPICBase(BaseReg, MRI);
1814     }
1815     return false;
1816   }
1817   }
1818 
1819   // All other instructions marked M_REMATERIALIZABLE are always trivially
1820   // rematerializable.
1821   return true;
1822 }
1823 
1824 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1825                                          MachineBasicBlock::iterator I) const {
1826   MachineBasicBlock::iterator E = MBB.end();
1827 
1828   // For compile time consideration, if we are not able to determine the
1829   // safety after visiting 4 instructions in each direction, we will assume
1830   // it's not safe.
1831   MachineBasicBlock::iterator Iter = I;
1832   for (unsigned i = 0; Iter != E && i < 4; ++i) {
1833     bool SeenDef = false;
1834     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1835       MachineOperand &MO = Iter->getOperand(j);
1836       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1837         SeenDef = true;
1838       if (!MO.isReg())
1839         continue;
1840       if (MO.getReg() == X86::EFLAGS) {
1841         if (MO.isUse())
1842           return false;
1843         SeenDef = true;
1844       }
1845     }
1846 
1847     if (SeenDef)
1848       // This instruction defines EFLAGS, no need to look any further.
1849       return true;
1850     ++Iter;
1851     // Skip over DBG_VALUE.
1852     while (Iter != E && Iter->isDebugValue())
1853       ++Iter;
1854   }
1855 
1856   // It is safe to clobber EFLAGS at the end of a block of no successor has it
1857   // live in.
1858   if (Iter == E) {
1859     for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1860            SE = MBB.succ_end(); SI != SE; ++SI)
1861       if ((*SI)->isLiveIn(X86::EFLAGS))
1862         return false;
1863     return true;
1864   }
1865 
1866   MachineBasicBlock::iterator B = MBB.begin();
1867   Iter = I;
1868   for (unsigned i = 0; i < 4; ++i) {
1869     // If we make it to the beginning of the block, it's safe to clobber
1870     // EFLAGS iff EFLAGS is not live-in.
1871     if (Iter == B)
1872       return !MBB.isLiveIn(X86::EFLAGS);
1873 
1874     --Iter;
1875     // Skip over DBG_VALUE.
1876     while (Iter != B && Iter->isDebugValue())
1877       --Iter;
1878 
1879     bool SawKill = false;
1880     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1881       MachineOperand &MO = Iter->getOperand(j);
1882       // A register mask may clobber EFLAGS, but we should still look for a
1883       // live EFLAGS def.
1884       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1885         SawKill = true;
1886       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1887         if (MO.isDef()) return MO.isDead();
1888         if (MO.isKill()) SawKill = true;
1889       }
1890     }
1891 
1892     if (SawKill)
1893       // This instruction kills EFLAGS and doesn't redefine it, so
1894       // there's no need to look further.
1895       return true;
1896   }
1897 
1898   // Conservative answer.
1899   return false;
1900 }
1901 
1902 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1903                                  MachineBasicBlock::iterator I,
1904                                  unsigned DestReg, unsigned SubIdx,
1905                                  const MachineInstr *Orig,
1906                                  const TargetRegisterInfo &TRI) const {
1907   // MOV32r0 is implemented with a xor which clobbers condition code.
1908   // Re-materialize it as movri instructions to avoid side effects.
1909   unsigned Opc = Orig->getOpcode();
1910   if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
1911     DebugLoc DL = Orig->getDebugLoc();
1912     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
1913       .addImm(0);
1914   } else {
1915     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1916     MBB.insert(I, MI);
1917   }
1918 
1919   MachineInstr *NewMI = std::prev(I);
1920   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1921 }
1922 
1923 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1924 /// is not marked dead.
1925 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1926   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1927     MachineOperand &MO = MI->getOperand(i);
1928     if (MO.isReg() && MO.isDef() &&
1929         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1930       return true;
1931     }
1932   }
1933   return false;
1934 }
1935 
1936 /// getTruncatedShiftCount - check whether the shift count for a machine operand
1937 /// is non-zero.
1938 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
1939                                               unsigned ShiftAmtOperandIdx) {
1940   // The shift count is six bits with the REX.W prefix and five bits without.
1941   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1942   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
1943   return Imm & ShiftCountMask;
1944 }
1945 
1946 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
1947 /// can be represented by a LEA instruction.
1948 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1949   // Left shift instructions can be transformed into load-effective-address
1950   // instructions if we can encode them appropriately.
1951   // A LEA instruction utilizes a SIB byte to encode it's scale factor.
1952   // The SIB.scale field is two bits wide which means that we can encode any
1953   // shift amount less than 4.
1954   return ShAmt < 4 && ShAmt > 0;
1955 }
1956 
1957 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
1958                                   unsigned Opc, bool AllowSP,
1959                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
1960                                   MachineOperand &ImplicitOp) const {
1961   MachineFunction &MF = *MI->getParent()->getParent();
1962   const TargetRegisterClass *RC;
1963   if (AllowSP) {
1964     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1965   } else {
1966     RC = Opc != X86::LEA32r ?
1967       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1968   }
1969   unsigned SrcReg = Src.getReg();
1970 
1971   // For both LEA64 and LEA32 the register already has essentially the right
1972   // type (32-bit or 64-bit) we may just need to forbid SP.
1973   if (Opc != X86::LEA64_32r) {
1974     NewSrc = SrcReg;
1975     isKill = Src.isKill();
1976     isUndef = Src.isUndef();
1977 
1978     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
1979         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1980       return false;
1981 
1982     return true;
1983   }
1984 
1985   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1986   // another we need to add 64-bit registers to the final MI.
1987   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1988     ImplicitOp = Src;
1989     ImplicitOp.setImplicit();
1990 
1991     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
1992     MachineBasicBlock::LivenessQueryResult LQR =
1993       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
1994 
1995     switch (LQR) {
1996     case MachineBasicBlock::LQR_Unknown:
1997       // We can't give sane liveness flags to the instruction, abandon LEA
1998       // formation.
1999       return false;
2000     case MachineBasicBlock::LQR_Live:
2001       isKill = MI->killsRegister(SrcReg);
2002       isUndef = false;
2003       break;
2004     default:
2005       // The physreg itself is dead, so we have to use it as an <undef>.
2006       isKill = false;
2007       isUndef = true;
2008       break;
2009     }
2010   } else {
2011     // Virtual register of the wrong class, we have to create a temporary 64-bit
2012     // vreg to feed into the LEA.
2013     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2014     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2015             get(TargetOpcode::COPY))
2016       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2017         .addOperand(Src);
2018 
2019     // Which is obviously going to be dead after we're done with it.
2020     isKill = true;
2021     isUndef = false;
2022   }
2023 
2024   // We've set all the parameters without issue.
2025   return true;
2026 }
2027 
2028 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
2029 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
2030 /// to a 32-bit superregister and then truncating back down to a 16-bit
2031 /// subregister.
2032 MachineInstr *
2033 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2034                                            MachineFunction::iterator &MFI,
2035                                            MachineBasicBlock::iterator &MBBI,
2036                                            LiveVariables *LV) const {
2037   MachineInstr *MI = MBBI;
2038   unsigned Dest = MI->getOperand(0).getReg();
2039   unsigned Src = MI->getOperand(1).getReg();
2040   bool isDead = MI->getOperand(0).isDead();
2041   bool isKill = MI->getOperand(1).isKill();
2042 
2043   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2044   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2045   unsigned Opc, leaInReg;
2046   if (Subtarget.is64Bit()) {
2047     Opc = X86::LEA64_32r;
2048     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2049   } else {
2050     Opc = X86::LEA32r;
2051     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2052   }
2053 
2054   // Build and insert into an implicit UNDEF value. This is OK because
2055   // well be shifting and then extracting the lower 16-bits.
2056   // This has the potential to cause partial register stall. e.g.
2057   //   movw    (%rbp,%rcx,2), %dx
2058   //   leal    -65(%rdx), %esi
2059   // But testing has shown this *does* help performance in 64-bit mode (at
2060   // least on modern x86 machines).
2061   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2062   MachineInstr *InsMI =
2063     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2064     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2065     .addReg(Src, getKillRegState(isKill));
2066 
2067   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2068                                     get(Opc), leaOutReg);
2069   switch (MIOpc) {
2070   default: llvm_unreachable("Unreachable!");
2071   case X86::SHL16ri: {
2072     unsigned ShAmt = MI->getOperand(2).getImm();
2073     MIB.addReg(0).addImm(1 << ShAmt)
2074        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2075     break;
2076   }
2077   case X86::INC16r:
2078   case X86::INC64_16r:
2079     addRegOffset(MIB, leaInReg, true, 1);
2080     break;
2081   case X86::DEC16r:
2082   case X86::DEC64_16r:
2083     addRegOffset(MIB, leaInReg, true, -1);
2084     break;
2085   case X86::ADD16ri:
2086   case X86::ADD16ri8:
2087   case X86::ADD16ri_DB:
2088   case X86::ADD16ri8_DB:
2089     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2090     break;
2091   case X86::ADD16rr:
2092   case X86::ADD16rr_DB: {
2093     unsigned Src2 = MI->getOperand(2).getReg();
2094     bool isKill2 = MI->getOperand(2).isKill();
2095     unsigned leaInReg2 = 0;
2096     MachineInstr *InsMI2 = nullptr;
2097     if (Src == Src2) {
2098       // ADD16rr %reg1028<kill>, %reg1028
2099       // just a single insert_subreg.
2100       addRegReg(MIB, leaInReg, true, leaInReg, false);
2101     } else {
2102       if (Subtarget.is64Bit())
2103         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2104       else
2105         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2106       // Build and insert into an implicit UNDEF value. This is OK because
2107       // well be shifting and then extracting the lower 16-bits.
2108       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2109       InsMI2 =
2110         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2111         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2112         .addReg(Src2, getKillRegState(isKill2));
2113       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2114     }
2115     if (LV && isKill2 && InsMI2)
2116       LV->replaceKillInstruction(Src2, MI, InsMI2);
2117     break;
2118   }
2119   }
2120 
2121   MachineInstr *NewMI = MIB;
2122   MachineInstr *ExtMI =
2123     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2124     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2125     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2126 
2127   if (LV) {
2128     // Update live variables
2129     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2130     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2131     if (isKill)
2132       LV->replaceKillInstruction(Src, MI, InsMI);
2133     if (isDead)
2134       LV->replaceKillInstruction(Dest, MI, ExtMI);
2135   }
2136 
2137   return ExtMI;
2138 }
2139 
2140 /// convertToThreeAddress - This method must be implemented by targets that
2141 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2142 /// may be able to convert a two-address instruction into a true
2143 /// three-address instruction on demand.  This allows the X86 target (for
2144 /// example) to convert ADD and SHL instructions into LEA instructions if they
2145 /// would require register copies due to two-addressness.
2146 ///
2147 /// This method returns a null pointer if the transformation cannot be
2148 /// performed, otherwise it returns the new instruction.
2149 ///
2150 MachineInstr *
2151 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2152                                     MachineBasicBlock::iterator &MBBI,
2153                                     LiveVariables *LV) const {
2154   MachineInstr *MI = MBBI;
2155 
2156   // The following opcodes also sets the condition code register(s). Only
2157   // convert them to equivalent lea if the condition code register def's
2158   // are dead!
2159   if (hasLiveCondCodeDef(MI))
2160     return nullptr;
2161 
2162   MachineFunction &MF = *MI->getParent()->getParent();
2163   // All instructions input are two-addr instructions.  Get the known operands.
2164   const MachineOperand &Dest = MI->getOperand(0);
2165   const MachineOperand &Src = MI->getOperand(1);
2166 
2167   MachineInstr *NewMI = nullptr;
2168   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2169   // we have better subtarget support, enable the 16-bit LEA generation here.
2170   // 16-bit LEA is also slow on Core2.
2171   bool DisableLEA16 = true;
2172   bool is64Bit = Subtarget.is64Bit();
2173 
2174   unsigned MIOpc = MI->getOpcode();
2175   switch (MIOpc) {
2176   case X86::SHL64ri: {
2177     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2178     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2179     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2180 
2181     // LEA can't handle RSP.
2182     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2183         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2184                                            &X86::GR64_NOSPRegClass))
2185       return nullptr;
2186 
2187     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2188       .addOperand(Dest)
2189       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2190     break;
2191   }
2192   case X86::SHL32ri: {
2193     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2194     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2195     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2196 
2197     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2198 
2199     // LEA can't handle ESP.
2200     bool isKill, isUndef;
2201     unsigned SrcReg;
2202     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2203     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2204                         SrcReg, isKill, isUndef, ImplicitOp))
2205       return nullptr;
2206 
2207     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2208       .addOperand(Dest)
2209       .addReg(0).addImm(1 << ShAmt)
2210       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2211       .addImm(0).addReg(0);
2212     if (ImplicitOp.getReg() != 0)
2213       MIB.addOperand(ImplicitOp);
2214     NewMI = MIB;
2215 
2216     break;
2217   }
2218   case X86::SHL16ri: {
2219     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2220     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2221     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2222 
2223     if (DisableLEA16)
2224       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2225     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2226       .addOperand(Dest)
2227       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2228     break;
2229   }
2230   default: {
2231 
2232     switch (MIOpc) {
2233     default: return nullptr;
2234     case X86::INC64r:
2235     case X86::INC32r:
2236     case X86::INC64_32r: {
2237       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2238       unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2239         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2240       bool isKill, isUndef;
2241       unsigned SrcReg;
2242       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2243       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2244                           SrcReg, isKill, isUndef, ImplicitOp))
2245         return nullptr;
2246 
2247       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2248           .addOperand(Dest)
2249           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2250       if (ImplicitOp.getReg() != 0)
2251         MIB.addOperand(ImplicitOp);
2252 
2253       NewMI = addOffset(MIB, 1);
2254       break;
2255     }
2256     case X86::INC16r:
2257     case X86::INC64_16r:
2258       if (DisableLEA16)
2259         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2260                        : nullptr;
2261       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2262       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2263                         .addOperand(Dest).addOperand(Src), 1);
2264       break;
2265     case X86::DEC64r:
2266     case X86::DEC32r:
2267     case X86::DEC64_32r: {
2268       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2269       unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2270         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2271 
2272       bool isKill, isUndef;
2273       unsigned SrcReg;
2274       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2275       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2276                           SrcReg, isKill, isUndef, ImplicitOp))
2277         return nullptr;
2278 
2279       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2280           .addOperand(Dest)
2281           .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2282       if (ImplicitOp.getReg() != 0)
2283         MIB.addOperand(ImplicitOp);
2284 
2285       NewMI = addOffset(MIB, -1);
2286 
2287       break;
2288     }
2289     case X86::DEC16r:
2290     case X86::DEC64_16r:
2291       if (DisableLEA16)
2292         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2293                        : nullptr;
2294       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2295       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2296                         .addOperand(Dest).addOperand(Src), -1);
2297       break;
2298     case X86::ADD64rr:
2299     case X86::ADD64rr_DB:
2300     case X86::ADD32rr:
2301     case X86::ADD32rr_DB: {
2302       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2303       unsigned Opc;
2304       if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2305         Opc = X86::LEA64r;
2306       else
2307         Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2308 
2309       bool isKill, isUndef;
2310       unsigned SrcReg;
2311       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2312       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2313                           SrcReg, isKill, isUndef, ImplicitOp))
2314         return nullptr;
2315 
2316       const MachineOperand &Src2 = MI->getOperand(2);
2317       bool isKill2, isUndef2;
2318       unsigned SrcReg2;
2319       MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2320       if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2321                           SrcReg2, isKill2, isUndef2, ImplicitOp2))
2322         return nullptr;
2323 
2324       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2325         .addOperand(Dest);
2326       if (ImplicitOp.getReg() != 0)
2327         MIB.addOperand(ImplicitOp);
2328       if (ImplicitOp2.getReg() != 0)
2329         MIB.addOperand(ImplicitOp2);
2330 
2331       NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2332 
2333       // Preserve undefness of the operands.
2334       NewMI->getOperand(1).setIsUndef(isUndef);
2335       NewMI->getOperand(3).setIsUndef(isUndef2);
2336 
2337       if (LV && Src2.isKill())
2338         LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2339       break;
2340     }
2341     case X86::ADD16rr:
2342     case X86::ADD16rr_DB: {
2343       if (DisableLEA16)
2344         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2345                        : nullptr;
2346       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2347       unsigned Src2 = MI->getOperand(2).getReg();
2348       bool isKill2 = MI->getOperand(2).isKill();
2349       NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2350                         .addOperand(Dest),
2351                         Src.getReg(), Src.isKill(), Src2, isKill2);
2352 
2353       // Preserve undefness of the operands.
2354       bool isUndef = MI->getOperand(1).isUndef();
2355       bool isUndef2 = MI->getOperand(2).isUndef();
2356       NewMI->getOperand(1).setIsUndef(isUndef);
2357       NewMI->getOperand(3).setIsUndef(isUndef2);
2358 
2359       if (LV && isKill2)
2360         LV->replaceKillInstruction(Src2, MI, NewMI);
2361       break;
2362     }
2363     case X86::ADD64ri32:
2364     case X86::ADD64ri8:
2365     case X86::ADD64ri32_DB:
2366     case X86::ADD64ri8_DB:
2367       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2368       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2369                         .addOperand(Dest).addOperand(Src),
2370                         MI->getOperand(2).getImm());
2371       break;
2372     case X86::ADD32ri:
2373     case X86::ADD32ri8:
2374     case X86::ADD32ri_DB:
2375     case X86::ADD32ri8_DB: {
2376       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2377       unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2378 
2379       bool isKill, isUndef;
2380       unsigned SrcReg;
2381       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2382       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2383                           SrcReg, isKill, isUndef, ImplicitOp))
2384         return nullptr;
2385 
2386       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2387           .addOperand(Dest)
2388           .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2389       if (ImplicitOp.getReg() != 0)
2390         MIB.addOperand(ImplicitOp);
2391 
2392       NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2393       break;
2394     }
2395     case X86::ADD16ri:
2396     case X86::ADD16ri8:
2397     case X86::ADD16ri_DB:
2398     case X86::ADD16ri8_DB:
2399       if (DisableLEA16)
2400         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2401                        : nullptr;
2402       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2403       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2404                         .addOperand(Dest).addOperand(Src),
2405                         MI->getOperand(2).getImm());
2406       break;
2407     }
2408   }
2409   }
2410 
2411   if (!NewMI) return nullptr;
2412 
2413   if (LV) {  // Update live variables
2414     if (Src.isKill())
2415       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2416     if (Dest.isDead())
2417       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2418   }
2419 
2420   MFI->insert(MBBI, NewMI);          // Insert the new inst
2421   return NewMI;
2422 }
2423 
2424 /// commuteInstruction - We have a few instructions that must be hacked on to
2425 /// commute them.
2426 ///
2427 MachineInstr *
2428 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2429   switch (MI->getOpcode()) {
2430   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2431   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2432   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2433   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2434   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2435   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2436     unsigned Opc;
2437     unsigned Size;
2438     switch (MI->getOpcode()) {
2439     default: llvm_unreachable("Unreachable!");
2440     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2441     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2442     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2443     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2444     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2445     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2446     }
2447     unsigned Amt = MI->getOperand(3).getImm();
2448     if (NewMI) {
2449       MachineFunction &MF = *MI->getParent()->getParent();
2450       MI = MF.CloneMachineInstr(MI);
2451       NewMI = false;
2452     }
2453     MI->setDesc(get(Opc));
2454     MI->getOperand(3).setImm(Size-Amt);
2455     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2456   }
2457   case X86::BLENDPDrri:
2458   case X86::BLENDPSrri:
2459   case X86::PBLENDWrri:
2460   case X86::VBLENDPDrri:
2461   case X86::VBLENDPSrri:
2462   case X86::VBLENDPDYrri:
2463   case X86::VBLENDPSYrri:
2464   case X86::VPBLENDDrri:
2465   case X86::VPBLENDWrri:
2466   case X86::VPBLENDDYrri:
2467   case X86::VPBLENDWYrri:{
2468     unsigned Mask;
2469     switch (MI->getOpcode()) {
2470     default: llvm_unreachable("Unreachable!");
2471     case X86::BLENDPDrri:    Mask = 0x03; break;
2472     case X86::BLENDPSrri:    Mask = 0x0F; break;
2473     case X86::PBLENDWrri:    Mask = 0xFF; break;
2474     case X86::VBLENDPDrri:   Mask = 0x03; break;
2475     case X86::VBLENDPSrri:   Mask = 0x0F; break;
2476     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
2477     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
2478     case X86::VPBLENDDrri:   Mask = 0x0F; break;
2479     case X86::VPBLENDWrri:   Mask = 0xFF; break;
2480     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
2481     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
2482     }
2483     // Only the least significant bits of Imm are used.
2484     unsigned Imm = MI->getOperand(3).getImm() & Mask;
2485     if (NewMI) {
2486       MachineFunction &MF = *MI->getParent()->getParent();
2487       MI = MF.CloneMachineInstr(MI);
2488       NewMI = false;
2489     }
2490     MI->getOperand(3).setImm(Mask ^ Imm);
2491     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2492   }
2493   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
2494   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2495   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
2496   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2497   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2498   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
2499   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
2500   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2501   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2502   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
2503   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
2504   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2505   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
2506   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2507   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
2508   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2509     unsigned Opc;
2510     switch (MI->getOpcode()) {
2511     default: llvm_unreachable("Unreachable!");
2512     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2513     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2514     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2515     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2516     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2517     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2518     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2519     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2520     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2521     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2522     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2523     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2524     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2525     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2526     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2527     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2528     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2529     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2530     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2531     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2532     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2533     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2534     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2535     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2536     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2537     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2538     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2539     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2540     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2541     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2542     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2543     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2544     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2545     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2546     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2547     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2548     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2549     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2550     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2551     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2552     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2553     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2554     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2555     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2556     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2557     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2558     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2559     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2560     }
2561     if (NewMI) {
2562       MachineFunction &MF = *MI->getParent()->getParent();
2563       MI = MF.CloneMachineInstr(MI);
2564       NewMI = false;
2565     }
2566     MI->setDesc(get(Opc));
2567     // Fallthrough intended.
2568   }
2569   default:
2570     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2571   }
2572 }
2573 
2574 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
2575                                          unsigned &SrcOpIdx2) const {
2576   switch (MI->getOpcode()) {
2577     case X86::BLENDPDrri:
2578     case X86::BLENDPSrri:
2579     case X86::PBLENDWrri:
2580     case X86::VBLENDPDrri:
2581     case X86::VBLENDPSrri:
2582     case X86::VBLENDPDYrri:
2583     case X86::VBLENDPSYrri:
2584     case X86::VPBLENDDrri:
2585     case X86::VPBLENDDYrri:
2586     case X86::VPBLENDWrri:
2587     case X86::VPBLENDWYrri:
2588       SrcOpIdx1 = 1;
2589       SrcOpIdx2 = 2;
2590       return true;
2591     case X86::VFMADDPDr231r:
2592     case X86::VFMADDPSr231r:
2593     case X86::VFMADDSDr231r:
2594     case X86::VFMADDSSr231r:
2595     case X86::VFMSUBPDr231r:
2596     case X86::VFMSUBPSr231r:
2597     case X86::VFMSUBSDr231r:
2598     case X86::VFMSUBSSr231r:
2599     case X86::VFNMADDPDr231r:
2600     case X86::VFNMADDPSr231r:
2601     case X86::VFNMADDSDr231r:
2602     case X86::VFNMADDSSr231r:
2603     case X86::VFNMSUBPDr231r:
2604     case X86::VFNMSUBPSr231r:
2605     case X86::VFNMSUBSDr231r:
2606     case X86::VFNMSUBSSr231r:
2607     case X86::VFMADDPDr231rY:
2608     case X86::VFMADDPSr231rY:
2609     case X86::VFMSUBPDr231rY:
2610     case X86::VFMSUBPSr231rY:
2611     case X86::VFNMADDPDr231rY:
2612     case X86::VFNMADDPSr231rY:
2613     case X86::VFNMSUBPDr231rY:
2614     case X86::VFNMSUBPSr231rY:
2615       SrcOpIdx1 = 2;
2616       SrcOpIdx2 = 3;
2617       return true;
2618     default:
2619       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2620   }
2621 }
2622 
2623 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2624   switch (BrOpc) {
2625   default: return X86::COND_INVALID;
2626   case X86::JE_4:  return X86::COND_E;
2627   case X86::JNE_4: return X86::COND_NE;
2628   case X86::JL_4:  return X86::COND_L;
2629   case X86::JLE_4: return X86::COND_LE;
2630   case X86::JG_4:  return X86::COND_G;
2631   case X86::JGE_4: return X86::COND_GE;
2632   case X86::JB_4:  return X86::COND_B;
2633   case X86::JBE_4: return X86::COND_BE;
2634   case X86::JA_4:  return X86::COND_A;
2635   case X86::JAE_4: return X86::COND_AE;
2636   case X86::JS_4:  return X86::COND_S;
2637   case X86::JNS_4: return X86::COND_NS;
2638   case X86::JP_4:  return X86::COND_P;
2639   case X86::JNP_4: return X86::COND_NP;
2640   case X86::JO_4:  return X86::COND_O;
2641   case X86::JNO_4: return X86::COND_NO;
2642   }
2643 }
2644 
2645 /// getCondFromSETOpc - return condition code of a SET opcode.
2646 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2647   switch (Opc) {
2648   default: return X86::COND_INVALID;
2649   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
2650   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2651   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
2652   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2653   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
2654   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
2655   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2656   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
2657   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2658   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2659   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2660   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2661   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2662   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
2663   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
2664   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
2665   }
2666 }
2667 
2668 /// getCondFromCmovOpc - return condition code of a CMov opcode.
2669 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2670   switch (Opc) {
2671   default: return X86::COND_INVALID;
2672   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
2673   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
2674     return X86::COND_A;
2675   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2676   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2677     return X86::COND_AE;
2678   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
2679   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
2680     return X86::COND_B;
2681   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2682   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2683     return X86::COND_BE;
2684   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
2685   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
2686     return X86::COND_E;
2687   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
2688   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
2689     return X86::COND_G;
2690   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2691   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2692     return X86::COND_GE;
2693   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
2694   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
2695     return X86::COND_L;
2696   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2697   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2698     return X86::COND_LE;
2699   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2700   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2701     return X86::COND_NE;
2702   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2703   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2704     return X86::COND_NO;
2705   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2706   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2707     return X86::COND_NP;
2708   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2709   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2710     return X86::COND_NS;
2711   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
2712   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
2713     return X86::COND_O;
2714   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
2715   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
2716     return X86::COND_P;
2717   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
2718   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
2719     return X86::COND_S;
2720   }
2721 }
2722 
2723 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2724   switch (CC) {
2725   default: llvm_unreachable("Illegal condition code!");
2726   case X86::COND_E:  return X86::JE_4;
2727   case X86::COND_NE: return X86::JNE_4;
2728   case X86::COND_L:  return X86::JL_4;
2729   case X86::COND_LE: return X86::JLE_4;
2730   case X86::COND_G:  return X86::JG_4;
2731   case X86::COND_GE: return X86::JGE_4;
2732   case X86::COND_B:  return X86::JB_4;
2733   case X86::COND_BE: return X86::JBE_4;
2734   case X86::COND_A:  return X86::JA_4;
2735   case X86::COND_AE: return X86::JAE_4;
2736   case X86::COND_S:  return X86::JS_4;
2737   case X86::COND_NS: return X86::JNS_4;
2738   case X86::COND_P:  return X86::JP_4;
2739   case X86::COND_NP: return X86::JNP_4;
2740   case X86::COND_O:  return X86::JO_4;
2741   case X86::COND_NO: return X86::JNO_4;
2742   }
2743 }
2744 
2745 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2746 /// e.g. turning COND_E to COND_NE.
2747 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2748   switch (CC) {
2749   default: llvm_unreachable("Illegal condition code!");
2750   case X86::COND_E:  return X86::COND_NE;
2751   case X86::COND_NE: return X86::COND_E;
2752   case X86::COND_L:  return X86::COND_GE;
2753   case X86::COND_LE: return X86::COND_G;
2754   case X86::COND_G:  return X86::COND_LE;
2755   case X86::COND_GE: return X86::COND_L;
2756   case X86::COND_B:  return X86::COND_AE;
2757   case X86::COND_BE: return X86::COND_A;
2758   case X86::COND_A:  return X86::COND_BE;
2759   case X86::COND_AE: return X86::COND_B;
2760   case X86::COND_S:  return X86::COND_NS;
2761   case X86::COND_NS: return X86::COND_S;
2762   case X86::COND_P:  return X86::COND_NP;
2763   case X86::COND_NP: return X86::COND_P;
2764   case X86::COND_O:  return X86::COND_NO;
2765   case X86::COND_NO: return X86::COND_O;
2766   }
2767 }
2768 
2769 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2770 /// the condition code if we modify the instructions such that flags are
2771 /// set by MI(b,a).
2772 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2773   switch (CC) {
2774   default: return X86::COND_INVALID;
2775   case X86::COND_E:  return X86::COND_E;
2776   case X86::COND_NE: return X86::COND_NE;
2777   case X86::COND_L:  return X86::COND_G;
2778   case X86::COND_LE: return X86::COND_GE;
2779   case X86::COND_G:  return X86::COND_L;
2780   case X86::COND_GE: return X86::COND_LE;
2781   case X86::COND_B:  return X86::COND_A;
2782   case X86::COND_BE: return X86::COND_AE;
2783   case X86::COND_A:  return X86::COND_B;
2784   case X86::COND_AE: return X86::COND_BE;
2785   }
2786 }
2787 
2788 /// getSETFromCond - Return a set opcode for the given condition and
2789 /// whether it has memory operand.
2790 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
2791   static const uint16_t Opc[16][2] = {
2792     { X86::SETAr,  X86::SETAm  },
2793     { X86::SETAEr, X86::SETAEm },
2794     { X86::SETBr,  X86::SETBm  },
2795     { X86::SETBEr, X86::SETBEm },
2796     { X86::SETEr,  X86::SETEm  },
2797     { X86::SETGr,  X86::SETGm  },
2798     { X86::SETGEr, X86::SETGEm },
2799     { X86::SETLr,  X86::SETLm  },
2800     { X86::SETLEr, X86::SETLEm },
2801     { X86::SETNEr, X86::SETNEm },
2802     { X86::SETNOr, X86::SETNOm },
2803     { X86::SETNPr, X86::SETNPm },
2804     { X86::SETNSr, X86::SETNSm },
2805     { X86::SETOr,  X86::SETOm  },
2806     { X86::SETPr,  X86::SETPm  },
2807     { X86::SETSr,  X86::SETSm  }
2808   };
2809 
2810   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
2811   return Opc[CC][HasMemoryOperand ? 1 : 0];
2812 }
2813 
2814 /// getCMovFromCond - Return a cmov opcode for the given condition,
2815 /// register size in bytes, and operand type.
2816 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
2817                               bool HasMemoryOperand) {
2818   static const uint16_t Opc[32][3] = {
2819     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
2820     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2821     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
2822     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2823     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
2824     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
2825     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2826     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
2827     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2828     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2829     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2830     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2831     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2832     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
2833     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
2834     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
2835     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
2836     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2837     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
2838     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2839     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
2840     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
2841     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2842     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
2843     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2844     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2845     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2846     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2847     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2848     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
2849     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
2850     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
2851   };
2852 
2853   assert(CC < 16 && "Can only handle standard cond codes");
2854   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2855   switch(RegBytes) {
2856   default: llvm_unreachable("Illegal register size!");
2857   case 2: return Opc[Idx][0];
2858   case 4: return Opc[Idx][1];
2859   case 8: return Opc[Idx][2];
2860   }
2861 }
2862 
2863 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2864   if (!MI->isTerminator()) return false;
2865 
2866   // Conditional branch is a special case.
2867   if (MI->isBranch() && !MI->isBarrier())
2868     return true;
2869   if (!MI->isPredicable())
2870     return true;
2871   return !isPredicated(MI);
2872 }
2873 
2874 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2875                                  MachineBasicBlock *&TBB,
2876                                  MachineBasicBlock *&FBB,
2877                                  SmallVectorImpl<MachineOperand> &Cond,
2878                                  bool AllowModify) const {
2879   // Start from the bottom of the block and work up, examining the
2880   // terminator instructions.
2881   MachineBasicBlock::iterator I = MBB.end();
2882   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2883   while (I != MBB.begin()) {
2884     --I;
2885     if (I->isDebugValue())
2886       continue;
2887 
2888     // Working from the bottom, when we see a non-terminator instruction, we're
2889     // done.
2890     if (!isUnpredicatedTerminator(I))
2891       break;
2892 
2893     // A terminator that isn't a branch can't easily be handled by this
2894     // analysis.
2895     if (!I->isBranch())
2896       return true;
2897 
2898     // Handle unconditional branches.
2899     if (I->getOpcode() == X86::JMP_4) {
2900       UnCondBrIter = I;
2901 
2902       if (!AllowModify) {
2903         TBB = I->getOperand(0).getMBB();
2904         continue;
2905       }
2906 
2907       // If the block has any instructions after a JMP, delete them.
2908       while (std::next(I) != MBB.end())
2909         std::next(I)->eraseFromParent();
2910 
2911       Cond.clear();
2912       FBB = nullptr;
2913 
2914       // Delete the JMP if it's equivalent to a fall-through.
2915       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2916         TBB = nullptr;
2917         I->eraseFromParent();
2918         I = MBB.end();
2919         UnCondBrIter = MBB.end();
2920         continue;
2921       }
2922 
2923       // TBB is used to indicate the unconditional destination.
2924       TBB = I->getOperand(0).getMBB();
2925       continue;
2926     }
2927 
2928     // Handle conditional branches.
2929     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2930     if (BranchCode == X86::COND_INVALID)
2931       return true;  // Can't handle indirect branch.
2932 
2933     // Working from the bottom, handle the first conditional branch.
2934     if (Cond.empty()) {
2935       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2936       if (AllowModify && UnCondBrIter != MBB.end() &&
2937           MBB.isLayoutSuccessor(TargetBB)) {
2938         // If we can modify the code and it ends in something like:
2939         //
2940         //     jCC L1
2941         //     jmp L2
2942         //   L1:
2943         //     ...
2944         //   L2:
2945         //
2946         // Then we can change this to:
2947         //
2948         //     jnCC L2
2949         //   L1:
2950         //     ...
2951         //   L2:
2952         //
2953         // Which is a bit more efficient.
2954         // We conditionally jump to the fall-through block.
2955         BranchCode = GetOppositeBranchCondition(BranchCode);
2956         unsigned JNCC = GetCondBranchFromCond(BranchCode);
2957         MachineBasicBlock::iterator OldInst = I;
2958 
2959         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2960           .addMBB(UnCondBrIter->getOperand(0).getMBB());
2961         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2962           .addMBB(TargetBB);
2963 
2964         OldInst->eraseFromParent();
2965         UnCondBrIter->eraseFromParent();
2966 
2967         // Restart the analysis.
2968         UnCondBrIter = MBB.end();
2969         I = MBB.end();
2970         continue;
2971       }
2972 
2973       FBB = TBB;
2974       TBB = I->getOperand(0).getMBB();
2975       Cond.push_back(MachineOperand::CreateImm(BranchCode));
2976       continue;
2977     }
2978 
2979     // Handle subsequent conditional branches. Only handle the case where all
2980     // conditional branches branch to the same destination and their condition
2981     // opcodes fit one of the special multi-branch idioms.
2982     assert(Cond.size() == 1);
2983     assert(TBB);
2984 
2985     // Only handle the case where all conditional branches branch to the same
2986     // destination.
2987     if (TBB != I->getOperand(0).getMBB())
2988       return true;
2989 
2990     // If the conditions are the same, we can leave them alone.
2991     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2992     if (OldBranchCode == BranchCode)
2993       continue;
2994 
2995     // If they differ, see if they fit one of the known patterns. Theoretically,
2996     // we could handle more patterns here, but we shouldn't expect to see them
2997     // if instruction selection has done a reasonable job.
2998     if ((OldBranchCode == X86::COND_NP &&
2999          BranchCode == X86::COND_E) ||
3000         (OldBranchCode == X86::COND_E &&
3001          BranchCode == X86::COND_NP))
3002       BranchCode = X86::COND_NP_OR_E;
3003     else if ((OldBranchCode == X86::COND_P &&
3004               BranchCode == X86::COND_NE) ||
3005              (OldBranchCode == X86::COND_NE &&
3006               BranchCode == X86::COND_P))
3007       BranchCode = X86::COND_NE_OR_P;
3008     else
3009       return true;
3010 
3011     // Update the MachineOperand.
3012     Cond[0].setImm(BranchCode);
3013   }
3014 
3015   return false;
3016 }
3017 
3018 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
3019   MachineBasicBlock::iterator I = MBB.end();
3020   unsigned Count = 0;
3021 
3022   while (I != MBB.begin()) {
3023     --I;
3024     if (I->isDebugValue())
3025       continue;
3026     if (I->getOpcode() != X86::JMP_4 &&
3027         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
3028       break;
3029     // Remove the branch.
3030     I->eraseFromParent();
3031     I = MBB.end();
3032     ++Count;
3033   }
3034 
3035   return Count;
3036 }
3037 
3038 unsigned
3039 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3040                            MachineBasicBlock *FBB,
3041                            const SmallVectorImpl<MachineOperand> &Cond,
3042                            DebugLoc DL) const {
3043   // Shouldn't be a fall through.
3044   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
3045   assert((Cond.size() == 1 || Cond.size() == 0) &&
3046          "X86 branch conditions have one component!");
3047 
3048   if (Cond.empty()) {
3049     // Unconditional branch?
3050     assert(!FBB && "Unconditional branch with multiple successors!");
3051     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
3052     return 1;
3053   }
3054 
3055   // Conditional branch.
3056   unsigned Count = 0;
3057   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3058   switch (CC) {
3059   case X86::COND_NP_OR_E:
3060     // Synthesize NP_OR_E with two branches.
3061     BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
3062     ++Count;
3063     BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
3064     ++Count;
3065     break;
3066   case X86::COND_NE_OR_P:
3067     // Synthesize NE_OR_P with two branches.
3068     BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
3069     ++Count;
3070     BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
3071     ++Count;
3072     break;
3073   default: {
3074     unsigned Opc = GetCondBranchFromCond(CC);
3075     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
3076     ++Count;
3077   }
3078   }
3079   if (FBB) {
3080     // Two-way Conditional branch. Insert the second branch.
3081     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
3082     ++Count;
3083   }
3084   return Count;
3085 }
3086 
3087 bool X86InstrInfo::
3088 canInsertSelect(const MachineBasicBlock &MBB,
3089                 const SmallVectorImpl<MachineOperand> &Cond,
3090                 unsigned TrueReg, unsigned FalseReg,
3091                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3092   // Not all subtargets have cmov instructions.
3093   if (!Subtarget.hasCMov())
3094     return false;
3095   if (Cond.size() != 1)
3096     return false;
3097   // We cannot do the composite conditions, at least not in SSA form.
3098   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3099     return false;
3100 
3101   // Check register classes.
3102   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3103   const TargetRegisterClass *RC =
3104     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3105   if (!RC)
3106     return false;
3107 
3108   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3109   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3110       X86::GR32RegClass.hasSubClassEq(RC) ||
3111       X86::GR64RegClass.hasSubClassEq(RC)) {
3112     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3113     // Bridge. Probably Ivy Bridge as well.
3114     CondCycles = 2;
3115     TrueCycles = 2;
3116     FalseCycles = 2;
3117     return true;
3118   }
3119 
3120   // Can't do vectors.
3121   return false;
3122 }
3123 
3124 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3125                                 MachineBasicBlock::iterator I, DebugLoc DL,
3126                                 unsigned DstReg,
3127                                 const SmallVectorImpl<MachineOperand> &Cond,
3128                                 unsigned TrueReg, unsigned FalseReg) const {
3129    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3130    assert(Cond.size() == 1 && "Invalid Cond array");
3131    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
3132                                   MRI.getRegClass(DstReg)->getSize(),
3133                                   false/*HasMemoryOperand*/);
3134    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3135 }
3136 
3137 /// isHReg - Test if the given register is a physical h register.
3138 static bool isHReg(unsigned Reg) {
3139   return X86::GR8_ABCD_HRegClass.contains(Reg);
3140 }
3141 
3142 // Try and copy between VR128/VR64 and GR64 registers.
3143 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3144                                         const X86Subtarget &Subtarget) {
3145 
3146   // SrcReg(VR128) -> DestReg(GR64)
3147   // SrcReg(VR64)  -> DestReg(GR64)
3148   // SrcReg(GR64)  -> DestReg(VR128)
3149   // SrcReg(GR64)  -> DestReg(VR64)
3150 
3151   bool HasAVX = Subtarget.hasAVX();
3152   bool HasAVX512 = Subtarget.hasAVX512();
3153   if (X86::GR64RegClass.contains(DestReg)) {
3154     if (X86::VR128XRegClass.contains(SrcReg))
3155       // Copy from a VR128 register to a GR64 register.
3156       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3157                                                X86::MOVPQIto64rr);
3158     if (X86::VR64RegClass.contains(SrcReg))
3159       // Copy from a VR64 register to a GR64 register.
3160       return X86::MOVSDto64rr;
3161   } else if (X86::GR64RegClass.contains(SrcReg)) {
3162     // Copy from a GR64 register to a VR128 register.
3163     if (X86::VR128XRegClass.contains(DestReg))
3164       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3165                                                X86::MOV64toPQIrr);
3166     // Copy from a GR64 register to a VR64 register.
3167     if (X86::VR64RegClass.contains(DestReg))
3168       return X86::MOV64toSDrr;
3169   }
3170 
3171   // SrcReg(FR32) -> DestReg(GR32)
3172   // SrcReg(GR32) -> DestReg(FR32)
3173 
3174   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3175     // Copy from a FR32 register to a GR32 register.
3176     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3177 
3178   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3179     // Copy from a GR32 register to a FR32 register.
3180     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3181   return 0;
3182 }
3183 
3184 inline static bool MaskRegClassContains(unsigned Reg) {
3185   return X86::VK8RegClass.contains(Reg) ||
3186          X86::VK16RegClass.contains(Reg) ||
3187          X86::VK32RegClass.contains(Reg) ||
3188          X86::VK64RegClass.contains(Reg) ||
3189          X86::VK1RegClass.contains(Reg);
3190 }
3191 static
3192 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3193   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3194       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3195       X86::VR512RegClass.contains(DestReg, SrcReg)) {
3196      DestReg = get512BitSuperRegister(DestReg);
3197      SrcReg = get512BitSuperRegister(SrcReg);
3198      return X86::VMOVAPSZrr;
3199   }
3200   if (MaskRegClassContains(DestReg) &&
3201       MaskRegClassContains(SrcReg))
3202     return X86::KMOVWkk;
3203   if (MaskRegClassContains(DestReg) &&
3204       (X86::GR32RegClass.contains(SrcReg) ||
3205        X86::GR16RegClass.contains(SrcReg) ||
3206        X86::GR8RegClass.contains(SrcReg))) {
3207     SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3208     return X86::KMOVWkr;
3209   }
3210   if ((X86::GR32RegClass.contains(DestReg) ||
3211        X86::GR16RegClass.contains(DestReg) ||
3212        X86::GR8RegClass.contains(DestReg)) &&
3213        MaskRegClassContains(SrcReg)) {
3214     DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3215     return X86::KMOVWrk;
3216   }
3217   return 0;
3218 }
3219 
3220 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3221                                MachineBasicBlock::iterator MI, DebugLoc DL,
3222                                unsigned DestReg, unsigned SrcReg,
3223                                bool KillSrc) const {
3224   // First deal with the normal symmetric copies.
3225   bool HasAVX = Subtarget.hasAVX();
3226   bool HasAVX512 = Subtarget.hasAVX512();
3227   unsigned Opc = 0;
3228   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3229     Opc = X86::MOV64rr;
3230   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3231     Opc = X86::MOV32rr;
3232   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3233     Opc = X86::MOV16rr;
3234   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3235     // Copying to or from a physical H register on x86-64 requires a NOREX
3236     // move.  Otherwise use a normal move.
3237     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3238         Subtarget.is64Bit()) {
3239       Opc = X86::MOV8rr_NOREX;
3240       // Both operands must be encodable without an REX prefix.
3241       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3242              "8-bit H register can not be copied outside GR8_NOREX");
3243     } else
3244       Opc = X86::MOV8rr;
3245   }
3246   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3247     Opc = X86::MMX_MOVQ64rr;
3248   else if (HasAVX512)
3249     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3250   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3251     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3252   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3253     Opc = X86::VMOVAPSYrr;
3254   if (!Opc)
3255     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3256 
3257   if (Opc) {
3258     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3259       .addReg(SrcReg, getKillRegState(KillSrc));
3260     return;
3261   }
3262 
3263   // Moving EFLAGS to / from another register requires a push and a pop.
3264   // Notice that we have to adjust the stack if we don't want to clobber the
3265   // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
3266   if (SrcReg == X86::EFLAGS) {
3267     if (X86::GR64RegClass.contains(DestReg)) {
3268       BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3269       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3270       return;
3271     }
3272     if (X86::GR32RegClass.contains(DestReg)) {
3273       BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3274       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3275       return;
3276     }
3277   }
3278   if (DestReg == X86::EFLAGS) {
3279     if (X86::GR64RegClass.contains(SrcReg)) {
3280       BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3281         .addReg(SrcReg, getKillRegState(KillSrc));
3282       BuildMI(MBB, MI, DL, get(X86::POPF64));
3283       return;
3284     }
3285     if (X86::GR32RegClass.contains(SrcReg)) {
3286       BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3287         .addReg(SrcReg, getKillRegState(KillSrc));
3288       BuildMI(MBB, MI, DL, get(X86::POPF32));
3289       return;
3290     }
3291   }
3292 
3293   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3294                << " to " << RI.getName(DestReg) << '\n');
3295   llvm_unreachable("Cannot emit physreg copy instruction");
3296 }
3297 
3298 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3299                                       const TargetRegisterClass *RC,
3300                                       bool isStackAligned,
3301                                       const X86Subtarget &STI,
3302                                       bool load) {
3303   if (STI.hasAVX512()) {
3304     if (X86::VK8RegClass.hasSubClassEq(RC)  ||
3305       X86::VK16RegClass.hasSubClassEq(RC))
3306       return load ? X86::KMOVWkm : X86::KMOVWmk;
3307     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3308       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3309     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3310       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3311     if (X86::VR512RegClass.hasSubClassEq(RC))
3312       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3313   }
3314 
3315   bool HasAVX = STI.hasAVX();
3316   switch (RC->getSize()) {
3317   default:
3318     llvm_unreachable("Unknown spill size");
3319   case 1:
3320     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3321     if (STI.is64Bit())
3322       // Copying to or from a physical H register on x86-64 requires a NOREX
3323       // move.  Otherwise use a normal move.
3324       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3325         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3326     return load ? X86::MOV8rm : X86::MOV8mr;
3327   case 2:
3328     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3329     return load ? X86::MOV16rm : X86::MOV16mr;
3330   case 4:
3331     if (X86::GR32RegClass.hasSubClassEq(RC))
3332       return load ? X86::MOV32rm : X86::MOV32mr;
3333     if (X86::FR32RegClass.hasSubClassEq(RC))
3334       return load ?
3335         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3336         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3337     if (X86::RFP32RegClass.hasSubClassEq(RC))
3338       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3339     llvm_unreachable("Unknown 4-byte regclass");
3340   case 8:
3341     if (X86::GR64RegClass.hasSubClassEq(RC))
3342       return load ? X86::MOV64rm : X86::MOV64mr;
3343     if (X86::FR64RegClass.hasSubClassEq(RC))
3344       return load ?
3345         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3346         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3347     if (X86::VR64RegClass.hasSubClassEq(RC))
3348       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3349     if (X86::RFP64RegClass.hasSubClassEq(RC))
3350       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3351     llvm_unreachable("Unknown 8-byte regclass");
3352   case 10:
3353     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3354     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3355   case 16: {
3356     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3357             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
3358     // If stack is realigned we can use aligned stores.
3359     if (isStackAligned)
3360       return load ?
3361         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3362         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3363     else
3364       return load ?
3365         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3366         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3367   }
3368   case 32:
3369     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3370             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
3371     // If stack is realigned we can use aligned stores.
3372     if (isStackAligned)
3373       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3374     else
3375       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3376   case 64:
3377     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3378     if (isStackAligned)
3379       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3380     else
3381       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3382   }
3383 }
3384 
3385 static unsigned getStoreRegOpcode(unsigned SrcReg,
3386                                   const TargetRegisterClass *RC,
3387                                   bool isStackAligned,
3388                                   const X86Subtarget &STI) {
3389   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3390 }
3391 
3392 
3393 static unsigned getLoadRegOpcode(unsigned DestReg,
3394                                  const TargetRegisterClass *RC,
3395                                  bool isStackAligned,
3396                                  const X86Subtarget &STI) {
3397   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3398 }
3399 
3400 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3401                                        MachineBasicBlock::iterator MI,
3402                                        unsigned SrcReg, bool isKill, int FrameIdx,
3403                                        const TargetRegisterClass *RC,
3404                                        const TargetRegisterInfo *TRI) const {
3405   const MachineFunction &MF = *MBB.getParent();
3406   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3407          "Stack slot too small for store");
3408   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3409   bool isAligned = (MF.getTarget()
3410                         .getSubtargetImpl()
3411                         ->getFrameLowering()
3412                         ->getStackAlignment() >= Alignment) ||
3413                    RI.canRealignStack(MF);
3414   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3415   DebugLoc DL = MBB.findDebugLoc(MI);
3416   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3417     .addReg(SrcReg, getKillRegState(isKill));
3418 }
3419 
3420 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3421                                   bool isKill,
3422                                   SmallVectorImpl<MachineOperand> &Addr,
3423                                   const TargetRegisterClass *RC,
3424                                   MachineInstr::mmo_iterator MMOBegin,
3425                                   MachineInstr::mmo_iterator MMOEnd,
3426                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
3427   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3428   bool isAligned = MMOBegin != MMOEnd &&
3429                    (*MMOBegin)->getAlignment() >= Alignment;
3430   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3431   DebugLoc DL;
3432   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3433   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3434     MIB.addOperand(Addr[i]);
3435   MIB.addReg(SrcReg, getKillRegState(isKill));
3436   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3437   NewMIs.push_back(MIB);
3438 }
3439 
3440 
3441 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3442                                         MachineBasicBlock::iterator MI,
3443                                         unsigned DestReg, int FrameIdx,
3444                                         const TargetRegisterClass *RC,
3445                                         const TargetRegisterInfo *TRI) const {
3446   const MachineFunction &MF = *MBB.getParent();
3447   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3448   bool isAligned = (MF.getTarget()
3449                         .getSubtargetImpl()
3450                         ->getFrameLowering()
3451                         ->getStackAlignment() >= Alignment) ||
3452                    RI.canRealignStack(MF);
3453   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3454   DebugLoc DL = MBB.findDebugLoc(MI);
3455   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
3456 }
3457 
3458 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
3459                                  SmallVectorImpl<MachineOperand> &Addr,
3460                                  const TargetRegisterClass *RC,
3461                                  MachineInstr::mmo_iterator MMOBegin,
3462                                  MachineInstr::mmo_iterator MMOEnd,
3463                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
3464   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3465   bool isAligned = MMOBegin != MMOEnd &&
3466                    (*MMOBegin)->getAlignment() >= Alignment;
3467   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3468   DebugLoc DL;
3469   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3470   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3471     MIB.addOperand(Addr[i]);
3472   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3473   NewMIs.push_back(MIB);
3474 }
3475 
3476 bool X86InstrInfo::
3477 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3478                int &CmpMask, int &CmpValue) const {
3479   switch (MI->getOpcode()) {
3480   default: break;
3481   case X86::CMP64ri32:
3482   case X86::CMP64ri8:
3483   case X86::CMP32ri:
3484   case X86::CMP32ri8:
3485   case X86::CMP16ri:
3486   case X86::CMP16ri8:
3487   case X86::CMP8ri:
3488     SrcReg = MI->getOperand(0).getReg();
3489     SrcReg2 = 0;
3490     CmpMask = ~0;
3491     CmpValue = MI->getOperand(1).getImm();
3492     return true;
3493   // A SUB can be used to perform comparison.
3494   case X86::SUB64rm:
3495   case X86::SUB32rm:
3496   case X86::SUB16rm:
3497   case X86::SUB8rm:
3498     SrcReg = MI->getOperand(1).getReg();
3499     SrcReg2 = 0;
3500     CmpMask = ~0;
3501     CmpValue = 0;
3502     return true;
3503   case X86::SUB64rr:
3504   case X86::SUB32rr:
3505   case X86::SUB16rr:
3506   case X86::SUB8rr:
3507     SrcReg = MI->getOperand(1).getReg();
3508     SrcReg2 = MI->getOperand(2).getReg();
3509     CmpMask = ~0;
3510     CmpValue = 0;
3511     return true;
3512   case X86::SUB64ri32:
3513   case X86::SUB64ri8:
3514   case X86::SUB32ri:
3515   case X86::SUB32ri8:
3516   case X86::SUB16ri:
3517   case X86::SUB16ri8:
3518   case X86::SUB8ri:
3519     SrcReg = MI->getOperand(1).getReg();
3520     SrcReg2 = 0;
3521     CmpMask = ~0;
3522     CmpValue = MI->getOperand(2).getImm();
3523     return true;
3524   case X86::CMP64rr:
3525   case X86::CMP32rr:
3526   case X86::CMP16rr:
3527   case X86::CMP8rr:
3528     SrcReg = MI->getOperand(0).getReg();
3529     SrcReg2 = MI->getOperand(1).getReg();
3530     CmpMask = ~0;
3531     CmpValue = 0;
3532     return true;
3533   case X86::TEST8rr:
3534   case X86::TEST16rr:
3535   case X86::TEST32rr:
3536   case X86::TEST64rr:
3537     SrcReg = MI->getOperand(0).getReg();
3538     if (MI->getOperand(1).getReg() != SrcReg) return false;
3539     // Compare against zero.
3540     SrcReg2 = 0;
3541     CmpMask = ~0;
3542     CmpValue = 0;
3543     return true;
3544   }
3545   return false;
3546 }
3547 
3548 /// isRedundantFlagInstr - check whether the first instruction, whose only
3549 /// purpose is to update flags, can be made redundant.
3550 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3551 /// This function can be extended later on.
3552 /// SrcReg, SrcRegs: register operands for FlagI.
3553 /// ImmValue: immediate for FlagI if it takes an immediate.
3554 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3555                                         unsigned SrcReg2, int ImmValue,
3556                                         MachineInstr *OI) {
3557   if (((FlagI->getOpcode() == X86::CMP64rr &&
3558         OI->getOpcode() == X86::SUB64rr) ||
3559        (FlagI->getOpcode() == X86::CMP32rr &&
3560         OI->getOpcode() == X86::SUB32rr)||
3561        (FlagI->getOpcode() == X86::CMP16rr &&
3562         OI->getOpcode() == X86::SUB16rr)||
3563        (FlagI->getOpcode() == X86::CMP8rr &&
3564         OI->getOpcode() == X86::SUB8rr)) &&
3565       ((OI->getOperand(1).getReg() == SrcReg &&
3566         OI->getOperand(2).getReg() == SrcReg2) ||
3567        (OI->getOperand(1).getReg() == SrcReg2 &&
3568         OI->getOperand(2).getReg() == SrcReg)))
3569     return true;
3570 
3571   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3572         OI->getOpcode() == X86::SUB64ri32) ||
3573        (FlagI->getOpcode() == X86::CMP64ri8 &&
3574         OI->getOpcode() == X86::SUB64ri8) ||
3575        (FlagI->getOpcode() == X86::CMP32ri &&
3576         OI->getOpcode() == X86::SUB32ri) ||
3577        (FlagI->getOpcode() == X86::CMP32ri8 &&
3578         OI->getOpcode() == X86::SUB32ri8) ||
3579        (FlagI->getOpcode() == X86::CMP16ri &&
3580         OI->getOpcode() == X86::SUB16ri) ||
3581        (FlagI->getOpcode() == X86::CMP16ri8 &&
3582         OI->getOpcode() == X86::SUB16ri8) ||
3583        (FlagI->getOpcode() == X86::CMP8ri &&
3584         OI->getOpcode() == X86::SUB8ri)) &&
3585       OI->getOperand(1).getReg() == SrcReg &&
3586       OI->getOperand(2).getImm() == ImmValue)
3587     return true;
3588   return false;
3589 }
3590 
3591 /// isDefConvertible - check whether the definition can be converted
3592 /// to remove a comparison against zero.
3593 inline static bool isDefConvertible(MachineInstr *MI) {
3594   switch (MI->getOpcode()) {
3595   default: return false;
3596 
3597   // The shift instructions only modify ZF if their shift count is non-zero.
3598   // N.B.: The processor truncates the shift count depending on the encoding.
3599   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3600   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3601      return getTruncatedShiftCount(MI, 2) != 0;
3602 
3603   // Some left shift instructions can be turned into LEA instructions but only
3604   // if their flags aren't used. Avoid transforming such instructions.
3605   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3606     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3607     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3608     return ShAmt != 0;
3609   }
3610 
3611   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3612   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3613      return getTruncatedShiftCount(MI, 3) != 0;
3614 
3615   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3616   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3617   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3618   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3619   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3620   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3621   case X86::DEC64_32r: case X86::DEC64_16r:
3622   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3623   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3624   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3625   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3626   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3627   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3628   case X86::INC64_32r: case X86::INC64_16r:
3629   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3630   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3631   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3632   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3633   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3634   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3635   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3636   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3637   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3638   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3639   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3640   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3641   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3642   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3643   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3644   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
3645   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
3646   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
3647   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
3648   case X86::ADC32ri:   case X86::ADC32ri8:
3649   case X86::ADC32rr:   case X86::ADC64ri32:
3650   case X86::ADC64ri8:  case X86::ADC64rr:
3651   case X86::SBB32ri:   case X86::SBB32ri8:
3652   case X86::SBB32rr:   case X86::SBB64ri32:
3653   case X86::SBB64ri8:  case X86::SBB64rr:
3654   case X86::ANDN32rr:  case X86::ANDN32rm:
3655   case X86::ANDN64rr:  case X86::ANDN64rm:
3656   case X86::BEXTR32rr: case X86::BEXTR64rr:
3657   case X86::BEXTR32rm: case X86::BEXTR64rm:
3658   case X86::BLSI32rr:  case X86::BLSI32rm:
3659   case X86::BLSI64rr:  case X86::BLSI64rm:
3660   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3661   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3662   case X86::BLSR32rr:  case X86::BLSR32rm:
3663   case X86::BLSR64rr:  case X86::BLSR64rm:
3664   case X86::BZHI32rr:  case X86::BZHI32rm:
3665   case X86::BZHI64rr:  case X86::BZHI64rm:
3666   case X86::LZCNT16rr: case X86::LZCNT16rm:
3667   case X86::LZCNT32rr: case X86::LZCNT32rm:
3668   case X86::LZCNT64rr: case X86::LZCNT64rm:
3669   case X86::POPCNT16rr:case X86::POPCNT16rm:
3670   case X86::POPCNT32rr:case X86::POPCNT32rm:
3671   case X86::POPCNT64rr:case X86::POPCNT64rm:
3672   case X86::TZCNT16rr: case X86::TZCNT16rm:
3673   case X86::TZCNT32rr: case X86::TZCNT32rm:
3674   case X86::TZCNT64rr: case X86::TZCNT64rm:
3675     return true;
3676   }
3677 }
3678 
3679 /// isUseDefConvertible - check whether the use can be converted
3680 /// to remove a comparison against zero.
3681 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
3682   switch (MI->getOpcode()) {
3683   default: return X86::COND_INVALID;
3684   case X86::LZCNT16rr: case X86::LZCNT16rm:
3685   case X86::LZCNT32rr: case X86::LZCNT32rm:
3686   case X86::LZCNT64rr: case X86::LZCNT64rm:
3687     return X86::COND_B;
3688   case X86::POPCNT16rr:case X86::POPCNT16rm:
3689   case X86::POPCNT32rr:case X86::POPCNT32rm:
3690   case X86::POPCNT64rr:case X86::POPCNT64rm:
3691     return X86::COND_E;
3692   case X86::TZCNT16rr: case X86::TZCNT16rm:
3693   case X86::TZCNT32rr: case X86::TZCNT32rm:
3694   case X86::TZCNT64rr: case X86::TZCNT64rm:
3695     return X86::COND_B;
3696   }
3697 }
3698 
3699 /// optimizeCompareInstr - Check if there exists an earlier instruction that
3700 /// operates on the same source operands and sets flags in the same way as
3701 /// Compare; remove Compare if possible.
3702 bool X86InstrInfo::
3703 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3704                      int CmpMask, int CmpValue,
3705                      const MachineRegisterInfo *MRI) const {
3706   // Check whether we can replace SUB with CMP.
3707   unsigned NewOpcode = 0;
3708   switch (CmpInstr->getOpcode()) {
3709   default: break;
3710   case X86::SUB64ri32:
3711   case X86::SUB64ri8:
3712   case X86::SUB32ri:
3713   case X86::SUB32ri8:
3714   case X86::SUB16ri:
3715   case X86::SUB16ri8:
3716   case X86::SUB8ri:
3717   case X86::SUB64rm:
3718   case X86::SUB32rm:
3719   case X86::SUB16rm:
3720   case X86::SUB8rm:
3721   case X86::SUB64rr:
3722   case X86::SUB32rr:
3723   case X86::SUB16rr:
3724   case X86::SUB8rr: {
3725     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3726       return false;
3727     // There is no use of the destination register, we can replace SUB with CMP.
3728     switch (CmpInstr->getOpcode()) {
3729     default: llvm_unreachable("Unreachable!");
3730     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
3731     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
3732     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
3733     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
3734     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
3735     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
3736     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
3737     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
3738     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3739     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
3740     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
3741     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
3742     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
3743     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
3744     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
3745     }
3746     CmpInstr->setDesc(get(NewOpcode));
3747     CmpInstr->RemoveOperand(0);
3748     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3749     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3750         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3751       return false;
3752   }
3753   }
3754 
3755   // Get the unique definition of SrcReg.
3756   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3757   if (!MI) return false;
3758 
3759   // CmpInstr is the first instruction of the BB.
3760   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3761 
3762   // If we are comparing against zero, check whether we can use MI to update
3763   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3764   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
3765   if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
3766     return false;
3767 
3768   // If we have a use of the source register between the def and our compare
3769   // instruction we can eliminate the compare iff the use sets EFLAGS in the
3770   // right way.
3771   bool ShouldUpdateCC = false;
3772   X86::CondCode NewCC = X86::COND_INVALID;
3773   if (IsCmpZero && !isDefConvertible(MI)) {
3774     // Scan forward from the use until we hit the use we're looking for or the
3775     // compare instruction.
3776     for (MachineBasicBlock::iterator J = MI;; ++J) {
3777       // Do we have a convertible instruction?
3778       NewCC = isUseDefConvertible(J);
3779       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3780           J->getOperand(1).getReg() == SrcReg) {
3781         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3782         ShouldUpdateCC = true; // Update CC later on.
3783         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3784         // with the new def.
3785         MI = Def = J;
3786         break;
3787       }
3788 
3789       if (J == I)
3790         return false;
3791     }
3792   }
3793 
3794   // We are searching for an earlier instruction that can make CmpInstr
3795   // redundant and that instruction will be saved in Sub.
3796   MachineInstr *Sub = nullptr;
3797   const TargetRegisterInfo *TRI = &getRegisterInfo();
3798 
3799   // We iterate backward, starting from the instruction before CmpInstr and
3800   // stop when reaching the definition of a source register or done with the BB.
3801   // RI points to the instruction before CmpInstr.
3802   // If the definition is in this basic block, RE points to the definition;
3803   // otherwise, RE is the rend of the basic block.
3804   MachineBasicBlock::reverse_iterator
3805       RI = MachineBasicBlock::reverse_iterator(I),
3806       RE = CmpInstr->getParent() == MI->getParent() ?
3807            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3808            CmpInstr->getParent()->rend();
3809   MachineInstr *Movr0Inst = nullptr;
3810   for (; RI != RE; ++RI) {
3811     MachineInstr *Instr = &*RI;
3812     // Check whether CmpInstr can be made redundant by the current instruction.
3813     if (!IsCmpZero &&
3814         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
3815       Sub = Instr;
3816       break;
3817     }
3818 
3819     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3820         Instr->readsRegister(X86::EFLAGS, TRI)) {
3821       // This instruction modifies or uses EFLAGS.
3822 
3823       // MOV32r0 etc. are implemented with xor which clobbers condition code.
3824       // They are safe to move up, if the definition to EFLAGS is dead and
3825       // earlier instructions do not read or write EFLAGS.
3826       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
3827           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3828         Movr0Inst = Instr;
3829         continue;
3830       }
3831 
3832       // We can't remove CmpInstr.
3833       return false;
3834     }
3835   }
3836 
3837   // Return false if no candidates exist.
3838   if (!IsCmpZero && !Sub)
3839     return false;
3840 
3841   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3842                     Sub->getOperand(2).getReg() == SrcReg);
3843 
3844   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3845   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3846   // If we are done with the basic block, we need to check whether EFLAGS is
3847   // live-out.
3848   bool IsSafe = false;
3849   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3850   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3851   for (++I; I != E; ++I) {
3852     const MachineInstr &Instr = *I;
3853     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3854     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3855     // We should check the usage if this instruction uses and updates EFLAGS.
3856     if (!UseEFLAGS && ModifyEFLAGS) {
3857       // It is safe to remove CmpInstr if EFLAGS is updated again.
3858       IsSafe = true;
3859       break;
3860     }
3861     if (!UseEFLAGS && !ModifyEFLAGS)
3862       continue;
3863 
3864     // EFLAGS is used by this instruction.
3865     X86::CondCode OldCC = X86::COND_INVALID;
3866     bool OpcIsSET = false;
3867     if (IsCmpZero || IsSwapped) {
3868       // We decode the condition code from opcode.
3869       if (Instr.isBranch())
3870         OldCC = getCondFromBranchOpc(Instr.getOpcode());
3871       else {
3872         OldCC = getCondFromSETOpc(Instr.getOpcode());
3873         if (OldCC != X86::COND_INVALID)
3874           OpcIsSET = true;
3875         else
3876           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3877       }
3878       if (OldCC == X86::COND_INVALID) return false;
3879     }
3880     if (IsCmpZero) {
3881       switch (OldCC) {
3882       default: break;
3883       case X86::COND_A: case X86::COND_AE:
3884       case X86::COND_B: case X86::COND_BE:
3885       case X86::COND_G: case X86::COND_GE:
3886       case X86::COND_L: case X86::COND_LE:
3887       case X86::COND_O: case X86::COND_NO:
3888         // CF and OF are used, we can't perform this optimization.
3889         return false;
3890       }
3891 
3892       // If we're updating the condition code check if we have to reverse the
3893       // condition.
3894       if (ShouldUpdateCC)
3895         switch (OldCC) {
3896         default:
3897           return false;
3898         case X86::COND_E:
3899           break;
3900         case X86::COND_NE:
3901           NewCC = GetOppositeBranchCondition(NewCC);
3902           break;
3903         }
3904     } else if (IsSwapped) {
3905       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3906       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3907       // We swap the condition code and synthesize the new opcode.
3908       NewCC = getSwappedCondition(OldCC);
3909       if (NewCC == X86::COND_INVALID) return false;
3910     }
3911 
3912     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
3913       // Synthesize the new opcode.
3914       bool HasMemoryOperand = Instr.hasOneMemOperand();
3915       unsigned NewOpc;
3916       if (Instr.isBranch())
3917         NewOpc = GetCondBranchFromCond(NewCC);
3918       else if(OpcIsSET)
3919         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3920       else {
3921         unsigned DstReg = Instr.getOperand(0).getReg();
3922         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3923                                  HasMemoryOperand);
3924       }
3925 
3926       // Push the MachineInstr to OpsToUpdate.
3927       // If it is safe to remove CmpInstr, the condition code of these
3928       // instructions will be modified.
3929       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3930     }
3931     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3932       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3933       IsSafe = true;
3934       break;
3935     }
3936   }
3937 
3938   // If EFLAGS is not killed nor re-defined, we should check whether it is
3939   // live-out. If it is live-out, do not optimize.
3940   if ((IsCmpZero || IsSwapped) && !IsSafe) {
3941     MachineBasicBlock *MBB = CmpInstr->getParent();
3942     for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
3943              SE = MBB->succ_end(); SI != SE; ++SI)
3944       if ((*SI)->isLiveIn(X86::EFLAGS))
3945         return false;
3946   }
3947 
3948   // The instruction to be updated is either Sub or MI.
3949   Sub = IsCmpZero ? MI : Sub;
3950   // Move Movr0Inst to the appropriate place before Sub.
3951   if (Movr0Inst) {
3952     // Look backwards until we find a def that doesn't use the current EFLAGS.
3953     Def = Sub;
3954     MachineBasicBlock::reverse_iterator
3955       InsertI = MachineBasicBlock::reverse_iterator(++Def),
3956                 InsertE = Sub->getParent()->rend();
3957     for (; InsertI != InsertE; ++InsertI) {
3958       MachineInstr *Instr = &*InsertI;
3959       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3960           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3961         Sub->getParent()->remove(Movr0Inst);
3962         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3963                                    Movr0Inst);
3964         break;
3965       }
3966     }
3967     if (InsertI == InsertE)
3968       return false;
3969   }
3970 
3971   // Make sure Sub instruction defines EFLAGS and mark the def live.
3972   unsigned i = 0, e = Sub->getNumOperands();
3973   for (; i != e; ++i) {
3974     MachineOperand &MO = Sub->getOperand(i);
3975     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3976       MO.setIsDead(false);
3977       break;
3978     }
3979   }
3980   assert(i != e && "Unable to locate a def EFLAGS operand");
3981 
3982   CmpInstr->eraseFromParent();
3983 
3984   // Modify the condition code of instructions in OpsToUpdate.
3985   for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
3986     OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
3987   return true;
3988 }
3989 
3990 /// optimizeLoadInstr - Try to remove the load by folding it to a register
3991 /// operand at the use. We fold the load instructions if load defines a virtual
3992 /// register, the virtual register is used once in the same BB, and the
3993 /// instructions in-between do not load or store, and have no side effects.
3994 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
3995                                               const MachineRegisterInfo *MRI,
3996                                               unsigned &FoldAsLoadDefReg,
3997                                               MachineInstr *&DefMI) const {
3998   if (FoldAsLoadDefReg == 0)
3999     return nullptr;
4000   // To be conservative, if there exists another load, clear the load candidate.
4001   if (MI->mayLoad()) {
4002     FoldAsLoadDefReg = 0;
4003     return nullptr;
4004   }
4005 
4006   // Check whether we can move DefMI here.
4007   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4008   assert(DefMI);
4009   bool SawStore = false;
4010   if (!DefMI->isSafeToMove(this, nullptr, SawStore))
4011     return nullptr;
4012 
4013   // Collect information about virtual register operands of MI.
4014   unsigned SrcOperandId = 0;
4015   bool FoundSrcOperand = false;
4016   for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
4017     MachineOperand &MO = MI->getOperand(i);
4018     if (!MO.isReg())
4019       continue;
4020     unsigned Reg = MO.getReg();
4021     if (Reg != FoldAsLoadDefReg)
4022       continue;
4023     // Do not fold if we have a subreg use or a def or multiple uses.
4024     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
4025       return nullptr;
4026 
4027     SrcOperandId = i;
4028     FoundSrcOperand = true;
4029   }
4030   if (!FoundSrcOperand)
4031     return nullptr;
4032 
4033   // Check whether we can fold the def into SrcOperandId.
4034   SmallVector<unsigned, 8> Ops;
4035   Ops.push_back(SrcOperandId);
4036   MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
4037   if (FoldMI) {
4038     FoldAsLoadDefReg = 0;
4039     return FoldMI;
4040   }
4041 
4042   return nullptr;
4043 }
4044 
4045 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
4046 /// instruction with two undef reads of the register being defined.  This is
4047 /// used for mapping:
4048 ///   %xmm4 = V_SET0
4049 /// to:
4050 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
4051 ///
4052 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4053                              const MCInstrDesc &Desc) {
4054   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4055   unsigned Reg = MIB->getOperand(0).getReg();
4056   MIB->setDesc(Desc);
4057 
4058   // MachineInstr::addOperand() will insert explicit operands before any
4059   // implicit operands.
4060   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4061   // But we don't trust that.
4062   assert(MIB->getOperand(1).getReg() == Reg &&
4063          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
4064   return true;
4065 }
4066 
4067 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4068 // code sequence is needed for other targets.
4069 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4070                                  const TargetInstrInfo &TII) {
4071   MachineBasicBlock &MBB = *MIB->getParent();
4072   DebugLoc DL = MIB->getDebugLoc();
4073   unsigned Reg = MIB->getOperand(0).getReg();
4074   const GlobalValue *GV =
4075       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4076   unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4077   MachineMemOperand *MMO = MBB.getParent()->
4078       getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8);
4079   MachineBasicBlock::iterator I = MIB.getInstr();
4080 
4081   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4082       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4083       .addMemOperand(MMO);
4084   MIB->setDebugLoc(DL);
4085   MIB->setDesc(TII.get(X86::MOV64rm));
4086   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4087 }
4088 
4089 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
4090   bool HasAVX = Subtarget.hasAVX();
4091   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4092   switch (MI->getOpcode()) {
4093   case X86::MOV32r0:
4094     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4095   case X86::SETB_C8r:
4096     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4097   case X86::SETB_C16r:
4098     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4099   case X86::SETB_C32r:
4100     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4101   case X86::SETB_C64r:
4102     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4103   case X86::V_SET0:
4104   case X86::FsFLD0SS:
4105   case X86::FsFLD0SD:
4106     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4107   case X86::AVX_SET0:
4108     assert(HasAVX && "AVX not supported");
4109     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
4110   case X86::AVX512_512_SET0:
4111     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4112   case X86::V_SETALLONES:
4113     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4114   case X86::AVX2_SETALLONES:
4115     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4116   case X86::TEST8ri_NOREX:
4117     MI->setDesc(get(X86::TEST8ri));
4118     return true;
4119   case X86::KSET0B:
4120   case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4121   case X86::KSET1B:
4122   case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
4123   case TargetOpcode::LOAD_STACK_GUARD:
4124     expandLoadStackGuard(MIB, *this);
4125     return true;
4126   }
4127   return false;
4128 }
4129 
4130 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4131                                      const SmallVectorImpl<MachineOperand> &MOs,
4132                                      MachineInstr *MI,
4133                                      const TargetInstrInfo &TII) {
4134   // Create the base instruction with the memory operand as the first part.
4135   // Omit the implicit operands, something BuildMI can't do.
4136   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4137                                               MI->getDebugLoc(), true);
4138   MachineInstrBuilder MIB(MF, NewMI);
4139   unsigned NumAddrOps = MOs.size();
4140   for (unsigned i = 0; i != NumAddrOps; ++i)
4141     MIB.addOperand(MOs[i]);
4142   if (NumAddrOps < 4)  // FrameIndex only
4143     addOffset(MIB, 0);
4144 
4145   // Loop over the rest of the ri operands, converting them over.
4146   unsigned NumOps = MI->getDesc().getNumOperands()-2;
4147   for (unsigned i = 0; i != NumOps; ++i) {
4148     MachineOperand &MO = MI->getOperand(i+2);
4149     MIB.addOperand(MO);
4150   }
4151   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4152     MachineOperand &MO = MI->getOperand(i);
4153     MIB.addOperand(MO);
4154   }
4155   return MIB;
4156 }
4157 
4158 static MachineInstr *FuseInst(MachineFunction &MF,
4159                               unsigned Opcode, unsigned OpNo,
4160                               const SmallVectorImpl<MachineOperand> &MOs,
4161                               MachineInstr *MI, const TargetInstrInfo &TII) {
4162   // Omit the implicit operands, something BuildMI can't do.
4163   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4164                                               MI->getDebugLoc(), true);
4165   MachineInstrBuilder MIB(MF, NewMI);
4166 
4167   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4168     MachineOperand &MO = MI->getOperand(i);
4169     if (i == OpNo) {
4170       assert(MO.isReg() && "Expected to fold into reg operand!");
4171       unsigned NumAddrOps = MOs.size();
4172       for (unsigned i = 0; i != NumAddrOps; ++i)
4173         MIB.addOperand(MOs[i]);
4174       if (NumAddrOps < 4)  // FrameIndex only
4175         addOffset(MIB, 0);
4176     } else {
4177       MIB.addOperand(MO);
4178     }
4179   }
4180   return MIB;
4181 }
4182 
4183 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4184                                 const SmallVectorImpl<MachineOperand> &MOs,
4185                                 MachineInstr *MI) {
4186   MachineFunction &MF = *MI->getParent()->getParent();
4187   MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
4188 
4189   unsigned NumAddrOps = MOs.size();
4190   for (unsigned i = 0; i != NumAddrOps; ++i)
4191     MIB.addOperand(MOs[i]);
4192   if (NumAddrOps < 4)  // FrameIndex only
4193     addOffset(MIB, 0);
4194   return MIB.addImm(0);
4195 }
4196 
4197 MachineInstr*
4198 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4199                                     MachineInstr *MI, unsigned i,
4200                                     const SmallVectorImpl<MachineOperand> &MOs,
4201                                     unsigned Size, unsigned Align,
4202                                     bool AllowCommute) const {
4203   const DenseMap<unsigned,
4204                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4205   bool isCallRegIndirect = Subtarget.callRegIndirect();
4206   bool isTwoAddrFold = false;
4207 
4208   // Atom favors register form of call. So, we do not fold loads into calls
4209   // when X86Subtarget is Atom.
4210   if (isCallRegIndirect &&
4211     (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
4212     return nullptr;
4213   }
4214 
4215   unsigned NumOps = MI->getDesc().getNumOperands();
4216   bool isTwoAddr = NumOps > 1 &&
4217     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4218 
4219   // FIXME: AsmPrinter doesn't know how to handle
4220   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4221   if (MI->getOpcode() == X86::ADD32ri &&
4222       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4223     return nullptr;
4224 
4225   MachineInstr *NewMI = nullptr;
4226   // Folding a memory location into the two-address part of a two-address
4227   // instruction is different than folding it other places.  It requires
4228   // replacing the *two* registers with the memory location.
4229   if (isTwoAddr && NumOps >= 2 && i < 2 &&
4230       MI->getOperand(0).isReg() &&
4231       MI->getOperand(1).isReg() &&
4232       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
4233     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4234     isTwoAddrFold = true;
4235   } else if (i == 0) { // If operand 0
4236     if (MI->getOpcode() == X86::MOV32r0) {
4237       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4238       if (NewMI)
4239         return NewMI;
4240     }
4241 
4242     OpcodeTablePtr = &RegOp2MemOpTable0;
4243   } else if (i == 1) {
4244     OpcodeTablePtr = &RegOp2MemOpTable1;
4245   } else if (i == 2) {
4246     OpcodeTablePtr = &RegOp2MemOpTable2;
4247   } else if (i == 3) {
4248     OpcodeTablePtr = &RegOp2MemOpTable3;
4249   }
4250 
4251   // If table selected...
4252   if (OpcodeTablePtr) {
4253     // Find the Opcode to fuse
4254     DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4255       OpcodeTablePtr->find(MI->getOpcode());
4256     if (I != OpcodeTablePtr->end()) {
4257       unsigned Opcode = I->second.first;
4258       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4259       if (Align < MinAlign)
4260         return nullptr;
4261       bool NarrowToMOV32rm = false;
4262       if (Size) {
4263         unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
4264         if (Size < RCSize) {
4265           // Check if it's safe to fold the load. If the size of the object is
4266           // narrower than the load width, then it's not.
4267           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4268             return nullptr;
4269           // If this is a 64-bit load, but the spill slot is 32, then we can do
4270           // a 32-bit load which is implicitly zero-extended. This likely is
4271           // due to live interval analysis remat'ing a load from stack slot.
4272           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4273             return nullptr;
4274           Opcode = X86::MOV32rm;
4275           NarrowToMOV32rm = true;
4276         }
4277       }
4278 
4279       if (isTwoAddrFold)
4280         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
4281       else
4282         NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
4283 
4284       if (NarrowToMOV32rm) {
4285         // If this is the special case where we use a MOV32rm to load a 32-bit
4286         // value and zero-extend the top bits. Change the destination register
4287         // to a 32-bit one.
4288         unsigned DstReg = NewMI->getOperand(0).getReg();
4289         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4290           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4291         else
4292           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4293       }
4294       return NewMI;
4295     }
4296   }
4297 
4298   // If the instruction and target operand are commutable, commute the
4299   // instruction and try again.
4300   if (AllowCommute) {
4301     unsigned OriginalOpIdx = i, CommuteOpIdx1, CommuteOpIdx2;
4302     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4303       bool HasDef = MI->getDesc().getNumDefs();
4304       unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
4305       unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
4306       unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
4307       bool Tied0 =
4308           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4309       bool Tied1 =
4310           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4311 
4312       // If either of the commutable operands are tied to the destination
4313       // then we can not commute + fold.
4314       if ((HasDef && Reg0 == Reg1 && Tied0) ||
4315           (HasDef && Reg0 == Reg2 && Tied1))
4316         return nullptr;
4317 
4318       if ((CommuteOpIdx1 == OriginalOpIdx) ||
4319           (CommuteOpIdx2 == OriginalOpIdx)) {
4320         MachineInstr *CommutedMI = commuteInstruction(MI, false);
4321         if (!CommutedMI) {
4322           // Unable to commute.
4323           return nullptr;
4324         }
4325         if (CommutedMI != MI) {
4326           // New instruction. We can't fold from this.
4327           CommutedMI->eraseFromParent();
4328           return nullptr;
4329         }
4330 
4331         // Attempt to fold with the commuted version of the instruction.
4332         unsigned CommuteOp =
4333             (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1);
4334         NewMI = foldMemoryOperandImpl(MF, MI, CommuteOp, MOs, Size, Align,
4335                                       /*AllowCommute=*/false);
4336         if (NewMI)
4337           return NewMI;
4338 
4339         // Folding failed again - undo the commute before returning.
4340         MachineInstr *UncommutedMI = commuteInstruction(MI, false);
4341         if (!UncommutedMI) {
4342           // Unable to commute.
4343           return nullptr;
4344         }
4345         if (UncommutedMI != MI) {
4346           // New instruction. It doesn't need to be kept.
4347           UncommutedMI->eraseFromParent();
4348           return nullptr;
4349         }
4350 
4351         // Return here to prevent duplicate fuse failure report.
4352         return nullptr;
4353       }
4354     }
4355   }
4356 
4357   // No fusion
4358   if (PrintFailedFusing && !MI->isCopy())
4359     dbgs() << "We failed to fuse operand " << i << " in " << *MI;
4360   return nullptr;
4361 }
4362 
4363 /// hasPartialRegUpdate - Return true for all instructions that only update
4364 /// the first 32 or 64-bits of the destination register and leave the rest
4365 /// unmodified. This can be used to avoid folding loads if the instructions
4366 /// only update part of the destination register, and the non-updated part is
4367 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4368 /// instructions breaks the partial register dependency and it can improve
4369 /// performance. e.g.:
4370 ///
4371 ///   movss (%rdi), %xmm0
4372 ///   cvtss2sd %xmm0, %xmm0
4373 ///
4374 /// Instead of
4375 ///   cvtss2sd (%rdi), %xmm0
4376 ///
4377 /// FIXME: This should be turned into a TSFlags.
4378 ///
4379 static bool hasPartialRegUpdate(unsigned Opcode) {
4380   switch (Opcode) {
4381   case X86::CVTSI2SSrr:
4382   case X86::CVTSI2SS64rr:
4383   case X86::CVTSI2SDrr:
4384   case X86::CVTSI2SD64rr:
4385   case X86::CVTSD2SSrr:
4386   case X86::Int_CVTSD2SSrr:
4387   case X86::CVTSS2SDrr:
4388   case X86::Int_CVTSS2SDrr:
4389   case X86::RCPSSr:
4390   case X86::RCPSSr_Int:
4391   case X86::ROUNDSDr:
4392   case X86::ROUNDSDr_Int:
4393   case X86::ROUNDSSr:
4394   case X86::ROUNDSSr_Int:
4395   case X86::RSQRTSSr:
4396   case X86::RSQRTSSr_Int:
4397   case X86::SQRTSSr:
4398   case X86::SQRTSSr_Int:
4399     return true;
4400   }
4401 
4402   return false;
4403 }
4404 
4405 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4406 /// instructions we would like before a partial register update.
4407 unsigned X86InstrInfo::
4408 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4409                              const TargetRegisterInfo *TRI) const {
4410   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4411     return 0;
4412 
4413   // If MI is marked as reading Reg, the partial register update is wanted.
4414   const MachineOperand &MO = MI->getOperand(0);
4415   unsigned Reg = MO.getReg();
4416   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4417     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4418       return 0;
4419   } else {
4420     if (MI->readsRegister(Reg, TRI))
4421       return 0;
4422   }
4423 
4424   // If any of the preceding 16 instructions are reading Reg, insert a
4425   // dependency breaking instruction.  The magic number is based on a few
4426   // Nehalem experiments.
4427   return 16;
4428 }
4429 
4430 // Return true for any instruction the copies the high bits of the first source
4431 // operand into the unused high bits of the destination operand.
4432 static bool hasUndefRegUpdate(unsigned Opcode) {
4433   switch (Opcode) {
4434   case X86::VCVTSI2SSrr:
4435   case X86::Int_VCVTSI2SSrr:
4436   case X86::VCVTSI2SS64rr:
4437   case X86::Int_VCVTSI2SS64rr:
4438   case X86::VCVTSI2SDrr:
4439   case X86::Int_VCVTSI2SDrr:
4440   case X86::VCVTSI2SD64rr:
4441   case X86::Int_VCVTSI2SD64rr:
4442   case X86::VCVTSD2SSrr:
4443   case X86::Int_VCVTSD2SSrr:
4444   case X86::VCVTSS2SDrr:
4445   case X86::Int_VCVTSS2SDrr:
4446   case X86::VRCPSSr:
4447   case X86::VROUNDSDr:
4448   case X86::VROUNDSDr_Int:
4449   case X86::VROUNDSSr:
4450   case X86::VROUNDSSr_Int:
4451   case X86::VRSQRTSSr:
4452   case X86::VSQRTSSr:
4453 
4454   // AVX-512
4455   case X86::VCVTSD2SSZrr:
4456   case X86::VCVTSS2SDZrr:
4457     return true;
4458   }
4459 
4460   return false;
4461 }
4462 
4463 /// Inform the ExeDepsFix pass how many idle instructions we would like before
4464 /// certain undef register reads.
4465 ///
4466 /// This catches the VCVTSI2SD family of instructions:
4467 ///
4468 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4469 ///
4470 /// We should to be careful *not* to catch VXOR idioms which are presumably
4471 /// handled specially in the pipeline:
4472 ///
4473 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4474 ///
4475 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4476 /// high bits that are passed-through are not live.
4477 unsigned X86InstrInfo::
4478 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4479                      const TargetRegisterInfo *TRI) const {
4480   if (!hasUndefRegUpdate(MI->getOpcode()))
4481     return 0;
4482 
4483   // Set the OpNum parameter to the first source operand.
4484   OpNum = 1;
4485 
4486   const MachineOperand &MO = MI->getOperand(OpNum);
4487   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4488     // Use the same magic number as getPartialRegUpdateClearance.
4489     return 16;
4490   }
4491   return 0;
4492 }
4493 
4494 void X86InstrInfo::
4495 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4496                           const TargetRegisterInfo *TRI) const {
4497   unsigned Reg = MI->getOperand(OpNum).getReg();
4498   // If MI kills this register, the false dependence is already broken.
4499   if (MI->killsRegister(Reg, TRI))
4500     return;
4501   if (X86::VR128RegClass.contains(Reg)) {
4502     // These instructions are all floating point domain, so xorps is the best
4503     // choice.
4504     bool HasAVX = Subtarget.hasAVX();
4505     unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4506     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4507       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4508   } else if (X86::VR256RegClass.contains(Reg)) {
4509     // Use vxorps to clear the full ymm register.
4510     // It wants to read and write the xmm sub-register.
4511     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4512     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4513       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4514       .addReg(Reg, RegState::ImplicitDefine);
4515   } else
4516     return;
4517   MI->addRegisterKilled(Reg, TRI, true);
4518 }
4519 
4520 MachineInstr*
4521 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4522                                     const SmallVectorImpl<unsigned> &Ops,
4523                                     int FrameIndex) const {
4524   // Check switch flag
4525   if (NoFusing) return nullptr;
4526 
4527   // Unless optimizing for size, don't fold to avoid partial
4528   // register update stalls
4529   if (!MF.getFunction()->getAttributes().
4530         hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4531       hasPartialRegUpdate(MI->getOpcode()))
4532     return nullptr;
4533 
4534   const MachineFrameInfo *MFI = MF.getFrameInfo();
4535   unsigned Size = MFI->getObjectSize(FrameIndex);
4536   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
4537   // If the function stack isn't realigned we don't want to fold instructions
4538   // that need increased alignment.
4539   if (!RI.needsStackRealignment(MF))
4540     Alignment = std::min(Alignment, MF.getTarget()
4541                                         .getSubtargetImpl()
4542                                         ->getFrameLowering()
4543                                         ->getStackAlignment());
4544   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4545     unsigned NewOpc = 0;
4546     unsigned RCSize = 0;
4547     switch (MI->getOpcode()) {
4548     default: return nullptr;
4549     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
4550     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4551     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4552     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4553     }
4554     // Check if it's safe to fold the load. If the size of the object is
4555     // narrower than the load width, then it's not.
4556     if (Size < RCSize)
4557       return nullptr;
4558     // Change to CMPXXri r, 0 first.
4559     MI->setDesc(get(NewOpc));
4560     MI->getOperand(1).ChangeToImmediate(0);
4561   } else if (Ops.size() != 1)
4562     return nullptr;
4563 
4564   SmallVector<MachineOperand,4> MOs;
4565   MOs.push_back(MachineOperand::CreateFI(FrameIndex));
4566   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
4567                                Size, Alignment, /*AllowCommute=*/true);
4568 }
4569 
4570 static bool isPartialRegisterLoad(const MachineInstr &LoadMI,
4571                                   const MachineFunction &MF) {
4572   unsigned Opc = LoadMI.getOpcode();
4573   unsigned RegSize =
4574       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
4575 
4576   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
4577     // These instructions only load 32 bits, we can't fold them if the
4578     // destination register is wider than 32 bits (4 bytes).
4579     return true;
4580 
4581   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
4582     // These instructions only load 64 bits, we can't fold them if the
4583     // destination register is wider than 64 bits (8 bytes).
4584     return true;
4585 
4586   return false;
4587 }
4588 
4589 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4590                                                   MachineInstr *MI,
4591                                            const SmallVectorImpl<unsigned> &Ops,
4592                                                   MachineInstr *LoadMI) const {
4593   // If loading from a FrameIndex, fold directly from the FrameIndex.
4594   unsigned NumOps = LoadMI->getDesc().getNumOperands();
4595   int FrameIndex;
4596   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
4597     if (isPartialRegisterLoad(*LoadMI, MF))
4598       return nullptr;
4599     return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
4600   }
4601 
4602   // Check switch flag
4603   if (NoFusing) return nullptr;
4604 
4605   // Unless optimizing for size, don't fold to avoid partial
4606   // register update stalls
4607   if (!MF.getFunction()->getAttributes().
4608         hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4609       hasPartialRegUpdate(MI->getOpcode()))
4610     return nullptr;
4611 
4612   // Determine the alignment of the load.
4613   unsigned Alignment = 0;
4614   if (LoadMI->hasOneMemOperand())
4615     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
4616   else
4617     switch (LoadMI->getOpcode()) {
4618     case X86::AVX2_SETALLONES:
4619     case X86::AVX_SET0:
4620       Alignment = 32;
4621       break;
4622     case X86::V_SET0:
4623     case X86::V_SETALLONES:
4624       Alignment = 16;
4625       break;
4626     case X86::FsFLD0SD:
4627       Alignment = 8;
4628       break;
4629     case X86::FsFLD0SS:
4630       Alignment = 4;
4631       break;
4632     default:
4633       return nullptr;
4634     }
4635   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4636     unsigned NewOpc = 0;
4637     switch (MI->getOpcode()) {
4638     default: return nullptr;
4639     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
4640     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4641     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4642     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
4643     }
4644     // Change to CMPXXri r, 0 first.
4645     MI->setDesc(get(NewOpc));
4646     MI->getOperand(1).ChangeToImmediate(0);
4647   } else if (Ops.size() != 1)
4648     return nullptr;
4649 
4650   // Make sure the subregisters match.
4651   // Otherwise we risk changing the size of the load.
4652   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
4653     return nullptr;
4654 
4655   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
4656   switch (LoadMI->getOpcode()) {
4657   case X86::V_SET0:
4658   case X86::V_SETALLONES:
4659   case X86::AVX2_SETALLONES:
4660   case X86::AVX_SET0:
4661   case X86::FsFLD0SD:
4662   case X86::FsFLD0SS: {
4663     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
4664     // Create a constant-pool entry and operands to load from it.
4665 
4666     // Medium and large mode can't fold loads this way.
4667     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
4668         MF.getTarget().getCodeModel() != CodeModel::Kernel)
4669       return nullptr;
4670 
4671     // x86-32 PIC requires a PIC base register for constant pools.
4672     unsigned PICBase = 0;
4673     if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
4674       if (Subtarget.is64Bit())
4675         PICBase = X86::RIP;
4676       else
4677         // FIXME: PICBase = getGlobalBaseReg(&MF);
4678         // This doesn't work for several reasons.
4679         // 1. GlobalBaseReg may have been spilled.
4680         // 2. It may not be live at MI.
4681         return nullptr;
4682     }
4683 
4684     // Create a constant-pool entry.
4685     MachineConstantPool &MCP = *MF.getConstantPool();
4686     Type *Ty;
4687     unsigned Opc = LoadMI->getOpcode();
4688     if (Opc == X86::FsFLD0SS)
4689       Ty = Type::getFloatTy(MF.getFunction()->getContext());
4690     else if (Opc == X86::FsFLD0SD)
4691       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
4692     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
4693       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
4694     else
4695       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
4696 
4697     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
4698     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4699                                     Constant::getNullValue(Ty);
4700     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
4701 
4702     // Create operands to load from the constant pool entry.
4703     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4704     MOs.push_back(MachineOperand::CreateImm(1));
4705     MOs.push_back(MachineOperand::CreateReg(0, false));
4706     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
4707     MOs.push_back(MachineOperand::CreateReg(0, false));
4708     break;
4709   }
4710   default: {
4711     if (isPartialRegisterLoad(*LoadMI, MF))
4712       return nullptr;
4713 
4714     // Folding a normal load. Just copy the load's address operands.
4715     for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
4716       MOs.push_back(LoadMI->getOperand(i));
4717     break;
4718   }
4719   }
4720   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
4721                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
4722 }
4723 
4724 
4725 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4726                                   const SmallVectorImpl<unsigned> &Ops) const {
4727   // Check switch flag
4728   if (NoFusing) return 0;
4729 
4730   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4731     switch (MI->getOpcode()) {
4732     default: return false;
4733     case X86::TEST8rr:
4734     case X86::TEST16rr:
4735     case X86::TEST32rr:
4736     case X86::TEST64rr:
4737       return true;
4738     case X86::ADD32ri:
4739       // FIXME: AsmPrinter doesn't know how to handle
4740       // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4741       if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4742         return false;
4743       break;
4744     }
4745   }
4746 
4747   if (Ops.size() != 1)
4748     return false;
4749 
4750   unsigned OpNum = Ops[0];
4751   unsigned Opc = MI->getOpcode();
4752   unsigned NumOps = MI->getDesc().getNumOperands();
4753   bool isTwoAddr = NumOps > 1 &&
4754     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4755 
4756   // Folding a memory location into the two-address part of a two-address
4757   // instruction is different than folding it other places.  It requires
4758   // replacing the *two* registers with the memory location.
4759   const DenseMap<unsigned,
4760                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4761   if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
4762     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4763   } else if (OpNum == 0) { // If operand 0
4764     if (Opc == X86::MOV32r0)
4765       return true;
4766 
4767     OpcodeTablePtr = &RegOp2MemOpTable0;
4768   } else if (OpNum == 1) {
4769     OpcodeTablePtr = &RegOp2MemOpTable1;
4770   } else if (OpNum == 2) {
4771     OpcodeTablePtr = &RegOp2MemOpTable2;
4772   } else if (OpNum == 3) {
4773     OpcodeTablePtr = &RegOp2MemOpTable3;
4774   }
4775 
4776   if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4777     return true;
4778   return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
4779 }
4780 
4781 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4782                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
4783                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4784   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4785     MemOp2RegOpTable.find(MI->getOpcode());
4786   if (I == MemOp2RegOpTable.end())
4787     return false;
4788   unsigned Opc = I->second.first;
4789   unsigned Index = I->second.second & TB_INDEX_MASK;
4790   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4791   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4792   if (UnfoldLoad && !FoldedLoad)
4793     return false;
4794   UnfoldLoad &= FoldedLoad;
4795   if (UnfoldStore && !FoldedStore)
4796     return false;
4797   UnfoldStore &= FoldedStore;
4798 
4799   const MCInstrDesc &MCID = get(Opc);
4800   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4801   if (!MI->hasOneMemOperand() &&
4802       RC == &X86::VR128RegClass &&
4803       !Subtarget.isUnalignedMemAccessFast())
4804     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4805     // conservatively assume the address is unaligned. That's bad for
4806     // performance.
4807     return false;
4808   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
4809   SmallVector<MachineOperand,2> BeforeOps;
4810   SmallVector<MachineOperand,2> AfterOps;
4811   SmallVector<MachineOperand,4> ImpOps;
4812   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4813     MachineOperand &Op = MI->getOperand(i);
4814     if (i >= Index && i < Index + X86::AddrNumOperands)
4815       AddrOps.push_back(Op);
4816     else if (Op.isReg() && Op.isImplicit())
4817       ImpOps.push_back(Op);
4818     else if (i < Index)
4819       BeforeOps.push_back(Op);
4820     else if (i > Index)
4821       AfterOps.push_back(Op);
4822   }
4823 
4824   // Emit the load instruction.
4825   if (UnfoldLoad) {
4826     std::pair<MachineInstr::mmo_iterator,
4827               MachineInstr::mmo_iterator> MMOs =
4828       MF.extractLoadMemRefs(MI->memoperands_begin(),
4829                             MI->memoperands_end());
4830     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
4831     if (UnfoldStore) {
4832       // Address operands cannot be marked isKill.
4833       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
4834         MachineOperand &MO = NewMIs[0]->getOperand(i);
4835         if (MO.isReg())
4836           MO.setIsKill(false);
4837       }
4838     }
4839   }
4840 
4841   // Emit the data processing instruction.
4842   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
4843   MachineInstrBuilder MIB(MF, DataMI);
4844 
4845   if (FoldedStore)
4846     MIB.addReg(Reg, RegState::Define);
4847   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
4848     MIB.addOperand(BeforeOps[i]);
4849   if (FoldedLoad)
4850     MIB.addReg(Reg);
4851   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
4852     MIB.addOperand(AfterOps[i]);
4853   for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
4854     MachineOperand &MO = ImpOps[i];
4855     MIB.addReg(MO.getReg(),
4856                getDefRegState(MO.isDef()) |
4857                RegState::Implicit |
4858                getKillRegState(MO.isKill()) |
4859                getDeadRegState(MO.isDead()) |
4860                getUndefRegState(MO.isUndef()));
4861   }
4862   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
4863   switch (DataMI->getOpcode()) {
4864   default: break;
4865   case X86::CMP64ri32:
4866   case X86::CMP64ri8:
4867   case X86::CMP32ri:
4868   case X86::CMP32ri8:
4869   case X86::CMP16ri:
4870   case X86::CMP16ri8:
4871   case X86::CMP8ri: {
4872     MachineOperand &MO0 = DataMI->getOperand(0);
4873     MachineOperand &MO1 = DataMI->getOperand(1);
4874     if (MO1.getImm() == 0) {
4875       unsigned NewOpc;
4876       switch (DataMI->getOpcode()) {
4877       default: llvm_unreachable("Unreachable!");
4878       case X86::CMP64ri8:
4879       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
4880       case X86::CMP32ri8:
4881       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
4882       case X86::CMP16ri8:
4883       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
4884       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
4885       }
4886       DataMI->setDesc(get(NewOpc));
4887       MO1.ChangeToRegister(MO0.getReg(), false);
4888     }
4889   }
4890   }
4891   NewMIs.push_back(DataMI);
4892 
4893   // Emit the store instruction.
4894   if (UnfoldStore) {
4895     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
4896     std::pair<MachineInstr::mmo_iterator,
4897               MachineInstr::mmo_iterator> MMOs =
4898       MF.extractStoreMemRefs(MI->memoperands_begin(),
4899                              MI->memoperands_end());
4900     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
4901   }
4902 
4903   return true;
4904 }
4905 
4906 bool
4907 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
4908                                   SmallVectorImpl<SDNode*> &NewNodes) const {
4909   if (!N->isMachineOpcode())
4910     return false;
4911 
4912   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4913     MemOp2RegOpTable.find(N->getMachineOpcode());
4914   if (I == MemOp2RegOpTable.end())
4915     return false;
4916   unsigned Opc = I->second.first;
4917   unsigned Index = I->second.second & TB_INDEX_MASK;
4918   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4919   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4920   const MCInstrDesc &MCID = get(Opc);
4921   MachineFunction &MF = DAG.getMachineFunction();
4922   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4923   unsigned NumDefs = MCID.NumDefs;
4924   std::vector<SDValue> AddrOps;
4925   std::vector<SDValue> BeforeOps;
4926   std::vector<SDValue> AfterOps;
4927   SDLoc dl(N);
4928   unsigned NumOps = N->getNumOperands();
4929   for (unsigned i = 0; i != NumOps-1; ++i) {
4930     SDValue Op = N->getOperand(i);
4931     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
4932       AddrOps.push_back(Op);
4933     else if (i < Index-NumDefs)
4934       BeforeOps.push_back(Op);
4935     else if (i > Index-NumDefs)
4936       AfterOps.push_back(Op);
4937   }
4938   SDValue Chain = N->getOperand(NumOps-1);
4939   AddrOps.push_back(Chain);
4940 
4941   // Emit the load instruction.
4942   SDNode *Load = nullptr;
4943   if (FoldedLoad) {
4944     EVT VT = *RC->vt_begin();
4945     std::pair<MachineInstr::mmo_iterator,
4946               MachineInstr::mmo_iterator> MMOs =
4947       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4948                             cast<MachineSDNode>(N)->memoperands_end());
4949     if (!(*MMOs.first) &&
4950         RC == &X86::VR128RegClass &&
4951         !Subtarget.isUnalignedMemAccessFast())
4952       // Do not introduce a slow unaligned load.
4953       return false;
4954     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4955     bool isAligned = (*MMOs.first) &&
4956                      (*MMOs.first)->getAlignment() >= Alignment;
4957     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
4958                               VT, MVT::Other, AddrOps);
4959     NewNodes.push_back(Load);
4960 
4961     // Preserve memory reference information.
4962     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4963   }
4964 
4965   // Emit the data processing instruction.
4966   std::vector<EVT> VTs;
4967   const TargetRegisterClass *DstRC = nullptr;
4968   if (MCID.getNumDefs() > 0) {
4969     DstRC = getRegClass(MCID, 0, &RI, MF);
4970     VTs.push_back(*DstRC->vt_begin());
4971   }
4972   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
4973     EVT VT = N->getValueType(i);
4974     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
4975       VTs.push_back(VT);
4976   }
4977   if (Load)
4978     BeforeOps.push_back(SDValue(Load, 0));
4979   std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
4980   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
4981   NewNodes.push_back(NewNode);
4982 
4983   // Emit the store instruction.
4984   if (FoldedStore) {
4985     AddrOps.pop_back();
4986     AddrOps.push_back(SDValue(NewNode, 0));
4987     AddrOps.push_back(Chain);
4988     std::pair<MachineInstr::mmo_iterator,
4989               MachineInstr::mmo_iterator> MMOs =
4990       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4991                              cast<MachineSDNode>(N)->memoperands_end());
4992     if (!(*MMOs.first) &&
4993         RC == &X86::VR128RegClass &&
4994         !Subtarget.isUnalignedMemAccessFast())
4995       // Do not introduce a slow unaligned store.
4996       return false;
4997     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4998     bool isAligned = (*MMOs.first) &&
4999                      (*MMOs.first)->getAlignment() >= Alignment;
5000     SDNode *Store =
5001         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5002                            dl, MVT::Other, AddrOps);
5003     NewNodes.push_back(Store);
5004 
5005     // Preserve memory reference information.
5006     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
5007   }
5008 
5009   return true;
5010 }
5011 
5012 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5013                                       bool UnfoldLoad, bool UnfoldStore,
5014                                       unsigned *LoadRegIndex) const {
5015   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5016     MemOp2RegOpTable.find(Opc);
5017   if (I == MemOp2RegOpTable.end())
5018     return 0;
5019   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5020   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5021   if (UnfoldLoad && !FoldedLoad)
5022     return 0;
5023   if (UnfoldStore && !FoldedStore)
5024     return 0;
5025   if (LoadRegIndex)
5026     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
5027   return I->second.first;
5028 }
5029 
5030 bool
5031 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5032                                      int64_t &Offset1, int64_t &Offset2) const {
5033   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5034     return false;
5035   unsigned Opc1 = Load1->getMachineOpcode();
5036   unsigned Opc2 = Load2->getMachineOpcode();
5037   switch (Opc1) {
5038   default: return false;
5039   case X86::MOV8rm:
5040   case X86::MOV16rm:
5041   case X86::MOV32rm:
5042   case X86::MOV64rm:
5043   case X86::LD_Fp32m:
5044   case X86::LD_Fp64m:
5045   case X86::LD_Fp80m:
5046   case X86::MOVSSrm:
5047   case X86::MOVSDrm:
5048   case X86::MMX_MOVD64rm:
5049   case X86::MMX_MOVQ64rm:
5050   case X86::FsMOVAPSrm:
5051   case X86::FsMOVAPDrm:
5052   case X86::MOVAPSrm:
5053   case X86::MOVUPSrm:
5054   case X86::MOVAPDrm:
5055   case X86::MOVDQArm:
5056   case X86::MOVDQUrm:
5057   // AVX load instructions
5058   case X86::VMOVSSrm:
5059   case X86::VMOVSDrm:
5060   case X86::FsVMOVAPSrm:
5061   case X86::FsVMOVAPDrm:
5062   case X86::VMOVAPSrm:
5063   case X86::VMOVUPSrm:
5064   case X86::VMOVAPDrm:
5065   case X86::VMOVDQArm:
5066   case X86::VMOVDQUrm:
5067   case X86::VMOVAPSYrm:
5068   case X86::VMOVUPSYrm:
5069   case X86::VMOVAPDYrm:
5070   case X86::VMOVDQAYrm:
5071   case X86::VMOVDQUYrm:
5072     break;
5073   }
5074   switch (Opc2) {
5075   default: return false;
5076   case X86::MOV8rm:
5077   case X86::MOV16rm:
5078   case X86::MOV32rm:
5079   case X86::MOV64rm:
5080   case X86::LD_Fp32m:
5081   case X86::LD_Fp64m:
5082   case X86::LD_Fp80m:
5083   case X86::MOVSSrm:
5084   case X86::MOVSDrm:
5085   case X86::MMX_MOVD64rm:
5086   case X86::MMX_MOVQ64rm:
5087   case X86::FsMOVAPSrm:
5088   case X86::FsMOVAPDrm:
5089   case X86::MOVAPSrm:
5090   case X86::MOVUPSrm:
5091   case X86::MOVAPDrm:
5092   case X86::MOVDQArm:
5093   case X86::MOVDQUrm:
5094   // AVX load instructions
5095   case X86::VMOVSSrm:
5096   case X86::VMOVSDrm:
5097   case X86::FsVMOVAPSrm:
5098   case X86::FsVMOVAPDrm:
5099   case X86::VMOVAPSrm:
5100   case X86::VMOVUPSrm:
5101   case X86::VMOVAPDrm:
5102   case X86::VMOVDQArm:
5103   case X86::VMOVDQUrm:
5104   case X86::VMOVAPSYrm:
5105   case X86::VMOVUPSYrm:
5106   case X86::VMOVAPDYrm:
5107   case X86::VMOVDQAYrm:
5108   case X86::VMOVDQUYrm:
5109     break;
5110   }
5111 
5112   // Check if chain operands and base addresses match.
5113   if (Load1->getOperand(0) != Load2->getOperand(0) ||
5114       Load1->getOperand(5) != Load2->getOperand(5))
5115     return false;
5116   // Segment operands should match as well.
5117   if (Load1->getOperand(4) != Load2->getOperand(4))
5118     return false;
5119   // Scale should be 1, Index should be Reg0.
5120   if (Load1->getOperand(1) == Load2->getOperand(1) &&
5121       Load1->getOperand(2) == Load2->getOperand(2)) {
5122     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5123       return false;
5124 
5125     // Now let's examine the displacements.
5126     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5127         isa<ConstantSDNode>(Load2->getOperand(3))) {
5128       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5129       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5130       return true;
5131     }
5132   }
5133   return false;
5134 }
5135 
5136 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5137                                            int64_t Offset1, int64_t Offset2,
5138                                            unsigned NumLoads) const {
5139   assert(Offset2 > Offset1);
5140   if ((Offset2 - Offset1) / 8 > 64)
5141     return false;
5142 
5143   unsigned Opc1 = Load1->getMachineOpcode();
5144   unsigned Opc2 = Load2->getMachineOpcode();
5145   if (Opc1 != Opc2)
5146     return false;  // FIXME: overly conservative?
5147 
5148   switch (Opc1) {
5149   default: break;
5150   case X86::LD_Fp32m:
5151   case X86::LD_Fp64m:
5152   case X86::LD_Fp80m:
5153   case X86::MMX_MOVD64rm:
5154   case X86::MMX_MOVQ64rm:
5155     return false;
5156   }
5157 
5158   EVT VT = Load1->getValueType(0);
5159   switch (VT.getSimpleVT().SimpleTy) {
5160   default:
5161     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5162     // have 16 of them to play with.
5163     if (Subtarget.is64Bit()) {
5164       if (NumLoads >= 3)
5165         return false;
5166     } else if (NumLoads) {
5167       return false;
5168     }
5169     break;
5170   case MVT::i8:
5171   case MVT::i16:
5172   case MVT::i32:
5173   case MVT::i64:
5174   case MVT::f32:
5175   case MVT::f64:
5176     if (NumLoads)
5177       return false;
5178     break;
5179   }
5180 
5181   return true;
5182 }
5183 
5184 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5185                                           MachineInstr *Second) const {
5186   // Check if this processor supports macro-fusion. Since this is a minor
5187   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5188   // proxy for SandyBridge+.
5189   if (!Subtarget.hasAVX())
5190     return false;
5191 
5192   enum {
5193     FuseTest,
5194     FuseCmp,
5195     FuseInc
5196   } FuseKind;
5197 
5198   switch(Second->getOpcode()) {
5199   default:
5200     return false;
5201   case X86::JE_4:
5202   case X86::JNE_4:
5203   case X86::JL_4:
5204   case X86::JLE_4:
5205   case X86::JG_4:
5206   case X86::JGE_4:
5207     FuseKind = FuseInc;
5208     break;
5209   case X86::JB_4:
5210   case X86::JBE_4:
5211   case X86::JA_4:
5212   case X86::JAE_4:
5213     FuseKind = FuseCmp;
5214     break;
5215   case X86::JS_4:
5216   case X86::JNS_4:
5217   case X86::JP_4:
5218   case X86::JNP_4:
5219   case X86::JO_4:
5220   case X86::JNO_4:
5221     FuseKind = FuseTest;
5222     break;
5223   }
5224   switch (First->getOpcode()) {
5225   default:
5226     return false;
5227   case X86::TEST8rr:
5228   case X86::TEST16rr:
5229   case X86::TEST32rr:
5230   case X86::TEST64rr:
5231   case X86::TEST8ri:
5232   case X86::TEST16ri:
5233   case X86::TEST32ri:
5234   case X86::TEST32i32:
5235   case X86::TEST64i32:
5236   case X86::TEST64ri32:
5237   case X86::TEST8rm:
5238   case X86::TEST16rm:
5239   case X86::TEST32rm:
5240   case X86::TEST64rm:
5241   case X86::TEST8ri_NOREX:
5242   case X86::AND16i16:
5243   case X86::AND16ri:
5244   case X86::AND16ri8:
5245   case X86::AND16rm:
5246   case X86::AND16rr:
5247   case X86::AND32i32:
5248   case X86::AND32ri:
5249   case X86::AND32ri8:
5250   case X86::AND32rm:
5251   case X86::AND32rr:
5252   case X86::AND64i32:
5253   case X86::AND64ri32:
5254   case X86::AND64ri8:
5255   case X86::AND64rm:
5256   case X86::AND64rr:
5257   case X86::AND8i8:
5258   case X86::AND8ri:
5259   case X86::AND8rm:
5260   case X86::AND8rr:
5261     return true;
5262   case X86::CMP16i16:
5263   case X86::CMP16ri:
5264   case X86::CMP16ri8:
5265   case X86::CMP16rm:
5266   case X86::CMP16rr:
5267   case X86::CMP32i32:
5268   case X86::CMP32ri:
5269   case X86::CMP32ri8:
5270   case X86::CMP32rm:
5271   case X86::CMP32rr:
5272   case X86::CMP64i32:
5273   case X86::CMP64ri32:
5274   case X86::CMP64ri8:
5275   case X86::CMP64rm:
5276   case X86::CMP64rr:
5277   case X86::CMP8i8:
5278   case X86::CMP8ri:
5279   case X86::CMP8rm:
5280   case X86::CMP8rr:
5281   case X86::ADD16i16:
5282   case X86::ADD16ri:
5283   case X86::ADD16ri8:
5284   case X86::ADD16ri8_DB:
5285   case X86::ADD16ri_DB:
5286   case X86::ADD16rm:
5287   case X86::ADD16rr:
5288   case X86::ADD16rr_DB:
5289   case X86::ADD32i32:
5290   case X86::ADD32ri:
5291   case X86::ADD32ri8:
5292   case X86::ADD32ri8_DB:
5293   case X86::ADD32ri_DB:
5294   case X86::ADD32rm:
5295   case X86::ADD32rr:
5296   case X86::ADD32rr_DB:
5297   case X86::ADD64i32:
5298   case X86::ADD64ri32:
5299   case X86::ADD64ri32_DB:
5300   case X86::ADD64ri8:
5301   case X86::ADD64ri8_DB:
5302   case X86::ADD64rm:
5303   case X86::ADD64rr:
5304   case X86::ADD64rr_DB:
5305   case X86::ADD8i8:
5306   case X86::ADD8mi:
5307   case X86::ADD8mr:
5308   case X86::ADD8ri:
5309   case X86::ADD8rm:
5310   case X86::ADD8rr:
5311   case X86::SUB16i16:
5312   case X86::SUB16ri:
5313   case X86::SUB16ri8:
5314   case X86::SUB16rm:
5315   case X86::SUB16rr:
5316   case X86::SUB32i32:
5317   case X86::SUB32ri:
5318   case X86::SUB32ri8:
5319   case X86::SUB32rm:
5320   case X86::SUB32rr:
5321   case X86::SUB64i32:
5322   case X86::SUB64ri32:
5323   case X86::SUB64ri8:
5324   case X86::SUB64rm:
5325   case X86::SUB64rr:
5326   case X86::SUB8i8:
5327   case X86::SUB8ri:
5328   case X86::SUB8rm:
5329   case X86::SUB8rr:
5330     return FuseKind == FuseCmp || FuseKind == FuseInc;
5331   case X86::INC16r:
5332   case X86::INC32r:
5333   case X86::INC64_16r:
5334   case X86::INC64_32r:
5335   case X86::INC64r:
5336   case X86::INC8r:
5337   case X86::DEC16r:
5338   case X86::DEC32r:
5339   case X86::DEC64_16r:
5340   case X86::DEC64_32r:
5341   case X86::DEC64r:
5342   case X86::DEC8r:
5343     return FuseKind == FuseInc;
5344   }
5345 }
5346 
5347 bool X86InstrInfo::
5348 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5349   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5350   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5351   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5352     return true;
5353   Cond[0].setImm(GetOppositeBranchCondition(CC));
5354   return false;
5355 }
5356 
5357 bool X86InstrInfo::
5358 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5359   // FIXME: Return false for x87 stack register classes for now. We can't
5360   // allow any loads of these registers before FpGet_ST0_80.
5361   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5362            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
5363 }
5364 
5365 /// getGlobalBaseReg - Return a virtual register initialized with the
5366 /// the global base register value. Output instructions required to
5367 /// initialize the register in the function entry block, if necessary.
5368 ///
5369 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5370 ///
5371 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5372   assert(!Subtarget.is64Bit() &&
5373          "X86-64 PIC uses RIP relative addressing");
5374 
5375   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5376   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5377   if (GlobalBaseReg != 0)
5378     return GlobalBaseReg;
5379 
5380   // Create the register. The code to initialize it is inserted
5381   // later, by the CGBR pass (below).
5382   MachineRegisterInfo &RegInfo = MF->getRegInfo();
5383   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
5384   X86FI->setGlobalBaseReg(GlobalBaseReg);
5385   return GlobalBaseReg;
5386 }
5387 
5388 // These are the replaceable SSE instructions. Some of these have Int variants
5389 // that we don't include here. We don't want to replace instructions selected
5390 // by intrinsics.
5391 static const uint16_t ReplaceableInstrs[][3] = {
5392   //PackedSingle     PackedDouble    PackedInt
5393   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
5394   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
5395   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
5396   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
5397   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
5398   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
5399   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
5400   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
5401   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
5402   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
5403   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
5404   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
5405   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
5406   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
5407   // AVX 128-bit support
5408   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
5409   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
5410   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
5411   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
5412   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
5413   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5414   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
5415   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
5416   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
5417   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
5418   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
5419   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
5420   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
5421   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
5422   // AVX 256-bit support
5423   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
5424   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
5425   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
5426   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
5427   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
5428   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
5429 };
5430 
5431 static const uint16_t ReplaceableInstrsAVX2[][3] = {
5432   //PackedSingle       PackedDouble       PackedInt
5433   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
5434   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
5435   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
5436   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
5437   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
5438   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
5439   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
5440   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
5441   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5442   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5443   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
5444   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
5445   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
5446   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
5447   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5448   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5449   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5450   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5451   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5452   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
5453 };
5454 
5455 // FIXME: Some shuffle and unpack instructions have equivalents in different
5456 // domains, but they require a bit more work than just switching opcodes.
5457 
5458 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
5459   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
5460     if (ReplaceableInstrs[i][domain-1] == opcode)
5461       return ReplaceableInstrs[i];
5462   return nullptr;
5463 }
5464 
5465 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
5466   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5467     if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5468       return ReplaceableInstrsAVX2[i];
5469   return nullptr;
5470 }
5471 
5472 std::pair<uint16_t, uint16_t>
5473 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
5474   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5475   bool hasAVX2 = Subtarget.hasAVX2();
5476   uint16_t validDomains = 0;
5477   if (domain && lookup(MI->getOpcode(), domain))
5478     validDomains = 0xe;
5479   else if (domain && lookupAVX2(MI->getOpcode(), domain))
5480     validDomains = hasAVX2 ? 0xe : 0x6;
5481   return std::make_pair(domain, validDomains);
5482 }
5483 
5484 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
5485   assert(Domain>0 && Domain<4 && "Invalid execution domain");
5486   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5487   assert(dom && "Not an SSE instruction");
5488   const uint16_t *table = lookup(MI->getOpcode(), dom);
5489   if (!table) { // try the other table
5490     assert((Subtarget.hasAVX2() || Domain < 3) &&
5491            "256-bit vector operations only available in AVX2");
5492     table = lookupAVX2(MI->getOpcode(), dom);
5493   }
5494   assert(table && "Cannot change domain");
5495   MI->setDesc(get(table[Domain-1]));
5496 }
5497 
5498 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5499 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5500   NopInst.setOpcode(X86::NOOP);
5501 }
5502 
5503 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
5504 // In particular, getJumpInstrTableEntryBound must always return an upper bound
5505 // on the encoding lengths of the instructions generated by
5506 // getUnconditionalBranch and getTrap.
5507 void X86InstrInfo::getUnconditionalBranch(
5508     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
5509   Branch.setOpcode(X86::JMP_4);
5510   Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
5511 }
5512 
5513 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
5514 // In particular, getJumpInstrTableEntryBound must always return an upper bound
5515 // on the encoding lengths of the instructions generated by
5516 // getUnconditionalBranch and getTrap.
5517 void X86InstrInfo::getTrap(MCInst &MI) const {
5518   MI.setOpcode(X86::TRAP);
5519 }
5520 
5521 // See getTrap and getUnconditionalBranch for conditions on the value returned
5522 // by this function.
5523 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
5524   // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
5525   // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
5526   return 5;
5527 }
5528 
5529 bool X86InstrInfo::isHighLatencyDef(int opc) const {
5530   switch (opc) {
5531   default: return false;
5532   case X86::DIVSDrm:
5533   case X86::DIVSDrm_Int:
5534   case X86::DIVSDrr:
5535   case X86::DIVSDrr_Int:
5536   case X86::DIVSSrm:
5537   case X86::DIVSSrm_Int:
5538   case X86::DIVSSrr:
5539   case X86::DIVSSrr_Int:
5540   case X86::SQRTPDm:
5541   case X86::SQRTPDr:
5542   case X86::SQRTPSm:
5543   case X86::SQRTPSr:
5544   case X86::SQRTSDm:
5545   case X86::SQRTSDm_Int:
5546   case X86::SQRTSDr:
5547   case X86::SQRTSDr_Int:
5548   case X86::SQRTSSm:
5549   case X86::SQRTSSm_Int:
5550   case X86::SQRTSSr:
5551   case X86::SQRTSSr_Int:
5552   // AVX instructions with high latency
5553   case X86::VDIVSDrm:
5554   case X86::VDIVSDrm_Int:
5555   case X86::VDIVSDrr:
5556   case X86::VDIVSDrr_Int:
5557   case X86::VDIVSSrm:
5558   case X86::VDIVSSrm_Int:
5559   case X86::VDIVSSrr:
5560   case X86::VDIVSSrr_Int:
5561   case X86::VSQRTPDm:
5562   case X86::VSQRTPDr:
5563   case X86::VSQRTPSm:
5564   case X86::VSQRTPSr:
5565   case X86::VSQRTSDm:
5566   case X86::VSQRTSDm_Int:
5567   case X86::VSQRTSDr:
5568   case X86::VSQRTSSm:
5569   case X86::VSQRTSSm_Int:
5570   case X86::VSQRTSSr:
5571   case X86::VSQRTPDZm:
5572   case X86::VSQRTPDZr:
5573   case X86::VSQRTPSZm:
5574   case X86::VSQRTPSZr:
5575   case X86::VSQRTSDZm:
5576   case X86::VSQRTSDZm_Int:
5577   case X86::VSQRTSDZr:
5578   case X86::VSQRTSSZm_Int:
5579   case X86::VSQRTSSZr:
5580   case X86::VSQRTSSZm:
5581   case X86::VDIVSDZrm:
5582   case X86::VDIVSDZrr:
5583   case X86::VDIVSSZrm:
5584   case X86::VDIVSSZrr:
5585 
5586   case X86::VGATHERQPSZrm:
5587   case X86::VGATHERQPDZrm:
5588   case X86::VGATHERDPDZrm:
5589   case X86::VGATHERDPSZrm:
5590   case X86::VPGATHERQDZrm:
5591   case X86::VPGATHERQQZrm:
5592   case X86::VPGATHERDDZrm:
5593   case X86::VPGATHERDQZrm:
5594   case X86::VSCATTERQPDZmr:
5595   case X86::VSCATTERQPSZmr:
5596   case X86::VSCATTERDPDZmr:
5597   case X86::VSCATTERDPSZmr:
5598   case X86::VPSCATTERQDZmr:
5599   case X86::VPSCATTERQQZmr:
5600   case X86::VPSCATTERDDZmr:
5601   case X86::VPSCATTERDQZmr:
5602     return true;
5603   }
5604 }
5605 
5606 bool X86InstrInfo::
5607 hasHighOperandLatency(const InstrItineraryData *ItinData,
5608                       const MachineRegisterInfo *MRI,
5609                       const MachineInstr *DefMI, unsigned DefIdx,
5610                       const MachineInstr *UseMI, unsigned UseIdx) const {
5611   return isHighLatencyDef(DefMI->getOpcode());
5612 }
5613 
5614 namespace {
5615   /// CGBR - Create Global Base Reg pass. This initializes the PIC
5616   /// global base register for x86-32.
5617   struct CGBR : public MachineFunctionPass {
5618     static char ID;
5619     CGBR() : MachineFunctionPass(ID) {}
5620 
5621     bool runOnMachineFunction(MachineFunction &MF) override {
5622       const X86TargetMachine *TM =
5623         static_cast<const X86TargetMachine *>(&MF.getTarget());
5624 
5625       // Don't do anything if this is 64-bit as 64-bit PIC
5626       // uses RIP relative addressing.
5627       if (TM->getSubtarget<X86Subtarget>().is64Bit())
5628         return false;
5629 
5630       // Only emit a global base reg in PIC mode.
5631       if (TM->getRelocationModel() != Reloc::PIC_)
5632         return false;
5633 
5634       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
5635       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5636 
5637       // If we didn't need a GlobalBaseReg, don't insert code.
5638       if (GlobalBaseReg == 0)
5639         return false;
5640 
5641       // Insert the set of GlobalBaseReg into the first MBB of the function
5642       MachineBasicBlock &FirstMBB = MF.front();
5643       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
5644       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
5645       MachineRegisterInfo &RegInfo = MF.getRegInfo();
5646       const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5647 
5648       unsigned PC;
5649       if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
5650         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
5651       else
5652         PC = GlobalBaseReg;
5653 
5654       // Operand of MovePCtoStack is completely ignored by asm printer. It's
5655       // only used in JIT code emission as displacement to pc.
5656       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
5657 
5658       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
5659       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
5660       if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
5661         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
5662         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5663           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
5664                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
5665       }
5666 
5667       return true;
5668     }
5669 
5670     const char *getPassName() const override {
5671       return "X86 PIC Global Base Reg Initialization";
5672     }
5673 
5674     void getAnalysisUsage(AnalysisUsage &AU) const override {
5675       AU.setPreservesCFG();
5676       MachineFunctionPass::getAnalysisUsage(AU);
5677     }
5678   };
5679 }
5680 
5681 char CGBR::ID = 0;
5682 FunctionPass*
5683 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
5684 
5685 namespace {
5686   struct LDTLSCleanup : public MachineFunctionPass {
5687     static char ID;
5688     LDTLSCleanup() : MachineFunctionPass(ID) {}
5689 
5690     bool runOnMachineFunction(MachineFunction &MF) override {
5691       X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
5692       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
5693         // No point folding accesses if there isn't at least two.
5694         return false;
5695       }
5696 
5697       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
5698       return VisitNode(DT->getRootNode(), 0);
5699     }
5700 
5701     // Visit the dominator subtree rooted at Node in pre-order.
5702     // If TLSBaseAddrReg is non-null, then use that to replace any
5703     // TLS_base_addr instructions. Otherwise, create the register
5704     // when the first such instruction is seen, and then use it
5705     // as we encounter more instructions.
5706     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
5707       MachineBasicBlock *BB = Node->getBlock();
5708       bool Changed = false;
5709 
5710       // Traverse the current block.
5711       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
5712            ++I) {
5713         switch (I->getOpcode()) {
5714           case X86::TLS_base_addr32:
5715           case X86::TLS_base_addr64:
5716             if (TLSBaseAddrReg)
5717               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
5718             else
5719               I = SetRegister(I, &TLSBaseAddrReg);
5720             Changed = true;
5721             break;
5722           default:
5723             break;
5724         }
5725       }
5726 
5727       // Visit the children of this block in the dominator tree.
5728       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
5729            I != E; ++I) {
5730         Changed |= VisitNode(*I, TLSBaseAddrReg);
5731       }
5732 
5733       return Changed;
5734     }
5735 
5736     // Replace the TLS_base_addr instruction I with a copy from
5737     // TLSBaseAddrReg, returning the new instruction.
5738     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
5739                                          unsigned TLSBaseAddrReg) {
5740       MachineFunction *MF = I->getParent()->getParent();
5741       const X86TargetMachine *TM =
5742           static_cast<const X86TargetMachine *>(&MF->getTarget());
5743       const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5744       const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5745 
5746       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5747       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
5748                                    TII->get(TargetOpcode::COPY),
5749                                    is64Bit ? X86::RAX : X86::EAX)
5750                                    .addReg(TLSBaseAddrReg);
5751 
5752       // Erase the TLS_base_addr instruction.
5753       I->eraseFromParent();
5754 
5755       return Copy;
5756     }
5757 
5758     // Create a virtal register in *TLSBaseAddrReg, and populate it by
5759     // inserting a copy instruction after I. Returns the new instruction.
5760     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
5761       MachineFunction *MF = I->getParent()->getParent();
5762       const X86TargetMachine *TM =
5763           static_cast<const X86TargetMachine *>(&MF->getTarget());
5764       const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5765       const X86InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
5766 
5767       // Create a virtual register for the TLS base address.
5768       MachineRegisterInfo &RegInfo = MF->getRegInfo();
5769       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
5770                                                       ? &X86::GR64RegClass
5771                                                       : &X86::GR32RegClass);
5772 
5773       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
5774       MachineInstr *Next = I->getNextNode();
5775       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
5776                                    TII->get(TargetOpcode::COPY),
5777                                    *TLSBaseAddrReg)
5778                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
5779 
5780       return Copy;
5781     }
5782 
5783     const char *getPassName() const override {
5784       return "Local Dynamic TLS Access Clean-up";
5785     }
5786 
5787     void getAnalysisUsage(AnalysisUsage &AU) const override {
5788       AU.setPreservesCFG();
5789       AU.addRequired<MachineDominatorTree>();
5790       MachineFunctionPass::getAnalysisUsage(AU);
5791     }
5792   };
5793 }
5794 
5795 char LDTLSCleanup::ID = 0;
5796 FunctionPass*
5797 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
5798