1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "x86-instr-info"
45 
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
48 
49 static cl::opt<bool>
50 NoFusing("disable-spill-fusing",
51          cl::desc("Disable fusing of spill code into instructions"));
52 static cl::opt<bool>
53 PrintFailedFusing("print-failed-fuse-candidates",
54                   cl::desc("Print instructions that the allocator wants to"
55                            " fuse, but the X86 backend currently can't"),
56                   cl::Hidden);
57 static cl::opt<bool>
58 ReMatPICStubLoad("remat-pic-stub-load",
59                  cl::desc("Re-materialize load from stub in PIC mode"),
60                  cl::init(false), cl::Hidden);
61 static cl::opt<unsigned>
62 PartialRegUpdateClearance("partial-reg-update-clearance",
63                           cl::desc("Clearance between two register writes "
64                                    "for inserting XOR to avoid partial "
65                                    "register update"),
66                           cl::init(64), cl::Hidden);
67 static cl::opt<unsigned>
68 UndefRegClearance("undef-reg-clearance",
69                   cl::desc("How many idle instructions we would like before "
70                            "certain undef register reads"),
71                   cl::init(128), cl::Hidden);
72 
73 enum {
74   // Select which memory operand is being unfolded.
75   // (stored in bits 0 - 3)
76   TB_INDEX_0    = 0,
77   TB_INDEX_1    = 1,
78   TB_INDEX_2    = 2,
79   TB_INDEX_3    = 3,
80   TB_INDEX_4    = 4,
81   TB_INDEX_MASK = 0xf,
82 
83   // Do not insert the reverse map (MemOp -> RegOp) into the table.
84   // This may be needed because there is a many -> one mapping.
85   TB_NO_REVERSE   = 1 << 4,
86 
87   // Do not insert the forward map (RegOp -> MemOp) into the table.
88   // This is needed for Native Client, which prohibits branch
89   // instructions from using a memory operand.
90   TB_NO_FORWARD   = 1 << 5,
91 
92   TB_FOLDED_LOAD  = 1 << 6,
93   TB_FOLDED_STORE = 1 << 7,
94 
95   // Minimum alignment required for load/store.
96   // Used for RegOp->MemOp conversion.
97   // (stored in bits 8 - 15)
98   TB_ALIGN_SHIFT = 8,
99   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
100   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
101   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
102   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
103   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
104 };
105 
106 struct X86MemoryFoldTableEntry {
107   uint16_t RegOp;
108   uint16_t MemOp;
109   uint16_t Flags;
110 };
111 
112 // Pin the vtable to this file.
113 void X86InstrInfo::anchor() {}
114 
115 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
116     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117                                                : X86::ADJCALLSTACKDOWN32),
118                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119                                                : X86::ADJCALLSTACKUP32),
120                       X86::CATCHRET,
121                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
122       Subtarget(STI), RI(STI.getTargetTriple()) {
123 
124   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
125     { X86::ADC32ri,     X86::ADC32mi,    0 },
126     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
127     { X86::ADC32rr,     X86::ADC32mr,    0 },
128     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
129     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
130     { X86::ADC64rr,     X86::ADC64mr,    0 },
131     { X86::ADD16ri,     X86::ADD16mi,    0 },
132     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
133     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
134     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
135     { X86::ADD16rr,     X86::ADD16mr,    0 },
136     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
137     { X86::ADD32ri,     X86::ADD32mi,    0 },
138     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
139     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
140     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
141     { X86::ADD32rr,     X86::ADD32mr,    0 },
142     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
143     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
144     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
145     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
146     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
147     { X86::ADD64rr,     X86::ADD64mr,    0 },
148     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
149     { X86::ADD8ri,      X86::ADD8mi,     0 },
150     { X86::ADD8rr,      X86::ADD8mr,     0 },
151     { X86::AND16ri,     X86::AND16mi,    0 },
152     { X86::AND16ri8,    X86::AND16mi8,   0 },
153     { X86::AND16rr,     X86::AND16mr,    0 },
154     { X86::AND32ri,     X86::AND32mi,    0 },
155     { X86::AND32ri8,    X86::AND32mi8,   0 },
156     { X86::AND32rr,     X86::AND32mr,    0 },
157     { X86::AND64ri32,   X86::AND64mi32,  0 },
158     { X86::AND64ri8,    X86::AND64mi8,   0 },
159     { X86::AND64rr,     X86::AND64mr,    0 },
160     { X86::AND8ri,      X86::AND8mi,     0 },
161     { X86::AND8rr,      X86::AND8mr,     0 },
162     { X86::DEC16r,      X86::DEC16m,     0 },
163     { X86::DEC32r,      X86::DEC32m,     0 },
164     { X86::DEC64r,      X86::DEC64m,     0 },
165     { X86::DEC8r,       X86::DEC8m,      0 },
166     { X86::INC16r,      X86::INC16m,     0 },
167     { X86::INC32r,      X86::INC32m,     0 },
168     { X86::INC64r,      X86::INC64m,     0 },
169     { X86::INC8r,       X86::INC8m,      0 },
170     { X86::NEG16r,      X86::NEG16m,     0 },
171     { X86::NEG32r,      X86::NEG32m,     0 },
172     { X86::NEG64r,      X86::NEG64m,     0 },
173     { X86::NEG8r,       X86::NEG8m,      0 },
174     { X86::NOT16r,      X86::NOT16m,     0 },
175     { X86::NOT32r,      X86::NOT32m,     0 },
176     { X86::NOT64r,      X86::NOT64m,     0 },
177     { X86::NOT8r,       X86::NOT8m,      0 },
178     { X86::OR16ri,      X86::OR16mi,     0 },
179     { X86::OR16ri8,     X86::OR16mi8,    0 },
180     { X86::OR16rr,      X86::OR16mr,     0 },
181     { X86::OR32ri,      X86::OR32mi,     0 },
182     { X86::OR32ri8,     X86::OR32mi8,    0 },
183     { X86::OR32rr,      X86::OR32mr,     0 },
184     { X86::OR64ri32,    X86::OR64mi32,   0 },
185     { X86::OR64ri8,     X86::OR64mi8,    0 },
186     { X86::OR64rr,      X86::OR64mr,     0 },
187     { X86::OR8ri,       X86::OR8mi,      0 },
188     { X86::OR8rr,       X86::OR8mr,      0 },
189     { X86::ROL16r1,     X86::ROL16m1,    0 },
190     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
191     { X86::ROL16ri,     X86::ROL16mi,    0 },
192     { X86::ROL32r1,     X86::ROL32m1,    0 },
193     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
194     { X86::ROL32ri,     X86::ROL32mi,    0 },
195     { X86::ROL64r1,     X86::ROL64m1,    0 },
196     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
197     { X86::ROL64ri,     X86::ROL64mi,    0 },
198     { X86::ROL8r1,      X86::ROL8m1,     0 },
199     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
200     { X86::ROL8ri,      X86::ROL8mi,     0 },
201     { X86::ROR16r1,     X86::ROR16m1,    0 },
202     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
203     { X86::ROR16ri,     X86::ROR16mi,    0 },
204     { X86::ROR32r1,     X86::ROR32m1,    0 },
205     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
206     { X86::ROR32ri,     X86::ROR32mi,    0 },
207     { X86::ROR64r1,     X86::ROR64m1,    0 },
208     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
209     { X86::ROR64ri,     X86::ROR64mi,    0 },
210     { X86::ROR8r1,      X86::ROR8m1,     0 },
211     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
212     { X86::ROR8ri,      X86::ROR8mi,     0 },
213     { X86::SAR16r1,     X86::SAR16m1,    0 },
214     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
215     { X86::SAR16ri,     X86::SAR16mi,    0 },
216     { X86::SAR32r1,     X86::SAR32m1,    0 },
217     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
218     { X86::SAR32ri,     X86::SAR32mi,    0 },
219     { X86::SAR64r1,     X86::SAR64m1,    0 },
220     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
221     { X86::SAR64ri,     X86::SAR64mi,    0 },
222     { X86::SAR8r1,      X86::SAR8m1,     0 },
223     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
224     { X86::SAR8ri,      X86::SAR8mi,     0 },
225     { X86::SBB32ri,     X86::SBB32mi,    0 },
226     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
227     { X86::SBB32rr,     X86::SBB32mr,    0 },
228     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
229     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
230     { X86::SBB64rr,     X86::SBB64mr,    0 },
231     { X86::SHL16r1,     X86::SHL16m1,    0 },
232     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
233     { X86::SHL16ri,     X86::SHL16mi,    0 },
234     { X86::SHL32r1,     X86::SHL32m1,    0 },
235     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
236     { X86::SHL32ri,     X86::SHL32mi,    0 },
237     { X86::SHL64r1,     X86::SHL64m1,    0 },
238     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
239     { X86::SHL64ri,     X86::SHL64mi,    0 },
240     { X86::SHL8r1,      X86::SHL8m1,     0 },
241     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
242     { X86::SHL8ri,      X86::SHL8mi,     0 },
243     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
244     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
245     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
246     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
247     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
248     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
249     { X86::SHR16r1,     X86::SHR16m1,    0 },
250     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
251     { X86::SHR16ri,     X86::SHR16mi,    0 },
252     { X86::SHR32r1,     X86::SHR32m1,    0 },
253     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
254     { X86::SHR32ri,     X86::SHR32mi,    0 },
255     { X86::SHR64r1,     X86::SHR64m1,    0 },
256     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
257     { X86::SHR64ri,     X86::SHR64mi,    0 },
258     { X86::SHR8r1,      X86::SHR8m1,     0 },
259     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
260     { X86::SHR8ri,      X86::SHR8mi,     0 },
261     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
262     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
263     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
264     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
265     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
266     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
267     { X86::SUB16ri,     X86::SUB16mi,    0 },
268     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
269     { X86::SUB16rr,     X86::SUB16mr,    0 },
270     { X86::SUB32ri,     X86::SUB32mi,    0 },
271     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
272     { X86::SUB32rr,     X86::SUB32mr,    0 },
273     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
274     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
275     { X86::SUB64rr,     X86::SUB64mr,    0 },
276     { X86::SUB8ri,      X86::SUB8mi,     0 },
277     { X86::SUB8rr,      X86::SUB8mr,     0 },
278     { X86::XOR16ri,     X86::XOR16mi,    0 },
279     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
280     { X86::XOR16rr,     X86::XOR16mr,    0 },
281     { X86::XOR32ri,     X86::XOR32mi,    0 },
282     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
283     { X86::XOR32rr,     X86::XOR32mr,    0 },
284     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
285     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
286     { X86::XOR64rr,     X86::XOR64mr,    0 },
287     { X86::XOR8ri,      X86::XOR8mi,     0 },
288     { X86::XOR8rr,      X86::XOR8mr,     0 }
289   };
290 
291   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
292     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
293                   Entry.RegOp, Entry.MemOp,
294                   // Index 0, folded load and store, no alignment requirement.
295                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
296   }
297 
298   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
299     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
300     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
301     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
302     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
303     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
304     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
305     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
306     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
307     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
308     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
309     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
310     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
311     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
312     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
313     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
314     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
315     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
316     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
317     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
318     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
319     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
320     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
321     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
322     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
323     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
324     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
325     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
326     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
327     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
328     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
329     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
330     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
331     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
332     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
333     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
334     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
335     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
336     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
337     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
338     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
339     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
340     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
341     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
342     { X86::MOVDQUrr,    X86::MOVDQUmr,      TB_FOLDED_STORE },
343     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
344     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
345     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
346     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
347     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
348     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
349     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
350     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
351     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
352     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
353     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
354     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
355     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
356     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
357     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
358     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
359     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
360     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
361     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
362     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
363     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
364     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
365     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
366     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
367     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
368     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
369     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
370     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
371     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
372     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
373     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
374     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
375     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
376     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
377     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
378     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
379     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
380     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
381 
382     // AVX 128-bit versions of foldable instructions
383     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
384     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
385     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
386     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
387     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
388     { X86::VMOVDQUrr,   X86::VMOVDQUmr,     TB_FOLDED_STORE },
389     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
390     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
391     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
392     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
393     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
394     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
395     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
396     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
397 
398     // AVX 256-bit foldable instructions
399     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
400     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
401     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
402     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
403     { X86::VMOVDQUYrr,  X86::VMOVDQUYmr,    TB_FOLDED_STORE },
404     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
405     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
406 
407     // AVX-512 foldable instructions
408     { X86::VEXTRACTF32x4Zrr,X86::VEXTRACTF32x4Zmr, TB_FOLDED_STORE },
409     { X86::VEXTRACTF32x8Zrr,X86::VEXTRACTF32x8Zmr, TB_FOLDED_STORE },
410     { X86::VEXTRACTF64x2Zrr,X86::VEXTRACTF64x2Zmr, TB_FOLDED_STORE },
411     { X86::VEXTRACTF64x4Zrr,X86::VEXTRACTF64x4Zmr, TB_FOLDED_STORE },
412     { X86::VEXTRACTI32x4Zrr,X86::VEXTRACTI32x4Zmr, TB_FOLDED_STORE },
413     { X86::VEXTRACTI32x8Zrr,X86::VEXTRACTI32x8Zmr, TB_FOLDED_STORE },
414     { X86::VEXTRACTI64x2Zrr,X86::VEXTRACTI64x2Zmr, TB_FOLDED_STORE },
415     { X86::VEXTRACTI64x4Zrr,X86::VEXTRACTI64x4Zmr, TB_FOLDED_STORE },
416     { X86::VEXTRACTPSZrr,   X86::VEXTRACTPSZmr,    TB_FOLDED_STORE },
417     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
418     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
419     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
420     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
421     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
422     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
423     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
424     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
425     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
426     { X86::VMOVPQIto64Zrr,  X86::VMOVPQI2QIZmr, TB_FOLDED_STORE },
427     { X86::VMOVSDto64Zrr,   X86::VMOVSDto64Zmr, TB_FOLDED_STORE },
428     { X86::VMOVSS2DIZrr,    X86::VMOVSS2DIZmr,  TB_FOLDED_STORE },
429     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
430     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
431     { X86::VPEXTRDZrr,      X86::VPEXTRDZmr,    TB_FOLDED_STORE },
432     { X86::VPEXTRQZrr,      X86::VPEXTRQZmr,    TB_FOLDED_STORE },
433     { X86::VPMOVDBZrr,      X86::VPMOVDBZmr,    TB_FOLDED_STORE },
434     { X86::VPMOVDWZrr,      X86::VPMOVDWZmr,    TB_FOLDED_STORE },
435     { X86::VPMOVQDZrr,      X86::VPMOVQDZmr,    TB_FOLDED_STORE },
436     { X86::VPMOVQWZrr,      X86::VPMOVQWZmr,    TB_FOLDED_STORE },
437     { X86::VPMOVWBZrr,      X86::VPMOVWBZmr,    TB_FOLDED_STORE },
438     { X86::VPMOVSDBZrr,     X86::VPMOVSDBZmr,   TB_FOLDED_STORE },
439     { X86::VPMOVSDWZrr,     X86::VPMOVSDWZmr,   TB_FOLDED_STORE },
440     { X86::VPMOVSQDZrr,     X86::VPMOVSQDZmr,   TB_FOLDED_STORE },
441     { X86::VPMOVSQWZrr,     X86::VPMOVSQWZmr,   TB_FOLDED_STORE },
442     { X86::VPMOVSWBZrr,     X86::VPMOVSWBZmr,   TB_FOLDED_STORE },
443     { X86::VPMOVUSDBZrr,    X86::VPMOVUSDBZmr,  TB_FOLDED_STORE },
444     { X86::VPMOVUSDWZrr,    X86::VPMOVUSDWZmr,  TB_FOLDED_STORE },
445     { X86::VPMOVUSQDZrr,    X86::VPMOVUSQDZmr,  TB_FOLDED_STORE },
446     { X86::VPMOVUSQWZrr,    X86::VPMOVUSQWZmr,  TB_FOLDED_STORE },
447     { X86::VPMOVUSWBZrr,    X86::VPMOVUSWBZmr,  TB_FOLDED_STORE },
448 
449     // AVX-512 foldable instructions (256-bit versions)
450     { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256mr, TB_FOLDED_STORE },
451     { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256mr, TB_FOLDED_STORE },
452     { X86::VEXTRACTI32x4Z256rr,X86::VEXTRACTI32x4Z256mr, TB_FOLDED_STORE },
453     { X86::VEXTRACTI64x2Z256rr,X86::VEXTRACTI64x2Z256mr, TB_FOLDED_STORE },
454     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
455     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
456     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
457     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
458     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
459     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
460     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
461     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
462     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
463     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
464     { X86::VPMOVDWZ256rr,      X86::VPMOVDWZ256mr,    TB_FOLDED_STORE },
465     { X86::VPMOVQDZ256rr,      X86::VPMOVQDZ256mr,    TB_FOLDED_STORE },
466     { X86::VPMOVWBZ256rr,      X86::VPMOVWBZ256mr,    TB_FOLDED_STORE },
467     { X86::VPMOVSDWZ256rr,     X86::VPMOVSDWZ256mr,   TB_FOLDED_STORE },
468     { X86::VPMOVSQDZ256rr,     X86::VPMOVSQDZ256mr,   TB_FOLDED_STORE },
469     { X86::VPMOVSWBZ256rr,     X86::VPMOVSWBZ256mr,   TB_FOLDED_STORE },
470     { X86::VPMOVUSDWZ256rr,    X86::VPMOVUSDWZ256mr,  TB_FOLDED_STORE },
471     { X86::VPMOVUSQDZ256rr,    X86::VPMOVUSQDZ256mr,  TB_FOLDED_STORE },
472     { X86::VPMOVUSWBZ256rr,    X86::VPMOVUSWBZ256mr,  TB_FOLDED_STORE },
473 
474     // AVX-512 foldable instructions (128-bit versions)
475     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
476     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
477     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
478     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
479     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
480     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
481     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
482     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
483     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
484     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
485 
486     // F16C foldable instructions
487     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
488     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
489   };
490 
491   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
492     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
493                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
494   }
495 
496   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
497     { X86::BSF16rr,         X86::BSF16rm,             0 },
498     { X86::BSF32rr,         X86::BSF32rm,             0 },
499     { X86::BSF64rr,         X86::BSF64rm,             0 },
500     { X86::BSR16rr,         X86::BSR16rm,             0 },
501     { X86::BSR32rr,         X86::BSR32rm,             0 },
502     { X86::BSR64rr,         X86::BSR64rm,             0 },
503     { X86::CMP16rr,         X86::CMP16rm,             0 },
504     { X86::CMP32rr,         X86::CMP32rm,             0 },
505     { X86::CMP64rr,         X86::CMP64rm,             0 },
506     { X86::CMP8rr,          X86::CMP8rm,              0 },
507     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
508     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
509     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
510     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
511     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
512     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
513     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
514     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
515     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
516     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
517     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
518     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
519     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
520     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
521     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
522     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
523     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        TB_NO_REVERSE },
524     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        TB_NO_REVERSE },
525     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        TB_NO_REVERSE },
526     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          TB_NO_REVERSE },
527     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        TB_NO_REVERSE },
528     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          TB_NO_REVERSE },
529     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_NO_REVERSE },
530     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
531     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
532     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
533     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
534     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_NO_REVERSE },
535     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
536     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
537     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  TB_NO_REVERSE },
538     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     TB_NO_REVERSE },
539     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  TB_NO_REVERSE },
540     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     TB_NO_REVERSE },
541     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       TB_NO_REVERSE },
542     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       TB_NO_REVERSE },
543     { X86::MOV16rr,         X86::MOV16rm,             0 },
544     { X86::MOV32rr,         X86::MOV32rm,             0 },
545     { X86::MOV64rr,         X86::MOV64rm,             0 },
546     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
547     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
548     { X86::MOV8rr,          X86::MOV8rm,              0 },
549     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
550     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
551     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           TB_NO_REVERSE },
552     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
553     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
554     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
555     { X86::MOVDQUrr,        X86::MOVDQUrm,            0 },
556     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
557     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
558     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
559     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
560     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
561     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
562     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
563     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
564     { X86::MOVUPDrr,        X86::MOVUPDrm,            0 },
565     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
566     { X86::MOVZPQILo2PQIrr, X86::MOVQI2PQIrm,         TB_NO_REVERSE },
567     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
568     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
569     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
570     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
571     { X86::PABSBrr,         X86::PABSBrm,             TB_ALIGN_16 },
572     { X86::PABSDrr,         X86::PABSDrm,             TB_ALIGN_16 },
573     { X86::PABSWrr,         X86::PABSWrm,             TB_ALIGN_16 },
574     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
575     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
576     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
577     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
578     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
579     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_NO_REVERSE },
580     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_NO_REVERSE },
581     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_NO_REVERSE },
582     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_NO_REVERSE },
583     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_NO_REVERSE },
584     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_NO_REVERSE },
585     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_NO_REVERSE },
586     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_NO_REVERSE },
587     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_NO_REVERSE },
588     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_NO_REVERSE },
589     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_NO_REVERSE },
590     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_NO_REVERSE },
591     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
592     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
593     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
594     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
595     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
596     { X86::RCPSSr,          X86::RCPSSm,              0 },
597     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          TB_NO_REVERSE },
598     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
599     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
600     { X86::ROUNDSDr,        X86::ROUNDSDm,            0 },
601     { X86::ROUNDSSr,        X86::ROUNDSSm,            0 },
602     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
603     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
604     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        TB_NO_REVERSE },
605     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
606     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
607     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
608     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         TB_NO_REVERSE },
609     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
610     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         TB_NO_REVERSE },
611     { X86::TEST16rr,        X86::TEST16rm,            0 },
612     { X86::TEST32rr,        X86::TEST32rm,            0 },
613     { X86::TEST64rr,        X86::TEST64rm,            0 },
614     { X86::TEST8rr,         X86::TEST8rm,             0 },
615     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
616     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
617     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
618 
619     // MMX version of foldable instructions
620     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
621     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
622     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
623     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
624     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
625     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
626     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
627     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
628     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
629     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
630 
631     // 3DNow! version of foldable instructions
632     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
633     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
634     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
635     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
636     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
637     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
638     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
639 
640     // AVX 128-bit versions of foldable instructions
641     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       TB_NO_REVERSE },
642     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       TB_NO_REVERSE },
643     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      TB_NO_REVERSE },
644     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      TB_NO_REVERSE },
645     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
646     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,TB_NO_REVERSE },
647     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
648     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    TB_NO_REVERSE },
649     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
650     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,TB_NO_REVERSE },
651     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
652     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    TB_NO_REVERSE },
653     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       TB_NO_REVERSE },
654     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         TB_NO_REVERSE },
655     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       TB_NO_REVERSE },
656     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         TB_NO_REVERSE },
657     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         TB_NO_REVERSE },
658     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
659     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQrm,         0 },
660     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSrm,         0 },
661     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
662     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         TB_NO_REVERSE },
663     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQrm,        0 },
664     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
665     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
666     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
667     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
668     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
669     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          TB_NO_REVERSE },
670     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
671     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
672     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
673     { X86::VMOVDQUrr,       X86::VMOVDQUrm,           0 },
674     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
675     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
676     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
677     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
678     { X86::VMOVZPQILo2PQIrr,X86::VMOVQI2PQIrm,        TB_NO_REVERSE },
679     { X86::VPABSBrr,        X86::VPABSBrm,            0 },
680     { X86::VPABSDrr,        X86::VPABSDrm,            0 },
681     { X86::VPABSWrr,        X86::VPABSWrm,            0 },
682     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
683     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
684     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
685     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
686     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
687     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
688     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
689     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         TB_NO_REVERSE },
690     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         TB_NO_REVERSE },
691     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         TB_NO_REVERSE },
692     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         TB_NO_REVERSE },
693     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         TB_NO_REVERSE },
694     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         TB_NO_REVERSE },
695     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         TB_NO_REVERSE },
696     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         TB_NO_REVERSE },
697     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         TB_NO_REVERSE },
698     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         TB_NO_REVERSE },
699     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         TB_NO_REVERSE },
700     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         TB_NO_REVERSE },
701     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
702     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
703     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
704     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
705     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
706     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
707     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
708     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
709     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
710     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
711     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
712     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
713     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
714     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
715 
716     // AVX 256-bit foldable instructions
717     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        TB_NO_REVERSE },
718     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
719     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
720     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
721     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
722     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        TB_NO_REVERSE },
723     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
724     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
725     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
726     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
727     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
728     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
729     { X86::VMOVDQUYrr,      X86::VMOVDQUYrm,          0 },
730     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
731     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
732     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
733     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
734     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
735     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
736     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
737     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
738     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
739     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
740     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
741     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
742     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
743     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
744     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
745 
746     // AVX2 foldable instructions
747 
748     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
749     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
750     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
751     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
752     // so they don't need an equivalent limitation.
753     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
754     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
755     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
756     { X86::VPABSBYrr,       X86::VPABSBYrm,           0 },
757     { X86::VPABSDYrr,       X86::VPABSDYrm,           0 },
758     { X86::VPABSWYrr,       X86::VPABSWYrm,           0 },
759     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      TB_NO_REVERSE },
760     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     TB_NO_REVERSE },
761     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      TB_NO_REVERSE },
762     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     TB_NO_REVERSE },
763     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      TB_NO_REVERSE },
764     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     TB_NO_REVERSE },
765     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      TB_NO_REVERSE },
766     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     TB_NO_REVERSE },
767     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
768     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
769     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        TB_NO_REVERSE },
770     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        TB_NO_REVERSE },
771     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
772     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
773     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
774     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        TB_NO_REVERSE },
775     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        TB_NO_REVERSE },
776     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        TB_NO_REVERSE },
777     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
778     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
779     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
780     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        TB_NO_REVERSE },
781     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
782     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
783     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
784 
785     // XOP foldable instructions
786     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
787     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
788     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
789     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
790     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
791     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
792     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
793     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
794     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
795     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
796     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
797     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
798     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
799     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
800     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
801     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
802     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
803     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
804     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
805     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
806     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
807     { X86::VPROTBri,           X86::VPROTBmi,         0 },
808     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
809     { X86::VPROTDri,           X86::VPROTDmi,         0 },
810     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
811     { X86::VPROTQri,           X86::VPROTQmi,         0 },
812     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
813     { X86::VPROTWri,           X86::VPROTWmi,         0 },
814     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
815     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
816     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
817     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
818     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
819     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
820     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
821     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
822     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
823 
824     // LWP foldable instructions
825     { X86::LWPINS32rri,        X86::LWPINS32rmi,      0 },
826     { X86::LWPINS64rri,        X86::LWPINS64rmi,      0 },
827     { X86::LWPVAL32rri,        X86::LWPVAL32rmi,      0 },
828     { X86::LWPVAL64rri,        X86::LWPVAL64rmi,      0 },
829 
830     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
831     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
832     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
833     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
834     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
835     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
836     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
837     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
838     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
839     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
840     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
841     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
842     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
843     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
844     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
845     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
846     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
847     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
848     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
849     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
850     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
851     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
852     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
853     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
854     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
855     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
856     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
857     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
858     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
859     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
860     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
861     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
862     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
863     { X86::RORX32ri,        X86::RORX32mi,            0 },
864     { X86::RORX64ri,        X86::RORX64mi,            0 },
865     { X86::SARX32rr,        X86::SARX32rm,            0 },
866     { X86::SARX64rr,        X86::SARX64rm,            0 },
867     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
868     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
869     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
870     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
871     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
872     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
873     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
874     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
875     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
876     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
877     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
878 
879     // AVX-512 foldable instructions
880     { X86::VBROADCASTSSZr,   X86::VBROADCASTSSZm,     TB_NO_REVERSE },
881     { X86::VBROADCASTSDZr,   X86::VBROADCASTSDZm,     TB_NO_REVERSE },
882     { X86::VMOV64toPQIZrr,   X86::VMOVQI2PQIZrm,      0 },
883     { X86::VMOV64toSDZrr,    X86::VMOV64toSDZrm,      0 },
884     { X86::VMOVDI2PDIZrr,    X86::VMOVDI2PDIZrm,      0 },
885     { X86::VMOVDI2SSZrr,     X86::VMOVDI2SSZrm,       0 },
886     { X86::VMOVAPDZrr,       X86::VMOVAPDZrm,         TB_ALIGN_64 },
887     { X86::VMOVAPSZrr,       X86::VMOVAPSZrm,         TB_ALIGN_64 },
888     { X86::VMOVDQA32Zrr,     X86::VMOVDQA32Zrm,       TB_ALIGN_64 },
889     { X86::VMOVDQA64Zrr,     X86::VMOVDQA64Zrm,       TB_ALIGN_64 },
890     { X86::VMOVDQU8Zrr,      X86::VMOVDQU8Zrm,        0 },
891     { X86::VMOVDQU16Zrr,     X86::VMOVDQU16Zrm,       0 },
892     { X86::VMOVDQU32Zrr,     X86::VMOVDQU32Zrm,       0 },
893     { X86::VMOVDQU64Zrr,     X86::VMOVDQU64Zrm,       0 },
894     { X86::VMOVUPDZrr,       X86::VMOVUPDZrm,         0 },
895     { X86::VMOVUPSZrr,       X86::VMOVUPSZrm,         0 },
896     { X86::VMOVZPQILo2PQIZrr,X86::VMOVQI2PQIZrm,      TB_NO_REVERSE },
897     { X86::VPABSBZrr,        X86::VPABSBZrm,          0 },
898     { X86::VPABSDZrr,        X86::VPABSDZrm,          0 },
899     { X86::VPABSQZrr,        X86::VPABSQZrm,          0 },
900     { X86::VPABSWZrr,        X86::VPABSWZrm,          0 },
901     { X86::VPCONFLICTDZrr,   X86::VPCONFLICTDZrm,     0 },
902     { X86::VPCONFLICTQZrr,   X86::VPCONFLICTQZrm,     0 },
903     { X86::VPERMILPDZri,     X86::VPERMILPDZmi,       0 },
904     { X86::VPERMILPSZri,     X86::VPERMILPSZmi,       0 },
905     { X86::VPERMPDZri,       X86::VPERMPDZmi,         0 },
906     { X86::VPERMQZri,        X86::VPERMQZmi,          0 },
907     { X86::VPLZCNTDZrr,      X86::VPLZCNTDZrm,        0 },
908     { X86::VPLZCNTQZrr,      X86::VPLZCNTQZrm,        0 },
909     { X86::VPMOVSXBDZrr,     X86::VPMOVSXBDZrm,       0 },
910     { X86::VPMOVSXBQZrr,     X86::VPMOVSXBQZrm,       TB_NO_REVERSE },
911     { X86::VPMOVSXBWZrr,     X86::VPMOVSXBWZrm,       0 },
912     { X86::VPMOVSXDQZrr,     X86::VPMOVSXDQZrm,       0 },
913     { X86::VPMOVSXWDZrr,     X86::VPMOVSXWDZrm,       0 },
914     { X86::VPMOVSXWQZrr,     X86::VPMOVSXWQZrm,       0 },
915     { X86::VPMOVZXBDZrr,     X86::VPMOVZXBDZrm,       0 },
916     { X86::VPMOVZXBQZrr,     X86::VPMOVZXBQZrm,       TB_NO_REVERSE },
917     { X86::VPMOVZXBWZrr,     X86::VPMOVZXBWZrm,       0 },
918     { X86::VPMOVZXDQZrr,     X86::VPMOVZXDQZrm,       0 },
919     { X86::VPMOVZXWDZrr,     X86::VPMOVZXWDZrm,       0 },
920     { X86::VPMOVZXWQZrr,     X86::VPMOVZXWQZrm,       0 },
921     { X86::VPOPCNTDZrr,      X86::VPOPCNTDZrm,        0 },
922     { X86::VPOPCNTQZrr,      X86::VPOPCNTQZrm,        0 },
923     { X86::VPSHUFDZri,       X86::VPSHUFDZmi,         0 },
924     { X86::VPSHUFHWZri,      X86::VPSHUFHWZmi,        0 },
925     { X86::VPSHUFLWZri,      X86::VPSHUFLWZmi,        0 },
926     { X86::VPSLLDQZ512rr,    X86::VPSLLDQZ512rm,      0 },
927     { X86::VPSLLDZri,        X86::VPSLLDZmi,          0 },
928     { X86::VPSLLQZri,        X86::VPSLLQZmi,          0 },
929     { X86::VPSLLWZri,        X86::VPSLLWZmi,          0 },
930     { X86::VPSRADZri,        X86::VPSRADZmi,          0 },
931     { X86::VPSRAQZri,        X86::VPSRAQZmi,          0 },
932     { X86::VPSRAWZri,        X86::VPSRAWZmi,          0 },
933     { X86::VPSRLDQZ512rr,    X86::VPSRLDQZ512rm,      0 },
934     { X86::VPSRLDZri,        X86::VPSRLDZmi,          0 },
935     { X86::VPSRLQZri,        X86::VPSRLQZmi,          0 },
936     { X86::VPSRLWZri,        X86::VPSRLWZmi,          0 },
937 
938     // AVX-512 foldable instructions (256-bit versions)
939     { X86::VBROADCASTSSZ256r,    X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
940     { X86::VBROADCASTSDZ256r,    X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
941     { X86::VMOVAPDZ256rr,        X86::VMOVAPDZ256rm,        TB_ALIGN_32 },
942     { X86::VMOVAPSZ256rr,        X86::VMOVAPSZ256rm,        TB_ALIGN_32 },
943     { X86::VMOVDQA32Z256rr,      X86::VMOVDQA32Z256rm,      TB_ALIGN_32 },
944     { X86::VMOVDQA64Z256rr,      X86::VMOVDQA64Z256rm,      TB_ALIGN_32 },
945     { X86::VMOVDQU8Z256rr,       X86::VMOVDQU8Z256rm,       0 },
946     { X86::VMOVDQU16Z256rr,      X86::VMOVDQU16Z256rm,      0 },
947     { X86::VMOVDQU32Z256rr,      X86::VMOVDQU32Z256rm,      0 },
948     { X86::VMOVDQU64Z256rr,      X86::VMOVDQU64Z256rm,      0 },
949     { X86::VMOVUPDZ256rr,        X86::VMOVUPDZ256rm,        0 },
950     { X86::VMOVUPSZ256rr,        X86::VMOVUPSZ256rm,        0 },
951     { X86::VPABSBZ256rr,         X86::VPABSBZ256rm,         0 },
952     { X86::VPABSDZ256rr,         X86::VPABSDZ256rm,         0 },
953     { X86::VPABSQZ256rr,         X86::VPABSQZ256rm,         0 },
954     { X86::VPABSWZ256rr,         X86::VPABSWZ256rm,         0 },
955     { X86::VPCONFLICTDZ256rr,    X86::VPCONFLICTDZ256rm,    0 },
956     { X86::VPCONFLICTQZ256rr,    X86::VPCONFLICTQZ256rm,    0 },
957     { X86::VPERMILPDZ256ri,      X86::VPERMILPDZ256mi,      0 },
958     { X86::VPERMILPSZ256ri,      X86::VPERMILPSZ256mi,      0 },
959     { X86::VPERMPDZ256ri,        X86::VPERMPDZ256mi,        0 },
960     { X86::VPERMQZ256ri,         X86::VPERMQZ256mi,         0 },
961     { X86::VPLZCNTDZ256rr,       X86::VPLZCNTDZ256rm,       0 },
962     { X86::VPLZCNTQZ256rr,       X86::VPLZCNTQZ256rm,       0 },
963     { X86::VPMOVSXBDZ256rr,      X86::VPMOVSXBDZ256rm,      TB_NO_REVERSE },
964     { X86::VPMOVSXBQZ256rr,      X86::VPMOVSXBQZ256rm,      TB_NO_REVERSE },
965     { X86::VPMOVSXBWZ256rr,      X86::VPMOVSXBWZ256rm,      0 },
966     { X86::VPMOVSXDQZ256rr,      X86::VPMOVSXDQZ256rm,      0 },
967     { X86::VPMOVSXWDZ256rr,      X86::VPMOVSXWDZ256rm,      0 },
968     { X86::VPMOVSXWQZ256rr,      X86::VPMOVSXWQZ256rm,      TB_NO_REVERSE },
969     { X86::VPMOVZXBDZ256rr,      X86::VPMOVZXBDZ256rm,      TB_NO_REVERSE },
970     { X86::VPMOVZXBQZ256rr,      X86::VPMOVZXBQZ256rm,      TB_NO_REVERSE },
971     { X86::VPMOVZXBWZ256rr,      X86::VPMOVZXBWZ256rm,      0 },
972     { X86::VPMOVZXDQZ256rr,      X86::VPMOVZXDQZ256rm,      0 },
973     { X86::VPMOVZXWDZ256rr,      X86::VPMOVZXWDZ256rm,      0 },
974     { X86::VPMOVZXWQZ256rr,      X86::VPMOVZXWQZ256rm,      TB_NO_REVERSE },
975     { X86::VPSHUFDZ256ri,        X86::VPSHUFDZ256mi,        0 },
976     { X86::VPSHUFHWZ256ri,       X86::VPSHUFHWZ256mi,       0 },
977     { X86::VPSHUFLWZ256ri,       X86::VPSHUFLWZ256mi,       0 },
978     { X86::VPSLLDQZ256rr,        X86::VPSLLDQZ256rm,        0 },
979     { X86::VPSLLDZ256ri,         X86::VPSLLDZ256mi,         0 },
980     { X86::VPSLLQZ256ri,         X86::VPSLLQZ256mi,         0 },
981     { X86::VPSLLWZ256ri,         X86::VPSLLWZ256mi,         0 },
982     { X86::VPSRADZ256ri,         X86::VPSRADZ256mi,         0 },
983     { X86::VPSRAQZ256ri,         X86::VPSRAQZ256mi,         0 },
984     { X86::VPSRAWZ256ri,         X86::VPSRAWZ256mi,         0 },
985     { X86::VPSRLDQZ256rr,        X86::VPSRLDQZ256rm,        0 },
986     { X86::VPSRLDZ256ri,         X86::VPSRLDZ256mi,         0 },
987     { X86::VPSRLQZ256ri,         X86::VPSRLQZ256mi,         0 },
988     { X86::VPSRLWZ256ri,         X86::VPSRLWZ256mi,         0 },
989 
990     // AVX-512 foldable instructions (128-bit versions)
991     { X86::VBROADCASTSSZ128r,    X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
992     { X86::VMOVAPDZ128rr,        X86::VMOVAPDZ128rm,        TB_ALIGN_16 },
993     { X86::VMOVAPSZ128rr,        X86::VMOVAPSZ128rm,        TB_ALIGN_16 },
994     { X86::VMOVDQA32Z128rr,      X86::VMOVDQA32Z128rm,      TB_ALIGN_16 },
995     { X86::VMOVDQA64Z128rr,      X86::VMOVDQA64Z128rm,      TB_ALIGN_16 },
996     { X86::VMOVDQU8Z128rr,       X86::VMOVDQU8Z128rm,       0 },
997     { X86::VMOVDQU16Z128rr,      X86::VMOVDQU16Z128rm,      0 },
998     { X86::VMOVDQU32Z128rr,      X86::VMOVDQU32Z128rm,      0 },
999     { X86::VMOVDQU64Z128rr,      X86::VMOVDQU64Z128rm,      0 },
1000     { X86::VMOVUPDZ128rr,        X86::VMOVUPDZ128rm,        0 },
1001     { X86::VMOVUPSZ128rr,        X86::VMOVUPSZ128rm,        0 },
1002     { X86::VPABSBZ128rr,         X86::VPABSBZ128rm,         0 },
1003     { X86::VPABSDZ128rr,         X86::VPABSDZ128rm,         0 },
1004     { X86::VPABSQZ128rr,         X86::VPABSQZ128rm,         0 },
1005     { X86::VPABSWZ128rr,         X86::VPABSWZ128rm,         0 },
1006     { X86::VPCONFLICTDZ128rr,    X86::VPCONFLICTDZ128rm,    0 },
1007     { X86::VPCONFLICTQZ128rr,    X86::VPCONFLICTQZ128rm,    0 },
1008     { X86::VPERMILPDZ128ri,      X86::VPERMILPDZ128mi,      0 },
1009     { X86::VPERMILPSZ128ri,      X86::VPERMILPSZ128mi,      0 },
1010     { X86::VPLZCNTDZ128rr,       X86::VPLZCNTDZ128rm,       0 },
1011     { X86::VPLZCNTQZ128rr,       X86::VPLZCNTQZ128rm,       0 },
1012     { X86::VPMOVSXBDZ128rr,      X86::VPMOVSXBDZ128rm,      TB_NO_REVERSE },
1013     { X86::VPMOVSXBQZ128rr,      X86::VPMOVSXBQZ128rm,      TB_NO_REVERSE },
1014     { X86::VPMOVSXBWZ128rr,      X86::VPMOVSXBWZ128rm,      TB_NO_REVERSE },
1015     { X86::VPMOVSXDQZ128rr,      X86::VPMOVSXDQZ128rm,      TB_NO_REVERSE },
1016     { X86::VPMOVSXWDZ128rr,      X86::VPMOVSXWDZ128rm,      TB_NO_REVERSE },
1017     { X86::VPMOVSXWQZ128rr,      X86::VPMOVSXWQZ128rm,      TB_NO_REVERSE },
1018     { X86::VPMOVZXBDZ128rr,      X86::VPMOVZXBDZ128rm,      TB_NO_REVERSE },
1019     { X86::VPMOVZXBQZ128rr,      X86::VPMOVZXBQZ128rm,      TB_NO_REVERSE },
1020     { X86::VPMOVZXBWZ128rr,      X86::VPMOVZXBWZ128rm,      TB_NO_REVERSE },
1021     { X86::VPMOVZXDQZ128rr,      X86::VPMOVZXDQZ128rm,      TB_NO_REVERSE },
1022     { X86::VPMOVZXWDZ128rr,      X86::VPMOVZXWDZ128rm,      TB_NO_REVERSE },
1023     { X86::VPMOVZXWQZ128rr,      X86::VPMOVZXWQZ128rm,      TB_NO_REVERSE },
1024     { X86::VPSHUFDZ128ri,        X86::VPSHUFDZ128mi,        0 },
1025     { X86::VPSHUFHWZ128ri,       X86::VPSHUFHWZ128mi,       0 },
1026     { X86::VPSHUFLWZ128ri,       X86::VPSHUFLWZ128mi,       0 },
1027     { X86::VPSLLDQZ128rr,        X86::VPSLLDQZ128rm,        0 },
1028     { X86::VPSLLDZ128ri,         X86::VPSLLDZ128mi,         0 },
1029     { X86::VPSLLQZ128ri,         X86::VPSLLQZ128mi,         0 },
1030     { X86::VPSLLWZ128ri,         X86::VPSLLWZ128mi,         0 },
1031     { X86::VPSRADZ128ri,         X86::VPSRADZ128mi,         0 },
1032     { X86::VPSRAQZ128ri,         X86::VPSRAQZ128mi,         0 },
1033     { X86::VPSRAWZ128ri,         X86::VPSRAWZ128mi,         0 },
1034     { X86::VPSRLDQZ128rr,        X86::VPSRLDQZ128rm,        0 },
1035     { X86::VPSRLDZ128ri,         X86::VPSRLDZ128mi,         0 },
1036     { X86::VPSRLQZ128ri,         X86::VPSRLQZ128mi,         0 },
1037     { X86::VPSRLWZ128ri,         X86::VPSRLWZ128mi,         0 },
1038 
1039     // F16C foldable instructions
1040     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
1041     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
1042 
1043     // AES foldable instructions
1044     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
1045     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
1046     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
1047     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
1048   };
1049 
1050   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
1051     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
1052                   Entry.RegOp, Entry.MemOp,
1053                   // Index 1, folded load
1054                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
1055   }
1056 
1057   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
1058     { X86::ADC32rr,         X86::ADC32rm,       0 },
1059     { X86::ADC64rr,         X86::ADC64rm,       0 },
1060     { X86::ADD16rr,         X86::ADD16rm,       0 },
1061     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
1062     { X86::ADD32rr,         X86::ADD32rm,       0 },
1063     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
1064     { X86::ADD64rr,         X86::ADD64rm,       0 },
1065     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
1066     { X86::ADD8rr,          X86::ADD8rm,        0 },
1067     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
1068     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
1069     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
1070     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   TB_NO_REVERSE },
1071     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
1072     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   TB_NO_REVERSE },
1073     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
1074     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
1075     { X86::AND16rr,         X86::AND16rm,       0 },
1076     { X86::AND32rr,         X86::AND32rm,       0 },
1077     { X86::AND64rr,         X86::AND64rm,       0 },
1078     { X86::AND8rr,          X86::AND8rm,        0 },
1079     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
1080     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
1081     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
1082     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
1083     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
1084     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
1085     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
1086     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
1087     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
1088     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
1089     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
1090     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
1091     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
1092     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
1093     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
1094     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
1095     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
1096     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
1097     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
1098     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
1099     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
1100     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
1101     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
1102     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
1103     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
1104     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
1105     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
1106     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
1107     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
1108     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
1109     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
1110     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
1111     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
1112     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
1113     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
1114     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
1115     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
1116     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
1117     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
1118     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
1119     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
1120     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
1121     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
1122     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
1123     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
1124     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
1125     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
1126     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
1127     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
1128     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
1129     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
1130     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
1131     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
1132     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
1133     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
1134     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
1135     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
1136     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
1137     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
1138     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
1139     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
1140     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
1141     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
1142     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
1143     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
1144     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   TB_NO_REVERSE },
1145     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
1146     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   TB_NO_REVERSE },
1147     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
1148     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
1149     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
1150     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
1151     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
1152     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
1153     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
1154     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
1155     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
1156     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   TB_NO_REVERSE },
1157     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   TB_NO_REVERSE },
1158     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      TB_NO_REVERSE },
1159     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
1160     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
1161     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
1162     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
1163     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      TB_NO_REVERSE },
1164     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
1165     { X86::MAXCPDrr,        X86::MAXCPDrm,      TB_ALIGN_16 },
1166     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
1167     { X86::MAXCPSrr,        X86::MAXCPSrm,      TB_ALIGN_16 },
1168     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
1169     { X86::MAXCSDrr,        X86::MAXCSDrm,      0 },
1170     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   TB_NO_REVERSE },
1171     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
1172     { X86::MAXCSSrr,        X86::MAXCSSrm,      0 },
1173     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   TB_NO_REVERSE },
1174     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
1175     { X86::MINCPDrr,        X86::MINCPDrm,      TB_ALIGN_16 },
1176     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
1177     { X86::MINCPSrr,        X86::MINCPSrm,      TB_ALIGN_16 },
1178     { X86::MINSDrr,         X86::MINSDrm,       0 },
1179     { X86::MINCSDrr,        X86::MINCSDrm,      0 },
1180     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   TB_NO_REVERSE },
1181     { X86::MINSSrr,         X86::MINSSrm,       0 },
1182     { X86::MINCSSrr,        X86::MINCSSrm,      0 },
1183     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   TB_NO_REVERSE },
1184     { X86::MOVLHPSrr,       X86::MOVHPSrm,      TB_NO_REVERSE },
1185     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1186     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1187     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1188     { X86::MULSDrr,         X86::MULSDrm,       0 },
1189     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   TB_NO_REVERSE },
1190     { X86::MULSSrr,         X86::MULSSrm,       0 },
1191     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   TB_NO_REVERSE },
1192     { X86::OR16rr,          X86::OR16rm,        0 },
1193     { X86::OR32rr,          X86::OR32rm,        0 },
1194     { X86::OR64rr,          X86::OR64rm,        0 },
1195     { X86::OR8rr,           X86::OR8rm,         0 },
1196     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1197     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1198     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1199     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1200     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1201     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1202     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1203     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1204     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1205     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1206     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1207     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1208     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1209     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1210     { X86::PALIGNRrri,      X86::PALIGNRrmi,    TB_ALIGN_16 },
1211     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1212     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1213     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1214     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1215     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1216     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1217     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1218     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1219     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1220     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1221     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1222     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1223     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1224     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1225     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1226     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1227     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1228     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1229     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1230     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1231     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1232     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1233     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1234     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1235     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1236     { X86::PMADDUBSWrr,     X86::PMADDUBSWrm,   TB_ALIGN_16 },
1237     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1238     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1239     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1240     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1241     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1242     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1243     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1244     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1245     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1246     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1247     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1248     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1249     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1250     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1251     { X86::PMULHRSWrr,      X86::PMULHRSWrm,    TB_ALIGN_16 },
1252     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1253     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1254     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1255     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1256     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1257     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1258     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1259     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1260     { X86::PSIGNBrr128,     X86::PSIGNBrm128,   TB_ALIGN_16 },
1261     { X86::PSIGNWrr128,     X86::PSIGNWrm128,   TB_ALIGN_16 },
1262     { X86::PSIGNDrr128,     X86::PSIGNDrm128,   TB_ALIGN_16 },
1263     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1264     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1265     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1266     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1267     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1268     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1269     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1270     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1271     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1272     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1273     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1274     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1275     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1276     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1277     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1278     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1279     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1280     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1281     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1282     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1283     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1284     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1285     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1286     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1287     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1288     { X86::ROUNDSDr_Int,    X86::ROUNDSDm_Int,  TB_NO_REVERSE },
1289     { X86::ROUNDSSr_Int,    X86::ROUNDSSm_Int,  TB_NO_REVERSE },
1290     { X86::SBB32rr,         X86::SBB32rm,       0 },
1291     { X86::SBB64rr,         X86::SBB64rm,       0 },
1292     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1293     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1294     { X86::SUB16rr,         X86::SUB16rm,       0 },
1295     { X86::SUB32rr,         X86::SUB32rm,       0 },
1296     { X86::SUB64rr,         X86::SUB64rm,       0 },
1297     { X86::SUB8rr,          X86::SUB8rm,        0 },
1298     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1299     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1300     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1301     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   TB_NO_REVERSE },
1302     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1303     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   TB_NO_REVERSE },
1304     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1305     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1306     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1307     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1308     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1309     { X86::XOR16rr,         X86::XOR16rm,       0 },
1310     { X86::XOR32rr,         X86::XOR32rm,       0 },
1311     { X86::XOR64rr,         X86::XOR64rm,       0 },
1312     { X86::XOR8rr,          X86::XOR8rm,        0 },
1313     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1314     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1315 
1316     // MMX version of foldable instructions
1317     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1318     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1319     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1320     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1321     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1322     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1323     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1324     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1325     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1326     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1327     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1328     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1329     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1330     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1331     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1332     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1333     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1334     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1335     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1336     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1337     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1338     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1339     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1340     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1341     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1342     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1343     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1344     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1345     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1346     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1347     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1348     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1349     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1350     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1351     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1352     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1353     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1354     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1355     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1356     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1357     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1358     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1359     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1360     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1361     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1362     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1363     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1364     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1365     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1366     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1367     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1368     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1369     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1370     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1371     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1372     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1373     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1374     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1375     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1376     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1377     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1378     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1379     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1380     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1381     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1382     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1383     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1384     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1385     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1386     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1387 
1388     // 3DNow! version of foldable instructions
1389     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1390     { X86::PFACCrr,           X86::PFACCrm,           0 },
1391     { X86::PFADDrr,           X86::PFADDrm,           0 },
1392     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1393     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1394     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1395     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1396     { X86::PFMINrr,           X86::PFMINrm,           0 },
1397     { X86::PFMULrr,           X86::PFMULrm,           0 },
1398     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1399     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1400     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1401     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1402     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1403     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1404     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1405     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1406 
1407     // AVX 128-bit versions of foldable instructions
1408     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1409     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1410     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1411     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1412     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1413     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1414     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1415     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1416     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1417     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1418     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1419     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       TB_NO_REVERSE },
1420     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1421     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       TB_NO_REVERSE },
1422     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1423     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1424     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1425     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1426     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1427     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1428     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1429     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1430     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1431     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1432     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1433     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1434     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1435     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1436     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1437     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1438     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1439     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       TB_NO_REVERSE },
1440     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1441     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       TB_NO_REVERSE },
1442     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1443     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1444     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1445     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1446     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1447     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1448     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       TB_NO_REVERSE },
1449     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       TB_NO_REVERSE },
1450     { X86::VMAXCPDrr,         X86::VMAXCPDrm,          0 },
1451     { X86::VMAXCPSrr,         X86::VMAXCPSrm,          0 },
1452     { X86::VMAXCSDrr,         X86::VMAXCSDrm,          0 },
1453     { X86::VMAXCSSrr,         X86::VMAXCSSrm,          0 },
1454     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1455     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1456     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1457     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       TB_NO_REVERSE },
1458     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1459     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       TB_NO_REVERSE },
1460     { X86::VMINCPDrr,         X86::VMINCPDrm,          0 },
1461     { X86::VMINCPSrr,         X86::VMINCPSrm,          0 },
1462     { X86::VMINCSDrr,         X86::VMINCSDrm,          0 },
1463     { X86::VMINCSSrr,         X86::VMINCSSrm,          0 },
1464     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1465     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1466     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1467     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       TB_NO_REVERSE },
1468     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1469     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       TB_NO_REVERSE },
1470     { X86::VMOVLHPSrr,        X86::VMOVHPSrm,          TB_NO_REVERSE },
1471     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1472     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1473     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1474     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1475     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       TB_NO_REVERSE },
1476     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1477     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       TB_NO_REVERSE },
1478     { X86::VORPDrr,           X86::VORPDrm,            0 },
1479     { X86::VORPSrr,           X86::VORPSrm,            0 },
1480     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1481     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1482     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1483     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1484     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1485     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1486     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1487     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1488     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1489     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1490     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1491     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1492     { X86::VPALIGNRrri,       X86::VPALIGNRrmi,        0 },
1493     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1494     { X86::VPANDrr,           X86::VPANDrm,            0 },
1495     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1496     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1497     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1498     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1499     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1500     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1501     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1502     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1503     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1504     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1505     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1506     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1507     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1508     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1509     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1510     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1511     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1512     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1513     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1514     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1515     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1516     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1517     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1518     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1519     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1520     { X86::VPMADDUBSWrr,      X86::VPMADDUBSWrm,       0 },
1521     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1522     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1523     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1524     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1525     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1526     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1527     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1528     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1529     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1530     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1531     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1532     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1533     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1534     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1535     { X86::VPMULHRSWrr,       X86::VPMULHRSWrm,        0 },
1536     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1537     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1538     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1539     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1540     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1541     { X86::VPORrr,            X86::VPORrm,             0 },
1542     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1543     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1544     { X86::VPSIGNBrr128,      X86::VPSIGNBrm128,       0 },
1545     { X86::VPSIGNWrr128,      X86::VPSIGNWrm128,       0 },
1546     { X86::VPSIGNDrr128,      X86::VPSIGNDrm128,       0 },
1547     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1548     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1549     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1550     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1551     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1552     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1553     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1554     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1555     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1556     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1557     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1558     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1559     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1560     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1561     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1562     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1563     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1564     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1565     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1566     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1567     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1568     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1569     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1570     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1571     { X86::VPXORrr,           X86::VPXORrm,            0 },
1572     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1573     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        TB_NO_REVERSE },
1574     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1575     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      TB_NO_REVERSE },
1576     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1577     { X86::VROUNDSDr_Int,     X86::VROUNDSDm_Int,      TB_NO_REVERSE },
1578     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1579     { X86::VROUNDSSr_Int,     X86::VROUNDSSm_Int,      TB_NO_REVERSE },
1580     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1581     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1582     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1583     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       TB_NO_REVERSE },
1584     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1585     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       TB_NO_REVERSE },
1586     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1587     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1588     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1589     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       TB_NO_REVERSE },
1590     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1591     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       TB_NO_REVERSE },
1592     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1593     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1594     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1595     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1596     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1597     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1598 
1599     // AVX 256-bit foldable instructions
1600     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1601     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1602     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1603     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1604     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1605     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1606     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1607     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1608     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1609     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1610     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1611     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1612     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1613     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1614     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1615     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1616     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1617     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1618     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1619     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1620     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1621     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1622     { X86::VMAXCPDYrr,        X86::VMAXCPDYrm,         0 },
1623     { X86::VMAXCPSYrr,        X86::VMAXCPSYrm,         0 },
1624     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1625     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1626     { X86::VMINCPDYrr,        X86::VMINCPDYrm,         0 },
1627     { X86::VMINCPSYrr,        X86::VMINCPSYrm,         0 },
1628     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1629     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1630     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1631     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1632     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1633     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1634     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1635     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1636     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1637     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1638     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1639     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1640     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1641     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1642     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1643     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1644     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1645     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1646     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1647 
1648     // AVX2 foldable instructions
1649     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1650     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1651     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1652     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1653     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1654     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1655     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1656     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1657     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1658     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1659     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1660     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1661     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1662     { X86::VPALIGNRYrri,      X86::VPALIGNRYrmi,       0 },
1663     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1664     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1665     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1666     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1667     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1668     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1669     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1670     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1671     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1672     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1673     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1674     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1675     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1676     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1677     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1678     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1679     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1680     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1681     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1682     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1683     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1684     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1685     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1686     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1687     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1688     { X86::VPMADDUBSWYrr,     X86::VPMADDUBSWYrm,      0 },
1689     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1690     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1691     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1692     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1693     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1694     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1695     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1696     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1697     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1698     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1699     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1700     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1701     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1702     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1703     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1704     { X86::VPMULHRSWYrr,      X86::VPMULHRSWYrm,       0 },
1705     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1706     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1707     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1708     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1709     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1710     { X86::VPORYrr,           X86::VPORYrm,            0 },
1711     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1712     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1713     { X86::VPSIGNBYrr256,     X86::VPSIGNBYrm256,      0 },
1714     { X86::VPSIGNWYrr256,     X86::VPSIGNWYrm256,      0 },
1715     { X86::VPSIGNDYrr256,     X86::VPSIGNDYrm256,      0 },
1716     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1717     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1718     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1719     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1720     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1721     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1722     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1723     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1724     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1725     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1726     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1727     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1728     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1729     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1730     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1731     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1732     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1733     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1734     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1735     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1736     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1737     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1738     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1739     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1740     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1741     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1742     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1743     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1744     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1745     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1746     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1747     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1748     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1749     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1750     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1751 
1752     // FMA4 foldable patterns
1753     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1754     { X86::VFMADDSS4rr_Int,   X86::VFMADDSS4mr_Int,    TB_NO_REVERSE },
1755     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1756     { X86::VFMADDSD4rr_Int,   X86::VFMADDSD4mr_Int,    TB_NO_REVERSE },
1757     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1758     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1759     { X86::VFMADDPS4Yrr,      X86::VFMADDPS4Ymr,       TB_ALIGN_NONE },
1760     { X86::VFMADDPD4Yrr,      X86::VFMADDPD4Ymr,       TB_ALIGN_NONE },
1761     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1762     { X86::VFNMADDSS4rr_Int,  X86::VFNMADDSS4mr_Int,   TB_NO_REVERSE },
1763     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1764     { X86::VFNMADDSD4rr_Int,  X86::VFNMADDSD4mr_Int,   TB_NO_REVERSE },
1765     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1766     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1767     { X86::VFNMADDPS4Yrr,     X86::VFNMADDPS4Ymr,      TB_ALIGN_NONE },
1768     { X86::VFNMADDPD4Yrr,     X86::VFNMADDPD4Ymr,      TB_ALIGN_NONE },
1769     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1770     { X86::VFMSUBSS4rr_Int,   X86::VFMSUBSS4mr_Int,    TB_NO_REVERSE },
1771     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1772     { X86::VFMSUBSD4rr_Int,   X86::VFMSUBSD4mr_Int,    TB_NO_REVERSE },
1773     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1774     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1775     { X86::VFMSUBPS4Yrr,      X86::VFMSUBPS4Ymr,       TB_ALIGN_NONE },
1776     { X86::VFMSUBPD4Yrr,      X86::VFMSUBPD4Ymr,       TB_ALIGN_NONE },
1777     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1778     { X86::VFNMSUBSS4rr_Int,  X86::VFNMSUBSS4mr_Int,   TB_NO_REVERSE },
1779     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1780     { X86::VFNMSUBSD4rr_Int,  X86::VFNMSUBSD4mr_Int,   TB_NO_REVERSE },
1781     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1782     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1783     { X86::VFNMSUBPS4Yrr,     X86::VFNMSUBPS4Ymr,      TB_ALIGN_NONE },
1784     { X86::VFNMSUBPD4Yrr,     X86::VFNMSUBPD4Ymr,      TB_ALIGN_NONE },
1785     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1786     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1787     { X86::VFMADDSUBPS4Yrr,   X86::VFMADDSUBPS4Ymr,    TB_ALIGN_NONE },
1788     { X86::VFMADDSUBPD4Yrr,   X86::VFMADDSUBPD4Ymr,    TB_ALIGN_NONE },
1789     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1790     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1791     { X86::VFMSUBADDPS4Yrr,   X86::VFMSUBADDPS4Ymr,    TB_ALIGN_NONE },
1792     { X86::VFMSUBADDPD4Yrr,   X86::VFMSUBADDPD4Ymr,    TB_ALIGN_NONE },
1793 
1794     // XOP foldable instructions
1795     { X86::VPCMOVrrr,         X86::VPCMOVrmr,           0 },
1796     { X86::VPCMOVYrrr,        X86::VPCMOVYrmr,          0 },
1797     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1798     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1799     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1800     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1801     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1802     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1803     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1804     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1805     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1806     { X86::VPERMIL2PDYrr,     X86::VPERMIL2PDYmr,       0 },
1807     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1808     { X86::VPERMIL2PSYrr,     X86::VPERMIL2PSYmr,       0 },
1809     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1810     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1811     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1812     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1813     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1814     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1815     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1816     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1817     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1818     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1819     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1820     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1821     { X86::VPPERMrrr,         X86::VPPERMrmr,           0 },
1822     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1823     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1824     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1825     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1826     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1827     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1828     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1829     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1830     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1831     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1832     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1833     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1834 
1835     // BMI/BMI2 foldable instructions
1836     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1837     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1838     { X86::MULX32rr,          X86::MULX32rm,            0 },
1839     { X86::MULX64rr,          X86::MULX64rm,            0 },
1840     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1841     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1842     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1843     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1844 
1845     // ADX foldable instructions
1846     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1847     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1848     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1849     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1850 
1851     // AVX-512 foldable instructions
1852     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1853     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1854     { X86::VADDSDZrr,         X86::VADDSDZrm,           0 },
1855     { X86::VADDSDZrr_Int,     X86::VADDSDZrm_Int,       TB_NO_REVERSE },
1856     { X86::VADDSSZrr,         X86::VADDSSZrm,           0 },
1857     { X86::VADDSSZrr_Int,     X86::VADDSSZrm_Int,       TB_NO_REVERSE },
1858     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1859     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1860     { X86::VANDNPDZrr,        X86::VANDNPDZrm,          0 },
1861     { X86::VANDNPSZrr,        X86::VANDNPSZrm,          0 },
1862     { X86::VANDPDZrr,         X86::VANDPDZrm,           0 },
1863     { X86::VANDPSZrr,         X86::VANDPSZrm,           0 },
1864     { X86::VCMPPDZrri,        X86::VCMPPDZrmi,          0 },
1865     { X86::VCMPPSZrri,        X86::VCMPPSZrmi,          0 },
1866     { X86::VCMPSDZrr,         X86::VCMPSDZrm,           0 },
1867     { X86::VCMPSDZrr_Int,     X86::VCMPSDZrm_Int,       TB_NO_REVERSE },
1868     { X86::VCMPSSZrr,         X86::VCMPSSZrm,           0 },
1869     { X86::VCMPSSZrr_Int,     X86::VCMPSSZrm_Int,       TB_NO_REVERSE },
1870     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1871     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1872     { X86::VDIVSDZrr,         X86::VDIVSDZrm,           0 },
1873     { X86::VDIVSDZrr_Int,     X86::VDIVSDZrm_Int,       TB_NO_REVERSE },
1874     { X86::VDIVSSZrr,         X86::VDIVSSZrm,           0 },
1875     { X86::VDIVSSZrr_Int,     X86::VDIVSSZrm_Int,       TB_NO_REVERSE },
1876     { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrm,     0 },
1877     { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrm,     0 },
1878     { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrm,     0 },
1879     { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrm,     0 },
1880     { X86::VINSERTI32x4Zrr,   X86::VINSERTI32x4Zrm,     0 },
1881     { X86::VINSERTI32x8Zrr,   X86::VINSERTI32x8Zrm,     0 },
1882     { X86::VINSERTI64x2Zrr,   X86::VINSERTI64x2Zrm,     0 },
1883     { X86::VINSERTI64x4Zrr,   X86::VINSERTI64x4Zrm,     0 },
1884     { X86::VMAXCPDZrr,        X86::VMAXCPDZrm,          0 },
1885     { X86::VMAXCPSZrr,        X86::VMAXCPSZrm,          0 },
1886     { X86::VMAXCSDZrr,        X86::VMAXCSDZrm,          0 },
1887     { X86::VMAXCSSZrr,        X86::VMAXCSSZrm,          0 },
1888     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1889     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1890     { X86::VMAXSDZrr,         X86::VMAXSDZrm,           0 },
1891     { X86::VMAXSDZrr_Int,     X86::VMAXSDZrm_Int,       TB_NO_REVERSE },
1892     { X86::VMAXSSZrr,         X86::VMAXSSZrm,           0 },
1893     { X86::VMAXSSZrr_Int,     X86::VMAXSSZrm_Int,       TB_NO_REVERSE },
1894     { X86::VMINCPDZrr,        X86::VMINCPDZrm,          0 },
1895     { X86::VMINCPSZrr,        X86::VMINCPSZrm,          0 },
1896     { X86::VMINCSDZrr,        X86::VMINCSDZrm,          0 },
1897     { X86::VMINCSSZrr,        X86::VMINCSSZrm,          0 },
1898     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1899     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1900     { X86::VMINSDZrr,         X86::VMINSDZrm,           0 },
1901     { X86::VMINSDZrr_Int,     X86::VMINSDZrm_Int,       TB_NO_REVERSE },
1902     { X86::VMINSSZrr,         X86::VMINSSZrm,           0 },
1903     { X86::VMINSSZrr_Int,     X86::VMINSSZrm_Int,       TB_NO_REVERSE },
1904     { X86::VMOVLHPSZrr,       X86::VMOVHPSZ128rm,       TB_NO_REVERSE },
1905     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1906     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1907     { X86::VMULSDZrr,         X86::VMULSDZrm,           0 },
1908     { X86::VMULSDZrr_Int,     X86::VMULSDZrm_Int,       TB_NO_REVERSE },
1909     { X86::VMULSSZrr,         X86::VMULSSZrm,           0 },
1910     { X86::VMULSSZrr_Int,     X86::VMULSSZrm_Int,       TB_NO_REVERSE },
1911     { X86::VORPDZrr,          X86::VORPDZrm,            0 },
1912     { X86::VORPSZrr,          X86::VORPSZrm,            0 },
1913     { X86::VPACKSSDWZrr,      X86::VPACKSSDWZrm,        0 },
1914     { X86::VPACKSSWBZrr,      X86::VPACKSSWBZrm,        0 },
1915     { X86::VPACKUSDWZrr,      X86::VPACKUSDWZrm,        0 },
1916     { X86::VPACKUSWBZrr,      X86::VPACKUSWBZrm,        0 },
1917     { X86::VPADDBZrr,         X86::VPADDBZrm,           0 },
1918     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1919     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1920     { X86::VPADDSBZrr,        X86::VPADDSBZrm,          0 },
1921     { X86::VPADDSWZrr,        X86::VPADDSWZrm,          0 },
1922     { X86::VPADDUSBZrr,       X86::VPADDUSBZrm,         0 },
1923     { X86::VPADDUSWZrr,       X86::VPADDUSWZrm,         0 },
1924     { X86::VPADDWZrr,         X86::VPADDWZrm,           0 },
1925     { X86::VPALIGNRZrri,      X86::VPALIGNRZrmi,        0 },
1926     { X86::VPANDDZrr,         X86::VPANDDZrm,           0 },
1927     { X86::VPANDNDZrr,        X86::VPANDNDZrm,          0 },
1928     { X86::VPANDNQZrr,        X86::VPANDNQZrm,          0 },
1929     { X86::VPANDQZrr,         X86::VPANDQZrm,           0 },
1930     { X86::VPAVGBZrr,         X86::VPAVGBZrm,           0 },
1931     { X86::VPAVGWZrr,         X86::VPAVGWZrm,           0 },
1932     { X86::VPCMPBZrri,        X86::VPCMPBZrmi,          0 },
1933     { X86::VPCMPDZrri,        X86::VPCMPDZrmi,          0 },
1934     { X86::VPCMPEQBZrr,       X86::VPCMPEQBZrm,         0 },
1935     { X86::VPCMPEQDZrr,       X86::VPCMPEQDZrm,         0 },
1936     { X86::VPCMPEQQZrr,       X86::VPCMPEQQZrm,         0 },
1937     { X86::VPCMPEQWZrr,       X86::VPCMPEQWZrm,         0 },
1938     { X86::VPCMPGTBZrr,       X86::VPCMPGTBZrm,         0 },
1939     { X86::VPCMPGTDZrr,       X86::VPCMPGTDZrm,         0 },
1940     { X86::VPCMPGTQZrr,       X86::VPCMPGTQZrm,         0 },
1941     { X86::VPCMPGTWZrr,       X86::VPCMPGTWZrm,         0 },
1942     { X86::VPCMPQZrri,        X86::VPCMPQZrmi,          0 },
1943     { X86::VPCMPUBZrri,       X86::VPCMPUBZrmi,         0 },
1944     { X86::VPCMPUDZrri,       X86::VPCMPUDZrmi,         0 },
1945     { X86::VPCMPUQZrri,       X86::VPCMPUQZrmi,         0 },
1946     { X86::VPCMPUWZrri,       X86::VPCMPUWZrmi,         0 },
1947     { X86::VPCMPWZrri,        X86::VPCMPWZrmi,          0 },
1948     { X86::VPERMBZrr,         X86::VPERMBZrm,           0 },
1949     { X86::VPERMDZrr,         X86::VPERMDZrm,           0 },
1950     { X86::VPERMILPDZrr,      X86::VPERMILPDZrm,        0 },
1951     { X86::VPERMILPSZrr,      X86::VPERMILPSZrm,        0 },
1952     { X86::VPERMPDZrr,        X86::VPERMPDZrm,          0 },
1953     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1954     { X86::VPERMQZrr,         X86::VPERMQZrm,           0 },
1955     { X86::VPERMWZrr,         X86::VPERMWZrm,           0 },
1956     { X86::VPINSRBZrr,        X86::VPINSRBZrm,          0 },
1957     { X86::VPINSRDZrr,        X86::VPINSRDZrm,          0 },
1958     { X86::VPINSRQZrr,        X86::VPINSRQZrm,          0 },
1959     { X86::VPINSRWZrr,        X86::VPINSRWZrm,          0 },
1960     { X86::VPMADDUBSWZrr,     X86::VPMADDUBSWZrm,       0 },
1961     { X86::VPMADDWDZrr,       X86::VPMADDWDZrm,         0 },
1962     { X86::VPMAXSBZrr,        X86::VPMAXSBZrm,          0 },
1963     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1964     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1965     { X86::VPMAXSWZrr,        X86::VPMAXSWZrm,          0 },
1966     { X86::VPMAXUBZrr,        X86::VPMAXUBZrm,          0 },
1967     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1968     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1969     { X86::VPMAXUWZrr,        X86::VPMAXUWZrm,          0 },
1970     { X86::VPMINSBZrr,        X86::VPMINSBZrm,          0 },
1971     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1972     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1973     { X86::VPMINSWZrr,        X86::VPMINSWZrm,          0 },
1974     { X86::VPMINUBZrr,        X86::VPMINUBZrm,          0 },
1975     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1976     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1977     { X86::VPMINUWZrr,        X86::VPMINUWZrm,          0 },
1978     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1979     { X86::VPMULLDZrr,        X86::VPMULLDZrm,          0 },
1980     { X86::VPMULLQZrr,        X86::VPMULLQZrm,          0 },
1981     { X86::VPMULLWZrr,        X86::VPMULLWZrm,          0 },
1982     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1983     { X86::VPORDZrr,          X86::VPORDZrm,            0 },
1984     { X86::VPORQZrr,          X86::VPORQZrm,            0 },
1985     { X86::VPSADBWZ512rr,     X86::VPSADBWZ512rm,       0 },
1986     { X86::VPSHUFBZrr,        X86::VPSHUFBZrm,          0 },
1987     { X86::VPSLLDZrr,         X86::VPSLLDZrm,           0 },
1988     { X86::VPSLLQZrr,         X86::VPSLLQZrm,           0 },
1989     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1990     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1991     { X86::VPSLLVWZrr,        X86::VPSLLVWZrm,          0 },
1992     { X86::VPSLLWZrr,         X86::VPSLLWZrm,           0 },
1993     { X86::VPSRADZrr,         X86::VPSRADZrm,           0 },
1994     { X86::VPSRAQZrr,         X86::VPSRAQZrm,           0 },
1995     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1996     { X86::VPSRAVQZrr,        X86::VPSRAVQZrm,          0 },
1997     { X86::VPSRAVWZrr,        X86::VPSRAVWZrm,          0 },
1998     { X86::VPSRAWZrr,         X86::VPSRAWZrm,           0 },
1999     { X86::VPSRLDZrr,         X86::VPSRLDZrm,           0 },
2000     { X86::VPSRLQZrr,         X86::VPSRLQZrm,           0 },
2001     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
2002     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
2003     { X86::VPSRLVWZrr,        X86::VPSRLVWZrm,          0 },
2004     { X86::VPSRLWZrr,         X86::VPSRLWZrm,           0 },
2005     { X86::VPSUBBZrr,         X86::VPSUBBZrm,           0 },
2006     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
2007     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
2008     { X86::VPSUBSBZrr,        X86::VPSUBSBZrm,          0 },
2009     { X86::VPSUBSWZrr,        X86::VPSUBSWZrm,          0 },
2010     { X86::VPSUBUSBZrr,       X86::VPSUBUSBZrm,         0 },
2011     { X86::VPSUBUSWZrr,       X86::VPSUBUSWZrm,         0 },
2012     { X86::VPSUBWZrr,         X86::VPSUBWZrm,           0 },
2013     { X86::VPUNPCKHBWZrr,     X86::VPUNPCKHBWZrm,       0 },
2014     { X86::VPUNPCKHDQZrr,     X86::VPUNPCKHDQZrm,       0 },
2015     { X86::VPUNPCKHQDQZrr,    X86::VPUNPCKHQDQZrm,      0 },
2016     { X86::VPUNPCKHWDZrr,     X86::VPUNPCKHWDZrm,       0 },
2017     { X86::VPUNPCKLBWZrr,     X86::VPUNPCKLBWZrm,       0 },
2018     { X86::VPUNPCKLDQZrr,     X86::VPUNPCKLDQZrm,       0 },
2019     { X86::VPUNPCKLQDQZrr,    X86::VPUNPCKLQDQZrm,      0 },
2020     { X86::VPUNPCKLWDZrr,     X86::VPUNPCKLWDZrm,       0 },
2021     { X86::VPXORDZrr,         X86::VPXORDZrm,           0 },
2022     { X86::VPXORQZrr,         X86::VPXORQZrm,           0 },
2023     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
2024     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
2025     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
2026     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
2027     { X86::VSUBSDZrr,         X86::VSUBSDZrm,           0 },
2028     { X86::VSUBSDZrr_Int,     X86::VSUBSDZrm_Int,       TB_NO_REVERSE },
2029     { X86::VSUBSSZrr,         X86::VSUBSSZrm,           0 },
2030     { X86::VSUBSSZrr_Int,     X86::VSUBSSZrm_Int,       TB_NO_REVERSE },
2031     { X86::VUNPCKHPDZrr,      X86::VUNPCKHPDZrm,        0 },
2032     { X86::VUNPCKHPSZrr,      X86::VUNPCKHPSZrm,        0 },
2033     { X86::VUNPCKLPDZrr,      X86::VUNPCKLPDZrm,        0 },
2034     { X86::VUNPCKLPSZrr,      X86::VUNPCKLPSZrm,        0 },
2035     { X86::VXORPDZrr,         X86::VXORPDZrm,           0 },
2036     { X86::VXORPSZrr,         X86::VXORPSZrm,           0 },
2037 
2038     // AVX-512{F,VL} foldable instructions
2039     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
2040     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
2041     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
2042     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
2043     { X86::VALIGNDZ128rri,    X86::VALIGNDZ128rmi,      0 },
2044     { X86::VALIGNDZ256rri,    X86::VALIGNDZ256rmi,      0 },
2045     { X86::VALIGNQZ128rri,    X86::VALIGNQZ128rmi,      0 },
2046     { X86::VALIGNQZ256rri,    X86::VALIGNQZ256rmi,      0 },
2047     { X86::VANDNPDZ128rr,     X86::VANDNPDZ128rm,       0 },
2048     { X86::VANDNPDZ256rr,     X86::VANDNPDZ256rm,       0 },
2049     { X86::VANDNPSZ128rr,     X86::VANDNPSZ128rm,       0 },
2050     { X86::VANDNPSZ256rr,     X86::VANDNPSZ256rm,       0 },
2051     { X86::VANDPDZ128rr,      X86::VANDPDZ128rm,        0 },
2052     { X86::VANDPDZ256rr,      X86::VANDPDZ256rm,        0 },
2053     { X86::VANDPSZ128rr,      X86::VANDPSZ128rm,        0 },
2054     { X86::VANDPSZ256rr,      X86::VANDPSZ256rm,        0 },
2055     { X86::VCMPPDZ128rri,     X86::VCMPPDZ128rmi,       0 },
2056     { X86::VCMPPDZ256rri,     X86::VCMPPDZ256rmi,       0 },
2057     { X86::VCMPPSZ128rri,     X86::VCMPPSZ128rmi,       0 },
2058     { X86::VCMPPSZ256rri,     X86::VCMPPSZ256rmi,       0 },
2059     { X86::VDIVPDZ128rr,      X86::VDIVPDZ128rm,        0 },
2060     { X86::VDIVPDZ256rr,      X86::VDIVPDZ256rm,        0 },
2061     { X86::VDIVPSZ128rr,      X86::VDIVPSZ128rm,        0 },
2062     { X86::VDIVPSZ256rr,      X86::VDIVPSZ256rm,        0 },
2063     { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rm,  0 },
2064     { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rm,  0 },
2065     { X86::VINSERTI32x4Z256rr,X86::VINSERTI32x4Z256rm,  0 },
2066     { X86::VINSERTI64x2Z256rr,X86::VINSERTI64x2Z256rm,  0 },
2067     { X86::VMAXCPDZ128rr,     X86::VMAXCPDZ128rm,       0 },
2068     { X86::VMAXCPDZ256rr,     X86::VMAXCPDZ256rm,       0 },
2069     { X86::VMAXCPSZ128rr,     X86::VMAXCPSZ128rm,       0 },
2070     { X86::VMAXCPSZ256rr,     X86::VMAXCPSZ256rm,       0 },
2071     { X86::VMAXPDZ128rr,      X86::VMAXPDZ128rm,        0 },
2072     { X86::VMAXPDZ256rr,      X86::VMAXPDZ256rm,        0 },
2073     { X86::VMAXPSZ128rr,      X86::VMAXPSZ128rm,        0 },
2074     { X86::VMAXPSZ256rr,      X86::VMAXPSZ256rm,        0 },
2075     { X86::VMINCPDZ128rr,     X86::VMINCPDZ128rm,       0 },
2076     { X86::VMINCPDZ256rr,     X86::VMINCPDZ256rm,       0 },
2077     { X86::VMINCPSZ128rr,     X86::VMINCPSZ128rm,       0 },
2078     { X86::VMINCPSZ256rr,     X86::VMINCPSZ256rm,       0 },
2079     { X86::VMINPDZ128rr,      X86::VMINPDZ128rm,        0 },
2080     { X86::VMINPDZ256rr,      X86::VMINPDZ256rm,        0 },
2081     { X86::VMINPSZ128rr,      X86::VMINPSZ128rm,        0 },
2082     { X86::VMINPSZ256rr,      X86::VMINPSZ256rm,        0 },
2083     { X86::VMULPDZ128rr,      X86::VMULPDZ128rm,        0 },
2084     { X86::VMULPDZ256rr,      X86::VMULPDZ256rm,        0 },
2085     { X86::VMULPSZ128rr,      X86::VMULPSZ128rm,        0 },
2086     { X86::VMULPSZ256rr,      X86::VMULPSZ256rm,        0 },
2087     { X86::VORPDZ128rr,       X86::VORPDZ128rm,         0 },
2088     { X86::VORPDZ256rr,       X86::VORPDZ256rm,         0 },
2089     { X86::VORPSZ128rr,       X86::VORPSZ128rm,         0 },
2090     { X86::VORPSZ256rr,       X86::VORPSZ256rm,         0 },
2091     { X86::VPACKSSDWZ256rr,   X86::VPACKSSDWZ256rm,     0 },
2092     { X86::VPACKSSDWZ128rr,   X86::VPACKSSDWZ128rm,     0 },
2093     { X86::VPACKSSWBZ256rr,   X86::VPACKSSWBZ256rm,     0 },
2094     { X86::VPACKSSWBZ128rr,   X86::VPACKSSWBZ128rm,     0 },
2095     { X86::VPACKUSDWZ256rr,   X86::VPACKUSDWZ256rm,     0 },
2096     { X86::VPACKUSDWZ128rr,   X86::VPACKUSDWZ128rm,     0 },
2097     { X86::VPACKUSWBZ256rr,   X86::VPACKUSWBZ256rm,     0 },
2098     { X86::VPACKUSWBZ128rr,   X86::VPACKUSWBZ128rm,     0 },
2099     { X86::VPADDBZ128rr,      X86::VPADDBZ128rm,        0 },
2100     { X86::VPADDBZ256rr,      X86::VPADDBZ256rm,        0 },
2101     { X86::VPADDDZ128rr,      X86::VPADDDZ128rm,        0 },
2102     { X86::VPADDDZ256rr,      X86::VPADDDZ256rm,        0 },
2103     { X86::VPADDQZ128rr,      X86::VPADDQZ128rm,        0 },
2104     { X86::VPADDQZ256rr,      X86::VPADDQZ256rm,        0 },
2105     { X86::VPADDSBZ128rr,     X86::VPADDSBZ128rm,       0 },
2106     { X86::VPADDSBZ256rr,     X86::VPADDSBZ256rm,       0 },
2107     { X86::VPADDSWZ128rr,     X86::VPADDSWZ128rm,       0 },
2108     { X86::VPADDSWZ256rr,     X86::VPADDSWZ256rm,       0 },
2109     { X86::VPADDUSBZ128rr,    X86::VPADDUSBZ128rm,      0 },
2110     { X86::VPADDUSBZ256rr,    X86::VPADDUSBZ256rm,      0 },
2111     { X86::VPADDUSWZ128rr,    X86::VPADDUSWZ128rm,      0 },
2112     { X86::VPADDUSWZ256rr,    X86::VPADDUSWZ256rm,      0 },
2113     { X86::VPADDWZ128rr,      X86::VPADDWZ128rm,        0 },
2114     { X86::VPADDWZ256rr,      X86::VPADDWZ256rm,        0 },
2115     { X86::VPALIGNRZ128rri,   X86::VPALIGNRZ128rmi,     0 },
2116     { X86::VPALIGNRZ256rri,   X86::VPALIGNRZ256rmi,     0 },
2117     { X86::VPANDDZ128rr,      X86::VPANDDZ128rm,        0 },
2118     { X86::VPANDDZ256rr,      X86::VPANDDZ256rm,        0 },
2119     { X86::VPANDNDZ128rr,     X86::VPANDNDZ128rm,       0 },
2120     { X86::VPANDNDZ256rr,     X86::VPANDNDZ256rm,       0 },
2121     { X86::VPANDNQZ128rr,     X86::VPANDNQZ128rm,       0 },
2122     { X86::VPANDNQZ256rr,     X86::VPANDNQZ256rm,       0 },
2123     { X86::VPANDQZ128rr,      X86::VPANDQZ128rm,        0 },
2124     { X86::VPANDQZ256rr,      X86::VPANDQZ256rm,        0 },
2125     { X86::VPAVGBZ128rr,      X86::VPAVGBZ128rm,        0 },
2126     { X86::VPAVGBZ256rr,      X86::VPAVGBZ256rm,        0 },
2127     { X86::VPAVGWZ128rr,      X86::VPAVGWZ128rm,        0 },
2128     { X86::VPAVGWZ256rr,      X86::VPAVGWZ256rm,        0 },
2129     { X86::VPCMPBZ128rri,     X86::VPCMPBZ128rmi,       0 },
2130     { X86::VPCMPBZ256rri,     X86::VPCMPBZ256rmi,       0 },
2131     { X86::VPCMPDZ128rri,     X86::VPCMPDZ128rmi,       0 },
2132     { X86::VPCMPDZ256rri,     X86::VPCMPDZ256rmi,       0 },
2133     { X86::VPCMPEQBZ128rr,    X86::VPCMPEQBZ128rm,      0 },
2134     { X86::VPCMPEQBZ256rr,    X86::VPCMPEQBZ256rm,      0 },
2135     { X86::VPCMPEQDZ128rr,    X86::VPCMPEQDZ128rm,      0 },
2136     { X86::VPCMPEQDZ256rr,    X86::VPCMPEQDZ256rm,      0 },
2137     { X86::VPCMPEQQZ128rr,    X86::VPCMPEQQZ128rm,      0 },
2138     { X86::VPCMPEQQZ256rr,    X86::VPCMPEQQZ256rm,      0 },
2139     { X86::VPCMPEQWZ128rr,    X86::VPCMPEQWZ128rm,      0 },
2140     { X86::VPCMPEQWZ256rr,    X86::VPCMPEQWZ256rm,      0 },
2141     { X86::VPCMPGTBZ128rr,    X86::VPCMPGTBZ128rm,      0 },
2142     { X86::VPCMPGTBZ256rr,    X86::VPCMPGTBZ256rm,      0 },
2143     { X86::VPCMPGTDZ128rr,    X86::VPCMPGTDZ128rm,      0 },
2144     { X86::VPCMPGTDZ256rr,    X86::VPCMPGTDZ256rm,      0 },
2145     { X86::VPCMPGTQZ128rr,    X86::VPCMPGTQZ128rm,      0 },
2146     { X86::VPCMPGTQZ256rr,    X86::VPCMPGTQZ256rm,      0 },
2147     { X86::VPCMPGTWZ128rr,    X86::VPCMPGTWZ128rm,      0 },
2148     { X86::VPCMPGTWZ256rr,    X86::VPCMPGTWZ256rm,      0 },
2149     { X86::VPCMPQZ128rri,     X86::VPCMPQZ128rmi,       0 },
2150     { X86::VPCMPQZ256rri,     X86::VPCMPQZ256rmi,       0 },
2151     { X86::VPCMPUBZ128rri,    X86::VPCMPUBZ128rmi,      0 },
2152     { X86::VPCMPUBZ256rri,    X86::VPCMPUBZ256rmi,      0 },
2153     { X86::VPCMPUDZ128rri,    X86::VPCMPUDZ128rmi,      0 },
2154     { X86::VPCMPUDZ256rri,    X86::VPCMPUDZ256rmi,      0 },
2155     { X86::VPCMPUQZ128rri,    X86::VPCMPUQZ128rmi,      0 },
2156     { X86::VPCMPUQZ256rri,    X86::VPCMPUQZ256rmi,      0 },
2157     { X86::VPCMPUWZ128rri,    X86::VPCMPUWZ128rmi,      0 },
2158     { X86::VPCMPUWZ256rri,    X86::VPCMPUWZ256rmi,      0 },
2159     { X86::VPCMPWZ128rri,     X86::VPCMPWZ128rmi,       0 },
2160     { X86::VPCMPWZ256rri,     X86::VPCMPWZ256rmi,       0 },
2161     { X86::VPERMBZ128rr,      X86::VPERMBZ128rm,        0 },
2162     { X86::VPERMBZ256rr,      X86::VPERMBZ256rm,        0 },
2163     { X86::VPERMDZ256rr,      X86::VPERMDZ256rm,        0 },
2164     { X86::VPERMILPDZ128rr,   X86::VPERMILPDZ128rm,     0 },
2165     { X86::VPERMILPDZ256rr,   X86::VPERMILPDZ256rm,     0 },
2166     { X86::VPERMILPSZ128rr,   X86::VPERMILPSZ128rm,     0 },
2167     { X86::VPERMILPSZ256rr,   X86::VPERMILPSZ256rm,     0 },
2168     { X86::VPERMPDZ256rr,     X86::VPERMPDZ256rm,       0 },
2169     { X86::VPERMPSZ256rr,     X86::VPERMPSZ256rm,       0 },
2170     { X86::VPERMQZ256rr,      X86::VPERMQZ256rm,        0 },
2171     { X86::VPERMWZ128rr,      X86::VPERMWZ128rm,        0 },
2172     { X86::VPERMWZ256rr,      X86::VPERMWZ256rm,        0 },
2173     { X86::VPMADDUBSWZ128rr,  X86::VPMADDUBSWZ128rm,    0 },
2174     { X86::VPMADDUBSWZ256rr,  X86::VPMADDUBSWZ256rm,    0 },
2175     { X86::VPMADDWDZ128rr,    X86::VPMADDWDZ128rm,      0 },
2176     { X86::VPMADDWDZ256rr,    X86::VPMADDWDZ256rm,      0 },
2177     { X86::VPMAXSBZ128rr,     X86::VPMAXSBZ128rm,       0 },
2178     { X86::VPMAXSBZ256rr,     X86::VPMAXSBZ256rm,       0 },
2179     { X86::VPMAXSDZ128rr,     X86::VPMAXSDZ128rm,       0 },
2180     { X86::VPMAXSDZ256rr,     X86::VPMAXSDZ256rm,       0 },
2181     { X86::VPMAXSQZ128rr,     X86::VPMAXSQZ128rm,       0 },
2182     { X86::VPMAXSQZ256rr,     X86::VPMAXSQZ256rm,       0 },
2183     { X86::VPMAXSWZ128rr,     X86::VPMAXSWZ128rm,       0 },
2184     { X86::VPMAXSWZ256rr,     X86::VPMAXSWZ256rm,       0 },
2185     { X86::VPMAXUBZ128rr,     X86::VPMAXUBZ128rm,       0 },
2186     { X86::VPMAXUBZ256rr,     X86::VPMAXUBZ256rm,       0 },
2187     { X86::VPMAXUDZ128rr,     X86::VPMAXUDZ128rm,       0 },
2188     { X86::VPMAXUDZ256rr,     X86::VPMAXUDZ256rm,       0 },
2189     { X86::VPMAXUQZ128rr,     X86::VPMAXUQZ128rm,       0 },
2190     { X86::VPMAXUQZ256rr,     X86::VPMAXUQZ256rm,       0 },
2191     { X86::VPMAXUWZ128rr,     X86::VPMAXUWZ128rm,       0 },
2192     { X86::VPMAXUWZ256rr,     X86::VPMAXUWZ256rm,       0 },
2193     { X86::VPMINSBZ128rr,     X86::VPMINSBZ128rm,       0 },
2194     { X86::VPMINSBZ256rr,     X86::VPMINSBZ256rm,       0 },
2195     { X86::VPMINSDZ128rr,     X86::VPMINSDZ128rm,       0 },
2196     { X86::VPMINSDZ256rr,     X86::VPMINSDZ256rm,       0 },
2197     { X86::VPMINSQZ128rr,     X86::VPMINSQZ128rm,       0 },
2198     { X86::VPMINSQZ256rr,     X86::VPMINSQZ256rm,       0 },
2199     { X86::VPMINSWZ128rr,     X86::VPMINSWZ128rm,       0 },
2200     { X86::VPMINSWZ256rr,     X86::VPMINSWZ256rm,       0 },
2201     { X86::VPMINUBZ128rr,     X86::VPMINUBZ128rm,       0 },
2202     { X86::VPMINUBZ256rr,     X86::VPMINUBZ256rm,       0 },
2203     { X86::VPMINUDZ128rr,     X86::VPMINUDZ128rm,       0 },
2204     { X86::VPMINUDZ256rr,     X86::VPMINUDZ256rm,       0 },
2205     { X86::VPMINUQZ128rr,     X86::VPMINUQZ128rm,       0 },
2206     { X86::VPMINUQZ256rr,     X86::VPMINUQZ256rm,       0 },
2207     { X86::VPMINUWZ128rr,     X86::VPMINUWZ128rm,       0 },
2208     { X86::VPMINUWZ256rr,     X86::VPMINUWZ256rm,       0 },
2209     { X86::VPMULDQZ128rr,     X86::VPMULDQZ128rm,       0 },
2210     { X86::VPMULDQZ256rr,     X86::VPMULDQZ256rm,       0 },
2211     { X86::VPMULLDZ128rr,     X86::VPMULLDZ128rm,       0 },
2212     { X86::VPMULLDZ256rr,     X86::VPMULLDZ256rm,       0 },
2213     { X86::VPMULLQZ128rr,     X86::VPMULLQZ128rm,       0 },
2214     { X86::VPMULLQZ256rr,     X86::VPMULLQZ256rm,       0 },
2215     { X86::VPMULLWZ128rr,     X86::VPMULLWZ128rm,       0 },
2216     { X86::VPMULLWZ256rr,     X86::VPMULLWZ256rm,       0 },
2217     { X86::VPMULUDQZ128rr,    X86::VPMULUDQZ128rm,      0 },
2218     { X86::VPMULUDQZ256rr,    X86::VPMULUDQZ256rm,      0 },
2219     { X86::VPORDZ128rr,       X86::VPORDZ128rm,         0 },
2220     { X86::VPORDZ256rr,       X86::VPORDZ256rm,         0 },
2221     { X86::VPORQZ128rr,       X86::VPORQZ128rm,         0 },
2222     { X86::VPORQZ256rr,       X86::VPORQZ256rm,         0 },
2223     { X86::VPSADBWZ128rr,     X86::VPSADBWZ128rm,       0 },
2224     { X86::VPSADBWZ256rr,     X86::VPSADBWZ256rm,       0 },
2225     { X86::VPSHUFBZ128rr,     X86::VPSHUFBZ128rm,       0 },
2226     { X86::VPSHUFBZ256rr,     X86::VPSHUFBZ256rm,       0 },
2227     { X86::VPSLLDZ128rr,      X86::VPSLLDZ128rm,        0 },
2228     { X86::VPSLLDZ256rr,      X86::VPSLLDZ256rm,        0 },
2229     { X86::VPSLLQZ128rr,      X86::VPSLLQZ128rm,        0 },
2230     { X86::VPSLLQZ256rr,      X86::VPSLLQZ256rm,        0 },
2231     { X86::VPSLLVDZ128rr,     X86::VPSLLVDZ128rm,       0 },
2232     { X86::VPSLLVDZ256rr,     X86::VPSLLVDZ256rm,       0 },
2233     { X86::VPSLLVQZ128rr,     X86::VPSLLVQZ128rm,       0 },
2234     { X86::VPSLLVQZ256rr,     X86::VPSLLVQZ256rm,       0 },
2235     { X86::VPSLLVWZ128rr,     X86::VPSLLVWZ128rm,       0 },
2236     { X86::VPSLLVWZ256rr,     X86::VPSLLVWZ256rm,       0 },
2237     { X86::VPSLLWZ128rr,      X86::VPSLLWZ128rm,        0 },
2238     { X86::VPSLLWZ256rr,      X86::VPSLLWZ256rm,        0 },
2239     { X86::VPSRADZ128rr,      X86::VPSRADZ128rm,        0 },
2240     { X86::VPSRADZ256rr,      X86::VPSRADZ256rm,        0 },
2241     { X86::VPSRAQZ128rr,      X86::VPSRAQZ128rm,        0 },
2242     { X86::VPSRAQZ256rr,      X86::VPSRAQZ256rm,        0 },
2243     { X86::VPSRAVDZ128rr,     X86::VPSRAVDZ128rm,       0 },
2244     { X86::VPSRAVDZ256rr,     X86::VPSRAVDZ256rm,       0 },
2245     { X86::VPSRAVQZ128rr,     X86::VPSRAVQZ128rm,       0 },
2246     { X86::VPSRAVQZ256rr,     X86::VPSRAVQZ256rm,       0 },
2247     { X86::VPSRAVWZ128rr,     X86::VPSRAVWZ128rm,       0 },
2248     { X86::VPSRAVWZ256rr,     X86::VPSRAVWZ256rm,       0 },
2249     { X86::VPSRAWZ128rr,      X86::VPSRAWZ128rm,        0 },
2250     { X86::VPSRAWZ256rr,      X86::VPSRAWZ256rm,        0 },
2251     { X86::VPSRLDZ128rr,      X86::VPSRLDZ128rm,        0 },
2252     { X86::VPSRLDZ256rr,      X86::VPSRLDZ256rm,        0 },
2253     { X86::VPSRLQZ128rr,      X86::VPSRLQZ128rm,        0 },
2254     { X86::VPSRLQZ256rr,      X86::VPSRLQZ256rm,        0 },
2255     { X86::VPSRLVDZ128rr,     X86::VPSRLVDZ128rm,       0 },
2256     { X86::VPSRLVDZ256rr,     X86::VPSRLVDZ256rm,       0 },
2257     { X86::VPSRLVQZ128rr,     X86::VPSRLVQZ128rm,       0 },
2258     { X86::VPSRLVQZ256rr,     X86::VPSRLVQZ256rm,       0 },
2259     { X86::VPSRLVWZ128rr,     X86::VPSRLVWZ128rm,       0 },
2260     { X86::VPSRLVWZ256rr,     X86::VPSRLVWZ256rm,       0 },
2261     { X86::VPSRLWZ128rr,      X86::VPSRLWZ128rm,        0 },
2262     { X86::VPSRLWZ256rr,      X86::VPSRLWZ256rm,        0 },
2263     { X86::VPSUBBZ128rr,      X86::VPSUBBZ128rm,        0 },
2264     { X86::VPSUBBZ256rr,      X86::VPSUBBZ256rm,        0 },
2265     { X86::VPSUBDZ128rr,      X86::VPSUBDZ128rm,        0 },
2266     { X86::VPSUBDZ256rr,      X86::VPSUBDZ256rm,        0 },
2267     { X86::VPSUBQZ128rr,      X86::VPSUBQZ128rm,        0 },
2268     { X86::VPSUBQZ256rr,      X86::VPSUBQZ256rm,        0 },
2269     { X86::VPSUBSBZ128rr,     X86::VPSUBSBZ128rm,       0 },
2270     { X86::VPSUBSBZ256rr,     X86::VPSUBSBZ256rm,       0 },
2271     { X86::VPSUBSWZ128rr,     X86::VPSUBSWZ128rm,       0 },
2272     { X86::VPSUBSWZ256rr,     X86::VPSUBSWZ256rm,       0 },
2273     { X86::VPSUBUSBZ128rr,    X86::VPSUBUSBZ128rm,      0 },
2274     { X86::VPSUBUSBZ256rr,    X86::VPSUBUSBZ256rm,      0 },
2275     { X86::VPSUBUSWZ128rr,    X86::VPSUBUSWZ128rm,      0 },
2276     { X86::VPSUBUSWZ256rr,    X86::VPSUBUSWZ256rm,      0 },
2277     { X86::VPSUBWZ128rr,      X86::VPSUBWZ128rm,        0 },
2278     { X86::VPSUBWZ256rr,      X86::VPSUBWZ256rm,        0 },
2279     { X86::VPUNPCKHBWZ128rr,  X86::VPUNPCKHBWZ128rm,    0 },
2280     { X86::VPUNPCKHBWZ256rr,  X86::VPUNPCKHBWZ256rm,    0 },
2281     { X86::VPUNPCKHDQZ128rr,  X86::VPUNPCKHDQZ128rm,    0 },
2282     { X86::VPUNPCKHDQZ256rr,  X86::VPUNPCKHDQZ256rm,    0 },
2283     { X86::VPUNPCKHQDQZ128rr, X86::VPUNPCKHQDQZ128rm,   0 },
2284     { X86::VPUNPCKHQDQZ256rr, X86::VPUNPCKHQDQZ256rm,   0 },
2285     { X86::VPUNPCKHWDZ128rr,  X86::VPUNPCKHWDZ128rm,    0 },
2286     { X86::VPUNPCKHWDZ256rr,  X86::VPUNPCKHWDZ256rm,    0 },
2287     { X86::VPUNPCKLBWZ128rr,  X86::VPUNPCKLBWZ128rm,    0 },
2288     { X86::VPUNPCKLBWZ256rr,  X86::VPUNPCKLBWZ256rm,    0 },
2289     { X86::VPUNPCKLDQZ128rr,  X86::VPUNPCKLDQZ128rm,    0 },
2290     { X86::VPUNPCKLDQZ256rr,  X86::VPUNPCKLDQZ256rm,    0 },
2291     { X86::VPUNPCKLQDQZ128rr, X86::VPUNPCKLQDQZ128rm,   0 },
2292     { X86::VPUNPCKLQDQZ256rr, X86::VPUNPCKLQDQZ256rm,   0 },
2293     { X86::VPUNPCKLWDZ128rr,  X86::VPUNPCKLWDZ128rm,    0 },
2294     { X86::VPUNPCKLWDZ256rr,  X86::VPUNPCKLWDZ256rm,    0 },
2295     { X86::VPXORDZ128rr,      X86::VPXORDZ128rm,        0 },
2296     { X86::VPXORDZ256rr,      X86::VPXORDZ256rm,        0 },
2297     { X86::VPXORQZ128rr,      X86::VPXORQZ128rm,        0 },
2298     { X86::VPXORQZ256rr,      X86::VPXORQZ256rm,        0 },
2299     { X86::VSHUFPDZ128rri,    X86::VSHUFPDZ128rmi,      0 },
2300     { X86::VSHUFPDZ256rri,    X86::VSHUFPDZ256rmi,      0 },
2301     { X86::VSHUFPSZ128rri,    X86::VSHUFPSZ128rmi,      0 },
2302     { X86::VSHUFPSZ256rri,    X86::VSHUFPSZ256rmi,      0 },
2303     { X86::VSUBPDZ128rr,      X86::VSUBPDZ128rm,        0 },
2304     { X86::VSUBPDZ256rr,      X86::VSUBPDZ256rm,        0 },
2305     { X86::VSUBPSZ128rr,      X86::VSUBPSZ128rm,        0 },
2306     { X86::VSUBPSZ256rr,      X86::VSUBPSZ256rm,        0 },
2307     { X86::VUNPCKHPDZ128rr,   X86::VUNPCKHPDZ128rm,     0 },
2308     { X86::VUNPCKHPDZ256rr,   X86::VUNPCKHPDZ256rm,     0 },
2309     { X86::VUNPCKHPSZ128rr,   X86::VUNPCKHPSZ128rm,     0 },
2310     { X86::VUNPCKHPSZ256rr,   X86::VUNPCKHPSZ256rm,     0 },
2311     { X86::VUNPCKLPDZ128rr,   X86::VUNPCKLPDZ128rm,     0 },
2312     { X86::VUNPCKLPDZ256rr,   X86::VUNPCKLPDZ256rm,     0 },
2313     { X86::VUNPCKLPSZ128rr,   X86::VUNPCKLPSZ128rm,     0 },
2314     { X86::VUNPCKLPSZ256rr,   X86::VUNPCKLPSZ256rm,     0 },
2315     { X86::VXORPDZ128rr,      X86::VXORPDZ128rm,        0 },
2316     { X86::VXORPDZ256rr,      X86::VXORPDZ256rm,        0 },
2317     { X86::VXORPSZ128rr,      X86::VXORPSZ128rm,        0 },
2318     { X86::VXORPSZ256rr,      X86::VXORPSZ256rm,        0 },
2319 
2320     // AVX-512 masked foldable instructions
2321     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
2322     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
2323     { X86::VPABSBZrrkz,       X86::VPABSBZrmkz,         0 },
2324     { X86::VPABSDZrrkz,       X86::VPABSDZrmkz,         0 },
2325     { X86::VPABSQZrrkz,       X86::VPABSQZrmkz,         0 },
2326     { X86::VPABSWZrrkz,       X86::VPABSWZrmkz,         0 },
2327     { X86::VPCONFLICTDZrrkz,  X86::VPCONFLICTDZrmkz,    0 },
2328     { X86::VPCONFLICTQZrrkz,  X86::VPCONFLICTQZrmkz,    0 },
2329     { X86::VPERMILPDZrikz,    X86::VPERMILPDZmikz,      0 },
2330     { X86::VPERMILPSZrikz,    X86::VPERMILPSZmikz,      0 },
2331     { X86::VPERMPDZrikz,      X86::VPERMPDZmikz,        0 },
2332     { X86::VPERMQZrikz,       X86::VPERMQZmikz,         0 },
2333     { X86::VPLZCNTDZrrkz,     X86::VPLZCNTDZrmkz,       0 },
2334     { X86::VPLZCNTQZrrkz,     X86::VPLZCNTQZrmkz,       0 },
2335     { X86::VPMOVSXBDZrrkz,    X86::VPMOVSXBDZrmkz,      0 },
2336     { X86::VPMOVSXBQZrrkz,    X86::VPMOVSXBQZrmkz,      TB_NO_REVERSE },
2337     { X86::VPMOVSXBWZrrkz,    X86::VPMOVSXBWZrmkz,      0 },
2338     { X86::VPMOVSXDQZrrkz,    X86::VPMOVSXDQZrmkz,      0 },
2339     { X86::VPMOVSXWDZrrkz,    X86::VPMOVSXWDZrmkz,      0 },
2340     { X86::VPMOVSXWQZrrkz,    X86::VPMOVSXWQZrmkz,      0 },
2341     { X86::VPMOVZXBDZrrkz,    X86::VPMOVZXBDZrmkz,      0 },
2342     { X86::VPMOVZXBQZrrkz,    X86::VPMOVZXBQZrmkz,      TB_NO_REVERSE },
2343     { X86::VPMOVZXBWZrrkz,    X86::VPMOVZXBWZrmkz,      0 },
2344     { X86::VPMOVZXDQZrrkz,    X86::VPMOVZXDQZrmkz,      0 },
2345     { X86::VPMOVZXWDZrrkz,    X86::VPMOVZXWDZrmkz,      0 },
2346     { X86::VPMOVZXWQZrrkz,    X86::VPMOVZXWQZrmkz,      0 },
2347     { X86::VPOPCNTDZrrkz,     X86::VPOPCNTDZrmkz,       0 },
2348     { X86::VPOPCNTQZrrkz,     X86::VPOPCNTQZrmkz,       0 },
2349     { X86::VPSHUFDZrikz,      X86::VPSHUFDZmikz,        0 },
2350     { X86::VPSHUFHWZrikz,     X86::VPSHUFHWZmikz,       0 },
2351     { X86::VPSHUFLWZrikz,     X86::VPSHUFLWZmikz,       0 },
2352     { X86::VPSLLDZrikz,       X86::VPSLLDZmikz,         0 },
2353     { X86::VPSLLQZrikz,       X86::VPSLLQZmikz,         0 },
2354     { X86::VPSLLWZrikz,       X86::VPSLLWZmikz,         0 },
2355     { X86::VPSRADZrikz,       X86::VPSRADZmikz,         0 },
2356     { X86::VPSRAQZrikz,       X86::VPSRAQZmikz,         0 },
2357     { X86::VPSRAWZrikz,       X86::VPSRAWZmikz,         0 },
2358     { X86::VPSRLDZrikz,       X86::VPSRLDZmikz,         0 },
2359     { X86::VPSRLQZrikz,       X86::VPSRLQZmikz,         0 },
2360     { X86::VPSRLWZrikz,       X86::VPSRLWZmikz,         0 },
2361 
2362     // AVX-512VL 256-bit masked foldable instructions
2363     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
2364     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
2365     { X86::VPABSBZ256rrkz,    X86::VPABSBZ256rmkz,      0 },
2366     { X86::VPABSDZ256rrkz,    X86::VPABSDZ256rmkz,      0 },
2367     { X86::VPABSQZ256rrkz,    X86::VPABSQZ256rmkz,      0 },
2368     { X86::VPABSWZ256rrkz,    X86::VPABSWZ256rmkz,      0 },
2369     { X86::VPCONFLICTDZ256rrkz, X86::VPCONFLICTDZ256rmkz, 0 },
2370     { X86::VPCONFLICTQZ256rrkz, X86::VPCONFLICTQZ256rmkz, 0 },
2371     { X86::VPERMILPDZ256rikz, X86::VPERMILPDZ256mikz,   0 },
2372     { X86::VPERMILPSZ256rikz, X86::VPERMILPSZ256mikz,   0 },
2373     { X86::VPERMPDZ256rikz,   X86::VPERMPDZ256mikz,     0 },
2374     { X86::VPERMQZ256rikz,    X86::VPERMQZ256mikz,      0 },
2375     { X86::VPLZCNTDZ256rrkz,  X86::VPLZCNTDZ256rmkz,    0 },
2376     { X86::VPLZCNTQZ256rrkz,  X86::VPLZCNTQZ256rmkz,    0 },
2377     { X86::VPMOVSXBDZ256rrkz, X86::VPMOVSXBDZ256rmkz,   TB_NO_REVERSE },
2378     { X86::VPMOVSXBQZ256rrkz, X86::VPMOVSXBQZ256rmkz,   TB_NO_REVERSE },
2379     { X86::VPMOVSXBWZ256rrkz, X86::VPMOVSXBWZ256rmkz,   0 },
2380     { X86::VPMOVSXDQZ256rrkz, X86::VPMOVSXDQZ256rmkz,   0 },
2381     { X86::VPMOVSXWDZ256rrkz, X86::VPMOVSXWDZ256rmkz,   0 },
2382     { X86::VPMOVSXWQZ256rrkz, X86::VPMOVSXWQZ256rmkz,   TB_NO_REVERSE },
2383     { X86::VPMOVZXBDZ256rrkz, X86::VPMOVZXBDZ256rmkz,   TB_NO_REVERSE },
2384     { X86::VPMOVZXBQZ256rrkz, X86::VPMOVZXBQZ256rmkz,   TB_NO_REVERSE },
2385     { X86::VPMOVZXBWZ256rrkz, X86::VPMOVZXBWZ256rmkz,   0 },
2386     { X86::VPMOVZXDQZ256rrkz, X86::VPMOVZXDQZ256rmkz,   0 },
2387     { X86::VPMOVZXWDZ256rrkz, X86::VPMOVZXWDZ256rmkz,   0 },
2388     { X86::VPMOVZXWQZ256rrkz, X86::VPMOVZXWQZ256rmkz,   TB_NO_REVERSE },
2389     { X86::VPSHUFDZ256rikz,   X86::VPSHUFDZ256mikz,     0 },
2390     { X86::VPSHUFHWZ256rikz,  X86::VPSHUFHWZ256mikz,    0 },
2391     { X86::VPSHUFLWZ256rikz,  X86::VPSHUFLWZ256mikz,    0 },
2392     { X86::VPSLLDZ256rikz,    X86::VPSLLDZ256mikz,      0 },
2393     { X86::VPSLLQZ256rikz,    X86::VPSLLQZ256mikz,      0 },
2394     { X86::VPSLLWZ256rikz,    X86::VPSLLWZ256mikz,      0 },
2395     { X86::VPSRADZ256rikz,    X86::VPSRADZ256mikz,      0 },
2396     { X86::VPSRAQZ256rikz,    X86::VPSRAQZ256mikz,      0 },
2397     { X86::VPSRAWZ256rikz,    X86::VPSRAWZ256mikz,      0 },
2398     { X86::VPSRLDZ256rikz,    X86::VPSRLDZ256mikz,      0 },
2399     { X86::VPSRLQZ256rikz,    X86::VPSRLQZ256mikz,      0 },
2400     { X86::VPSRLWZ256rikz,    X86::VPSRLWZ256mikz,      0 },
2401 
2402     // AVX-512VL 128-bit masked foldable instructions
2403     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
2404     { X86::VPABSBZ128rrkz,    X86::VPABSBZ128rmkz,      0 },
2405     { X86::VPABSDZ128rrkz,    X86::VPABSDZ128rmkz,      0 },
2406     { X86::VPABSQZ128rrkz,    X86::VPABSQZ128rmkz,      0 },
2407     { X86::VPABSWZ128rrkz,    X86::VPABSWZ128rmkz,      0 },
2408     { X86::VPCONFLICTDZ128rrkz, X86::VPCONFLICTDZ128rmkz, 0 },
2409     { X86::VPCONFLICTQZ128rrkz, X86::VPCONFLICTQZ128rmkz, 0 },
2410     { X86::VPERMILPDZ128rikz, X86::VPERMILPDZ128mikz,   0 },
2411     { X86::VPERMILPSZ128rikz, X86::VPERMILPSZ128mikz,   0 },
2412     { X86::VPLZCNTDZ128rrkz,  X86::VPLZCNTDZ128rmkz,    0 },
2413     { X86::VPLZCNTQZ128rrkz,  X86::VPLZCNTQZ128rmkz,    0 },
2414     { X86::VPMOVSXBDZ128rrkz, X86::VPMOVSXBDZ128rmkz,   TB_NO_REVERSE },
2415     { X86::VPMOVSXBQZ128rrkz, X86::VPMOVSXBQZ128rmkz,   TB_NO_REVERSE },
2416     { X86::VPMOVSXBWZ128rrkz, X86::VPMOVSXBWZ128rmkz,   TB_NO_REVERSE },
2417     { X86::VPMOVSXDQZ128rrkz, X86::VPMOVSXDQZ128rmkz,   TB_NO_REVERSE },
2418     { X86::VPMOVSXWDZ128rrkz, X86::VPMOVSXWDZ128rmkz,   TB_NO_REVERSE },
2419     { X86::VPMOVSXWQZ128rrkz, X86::VPMOVSXWQZ128rmkz,   TB_NO_REVERSE },
2420     { X86::VPMOVZXBDZ128rrkz, X86::VPMOVZXBDZ128rmkz,   TB_NO_REVERSE },
2421     { X86::VPMOVZXBQZ128rrkz, X86::VPMOVZXBQZ128rmkz,   TB_NO_REVERSE },
2422     { X86::VPMOVZXBWZ128rrkz, X86::VPMOVZXBWZ128rmkz,   TB_NO_REVERSE },
2423     { X86::VPMOVZXDQZ128rrkz, X86::VPMOVZXDQZ128rmkz,   TB_NO_REVERSE },
2424     { X86::VPMOVZXWDZ128rrkz, X86::VPMOVZXWDZ128rmkz,   TB_NO_REVERSE },
2425     { X86::VPMOVZXWQZ128rrkz, X86::VPMOVZXWQZ128rmkz,   TB_NO_REVERSE },
2426     { X86::VPSHUFDZ128rikz,   X86::VPSHUFDZ128mikz,     0 },
2427     { X86::VPSHUFHWZ128rikz,  X86::VPSHUFHWZ128mikz,    0 },
2428     { X86::VPSHUFLWZ128rikz,  X86::VPSHUFLWZ128mikz,    0 },
2429     { X86::VPSLLDZ128rikz,    X86::VPSLLDZ128mikz,      0 },
2430     { X86::VPSLLQZ128rikz,    X86::VPSLLQZ128mikz,      0 },
2431     { X86::VPSLLWZ128rikz,    X86::VPSLLWZ128mikz,      0 },
2432     { X86::VPSRADZ128rikz,    X86::VPSRADZ128mikz,      0 },
2433     { X86::VPSRAQZ128rikz,    X86::VPSRAQZ128mikz,      0 },
2434     { X86::VPSRAWZ128rikz,    X86::VPSRAWZ128mikz,      0 },
2435     { X86::VPSRLDZ128rikz,    X86::VPSRLDZ128mikz,      0 },
2436     { X86::VPSRLQZ128rikz,    X86::VPSRLQZ128mikz,      0 },
2437     { X86::VPSRLWZ128rikz,    X86::VPSRLWZ128mikz,      0 },
2438 
2439     // AES foldable instructions
2440     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
2441     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
2442     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
2443     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
2444     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
2445     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
2446     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
2447     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
2448 
2449     // SHA foldable instructions
2450     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
2451     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
2452     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
2453     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
2454     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
2455     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
2456     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
2457   };
2458 
2459   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
2460     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
2461                   Entry.RegOp, Entry.MemOp,
2462                   // Index 2, folded load
2463                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
2464   }
2465 
2466   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
2467     // FMA4 foldable patterns
2468     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
2469     { X86::VFMADDSS4rr_Int,       X86::VFMADDSS4rm_Int,       TB_NO_REVERSE },
2470     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
2471     { X86::VFMADDSD4rr_Int,       X86::VFMADDSD4rm_Int,       TB_NO_REVERSE },
2472     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
2473     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
2474     { X86::VFMADDPS4Yrr,          X86::VFMADDPS4Yrm,          TB_ALIGN_NONE },
2475     { X86::VFMADDPD4Yrr,          X86::VFMADDPD4Yrm,          TB_ALIGN_NONE },
2476     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
2477     { X86::VFNMADDSS4rr_Int,      X86::VFNMADDSS4rm_Int,      TB_NO_REVERSE },
2478     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
2479     { X86::VFNMADDSD4rr_Int,      X86::VFNMADDSD4rm_Int,      TB_NO_REVERSE },
2480     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
2481     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
2482     { X86::VFNMADDPS4Yrr,         X86::VFNMADDPS4Yrm,         TB_ALIGN_NONE },
2483     { X86::VFNMADDPD4Yrr,         X86::VFNMADDPD4Yrm,         TB_ALIGN_NONE },
2484     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
2485     { X86::VFMSUBSS4rr_Int,       X86::VFMSUBSS4rm_Int,       TB_NO_REVERSE },
2486     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
2487     { X86::VFMSUBSD4rr_Int,       X86::VFMSUBSD4rm_Int,       TB_NO_REVERSE },
2488     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
2489     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
2490     { X86::VFMSUBPS4Yrr,          X86::VFMSUBPS4Yrm,          TB_ALIGN_NONE },
2491     { X86::VFMSUBPD4Yrr,          X86::VFMSUBPD4Yrm,          TB_ALIGN_NONE },
2492     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
2493     { X86::VFNMSUBSS4rr_Int,      X86::VFNMSUBSS4rm_Int,      TB_NO_REVERSE },
2494     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
2495     { X86::VFNMSUBSD4rr_Int,      X86::VFNMSUBSD4rm_Int,      TB_NO_REVERSE },
2496     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
2497     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
2498     { X86::VFNMSUBPS4Yrr,         X86::VFNMSUBPS4Yrm,         TB_ALIGN_NONE },
2499     { X86::VFNMSUBPD4Yrr,         X86::VFNMSUBPD4Yrm,         TB_ALIGN_NONE },
2500     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
2501     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
2502     { X86::VFMADDSUBPS4Yrr,       X86::VFMADDSUBPS4Yrm,       TB_ALIGN_NONE },
2503     { X86::VFMADDSUBPD4Yrr,       X86::VFMADDSUBPD4Yrm,       TB_ALIGN_NONE },
2504     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
2505     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
2506     { X86::VFMSUBADDPS4Yrr,       X86::VFMSUBADDPS4Yrm,       TB_ALIGN_NONE },
2507     { X86::VFMSUBADDPD4Yrr,       X86::VFMSUBADDPD4Yrm,       TB_ALIGN_NONE },
2508 
2509     // XOP foldable instructions
2510     { X86::VPCMOVrrr,             X86::VPCMOVrrm,             0 },
2511     { X86::VPCMOVYrrr,            X86::VPCMOVYrrm,            0 },
2512     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
2513     { X86::VPERMIL2PDYrr,         X86::VPERMIL2PDYrm,         0 },
2514     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
2515     { X86::VPERMIL2PSYrr,         X86::VPERMIL2PSYrm,         0 },
2516     { X86::VPPERMrrr,             X86::VPPERMrrm,             0 },
2517 
2518     // AVX-512 instructions with 3 source operands.
2519     { X86::VPERMI2Brr,            X86::VPERMI2Brm,            0 },
2520     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
2521     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
2522     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
2523     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
2524     { X86::VPERMI2Wrr,            X86::VPERMI2Wrm,            0 },
2525     { X86::VPERMT2Brr,            X86::VPERMT2Brm,            0 },
2526     { X86::VPERMT2Drr,            X86::VPERMT2Drm,            0 },
2527     { X86::VPERMT2PSrr,           X86::VPERMT2PSrm,           0 },
2528     { X86::VPERMT2PDrr,           X86::VPERMT2PDrm,           0 },
2529     { X86::VPERMT2Qrr,            X86::VPERMT2Qrm,            0 },
2530     { X86::VPERMT2Wrr,            X86::VPERMT2Wrm,            0 },
2531     { X86::VPMADD52HUQZr,         X86::VPMADD52HUQZm,         0 },
2532     { X86::VPMADD52LUQZr,         X86::VPMADD52LUQZm,         0 },
2533     { X86::VPTERNLOGDZrri,        X86::VPTERNLOGDZrmi,        0 },
2534     { X86::VPTERNLOGQZrri,        X86::VPTERNLOGQZrmi,        0 },
2535 
2536     // AVX-512VL 256-bit instructions with 3 source operands.
2537     { X86::VPERMI2B256rr,         X86::VPERMI2B256rm,         0 },
2538     { X86::VPERMI2D256rr,         X86::VPERMI2D256rm,         0 },
2539     { X86::VPERMI2PD256rr,        X86::VPERMI2PD256rm,        0 },
2540     { X86::VPERMI2PS256rr,        X86::VPERMI2PS256rm,        0 },
2541     { X86::VPERMI2Q256rr,         X86::VPERMI2Q256rm,         0 },
2542     { X86::VPERMI2W256rr,         X86::VPERMI2W256rm,         0 },
2543     { X86::VPERMT2B256rr,         X86::VPERMT2B256rm,         0 },
2544     { X86::VPERMT2D256rr,         X86::VPERMT2D256rm,         0 },
2545     { X86::VPERMT2PD256rr,        X86::VPERMT2PD256rm,        0 },
2546     { X86::VPERMT2PS256rr,        X86::VPERMT2PS256rm,        0 },
2547     { X86::VPERMT2Q256rr,         X86::VPERMT2Q256rm,         0 },
2548     { X86::VPERMT2W256rr,         X86::VPERMT2W256rm,         0 },
2549     { X86::VPMADD52HUQZ256r,      X86::VPMADD52HUQZ256m,      0 },
2550     { X86::VPMADD52LUQZ256r,      X86::VPMADD52LUQZ256m,      0 },
2551     { X86::VPTERNLOGDZ256rri,     X86::VPTERNLOGDZ256rmi,     0 },
2552     { X86::VPTERNLOGQZ256rri,     X86::VPTERNLOGQZ256rmi,     0 },
2553 
2554     // AVX-512VL 128-bit instructions with 3 source operands.
2555     { X86::VPERMI2B128rr,         X86::VPERMI2B128rm,         0 },
2556     { X86::VPERMI2D128rr,         X86::VPERMI2D128rm,         0 },
2557     { X86::VPERMI2PD128rr,        X86::VPERMI2PD128rm,        0 },
2558     { X86::VPERMI2PS128rr,        X86::VPERMI2PS128rm,        0 },
2559     { X86::VPERMI2Q128rr,         X86::VPERMI2Q128rm,         0 },
2560     { X86::VPERMI2W128rr,         X86::VPERMI2W128rm,         0 },
2561     { X86::VPERMT2B128rr,         X86::VPERMT2B128rm,         0 },
2562     { X86::VPERMT2D128rr,         X86::VPERMT2D128rm,         0 },
2563     { X86::VPERMT2PD128rr,        X86::VPERMT2PD128rm,        0 },
2564     { X86::VPERMT2PS128rr,        X86::VPERMT2PS128rm,        0 },
2565     { X86::VPERMT2Q128rr,         X86::VPERMT2Q128rm,         0 },
2566     { X86::VPERMT2W128rr,         X86::VPERMT2W128rm,         0 },
2567     { X86::VPMADD52HUQZ128r,      X86::VPMADD52HUQZ128m,      0 },
2568     { X86::VPMADD52LUQZ128r,      X86::VPMADD52LUQZ128m,      0 },
2569     { X86::VPTERNLOGDZ128rri,     X86::VPTERNLOGDZ128rmi,     0 },
2570     { X86::VPTERNLOGQZ128rri,     X86::VPTERNLOGQZ128rmi,     0 },
2571 
2572     // AVX-512 masked instructions
2573     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
2574     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
2575     { X86::VADDSDZrr_Intkz,       X86::VADDSDZrm_Intkz,       TB_NO_REVERSE },
2576     { X86::VADDSSZrr_Intkz,       X86::VADDSSZrm_Intkz,       TB_NO_REVERSE },
2577     { X86::VALIGNDZrrikz,         X86::VALIGNDZrmikz,         0 },
2578     { X86::VALIGNQZrrikz,         X86::VALIGNQZrmikz,         0 },
2579     { X86::VANDNPDZrrkz,          X86::VANDNPDZrmkz,          0 },
2580     { X86::VANDNPSZrrkz,          X86::VANDNPSZrmkz,          0 },
2581     { X86::VANDPDZrrkz,           X86::VANDPDZrmkz,           0 },
2582     { X86::VANDPSZrrkz,           X86::VANDPSZrmkz,           0 },
2583     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
2584     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
2585     { X86::VDIVSDZrr_Intkz,       X86::VDIVSDZrm_Intkz,       TB_NO_REVERSE },
2586     { X86::VDIVSSZrr_Intkz,       X86::VDIVSSZrm_Intkz,       TB_NO_REVERSE },
2587     { X86::VINSERTF32x4Zrrkz,     X86::VINSERTF32x4Zrmkz,     0 },
2588     { X86::VINSERTF32x8Zrrkz,     X86::VINSERTF32x8Zrmkz,     0 },
2589     { X86::VINSERTF64x2Zrrkz,     X86::VINSERTF64x2Zrmkz,     0 },
2590     { X86::VINSERTF64x4Zrrkz,     X86::VINSERTF64x4Zrmkz,     0 },
2591     { X86::VINSERTI32x4Zrrkz,     X86::VINSERTI32x4Zrmkz,     0 },
2592     { X86::VINSERTI32x8Zrrkz,     X86::VINSERTI32x8Zrmkz,     0 },
2593     { X86::VINSERTI64x2Zrrkz,     X86::VINSERTI64x2Zrmkz,     0 },
2594     { X86::VINSERTI64x4Zrrkz,     X86::VINSERTI64x4Zrmkz,     0 },
2595     { X86::VMAXCPDZrrkz,          X86::VMAXCPDZrmkz,          0 },
2596     { X86::VMAXCPSZrrkz,          X86::VMAXCPSZrmkz,          0 },
2597     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
2598     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
2599     { X86::VMAXSDZrr_Intkz,       X86::VMAXSDZrm_Intkz,       0 },
2600     { X86::VMAXSSZrr_Intkz,       X86::VMAXSSZrm_Intkz,       0 },
2601     { X86::VMINCPDZrrkz,          X86::VMINCPDZrmkz,          0 },
2602     { X86::VMINCPSZrrkz,          X86::VMINCPSZrmkz,          0 },
2603     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
2604     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
2605     { X86::VMINSDZrr_Intkz,       X86::VMINSDZrm_Intkz,       0 },
2606     { X86::VMINSSZrr_Intkz,       X86::VMINSSZrm_Intkz,       0 },
2607     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
2608     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
2609     { X86::VMULSDZrr_Intkz,       X86::VMULSDZrm_Intkz,       TB_NO_REVERSE },
2610     { X86::VMULSSZrr_Intkz,       X86::VMULSSZrm_Intkz,       TB_NO_REVERSE },
2611     { X86::VORPDZrrkz,            X86::VORPDZrmkz,            0 },
2612     { X86::VORPSZrrkz,            X86::VORPSZrmkz,            0 },
2613     { X86::VPACKSSDWZrrkz,        X86::VPACKSSDWZrmkz,        0 },
2614     { X86::VPACKSSWBZrrkz,        X86::VPACKSSWBZrmkz,        0 },
2615     { X86::VPACKUSDWZrrkz,        X86::VPACKUSDWZrmkz,        0 },
2616     { X86::VPACKUSWBZrrkz,        X86::VPACKUSWBZrmkz,        0 },
2617     { X86::VPADDBZrrkz,           X86::VPADDBZrmkz,           0 },
2618     { X86::VPADDDZrrkz,           X86::VPADDDZrmkz,           0 },
2619     { X86::VPADDQZrrkz,           X86::VPADDQZrmkz,           0 },
2620     { X86::VPADDSBZrrkz,          X86::VPADDSBZrmkz,          0 },
2621     { X86::VPADDSWZrrkz,          X86::VPADDSWZrmkz,          0 },
2622     { X86::VPADDUSBZrrkz,         X86::VPADDUSBZrmkz,         0 },
2623     { X86::VPADDUSWZrrkz,         X86::VPADDUSWZrmkz,         0 },
2624     { X86::VPADDWZrrkz,           X86::VPADDWZrmkz,           0 },
2625     { X86::VPALIGNRZrrikz,        X86::VPALIGNRZrmikz,        0 },
2626     { X86::VPANDDZrrkz,           X86::VPANDDZrmkz,           0 },
2627     { X86::VPANDNDZrrkz,          X86::VPANDNDZrmkz,          0 },
2628     { X86::VPANDNQZrrkz,          X86::VPANDNQZrmkz,          0 },
2629     { X86::VPANDQZrrkz,           X86::VPANDQZrmkz,           0 },
2630     { X86::VPAVGBZrrkz,           X86::VPAVGBZrmkz,           0 },
2631     { X86::VPAVGWZrrkz,           X86::VPAVGWZrmkz,           0 },
2632     { X86::VPERMBZrrkz,           X86::VPERMBZrmkz,           0 },
2633     { X86::VPERMDZrrkz,           X86::VPERMDZrmkz,           0 },
2634     { X86::VPERMILPDZrrkz,        X86::VPERMILPDZrmkz,        0 },
2635     { X86::VPERMILPSZrrkz,        X86::VPERMILPSZrmkz,        0 },
2636     { X86::VPERMPDZrrkz,          X86::VPERMPDZrmkz,          0 },
2637     { X86::VPERMPSZrrkz,          X86::VPERMPSZrmkz,          0 },
2638     { X86::VPERMQZrrkz,           X86::VPERMQZrmkz,           0 },
2639     { X86::VPERMWZrrkz,           X86::VPERMWZrmkz,           0 },
2640     { X86::VPMADDUBSWZrrkz,       X86::VPMADDUBSWZrmkz,       0 },
2641     { X86::VPMADDWDZrrkz,         X86::VPMADDWDZrmkz,         0 },
2642     { X86::VPMAXSBZrrkz,          X86::VPMAXSBZrmkz,          0 },
2643     { X86::VPMAXSDZrrkz,          X86::VPMAXSDZrmkz,          0 },
2644     { X86::VPMAXSQZrrkz,          X86::VPMAXSQZrmkz,          0 },
2645     { X86::VPMAXSWZrrkz,          X86::VPMAXSWZrmkz,          0 },
2646     { X86::VPMAXUBZrrkz,          X86::VPMAXUBZrmkz,          0 },
2647     { X86::VPMAXUDZrrkz,          X86::VPMAXUDZrmkz,          0 },
2648     { X86::VPMAXUQZrrkz,          X86::VPMAXUQZrmkz,          0 },
2649     { X86::VPMAXUWZrrkz,          X86::VPMAXUWZrmkz,          0 },
2650     { X86::VPMINSBZrrkz,          X86::VPMINSBZrmkz,          0 },
2651     { X86::VPMINSDZrrkz,          X86::VPMINSDZrmkz,          0 },
2652     { X86::VPMINSQZrrkz,          X86::VPMINSQZrmkz,          0 },
2653     { X86::VPMINSWZrrkz,          X86::VPMINSWZrmkz,          0 },
2654     { X86::VPMINUBZrrkz,          X86::VPMINUBZrmkz,          0 },
2655     { X86::VPMINUDZrrkz,          X86::VPMINUDZrmkz,          0 },
2656     { X86::VPMINUQZrrkz,          X86::VPMINUQZrmkz,          0 },
2657     { X86::VPMINUWZrrkz,          X86::VPMINUWZrmkz,          0 },
2658     { X86::VPMULLDZrrkz,          X86::VPMULLDZrmkz,          0 },
2659     { X86::VPMULLQZrrkz,          X86::VPMULLQZrmkz,          0 },
2660     { X86::VPMULLWZrrkz,          X86::VPMULLWZrmkz,          0 },
2661     { X86::VPMULDQZrrkz,          X86::VPMULDQZrmkz,          0 },
2662     { X86::VPMULUDQZrrkz,         X86::VPMULUDQZrmkz,         0 },
2663     { X86::VPORDZrrkz,            X86::VPORDZrmkz,            0 },
2664     { X86::VPORQZrrkz,            X86::VPORQZrmkz,            0 },
2665     { X86::VPSHUFBZrrkz,          X86::VPSHUFBZrmkz,          0 },
2666     { X86::VPSLLDZrrkz,           X86::VPSLLDZrmkz,           0 },
2667     { X86::VPSLLQZrrkz,           X86::VPSLLQZrmkz,           0 },
2668     { X86::VPSLLVDZrrkz,          X86::VPSLLVDZrmkz,          0 },
2669     { X86::VPSLLVQZrrkz,          X86::VPSLLVQZrmkz,          0 },
2670     { X86::VPSLLVWZrrkz,          X86::VPSLLVWZrmkz,          0 },
2671     { X86::VPSLLWZrrkz,           X86::VPSLLWZrmkz,           0 },
2672     { X86::VPSRADZrrkz,           X86::VPSRADZrmkz,           0 },
2673     { X86::VPSRAQZrrkz,           X86::VPSRAQZrmkz,           0 },
2674     { X86::VPSRAVDZrrkz,          X86::VPSRAVDZrmkz,          0 },
2675     { X86::VPSRAVQZrrkz,          X86::VPSRAVQZrmkz,          0 },
2676     { X86::VPSRAVWZrrkz,          X86::VPSRAVWZrmkz,          0 },
2677     { X86::VPSRAWZrrkz,           X86::VPSRAWZrmkz,           0 },
2678     { X86::VPSRLDZrrkz,           X86::VPSRLDZrmkz,           0 },
2679     { X86::VPSRLQZrrkz,           X86::VPSRLQZrmkz,           0 },
2680     { X86::VPSRLVDZrrkz,          X86::VPSRLVDZrmkz,          0 },
2681     { X86::VPSRLVQZrrkz,          X86::VPSRLVQZrmkz,          0 },
2682     { X86::VPSRLVWZrrkz,          X86::VPSRLVWZrmkz,          0 },
2683     { X86::VPSRLWZrrkz,           X86::VPSRLWZrmkz,           0 },
2684     { X86::VPSUBBZrrkz,           X86::VPSUBBZrmkz,           0 },
2685     { X86::VPSUBDZrrkz,           X86::VPSUBDZrmkz,           0 },
2686     { X86::VPSUBQZrrkz,           X86::VPSUBQZrmkz,           0 },
2687     { X86::VPSUBSBZrrkz,          X86::VPSUBSBZrmkz,          0 },
2688     { X86::VPSUBSWZrrkz,          X86::VPSUBSWZrmkz,          0 },
2689     { X86::VPSUBUSBZrrkz,         X86::VPSUBUSBZrmkz,         0 },
2690     { X86::VPSUBUSWZrrkz,         X86::VPSUBUSWZrmkz,         0 },
2691     { X86::VPSUBWZrrkz,           X86::VPSUBWZrmkz,           0 },
2692     { X86::VPUNPCKHBWZrrkz,       X86::VPUNPCKHBWZrmkz,       0 },
2693     { X86::VPUNPCKHDQZrrkz,       X86::VPUNPCKHDQZrmkz,       0 },
2694     { X86::VPUNPCKHQDQZrrkz,      X86::VPUNPCKHQDQZrmkz,      0 },
2695     { X86::VPUNPCKHWDZrrkz,       X86::VPUNPCKHWDZrmkz,       0 },
2696     { X86::VPUNPCKLBWZrrkz,       X86::VPUNPCKLBWZrmkz,       0 },
2697     { X86::VPUNPCKLDQZrrkz,       X86::VPUNPCKLDQZrmkz,       0 },
2698     { X86::VPUNPCKLQDQZrrkz,      X86::VPUNPCKLQDQZrmkz,      0 },
2699     { X86::VPUNPCKLWDZrrkz,       X86::VPUNPCKLWDZrmkz,       0 },
2700     { X86::VPXORDZrrkz,           X86::VPXORDZrmkz,           0 },
2701     { X86::VPXORQZrrkz,           X86::VPXORQZrmkz,           0 },
2702     { X86::VSHUFPDZrrikz,         X86::VSHUFPDZrmikz,         0 },
2703     { X86::VSHUFPSZrrikz,         X86::VSHUFPSZrmikz,         0 },
2704     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
2705     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
2706     { X86::VSUBSDZrr_Intkz,       X86::VSUBSDZrm_Intkz,       TB_NO_REVERSE },
2707     { X86::VSUBSSZrr_Intkz,       X86::VSUBSSZrm_Intkz,       TB_NO_REVERSE },
2708     { X86::VUNPCKHPDZrrkz,        X86::VUNPCKHPDZrmkz,        0 },
2709     { X86::VUNPCKHPSZrrkz,        X86::VUNPCKHPSZrmkz,        0 },
2710     { X86::VUNPCKLPDZrrkz,        X86::VUNPCKLPDZrmkz,        0 },
2711     { X86::VUNPCKLPSZrrkz,        X86::VUNPCKLPSZrmkz,        0 },
2712     { X86::VXORPDZrrkz,           X86::VXORPDZrmkz,           0 },
2713     { X86::VXORPSZrrkz,           X86::VXORPSZrmkz,           0 },
2714 
2715     // AVX-512{F,VL} masked arithmetic instructions 256-bit
2716     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
2717     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
2718     { X86::VALIGNDZ256rrikz,      X86::VALIGNDZ256rmikz,      0 },
2719     { X86::VALIGNQZ256rrikz,      X86::VALIGNQZ256rmikz,      0 },
2720     { X86::VANDNPDZ256rrkz,       X86::VANDNPDZ256rmkz,       0 },
2721     { X86::VANDNPSZ256rrkz,       X86::VANDNPSZ256rmkz,       0 },
2722     { X86::VANDPDZ256rrkz,        X86::VANDPDZ256rmkz,        0 },
2723     { X86::VANDPSZ256rrkz,        X86::VANDPSZ256rmkz,        0 },
2724     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
2725     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
2726     { X86::VINSERTF32x4Z256rrkz,  X86::VINSERTF32x4Z256rmkz,  0 },
2727     { X86::VINSERTF64x2Z256rrkz,  X86::VINSERTF64x2Z256rmkz,  0 },
2728     { X86::VINSERTI32x4Z256rrkz,  X86::VINSERTI32x4Z256rmkz,  0 },
2729     { X86::VINSERTI64x2Z256rrkz,  X86::VINSERTI64x2Z256rmkz,  0 },
2730     { X86::VMAXCPDZ256rrkz,       X86::VMAXCPDZ256rmkz,       0 },
2731     { X86::VMAXCPSZ256rrkz,       X86::VMAXCPSZ256rmkz,       0 },
2732     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
2733     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
2734     { X86::VMINCPDZ256rrkz,       X86::VMINCPDZ256rmkz,       0 },
2735     { X86::VMINCPSZ256rrkz,       X86::VMINCPSZ256rmkz,       0 },
2736     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
2737     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
2738     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
2739     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
2740     { X86::VORPDZ256rrkz,         X86::VORPDZ256rmkz,         0 },
2741     { X86::VORPSZ256rrkz,         X86::VORPSZ256rmkz,         0 },
2742     { X86::VPACKSSDWZ256rrkz,     X86::VPACKSSDWZ256rmkz,     0 },
2743     { X86::VPACKSSWBZ256rrkz,     X86::VPACKSSWBZ256rmkz,     0 },
2744     { X86::VPACKUSDWZ256rrkz,     X86::VPACKUSDWZ256rmkz,     0 },
2745     { X86::VPACKUSWBZ256rrkz,     X86::VPACKUSWBZ256rmkz,     0 },
2746     { X86::VPADDBZ256rrkz,        X86::VPADDBZ256rmkz,        0 },
2747     { X86::VPADDDZ256rrkz,        X86::VPADDDZ256rmkz,        0 },
2748     { X86::VPADDQZ256rrkz,        X86::VPADDQZ256rmkz,        0 },
2749     { X86::VPADDSBZ256rrkz,       X86::VPADDSBZ256rmkz,       0 },
2750     { X86::VPADDSWZ256rrkz,       X86::VPADDSWZ256rmkz,       0 },
2751     { X86::VPADDUSBZ256rrkz,      X86::VPADDUSBZ256rmkz,      0 },
2752     { X86::VPADDUSWZ256rrkz,      X86::VPADDUSWZ256rmkz,      0 },
2753     { X86::VPADDWZ256rrkz,        X86::VPADDWZ256rmkz,        0 },
2754     { X86::VPALIGNRZ256rrikz,     X86::VPALIGNRZ256rmikz,     0 },
2755     { X86::VPANDDZ256rrkz,        X86::VPANDDZ256rmkz,        0 },
2756     { X86::VPANDNDZ256rrkz,       X86::VPANDNDZ256rmkz,       0 },
2757     { X86::VPANDNQZ256rrkz,       X86::VPANDNQZ256rmkz,       0 },
2758     { X86::VPANDQZ256rrkz,        X86::VPANDQZ256rmkz,        0 },
2759     { X86::VPAVGBZ256rrkz,        X86::VPAVGBZ256rmkz,        0 },
2760     { X86::VPAVGWZ256rrkz,        X86::VPAVGWZ256rmkz,        0 },
2761     { X86::VPERMBZ256rrkz,        X86::VPERMBZ256rmkz,        0 },
2762     { X86::VPERMDZ256rrkz,        X86::VPERMDZ256rmkz,        0 },
2763     { X86::VPERMILPDZ256rrkz,     X86::VPERMILPDZ256rmkz,     0 },
2764     { X86::VPERMILPSZ256rrkz,     X86::VPERMILPSZ256rmkz,     0 },
2765     { X86::VPERMPDZ256rrkz,       X86::VPERMPDZ256rmkz,       0 },
2766     { X86::VPERMPSZ256rrkz,       X86::VPERMPSZ256rmkz,       0 },
2767     { X86::VPERMQZ256rrkz,        X86::VPERMQZ256rmkz,        0 },
2768     { X86::VPERMWZ256rrkz,        X86::VPERMWZ256rmkz,        0 },
2769     { X86::VPMADDUBSWZ256rrkz,    X86::VPMADDUBSWZ256rmkz,    0 },
2770     { X86::VPMADDWDZ256rrkz,      X86::VPMADDWDZ256rmkz,      0 },
2771     { X86::VPMAXSBZ256rrkz,       X86::VPMAXSBZ256rmkz,       0 },
2772     { X86::VPMAXSDZ256rrkz,       X86::VPMAXSDZ256rmkz,       0 },
2773     { X86::VPMAXSQZ256rrkz,       X86::VPMAXSQZ256rmkz,       0 },
2774     { X86::VPMAXSWZ256rrkz,       X86::VPMAXSWZ256rmkz,       0 },
2775     { X86::VPMAXUBZ256rrkz,       X86::VPMAXUBZ256rmkz,       0 },
2776     { X86::VPMAXUDZ256rrkz,       X86::VPMAXUDZ256rmkz,       0 },
2777     { X86::VPMAXUQZ256rrkz,       X86::VPMAXUQZ256rmkz,       0 },
2778     { X86::VPMAXUWZ256rrkz,       X86::VPMAXUWZ256rmkz,       0 },
2779     { X86::VPMINSBZ256rrkz,       X86::VPMINSBZ256rmkz,       0 },
2780     { X86::VPMINSDZ256rrkz,       X86::VPMINSDZ256rmkz,       0 },
2781     { X86::VPMINSQZ256rrkz,       X86::VPMINSQZ256rmkz,       0 },
2782     { X86::VPMINSWZ256rrkz,       X86::VPMINSWZ256rmkz,       0 },
2783     { X86::VPMINUBZ256rrkz,       X86::VPMINUBZ256rmkz,       0 },
2784     { X86::VPMINUDZ256rrkz,       X86::VPMINUDZ256rmkz,       0 },
2785     { X86::VPMINUQZ256rrkz,       X86::VPMINUQZ256rmkz,       0 },
2786     { X86::VPMINUWZ256rrkz,       X86::VPMINUWZ256rmkz,       0 },
2787     { X86::VPMULDQZ256rrkz,       X86::VPMULDQZ256rmkz,       0 },
2788     { X86::VPMULLDZ256rrkz,       X86::VPMULLDZ256rmkz,       0 },
2789     { X86::VPMULLQZ256rrkz,       X86::VPMULLQZ256rmkz,       0 },
2790     { X86::VPMULLWZ256rrkz,       X86::VPMULLWZ256rmkz,       0 },
2791     { X86::VPMULUDQZ256rrkz,      X86::VPMULUDQZ256rmkz,      0 },
2792     { X86::VPORDZ256rrkz,         X86::VPORDZ256rmkz,         0 },
2793     { X86::VPORQZ256rrkz,         X86::VPORQZ256rmkz,         0 },
2794     { X86::VPSHUFBZ256rrkz,       X86::VPSHUFBZ256rmkz,       0 },
2795     { X86::VPSLLDZ256rrkz,        X86::VPSLLDZ256rmkz,        0 },
2796     { X86::VPSLLQZ256rrkz,        X86::VPSLLQZ256rmkz,        0 },
2797     { X86::VPSLLVDZ256rrkz,       X86::VPSLLVDZ256rmkz,       0 },
2798     { X86::VPSLLVQZ256rrkz,       X86::VPSLLVQZ256rmkz,       0 },
2799     { X86::VPSLLVWZ256rrkz,       X86::VPSLLVWZ256rmkz,       0 },
2800     { X86::VPSLLWZ256rrkz,        X86::VPSLLWZ256rmkz,        0 },
2801     { X86::VPSRADZ256rrkz,        X86::VPSRADZ256rmkz,        0 },
2802     { X86::VPSRAQZ256rrkz,        X86::VPSRAQZ256rmkz,        0 },
2803     { X86::VPSRAVDZ256rrkz,       X86::VPSRAVDZ256rmkz,       0 },
2804     { X86::VPSRAVQZ256rrkz,       X86::VPSRAVQZ256rmkz,       0 },
2805     { X86::VPSRAVWZ256rrkz,       X86::VPSRAVWZ256rmkz,       0 },
2806     { X86::VPSRAWZ256rrkz,        X86::VPSRAWZ256rmkz,        0 },
2807     { X86::VPSRLDZ256rrkz,        X86::VPSRLDZ256rmkz,        0 },
2808     { X86::VPSRLQZ256rrkz,        X86::VPSRLQZ256rmkz,        0 },
2809     { X86::VPSRLVDZ256rrkz,       X86::VPSRLVDZ256rmkz,       0 },
2810     { X86::VPSRLVQZ256rrkz,       X86::VPSRLVQZ256rmkz,       0 },
2811     { X86::VPSRLVWZ256rrkz,       X86::VPSRLVWZ256rmkz,       0 },
2812     { X86::VPSRLWZ256rrkz,        X86::VPSRLWZ256rmkz,        0 },
2813     { X86::VPSUBBZ256rrkz,        X86::VPSUBBZ256rmkz,        0 },
2814     { X86::VPSUBDZ256rrkz,        X86::VPSUBDZ256rmkz,        0 },
2815     { X86::VPSUBQZ256rrkz,        X86::VPSUBQZ256rmkz,        0 },
2816     { X86::VPSUBSBZ256rrkz,       X86::VPSUBSBZ256rmkz,       0 },
2817     { X86::VPSUBSWZ256rrkz,       X86::VPSUBSWZ256rmkz,       0 },
2818     { X86::VPSUBUSBZ256rrkz,      X86::VPSUBUSBZ256rmkz,      0 },
2819     { X86::VPSUBUSWZ256rrkz,      X86::VPSUBUSWZ256rmkz,      0 },
2820     { X86::VPSUBWZ256rrkz,        X86::VPSUBWZ256rmkz,        0 },
2821     { X86::VPUNPCKHBWZ256rrkz,    X86::VPUNPCKHBWZ256rmkz,    0 },
2822     { X86::VPUNPCKHDQZ256rrkz,    X86::VPUNPCKHDQZ256rmkz,    0 },
2823     { X86::VPUNPCKHQDQZ256rrkz,   X86::VPUNPCKHQDQZ256rmkz,   0 },
2824     { X86::VPUNPCKHWDZ256rrkz,    X86::VPUNPCKHWDZ256rmkz,    0 },
2825     { X86::VPUNPCKLBWZ256rrkz,    X86::VPUNPCKLBWZ256rmkz,    0 },
2826     { X86::VPUNPCKLDQZ256rrkz,    X86::VPUNPCKLDQZ256rmkz,    0 },
2827     { X86::VPUNPCKLQDQZ256rrkz,   X86::VPUNPCKLQDQZ256rmkz,   0 },
2828     { X86::VPUNPCKLWDZ256rrkz,    X86::VPUNPCKLWDZ256rmkz,    0 },
2829     { X86::VPXORDZ256rrkz,        X86::VPXORDZ256rmkz,        0 },
2830     { X86::VPXORQZ256rrkz,        X86::VPXORQZ256rmkz,        0 },
2831     { X86::VSHUFPDZ256rrikz,      X86::VSHUFPDZ256rmikz,      0 },
2832     { X86::VSHUFPSZ256rrikz,      X86::VSHUFPSZ256rmikz,      0 },
2833     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
2834     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
2835     { X86::VUNPCKHPDZ256rrkz,     X86::VUNPCKHPDZ256rmkz,     0 },
2836     { X86::VUNPCKHPSZ256rrkz,     X86::VUNPCKHPSZ256rmkz,     0 },
2837     { X86::VUNPCKLPDZ256rrkz,     X86::VUNPCKLPDZ256rmkz,     0 },
2838     { X86::VUNPCKLPSZ256rrkz,     X86::VUNPCKLPSZ256rmkz,     0 },
2839     { X86::VXORPDZ256rrkz,        X86::VXORPDZ256rmkz,        0 },
2840     { X86::VXORPSZ256rrkz,        X86::VXORPSZ256rmkz,        0 },
2841 
2842     // AVX-512{F,VL} masked arithmetic instructions 128-bit
2843     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
2844     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
2845     { X86::VALIGNDZ128rrikz,      X86::VALIGNDZ128rmikz,      0 },
2846     { X86::VALIGNQZ128rrikz,      X86::VALIGNQZ128rmikz,      0 },
2847     { X86::VANDNPDZ128rrkz,       X86::VANDNPDZ128rmkz,       0 },
2848     { X86::VANDNPSZ128rrkz,       X86::VANDNPSZ128rmkz,       0 },
2849     { X86::VANDPDZ128rrkz,        X86::VANDPDZ128rmkz,        0 },
2850     { X86::VANDPSZ128rrkz,        X86::VANDPSZ128rmkz,        0 },
2851     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
2852     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
2853     { X86::VMAXCPDZ128rrkz,       X86::VMAXCPDZ128rmkz,       0 },
2854     { X86::VMAXCPSZ128rrkz,       X86::VMAXCPSZ128rmkz,       0 },
2855     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 },
2856     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
2857     { X86::VMINCPDZ128rrkz,       X86::VMINCPDZ128rmkz,       0 },
2858     { X86::VMINCPSZ128rrkz,       X86::VMINCPSZ128rmkz,       0 },
2859     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
2860     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
2861     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
2862     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
2863     { X86::VORPDZ128rrkz,         X86::VORPDZ128rmkz,         0 },
2864     { X86::VORPSZ128rrkz,         X86::VORPSZ128rmkz,         0 },
2865     { X86::VPACKSSDWZ128rrkz,     X86::VPACKSSDWZ128rmkz,     0 },
2866     { X86::VPACKSSWBZ128rrkz,     X86::VPACKSSWBZ128rmkz,     0 },
2867     { X86::VPACKUSDWZ128rrkz,     X86::VPACKUSDWZ128rmkz,     0 },
2868     { X86::VPACKUSWBZ128rrkz,     X86::VPACKUSWBZ128rmkz,     0 },
2869     { X86::VPADDBZ128rrkz,        X86::VPADDBZ128rmkz,        0 },
2870     { X86::VPADDDZ128rrkz,        X86::VPADDDZ128rmkz,        0 },
2871     { X86::VPADDQZ128rrkz,        X86::VPADDQZ128rmkz,        0 },
2872     { X86::VPADDSBZ128rrkz,       X86::VPADDSBZ128rmkz,       0 },
2873     { X86::VPADDSWZ128rrkz,       X86::VPADDSWZ128rmkz,       0 },
2874     { X86::VPADDUSBZ128rrkz,      X86::VPADDUSBZ128rmkz,      0 },
2875     { X86::VPADDUSWZ128rrkz,      X86::VPADDUSWZ128rmkz,      0 },
2876     { X86::VPADDWZ128rrkz,        X86::VPADDWZ128rmkz,        0 },
2877     { X86::VPALIGNRZ128rrikz,     X86::VPALIGNRZ128rmikz,     0 },
2878     { X86::VPANDDZ128rrkz,        X86::VPANDDZ128rmkz,        0 },
2879     { X86::VPANDNDZ128rrkz,       X86::VPANDNDZ128rmkz,       0 },
2880     { X86::VPANDNQZ128rrkz,       X86::VPANDNQZ128rmkz,       0 },
2881     { X86::VPANDQZ128rrkz,        X86::VPANDQZ128rmkz,        0 },
2882     { X86::VPAVGBZ128rrkz,        X86::VPAVGBZ128rmkz,        0 },
2883     { X86::VPAVGWZ128rrkz,        X86::VPAVGWZ128rmkz,        0 },
2884     { X86::VPERMBZ128rrkz,        X86::VPERMBZ128rmkz,        0 },
2885     { X86::VPERMILPDZ128rrkz,     X86::VPERMILPDZ128rmkz,     0 },
2886     { X86::VPERMILPSZ128rrkz,     X86::VPERMILPSZ128rmkz,     0 },
2887     { X86::VPERMWZ128rrkz,        X86::VPERMWZ128rmkz,        0 },
2888     { X86::VPMADDUBSWZ128rrkz,    X86::VPMADDUBSWZ128rmkz,    0 },
2889     { X86::VPMADDWDZ128rrkz,      X86::VPMADDWDZ128rmkz,      0 },
2890     { X86::VPMAXSBZ128rrkz,       X86::VPMAXSBZ128rmkz,       0 },
2891     { X86::VPMAXSDZ128rrkz,       X86::VPMAXSDZ128rmkz,       0 },
2892     { X86::VPMAXSQZ128rrkz,       X86::VPMAXSQZ128rmkz,       0 },
2893     { X86::VPMAXSWZ128rrkz,       X86::VPMAXSWZ128rmkz,       0 },
2894     { X86::VPMAXUBZ128rrkz,       X86::VPMAXUBZ128rmkz,       0 },
2895     { X86::VPMAXUDZ128rrkz,       X86::VPMAXUDZ128rmkz,       0 },
2896     { X86::VPMAXUQZ128rrkz,       X86::VPMAXUQZ128rmkz,       0 },
2897     { X86::VPMAXUWZ128rrkz,       X86::VPMAXUWZ128rmkz,       0 },
2898     { X86::VPMINSBZ128rrkz,       X86::VPMINSBZ128rmkz,       0 },
2899     { X86::VPMINSDZ128rrkz,       X86::VPMINSDZ128rmkz,       0 },
2900     { X86::VPMINSQZ128rrkz,       X86::VPMINSQZ128rmkz,       0 },
2901     { X86::VPMINSWZ128rrkz,       X86::VPMINSWZ128rmkz,       0 },
2902     { X86::VPMINUBZ128rrkz,       X86::VPMINUBZ128rmkz,       0 },
2903     { X86::VPMINUDZ128rrkz,       X86::VPMINUDZ128rmkz,       0 },
2904     { X86::VPMINUQZ128rrkz,       X86::VPMINUQZ128rmkz,       0 },
2905     { X86::VPMINUWZ128rrkz,       X86::VPMINUWZ128rmkz,       0 },
2906     { X86::VPMULDQZ128rrkz,       X86::VPMULDQZ128rmkz,       0 },
2907     { X86::VPMULLDZ128rrkz,       X86::VPMULLDZ128rmkz,       0 },
2908     { X86::VPMULLQZ128rrkz,       X86::VPMULLQZ128rmkz,       0 },
2909     { X86::VPMULLWZ128rrkz,       X86::VPMULLWZ128rmkz,       0 },
2910     { X86::VPMULUDQZ128rrkz,      X86::VPMULUDQZ128rmkz,      0 },
2911     { X86::VPORDZ128rrkz,         X86::VPORDZ128rmkz,         0 },
2912     { X86::VPORQZ128rrkz,         X86::VPORQZ128rmkz,         0 },
2913     { X86::VPSHUFBZ128rrkz,       X86::VPSHUFBZ128rmkz,       0 },
2914     { X86::VPSLLDZ128rrkz,        X86::VPSLLDZ128rmkz,        0 },
2915     { X86::VPSLLQZ128rrkz,        X86::VPSLLQZ128rmkz,        0 },
2916     { X86::VPSLLVDZ128rrkz,       X86::VPSLLVDZ128rmkz,       0 },
2917     { X86::VPSLLVQZ128rrkz,       X86::VPSLLVQZ128rmkz,       0 },
2918     { X86::VPSLLVWZ128rrkz,       X86::VPSLLVWZ128rmkz,       0 },
2919     { X86::VPSLLWZ128rrkz,        X86::VPSLLWZ128rmkz,        0 },
2920     { X86::VPSRADZ128rrkz,        X86::VPSRADZ128rmkz,        0 },
2921     { X86::VPSRAQZ128rrkz,        X86::VPSRAQZ128rmkz,        0 },
2922     { X86::VPSRAVDZ128rrkz,       X86::VPSRAVDZ128rmkz,       0 },
2923     { X86::VPSRAVQZ128rrkz,       X86::VPSRAVQZ128rmkz,       0 },
2924     { X86::VPSRAVWZ128rrkz,       X86::VPSRAVWZ128rmkz,       0 },
2925     { X86::VPSRAWZ128rrkz,        X86::VPSRAWZ128rmkz,        0 },
2926     { X86::VPSRLDZ128rrkz,        X86::VPSRLDZ128rmkz,        0 },
2927     { X86::VPSRLQZ128rrkz,        X86::VPSRLQZ128rmkz,        0 },
2928     { X86::VPSRLVDZ128rrkz,       X86::VPSRLVDZ128rmkz,       0 },
2929     { X86::VPSRLVQZ128rrkz,       X86::VPSRLVQZ128rmkz,       0 },
2930     { X86::VPSRLVWZ128rrkz,       X86::VPSRLVWZ128rmkz,       0 },
2931     { X86::VPSRLWZ128rrkz,        X86::VPSRLWZ128rmkz,        0 },
2932     { X86::VPSUBBZ128rrkz,        X86::VPSUBBZ128rmkz,        0 },
2933     { X86::VPSUBDZ128rrkz,        X86::VPSUBDZ128rmkz,        0 },
2934     { X86::VPSUBQZ128rrkz,        X86::VPSUBQZ128rmkz,        0 },
2935     { X86::VPSUBSBZ128rrkz,       X86::VPSUBSBZ128rmkz,       0 },
2936     { X86::VPSUBSWZ128rrkz,       X86::VPSUBSWZ128rmkz,       0 },
2937     { X86::VPSUBUSBZ128rrkz,      X86::VPSUBUSBZ128rmkz,      0 },
2938     { X86::VPSUBUSWZ128rrkz,      X86::VPSUBUSWZ128rmkz,      0 },
2939     { X86::VPSUBWZ128rrkz,        X86::VPSUBWZ128rmkz,        0 },
2940     { X86::VPUNPCKHBWZ128rrkz,    X86::VPUNPCKHBWZ128rmkz,    0 },
2941     { X86::VPUNPCKHDQZ128rrkz,    X86::VPUNPCKHDQZ128rmkz,    0 },
2942     { X86::VPUNPCKHQDQZ128rrkz,   X86::VPUNPCKHQDQZ128rmkz,   0 },
2943     { X86::VPUNPCKHWDZ128rrkz,    X86::VPUNPCKHWDZ128rmkz,    0 },
2944     { X86::VPUNPCKLBWZ128rrkz,    X86::VPUNPCKLBWZ128rmkz,    0 },
2945     { X86::VPUNPCKLDQZ128rrkz,    X86::VPUNPCKLDQZ128rmkz,    0 },
2946     { X86::VPUNPCKLQDQZ128rrkz,   X86::VPUNPCKLQDQZ128rmkz,   0 },
2947     { X86::VPUNPCKLWDZ128rrkz,    X86::VPUNPCKLWDZ128rmkz,    0 },
2948     { X86::VPXORDZ128rrkz,        X86::VPXORDZ128rmkz,        0 },
2949     { X86::VPXORQZ128rrkz,        X86::VPXORQZ128rmkz,        0 },
2950     { X86::VSHUFPDZ128rrikz,      X86::VSHUFPDZ128rmikz,      0 },
2951     { X86::VSHUFPSZ128rrikz,      X86::VSHUFPSZ128rmikz,      0 },
2952     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
2953     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
2954     { X86::VUNPCKHPDZ128rrkz,     X86::VUNPCKHPDZ128rmkz,     0 },
2955     { X86::VUNPCKHPSZ128rrkz,     X86::VUNPCKHPSZ128rmkz,     0 },
2956     { X86::VUNPCKLPDZ128rrkz,     X86::VUNPCKLPDZ128rmkz,     0 },
2957     { X86::VUNPCKLPSZ128rrkz,     X86::VUNPCKLPSZ128rmkz,     0 },
2958     { X86::VXORPDZ128rrkz,        X86::VXORPDZ128rmkz,        0 },
2959     { X86::VXORPSZ128rrkz,        X86::VXORPSZ128rmkz,        0 },
2960 
2961     // AVX-512 masked foldable instructions
2962     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
2963     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
2964     { X86::VPABSBZrrk,            X86::VPABSBZrmk,            0 },
2965     { X86::VPABSDZrrk,            X86::VPABSDZrmk,            0 },
2966     { X86::VPABSQZrrk,            X86::VPABSQZrmk,            0 },
2967     { X86::VPABSWZrrk,            X86::VPABSWZrmk,            0 },
2968     { X86::VPCONFLICTDZrrk,       X86::VPCONFLICTDZrmk,       0 },
2969     { X86::VPCONFLICTQZrrk,       X86::VPCONFLICTQZrmk,       0 },
2970     { X86::VPERMILPDZrik,         X86::VPERMILPDZmik,         0 },
2971     { X86::VPERMILPSZrik,         X86::VPERMILPSZmik,         0 },
2972     { X86::VPERMPDZrik,           X86::VPERMPDZmik,           0 },
2973     { X86::VPERMQZrik,            X86::VPERMQZmik,            0 },
2974     { X86::VPLZCNTDZrrk,          X86::VPLZCNTDZrmk,          0 },
2975     { X86::VPLZCNTQZrrk,          X86::VPLZCNTQZrmk,          0 },
2976     { X86::VPMOVSXBDZrrk,         X86::VPMOVSXBDZrmk,         0 },
2977     { X86::VPMOVSXBQZrrk,         X86::VPMOVSXBQZrmk,         TB_NO_REVERSE },
2978     { X86::VPMOVSXBWZrrk,         X86::VPMOVSXBWZrmk,         0 },
2979     { X86::VPMOVSXDQZrrk,         X86::VPMOVSXDQZrmk,         0 },
2980     { X86::VPMOVSXWDZrrk,         X86::VPMOVSXWDZrmk,         0 },
2981     { X86::VPMOVSXWQZrrk,         X86::VPMOVSXWQZrmk,         0 },
2982     { X86::VPMOVZXBDZrrk,         X86::VPMOVZXBDZrmk,         0 },
2983     { X86::VPMOVZXBQZrrk,         X86::VPMOVZXBQZrmk,         TB_NO_REVERSE },
2984     { X86::VPMOVZXBWZrrk,         X86::VPMOVZXBWZrmk,         0 },
2985     { X86::VPMOVZXDQZrrk,         X86::VPMOVZXDQZrmk,         0 },
2986     { X86::VPMOVZXWDZrrk,         X86::VPMOVZXWDZrmk,         0 },
2987     { X86::VPMOVZXWQZrrk,         X86::VPMOVZXWQZrmk,         0 },
2988     { X86::VPOPCNTDZrrk,          X86::VPOPCNTDZrmk,          0 },
2989     { X86::VPOPCNTQZrrk,          X86::VPOPCNTQZrmk,          0 },
2990     { X86::VPSHUFDZrik,           X86::VPSHUFDZmik,           0 },
2991     { X86::VPSHUFHWZrik,          X86::VPSHUFHWZmik,          0 },
2992     { X86::VPSHUFLWZrik,          X86::VPSHUFLWZmik,          0 },
2993     { X86::VPSLLDZrik,            X86::VPSLLDZmik,            0 },
2994     { X86::VPSLLQZrik,            X86::VPSLLQZmik,            0 },
2995     { X86::VPSLLWZrik,            X86::VPSLLWZmik,            0 },
2996     { X86::VPSRADZrik,            X86::VPSRADZmik,            0 },
2997     { X86::VPSRAQZrik,            X86::VPSRAQZmik,            0 },
2998     { X86::VPSRAWZrik,            X86::VPSRAWZmik,            0 },
2999     { X86::VPSRLDZrik,            X86::VPSRLDZmik,            0 },
3000     { X86::VPSRLQZrik,            X86::VPSRLQZmik,            0 },
3001     { X86::VPSRLWZrik,            X86::VPSRLWZmik,            0 },
3002 
3003     // AVX-512VL 256-bit masked foldable instructions
3004     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
3005     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
3006     { X86::VPABSBZ256rrk,         X86::VPABSBZ256rmk,         0 },
3007     { X86::VPABSDZ256rrk,         X86::VPABSDZ256rmk,         0 },
3008     { X86::VPABSQZ256rrk,         X86::VPABSQZ256rmk,         0 },
3009     { X86::VPABSWZ256rrk,         X86::VPABSWZ256rmk,         0 },
3010     { X86::VPCONFLICTDZ256rrk,    X86::VPCONFLICTDZ256rmk,    0 },
3011     { X86::VPCONFLICTQZ256rrk,    X86::VPCONFLICTQZ256rmk,    0 },
3012     { X86::VPERMILPDZ256rik,      X86::VPERMILPDZ256mik,      0 },
3013     { X86::VPERMILPSZ256rik,      X86::VPERMILPSZ256mik,      0 },
3014     { X86::VPERMPDZ256rik,        X86::VPERMPDZ256mik,        0 },
3015     { X86::VPERMQZ256rik,         X86::VPERMQZ256mik,         0 },
3016     { X86::VPLZCNTDZ256rrk,       X86::VPLZCNTDZ256rmk,       0 },
3017     { X86::VPLZCNTQZ256rrk,       X86::VPLZCNTQZ256rmk,       0 },
3018     { X86::VPMOVSXBDZ256rrk,      X86::VPMOVSXBDZ256rmk,      TB_NO_REVERSE },
3019     { X86::VPMOVSXBQZ256rrk,      X86::VPMOVSXBQZ256rmk,      TB_NO_REVERSE },
3020     { X86::VPMOVSXBWZ256rrk,      X86::VPMOVSXBWZ256rmk,      0 },
3021     { X86::VPMOVSXDQZ256rrk,      X86::VPMOVSXDQZ256rmk,      0 },
3022     { X86::VPMOVSXWDZ256rrk,      X86::VPMOVSXWDZ256rmk,      0 },
3023     { X86::VPMOVSXWQZ256rrk,      X86::VPMOVSXWQZ256rmk,      TB_NO_REVERSE },
3024     { X86::VPMOVZXBDZ256rrk,      X86::VPMOVZXBDZ256rmk,      TB_NO_REVERSE },
3025     { X86::VPMOVZXBQZ256rrk,      X86::VPMOVZXBQZ256rmk,      TB_NO_REVERSE },
3026     { X86::VPMOVZXBWZ256rrk,      X86::VPMOVZXBWZ256rmk,      0 },
3027     { X86::VPMOVZXDQZ256rrk,      X86::VPMOVZXDQZ256rmk,      0 },
3028     { X86::VPMOVZXWDZ256rrk,      X86::VPMOVZXWDZ256rmk,      0 },
3029     { X86::VPMOVZXWQZ256rrk,      X86::VPMOVZXWQZ256rmk,      TB_NO_REVERSE },
3030     { X86::VPSHUFDZ256rik,        X86::VPSHUFDZ256mik,        0 },
3031     { X86::VPSHUFHWZ256rik,       X86::VPSHUFHWZ256mik,       0 },
3032     { X86::VPSHUFLWZ256rik,       X86::VPSHUFLWZ256mik,       0 },
3033     { X86::VPSLLDZ256rik,         X86::VPSLLDZ256mik,         0 },
3034     { X86::VPSLLQZ256rik,         X86::VPSLLQZ256mik,         0 },
3035     { X86::VPSLLWZ256rik,         X86::VPSLLWZ256mik,         0 },
3036     { X86::VPSRADZ256rik,         X86::VPSRADZ256mik,         0 },
3037     { X86::VPSRAQZ256rik,         X86::VPSRAQZ256mik,         0 },
3038     { X86::VPSRAWZ256rik,         X86::VPSRAWZ256mik,         0 },
3039     { X86::VPSRLDZ256rik,         X86::VPSRLDZ256mik,         0 },
3040     { X86::VPSRLQZ256rik,         X86::VPSRLQZ256mik,         0 },
3041     { X86::VPSRLWZ256rik,         X86::VPSRLWZ256mik,         0 },
3042 
3043     // AVX-512VL 128-bit masked foldable instructions
3044     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
3045     { X86::VPABSBZ128rrk,         X86::VPABSBZ128rmk,         0 },
3046     { X86::VPABSDZ128rrk,         X86::VPABSDZ128rmk,         0 },
3047     { X86::VPABSQZ128rrk,         X86::VPABSQZ128rmk,         0 },
3048     { X86::VPABSWZ128rrk,         X86::VPABSWZ128rmk,         0 },
3049     { X86::VPCONFLICTDZ128rrk,    X86::VPCONFLICTDZ128rmk,    0 },
3050     { X86::VPCONFLICTQZ128rrk,    X86::VPCONFLICTQZ128rmk,    0 },
3051     { X86::VPERMILPDZ128rik,      X86::VPERMILPDZ128mik,      0 },
3052     { X86::VPERMILPSZ128rik,      X86::VPERMILPSZ128mik,      0 },
3053     { X86::VPLZCNTDZ128rrk,       X86::VPLZCNTDZ128rmk,       0 },
3054     { X86::VPLZCNTQZ128rrk,       X86::VPLZCNTQZ128rmk,       0 },
3055     { X86::VPMOVSXBDZ128rrk,      X86::VPMOVSXBDZ128rmk,      TB_NO_REVERSE },
3056     { X86::VPMOVSXBQZ128rrk,      X86::VPMOVSXBQZ128rmk,      TB_NO_REVERSE },
3057     { X86::VPMOVSXBWZ128rrk,      X86::VPMOVSXBWZ128rmk,      TB_NO_REVERSE },
3058     { X86::VPMOVSXDQZ128rrk,      X86::VPMOVSXDQZ128rmk,      TB_NO_REVERSE },
3059     { X86::VPMOVSXWDZ128rrk,      X86::VPMOVSXWDZ128rmk,      TB_NO_REVERSE },
3060     { X86::VPMOVSXWQZ128rrk,      X86::VPMOVSXWQZ128rmk,      TB_NO_REVERSE },
3061     { X86::VPMOVZXBDZ128rrk,      X86::VPMOVZXBDZ128rmk,      TB_NO_REVERSE },
3062     { X86::VPMOVZXBQZ128rrk,      X86::VPMOVZXBQZ128rmk,      TB_NO_REVERSE },
3063     { X86::VPMOVZXBWZ128rrk,      X86::VPMOVZXBWZ128rmk,      TB_NO_REVERSE },
3064     { X86::VPMOVZXDQZ128rrk,      X86::VPMOVZXDQZ128rmk,      TB_NO_REVERSE },
3065     { X86::VPMOVZXWDZ128rrk,      X86::VPMOVZXWDZ128rmk,      TB_NO_REVERSE },
3066     { X86::VPMOVZXWQZ128rrk,      X86::VPMOVZXWQZ128rmk,      TB_NO_REVERSE },
3067     { X86::VPSHUFDZ128rik,        X86::VPSHUFDZ128mik,        0 },
3068     { X86::VPSHUFHWZ128rik,       X86::VPSHUFHWZ128mik,       0 },
3069     { X86::VPSHUFLWZ128rik,       X86::VPSHUFLWZ128mik,       0 },
3070     { X86::VPSLLDZ128rik,         X86::VPSLLDZ128mik,         0 },
3071     { X86::VPSLLQZ128rik,         X86::VPSLLQZ128mik,         0 },
3072     { X86::VPSLLWZ128rik,         X86::VPSLLWZ128mik,         0 },
3073     { X86::VPSRADZ128rik,         X86::VPSRADZ128mik,         0 },
3074     { X86::VPSRAQZ128rik,         X86::VPSRAQZ128mik,         0 },
3075     { X86::VPSRAWZ128rik,         X86::VPSRAWZ128mik,         0 },
3076     { X86::VPSRLDZ128rik,         X86::VPSRLDZ128mik,         0 },
3077     { X86::VPSRLQZ128rik,         X86::VPSRLQZ128mik,         0 },
3078     { X86::VPSRLWZ128rik,         X86::VPSRLWZ128mik,         0 },
3079 
3080     // AVX-512 masked compare instructions
3081     { X86::VCMPPDZ128rrik,        X86::VCMPPDZ128rmik,        0 },
3082     { X86::VCMPPSZ128rrik,        X86::VCMPPSZ128rmik,        0 },
3083     { X86::VCMPPDZ256rrik,        X86::VCMPPDZ256rmik,        0 },
3084     { X86::VCMPPSZ256rrik,        X86::VCMPPSZ256rmik,        0 },
3085     { X86::VCMPPDZrrik,           X86::VCMPPDZrmik,           0 },
3086     { X86::VCMPPSZrrik,           X86::VCMPPSZrmik,           0 },
3087     { X86::VCMPSDZrr_Intk,        X86::VCMPSDZrm_Intk,        TB_NO_REVERSE },
3088     { X86::VCMPSSZrr_Intk,        X86::VCMPSSZrm_Intk,        TB_NO_REVERSE },
3089     { X86::VPCMPBZ128rrik,        X86::VPCMPBZ128rmik,        0 },
3090     { X86::VPCMPBZ256rrik,        X86::VPCMPBZ256rmik,        0 },
3091     { X86::VPCMPBZrrik,           X86::VPCMPBZrmik,           0 },
3092     { X86::VPCMPDZ128rrik,        X86::VPCMPDZ128rmik,        0 },
3093     { X86::VPCMPDZ256rrik,        X86::VPCMPDZ256rmik,        0 },
3094     { X86::VPCMPDZrrik,           X86::VPCMPDZrmik,           0 },
3095     { X86::VPCMPEQBZ128rrk,       X86::VPCMPEQBZ128rmk,       0 },
3096     { X86::VPCMPEQBZ256rrk,       X86::VPCMPEQBZ256rmk,       0 },
3097     { X86::VPCMPEQBZrrk,          X86::VPCMPEQBZrmk,          0 },
3098     { X86::VPCMPEQDZ128rrk,       X86::VPCMPEQDZ128rmk,       0 },
3099     { X86::VPCMPEQDZ256rrk,       X86::VPCMPEQDZ256rmk,       0 },
3100     { X86::VPCMPEQDZrrk,          X86::VPCMPEQDZrmk,          0 },
3101     { X86::VPCMPEQQZ128rrk,       X86::VPCMPEQQZ128rmk,       0 },
3102     { X86::VPCMPEQQZ256rrk,       X86::VPCMPEQQZ256rmk,       0 },
3103     { X86::VPCMPEQQZrrk,          X86::VPCMPEQQZrmk,          0 },
3104     { X86::VPCMPEQWZ128rrk,       X86::VPCMPEQWZ128rmk,       0 },
3105     { X86::VPCMPEQWZ256rrk,       X86::VPCMPEQWZ256rmk,       0 },
3106     { X86::VPCMPEQWZrrk,          X86::VPCMPEQWZrmk,          0 },
3107     { X86::VPCMPGTBZ128rrk,       X86::VPCMPGTBZ128rmk,       0 },
3108     { X86::VPCMPGTBZ256rrk,       X86::VPCMPGTBZ256rmk,       0 },
3109     { X86::VPCMPGTBZrrk,          X86::VPCMPGTBZrmk,          0 },
3110     { X86::VPCMPGTDZ128rrk,       X86::VPCMPGTDZ128rmk,       0 },
3111     { X86::VPCMPGTDZ256rrk,       X86::VPCMPGTDZ256rmk,       0 },
3112     { X86::VPCMPGTDZrrk,          X86::VPCMPGTDZrmk,          0 },
3113     { X86::VPCMPGTQZ128rrk,       X86::VPCMPGTQZ128rmk,       0 },
3114     { X86::VPCMPGTQZ256rrk,       X86::VPCMPGTQZ256rmk,       0 },
3115     { X86::VPCMPGTQZrrk,          X86::VPCMPGTQZrmk,          0 },
3116     { X86::VPCMPGTWZ128rrk,       X86::VPCMPGTWZ128rmk,       0 },
3117     { X86::VPCMPGTWZ256rrk,       X86::VPCMPGTWZ256rmk,       0 },
3118     { X86::VPCMPGTWZrrk,          X86::VPCMPGTWZrmk,          0 },
3119     { X86::VPCMPQZ128rrik,        X86::VPCMPQZ128rmik,        0 },
3120     { X86::VPCMPQZ256rrik,        X86::VPCMPQZ256rmik,        0 },
3121     { X86::VPCMPQZrrik,           X86::VPCMPQZrmik,           0 },
3122     { X86::VPCMPUBZ128rrik,       X86::VPCMPUBZ128rmik,       0 },
3123     { X86::VPCMPUBZ256rrik,       X86::VPCMPUBZ256rmik,       0 },
3124     { X86::VPCMPUBZrrik,          X86::VPCMPUBZrmik,          0 },
3125     { X86::VPCMPUDZ128rrik,       X86::VPCMPUDZ128rmik,       0 },
3126     { X86::VPCMPUDZ256rrik,       X86::VPCMPUDZ256rmik,       0 },
3127     { X86::VPCMPUDZrrik,          X86::VPCMPUDZrmik,          0 },
3128     { X86::VPCMPUQZ128rrik,       X86::VPCMPUQZ128rmik,       0 },
3129     { X86::VPCMPUQZ256rrik,       X86::VPCMPUQZ256rmik,       0 },
3130     { X86::VPCMPUQZrrik,          X86::VPCMPUQZrmik,          0 },
3131     { X86::VPCMPUWZ128rrik,       X86::VPCMPUWZ128rmik,       0 },
3132     { X86::VPCMPUWZ256rrik,       X86::VPCMPUWZ256rmik,       0 },
3133     { X86::VPCMPUWZrrik,          X86::VPCMPUWZrmik,          0 },
3134     { X86::VPCMPWZ128rrik,        X86::VPCMPWZ128rmik,        0 },
3135     { X86::VPCMPWZ256rrik,        X86::VPCMPWZ256rmik,        0 },
3136     { X86::VPCMPWZrrik,           X86::VPCMPWZrmik,           0 },
3137   };
3138 
3139   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
3140     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3141                   Entry.RegOp, Entry.MemOp,
3142                   // Index 3, folded load
3143                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
3144   }
3145   auto I = X86InstrFMA3Info::rm_begin();
3146   auto E = X86InstrFMA3Info::rm_end();
3147   for (; I != E; ++I) {
3148     if (!I.getGroup()->isKMasked()) {
3149       // Intrinsic forms need to pass TB_NO_REVERSE.
3150       if (I.getGroup()->isIntrinsic()) {
3151         AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3152                       I.getRegOpcode(), I.getMemOpcode(),
3153                       TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD | TB_NO_REVERSE);
3154       } else {
3155         AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3156                       I.getRegOpcode(), I.getMemOpcode(),
3157                       TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD);
3158       }
3159     }
3160   }
3161 
3162   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
3163     // AVX-512 foldable masked instructions
3164     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
3165     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
3166     { X86::VADDSDZrr_Intk,     X86::VADDSDZrm_Intk,       TB_NO_REVERSE },
3167     { X86::VADDSSZrr_Intk,     X86::VADDSSZrm_Intk,       TB_NO_REVERSE },
3168     { X86::VALIGNDZrrik,       X86::VALIGNDZrmik,         0 },
3169     { X86::VALIGNQZrrik,       X86::VALIGNQZrmik,         0 },
3170     { X86::VANDNPDZrrk,        X86::VANDNPDZrmk,          0 },
3171     { X86::VANDNPSZrrk,        X86::VANDNPSZrmk,          0 },
3172     { X86::VANDPDZrrk,         X86::VANDPDZrmk,           0 },
3173     { X86::VANDPSZrrk,         X86::VANDPSZrmk,           0 },
3174     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
3175     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
3176     { X86::VDIVSDZrr_Intk,     X86::VDIVSDZrm_Intk,       TB_NO_REVERSE },
3177     { X86::VDIVSSZrr_Intk,     X86::VDIVSSZrm_Intk,       TB_NO_REVERSE },
3178     { X86::VINSERTF32x4Zrrk,   X86::VINSERTF32x4Zrmk,     0 },
3179     { X86::VINSERTF32x8Zrrk,   X86::VINSERTF32x8Zrmk,     0 },
3180     { X86::VINSERTF64x2Zrrk,   X86::VINSERTF64x2Zrmk,     0 },
3181     { X86::VINSERTF64x4Zrrk,   X86::VINSERTF64x4Zrmk,     0 },
3182     { X86::VINSERTI32x4Zrrk,   X86::VINSERTI32x4Zrmk,     0 },
3183     { X86::VINSERTI32x8Zrrk,   X86::VINSERTI32x8Zrmk,     0 },
3184     { X86::VINSERTI64x2Zrrk,   X86::VINSERTI64x2Zrmk,     0 },
3185     { X86::VINSERTI64x4Zrrk,   X86::VINSERTI64x4Zrmk,     0 },
3186     { X86::VMAXCPDZrrk,        X86::VMAXCPDZrmk,          0 },
3187     { X86::VMAXCPSZrrk,        X86::VMAXCPSZrmk,          0 },
3188     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
3189     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
3190     { X86::VMAXSDZrr_Intk,     X86::VMAXSDZrm_Intk,       0 },
3191     { X86::VMAXSSZrr_Intk,     X86::VMAXSSZrm_Intk,       0 },
3192     { X86::VMINCPDZrrk,        X86::VMINCPDZrmk,          0 },
3193     { X86::VMINCPSZrrk,        X86::VMINCPSZrmk,          0 },
3194     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
3195     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
3196     { X86::VMINSDZrr_Intk,     X86::VMINSDZrm_Intk,       0 },
3197     { X86::VMINSSZrr_Intk,     X86::VMINSSZrm_Intk,       0 },
3198     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
3199     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
3200     { X86::VMULSDZrr_Intk,     X86::VMULSDZrm_Intk,       TB_NO_REVERSE },
3201     { X86::VMULSSZrr_Intk,     X86::VMULSSZrm_Intk,       TB_NO_REVERSE },
3202     { X86::VORPDZrrk,          X86::VORPDZrmk,            0 },
3203     { X86::VORPSZrrk,          X86::VORPSZrmk,            0 },
3204     { X86::VPACKSSDWZrrk,      X86::VPACKSSDWZrmk,        0 },
3205     { X86::VPACKSSWBZrrk,      X86::VPACKSSWBZrmk,        0 },
3206     { X86::VPACKUSDWZrrk,      X86::VPACKUSDWZrmk,        0 },
3207     { X86::VPACKUSWBZrrk,      X86::VPACKUSWBZrmk,        0 },
3208     { X86::VPADDBZrrk,         X86::VPADDBZrmk,           0 },
3209     { X86::VPADDDZrrk,         X86::VPADDDZrmk,           0 },
3210     { X86::VPADDQZrrk,         X86::VPADDQZrmk,           0 },
3211     { X86::VPADDSBZrrk,        X86::VPADDSBZrmk,          0 },
3212     { X86::VPADDSWZrrk,        X86::VPADDSWZrmk,          0 },
3213     { X86::VPADDUSBZrrk,       X86::VPADDUSBZrmk,         0 },
3214     { X86::VPADDUSWZrrk,       X86::VPADDUSWZrmk,         0 },
3215     { X86::VPADDWZrrk,         X86::VPADDWZrmk,           0 },
3216     { X86::VPALIGNRZrrik,      X86::VPALIGNRZrmik,        0 },
3217     { X86::VPANDDZrrk,         X86::VPANDDZrmk,           0 },
3218     { X86::VPANDNDZrrk,        X86::VPANDNDZrmk,          0 },
3219     { X86::VPANDNQZrrk,        X86::VPANDNQZrmk,          0 },
3220     { X86::VPANDQZrrk,         X86::VPANDQZrmk,           0 },
3221     { X86::VPAVGBZrrk,         X86::VPAVGBZrmk,           0 },
3222     { X86::VPAVGWZrrk,         X86::VPAVGWZrmk,           0 },
3223     { X86::VPERMBZrrk,         X86::VPERMBZrmk,           0 },
3224     { X86::VPERMDZrrk,         X86::VPERMDZrmk,           0 },
3225     { X86::VPERMI2Brrk,        X86::VPERMI2Brmk,          0 },
3226     { X86::VPERMI2Drrk,        X86::VPERMI2Drmk,          0 },
3227     { X86::VPERMI2PSrrk,       X86::VPERMI2PSrmk,         0 },
3228     { X86::VPERMI2PDrrk,       X86::VPERMI2PDrmk,         0 },
3229     { X86::VPERMI2Qrrk,        X86::VPERMI2Qrmk,          0 },
3230     { X86::VPERMI2Wrrk,        X86::VPERMI2Wrmk,          0 },
3231     { X86::VPERMILPDZrrk,      X86::VPERMILPDZrmk,        0 },
3232     { X86::VPERMILPSZrrk,      X86::VPERMILPSZrmk,        0 },
3233     { X86::VPERMPDZrrk,        X86::VPERMPDZrmk,          0 },
3234     { X86::VPERMPSZrrk,        X86::VPERMPSZrmk,          0 },
3235     { X86::VPERMQZrrk,         X86::VPERMQZrmk,           0 },
3236     { X86::VPERMT2Brrk,        X86::VPERMT2Brmk,          0 },
3237     { X86::VPERMT2Drrk,        X86::VPERMT2Drmk,          0 },
3238     { X86::VPERMT2PSrrk,       X86::VPERMT2PSrmk,         0 },
3239     { X86::VPERMT2PDrrk,       X86::VPERMT2PDrmk,         0 },
3240     { X86::VPERMT2Qrrk,        X86::VPERMT2Qrmk,          0 },
3241     { X86::VPERMT2Wrrk,        X86::VPERMT2Wrmk,          0 },
3242     { X86::VPERMWZrrk,         X86::VPERMWZrmk,           0 },
3243     { X86::VPMADD52HUQZrk,     X86::VPMADD52HUQZmk,       0 },
3244     { X86::VPMADD52LUQZrk,     X86::VPMADD52LUQZmk,       0 },
3245     { X86::VPMADDUBSWZrrk,     X86::VPMADDUBSWZrmk,       0 },
3246     { X86::VPMADDWDZrrk,       X86::VPMADDWDZrmk,         0 },
3247     { X86::VPMAXSBZrrk,        X86::VPMAXSBZrmk,          0 },
3248     { X86::VPMAXSDZrrk,        X86::VPMAXSDZrmk,          0 },
3249     { X86::VPMAXSQZrrk,        X86::VPMAXSQZrmk,          0 },
3250     { X86::VPMAXSWZrrk,        X86::VPMAXSWZrmk,          0 },
3251     { X86::VPMAXUBZrrk,        X86::VPMAXUBZrmk,          0 },
3252     { X86::VPMAXUDZrrk,        X86::VPMAXUDZrmk,          0 },
3253     { X86::VPMAXUQZrrk,        X86::VPMAXUQZrmk,          0 },
3254     { X86::VPMAXUWZrrk,        X86::VPMAXUWZrmk,          0 },
3255     { X86::VPMINSBZrrk,        X86::VPMINSBZrmk,          0 },
3256     { X86::VPMINSDZrrk,        X86::VPMINSDZrmk,          0 },
3257     { X86::VPMINSQZrrk,        X86::VPMINSQZrmk,          0 },
3258     { X86::VPMINSWZrrk,        X86::VPMINSWZrmk,          0 },
3259     { X86::VPMINUBZrrk,        X86::VPMINUBZrmk,          0 },
3260     { X86::VPMINUDZrrk,        X86::VPMINUDZrmk,          0 },
3261     { X86::VPMINUQZrrk,        X86::VPMINUQZrmk,          0 },
3262     { X86::VPMINUWZrrk,        X86::VPMINUWZrmk,          0 },
3263     { X86::VPMULDQZrrk,        X86::VPMULDQZrmk,          0 },
3264     { X86::VPMULLDZrrk,        X86::VPMULLDZrmk,          0 },
3265     { X86::VPMULLQZrrk,        X86::VPMULLQZrmk,          0 },
3266     { X86::VPMULLWZrrk,        X86::VPMULLWZrmk,          0 },
3267     { X86::VPMULUDQZrrk,       X86::VPMULUDQZrmk,         0 },
3268     { X86::VPORDZrrk,          X86::VPORDZrmk,            0 },
3269     { X86::VPORQZrrk,          X86::VPORQZrmk,            0 },
3270     { X86::VPSHUFBZrrk,        X86::VPSHUFBZrmk,          0 },
3271     { X86::VPSLLDZrrk,         X86::VPSLLDZrmk,           0 },
3272     { X86::VPSLLQZrrk,         X86::VPSLLQZrmk,           0 },
3273     { X86::VPSLLVDZrrk,        X86::VPSLLVDZrmk,          0 },
3274     { X86::VPSLLVQZrrk,        X86::VPSLLVQZrmk,          0 },
3275     { X86::VPSLLVWZrrk,        X86::VPSLLVWZrmk,          0 },
3276     { X86::VPSLLWZrrk,         X86::VPSLLWZrmk,           0 },
3277     { X86::VPSRADZrrk,         X86::VPSRADZrmk,           0 },
3278     { X86::VPSRAQZrrk,         X86::VPSRAQZrmk,           0 },
3279     { X86::VPSRAVDZrrk,        X86::VPSRAVDZrmk,          0 },
3280     { X86::VPSRAVQZrrk,        X86::VPSRAVQZrmk,          0 },
3281     { X86::VPSRAVWZrrk,        X86::VPSRAVWZrmk,          0 },
3282     { X86::VPSRAWZrrk,         X86::VPSRAWZrmk,           0 },
3283     { X86::VPSRLDZrrk,         X86::VPSRLDZrmk,           0 },
3284     { X86::VPSRLQZrrk,         X86::VPSRLQZrmk,           0 },
3285     { X86::VPSRLVDZrrk,        X86::VPSRLVDZrmk,          0 },
3286     { X86::VPSRLVQZrrk,        X86::VPSRLVQZrmk,          0 },
3287     { X86::VPSRLVWZrrk,        X86::VPSRLVWZrmk,          0 },
3288     { X86::VPSRLWZrrk,         X86::VPSRLWZrmk,           0 },
3289     { X86::VPSUBBZrrk,         X86::VPSUBBZrmk,           0 },
3290     { X86::VPSUBDZrrk,         X86::VPSUBDZrmk,           0 },
3291     { X86::VPSUBQZrrk,         X86::VPSUBQZrmk,           0 },
3292     { X86::VPSUBSBZrrk,        X86::VPSUBSBZrmk,          0 },
3293     { X86::VPSUBSWZrrk,        X86::VPSUBSWZrmk,          0 },
3294     { X86::VPSUBUSBZrrk,       X86::VPSUBUSBZrmk,         0 },
3295     { X86::VPSUBUSWZrrk,       X86::VPSUBUSWZrmk,         0 },
3296     { X86::VPTERNLOGDZrrik,    X86::VPTERNLOGDZrmik,      0 },
3297     { X86::VPTERNLOGQZrrik,    X86::VPTERNLOGQZrmik,      0 },
3298     { X86::VPUNPCKHBWZrrk,     X86::VPUNPCKHBWZrmk,       0 },
3299     { X86::VPUNPCKHDQZrrk,     X86::VPUNPCKHDQZrmk,       0 },
3300     { X86::VPUNPCKHQDQZrrk,    X86::VPUNPCKHQDQZrmk,      0 },
3301     { X86::VPUNPCKHWDZrrk,     X86::VPUNPCKHWDZrmk,       0 },
3302     { X86::VPUNPCKLBWZrrk,     X86::VPUNPCKLBWZrmk,       0 },
3303     { X86::VPUNPCKLDQZrrk,     X86::VPUNPCKLDQZrmk,       0 },
3304     { X86::VPUNPCKLQDQZrrk,    X86::VPUNPCKLQDQZrmk,      0 },
3305     { X86::VPUNPCKLWDZrrk,     X86::VPUNPCKLWDZrmk,       0 },
3306     { X86::VPXORDZrrk,         X86::VPXORDZrmk,           0 },
3307     { X86::VPXORQZrrk,         X86::VPXORQZrmk,           0 },
3308     { X86::VSHUFPDZrrik,       X86::VSHUFPDZrmik,         0 },
3309     { X86::VSHUFPSZrrik,       X86::VSHUFPSZrmik,         0 },
3310     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
3311     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
3312     { X86::VSUBSDZrr_Intk,     X86::VSUBSDZrm_Intk,       TB_NO_REVERSE },
3313     { X86::VSUBSSZrr_Intk,     X86::VSUBSSZrm_Intk,       TB_NO_REVERSE },
3314     { X86::VUNPCKHPDZrrk,      X86::VUNPCKHPDZrmk,        0 },
3315     { X86::VUNPCKHPSZrrk,      X86::VUNPCKHPSZrmk,        0 },
3316     { X86::VUNPCKLPDZrrk,      X86::VUNPCKLPDZrmk,        0 },
3317     { X86::VUNPCKLPSZrrk,      X86::VUNPCKLPSZrmk,        0 },
3318     { X86::VXORPDZrrk,         X86::VXORPDZrmk,           0 },
3319     { X86::VXORPSZrrk,         X86::VXORPSZrmk,           0 },
3320 
3321     // AVX-512{F,VL} foldable masked instructions 256-bit
3322     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
3323     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
3324     { X86::VALIGNDZ256rrik,    X86::VALIGNDZ256rmik,      0 },
3325     { X86::VALIGNQZ256rrik,    X86::VALIGNQZ256rmik,      0 },
3326     { X86::VANDNPDZ256rrk,     X86::VANDNPDZ256rmk,       0 },
3327     { X86::VANDNPSZ256rrk,     X86::VANDNPSZ256rmk,       0 },
3328     { X86::VANDPDZ256rrk,      X86::VANDPDZ256rmk,        0 },
3329     { X86::VANDPSZ256rrk,      X86::VANDPSZ256rmk,        0 },
3330     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
3331     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
3332     { X86::VINSERTF32x4Z256rrk,X86::VINSERTF32x4Z256rmk,  0 },
3333     { X86::VINSERTF64x2Z256rrk,X86::VINSERTF64x2Z256rmk,  0 },
3334     { X86::VINSERTI32x4Z256rrk,X86::VINSERTI32x4Z256rmk,  0 },
3335     { X86::VINSERTI64x2Z256rrk,X86::VINSERTI64x2Z256rmk,  0 },
3336     { X86::VMAXCPDZ256rrk,     X86::VMAXCPDZ256rmk,       0 },
3337     { X86::VMAXCPSZ256rrk,     X86::VMAXCPSZ256rmk,       0 },
3338     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
3339     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
3340     { X86::VMINCPDZ256rrk,     X86::VMINCPDZ256rmk,       0 },
3341     { X86::VMINCPSZ256rrk,     X86::VMINCPSZ256rmk,       0 },
3342     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
3343     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
3344     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
3345     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
3346     { X86::VORPDZ256rrk,       X86::VORPDZ256rmk,         0 },
3347     { X86::VORPSZ256rrk,       X86::VORPSZ256rmk,         0 },
3348     { X86::VPACKSSDWZ256rrk,   X86::VPACKSSDWZ256rmk,     0 },
3349     { X86::VPACKSSWBZ256rrk,   X86::VPACKSSWBZ256rmk,     0 },
3350     { X86::VPACKUSDWZ256rrk,   X86::VPACKUSDWZ256rmk,     0 },
3351     { X86::VPACKUSWBZ256rrk,   X86::VPACKUSWBZ256rmk,     0 },
3352     { X86::VPADDBZ256rrk,      X86::VPADDBZ256rmk,        0 },
3353     { X86::VPADDDZ256rrk,      X86::VPADDDZ256rmk,        0 },
3354     { X86::VPADDQZ256rrk,      X86::VPADDQZ256rmk,        0 },
3355     { X86::VPADDSBZ256rrk,     X86::VPADDSBZ256rmk,       0 },
3356     { X86::VPADDSWZ256rrk,     X86::VPADDSWZ256rmk,       0 },
3357     { X86::VPADDUSBZ256rrk,    X86::VPADDUSBZ256rmk,      0 },
3358     { X86::VPADDUSWZ256rrk,    X86::VPADDUSWZ256rmk,      0 },
3359     { X86::VPADDWZ256rrk,      X86::VPADDWZ256rmk,        0 },
3360     { X86::VPALIGNRZ256rrik,   X86::VPALIGNRZ256rmik,     0 },
3361     { X86::VPANDDZ256rrk,      X86::VPANDDZ256rmk,        0 },
3362     { X86::VPANDNDZ256rrk,     X86::VPANDNDZ256rmk,       0 },
3363     { X86::VPANDNQZ256rrk,     X86::VPANDNQZ256rmk,       0 },
3364     { X86::VPANDQZ256rrk,      X86::VPANDQZ256rmk,        0 },
3365     { X86::VPAVGBZ256rrk,      X86::VPAVGBZ256rmk,        0 },
3366     { X86::VPAVGWZ256rrk,      X86::VPAVGWZ256rmk,        0 },
3367     { X86::VPERMBZ256rrk,      X86::VPERMBZ256rmk,        0 },
3368     { X86::VPERMDZ256rrk,      X86::VPERMDZ256rmk,        0 },
3369     { X86::VPERMI2B256rrk,     X86::VPERMI2B256rmk,       0 },
3370     { X86::VPERMI2D256rrk,     X86::VPERMI2D256rmk,       0 },
3371     { X86::VPERMI2PD256rrk,    X86::VPERMI2PD256rmk,      0 },
3372     { X86::VPERMI2PS256rrk,    X86::VPERMI2PS256rmk,      0 },
3373     { X86::VPERMI2Q256rrk,     X86::VPERMI2Q256rmk,       0 },
3374     { X86::VPERMI2W256rrk,     X86::VPERMI2W256rmk,       0 },
3375     { X86::VPERMILPDZ256rrk,   X86::VPERMILPDZ256rmk,     0 },
3376     { X86::VPERMILPSZ256rrk,   X86::VPERMILPSZ256rmk,     0 },
3377     { X86::VPERMPDZ256rrk,     X86::VPERMPDZ256rmk,       0 },
3378     { X86::VPERMPSZ256rrk,     X86::VPERMPSZ256rmk,       0 },
3379     { X86::VPERMQZ256rrk,      X86::VPERMQZ256rmk,        0 },
3380     { X86::VPERMT2B256rrk,     X86::VPERMT2B256rmk,       0 },
3381     { X86::VPERMT2D256rrk,     X86::VPERMT2D256rmk,       0 },
3382     { X86::VPERMT2PD256rrk,    X86::VPERMT2PD256rmk,      0 },
3383     { X86::VPERMT2PS256rrk,    X86::VPERMT2PS256rmk,      0 },
3384     { X86::VPERMT2Q256rrk,     X86::VPERMT2Q256rmk,       0 },
3385     { X86::VPERMT2W256rrk,     X86::VPERMT2W256rmk,       0 },
3386     { X86::VPERMWZ256rrk,      X86::VPERMWZ256rmk,        0 },
3387     { X86::VPMADD52HUQZ256rk,  X86::VPMADD52HUQZ256mk,    0 },
3388     { X86::VPMADD52LUQZ256rk,  X86::VPMADD52LUQZ256mk,    0 },
3389     { X86::VPMADDUBSWZ256rrk,  X86::VPMADDUBSWZ256rmk,    0 },
3390     { X86::VPMADDWDZ256rrk,    X86::VPMADDWDZ256rmk,      0 },
3391     { X86::VPMAXSBZ256rrk,     X86::VPMAXSBZ256rmk,       0 },
3392     { X86::VPMAXSDZ256rrk,     X86::VPMAXSDZ256rmk,       0 },
3393     { X86::VPMAXSQZ256rrk,     X86::VPMAXSQZ256rmk,       0 },
3394     { X86::VPMAXSWZ256rrk,     X86::VPMAXSWZ256rmk,       0 },
3395     { X86::VPMAXUBZ256rrk,     X86::VPMAXUBZ256rmk,       0 },
3396     { X86::VPMAXUDZ256rrk,     X86::VPMAXUDZ256rmk,       0 },
3397     { X86::VPMAXUQZ256rrk,     X86::VPMAXUQZ256rmk,       0 },
3398     { X86::VPMAXUWZ256rrk,     X86::VPMAXUWZ256rmk,       0 },
3399     { X86::VPMINSBZ256rrk,     X86::VPMINSBZ256rmk,       0 },
3400     { X86::VPMINSDZ256rrk,     X86::VPMINSDZ256rmk,       0 },
3401     { X86::VPMINSQZ256rrk,     X86::VPMINSQZ256rmk,       0 },
3402     { X86::VPMINSWZ256rrk,     X86::VPMINSWZ256rmk,       0 },
3403     { X86::VPMINUBZ256rrk,     X86::VPMINUBZ256rmk,       0 },
3404     { X86::VPMINUDZ256rrk,     X86::VPMINUDZ256rmk,       0 },
3405     { X86::VPMINUQZ256rrk,     X86::VPMINUQZ256rmk,       0 },
3406     { X86::VPMINUWZ256rrk,     X86::VPMINUWZ256rmk,       0 },
3407     { X86::VPMULDQZ256rrk,     X86::VPMULDQZ256rmk,       0 },
3408     { X86::VPMULLDZ256rrk,     X86::VPMULLDZ256rmk,       0 },
3409     { X86::VPMULLQZ256rrk,     X86::VPMULLQZ256rmk,       0 },
3410     { X86::VPMULLWZ256rrk,     X86::VPMULLWZ256rmk,       0 },
3411     { X86::VPMULUDQZ256rrk,    X86::VPMULUDQZ256rmk,      0 },
3412     { X86::VPORDZ256rrk,       X86::VPORDZ256rmk,         0 },
3413     { X86::VPORQZ256rrk,       X86::VPORQZ256rmk,         0 },
3414     { X86::VPSHUFBZ256rrk,     X86::VPSHUFBZ256rmk,       0 },
3415     { X86::VPSLLDZ256rrk,      X86::VPSLLDZ256rmk,        0 },
3416     { X86::VPSLLQZ256rrk,      X86::VPSLLQZ256rmk,        0 },
3417     { X86::VPSLLVDZ256rrk,     X86::VPSLLVDZ256rmk,       0 },
3418     { X86::VPSLLVQZ256rrk,     X86::VPSLLVQZ256rmk,       0 },
3419     { X86::VPSLLVWZ256rrk,     X86::VPSLLVWZ256rmk,       0 },
3420     { X86::VPSLLWZ256rrk,      X86::VPSLLWZ256rmk,        0 },
3421     { X86::VPSRADZ256rrk,      X86::VPSRADZ256rmk,        0 },
3422     { X86::VPSRAQZ256rrk,      X86::VPSRAQZ256rmk,        0 },
3423     { X86::VPSRAVDZ256rrk,     X86::VPSRAVDZ256rmk,       0 },
3424     { X86::VPSRAVQZ256rrk,     X86::VPSRAVQZ256rmk,       0 },
3425     { X86::VPSRAVWZ256rrk,     X86::VPSRAVWZ256rmk,       0 },
3426     { X86::VPSRAWZ256rrk,      X86::VPSRAWZ256rmk,        0 },
3427     { X86::VPSRLDZ256rrk,      X86::VPSRLDZ256rmk,        0 },
3428     { X86::VPSRLQZ256rrk,      X86::VPSRLQZ256rmk,        0 },
3429     { X86::VPSRLVDZ256rrk,     X86::VPSRLVDZ256rmk,       0 },
3430     { X86::VPSRLVQZ256rrk,     X86::VPSRLVQZ256rmk,       0 },
3431     { X86::VPSRLVWZ256rrk,     X86::VPSRLVWZ256rmk,       0 },
3432     { X86::VPSRLWZ256rrk,      X86::VPSRLWZ256rmk,        0 },
3433     { X86::VPSUBBZ256rrk,      X86::VPSUBBZ256rmk,        0 },
3434     { X86::VPSUBDZ256rrk,      X86::VPSUBDZ256rmk,        0 },
3435     { X86::VPSUBQZ256rrk,      X86::VPSUBQZ256rmk,        0 },
3436     { X86::VPSUBSBZ256rrk,     X86::VPSUBSBZ256rmk,       0 },
3437     { X86::VPSUBSWZ256rrk,     X86::VPSUBSWZ256rmk,       0 },
3438     { X86::VPSUBUSBZ256rrk,    X86::VPSUBUSBZ256rmk,      0 },
3439     { X86::VPSUBUSWZ256rrk,    X86::VPSUBUSWZ256rmk,      0 },
3440     { X86::VPSUBWZ256rrk,      X86::VPSUBWZ256rmk,        0 },
3441     { X86::VPTERNLOGDZ256rrik, X86::VPTERNLOGDZ256rmik,   0 },
3442     { X86::VPTERNLOGQZ256rrik, X86::VPTERNLOGQZ256rmik,   0 },
3443     { X86::VPUNPCKHBWZ256rrk,  X86::VPUNPCKHBWZ256rmk,    0 },
3444     { X86::VPUNPCKHDQZ256rrk,  X86::VPUNPCKHDQZ256rmk,    0 },
3445     { X86::VPUNPCKHQDQZ256rrk, X86::VPUNPCKHQDQZ256rmk,   0 },
3446     { X86::VPUNPCKHWDZ256rrk,  X86::VPUNPCKHWDZ256rmk,    0 },
3447     { X86::VPUNPCKLBWZ256rrk,  X86::VPUNPCKLBWZ256rmk,    0 },
3448     { X86::VPUNPCKLDQZ256rrk,  X86::VPUNPCKLDQZ256rmk,    0 },
3449     { X86::VPUNPCKLQDQZ256rrk, X86::VPUNPCKLQDQZ256rmk,   0 },
3450     { X86::VPUNPCKLWDZ256rrk,  X86::VPUNPCKLWDZ256rmk,    0 },
3451     { X86::VPXORDZ256rrk,      X86::VPXORDZ256rmk,        0 },
3452     { X86::VPXORQZ256rrk,      X86::VPXORQZ256rmk,        0 },
3453     { X86::VSHUFPDZ256rrik,    X86::VSHUFPDZ256rmik,      0 },
3454     { X86::VSHUFPSZ256rrik,    X86::VSHUFPSZ256rmik,      0 },
3455     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
3456     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
3457     { X86::VUNPCKHPDZ256rrk,   X86::VUNPCKHPDZ256rmk,     0 },
3458     { X86::VUNPCKHPSZ256rrk,   X86::VUNPCKHPSZ256rmk,     0 },
3459     { X86::VUNPCKLPDZ256rrk,   X86::VUNPCKLPDZ256rmk,     0 },
3460     { X86::VUNPCKLPSZ256rrk,   X86::VUNPCKLPSZ256rmk,     0 },
3461     { X86::VXORPDZ256rrk,      X86::VXORPDZ256rmk,        0 },
3462     { X86::VXORPSZ256rrk,      X86::VXORPSZ256rmk,        0 },
3463 
3464     // AVX-512{F,VL} foldable instructions 128-bit
3465     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
3466     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
3467     { X86::VALIGNDZ128rrik,    X86::VALIGNDZ128rmik,      0 },
3468     { X86::VALIGNQZ128rrik,    X86::VALIGNQZ128rmik,      0 },
3469     { X86::VANDNPDZ128rrk,     X86::VANDNPDZ128rmk,       0 },
3470     { X86::VANDNPSZ128rrk,     X86::VANDNPSZ128rmk,       0 },
3471     { X86::VANDPDZ128rrk,      X86::VANDPDZ128rmk,        0 },
3472     { X86::VANDPSZ128rrk,      X86::VANDPSZ128rmk,        0 },
3473     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
3474     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
3475     { X86::VMAXCPDZ128rrk,     X86::VMAXCPDZ128rmk,       0 },
3476     { X86::VMAXCPSZ128rrk,     X86::VMAXCPSZ128rmk,       0 },
3477     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 },
3478     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
3479     { X86::VMINCPDZ128rrk,     X86::VMINCPDZ128rmk,       0 },
3480     { X86::VMINCPSZ128rrk,     X86::VMINCPSZ128rmk,       0 },
3481     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
3482     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
3483     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
3484     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
3485     { X86::VORPDZ128rrk,       X86::VORPDZ128rmk,         0 },
3486     { X86::VORPSZ128rrk,       X86::VORPSZ128rmk,         0 },
3487     { X86::VPACKSSDWZ128rrk,   X86::VPACKSSDWZ128rmk,     0 },
3488     { X86::VPACKSSWBZ128rrk,   X86::VPACKSSWBZ128rmk,     0 },
3489     { X86::VPACKUSDWZ128rrk,   X86::VPACKUSDWZ128rmk,     0 },
3490     { X86::VPACKUSWBZ128rrk,   X86::VPACKUSWBZ128rmk,     0 },
3491     { X86::VPADDBZ128rrk,      X86::VPADDBZ128rmk,        0 },
3492     { X86::VPADDDZ128rrk,      X86::VPADDDZ128rmk,        0 },
3493     { X86::VPADDQZ128rrk,      X86::VPADDQZ128rmk,        0 },
3494     { X86::VPADDSBZ128rrk,     X86::VPADDSBZ128rmk,       0 },
3495     { X86::VPADDSWZ128rrk,     X86::VPADDSWZ128rmk,       0 },
3496     { X86::VPADDUSBZ128rrk,    X86::VPADDUSBZ128rmk,      0 },
3497     { X86::VPADDUSWZ128rrk,    X86::VPADDUSWZ128rmk,      0 },
3498     { X86::VPADDWZ128rrk,      X86::VPADDWZ128rmk,        0 },
3499     { X86::VPALIGNRZ128rrik,   X86::VPALIGNRZ128rmik,     0 },
3500     { X86::VPANDDZ128rrk,      X86::VPANDDZ128rmk,        0 },
3501     { X86::VPANDNDZ128rrk,     X86::VPANDNDZ128rmk,       0 },
3502     { X86::VPANDNQZ128rrk,     X86::VPANDNQZ128rmk,       0 },
3503     { X86::VPANDQZ128rrk,      X86::VPANDQZ128rmk,        0 },
3504     { X86::VPAVGBZ128rrk,      X86::VPAVGBZ128rmk,        0 },
3505     { X86::VPAVGWZ128rrk,      X86::VPAVGWZ128rmk,        0 },
3506     { X86::VPERMBZ128rrk,      X86::VPERMBZ128rmk,        0 },
3507     { X86::VPERMI2B128rrk,     X86::VPERMI2B128rmk,       0 },
3508     { X86::VPERMI2D128rrk,     X86::VPERMI2D128rmk,       0 },
3509     { X86::VPERMI2PD128rrk,    X86::VPERMI2PD128rmk,      0 },
3510     { X86::VPERMI2PS128rrk,    X86::VPERMI2PS128rmk,      0 },
3511     { X86::VPERMI2Q128rrk,     X86::VPERMI2Q128rmk,       0 },
3512     { X86::VPERMI2W128rrk,     X86::VPERMI2W128rmk,       0 },
3513     { X86::VPERMILPDZ128rrk,   X86::VPERMILPDZ128rmk,     0 },
3514     { X86::VPERMILPSZ128rrk,   X86::VPERMILPSZ128rmk,     0 },
3515     { X86::VPERMT2B128rrk,     X86::VPERMT2B128rmk,       0 },
3516     { X86::VPERMT2D128rrk,     X86::VPERMT2D128rmk,       0 },
3517     { X86::VPERMT2PD128rrk,    X86::VPERMT2PD128rmk,      0 },
3518     { X86::VPERMT2PS128rrk,    X86::VPERMT2PS128rmk,      0 },
3519     { X86::VPERMT2Q128rrk,     X86::VPERMT2Q128rmk,       0 },
3520     { X86::VPERMT2W128rrk,     X86::VPERMT2W128rmk,       0 },
3521     { X86::VPERMWZ128rrk,      X86::VPERMWZ128rmk,        0 },
3522     { X86::VPMADD52HUQZ128rk,  X86::VPMADD52HUQZ128mk,    0 },
3523     { X86::VPMADD52LUQZ128rk,  X86::VPMADD52LUQZ128mk,    0 },
3524     { X86::VPMADDUBSWZ128rrk,  X86::VPMADDUBSWZ128rmk,    0 },
3525     { X86::VPMADDWDZ128rrk,    X86::VPMADDWDZ128rmk,      0 },
3526     { X86::VPMAXSBZ128rrk,     X86::VPMAXSBZ128rmk,       0 },
3527     { X86::VPMAXSDZ128rrk,     X86::VPMAXSDZ128rmk,       0 },
3528     { X86::VPMAXSQZ128rrk,     X86::VPMAXSQZ128rmk,       0 },
3529     { X86::VPMAXSWZ128rrk,     X86::VPMAXSWZ128rmk,       0 },
3530     { X86::VPMAXUBZ128rrk,     X86::VPMAXUBZ128rmk,       0 },
3531     { X86::VPMAXUDZ128rrk,     X86::VPMAXUDZ128rmk,       0 },
3532     { X86::VPMAXUQZ128rrk,     X86::VPMAXUQZ128rmk,       0 },
3533     { X86::VPMAXUWZ128rrk,     X86::VPMAXUWZ128rmk,       0 },
3534     { X86::VPMINSBZ128rrk,     X86::VPMINSBZ128rmk,       0 },
3535     { X86::VPMINSDZ128rrk,     X86::VPMINSDZ128rmk,       0 },
3536     { X86::VPMINSQZ128rrk,     X86::VPMINSQZ128rmk,       0 },
3537     { X86::VPMINSWZ128rrk,     X86::VPMINSWZ128rmk,       0 },
3538     { X86::VPMINUBZ128rrk,     X86::VPMINUBZ128rmk,       0 },
3539     { X86::VPMINUDZ128rrk,     X86::VPMINUDZ128rmk,       0 },
3540     { X86::VPMINUQZ128rrk,     X86::VPMINUQZ128rmk,       0 },
3541     { X86::VPMINUWZ128rrk,     X86::VPMINUWZ128rmk,       0 },
3542     { X86::VPMULDQZ128rrk,     X86::VPMULDQZ128rmk,       0 },
3543     { X86::VPMULLDZ128rrk,     X86::VPMULLDZ128rmk,       0 },
3544     { X86::VPMULLQZ128rrk,     X86::VPMULLQZ128rmk,       0 },
3545     { X86::VPMULLWZ128rrk,     X86::VPMULLWZ128rmk,       0 },
3546     { X86::VPMULUDQZ128rrk,    X86::VPMULUDQZ128rmk,      0 },
3547     { X86::VPORDZ128rrk,       X86::VPORDZ128rmk,         0 },
3548     { X86::VPORQZ128rrk,       X86::VPORQZ128rmk,         0 },
3549     { X86::VPSHUFBZ128rrk,     X86::VPSHUFBZ128rmk,       0 },
3550     { X86::VPSLLDZ128rrk,      X86::VPSLLDZ128rmk,        0 },
3551     { X86::VPSLLQZ128rrk,      X86::VPSLLQZ128rmk,        0 },
3552     { X86::VPSLLVDZ128rrk,     X86::VPSLLVDZ128rmk,       0 },
3553     { X86::VPSLLVQZ128rrk,     X86::VPSLLVQZ128rmk,       0 },
3554     { X86::VPSLLVWZ128rrk,     X86::VPSLLVWZ128rmk,       0 },
3555     { X86::VPSLLWZ128rrk,      X86::VPSLLWZ128rmk,        0 },
3556     { X86::VPSRADZ128rrk,      X86::VPSRADZ128rmk,        0 },
3557     { X86::VPSRAQZ128rrk,      X86::VPSRAQZ128rmk,        0 },
3558     { X86::VPSRAVDZ128rrk,     X86::VPSRAVDZ128rmk,       0 },
3559     { X86::VPSRAVQZ128rrk,     X86::VPSRAVQZ128rmk,       0 },
3560     { X86::VPSRAVWZ128rrk,     X86::VPSRAVWZ128rmk,       0 },
3561     { X86::VPSRAWZ128rrk,      X86::VPSRAWZ128rmk,        0 },
3562     { X86::VPSRLDZ128rrk,      X86::VPSRLDZ128rmk,        0 },
3563     { X86::VPSRLQZ128rrk,      X86::VPSRLQZ128rmk,        0 },
3564     { X86::VPSRLVDZ128rrk,     X86::VPSRLVDZ128rmk,       0 },
3565     { X86::VPSRLVQZ128rrk,     X86::VPSRLVQZ128rmk,       0 },
3566     { X86::VPSRLVWZ128rrk,     X86::VPSRLVWZ128rmk,       0 },
3567     { X86::VPSRLWZ128rrk,      X86::VPSRLWZ128rmk,        0 },
3568     { X86::VPSUBBZ128rrk,      X86::VPSUBBZ128rmk,        0 },
3569     { X86::VPSUBDZ128rrk,      X86::VPSUBDZ128rmk,        0 },
3570     { X86::VPSUBQZ128rrk,      X86::VPSUBQZ128rmk,        0 },
3571     { X86::VPSUBSBZ128rrk,     X86::VPSUBSBZ128rmk,       0 },
3572     { X86::VPSUBSWZ128rrk,     X86::VPSUBSWZ128rmk,       0 },
3573     { X86::VPSUBUSBZ128rrk,    X86::VPSUBUSBZ128rmk,      0 },
3574     { X86::VPSUBUSWZ128rrk,    X86::VPSUBUSWZ128rmk,      0 },
3575     { X86::VPSUBWZ128rrk,      X86::VPSUBWZ128rmk,        0 },
3576     { X86::VPTERNLOGDZ128rrik, X86::VPTERNLOGDZ128rmik,   0 },
3577     { X86::VPTERNLOGQZ128rrik, X86::VPTERNLOGQZ128rmik,   0 },
3578     { X86::VPUNPCKHBWZ128rrk,  X86::VPUNPCKHBWZ128rmk,    0 },
3579     { X86::VPUNPCKHDQZ128rrk,  X86::VPUNPCKHDQZ128rmk,    0 },
3580     { X86::VPUNPCKHQDQZ128rrk, X86::VPUNPCKHQDQZ128rmk,   0 },
3581     { X86::VPUNPCKHWDZ128rrk,  X86::VPUNPCKHWDZ128rmk,    0 },
3582     { X86::VPUNPCKLBWZ128rrk,  X86::VPUNPCKLBWZ128rmk,    0 },
3583     { X86::VPUNPCKLDQZ128rrk,  X86::VPUNPCKLDQZ128rmk,    0 },
3584     { X86::VPUNPCKLQDQZ128rrk, X86::VPUNPCKLQDQZ128rmk,   0 },
3585     { X86::VPUNPCKLWDZ128rrk,  X86::VPUNPCKLWDZ128rmk,    0 },
3586     { X86::VPXORDZ128rrk,      X86::VPXORDZ128rmk,        0 },
3587     { X86::VPXORQZ128rrk,      X86::VPXORQZ128rmk,        0 },
3588     { X86::VSHUFPDZ128rrik,    X86::VSHUFPDZ128rmik,      0 },
3589     { X86::VSHUFPSZ128rrik,    X86::VSHUFPSZ128rmik,      0 },
3590     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
3591     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
3592     { X86::VUNPCKHPDZ128rrk,   X86::VUNPCKHPDZ128rmk,     0 },
3593     { X86::VUNPCKHPSZ128rrk,   X86::VUNPCKHPSZ128rmk,     0 },
3594     { X86::VUNPCKLPDZ128rrk,   X86::VUNPCKLPDZ128rmk,     0 },
3595     { X86::VUNPCKLPSZ128rrk,   X86::VUNPCKLPSZ128rmk,     0 },
3596     { X86::VXORPDZ128rrk,      X86::VXORPDZ128rmk,        0 },
3597     { X86::VXORPSZ128rrk,      X86::VXORPSZ128rmk,        0 },
3598 
3599     // 512-bit three source instructions with zero masking.
3600     { X86::VPERMI2Brrkz,       X86::VPERMI2Brmkz,         0 },
3601     { X86::VPERMI2Drrkz,       X86::VPERMI2Drmkz,         0 },
3602     { X86::VPERMI2PSrrkz,      X86::VPERMI2PSrmkz,        0 },
3603     { X86::VPERMI2PDrrkz,      X86::VPERMI2PDrmkz,        0 },
3604     { X86::VPERMI2Qrrkz,       X86::VPERMI2Qrmkz,         0 },
3605     { X86::VPERMI2Wrrkz,       X86::VPERMI2Wrmkz,         0 },
3606     { X86::VPERMT2Brrkz,       X86::VPERMT2Brmkz,         0 },
3607     { X86::VPERMT2Drrkz,       X86::VPERMT2Drmkz,         0 },
3608     { X86::VPERMT2PSrrkz,      X86::VPERMT2PSrmkz,        0 },
3609     { X86::VPERMT2PDrrkz,      X86::VPERMT2PDrmkz,        0 },
3610     { X86::VPERMT2Qrrkz,       X86::VPERMT2Qrmkz,         0 },
3611     { X86::VPERMT2Wrrkz,       X86::VPERMT2Wrmkz,         0 },
3612     { X86::VPMADD52HUQZrkz,    X86::VPMADD52HUQZmkz,      0 },
3613     { X86::VPMADD52LUQZrkz,    X86::VPMADD52LUQZmkz,      0 },
3614     { X86::VPTERNLOGDZrrikz,   X86::VPTERNLOGDZrmikz,     0 },
3615     { X86::VPTERNLOGQZrrikz,   X86::VPTERNLOGQZrmikz,     0 },
3616 
3617     // 256-bit three source instructions with zero masking.
3618     { X86::VPERMI2B256rrkz,    X86::VPERMI2B256rmkz,      0 },
3619     { X86::VPERMI2D256rrkz,    X86::VPERMI2D256rmkz,      0 },
3620     { X86::VPERMI2PD256rrkz,   X86::VPERMI2PD256rmkz,     0 },
3621     { X86::VPERMI2PS256rrkz,   X86::VPERMI2PS256rmkz,     0 },
3622     { X86::VPERMI2Q256rrkz,    X86::VPERMI2Q256rmkz,      0 },
3623     { X86::VPERMI2W256rrkz,    X86::VPERMI2W256rmkz,      0 },
3624     { X86::VPERMT2B256rrkz,    X86::VPERMT2B256rmkz,      0 },
3625     { X86::VPERMT2D256rrkz,    X86::VPERMT2D256rmkz,      0 },
3626     { X86::VPERMT2PD256rrkz,   X86::VPERMT2PD256rmkz,     0 },
3627     { X86::VPERMT2PS256rrkz,   X86::VPERMT2PS256rmkz,     0 },
3628     { X86::VPERMT2Q256rrkz,    X86::VPERMT2Q256rmkz,      0 },
3629     { X86::VPERMT2W256rrkz,    X86::VPERMT2W256rmkz,      0 },
3630     { X86::VPMADD52HUQZ256rkz, X86::VPMADD52HUQZ256mkz,   0 },
3631     { X86::VPMADD52LUQZ256rkz, X86::VPMADD52LUQZ256mkz,   0 },
3632     { X86::VPTERNLOGDZ256rrikz,X86::VPTERNLOGDZ256rmikz,  0 },
3633     { X86::VPTERNLOGQZ256rrikz,X86::VPTERNLOGQZ256rmikz,  0 },
3634 
3635     // 128-bit three source instructions with zero masking.
3636     { X86::VPERMI2B128rrkz,    X86::VPERMI2B128rmkz,      0 },
3637     { X86::VPERMI2D128rrkz,    X86::VPERMI2D128rmkz,      0 },
3638     { X86::VPERMI2PD128rrkz,   X86::VPERMI2PD128rmkz,     0 },
3639     { X86::VPERMI2PS128rrkz,   X86::VPERMI2PS128rmkz,     0 },
3640     { X86::VPERMI2Q128rrkz,    X86::VPERMI2Q128rmkz,      0 },
3641     { X86::VPERMI2W128rrkz,    X86::VPERMI2W128rmkz,      0 },
3642     { X86::VPERMT2B128rrkz,    X86::VPERMT2B128rmkz,      0 },
3643     { X86::VPERMT2D128rrkz,    X86::VPERMT2D128rmkz,      0 },
3644     { X86::VPERMT2PD128rrkz,   X86::VPERMT2PD128rmkz,     0 },
3645     { X86::VPERMT2PS128rrkz,   X86::VPERMT2PS128rmkz,     0 },
3646     { X86::VPERMT2Q128rrkz,    X86::VPERMT2Q128rmkz,      0 },
3647     { X86::VPERMT2W128rrkz,    X86::VPERMT2W128rmkz,      0 },
3648     { X86::VPMADD52HUQZ128rkz, X86::VPMADD52HUQZ128mkz,   0 },
3649     { X86::VPMADD52LUQZ128rkz, X86::VPMADD52LUQZ128mkz,   0 },
3650     { X86::VPTERNLOGDZ128rrikz,X86::VPTERNLOGDZ128rmikz,  0 },
3651     { X86::VPTERNLOGQZ128rrikz,X86::VPTERNLOGQZ128rmikz,  0 },
3652   };
3653 
3654   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
3655     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3656                   Entry.RegOp, Entry.MemOp,
3657                   // Index 4, folded load
3658                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
3659   }
3660   for (I = X86InstrFMA3Info::rm_begin(); I != E; ++I) {
3661     if (I.getGroup()->isKMasked()) {
3662       // Intrinsics need to pass TB_NO_REVERSE.
3663       if (I.getGroup()->isIntrinsic()) {
3664         AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3665                       I.getRegOpcode(), I.getMemOpcode(),
3666                       TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD | TB_NO_REVERSE);
3667       } else {
3668         AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3669                       I.getRegOpcode(), I.getMemOpcode(),
3670                       TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD);
3671       }
3672     }
3673   }
3674 }
3675 
3676 void
3677 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
3678                             MemOp2RegOpTableType &M2RTable,
3679                             uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
3680   if ((Flags & TB_NO_FORWARD) == 0) {
3681     assert(!R2MTable.count(RegOp) && "Duplicate entry!");
3682     R2MTable[RegOp] = std::make_pair(MemOp, Flags);
3683   }
3684   if ((Flags & TB_NO_REVERSE) == 0) {
3685     assert(!M2RTable.count(MemOp) &&
3686          "Duplicated entries in unfolding maps?");
3687     M2RTable[MemOp] = std::make_pair(RegOp, Flags);
3688   }
3689 }
3690 
3691 bool
3692 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
3693                                     unsigned &SrcReg, unsigned &DstReg,
3694                                     unsigned &SubIdx) const {
3695   switch (MI.getOpcode()) {
3696   default: break;
3697   case X86::MOVSX16rr8:
3698   case X86::MOVZX16rr8:
3699   case X86::MOVSX32rr8:
3700   case X86::MOVZX32rr8:
3701   case X86::MOVSX64rr8:
3702     if (!Subtarget.is64Bit())
3703       // It's not always legal to reference the low 8-bit of the larger
3704       // register in 32-bit mode.
3705       return false;
3706     LLVM_FALLTHROUGH;
3707   case X86::MOVSX32rr16:
3708   case X86::MOVZX32rr16:
3709   case X86::MOVSX64rr16:
3710   case X86::MOVSX64rr32: {
3711     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
3712       // Be conservative.
3713       return false;
3714     SrcReg = MI.getOperand(1).getReg();
3715     DstReg = MI.getOperand(0).getReg();
3716     switch (MI.getOpcode()) {
3717     default: llvm_unreachable("Unreachable!");
3718     case X86::MOVSX16rr8:
3719     case X86::MOVZX16rr8:
3720     case X86::MOVSX32rr8:
3721     case X86::MOVZX32rr8:
3722     case X86::MOVSX64rr8:
3723       SubIdx = X86::sub_8bit;
3724       break;
3725     case X86::MOVSX32rr16:
3726     case X86::MOVZX32rr16:
3727     case X86::MOVSX64rr16:
3728       SubIdx = X86::sub_16bit;
3729       break;
3730     case X86::MOVSX64rr32:
3731       SubIdx = X86::sub_32bit;
3732       break;
3733     }
3734     return true;
3735   }
3736   }
3737   return false;
3738 }
3739 
3740 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
3741   const MachineFunction *MF = MI.getParent()->getParent();
3742   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
3743 
3744   if (isFrameInstr(MI)) {
3745     unsigned StackAlign = TFI->getStackAlignment();
3746     int SPAdj = alignTo(getFrameSize(MI), StackAlign);
3747     SPAdj -= getFrameAdjustment(MI);
3748     if (!isFrameSetup(MI))
3749       SPAdj = -SPAdj;
3750     return SPAdj;
3751   }
3752 
3753   // To know whether a call adjusts the stack, we need information
3754   // that is bound to the following ADJCALLSTACKUP pseudo.
3755   // Look for the next ADJCALLSTACKUP that follows the call.
3756   if (MI.isCall()) {
3757     const MachineBasicBlock *MBB = MI.getParent();
3758     auto I = ++MachineBasicBlock::const_iterator(MI);
3759     for (auto E = MBB->end(); I != E; ++I) {
3760       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
3761           I->isCall())
3762         break;
3763     }
3764 
3765     // If we could not find a frame destroy opcode, then it has already
3766     // been simplified, so we don't care.
3767     if (I->getOpcode() != getCallFrameDestroyOpcode())
3768       return 0;
3769 
3770     return -(I->getOperand(1).getImm());
3771   }
3772 
3773   // Currently handle only PUSHes we can reasonably expect to see
3774   // in call sequences
3775   switch (MI.getOpcode()) {
3776   default:
3777     return 0;
3778   case X86::PUSH32i8:
3779   case X86::PUSH32r:
3780   case X86::PUSH32rmm:
3781   case X86::PUSH32rmr:
3782   case X86::PUSHi32:
3783     return 4;
3784   case X86::PUSH64i8:
3785   case X86::PUSH64r:
3786   case X86::PUSH64rmm:
3787   case X86::PUSH64rmr:
3788   case X86::PUSH64i32:
3789     return 8;
3790   }
3791 }
3792 
3793 /// Return true and the FrameIndex if the specified
3794 /// operand and follow operands form a reference to the stack frame.
3795 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
3796                                   int &FrameIndex) const {
3797   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
3798       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
3799       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
3800       MI.getOperand(Op + X86::AddrDisp).isImm() &&
3801       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
3802       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
3803       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
3804     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
3805     return true;
3806   }
3807   return false;
3808 }
3809 
3810 static bool isFrameLoadOpcode(int Opcode) {
3811   switch (Opcode) {
3812   default:
3813     return false;
3814   case X86::MOV8rm:
3815   case X86::MOV16rm:
3816   case X86::MOV32rm:
3817   case X86::MOV64rm:
3818   case X86::LD_Fp64m:
3819   case X86::MOVSSrm:
3820   case X86::MOVSDrm:
3821   case X86::MOVAPSrm:
3822   case X86::MOVUPSrm:
3823   case X86::MOVAPDrm:
3824   case X86::MOVUPDrm:
3825   case X86::MOVDQArm:
3826   case X86::MOVDQUrm:
3827   case X86::VMOVSSrm:
3828   case X86::VMOVSDrm:
3829   case X86::VMOVAPSrm:
3830   case X86::VMOVUPSrm:
3831   case X86::VMOVAPDrm:
3832   case X86::VMOVUPDrm:
3833   case X86::VMOVDQArm:
3834   case X86::VMOVDQUrm:
3835   case X86::VMOVUPSYrm:
3836   case X86::VMOVAPSYrm:
3837   case X86::VMOVUPDYrm:
3838   case X86::VMOVAPDYrm:
3839   case X86::VMOVDQUYrm:
3840   case X86::VMOVDQAYrm:
3841   case X86::MMX_MOVD64rm:
3842   case X86::MMX_MOVQ64rm:
3843   case X86::VMOVSSZrm:
3844   case X86::VMOVSDZrm:
3845   case X86::VMOVAPSZrm:
3846   case X86::VMOVAPSZ128rm:
3847   case X86::VMOVAPSZ256rm:
3848   case X86::VMOVAPSZ128rm_NOVLX:
3849   case X86::VMOVAPSZ256rm_NOVLX:
3850   case X86::VMOVUPSZrm:
3851   case X86::VMOVUPSZ128rm:
3852   case X86::VMOVUPSZ256rm:
3853   case X86::VMOVUPSZ128rm_NOVLX:
3854   case X86::VMOVUPSZ256rm_NOVLX:
3855   case X86::VMOVAPDZrm:
3856   case X86::VMOVAPDZ128rm:
3857   case X86::VMOVAPDZ256rm:
3858   case X86::VMOVUPDZrm:
3859   case X86::VMOVUPDZ128rm:
3860   case X86::VMOVUPDZ256rm:
3861   case X86::VMOVDQA32Zrm:
3862   case X86::VMOVDQA32Z128rm:
3863   case X86::VMOVDQA32Z256rm:
3864   case X86::VMOVDQU32Zrm:
3865   case X86::VMOVDQU32Z128rm:
3866   case X86::VMOVDQU32Z256rm:
3867   case X86::VMOVDQA64Zrm:
3868   case X86::VMOVDQA64Z128rm:
3869   case X86::VMOVDQA64Z256rm:
3870   case X86::VMOVDQU64Zrm:
3871   case X86::VMOVDQU64Z128rm:
3872   case X86::VMOVDQU64Z256rm:
3873   case X86::VMOVDQU8Zrm:
3874   case X86::VMOVDQU8Z128rm:
3875   case X86::VMOVDQU8Z256rm:
3876   case X86::VMOVDQU16Zrm:
3877   case X86::VMOVDQU16Z128rm:
3878   case X86::VMOVDQU16Z256rm:
3879   case X86::KMOVBkm:
3880   case X86::KMOVWkm:
3881   case X86::KMOVDkm:
3882   case X86::KMOVQkm:
3883     return true;
3884   }
3885 }
3886 
3887 static bool isFrameStoreOpcode(int Opcode) {
3888   switch (Opcode) {
3889   default: break;
3890   case X86::MOV8mr:
3891   case X86::MOV16mr:
3892   case X86::MOV32mr:
3893   case X86::MOV64mr:
3894   case X86::ST_FpP64m:
3895   case X86::MOVSSmr:
3896   case X86::MOVSDmr:
3897   case X86::MOVAPSmr:
3898   case X86::MOVUPSmr:
3899   case X86::MOVAPDmr:
3900   case X86::MOVUPDmr:
3901   case X86::MOVDQAmr:
3902   case X86::MOVDQUmr:
3903   case X86::VMOVSSmr:
3904   case X86::VMOVSDmr:
3905   case X86::VMOVAPSmr:
3906   case X86::VMOVUPSmr:
3907   case X86::VMOVAPDmr:
3908   case X86::VMOVUPDmr:
3909   case X86::VMOVDQAmr:
3910   case X86::VMOVDQUmr:
3911   case X86::VMOVUPSYmr:
3912   case X86::VMOVAPSYmr:
3913   case X86::VMOVUPDYmr:
3914   case X86::VMOVAPDYmr:
3915   case X86::VMOVDQUYmr:
3916   case X86::VMOVDQAYmr:
3917   case X86::VMOVSSZmr:
3918   case X86::VMOVSDZmr:
3919   case X86::VMOVUPSZmr:
3920   case X86::VMOVUPSZ128mr:
3921   case X86::VMOVUPSZ256mr:
3922   case X86::VMOVUPSZ128mr_NOVLX:
3923   case X86::VMOVUPSZ256mr_NOVLX:
3924   case X86::VMOVAPSZmr:
3925   case X86::VMOVAPSZ128mr:
3926   case X86::VMOVAPSZ256mr:
3927   case X86::VMOVAPSZ128mr_NOVLX:
3928   case X86::VMOVAPSZ256mr_NOVLX:
3929   case X86::VMOVUPDZmr:
3930   case X86::VMOVUPDZ128mr:
3931   case X86::VMOVUPDZ256mr:
3932   case X86::VMOVAPDZmr:
3933   case X86::VMOVAPDZ128mr:
3934   case X86::VMOVAPDZ256mr:
3935   case X86::VMOVDQA32Zmr:
3936   case X86::VMOVDQA32Z128mr:
3937   case X86::VMOVDQA32Z256mr:
3938   case X86::VMOVDQU32Zmr:
3939   case X86::VMOVDQU32Z128mr:
3940   case X86::VMOVDQU32Z256mr:
3941   case X86::VMOVDQA64Zmr:
3942   case X86::VMOVDQA64Z128mr:
3943   case X86::VMOVDQA64Z256mr:
3944   case X86::VMOVDQU64Zmr:
3945   case X86::VMOVDQU64Z128mr:
3946   case X86::VMOVDQU64Z256mr:
3947   case X86::VMOVDQU8Zmr:
3948   case X86::VMOVDQU8Z128mr:
3949   case X86::VMOVDQU8Z256mr:
3950   case X86::VMOVDQU16Zmr:
3951   case X86::VMOVDQU16Z128mr:
3952   case X86::VMOVDQU16Z256mr:
3953   case X86::MMX_MOVD64mr:
3954   case X86::MMX_MOVQ64mr:
3955   case X86::MMX_MOVNTQmr:
3956   case X86::KMOVBmk:
3957   case X86::KMOVWmk:
3958   case X86::KMOVDmk:
3959   case X86::KMOVQmk:
3960     return true;
3961   }
3962   return false;
3963 }
3964 
3965 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
3966                                            int &FrameIndex) const {
3967   if (isFrameLoadOpcode(MI.getOpcode()))
3968     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
3969       return MI.getOperand(0).getReg();
3970   return 0;
3971 }
3972 
3973 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
3974                                                  int &FrameIndex) const {
3975   if (isFrameLoadOpcode(MI.getOpcode())) {
3976     unsigned Reg;
3977     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
3978       return Reg;
3979     // Check for post-frame index elimination operations
3980     const MachineMemOperand *Dummy;
3981     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
3982   }
3983   return 0;
3984 }
3985 
3986 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
3987                                           int &FrameIndex) const {
3988   if (isFrameStoreOpcode(MI.getOpcode()))
3989     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
3990         isFrameOperand(MI, 0, FrameIndex))
3991       return MI.getOperand(X86::AddrNumOperands).getReg();
3992   return 0;
3993 }
3994 
3995 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
3996                                                 int &FrameIndex) const {
3997   if (isFrameStoreOpcode(MI.getOpcode())) {
3998     unsigned Reg;
3999     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
4000       return Reg;
4001     // Check for post-frame index elimination operations
4002     const MachineMemOperand *Dummy;
4003     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
4004   }
4005   return 0;
4006 }
4007 
4008 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
4009 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
4010   // Don't waste compile time scanning use-def chains of physregs.
4011   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
4012     return false;
4013   bool isPICBase = false;
4014   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
4015          E = MRI.def_instr_end(); I != E; ++I) {
4016     MachineInstr *DefMI = &*I;
4017     if (DefMI->getOpcode() != X86::MOVPC32r)
4018       return false;
4019     assert(!isPICBase && "More than one PIC base?");
4020     isPICBase = true;
4021   }
4022   return isPICBase;
4023 }
4024 
4025 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
4026                                                      AliasAnalysis *AA) const {
4027   switch (MI.getOpcode()) {
4028   default: break;
4029   case X86::MOV8rm:
4030   case X86::MOV8rm_NOREX:
4031   case X86::MOV16rm:
4032   case X86::MOV32rm:
4033   case X86::MOV64rm:
4034   case X86::LD_Fp64m:
4035   case X86::MOVSSrm:
4036   case X86::MOVSDrm:
4037   case X86::MOVAPSrm:
4038   case X86::MOVUPSrm:
4039   case X86::MOVAPDrm:
4040   case X86::MOVUPDrm:
4041   case X86::MOVDQArm:
4042   case X86::MOVDQUrm:
4043   case X86::VMOVSSrm:
4044   case X86::VMOVSDrm:
4045   case X86::VMOVAPSrm:
4046   case X86::VMOVUPSrm:
4047   case X86::VMOVAPDrm:
4048   case X86::VMOVUPDrm:
4049   case X86::VMOVDQArm:
4050   case X86::VMOVDQUrm:
4051   case X86::VMOVAPSYrm:
4052   case X86::VMOVUPSYrm:
4053   case X86::VMOVAPDYrm:
4054   case X86::VMOVUPDYrm:
4055   case X86::VMOVDQAYrm:
4056   case X86::VMOVDQUYrm:
4057   case X86::MMX_MOVD64rm:
4058   case X86::MMX_MOVQ64rm:
4059   // AVX-512
4060   case X86::VMOVSSZrm:
4061   case X86::VMOVSDZrm:
4062   case X86::VMOVAPDZ128rm:
4063   case X86::VMOVAPDZ256rm:
4064   case X86::VMOVAPDZrm:
4065   case X86::VMOVAPSZ128rm:
4066   case X86::VMOVAPSZ256rm:
4067   case X86::VMOVAPSZ128rm_NOVLX:
4068   case X86::VMOVAPSZ256rm_NOVLX:
4069   case X86::VMOVAPSZrm:
4070   case X86::VMOVDQA32Z128rm:
4071   case X86::VMOVDQA32Z256rm:
4072   case X86::VMOVDQA32Zrm:
4073   case X86::VMOVDQA64Z128rm:
4074   case X86::VMOVDQA64Z256rm:
4075   case X86::VMOVDQA64Zrm:
4076   case X86::VMOVDQU16Z128rm:
4077   case X86::VMOVDQU16Z256rm:
4078   case X86::VMOVDQU16Zrm:
4079   case X86::VMOVDQU32Z128rm:
4080   case X86::VMOVDQU32Z256rm:
4081   case X86::VMOVDQU32Zrm:
4082   case X86::VMOVDQU64Z128rm:
4083   case X86::VMOVDQU64Z256rm:
4084   case X86::VMOVDQU64Zrm:
4085   case X86::VMOVDQU8Z128rm:
4086   case X86::VMOVDQU8Z256rm:
4087   case X86::VMOVDQU8Zrm:
4088   case X86::VMOVUPDZ128rm:
4089   case X86::VMOVUPDZ256rm:
4090   case X86::VMOVUPDZrm:
4091   case X86::VMOVUPSZ128rm:
4092   case X86::VMOVUPSZ256rm:
4093   case X86::VMOVUPSZ128rm_NOVLX:
4094   case X86::VMOVUPSZ256rm_NOVLX:
4095   case X86::VMOVUPSZrm: {
4096     // Loads from constant pools are trivially rematerializable.
4097     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
4098         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
4099         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
4100         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
4101         MI.isDereferenceableInvariantLoad(AA)) {
4102       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
4103       if (BaseReg == 0 || BaseReg == X86::RIP)
4104         return true;
4105       // Allow re-materialization of PIC load.
4106       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
4107         return false;
4108       const MachineFunction &MF = *MI.getParent()->getParent();
4109       const MachineRegisterInfo &MRI = MF.getRegInfo();
4110       return regIsPICBase(BaseReg, MRI);
4111     }
4112     return false;
4113   }
4114 
4115   case X86::LEA32r:
4116   case X86::LEA64r: {
4117     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
4118         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
4119         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
4120         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
4121       // lea fi#, lea GV, etc. are all rematerializable.
4122       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
4123         return true;
4124       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
4125       if (BaseReg == 0)
4126         return true;
4127       // Allow re-materialization of lea PICBase + x.
4128       const MachineFunction &MF = *MI.getParent()->getParent();
4129       const MachineRegisterInfo &MRI = MF.getRegInfo();
4130       return regIsPICBase(BaseReg, MRI);
4131     }
4132     return false;
4133   }
4134   }
4135 
4136   // All other instructions marked M_REMATERIALIZABLE are always trivially
4137   // rematerializable.
4138   return true;
4139 }
4140 
4141 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
4142                                          MachineBasicBlock::iterator I) const {
4143   MachineBasicBlock::iterator E = MBB.end();
4144 
4145   // For compile time consideration, if we are not able to determine the
4146   // safety after visiting 4 instructions in each direction, we will assume
4147   // it's not safe.
4148   MachineBasicBlock::iterator Iter = I;
4149   for (unsigned i = 0; Iter != E && i < 4; ++i) {
4150     bool SeenDef = false;
4151     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
4152       MachineOperand &MO = Iter->getOperand(j);
4153       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
4154         SeenDef = true;
4155       if (!MO.isReg())
4156         continue;
4157       if (MO.getReg() == X86::EFLAGS) {
4158         if (MO.isUse())
4159           return false;
4160         SeenDef = true;
4161       }
4162     }
4163 
4164     if (SeenDef)
4165       // This instruction defines EFLAGS, no need to look any further.
4166       return true;
4167     ++Iter;
4168     // Skip over DBG_VALUE.
4169     while (Iter != E && Iter->isDebugValue())
4170       ++Iter;
4171   }
4172 
4173   // It is safe to clobber EFLAGS at the end of a block of no successor has it
4174   // live in.
4175   if (Iter == E) {
4176     for (MachineBasicBlock *S : MBB.successors())
4177       if (S->isLiveIn(X86::EFLAGS))
4178         return false;
4179     return true;
4180   }
4181 
4182   MachineBasicBlock::iterator B = MBB.begin();
4183   Iter = I;
4184   for (unsigned i = 0; i < 4; ++i) {
4185     // If we make it to the beginning of the block, it's safe to clobber
4186     // EFLAGS iff EFLAGS is not live-in.
4187     if (Iter == B)
4188       return !MBB.isLiveIn(X86::EFLAGS);
4189 
4190     --Iter;
4191     // Skip over DBG_VALUE.
4192     while (Iter != B && Iter->isDebugValue())
4193       --Iter;
4194 
4195     bool SawKill = false;
4196     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
4197       MachineOperand &MO = Iter->getOperand(j);
4198       // A register mask may clobber EFLAGS, but we should still look for a
4199       // live EFLAGS def.
4200       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
4201         SawKill = true;
4202       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
4203         if (MO.isDef()) return MO.isDead();
4204         if (MO.isKill()) SawKill = true;
4205       }
4206     }
4207 
4208     if (SawKill)
4209       // This instruction kills EFLAGS and doesn't redefine it, so
4210       // there's no need to look further.
4211       return true;
4212   }
4213 
4214   // Conservative answer.
4215   return false;
4216 }
4217 
4218 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
4219                                  MachineBasicBlock::iterator I,
4220                                  unsigned DestReg, unsigned SubIdx,
4221                                  const MachineInstr &Orig,
4222                                  const TargetRegisterInfo &TRI) const {
4223   bool ClobbersEFLAGS = false;
4224   for (const MachineOperand &MO : Orig.operands()) {
4225     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4226       ClobbersEFLAGS = true;
4227       break;
4228     }
4229   }
4230 
4231   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
4232     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
4233     // effects.
4234     int Value;
4235     switch (Orig.getOpcode()) {
4236     case X86::MOV32r0:  Value = 0; break;
4237     case X86::MOV32r1:  Value = 1; break;
4238     case X86::MOV32r_1: Value = -1; break;
4239     default:
4240       llvm_unreachable("Unexpected instruction!");
4241     }
4242 
4243     const DebugLoc &DL = Orig.getDebugLoc();
4244     BuildMI(MBB, I, DL, get(X86::MOV32ri))
4245         .add(Orig.getOperand(0))
4246         .addImm(Value);
4247   } else {
4248     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
4249     MBB.insert(I, MI);
4250   }
4251 
4252   MachineInstr &NewMI = *std::prev(I);
4253   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
4254 }
4255 
4256 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
4257 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
4258   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4259     MachineOperand &MO = MI.getOperand(i);
4260     if (MO.isReg() && MO.isDef() &&
4261         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
4262       return true;
4263     }
4264   }
4265   return false;
4266 }
4267 
4268 /// Check whether the shift count for a machine operand is non-zero.
4269 inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
4270                                               unsigned ShiftAmtOperandIdx) {
4271   // The shift count is six bits with the REX.W prefix and five bits without.
4272   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
4273   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
4274   return Imm & ShiftCountMask;
4275 }
4276 
4277 /// Check whether the given shift count is appropriate
4278 /// can be represented by a LEA instruction.
4279 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
4280   // Left shift instructions can be transformed into load-effective-address
4281   // instructions if we can encode them appropriately.
4282   // A LEA instruction utilizes a SIB byte to encode its scale factor.
4283   // The SIB.scale field is two bits wide which means that we can encode any
4284   // shift amount less than 4.
4285   return ShAmt < 4 && ShAmt > 0;
4286 }
4287 
4288 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
4289                                   unsigned Opc, bool AllowSP, unsigned &NewSrc,
4290                                   bool &isKill, bool &isUndef,
4291                                   MachineOperand &ImplicitOp,
4292                                   LiveVariables *LV) const {
4293   MachineFunction &MF = *MI.getParent()->getParent();
4294   const TargetRegisterClass *RC;
4295   if (AllowSP) {
4296     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
4297   } else {
4298     RC = Opc != X86::LEA32r ?
4299       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
4300   }
4301   unsigned SrcReg = Src.getReg();
4302 
4303   // For both LEA64 and LEA32 the register already has essentially the right
4304   // type (32-bit or 64-bit) we may just need to forbid SP.
4305   if (Opc != X86::LEA64_32r) {
4306     NewSrc = SrcReg;
4307     isKill = Src.isKill();
4308     isUndef = Src.isUndef();
4309 
4310     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
4311         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
4312       return false;
4313 
4314     return true;
4315   }
4316 
4317   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
4318   // another we need to add 64-bit registers to the final MI.
4319   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
4320     ImplicitOp = Src;
4321     ImplicitOp.setImplicit();
4322 
4323     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
4324     isKill = Src.isKill();
4325     isUndef = Src.isUndef();
4326   } else {
4327     // Virtual register of the wrong class, we have to create a temporary 64-bit
4328     // vreg to feed into the LEA.
4329     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
4330     MachineInstr *Copy =
4331         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4332             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
4333             .add(Src);
4334 
4335     // Which is obviously going to be dead after we're done with it.
4336     isKill = true;
4337     isUndef = false;
4338 
4339     if (LV)
4340       LV->replaceKillInstruction(SrcReg, MI, *Copy);
4341   }
4342 
4343   // We've set all the parameters without issue.
4344   return true;
4345 }
4346 
4347 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
4348 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
4349 /// truncating back down to a 16-bit subregister.
4350 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
4351     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
4352     LiveVariables *LV) const {
4353   MachineBasicBlock::iterator MBBI = MI.getIterator();
4354   unsigned Dest = MI.getOperand(0).getReg();
4355   unsigned Src = MI.getOperand(1).getReg();
4356   bool isDead = MI.getOperand(0).isDead();
4357   bool isKill = MI.getOperand(1).isKill();
4358 
4359   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
4360   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
4361   unsigned Opc, leaInReg;
4362   if (Subtarget.is64Bit()) {
4363     Opc = X86::LEA64_32r;
4364     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
4365   } else {
4366     Opc = X86::LEA32r;
4367     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4368   }
4369 
4370   // Build and insert into an implicit UNDEF value. This is OK because
4371   // well be shifting and then extracting the lower 16-bits.
4372   // This has the potential to cause partial register stall. e.g.
4373   //   movw    (%rbp,%rcx,2), %dx
4374   //   leal    -65(%rdx), %esi
4375   // But testing has shown this *does* help performance in 64-bit mode (at
4376   // least on modern x86 machines).
4377   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
4378   MachineInstr *InsMI =
4379       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4380           .addReg(leaInReg, RegState::Define, X86::sub_16bit)
4381           .addReg(Src, getKillRegState(isKill));
4382 
4383   MachineInstrBuilder MIB =
4384       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
4385   switch (MIOpc) {
4386   default: llvm_unreachable("Unreachable!");
4387   case X86::SHL16ri: {
4388     unsigned ShAmt = MI.getOperand(2).getImm();
4389     MIB.addReg(0).addImm(1ULL << ShAmt)
4390        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
4391     break;
4392   }
4393   case X86::INC16r:
4394     addRegOffset(MIB, leaInReg, true, 1);
4395     break;
4396   case X86::DEC16r:
4397     addRegOffset(MIB, leaInReg, true, -1);
4398     break;
4399   case X86::ADD16ri:
4400   case X86::ADD16ri8:
4401   case X86::ADD16ri_DB:
4402   case X86::ADD16ri8_DB:
4403     addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
4404     break;
4405   case X86::ADD16rr:
4406   case X86::ADD16rr_DB: {
4407     unsigned Src2 = MI.getOperand(2).getReg();
4408     bool isKill2 = MI.getOperand(2).isKill();
4409     unsigned leaInReg2 = 0;
4410     MachineInstr *InsMI2 = nullptr;
4411     if (Src == Src2) {
4412       // ADD16rr %reg1028<kill>, %reg1028
4413       // just a single insert_subreg.
4414       addRegReg(MIB, leaInReg, true, leaInReg, false);
4415     } else {
4416       if (Subtarget.is64Bit())
4417         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
4418       else
4419         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4420       // Build and insert into an implicit UNDEF value. This is OK because
4421       // well be shifting and then extracting the lower 16-bits.
4422       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
4423       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
4424                    .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
4425                    .addReg(Src2, getKillRegState(isKill2));
4426       addRegReg(MIB, leaInReg, true, leaInReg2, true);
4427     }
4428     if (LV && isKill2 && InsMI2)
4429       LV->replaceKillInstruction(Src2, MI, *InsMI2);
4430     break;
4431   }
4432   }
4433 
4434   MachineInstr *NewMI = MIB;
4435   MachineInstr *ExtMI =
4436       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4437           .addReg(Dest, RegState::Define | getDeadRegState(isDead))
4438           .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
4439 
4440   if (LV) {
4441     // Update live variables
4442     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
4443     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
4444     if (isKill)
4445       LV->replaceKillInstruction(Src, MI, *InsMI);
4446     if (isDead)
4447       LV->replaceKillInstruction(Dest, MI, *ExtMI);
4448   }
4449 
4450   return ExtMI;
4451 }
4452 
4453 /// This method must be implemented by targets that
4454 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
4455 /// may be able to convert a two-address instruction into a true
4456 /// three-address instruction on demand.  This allows the X86 target (for
4457 /// example) to convert ADD and SHL instructions into LEA instructions if they
4458 /// would require register copies due to two-addressness.
4459 ///
4460 /// This method returns a null pointer if the transformation cannot be
4461 /// performed, otherwise it returns the new instruction.
4462 ///
4463 MachineInstr *
4464 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
4465                                     MachineInstr &MI, LiveVariables *LV) const {
4466   // The following opcodes also sets the condition code register(s). Only
4467   // convert them to equivalent lea if the condition code register def's
4468   // are dead!
4469   if (hasLiveCondCodeDef(MI))
4470     return nullptr;
4471 
4472   MachineFunction &MF = *MI.getParent()->getParent();
4473   // All instructions input are two-addr instructions.  Get the known operands.
4474   const MachineOperand &Dest = MI.getOperand(0);
4475   const MachineOperand &Src = MI.getOperand(1);
4476 
4477   MachineInstr *NewMI = nullptr;
4478   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
4479   // we have better subtarget support, enable the 16-bit LEA generation here.
4480   // 16-bit LEA is also slow on Core2.
4481   bool DisableLEA16 = true;
4482   bool is64Bit = Subtarget.is64Bit();
4483 
4484   unsigned MIOpc = MI.getOpcode();
4485   switch (MIOpc) {
4486   default: return nullptr;
4487   case X86::SHL64ri: {
4488     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
4489     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4490     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4491 
4492     // LEA can't handle RSP.
4493     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
4494         !MF.getRegInfo().constrainRegClass(Src.getReg(),
4495                                            &X86::GR64_NOSPRegClass))
4496       return nullptr;
4497 
4498     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
4499                 .add(Dest)
4500                 .addReg(0)
4501                 .addImm(1ULL << ShAmt)
4502                 .add(Src)
4503                 .addImm(0)
4504                 .addReg(0);
4505     break;
4506   }
4507   case X86::SHL32ri: {
4508     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
4509     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4510     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4511 
4512     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4513 
4514     // LEA can't handle ESP.
4515     bool isKill, isUndef;
4516     unsigned SrcReg;
4517     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4518     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4519                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4520       return nullptr;
4521 
4522     MachineInstrBuilder MIB =
4523         BuildMI(MF, MI.getDebugLoc(), get(Opc))
4524             .add(Dest)
4525             .addReg(0)
4526             .addImm(1ULL << ShAmt)
4527             .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
4528             .addImm(0)
4529             .addReg(0);
4530     if (ImplicitOp.getReg() != 0)
4531       MIB.add(ImplicitOp);
4532     NewMI = MIB;
4533 
4534     break;
4535   }
4536   case X86::SHL16ri: {
4537     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
4538     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4539     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4540 
4541     if (DisableLEA16)
4542       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4543                      : nullptr;
4544     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
4545                 .add(Dest)
4546                 .addReg(0)
4547                 .addImm(1ULL << ShAmt)
4548                 .add(Src)
4549                 .addImm(0)
4550                 .addReg(0);
4551     break;
4552   }
4553   case X86::INC64r:
4554   case X86::INC32r: {
4555     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
4556     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
4557       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
4558     bool isKill, isUndef;
4559     unsigned SrcReg;
4560     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4561     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4562                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4563       return nullptr;
4564 
4565     MachineInstrBuilder MIB =
4566         BuildMI(MF, MI.getDebugLoc(), get(Opc))
4567             .add(Dest)
4568             .addReg(SrcReg,
4569                     getKillRegState(isKill) | getUndefRegState(isUndef));
4570     if (ImplicitOp.getReg() != 0)
4571       MIB.add(ImplicitOp);
4572 
4573     NewMI = addOffset(MIB, 1);
4574     break;
4575   }
4576   case X86::INC16r:
4577     if (DisableLEA16)
4578       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4579                      : nullptr;
4580     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
4581     NewMI = addOffset(
4582         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), 1);
4583     break;
4584   case X86::DEC64r:
4585   case X86::DEC32r: {
4586     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
4587     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
4588       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
4589 
4590     bool isKill, isUndef;
4591     unsigned SrcReg;
4592     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4593     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4594                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4595       return nullptr;
4596 
4597     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4598                                   .add(Dest)
4599                                   .addReg(SrcReg, getUndefRegState(isUndef) |
4600                                                       getKillRegState(isKill));
4601     if (ImplicitOp.getReg() != 0)
4602       MIB.add(ImplicitOp);
4603 
4604     NewMI = addOffset(MIB, -1);
4605 
4606     break;
4607   }
4608   case X86::DEC16r:
4609     if (DisableLEA16)
4610       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4611                      : nullptr;
4612     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
4613     NewMI = addOffset(
4614         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), -1);
4615     break;
4616   case X86::ADD64rr:
4617   case X86::ADD64rr_DB:
4618   case X86::ADD32rr:
4619   case X86::ADD32rr_DB: {
4620     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4621     unsigned Opc;
4622     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
4623       Opc = X86::LEA64r;
4624     else
4625       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4626 
4627     bool isKill, isUndef;
4628     unsigned SrcReg;
4629     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4630     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
4631                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4632       return nullptr;
4633 
4634     const MachineOperand &Src2 = MI.getOperand(2);
4635     bool isKill2, isUndef2;
4636     unsigned SrcReg2;
4637     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
4638     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
4639                         SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
4640       return nullptr;
4641 
4642     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
4643     if (ImplicitOp.getReg() != 0)
4644       MIB.add(ImplicitOp);
4645     if (ImplicitOp2.getReg() != 0)
4646       MIB.add(ImplicitOp2);
4647 
4648     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
4649 
4650     // Preserve undefness of the operands.
4651     NewMI->getOperand(1).setIsUndef(isUndef);
4652     NewMI->getOperand(3).setIsUndef(isUndef2);
4653 
4654     if (LV && Src2.isKill())
4655       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
4656     break;
4657   }
4658   case X86::ADD16rr:
4659   case X86::ADD16rr_DB: {
4660     if (DisableLEA16)
4661       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4662                      : nullptr;
4663     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4664     unsigned Src2 = MI.getOperand(2).getReg();
4665     bool isKill2 = MI.getOperand(2).isKill();
4666     NewMI = addRegReg(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest),
4667                       Src.getReg(), Src.isKill(), Src2, isKill2);
4668 
4669     // Preserve undefness of the operands.
4670     bool isUndef = MI.getOperand(1).isUndef();
4671     bool isUndef2 = MI.getOperand(2).isUndef();
4672     NewMI->getOperand(1).setIsUndef(isUndef);
4673     NewMI->getOperand(3).setIsUndef(isUndef2);
4674 
4675     if (LV && isKill2)
4676       LV->replaceKillInstruction(Src2, MI, *NewMI);
4677     break;
4678   }
4679   case X86::ADD64ri32:
4680   case X86::ADD64ri8:
4681   case X86::ADD64ri32_DB:
4682   case X86::ADD64ri8_DB:
4683     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4684     NewMI = addOffset(
4685         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
4686         MI.getOperand(2));
4687     break;
4688   case X86::ADD32ri:
4689   case X86::ADD32ri8:
4690   case X86::ADD32ri_DB:
4691   case X86::ADD32ri8_DB: {
4692     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4693     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4694 
4695     bool isKill, isUndef;
4696     unsigned SrcReg;
4697     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4698     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
4699                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4700       return nullptr;
4701 
4702     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4703                                   .add(Dest)
4704                                   .addReg(SrcReg, getUndefRegState(isUndef) |
4705                                                       getKillRegState(isKill));
4706     if (ImplicitOp.getReg() != 0)
4707       MIB.add(ImplicitOp);
4708 
4709     NewMI = addOffset(MIB, MI.getOperand(2));
4710     break;
4711   }
4712   case X86::ADD16ri:
4713   case X86::ADD16ri8:
4714   case X86::ADD16ri_DB:
4715   case X86::ADD16ri8_DB:
4716     if (DisableLEA16)
4717       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4718                      : nullptr;
4719     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4720     NewMI = addOffset(
4721         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src),
4722         MI.getOperand(2));
4723     break;
4724 
4725   case X86::VMOVDQU8Z128rmk:
4726   case X86::VMOVDQU8Z256rmk:
4727   case X86::VMOVDQU8Zrmk:
4728   case X86::VMOVDQU16Z128rmk:
4729   case X86::VMOVDQU16Z256rmk:
4730   case X86::VMOVDQU16Zrmk:
4731   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
4732   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
4733   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
4734   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
4735   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
4736   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
4737   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
4738   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
4739   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
4740   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
4741   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
4742   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk: {
4743     unsigned Opc;
4744     switch (MIOpc) {
4745     default: llvm_unreachable("Unreachable!");
4746     case X86::VMOVDQU8Z128rmk:  Opc = X86::VPBLENDMBZ128rmk; break;
4747     case X86::VMOVDQU8Z256rmk:  Opc = X86::VPBLENDMBZ256rmk; break;
4748     case X86::VMOVDQU8Zrmk:     Opc = X86::VPBLENDMBZrmk;    break;
4749     case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
4750     case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
4751     case X86::VMOVDQU16Zrmk:    Opc = X86::VPBLENDMWZrmk;    break;
4752     case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
4753     case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
4754     case X86::VMOVDQU32Zrmk:    Opc = X86::VPBLENDMDZrmk;    break;
4755     case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
4756     case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
4757     case X86::VMOVDQU64Zrmk:    Opc = X86::VPBLENDMQZrmk;    break;
4758     case X86::VMOVUPDZ128rmk:   Opc = X86::VBLENDMPDZ128rmk; break;
4759     case X86::VMOVUPDZ256rmk:   Opc = X86::VBLENDMPDZ256rmk; break;
4760     case X86::VMOVUPDZrmk:      Opc = X86::VBLENDMPDZrmk;    break;
4761     case X86::VMOVUPSZ128rmk:   Opc = X86::VBLENDMPSZ128rmk; break;
4762     case X86::VMOVUPSZ256rmk:   Opc = X86::VBLENDMPSZ256rmk; break;
4763     case X86::VMOVUPSZrmk:      Opc = X86::VBLENDMPSZrmk;    break;
4764     case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
4765     case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
4766     case X86::VMOVDQA32Zrmk:    Opc = X86::VPBLENDMDZrmk;    break;
4767     case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
4768     case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
4769     case X86::VMOVDQA64Zrmk:    Opc = X86::VPBLENDMQZrmk;    break;
4770     case X86::VMOVAPDZ128rmk:   Opc = X86::VBLENDMPDZ128rmk; break;
4771     case X86::VMOVAPDZ256rmk:   Opc = X86::VBLENDMPDZ256rmk; break;
4772     case X86::VMOVAPDZrmk:      Opc = X86::VBLENDMPDZrmk;    break;
4773     case X86::VMOVAPSZ128rmk:   Opc = X86::VBLENDMPSZ128rmk; break;
4774     case X86::VMOVAPSZ256rmk:   Opc = X86::VBLENDMPSZ256rmk; break;
4775     case X86::VMOVAPSZrmk:      Opc = X86::VBLENDMPSZrmk;    break;
4776     }
4777 
4778     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4779               .add(Dest)
4780               .add(MI.getOperand(2))
4781               .add(Src)
4782               .add(MI.getOperand(3))
4783               .add(MI.getOperand(4))
4784               .add(MI.getOperand(5))
4785               .add(MI.getOperand(6))
4786               .add(MI.getOperand(7));
4787     break;
4788   }
4789   case X86::VMOVDQU8Z128rrk:
4790   case X86::VMOVDQU8Z256rrk:
4791   case X86::VMOVDQU8Zrrk:
4792   case X86::VMOVDQU16Z128rrk:
4793   case X86::VMOVDQU16Z256rrk:
4794   case X86::VMOVDQU16Zrrk:
4795   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
4796   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
4797   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
4798   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
4799   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
4800   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
4801   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
4802   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
4803   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
4804   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
4805   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
4806   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
4807     unsigned Opc;
4808     switch (MIOpc) {
4809     default: llvm_unreachable("Unreachable!");
4810     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
4811     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
4812     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
4813     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
4814     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
4815     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
4816     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
4817     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
4818     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
4819     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
4820     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
4821     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
4822     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
4823     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
4824     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
4825     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
4826     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
4827     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
4828     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
4829     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
4830     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
4831     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
4832     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
4833     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
4834     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
4835     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
4836     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
4837     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
4838     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
4839     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
4840     }
4841 
4842     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4843               .add(Dest)
4844               .add(MI.getOperand(2))
4845               .add(Src)
4846               .add(MI.getOperand(3));
4847     break;
4848   }
4849   }
4850 
4851   if (!NewMI) return nullptr;
4852 
4853   if (LV) {  // Update live variables
4854     if (Src.isKill())
4855       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
4856     if (Dest.isDead())
4857       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
4858   }
4859 
4860   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
4861   return NewMI;
4862 }
4863 
4864 /// This determines which of three possible cases of a three source commute
4865 /// the source indexes correspond to taking into account any mask operands.
4866 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
4867 /// possible.
4868 /// Case 0 - Possible to commute the first and second operands.
4869 /// Case 1 - Possible to commute the first and third operands.
4870 /// Case 2 - Possible to commute the second and third operands.
4871 static int getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
4872                                   unsigned SrcOpIdx2) {
4873   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
4874   if (SrcOpIdx1 > SrcOpIdx2)
4875     std::swap(SrcOpIdx1, SrcOpIdx2);
4876 
4877   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
4878   if (X86II::isKMasked(TSFlags)) {
4879     // The k-mask operand cannot be commuted.
4880     if (SrcOpIdx1 == 2)
4881       return -1;
4882 
4883     // For k-zero-masked operations it is Ok to commute the first vector
4884     // operand.
4885     // For regular k-masked operations a conservative choice is done as the
4886     // elements of the first vector operand, for which the corresponding bit
4887     // in the k-mask operand is set to 0, are copied to the result of the
4888     // instruction.
4889     // TODO/FIXME: The commute still may be legal if it is known that the
4890     // k-mask operand is set to either all ones or all zeroes.
4891     // It is also Ok to commute the 1st operand if all users of MI use only
4892     // the elements enabled by the k-mask operand. For example,
4893     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
4894     //                                                     : v1[i];
4895     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
4896     //                                  // Ok, to commute v1 in FMADD213PSZrk.
4897     if (X86II::isKMergeMasked(TSFlags) && SrcOpIdx1 == Op1)
4898       return -1;
4899     Op2++;
4900     Op3++;
4901   }
4902 
4903   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
4904     return 0;
4905   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
4906     return 1;
4907   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
4908     return 2;
4909   return -1;
4910 }
4911 
4912 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
4913     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
4914     const X86InstrFMA3Group &FMA3Group) const {
4915 
4916   unsigned Opc = MI.getOpcode();
4917 
4918   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
4919   if (SrcOpIdx1 > SrcOpIdx2)
4920     std::swap(SrcOpIdx1, SrcOpIdx2);
4921 
4922   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
4923   // analysis. The commute optimization is legal only if all users of FMA*_Int
4924   // use only the lowest element of the FMA*_Int instruction. Such analysis are
4925   // not implemented yet. So, just return 0 in that case.
4926   // When such analysis are available this place will be the right place for
4927   // calling it.
4928   if (FMA3Group.isIntrinsic() && SrcOpIdx1 == 1)
4929     return 0;
4930 
4931   // Determine which case this commute is or if it can't be done.
4932   int Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
4933   if (Case < 0)
4934     return 0;
4935 
4936   // Define the FMA forms mapping array that helps to map input FMA form
4937   // to output FMA form to preserve the operation semantics after
4938   // commuting the operands.
4939   const unsigned Form132Index = 0;
4940   const unsigned Form213Index = 1;
4941   const unsigned Form231Index = 2;
4942   static const unsigned FormMapping[][3] = {
4943     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
4944     // FMA132 A, C, b; ==> FMA231 C, A, b;
4945     // FMA213 B, A, c; ==> FMA213 A, B, c;
4946     // FMA231 C, A, b; ==> FMA132 A, C, b;
4947     { Form231Index, Form213Index, Form132Index },
4948     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
4949     // FMA132 A, c, B; ==> FMA132 B, c, A;
4950     // FMA213 B, a, C; ==> FMA231 C, a, B;
4951     // FMA231 C, a, B; ==> FMA213 B, a, C;
4952     { Form132Index, Form231Index, Form213Index },
4953     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
4954     // FMA132 a, C, B; ==> FMA213 a, B, C;
4955     // FMA213 b, A, C; ==> FMA132 b, C, A;
4956     // FMA231 c, A, B; ==> FMA231 c, B, A;
4957     { Form213Index, Form132Index, Form231Index }
4958   };
4959 
4960   unsigned FMAForms[3];
4961   if (FMA3Group.isRegOpcodeFromGroup(Opc)) {
4962     FMAForms[0] = FMA3Group.getReg132Opcode();
4963     FMAForms[1] = FMA3Group.getReg213Opcode();
4964     FMAForms[2] = FMA3Group.getReg231Opcode();
4965   } else {
4966     FMAForms[0] = FMA3Group.getMem132Opcode();
4967     FMAForms[1] = FMA3Group.getMem213Opcode();
4968     FMAForms[2] = FMA3Group.getMem231Opcode();
4969   }
4970   unsigned FormIndex;
4971   for (FormIndex = 0; FormIndex < 3; FormIndex++)
4972     if (Opc == FMAForms[FormIndex])
4973       break;
4974 
4975   // Everything is ready, just adjust the FMA opcode and return it.
4976   FormIndex = FormMapping[Case][FormIndex];
4977   return FMAForms[FormIndex];
4978 }
4979 
4980 static bool commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
4981                              unsigned SrcOpIdx2) {
4982   uint64_t TSFlags = MI.getDesc().TSFlags;
4983 
4984   // Determine which case this commute is or if it can't be done.
4985   int Case = getThreeSrcCommuteCase(TSFlags, SrcOpIdx1, SrcOpIdx2);
4986   if (Case < 0)
4987     return false;
4988 
4989   // For each case we need to swap two pairs of bits in the final immediate.
4990   static const uint8_t SwapMasks[3][4] = {
4991     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
4992     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
4993     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
4994   };
4995 
4996   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
4997   // Clear out the bits we are swapping.
4998   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
4999                            SwapMasks[Case][2] | SwapMasks[Case][3]);
5000   // If the immediate had a bit of the pair set, then set the opposite bit.
5001   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
5002   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
5003   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
5004   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
5005   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
5006 
5007   return true;
5008 }
5009 
5010 // Returns true if this is a VPERMI2 or VPERMT2 instrution that can be
5011 // commuted.
5012 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
5013 #define VPERM_CASES(Suffix) \
5014   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
5015   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
5016   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
5017   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
5018   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
5019   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
5020   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
5021   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
5022   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
5023   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
5024   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
5025   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
5026 
5027 #define VPERM_CASES_BROADCAST(Suffix) \
5028   VPERM_CASES(Suffix) \
5029   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
5030   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
5031   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
5032   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
5033   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
5034   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
5035 
5036   switch (Opcode) {
5037   default: return false;
5038   VPERM_CASES(B)
5039   VPERM_CASES_BROADCAST(D)
5040   VPERM_CASES_BROADCAST(PD)
5041   VPERM_CASES_BROADCAST(PS)
5042   VPERM_CASES_BROADCAST(Q)
5043   VPERM_CASES(W)
5044     return true;
5045   }
5046 #undef VPERM_CASES_BROADCAST
5047 #undef VPERM_CASES
5048 }
5049 
5050 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
5051 // from the I opcod to the T opcode and vice versa.
5052 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
5053 #define VPERM_CASES(Orig, New) \
5054   case X86::Orig##128rr:    return X86::New##128rr;   \
5055   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
5056   case X86::Orig##128rm:    return X86::New##128rm;   \
5057   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
5058   case X86::Orig##256rr:    return X86::New##256rr;   \
5059   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
5060   case X86::Orig##256rm:    return X86::New##256rm;   \
5061   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
5062   case X86::Orig##rr:       return X86::New##rr;      \
5063   case X86::Orig##rrkz:     return X86::New##rrkz;    \
5064   case X86::Orig##rm:       return X86::New##rm;      \
5065   case X86::Orig##rmkz:     return X86::New##rmkz;
5066 
5067 #define VPERM_CASES_BROADCAST(Orig, New) \
5068   VPERM_CASES(Orig, New) \
5069   case X86::Orig##128rmb:   return X86::New##128rmb;   \
5070   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
5071   case X86::Orig##256rmb:   return X86::New##256rmb;   \
5072   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
5073   case X86::Orig##rmb:      return X86::New##rmb;      \
5074   case X86::Orig##rmbkz:    return X86::New##rmbkz;
5075 
5076   switch (Opcode) {
5077   VPERM_CASES(VPERMI2B, VPERMT2B)
5078   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
5079   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
5080   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
5081   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
5082   VPERM_CASES(VPERMI2W, VPERMT2W)
5083   VPERM_CASES(VPERMT2B, VPERMI2B)
5084   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
5085   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
5086   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
5087   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
5088   VPERM_CASES(VPERMT2W, VPERMI2W)
5089   }
5090 
5091   llvm_unreachable("Unreachable!");
5092 #undef VPERM_CASES_BROADCAST
5093 #undef VPERM_CASES
5094 }
5095 
5096 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
5097                                                    unsigned OpIdx1,
5098                                                    unsigned OpIdx2) const {
5099   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
5100     if (NewMI)
5101       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
5102     return MI;
5103   };
5104 
5105   switch (MI.getOpcode()) {
5106   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
5107   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
5108   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
5109   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
5110   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
5111   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
5112     unsigned Opc;
5113     unsigned Size;
5114     switch (MI.getOpcode()) {
5115     default: llvm_unreachable("Unreachable!");
5116     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
5117     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
5118     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
5119     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
5120     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
5121     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
5122     }
5123     unsigned Amt = MI.getOperand(3).getImm();
5124     auto &WorkingMI = cloneIfNew(MI);
5125     WorkingMI.setDesc(get(Opc));
5126     WorkingMI.getOperand(3).setImm(Size - Amt);
5127     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5128                                                    OpIdx1, OpIdx2);
5129   }
5130   case X86::PFSUBrr:
5131   case X86::PFSUBRrr: {
5132     // PFSUB  x, y: x = x - y
5133     // PFSUBR x, y: x = y - x
5134     unsigned Opc =
5135         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
5136     auto &WorkingMI = cloneIfNew(MI);
5137     WorkingMI.setDesc(get(Opc));
5138     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5139                                                    OpIdx1, OpIdx2);
5140     break;
5141   }
5142   case X86::BLENDPDrri:
5143   case X86::BLENDPSrri:
5144   case X86::PBLENDWrri:
5145   case X86::VBLENDPDrri:
5146   case X86::VBLENDPSrri:
5147   case X86::VBLENDPDYrri:
5148   case X86::VBLENDPSYrri:
5149   case X86::VPBLENDDrri:
5150   case X86::VPBLENDWrri:
5151   case X86::VPBLENDDYrri:
5152   case X86::VPBLENDWYrri:{
5153     unsigned Mask;
5154     switch (MI.getOpcode()) {
5155     default: llvm_unreachable("Unreachable!");
5156     case X86::BLENDPDrri:    Mask = 0x03; break;
5157     case X86::BLENDPSrri:    Mask = 0x0F; break;
5158     case X86::PBLENDWrri:    Mask = 0xFF; break;
5159     case X86::VBLENDPDrri:   Mask = 0x03; break;
5160     case X86::VBLENDPSrri:   Mask = 0x0F; break;
5161     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
5162     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
5163     case X86::VPBLENDDrri:   Mask = 0x0F; break;
5164     case X86::VPBLENDWrri:   Mask = 0xFF; break;
5165     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
5166     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
5167     }
5168     // Only the least significant bits of Imm are used.
5169     unsigned Imm = MI.getOperand(3).getImm() & Mask;
5170     auto &WorkingMI = cloneIfNew(MI);
5171     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
5172     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5173                                                    OpIdx1, OpIdx2);
5174   }
5175   case X86::MOVSDrr:
5176   case X86::MOVSSrr:
5177   case X86::VMOVSDrr:
5178   case X86::VMOVSSrr:{
5179     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
5180     if (!Subtarget.hasSSE41())
5181       return nullptr;
5182 
5183     unsigned Mask, Opc;
5184     switch (MI.getOpcode()) {
5185     default: llvm_unreachable("Unreachable!");
5186     case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
5187     case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
5188     case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
5189     case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
5190     }
5191 
5192     // MOVSD/MOVSS's 2nd operand is a FR64/FR32 reg class - we need to copy
5193     // this over to a VR128 class like the 1st operand to use a BLENDPD/BLENDPS.
5194     auto &MRI = MI.getParent()->getParent()->getRegInfo();
5195     auto VR128RC = MRI.getRegClass(MI.getOperand(1).getReg());
5196     unsigned VR128 = MRI.createVirtualRegister(VR128RC);
5197     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY),
5198             VR128)
5199         .addReg(MI.getOperand(2).getReg());
5200 
5201     auto &WorkingMI = cloneIfNew(MI);
5202     WorkingMI.setDesc(get(Opc));
5203     WorkingMI.getOperand(2).setReg(VR128);
5204     WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
5205     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5206                                                    OpIdx1, OpIdx2);
5207   }
5208   case X86::PCLMULQDQrr:
5209   case X86::VPCLMULQDQrr:{
5210     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
5211     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
5212     unsigned Imm = MI.getOperand(3).getImm();
5213     unsigned Src1Hi = Imm & 0x01;
5214     unsigned Src2Hi = Imm & 0x10;
5215     auto &WorkingMI = cloneIfNew(MI);
5216     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
5217     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5218                                                    OpIdx1, OpIdx2);
5219   }
5220   case X86::CMPSDrr:
5221   case X86::CMPSSrr:
5222   case X86::CMPPDrri:
5223   case X86::CMPPSrri:
5224   case X86::VCMPSDrr:
5225   case X86::VCMPSSrr:
5226   case X86::VCMPPDrri:
5227   case X86::VCMPPSrri:
5228   case X86::VCMPPDYrri:
5229   case X86::VCMPPSYrri:
5230   case X86::VCMPSDZrr:
5231   case X86::VCMPSSZrr:
5232   case X86::VCMPPDZrri:
5233   case X86::VCMPPSZrri:
5234   case X86::VCMPPDZ128rri:
5235   case X86::VCMPPSZ128rri:
5236   case X86::VCMPPDZ256rri:
5237   case X86::VCMPPSZ256rri: {
5238     // Float comparison can be safely commuted for
5239     // Ordered/Unordered/Equal/NotEqual tests
5240     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5241     switch (Imm) {
5242     case 0x00: // EQUAL
5243     case 0x03: // UNORDERED
5244     case 0x04: // NOT EQUAL
5245     case 0x07: // ORDERED
5246       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
5247     default:
5248       return nullptr;
5249     }
5250   }
5251   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
5252   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
5253   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
5254   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
5255   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
5256   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
5257   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
5258   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
5259   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
5260   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
5261   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
5262   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
5263   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
5264   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
5265   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
5266   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
5267   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
5268   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
5269   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
5270   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
5271   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
5272   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
5273   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
5274   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
5275     // Flip comparison mode immediate (if necessary).
5276     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
5277     switch (Imm) {
5278     default: llvm_unreachable("Unreachable!");
5279     case 0x01: Imm = 0x06; break; // LT  -> NLE
5280     case 0x02: Imm = 0x05; break; // LE  -> NLT
5281     case 0x05: Imm = 0x02; break; // NLT -> LE
5282     case 0x06: Imm = 0x01; break; // NLE -> LT
5283     case 0x00: // EQ
5284     case 0x03: // FALSE
5285     case 0x04: // NE
5286     case 0x07: // TRUE
5287       break;
5288     }
5289     auto &WorkingMI = cloneIfNew(MI);
5290     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
5291     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5292                                                    OpIdx1, OpIdx2);
5293   }
5294   case X86::VPCOMBri: case X86::VPCOMUBri:
5295   case X86::VPCOMDri: case X86::VPCOMUDri:
5296   case X86::VPCOMQri: case X86::VPCOMUQri:
5297   case X86::VPCOMWri: case X86::VPCOMUWri: {
5298     // Flip comparison mode immediate (if necessary).
5299     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5300     switch (Imm) {
5301     default: llvm_unreachable("Unreachable!");
5302     case 0x00: Imm = 0x02; break; // LT -> GT
5303     case 0x01: Imm = 0x03; break; // LE -> GE
5304     case 0x02: Imm = 0x00; break; // GT -> LT
5305     case 0x03: Imm = 0x01; break; // GE -> LE
5306     case 0x04: // EQ
5307     case 0x05: // NE
5308     case 0x06: // FALSE
5309     case 0x07: // TRUE
5310       break;
5311     }
5312     auto &WorkingMI = cloneIfNew(MI);
5313     WorkingMI.getOperand(3).setImm(Imm);
5314     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5315                                                    OpIdx1, OpIdx2);
5316   }
5317   case X86::VPERM2F128rr:
5318   case X86::VPERM2I128rr: {
5319     // Flip permute source immediate.
5320     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
5321     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
5322     unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
5323     auto &WorkingMI = cloneIfNew(MI);
5324     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
5325     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5326                                                    OpIdx1, OpIdx2);
5327   }
5328   case X86::MOVHLPSrr:
5329   case X86::UNPCKHPDrr: {
5330     if (!Subtarget.hasSSE2())
5331       return nullptr;
5332 
5333     unsigned Opc = MI.getOpcode();
5334     switch (Opc) {
5335       default: llvm_unreachable("Unreachable!");
5336       case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
5337       case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
5338     }
5339     auto &WorkingMI = cloneIfNew(MI);
5340     WorkingMI.setDesc(get(Opc));
5341     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5342                                                    OpIdx1, OpIdx2);
5343   }
5344   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
5345   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
5346   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
5347   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
5348   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
5349   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
5350   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
5351   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
5352   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
5353   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
5354   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
5355   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
5356   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
5357   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
5358   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
5359   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
5360     unsigned Opc;
5361     switch (MI.getOpcode()) {
5362     default: llvm_unreachable("Unreachable!");
5363     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
5364     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
5365     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
5366     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
5367     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
5368     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
5369     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
5370     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
5371     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
5372     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
5373     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
5374     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
5375     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
5376     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
5377     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
5378     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
5379     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
5380     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
5381     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
5382     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
5383     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
5384     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
5385     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
5386     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
5387     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
5388     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
5389     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
5390     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
5391     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
5392     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
5393     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
5394     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
5395     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
5396     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
5397     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
5398     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
5399     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
5400     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
5401     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
5402     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
5403     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
5404     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
5405     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
5406     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
5407     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
5408     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
5409     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
5410     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
5411     }
5412     auto &WorkingMI = cloneIfNew(MI);
5413     WorkingMI.setDesc(get(Opc));
5414     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5415                                                    OpIdx1, OpIdx2);
5416   }
5417   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
5418   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
5419   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
5420   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
5421   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
5422   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
5423   case X86::VPTERNLOGDZrrik:
5424   case X86::VPTERNLOGDZ128rrik:
5425   case X86::VPTERNLOGDZ256rrik:
5426   case X86::VPTERNLOGQZrrik:
5427   case X86::VPTERNLOGQZ128rrik:
5428   case X86::VPTERNLOGQZ256rrik:
5429   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
5430   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
5431   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
5432   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
5433   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
5434   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
5435   case X86::VPTERNLOGDZ128rmbi:
5436   case X86::VPTERNLOGDZ256rmbi:
5437   case X86::VPTERNLOGDZrmbi:
5438   case X86::VPTERNLOGQZ128rmbi:
5439   case X86::VPTERNLOGQZ256rmbi:
5440   case X86::VPTERNLOGQZrmbi:
5441   case X86::VPTERNLOGDZ128rmbikz:
5442   case X86::VPTERNLOGDZ256rmbikz:
5443   case X86::VPTERNLOGDZrmbikz:
5444   case X86::VPTERNLOGQZ128rmbikz:
5445   case X86::VPTERNLOGQZ256rmbikz:
5446   case X86::VPTERNLOGQZrmbikz: {
5447     auto &WorkingMI = cloneIfNew(MI);
5448     if (!commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2))
5449       return nullptr;
5450     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5451                                                    OpIdx1, OpIdx2);
5452   }
5453   default: {
5454     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
5455       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
5456       auto &WorkingMI = cloneIfNew(MI);
5457       WorkingMI.setDesc(get(Opc));
5458       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5459                                                      OpIdx1, OpIdx2);
5460     }
5461 
5462     const X86InstrFMA3Group *FMA3Group =
5463         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
5464     if (FMA3Group) {
5465       unsigned Opc =
5466         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
5467       if (Opc == 0)
5468         return nullptr;
5469       auto &WorkingMI = cloneIfNew(MI);
5470       WorkingMI.setDesc(get(Opc));
5471       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5472                                                      OpIdx1, OpIdx2);
5473     }
5474 
5475     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
5476   }
5477   }
5478 }
5479 
5480 bool X86InstrInfo::findFMA3CommutedOpIndices(
5481     const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2,
5482     const X86InstrFMA3Group &FMA3Group) const {
5483 
5484   if (!findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2))
5485     return false;
5486 
5487   // Check if we can adjust the opcode to preserve the semantics when
5488   // commute the register operands.
5489   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2, FMA3Group) != 0;
5490 }
5491 
5492 bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
5493                                                  unsigned &SrcOpIdx1,
5494                                                  unsigned &SrcOpIdx2) const {
5495   uint64_t TSFlags = MI.getDesc().TSFlags;
5496 
5497   unsigned FirstCommutableVecOp = 1;
5498   unsigned LastCommutableVecOp = 3;
5499   unsigned KMaskOp = 0;
5500   if (X86II::isKMasked(TSFlags)) {
5501     // The k-mask operand has index = 2 for masked and zero-masked operations.
5502     KMaskOp = 2;
5503 
5504     // The operand with index = 1 is used as a source for those elements for
5505     // which the corresponding bit in the k-mask is set to 0.
5506     if (X86II::isKMergeMasked(TSFlags))
5507       FirstCommutableVecOp = 3;
5508 
5509     LastCommutableVecOp++;
5510   }
5511 
5512   if (isMem(MI, LastCommutableVecOp))
5513     LastCommutableVecOp--;
5514 
5515   // Only the first RegOpsNum operands are commutable.
5516   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
5517   // that the operand is not specified/fixed.
5518   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
5519       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
5520        SrcOpIdx1 == KMaskOp))
5521     return false;
5522   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
5523       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
5524        SrcOpIdx2 == KMaskOp))
5525     return false;
5526 
5527   // Look for two different register operands assumed to be commutable
5528   // regardless of the FMA opcode. The FMA opcode is adjusted later.
5529   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
5530       SrcOpIdx2 == CommuteAnyOperandIndex) {
5531     unsigned CommutableOpIdx1 = SrcOpIdx1;
5532     unsigned CommutableOpIdx2 = SrcOpIdx2;
5533 
5534     // At least one of operands to be commuted is not specified and
5535     // this method is free to choose appropriate commutable operands.
5536     if (SrcOpIdx1 == SrcOpIdx2)
5537       // Both of operands are not fixed. By default set one of commutable
5538       // operands to the last register operand of the instruction.
5539       CommutableOpIdx2 = LastCommutableVecOp;
5540     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
5541       // Only one of operands is not fixed.
5542       CommutableOpIdx2 = SrcOpIdx1;
5543 
5544     // CommutableOpIdx2 is well defined now. Let's choose another commutable
5545     // operand and assign its index to CommutableOpIdx1.
5546     unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
5547     for (CommutableOpIdx1 = LastCommutableVecOp;
5548          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
5549       // Just ignore and skip the k-mask operand.
5550       if (CommutableOpIdx1 == KMaskOp)
5551         continue;
5552 
5553       // The commuted operands must have different registers.
5554       // Otherwise, the commute transformation does not change anything and
5555       // is useless then.
5556       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
5557         break;
5558     }
5559 
5560     // No appropriate commutable operands were found.
5561     if (CommutableOpIdx1 < FirstCommutableVecOp)
5562       return false;
5563 
5564     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
5565     // to return those values.
5566     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
5567                               CommutableOpIdx1, CommutableOpIdx2))
5568       return false;
5569   }
5570 
5571   return true;
5572 }
5573 
5574 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
5575                                          unsigned &SrcOpIdx2) const {
5576   const MCInstrDesc &Desc = MI.getDesc();
5577   if (!Desc.isCommutable())
5578     return false;
5579 
5580   switch (MI.getOpcode()) {
5581   case X86::CMPSDrr:
5582   case X86::CMPSSrr:
5583   case X86::CMPPDrri:
5584   case X86::CMPPSrri:
5585   case X86::VCMPSDrr:
5586   case X86::VCMPSSrr:
5587   case X86::VCMPPDrri:
5588   case X86::VCMPPSrri:
5589   case X86::VCMPPDYrri:
5590   case X86::VCMPPSYrri:
5591   case X86::VCMPSDZrr:
5592   case X86::VCMPSSZrr:
5593   case X86::VCMPPDZrri:
5594   case X86::VCMPPSZrri:
5595   case X86::VCMPPDZ128rri:
5596   case X86::VCMPPSZ128rri:
5597   case X86::VCMPPDZ256rri:
5598   case X86::VCMPPSZ256rri: {
5599     // Float comparison can be safely commuted for
5600     // Ordered/Unordered/Equal/NotEqual tests
5601     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5602     switch (Imm) {
5603     case 0x00: // EQUAL
5604     case 0x03: // UNORDERED
5605     case 0x04: // NOT EQUAL
5606     case 0x07: // ORDERED
5607       // The indices of the commutable operands are 1 and 2.
5608       // Assign them to the returned operand indices here.
5609       return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
5610     }
5611     return false;
5612   }
5613   case X86::MOVSDrr:
5614   case X86::MOVSSrr:
5615   case X86::VMOVSDrr:
5616   case X86::VMOVSSrr: {
5617     if (Subtarget.hasSSE41())
5618       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5619     return false;
5620   }
5621   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
5622   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
5623   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
5624   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
5625   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
5626   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
5627   case X86::VPTERNLOGDZrrik:
5628   case X86::VPTERNLOGDZ128rrik:
5629   case X86::VPTERNLOGDZ256rrik:
5630   case X86::VPTERNLOGQZrrik:
5631   case X86::VPTERNLOGQZ128rrik:
5632   case X86::VPTERNLOGQZ256rrik:
5633   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
5634   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
5635   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
5636   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
5637   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
5638   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
5639   case X86::VPTERNLOGDZ128rmbi:
5640   case X86::VPTERNLOGDZ256rmbi:
5641   case X86::VPTERNLOGDZrmbi:
5642   case X86::VPTERNLOGQZ128rmbi:
5643   case X86::VPTERNLOGQZ256rmbi:
5644   case X86::VPTERNLOGQZrmbi:
5645   case X86::VPTERNLOGDZ128rmbikz:
5646   case X86::VPTERNLOGDZ256rmbikz:
5647   case X86::VPTERNLOGDZrmbikz:
5648   case X86::VPTERNLOGQZ128rmbikz:
5649   case X86::VPTERNLOGQZ256rmbikz:
5650   case X86::VPTERNLOGQZrmbikz:
5651     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5652   case X86::VPMADD52HUQZ128r:
5653   case X86::VPMADD52HUQZ128rk:
5654   case X86::VPMADD52HUQZ128rkz:
5655   case X86::VPMADD52HUQZ256r:
5656   case X86::VPMADD52HUQZ256rk:
5657   case X86::VPMADD52HUQZ256rkz:
5658   case X86::VPMADD52HUQZr:
5659   case X86::VPMADD52HUQZrk:
5660   case X86::VPMADD52HUQZrkz:
5661   case X86::VPMADD52LUQZ128r:
5662   case X86::VPMADD52LUQZ128rk:
5663   case X86::VPMADD52LUQZ128rkz:
5664   case X86::VPMADD52LUQZ256r:
5665   case X86::VPMADD52LUQZ256rk:
5666   case X86::VPMADD52LUQZ256rkz:
5667   case X86::VPMADD52LUQZr:
5668   case X86::VPMADD52LUQZrk:
5669   case X86::VPMADD52LUQZrkz: {
5670     unsigned CommutableOpIdx1 = 2;
5671     unsigned CommutableOpIdx2 = 3;
5672     if (Desc.TSFlags & X86II::EVEX_K) {
5673       // Skip the mask register.
5674       ++CommutableOpIdx1;
5675       ++CommutableOpIdx2;
5676     }
5677     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
5678                               CommutableOpIdx1, CommutableOpIdx2))
5679       return false;
5680     if (!MI.getOperand(SrcOpIdx1).isReg() ||
5681         !MI.getOperand(SrcOpIdx2).isReg())
5682       // No idea.
5683       return false;
5684     return true;
5685   }
5686 
5687   default:
5688     const X86InstrFMA3Group *FMA3Group =
5689         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
5690     if (FMA3Group)
5691       return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2, *FMA3Group);
5692 
5693     // Handled masked instructions since we need to skip over the mask input
5694     // and the preserved input.
5695     if (Desc.TSFlags & X86II::EVEX_K) {
5696       // First assume that the first input is the mask operand and skip past it.
5697       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
5698       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
5699       // Check if the first input is tied. If there isn't one then we only
5700       // need to skip the mask operand which we did above.
5701       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
5702                                              MCOI::TIED_TO) != -1)) {
5703         // If this is zero masking instruction with a tied operand, we need to
5704         // move the first index back to the first input since this must
5705         // be a 3 input instruction and we want the first two non-mask inputs.
5706         // Otherwise this is a 2 input instruction with a preserved input and
5707         // mask, so we need to move the indices to skip one more input.
5708         if (Desc.TSFlags & X86II::EVEX_Z)
5709           --CommutableOpIdx1;
5710         else {
5711           ++CommutableOpIdx1;
5712           ++CommutableOpIdx2;
5713         }
5714       }
5715 
5716       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
5717                                 CommutableOpIdx1, CommutableOpIdx2))
5718         return false;
5719 
5720       if (!MI.getOperand(SrcOpIdx1).isReg() ||
5721           !MI.getOperand(SrcOpIdx2).isReg())
5722         // No idea.
5723         return false;
5724       return true;
5725     }
5726 
5727     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5728   }
5729   return false;
5730 }
5731 
5732 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
5733   switch (BrOpc) {
5734   default: return X86::COND_INVALID;
5735   case X86::JE_1:  return X86::COND_E;
5736   case X86::JNE_1: return X86::COND_NE;
5737   case X86::JL_1:  return X86::COND_L;
5738   case X86::JLE_1: return X86::COND_LE;
5739   case X86::JG_1:  return X86::COND_G;
5740   case X86::JGE_1: return X86::COND_GE;
5741   case X86::JB_1:  return X86::COND_B;
5742   case X86::JBE_1: return X86::COND_BE;
5743   case X86::JA_1:  return X86::COND_A;
5744   case X86::JAE_1: return X86::COND_AE;
5745   case X86::JS_1:  return X86::COND_S;
5746   case X86::JNS_1: return X86::COND_NS;
5747   case X86::JP_1:  return X86::COND_P;
5748   case X86::JNP_1: return X86::COND_NP;
5749   case X86::JO_1:  return X86::COND_O;
5750   case X86::JNO_1: return X86::COND_NO;
5751   }
5752 }
5753 
5754 /// Return condition code of a SET opcode.
5755 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
5756   switch (Opc) {
5757   default: return X86::COND_INVALID;
5758   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
5759   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
5760   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
5761   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
5762   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
5763   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
5764   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
5765   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
5766   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
5767   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
5768   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
5769   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
5770   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
5771   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
5772   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
5773   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
5774   }
5775 }
5776 
5777 /// Return condition code of a CMov opcode.
5778 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
5779   switch (Opc) {
5780   default: return X86::COND_INVALID;
5781   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
5782   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
5783     return X86::COND_A;
5784   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
5785   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
5786     return X86::COND_AE;
5787   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
5788   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
5789     return X86::COND_B;
5790   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
5791   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
5792     return X86::COND_BE;
5793   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
5794   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
5795     return X86::COND_E;
5796   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
5797   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
5798     return X86::COND_G;
5799   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
5800   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
5801     return X86::COND_GE;
5802   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
5803   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
5804     return X86::COND_L;
5805   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
5806   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
5807     return X86::COND_LE;
5808   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
5809   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
5810     return X86::COND_NE;
5811   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
5812   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
5813     return X86::COND_NO;
5814   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
5815   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
5816     return X86::COND_NP;
5817   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
5818   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
5819     return X86::COND_NS;
5820   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
5821   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
5822     return X86::COND_O;
5823   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
5824   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
5825     return X86::COND_P;
5826   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
5827   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
5828     return X86::COND_S;
5829   }
5830 }
5831 
5832 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
5833   switch (CC) {
5834   default: llvm_unreachable("Illegal condition code!");
5835   case X86::COND_E:  return X86::JE_1;
5836   case X86::COND_NE: return X86::JNE_1;
5837   case X86::COND_L:  return X86::JL_1;
5838   case X86::COND_LE: return X86::JLE_1;
5839   case X86::COND_G:  return X86::JG_1;
5840   case X86::COND_GE: return X86::JGE_1;
5841   case X86::COND_B:  return X86::JB_1;
5842   case X86::COND_BE: return X86::JBE_1;
5843   case X86::COND_A:  return X86::JA_1;
5844   case X86::COND_AE: return X86::JAE_1;
5845   case X86::COND_S:  return X86::JS_1;
5846   case X86::COND_NS: return X86::JNS_1;
5847   case X86::COND_P:  return X86::JP_1;
5848   case X86::COND_NP: return X86::JNP_1;
5849   case X86::COND_O:  return X86::JO_1;
5850   case X86::COND_NO: return X86::JNO_1;
5851   }
5852 }
5853 
5854 /// Return the inverse of the specified condition,
5855 /// e.g. turning COND_E to COND_NE.
5856 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
5857   switch (CC) {
5858   default: llvm_unreachable("Illegal condition code!");
5859   case X86::COND_E:  return X86::COND_NE;
5860   case X86::COND_NE: return X86::COND_E;
5861   case X86::COND_L:  return X86::COND_GE;
5862   case X86::COND_LE: return X86::COND_G;
5863   case X86::COND_G:  return X86::COND_LE;
5864   case X86::COND_GE: return X86::COND_L;
5865   case X86::COND_B:  return X86::COND_AE;
5866   case X86::COND_BE: return X86::COND_A;
5867   case X86::COND_A:  return X86::COND_BE;
5868   case X86::COND_AE: return X86::COND_B;
5869   case X86::COND_S:  return X86::COND_NS;
5870   case X86::COND_NS: return X86::COND_S;
5871   case X86::COND_P:  return X86::COND_NP;
5872   case X86::COND_NP: return X86::COND_P;
5873   case X86::COND_O:  return X86::COND_NO;
5874   case X86::COND_NO: return X86::COND_O;
5875   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
5876   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
5877   }
5878 }
5879 
5880 /// Assuming the flags are set by MI(a,b), return the condition code if we
5881 /// modify the instructions such that flags are set by MI(b,a).
5882 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
5883   switch (CC) {
5884   default: return X86::COND_INVALID;
5885   case X86::COND_E:  return X86::COND_E;
5886   case X86::COND_NE: return X86::COND_NE;
5887   case X86::COND_L:  return X86::COND_G;
5888   case X86::COND_LE: return X86::COND_GE;
5889   case X86::COND_G:  return X86::COND_L;
5890   case X86::COND_GE: return X86::COND_LE;
5891   case X86::COND_B:  return X86::COND_A;
5892   case X86::COND_BE: return X86::COND_AE;
5893   case X86::COND_A:  return X86::COND_B;
5894   case X86::COND_AE: return X86::COND_BE;
5895   }
5896 }
5897 
5898 std::pair<X86::CondCode, bool>
5899 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
5900   X86::CondCode CC = X86::COND_INVALID;
5901   bool NeedSwap = false;
5902   switch (Predicate) {
5903   default: break;
5904   // Floating-point Predicates
5905   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
5906   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
5907   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
5908   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
5909   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
5910   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
5911   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
5912   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
5913   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
5914   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
5915   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
5916   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
5917   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
5918   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
5919 
5920   // Integer Predicates
5921   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
5922   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
5923   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
5924   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
5925   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
5926   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
5927   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
5928   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
5929   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
5930   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
5931   }
5932 
5933   return std::make_pair(CC, NeedSwap);
5934 }
5935 
5936 /// Return a set opcode for the given condition and
5937 /// whether it has memory operand.
5938 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
5939   static const uint16_t Opc[16][2] = {
5940     { X86::SETAr,  X86::SETAm  },
5941     { X86::SETAEr, X86::SETAEm },
5942     { X86::SETBr,  X86::SETBm  },
5943     { X86::SETBEr, X86::SETBEm },
5944     { X86::SETEr,  X86::SETEm  },
5945     { X86::SETGr,  X86::SETGm  },
5946     { X86::SETGEr, X86::SETGEm },
5947     { X86::SETLr,  X86::SETLm  },
5948     { X86::SETLEr, X86::SETLEm },
5949     { X86::SETNEr, X86::SETNEm },
5950     { X86::SETNOr, X86::SETNOm },
5951     { X86::SETNPr, X86::SETNPm },
5952     { X86::SETNSr, X86::SETNSm },
5953     { X86::SETOr,  X86::SETOm  },
5954     { X86::SETPr,  X86::SETPm  },
5955     { X86::SETSr,  X86::SETSm  }
5956   };
5957 
5958   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
5959   return Opc[CC][HasMemoryOperand ? 1 : 0];
5960 }
5961 
5962 /// Return a cmov opcode for the given condition,
5963 /// register size in bytes, and operand type.
5964 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
5965                               bool HasMemoryOperand) {
5966   static const uint16_t Opc[32][3] = {
5967     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
5968     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
5969     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
5970     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
5971     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
5972     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
5973     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
5974     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
5975     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
5976     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
5977     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
5978     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
5979     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
5980     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
5981     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
5982     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
5983     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
5984     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
5985     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
5986     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
5987     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
5988     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
5989     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
5990     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
5991     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
5992     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
5993     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
5994     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
5995     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
5996     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
5997     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
5998     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
5999   };
6000 
6001   assert(CC < 16 && "Can only handle standard cond codes");
6002   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
6003   switch(RegBytes) {
6004   default: llvm_unreachable("Illegal register size!");
6005   case 2: return Opc[Idx][0];
6006   case 4: return Opc[Idx][1];
6007   case 8: return Opc[Idx][2];
6008   }
6009 }
6010 
6011 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
6012   if (!MI.isTerminator()) return false;
6013 
6014   // Conditional branch is a special case.
6015   if (MI.isBranch() && !MI.isBarrier())
6016     return true;
6017   if (!MI.isPredicable())
6018     return true;
6019   return !isPredicated(MI);
6020 }
6021 
6022 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
6023   switch (MI.getOpcode()) {
6024   case X86::TCRETURNdi:
6025   case X86::TCRETURNri:
6026   case X86::TCRETURNmi:
6027   case X86::TCRETURNdi64:
6028   case X86::TCRETURNri64:
6029   case X86::TCRETURNmi64:
6030     return true;
6031   default:
6032     return false;
6033   }
6034 }
6035 
6036 bool X86InstrInfo::canMakeTailCallConditional(
6037     SmallVectorImpl<MachineOperand> &BranchCond,
6038     const MachineInstr &TailCall) const {
6039   if (TailCall.getOpcode() != X86::TCRETURNdi &&
6040       TailCall.getOpcode() != X86::TCRETURNdi64) {
6041     // Only direct calls can be done with a conditional branch.
6042     return false;
6043   }
6044 
6045   const MachineFunction *MF = TailCall.getParent()->getParent();
6046   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
6047     // Conditional tail calls confuse the Win64 unwinder.
6048     return false;
6049   }
6050 
6051   assert(BranchCond.size() == 1);
6052   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
6053     // Can't make a conditional tail call with this condition.
6054     return false;
6055   }
6056 
6057   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6058   if (X86FI->getTCReturnAddrDelta() != 0 ||
6059       TailCall.getOperand(1).getImm() != 0) {
6060     // A conditional tail call cannot do any stack adjustment.
6061     return false;
6062   }
6063 
6064   return true;
6065 }
6066 
6067 void X86InstrInfo::replaceBranchWithTailCall(
6068     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
6069     const MachineInstr &TailCall) const {
6070   assert(canMakeTailCallConditional(BranchCond, TailCall));
6071 
6072   MachineBasicBlock::iterator I = MBB.end();
6073   while (I != MBB.begin()) {
6074     --I;
6075     if (I->isDebugValue())
6076       continue;
6077     if (!I->isBranch())
6078       assert(0 && "Can't find the branch to replace!");
6079 
6080     X86::CondCode CC = getCondFromBranchOpc(I->getOpcode());
6081     assert(BranchCond.size() == 1);
6082     if (CC != BranchCond[0].getImm())
6083       continue;
6084 
6085     break;
6086   }
6087 
6088   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
6089                                                          : X86::TCRETURNdi64cc;
6090 
6091   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
6092   MIB->addOperand(TailCall.getOperand(0)); // Destination.
6093   MIB.addImm(0); // Stack offset (not used).
6094   MIB->addOperand(BranchCond[0]); // Condition.
6095   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
6096 
6097   // Add implicit uses and defs of all live regs potentially clobbered by the
6098   // call. This way they still appear live across the call.
6099   LivePhysRegs LiveRegs(getRegisterInfo());
6100   LiveRegs.addLiveOuts(MBB);
6101   SmallVector<std::pair<unsigned, const MachineOperand *>, 8> Clobbers;
6102   LiveRegs.stepForward(*MIB, Clobbers);
6103   for (const auto &C : Clobbers) {
6104     MIB.addReg(C.first, RegState::Implicit);
6105     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
6106   }
6107 
6108   I->eraseFromParent();
6109 }
6110 
6111 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
6112 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
6113 // fallthrough MBB cannot be identified.
6114 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
6115                                             MachineBasicBlock *TBB) {
6116   // Look for non-EHPad successors other than TBB. If we find exactly one, it
6117   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
6118   // and fallthrough MBB. If we find more than one, we cannot identify the
6119   // fallthrough MBB and should return nullptr.
6120   MachineBasicBlock *FallthroughBB = nullptr;
6121   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
6122     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
6123       continue;
6124     // Return a nullptr if we found more than one fallthrough successor.
6125     if (FallthroughBB && FallthroughBB != TBB)
6126       return nullptr;
6127     FallthroughBB = *SI;
6128   }
6129   return FallthroughBB;
6130 }
6131 
6132 bool X86InstrInfo::AnalyzeBranchImpl(
6133     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
6134     SmallVectorImpl<MachineOperand> &Cond,
6135     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
6136 
6137   // Start from the bottom of the block and work up, examining the
6138   // terminator instructions.
6139   MachineBasicBlock::iterator I = MBB.end();
6140   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
6141   while (I != MBB.begin()) {
6142     --I;
6143     if (I->isDebugValue())
6144       continue;
6145 
6146     // Working from the bottom, when we see a non-terminator instruction, we're
6147     // done.
6148     if (!isUnpredicatedTerminator(*I))
6149       break;
6150 
6151     // A terminator that isn't a branch can't easily be handled by this
6152     // analysis.
6153     if (!I->isBranch())
6154       return true;
6155 
6156     // Handle unconditional branches.
6157     if (I->getOpcode() == X86::JMP_1) {
6158       UnCondBrIter = I;
6159 
6160       if (!AllowModify) {
6161         TBB = I->getOperand(0).getMBB();
6162         continue;
6163       }
6164 
6165       // If the block has any instructions after a JMP, delete them.
6166       while (std::next(I) != MBB.end())
6167         std::next(I)->eraseFromParent();
6168 
6169       Cond.clear();
6170       FBB = nullptr;
6171 
6172       // Delete the JMP if it's equivalent to a fall-through.
6173       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
6174         TBB = nullptr;
6175         I->eraseFromParent();
6176         I = MBB.end();
6177         UnCondBrIter = MBB.end();
6178         continue;
6179       }
6180 
6181       // TBB is used to indicate the unconditional destination.
6182       TBB = I->getOperand(0).getMBB();
6183       continue;
6184     }
6185 
6186     // Handle conditional branches.
6187     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
6188     if (BranchCode == X86::COND_INVALID)
6189       return true;  // Can't handle indirect branch.
6190 
6191     // Working from the bottom, handle the first conditional branch.
6192     if (Cond.empty()) {
6193       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
6194       if (AllowModify && UnCondBrIter != MBB.end() &&
6195           MBB.isLayoutSuccessor(TargetBB)) {
6196         // If we can modify the code and it ends in something like:
6197         //
6198         //     jCC L1
6199         //     jmp L2
6200         //   L1:
6201         //     ...
6202         //   L2:
6203         //
6204         // Then we can change this to:
6205         //
6206         //     jnCC L2
6207         //   L1:
6208         //     ...
6209         //   L2:
6210         //
6211         // Which is a bit more efficient.
6212         // We conditionally jump to the fall-through block.
6213         BranchCode = GetOppositeBranchCondition(BranchCode);
6214         unsigned JNCC = GetCondBranchFromCond(BranchCode);
6215         MachineBasicBlock::iterator OldInst = I;
6216 
6217         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
6218           .addMBB(UnCondBrIter->getOperand(0).getMBB());
6219         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
6220           .addMBB(TargetBB);
6221 
6222         OldInst->eraseFromParent();
6223         UnCondBrIter->eraseFromParent();
6224 
6225         // Restart the analysis.
6226         UnCondBrIter = MBB.end();
6227         I = MBB.end();
6228         continue;
6229       }
6230 
6231       FBB = TBB;
6232       TBB = I->getOperand(0).getMBB();
6233       Cond.push_back(MachineOperand::CreateImm(BranchCode));
6234       CondBranches.push_back(&*I);
6235       continue;
6236     }
6237 
6238     // Handle subsequent conditional branches. Only handle the case where all
6239     // conditional branches branch to the same destination and their condition
6240     // opcodes fit one of the special multi-branch idioms.
6241     assert(Cond.size() == 1);
6242     assert(TBB);
6243 
6244     // If the conditions are the same, we can leave them alone.
6245     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
6246     auto NewTBB = I->getOperand(0).getMBB();
6247     if (OldBranchCode == BranchCode && TBB == NewTBB)
6248       continue;
6249 
6250     // If they differ, see if they fit one of the known patterns. Theoretically,
6251     // we could handle more patterns here, but we shouldn't expect to see them
6252     // if instruction selection has done a reasonable job.
6253     if (TBB == NewTBB &&
6254                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
6255                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
6256       BranchCode = X86::COND_NE_OR_P;
6257     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
6258                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
6259       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
6260         return true;
6261 
6262       // X86::COND_E_AND_NP usually has two different branch destinations.
6263       //
6264       // JP B1
6265       // JE B2
6266       // JMP B1
6267       // B1:
6268       // B2:
6269       //
6270       // Here this condition branches to B2 only if NP && E. It has another
6271       // equivalent form:
6272       //
6273       // JNE B1
6274       // JNP B2
6275       // JMP B1
6276       // B1:
6277       // B2:
6278       //
6279       // Similarly it branches to B2 only if E && NP. That is why this condition
6280       // is named with COND_E_AND_NP.
6281       BranchCode = X86::COND_E_AND_NP;
6282     } else
6283       return true;
6284 
6285     // Update the MachineOperand.
6286     Cond[0].setImm(BranchCode);
6287     CondBranches.push_back(&*I);
6288   }
6289 
6290   return false;
6291 }
6292 
6293 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
6294                                  MachineBasicBlock *&TBB,
6295                                  MachineBasicBlock *&FBB,
6296                                  SmallVectorImpl<MachineOperand> &Cond,
6297                                  bool AllowModify) const {
6298   SmallVector<MachineInstr *, 4> CondBranches;
6299   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
6300 }
6301 
6302 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
6303                                           MachineBranchPredicate &MBP,
6304                                           bool AllowModify) const {
6305   using namespace std::placeholders;
6306 
6307   SmallVector<MachineOperand, 4> Cond;
6308   SmallVector<MachineInstr *, 4> CondBranches;
6309   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
6310                         AllowModify))
6311     return true;
6312 
6313   if (Cond.size() != 1)
6314     return true;
6315 
6316   assert(MBP.TrueDest && "expected!");
6317 
6318   if (!MBP.FalseDest)
6319     MBP.FalseDest = MBB.getNextNode();
6320 
6321   const TargetRegisterInfo *TRI = &getRegisterInfo();
6322 
6323   MachineInstr *ConditionDef = nullptr;
6324   bool SingleUseCondition = true;
6325 
6326   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
6327     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
6328       ConditionDef = &*I;
6329       break;
6330     }
6331 
6332     if (I->readsRegister(X86::EFLAGS, TRI))
6333       SingleUseCondition = false;
6334   }
6335 
6336   if (!ConditionDef)
6337     return true;
6338 
6339   if (SingleUseCondition) {
6340     for (auto *Succ : MBB.successors())
6341       if (Succ->isLiveIn(X86::EFLAGS))
6342         SingleUseCondition = false;
6343   }
6344 
6345   MBP.ConditionDef = ConditionDef;
6346   MBP.SingleUseCondition = SingleUseCondition;
6347 
6348   // Currently we only recognize the simple pattern:
6349   //
6350   //   test %reg, %reg
6351   //   je %label
6352   //
6353   const unsigned TestOpcode =
6354       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
6355 
6356   if (ConditionDef->getOpcode() == TestOpcode &&
6357       ConditionDef->getNumOperands() == 3 &&
6358       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
6359       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
6360     MBP.LHS = ConditionDef->getOperand(0);
6361     MBP.RHS = MachineOperand::CreateImm(0);
6362     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
6363                         ? MachineBranchPredicate::PRED_NE
6364                         : MachineBranchPredicate::PRED_EQ;
6365     return false;
6366   }
6367 
6368   return true;
6369 }
6370 
6371 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
6372                                     int *BytesRemoved) const {
6373   assert(!BytesRemoved && "code size not handled");
6374 
6375   MachineBasicBlock::iterator I = MBB.end();
6376   unsigned Count = 0;
6377 
6378   while (I != MBB.begin()) {
6379     --I;
6380     if (I->isDebugValue())
6381       continue;
6382     if (I->getOpcode() != X86::JMP_1 &&
6383         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
6384       break;
6385     // Remove the branch.
6386     I->eraseFromParent();
6387     I = MBB.end();
6388     ++Count;
6389   }
6390 
6391   return Count;
6392 }
6393 
6394 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
6395                                     MachineBasicBlock *TBB,
6396                                     MachineBasicBlock *FBB,
6397                                     ArrayRef<MachineOperand> Cond,
6398                                     const DebugLoc &DL,
6399                                     int *BytesAdded) const {
6400   // Shouldn't be a fall through.
6401   assert(TBB && "insertBranch must not be told to insert a fallthrough");
6402   assert((Cond.size() == 1 || Cond.size() == 0) &&
6403          "X86 branch conditions have one component!");
6404   assert(!BytesAdded && "code size not handled");
6405 
6406   if (Cond.empty()) {
6407     // Unconditional branch?
6408     assert(!FBB && "Unconditional branch with multiple successors!");
6409     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
6410     return 1;
6411   }
6412 
6413   // If FBB is null, it is implied to be a fall-through block.
6414   bool FallThru = FBB == nullptr;
6415 
6416   // Conditional branch.
6417   unsigned Count = 0;
6418   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
6419   switch (CC) {
6420   case X86::COND_NE_OR_P:
6421     // Synthesize NE_OR_P with two branches.
6422     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
6423     ++Count;
6424     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
6425     ++Count;
6426     break;
6427   case X86::COND_E_AND_NP:
6428     // Use the next block of MBB as FBB if it is null.
6429     if (FBB == nullptr) {
6430       FBB = getFallThroughMBB(&MBB, TBB);
6431       assert(FBB && "MBB cannot be the last block in function when the false "
6432                     "body is a fall-through.");
6433     }
6434     // Synthesize COND_E_AND_NP with two branches.
6435     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
6436     ++Count;
6437     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
6438     ++Count;
6439     break;
6440   default: {
6441     unsigned Opc = GetCondBranchFromCond(CC);
6442     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
6443     ++Count;
6444   }
6445   }
6446   if (!FallThru) {
6447     // Two-way Conditional branch. Insert the second branch.
6448     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
6449     ++Count;
6450   }
6451   return Count;
6452 }
6453 
6454 bool X86InstrInfo::
6455 canInsertSelect(const MachineBasicBlock &MBB,
6456                 ArrayRef<MachineOperand> Cond,
6457                 unsigned TrueReg, unsigned FalseReg,
6458                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
6459   // Not all subtargets have cmov instructions.
6460   if (!Subtarget.hasCMov())
6461     return false;
6462   if (Cond.size() != 1)
6463     return false;
6464   // We cannot do the composite conditions, at least not in SSA form.
6465   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
6466     return false;
6467 
6468   // Check register classes.
6469   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
6470   const TargetRegisterClass *RC =
6471     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
6472   if (!RC)
6473     return false;
6474 
6475   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
6476   if (X86::GR16RegClass.hasSubClassEq(RC) ||
6477       X86::GR32RegClass.hasSubClassEq(RC) ||
6478       X86::GR64RegClass.hasSubClassEq(RC)) {
6479     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
6480     // Bridge. Probably Ivy Bridge as well.
6481     CondCycles = 2;
6482     TrueCycles = 2;
6483     FalseCycles = 2;
6484     return true;
6485   }
6486 
6487   // Can't do vectors.
6488   return false;
6489 }
6490 
6491 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
6492                                 MachineBasicBlock::iterator I,
6493                                 const DebugLoc &DL, unsigned DstReg,
6494                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
6495                                 unsigned FalseReg) const {
6496   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
6497   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
6498   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
6499   assert(Cond.size() == 1 && "Invalid Cond array");
6500   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
6501                                  TRI.getRegSizeInBits(RC) / 8,
6502                                  false /*HasMemoryOperand*/);
6503   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
6504 }
6505 
6506 /// Test if the given register is a physical h register.
6507 static bool isHReg(unsigned Reg) {
6508   return X86::GR8_ABCD_HRegClass.contains(Reg);
6509 }
6510 
6511 // Try and copy between VR128/VR64 and GR64 registers.
6512 static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg,
6513                                         const X86Subtarget &Subtarget) {
6514   bool HasAVX = Subtarget.hasAVX();
6515   bool HasAVX512 = Subtarget.hasAVX512();
6516 
6517   // SrcReg(MaskReg) -> DestReg(GR64)
6518   // SrcReg(MaskReg) -> DestReg(GR32)
6519 
6520   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6521   if (X86::VK16RegClass.contains(SrcReg)) {
6522     if (X86::GR64RegClass.contains(DestReg)) {
6523       assert(Subtarget.hasBWI());
6524       return X86::KMOVQrk;
6525     }
6526     if (X86::GR32RegClass.contains(DestReg))
6527       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
6528   }
6529 
6530   // SrcReg(GR64) -> DestReg(MaskReg)
6531   // SrcReg(GR32) -> DestReg(MaskReg)
6532 
6533   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6534   if (X86::VK16RegClass.contains(DestReg)) {
6535     if (X86::GR64RegClass.contains(SrcReg)) {
6536       assert(Subtarget.hasBWI());
6537       return X86::KMOVQkr;
6538     }
6539     if (X86::GR32RegClass.contains(SrcReg))
6540       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
6541   }
6542 
6543 
6544   // SrcReg(VR128) -> DestReg(GR64)
6545   // SrcReg(VR64)  -> DestReg(GR64)
6546   // SrcReg(GR64)  -> DestReg(VR128)
6547   // SrcReg(GR64)  -> DestReg(VR64)
6548 
6549   if (X86::GR64RegClass.contains(DestReg)) {
6550     if (X86::VR128XRegClass.contains(SrcReg))
6551       // Copy from a VR128 register to a GR64 register.
6552       return HasAVX512 ? X86::VMOVPQIto64Zrr :
6553              HasAVX    ? X86::VMOVPQIto64rr  :
6554                          X86::MOVPQIto64rr;
6555     if (X86::VR64RegClass.contains(SrcReg))
6556       // Copy from a VR64 register to a GR64 register.
6557       return X86::MMX_MOVD64from64rr;
6558   } else if (X86::GR64RegClass.contains(SrcReg)) {
6559     // Copy from a GR64 register to a VR128 register.
6560     if (X86::VR128XRegClass.contains(DestReg))
6561       return HasAVX512 ? X86::VMOV64toPQIZrr :
6562              HasAVX    ? X86::VMOV64toPQIrr  :
6563                          X86::MOV64toPQIrr;
6564     // Copy from a GR64 register to a VR64 register.
6565     if (X86::VR64RegClass.contains(DestReg))
6566       return X86::MMX_MOVD64to64rr;
6567   }
6568 
6569   // SrcReg(FR32) -> DestReg(GR32)
6570   // SrcReg(GR32) -> DestReg(FR32)
6571 
6572   if (X86::GR32RegClass.contains(DestReg) &&
6573       X86::FR32XRegClass.contains(SrcReg))
6574     // Copy from a FR32 register to a GR32 register.
6575     return HasAVX512 ? X86::VMOVSS2DIZrr :
6576            HasAVX    ? X86::VMOVSS2DIrr  :
6577                        X86::MOVSS2DIrr;
6578 
6579   if (X86::FR32XRegClass.contains(DestReg) &&
6580       X86::GR32RegClass.contains(SrcReg))
6581     // Copy from a GR32 register to a FR32 register.
6582     return HasAVX512 ? X86::VMOVDI2SSZrr :
6583            HasAVX    ? X86::VMOVDI2SSrr  :
6584                        X86::MOVDI2SSrr;
6585   return 0;
6586 }
6587 
6588 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
6589                                MachineBasicBlock::iterator MI,
6590                                const DebugLoc &DL, unsigned DestReg,
6591                                unsigned SrcReg, bool KillSrc) const {
6592   // First deal with the normal symmetric copies.
6593   bool HasAVX = Subtarget.hasAVX();
6594   bool HasVLX = Subtarget.hasVLX();
6595   unsigned Opc = 0;
6596   if (X86::GR64RegClass.contains(DestReg, SrcReg))
6597     Opc = X86::MOV64rr;
6598   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
6599     Opc = X86::MOV32rr;
6600   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
6601     Opc = X86::MOV16rr;
6602   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
6603     // Copying to or from a physical H register on x86-64 must ensure it
6604     // doesn't require a REX prefix for the other register.
6605     if ((isHReg(DestReg) || isHReg(SrcReg)) && Subtarget.is64Bit()) {
6606       // Both operands must be encodable without an REX prefix.
6607       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
6608              "8-bit H register can not be copied outside GR8_NOREX");
6609     }
6610     Opc = X86::MOV8rr;
6611   }
6612   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
6613     Opc = X86::MMX_MOVQ64rr;
6614   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
6615     if (HasVLX)
6616       Opc = X86::VMOVAPSZ128rr;
6617     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
6618       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
6619     else {
6620       // If this an extended register and we don't have VLX we need to use a
6621       // 512-bit move.
6622       Opc = X86::VMOVAPSZrr;
6623       const TargetRegisterInfo *TRI = &getRegisterInfo();
6624       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
6625                                          &X86::VR512RegClass);
6626       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
6627                                         &X86::VR512RegClass);
6628     }
6629   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
6630     if (HasVLX)
6631       Opc = X86::VMOVAPSZ256rr;
6632     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
6633       Opc = X86::VMOVAPSYrr;
6634     else {
6635       // If this an extended register and we don't have VLX we need to use a
6636       // 512-bit move.
6637       Opc = X86::VMOVAPSZrr;
6638       const TargetRegisterInfo *TRI = &getRegisterInfo();
6639       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
6640                                          &X86::VR512RegClass);
6641       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
6642                                         &X86::VR512RegClass);
6643     }
6644   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
6645     Opc = X86::VMOVAPSZrr;
6646   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6647   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
6648     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
6649   if (!Opc)
6650     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
6651 
6652   if (Opc) {
6653     BuildMI(MBB, MI, DL, get(Opc), DestReg)
6654       .addReg(SrcReg, getKillRegState(KillSrc));
6655     return;
6656   }
6657 
6658   bool FromEFLAGS = SrcReg == X86::EFLAGS;
6659   bool ToEFLAGS = DestReg == X86::EFLAGS;
6660   int Reg = FromEFLAGS ? DestReg : SrcReg;
6661   bool is32 = X86::GR32RegClass.contains(Reg);
6662   bool is64 = X86::GR64RegClass.contains(Reg);
6663 
6664   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
6665     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
6666     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
6667     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
6668     int Pop = is64 ? X86::POP64r : X86::POP32r;
6669     int PopF = is64 ? X86::POPF64 : X86::POPF32;
6670     int AX = is64 ? X86::RAX : X86::EAX;
6671 
6672     if (!Subtarget.hasLAHFSAHF()) {
6673       assert(Subtarget.is64Bit() &&
6674              "Not having LAHF/SAHF only happens on 64-bit.");
6675       // Moving EFLAGS to / from another register requires a push and a pop.
6676       // Notice that we have to adjust the stack if we don't want to clobber the
6677       // first frame index. See X86FrameLowering.cpp - usesTheStack.
6678       if (FromEFLAGS) {
6679         BuildMI(MBB, MI, DL, get(PushF));
6680         BuildMI(MBB, MI, DL, get(Pop), DestReg);
6681       }
6682       if (ToEFLAGS) {
6683         BuildMI(MBB, MI, DL, get(Push))
6684             .addReg(SrcReg, getKillRegState(KillSrc));
6685         BuildMI(MBB, MI, DL, get(PopF));
6686       }
6687       return;
6688     }
6689 
6690     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
6691     // inefficient. Instead:
6692     //   - Save the overflow flag OF into AL using SETO, and restore it using a
6693     //     signed 8-bit addition of AL and INT8_MAX.
6694     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
6695     //     using LAHF/SAHF.
6696     //   - When RAX/EAX is live and isn't the destination register, make sure it
6697     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
6698     //     the flags.
6699     // This approach is ~2.25x faster than using PUSHF/POPF.
6700     //
6701     // This is still somewhat inefficient because we don't know which flags are
6702     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
6703     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
6704     //
6705     // PUSHF/POPF is also potentially incorrect because it affects other flags
6706     // such as TF/IF/DF, which LLVM doesn't model.
6707     //
6708     // Notice that we have to adjust the stack if we don't want to clobber the
6709     // first frame index.
6710     // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
6711 
6712     const TargetRegisterInfo &TRI = getRegisterInfo();
6713     MachineBasicBlock::LivenessQueryResult LQR =
6714         MBB.computeRegisterLiveness(&TRI, AX, MI);
6715     // We do not want to save and restore AX if we do not have to.
6716     // Moreover, if we do so whereas AX is dead, we would need to set
6717     // an undef flag on the use of AX, otherwise the verifier will
6718     // complain that we read an undef value.
6719     // We do not want to change the behavior of the machine verifier
6720     // as this is usually wrong to read an undef value.
6721     if (MachineBasicBlock::LQR_Unknown == LQR) {
6722       LivePhysRegs LPR(TRI);
6723       LPR.addLiveOuts(MBB);
6724       MachineBasicBlock::iterator I = MBB.end();
6725       while (I != MI) {
6726         --I;
6727         LPR.stepBackward(*I);
6728       }
6729       // AX contains the top most register in the aliasing hierarchy.
6730       // It may not be live, but one of its aliases may be.
6731       for (MCRegAliasIterator AI(AX, &TRI, true);
6732            AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
6733         LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
6734                                 : MachineBasicBlock::LQR_Dead;
6735     }
6736     bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
6737     if (!AXDead)
6738       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
6739     if (FromEFLAGS) {
6740       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
6741       BuildMI(MBB, MI, DL, get(X86::LAHF));
6742       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
6743     }
6744     if (ToEFLAGS) {
6745       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
6746       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
6747           .addReg(X86::AL)
6748           .addImm(INT8_MAX);
6749       BuildMI(MBB, MI, DL, get(X86::SAHF));
6750     }
6751     if (!AXDead)
6752       BuildMI(MBB, MI, DL, get(Pop), AX);
6753     return;
6754   }
6755 
6756   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
6757                << " to " << RI.getName(DestReg) << '\n');
6758   llvm_unreachable("Cannot emit physreg copy instruction");
6759 }
6760 
6761 static unsigned getLoadStoreRegOpcode(unsigned Reg,
6762                                       const TargetRegisterClass *RC,
6763                                       bool isStackAligned,
6764                                       const X86Subtarget &STI,
6765                                       bool load) {
6766   bool HasAVX = STI.hasAVX();
6767   bool HasAVX512 = STI.hasAVX512();
6768   bool HasVLX = STI.hasVLX();
6769 
6770   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
6771   default:
6772     llvm_unreachable("Unknown spill size");
6773   case 1:
6774     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
6775     if (STI.is64Bit())
6776       // Copying to or from a physical H register on x86-64 requires a NOREX
6777       // move.  Otherwise use a normal move.
6778       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
6779         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
6780     return load ? X86::MOV8rm : X86::MOV8mr;
6781   case 2:
6782     if (X86::VK16RegClass.hasSubClassEq(RC))
6783       return load ? X86::KMOVWkm : X86::KMOVWmk;
6784     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
6785     return load ? X86::MOV16rm : X86::MOV16mr;
6786   case 4:
6787     if (X86::GR32RegClass.hasSubClassEq(RC))
6788       return load ? X86::MOV32rm : X86::MOV32mr;
6789     if (X86::FR32XRegClass.hasSubClassEq(RC))
6790       return load ?
6791         (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
6792         (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
6793     if (X86::RFP32RegClass.hasSubClassEq(RC))
6794       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
6795     if (X86::VK32RegClass.hasSubClassEq(RC))
6796       return load ? X86::KMOVDkm : X86::KMOVDmk;
6797     llvm_unreachable("Unknown 4-byte regclass");
6798   case 8:
6799     if (X86::GR64RegClass.hasSubClassEq(RC))
6800       return load ? X86::MOV64rm : X86::MOV64mr;
6801     if (X86::FR64XRegClass.hasSubClassEq(RC))
6802       return load ?
6803         (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
6804         (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
6805     if (X86::VR64RegClass.hasSubClassEq(RC))
6806       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
6807     if (X86::RFP64RegClass.hasSubClassEq(RC))
6808       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
6809     if (X86::VK64RegClass.hasSubClassEq(RC))
6810       return load ? X86::KMOVQkm : X86::KMOVQmk;
6811     llvm_unreachable("Unknown 8-byte regclass");
6812   case 10:
6813     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
6814     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
6815   case 16: {
6816     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
6817       // If stack is realigned we can use aligned stores.
6818       if (isStackAligned)
6819         return load ?
6820           (HasVLX    ? X86::VMOVAPSZ128rm :
6821            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
6822            HasAVX    ? X86::VMOVAPSrm :
6823                        X86::MOVAPSrm):
6824           (HasVLX    ? X86::VMOVAPSZ128mr :
6825            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
6826            HasAVX    ? X86::VMOVAPSmr :
6827                        X86::MOVAPSmr);
6828       else
6829         return load ?
6830           (HasVLX    ? X86::VMOVUPSZ128rm :
6831            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
6832            HasAVX    ? X86::VMOVUPSrm :
6833                        X86::MOVUPSrm):
6834           (HasVLX    ? X86::VMOVUPSZ128mr :
6835            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
6836            HasAVX    ? X86::VMOVUPSmr :
6837                        X86::MOVUPSmr);
6838     }
6839     if (X86::BNDRRegClass.hasSubClassEq(RC)) {
6840       if (STI.is64Bit())
6841         return load ? X86::BNDMOVRM64rm : X86::BNDMOVMR64mr;
6842       else
6843         return load ? X86::BNDMOVRM32rm : X86::BNDMOVMR32mr;
6844     }
6845     llvm_unreachable("Unknown 16-byte regclass");
6846   }
6847   case 32:
6848     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
6849     // If stack is realigned we can use aligned stores.
6850     if (isStackAligned)
6851       return load ?
6852         (HasVLX    ? X86::VMOVAPSZ256rm :
6853          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
6854                      X86::VMOVAPSYrm) :
6855         (HasVLX    ? X86::VMOVAPSZ256mr :
6856          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
6857                      X86::VMOVAPSYmr);
6858     else
6859       return load ?
6860         (HasVLX    ? X86::VMOVUPSZ256rm :
6861          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
6862                      X86::VMOVUPSYrm) :
6863         (HasVLX    ? X86::VMOVUPSZ256mr :
6864          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
6865                      X86::VMOVUPSYmr);
6866   case 64:
6867     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
6868     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
6869     if (isStackAligned)
6870       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
6871     else
6872       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
6873   }
6874 }
6875 
6876 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
6877                                          int64_t &Offset,
6878                                          const TargetRegisterInfo *TRI) const {
6879   const MCInstrDesc &Desc = MemOp.getDesc();
6880   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
6881   if (MemRefBegin < 0)
6882     return false;
6883 
6884   MemRefBegin += X86II::getOperandBias(Desc);
6885 
6886   MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
6887   if (!BaseMO.isReg()) // Can be an MO_FrameIndex
6888     return false;
6889 
6890   BaseReg = BaseMO.getReg();
6891   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
6892     return false;
6893 
6894   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
6895       X86::NoRegister)
6896     return false;
6897 
6898   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
6899 
6900   // Displacement can be symbolic
6901   if (!DispMO.isImm())
6902     return false;
6903 
6904   Offset = DispMO.getImm();
6905 
6906   return true;
6907 }
6908 
6909 static unsigned getStoreRegOpcode(unsigned SrcReg,
6910                                   const TargetRegisterClass *RC,
6911                                   bool isStackAligned,
6912                                   const X86Subtarget &STI) {
6913   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
6914 }
6915 
6916 
6917 static unsigned getLoadRegOpcode(unsigned DestReg,
6918                                  const TargetRegisterClass *RC,
6919                                  bool isStackAligned,
6920                                  const X86Subtarget &STI) {
6921   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
6922 }
6923 
6924 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
6925                                        MachineBasicBlock::iterator MI,
6926                                        unsigned SrcReg, bool isKill, int FrameIdx,
6927                                        const TargetRegisterClass *RC,
6928                                        const TargetRegisterInfo *TRI) const {
6929   const MachineFunction &MF = *MBB.getParent();
6930   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
6931          "Stack slot too small for store");
6932   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
6933   bool isAligned =
6934       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
6935       RI.canRealignStack(MF);
6936   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
6937   DebugLoc DL = MBB.findDebugLoc(MI);
6938   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
6939     .addReg(SrcReg, getKillRegState(isKill));
6940 }
6941 
6942 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
6943                                   bool isKill,
6944                                   SmallVectorImpl<MachineOperand> &Addr,
6945                                   const TargetRegisterClass *RC,
6946                                   MachineInstr::mmo_iterator MMOBegin,
6947                                   MachineInstr::mmo_iterator MMOEnd,
6948                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
6949   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6950   unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6951   bool isAligned = MMOBegin != MMOEnd &&
6952                    (*MMOBegin)->getAlignment() >= Alignment;
6953   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
6954   DebugLoc DL;
6955   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6956   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
6957     MIB.add(Addr[i]);
6958   MIB.addReg(SrcReg, getKillRegState(isKill));
6959   (*MIB).setMemRefs(MMOBegin, MMOEnd);
6960   NewMIs.push_back(MIB);
6961 }
6962 
6963 
6964 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
6965                                         MachineBasicBlock::iterator MI,
6966                                         unsigned DestReg, int FrameIdx,
6967                                         const TargetRegisterClass *RC,
6968                                         const TargetRegisterInfo *TRI) const {
6969   const MachineFunction &MF = *MBB.getParent();
6970   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
6971   bool isAligned =
6972       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
6973       RI.canRealignStack(MF);
6974   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
6975   DebugLoc DL = MBB.findDebugLoc(MI);
6976   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
6977 }
6978 
6979 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
6980                                  SmallVectorImpl<MachineOperand> &Addr,
6981                                  const TargetRegisterClass *RC,
6982                                  MachineInstr::mmo_iterator MMOBegin,
6983                                  MachineInstr::mmo_iterator MMOEnd,
6984                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
6985   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6986   unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6987   bool isAligned = MMOBegin != MMOEnd &&
6988                    (*MMOBegin)->getAlignment() >= Alignment;
6989   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
6990   DebugLoc DL;
6991   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
6992   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
6993     MIB.add(Addr[i]);
6994   (*MIB).setMemRefs(MMOBegin, MMOEnd);
6995   NewMIs.push_back(MIB);
6996 }
6997 
6998 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
6999                                   unsigned &SrcReg2, int &CmpMask,
7000                                   int &CmpValue) const {
7001   switch (MI.getOpcode()) {
7002   default: break;
7003   case X86::CMP64ri32:
7004   case X86::CMP64ri8:
7005   case X86::CMP32ri:
7006   case X86::CMP32ri8:
7007   case X86::CMP16ri:
7008   case X86::CMP16ri8:
7009   case X86::CMP8ri:
7010     SrcReg = MI.getOperand(0).getReg();
7011     SrcReg2 = 0;
7012     if (MI.getOperand(1).isImm()) {
7013       CmpMask = ~0;
7014       CmpValue = MI.getOperand(1).getImm();
7015     } else {
7016       CmpMask = CmpValue = 0;
7017     }
7018     return true;
7019   // A SUB can be used to perform comparison.
7020   case X86::SUB64rm:
7021   case X86::SUB32rm:
7022   case X86::SUB16rm:
7023   case X86::SUB8rm:
7024     SrcReg = MI.getOperand(1).getReg();
7025     SrcReg2 = 0;
7026     CmpMask = 0;
7027     CmpValue = 0;
7028     return true;
7029   case X86::SUB64rr:
7030   case X86::SUB32rr:
7031   case X86::SUB16rr:
7032   case X86::SUB8rr:
7033     SrcReg = MI.getOperand(1).getReg();
7034     SrcReg2 = MI.getOperand(2).getReg();
7035     CmpMask = 0;
7036     CmpValue = 0;
7037     return true;
7038   case X86::SUB64ri32:
7039   case X86::SUB64ri8:
7040   case X86::SUB32ri:
7041   case X86::SUB32ri8:
7042   case X86::SUB16ri:
7043   case X86::SUB16ri8:
7044   case X86::SUB8ri:
7045     SrcReg = MI.getOperand(1).getReg();
7046     SrcReg2 = 0;
7047     if (MI.getOperand(2).isImm()) {
7048       CmpMask = ~0;
7049       CmpValue = MI.getOperand(2).getImm();
7050     } else {
7051       CmpMask = CmpValue = 0;
7052     }
7053     return true;
7054   case X86::CMP64rr:
7055   case X86::CMP32rr:
7056   case X86::CMP16rr:
7057   case X86::CMP8rr:
7058     SrcReg = MI.getOperand(0).getReg();
7059     SrcReg2 = MI.getOperand(1).getReg();
7060     CmpMask = 0;
7061     CmpValue = 0;
7062     return true;
7063   case X86::TEST8rr:
7064   case X86::TEST16rr:
7065   case X86::TEST32rr:
7066   case X86::TEST64rr:
7067     SrcReg = MI.getOperand(0).getReg();
7068     if (MI.getOperand(1).getReg() != SrcReg)
7069       return false;
7070     // Compare against zero.
7071     SrcReg2 = 0;
7072     CmpMask = ~0;
7073     CmpValue = 0;
7074     return true;
7075   }
7076   return false;
7077 }
7078 
7079 /// Check whether the first instruction, whose only
7080 /// purpose is to update flags, can be made redundant.
7081 /// CMPrr can be made redundant by SUBrr if the operands are the same.
7082 /// This function can be extended later on.
7083 /// SrcReg, SrcRegs: register operands for FlagI.
7084 /// ImmValue: immediate for FlagI if it takes an immediate.
7085 inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
7086                                         unsigned SrcReg2, int ImmMask,
7087                                         int ImmValue, MachineInstr &OI) {
7088   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
7089        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
7090        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
7091        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
7092       ((OI.getOperand(1).getReg() == SrcReg &&
7093         OI.getOperand(2).getReg() == SrcReg2) ||
7094        (OI.getOperand(1).getReg() == SrcReg2 &&
7095         OI.getOperand(2).getReg() == SrcReg)))
7096     return true;
7097 
7098   if (ImmMask != 0 &&
7099       ((FlagI.getOpcode() == X86::CMP64ri32 &&
7100         OI.getOpcode() == X86::SUB64ri32) ||
7101        (FlagI.getOpcode() == X86::CMP64ri8 &&
7102         OI.getOpcode() == X86::SUB64ri8) ||
7103        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
7104        (FlagI.getOpcode() == X86::CMP32ri8 &&
7105         OI.getOpcode() == X86::SUB32ri8) ||
7106        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
7107        (FlagI.getOpcode() == X86::CMP16ri8 &&
7108         OI.getOpcode() == X86::SUB16ri8) ||
7109        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
7110       OI.getOperand(1).getReg() == SrcReg &&
7111       OI.getOperand(2).getImm() == ImmValue)
7112     return true;
7113   return false;
7114 }
7115 
7116 /// Check whether the definition can be converted
7117 /// to remove a comparison against zero.
7118 inline static bool isDefConvertible(MachineInstr &MI) {
7119   switch (MI.getOpcode()) {
7120   default: return false;
7121 
7122   // The shift instructions only modify ZF if their shift count is non-zero.
7123   // N.B.: The processor truncates the shift count depending on the encoding.
7124   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
7125   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
7126      return getTruncatedShiftCount(MI, 2) != 0;
7127 
7128   // Some left shift instructions can be turned into LEA instructions but only
7129   // if their flags aren't used. Avoid transforming such instructions.
7130   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
7131     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
7132     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
7133     return ShAmt != 0;
7134   }
7135 
7136   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
7137   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
7138      return getTruncatedShiftCount(MI, 3) != 0;
7139 
7140   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
7141   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
7142   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
7143   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
7144   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
7145   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
7146   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
7147   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
7148   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
7149   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
7150   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
7151   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
7152   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
7153   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
7154   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
7155   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
7156   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
7157   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
7158   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
7159   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
7160   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
7161   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
7162   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
7163   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
7164   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
7165   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
7166   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
7167   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
7168   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
7169   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
7170   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
7171   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
7172   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
7173   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
7174   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
7175   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
7176   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
7177   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
7178   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
7179   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
7180   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
7181   case X86::ANDN32rr:  case X86::ANDN32rm:
7182   case X86::ANDN64rr:  case X86::ANDN64rm:
7183   case X86::BEXTR32rr: case X86::BEXTR64rr:
7184   case X86::BEXTR32rm: case X86::BEXTR64rm:
7185   case X86::BLSI32rr:  case X86::BLSI32rm:
7186   case X86::BLSI64rr:  case X86::BLSI64rm:
7187   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
7188   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
7189   case X86::BLSR32rr:  case X86::BLSR32rm:
7190   case X86::BLSR64rr:  case X86::BLSR64rm:
7191   case X86::BZHI32rr:  case X86::BZHI32rm:
7192   case X86::BZHI64rr:  case X86::BZHI64rm:
7193   case X86::LZCNT16rr: case X86::LZCNT16rm:
7194   case X86::LZCNT32rr: case X86::LZCNT32rm:
7195   case X86::LZCNT64rr: case X86::LZCNT64rm:
7196   case X86::POPCNT16rr:case X86::POPCNT16rm:
7197   case X86::POPCNT32rr:case X86::POPCNT32rm:
7198   case X86::POPCNT64rr:case X86::POPCNT64rm:
7199   case X86::TZCNT16rr: case X86::TZCNT16rm:
7200   case X86::TZCNT32rr: case X86::TZCNT32rm:
7201   case X86::TZCNT64rr: case X86::TZCNT64rm:
7202   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
7203   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
7204   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
7205   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
7206   case X86::BLCI32rr:    case X86::BLCI32rm:
7207   case X86::BLCI64rr:    case X86::BLCI64rm:
7208   case X86::BLCIC32rr:   case X86::BLCIC32rm:
7209   case X86::BLCIC64rr:   case X86::BLCIC64rm:
7210   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
7211   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
7212   case X86::BLCS32rr:    case X86::BLCS32rm:
7213   case X86::BLCS64rr:    case X86::BLCS64rm:
7214   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
7215   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
7216   case X86::BLSIC32rr:   case X86::BLSIC32rm:
7217   case X86::BLSIC64rr:   case X86::BLSIC64rm:
7218     return true;
7219   }
7220 }
7221 
7222 /// Check whether the use can be converted to remove a comparison against zero.
7223 static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
7224   switch (MI.getOpcode()) {
7225   default: return X86::COND_INVALID;
7226   case X86::LZCNT16rr: case X86::LZCNT16rm:
7227   case X86::LZCNT32rr: case X86::LZCNT32rm:
7228   case X86::LZCNT64rr: case X86::LZCNT64rm:
7229     return X86::COND_B;
7230   case X86::POPCNT16rr:case X86::POPCNT16rm:
7231   case X86::POPCNT32rr:case X86::POPCNT32rm:
7232   case X86::POPCNT64rr:case X86::POPCNT64rm:
7233     return X86::COND_E;
7234   case X86::TZCNT16rr: case X86::TZCNT16rm:
7235   case X86::TZCNT32rr: case X86::TZCNT32rm:
7236   case X86::TZCNT64rr: case X86::TZCNT64rm:
7237     return X86::COND_B;
7238   }
7239 }
7240 
7241 /// Check if there exists an earlier instruction that
7242 /// operates on the same source operands and sets flags in the same way as
7243 /// Compare; remove Compare if possible.
7244 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
7245                                         unsigned SrcReg2, int CmpMask,
7246                                         int CmpValue,
7247                                         const MachineRegisterInfo *MRI) const {
7248   // Check whether we can replace SUB with CMP.
7249   unsigned NewOpcode = 0;
7250   switch (CmpInstr.getOpcode()) {
7251   default: break;
7252   case X86::SUB64ri32:
7253   case X86::SUB64ri8:
7254   case X86::SUB32ri:
7255   case X86::SUB32ri8:
7256   case X86::SUB16ri:
7257   case X86::SUB16ri8:
7258   case X86::SUB8ri:
7259   case X86::SUB64rm:
7260   case X86::SUB32rm:
7261   case X86::SUB16rm:
7262   case X86::SUB8rm:
7263   case X86::SUB64rr:
7264   case X86::SUB32rr:
7265   case X86::SUB16rr:
7266   case X86::SUB8rr: {
7267     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
7268       return false;
7269     // There is no use of the destination register, we can replace SUB with CMP.
7270     switch (CmpInstr.getOpcode()) {
7271     default: llvm_unreachable("Unreachable!");
7272     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
7273     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
7274     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
7275     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
7276     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
7277     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
7278     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
7279     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
7280     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
7281     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
7282     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
7283     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
7284     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
7285     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
7286     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
7287     }
7288     CmpInstr.setDesc(get(NewOpcode));
7289     CmpInstr.RemoveOperand(0);
7290     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
7291     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
7292         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
7293       return false;
7294   }
7295   }
7296 
7297   // Get the unique definition of SrcReg.
7298   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
7299   if (!MI) return false;
7300 
7301   // CmpInstr is the first instruction of the BB.
7302   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
7303 
7304   // If we are comparing against zero, check whether we can use MI to update
7305   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
7306   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
7307   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
7308     return false;
7309 
7310   // If we have a use of the source register between the def and our compare
7311   // instruction we can eliminate the compare iff the use sets EFLAGS in the
7312   // right way.
7313   bool ShouldUpdateCC = false;
7314   X86::CondCode NewCC = X86::COND_INVALID;
7315   if (IsCmpZero && !isDefConvertible(*MI)) {
7316     // Scan forward from the use until we hit the use we're looking for or the
7317     // compare instruction.
7318     for (MachineBasicBlock::iterator J = MI;; ++J) {
7319       // Do we have a convertible instruction?
7320       NewCC = isUseDefConvertible(*J);
7321       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
7322           J->getOperand(1).getReg() == SrcReg) {
7323         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
7324         ShouldUpdateCC = true; // Update CC later on.
7325         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
7326         // with the new def.
7327         Def = J;
7328         MI = &*Def;
7329         break;
7330       }
7331 
7332       if (J == I)
7333         return false;
7334     }
7335   }
7336 
7337   // We are searching for an earlier instruction that can make CmpInstr
7338   // redundant and that instruction will be saved in Sub.
7339   MachineInstr *Sub = nullptr;
7340   const TargetRegisterInfo *TRI = &getRegisterInfo();
7341 
7342   // We iterate backward, starting from the instruction before CmpInstr and
7343   // stop when reaching the definition of a source register or done with the BB.
7344   // RI points to the instruction before CmpInstr.
7345   // If the definition is in this basic block, RE points to the definition;
7346   // otherwise, RE is the rend of the basic block.
7347   MachineBasicBlock::reverse_iterator
7348       RI = ++I.getReverse(),
7349       RE = CmpInstr.getParent() == MI->getParent()
7350                ? Def.getReverse() /* points to MI */
7351                : CmpInstr.getParent()->rend();
7352   MachineInstr *Movr0Inst = nullptr;
7353   for (; RI != RE; ++RI) {
7354     MachineInstr &Instr = *RI;
7355     // Check whether CmpInstr can be made redundant by the current instruction.
7356     if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
7357                                            CmpValue, Instr)) {
7358       Sub = &Instr;
7359       break;
7360     }
7361 
7362     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
7363         Instr.readsRegister(X86::EFLAGS, TRI)) {
7364       // This instruction modifies or uses EFLAGS.
7365 
7366       // MOV32r0 etc. are implemented with xor which clobbers condition code.
7367       // They are safe to move up, if the definition to EFLAGS is dead and
7368       // earlier instructions do not read or write EFLAGS.
7369       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
7370           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
7371         Movr0Inst = &Instr;
7372         continue;
7373       }
7374 
7375       // We can't remove CmpInstr.
7376       return false;
7377     }
7378   }
7379 
7380   // Return false if no candidates exist.
7381   if (!IsCmpZero && !Sub)
7382     return false;
7383 
7384   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
7385                     Sub->getOperand(2).getReg() == SrcReg);
7386 
7387   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
7388   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
7389   // If we are done with the basic block, we need to check whether EFLAGS is
7390   // live-out.
7391   bool IsSafe = false;
7392   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
7393   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
7394   for (++I; I != E; ++I) {
7395     const MachineInstr &Instr = *I;
7396     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
7397     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
7398     // We should check the usage if this instruction uses and updates EFLAGS.
7399     if (!UseEFLAGS && ModifyEFLAGS) {
7400       // It is safe to remove CmpInstr if EFLAGS is updated again.
7401       IsSafe = true;
7402       break;
7403     }
7404     if (!UseEFLAGS && !ModifyEFLAGS)
7405       continue;
7406 
7407     // EFLAGS is used by this instruction.
7408     X86::CondCode OldCC = X86::COND_INVALID;
7409     bool OpcIsSET = false;
7410     if (IsCmpZero || IsSwapped) {
7411       // We decode the condition code from opcode.
7412       if (Instr.isBranch())
7413         OldCC = getCondFromBranchOpc(Instr.getOpcode());
7414       else {
7415         OldCC = getCondFromSETOpc(Instr.getOpcode());
7416         if (OldCC != X86::COND_INVALID)
7417           OpcIsSET = true;
7418         else
7419           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
7420       }
7421       if (OldCC == X86::COND_INVALID) return false;
7422     }
7423     if (IsCmpZero) {
7424       switch (OldCC) {
7425       default: break;
7426       case X86::COND_A: case X86::COND_AE:
7427       case X86::COND_B: case X86::COND_BE:
7428       case X86::COND_G: case X86::COND_GE:
7429       case X86::COND_L: case X86::COND_LE:
7430       case X86::COND_O: case X86::COND_NO:
7431         // CF and OF are used, we can't perform this optimization.
7432         return false;
7433       }
7434 
7435       // If we're updating the condition code check if we have to reverse the
7436       // condition.
7437       if (ShouldUpdateCC)
7438         switch (OldCC) {
7439         default:
7440           return false;
7441         case X86::COND_E:
7442           break;
7443         case X86::COND_NE:
7444           NewCC = GetOppositeBranchCondition(NewCC);
7445           break;
7446         }
7447     } else if (IsSwapped) {
7448       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
7449       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
7450       // We swap the condition code and synthesize the new opcode.
7451       NewCC = getSwappedCondition(OldCC);
7452       if (NewCC == X86::COND_INVALID) return false;
7453     }
7454 
7455     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
7456       // Synthesize the new opcode.
7457       bool HasMemoryOperand = Instr.hasOneMemOperand();
7458       unsigned NewOpc;
7459       if (Instr.isBranch())
7460         NewOpc = GetCondBranchFromCond(NewCC);
7461       else if(OpcIsSET)
7462         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
7463       else {
7464         unsigned DstReg = Instr.getOperand(0).getReg();
7465         const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
7466         NewOpc = getCMovFromCond(NewCC, TRI->getRegSizeInBits(*DstRC)/8,
7467                                  HasMemoryOperand);
7468       }
7469 
7470       // Push the MachineInstr to OpsToUpdate.
7471       // If it is safe to remove CmpInstr, the condition code of these
7472       // instructions will be modified.
7473       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
7474     }
7475     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
7476       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
7477       IsSafe = true;
7478       break;
7479     }
7480   }
7481 
7482   // If EFLAGS is not killed nor re-defined, we should check whether it is
7483   // live-out. If it is live-out, do not optimize.
7484   if ((IsCmpZero || IsSwapped) && !IsSafe) {
7485     MachineBasicBlock *MBB = CmpInstr.getParent();
7486     for (MachineBasicBlock *Successor : MBB->successors())
7487       if (Successor->isLiveIn(X86::EFLAGS))
7488         return false;
7489   }
7490 
7491   // The instruction to be updated is either Sub or MI.
7492   Sub = IsCmpZero ? MI : Sub;
7493   // Move Movr0Inst to the appropriate place before Sub.
7494   if (Movr0Inst) {
7495     // Look backwards until we find a def that doesn't use the current EFLAGS.
7496     Def = Sub;
7497     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
7498                                         InsertE = Sub->getParent()->rend();
7499     for (; InsertI != InsertE; ++InsertI) {
7500       MachineInstr *Instr = &*InsertI;
7501       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
7502           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
7503         Sub->getParent()->remove(Movr0Inst);
7504         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
7505                                    Movr0Inst);
7506         break;
7507       }
7508     }
7509     if (InsertI == InsertE)
7510       return false;
7511   }
7512 
7513   // Make sure Sub instruction defines EFLAGS and mark the def live.
7514   unsigned i = 0, e = Sub->getNumOperands();
7515   for (; i != e; ++i) {
7516     MachineOperand &MO = Sub->getOperand(i);
7517     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
7518       MO.setIsDead(false);
7519       break;
7520     }
7521   }
7522   assert(i != e && "Unable to locate a def EFLAGS operand");
7523 
7524   CmpInstr.eraseFromParent();
7525 
7526   // Modify the condition code of instructions in OpsToUpdate.
7527   for (auto &Op : OpsToUpdate)
7528     Op.first->setDesc(get(Op.second));
7529   return true;
7530 }
7531 
7532 /// Try to remove the load by folding it to a register
7533 /// operand at the use. We fold the load instructions if load defines a virtual
7534 /// register, the virtual register is used once in the same BB, and the
7535 /// instructions in-between do not load or store, and have no side effects.
7536 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
7537                                               const MachineRegisterInfo *MRI,
7538                                               unsigned &FoldAsLoadDefReg,
7539                                               MachineInstr *&DefMI) const {
7540   // Check whether we can move DefMI here.
7541   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
7542   assert(DefMI);
7543   bool SawStore = false;
7544   if (!DefMI->isSafeToMove(nullptr, SawStore))
7545     return nullptr;
7546 
7547   // Collect information about virtual register operands of MI.
7548   SmallVector<unsigned, 1> SrcOperandIds;
7549   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
7550     MachineOperand &MO = MI.getOperand(i);
7551     if (!MO.isReg())
7552       continue;
7553     unsigned Reg = MO.getReg();
7554     if (Reg != FoldAsLoadDefReg)
7555       continue;
7556     // Do not fold if we have a subreg use or a def.
7557     if (MO.getSubReg() || MO.isDef())
7558       return nullptr;
7559     SrcOperandIds.push_back(i);
7560   }
7561   if (SrcOperandIds.empty())
7562     return nullptr;
7563 
7564   // Check whether we can fold the def into SrcOperandId.
7565   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
7566     FoldAsLoadDefReg = 0;
7567     return FoldMI;
7568   }
7569 
7570   return nullptr;
7571 }
7572 
7573 /// Expand a single-def pseudo instruction to a two-addr
7574 /// instruction with two undef reads of the register being defined.
7575 /// This is used for mapping:
7576 ///   %xmm4 = V_SET0
7577 /// to:
7578 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
7579 ///
7580 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
7581                              const MCInstrDesc &Desc) {
7582   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
7583   unsigned Reg = MIB->getOperand(0).getReg();
7584   MIB->setDesc(Desc);
7585 
7586   // MachineInstr::addOperand() will insert explicit operands before any
7587   // implicit operands.
7588   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
7589   // But we don't trust that.
7590   assert(MIB->getOperand(1).getReg() == Reg &&
7591          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
7592   return true;
7593 }
7594 
7595 /// Expand a single-def pseudo instruction to a two-addr
7596 /// instruction with two %k0 reads.
7597 /// This is used for mapping:
7598 ///   %k4 = K_SET1
7599 /// to:
7600 ///   %k4 = KXNORrr %k0, %k0
7601 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
7602                             const MCInstrDesc &Desc, unsigned Reg) {
7603   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
7604   MIB->setDesc(Desc);
7605   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
7606   return true;
7607 }
7608 
7609 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
7610                           bool MinusOne) {
7611   MachineBasicBlock &MBB = *MIB->getParent();
7612   DebugLoc DL = MIB->getDebugLoc();
7613   unsigned Reg = MIB->getOperand(0).getReg();
7614 
7615   // Insert the XOR.
7616   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
7617       .addReg(Reg, RegState::Undef)
7618       .addReg(Reg, RegState::Undef);
7619 
7620   // Turn the pseudo into an INC or DEC.
7621   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
7622   MIB.addReg(Reg);
7623 
7624   return true;
7625 }
7626 
7627 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
7628                                const TargetInstrInfo &TII,
7629                                const X86Subtarget &Subtarget) {
7630   MachineBasicBlock &MBB = *MIB->getParent();
7631   DebugLoc DL = MIB->getDebugLoc();
7632   int64_t Imm = MIB->getOperand(1).getImm();
7633   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
7634   MachineBasicBlock::iterator I = MIB.getInstr();
7635 
7636   int StackAdjustment;
7637 
7638   if (Subtarget.is64Bit()) {
7639     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
7640            MIB->getOpcode() == X86::MOV32ImmSExti8);
7641 
7642     // Can't use push/pop lowering if the function might write to the red zone.
7643     X86MachineFunctionInfo *X86FI =
7644         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
7645     if (X86FI->getUsesRedZone()) {
7646       MIB->setDesc(TII.get(MIB->getOpcode() ==
7647                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
7648       return true;
7649     }
7650 
7651     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
7652     // widen the register if necessary.
7653     StackAdjustment = 8;
7654     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
7655     MIB->setDesc(TII.get(X86::POP64r));
7656     MIB->getOperand(0)
7657         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
7658   } else {
7659     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
7660     StackAdjustment = 4;
7661     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
7662     MIB->setDesc(TII.get(X86::POP32r));
7663   }
7664 
7665   // Build CFI if necessary.
7666   MachineFunction &MF = *MBB.getParent();
7667   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
7668   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
7669   bool NeedsDwarfCFI =
7670       !IsWin64Prologue &&
7671       (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
7672   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
7673   if (EmitCFI) {
7674     TFL->BuildCFI(MBB, I, DL,
7675         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
7676     TFL->BuildCFI(MBB, std::next(I), DL,
7677         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
7678   }
7679 
7680   return true;
7681 }
7682 
7683 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
7684 // code sequence is needed for other targets.
7685 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
7686                                  const TargetInstrInfo &TII) {
7687   MachineBasicBlock &MBB = *MIB->getParent();
7688   DebugLoc DL = MIB->getDebugLoc();
7689   unsigned Reg = MIB->getOperand(0).getReg();
7690   const GlobalValue *GV =
7691       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
7692   auto Flags = MachineMemOperand::MOLoad |
7693                MachineMemOperand::MODereferenceable |
7694                MachineMemOperand::MOInvariant;
7695   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
7696       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
7697   MachineBasicBlock::iterator I = MIB.getInstr();
7698 
7699   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
7700       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
7701       .addMemOperand(MMO);
7702   MIB->setDebugLoc(DL);
7703   MIB->setDesc(TII.get(X86::MOV64rm));
7704   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
7705 }
7706 
7707 // This is used to handle spills for 128/256-bit registers when we have AVX512,
7708 // but not VLX. If it uses an extended register we need to use an instruction
7709 // that loads the lower 128/256-bit, but is available with only AVX512F.
7710 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
7711                             const TargetRegisterInfo *TRI,
7712                             const MCInstrDesc &LoadDesc,
7713                             const MCInstrDesc &BroadcastDesc,
7714                             unsigned SubIdx) {
7715   unsigned DestReg = MIB->getOperand(0).getReg();
7716   // Check if DestReg is XMM16-31 or YMM16-31.
7717   if (TRI->getEncodingValue(DestReg) < 16) {
7718     // We can use a normal VEX encoded load.
7719     MIB->setDesc(LoadDesc);
7720   } else {
7721     // Use a 128/256-bit VBROADCAST instruction.
7722     MIB->setDesc(BroadcastDesc);
7723     // Change the destination to a 512-bit register.
7724     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
7725     MIB->getOperand(0).setReg(DestReg);
7726   }
7727   return true;
7728 }
7729 
7730 // This is used to handle spills for 128/256-bit registers when we have AVX512,
7731 // but not VLX. If it uses an extended register we need to use an instruction
7732 // that stores the lower 128/256-bit, but is available with only AVX512F.
7733 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
7734                              const TargetRegisterInfo *TRI,
7735                              const MCInstrDesc &StoreDesc,
7736                              const MCInstrDesc &ExtractDesc,
7737                              unsigned SubIdx) {
7738   unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
7739   // Check if DestReg is XMM16-31 or YMM16-31.
7740   if (TRI->getEncodingValue(SrcReg) < 16) {
7741     // We can use a normal VEX encoded store.
7742     MIB->setDesc(StoreDesc);
7743   } else {
7744     // Use a VEXTRACTF instruction.
7745     MIB->setDesc(ExtractDesc);
7746     // Change the destination to a 512-bit register.
7747     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
7748     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
7749     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
7750   }
7751 
7752   return true;
7753 }
7754 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
7755   bool HasAVX = Subtarget.hasAVX();
7756   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
7757   switch (MI.getOpcode()) {
7758   case X86::MOV32r0:
7759     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
7760   case X86::MOV32r1:
7761     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
7762   case X86::MOV32r_1:
7763     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
7764   case X86::MOV32ImmSExti8:
7765   case X86::MOV64ImmSExti8:
7766     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
7767   case X86::SETB_C8r:
7768     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
7769   case X86::SETB_C16r:
7770     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
7771   case X86::SETB_C32r:
7772     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
7773   case X86::SETB_C64r:
7774     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
7775   case X86::V_SET0:
7776   case X86::FsFLD0SS:
7777   case X86::FsFLD0SD:
7778     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
7779   case X86::AVX_SET0: {
7780     assert(HasAVX && "AVX not supported");
7781     const TargetRegisterInfo *TRI = &getRegisterInfo();
7782     unsigned SrcReg = MIB->getOperand(0).getReg();
7783     unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
7784     MIB->getOperand(0).setReg(XReg);
7785     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
7786     MIB.addReg(SrcReg, RegState::ImplicitDefine);
7787     return true;
7788   }
7789   case X86::AVX512_128_SET0:
7790   case X86::AVX512_FsFLD0SS:
7791   case X86::AVX512_FsFLD0SD: {
7792     bool HasVLX = Subtarget.hasVLX();
7793     unsigned SrcReg = MIB->getOperand(0).getReg();
7794     const TargetRegisterInfo *TRI = &getRegisterInfo();
7795     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
7796       return Expand2AddrUndef(MIB,
7797                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
7798     // Extended register without VLX. Use a larger XOR.
7799     SrcReg =
7800         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
7801     MIB->getOperand(0).setReg(SrcReg);
7802     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7803   }
7804   case X86::AVX512_256_SET0: {
7805     bool HasVLX = Subtarget.hasVLX();
7806     unsigned SrcReg = MIB->getOperand(0).getReg();
7807     const TargetRegisterInfo *TRI = &getRegisterInfo();
7808     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
7809       unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
7810       MIB->getOperand(0).setReg(XReg);
7811       Expand2AddrUndef(MIB,
7812                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
7813       MIB.addReg(SrcReg, RegState::ImplicitDefine);
7814       return true;
7815     }
7816     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7817   }
7818   case X86::AVX512_512_SET0: {
7819     const TargetRegisterInfo *TRI = &getRegisterInfo();
7820     unsigned SrcReg = MIB->getOperand(0).getReg();
7821     if (TRI->getEncodingValue(SrcReg) < 16) {
7822       unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
7823       MIB->getOperand(0).setReg(XReg);
7824       Expand2AddrUndef(MIB, get(X86::VXORPSrr));
7825       MIB.addReg(SrcReg, RegState::ImplicitDefine);
7826       return true;
7827     }
7828     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7829   }
7830   case X86::V_SETALLONES:
7831     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
7832   case X86::AVX2_SETALLONES:
7833     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
7834   case X86::AVX1_SETALLONES: {
7835     unsigned Reg = MIB->getOperand(0).getReg();
7836     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
7837     MIB->setDesc(get(X86::VCMPPSYrri));
7838     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
7839     return true;
7840   }
7841   case X86::AVX512_512_SETALLONES: {
7842     unsigned Reg = MIB->getOperand(0).getReg();
7843     MIB->setDesc(get(X86::VPTERNLOGDZrri));
7844     // VPTERNLOGD needs 3 register inputs and an immediate.
7845     // 0xff will return 1s for any input.
7846     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
7847        .addReg(Reg, RegState::Undef).addImm(0xff);
7848     return true;
7849   }
7850   case X86::AVX512_512_SEXT_MASK_32:
7851   case X86::AVX512_512_SEXT_MASK_64: {
7852     unsigned Reg = MIB->getOperand(0).getReg();
7853     unsigned MaskReg = MIB->getOperand(1).getReg();
7854     unsigned MaskState = getRegState(MIB->getOperand(1));
7855     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
7856                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
7857     MI.RemoveOperand(1);
7858     MIB->setDesc(get(Opc));
7859     // VPTERNLOG needs 3 register inputs and an immediate.
7860     // 0xff will return 1s for any input.
7861     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
7862        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
7863     return true;
7864   }
7865   case X86::VMOVAPSZ128rm_NOVLX:
7866     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
7867                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
7868   case X86::VMOVUPSZ128rm_NOVLX:
7869     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
7870                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
7871   case X86::VMOVAPSZ256rm_NOVLX:
7872     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
7873                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
7874   case X86::VMOVUPSZ256rm_NOVLX:
7875     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
7876                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
7877   case X86::VMOVAPSZ128mr_NOVLX:
7878     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
7879                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
7880   case X86::VMOVUPSZ128mr_NOVLX:
7881     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
7882                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
7883   case X86::VMOVAPSZ256mr_NOVLX:
7884     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
7885                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
7886   case X86::VMOVUPSZ256mr_NOVLX:
7887     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
7888                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
7889   case X86::MOV8rr_NOREX:
7890     MI.setDesc(get(X86::MOV8rr));
7891     return true;
7892   case X86::MOV8rm_NOREX:
7893     MI.setDesc(get(X86::MOV8rm));
7894     return true;
7895   case X86::MOV8mr_NOREX:
7896     MI.setDesc(get(X86::MOV8mr));
7897     return true;
7898   case X86::MOVZX32_NOREXrr8:
7899     MI.setDesc(get(X86::MOVZX32rr8));
7900     return true;
7901   case X86::MOVZX32_NOREXrm8:
7902     MI.setDesc(get(X86::MOVZX32rm8));
7903     return true;
7904   case X86::MOVSX32_NOREXrr8:
7905     MI.setDesc(get(X86::MOVSX32rr8));
7906     return true;
7907   case X86::MOVSX32_NOREXrm8:
7908     MI.setDesc(get(X86::MOVSX32rm8));
7909     return true;
7910   case X86::TEST8ri_NOREX:
7911     MI.setDesc(get(X86::TEST8ri));
7912     return true;
7913   case X86::MOV32ri64:
7914     MI.setDesc(get(X86::MOV32ri));
7915     return true;
7916 
7917   // KNL does not recognize dependency-breaking idioms for mask registers,
7918   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
7919   // Using %k0 as the undef input register is a performance heuristic based
7920   // on the assumption that %k0 is used less frequently than the other mask
7921   // registers, since it is not usable as a write mask.
7922   // FIXME: A more advanced approach would be to choose the best input mask
7923   // register based on context.
7924   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
7925   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
7926   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
7927   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
7928   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
7929   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
7930   case TargetOpcode::LOAD_STACK_GUARD:
7931     expandLoadStackGuard(MIB, *this);
7932     return true;
7933   }
7934   return false;
7935 }
7936 
7937 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
7938                         int PtrOffset = 0) {
7939   unsigned NumAddrOps = MOs.size();
7940 
7941   if (NumAddrOps < 4) {
7942     // FrameIndex only - add an immediate offset (whether its zero or not).
7943     for (unsigned i = 0; i != NumAddrOps; ++i)
7944       MIB.add(MOs[i]);
7945     addOffset(MIB, PtrOffset);
7946   } else {
7947     // General Memory Addressing - we need to add any offset to an existing
7948     // offset.
7949     assert(MOs.size() == 5 && "Unexpected memory operand list length");
7950     for (unsigned i = 0; i != NumAddrOps; ++i) {
7951       const MachineOperand &MO = MOs[i];
7952       if (i == 3 && PtrOffset != 0) {
7953         MIB.addDisp(MO, PtrOffset);
7954       } else {
7955         MIB.add(MO);
7956       }
7957     }
7958   }
7959 }
7960 
7961 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
7962                                      ArrayRef<MachineOperand> MOs,
7963                                      MachineBasicBlock::iterator InsertPt,
7964                                      MachineInstr &MI,
7965                                      const TargetInstrInfo &TII) {
7966   // Create the base instruction with the memory operand as the first part.
7967   // Omit the implicit operands, something BuildMI can't do.
7968   MachineInstr *NewMI =
7969       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
7970   MachineInstrBuilder MIB(MF, NewMI);
7971   addOperands(MIB, MOs);
7972 
7973   // Loop over the rest of the ri operands, converting them over.
7974   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
7975   for (unsigned i = 0; i != NumOps; ++i) {
7976     MachineOperand &MO = MI.getOperand(i + 2);
7977     MIB.add(MO);
7978   }
7979   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
7980     MachineOperand &MO = MI.getOperand(i);
7981     MIB.add(MO);
7982   }
7983 
7984   MachineBasicBlock *MBB = InsertPt->getParent();
7985   MBB->insert(InsertPt, NewMI);
7986 
7987   return MIB;
7988 }
7989 
7990 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
7991                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
7992                               MachineBasicBlock::iterator InsertPt,
7993                               MachineInstr &MI, const TargetInstrInfo &TII,
7994                               int PtrOffset = 0) {
7995   // Omit the implicit operands, something BuildMI can't do.
7996   MachineInstr *NewMI =
7997       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
7998   MachineInstrBuilder MIB(MF, NewMI);
7999 
8000   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
8001     MachineOperand &MO = MI.getOperand(i);
8002     if (i == OpNo) {
8003       assert(MO.isReg() && "Expected to fold into reg operand!");
8004       addOperands(MIB, MOs, PtrOffset);
8005     } else {
8006       MIB.add(MO);
8007     }
8008   }
8009 
8010   MachineBasicBlock *MBB = InsertPt->getParent();
8011   MBB->insert(InsertPt, NewMI);
8012 
8013   return MIB;
8014 }
8015 
8016 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
8017                                 ArrayRef<MachineOperand> MOs,
8018                                 MachineBasicBlock::iterator InsertPt,
8019                                 MachineInstr &MI) {
8020   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
8021                                     MI.getDebugLoc(), TII.get(Opcode));
8022   addOperands(MIB, MOs);
8023   return MIB.addImm(0);
8024 }
8025 
8026 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
8027     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
8028     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
8029     unsigned Size, unsigned Align) const {
8030   switch (MI.getOpcode()) {
8031   case X86::INSERTPSrr:
8032   case X86::VINSERTPSrr:
8033   case X86::VINSERTPSZrr:
8034     // Attempt to convert the load of inserted vector into a fold load
8035     // of a single float.
8036     if (OpNum == 2) {
8037       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
8038       unsigned ZMask = Imm & 15;
8039       unsigned DstIdx = (Imm >> 4) & 3;
8040       unsigned SrcIdx = (Imm >> 6) & 3;
8041 
8042       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8043       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
8044       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
8045       if (Size <= RCSize && 4 <= Align) {
8046         int PtrOffset = SrcIdx * 4;
8047         unsigned NewImm = (DstIdx << 4) | ZMask;
8048         unsigned NewOpCode =
8049             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
8050             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
8051                                                     X86::INSERTPSrm;
8052         MachineInstr *NewMI =
8053             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
8054         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
8055         return NewMI;
8056       }
8057     }
8058     break;
8059   case X86::MOVHLPSrr:
8060   case X86::VMOVHLPSrr:
8061   case X86::VMOVHLPSZrr:
8062     // Move the upper 64-bits of the second operand to the lower 64-bits.
8063     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
8064     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
8065     if (OpNum == 2) {
8066       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8067       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
8068       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
8069       if (Size <= RCSize && 8 <= Align) {
8070         unsigned NewOpCode =
8071             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
8072             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
8073                                                    X86::MOVLPSrm;
8074         MachineInstr *NewMI =
8075             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
8076         return NewMI;
8077       }
8078     }
8079     break;
8080   };
8081 
8082   return nullptr;
8083 }
8084 
8085 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
8086     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
8087     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
8088     unsigned Size, unsigned Align, bool AllowCommute) const {
8089   const DenseMap<unsigned,
8090                  std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
8091   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
8092   bool isTwoAddrFold = false;
8093 
8094   // For CPUs that favor the register form of a call or push,
8095   // do not fold loads into calls or pushes, unless optimizing for size
8096   // aggressively.
8097   if (isSlowTwoMemOps && !MF.getFunction()->optForMinSize() &&
8098       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
8099        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
8100        MI.getOpcode() == X86::PUSH64r))
8101     return nullptr;
8102 
8103   unsigned NumOps = MI.getDesc().getNumOperands();
8104   bool isTwoAddr =
8105       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
8106 
8107   // FIXME: AsmPrinter doesn't know how to handle
8108   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
8109   if (MI.getOpcode() == X86::ADD32ri &&
8110       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
8111     return nullptr;
8112 
8113   MachineInstr *NewMI = nullptr;
8114 
8115   // Attempt to fold any custom cases we have.
8116   if (MachineInstr *CustomMI =
8117           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
8118     return CustomMI;
8119 
8120   // Folding a memory location into the two-address part of a two-address
8121   // instruction is different than folding it other places.  It requires
8122   // replacing the *two* registers with the memory location.
8123   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
8124       MI.getOperand(1).isReg() &&
8125       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
8126     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
8127     isTwoAddrFold = true;
8128   } else if (OpNum == 0) {
8129     if (MI.getOpcode() == X86::MOV32r0) {
8130       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
8131       if (NewMI)
8132         return NewMI;
8133     }
8134 
8135     OpcodeTablePtr = &RegOp2MemOpTable0;
8136   } else if (OpNum == 1) {
8137     OpcodeTablePtr = &RegOp2MemOpTable1;
8138   } else if (OpNum == 2) {
8139     OpcodeTablePtr = &RegOp2MemOpTable2;
8140   } else if (OpNum == 3) {
8141     OpcodeTablePtr = &RegOp2MemOpTable3;
8142   } else if (OpNum == 4) {
8143     OpcodeTablePtr = &RegOp2MemOpTable4;
8144   }
8145 
8146   // If table selected...
8147   if (OpcodeTablePtr) {
8148     // Find the Opcode to fuse
8149     auto I = OpcodeTablePtr->find(MI.getOpcode());
8150     if (I != OpcodeTablePtr->end()) {
8151       unsigned Opcode = I->second.first;
8152       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
8153       if (Align < MinAlign)
8154         return nullptr;
8155       bool NarrowToMOV32rm = false;
8156       if (Size) {
8157         const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8158         const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
8159                                                     &RI, MF);
8160         unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
8161         if (Size < RCSize) {
8162           // Check if it's safe to fold the load. If the size of the object is
8163           // narrower than the load width, then it's not.
8164           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
8165             return nullptr;
8166           // If this is a 64-bit load, but the spill slot is 32, then we can do
8167           // a 32-bit load which is implicitly zero-extended. This likely is
8168           // due to live interval analysis remat'ing a load from stack slot.
8169           if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
8170             return nullptr;
8171           Opcode = X86::MOV32rm;
8172           NarrowToMOV32rm = true;
8173         }
8174       }
8175 
8176       if (isTwoAddrFold)
8177         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
8178       else
8179         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
8180 
8181       if (NarrowToMOV32rm) {
8182         // If this is the special case where we use a MOV32rm to load a 32-bit
8183         // value and zero-extend the top bits. Change the destination register
8184         // to a 32-bit one.
8185         unsigned DstReg = NewMI->getOperand(0).getReg();
8186         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
8187           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
8188         else
8189           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
8190       }
8191       return NewMI;
8192     }
8193   }
8194 
8195   // If the instruction and target operand are commutable, commute the
8196   // instruction and try again.
8197   if (AllowCommute) {
8198     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
8199     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
8200       bool HasDef = MI.getDesc().getNumDefs();
8201       unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
8202       unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
8203       unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
8204       bool Tied1 =
8205           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
8206       bool Tied2 =
8207           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
8208 
8209       // If either of the commutable operands are tied to the destination
8210       // then we can not commute + fold.
8211       if ((HasDef && Reg0 == Reg1 && Tied1) ||
8212           (HasDef && Reg0 == Reg2 && Tied2))
8213         return nullptr;
8214 
8215       MachineInstr *CommutedMI =
8216           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
8217       if (!CommutedMI) {
8218         // Unable to commute.
8219         return nullptr;
8220       }
8221       if (CommutedMI != &MI) {
8222         // New instruction. We can't fold from this.
8223         CommutedMI->eraseFromParent();
8224         return nullptr;
8225       }
8226 
8227       // Attempt to fold with the commuted version of the instruction.
8228       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
8229                                     Size, Align, /*AllowCommute=*/false);
8230       if (NewMI)
8231         return NewMI;
8232 
8233       // Folding failed again - undo the commute before returning.
8234       MachineInstr *UncommutedMI =
8235           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
8236       if (!UncommutedMI) {
8237         // Unable to commute.
8238         return nullptr;
8239       }
8240       if (UncommutedMI != &MI) {
8241         // New instruction. It doesn't need to be kept.
8242         UncommutedMI->eraseFromParent();
8243         return nullptr;
8244       }
8245 
8246       // Return here to prevent duplicate fuse failure report.
8247       return nullptr;
8248     }
8249   }
8250 
8251   // No fusion
8252   if (PrintFailedFusing && !MI.isCopy())
8253     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
8254   return nullptr;
8255 }
8256 
8257 /// Return true for all instructions that only update
8258 /// the first 32 or 64-bits of the destination register and leave the rest
8259 /// unmodified. This can be used to avoid folding loads if the instructions
8260 /// only update part of the destination register, and the non-updated part is
8261 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
8262 /// instructions breaks the partial register dependency and it can improve
8263 /// performance. e.g.:
8264 ///
8265 ///   movss (%rdi), %xmm0
8266 ///   cvtss2sd %xmm0, %xmm0
8267 ///
8268 /// Instead of
8269 ///   cvtss2sd (%rdi), %xmm0
8270 ///
8271 /// FIXME: This should be turned into a TSFlags.
8272 ///
8273 static bool hasPartialRegUpdate(unsigned Opcode) {
8274   switch (Opcode) {
8275   case X86::CVTSI2SSrr:
8276   case X86::CVTSI2SSrm:
8277   case X86::CVTSI2SS64rr:
8278   case X86::CVTSI2SS64rm:
8279   case X86::CVTSI2SDrr:
8280   case X86::CVTSI2SDrm:
8281   case X86::CVTSI2SD64rr:
8282   case X86::CVTSI2SD64rm:
8283   case X86::CVTSD2SSrr:
8284   case X86::CVTSD2SSrm:
8285   case X86::CVTSS2SDrr:
8286   case X86::CVTSS2SDrm:
8287   case X86::MOVHPDrm:
8288   case X86::MOVHPSrm:
8289   case X86::MOVLPDrm:
8290   case X86::MOVLPSrm:
8291   case X86::RCPSSr:
8292   case X86::RCPSSm:
8293   case X86::RCPSSr_Int:
8294   case X86::RCPSSm_Int:
8295   case X86::ROUNDSDr:
8296   case X86::ROUNDSDm:
8297   case X86::ROUNDSSr:
8298   case X86::ROUNDSSm:
8299   case X86::RSQRTSSr:
8300   case X86::RSQRTSSm:
8301   case X86::RSQRTSSr_Int:
8302   case X86::RSQRTSSm_Int:
8303   case X86::SQRTSSr:
8304   case X86::SQRTSSm:
8305   case X86::SQRTSSr_Int:
8306   case X86::SQRTSSm_Int:
8307   case X86::SQRTSDr:
8308   case X86::SQRTSDm:
8309   case X86::SQRTSDr_Int:
8310   case X86::SQRTSDm_Int:
8311     return true;
8312   }
8313 
8314   return false;
8315 }
8316 
8317 /// Inform the ExecutionDepsFix pass how many idle
8318 /// instructions we would like before a partial register update.
8319 unsigned X86InstrInfo::getPartialRegUpdateClearance(
8320     const MachineInstr &MI, unsigned OpNum,
8321     const TargetRegisterInfo *TRI) const {
8322   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
8323     return 0;
8324 
8325   // If MI is marked as reading Reg, the partial register update is wanted.
8326   const MachineOperand &MO = MI.getOperand(0);
8327   unsigned Reg = MO.getReg();
8328   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
8329     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
8330       return 0;
8331   } else {
8332     if (MI.readsRegister(Reg, TRI))
8333       return 0;
8334   }
8335 
8336   // If any instructions in the clearance range are reading Reg, insert a
8337   // dependency breaking instruction, which is inexpensive and is likely to
8338   // be hidden in other instruction's cycles.
8339   return PartialRegUpdateClearance;
8340 }
8341 
8342 // Return true for any instruction the copies the high bits of the first source
8343 // operand into the unused high bits of the destination operand.
8344 static bool hasUndefRegUpdate(unsigned Opcode) {
8345   switch (Opcode) {
8346   case X86::VCVTSI2SSrr:
8347   case X86::VCVTSI2SSrm:
8348   case X86::Int_VCVTSI2SSrr:
8349   case X86::Int_VCVTSI2SSrm:
8350   case X86::VCVTSI2SS64rr:
8351   case X86::VCVTSI2SS64rm:
8352   case X86::Int_VCVTSI2SS64rr:
8353   case X86::Int_VCVTSI2SS64rm:
8354   case X86::VCVTSI2SDrr:
8355   case X86::VCVTSI2SDrm:
8356   case X86::Int_VCVTSI2SDrr:
8357   case X86::Int_VCVTSI2SDrm:
8358   case X86::VCVTSI2SD64rr:
8359   case X86::VCVTSI2SD64rm:
8360   case X86::Int_VCVTSI2SD64rr:
8361   case X86::Int_VCVTSI2SD64rm:
8362   case X86::VCVTSD2SSrr:
8363   case X86::VCVTSD2SSrm:
8364   case X86::Int_VCVTSD2SSrr:
8365   case X86::Int_VCVTSD2SSrm:
8366   case X86::VCVTSS2SDrr:
8367   case X86::VCVTSS2SDrm:
8368   case X86::Int_VCVTSS2SDrr:
8369   case X86::Int_VCVTSS2SDrm:
8370   case X86::VRCPSSr:
8371   case X86::VRCPSSr_Int:
8372   case X86::VRCPSSm:
8373   case X86::VRCPSSm_Int:
8374   case X86::VROUNDSDr:
8375   case X86::VROUNDSDm:
8376   case X86::VROUNDSDr_Int:
8377   case X86::VROUNDSDm_Int:
8378   case X86::VROUNDSSr:
8379   case X86::VROUNDSSm:
8380   case X86::VROUNDSSr_Int:
8381   case X86::VROUNDSSm_Int:
8382   case X86::VRSQRTSSr:
8383   case X86::VRSQRTSSr_Int:
8384   case X86::VRSQRTSSm:
8385   case X86::VRSQRTSSm_Int:
8386   case X86::VSQRTSSr:
8387   case X86::VSQRTSSr_Int:
8388   case X86::VSQRTSSm:
8389   case X86::VSQRTSSm_Int:
8390   case X86::VSQRTSDr:
8391   case X86::VSQRTSDr_Int:
8392   case X86::VSQRTSDm:
8393   case X86::VSQRTSDm_Int:
8394   // AVX-512
8395   case X86::VCVTSI2SSZrr:
8396   case X86::VCVTSI2SSZrm:
8397   case X86::VCVTSI2SSZrr_Int:
8398   case X86::VCVTSI2SSZrrb_Int:
8399   case X86::VCVTSI2SSZrm_Int:
8400   case X86::VCVTSI642SSZrr:
8401   case X86::VCVTSI642SSZrm:
8402   case X86::VCVTSI642SSZrr_Int:
8403   case X86::VCVTSI642SSZrrb_Int:
8404   case X86::VCVTSI642SSZrm_Int:
8405   case X86::VCVTSI2SDZrr:
8406   case X86::VCVTSI2SDZrm:
8407   case X86::VCVTSI2SDZrr_Int:
8408   case X86::VCVTSI2SDZrrb_Int:
8409   case X86::VCVTSI2SDZrm_Int:
8410   case X86::VCVTSI642SDZrr:
8411   case X86::VCVTSI642SDZrm:
8412   case X86::VCVTSI642SDZrr_Int:
8413   case X86::VCVTSI642SDZrrb_Int:
8414   case X86::VCVTSI642SDZrm_Int:
8415   case X86::VCVTUSI2SSZrr:
8416   case X86::VCVTUSI2SSZrm:
8417   case X86::VCVTUSI2SSZrr_Int:
8418   case X86::VCVTUSI2SSZrrb_Int:
8419   case X86::VCVTUSI2SSZrm_Int:
8420   case X86::VCVTUSI642SSZrr:
8421   case X86::VCVTUSI642SSZrm:
8422   case X86::VCVTUSI642SSZrr_Int:
8423   case X86::VCVTUSI642SSZrrb_Int:
8424   case X86::VCVTUSI642SSZrm_Int:
8425   case X86::VCVTUSI2SDZrr:
8426   case X86::VCVTUSI2SDZrm:
8427   case X86::VCVTUSI2SDZrr_Int:
8428   case X86::VCVTUSI2SDZrm_Int:
8429   case X86::VCVTUSI642SDZrr:
8430   case X86::VCVTUSI642SDZrm:
8431   case X86::VCVTUSI642SDZrr_Int:
8432   case X86::VCVTUSI642SDZrrb_Int:
8433   case X86::VCVTUSI642SDZrm_Int:
8434   case X86::VCVTSD2SSZrr:
8435   case X86::VCVTSD2SSZrr_Int:
8436   case X86::VCVTSD2SSZrrb_Int:
8437   case X86::VCVTSD2SSZrm:
8438   case X86::VCVTSD2SSZrm_Int:
8439   case X86::VCVTSS2SDZrr:
8440   case X86::VCVTSS2SDZrr_Int:
8441   case X86::VCVTSS2SDZrrb_Int:
8442   case X86::VCVTSS2SDZrm:
8443   case X86::VCVTSS2SDZrm_Int:
8444   case X86::VRNDSCALESDr:
8445   case X86::VRNDSCALESDrb:
8446   case X86::VRNDSCALESDm:
8447   case X86::VRNDSCALESSr:
8448   case X86::VRNDSCALESSrb:
8449   case X86::VRNDSCALESSm:
8450   case X86::VRCP14SSrr:
8451   case X86::VRCP14SSrm:
8452   case X86::VRSQRT14SSrr:
8453   case X86::VRSQRT14SSrm:
8454   case X86::VSQRTSSZr:
8455   case X86::VSQRTSSZr_Int:
8456   case X86::VSQRTSSZrb_Int:
8457   case X86::VSQRTSSZm:
8458   case X86::VSQRTSSZm_Int:
8459   case X86::VSQRTSDZr:
8460   case X86::VSQRTSDZr_Int:
8461   case X86::VSQRTSDZrb_Int:
8462   case X86::VSQRTSDZm:
8463   case X86::VSQRTSDZm_Int:
8464     return true;
8465   }
8466 
8467   return false;
8468 }
8469 
8470 /// Inform the ExecutionDepsFix pass how many idle instructions we would like
8471 /// before certain undef register reads.
8472 ///
8473 /// This catches the VCVTSI2SD family of instructions:
8474 ///
8475 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
8476 ///
8477 /// We should to be careful *not* to catch VXOR idioms which are presumably
8478 /// handled specially in the pipeline:
8479 ///
8480 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
8481 ///
8482 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
8483 /// high bits that are passed-through are not live.
8484 unsigned
8485 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
8486                                    const TargetRegisterInfo *TRI) const {
8487   if (!hasUndefRegUpdate(MI.getOpcode()))
8488     return 0;
8489 
8490   // Set the OpNum parameter to the first source operand.
8491   OpNum = 1;
8492 
8493   const MachineOperand &MO = MI.getOperand(OpNum);
8494   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
8495     return UndefRegClearance;
8496   }
8497   return 0;
8498 }
8499 
8500 void X86InstrInfo::breakPartialRegDependency(
8501     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
8502   unsigned Reg = MI.getOperand(OpNum).getReg();
8503   // If MI kills this register, the false dependence is already broken.
8504   if (MI.killsRegister(Reg, TRI))
8505     return;
8506 
8507   if (X86::VR128RegClass.contains(Reg)) {
8508     // These instructions are all floating point domain, so xorps is the best
8509     // choice.
8510     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
8511     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
8512         .addReg(Reg, RegState::Undef)
8513         .addReg(Reg, RegState::Undef);
8514     MI.addRegisterKilled(Reg, TRI, true);
8515   } else if (X86::VR256RegClass.contains(Reg)) {
8516     // Use vxorps to clear the full ymm register.
8517     // It wants to read and write the xmm sub-register.
8518     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
8519     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
8520         .addReg(XReg, RegState::Undef)
8521         .addReg(XReg, RegState::Undef)
8522         .addReg(Reg, RegState::ImplicitDefine);
8523     MI.addRegisterKilled(Reg, TRI, true);
8524   }
8525 }
8526 
8527 MachineInstr *
8528 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
8529                                     ArrayRef<unsigned> Ops,
8530                                     MachineBasicBlock::iterator InsertPt,
8531                                     int FrameIndex, LiveIntervals *LIS) const {
8532   // Check switch flag
8533   if (NoFusing)
8534     return nullptr;
8535 
8536   // Unless optimizing for size, don't fold to avoid partial
8537   // register update stalls
8538   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
8539     return nullptr;
8540 
8541   // Don't fold subreg spills, or reloads that use a high subreg.
8542   for (auto Op : Ops) {
8543     MachineOperand &MO = MI.getOperand(Op);
8544     auto SubReg = MO.getSubReg();
8545     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
8546       return nullptr;
8547   }
8548 
8549   const MachineFrameInfo &MFI = MF.getFrameInfo();
8550   unsigned Size = MFI.getObjectSize(FrameIndex);
8551   unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
8552   // If the function stack isn't realigned we don't want to fold instructions
8553   // that need increased alignment.
8554   if (!RI.needsStackRealignment(MF))
8555     Alignment =
8556         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
8557   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
8558     unsigned NewOpc = 0;
8559     unsigned RCSize = 0;
8560     switch (MI.getOpcode()) {
8561     default: return nullptr;
8562     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
8563     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
8564     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
8565     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
8566     }
8567     // Check if it's safe to fold the load. If the size of the object is
8568     // narrower than the load width, then it's not.
8569     if (Size < RCSize)
8570       return nullptr;
8571     // Change to CMPXXri r, 0 first.
8572     MI.setDesc(get(NewOpc));
8573     MI.getOperand(1).ChangeToImmediate(0);
8574   } else if (Ops.size() != 1)
8575     return nullptr;
8576 
8577   return foldMemoryOperandImpl(MF, MI, Ops[0],
8578                                MachineOperand::CreateFI(FrameIndex), InsertPt,
8579                                Size, Alignment, /*AllowCommute=*/true);
8580 }
8581 
8582 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
8583 /// because the latter uses contents that wouldn't be defined in the folded
8584 /// version.  For instance, this transformation isn't legal:
8585 ///   movss (%rdi), %xmm0
8586 ///   addps %xmm0, %xmm0
8587 /// ->
8588 ///   addps (%rdi), %xmm0
8589 ///
8590 /// But this one is:
8591 ///   movss (%rdi), %xmm0
8592 ///   addss %xmm0, %xmm0
8593 /// ->
8594 ///   addss (%rdi), %xmm0
8595 ///
8596 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
8597                                              const MachineInstr &UserMI,
8598                                              const MachineFunction &MF) {
8599   unsigned Opc = LoadMI.getOpcode();
8600   unsigned UserOpc = UserMI.getOpcode();
8601   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8602   const TargetRegisterClass *RC =
8603       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
8604   unsigned RegSize = TRI.getRegSizeInBits(*RC);
8605 
8606   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
8607       RegSize > 32) {
8608     // These instructions only load 32 bits, we can't fold them if the
8609     // destination register is wider than 32 bits (4 bytes), and its user
8610     // instruction isn't scalar (SS).
8611     switch (UserOpc) {
8612     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
8613     case X86::Int_CMPSSrr: case X86::Int_VCMPSSrr: case X86::VCMPSSZrr_Int:
8614     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
8615     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
8616     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
8617     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
8618     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
8619     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
8620     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
8621     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
8622     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
8623     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
8624     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
8625     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
8626     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
8627     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
8628     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
8629     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
8630     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
8631     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
8632     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
8633     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
8634     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
8635     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
8636     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
8637     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
8638     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
8639     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
8640     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
8641     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
8642     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
8643     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
8644     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
8645     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
8646     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
8647     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
8648     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
8649     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
8650     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
8651       return false;
8652     default:
8653       return true;
8654     }
8655   }
8656 
8657   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
8658       RegSize > 64) {
8659     // These instructions only load 64 bits, we can't fold them if the
8660     // destination register is wider than 64 bits (8 bytes), and its user
8661     // instruction isn't scalar (SD).
8662     switch (UserOpc) {
8663     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
8664     case X86::Int_CMPSDrr: case X86::Int_VCMPSDrr: case X86::VCMPSDZrr_Int:
8665     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
8666     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
8667     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
8668     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
8669     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
8670     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
8671     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
8672     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
8673     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
8674     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
8675     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
8676     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
8677     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
8678     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
8679     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
8680     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
8681     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
8682     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
8683     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
8684     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
8685     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
8686     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
8687     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
8688     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
8689     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
8690     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
8691     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
8692     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
8693     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
8694     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
8695     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
8696     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
8697     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
8698     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
8699     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
8700     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
8701     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
8702       return false;
8703     default:
8704       return true;
8705     }
8706   }
8707 
8708   return false;
8709 }
8710 
8711 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
8712     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
8713     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
8714     LiveIntervals *LIS) const {
8715 
8716   // TODO: Support the case where LoadMI loads a wide register, but MI
8717   // only uses a subreg.
8718   for (auto Op : Ops) {
8719     if (MI.getOperand(Op).getSubReg())
8720       return nullptr;
8721   }
8722 
8723   // If loading from a FrameIndex, fold directly from the FrameIndex.
8724   unsigned NumOps = LoadMI.getDesc().getNumOperands();
8725   int FrameIndex;
8726   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
8727     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
8728       return nullptr;
8729     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
8730   }
8731 
8732   // Check switch flag
8733   if (NoFusing) return nullptr;
8734 
8735   // Avoid partial register update stalls unless optimizing for size.
8736   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
8737     return nullptr;
8738 
8739   // Determine the alignment of the load.
8740   unsigned Alignment = 0;
8741   if (LoadMI.hasOneMemOperand())
8742     Alignment = (*LoadMI.memoperands_begin())->getAlignment();
8743   else
8744     switch (LoadMI.getOpcode()) {
8745     case X86::AVX512_512_SET0:
8746     case X86::AVX512_512_SETALLONES:
8747       Alignment = 64;
8748       break;
8749     case X86::AVX2_SETALLONES:
8750     case X86::AVX1_SETALLONES:
8751     case X86::AVX_SET0:
8752     case X86::AVX512_256_SET0:
8753       Alignment = 32;
8754       break;
8755     case X86::V_SET0:
8756     case X86::V_SETALLONES:
8757     case X86::AVX512_128_SET0:
8758       Alignment = 16;
8759       break;
8760     case X86::FsFLD0SD:
8761     case X86::AVX512_FsFLD0SD:
8762       Alignment = 8;
8763       break;
8764     case X86::FsFLD0SS:
8765     case X86::AVX512_FsFLD0SS:
8766       Alignment = 4;
8767       break;
8768     default:
8769       return nullptr;
8770     }
8771   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
8772     unsigned NewOpc = 0;
8773     switch (MI.getOpcode()) {
8774     default: return nullptr;
8775     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
8776     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
8777     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
8778     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
8779     }
8780     // Change to CMPXXri r, 0 first.
8781     MI.setDesc(get(NewOpc));
8782     MI.getOperand(1).ChangeToImmediate(0);
8783   } else if (Ops.size() != 1)
8784     return nullptr;
8785 
8786   // Make sure the subregisters match.
8787   // Otherwise we risk changing the size of the load.
8788   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
8789     return nullptr;
8790 
8791   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
8792   switch (LoadMI.getOpcode()) {
8793   case X86::V_SET0:
8794   case X86::V_SETALLONES:
8795   case X86::AVX2_SETALLONES:
8796   case X86::AVX1_SETALLONES:
8797   case X86::AVX_SET0:
8798   case X86::AVX512_128_SET0:
8799   case X86::AVX512_256_SET0:
8800   case X86::AVX512_512_SET0:
8801   case X86::AVX512_512_SETALLONES:
8802   case X86::FsFLD0SD:
8803   case X86::AVX512_FsFLD0SD:
8804   case X86::FsFLD0SS:
8805   case X86::AVX512_FsFLD0SS: {
8806     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
8807     // Create a constant-pool entry and operands to load from it.
8808 
8809     // Medium and large mode can't fold loads this way.
8810     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
8811         MF.getTarget().getCodeModel() != CodeModel::Kernel)
8812       return nullptr;
8813 
8814     // x86-32 PIC requires a PIC base register for constant pools.
8815     unsigned PICBase = 0;
8816     if (MF.getTarget().isPositionIndependent()) {
8817       if (Subtarget.is64Bit())
8818         PICBase = X86::RIP;
8819       else
8820         // FIXME: PICBase = getGlobalBaseReg(&MF);
8821         // This doesn't work for several reasons.
8822         // 1. GlobalBaseReg may have been spilled.
8823         // 2. It may not be live at MI.
8824         return nullptr;
8825     }
8826 
8827     // Create a constant-pool entry.
8828     MachineConstantPool &MCP = *MF.getConstantPool();
8829     Type *Ty;
8830     unsigned Opc = LoadMI.getOpcode();
8831     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
8832       Ty = Type::getFloatTy(MF.getFunction()->getContext());
8833     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
8834       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
8835     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
8836       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
8837     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
8838              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
8839       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
8840     else
8841       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
8842 
8843     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
8844                       Opc == X86::AVX512_512_SETALLONES ||
8845                       Opc == X86::AVX1_SETALLONES);
8846     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
8847                                     Constant::getNullValue(Ty);
8848     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
8849 
8850     // Create operands to load from the constant pool entry.
8851     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
8852     MOs.push_back(MachineOperand::CreateImm(1));
8853     MOs.push_back(MachineOperand::CreateReg(0, false));
8854     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
8855     MOs.push_back(MachineOperand::CreateReg(0, false));
8856     break;
8857   }
8858   default: {
8859     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
8860       return nullptr;
8861 
8862     // Folding a normal load. Just copy the load's address operands.
8863     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
8864                LoadMI.operands_begin() + NumOps);
8865     break;
8866   }
8867   }
8868   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
8869                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
8870 }
8871 
8872 bool X86InstrInfo::unfoldMemoryOperand(
8873     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
8874     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
8875   auto I = MemOp2RegOpTable.find(MI.getOpcode());
8876   if (I == MemOp2RegOpTable.end())
8877     return false;
8878   unsigned Opc = I->second.first;
8879   unsigned Index = I->second.second & TB_INDEX_MASK;
8880   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
8881   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
8882   if (UnfoldLoad && !FoldedLoad)
8883     return false;
8884   UnfoldLoad &= FoldedLoad;
8885   if (UnfoldStore && !FoldedStore)
8886     return false;
8887   UnfoldStore &= FoldedStore;
8888 
8889   const MCInstrDesc &MCID = get(Opc);
8890   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
8891   // TODO: Check if 32-byte or greater accesses are slow too?
8892   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
8893       Subtarget.isUnalignedMem16Slow())
8894     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
8895     // conservatively assume the address is unaligned. That's bad for
8896     // performance.
8897     return false;
8898   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
8899   SmallVector<MachineOperand,2> BeforeOps;
8900   SmallVector<MachineOperand,2> AfterOps;
8901   SmallVector<MachineOperand,4> ImpOps;
8902   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
8903     MachineOperand &Op = MI.getOperand(i);
8904     if (i >= Index && i < Index + X86::AddrNumOperands)
8905       AddrOps.push_back(Op);
8906     else if (Op.isReg() && Op.isImplicit())
8907       ImpOps.push_back(Op);
8908     else if (i < Index)
8909       BeforeOps.push_back(Op);
8910     else if (i > Index)
8911       AfterOps.push_back(Op);
8912   }
8913 
8914   // Emit the load instruction.
8915   if (UnfoldLoad) {
8916     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
8917         MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
8918     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
8919     if (UnfoldStore) {
8920       // Address operands cannot be marked isKill.
8921       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
8922         MachineOperand &MO = NewMIs[0]->getOperand(i);
8923         if (MO.isReg())
8924           MO.setIsKill(false);
8925       }
8926     }
8927   }
8928 
8929   // Emit the data processing instruction.
8930   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
8931   MachineInstrBuilder MIB(MF, DataMI);
8932 
8933   if (FoldedStore)
8934     MIB.addReg(Reg, RegState::Define);
8935   for (MachineOperand &BeforeOp : BeforeOps)
8936     MIB.add(BeforeOp);
8937   if (FoldedLoad)
8938     MIB.addReg(Reg);
8939   for (MachineOperand &AfterOp : AfterOps)
8940     MIB.add(AfterOp);
8941   for (MachineOperand &ImpOp : ImpOps) {
8942     MIB.addReg(ImpOp.getReg(),
8943                getDefRegState(ImpOp.isDef()) |
8944                RegState::Implicit |
8945                getKillRegState(ImpOp.isKill()) |
8946                getDeadRegState(ImpOp.isDead()) |
8947                getUndefRegState(ImpOp.isUndef()));
8948   }
8949   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
8950   switch (DataMI->getOpcode()) {
8951   default: break;
8952   case X86::CMP64ri32:
8953   case X86::CMP64ri8:
8954   case X86::CMP32ri:
8955   case X86::CMP32ri8:
8956   case X86::CMP16ri:
8957   case X86::CMP16ri8:
8958   case X86::CMP8ri: {
8959     MachineOperand &MO0 = DataMI->getOperand(0);
8960     MachineOperand &MO1 = DataMI->getOperand(1);
8961     if (MO1.getImm() == 0) {
8962       unsigned NewOpc;
8963       switch (DataMI->getOpcode()) {
8964       default: llvm_unreachable("Unreachable!");
8965       case X86::CMP64ri8:
8966       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
8967       case X86::CMP32ri8:
8968       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
8969       case X86::CMP16ri8:
8970       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
8971       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
8972       }
8973       DataMI->setDesc(get(NewOpc));
8974       MO1.ChangeToRegister(MO0.getReg(), false);
8975     }
8976   }
8977   }
8978   NewMIs.push_back(DataMI);
8979 
8980   // Emit the store instruction.
8981   if (UnfoldStore) {
8982     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
8983     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
8984         MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
8985     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
8986   }
8987 
8988   return true;
8989 }
8990 
8991 bool
8992 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
8993                                   SmallVectorImpl<SDNode*> &NewNodes) const {
8994   if (!N->isMachineOpcode())
8995     return false;
8996 
8997   auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
8998   if (I == MemOp2RegOpTable.end())
8999     return false;
9000   unsigned Opc = I->second.first;
9001   unsigned Index = I->second.second & TB_INDEX_MASK;
9002   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
9003   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
9004   const MCInstrDesc &MCID = get(Opc);
9005   MachineFunction &MF = DAG.getMachineFunction();
9006   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
9007   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
9008   unsigned NumDefs = MCID.NumDefs;
9009   std::vector<SDValue> AddrOps;
9010   std::vector<SDValue> BeforeOps;
9011   std::vector<SDValue> AfterOps;
9012   SDLoc dl(N);
9013   unsigned NumOps = N->getNumOperands();
9014   for (unsigned i = 0; i != NumOps-1; ++i) {
9015     SDValue Op = N->getOperand(i);
9016     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
9017       AddrOps.push_back(Op);
9018     else if (i < Index-NumDefs)
9019       BeforeOps.push_back(Op);
9020     else if (i > Index-NumDefs)
9021       AfterOps.push_back(Op);
9022   }
9023   SDValue Chain = N->getOperand(NumOps-1);
9024   AddrOps.push_back(Chain);
9025 
9026   // Emit the load instruction.
9027   SDNode *Load = nullptr;
9028   if (FoldedLoad) {
9029     EVT VT = *TRI.legalclasstypes_begin(*RC);
9030     std::pair<MachineInstr::mmo_iterator,
9031               MachineInstr::mmo_iterator> MMOs =
9032       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
9033                             cast<MachineSDNode>(N)->memoperands_end());
9034     if (!(*MMOs.first) &&
9035         RC == &X86::VR128RegClass &&
9036         Subtarget.isUnalignedMem16Slow())
9037       // Do not introduce a slow unaligned load.
9038       return false;
9039     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
9040     // memory access is slow above.
9041     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
9042     bool isAligned = (*MMOs.first) &&
9043                      (*MMOs.first)->getAlignment() >= Alignment;
9044     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
9045                               VT, MVT::Other, AddrOps);
9046     NewNodes.push_back(Load);
9047 
9048     // Preserve memory reference information.
9049     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
9050   }
9051 
9052   // Emit the data processing instruction.
9053   std::vector<EVT> VTs;
9054   const TargetRegisterClass *DstRC = nullptr;
9055   if (MCID.getNumDefs() > 0) {
9056     DstRC = getRegClass(MCID, 0, &RI, MF);
9057     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
9058   }
9059   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
9060     EVT VT = N->getValueType(i);
9061     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
9062       VTs.push_back(VT);
9063   }
9064   if (Load)
9065     BeforeOps.push_back(SDValue(Load, 0));
9066   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
9067   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
9068   NewNodes.push_back(NewNode);
9069 
9070   // Emit the store instruction.
9071   if (FoldedStore) {
9072     AddrOps.pop_back();
9073     AddrOps.push_back(SDValue(NewNode, 0));
9074     AddrOps.push_back(Chain);
9075     std::pair<MachineInstr::mmo_iterator,
9076               MachineInstr::mmo_iterator> MMOs =
9077       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
9078                              cast<MachineSDNode>(N)->memoperands_end());
9079     if (!(*MMOs.first) &&
9080         RC == &X86::VR128RegClass &&
9081         Subtarget.isUnalignedMem16Slow())
9082       // Do not introduce a slow unaligned store.
9083       return false;
9084     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
9085     // memory access is slow above.
9086     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
9087     bool isAligned = (*MMOs.first) &&
9088                      (*MMOs.first)->getAlignment() >= Alignment;
9089     SDNode *Store =
9090         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
9091                            dl, MVT::Other, AddrOps);
9092     NewNodes.push_back(Store);
9093 
9094     // Preserve memory reference information.
9095     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
9096   }
9097 
9098   return true;
9099 }
9100 
9101 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
9102                                       bool UnfoldLoad, bool UnfoldStore,
9103                                       unsigned *LoadRegIndex) const {
9104   auto I = MemOp2RegOpTable.find(Opc);
9105   if (I == MemOp2RegOpTable.end())
9106     return 0;
9107   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
9108   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
9109   if (UnfoldLoad && !FoldedLoad)
9110     return 0;
9111   if (UnfoldStore && !FoldedStore)
9112     return 0;
9113   if (LoadRegIndex)
9114     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
9115   return I->second.first;
9116 }
9117 
9118 bool
9119 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
9120                                      int64_t &Offset1, int64_t &Offset2) const {
9121   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
9122     return false;
9123   unsigned Opc1 = Load1->getMachineOpcode();
9124   unsigned Opc2 = Load2->getMachineOpcode();
9125   switch (Opc1) {
9126   default: return false;
9127   case X86::MOV8rm:
9128   case X86::MOV16rm:
9129   case X86::MOV32rm:
9130   case X86::MOV64rm:
9131   case X86::LD_Fp32m:
9132   case X86::LD_Fp64m:
9133   case X86::LD_Fp80m:
9134   case X86::MOVSSrm:
9135   case X86::MOVSDrm:
9136   case X86::MMX_MOVD64rm:
9137   case X86::MMX_MOVQ64rm:
9138   case X86::MOVAPSrm:
9139   case X86::MOVUPSrm:
9140   case X86::MOVAPDrm:
9141   case X86::MOVUPDrm:
9142   case X86::MOVDQArm:
9143   case X86::MOVDQUrm:
9144   // AVX load instructions
9145   case X86::VMOVSSrm:
9146   case X86::VMOVSDrm:
9147   case X86::VMOVAPSrm:
9148   case X86::VMOVUPSrm:
9149   case X86::VMOVAPDrm:
9150   case X86::VMOVUPDrm:
9151   case X86::VMOVDQArm:
9152   case X86::VMOVDQUrm:
9153   case X86::VMOVAPSYrm:
9154   case X86::VMOVUPSYrm:
9155   case X86::VMOVAPDYrm:
9156   case X86::VMOVUPDYrm:
9157   case X86::VMOVDQAYrm:
9158   case X86::VMOVDQUYrm:
9159   // AVX512 load instructions
9160   case X86::VMOVSSZrm:
9161   case X86::VMOVSDZrm:
9162   case X86::VMOVAPSZ128rm:
9163   case X86::VMOVUPSZ128rm:
9164   case X86::VMOVAPSZ128rm_NOVLX:
9165   case X86::VMOVUPSZ128rm_NOVLX:
9166   case X86::VMOVAPDZ128rm:
9167   case X86::VMOVUPDZ128rm:
9168   case X86::VMOVDQU8Z128rm:
9169   case X86::VMOVDQU16Z128rm:
9170   case X86::VMOVDQA32Z128rm:
9171   case X86::VMOVDQU32Z128rm:
9172   case X86::VMOVDQA64Z128rm:
9173   case X86::VMOVDQU64Z128rm:
9174   case X86::VMOVAPSZ256rm:
9175   case X86::VMOVUPSZ256rm:
9176   case X86::VMOVAPSZ256rm_NOVLX:
9177   case X86::VMOVUPSZ256rm_NOVLX:
9178   case X86::VMOVAPDZ256rm:
9179   case X86::VMOVUPDZ256rm:
9180   case X86::VMOVDQU8Z256rm:
9181   case X86::VMOVDQU16Z256rm:
9182   case X86::VMOVDQA32Z256rm:
9183   case X86::VMOVDQU32Z256rm:
9184   case X86::VMOVDQA64Z256rm:
9185   case X86::VMOVDQU64Z256rm:
9186   case X86::VMOVAPSZrm:
9187   case X86::VMOVUPSZrm:
9188   case X86::VMOVAPDZrm:
9189   case X86::VMOVUPDZrm:
9190   case X86::VMOVDQU8Zrm:
9191   case X86::VMOVDQU16Zrm:
9192   case X86::VMOVDQA32Zrm:
9193   case X86::VMOVDQU32Zrm:
9194   case X86::VMOVDQA64Zrm:
9195   case X86::VMOVDQU64Zrm:
9196   case X86::KMOVBkm:
9197   case X86::KMOVWkm:
9198   case X86::KMOVDkm:
9199   case X86::KMOVQkm:
9200     break;
9201   }
9202   switch (Opc2) {
9203   default: return false;
9204   case X86::MOV8rm:
9205   case X86::MOV16rm:
9206   case X86::MOV32rm:
9207   case X86::MOV64rm:
9208   case X86::LD_Fp32m:
9209   case X86::LD_Fp64m:
9210   case X86::LD_Fp80m:
9211   case X86::MOVSSrm:
9212   case X86::MOVSDrm:
9213   case X86::MMX_MOVD64rm:
9214   case X86::MMX_MOVQ64rm:
9215   case X86::MOVAPSrm:
9216   case X86::MOVUPSrm:
9217   case X86::MOVAPDrm:
9218   case X86::MOVUPDrm:
9219   case X86::MOVDQArm:
9220   case X86::MOVDQUrm:
9221   // AVX load instructions
9222   case X86::VMOVSSrm:
9223   case X86::VMOVSDrm:
9224   case X86::VMOVAPSrm:
9225   case X86::VMOVUPSrm:
9226   case X86::VMOVAPDrm:
9227   case X86::VMOVUPDrm:
9228   case X86::VMOVDQArm:
9229   case X86::VMOVDQUrm:
9230   case X86::VMOVAPSYrm:
9231   case X86::VMOVUPSYrm:
9232   case X86::VMOVAPDYrm:
9233   case X86::VMOVUPDYrm:
9234   case X86::VMOVDQAYrm:
9235   case X86::VMOVDQUYrm:
9236   // AVX512 load instructions
9237   case X86::VMOVSSZrm:
9238   case X86::VMOVSDZrm:
9239   case X86::VMOVAPSZ128rm:
9240   case X86::VMOVUPSZ128rm:
9241   case X86::VMOVAPSZ128rm_NOVLX:
9242   case X86::VMOVUPSZ128rm_NOVLX:
9243   case X86::VMOVAPDZ128rm:
9244   case X86::VMOVUPDZ128rm:
9245   case X86::VMOVDQU8Z128rm:
9246   case X86::VMOVDQU16Z128rm:
9247   case X86::VMOVDQA32Z128rm:
9248   case X86::VMOVDQU32Z128rm:
9249   case X86::VMOVDQA64Z128rm:
9250   case X86::VMOVDQU64Z128rm:
9251   case X86::VMOVAPSZ256rm:
9252   case X86::VMOVUPSZ256rm:
9253   case X86::VMOVAPSZ256rm_NOVLX:
9254   case X86::VMOVUPSZ256rm_NOVLX:
9255   case X86::VMOVAPDZ256rm:
9256   case X86::VMOVUPDZ256rm:
9257   case X86::VMOVDQU8Z256rm:
9258   case X86::VMOVDQU16Z256rm:
9259   case X86::VMOVDQA32Z256rm:
9260   case X86::VMOVDQU32Z256rm:
9261   case X86::VMOVDQA64Z256rm:
9262   case X86::VMOVDQU64Z256rm:
9263   case X86::VMOVAPSZrm:
9264   case X86::VMOVUPSZrm:
9265   case X86::VMOVAPDZrm:
9266   case X86::VMOVUPDZrm:
9267   case X86::VMOVDQU8Zrm:
9268   case X86::VMOVDQU16Zrm:
9269   case X86::VMOVDQA32Zrm:
9270   case X86::VMOVDQU32Zrm:
9271   case X86::VMOVDQA64Zrm:
9272   case X86::VMOVDQU64Zrm:
9273   case X86::KMOVBkm:
9274   case X86::KMOVWkm:
9275   case X86::KMOVDkm:
9276   case X86::KMOVQkm:
9277     break;
9278   }
9279 
9280   // Lambda to check if both the loads have the same value for an operand index.
9281   auto HasSameOp = [&](int I) {
9282     return Load1->getOperand(I) == Load2->getOperand(I);
9283   };
9284 
9285   // All operands except the displacement should match.
9286   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
9287       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
9288     return false;
9289 
9290   // Chain Operand must be the same.
9291   if (!HasSameOp(5))
9292     return false;
9293 
9294   // Now let's examine if the displacements are constants.
9295   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
9296   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
9297   if (!Disp1 || !Disp2)
9298     return false;
9299 
9300   Offset1 = Disp1->getSExtValue();
9301   Offset2 = Disp2->getSExtValue();
9302   return true;
9303 }
9304 
9305 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
9306                                            int64_t Offset1, int64_t Offset2,
9307                                            unsigned NumLoads) const {
9308   assert(Offset2 > Offset1);
9309   if ((Offset2 - Offset1) / 8 > 64)
9310     return false;
9311 
9312   unsigned Opc1 = Load1->getMachineOpcode();
9313   unsigned Opc2 = Load2->getMachineOpcode();
9314   if (Opc1 != Opc2)
9315     return false;  // FIXME: overly conservative?
9316 
9317   switch (Opc1) {
9318   default: break;
9319   case X86::LD_Fp32m:
9320   case X86::LD_Fp64m:
9321   case X86::LD_Fp80m:
9322   case X86::MMX_MOVD64rm:
9323   case X86::MMX_MOVQ64rm:
9324     return false;
9325   }
9326 
9327   EVT VT = Load1->getValueType(0);
9328   switch (VT.getSimpleVT().SimpleTy) {
9329   default:
9330     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
9331     // have 16 of them to play with.
9332     if (Subtarget.is64Bit()) {
9333       if (NumLoads >= 3)
9334         return false;
9335     } else if (NumLoads) {
9336       return false;
9337     }
9338     break;
9339   case MVT::i8:
9340   case MVT::i16:
9341   case MVT::i32:
9342   case MVT::i64:
9343   case MVT::f32:
9344   case MVT::f64:
9345     if (NumLoads)
9346       return false;
9347     break;
9348   }
9349 
9350   return true;
9351 }
9352 
9353 bool X86InstrInfo::
9354 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
9355   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
9356   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
9357   Cond[0].setImm(GetOppositeBranchCondition(CC));
9358   return false;
9359 }
9360 
9361 bool X86InstrInfo::
9362 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
9363   // FIXME: Return false for x87 stack register classes for now. We can't
9364   // allow any loads of these registers before FpGet_ST0_80.
9365   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
9366            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
9367 }
9368 
9369 /// Return a virtual register initialized with the
9370 /// the global base register value. Output instructions required to
9371 /// initialize the register in the function entry block, if necessary.
9372 ///
9373 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
9374 ///
9375 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
9376   assert(!Subtarget.is64Bit() &&
9377          "X86-64 PIC uses RIP relative addressing");
9378 
9379   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
9380   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
9381   if (GlobalBaseReg != 0)
9382     return GlobalBaseReg;
9383 
9384   // Create the register. The code to initialize it is inserted
9385   // later, by the CGBR pass (below).
9386   MachineRegisterInfo &RegInfo = MF->getRegInfo();
9387   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
9388   X86FI->setGlobalBaseReg(GlobalBaseReg);
9389   return GlobalBaseReg;
9390 }
9391 
9392 // These are the replaceable SSE instructions. Some of these have Int variants
9393 // that we don't include here. We don't want to replace instructions selected
9394 // by intrinsics.
9395 static const uint16_t ReplaceableInstrs[][3] = {
9396   //PackedSingle     PackedDouble    PackedInt
9397   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
9398   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
9399   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
9400   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
9401   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
9402   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
9403   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
9404   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
9405   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
9406   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
9407   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
9408   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
9409   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
9410   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
9411   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
9412   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
9413   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
9414   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
9415   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
9416   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
9417   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
9418   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
9419   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
9420   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
9421   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
9422   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
9423   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
9424   // AVX 128-bit support
9425   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
9426   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
9427   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
9428   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
9429   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
9430   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
9431   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
9432   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
9433   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
9434   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
9435   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
9436   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
9437   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
9438   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
9439   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
9440   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
9441   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
9442   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
9443   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
9444   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
9445   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
9446   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
9447   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
9448   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
9449   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
9450   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
9451   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
9452   // AVX 256-bit support
9453   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
9454   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
9455   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
9456   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
9457   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
9458   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
9459   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
9460   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
9461   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
9462   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
9463   // AVX512 support
9464   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
9465   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
9466   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
9467   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
9468   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
9469   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
9470   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
9471   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
9472   { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
9473   { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
9474   { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
9475   { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
9476   { X86::VBROADCASTSSZr,    X86::VBROADCASTSSZr,    X86::VPBROADCASTDZr },
9477   { X86::VBROADCASTSSZm,    X86::VBROADCASTSSZm,    X86::VPBROADCASTDZm },
9478   { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
9479   { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
9480   { X86::VBROADCASTSDZr,    X86::VBROADCASTSDZr,    X86::VPBROADCASTQZr },
9481   { X86::VBROADCASTSDZm,    X86::VBROADCASTSDZm,    X86::VPBROADCASTQZm },
9482   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
9483   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
9484   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
9485   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
9486   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
9487   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
9488   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
9489   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
9490   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
9491   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
9492   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
9493   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
9494   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
9495   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
9496   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
9497   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
9498   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
9499   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
9500   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
9501   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
9502   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
9503   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
9504   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
9505   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
9506   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
9507   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
9508   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
9509   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
9510   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
9511   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
9512   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
9513   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
9514   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
9515   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
9516   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
9517   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
9518   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
9519   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
9520   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
9521   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
9522   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
9523   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
9524   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
9525   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
9526   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
9527   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
9528   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
9529   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
9530   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
9531   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
9532   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
9533   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
9534   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
9535   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
9536   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
9537   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
9538   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
9539   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
9540   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
9541   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
9542   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
9543   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
9544   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
9545   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
9546   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
9547   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
9548   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
9549   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
9550 };
9551 
9552 static const uint16_t ReplaceableInstrsAVX2[][3] = {
9553   //PackedSingle       PackedDouble       PackedInt
9554   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
9555   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
9556   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
9557   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
9558   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
9559   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
9560   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
9561   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
9562   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
9563   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
9564   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
9565   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
9566   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
9567   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
9568   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
9569   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
9570   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
9571   { X86::VBLENDPSrri,     X86::VBLENDPSrri,     X86::VPBLENDDrri },
9572   { X86::VBLENDPSrmi,     X86::VBLENDPSrmi,     X86::VPBLENDDrmi },
9573   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
9574   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
9575   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
9576   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
9577   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
9578   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
9579   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
9580   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
9581   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
9582   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
9583   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
9584   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
9585 };
9586 
9587 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
9588   //PackedSingle       PackedDouble       PackedInt
9589   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
9590   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
9591   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
9592   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
9593 };
9594 
9595 static const uint16_t ReplaceableInstrsAVX512[][4] = {
9596   // Two integer columns for 64-bit and 32-bit elements.
9597   //PackedSingle        PackedDouble        PackedInt             PackedInt
9598   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
9599   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
9600   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
9601   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
9602   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
9603   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
9604   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
9605   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
9606   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
9607   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
9608   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
9609   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
9610   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
9611   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
9612   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
9613 };
9614 
9615 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
9616   // Two integer columns for 64-bit and 32-bit elements.
9617   //PackedSingle        PackedDouble        PackedInt           PackedInt
9618   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
9619   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
9620   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
9621   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
9622   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
9623   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
9624   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
9625   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
9626   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
9627   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
9628   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
9629   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
9630   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
9631   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
9632   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
9633   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
9634   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
9635   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
9636   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
9637   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
9638   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
9639   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
9640   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
9641   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
9642 };
9643 
9644 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
9645   // Two integer columns for 64-bit and 32-bit elements.
9646   //PackedSingle          PackedDouble
9647   //PackedInt             PackedInt
9648   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
9649     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
9650   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
9651     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
9652   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
9653     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
9654   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
9655     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
9656   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
9657     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
9658   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
9659     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
9660   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
9661     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
9662   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
9663     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
9664   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
9665     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
9666   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
9667     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
9668   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
9669     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
9670   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
9671     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
9672   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
9673     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
9674   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
9675     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
9676   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
9677     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
9678   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
9679     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
9680   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
9681     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
9682   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
9683     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
9684   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
9685     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
9686   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
9687     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
9688   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
9689     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
9690   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
9691     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
9692   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
9693     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
9694   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
9695     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
9696   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
9697     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
9698   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
9699     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
9700   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
9701     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
9702   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
9703     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
9704   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
9705     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
9706   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
9707     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
9708   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
9709     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
9710   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
9711     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
9712   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
9713     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
9714   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
9715     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
9716   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
9717     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
9718   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
9719     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
9720   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
9721     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
9722   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
9723     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
9724   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
9725     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
9726   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
9727     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
9728   { X86::VORPSZrmk,       X86::VORPDZrmk,
9729     X86::VPORQZrmk,       X86::VPORDZrmk       },
9730   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
9731     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
9732   { X86::VORPSZrrk,       X86::VORPDZrrk,
9733     X86::VPORQZrrk,       X86::VPORDZrrk       },
9734   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
9735     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
9736   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
9737     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
9738   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
9739     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
9740   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
9741     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
9742   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
9743     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
9744   // Broadcast loads can be handled the same as masked operations to avoid
9745   // changing element size.
9746   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
9747     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
9748   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
9749     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
9750   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
9751     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
9752   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
9753     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
9754   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
9755     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
9756   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
9757     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
9758   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
9759     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
9760   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
9761     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
9762   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
9763     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
9764   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
9765     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
9766   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
9767     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
9768   { X86::VORPSZrmb,       X86::VORPDZrmb,
9769     X86::VPORQZrmb,       X86::VPORDZrmb       },
9770   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
9771     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
9772   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
9773     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
9774   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
9775     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
9776   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
9777     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
9778   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
9779     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
9780   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
9781     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
9782   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
9783     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
9784   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
9785     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
9786   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
9787     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
9788   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
9789     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
9790   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
9791     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
9792   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
9793     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
9794   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
9795     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
9796   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
9797     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
9798   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
9799     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
9800   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
9801     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
9802   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
9803     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
9804   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
9805     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
9806   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
9807     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
9808   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
9809     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
9810   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
9811     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
9812   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
9813     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
9814   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
9815     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
9816   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
9817     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
9818   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
9819     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
9820   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
9821     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
9822   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
9823     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
9824 };
9825 
9826 // FIXME: Some shuffle and unpack instructions have equivalents in different
9827 // domains, but they require a bit more work than just switching opcodes.
9828 
9829 static const uint16_t *lookup(unsigned opcode, unsigned domain,
9830                               ArrayRef<uint16_t[3]> Table) {
9831   for (const uint16_t (&Row)[3] : Table)
9832     if (Row[domain-1] == opcode)
9833       return Row;
9834   return nullptr;
9835 }
9836 
9837 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
9838                                     ArrayRef<uint16_t[4]> Table) {
9839   // If this is the integer domain make sure to check both integer columns.
9840   for (const uint16_t (&Row)[4] : Table)
9841     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
9842       return Row;
9843   return nullptr;
9844 }
9845 
9846 std::pair<uint16_t, uint16_t>
9847 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
9848   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9849   unsigned opcode = MI.getOpcode();
9850   uint16_t validDomains = 0;
9851   if (domain) {
9852     if (lookup(MI.getOpcode(), domain, ReplaceableInstrs)) {
9853       validDomains = 0xe;
9854     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
9855       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
9856     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
9857       // Insert/extract instructions should only effect domain if AVX2
9858       // is enabled.
9859       if (!Subtarget.hasAVX2())
9860         return std::make_pair(0, 0);
9861       validDomains = 0xe;
9862     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
9863       validDomains = 0xe;
9864     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
9865                                                   ReplaceableInstrsAVX512DQ)) {
9866       validDomains = 0xe;
9867     } else if (Subtarget.hasDQI()) {
9868       if (const uint16_t *table = lookupAVX512(opcode, domain,
9869                                              ReplaceableInstrsAVX512DQMasked)) {
9870         if (domain == 1 || (domain == 3 && table[3] == opcode))
9871           validDomains = 0xa;
9872         else
9873           validDomains = 0xc;
9874       }
9875     }
9876   }
9877   return std::make_pair(domain, validDomains);
9878 }
9879 
9880 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
9881   assert(Domain>0 && Domain<4 && "Invalid execution domain");
9882   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9883   assert(dom && "Not an SSE instruction");
9884   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
9885   if (!table) { // try the other table
9886     assert((Subtarget.hasAVX2() || Domain < 3) &&
9887            "256-bit vector operations only available in AVX2");
9888     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
9889   }
9890   if (!table) { // try the other table
9891     assert(Subtarget.hasAVX2() &&
9892            "256-bit insert/extract only available in AVX2");
9893     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
9894   }
9895   if (!table) { // try the AVX512 table
9896     assert(Subtarget.hasAVX512() && "Requires AVX-512");
9897     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
9898     // Don't change integer Q instructions to D instructions.
9899     if (table && Domain == 3 && table[3] == MI.getOpcode())
9900       Domain = 4;
9901   }
9902   if (!table) { // try the AVX512DQ table
9903     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
9904     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
9905     // Don't change integer Q instructions to D instructions and
9906     // use D intructions if we started with a PS instruction.
9907     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9908       Domain = 4;
9909   }
9910   if (!table) { // try the AVX512DQMasked table
9911     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
9912     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
9913     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9914       Domain = 4;
9915   }
9916   assert(table && "Cannot change domain");
9917   MI.setDesc(get(table[Domain - 1]));
9918 }
9919 
9920 /// Return the noop instruction to use for a noop.
9921 void X86InstrInfo::getNoop(MCInst &NopInst) const {
9922   NopInst.setOpcode(X86::NOOP);
9923 }
9924 
9925 bool X86InstrInfo::isHighLatencyDef(int opc) const {
9926   switch (opc) {
9927   default: return false;
9928   case X86::DIVPDrm:
9929   case X86::DIVPDrr:
9930   case X86::DIVPSrm:
9931   case X86::DIVPSrr:
9932   case X86::DIVSDrm:
9933   case X86::DIVSDrm_Int:
9934   case X86::DIVSDrr:
9935   case X86::DIVSDrr_Int:
9936   case X86::DIVSSrm:
9937   case X86::DIVSSrm_Int:
9938   case X86::DIVSSrr:
9939   case X86::DIVSSrr_Int:
9940   case X86::SQRTPDm:
9941   case X86::SQRTPDr:
9942   case X86::SQRTPSm:
9943   case X86::SQRTPSr:
9944   case X86::SQRTSDm:
9945   case X86::SQRTSDm_Int:
9946   case X86::SQRTSDr:
9947   case X86::SQRTSDr_Int:
9948   case X86::SQRTSSm:
9949   case X86::SQRTSSm_Int:
9950   case X86::SQRTSSr:
9951   case X86::SQRTSSr_Int:
9952   // AVX instructions with high latency
9953   case X86::VDIVPDrm:
9954   case X86::VDIVPDrr:
9955   case X86::VDIVPDYrm:
9956   case X86::VDIVPDYrr:
9957   case X86::VDIVPSrm:
9958   case X86::VDIVPSrr:
9959   case X86::VDIVPSYrm:
9960   case X86::VDIVPSYrr:
9961   case X86::VDIVSDrm:
9962   case X86::VDIVSDrm_Int:
9963   case X86::VDIVSDrr:
9964   case X86::VDIVSDrr_Int:
9965   case X86::VDIVSSrm:
9966   case X86::VDIVSSrm_Int:
9967   case X86::VDIVSSrr:
9968   case X86::VDIVSSrr_Int:
9969   case X86::VSQRTPDm:
9970   case X86::VSQRTPDr:
9971   case X86::VSQRTPDYm:
9972   case X86::VSQRTPDYr:
9973   case X86::VSQRTPSm:
9974   case X86::VSQRTPSr:
9975   case X86::VSQRTPSYm:
9976   case X86::VSQRTPSYr:
9977   case X86::VSQRTSDm:
9978   case X86::VSQRTSDm_Int:
9979   case X86::VSQRTSDr:
9980   case X86::VSQRTSDr_Int:
9981   case X86::VSQRTSSm:
9982   case X86::VSQRTSSm_Int:
9983   case X86::VSQRTSSr:
9984   case X86::VSQRTSSr_Int:
9985   // AVX512 instructions with high latency
9986   case X86::VDIVPDZ128rm:
9987   case X86::VDIVPDZ128rmb:
9988   case X86::VDIVPDZ128rmbk:
9989   case X86::VDIVPDZ128rmbkz:
9990   case X86::VDIVPDZ128rmk:
9991   case X86::VDIVPDZ128rmkz:
9992   case X86::VDIVPDZ128rr:
9993   case X86::VDIVPDZ128rrk:
9994   case X86::VDIVPDZ128rrkz:
9995   case X86::VDIVPDZ256rm:
9996   case X86::VDIVPDZ256rmb:
9997   case X86::VDIVPDZ256rmbk:
9998   case X86::VDIVPDZ256rmbkz:
9999   case X86::VDIVPDZ256rmk:
10000   case X86::VDIVPDZ256rmkz:
10001   case X86::VDIVPDZ256rr:
10002   case X86::VDIVPDZ256rrk:
10003   case X86::VDIVPDZ256rrkz:
10004   case X86::VDIVPDZrb:
10005   case X86::VDIVPDZrbk:
10006   case X86::VDIVPDZrbkz:
10007   case X86::VDIVPDZrm:
10008   case X86::VDIVPDZrmb:
10009   case X86::VDIVPDZrmbk:
10010   case X86::VDIVPDZrmbkz:
10011   case X86::VDIVPDZrmk:
10012   case X86::VDIVPDZrmkz:
10013   case X86::VDIVPDZrr:
10014   case X86::VDIVPDZrrk:
10015   case X86::VDIVPDZrrkz:
10016   case X86::VDIVPSZ128rm:
10017   case X86::VDIVPSZ128rmb:
10018   case X86::VDIVPSZ128rmbk:
10019   case X86::VDIVPSZ128rmbkz:
10020   case X86::VDIVPSZ128rmk:
10021   case X86::VDIVPSZ128rmkz:
10022   case X86::VDIVPSZ128rr:
10023   case X86::VDIVPSZ128rrk:
10024   case X86::VDIVPSZ128rrkz:
10025   case X86::VDIVPSZ256rm:
10026   case X86::VDIVPSZ256rmb:
10027   case X86::VDIVPSZ256rmbk:
10028   case X86::VDIVPSZ256rmbkz:
10029   case X86::VDIVPSZ256rmk:
10030   case X86::VDIVPSZ256rmkz:
10031   case X86::VDIVPSZ256rr:
10032   case X86::VDIVPSZ256rrk:
10033   case X86::VDIVPSZ256rrkz:
10034   case X86::VDIVPSZrb:
10035   case X86::VDIVPSZrbk:
10036   case X86::VDIVPSZrbkz:
10037   case X86::VDIVPSZrm:
10038   case X86::VDIVPSZrmb:
10039   case X86::VDIVPSZrmbk:
10040   case X86::VDIVPSZrmbkz:
10041   case X86::VDIVPSZrmk:
10042   case X86::VDIVPSZrmkz:
10043   case X86::VDIVPSZrr:
10044   case X86::VDIVPSZrrk:
10045   case X86::VDIVPSZrrkz:
10046   case X86::VDIVSDZrm:
10047   case X86::VDIVSDZrr:
10048   case X86::VDIVSDZrm_Int:
10049   case X86::VDIVSDZrm_Intk:
10050   case X86::VDIVSDZrm_Intkz:
10051   case X86::VDIVSDZrr_Int:
10052   case X86::VDIVSDZrr_Intk:
10053   case X86::VDIVSDZrr_Intkz:
10054   case X86::VDIVSDZrrb:
10055   case X86::VDIVSDZrrbk:
10056   case X86::VDIVSDZrrbkz:
10057   case X86::VDIVSSZrm:
10058   case X86::VDIVSSZrr:
10059   case X86::VDIVSSZrm_Int:
10060   case X86::VDIVSSZrm_Intk:
10061   case X86::VDIVSSZrm_Intkz:
10062   case X86::VDIVSSZrr_Int:
10063   case X86::VDIVSSZrr_Intk:
10064   case X86::VDIVSSZrr_Intkz:
10065   case X86::VDIVSSZrrb:
10066   case X86::VDIVSSZrrbk:
10067   case X86::VDIVSSZrrbkz:
10068   case X86::VSQRTPDZ128m:
10069   case X86::VSQRTPDZ128mb:
10070   case X86::VSQRTPDZ128mbk:
10071   case X86::VSQRTPDZ128mbkz:
10072   case X86::VSQRTPDZ128mk:
10073   case X86::VSQRTPDZ128mkz:
10074   case X86::VSQRTPDZ128r:
10075   case X86::VSQRTPDZ128rk:
10076   case X86::VSQRTPDZ128rkz:
10077   case X86::VSQRTPDZ256m:
10078   case X86::VSQRTPDZ256mb:
10079   case X86::VSQRTPDZ256mbk:
10080   case X86::VSQRTPDZ256mbkz:
10081   case X86::VSQRTPDZ256mk:
10082   case X86::VSQRTPDZ256mkz:
10083   case X86::VSQRTPDZ256r:
10084   case X86::VSQRTPDZ256rk:
10085   case X86::VSQRTPDZ256rkz:
10086   case X86::VSQRTPDZm:
10087   case X86::VSQRTPDZmb:
10088   case X86::VSQRTPDZmbk:
10089   case X86::VSQRTPDZmbkz:
10090   case X86::VSQRTPDZmk:
10091   case X86::VSQRTPDZmkz:
10092   case X86::VSQRTPDZr:
10093   case X86::VSQRTPDZrb:
10094   case X86::VSQRTPDZrbk:
10095   case X86::VSQRTPDZrbkz:
10096   case X86::VSQRTPDZrk:
10097   case X86::VSQRTPDZrkz:
10098   case X86::VSQRTPSZ128m:
10099   case X86::VSQRTPSZ128mb:
10100   case X86::VSQRTPSZ128mbk:
10101   case X86::VSQRTPSZ128mbkz:
10102   case X86::VSQRTPSZ128mk:
10103   case X86::VSQRTPSZ128mkz:
10104   case X86::VSQRTPSZ128r:
10105   case X86::VSQRTPSZ128rk:
10106   case X86::VSQRTPSZ128rkz:
10107   case X86::VSQRTPSZ256m:
10108   case X86::VSQRTPSZ256mb:
10109   case X86::VSQRTPSZ256mbk:
10110   case X86::VSQRTPSZ256mbkz:
10111   case X86::VSQRTPSZ256mk:
10112   case X86::VSQRTPSZ256mkz:
10113   case X86::VSQRTPSZ256r:
10114   case X86::VSQRTPSZ256rk:
10115   case X86::VSQRTPSZ256rkz:
10116   case X86::VSQRTPSZm:
10117   case X86::VSQRTPSZmb:
10118   case X86::VSQRTPSZmbk:
10119   case X86::VSQRTPSZmbkz:
10120   case X86::VSQRTPSZmk:
10121   case X86::VSQRTPSZmkz:
10122   case X86::VSQRTPSZr:
10123   case X86::VSQRTPSZrb:
10124   case X86::VSQRTPSZrbk:
10125   case X86::VSQRTPSZrbkz:
10126   case X86::VSQRTPSZrk:
10127   case X86::VSQRTPSZrkz:
10128   case X86::VSQRTSDZm:
10129   case X86::VSQRTSDZm_Int:
10130   case X86::VSQRTSDZm_Intk:
10131   case X86::VSQRTSDZm_Intkz:
10132   case X86::VSQRTSDZr:
10133   case X86::VSQRTSDZr_Int:
10134   case X86::VSQRTSDZr_Intk:
10135   case X86::VSQRTSDZr_Intkz:
10136   case X86::VSQRTSDZrb_Int:
10137   case X86::VSQRTSDZrb_Intk:
10138   case X86::VSQRTSDZrb_Intkz:
10139   case X86::VSQRTSSZm:
10140   case X86::VSQRTSSZm_Int:
10141   case X86::VSQRTSSZm_Intk:
10142   case X86::VSQRTSSZm_Intkz:
10143   case X86::VSQRTSSZr:
10144   case X86::VSQRTSSZr_Int:
10145   case X86::VSQRTSSZr_Intk:
10146   case X86::VSQRTSSZr_Intkz:
10147   case X86::VSQRTSSZrb_Int:
10148   case X86::VSQRTSSZrb_Intk:
10149   case X86::VSQRTSSZrb_Intkz:
10150 
10151   case X86::VGATHERDPDYrm:
10152   case X86::VGATHERDPDZ128rm:
10153   case X86::VGATHERDPDZ256rm:
10154   case X86::VGATHERDPDZrm:
10155   case X86::VGATHERDPDrm:
10156   case X86::VGATHERDPSYrm:
10157   case X86::VGATHERDPSZ128rm:
10158   case X86::VGATHERDPSZ256rm:
10159   case X86::VGATHERDPSZrm:
10160   case X86::VGATHERDPSrm:
10161   case X86::VGATHERPF0DPDm:
10162   case X86::VGATHERPF0DPSm:
10163   case X86::VGATHERPF0QPDm:
10164   case X86::VGATHERPF0QPSm:
10165   case X86::VGATHERPF1DPDm:
10166   case X86::VGATHERPF1DPSm:
10167   case X86::VGATHERPF1QPDm:
10168   case X86::VGATHERPF1QPSm:
10169   case X86::VGATHERQPDYrm:
10170   case X86::VGATHERQPDZ128rm:
10171   case X86::VGATHERQPDZ256rm:
10172   case X86::VGATHERQPDZrm:
10173   case X86::VGATHERQPDrm:
10174   case X86::VGATHERQPSYrm:
10175   case X86::VGATHERQPSZ128rm:
10176   case X86::VGATHERQPSZ256rm:
10177   case X86::VGATHERQPSZrm:
10178   case X86::VGATHERQPSrm:
10179   case X86::VPGATHERDDYrm:
10180   case X86::VPGATHERDDZ128rm:
10181   case X86::VPGATHERDDZ256rm:
10182   case X86::VPGATHERDDZrm:
10183   case X86::VPGATHERDDrm:
10184   case X86::VPGATHERDQYrm:
10185   case X86::VPGATHERDQZ128rm:
10186   case X86::VPGATHERDQZ256rm:
10187   case X86::VPGATHERDQZrm:
10188   case X86::VPGATHERDQrm:
10189   case X86::VPGATHERQDYrm:
10190   case X86::VPGATHERQDZ128rm:
10191   case X86::VPGATHERQDZ256rm:
10192   case X86::VPGATHERQDZrm:
10193   case X86::VPGATHERQDrm:
10194   case X86::VPGATHERQQYrm:
10195   case X86::VPGATHERQQZ128rm:
10196   case X86::VPGATHERQQZ256rm:
10197   case X86::VPGATHERQQZrm:
10198   case X86::VPGATHERQQrm:
10199   case X86::VSCATTERDPDZ128mr:
10200   case X86::VSCATTERDPDZ256mr:
10201   case X86::VSCATTERDPDZmr:
10202   case X86::VSCATTERDPSZ128mr:
10203   case X86::VSCATTERDPSZ256mr:
10204   case X86::VSCATTERDPSZmr:
10205   case X86::VSCATTERPF0DPDm:
10206   case X86::VSCATTERPF0DPSm:
10207   case X86::VSCATTERPF0QPDm:
10208   case X86::VSCATTERPF0QPSm:
10209   case X86::VSCATTERPF1DPDm:
10210   case X86::VSCATTERPF1DPSm:
10211   case X86::VSCATTERPF1QPDm:
10212   case X86::VSCATTERPF1QPSm:
10213   case X86::VSCATTERQPDZ128mr:
10214   case X86::VSCATTERQPDZ256mr:
10215   case X86::VSCATTERQPDZmr:
10216   case X86::VSCATTERQPSZ128mr:
10217   case X86::VSCATTERQPSZ256mr:
10218   case X86::VSCATTERQPSZmr:
10219   case X86::VPSCATTERDDZ128mr:
10220   case X86::VPSCATTERDDZ256mr:
10221   case X86::VPSCATTERDDZmr:
10222   case X86::VPSCATTERDQZ128mr:
10223   case X86::VPSCATTERDQZ256mr:
10224   case X86::VPSCATTERDQZmr:
10225   case X86::VPSCATTERQDZ128mr:
10226   case X86::VPSCATTERQDZ256mr:
10227   case X86::VPSCATTERQDZmr:
10228   case X86::VPSCATTERQQZ128mr:
10229   case X86::VPSCATTERQQZ256mr:
10230   case X86::VPSCATTERQQZmr:
10231     return true;
10232   }
10233 }
10234 
10235 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
10236                                          const MachineRegisterInfo *MRI,
10237                                          const MachineInstr &DefMI,
10238                                          unsigned DefIdx,
10239                                          const MachineInstr &UseMI,
10240                                          unsigned UseIdx) const {
10241   return isHighLatencyDef(DefMI.getOpcode());
10242 }
10243 
10244 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
10245                                            const MachineBasicBlock *MBB) const {
10246   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
10247          "Reassociation needs binary operators");
10248 
10249   // Integer binary math/logic instructions have a third source operand:
10250   // the EFLAGS register. That operand must be both defined here and never
10251   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
10252   // not change anything because rearranging the operands could affect other
10253   // instructions that depend on the exact status flags (zero, sign, etc.)
10254   // that are set by using these particular operands with this operation.
10255   if (Inst.getNumOperands() == 4) {
10256     assert(Inst.getOperand(3).isReg() &&
10257            Inst.getOperand(3).getReg() == X86::EFLAGS &&
10258            "Unexpected operand in reassociable instruction");
10259     if (!Inst.getOperand(3).isDead())
10260       return false;
10261   }
10262 
10263   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
10264 }
10265 
10266 // TODO: There are many more machine instruction opcodes to match:
10267 //       1. Other data types (integer, vectors)
10268 //       2. Other math / logic operations (xor, or)
10269 //       3. Other forms of the same operation (intrinsics and other variants)
10270 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
10271   switch (Inst.getOpcode()) {
10272   case X86::AND8rr:
10273   case X86::AND16rr:
10274   case X86::AND32rr:
10275   case X86::AND64rr:
10276   case X86::OR8rr:
10277   case X86::OR16rr:
10278   case X86::OR32rr:
10279   case X86::OR64rr:
10280   case X86::XOR8rr:
10281   case X86::XOR16rr:
10282   case X86::XOR32rr:
10283   case X86::XOR64rr:
10284   case X86::IMUL16rr:
10285   case X86::IMUL32rr:
10286   case X86::IMUL64rr:
10287   case X86::PANDrr:
10288   case X86::PORrr:
10289   case X86::PXORrr:
10290   case X86::ANDPDrr:
10291   case X86::ANDPSrr:
10292   case X86::ORPDrr:
10293   case X86::ORPSrr:
10294   case X86::XORPDrr:
10295   case X86::XORPSrr:
10296   case X86::PADDBrr:
10297   case X86::PADDWrr:
10298   case X86::PADDDrr:
10299   case X86::PADDQrr:
10300   case X86::VPANDrr:
10301   case X86::VPANDYrr:
10302   case X86::VPANDDZ128rr:
10303   case X86::VPANDDZ256rr:
10304   case X86::VPANDDZrr:
10305   case X86::VPANDQZ128rr:
10306   case X86::VPANDQZ256rr:
10307   case X86::VPANDQZrr:
10308   case X86::VPORrr:
10309   case X86::VPORYrr:
10310   case X86::VPORDZ128rr:
10311   case X86::VPORDZ256rr:
10312   case X86::VPORDZrr:
10313   case X86::VPORQZ128rr:
10314   case X86::VPORQZ256rr:
10315   case X86::VPORQZrr:
10316   case X86::VPXORrr:
10317   case X86::VPXORYrr:
10318   case X86::VPXORDZ128rr:
10319   case X86::VPXORDZ256rr:
10320   case X86::VPXORDZrr:
10321   case X86::VPXORQZ128rr:
10322   case X86::VPXORQZ256rr:
10323   case X86::VPXORQZrr:
10324   case X86::VANDPDrr:
10325   case X86::VANDPSrr:
10326   case X86::VANDPDYrr:
10327   case X86::VANDPSYrr:
10328   case X86::VANDPDZ128rr:
10329   case X86::VANDPSZ128rr:
10330   case X86::VANDPDZ256rr:
10331   case X86::VANDPSZ256rr:
10332   case X86::VANDPDZrr:
10333   case X86::VANDPSZrr:
10334   case X86::VORPDrr:
10335   case X86::VORPSrr:
10336   case X86::VORPDYrr:
10337   case X86::VORPSYrr:
10338   case X86::VORPDZ128rr:
10339   case X86::VORPSZ128rr:
10340   case X86::VORPDZ256rr:
10341   case X86::VORPSZ256rr:
10342   case X86::VORPDZrr:
10343   case X86::VORPSZrr:
10344   case X86::VXORPDrr:
10345   case X86::VXORPSrr:
10346   case X86::VXORPDYrr:
10347   case X86::VXORPSYrr:
10348   case X86::VXORPDZ128rr:
10349   case X86::VXORPSZ128rr:
10350   case X86::VXORPDZ256rr:
10351   case X86::VXORPSZ256rr:
10352   case X86::VXORPDZrr:
10353   case X86::VXORPSZrr:
10354   case X86::KADDBrr:
10355   case X86::KADDWrr:
10356   case X86::KADDDrr:
10357   case X86::KADDQrr:
10358   case X86::KANDBrr:
10359   case X86::KANDWrr:
10360   case X86::KANDDrr:
10361   case X86::KANDQrr:
10362   case X86::KORBrr:
10363   case X86::KORWrr:
10364   case X86::KORDrr:
10365   case X86::KORQrr:
10366   case X86::KXORBrr:
10367   case X86::KXORWrr:
10368   case X86::KXORDrr:
10369   case X86::KXORQrr:
10370   case X86::VPADDBrr:
10371   case X86::VPADDWrr:
10372   case X86::VPADDDrr:
10373   case X86::VPADDQrr:
10374   case X86::VPADDBYrr:
10375   case X86::VPADDWYrr:
10376   case X86::VPADDDYrr:
10377   case X86::VPADDQYrr:
10378   case X86::VPADDBZ128rr:
10379   case X86::VPADDWZ128rr:
10380   case X86::VPADDDZ128rr:
10381   case X86::VPADDQZ128rr:
10382   case X86::VPADDBZ256rr:
10383   case X86::VPADDWZ256rr:
10384   case X86::VPADDDZ256rr:
10385   case X86::VPADDQZ256rr:
10386   case X86::VPADDBZrr:
10387   case X86::VPADDWZrr:
10388   case X86::VPADDDZrr:
10389   case X86::VPADDQZrr:
10390   case X86::VPMULLWrr:
10391   case X86::VPMULLWYrr:
10392   case X86::VPMULLWZ128rr:
10393   case X86::VPMULLWZ256rr:
10394   case X86::VPMULLWZrr:
10395   case X86::VPMULLDrr:
10396   case X86::VPMULLDYrr:
10397   case X86::VPMULLDZ128rr:
10398   case X86::VPMULLDZ256rr:
10399   case X86::VPMULLDZrr:
10400   case X86::VPMULLQZ128rr:
10401   case X86::VPMULLQZ256rr:
10402   case X86::VPMULLQZrr:
10403   // Normal min/max instructions are not commutative because of NaN and signed
10404   // zero semantics, but these are. Thus, there's no need to check for global
10405   // relaxed math; the instructions themselves have the properties we need.
10406   case X86::MAXCPDrr:
10407   case X86::MAXCPSrr:
10408   case X86::MAXCSDrr:
10409   case X86::MAXCSSrr:
10410   case X86::MINCPDrr:
10411   case X86::MINCPSrr:
10412   case X86::MINCSDrr:
10413   case X86::MINCSSrr:
10414   case X86::VMAXCPDrr:
10415   case X86::VMAXCPSrr:
10416   case X86::VMAXCPDYrr:
10417   case X86::VMAXCPSYrr:
10418   case X86::VMAXCPDZ128rr:
10419   case X86::VMAXCPSZ128rr:
10420   case X86::VMAXCPDZ256rr:
10421   case X86::VMAXCPSZ256rr:
10422   case X86::VMAXCPDZrr:
10423   case X86::VMAXCPSZrr:
10424   case X86::VMAXCSDrr:
10425   case X86::VMAXCSSrr:
10426   case X86::VMAXCSDZrr:
10427   case X86::VMAXCSSZrr:
10428   case X86::VMINCPDrr:
10429   case X86::VMINCPSrr:
10430   case X86::VMINCPDYrr:
10431   case X86::VMINCPSYrr:
10432   case X86::VMINCPDZ128rr:
10433   case X86::VMINCPSZ128rr:
10434   case X86::VMINCPDZ256rr:
10435   case X86::VMINCPSZ256rr:
10436   case X86::VMINCPDZrr:
10437   case X86::VMINCPSZrr:
10438   case X86::VMINCSDrr:
10439   case X86::VMINCSSrr:
10440   case X86::VMINCSDZrr:
10441   case X86::VMINCSSZrr:
10442     return true;
10443   case X86::ADDPDrr:
10444   case X86::ADDPSrr:
10445   case X86::ADDSDrr:
10446   case X86::ADDSSrr:
10447   case X86::MULPDrr:
10448   case X86::MULPSrr:
10449   case X86::MULSDrr:
10450   case X86::MULSSrr:
10451   case X86::VADDPDrr:
10452   case X86::VADDPSrr:
10453   case X86::VADDPDYrr:
10454   case X86::VADDPSYrr:
10455   case X86::VADDPDZ128rr:
10456   case X86::VADDPSZ128rr:
10457   case X86::VADDPDZ256rr:
10458   case X86::VADDPSZ256rr:
10459   case X86::VADDPDZrr:
10460   case X86::VADDPSZrr:
10461   case X86::VADDSDrr:
10462   case X86::VADDSSrr:
10463   case X86::VADDSDZrr:
10464   case X86::VADDSSZrr:
10465   case X86::VMULPDrr:
10466   case X86::VMULPSrr:
10467   case X86::VMULPDYrr:
10468   case X86::VMULPSYrr:
10469   case X86::VMULPDZ128rr:
10470   case X86::VMULPSZ128rr:
10471   case X86::VMULPDZ256rr:
10472   case X86::VMULPSZ256rr:
10473   case X86::VMULPDZrr:
10474   case X86::VMULPSZrr:
10475   case X86::VMULSDrr:
10476   case X86::VMULSSrr:
10477   case X86::VMULSDZrr:
10478   case X86::VMULSSZrr:
10479     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
10480   default:
10481     return false;
10482   }
10483 }
10484 
10485 /// This is an architecture-specific helper function of reassociateOps.
10486 /// Set special operand attributes for new instructions after reassociation.
10487 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
10488                                          MachineInstr &OldMI2,
10489                                          MachineInstr &NewMI1,
10490                                          MachineInstr &NewMI2) const {
10491   // Integer instructions define an implicit EFLAGS source register operand as
10492   // the third source (fourth total) operand.
10493   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
10494     return;
10495 
10496   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
10497          "Unexpected instruction type for reassociation");
10498 
10499   MachineOperand &OldOp1 = OldMI1.getOperand(3);
10500   MachineOperand &OldOp2 = OldMI2.getOperand(3);
10501   MachineOperand &NewOp1 = NewMI1.getOperand(3);
10502   MachineOperand &NewOp2 = NewMI2.getOperand(3);
10503 
10504   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
10505          "Must have dead EFLAGS operand in reassociable instruction");
10506   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
10507          "Must have dead EFLAGS operand in reassociable instruction");
10508 
10509   (void)OldOp1;
10510   (void)OldOp2;
10511 
10512   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
10513          "Unexpected operand in reassociable instruction");
10514   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
10515          "Unexpected operand in reassociable instruction");
10516 
10517   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
10518   // of this pass or other passes. The EFLAGS operands must be dead in these new
10519   // instructions because the EFLAGS operands in the original instructions must
10520   // be dead in order for reassociation to occur.
10521   NewOp1.setIsDead();
10522   NewOp2.setIsDead();
10523 }
10524 
10525 std::pair<unsigned, unsigned>
10526 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
10527   return std::make_pair(TF, 0u);
10528 }
10529 
10530 ArrayRef<std::pair<unsigned, const char *>>
10531 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
10532   using namespace X86II;
10533   static const std::pair<unsigned, const char *> TargetFlags[] = {
10534       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
10535       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
10536       {MO_GOT, "x86-got"},
10537       {MO_GOTOFF, "x86-gotoff"},
10538       {MO_GOTPCREL, "x86-gotpcrel"},
10539       {MO_PLT, "x86-plt"},
10540       {MO_TLSGD, "x86-tlsgd"},
10541       {MO_TLSLD, "x86-tlsld"},
10542       {MO_TLSLDM, "x86-tlsldm"},
10543       {MO_GOTTPOFF, "x86-gottpoff"},
10544       {MO_INDNTPOFF, "x86-indntpoff"},
10545       {MO_TPOFF, "x86-tpoff"},
10546       {MO_DTPOFF, "x86-dtpoff"},
10547       {MO_NTPOFF, "x86-ntpoff"},
10548       {MO_GOTNTPOFF, "x86-gotntpoff"},
10549       {MO_DLLIMPORT, "x86-dllimport"},
10550       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
10551       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
10552       {MO_TLVP, "x86-tlvp"},
10553       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
10554       {MO_SECREL, "x86-secrel"}};
10555   return makeArrayRef(TargetFlags);
10556 }
10557 
10558 namespace {
10559   /// Create Global Base Reg pass. This initializes the PIC
10560   /// global base register for x86-32.
10561   struct CGBR : public MachineFunctionPass {
10562     static char ID;
10563     CGBR() : MachineFunctionPass(ID) {}
10564 
10565     bool runOnMachineFunction(MachineFunction &MF) override {
10566       const X86TargetMachine *TM =
10567         static_cast<const X86TargetMachine *>(&MF.getTarget());
10568       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
10569 
10570       // Don't do anything if this is 64-bit as 64-bit PIC
10571       // uses RIP relative addressing.
10572       if (STI.is64Bit())
10573         return false;
10574 
10575       // Only emit a global base reg in PIC mode.
10576       if (!TM->isPositionIndependent())
10577         return false;
10578 
10579       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
10580       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
10581 
10582       // If we didn't need a GlobalBaseReg, don't insert code.
10583       if (GlobalBaseReg == 0)
10584         return false;
10585 
10586       // Insert the set of GlobalBaseReg into the first MBB of the function
10587       MachineBasicBlock &FirstMBB = MF.front();
10588       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
10589       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
10590       MachineRegisterInfo &RegInfo = MF.getRegInfo();
10591       const X86InstrInfo *TII = STI.getInstrInfo();
10592 
10593       unsigned PC;
10594       if (STI.isPICStyleGOT())
10595         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
10596       else
10597         PC = GlobalBaseReg;
10598 
10599       // Operand of MovePCtoStack is completely ignored by asm printer. It's
10600       // only used in JIT code emission as displacement to pc.
10601       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
10602 
10603       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
10604       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
10605       if (STI.isPICStyleGOT()) {
10606         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
10607         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
10608           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
10609                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
10610       }
10611 
10612       return true;
10613     }
10614 
10615     StringRef getPassName() const override {
10616       return "X86 PIC Global Base Reg Initialization";
10617     }
10618 
10619     void getAnalysisUsage(AnalysisUsage &AU) const override {
10620       AU.setPreservesCFG();
10621       MachineFunctionPass::getAnalysisUsage(AU);
10622     }
10623   };
10624 }
10625 
10626 char CGBR::ID = 0;
10627 FunctionPass*
10628 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
10629 
10630 namespace {
10631   struct LDTLSCleanup : public MachineFunctionPass {
10632     static char ID;
10633     LDTLSCleanup() : MachineFunctionPass(ID) {}
10634 
10635     bool runOnMachineFunction(MachineFunction &MF) override {
10636       if (skipFunction(*MF.getFunction()))
10637         return false;
10638 
10639       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
10640       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
10641         // No point folding accesses if there isn't at least two.
10642         return false;
10643       }
10644 
10645       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
10646       return VisitNode(DT->getRootNode(), 0);
10647     }
10648 
10649     // Visit the dominator subtree rooted at Node in pre-order.
10650     // If TLSBaseAddrReg is non-null, then use that to replace any
10651     // TLS_base_addr instructions. Otherwise, create the register
10652     // when the first such instruction is seen, and then use it
10653     // as we encounter more instructions.
10654     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
10655       MachineBasicBlock *BB = Node->getBlock();
10656       bool Changed = false;
10657 
10658       // Traverse the current block.
10659       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
10660            ++I) {
10661         switch (I->getOpcode()) {
10662           case X86::TLS_base_addr32:
10663           case X86::TLS_base_addr64:
10664             if (TLSBaseAddrReg)
10665               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
10666             else
10667               I = SetRegister(*I, &TLSBaseAddrReg);
10668             Changed = true;
10669             break;
10670           default:
10671             break;
10672         }
10673       }
10674 
10675       // Visit the children of this block in the dominator tree.
10676       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
10677            I != E; ++I) {
10678         Changed |= VisitNode(*I, TLSBaseAddrReg);
10679       }
10680 
10681       return Changed;
10682     }
10683 
10684     // Replace the TLS_base_addr instruction I with a copy from
10685     // TLSBaseAddrReg, returning the new instruction.
10686     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
10687                                          unsigned TLSBaseAddrReg) {
10688       MachineFunction *MF = I.getParent()->getParent();
10689       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
10690       const bool is64Bit = STI.is64Bit();
10691       const X86InstrInfo *TII = STI.getInstrInfo();
10692 
10693       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
10694       MachineInstr *Copy =
10695           BuildMI(*I.getParent(), I, I.getDebugLoc(),
10696                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
10697               .addReg(TLSBaseAddrReg);
10698 
10699       // Erase the TLS_base_addr instruction.
10700       I.eraseFromParent();
10701 
10702       return Copy;
10703     }
10704 
10705     // Create a virtual register in *TLSBaseAddrReg, and populate it by
10706     // inserting a copy instruction after I. Returns the new instruction.
10707     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
10708       MachineFunction *MF = I.getParent()->getParent();
10709       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
10710       const bool is64Bit = STI.is64Bit();
10711       const X86InstrInfo *TII = STI.getInstrInfo();
10712 
10713       // Create a virtual register for the TLS base address.
10714       MachineRegisterInfo &RegInfo = MF->getRegInfo();
10715       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
10716                                                       ? &X86::GR64RegClass
10717                                                       : &X86::GR32RegClass);
10718 
10719       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
10720       MachineInstr *Next = I.getNextNode();
10721       MachineInstr *Copy =
10722           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
10723                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
10724               .addReg(is64Bit ? X86::RAX : X86::EAX);
10725 
10726       return Copy;
10727     }
10728 
10729     StringRef getPassName() const override {
10730       return "Local Dynamic TLS Access Clean-up";
10731     }
10732 
10733     void getAnalysisUsage(AnalysisUsage &AU) const override {
10734       AU.setPreservesCFG();
10735       AU.addRequired<MachineDominatorTree>();
10736       MachineFunctionPass::getAnalysisUsage(AU);
10737     }
10738   };
10739 }
10740 
10741 char LDTLSCleanup::ID = 0;
10742 FunctionPass*
10743 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
10744 
10745 // Constants defining how certain sequences should be outlined.
10746 const unsigned MachineOutlinerDefaultFn = 0;
10747 const unsigned MachineOutlinerTailCallFn = 1;
10748 
10749 std::pair<size_t, unsigned> X86InstrInfo::getOutliningCallOverhead(
10750     MachineBasicBlock::iterator &StartIt,
10751     MachineBasicBlock::iterator &EndIt) const {
10752 
10753   // Is this a tail call? If it is, make note of it.
10754   if (EndIt->isTerminator())
10755     return std::make_pair(1, MachineOutlinerTailCallFn);
10756 
10757   return std::make_pair(1, MachineOutlinerDefaultFn);
10758 }
10759 
10760 std::pair<size_t, unsigned> X86InstrInfo::getOutliningFrameOverhead(
10761   std::vector<std::pair<MachineBasicBlock::iterator,
10762                         MachineBasicBlock::iterator>> &CandidateClass) const {
10763   // Is this a tail-call?
10764   // Is the last instruction in this class a terminator?
10765   if (CandidateClass[0].second->isTerminator())
10766     return std::make_pair(0, MachineOutlinerTailCallFn);
10767 
10768   // No, so we have to add a return to the end.
10769   return std::make_pair(1, MachineOutlinerDefaultFn);
10770 }
10771 
10772 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF) const {
10773   return MF.getFunction()->hasFnAttribute(Attribute::NoRedZone);
10774 }
10775 
10776 X86GenInstrInfo::MachineOutlinerInstrType
10777 X86InstrInfo::getOutliningType(MachineInstr &MI) const {
10778 
10779   // Don't allow debug values to impact outlining type.
10780   if (MI.isDebugValue() || MI.isIndirectDebugValue())
10781     return MachineOutlinerInstrType::Invisible;
10782 
10783   // Is this a tail call? If yes, we can outline as a tail call.
10784   if (isTailCall(MI))
10785     return MachineOutlinerInstrType::Legal;
10786 
10787   // Is this the terminator of a basic block?
10788   if (MI.isTerminator() || MI.isReturn()) {
10789 
10790     // Does its parent have any successors in its MachineFunction?
10791     if (MI.getParent()->succ_empty())
10792         return MachineOutlinerInstrType::Legal;
10793 
10794     // It does, so we can't tail call it.
10795     return MachineOutlinerInstrType::Illegal;
10796   }
10797 
10798   // Don't outline anything that modifies or reads from the stack pointer.
10799   //
10800   // FIXME: There are instructions which are being manually built without
10801   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
10802   // able to remove the extra checks once those are fixed up. For example,
10803   // sometimes we might get something like %RAX<def> = POP64r 1. This won't be
10804   // caught by modifiesRegister or readsRegister even though the instruction
10805   // really ought to be formed so that modifiesRegister/readsRegister would
10806   // catch it.
10807   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
10808       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
10809       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
10810     return MachineOutlinerInstrType::Illegal;
10811 
10812   // Outlined calls change the instruction pointer, so don't read from it.
10813   if (MI.readsRegister(X86::RIP, &RI) ||
10814       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
10815       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
10816     return MachineOutlinerInstrType::Illegal;
10817 
10818   // Positions can't safely be outlined.
10819   if (MI.isPosition())
10820     return MachineOutlinerInstrType::Illegal;
10821 
10822   // Make sure none of the operands of this instruction do anything tricky.
10823   for (const MachineOperand &MOP : MI.operands())
10824     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
10825         MOP.isTargetIndex())
10826       return MachineOutlinerInstrType::Illegal;
10827 
10828   return MachineOutlinerInstrType::Legal;
10829 }
10830 
10831 void X86InstrInfo::insertOutlinerEpilogue(MachineBasicBlock &MBB,
10832                                           MachineFunction &MF,
10833                                           unsigned FrameClass) const {
10834 
10835   // If we're a tail call, we already have a return, so don't do anything.
10836   if (FrameClass == MachineOutlinerTailCallFn)
10837     return;
10838 
10839   // We're a normal call, so our sequence doesn't have a return instruction.
10840   // Add it in.
10841   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
10842   MBB.insert(MBB.end(), retq);
10843 }
10844 
10845 void X86InstrInfo::insertOutlinerPrologue(MachineBasicBlock &MBB,
10846                                           MachineFunction &MF,
10847                                           unsigned FrameClass) const {}
10848 
10849 MachineBasicBlock::iterator
10850 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
10851                                  MachineBasicBlock::iterator &It,
10852                                  MachineFunction &MF,
10853                                  unsigned CallClass) const {
10854   // Is it a tail call?
10855   if (CallClass == MachineOutlinerTailCallFn) {
10856     // Yes, just insert a JMP.
10857     It = MBB.insert(It,
10858                   BuildMI(MF, DebugLoc(), get(X86::JMP_1))
10859                       .addGlobalAddress(M.getNamedValue(MF.getName())));
10860   } else {
10861     // No, insert a call.
10862     It = MBB.insert(It,
10863                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
10864                       .addGlobalAddress(M.getNamedValue(MF.getName())));
10865   }
10866 
10867   return It;
10868 }
10869