1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "x86-instr-info"
45 
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
48 
49 static cl::opt<bool>
50 NoFusing("disable-spill-fusing",
51          cl::desc("Disable fusing of spill code into instructions"));
52 static cl::opt<bool>
53 PrintFailedFusing("print-failed-fuse-candidates",
54                   cl::desc("Print instructions that the allocator wants to"
55                            " fuse, but the X86 backend currently can't"),
56                   cl::Hidden);
57 static cl::opt<bool>
58 ReMatPICStubLoad("remat-pic-stub-load",
59                  cl::desc("Re-materialize load from stub in PIC mode"),
60                  cl::init(false), cl::Hidden);
61 
62 enum {
63   // Select which memory operand is being unfolded.
64   // (stored in bits 0 - 3)
65   TB_INDEX_0    = 0,
66   TB_INDEX_1    = 1,
67   TB_INDEX_2    = 2,
68   TB_INDEX_3    = 3,
69   TB_INDEX_4    = 4,
70   TB_INDEX_MASK = 0xf,
71 
72   // Do not insert the reverse map (MemOp -> RegOp) into the table.
73   // This may be needed because there is a many -> one mapping.
74   TB_NO_REVERSE   = 1 << 4,
75 
76   // Do not insert the forward map (RegOp -> MemOp) into the table.
77   // This is needed for Native Client, which prohibits branch
78   // instructions from using a memory operand.
79   TB_NO_FORWARD   = 1 << 5,
80 
81   TB_FOLDED_LOAD  = 1 << 6,
82   TB_FOLDED_STORE = 1 << 7,
83 
84   // Minimum alignment required for load/store.
85   // Used for RegOp->MemOp conversion.
86   // (stored in bits 8 - 15)
87   TB_ALIGN_SHIFT = 8,
88   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
89   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
90   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
91   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
92   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
93 };
94 
95 struct X86MemoryFoldTableEntry {
96   uint16_t RegOp;
97   uint16_t MemOp;
98   uint16_t Flags;
99 };
100 
101 // Pin the vtable to this file.
102 void X86InstrInfo::anchor() {}
103 
104 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
105     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
106                                                : X86::ADJCALLSTACKDOWN32),
107                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
108                                                : X86::ADJCALLSTACKUP32),
109                       X86::CATCHRET),
110       Subtarget(STI), RI(STI.getTargetTriple()) {
111 
112   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
113     { X86::ADC32ri,     X86::ADC32mi,    0 },
114     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
115     { X86::ADC32rr,     X86::ADC32mr,    0 },
116     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
117     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
118     { X86::ADC64rr,     X86::ADC64mr,    0 },
119     { X86::ADD16ri,     X86::ADD16mi,    0 },
120     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
121     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
122     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
123     { X86::ADD16rr,     X86::ADD16mr,    0 },
124     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
125     { X86::ADD32ri,     X86::ADD32mi,    0 },
126     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
127     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
128     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
129     { X86::ADD32rr,     X86::ADD32mr,    0 },
130     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
131     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
132     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
133     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
134     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
135     { X86::ADD64rr,     X86::ADD64mr,    0 },
136     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
137     { X86::ADD8ri,      X86::ADD8mi,     0 },
138     { X86::ADD8rr,      X86::ADD8mr,     0 },
139     { X86::AND16ri,     X86::AND16mi,    0 },
140     { X86::AND16ri8,    X86::AND16mi8,   0 },
141     { X86::AND16rr,     X86::AND16mr,    0 },
142     { X86::AND32ri,     X86::AND32mi,    0 },
143     { X86::AND32ri8,    X86::AND32mi8,   0 },
144     { X86::AND32rr,     X86::AND32mr,    0 },
145     { X86::AND64ri32,   X86::AND64mi32,  0 },
146     { X86::AND64ri8,    X86::AND64mi8,   0 },
147     { X86::AND64rr,     X86::AND64mr,    0 },
148     { X86::AND8ri,      X86::AND8mi,     0 },
149     { X86::AND8rr,      X86::AND8mr,     0 },
150     { X86::DEC16r,      X86::DEC16m,     0 },
151     { X86::DEC32r,      X86::DEC32m,     0 },
152     { X86::DEC64r,      X86::DEC64m,     0 },
153     { X86::DEC8r,       X86::DEC8m,      0 },
154     { X86::INC16r,      X86::INC16m,     0 },
155     { X86::INC32r,      X86::INC32m,     0 },
156     { X86::INC64r,      X86::INC64m,     0 },
157     { X86::INC8r,       X86::INC8m,      0 },
158     { X86::NEG16r,      X86::NEG16m,     0 },
159     { X86::NEG32r,      X86::NEG32m,     0 },
160     { X86::NEG64r,      X86::NEG64m,     0 },
161     { X86::NEG8r,       X86::NEG8m,      0 },
162     { X86::NOT16r,      X86::NOT16m,     0 },
163     { X86::NOT32r,      X86::NOT32m,     0 },
164     { X86::NOT64r,      X86::NOT64m,     0 },
165     { X86::NOT8r,       X86::NOT8m,      0 },
166     { X86::OR16ri,      X86::OR16mi,     0 },
167     { X86::OR16ri8,     X86::OR16mi8,    0 },
168     { X86::OR16rr,      X86::OR16mr,     0 },
169     { X86::OR32ri,      X86::OR32mi,     0 },
170     { X86::OR32ri8,     X86::OR32mi8,    0 },
171     { X86::OR32rr,      X86::OR32mr,     0 },
172     { X86::OR64ri32,    X86::OR64mi32,   0 },
173     { X86::OR64ri8,     X86::OR64mi8,    0 },
174     { X86::OR64rr,      X86::OR64mr,     0 },
175     { X86::OR8ri,       X86::OR8mi,      0 },
176     { X86::OR8rr,       X86::OR8mr,      0 },
177     { X86::ROL16r1,     X86::ROL16m1,    0 },
178     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
179     { X86::ROL16ri,     X86::ROL16mi,    0 },
180     { X86::ROL32r1,     X86::ROL32m1,    0 },
181     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
182     { X86::ROL32ri,     X86::ROL32mi,    0 },
183     { X86::ROL64r1,     X86::ROL64m1,    0 },
184     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
185     { X86::ROL64ri,     X86::ROL64mi,    0 },
186     { X86::ROL8r1,      X86::ROL8m1,     0 },
187     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
188     { X86::ROL8ri,      X86::ROL8mi,     0 },
189     { X86::ROR16r1,     X86::ROR16m1,    0 },
190     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
191     { X86::ROR16ri,     X86::ROR16mi,    0 },
192     { X86::ROR32r1,     X86::ROR32m1,    0 },
193     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
194     { X86::ROR32ri,     X86::ROR32mi,    0 },
195     { X86::ROR64r1,     X86::ROR64m1,    0 },
196     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
197     { X86::ROR64ri,     X86::ROR64mi,    0 },
198     { X86::ROR8r1,      X86::ROR8m1,     0 },
199     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
200     { X86::ROR8ri,      X86::ROR8mi,     0 },
201     { X86::SAR16r1,     X86::SAR16m1,    0 },
202     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
203     { X86::SAR16ri,     X86::SAR16mi,    0 },
204     { X86::SAR32r1,     X86::SAR32m1,    0 },
205     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
206     { X86::SAR32ri,     X86::SAR32mi,    0 },
207     { X86::SAR64r1,     X86::SAR64m1,    0 },
208     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
209     { X86::SAR64ri,     X86::SAR64mi,    0 },
210     { X86::SAR8r1,      X86::SAR8m1,     0 },
211     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
212     { X86::SAR8ri,      X86::SAR8mi,     0 },
213     { X86::SBB32ri,     X86::SBB32mi,    0 },
214     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
215     { X86::SBB32rr,     X86::SBB32mr,    0 },
216     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
217     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
218     { X86::SBB64rr,     X86::SBB64mr,    0 },
219     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
220     { X86::SHL16ri,     X86::SHL16mi,    0 },
221     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
222     { X86::SHL32ri,     X86::SHL32mi,    0 },
223     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
224     { X86::SHL64ri,     X86::SHL64mi,    0 },
225     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
226     { X86::SHL8ri,      X86::SHL8mi,     0 },
227     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
228     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
229     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
230     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
231     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
232     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
233     { X86::SHR16r1,     X86::SHR16m1,    0 },
234     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
235     { X86::SHR16ri,     X86::SHR16mi,    0 },
236     { X86::SHR32r1,     X86::SHR32m1,    0 },
237     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
238     { X86::SHR32ri,     X86::SHR32mi,    0 },
239     { X86::SHR64r1,     X86::SHR64m1,    0 },
240     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
241     { X86::SHR64ri,     X86::SHR64mi,    0 },
242     { X86::SHR8r1,      X86::SHR8m1,     0 },
243     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
244     { X86::SHR8ri,      X86::SHR8mi,     0 },
245     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
246     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
247     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
248     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
249     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
250     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
251     { X86::SUB16ri,     X86::SUB16mi,    0 },
252     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
253     { X86::SUB16rr,     X86::SUB16mr,    0 },
254     { X86::SUB32ri,     X86::SUB32mi,    0 },
255     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
256     { X86::SUB32rr,     X86::SUB32mr,    0 },
257     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
258     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
259     { X86::SUB64rr,     X86::SUB64mr,    0 },
260     { X86::SUB8ri,      X86::SUB8mi,     0 },
261     { X86::SUB8rr,      X86::SUB8mr,     0 },
262     { X86::XOR16ri,     X86::XOR16mi,    0 },
263     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
264     { X86::XOR16rr,     X86::XOR16mr,    0 },
265     { X86::XOR32ri,     X86::XOR32mi,    0 },
266     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
267     { X86::XOR32rr,     X86::XOR32mr,    0 },
268     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
269     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
270     { X86::XOR64rr,     X86::XOR64mr,    0 },
271     { X86::XOR8ri,      X86::XOR8mi,     0 },
272     { X86::XOR8rr,      X86::XOR8mr,     0 }
273   };
274 
275   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
276     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
277                   Entry.RegOp, Entry.MemOp,
278                   // Index 0, folded load and store, no alignment requirement.
279                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
280   }
281 
282   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
283     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
284     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
285     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
286     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
287     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
288     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
289     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
290     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
291     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
292     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
293     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
294     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
295     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
296     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
297     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
298     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
299     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
300     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
301     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
302     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
303     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
304     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
305     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
306     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
307     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
308     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
309     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
310     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
311     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
312     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
313     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
314     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
315     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
316     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
317     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
318     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
319     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
320     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
321     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
322     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
326     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
327     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
328     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
329     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
330     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
331     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
332     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
333     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
334     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
335     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
336     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
337     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
338     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
339     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
340     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
341     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
342     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
343     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
344     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
345     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
346     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
347     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
348     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
349     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
350     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
351     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
352     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
353     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
354     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
355     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
356     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
357     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
358     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
359     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
360     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
361     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
362     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
363     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
364 
365     // AVX 128-bit versions of foldable instructions
366     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
367     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
368     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
369     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
370     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
371     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
372     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
373     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
374     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
375     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
376     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
377     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
378     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
379 
380     // AVX 256-bit foldable instructions
381     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
382     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
383     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
384     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
385     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
386     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
387 
388     // AVX-512 foldable instructions
389     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
390     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
391     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
392     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
393     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
394     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
395     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
396     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
397     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
398     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
399     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
400 
401     // AVX-512 foldable instructions (256-bit versions)
402     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
403     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
404     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
405     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
406     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
407     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
408     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
409     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
410     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
411     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
412 
413     // AVX-512 foldable instructions (128-bit versions)
414     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
415     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
416     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
417     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
418     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
419     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
420     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
421     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
422     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
423     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
424 
425     // F16C foldable instructions
426     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
427     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
428   };
429 
430   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
431     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
432                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
433   }
434 
435   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
436     { X86::BSF16rr,         X86::BSF16rm,             0 },
437     { X86::BSF32rr,         X86::BSF32rm,             0 },
438     { X86::BSF64rr,         X86::BSF64rm,             0 },
439     { X86::BSR16rr,         X86::BSR16rm,             0 },
440     { X86::BSR32rr,         X86::BSR32rm,             0 },
441     { X86::BSR64rr,         X86::BSR64rm,             0 },
442     { X86::CMP16rr,         X86::CMP16rm,             0 },
443     { X86::CMP32rr,         X86::CMP32rm,             0 },
444     { X86::CMP64rr,         X86::CMP64rm,             0 },
445     { X86::CMP8rr,          X86::CMP8rm,              0 },
446     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
447     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
448     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
449     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
450     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
451     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
452     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
453     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
454     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
455     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
456     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
457     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
458     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
459     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
460     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
461     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
462     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
463     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
464     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
465     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
466     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
467     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
468     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
469     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
470     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
471     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
472     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
473     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
474     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
475     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
476     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
477     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
478     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
479     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
480     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
481     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
482     { X86::MOV16rr,         X86::MOV16rm,             0 },
483     { X86::MOV32rr,         X86::MOV32rm,             0 },
484     { X86::MOV64rr,         X86::MOV64rm,             0 },
485     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
486     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
487     { X86::MOV8rr,          X86::MOV8rm,              0 },
488     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
489     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
490     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
491     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
492     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
493     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
494     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
495     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
496     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
497     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
498     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
499     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
500     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
501     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
502     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
503     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
504     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
505     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
506     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
507     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
508     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
509     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
510     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
511     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
512     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
513     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
514     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
515     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
516     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
517     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
518     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
519     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
520     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
521     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
522     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
523     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
524     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
525     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
526     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
527     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
528     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
529     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
530     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
531     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
532     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
533     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
534     { X86::RCPSSr,          X86::RCPSSm,              0 },
535     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          0 },
536     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
537     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
538     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
539     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
540     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
541     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
542     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
543     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
544     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
545     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
546     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
547     { X86::TEST16rr,        X86::TEST16rm,            0 },
548     { X86::TEST32rr,        X86::TEST32rm,            0 },
549     { X86::TEST64rr,        X86::TEST64rm,            0 },
550     { X86::TEST8rr,         X86::TEST8rm,             0 },
551     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
552     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
553     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
554 
555     // MMX version of foldable instructions
556     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
557     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
558     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
559     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
560     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
561     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
562     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
563     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
564     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
565     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
566 
567     // 3DNow! version of foldable instructions
568     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
569     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
570     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
571     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
572     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
573     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
574     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
575 
576     // AVX 128-bit versions of foldable instructions
577     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
578     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
579     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
580     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
581     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
582     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
583     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
584     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
585     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
586     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
587     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
588     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
589     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
590     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
591     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
592     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
593     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
594     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
595     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
596     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
597     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
598     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
599     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
600     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
601     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
602     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
603     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
604     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
605     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
606     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
607     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
608     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
609     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
610     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
611     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
612     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
613     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
614     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
615     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
616     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
617     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
618     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
619     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
620     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
621     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
622     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
623     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
624     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
625     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
626     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
627     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
628     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
629     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
630     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
631     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
632     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
633     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
634     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
635     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
636     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
637     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
638     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
639     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
640     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
641     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
642     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
643     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
644     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
645     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
646     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
647     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
648     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
649     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
650 
651     // AVX 256-bit foldable instructions
652     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
653     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
654     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
655     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
656     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
657     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
658     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
659     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
660     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
661     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
662     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
663     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
664     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
665     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
666     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
667     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
668     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
669     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
670     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
671     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
672     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
673     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
674     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
675     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
676     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
677     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
678     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
679 
680     // AVX2 foldable instructions
681 
682     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
683     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
684     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
685     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
686     // so they don't need an equivalent limitation.
687     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
688     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
689     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
690     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
691     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
692     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
693     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      0 },
694     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     0 },
695     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      0 },
696     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     0 },
697     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      0 },
698     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     0 },
699     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      0 },
700     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     0 },
701     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
702     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
703     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        0 },
704     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        0 },
705     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
706     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
707     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
708     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        0 },
709     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        0 },
710     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        0 },
711     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
712     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
713     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
714     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        0 },
715     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
716     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
717     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
718 
719     // XOP foldable instructions
720     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
721     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
722     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
723     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
724     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
725     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
726     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
727     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
728     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
729     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
730     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
731     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
732     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
733     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
734     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
735     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
736     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
737     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
738     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
739     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
740     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
741     { X86::VPROTBri,           X86::VPROTBmi,         0 },
742     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
743     { X86::VPROTDri,           X86::VPROTDmi,         0 },
744     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
745     { X86::VPROTQri,           X86::VPROTQmi,         0 },
746     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
747     { X86::VPROTWri,           X86::VPROTWmi,         0 },
748     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
749     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
750     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
751     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
752     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
753     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
754     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
755     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
756     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
757 
758     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
759     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
760     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
761     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
762     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
763     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
764     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
765     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
766     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
767     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
768     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
769     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
770     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
771     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
772     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
773     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
774     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
775     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
776     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
777     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
778     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
779     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
780     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
781     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
782     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
783     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
784     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
785     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
786     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
787     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
788     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
789     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
790     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
791     { X86::RORX32ri,        X86::RORX32mi,            0 },
792     { X86::RORX64ri,        X86::RORX64mi,            0 },
793     { X86::SARX32rr,        X86::SARX32rm,            0 },
794     { X86::SARX64rr,        X86::SARX64rm,            0 },
795     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
796     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
797     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
798     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
799     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
800     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
801     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
802     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
803     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
804     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
805     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
806 
807     // AVX-512 foldable instructions
808     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
809     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
810     { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
811     { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
812     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
813     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
814     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zrm,         0 },
815     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zrm,        0 },
816     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
817     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
818     { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
819     { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
820     { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
821     { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
822     { X86::VBROADCASTSSZr,  X86::VBROADCASTSSZm,      TB_NO_REVERSE },
823     { X86::VBROADCASTSDZr,  X86::VBROADCASTSDZm,      TB_NO_REVERSE },
824 
825     // AVX-512 foldable instructions (256-bit versions)
826     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256rm,          TB_ALIGN_32 },
827     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256rm,          TB_ALIGN_32 },
828     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256rm,        TB_ALIGN_32 },
829     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256rm,        TB_ALIGN_32 },
830     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256rm,         0 },
831     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256rm,        0 },
832     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256rm,        0 },
833     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256rm,        0 },
834     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256rm,          0 },
835     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256rm,          0 },
836     { X86::VBROADCASTSSZ256r,  X86::VBROADCASTSSZ256m,      TB_NO_REVERSE },
837     { X86::VBROADCASTSDZ256r,  X86::VBROADCASTSDZ256m,      TB_NO_REVERSE },
838 
839     // AVX-512 foldable instructions (256-bit versions)
840     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128rm,          TB_ALIGN_16 },
841     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128rm,          TB_ALIGN_16 },
842     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128rm,        TB_ALIGN_16 },
843     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128rm,        TB_ALIGN_16 },
844     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128rm,         0 },
845     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128rm,        0 },
846     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128rm,        0 },
847     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128rm,        0 },
848     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128rm,          0 },
849     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128rm,          0 },
850     { X86::VBROADCASTSSZ128r,  X86::VBROADCASTSSZ128m,      TB_NO_REVERSE },
851 
852     // F16C foldable instructions
853     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
854     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
855 
856     // AES foldable instructions
857     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
858     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
859     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
860     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
861   };
862 
863   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
864     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
865                   Entry.RegOp, Entry.MemOp,
866                   // Index 1, folded load
867                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
868   }
869 
870   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
871     { X86::ADC32rr,         X86::ADC32rm,       0 },
872     { X86::ADC64rr,         X86::ADC64rm,       0 },
873     { X86::ADD16rr,         X86::ADD16rm,       0 },
874     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
875     { X86::ADD32rr,         X86::ADD32rm,       0 },
876     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
877     { X86::ADD64rr,         X86::ADD64rm,       0 },
878     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
879     { X86::ADD8rr,          X86::ADD8rm,        0 },
880     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
881     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
882     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
883     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
884     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
885     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
886     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
887     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
888     { X86::AND16rr,         X86::AND16rm,       0 },
889     { X86::AND32rr,         X86::AND32rm,       0 },
890     { X86::AND64rr,         X86::AND64rm,       0 },
891     { X86::AND8rr,          X86::AND8rm,        0 },
892     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
893     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
894     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
895     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
896     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
897     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
898     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
899     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
900     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
901     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
902     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
903     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
904     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
905     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
906     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
907     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
908     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
909     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
910     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
911     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
912     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
913     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
914     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
915     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
916     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
917     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
918     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
919     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
920     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
921     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
922     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
923     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
924     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
925     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
926     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
927     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
928     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
929     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
930     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
931     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
932     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
933     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
934     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
935     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
936     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
937     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
938     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
939     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
940     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
941     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
942     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
943     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
944     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
945     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
946     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
947     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
948     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
949     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
950     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
951     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
952     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
953     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
954     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
955     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
956     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
957     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
958     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
959     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
960     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
961     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
962 
963     // Do not fold Fs* scalar logical op loads because there are no scalar
964     // load variants for these instructions. When folded, the load is required
965     // to be 128-bits, so the load size would not match.
966 
967     { X86::FvANDNPDrr,      X86::FvANDNPDrm,    TB_ALIGN_16 },
968     { X86::FvANDNPSrr,      X86::FvANDNPSrm,    TB_ALIGN_16 },
969     { X86::FvANDPDrr,       X86::FvANDPDrm,     TB_ALIGN_16 },
970     { X86::FvANDPSrr,       X86::FvANDPSrm,     TB_ALIGN_16 },
971     { X86::FvORPDrr,        X86::FvORPDrm,      TB_ALIGN_16 },
972     { X86::FvORPSrr,        X86::FvORPSrm,      TB_ALIGN_16 },
973     { X86::FvXORPDrr,       X86::FvXORPDrm,     TB_ALIGN_16 },
974     { X86::FvXORPSrr,       X86::FvXORPSrm,     TB_ALIGN_16 },
975     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
976     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
977     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
978     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
979     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
980     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
981     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
982     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
983     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
984     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
985     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
986     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
987     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
988     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
989     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
990     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
991     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
992     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
993     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
994     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
995     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
996     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
997     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
998     { X86::MINSDrr,         X86::MINSDrm,       0 },
999     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
1000     { X86::MINSSrr,         X86::MINSSrm,       0 },
1001     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
1002     { X86::MOVLHPSrr,       X86::MOVHPSrm,      TB_NO_REVERSE },
1003     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1004     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1005     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1006     { X86::MULSDrr,         X86::MULSDrm,       0 },
1007     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
1008     { X86::MULSSrr,         X86::MULSSrm,       0 },
1009     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
1010     { X86::OR16rr,          X86::OR16rm,        0 },
1011     { X86::OR32rr,          X86::OR32rm,        0 },
1012     { X86::OR64rr,          X86::OR64rm,        0 },
1013     { X86::OR8rr,           X86::OR8rm,         0 },
1014     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1015     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1016     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1017     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1018     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1019     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1020     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1021     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1022     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1023     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1024     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1025     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1026     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1027     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1028     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
1029     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1030     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1031     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1032     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1033     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1034     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1035     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1036     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1037     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1038     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1039     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1040     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1041     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1042     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1043     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1044     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1045     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1046     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1047     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1048     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1049     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1050     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1051     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1052     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1053     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1054     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
1055     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1056     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1057     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1058     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1059     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1060     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1061     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1062     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1063     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1064     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1065     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1066     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1067     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1068     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1069     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
1070     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1071     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1072     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1073     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1074     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1075     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1076     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1077     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1078     { X86::PSIGNBrr128,     X86::PSIGNBrm128,   TB_ALIGN_16 },
1079     { X86::PSIGNWrr128,     X86::PSIGNWrm128,   TB_ALIGN_16 },
1080     { X86::PSIGNDrr128,     X86::PSIGNDrm128,   TB_ALIGN_16 },
1081     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1082     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1083     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1084     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1085     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1086     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1087     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1088     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1089     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1090     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1091     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1092     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1093     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1094     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1095     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1096     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1097     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1098     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1099     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1100     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1101     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1102     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1103     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1104     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1105     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1106     { X86::ROUNDSDr,        X86::ROUNDSDm,      0 },
1107     { X86::ROUNDSSr,        X86::ROUNDSSm,      0 },
1108     { X86::SBB32rr,         X86::SBB32rm,       0 },
1109     { X86::SBB64rr,         X86::SBB64rm,       0 },
1110     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1111     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1112     { X86::SUB16rr,         X86::SUB16rm,       0 },
1113     { X86::SUB32rr,         X86::SUB32rm,       0 },
1114     { X86::SUB64rr,         X86::SUB64rm,       0 },
1115     { X86::SUB8rr,          X86::SUB8rm,        0 },
1116     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1117     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1118     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1119     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1120     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1121     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1122     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1123     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1124     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1125     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1126     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1127     { X86::XOR16rr,         X86::XOR16rm,       0 },
1128     { X86::XOR32rr,         X86::XOR32rm,       0 },
1129     { X86::XOR64rr,         X86::XOR64rm,       0 },
1130     { X86::XOR8rr,          X86::XOR8rm,        0 },
1131     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1132     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1133 
1134     // MMX version of foldable instructions
1135     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1136     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1137     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1138     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1139     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1140     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1141     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1142     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1143     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1144     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1145     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1146     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1147     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1148     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1149     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1150     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1151     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1152     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1153     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1154     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1155     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1156     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1157     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1158     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1159     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1160     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1161     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1162     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1163     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1164     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1165     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1166     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1167     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1168     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1169     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1170     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1171     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1172     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1173     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1174     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1175     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1176     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1177     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1178     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1179     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1180     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1181     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1182     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1183     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1184     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1185     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1186     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1187     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1188     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1189     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1190     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1191     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1192     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1193     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1194     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1195     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1196     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1197     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1198     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1199     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1200     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1201     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1202     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1203     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1204     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1205 
1206     // 3DNow! version of foldable instructions
1207     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1208     { X86::PFACCrr,           X86::PFACCrm,           0 },
1209     { X86::PFADDrr,           X86::PFADDrm,           0 },
1210     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1211     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1212     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1213     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1214     { X86::PFMINrr,           X86::PFMINrm,           0 },
1215     { X86::PFMULrr,           X86::PFMULrm,           0 },
1216     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1217     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1218     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1219     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1220     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1221     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1222     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1223     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1224 
1225     // AVX 128-bit versions of foldable instructions
1226     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1227     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1228     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1229     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1230     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1231     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1232     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1233     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1234     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1235     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1236     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1237     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1238     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1239     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        0 },
1240     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1241     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      0 },
1242     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1243     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       0 },
1244     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1245     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       0 },
1246     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1247     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1248     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1249     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1250     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1251     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1252     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1253     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1254     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1255     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1256     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1257     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1258     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1259     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1260     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1261     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1262     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1263     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1264     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1265     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1266     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1267     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1268     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1269     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1270     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1271     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1272     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1273     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1274     // Do not fold VFs* loads because there are no scalar load variants for
1275     // these instructions. When folded, the load is required to be 128-bits, so
1276     // the load size would not match.
1277     { X86::VFvANDNPDrr,       X86::VFvANDNPDrm,        0 },
1278     { X86::VFvANDNPSrr,       X86::VFvANDNPSrm,        0 },
1279     { X86::VFvANDPDrr,        X86::VFvANDPDrm,         0 },
1280     { X86::VFvANDPSrr,        X86::VFvANDPSrm,         0 },
1281     { X86::VFvORPDrr,         X86::VFvORPDrm,          0 },
1282     { X86::VFvORPSrr,         X86::VFvORPSrm,          0 },
1283     { X86::VFvXORPDrr,        X86::VFvXORPDrm,         0 },
1284     { X86::VFvXORPSrr,        X86::VFvXORPSrm,         0 },
1285     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1286     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1287     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1288     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1289     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1290     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1291     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1292     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1293     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1294     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1295     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1296     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1297     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1298     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1299     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1300     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1301     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1302     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1303     { X86::VMOVLHPSrr,        X86::VMOVHPSrm,          TB_NO_REVERSE },
1304     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1305     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1306     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1307     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1308     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1309     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1310     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1311     { X86::VORPDrr,           X86::VORPDrm,            0 },
1312     { X86::VORPSrr,           X86::VORPSrm,            0 },
1313     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1314     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1315     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1316     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1317     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1318     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1319     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1320     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1321     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1322     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1323     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1324     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1325     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
1326     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1327     { X86::VPANDrr,           X86::VPANDrm,            0 },
1328     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1329     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1330     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1331     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1332     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1333     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1334     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1335     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1336     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1337     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1338     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1339     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1340     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1341     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1342     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1343     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1344     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1345     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1346     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1347     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1348     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1349     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1350     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1351     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1352     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1353     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1354     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1355     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1356     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1357     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1358     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1359     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1360     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1361     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1362     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1363     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1364     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1365     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1366     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1367     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1368     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1369     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1370     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1371     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1372     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1373     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1374     { X86::VPORrr,            X86::VPORrm,             0 },
1375     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1376     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1377     { X86::VPSIGNBrr128,      X86::VPSIGNBrm128,       0 },
1378     { X86::VPSIGNWrr128,      X86::VPSIGNWrm128,       0 },
1379     { X86::VPSIGNDrr128,      X86::VPSIGNDrm128,       0 },
1380     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1381     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1382     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1383     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1384     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1385     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1386     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1387     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1388     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1389     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1390     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1391     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1392     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1393     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1394     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1395     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1396     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1397     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1398     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1399     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1400     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1401     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1402     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1403     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1404     { X86::VPXORrr,           X86::VPXORrm,            0 },
1405     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1406     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1407     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1408     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1409     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1410     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1411     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1412     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1413     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1414     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1415     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1416     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1417     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1418     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1419     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1420     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1421 
1422     // AVX 256-bit foldable instructions
1423     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1424     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1425     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1426     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1427     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1428     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1429     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1430     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1431     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1432     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1433     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1434     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1435     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1436     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1437     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1438     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1439     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1440     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1441     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1442     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1443     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1444     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1445     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1446     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1447     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1448     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1449     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1450     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1451     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1452     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1453     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1454     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1455     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1456     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1457     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1458     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1459     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1460     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1461     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1462     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1463     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1464     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1465     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1466 
1467     // AVX2 foldable instructions
1468     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1469     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1470     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1471     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1472     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1473     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1474     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1475     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1476     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1477     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1478     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1479     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1480     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1481     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1482     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1483     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1484     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1485     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1486     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1487     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1488     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1489     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1490     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1491     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1492     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1493     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1494     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1495     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1496     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1497     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1498     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1499     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1500     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1501     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1502     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1503     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1504     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1505     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1506     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1507     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1508     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1509     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1510     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1511     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1512     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1513     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1514     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1515     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1516     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1517     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1518     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1519     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1520     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1521     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1522     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1523     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1524     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1525     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1526     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1527     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1528     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1529     { X86::VPORYrr,           X86::VPORYrm,            0 },
1530     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1531     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1532     { X86::VPSIGNBYrr256,     X86::VPSIGNBYrm256,      0 },
1533     { X86::VPSIGNWYrr256,     X86::VPSIGNWYrm256,      0 },
1534     { X86::VPSIGNDYrr256,     X86::VPSIGNDYrm256,      0 },
1535     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1536     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1537     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1538     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1539     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1540     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1541     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1542     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1543     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1544     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1545     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1546     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1547     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1548     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1549     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1550     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1551     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1552     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1553     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1554     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1555     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1556     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1557     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1558     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1559     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1560     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1561     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1562     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1563     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1564     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1565     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1566     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1567     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1568     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1569     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1570 
1571     // FMA4 foldable patterns
1572     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1573     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1574     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1575     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1576     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_NONE },
1577     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_NONE },
1578     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1579     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1580     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1581     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1582     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_NONE },
1583     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_NONE },
1584     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1585     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1586     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1587     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1588     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_NONE },
1589     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_NONE },
1590     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1591     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1592     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1593     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1594     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_NONE },
1595     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_NONE },
1596     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1597     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1598     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_NONE },
1599     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_NONE },
1600     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1601     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1602     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_NONE },
1603     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_NONE },
1604 
1605     // XOP foldable instructions
1606     { X86::VPCMOVrrr,         X86::VPCMOVrmr,           0 },
1607     { X86::VPCMOVrrrY,        X86::VPCMOVrmrY,          0 },
1608     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1609     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1610     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1611     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1612     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1613     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1614     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1615     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1616     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1617     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1618     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1619     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1620     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1621     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1622     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1623     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1624     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1625     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1626     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1627     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1628     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1629     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1630     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1631     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1632     { X86::VPPERMrrr,         X86::VPPERMrmr,           0 },
1633     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1634     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1635     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1636     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1637     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1638     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1639     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1640     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1641     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1642     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1643     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1644     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1645 
1646     // BMI/BMI2 foldable instructions
1647     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1648     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1649     { X86::MULX32rr,          X86::MULX32rm,            0 },
1650     { X86::MULX64rr,          X86::MULX64rm,            0 },
1651     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1652     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1653     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1654     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1655 
1656     // ADX foldable instructions
1657     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1658     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1659     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1660     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1661 
1662     // AVX-512 foldable instructions
1663     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1664     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1665     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1666     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1667     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1668     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1669     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1670     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1671     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1672     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1673     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1674     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1675     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1676     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1677     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1678     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1679     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1680     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1681     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1682     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1683     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1684     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1685     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1686     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1687     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1688     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1689     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1690     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1691     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1692     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1693     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1694     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1695     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1696     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1697     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1698     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1699     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1700     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1701     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1702 
1703     // AVX-512{F,VL} foldable instructions
1704     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1705     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1706     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1707 
1708     // AVX-512{F,VL} foldable instructions
1709     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1710     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1711     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1712     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1713 
1714     // AES foldable instructions
1715     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1716     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1717     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1718     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1719     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
1720     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
1721     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
1722     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
1723 
1724     // SHA foldable instructions
1725     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1726     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1727     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1728     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1729     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1730     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1731     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
1732   };
1733 
1734   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
1735     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1736                   Entry.RegOp, Entry.MemOp,
1737                   // Index 2, folded load
1738                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1739   }
1740 
1741   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1742     // FMA foldable instructions
1743     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1744     { X86::VFMADDSSr231r_Int,     X86::VFMADDSSr231m_Int,     TB_ALIGN_NONE },
1745     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1746     { X86::VFMADDSDr231r_Int,     X86::VFMADDSDr231m_Int,     TB_ALIGN_NONE },
1747     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1748     { X86::VFMADDSSr132r_Int,     X86::VFMADDSSr132m_Int,     TB_ALIGN_NONE },
1749     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1750     { X86::VFMADDSDr132r_Int,     X86::VFMADDSDr132m_Int,     TB_ALIGN_NONE },
1751     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1752     { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     TB_ALIGN_NONE },
1753     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1754     { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     TB_ALIGN_NONE },
1755 
1756     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1757     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1758     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1759     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1760     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1761     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1762     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1763     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1764     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1765     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1766     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1767     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1768 
1769     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1770     { X86::VFNMADDSSr231r_Int,    X86::VFNMADDSSr231m_Int,    TB_ALIGN_NONE },
1771     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1772     { X86::VFNMADDSDr231r_Int,    X86::VFNMADDSDr231m_Int,    TB_ALIGN_NONE },
1773     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1774     { X86::VFNMADDSSr132r_Int,    X86::VFNMADDSSr132m_Int,    TB_ALIGN_NONE },
1775     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1776     { X86::VFNMADDSDr132r_Int,    X86::VFNMADDSDr132m_Int,    TB_ALIGN_NONE },
1777     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1778     { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    TB_ALIGN_NONE },
1779     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1780     { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    TB_ALIGN_NONE },
1781 
1782     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1783     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1784     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1785     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1786     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1787     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1788     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1789     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1790     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1791     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1792     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1793     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1794 
1795     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1796     { X86::VFMSUBSSr231r_Int,     X86::VFMSUBSSr231m_Int,     TB_ALIGN_NONE },
1797     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1798     { X86::VFMSUBSDr231r_Int,     X86::VFMSUBSDr231m_Int,     TB_ALIGN_NONE },
1799     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1800     { X86::VFMSUBSSr132r_Int,     X86::VFMSUBSSr132m_Int,     TB_ALIGN_NONE },
1801     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1802     { X86::VFMSUBSDr132r_Int,     X86::VFMSUBSDr132m_Int,     TB_ALIGN_NONE },
1803     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1804     { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     TB_ALIGN_NONE },
1805     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1806     { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     TB_ALIGN_NONE },
1807 
1808     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1809     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1810     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1811     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1812     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1813     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1814     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1815     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1816     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1817     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1818     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1819     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1820 
1821     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1822     { X86::VFNMSUBSSr231r_Int,    X86::VFNMSUBSSr231m_Int,    TB_ALIGN_NONE },
1823     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1824     { X86::VFNMSUBSDr231r_Int,    X86::VFNMSUBSDr231m_Int,    TB_ALIGN_NONE },
1825     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1826     { X86::VFNMSUBSSr132r_Int,    X86::VFNMSUBSSr132m_Int,    TB_ALIGN_NONE },
1827     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1828     { X86::VFNMSUBSDr132r_Int,    X86::VFNMSUBSDr132m_Int,    TB_ALIGN_NONE },
1829     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1830     { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    TB_ALIGN_NONE },
1831     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1832     { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    TB_ALIGN_NONE },
1833 
1834     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1835     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1836     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1837     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1838     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1839     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1840     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1841     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1842     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1843     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1844     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1845     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1846 
1847     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1848     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1849     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1850     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1851     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1852     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1853     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1854     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1855     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1856     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1857     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1858     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1859 
1860     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1861     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1862     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1863     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1864     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1865     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1866     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1867     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1868     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1869     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1870     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1871     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1872 
1873     // FMA4 foldable patterns
1874     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
1875     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
1876     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
1877     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
1878     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_NONE },
1879     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_NONE },
1880     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
1881     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
1882     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
1883     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
1884     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_NONE },
1885     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_NONE },
1886     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
1887     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
1888     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
1889     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
1890     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_NONE },
1891     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_NONE },
1892     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
1893     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
1894     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
1895     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
1896     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_NONE },
1897     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_NONE },
1898     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
1899     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
1900     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_NONE },
1901     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_NONE },
1902     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
1903     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
1904     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_NONE },
1905     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_NONE },
1906 
1907     // XOP foldable instructions
1908     { X86::VPCMOVrrr,             X86::VPCMOVrrm,             0 },
1909     { X86::VPCMOVrrrY,            X86::VPCMOVrrmY,            0 },
1910     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
1911     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
1912     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
1913     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
1914     { X86::VPPERMrrr,             X86::VPPERMrrm,             0 },
1915 
1916     // AVX-512 VPERMI instructions with 3 source operands.
1917     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1918     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1919     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1920     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1921     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1922     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1923     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1924     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1925     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1926     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1927     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1928     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1929     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
1930      // AVX-512 arithmetic instructions
1931     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
1932     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
1933     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
1934     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
1935     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
1936     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
1937     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
1938     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
1939     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
1940     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
1941     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
1942     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
1943     // AVX-512{F,VL} arithmetic instructions 256-bit
1944     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
1945     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
1946     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
1947     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
1948     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
1949     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
1950     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
1951     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
1952     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
1953     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
1954     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
1955     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
1956     // AVX-512{F,VL} arithmetic instructions 128-bit
1957     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
1958     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
1959     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
1960     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
1961     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
1962     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
1963     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
1964     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
1965     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
1966     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
1967     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
1968     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
1969   };
1970 
1971   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
1972     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1973                   Entry.RegOp, Entry.MemOp,
1974                   // Index 3, folded load
1975                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1976   }
1977 
1978   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
1979      // AVX-512 foldable instructions
1980     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
1981     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
1982     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
1983     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
1984     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
1985     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
1986     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
1987     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
1988     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
1989     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
1990     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
1991     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
1992     // AVX-512{F,VL} foldable instructions 256-bit
1993     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
1994     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
1995     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
1996     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
1997     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
1998     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
1999     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
2000     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
2001     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
2002     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
2003     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
2004     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
2005     // AVX-512{F,VL} foldable instructions 128-bit
2006     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
2007     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
2008     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
2009     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
2010     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
2011     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
2012     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
2013     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
2014     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
2015     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
2016     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
2017     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
2018   };
2019 
2020   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
2021     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2022                   Entry.RegOp, Entry.MemOp,
2023                   // Index 4, folded load
2024                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
2025   }
2026 }
2027 
2028 void
2029 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2030                             MemOp2RegOpTableType &M2RTable,
2031                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
2032     if ((Flags & TB_NO_FORWARD) == 0) {
2033       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2034       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2035     }
2036     if ((Flags & TB_NO_REVERSE) == 0) {
2037       assert(!M2RTable.count(MemOp) &&
2038            "Duplicated entries in unfolding maps?");
2039       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2040     }
2041 }
2042 
2043 bool
2044 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2045                                     unsigned &SrcReg, unsigned &DstReg,
2046                                     unsigned &SubIdx) const {
2047   switch (MI.getOpcode()) {
2048   default: break;
2049   case X86::MOVSX16rr8:
2050   case X86::MOVZX16rr8:
2051   case X86::MOVSX32rr8:
2052   case X86::MOVZX32rr8:
2053   case X86::MOVSX64rr8:
2054     if (!Subtarget.is64Bit())
2055       // It's not always legal to reference the low 8-bit of the larger
2056       // register in 32-bit mode.
2057       return false;
2058   case X86::MOVSX32rr16:
2059   case X86::MOVZX32rr16:
2060   case X86::MOVSX64rr16:
2061   case X86::MOVSX64rr32: {
2062     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2063       // Be conservative.
2064       return false;
2065     SrcReg = MI.getOperand(1).getReg();
2066     DstReg = MI.getOperand(0).getReg();
2067     switch (MI.getOpcode()) {
2068     default: llvm_unreachable("Unreachable!");
2069     case X86::MOVSX16rr8:
2070     case X86::MOVZX16rr8:
2071     case X86::MOVSX32rr8:
2072     case X86::MOVZX32rr8:
2073     case X86::MOVSX64rr8:
2074       SubIdx = X86::sub_8bit;
2075       break;
2076     case X86::MOVSX32rr16:
2077     case X86::MOVZX32rr16:
2078     case X86::MOVSX64rr16:
2079       SubIdx = X86::sub_16bit;
2080       break;
2081     case X86::MOVSX64rr32:
2082       SubIdx = X86::sub_32bit;
2083       break;
2084     }
2085     return true;
2086   }
2087   }
2088   return false;
2089 }
2090 
2091 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
2092   const MachineFunction *MF = MI->getParent()->getParent();
2093   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2094 
2095   if (MI->getOpcode() == getCallFrameSetupOpcode() ||
2096       MI->getOpcode() == getCallFrameDestroyOpcode()) {
2097     unsigned StackAlign = TFI->getStackAlignment();
2098     int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
2099                  StackAlign;
2100 
2101     SPAdj -= MI->getOperand(1).getImm();
2102 
2103     if (MI->getOpcode() == getCallFrameSetupOpcode())
2104       return SPAdj;
2105     else
2106       return -SPAdj;
2107   }
2108 
2109   // To know whether a call adjusts the stack, we need information
2110   // that is bound to the following ADJCALLSTACKUP pseudo.
2111   // Look for the next ADJCALLSTACKUP that follows the call.
2112   if (MI->isCall()) {
2113     const MachineBasicBlock* MBB = MI->getParent();
2114     auto I = ++MachineBasicBlock::const_iterator(MI);
2115     for (auto E = MBB->end(); I != E; ++I) {
2116       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2117           I->isCall())
2118         break;
2119     }
2120 
2121     // If we could not find a frame destroy opcode, then it has already
2122     // been simplified, so we don't care.
2123     if (I->getOpcode() != getCallFrameDestroyOpcode())
2124       return 0;
2125 
2126     return -(I->getOperand(1).getImm());
2127   }
2128 
2129   // Currently handle only PUSHes we can reasonably expect to see
2130   // in call sequences
2131   switch (MI->getOpcode()) {
2132   default:
2133     return 0;
2134   case X86::PUSH32i8:
2135   case X86::PUSH32r:
2136   case X86::PUSH32rmm:
2137   case X86::PUSH32rmr:
2138   case X86::PUSHi32:
2139     return 4;
2140   }
2141 }
2142 
2143 /// Return true and the FrameIndex if the specified
2144 /// operand and follow operands form a reference to the stack frame.
2145 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2146                                   int &FrameIndex) const {
2147   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2148       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2149       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2150       MI->getOperand(Op+X86::AddrDisp).isImm() &&
2151       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2152       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2153       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2154     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
2155     return true;
2156   }
2157   return false;
2158 }
2159 
2160 static bool isFrameLoadOpcode(int Opcode) {
2161   switch (Opcode) {
2162   default:
2163     return false;
2164   case X86::MOV8rm:
2165   case X86::MOV16rm:
2166   case X86::MOV32rm:
2167   case X86::MOV64rm:
2168   case X86::LD_Fp64m:
2169   case X86::MOVSSrm:
2170   case X86::MOVSDrm:
2171   case X86::MOVAPSrm:
2172   case X86::MOVAPDrm:
2173   case X86::MOVDQArm:
2174   case X86::VMOVSSrm:
2175   case X86::VMOVSDrm:
2176   case X86::VMOVAPSrm:
2177   case X86::VMOVAPDrm:
2178   case X86::VMOVDQArm:
2179   case X86::VMOVUPSYrm:
2180   case X86::VMOVAPSYrm:
2181   case X86::VMOVUPDYrm:
2182   case X86::VMOVAPDYrm:
2183   case X86::VMOVDQUYrm:
2184   case X86::VMOVDQAYrm:
2185   case X86::MMX_MOVD64rm:
2186   case X86::MMX_MOVQ64rm:
2187   case X86::VMOVAPSZrm:
2188   case X86::VMOVUPSZrm:
2189     return true;
2190   }
2191 }
2192 
2193 static bool isFrameStoreOpcode(int Opcode) {
2194   switch (Opcode) {
2195   default: break;
2196   case X86::MOV8mr:
2197   case X86::MOV16mr:
2198   case X86::MOV32mr:
2199   case X86::MOV64mr:
2200   case X86::ST_FpP64m:
2201   case X86::MOVSSmr:
2202   case X86::MOVSDmr:
2203   case X86::MOVAPSmr:
2204   case X86::MOVAPDmr:
2205   case X86::MOVDQAmr:
2206   case X86::VMOVSSmr:
2207   case X86::VMOVSDmr:
2208   case X86::VMOVAPSmr:
2209   case X86::VMOVAPDmr:
2210   case X86::VMOVDQAmr:
2211   case X86::VMOVUPSYmr:
2212   case X86::VMOVAPSYmr:
2213   case X86::VMOVUPDYmr:
2214   case X86::VMOVAPDYmr:
2215   case X86::VMOVDQUYmr:
2216   case X86::VMOVDQAYmr:
2217   case X86::VMOVUPSZmr:
2218   case X86::VMOVAPSZmr:
2219   case X86::MMX_MOVD64mr:
2220   case X86::MMX_MOVQ64mr:
2221   case X86::MMX_MOVNTQmr:
2222     return true;
2223   }
2224   return false;
2225 }
2226 
2227 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
2228                                            int &FrameIndex) const {
2229   if (isFrameLoadOpcode(MI->getOpcode()))
2230     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2231       return MI->getOperand(0).getReg();
2232   return 0;
2233 }
2234 
2235 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
2236                                                  int &FrameIndex) const {
2237   if (isFrameLoadOpcode(MI->getOpcode())) {
2238     unsigned Reg;
2239     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2240       return Reg;
2241     // Check for post-frame index elimination operations
2242     const MachineMemOperand *Dummy;
2243     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2244   }
2245   return 0;
2246 }
2247 
2248 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
2249                                           int &FrameIndex) const {
2250   if (isFrameStoreOpcode(MI->getOpcode()))
2251     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2252         isFrameOperand(MI, 0, FrameIndex))
2253       return MI->getOperand(X86::AddrNumOperands).getReg();
2254   return 0;
2255 }
2256 
2257 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2258                                                 int &FrameIndex) const {
2259   if (isFrameStoreOpcode(MI->getOpcode())) {
2260     unsigned Reg;
2261     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2262       return Reg;
2263     // Check for post-frame index elimination operations
2264     const MachineMemOperand *Dummy;
2265     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2266   }
2267   return 0;
2268 }
2269 
2270 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2271 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2272   // Don't waste compile time scanning use-def chains of physregs.
2273   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2274     return false;
2275   bool isPICBase = false;
2276   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2277          E = MRI.def_instr_end(); I != E; ++I) {
2278     MachineInstr *DefMI = &*I;
2279     if (DefMI->getOpcode() != X86::MOVPC32r)
2280       return false;
2281     assert(!isPICBase && "More than one PIC base?");
2282     isPICBase = true;
2283   }
2284   return isPICBase;
2285 }
2286 
2287 bool
2288 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2289                                                 AliasAnalysis *AA) const {
2290   switch (MI->getOpcode()) {
2291   default: break;
2292   case X86::MOV8rm:
2293   case X86::MOV16rm:
2294   case X86::MOV32rm:
2295   case X86::MOV64rm:
2296   case X86::LD_Fp64m:
2297   case X86::MOVSSrm:
2298   case X86::MOVSDrm:
2299   case X86::MOVAPSrm:
2300   case X86::MOVUPSrm:
2301   case X86::MOVAPDrm:
2302   case X86::MOVDQArm:
2303   case X86::MOVDQUrm:
2304   case X86::VMOVSSrm:
2305   case X86::VMOVSDrm:
2306   case X86::VMOVAPSrm:
2307   case X86::VMOVUPSrm:
2308   case X86::VMOVAPDrm:
2309   case X86::VMOVDQArm:
2310   case X86::VMOVDQUrm:
2311   case X86::VMOVAPSYrm:
2312   case X86::VMOVUPSYrm:
2313   case X86::VMOVAPDYrm:
2314   case X86::VMOVDQAYrm:
2315   case X86::VMOVDQUYrm:
2316   case X86::MMX_MOVD64rm:
2317   case X86::MMX_MOVQ64rm:
2318   case X86::FsVMOVAPSrm:
2319   case X86::FsVMOVAPDrm:
2320   case X86::FsMOVAPSrm:
2321   case X86::FsMOVAPDrm:
2322   // AVX-512
2323   case X86::VMOVAPDZ128rm:
2324   case X86::VMOVAPDZ256rm:
2325   case X86::VMOVAPDZrm:
2326   case X86::VMOVAPSZ128rm:
2327   case X86::VMOVAPSZ256rm:
2328   case X86::VMOVAPSZrm:
2329   case X86::VMOVDQA32Z128rm:
2330   case X86::VMOVDQA32Z256rm:
2331   case X86::VMOVDQA32Zrm:
2332   case X86::VMOVDQA64Z128rm:
2333   case X86::VMOVDQA64Z256rm:
2334   case X86::VMOVDQA64Zrm:
2335   case X86::VMOVDQU16Z128rm:
2336   case X86::VMOVDQU16Z256rm:
2337   case X86::VMOVDQU16Zrm:
2338   case X86::VMOVDQU32Z128rm:
2339   case X86::VMOVDQU32Z256rm:
2340   case X86::VMOVDQU32Zrm:
2341   case X86::VMOVDQU64Z128rm:
2342   case X86::VMOVDQU64Z256rm:
2343   case X86::VMOVDQU64Zrm:
2344   case X86::VMOVDQU8Z128rm:
2345   case X86::VMOVDQU8Z256rm:
2346   case X86::VMOVDQU8Zrm:
2347   case X86::VMOVUPSZ128rm:
2348   case X86::VMOVUPSZ256rm:
2349   case X86::VMOVUPSZrm: {
2350     // Loads from constant pools are trivially rematerializable.
2351     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2352         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2353         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2354         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2355         MI->isInvariantLoad(AA)) {
2356       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2357       if (BaseReg == 0 || BaseReg == X86::RIP)
2358         return true;
2359       // Allow re-materialization of PIC load.
2360       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
2361         return false;
2362       const MachineFunction &MF = *MI->getParent()->getParent();
2363       const MachineRegisterInfo &MRI = MF.getRegInfo();
2364       return regIsPICBase(BaseReg, MRI);
2365     }
2366     return false;
2367   }
2368 
2369   case X86::LEA32r:
2370   case X86::LEA64r: {
2371     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2372         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2373         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2374         !MI->getOperand(1+X86::AddrDisp).isReg()) {
2375       // lea fi#, lea GV, etc. are all rematerializable.
2376       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
2377         return true;
2378       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2379       if (BaseReg == 0)
2380         return true;
2381       // Allow re-materialization of lea PICBase + x.
2382       const MachineFunction &MF = *MI->getParent()->getParent();
2383       const MachineRegisterInfo &MRI = MF.getRegInfo();
2384       return regIsPICBase(BaseReg, MRI);
2385     }
2386     return false;
2387   }
2388   }
2389 
2390   // All other instructions marked M_REMATERIALIZABLE are always trivially
2391   // rematerializable.
2392   return true;
2393 }
2394 
2395 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2396                                          MachineBasicBlock::iterator I) const {
2397   MachineBasicBlock::iterator E = MBB.end();
2398 
2399   // For compile time consideration, if we are not able to determine the
2400   // safety after visiting 4 instructions in each direction, we will assume
2401   // it's not safe.
2402   MachineBasicBlock::iterator Iter = I;
2403   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2404     bool SeenDef = false;
2405     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2406       MachineOperand &MO = Iter->getOperand(j);
2407       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2408         SeenDef = true;
2409       if (!MO.isReg())
2410         continue;
2411       if (MO.getReg() == X86::EFLAGS) {
2412         if (MO.isUse())
2413           return false;
2414         SeenDef = true;
2415       }
2416     }
2417 
2418     if (SeenDef)
2419       // This instruction defines EFLAGS, no need to look any further.
2420       return true;
2421     ++Iter;
2422     // Skip over DBG_VALUE.
2423     while (Iter != E && Iter->isDebugValue())
2424       ++Iter;
2425   }
2426 
2427   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2428   // live in.
2429   if (Iter == E) {
2430     for (MachineBasicBlock *S : MBB.successors())
2431       if (S->isLiveIn(X86::EFLAGS))
2432         return false;
2433     return true;
2434   }
2435 
2436   MachineBasicBlock::iterator B = MBB.begin();
2437   Iter = I;
2438   for (unsigned i = 0; i < 4; ++i) {
2439     // If we make it to the beginning of the block, it's safe to clobber
2440     // EFLAGS iff EFLAGS is not live-in.
2441     if (Iter == B)
2442       return !MBB.isLiveIn(X86::EFLAGS);
2443 
2444     --Iter;
2445     // Skip over DBG_VALUE.
2446     while (Iter != B && Iter->isDebugValue())
2447       --Iter;
2448 
2449     bool SawKill = false;
2450     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2451       MachineOperand &MO = Iter->getOperand(j);
2452       // A register mask may clobber EFLAGS, but we should still look for a
2453       // live EFLAGS def.
2454       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2455         SawKill = true;
2456       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2457         if (MO.isDef()) return MO.isDead();
2458         if (MO.isKill()) SawKill = true;
2459       }
2460     }
2461 
2462     if (SawKill)
2463       // This instruction kills EFLAGS and doesn't redefine it, so
2464       // there's no need to look further.
2465       return true;
2466   }
2467 
2468   // Conservative answer.
2469   return false;
2470 }
2471 
2472 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2473                                  MachineBasicBlock::iterator I,
2474                                  unsigned DestReg, unsigned SubIdx,
2475                                  const MachineInstr *Orig,
2476                                  const TargetRegisterInfo &TRI) const {
2477   bool ClobbersEFLAGS = false;
2478   for (const MachineOperand &MO : Orig->operands()) {
2479     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2480       ClobbersEFLAGS = true;
2481       break;
2482     }
2483   }
2484 
2485   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2486     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2487     // effects.
2488     int Value;
2489     switch (Orig->getOpcode()) {
2490     case X86::MOV32r0:  Value = 0; break;
2491     case X86::MOV32r1:  Value = 1; break;
2492     case X86::MOV32r_1: Value = -1; break;
2493     default:
2494       llvm_unreachable("Unexpected instruction!");
2495     }
2496 
2497     DebugLoc DL = Orig->getDebugLoc();
2498     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2499       .addImm(Value);
2500   } else {
2501     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2502     MBB.insert(I, MI);
2503   }
2504 
2505   MachineInstr *NewMI = std::prev(I);
2506   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2507 }
2508 
2509 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2510 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr *MI) const {
2511   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2512     MachineOperand &MO = MI->getOperand(i);
2513     if (MO.isReg() && MO.isDef() &&
2514         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2515       return true;
2516     }
2517   }
2518   return false;
2519 }
2520 
2521 /// Check whether the shift count for a machine operand is non-zero.
2522 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2523                                               unsigned ShiftAmtOperandIdx) {
2524   // The shift count is six bits with the REX.W prefix and five bits without.
2525   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2526   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2527   return Imm & ShiftCountMask;
2528 }
2529 
2530 /// Check whether the given shift count is appropriate
2531 /// can be represented by a LEA instruction.
2532 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2533   // Left shift instructions can be transformed into load-effective-address
2534   // instructions if we can encode them appropriately.
2535   // A LEA instruction utilizes a SIB byte to encode its scale factor.
2536   // The SIB.scale field is two bits wide which means that we can encode any
2537   // shift amount less than 4.
2538   return ShAmt < 4 && ShAmt > 0;
2539 }
2540 
2541 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2542                                   unsigned Opc, bool AllowSP,
2543                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
2544                                   MachineOperand &ImplicitOp) const {
2545   MachineFunction &MF = *MI->getParent()->getParent();
2546   const TargetRegisterClass *RC;
2547   if (AllowSP) {
2548     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2549   } else {
2550     RC = Opc != X86::LEA32r ?
2551       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2552   }
2553   unsigned SrcReg = Src.getReg();
2554 
2555   // For both LEA64 and LEA32 the register already has essentially the right
2556   // type (32-bit or 64-bit) we may just need to forbid SP.
2557   if (Opc != X86::LEA64_32r) {
2558     NewSrc = SrcReg;
2559     isKill = Src.isKill();
2560     isUndef = Src.isUndef();
2561 
2562     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2563         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2564       return false;
2565 
2566     return true;
2567   }
2568 
2569   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2570   // another we need to add 64-bit registers to the final MI.
2571   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2572     ImplicitOp = Src;
2573     ImplicitOp.setImplicit();
2574 
2575     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
2576     MachineBasicBlock::LivenessQueryResult LQR =
2577       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2578 
2579     switch (LQR) {
2580     case MachineBasicBlock::LQR_Unknown:
2581       // We can't give sane liveness flags to the instruction, abandon LEA
2582       // formation.
2583       return false;
2584     case MachineBasicBlock::LQR_Live:
2585       isKill = MI->killsRegister(SrcReg);
2586       isUndef = false;
2587       break;
2588     default:
2589       // The physreg itself is dead, so we have to use it as an <undef>.
2590       isKill = false;
2591       isUndef = true;
2592       break;
2593     }
2594   } else {
2595     // Virtual register of the wrong class, we have to create a temporary 64-bit
2596     // vreg to feed into the LEA.
2597     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2598     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2599             get(TargetOpcode::COPY))
2600       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2601         .addOperand(Src);
2602 
2603     // Which is obviously going to be dead after we're done with it.
2604     isKill = true;
2605     isUndef = false;
2606   }
2607 
2608   // We've set all the parameters without issue.
2609   return true;
2610 }
2611 
2612 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2613 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2614 /// truncating back down to a 16-bit subregister.
2615 MachineInstr *
2616 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2617                                            MachineFunction::iterator &MFI,
2618                                            MachineBasicBlock::iterator &MBBI,
2619                                            LiveVariables *LV) const {
2620   MachineInstr *MI = MBBI;
2621   unsigned Dest = MI->getOperand(0).getReg();
2622   unsigned Src = MI->getOperand(1).getReg();
2623   bool isDead = MI->getOperand(0).isDead();
2624   bool isKill = MI->getOperand(1).isKill();
2625 
2626   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2627   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2628   unsigned Opc, leaInReg;
2629   if (Subtarget.is64Bit()) {
2630     Opc = X86::LEA64_32r;
2631     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2632   } else {
2633     Opc = X86::LEA32r;
2634     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2635   }
2636 
2637   // Build and insert into an implicit UNDEF value. This is OK because
2638   // well be shifting and then extracting the lower 16-bits.
2639   // This has the potential to cause partial register stall. e.g.
2640   //   movw    (%rbp,%rcx,2), %dx
2641   //   leal    -65(%rdx), %esi
2642   // But testing has shown this *does* help performance in 64-bit mode (at
2643   // least on modern x86 machines).
2644   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2645   MachineInstr *InsMI =
2646     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2647     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2648     .addReg(Src, getKillRegState(isKill));
2649 
2650   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2651                                     get(Opc), leaOutReg);
2652   switch (MIOpc) {
2653   default: llvm_unreachable("Unreachable!");
2654   case X86::SHL16ri: {
2655     unsigned ShAmt = MI->getOperand(2).getImm();
2656     MIB.addReg(0).addImm(1ULL << ShAmt)
2657        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2658     break;
2659   }
2660   case X86::INC16r:
2661     addRegOffset(MIB, leaInReg, true, 1);
2662     break;
2663   case X86::DEC16r:
2664     addRegOffset(MIB, leaInReg, true, -1);
2665     break;
2666   case X86::ADD16ri:
2667   case X86::ADD16ri8:
2668   case X86::ADD16ri_DB:
2669   case X86::ADD16ri8_DB:
2670     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2671     break;
2672   case X86::ADD16rr:
2673   case X86::ADD16rr_DB: {
2674     unsigned Src2 = MI->getOperand(2).getReg();
2675     bool isKill2 = MI->getOperand(2).isKill();
2676     unsigned leaInReg2 = 0;
2677     MachineInstr *InsMI2 = nullptr;
2678     if (Src == Src2) {
2679       // ADD16rr %reg1028<kill>, %reg1028
2680       // just a single insert_subreg.
2681       addRegReg(MIB, leaInReg, true, leaInReg, false);
2682     } else {
2683       if (Subtarget.is64Bit())
2684         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2685       else
2686         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2687       // Build and insert into an implicit UNDEF value. This is OK because
2688       // well be shifting and then extracting the lower 16-bits.
2689       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2690       InsMI2 =
2691         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2692         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2693         .addReg(Src2, getKillRegState(isKill2));
2694       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2695     }
2696     if (LV && isKill2 && InsMI2)
2697       LV->replaceKillInstruction(Src2, MI, InsMI2);
2698     break;
2699   }
2700   }
2701 
2702   MachineInstr *NewMI = MIB;
2703   MachineInstr *ExtMI =
2704     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2705     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2706     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2707 
2708   if (LV) {
2709     // Update live variables
2710     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2711     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2712     if (isKill)
2713       LV->replaceKillInstruction(Src, MI, InsMI);
2714     if (isDead)
2715       LV->replaceKillInstruction(Dest, MI, ExtMI);
2716   }
2717 
2718   return ExtMI;
2719 }
2720 
2721 /// This method must be implemented by targets that
2722 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2723 /// may be able to convert a two-address instruction into a true
2724 /// three-address instruction on demand.  This allows the X86 target (for
2725 /// example) to convert ADD and SHL instructions into LEA instructions if they
2726 /// would require register copies due to two-addressness.
2727 ///
2728 /// This method returns a null pointer if the transformation cannot be
2729 /// performed, otherwise it returns the new instruction.
2730 ///
2731 MachineInstr *
2732 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2733                                     MachineBasicBlock::iterator &MBBI,
2734                                     LiveVariables *LV) const {
2735   MachineInstr *MI = MBBI;
2736 
2737   // The following opcodes also sets the condition code register(s). Only
2738   // convert them to equivalent lea if the condition code register def's
2739   // are dead!
2740   if (hasLiveCondCodeDef(MI))
2741     return nullptr;
2742 
2743   MachineFunction &MF = *MI->getParent()->getParent();
2744   // All instructions input are two-addr instructions.  Get the known operands.
2745   const MachineOperand &Dest = MI->getOperand(0);
2746   const MachineOperand &Src = MI->getOperand(1);
2747 
2748   MachineInstr *NewMI = nullptr;
2749   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2750   // we have better subtarget support, enable the 16-bit LEA generation here.
2751   // 16-bit LEA is also slow on Core2.
2752   bool DisableLEA16 = true;
2753   bool is64Bit = Subtarget.is64Bit();
2754 
2755   unsigned MIOpc = MI->getOpcode();
2756   switch (MIOpc) {
2757   default: return nullptr;
2758   case X86::SHL64ri: {
2759     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2760     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2761     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2762 
2763     // LEA can't handle RSP.
2764     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2765         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2766                                            &X86::GR64_NOSPRegClass))
2767       return nullptr;
2768 
2769     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2770       .addOperand(Dest)
2771       .addReg(0).addImm(1ULL << ShAmt).addOperand(Src).addImm(0).addReg(0);
2772     break;
2773   }
2774   case X86::SHL32ri: {
2775     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2776     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2777     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2778 
2779     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2780 
2781     // LEA can't handle ESP.
2782     bool isKill, isUndef;
2783     unsigned SrcReg;
2784     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2785     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2786                         SrcReg, isKill, isUndef, ImplicitOp))
2787       return nullptr;
2788 
2789     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2790       .addOperand(Dest)
2791       .addReg(0).addImm(1ULL << ShAmt)
2792       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2793       .addImm(0).addReg(0);
2794     if (ImplicitOp.getReg() != 0)
2795       MIB.addOperand(ImplicitOp);
2796     NewMI = MIB;
2797 
2798     break;
2799   }
2800   case X86::SHL16ri: {
2801     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2802     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2803     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2804 
2805     if (DisableLEA16)
2806       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2807     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2808       .addOperand(Dest)
2809       .addReg(0).addImm(1ULL << ShAmt).addOperand(Src).addImm(0).addReg(0);
2810     break;
2811   }
2812   case X86::INC64r:
2813   case X86::INC32r: {
2814     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2815     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2816       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2817     bool isKill, isUndef;
2818     unsigned SrcReg;
2819     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2820     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2821                         SrcReg, isKill, isUndef, ImplicitOp))
2822       return nullptr;
2823 
2824     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2825         .addOperand(Dest)
2826         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2827     if (ImplicitOp.getReg() != 0)
2828       MIB.addOperand(ImplicitOp);
2829 
2830     NewMI = addOffset(MIB, 1);
2831     break;
2832   }
2833   case X86::INC16r:
2834     if (DisableLEA16)
2835       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2836                      : nullptr;
2837     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2838     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2839                       .addOperand(Dest).addOperand(Src), 1);
2840     break;
2841   case X86::DEC64r:
2842   case X86::DEC32r: {
2843     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2844     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2845       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2846 
2847     bool isKill, isUndef;
2848     unsigned SrcReg;
2849     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2850     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2851                         SrcReg, isKill, isUndef, ImplicitOp))
2852       return nullptr;
2853 
2854     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2855         .addOperand(Dest)
2856         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2857     if (ImplicitOp.getReg() != 0)
2858       MIB.addOperand(ImplicitOp);
2859 
2860     NewMI = addOffset(MIB, -1);
2861 
2862     break;
2863   }
2864   case X86::DEC16r:
2865     if (DisableLEA16)
2866       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2867                      : nullptr;
2868     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2869     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2870                       .addOperand(Dest).addOperand(Src), -1);
2871     break;
2872   case X86::ADD64rr:
2873   case X86::ADD64rr_DB:
2874   case X86::ADD32rr:
2875   case X86::ADD32rr_DB: {
2876     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2877     unsigned Opc;
2878     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2879       Opc = X86::LEA64r;
2880     else
2881       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2882 
2883     bool isKill, isUndef;
2884     unsigned SrcReg;
2885     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2886     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2887                         SrcReg, isKill, isUndef, ImplicitOp))
2888       return nullptr;
2889 
2890     const MachineOperand &Src2 = MI->getOperand(2);
2891     bool isKill2, isUndef2;
2892     unsigned SrcReg2;
2893     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2894     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2895                         SrcReg2, isKill2, isUndef2, ImplicitOp2))
2896       return nullptr;
2897 
2898     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2899       .addOperand(Dest);
2900     if (ImplicitOp.getReg() != 0)
2901       MIB.addOperand(ImplicitOp);
2902     if (ImplicitOp2.getReg() != 0)
2903       MIB.addOperand(ImplicitOp2);
2904 
2905     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2906 
2907     // Preserve undefness of the operands.
2908     NewMI->getOperand(1).setIsUndef(isUndef);
2909     NewMI->getOperand(3).setIsUndef(isUndef2);
2910 
2911     if (LV && Src2.isKill())
2912       LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2913     break;
2914   }
2915   case X86::ADD16rr:
2916   case X86::ADD16rr_DB: {
2917     if (DisableLEA16)
2918       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2919                      : nullptr;
2920     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2921     unsigned Src2 = MI->getOperand(2).getReg();
2922     bool isKill2 = MI->getOperand(2).isKill();
2923     NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2924                       .addOperand(Dest),
2925                       Src.getReg(), Src.isKill(), Src2, isKill2);
2926 
2927     // Preserve undefness of the operands.
2928     bool isUndef = MI->getOperand(1).isUndef();
2929     bool isUndef2 = MI->getOperand(2).isUndef();
2930     NewMI->getOperand(1).setIsUndef(isUndef);
2931     NewMI->getOperand(3).setIsUndef(isUndef2);
2932 
2933     if (LV && isKill2)
2934       LV->replaceKillInstruction(Src2, MI, NewMI);
2935     break;
2936   }
2937   case X86::ADD64ri32:
2938   case X86::ADD64ri8:
2939   case X86::ADD64ri32_DB:
2940   case X86::ADD64ri8_DB:
2941     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2942     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2943                       .addOperand(Dest).addOperand(Src),
2944                       MI->getOperand(2).getImm());
2945     break;
2946   case X86::ADD32ri:
2947   case X86::ADD32ri8:
2948   case X86::ADD32ri_DB:
2949   case X86::ADD32ri8_DB: {
2950     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2951     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2952 
2953     bool isKill, isUndef;
2954     unsigned SrcReg;
2955     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2956     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2957                         SrcReg, isKill, isUndef, ImplicitOp))
2958       return nullptr;
2959 
2960     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2961         .addOperand(Dest)
2962         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2963     if (ImplicitOp.getReg() != 0)
2964       MIB.addOperand(ImplicitOp);
2965 
2966     NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2967     break;
2968   }
2969   case X86::ADD16ri:
2970   case X86::ADD16ri8:
2971   case X86::ADD16ri_DB:
2972   case X86::ADD16ri8_DB:
2973     if (DisableLEA16)
2974       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2975                      : nullptr;
2976     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2977     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2978                       .addOperand(Dest).addOperand(Src),
2979                       MI->getOperand(2).getImm());
2980     break;
2981   }
2982 
2983   if (!NewMI) return nullptr;
2984 
2985   if (LV) {  // Update live variables
2986     if (Src.isKill())
2987       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2988     if (Dest.isDead())
2989       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2990   }
2991 
2992   MFI->insert(MBBI, NewMI);          // Insert the new inst
2993   return NewMI;
2994 }
2995 
2996 /// Returns true if the given instruction opcode is FMA3.
2997 /// Otherwise, returns false.
2998 /// The second parameter is optional and is used as the second return from
2999 /// the function. It is set to true if the given instruction has FMA3 opcode
3000 /// that is used for lowering of scalar FMA intrinsics, and it is set to false
3001 /// otherwise.
3002 static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
3003   if (IsIntrinsic)
3004     *IsIntrinsic = false;
3005 
3006   switch (Opcode) {
3007     case X86::VFMADDSDr132r:      case X86::VFMADDSDr132m:
3008     case X86::VFMADDSSr132r:      case X86::VFMADDSSr132m:
3009     case X86::VFMSUBSDr132r:      case X86::VFMSUBSDr132m:
3010     case X86::VFMSUBSSr132r:      case X86::VFMSUBSSr132m:
3011     case X86::VFNMADDSDr132r:     case X86::VFNMADDSDr132m:
3012     case X86::VFNMADDSSr132r:     case X86::VFNMADDSSr132m:
3013     case X86::VFNMSUBSDr132r:     case X86::VFNMSUBSDr132m:
3014     case X86::VFNMSUBSSr132r:     case X86::VFNMSUBSSr132m:
3015 
3016     case X86::VFMADDSDr213r:      case X86::VFMADDSDr213m:
3017     case X86::VFMADDSSr213r:      case X86::VFMADDSSr213m:
3018     case X86::VFMSUBSDr213r:      case X86::VFMSUBSDr213m:
3019     case X86::VFMSUBSSr213r:      case X86::VFMSUBSSr213m:
3020     case X86::VFNMADDSDr213r:     case X86::VFNMADDSDr213m:
3021     case X86::VFNMADDSSr213r:     case X86::VFNMADDSSr213m:
3022     case X86::VFNMSUBSDr213r:     case X86::VFNMSUBSDr213m:
3023     case X86::VFNMSUBSSr213r:     case X86::VFNMSUBSSr213m:
3024 
3025     case X86::VFMADDSDr231r:      case X86::VFMADDSDr231m:
3026     case X86::VFMADDSSr231r:      case X86::VFMADDSSr231m:
3027     case X86::VFMSUBSDr231r:      case X86::VFMSUBSDr231m:
3028     case X86::VFMSUBSSr231r:      case X86::VFMSUBSSr231m:
3029     case X86::VFNMADDSDr231r:     case X86::VFNMADDSDr231m:
3030     case X86::VFNMADDSSr231r:     case X86::VFNMADDSSr231m:
3031     case X86::VFNMSUBSDr231r:     case X86::VFNMSUBSDr231m:
3032     case X86::VFNMSUBSSr231r:     case X86::VFNMSUBSSr231m:
3033 
3034     case X86::VFMADDSUBPDr132r:   case X86::VFMADDSUBPDr132m:
3035     case X86::VFMADDSUBPSr132r:   case X86::VFMADDSUBPSr132m:
3036     case X86::VFMSUBADDPDr132r:   case X86::VFMSUBADDPDr132m:
3037     case X86::VFMSUBADDPSr132r:   case X86::VFMSUBADDPSr132m:
3038     case X86::VFMADDSUBPDr132rY:  case X86::VFMADDSUBPDr132mY:
3039     case X86::VFMADDSUBPSr132rY:  case X86::VFMADDSUBPSr132mY:
3040     case X86::VFMSUBADDPDr132rY:  case X86::VFMSUBADDPDr132mY:
3041     case X86::VFMSUBADDPSr132rY:  case X86::VFMSUBADDPSr132mY:
3042 
3043     case X86::VFMADDPDr132r:      case X86::VFMADDPDr132m:
3044     case X86::VFMADDPSr132r:      case X86::VFMADDPSr132m:
3045     case X86::VFMSUBPDr132r:      case X86::VFMSUBPDr132m:
3046     case X86::VFMSUBPSr132r:      case X86::VFMSUBPSr132m:
3047     case X86::VFNMADDPDr132r:     case X86::VFNMADDPDr132m:
3048     case X86::VFNMADDPSr132r:     case X86::VFNMADDPSr132m:
3049     case X86::VFNMSUBPDr132r:     case X86::VFNMSUBPDr132m:
3050     case X86::VFNMSUBPSr132r:     case X86::VFNMSUBPSr132m:
3051     case X86::VFMADDPDr132rY:     case X86::VFMADDPDr132mY:
3052     case X86::VFMADDPSr132rY:     case X86::VFMADDPSr132mY:
3053     case X86::VFMSUBPDr132rY:     case X86::VFMSUBPDr132mY:
3054     case X86::VFMSUBPSr132rY:     case X86::VFMSUBPSr132mY:
3055     case X86::VFNMADDPDr132rY:    case X86::VFNMADDPDr132mY:
3056     case X86::VFNMADDPSr132rY:    case X86::VFNMADDPSr132mY:
3057     case X86::VFNMSUBPDr132rY:    case X86::VFNMSUBPDr132mY:
3058     case X86::VFNMSUBPSr132rY:    case X86::VFNMSUBPSr132mY:
3059 
3060     case X86::VFMADDSUBPDr213r:   case X86::VFMADDSUBPDr213m:
3061     case X86::VFMADDSUBPSr213r:   case X86::VFMADDSUBPSr213m:
3062     case X86::VFMSUBADDPDr213r:   case X86::VFMSUBADDPDr213m:
3063     case X86::VFMSUBADDPSr213r:   case X86::VFMSUBADDPSr213m:
3064     case X86::VFMADDSUBPDr213rY:  case X86::VFMADDSUBPDr213mY:
3065     case X86::VFMADDSUBPSr213rY:  case X86::VFMADDSUBPSr213mY:
3066     case X86::VFMSUBADDPDr213rY:  case X86::VFMSUBADDPDr213mY:
3067     case X86::VFMSUBADDPSr213rY:  case X86::VFMSUBADDPSr213mY:
3068 
3069     case X86::VFMADDPDr213r:      case X86::VFMADDPDr213m:
3070     case X86::VFMADDPSr213r:      case X86::VFMADDPSr213m:
3071     case X86::VFMSUBPDr213r:      case X86::VFMSUBPDr213m:
3072     case X86::VFMSUBPSr213r:      case X86::VFMSUBPSr213m:
3073     case X86::VFNMADDPDr213r:     case X86::VFNMADDPDr213m:
3074     case X86::VFNMADDPSr213r:     case X86::VFNMADDPSr213m:
3075     case X86::VFNMSUBPDr213r:     case X86::VFNMSUBPDr213m:
3076     case X86::VFNMSUBPSr213r:     case X86::VFNMSUBPSr213m:
3077     case X86::VFMADDPDr213rY:     case X86::VFMADDPDr213mY:
3078     case X86::VFMADDPSr213rY:     case X86::VFMADDPSr213mY:
3079     case X86::VFMSUBPDr213rY:     case X86::VFMSUBPDr213mY:
3080     case X86::VFMSUBPSr213rY:     case X86::VFMSUBPSr213mY:
3081     case X86::VFNMADDPDr213rY:    case X86::VFNMADDPDr213mY:
3082     case X86::VFNMADDPSr213rY:    case X86::VFNMADDPSr213mY:
3083     case X86::VFNMSUBPDr213rY:    case X86::VFNMSUBPDr213mY:
3084     case X86::VFNMSUBPSr213rY:    case X86::VFNMSUBPSr213mY:
3085 
3086     case X86::VFMADDSUBPDr231r:   case X86::VFMADDSUBPDr231m:
3087     case X86::VFMADDSUBPSr231r:   case X86::VFMADDSUBPSr231m:
3088     case X86::VFMSUBADDPDr231r:   case X86::VFMSUBADDPDr231m:
3089     case X86::VFMSUBADDPSr231r:   case X86::VFMSUBADDPSr231m:
3090     case X86::VFMADDSUBPDr231rY:  case X86::VFMADDSUBPDr231mY:
3091     case X86::VFMADDSUBPSr231rY:  case X86::VFMADDSUBPSr231mY:
3092     case X86::VFMSUBADDPDr231rY:  case X86::VFMSUBADDPDr231mY:
3093     case X86::VFMSUBADDPSr231rY:  case X86::VFMSUBADDPSr231mY:
3094 
3095     case X86::VFMADDPDr231r:      case X86::VFMADDPDr231m:
3096     case X86::VFMADDPSr231r:      case X86::VFMADDPSr231m:
3097     case X86::VFMSUBPDr231r:      case X86::VFMSUBPDr231m:
3098     case X86::VFMSUBPSr231r:      case X86::VFMSUBPSr231m:
3099     case X86::VFNMADDPDr231r:     case X86::VFNMADDPDr231m:
3100     case X86::VFNMADDPSr231r:     case X86::VFNMADDPSr231m:
3101     case X86::VFNMSUBPDr231r:     case X86::VFNMSUBPDr231m:
3102     case X86::VFNMSUBPSr231r:     case X86::VFNMSUBPSr231m:
3103     case X86::VFMADDPDr231rY:     case X86::VFMADDPDr231mY:
3104     case X86::VFMADDPSr231rY:     case X86::VFMADDPSr231mY:
3105     case X86::VFMSUBPDr231rY:     case X86::VFMSUBPDr231mY:
3106     case X86::VFMSUBPSr231rY:     case X86::VFMSUBPSr231mY:
3107     case X86::VFNMADDPDr231rY:    case X86::VFNMADDPDr231mY:
3108     case X86::VFNMADDPSr231rY:    case X86::VFNMADDPSr231mY:
3109     case X86::VFNMSUBPDr231rY:    case X86::VFNMSUBPDr231mY:
3110     case X86::VFNMSUBPSr231rY:    case X86::VFNMSUBPSr231mY:
3111       return true;
3112 
3113     case X86::VFMADDSDr132r_Int:  case X86::VFMADDSDr132m_Int:
3114     case X86::VFMADDSSr132r_Int:  case X86::VFMADDSSr132m_Int:
3115     case X86::VFMSUBSDr132r_Int:  case X86::VFMSUBSDr132m_Int:
3116     case X86::VFMSUBSSr132r_Int:  case X86::VFMSUBSSr132m_Int:
3117     case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int:
3118     case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int:
3119     case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int:
3120     case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int:
3121 
3122     case X86::VFMADDSDr213r_Int:  case X86::VFMADDSDr213m_Int:
3123     case X86::VFMADDSSr213r_Int:  case X86::VFMADDSSr213m_Int:
3124     case X86::VFMSUBSDr213r_Int:  case X86::VFMSUBSDr213m_Int:
3125     case X86::VFMSUBSSr213r_Int:  case X86::VFMSUBSSr213m_Int:
3126     case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int:
3127     case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int:
3128     case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int:
3129     case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int:
3130 
3131     case X86::VFMADDSDr231r_Int:  case X86::VFMADDSDr231m_Int:
3132     case X86::VFMADDSSr231r_Int:  case X86::VFMADDSSr231m_Int:
3133     case X86::VFMSUBSDr231r_Int:  case X86::VFMSUBSDr231m_Int:
3134     case X86::VFMSUBSSr231r_Int:  case X86::VFMSUBSSr231m_Int:
3135     case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int:
3136     case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
3137     case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
3138     case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
3139       if (IsIntrinsic)
3140         *IsIntrinsic = true;
3141       return true;
3142     default:
3143       return false;
3144   }
3145   llvm_unreachable("Opcode not handled by the switch");
3146 }
3147 
3148 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr *MI,
3149                                                    bool NewMI,
3150                                                    unsigned OpIdx1,
3151                                                    unsigned OpIdx2) const {
3152   switch (MI->getOpcode()) {
3153   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3154   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
3155   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
3156   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3157   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3158   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
3159     unsigned Opc;
3160     unsigned Size;
3161     switch (MI->getOpcode()) {
3162     default: llvm_unreachable("Unreachable!");
3163     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3164     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3165     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3166     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
3167     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3168     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
3169     }
3170     unsigned Amt = MI->getOperand(3).getImm();
3171     if (NewMI) {
3172       MachineFunction &MF = *MI->getParent()->getParent();
3173       MI = MF.CloneMachineInstr(MI);
3174       NewMI = false;
3175     }
3176     MI->setDesc(get(Opc));
3177     MI->getOperand(3).setImm(Size-Amt);
3178     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3179   }
3180   case X86::BLENDPDrri:
3181   case X86::BLENDPSrri:
3182   case X86::PBLENDWrri:
3183   case X86::VBLENDPDrri:
3184   case X86::VBLENDPSrri:
3185   case X86::VBLENDPDYrri:
3186   case X86::VBLENDPSYrri:
3187   case X86::VPBLENDDrri:
3188   case X86::VPBLENDWrri:
3189   case X86::VPBLENDDYrri:
3190   case X86::VPBLENDWYrri:{
3191     unsigned Mask;
3192     switch (MI->getOpcode()) {
3193     default: llvm_unreachable("Unreachable!");
3194     case X86::BLENDPDrri:    Mask = 0x03; break;
3195     case X86::BLENDPSrri:    Mask = 0x0F; break;
3196     case X86::PBLENDWrri:    Mask = 0xFF; break;
3197     case X86::VBLENDPDrri:   Mask = 0x03; break;
3198     case X86::VBLENDPSrri:   Mask = 0x0F; break;
3199     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
3200     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
3201     case X86::VPBLENDDrri:   Mask = 0x0F; break;
3202     case X86::VPBLENDWrri:   Mask = 0xFF; break;
3203     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
3204     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
3205     }
3206     // Only the least significant bits of Imm are used.
3207     unsigned Imm = MI->getOperand(3).getImm() & Mask;
3208     if (NewMI) {
3209       MachineFunction &MF = *MI->getParent()->getParent();
3210       MI = MF.CloneMachineInstr(MI);
3211       NewMI = false;
3212     }
3213     MI->getOperand(3).setImm(Mask ^ Imm);
3214     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3215   }
3216   case X86::PCLMULQDQrr:
3217   case X86::VPCLMULQDQrr:{
3218     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3219     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3220     unsigned Imm = MI->getOperand(3).getImm();
3221     unsigned Src1Hi = Imm & 0x01;
3222     unsigned Src2Hi = Imm & 0x10;
3223     if (NewMI) {
3224       MachineFunction &MF = *MI->getParent()->getParent();
3225       MI = MF.CloneMachineInstr(MI);
3226       NewMI = false;
3227     }
3228     MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3229     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3230   }
3231   case X86::CMPPDrri:
3232   case X86::CMPPSrri:
3233   case X86::VCMPPDrri:
3234   case X86::VCMPPSrri:
3235   case X86::VCMPPDYrri:
3236   case X86::VCMPPSYrri: {
3237     // Float comparison can be safely commuted for
3238     // Ordered/Unordered/Equal/NotEqual tests
3239     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3240     switch (Imm) {
3241     case 0x00: // EQUAL
3242     case 0x03: // UNORDERED
3243     case 0x04: // NOT EQUAL
3244     case 0x07: // ORDERED
3245       if (NewMI) {
3246         MachineFunction &MF = *MI->getParent()->getParent();
3247         MI = MF.CloneMachineInstr(MI);
3248         NewMI = false;
3249       }
3250       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3251     default:
3252       return nullptr;
3253     }
3254   }
3255   case X86::VPCOMBri: case X86::VPCOMUBri:
3256   case X86::VPCOMDri: case X86::VPCOMUDri:
3257   case X86::VPCOMQri: case X86::VPCOMUQri:
3258   case X86::VPCOMWri: case X86::VPCOMUWri: {
3259     // Flip comparison mode immediate (if necessary).
3260     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3261     switch (Imm) {
3262     case 0x00: Imm = 0x02; break; // LT -> GT
3263     case 0x01: Imm = 0x03; break; // LE -> GE
3264     case 0x02: Imm = 0x00; break; // GT -> LT
3265     case 0x03: Imm = 0x01; break; // GE -> LE
3266     case 0x04: // EQ
3267     case 0x05: // NE
3268     case 0x06: // FALSE
3269     case 0x07: // TRUE
3270     default:
3271       break;
3272     }
3273     if (NewMI) {
3274       MachineFunction &MF = *MI->getParent()->getParent();
3275       MI = MF.CloneMachineInstr(MI);
3276       NewMI = false;
3277     }
3278     MI->getOperand(3).setImm(Imm);
3279     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3280   }
3281   case X86::VPERM2F128rr:
3282   case X86::VPERM2I128rr: {
3283     // Flip permute source immediate.
3284     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3285     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
3286     unsigned Imm = MI->getOperand(3).getImm() & 0xFF;
3287     if (NewMI) {
3288       MachineFunction &MF = *MI->getParent()->getParent();
3289       MI = MF.CloneMachineInstr(MI);
3290       NewMI = false;
3291     }
3292     MI->getOperand(3).setImm(Imm ^ 0x22);
3293     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3294   }
3295   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
3296   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3297   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
3298   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3299   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3300   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
3301   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
3302   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3303   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3304   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
3305   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
3306   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3307   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
3308   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3309   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
3310   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3311     unsigned Opc;
3312     switch (MI->getOpcode()) {
3313     default: llvm_unreachable("Unreachable!");
3314     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
3315     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
3316     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
3317     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3318     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3319     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3320     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
3321     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
3322     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
3323     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3324     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3325     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
3326     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3327     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3328     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3329     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
3330     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
3331     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
3332     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
3333     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
3334     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
3335     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3336     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3337     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3338     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3339     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3340     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3341     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
3342     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
3343     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
3344     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
3345     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
3346     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
3347     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3348     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3349     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3350     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
3351     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
3352     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
3353     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3354     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3355     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3356     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
3357     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
3358     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
3359     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3360     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3361     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3362     }
3363     if (NewMI) {
3364       MachineFunction &MF = *MI->getParent()->getParent();
3365       MI = MF.CloneMachineInstr(MI);
3366       NewMI = false;
3367     }
3368     MI->setDesc(get(Opc));
3369     // Fallthrough intended.
3370   }
3371   default:
3372     if (isFMA3(MI->getOpcode())) {
3373       unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
3374       if (Opc == 0)
3375         return nullptr;
3376       if (NewMI) {
3377         MachineFunction &MF = *MI->getParent()->getParent();
3378         MI = MF.CloneMachineInstr(MI);
3379         NewMI = false;
3380       }
3381       MI->setDesc(get(Opc));
3382     }
3383     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3384   }
3385 }
3386 
3387 bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr *MI,
3388                                              unsigned &SrcOpIdx1,
3389                                              unsigned &SrcOpIdx2) const {
3390 
3391   unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3392 
3393   // Only the first RegOpsNum operands are commutable.
3394   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3395   // that the operand is not specified/fixed.
3396   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3397       (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3398     return false;
3399   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3400       (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3401     return false;
3402 
3403   // Look for two different register operands assumed to be commutable
3404   // regardless of the FMA opcode. The FMA opcode is adjusted later.
3405   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3406       SrcOpIdx2 == CommuteAnyOperandIndex) {
3407     unsigned CommutableOpIdx1 = SrcOpIdx1;
3408     unsigned CommutableOpIdx2 = SrcOpIdx2;
3409 
3410     // At least one of operands to be commuted is not specified and
3411     // this method is free to choose appropriate commutable operands.
3412     if (SrcOpIdx1 == SrcOpIdx2)
3413       // Both of operands are not fixed. By default set one of commutable
3414       // operands to the last register operand of the instruction.
3415       CommutableOpIdx2 = RegOpsNum;
3416     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3417       // Only one of operands is not fixed.
3418       CommutableOpIdx2 = SrcOpIdx1;
3419 
3420     // CommutableOpIdx2 is well defined now. Let's choose another commutable
3421     // operand and assign its index to CommutableOpIdx1.
3422     unsigned Op2Reg = MI->getOperand(CommutableOpIdx2).getReg();
3423     for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3424       // The commuted operands must have different registers.
3425       // Otherwise, the commute transformation does not change anything and
3426       // is useless then.
3427       if (Op2Reg != MI->getOperand(CommutableOpIdx1).getReg())
3428         break;
3429     }
3430 
3431     // No appropriate commutable operands were found.
3432     if (CommutableOpIdx1 == 0)
3433       return false;
3434 
3435     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3436     // to return those values.
3437     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3438                               CommutableOpIdx1, CommutableOpIdx2))
3439       return false;
3440   }
3441 
3442   // Check if we can adjust the opcode to preserve the semantics when
3443   // commute the register operands.
3444   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
3445 }
3446 
3447 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(MachineInstr *MI,
3448                                                       unsigned SrcOpIdx1,
3449                                                       unsigned SrcOpIdx2) const {
3450   unsigned Opc = MI->getOpcode();
3451 
3452   // Define the array that holds FMA opcodes in groups
3453   // of 3 opcodes(132, 213, 231) in each group.
3454   static const uint16_t RegularOpcodeGroups[][3] = {
3455     { X86::VFMADDSSr132r,   X86::VFMADDSSr213r,   X86::VFMADDSSr231r  },
3456     { X86::VFMADDSDr132r,   X86::VFMADDSDr213r,   X86::VFMADDSDr231r  },
3457     { X86::VFMADDPSr132r,   X86::VFMADDPSr213r,   X86::VFMADDPSr231r  },
3458     { X86::VFMADDPDr132r,   X86::VFMADDPDr213r,   X86::VFMADDPDr231r  },
3459     { X86::VFMADDPSr132rY,  X86::VFMADDPSr213rY,  X86::VFMADDPSr231rY },
3460     { X86::VFMADDPDr132rY,  X86::VFMADDPDr213rY,  X86::VFMADDPDr231rY },
3461     { X86::VFMADDSSr132m,   X86::VFMADDSSr213m,   X86::VFMADDSSr231m  },
3462     { X86::VFMADDSDr132m,   X86::VFMADDSDr213m,   X86::VFMADDSDr231m  },
3463     { X86::VFMADDPSr132m,   X86::VFMADDPSr213m,   X86::VFMADDPSr231m  },
3464     { X86::VFMADDPDr132m,   X86::VFMADDPDr213m,   X86::VFMADDPDr231m  },
3465     { X86::VFMADDPSr132mY,  X86::VFMADDPSr213mY,  X86::VFMADDPSr231mY },
3466     { X86::VFMADDPDr132mY,  X86::VFMADDPDr213mY,  X86::VFMADDPDr231mY },
3467 
3468     { X86::VFMSUBSSr132r,   X86::VFMSUBSSr213r,   X86::VFMSUBSSr231r  },
3469     { X86::VFMSUBSDr132r,   X86::VFMSUBSDr213r,   X86::VFMSUBSDr231r  },
3470     { X86::VFMSUBPSr132r,   X86::VFMSUBPSr213r,   X86::VFMSUBPSr231r  },
3471     { X86::VFMSUBPDr132r,   X86::VFMSUBPDr213r,   X86::VFMSUBPDr231r  },
3472     { X86::VFMSUBPSr132rY,  X86::VFMSUBPSr213rY,  X86::VFMSUBPSr231rY },
3473     { X86::VFMSUBPDr132rY,  X86::VFMSUBPDr213rY,  X86::VFMSUBPDr231rY },
3474     { X86::VFMSUBSSr132m,   X86::VFMSUBSSr213m,   X86::VFMSUBSSr231m  },
3475     { X86::VFMSUBSDr132m,   X86::VFMSUBSDr213m,   X86::VFMSUBSDr231m  },
3476     { X86::VFMSUBPSr132m,   X86::VFMSUBPSr213m,   X86::VFMSUBPSr231m  },
3477     { X86::VFMSUBPDr132m,   X86::VFMSUBPDr213m,   X86::VFMSUBPDr231m  },
3478     { X86::VFMSUBPSr132mY,  X86::VFMSUBPSr213mY,  X86::VFMSUBPSr231mY },
3479     { X86::VFMSUBPDr132mY,  X86::VFMSUBPDr213mY,  X86::VFMSUBPDr231mY },
3480 
3481     { X86::VFNMADDSSr132r,  X86::VFNMADDSSr213r,  X86::VFNMADDSSr231r  },
3482     { X86::VFNMADDSDr132r,  X86::VFNMADDSDr213r,  X86::VFNMADDSDr231r  },
3483     { X86::VFNMADDPSr132r,  X86::VFNMADDPSr213r,  X86::VFNMADDPSr231r  },
3484     { X86::VFNMADDPDr132r,  X86::VFNMADDPDr213r,  X86::VFNMADDPDr231r  },
3485     { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
3486     { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
3487     { X86::VFNMADDSSr132m,  X86::VFNMADDSSr213m,  X86::VFNMADDSSr231m  },
3488     { X86::VFNMADDSDr132m,  X86::VFNMADDSDr213m,  X86::VFNMADDSDr231m  },
3489     { X86::VFNMADDPSr132m,  X86::VFNMADDPSr213m,  X86::VFNMADDPSr231m  },
3490     { X86::VFNMADDPDr132m,  X86::VFNMADDPDr213m,  X86::VFNMADDPDr231m  },
3491     { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
3492     { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
3493 
3494     { X86::VFNMSUBSSr132r,  X86::VFNMSUBSSr213r,  X86::VFNMSUBSSr231r  },
3495     { X86::VFNMSUBSDr132r,  X86::VFNMSUBSDr213r,  X86::VFNMSUBSDr231r  },
3496     { X86::VFNMSUBPSr132r,  X86::VFNMSUBPSr213r,  X86::VFNMSUBPSr231r  },
3497     { X86::VFNMSUBPDr132r,  X86::VFNMSUBPDr213r,  X86::VFNMSUBPDr231r  },
3498     { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
3499     { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
3500     { X86::VFNMSUBSSr132m,  X86::VFNMSUBSSr213m,  X86::VFNMSUBSSr231m  },
3501     { X86::VFNMSUBSDr132m,  X86::VFNMSUBSDr213m,  X86::VFNMSUBSDr231m  },
3502     { X86::VFNMSUBPSr132m,  X86::VFNMSUBPSr213m,  X86::VFNMSUBPSr231m  },
3503     { X86::VFNMSUBPDr132m,  X86::VFNMSUBPDr213m,  X86::VFNMSUBPDr231m  },
3504     { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
3505     { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
3506 
3507     { X86::VFMADDSUBPSr132r,  X86::VFMADDSUBPSr213r,  X86::VFMADDSUBPSr231r  },
3508     { X86::VFMADDSUBPDr132r,  X86::VFMADDSUBPDr213r,  X86::VFMADDSUBPDr231r  },
3509     { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
3510     { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
3511     { X86::VFMADDSUBPSr132m,  X86::VFMADDSUBPSr213m,  X86::VFMADDSUBPSr231m  },
3512     { X86::VFMADDSUBPDr132m,  X86::VFMADDSUBPDr213m,  X86::VFMADDSUBPDr231m  },
3513     { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
3514     { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
3515 
3516     { X86::VFMSUBADDPSr132r,  X86::VFMSUBADDPSr213r,  X86::VFMSUBADDPSr231r  },
3517     { X86::VFMSUBADDPDr132r,  X86::VFMSUBADDPDr213r,  X86::VFMSUBADDPDr231r  },
3518     { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
3519     { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
3520     { X86::VFMSUBADDPSr132m,  X86::VFMSUBADDPSr213m,  X86::VFMSUBADDPSr231m  },
3521     { X86::VFMSUBADDPDr132m,  X86::VFMSUBADDPDr213m,  X86::VFMSUBADDPDr231m  },
3522     { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
3523     { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
3524   };
3525 
3526   // Define the array that holds FMA*_Int opcodes in groups
3527   // of 3 opcodes(132, 213, 231) in each group.
3528   static const uint16_t IntrinOpcodeGroups[][3] = {
3529     { X86::VFMADDSSr132r_Int,  X86::VFMADDSSr213r_Int,  X86::VFMADDSSr231r_Int },
3530     { X86::VFMADDSDr132r_Int,  X86::VFMADDSDr213r_Int,  X86::VFMADDSDr231r_Int },
3531     { X86::VFMADDSSr132m_Int,  X86::VFMADDSSr213m_Int,  X86::VFMADDSSr231m_Int },
3532     { X86::VFMADDSDr132m_Int,  X86::VFMADDSDr213m_Int,  X86::VFMADDSDr231m_Int },
3533 
3534     { X86::VFMSUBSSr132r_Int,  X86::VFMSUBSSr213r_Int,  X86::VFMSUBSSr231r_Int },
3535     { X86::VFMSUBSDr132r_Int,  X86::VFMSUBSDr213r_Int,  X86::VFMSUBSDr231r_Int },
3536     { X86::VFMSUBSSr132m_Int,  X86::VFMSUBSSr213m_Int,  X86::VFMSUBSSr231m_Int },
3537     { X86::VFMSUBSDr132m_Int,  X86::VFMSUBSDr213m_Int,  X86::VFMSUBSDr231m_Int },
3538 
3539     { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
3540     { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
3541     { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
3542     { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
3543 
3544     { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
3545     { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
3546     { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
3547     { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
3548   };
3549 
3550   const unsigned Form132Index = 0;
3551   const unsigned Form213Index = 1;
3552   const unsigned Form231Index = 2;
3553   const unsigned FormsNum = 3;
3554 
3555   bool IsIntrinOpcode;
3556   isFMA3(Opc, &IsIntrinOpcode);
3557 
3558   size_t GroupsNum;
3559   const uint16_t (*OpcodeGroups)[3];
3560   if (IsIntrinOpcode) {
3561     GroupsNum = array_lengthof(IntrinOpcodeGroups);
3562     OpcodeGroups = IntrinOpcodeGroups;
3563   } else {
3564     GroupsNum = array_lengthof(RegularOpcodeGroups);
3565     OpcodeGroups = RegularOpcodeGroups;
3566   }
3567 
3568   const uint16_t *FoundOpcodesGroup = nullptr;
3569   size_t FormIndex;
3570 
3571   // Look for the input opcode in the corresponding opcodes table.
3572   for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
3573          ++GroupIndex) {
3574     for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
3575       if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
3576         FoundOpcodesGroup = OpcodeGroups[GroupIndex];
3577         break;
3578       }
3579     }
3580   }
3581 
3582   // The input opcode does not match with any of the opcodes from the tables.
3583   // The unsupported FMA opcode must be added to one of the two opcode groups
3584   // defined above.
3585   assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
3586 
3587   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3588   if (SrcOpIdx1 > SrcOpIdx2)
3589     std::swap(SrcOpIdx1, SrcOpIdx2);
3590 
3591   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3592   // analysis. The commute optimization is legal only if all users of FMA*_Int
3593   // use only the lowest element of the FMA*_Int instruction. Such analysis are
3594   // not implemented yet. So, just return 0 in that case.
3595   // When such analysis are available this place will be the right place for
3596   // calling it.
3597   if (IsIntrinOpcode && SrcOpIdx1 == 1)
3598     return 0;
3599 
3600   unsigned Case;
3601   if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
3602     Case = 0;
3603   else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3604     Case = 1;
3605   else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3606     Case = 2;
3607   else
3608     return 0;
3609 
3610   // Define the FMA forms mapping array that helps to map input FMA form
3611   // to output FMA form to preserve the operation semantics after
3612   // commuting the operands.
3613   static const unsigned FormMapping[][3] = {
3614     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3615     // FMA132 A, C, b; ==> FMA231 C, A, b;
3616     // FMA213 B, A, c; ==> FMA213 A, B, c;
3617     // FMA231 C, A, b; ==> FMA132 A, C, b;
3618     { Form231Index, Form213Index, Form132Index },
3619     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3620     // FMA132 A, c, B; ==> FMA132 B, c, A;
3621     // FMA213 B, a, C; ==> FMA231 C, a, B;
3622     // FMA231 C, a, B; ==> FMA213 B, a, C;
3623     { Form132Index, Form231Index, Form213Index },
3624     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3625     // FMA132 a, C, B; ==> FMA213 a, B, C;
3626     // FMA213 b, A, C; ==> FMA132 b, C, A;
3627     // FMA231 c, A, B; ==> FMA231 c, B, A;
3628     { Form213Index, Form132Index, Form231Index }
3629   };
3630 
3631   // Everything is ready, just adjust the FMA opcode and return it.
3632   FormIndex = FormMapping[Case][FormIndex];
3633   return FoundOpcodesGroup[FormIndex];
3634 }
3635 
3636 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI,
3637                                          unsigned &SrcOpIdx1,
3638                                          unsigned &SrcOpIdx2) const {
3639   switch (MI->getOpcode()) {
3640     case X86::CMPPDrri:
3641     case X86::CMPPSrri:
3642     case X86::VCMPPDrri:
3643     case X86::VCMPPSrri:
3644     case X86::VCMPPDYrri:
3645     case X86::VCMPPSYrri: {
3646       // Float comparison can be safely commuted for
3647       // Ordered/Unordered/Equal/NotEqual tests
3648       unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3649       switch (Imm) {
3650         case 0x00: // EQUAL
3651         case 0x03: // UNORDERED
3652         case 0x04: // NOT EQUAL
3653         case 0x07: // ORDERED
3654           // The indices of the commutable operands are 1 and 2.
3655           // Assign them to the returned operand indices here.
3656           return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
3657       }
3658       return false;
3659     }
3660     default:
3661       if (isFMA3(MI->getOpcode()))
3662         return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3663       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3664   }
3665   return false;
3666 }
3667 
3668 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
3669   switch (BrOpc) {
3670   default: return X86::COND_INVALID;
3671   case X86::JE_1:  return X86::COND_E;
3672   case X86::JNE_1: return X86::COND_NE;
3673   case X86::JL_1:  return X86::COND_L;
3674   case X86::JLE_1: return X86::COND_LE;
3675   case X86::JG_1:  return X86::COND_G;
3676   case X86::JGE_1: return X86::COND_GE;
3677   case X86::JB_1:  return X86::COND_B;
3678   case X86::JBE_1: return X86::COND_BE;
3679   case X86::JA_1:  return X86::COND_A;
3680   case X86::JAE_1: return X86::COND_AE;
3681   case X86::JS_1:  return X86::COND_S;
3682   case X86::JNS_1: return X86::COND_NS;
3683   case X86::JP_1:  return X86::COND_P;
3684   case X86::JNP_1: return X86::COND_NP;
3685   case X86::JO_1:  return X86::COND_O;
3686   case X86::JNO_1: return X86::COND_NO;
3687   }
3688 }
3689 
3690 /// Return condition code of a SET opcode.
3691 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3692   switch (Opc) {
3693   default: return X86::COND_INVALID;
3694   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
3695   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3696   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
3697   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3698   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
3699   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
3700   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3701   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
3702   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3703   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3704   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3705   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3706   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3707   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
3708   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
3709   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
3710   }
3711 }
3712 
3713 /// Return condition code of a CMov opcode.
3714 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
3715   switch (Opc) {
3716   default: return X86::COND_INVALID;
3717   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
3718   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
3719     return X86::COND_A;
3720   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3721   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3722     return X86::COND_AE;
3723   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
3724   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
3725     return X86::COND_B;
3726   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3727   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3728     return X86::COND_BE;
3729   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
3730   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
3731     return X86::COND_E;
3732   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
3733   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
3734     return X86::COND_G;
3735   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3736   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3737     return X86::COND_GE;
3738   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
3739   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
3740     return X86::COND_L;
3741   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3742   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3743     return X86::COND_LE;
3744   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3745   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3746     return X86::COND_NE;
3747   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3748   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3749     return X86::COND_NO;
3750   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3751   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3752     return X86::COND_NP;
3753   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3754   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3755     return X86::COND_NS;
3756   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
3757   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
3758     return X86::COND_O;
3759   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
3760   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
3761     return X86::COND_P;
3762   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
3763   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
3764     return X86::COND_S;
3765   }
3766 }
3767 
3768 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3769   switch (CC) {
3770   default: llvm_unreachable("Illegal condition code!");
3771   case X86::COND_E:  return X86::JE_1;
3772   case X86::COND_NE: return X86::JNE_1;
3773   case X86::COND_L:  return X86::JL_1;
3774   case X86::COND_LE: return X86::JLE_1;
3775   case X86::COND_G:  return X86::JG_1;
3776   case X86::COND_GE: return X86::JGE_1;
3777   case X86::COND_B:  return X86::JB_1;
3778   case X86::COND_BE: return X86::JBE_1;
3779   case X86::COND_A:  return X86::JA_1;
3780   case X86::COND_AE: return X86::JAE_1;
3781   case X86::COND_S:  return X86::JS_1;
3782   case X86::COND_NS: return X86::JNS_1;
3783   case X86::COND_P:  return X86::JP_1;
3784   case X86::COND_NP: return X86::JNP_1;
3785   case X86::COND_O:  return X86::JO_1;
3786   case X86::COND_NO: return X86::JNO_1;
3787   }
3788 }
3789 
3790 /// Return the inverse of the specified condition,
3791 /// e.g. turning COND_E to COND_NE.
3792 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3793   switch (CC) {
3794   default: llvm_unreachable("Illegal condition code!");
3795   case X86::COND_E:  return X86::COND_NE;
3796   case X86::COND_NE: return X86::COND_E;
3797   case X86::COND_L:  return X86::COND_GE;
3798   case X86::COND_LE: return X86::COND_G;
3799   case X86::COND_G:  return X86::COND_LE;
3800   case X86::COND_GE: return X86::COND_L;
3801   case X86::COND_B:  return X86::COND_AE;
3802   case X86::COND_BE: return X86::COND_A;
3803   case X86::COND_A:  return X86::COND_BE;
3804   case X86::COND_AE: return X86::COND_B;
3805   case X86::COND_S:  return X86::COND_NS;
3806   case X86::COND_NS: return X86::COND_S;
3807   case X86::COND_P:  return X86::COND_NP;
3808   case X86::COND_NP: return X86::COND_P;
3809   case X86::COND_O:  return X86::COND_NO;
3810   case X86::COND_NO: return X86::COND_O;
3811   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
3812   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
3813   }
3814 }
3815 
3816 /// Assuming the flags are set by MI(a,b), return the condition code if we
3817 /// modify the instructions such that flags are set by MI(b,a).
3818 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3819   switch (CC) {
3820   default: return X86::COND_INVALID;
3821   case X86::COND_E:  return X86::COND_E;
3822   case X86::COND_NE: return X86::COND_NE;
3823   case X86::COND_L:  return X86::COND_G;
3824   case X86::COND_LE: return X86::COND_GE;
3825   case X86::COND_G:  return X86::COND_L;
3826   case X86::COND_GE: return X86::COND_LE;
3827   case X86::COND_B:  return X86::COND_A;
3828   case X86::COND_BE: return X86::COND_AE;
3829   case X86::COND_A:  return X86::COND_B;
3830   case X86::COND_AE: return X86::COND_BE;
3831   }
3832 }
3833 
3834 /// Return a set opcode for the given condition and
3835 /// whether it has memory operand.
3836 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
3837   static const uint16_t Opc[16][2] = {
3838     { X86::SETAr,  X86::SETAm  },
3839     { X86::SETAEr, X86::SETAEm },
3840     { X86::SETBr,  X86::SETBm  },
3841     { X86::SETBEr, X86::SETBEm },
3842     { X86::SETEr,  X86::SETEm  },
3843     { X86::SETGr,  X86::SETGm  },
3844     { X86::SETGEr, X86::SETGEm },
3845     { X86::SETLr,  X86::SETLm  },
3846     { X86::SETLEr, X86::SETLEm },
3847     { X86::SETNEr, X86::SETNEm },
3848     { X86::SETNOr, X86::SETNOm },
3849     { X86::SETNPr, X86::SETNPm },
3850     { X86::SETNSr, X86::SETNSm },
3851     { X86::SETOr,  X86::SETOm  },
3852     { X86::SETPr,  X86::SETPm  },
3853     { X86::SETSr,  X86::SETSm  }
3854   };
3855 
3856   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
3857   return Opc[CC][HasMemoryOperand ? 1 : 0];
3858 }
3859 
3860 /// Return a cmov opcode for the given condition,
3861 /// register size in bytes, and operand type.
3862 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3863                               bool HasMemoryOperand) {
3864   static const uint16_t Opc[32][3] = {
3865     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
3866     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3867     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
3868     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3869     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
3870     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
3871     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3872     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
3873     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3874     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3875     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3876     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3877     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3878     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
3879     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
3880     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
3881     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
3882     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3883     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
3884     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3885     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
3886     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
3887     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3888     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
3889     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3890     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3891     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3892     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3893     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3894     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
3895     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
3896     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
3897   };
3898 
3899   assert(CC < 16 && "Can only handle standard cond codes");
3900   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
3901   switch(RegBytes) {
3902   default: llvm_unreachable("Illegal register size!");
3903   case 2: return Opc[Idx][0];
3904   case 4: return Opc[Idx][1];
3905   case 8: return Opc[Idx][2];
3906   }
3907 }
3908 
3909 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
3910   if (!MI.isTerminator()) return false;
3911 
3912   // Conditional branch is a special case.
3913   if (MI.isBranch() && !MI.isBarrier())
3914     return true;
3915   if (!MI.isPredicable())
3916     return true;
3917   return !isPredicated(MI);
3918 }
3919 
3920 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may not
3921 // be a fallthorough MBB now due to layout changes). Return nullptr if the
3922 // fallthough MBB cannot be identified.
3923 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3924                                             MachineBasicBlock *TBB) {
3925   MachineBasicBlock *FallthroughBB = nullptr;
3926   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
3927     if ((*SI)->isEHPad() || *SI == TBB)
3928       continue;
3929     // Return a nullptr if we found more than one fallthrough successor.
3930     if (FallthroughBB)
3931       return nullptr;
3932     FallthroughBB = *SI;
3933   }
3934   return FallthroughBB;
3935 }
3936 
3937 bool X86InstrInfo::AnalyzeBranchImpl(
3938     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3939     SmallVectorImpl<MachineOperand> &Cond,
3940     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3941 
3942   // Start from the bottom of the block and work up, examining the
3943   // terminator instructions.
3944   MachineBasicBlock::iterator I = MBB.end();
3945   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3946   while (I != MBB.begin()) {
3947     --I;
3948     if (I->isDebugValue())
3949       continue;
3950 
3951     // Working from the bottom, when we see a non-terminator instruction, we're
3952     // done.
3953     if (!isUnpredicatedTerminator(*I))
3954       break;
3955 
3956     // A terminator that isn't a branch can't easily be handled by this
3957     // analysis.
3958     if (!I->isBranch())
3959       return true;
3960 
3961     // Handle unconditional branches.
3962     if (I->getOpcode() == X86::JMP_1) {
3963       UnCondBrIter = I;
3964 
3965       if (!AllowModify) {
3966         TBB = I->getOperand(0).getMBB();
3967         continue;
3968       }
3969 
3970       // If the block has any instructions after a JMP, delete them.
3971       while (std::next(I) != MBB.end())
3972         std::next(I)->eraseFromParent();
3973 
3974       Cond.clear();
3975       FBB = nullptr;
3976 
3977       // Delete the JMP if it's equivalent to a fall-through.
3978       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3979         TBB = nullptr;
3980         I->eraseFromParent();
3981         I = MBB.end();
3982         UnCondBrIter = MBB.end();
3983         continue;
3984       }
3985 
3986       // TBB is used to indicate the unconditional destination.
3987       TBB = I->getOperand(0).getMBB();
3988       continue;
3989     }
3990 
3991     // Handle conditional branches.
3992     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
3993     if (BranchCode == X86::COND_INVALID)
3994       return true;  // Can't handle indirect branch.
3995 
3996     // Working from the bottom, handle the first conditional branch.
3997     if (Cond.empty()) {
3998       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3999       if (AllowModify && UnCondBrIter != MBB.end() &&
4000           MBB.isLayoutSuccessor(TargetBB)) {
4001         // If we can modify the code and it ends in something like:
4002         //
4003         //     jCC L1
4004         //     jmp L2
4005         //   L1:
4006         //     ...
4007         //   L2:
4008         //
4009         // Then we can change this to:
4010         //
4011         //     jnCC L2
4012         //   L1:
4013         //     ...
4014         //   L2:
4015         //
4016         // Which is a bit more efficient.
4017         // We conditionally jump to the fall-through block.
4018         BranchCode = GetOppositeBranchCondition(BranchCode);
4019         unsigned JNCC = GetCondBranchFromCond(BranchCode);
4020         MachineBasicBlock::iterator OldInst = I;
4021 
4022         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
4023           .addMBB(UnCondBrIter->getOperand(0).getMBB());
4024         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
4025           .addMBB(TargetBB);
4026 
4027         OldInst->eraseFromParent();
4028         UnCondBrIter->eraseFromParent();
4029 
4030         // Restart the analysis.
4031         UnCondBrIter = MBB.end();
4032         I = MBB.end();
4033         continue;
4034       }
4035 
4036       FBB = TBB;
4037       TBB = I->getOperand(0).getMBB();
4038       Cond.push_back(MachineOperand::CreateImm(BranchCode));
4039       CondBranches.push_back(I);
4040       continue;
4041     }
4042 
4043     // Handle subsequent conditional branches. Only handle the case where all
4044     // conditional branches branch to the same destination and their condition
4045     // opcodes fit one of the special multi-branch idioms.
4046     assert(Cond.size() == 1);
4047     assert(TBB);
4048 
4049     // If the conditions are the same, we can leave them alone.
4050     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
4051     auto NewTBB = I->getOperand(0).getMBB();
4052     if (OldBranchCode == BranchCode && TBB == NewTBB)
4053       continue;
4054 
4055     // If they differ, see if they fit one of the known patterns. Theoretically,
4056     // we could handle more patterns here, but we shouldn't expect to see them
4057     // if instruction selection has done a reasonable job.
4058     if (TBB == NewTBB &&
4059                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4060                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
4061       BranchCode = X86::COND_NE_OR_P;
4062     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4063                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4064       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4065         return true;
4066 
4067       // X86::COND_E_AND_NP usually has two different branch destinations.
4068       //
4069       // JP B1
4070       // JE B2
4071       // JMP B1
4072       // B1:
4073       // B2:
4074       //
4075       // Here this condition branches to B2 only if NP && E. It has another
4076       // equivalent form:
4077       //
4078       // JNE B1
4079       // JNP B2
4080       // JMP B1
4081       // B1:
4082       // B2:
4083       //
4084       // Similarly it branches to B2 only if E && NP. That is why this condition
4085       // is named with COND_E_AND_NP.
4086       BranchCode = X86::COND_E_AND_NP;
4087     } else
4088       return true;
4089 
4090     // Update the MachineOperand.
4091     Cond[0].setImm(BranchCode);
4092     CondBranches.push_back(I);
4093   }
4094 
4095   return false;
4096 }
4097 
4098 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
4099                                  MachineBasicBlock *&TBB,
4100                                  MachineBasicBlock *&FBB,
4101                                  SmallVectorImpl<MachineOperand> &Cond,
4102                                  bool AllowModify) const {
4103   SmallVector<MachineInstr *, 4> CondBranches;
4104   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4105 }
4106 
4107 bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB,
4108                                           MachineBranchPredicate &MBP,
4109                                           bool AllowModify) const {
4110   using namespace std::placeholders;
4111 
4112   SmallVector<MachineOperand, 4> Cond;
4113   SmallVector<MachineInstr *, 4> CondBranches;
4114   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4115                         AllowModify))
4116     return true;
4117 
4118   if (Cond.size() != 1)
4119     return true;
4120 
4121   assert(MBP.TrueDest && "expected!");
4122 
4123   if (!MBP.FalseDest)
4124     MBP.FalseDest = MBB.getNextNode();
4125 
4126   const TargetRegisterInfo *TRI = &getRegisterInfo();
4127 
4128   MachineInstr *ConditionDef = nullptr;
4129   bool SingleUseCondition = true;
4130 
4131   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4132     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4133       ConditionDef = &*I;
4134       break;
4135     }
4136 
4137     if (I->readsRegister(X86::EFLAGS, TRI))
4138       SingleUseCondition = false;
4139   }
4140 
4141   if (!ConditionDef)
4142     return true;
4143 
4144   if (SingleUseCondition) {
4145     for (auto *Succ : MBB.successors())
4146       if (Succ->isLiveIn(X86::EFLAGS))
4147         SingleUseCondition = false;
4148   }
4149 
4150   MBP.ConditionDef = ConditionDef;
4151   MBP.SingleUseCondition = SingleUseCondition;
4152 
4153   // Currently we only recognize the simple pattern:
4154   //
4155   //   test %reg, %reg
4156   //   je %label
4157   //
4158   const unsigned TestOpcode =
4159       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4160 
4161   if (ConditionDef->getOpcode() == TestOpcode &&
4162       ConditionDef->getNumOperands() == 3 &&
4163       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4164       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4165     MBP.LHS = ConditionDef->getOperand(0);
4166     MBP.RHS = MachineOperand::CreateImm(0);
4167     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4168                         ? MachineBranchPredicate::PRED_NE
4169                         : MachineBranchPredicate::PRED_EQ;
4170     return false;
4171   }
4172 
4173   return true;
4174 }
4175 
4176 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
4177   MachineBasicBlock::iterator I = MBB.end();
4178   unsigned Count = 0;
4179 
4180   while (I != MBB.begin()) {
4181     --I;
4182     if (I->isDebugValue())
4183       continue;
4184     if (I->getOpcode() != X86::JMP_1 &&
4185         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
4186       break;
4187     // Remove the branch.
4188     I->eraseFromParent();
4189     I = MBB.end();
4190     ++Count;
4191   }
4192 
4193   return Count;
4194 }
4195 
4196 unsigned
4197 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
4198                            MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
4199                            DebugLoc DL) const {
4200   // Shouldn't be a fall through.
4201   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
4202   assert((Cond.size() == 1 || Cond.size() == 0) &&
4203          "X86 branch conditions have one component!");
4204 
4205   if (Cond.empty()) {
4206     // Unconditional branch?
4207     assert(!FBB && "Unconditional branch with multiple successors!");
4208     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
4209     return 1;
4210   }
4211 
4212   // If FBB is null, it is implied to be a fall-through block.
4213   bool FallThru = FBB == nullptr;
4214 
4215   // Conditional branch.
4216   unsigned Count = 0;
4217   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4218   switch (CC) {
4219   case X86::COND_NE_OR_P:
4220     // Synthesize NE_OR_P with two branches.
4221     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
4222     ++Count;
4223     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
4224     ++Count;
4225     break;
4226   case X86::COND_E_AND_NP:
4227     // Use the next block of MBB as FBB if it is null.
4228     if (FBB == nullptr) {
4229       FBB = getFallThroughMBB(&MBB, TBB);
4230       assert(FBB && "MBB cannot be the last block in function when the false "
4231                     "body is a fall-through.");
4232     }
4233     // Synthesize COND_E_AND_NP with two branches.
4234     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4235     ++Count;
4236     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4237     ++Count;
4238     break;
4239   default: {
4240     unsigned Opc = GetCondBranchFromCond(CC);
4241     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
4242     ++Count;
4243   }
4244   }
4245   if (!FallThru) {
4246     // Two-way Conditional branch. Insert the second branch.
4247     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
4248     ++Count;
4249   }
4250   return Count;
4251 }
4252 
4253 bool X86InstrInfo::
4254 canInsertSelect(const MachineBasicBlock &MBB,
4255                 ArrayRef<MachineOperand> Cond,
4256                 unsigned TrueReg, unsigned FalseReg,
4257                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4258   // Not all subtargets have cmov instructions.
4259   if (!Subtarget.hasCMov())
4260     return false;
4261   if (Cond.size() != 1)
4262     return false;
4263   // We cannot do the composite conditions, at least not in SSA form.
4264   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4265     return false;
4266 
4267   // Check register classes.
4268   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4269   const TargetRegisterClass *RC =
4270     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4271   if (!RC)
4272     return false;
4273 
4274   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4275   if (X86::GR16RegClass.hasSubClassEq(RC) ||
4276       X86::GR32RegClass.hasSubClassEq(RC) ||
4277       X86::GR64RegClass.hasSubClassEq(RC)) {
4278     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4279     // Bridge. Probably Ivy Bridge as well.
4280     CondCycles = 2;
4281     TrueCycles = 2;
4282     FalseCycles = 2;
4283     return true;
4284   }
4285 
4286   // Can't do vectors.
4287   return false;
4288 }
4289 
4290 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4291                                 MachineBasicBlock::iterator I, DebugLoc DL,
4292                                 unsigned DstReg, ArrayRef<MachineOperand> Cond,
4293                                 unsigned TrueReg, unsigned FalseReg) const {
4294    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4295    assert(Cond.size() == 1 && "Invalid Cond array");
4296    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4297                                   MRI.getRegClass(DstReg)->getSize(),
4298                                   false/*HasMemoryOperand*/);
4299    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
4300 }
4301 
4302 /// Test if the given register is a physical h register.
4303 static bool isHReg(unsigned Reg) {
4304   return X86::GR8_ABCD_HRegClass.contains(Reg);
4305 }
4306 
4307 // Try and copy between VR128/VR64 and GR64 registers.
4308 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
4309                                         const X86Subtarget &Subtarget) {
4310 
4311   // SrcReg(VR128) -> DestReg(GR64)
4312   // SrcReg(VR64)  -> DestReg(GR64)
4313   // SrcReg(GR64)  -> DestReg(VR128)
4314   // SrcReg(GR64)  -> DestReg(VR64)
4315 
4316   bool HasAVX = Subtarget.hasAVX();
4317   bool HasAVX512 = Subtarget.hasAVX512();
4318   if (X86::GR64RegClass.contains(DestReg)) {
4319     if (X86::VR128XRegClass.contains(SrcReg))
4320       // Copy from a VR128 register to a GR64 register.
4321       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
4322                                                X86::MOVPQIto64rr);
4323     if (X86::VR64RegClass.contains(SrcReg))
4324       // Copy from a VR64 register to a GR64 register.
4325       return X86::MMX_MOVD64from64rr;
4326   } else if (X86::GR64RegClass.contains(SrcReg)) {
4327     // Copy from a GR64 register to a VR128 register.
4328     if (X86::VR128XRegClass.contains(DestReg))
4329       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
4330                                                X86::MOV64toPQIrr);
4331     // Copy from a GR64 register to a VR64 register.
4332     if (X86::VR64RegClass.contains(DestReg))
4333       return X86::MMX_MOVD64to64rr;
4334   }
4335 
4336   // SrcReg(FR32) -> DestReg(GR32)
4337   // SrcReg(GR32) -> DestReg(FR32)
4338 
4339   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
4340     // Copy from a FR32 register to a GR32 register.
4341     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
4342 
4343   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4344     // Copy from a GR32 register to a FR32 register.
4345     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
4346   return 0;
4347 }
4348 
4349 static bool isMaskRegClass(const TargetRegisterClass *RC) {
4350   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4351   return X86::VK16RegClass.hasSubClassEq(RC);
4352 }
4353 
4354 static bool MaskRegClassContains(unsigned Reg) {
4355   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4356   return X86::VK16RegClass.contains(Reg);
4357 }
4358 
4359 static bool GRRegClassContains(unsigned Reg) {
4360   return X86::GR64RegClass.contains(Reg) ||
4361          X86::GR32RegClass.contains(Reg) ||
4362          X86::GR16RegClass.contains(Reg) ||
4363          X86::GR8RegClass.contains(Reg);
4364 }
4365 static
4366 unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4367   if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
4368     DestReg = getX86SubSuperRegister(DestReg, 32);
4369     return X86::KMOVBrk;
4370   }
4371   if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
4372     SrcReg = getX86SubSuperRegister(SrcReg, 32);
4373     return X86::KMOVBkr;
4374   }
4375   return 0;
4376 }
4377 
4378 static
4379 unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4380   if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4381     return X86::KMOVQkk;
4382   if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4383     return X86::KMOVDrk;
4384   if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4385     return X86::KMOVQrk;
4386   if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4387     return X86::KMOVDkr;
4388   if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4389     return X86::KMOVQkr;
4390   return 0;
4391 }
4392 
4393 static
4394 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4395                                   const X86Subtarget &Subtarget)
4396 {
4397   if (Subtarget.hasDQI())
4398     if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4399       return Opc;
4400   if (Subtarget.hasBWI())
4401     if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4402       return Opc;
4403   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
4404       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
4405       X86::VR512RegClass.contains(DestReg, SrcReg)) {
4406      DestReg = get512BitSuperRegister(DestReg);
4407      SrcReg = get512BitSuperRegister(SrcReg);
4408      return X86::VMOVAPSZrr;
4409   }
4410   if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
4411     return X86::KMOVWkk;
4412   if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
4413     SrcReg = getX86SubSuperRegister(SrcReg, 32);
4414     return X86::KMOVWkr;
4415   }
4416   if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
4417     DestReg = getX86SubSuperRegister(DestReg, 32);
4418     return X86::KMOVWrk;
4419   }
4420   return 0;
4421 }
4422 
4423 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4424                                MachineBasicBlock::iterator MI, DebugLoc DL,
4425                                unsigned DestReg, unsigned SrcReg,
4426                                bool KillSrc) const {
4427   // First deal with the normal symmetric copies.
4428   bool HasAVX = Subtarget.hasAVX();
4429   bool HasAVX512 = Subtarget.hasAVX512();
4430   unsigned Opc = 0;
4431   if (X86::GR64RegClass.contains(DestReg, SrcReg))
4432     Opc = X86::MOV64rr;
4433   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4434     Opc = X86::MOV32rr;
4435   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4436     Opc = X86::MOV16rr;
4437   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4438     // Copying to or from a physical H register on x86-64 requires a NOREX
4439     // move.  Otherwise use a normal move.
4440     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
4441         Subtarget.is64Bit()) {
4442       Opc = X86::MOV8rr_NOREX;
4443       // Both operands must be encodable without an REX prefix.
4444       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4445              "8-bit H register can not be copied outside GR8_NOREX");
4446     } else
4447       Opc = X86::MOV8rr;
4448   }
4449   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4450     Opc = X86::MMX_MOVQ64rr;
4451   else if (HasAVX512)
4452     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
4453   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
4454     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4455   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4456     Opc = X86::VMOVAPSYrr;
4457   if (!Opc)
4458     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4459 
4460   if (Opc) {
4461     BuildMI(MBB, MI, DL, get(Opc), DestReg)
4462       .addReg(SrcReg, getKillRegState(KillSrc));
4463     return;
4464   }
4465 
4466   bool FromEFLAGS = SrcReg == X86::EFLAGS;
4467   bool ToEFLAGS = DestReg == X86::EFLAGS;
4468   int Reg = FromEFLAGS ? DestReg : SrcReg;
4469   bool is32 = X86::GR32RegClass.contains(Reg);
4470   bool is64 = X86::GR64RegClass.contains(Reg);
4471 
4472   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
4473     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4474     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4475     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4476     int Pop = is64 ? X86::POP64r : X86::POP32r;
4477     int PopF = is64 ? X86::POPF64 : X86::POPF32;
4478     int AX = is64 ? X86::RAX : X86::EAX;
4479 
4480     if (!Subtarget.hasLAHFSAHF()) {
4481       assert(Subtarget.is64Bit() &&
4482              "Not having LAHF/SAHF only happens on 64-bit.");
4483       // Moving EFLAGS to / from another register requires a push and a pop.
4484       // Notice that we have to adjust the stack if we don't want to clobber the
4485       // first frame index. See X86FrameLowering.cpp - usesTheStack.
4486       if (FromEFLAGS) {
4487         BuildMI(MBB, MI, DL, get(PushF));
4488         BuildMI(MBB, MI, DL, get(Pop), DestReg);
4489       }
4490       if (ToEFLAGS) {
4491         BuildMI(MBB, MI, DL, get(Push))
4492             .addReg(SrcReg, getKillRegState(KillSrc));
4493         BuildMI(MBB, MI, DL, get(PopF));
4494       }
4495       return;
4496     }
4497 
4498     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4499     // inefficient. Instead:
4500     //   - Save the overflow flag OF into AL using SETO, and restore it using a
4501     //     signed 8-bit addition of AL and INT8_MAX.
4502     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4503     //     using LAHF/SAHF.
4504     //   - When RAX/EAX is live and isn't the destination register, make sure it
4505     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4506     //     the flags.
4507     // This approach is ~2.25x faster than using PUSHF/POPF.
4508     //
4509     // This is still somewhat inefficient because we don't know which flags are
4510     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4511     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4512     //
4513     // PUSHF/POPF is also potentially incorrect because it affects other flags
4514     // such as TF/IF/DF, which LLVM doesn't model.
4515     //
4516     // Notice that we have to adjust the stack if we don't want to clobber the
4517     // first frame index.
4518     // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
4519 
4520     MachineBasicBlock::LivenessQueryResult LQR =
4521         MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI);
4522     // We do not want to save and restore AX if we do not have to.
4523     // Moreover, if we do so whereas AX is dead, we would need to set
4524     // an undef flag on the use of AX, otherwise the verifier will
4525     // complain that we read an undef value.
4526     // We do not want to change the behavior of the machine verifier
4527     // as this is usually wrong to read an undef value.
4528     if (MachineBasicBlock::LQR_Unknown == LQR) {
4529       LivePhysRegs LPR(&getRegisterInfo());
4530       LPR.addLiveOuts(&MBB, /*AddPristinesAndCSRs*/ true);
4531       MachineBasicBlock::iterator I = MBB.end();
4532       while (I != MI) {
4533         --I;
4534         LPR.stepBackward(*I);
4535       }
4536       LQR = LPR.contains(AX) ? MachineBasicBlock::LQR_Live
4537                              : MachineBasicBlock::LQR_Dead;
4538     }
4539     bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4540     if (!AXDead)
4541       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
4542     if (FromEFLAGS) {
4543       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4544       BuildMI(MBB, MI, DL, get(X86::LAHF));
4545       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
4546     }
4547     if (ToEFLAGS) {
4548       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4549       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4550           .addReg(X86::AL)
4551           .addImm(INT8_MAX);
4552       BuildMI(MBB, MI, DL, get(X86::SAHF));
4553     }
4554     if (!AXDead)
4555       BuildMI(MBB, MI, DL, get(Pop), AX);
4556     return;
4557   }
4558 
4559   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4560                << " to " << RI.getName(DestReg) << '\n');
4561   llvm_unreachable("Cannot emit physreg copy instruction");
4562 }
4563 
4564 static unsigned getLoadStoreMaskRegOpcode(const TargetRegisterClass *RC,
4565                                           bool load) {
4566   switch (RC->getSize()) {
4567   default:
4568     llvm_unreachable("Unknown spill size");
4569   case 2:
4570     return load ? X86::KMOVWkm : X86::KMOVWmk;
4571   case 4:
4572     return load ? X86::KMOVDkm : X86::KMOVDmk;
4573   case 8:
4574     return load ? X86::KMOVQkm : X86::KMOVQmk;
4575   }
4576 }
4577 
4578 static unsigned getLoadStoreRegOpcode(unsigned Reg,
4579                                       const TargetRegisterClass *RC,
4580                                       bool isStackAligned,
4581                                       const X86Subtarget &STI,
4582                                       bool load) {
4583   if (STI.hasAVX512()) {
4584     if (isMaskRegClass(RC))
4585       return getLoadStoreMaskRegOpcode(RC, load);
4586     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
4587       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
4588     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
4589       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
4590     if (X86::VR512RegClass.hasSubClassEq(RC))
4591       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4592   }
4593 
4594   bool HasAVX = STI.hasAVX();
4595   switch (RC->getSize()) {
4596   default:
4597     llvm_unreachable("Unknown spill size");
4598   case 1:
4599     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
4600     if (STI.is64Bit())
4601       // Copying to or from a physical H register on x86-64 requires a NOREX
4602       // move.  Otherwise use a normal move.
4603       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4604         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4605     return load ? X86::MOV8rm : X86::MOV8mr;
4606   case 2:
4607     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4608     return load ? X86::MOV16rm : X86::MOV16mr;
4609   case 4:
4610     if (X86::GR32RegClass.hasSubClassEq(RC))
4611       return load ? X86::MOV32rm : X86::MOV32mr;
4612     if (X86::FR32RegClass.hasSubClassEq(RC))
4613       return load ?
4614         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4615         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
4616     if (X86::RFP32RegClass.hasSubClassEq(RC))
4617       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4618     llvm_unreachable("Unknown 4-byte regclass");
4619   case 8:
4620     if (X86::GR64RegClass.hasSubClassEq(RC))
4621       return load ? X86::MOV64rm : X86::MOV64mr;
4622     if (X86::FR64RegClass.hasSubClassEq(RC))
4623       return load ?
4624         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4625         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
4626     if (X86::VR64RegClass.hasSubClassEq(RC))
4627       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4628     if (X86::RFP64RegClass.hasSubClassEq(RC))
4629       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4630     llvm_unreachable("Unknown 8-byte regclass");
4631   case 10:
4632     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
4633     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
4634   case 16: {
4635     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4636             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
4637     // If stack is realigned we can use aligned stores.
4638     if (isStackAligned)
4639       return load ?
4640         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
4641         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4642     else
4643       return load ?
4644         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
4645         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4646   }
4647   case 32:
4648     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4649             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
4650     // If stack is realigned we can use aligned stores.
4651     if (isStackAligned)
4652       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4653     else
4654       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
4655   case 64:
4656     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4657     if (isStackAligned)
4658       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4659     else
4660       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4661   }
4662 }
4663 
4664 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
4665                                          int64_t &Offset,
4666                                          const TargetRegisterInfo *TRI) const {
4667   const MCInstrDesc &Desc = MemOp->getDesc();
4668   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
4669   if (MemRefBegin < 0)
4670     return false;
4671 
4672   MemRefBegin += X86II::getOperandBias(Desc);
4673 
4674   MachineOperand &BaseMO = MemOp->getOperand(MemRefBegin + X86::AddrBaseReg);
4675   if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4676     return false;
4677 
4678   BaseReg = BaseMO.getReg();
4679   if (MemOp->getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4680     return false;
4681 
4682   if (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
4683       X86::NoRegister)
4684     return false;
4685 
4686   const MachineOperand &DispMO = MemOp->getOperand(MemRefBegin + X86::AddrDisp);
4687 
4688   // Displacement can be symbolic
4689   if (!DispMO.isImm())
4690     return false;
4691 
4692   Offset = DispMO.getImm();
4693 
4694   return (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4695           X86::NoRegister);
4696 }
4697 
4698 static unsigned getStoreRegOpcode(unsigned SrcReg,
4699                                   const TargetRegisterClass *RC,
4700                                   bool isStackAligned,
4701                                   const X86Subtarget &STI) {
4702   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
4703 }
4704 
4705 
4706 static unsigned getLoadRegOpcode(unsigned DestReg,
4707                                  const TargetRegisterClass *RC,
4708                                  bool isStackAligned,
4709                                  const X86Subtarget &STI) {
4710   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
4711 }
4712 
4713 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4714                                        MachineBasicBlock::iterator MI,
4715                                        unsigned SrcReg, bool isKill, int FrameIdx,
4716                                        const TargetRegisterClass *RC,
4717                                        const TargetRegisterInfo *TRI) const {
4718   const MachineFunction &MF = *MBB.getParent();
4719   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4720          "Stack slot too small for store");
4721   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4722   bool isAligned =
4723       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4724       RI.canRealignStack(MF);
4725   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4726   DebugLoc DL = MBB.findDebugLoc(MI);
4727   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
4728     .addReg(SrcReg, getKillRegState(isKill));
4729 }
4730 
4731 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4732                                   bool isKill,
4733                                   SmallVectorImpl<MachineOperand> &Addr,
4734                                   const TargetRegisterClass *RC,
4735                                   MachineInstr::mmo_iterator MMOBegin,
4736                                   MachineInstr::mmo_iterator MMOEnd,
4737                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
4738   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4739   bool isAligned = MMOBegin != MMOEnd &&
4740                    (*MMOBegin)->getAlignment() >= Alignment;
4741   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4742   DebugLoc DL;
4743   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
4744   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4745     MIB.addOperand(Addr[i]);
4746   MIB.addReg(SrcReg, getKillRegState(isKill));
4747   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4748   NewMIs.push_back(MIB);
4749 }
4750 
4751 
4752 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
4753                                         MachineBasicBlock::iterator MI,
4754                                         unsigned DestReg, int FrameIdx,
4755                                         const TargetRegisterClass *RC,
4756                                         const TargetRegisterInfo *TRI) const {
4757   const MachineFunction &MF = *MBB.getParent();
4758   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4759   bool isAligned =
4760       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4761       RI.canRealignStack(MF);
4762   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4763   DebugLoc DL = MBB.findDebugLoc(MI);
4764   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
4765 }
4766 
4767 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
4768                                  SmallVectorImpl<MachineOperand> &Addr,
4769                                  const TargetRegisterClass *RC,
4770                                  MachineInstr::mmo_iterator MMOBegin,
4771                                  MachineInstr::mmo_iterator MMOEnd,
4772                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
4773   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
4774   bool isAligned = MMOBegin != MMOEnd &&
4775                    (*MMOBegin)->getAlignment() >= Alignment;
4776   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
4777   DebugLoc DL;
4778   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
4779   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
4780     MIB.addOperand(Addr[i]);
4781   (*MIB).setMemRefs(MMOBegin, MMOEnd);
4782   NewMIs.push_back(MIB);
4783 }
4784 
4785 bool X86InstrInfo::
4786 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
4787                int &CmpMask, int &CmpValue) const {
4788   switch (MI->getOpcode()) {
4789   default: break;
4790   case X86::CMP64ri32:
4791   case X86::CMP64ri8:
4792   case X86::CMP32ri:
4793   case X86::CMP32ri8:
4794   case X86::CMP16ri:
4795   case X86::CMP16ri8:
4796   case X86::CMP8ri:
4797     SrcReg = MI->getOperand(0).getReg();
4798     SrcReg2 = 0;
4799     CmpMask = ~0;
4800     CmpValue = MI->getOperand(1).getImm();
4801     return true;
4802   // A SUB can be used to perform comparison.
4803   case X86::SUB64rm:
4804   case X86::SUB32rm:
4805   case X86::SUB16rm:
4806   case X86::SUB8rm:
4807     SrcReg = MI->getOperand(1).getReg();
4808     SrcReg2 = 0;
4809     CmpMask = ~0;
4810     CmpValue = 0;
4811     return true;
4812   case X86::SUB64rr:
4813   case X86::SUB32rr:
4814   case X86::SUB16rr:
4815   case X86::SUB8rr:
4816     SrcReg = MI->getOperand(1).getReg();
4817     SrcReg2 = MI->getOperand(2).getReg();
4818     CmpMask = ~0;
4819     CmpValue = 0;
4820     return true;
4821   case X86::SUB64ri32:
4822   case X86::SUB64ri8:
4823   case X86::SUB32ri:
4824   case X86::SUB32ri8:
4825   case X86::SUB16ri:
4826   case X86::SUB16ri8:
4827   case X86::SUB8ri:
4828     SrcReg = MI->getOperand(1).getReg();
4829     SrcReg2 = 0;
4830     CmpMask = ~0;
4831     CmpValue = MI->getOperand(2).getImm();
4832     return true;
4833   case X86::CMP64rr:
4834   case X86::CMP32rr:
4835   case X86::CMP16rr:
4836   case X86::CMP8rr:
4837     SrcReg = MI->getOperand(0).getReg();
4838     SrcReg2 = MI->getOperand(1).getReg();
4839     CmpMask = ~0;
4840     CmpValue = 0;
4841     return true;
4842   case X86::TEST8rr:
4843   case X86::TEST16rr:
4844   case X86::TEST32rr:
4845   case X86::TEST64rr:
4846     SrcReg = MI->getOperand(0).getReg();
4847     if (MI->getOperand(1).getReg() != SrcReg) return false;
4848     // Compare against zero.
4849     SrcReg2 = 0;
4850     CmpMask = ~0;
4851     CmpValue = 0;
4852     return true;
4853   }
4854   return false;
4855 }
4856 
4857 /// Check whether the first instruction, whose only
4858 /// purpose is to update flags, can be made redundant.
4859 /// CMPrr can be made redundant by SUBrr if the operands are the same.
4860 /// This function can be extended later on.
4861 /// SrcReg, SrcRegs: register operands for FlagI.
4862 /// ImmValue: immediate for FlagI if it takes an immediate.
4863 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4864                                         unsigned SrcReg2, int ImmValue,
4865                                         MachineInstr *OI) {
4866   if (((FlagI->getOpcode() == X86::CMP64rr &&
4867         OI->getOpcode() == X86::SUB64rr) ||
4868        (FlagI->getOpcode() == X86::CMP32rr &&
4869         OI->getOpcode() == X86::SUB32rr)||
4870        (FlagI->getOpcode() == X86::CMP16rr &&
4871         OI->getOpcode() == X86::SUB16rr)||
4872        (FlagI->getOpcode() == X86::CMP8rr &&
4873         OI->getOpcode() == X86::SUB8rr)) &&
4874       ((OI->getOperand(1).getReg() == SrcReg &&
4875         OI->getOperand(2).getReg() == SrcReg2) ||
4876        (OI->getOperand(1).getReg() == SrcReg2 &&
4877         OI->getOperand(2).getReg() == SrcReg)))
4878     return true;
4879 
4880   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4881         OI->getOpcode() == X86::SUB64ri32) ||
4882        (FlagI->getOpcode() == X86::CMP64ri8 &&
4883         OI->getOpcode() == X86::SUB64ri8) ||
4884        (FlagI->getOpcode() == X86::CMP32ri &&
4885         OI->getOpcode() == X86::SUB32ri) ||
4886        (FlagI->getOpcode() == X86::CMP32ri8 &&
4887         OI->getOpcode() == X86::SUB32ri8) ||
4888        (FlagI->getOpcode() == X86::CMP16ri &&
4889         OI->getOpcode() == X86::SUB16ri) ||
4890        (FlagI->getOpcode() == X86::CMP16ri8 &&
4891         OI->getOpcode() == X86::SUB16ri8) ||
4892        (FlagI->getOpcode() == X86::CMP8ri &&
4893         OI->getOpcode() == X86::SUB8ri)) &&
4894       OI->getOperand(1).getReg() == SrcReg &&
4895       OI->getOperand(2).getImm() == ImmValue)
4896     return true;
4897   return false;
4898 }
4899 
4900 /// Check whether the definition can be converted
4901 /// to remove a comparison against zero.
4902 inline static bool isDefConvertible(MachineInstr *MI) {
4903   switch (MI->getOpcode()) {
4904   default: return false;
4905 
4906   // The shift instructions only modify ZF if their shift count is non-zero.
4907   // N.B.: The processor truncates the shift count depending on the encoding.
4908   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
4909   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
4910      return getTruncatedShiftCount(MI, 2) != 0;
4911 
4912   // Some left shift instructions can be turned into LEA instructions but only
4913   // if their flags aren't used. Avoid transforming such instructions.
4914   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
4915     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4916     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4917     return ShAmt != 0;
4918   }
4919 
4920   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4921   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4922      return getTruncatedShiftCount(MI, 3) != 0;
4923 
4924   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4925   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
4926   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
4927   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
4928   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
4929   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
4930   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4931   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
4932   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
4933   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
4934   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
4935   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
4936   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4937   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
4938   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
4939   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
4940   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
4941   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4942   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
4943   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
4944   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
4945   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
4946   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
4947   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
4948   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
4949   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
4950   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
4951   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4952   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
4953   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
4954   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
4955   case X86::ADC32ri:   case X86::ADC32ri8:
4956   case X86::ADC32rr:   case X86::ADC64ri32:
4957   case X86::ADC64ri8:  case X86::ADC64rr:
4958   case X86::SBB32ri:   case X86::SBB32ri8:
4959   case X86::SBB32rr:   case X86::SBB64ri32:
4960   case X86::SBB64ri8:  case X86::SBB64rr:
4961   case X86::ANDN32rr:  case X86::ANDN32rm:
4962   case X86::ANDN64rr:  case X86::ANDN64rm:
4963   case X86::BEXTR32rr: case X86::BEXTR64rr:
4964   case X86::BEXTR32rm: case X86::BEXTR64rm:
4965   case X86::BLSI32rr:  case X86::BLSI32rm:
4966   case X86::BLSI64rr:  case X86::BLSI64rm:
4967   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4968   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4969   case X86::BLSR32rr:  case X86::BLSR32rm:
4970   case X86::BLSR64rr:  case X86::BLSR64rm:
4971   case X86::BZHI32rr:  case X86::BZHI32rm:
4972   case X86::BZHI64rr:  case X86::BZHI64rm:
4973   case X86::LZCNT16rr: case X86::LZCNT16rm:
4974   case X86::LZCNT32rr: case X86::LZCNT32rm:
4975   case X86::LZCNT64rr: case X86::LZCNT64rm:
4976   case X86::POPCNT16rr:case X86::POPCNT16rm:
4977   case X86::POPCNT32rr:case X86::POPCNT32rm:
4978   case X86::POPCNT64rr:case X86::POPCNT64rm:
4979   case X86::TZCNT16rr: case X86::TZCNT16rm:
4980   case X86::TZCNT32rr: case X86::TZCNT32rm:
4981   case X86::TZCNT64rr: case X86::TZCNT64rm:
4982     return true;
4983   }
4984 }
4985 
4986 /// Check whether the use can be converted to remove a comparison against zero.
4987 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
4988   switch (MI->getOpcode()) {
4989   default: return X86::COND_INVALID;
4990   case X86::LZCNT16rr: case X86::LZCNT16rm:
4991   case X86::LZCNT32rr: case X86::LZCNT32rm:
4992   case X86::LZCNT64rr: case X86::LZCNT64rm:
4993     return X86::COND_B;
4994   case X86::POPCNT16rr:case X86::POPCNT16rm:
4995   case X86::POPCNT32rr:case X86::POPCNT32rm:
4996   case X86::POPCNT64rr:case X86::POPCNT64rm:
4997     return X86::COND_E;
4998   case X86::TZCNT16rr: case X86::TZCNT16rm:
4999   case X86::TZCNT32rr: case X86::TZCNT32rm:
5000   case X86::TZCNT64rr: case X86::TZCNT64rm:
5001     return X86::COND_B;
5002   }
5003 }
5004 
5005 /// Check if there exists an earlier instruction that
5006 /// operates on the same source operands and sets flags in the same way as
5007 /// Compare; remove Compare if possible.
5008 bool X86InstrInfo::
5009 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
5010                      int CmpMask, int CmpValue,
5011                      const MachineRegisterInfo *MRI) const {
5012   // Check whether we can replace SUB with CMP.
5013   unsigned NewOpcode = 0;
5014   switch (CmpInstr->getOpcode()) {
5015   default: break;
5016   case X86::SUB64ri32:
5017   case X86::SUB64ri8:
5018   case X86::SUB32ri:
5019   case X86::SUB32ri8:
5020   case X86::SUB16ri:
5021   case X86::SUB16ri8:
5022   case X86::SUB8ri:
5023   case X86::SUB64rm:
5024   case X86::SUB32rm:
5025   case X86::SUB16rm:
5026   case X86::SUB8rm:
5027   case X86::SUB64rr:
5028   case X86::SUB32rr:
5029   case X86::SUB16rr:
5030   case X86::SUB8rr: {
5031     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
5032       return false;
5033     // There is no use of the destination register, we can replace SUB with CMP.
5034     switch (CmpInstr->getOpcode()) {
5035     default: llvm_unreachable("Unreachable!");
5036     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
5037     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
5038     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
5039     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
5040     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
5041     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
5042     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
5043     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
5044     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5045     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
5046     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
5047     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
5048     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
5049     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
5050     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
5051     }
5052     CmpInstr->setDesc(get(NewOpcode));
5053     CmpInstr->RemoveOperand(0);
5054     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5055     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5056         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5057       return false;
5058   }
5059   }
5060 
5061   // Get the unique definition of SrcReg.
5062   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5063   if (!MI) return false;
5064 
5065   // CmpInstr is the first instruction of the BB.
5066   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5067 
5068   // If we are comparing against zero, check whether we can use MI to update
5069   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5070   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
5071   if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
5072     return false;
5073 
5074   // If we have a use of the source register between the def and our compare
5075   // instruction we can eliminate the compare iff the use sets EFLAGS in the
5076   // right way.
5077   bool ShouldUpdateCC = false;
5078   X86::CondCode NewCC = X86::COND_INVALID;
5079   if (IsCmpZero && !isDefConvertible(MI)) {
5080     // Scan forward from the use until we hit the use we're looking for or the
5081     // compare instruction.
5082     for (MachineBasicBlock::iterator J = MI;; ++J) {
5083       // Do we have a convertible instruction?
5084       NewCC = isUseDefConvertible(J);
5085       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5086           J->getOperand(1).getReg() == SrcReg) {
5087         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5088         ShouldUpdateCC = true; // Update CC later on.
5089         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5090         // with the new def.
5091         MI = Def = J;
5092         break;
5093       }
5094 
5095       if (J == I)
5096         return false;
5097     }
5098   }
5099 
5100   // We are searching for an earlier instruction that can make CmpInstr
5101   // redundant and that instruction will be saved in Sub.
5102   MachineInstr *Sub = nullptr;
5103   const TargetRegisterInfo *TRI = &getRegisterInfo();
5104 
5105   // We iterate backward, starting from the instruction before CmpInstr and
5106   // stop when reaching the definition of a source register or done with the BB.
5107   // RI points to the instruction before CmpInstr.
5108   // If the definition is in this basic block, RE points to the definition;
5109   // otherwise, RE is the rend of the basic block.
5110   MachineBasicBlock::reverse_iterator
5111       RI = MachineBasicBlock::reverse_iterator(I),
5112       RE = CmpInstr->getParent() == MI->getParent() ?
5113            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
5114            CmpInstr->getParent()->rend();
5115   MachineInstr *Movr0Inst = nullptr;
5116   for (; RI != RE; ++RI) {
5117     MachineInstr *Instr = &*RI;
5118     // Check whether CmpInstr can be made redundant by the current instruction.
5119     if (!IsCmpZero &&
5120         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
5121       Sub = Instr;
5122       break;
5123     }
5124 
5125     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
5126         Instr->readsRegister(X86::EFLAGS, TRI)) {
5127       // This instruction modifies or uses EFLAGS.
5128 
5129       // MOV32r0 etc. are implemented with xor which clobbers condition code.
5130       // They are safe to move up, if the definition to EFLAGS is dead and
5131       // earlier instructions do not read or write EFLAGS.
5132       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
5133           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
5134         Movr0Inst = Instr;
5135         continue;
5136       }
5137 
5138       // We can't remove CmpInstr.
5139       return false;
5140     }
5141   }
5142 
5143   // Return false if no candidates exist.
5144   if (!IsCmpZero && !Sub)
5145     return false;
5146 
5147   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5148                     Sub->getOperand(2).getReg() == SrcReg);
5149 
5150   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
5151   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5152   // If we are done with the basic block, we need to check whether EFLAGS is
5153   // live-out.
5154   bool IsSafe = false;
5155   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
5156   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
5157   for (++I; I != E; ++I) {
5158     const MachineInstr &Instr = *I;
5159     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5160     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5161     // We should check the usage if this instruction uses and updates EFLAGS.
5162     if (!UseEFLAGS && ModifyEFLAGS) {
5163       // It is safe to remove CmpInstr if EFLAGS is updated again.
5164       IsSafe = true;
5165       break;
5166     }
5167     if (!UseEFLAGS && !ModifyEFLAGS)
5168       continue;
5169 
5170     // EFLAGS is used by this instruction.
5171     X86::CondCode OldCC = X86::COND_INVALID;
5172     bool OpcIsSET = false;
5173     if (IsCmpZero || IsSwapped) {
5174       // We decode the condition code from opcode.
5175       if (Instr.isBranch())
5176         OldCC = getCondFromBranchOpc(Instr.getOpcode());
5177       else {
5178         OldCC = getCondFromSETOpc(Instr.getOpcode());
5179         if (OldCC != X86::COND_INVALID)
5180           OpcIsSET = true;
5181         else
5182           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
5183       }
5184       if (OldCC == X86::COND_INVALID) return false;
5185     }
5186     if (IsCmpZero) {
5187       switch (OldCC) {
5188       default: break;
5189       case X86::COND_A: case X86::COND_AE:
5190       case X86::COND_B: case X86::COND_BE:
5191       case X86::COND_G: case X86::COND_GE:
5192       case X86::COND_L: case X86::COND_LE:
5193       case X86::COND_O: case X86::COND_NO:
5194         // CF and OF are used, we can't perform this optimization.
5195         return false;
5196       }
5197 
5198       // If we're updating the condition code check if we have to reverse the
5199       // condition.
5200       if (ShouldUpdateCC)
5201         switch (OldCC) {
5202         default:
5203           return false;
5204         case X86::COND_E:
5205           break;
5206         case X86::COND_NE:
5207           NewCC = GetOppositeBranchCondition(NewCC);
5208           break;
5209         }
5210     } else if (IsSwapped) {
5211       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5212       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5213       // We swap the condition code and synthesize the new opcode.
5214       NewCC = getSwappedCondition(OldCC);
5215       if (NewCC == X86::COND_INVALID) return false;
5216     }
5217 
5218     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
5219       // Synthesize the new opcode.
5220       bool HasMemoryOperand = Instr.hasOneMemOperand();
5221       unsigned NewOpc;
5222       if (Instr.isBranch())
5223         NewOpc = GetCondBranchFromCond(NewCC);
5224       else if(OpcIsSET)
5225         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5226       else {
5227         unsigned DstReg = Instr.getOperand(0).getReg();
5228         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5229                                  HasMemoryOperand);
5230       }
5231 
5232       // Push the MachineInstr to OpsToUpdate.
5233       // If it is safe to remove CmpInstr, the condition code of these
5234       // instructions will be modified.
5235       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5236     }
5237     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5238       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
5239       IsSafe = true;
5240       break;
5241     }
5242   }
5243 
5244   // If EFLAGS is not killed nor re-defined, we should check whether it is
5245   // live-out. If it is live-out, do not optimize.
5246   if ((IsCmpZero || IsSwapped) && !IsSafe) {
5247     MachineBasicBlock *MBB = CmpInstr->getParent();
5248     for (MachineBasicBlock *Successor : MBB->successors())
5249       if (Successor->isLiveIn(X86::EFLAGS))
5250         return false;
5251   }
5252 
5253   // The instruction to be updated is either Sub or MI.
5254   Sub = IsCmpZero ? MI : Sub;
5255   // Move Movr0Inst to the appropriate place before Sub.
5256   if (Movr0Inst) {
5257     // Look backwards until we find a def that doesn't use the current EFLAGS.
5258     Def = Sub;
5259     MachineBasicBlock::reverse_iterator
5260       InsertI = MachineBasicBlock::reverse_iterator(++Def),
5261                 InsertE = Sub->getParent()->rend();
5262     for (; InsertI != InsertE; ++InsertI) {
5263       MachineInstr *Instr = &*InsertI;
5264       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5265           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5266         Sub->getParent()->remove(Movr0Inst);
5267         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5268                                    Movr0Inst);
5269         break;
5270       }
5271     }
5272     if (InsertI == InsertE)
5273       return false;
5274   }
5275 
5276   // Make sure Sub instruction defines EFLAGS and mark the def live.
5277   unsigned i = 0, e = Sub->getNumOperands();
5278   for (; i != e; ++i) {
5279     MachineOperand &MO = Sub->getOperand(i);
5280     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5281       MO.setIsDead(false);
5282       break;
5283     }
5284   }
5285   assert(i != e && "Unable to locate a def EFLAGS operand");
5286 
5287   CmpInstr->eraseFromParent();
5288 
5289   // Modify the condition code of instructions in OpsToUpdate.
5290   for (auto &Op : OpsToUpdate)
5291     Op.first->setDesc(get(Op.second));
5292   return true;
5293 }
5294 
5295 /// Try to remove the load by folding it to a register
5296 /// operand at the use. We fold the load instructions if load defines a virtual
5297 /// register, the virtual register is used once in the same BB, and the
5298 /// instructions in-between do not load or store, and have no side effects.
5299 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
5300                                               const MachineRegisterInfo *MRI,
5301                                               unsigned &FoldAsLoadDefReg,
5302                                               MachineInstr *&DefMI) const {
5303   if (FoldAsLoadDefReg == 0)
5304     return nullptr;
5305   // To be conservative, if there exists another load, clear the load candidate.
5306   if (MI->mayLoad()) {
5307     FoldAsLoadDefReg = 0;
5308     return nullptr;
5309   }
5310 
5311   // Check whether we can move DefMI here.
5312   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5313   assert(DefMI);
5314   bool SawStore = false;
5315   if (!DefMI->isSafeToMove(nullptr, SawStore))
5316     return nullptr;
5317 
5318   // Collect information about virtual register operands of MI.
5319   unsigned SrcOperandId = 0;
5320   bool FoundSrcOperand = false;
5321   for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
5322     MachineOperand &MO = MI->getOperand(i);
5323     if (!MO.isReg())
5324       continue;
5325     unsigned Reg = MO.getReg();
5326     if (Reg != FoldAsLoadDefReg)
5327       continue;
5328     // Do not fold if we have a subreg use or a def or multiple uses.
5329     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
5330       return nullptr;
5331 
5332     SrcOperandId = i;
5333     FoundSrcOperand = true;
5334   }
5335   if (!FoundSrcOperand)
5336     return nullptr;
5337 
5338   // Check whether we can fold the def into SrcOperandId.
5339   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI)) {
5340     FoldAsLoadDefReg = 0;
5341     return FoldMI;
5342   }
5343 
5344   return nullptr;
5345 }
5346 
5347 /// Expand a single-def pseudo instruction to a two-addr
5348 /// instruction with two undef reads of the register being defined.
5349 /// This is used for mapping:
5350 ///   %xmm4 = V_SET0
5351 /// to:
5352 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5353 ///
5354 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5355                              const MCInstrDesc &Desc) {
5356   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5357   unsigned Reg = MIB->getOperand(0).getReg();
5358   MIB->setDesc(Desc);
5359 
5360   // MachineInstr::addOperand() will insert explicit operands before any
5361   // implicit operands.
5362   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5363   // But we don't trust that.
5364   assert(MIB->getOperand(1).getReg() == Reg &&
5365          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
5366   return true;
5367 }
5368 
5369 /// Expand a single-def pseudo instruction to a two-addr
5370 /// instruction with two %k0 reads.
5371 /// This is used for mapping:
5372 ///   %k4 = K_SET1
5373 /// to:
5374 ///   %k4 = KXNORrr %k0, %k0
5375 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5376                             const MCInstrDesc &Desc, unsigned Reg) {
5377   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5378   MIB->setDesc(Desc);
5379   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5380   return true;
5381 }
5382 
5383 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5384                           bool MinusOne) {
5385   MachineBasicBlock &MBB = *MIB->getParent();
5386   DebugLoc DL = MIB->getDebugLoc();
5387   unsigned Reg = MIB->getOperand(0).getReg();
5388 
5389   // Insert the XOR.
5390   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5391       .addReg(Reg, RegState::Undef)
5392       .addReg(Reg, RegState::Undef);
5393 
5394   // Turn the pseudo into an INC or DEC.
5395   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5396   MIB.addReg(Reg);
5397 
5398   return true;
5399 }
5400 
5401 bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5402   MachineBasicBlock &MBB = *MIB->getParent();
5403   DebugLoc DL = MIB->getDebugLoc();
5404   int64_t Imm = MIB->getOperand(1).getImm();
5405   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5406   MachineBasicBlock::iterator I = MIB.getInstr();
5407 
5408   int StackAdjustment;
5409 
5410   if (Subtarget.is64Bit()) {
5411     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5412            MIB->getOpcode() == X86::MOV32ImmSExti8);
5413 
5414     // Can't use push/pop lowering if the function might write to the red zone.
5415     X86MachineFunctionInfo *X86FI =
5416         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5417     if (X86FI->getUsesRedZone()) {
5418       MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5419                                                                : X86::MOV64ri));
5420       return true;
5421     }
5422 
5423     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5424     // widen the register if necessary.
5425     StackAdjustment = 8;
5426     BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5427     MIB->setDesc(get(X86::POP64r));
5428     MIB->getOperand(0)
5429         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5430   } else {
5431     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5432     StackAdjustment = 4;
5433     BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5434     MIB->setDesc(get(X86::POP32r));
5435   }
5436 
5437   // Build CFI if necessary.
5438   MachineFunction &MF = *MBB.getParent();
5439   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5440   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5441   bool NeedsDwarfCFI =
5442       !IsWin64Prologue &&
5443       (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5444   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5445   if (EmitCFI) {
5446     TFL->BuildCFI(MBB, I, DL,
5447         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5448     TFL->BuildCFI(MBB, std::next(I), DL,
5449         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5450   }
5451 
5452   return true;
5453 }
5454 
5455 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5456 // code sequence is needed for other targets.
5457 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5458                                  const TargetInstrInfo &TII) {
5459   MachineBasicBlock &MBB = *MIB->getParent();
5460   DebugLoc DL = MIB->getDebugLoc();
5461   unsigned Reg = MIB->getOperand(0).getReg();
5462   const GlobalValue *GV =
5463       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
5464   unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
5465   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
5466       MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8);
5467   MachineBasicBlock::iterator I = MIB.getInstr();
5468 
5469   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5470       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5471       .addMemOperand(MMO);
5472   MIB->setDebugLoc(DL);
5473   MIB->setDesc(TII.get(X86::MOV64rm));
5474   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5475 }
5476 
5477 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
5478   bool HasAVX = Subtarget.hasAVX();
5479   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
5480   switch (MI->getOpcode()) {
5481   case X86::MOV32r0:
5482     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
5483   case X86::MOV32r1:
5484     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5485   case X86::MOV32r_1:
5486     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
5487   case X86::MOV32ImmSExti8:
5488   case X86::MOV64ImmSExti8:
5489     return ExpandMOVImmSExti8(MIB);
5490   case X86::SETB_C8r:
5491     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
5492   case X86::SETB_C16r:
5493     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
5494   case X86::SETB_C32r:
5495     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
5496   case X86::SETB_C64r:
5497     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
5498   case X86::V_SET0:
5499   case X86::FsFLD0SS:
5500   case X86::FsFLD0SD:
5501     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
5502   case X86::AVX_SET0:
5503     assert(HasAVX && "AVX not supported");
5504     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
5505   case X86::AVX512_512_SET0:
5506     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
5507   case X86::V_SETALLONES:
5508     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
5509   case X86::AVX2_SETALLONES:
5510     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
5511   case X86::TEST8ri_NOREX:
5512     MI->setDesc(get(X86::TEST8ri));
5513     return true;
5514   case X86::MOV32ri64:
5515     MI->setDesc(get(X86::MOV32ri));
5516     return true;
5517 
5518   // KNL does not recognize dependency-breaking idioms for mask registers,
5519   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5520   // Using %k0 as the undef input register is a performance heuristic based
5521   // on the assumption that %k0 is used less frequently than the other mask
5522   // registers, since it is not usable as a write mask.
5523   // FIXME: A more advanced approach would be to choose the best input mask
5524   // register based on context.
5525   case X86::KSET0B:
5526   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5527   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5528   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
5529   case X86::KSET1B:
5530   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5531   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5532   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
5533   case TargetOpcode::LOAD_STACK_GUARD:
5534     expandLoadStackGuard(MIB, *this);
5535     return true;
5536   }
5537   return false;
5538 }
5539 
5540 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5541                         int PtrOffset = 0) {
5542   unsigned NumAddrOps = MOs.size();
5543 
5544   if (NumAddrOps < 4) {
5545     // FrameIndex only - add an immediate offset (whether its zero or not).
5546     for (unsigned i = 0; i != NumAddrOps; ++i)
5547       MIB.addOperand(MOs[i]);
5548     addOffset(MIB, PtrOffset);
5549   } else {
5550     // General Memory Addressing - we need to add any offset to an existing
5551     // offset.
5552     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5553     for (unsigned i = 0; i != NumAddrOps; ++i) {
5554       const MachineOperand &MO = MOs[i];
5555       if (i == 3 && PtrOffset != 0) {
5556         MIB.addDisp(MO, PtrOffset);
5557       } else {
5558         MIB.addOperand(MO);
5559       }
5560     }
5561   }
5562 }
5563 
5564 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5565                                      ArrayRef<MachineOperand> MOs,
5566                                      MachineBasicBlock::iterator InsertPt,
5567                                      MachineInstr *MI,
5568                                      const TargetInstrInfo &TII) {
5569   // Create the base instruction with the memory operand as the first part.
5570   // Omit the implicit operands, something BuildMI can't do.
5571   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5572                                               MI->getDebugLoc(), true);
5573   MachineInstrBuilder MIB(MF, NewMI);
5574   addOperands(MIB, MOs);
5575 
5576   // Loop over the rest of the ri operands, converting them over.
5577   unsigned NumOps = MI->getDesc().getNumOperands()-2;
5578   for (unsigned i = 0; i != NumOps; ++i) {
5579     MachineOperand &MO = MI->getOperand(i+2);
5580     MIB.addOperand(MO);
5581   }
5582   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
5583     MachineOperand &MO = MI->getOperand(i);
5584     MIB.addOperand(MO);
5585   }
5586 
5587   MachineBasicBlock *MBB = InsertPt->getParent();
5588   MBB->insert(InsertPt, NewMI);
5589 
5590   return MIB;
5591 }
5592 
5593 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5594                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5595                               MachineBasicBlock::iterator InsertPt,
5596                               MachineInstr *MI, const TargetInstrInfo &TII,
5597                               int PtrOffset = 0) {
5598   // Omit the implicit operands, something BuildMI can't do.
5599   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5600                                               MI->getDebugLoc(), true);
5601   MachineInstrBuilder MIB(MF, NewMI);
5602 
5603   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5604     MachineOperand &MO = MI->getOperand(i);
5605     if (i == OpNo) {
5606       assert(MO.isReg() && "Expected to fold into reg operand!");
5607       addOperands(MIB, MOs, PtrOffset);
5608     } else {
5609       MIB.addOperand(MO);
5610     }
5611   }
5612 
5613   MachineBasicBlock *MBB = InsertPt->getParent();
5614   MBB->insert(InsertPt, NewMI);
5615 
5616   return MIB;
5617 }
5618 
5619 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5620                                 ArrayRef<MachineOperand> MOs,
5621                                 MachineBasicBlock::iterator InsertPt,
5622                                 MachineInstr *MI) {
5623   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5624                                     MI->getDebugLoc(), TII.get(Opcode));
5625   addOperands(MIB, MOs);
5626   return MIB.addImm(0);
5627 }
5628 
5629 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5630     MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5631     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5632     unsigned Size, unsigned Align) const {
5633   switch (MI->getOpcode()) {
5634   case X86::INSERTPSrr:
5635   case X86::VINSERTPSrr:
5636     // Attempt to convert the load of inserted vector into a fold load
5637     // of a single float.
5638     if (OpNum == 2) {
5639       unsigned Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
5640       unsigned ZMask = Imm & 15;
5641       unsigned DstIdx = (Imm >> 4) & 3;
5642       unsigned SrcIdx = (Imm >> 6) & 3;
5643 
5644       unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5645       if (Size <= RCSize && 4 <= Align) {
5646         int PtrOffset = SrcIdx * 4;
5647         unsigned NewImm = (DstIdx << 4) | ZMask;
5648         unsigned NewOpCode =
5649             (MI->getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
5650                                                  : X86::INSERTPSrm);
5651         MachineInstr *NewMI =
5652             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5653         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5654         return NewMI;
5655       }
5656     }
5657     break;
5658   case X86::MOVHLPSrr:
5659   case X86::VMOVHLPSrr:
5660     // Move the upper 64-bits of the second operand to the lower 64-bits.
5661     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5662     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5663     if (OpNum == 2) {
5664       unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5665       if (Size <= RCSize && 8 <= Align) {
5666         unsigned NewOpCode =
5667             (MI->getOpcode() == X86::VMOVHLPSrr ? X86::VMOVLPSrm
5668                                                 : X86::MOVLPSrm);
5669         MachineInstr *NewMI =
5670             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5671         return NewMI;
5672       }
5673     }
5674     break;
5675   };
5676 
5677   return nullptr;
5678 }
5679 
5680 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5681     MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5682     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5683     unsigned Size, unsigned Align, bool AllowCommute) const {
5684   const DenseMap<unsigned,
5685                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
5686   bool isCallRegIndirect = Subtarget.callRegIndirect();
5687   bool isTwoAddrFold = false;
5688 
5689   // For CPUs that favor the register form of a call or push,
5690   // do not fold loads into calls or pushes, unless optimizing for size
5691   // aggressively.
5692   if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
5693       (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r ||
5694        MI->getOpcode() == X86::PUSH16r || MI->getOpcode() == X86::PUSH32r ||
5695        MI->getOpcode() == X86::PUSH64r))
5696     return nullptr;
5697 
5698   unsigned NumOps = MI->getDesc().getNumOperands();
5699   bool isTwoAddr = NumOps > 1 &&
5700     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5701 
5702   // FIXME: AsmPrinter doesn't know how to handle
5703   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5704   if (MI->getOpcode() == X86::ADD32ri &&
5705       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5706     return nullptr;
5707 
5708   MachineInstr *NewMI = nullptr;
5709 
5710   // Attempt to fold any custom cases we have.
5711   if (MachineInstr *CustomMI =
5712           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
5713     return CustomMI;
5714 
5715   // Folding a memory location into the two-address part of a two-address
5716   // instruction is different than folding it other places.  It requires
5717   // replacing the *two* registers with the memory location.
5718   if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
5719       MI->getOperand(0).isReg() &&
5720       MI->getOperand(1).isReg() &&
5721       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
5722     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5723     isTwoAddrFold = true;
5724   } else if (OpNum == 0) {
5725     if (MI->getOpcode() == X86::MOV32r0) {
5726       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5727       if (NewMI)
5728         return NewMI;
5729     }
5730 
5731     OpcodeTablePtr = &RegOp2MemOpTable0;
5732   } else if (OpNum == 1) {
5733     OpcodeTablePtr = &RegOp2MemOpTable1;
5734   } else if (OpNum == 2) {
5735     OpcodeTablePtr = &RegOp2MemOpTable2;
5736   } else if (OpNum == 3) {
5737     OpcodeTablePtr = &RegOp2MemOpTable3;
5738   } else if (OpNum == 4) {
5739     OpcodeTablePtr = &RegOp2MemOpTable4;
5740   }
5741 
5742   // If table selected...
5743   if (OpcodeTablePtr) {
5744     // Find the Opcode to fuse
5745     DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5746       OpcodeTablePtr->find(MI->getOpcode());
5747     if (I != OpcodeTablePtr->end()) {
5748       unsigned Opcode = I->second.first;
5749       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
5750       if (Align < MinAlign)
5751         return nullptr;
5752       bool NarrowToMOV32rm = false;
5753       if (Size) {
5754         unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5755         if (Size < RCSize) {
5756           // Check if it's safe to fold the load. If the size of the object is
5757           // narrower than the load width, then it's not.
5758           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5759             return nullptr;
5760           // If this is a 64-bit load, but the spill slot is 32, then we can do
5761           // a 32-bit load which is implicitly zero-extended. This likely is
5762           // due to live interval analysis remat'ing a load from stack slot.
5763           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
5764             return nullptr;
5765           Opcode = X86::MOV32rm;
5766           NarrowToMOV32rm = true;
5767         }
5768       }
5769 
5770       if (isTwoAddrFold)
5771         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5772       else
5773         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5774 
5775       if (NarrowToMOV32rm) {
5776         // If this is the special case where we use a MOV32rm to load a 32-bit
5777         // value and zero-extend the top bits. Change the destination register
5778         // to a 32-bit one.
5779         unsigned DstReg = NewMI->getOperand(0).getReg();
5780         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
5781           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5782         else
5783           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5784       }
5785       return NewMI;
5786     }
5787   }
5788 
5789   // If the instruction and target operand are commutable, commute the
5790   // instruction and try again.
5791   if (AllowCommute) {
5792     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5793     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5794       bool HasDef = MI->getDesc().getNumDefs();
5795       unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
5796       unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
5797       unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
5798       bool Tied1 =
5799           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5800       bool Tied2 =
5801           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5802 
5803       // If either of the commutable operands are tied to the destination
5804       // then we can not commute + fold.
5805       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5806           (HasDef && Reg0 == Reg2 && Tied2))
5807         return nullptr;
5808 
5809       MachineInstr *CommutedMI =
5810           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5811       if (!CommutedMI) {
5812         // Unable to commute.
5813         return nullptr;
5814       }
5815       if (CommutedMI != MI) {
5816         // New instruction. We can't fold from this.
5817         CommutedMI->eraseFromParent();
5818         return nullptr;
5819       }
5820 
5821       // Attempt to fold with the commuted version of the instruction.
5822       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5823                                     Size, Align, /*AllowCommute=*/false);
5824       if (NewMI)
5825         return NewMI;
5826 
5827       // Folding failed again - undo the commute before returning.
5828       MachineInstr *UncommutedMI =
5829           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5830       if (!UncommutedMI) {
5831         // Unable to commute.
5832         return nullptr;
5833       }
5834       if (UncommutedMI != MI) {
5835         // New instruction. It doesn't need to be kept.
5836         UncommutedMI->eraseFromParent();
5837         return nullptr;
5838       }
5839 
5840       // Return here to prevent duplicate fuse failure report.
5841       return nullptr;
5842     }
5843   }
5844 
5845   // No fusion
5846   if (PrintFailedFusing && !MI->isCopy())
5847     dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
5848   return nullptr;
5849 }
5850 
5851 /// Return true for all instructions that only update
5852 /// the first 32 or 64-bits of the destination register and leave the rest
5853 /// unmodified. This can be used to avoid folding loads if the instructions
5854 /// only update part of the destination register, and the non-updated part is
5855 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5856 /// instructions breaks the partial register dependency and it can improve
5857 /// performance. e.g.:
5858 ///
5859 ///   movss (%rdi), %xmm0
5860 ///   cvtss2sd %xmm0, %xmm0
5861 ///
5862 /// Instead of
5863 ///   cvtss2sd (%rdi), %xmm0
5864 ///
5865 /// FIXME: This should be turned into a TSFlags.
5866 ///
5867 static bool hasPartialRegUpdate(unsigned Opcode) {
5868   switch (Opcode) {
5869   case X86::CVTSI2SSrr:
5870   case X86::CVTSI2SSrm:
5871   case X86::CVTSI2SS64rr:
5872   case X86::CVTSI2SS64rm:
5873   case X86::CVTSI2SDrr:
5874   case X86::CVTSI2SDrm:
5875   case X86::CVTSI2SD64rr:
5876   case X86::CVTSI2SD64rm:
5877   case X86::CVTSD2SSrr:
5878   case X86::CVTSD2SSrm:
5879   case X86::Int_CVTSD2SSrr:
5880   case X86::Int_CVTSD2SSrm:
5881   case X86::CVTSS2SDrr:
5882   case X86::CVTSS2SDrm:
5883   case X86::Int_CVTSS2SDrr:
5884   case X86::Int_CVTSS2SDrm:
5885   case X86::MOVHPDrm:
5886   case X86::MOVHPSrm:
5887   case X86::MOVLPDrm:
5888   case X86::MOVLPSrm:
5889   case X86::RCPSSr:
5890   case X86::RCPSSm:
5891   case X86::RCPSSr_Int:
5892   case X86::RCPSSm_Int:
5893   case X86::ROUNDSDr:
5894   case X86::ROUNDSDm:
5895   case X86::ROUNDSDr_Int:
5896   case X86::ROUNDSSr:
5897   case X86::ROUNDSSm:
5898   case X86::ROUNDSSr_Int:
5899   case X86::RSQRTSSr:
5900   case X86::RSQRTSSm:
5901   case X86::RSQRTSSr_Int:
5902   case X86::RSQRTSSm_Int:
5903   case X86::SQRTSSr:
5904   case X86::SQRTSSm:
5905   case X86::SQRTSSr_Int:
5906   case X86::SQRTSSm_Int:
5907   case X86::SQRTSDr:
5908   case X86::SQRTSDm:
5909   case X86::SQRTSDr_Int:
5910   case X86::SQRTSDm_Int:
5911     return true;
5912   }
5913 
5914   return false;
5915 }
5916 
5917 /// Inform the ExeDepsFix pass how many idle
5918 /// instructions we would like before a partial register update.
5919 unsigned X86InstrInfo::
5920 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
5921                              const TargetRegisterInfo *TRI) const {
5922   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
5923     return 0;
5924 
5925   // If MI is marked as reading Reg, the partial register update is wanted.
5926   const MachineOperand &MO = MI->getOperand(0);
5927   unsigned Reg = MO.getReg();
5928   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
5929     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
5930       return 0;
5931   } else {
5932     if (MI->readsRegister(Reg, TRI))
5933       return 0;
5934   }
5935 
5936   // If any of the preceding 16 instructions are reading Reg, insert a
5937   // dependency breaking instruction.  The magic number is based on a few
5938   // Nehalem experiments.
5939   return 16;
5940 }
5941 
5942 // Return true for any instruction the copies the high bits of the first source
5943 // operand into the unused high bits of the destination operand.
5944 static bool hasUndefRegUpdate(unsigned Opcode) {
5945   switch (Opcode) {
5946   case X86::VCVTSI2SSrr:
5947   case X86::VCVTSI2SSrm:
5948   case X86::Int_VCVTSI2SSrr:
5949   case X86::Int_VCVTSI2SSrm:
5950   case X86::VCVTSI2SS64rr:
5951   case X86::VCVTSI2SS64rm:
5952   case X86::Int_VCVTSI2SS64rr:
5953   case X86::Int_VCVTSI2SS64rm:
5954   case X86::VCVTSI2SDrr:
5955   case X86::VCVTSI2SDrm:
5956   case X86::Int_VCVTSI2SDrr:
5957   case X86::Int_VCVTSI2SDrm:
5958   case X86::VCVTSI2SD64rr:
5959   case X86::VCVTSI2SD64rm:
5960   case X86::Int_VCVTSI2SD64rr:
5961   case X86::Int_VCVTSI2SD64rm:
5962   case X86::VCVTSD2SSrr:
5963   case X86::VCVTSD2SSrm:
5964   case X86::Int_VCVTSD2SSrr:
5965   case X86::Int_VCVTSD2SSrm:
5966   case X86::VCVTSS2SDrr:
5967   case X86::VCVTSS2SDrm:
5968   case X86::Int_VCVTSS2SDrr:
5969   case X86::Int_VCVTSS2SDrm:
5970   case X86::VRCPSSr:
5971   case X86::VRCPSSm:
5972   case X86::VRCPSSm_Int:
5973   case X86::VROUNDSDr:
5974   case X86::VROUNDSDm:
5975   case X86::VROUNDSDr_Int:
5976   case X86::VROUNDSSr:
5977   case X86::VROUNDSSm:
5978   case X86::VROUNDSSr_Int:
5979   case X86::VRSQRTSSr:
5980   case X86::VRSQRTSSm:
5981   case X86::VRSQRTSSm_Int:
5982   case X86::VSQRTSSr:
5983   case X86::VSQRTSSm:
5984   case X86::VSQRTSSm_Int:
5985   case X86::VSQRTSDr:
5986   case X86::VSQRTSDm:
5987   case X86::VSQRTSDm_Int:
5988     // AVX-512
5989   case X86::VCVTSD2SSZrr:
5990   case X86::VCVTSD2SSZrm:
5991   case X86::VCVTSS2SDZrr:
5992   case X86::VCVTSS2SDZrm:
5993     return true;
5994   }
5995 
5996   return false;
5997 }
5998 
5999 /// Inform the ExeDepsFix pass how many idle instructions we would like before
6000 /// certain undef register reads.
6001 ///
6002 /// This catches the VCVTSI2SD family of instructions:
6003 ///
6004 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6005 ///
6006 /// We should to be careful *not* to catch VXOR idioms which are presumably
6007 /// handled specially in the pipeline:
6008 ///
6009 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6010 ///
6011 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6012 /// high bits that are passed-through are not live.
6013 unsigned X86InstrInfo::
6014 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
6015                      const TargetRegisterInfo *TRI) const {
6016   if (!hasUndefRegUpdate(MI->getOpcode()))
6017     return 0;
6018 
6019   // Set the OpNum parameter to the first source operand.
6020   OpNum = 1;
6021 
6022   const MachineOperand &MO = MI->getOperand(OpNum);
6023   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
6024     // Use the same magic number as getPartialRegUpdateClearance.
6025     return 16;
6026   }
6027   return 0;
6028 }
6029 
6030 void X86InstrInfo::
6031 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
6032                           const TargetRegisterInfo *TRI) const {
6033   unsigned Reg = MI->getOperand(OpNum).getReg();
6034   // If MI kills this register, the false dependence is already broken.
6035   if (MI->killsRegister(Reg, TRI))
6036     return;
6037 
6038   if (X86::VR128RegClass.contains(Reg)) {
6039     // These instructions are all floating point domain, so xorps is the best
6040     // choice.
6041     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
6042     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
6043       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
6044     MI->addRegisterKilled(Reg, TRI, true);
6045   } else if (X86::VR256RegClass.contains(Reg)) {
6046     // Use vxorps to clear the full ymm register.
6047     // It wants to read and write the xmm sub-register.
6048     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
6049     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
6050       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
6051       .addReg(Reg, RegState::ImplicitDefine);
6052     MI->addRegisterKilled(Reg, TRI, true);
6053   }
6054 }
6055 
6056 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6057     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
6058     MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
6059   // Check switch flag
6060   if (NoFusing)
6061     return nullptr;
6062 
6063   // Unless optimizing for size, don't fold to avoid partial
6064   // register update stalls
6065   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
6066     return nullptr;
6067 
6068   const MachineFrameInfo *MFI = MF.getFrameInfo();
6069   unsigned Size = MFI->getObjectSize(FrameIndex);
6070   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
6071   // If the function stack isn't realigned we don't want to fold instructions
6072   // that need increased alignment.
6073   if (!RI.needsStackRealignment(MF))
6074     Alignment =
6075         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
6076   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6077     unsigned NewOpc = 0;
6078     unsigned RCSize = 0;
6079     switch (MI->getOpcode()) {
6080     default: return nullptr;
6081     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
6082     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6083     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6084     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
6085     }
6086     // Check if it's safe to fold the load. If the size of the object is
6087     // narrower than the load width, then it's not.
6088     if (Size < RCSize)
6089       return nullptr;
6090     // Change to CMPXXri r, 0 first.
6091     MI->setDesc(get(NewOpc));
6092     MI->getOperand(1).ChangeToImmediate(0);
6093   } else if (Ops.size() != 1)
6094     return nullptr;
6095 
6096   return foldMemoryOperandImpl(MF, MI, Ops[0],
6097                                MachineOperand::CreateFI(FrameIndex), InsertPt,
6098                                Size, Alignment, /*AllowCommute=*/true);
6099 }
6100 
6101 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6102 /// because the latter uses contents that wouldn't be defined in the folded
6103 /// version.  For instance, this transformation isn't legal:
6104 ///   movss (%rdi), %xmm0
6105 ///   addps %xmm0, %xmm0
6106 /// ->
6107 ///   addps (%rdi), %xmm0
6108 ///
6109 /// But this one is:
6110 ///   movss (%rdi), %xmm0
6111 ///   addss %xmm0, %xmm0
6112 /// ->
6113 ///   addss (%rdi), %xmm0
6114 ///
6115 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6116                                              const MachineInstr &UserMI,
6117                                              const MachineFunction &MF) {
6118   unsigned Opc = LoadMI.getOpcode();
6119   unsigned UserOpc = UserMI.getOpcode();
6120   unsigned RegSize =
6121       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6122 
6123   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
6124     // These instructions only load 32 bits, we can't fold them if the
6125     // destination register is wider than 32 bits (4 bytes), and its user
6126     // instruction isn't scalar (SS).
6127     switch (UserOpc) {
6128     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
6129     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
6130     case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
6131     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
6132     case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int:
6133     case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int:
6134     case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int:
6135     case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int:
6136     case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int:
6137     case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int:
6138       return false;
6139     default:
6140       return true;
6141     }
6142   }
6143 
6144   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
6145     // These instructions only load 64 bits, we can't fold them if the
6146     // destination register is wider than 64 bits (8 bytes), and its user
6147     // instruction isn't scalar (SD).
6148     switch (UserOpc) {
6149     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
6150     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
6151     case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
6152     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
6153     case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int:
6154     case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int:
6155     case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int:
6156     case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int:
6157     case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int:
6158     case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int:
6159       return false;
6160     default:
6161       return true;
6162     }
6163   }
6164 
6165   return false;
6166 }
6167 
6168 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6169     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
6170     MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
6171   // If loading from a FrameIndex, fold directly from the FrameIndex.
6172   unsigned NumOps = LoadMI->getDesc().getNumOperands();
6173   int FrameIndex;
6174   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6175     if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
6176       return nullptr;
6177     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex);
6178   }
6179 
6180   // Check switch flag
6181   if (NoFusing) return nullptr;
6182 
6183   // Avoid partial register update stalls unless optimizing for size.
6184   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
6185     return nullptr;
6186 
6187   // Determine the alignment of the load.
6188   unsigned Alignment = 0;
6189   if (LoadMI->hasOneMemOperand())
6190     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
6191   else
6192     switch (LoadMI->getOpcode()) {
6193     case X86::AVX2_SETALLONES:
6194     case X86::AVX_SET0:
6195       Alignment = 32;
6196       break;
6197     case X86::V_SET0:
6198     case X86::V_SETALLONES:
6199       Alignment = 16;
6200       break;
6201     case X86::FsFLD0SD:
6202       Alignment = 8;
6203       break;
6204     case X86::FsFLD0SS:
6205       Alignment = 4;
6206       break;
6207     default:
6208       return nullptr;
6209     }
6210   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6211     unsigned NewOpc = 0;
6212     switch (MI->getOpcode()) {
6213     default: return nullptr;
6214     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6215     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6216     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6217     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6218     }
6219     // Change to CMPXXri r, 0 first.
6220     MI->setDesc(get(NewOpc));
6221     MI->getOperand(1).ChangeToImmediate(0);
6222   } else if (Ops.size() != 1)
6223     return nullptr;
6224 
6225   // Make sure the subregisters match.
6226   // Otherwise we risk changing the size of the load.
6227   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
6228     return nullptr;
6229 
6230   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6231   switch (LoadMI->getOpcode()) {
6232   case X86::V_SET0:
6233   case X86::V_SETALLONES:
6234   case X86::AVX2_SETALLONES:
6235   case X86::AVX_SET0:
6236   case X86::FsFLD0SD:
6237   case X86::FsFLD0SS: {
6238     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6239     // Create a constant-pool entry and operands to load from it.
6240 
6241     // Medium and large mode can't fold loads this way.
6242     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6243         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6244       return nullptr;
6245 
6246     // x86-32 PIC requires a PIC base register for constant pools.
6247     unsigned PICBase = 0;
6248     if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
6249       if (Subtarget.is64Bit())
6250         PICBase = X86::RIP;
6251       else
6252         // FIXME: PICBase = getGlobalBaseReg(&MF);
6253         // This doesn't work for several reasons.
6254         // 1. GlobalBaseReg may have been spilled.
6255         // 2. It may not be live at MI.
6256         return nullptr;
6257     }
6258 
6259     // Create a constant-pool entry.
6260     MachineConstantPool &MCP = *MF.getConstantPool();
6261     Type *Ty;
6262     unsigned Opc = LoadMI->getOpcode();
6263     if (Opc == X86::FsFLD0SS)
6264       Ty = Type::getFloatTy(MF.getFunction()->getContext());
6265     else if (Opc == X86::FsFLD0SD)
6266       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
6267     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
6268       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
6269     else
6270       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
6271 
6272     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
6273     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6274                                     Constant::getNullValue(Ty);
6275     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6276 
6277     // Create operands to load from the constant pool entry.
6278     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6279     MOs.push_back(MachineOperand::CreateImm(1));
6280     MOs.push_back(MachineOperand::CreateReg(0, false));
6281     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6282     MOs.push_back(MachineOperand::CreateReg(0, false));
6283     break;
6284   }
6285   default: {
6286     if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
6287       return nullptr;
6288 
6289     // Folding a normal load. Just copy the load's address operands.
6290     MOs.append(LoadMI->operands_begin() + NumOps - X86::AddrNumOperands,
6291                LoadMI->operands_begin() + NumOps);
6292     break;
6293   }
6294   }
6295   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6296                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6297 }
6298 
6299 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
6300                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
6301                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
6302   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
6303     MemOp2RegOpTable.find(MI->getOpcode());
6304   if (I == MemOp2RegOpTable.end())
6305     return false;
6306   unsigned Opc = I->second.first;
6307   unsigned Index = I->second.second & TB_INDEX_MASK;
6308   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6309   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6310   if (UnfoldLoad && !FoldedLoad)
6311     return false;
6312   UnfoldLoad &= FoldedLoad;
6313   if (UnfoldStore && !FoldedStore)
6314     return false;
6315   UnfoldStore &= FoldedStore;
6316 
6317   const MCInstrDesc &MCID = get(Opc);
6318   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6319   // TODO: Check if 32-byte or greater accesses are slow too?
6320   if (!MI->hasOneMemOperand() &&
6321       RC == &X86::VR128RegClass &&
6322       Subtarget.isUnalignedMem16Slow())
6323     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6324     // conservatively assume the address is unaligned. That's bad for
6325     // performance.
6326     return false;
6327   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6328   SmallVector<MachineOperand,2> BeforeOps;
6329   SmallVector<MachineOperand,2> AfterOps;
6330   SmallVector<MachineOperand,4> ImpOps;
6331   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
6332     MachineOperand &Op = MI->getOperand(i);
6333     if (i >= Index && i < Index + X86::AddrNumOperands)
6334       AddrOps.push_back(Op);
6335     else if (Op.isReg() && Op.isImplicit())
6336       ImpOps.push_back(Op);
6337     else if (i < Index)
6338       BeforeOps.push_back(Op);
6339     else if (i > Index)
6340       AfterOps.push_back(Op);
6341   }
6342 
6343   // Emit the load instruction.
6344   if (UnfoldLoad) {
6345     std::pair<MachineInstr::mmo_iterator,
6346               MachineInstr::mmo_iterator> MMOs =
6347       MF.extractLoadMemRefs(MI->memoperands_begin(),
6348                             MI->memoperands_end());
6349     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
6350     if (UnfoldStore) {
6351       // Address operands cannot be marked isKill.
6352       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6353         MachineOperand &MO = NewMIs[0]->getOperand(i);
6354         if (MO.isReg())
6355           MO.setIsKill(false);
6356       }
6357     }
6358   }
6359 
6360   // Emit the data processing instruction.
6361   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
6362   MachineInstrBuilder MIB(MF, DataMI);
6363 
6364   if (FoldedStore)
6365     MIB.addReg(Reg, RegState::Define);
6366   for (MachineOperand &BeforeOp : BeforeOps)
6367     MIB.addOperand(BeforeOp);
6368   if (FoldedLoad)
6369     MIB.addReg(Reg);
6370   for (MachineOperand &AfterOp : AfterOps)
6371     MIB.addOperand(AfterOp);
6372   for (MachineOperand &ImpOp : ImpOps) {
6373     MIB.addReg(ImpOp.getReg(),
6374                getDefRegState(ImpOp.isDef()) |
6375                RegState::Implicit |
6376                getKillRegState(ImpOp.isKill()) |
6377                getDeadRegState(ImpOp.isDead()) |
6378                getUndefRegState(ImpOp.isUndef()));
6379   }
6380   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6381   switch (DataMI->getOpcode()) {
6382   default: break;
6383   case X86::CMP64ri32:
6384   case X86::CMP64ri8:
6385   case X86::CMP32ri:
6386   case X86::CMP32ri8:
6387   case X86::CMP16ri:
6388   case X86::CMP16ri8:
6389   case X86::CMP8ri: {
6390     MachineOperand &MO0 = DataMI->getOperand(0);
6391     MachineOperand &MO1 = DataMI->getOperand(1);
6392     if (MO1.getImm() == 0) {
6393       unsigned NewOpc;
6394       switch (DataMI->getOpcode()) {
6395       default: llvm_unreachable("Unreachable!");
6396       case X86::CMP64ri8:
6397       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6398       case X86::CMP32ri8:
6399       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6400       case X86::CMP16ri8:
6401       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6402       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6403       }
6404       DataMI->setDesc(get(NewOpc));
6405       MO1.ChangeToRegister(MO0.getReg(), false);
6406     }
6407   }
6408   }
6409   NewMIs.push_back(DataMI);
6410 
6411   // Emit the store instruction.
6412   if (UnfoldStore) {
6413     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6414     std::pair<MachineInstr::mmo_iterator,
6415               MachineInstr::mmo_iterator> MMOs =
6416       MF.extractStoreMemRefs(MI->memoperands_begin(),
6417                              MI->memoperands_end());
6418     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
6419   }
6420 
6421   return true;
6422 }
6423 
6424 bool
6425 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6426                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6427   if (!N->isMachineOpcode())
6428     return false;
6429 
6430   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
6431     MemOp2RegOpTable.find(N->getMachineOpcode());
6432   if (I == MemOp2RegOpTable.end())
6433     return false;
6434   unsigned Opc = I->second.first;
6435   unsigned Index = I->second.second & TB_INDEX_MASK;
6436   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6437   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6438   const MCInstrDesc &MCID = get(Opc);
6439   MachineFunction &MF = DAG.getMachineFunction();
6440   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6441   unsigned NumDefs = MCID.NumDefs;
6442   std::vector<SDValue> AddrOps;
6443   std::vector<SDValue> BeforeOps;
6444   std::vector<SDValue> AfterOps;
6445   SDLoc dl(N);
6446   unsigned NumOps = N->getNumOperands();
6447   for (unsigned i = 0; i != NumOps-1; ++i) {
6448     SDValue Op = N->getOperand(i);
6449     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6450       AddrOps.push_back(Op);
6451     else if (i < Index-NumDefs)
6452       BeforeOps.push_back(Op);
6453     else if (i > Index-NumDefs)
6454       AfterOps.push_back(Op);
6455   }
6456   SDValue Chain = N->getOperand(NumOps-1);
6457   AddrOps.push_back(Chain);
6458 
6459   // Emit the load instruction.
6460   SDNode *Load = nullptr;
6461   if (FoldedLoad) {
6462     EVT VT = *RC->vt_begin();
6463     std::pair<MachineInstr::mmo_iterator,
6464               MachineInstr::mmo_iterator> MMOs =
6465       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6466                             cast<MachineSDNode>(N)->memoperands_end());
6467     if (!(*MMOs.first) &&
6468         RC == &X86::VR128RegClass &&
6469         Subtarget.isUnalignedMem16Slow())
6470       // Do not introduce a slow unaligned load.
6471       return false;
6472     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6473     // memory access is slow above.
6474     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6475     bool isAligned = (*MMOs.first) &&
6476                      (*MMOs.first)->getAlignment() >= Alignment;
6477     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
6478                               VT, MVT::Other, AddrOps);
6479     NewNodes.push_back(Load);
6480 
6481     // Preserve memory reference information.
6482     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
6483   }
6484 
6485   // Emit the data processing instruction.
6486   std::vector<EVT> VTs;
6487   const TargetRegisterClass *DstRC = nullptr;
6488   if (MCID.getNumDefs() > 0) {
6489     DstRC = getRegClass(MCID, 0, &RI, MF);
6490     VTs.push_back(*DstRC->vt_begin());
6491   }
6492   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6493     EVT VT = N->getValueType(i);
6494     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6495       VTs.push_back(VT);
6496   }
6497   if (Load)
6498     BeforeOps.push_back(SDValue(Load, 0));
6499   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
6500   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6501   NewNodes.push_back(NewNode);
6502 
6503   // Emit the store instruction.
6504   if (FoldedStore) {
6505     AddrOps.pop_back();
6506     AddrOps.push_back(SDValue(NewNode, 0));
6507     AddrOps.push_back(Chain);
6508     std::pair<MachineInstr::mmo_iterator,
6509               MachineInstr::mmo_iterator> MMOs =
6510       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6511                              cast<MachineSDNode>(N)->memoperands_end());
6512     if (!(*MMOs.first) &&
6513         RC == &X86::VR128RegClass &&
6514         Subtarget.isUnalignedMem16Slow())
6515       // Do not introduce a slow unaligned store.
6516       return false;
6517     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6518     // memory access is slow above.
6519     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6520     bool isAligned = (*MMOs.first) &&
6521                      (*MMOs.first)->getAlignment() >= Alignment;
6522     SDNode *Store =
6523         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6524                            dl, MVT::Other, AddrOps);
6525     NewNodes.push_back(Store);
6526 
6527     // Preserve memory reference information.
6528     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
6529   }
6530 
6531   return true;
6532 }
6533 
6534 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6535                                       bool UnfoldLoad, bool UnfoldStore,
6536                                       unsigned *LoadRegIndex) const {
6537   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
6538     MemOp2RegOpTable.find(Opc);
6539   if (I == MemOp2RegOpTable.end())
6540     return 0;
6541   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6542   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
6543   if (UnfoldLoad && !FoldedLoad)
6544     return 0;
6545   if (UnfoldStore && !FoldedStore)
6546     return 0;
6547   if (LoadRegIndex)
6548     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
6549   return I->second.first;
6550 }
6551 
6552 bool
6553 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6554                                      int64_t &Offset1, int64_t &Offset2) const {
6555   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6556     return false;
6557   unsigned Opc1 = Load1->getMachineOpcode();
6558   unsigned Opc2 = Load2->getMachineOpcode();
6559   switch (Opc1) {
6560   default: return false;
6561   case X86::MOV8rm:
6562   case X86::MOV16rm:
6563   case X86::MOV32rm:
6564   case X86::MOV64rm:
6565   case X86::LD_Fp32m:
6566   case X86::LD_Fp64m:
6567   case X86::LD_Fp80m:
6568   case X86::MOVSSrm:
6569   case X86::MOVSDrm:
6570   case X86::MMX_MOVD64rm:
6571   case X86::MMX_MOVQ64rm:
6572   case X86::FsMOVAPSrm:
6573   case X86::FsMOVAPDrm:
6574   case X86::MOVAPSrm:
6575   case X86::MOVUPSrm:
6576   case X86::MOVAPDrm:
6577   case X86::MOVDQArm:
6578   case X86::MOVDQUrm:
6579   // AVX load instructions
6580   case X86::VMOVSSrm:
6581   case X86::VMOVSDrm:
6582   case X86::FsVMOVAPSrm:
6583   case X86::FsVMOVAPDrm:
6584   case X86::VMOVAPSrm:
6585   case X86::VMOVUPSrm:
6586   case X86::VMOVAPDrm:
6587   case X86::VMOVDQArm:
6588   case X86::VMOVDQUrm:
6589   case X86::VMOVAPSYrm:
6590   case X86::VMOVUPSYrm:
6591   case X86::VMOVAPDYrm:
6592   case X86::VMOVDQAYrm:
6593   case X86::VMOVDQUYrm:
6594     break;
6595   }
6596   switch (Opc2) {
6597   default: return false;
6598   case X86::MOV8rm:
6599   case X86::MOV16rm:
6600   case X86::MOV32rm:
6601   case X86::MOV64rm:
6602   case X86::LD_Fp32m:
6603   case X86::LD_Fp64m:
6604   case X86::LD_Fp80m:
6605   case X86::MOVSSrm:
6606   case X86::MOVSDrm:
6607   case X86::MMX_MOVD64rm:
6608   case X86::MMX_MOVQ64rm:
6609   case X86::FsMOVAPSrm:
6610   case X86::FsMOVAPDrm:
6611   case X86::MOVAPSrm:
6612   case X86::MOVUPSrm:
6613   case X86::MOVAPDrm:
6614   case X86::MOVDQArm:
6615   case X86::MOVDQUrm:
6616   // AVX load instructions
6617   case X86::VMOVSSrm:
6618   case X86::VMOVSDrm:
6619   case X86::FsVMOVAPSrm:
6620   case X86::FsVMOVAPDrm:
6621   case X86::VMOVAPSrm:
6622   case X86::VMOVUPSrm:
6623   case X86::VMOVAPDrm:
6624   case X86::VMOVDQArm:
6625   case X86::VMOVDQUrm:
6626   case X86::VMOVAPSYrm:
6627   case X86::VMOVUPSYrm:
6628   case X86::VMOVAPDYrm:
6629   case X86::VMOVDQAYrm:
6630   case X86::VMOVDQUYrm:
6631     break;
6632   }
6633 
6634   // Check if chain operands and base addresses match.
6635   if (Load1->getOperand(0) != Load2->getOperand(0) ||
6636       Load1->getOperand(5) != Load2->getOperand(5))
6637     return false;
6638   // Segment operands should match as well.
6639   if (Load1->getOperand(4) != Load2->getOperand(4))
6640     return false;
6641   // Scale should be 1, Index should be Reg0.
6642   if (Load1->getOperand(1) == Load2->getOperand(1) &&
6643       Load1->getOperand(2) == Load2->getOperand(2)) {
6644     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6645       return false;
6646 
6647     // Now let's examine the displacements.
6648     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6649         isa<ConstantSDNode>(Load2->getOperand(3))) {
6650       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6651       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6652       return true;
6653     }
6654   }
6655   return false;
6656 }
6657 
6658 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6659                                            int64_t Offset1, int64_t Offset2,
6660                                            unsigned NumLoads) const {
6661   assert(Offset2 > Offset1);
6662   if ((Offset2 - Offset1) / 8 > 64)
6663     return false;
6664 
6665   unsigned Opc1 = Load1->getMachineOpcode();
6666   unsigned Opc2 = Load2->getMachineOpcode();
6667   if (Opc1 != Opc2)
6668     return false;  // FIXME: overly conservative?
6669 
6670   switch (Opc1) {
6671   default: break;
6672   case X86::LD_Fp32m:
6673   case X86::LD_Fp64m:
6674   case X86::LD_Fp80m:
6675   case X86::MMX_MOVD64rm:
6676   case X86::MMX_MOVQ64rm:
6677     return false;
6678   }
6679 
6680   EVT VT = Load1->getValueType(0);
6681   switch (VT.getSimpleVT().SimpleTy) {
6682   default:
6683     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6684     // have 16 of them to play with.
6685     if (Subtarget.is64Bit()) {
6686       if (NumLoads >= 3)
6687         return false;
6688     } else if (NumLoads) {
6689       return false;
6690     }
6691     break;
6692   case MVT::i8:
6693   case MVT::i16:
6694   case MVT::i32:
6695   case MVT::i64:
6696   case MVT::f32:
6697   case MVT::f64:
6698     if (NumLoads)
6699       return false;
6700     break;
6701   }
6702 
6703   return true;
6704 }
6705 
6706 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
6707                                           MachineInstr *Second) const {
6708   // Check if this processor supports macro-fusion. Since this is a minor
6709   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6710   // proxy for SandyBridge+.
6711   if (!Subtarget.hasAVX())
6712     return false;
6713 
6714   enum {
6715     FuseTest,
6716     FuseCmp,
6717     FuseInc
6718   } FuseKind;
6719 
6720   switch(Second->getOpcode()) {
6721   default:
6722     return false;
6723   case X86::JE_1:
6724   case X86::JNE_1:
6725   case X86::JL_1:
6726   case X86::JLE_1:
6727   case X86::JG_1:
6728   case X86::JGE_1:
6729     FuseKind = FuseInc;
6730     break;
6731   case X86::JB_1:
6732   case X86::JBE_1:
6733   case X86::JA_1:
6734   case X86::JAE_1:
6735     FuseKind = FuseCmp;
6736     break;
6737   case X86::JS_1:
6738   case X86::JNS_1:
6739   case X86::JP_1:
6740   case X86::JNP_1:
6741   case X86::JO_1:
6742   case X86::JNO_1:
6743     FuseKind = FuseTest;
6744     break;
6745   }
6746   switch (First->getOpcode()) {
6747   default:
6748     return false;
6749   case X86::TEST8rr:
6750   case X86::TEST16rr:
6751   case X86::TEST32rr:
6752   case X86::TEST64rr:
6753   case X86::TEST8ri:
6754   case X86::TEST16ri:
6755   case X86::TEST32ri:
6756   case X86::TEST32i32:
6757   case X86::TEST64i32:
6758   case X86::TEST64ri32:
6759   case X86::TEST8rm:
6760   case X86::TEST16rm:
6761   case X86::TEST32rm:
6762   case X86::TEST64rm:
6763   case X86::TEST8ri_NOREX:
6764   case X86::AND16i16:
6765   case X86::AND16ri:
6766   case X86::AND16ri8:
6767   case X86::AND16rm:
6768   case X86::AND16rr:
6769   case X86::AND32i32:
6770   case X86::AND32ri:
6771   case X86::AND32ri8:
6772   case X86::AND32rm:
6773   case X86::AND32rr:
6774   case X86::AND64i32:
6775   case X86::AND64ri32:
6776   case X86::AND64ri8:
6777   case X86::AND64rm:
6778   case X86::AND64rr:
6779   case X86::AND8i8:
6780   case X86::AND8ri:
6781   case X86::AND8rm:
6782   case X86::AND8rr:
6783     return true;
6784   case X86::CMP16i16:
6785   case X86::CMP16ri:
6786   case X86::CMP16ri8:
6787   case X86::CMP16rm:
6788   case X86::CMP16rr:
6789   case X86::CMP32i32:
6790   case X86::CMP32ri:
6791   case X86::CMP32ri8:
6792   case X86::CMP32rm:
6793   case X86::CMP32rr:
6794   case X86::CMP64i32:
6795   case X86::CMP64ri32:
6796   case X86::CMP64ri8:
6797   case X86::CMP64rm:
6798   case X86::CMP64rr:
6799   case X86::CMP8i8:
6800   case X86::CMP8ri:
6801   case X86::CMP8rm:
6802   case X86::CMP8rr:
6803   case X86::ADD16i16:
6804   case X86::ADD16ri:
6805   case X86::ADD16ri8:
6806   case X86::ADD16ri8_DB:
6807   case X86::ADD16ri_DB:
6808   case X86::ADD16rm:
6809   case X86::ADD16rr:
6810   case X86::ADD16rr_DB:
6811   case X86::ADD32i32:
6812   case X86::ADD32ri:
6813   case X86::ADD32ri8:
6814   case X86::ADD32ri8_DB:
6815   case X86::ADD32ri_DB:
6816   case X86::ADD32rm:
6817   case X86::ADD32rr:
6818   case X86::ADD32rr_DB:
6819   case X86::ADD64i32:
6820   case X86::ADD64ri32:
6821   case X86::ADD64ri32_DB:
6822   case X86::ADD64ri8:
6823   case X86::ADD64ri8_DB:
6824   case X86::ADD64rm:
6825   case X86::ADD64rr:
6826   case X86::ADD64rr_DB:
6827   case X86::ADD8i8:
6828   case X86::ADD8mi:
6829   case X86::ADD8mr:
6830   case X86::ADD8ri:
6831   case X86::ADD8rm:
6832   case X86::ADD8rr:
6833   case X86::SUB16i16:
6834   case X86::SUB16ri:
6835   case X86::SUB16ri8:
6836   case X86::SUB16rm:
6837   case X86::SUB16rr:
6838   case X86::SUB32i32:
6839   case X86::SUB32ri:
6840   case X86::SUB32ri8:
6841   case X86::SUB32rm:
6842   case X86::SUB32rr:
6843   case X86::SUB64i32:
6844   case X86::SUB64ri32:
6845   case X86::SUB64ri8:
6846   case X86::SUB64rm:
6847   case X86::SUB64rr:
6848   case X86::SUB8i8:
6849   case X86::SUB8ri:
6850   case X86::SUB8rm:
6851   case X86::SUB8rr:
6852     return FuseKind == FuseCmp || FuseKind == FuseInc;
6853   case X86::INC16r:
6854   case X86::INC32r:
6855   case X86::INC64r:
6856   case X86::INC8r:
6857   case X86::DEC16r:
6858   case X86::DEC32r:
6859   case X86::DEC64r:
6860   case X86::DEC8r:
6861     return FuseKind == FuseInc;
6862   }
6863 }
6864 
6865 bool X86InstrInfo::
6866 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6867   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6868   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6869   Cond[0].setImm(GetOppositeBranchCondition(CC));
6870   return false;
6871 }
6872 
6873 bool X86InstrInfo::
6874 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6875   // FIXME: Return false for x87 stack register classes for now. We can't
6876   // allow any loads of these registers before FpGet_ST0_80.
6877   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6878            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
6879 }
6880 
6881 /// Return a virtual register initialized with the
6882 /// the global base register value. Output instructions required to
6883 /// initialize the register in the function entry block, if necessary.
6884 ///
6885 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6886 ///
6887 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6888   assert(!Subtarget.is64Bit() &&
6889          "X86-64 PIC uses RIP relative addressing");
6890 
6891   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6892   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6893   if (GlobalBaseReg != 0)
6894     return GlobalBaseReg;
6895 
6896   // Create the register. The code to initialize it is inserted
6897   // later, by the CGBR pass (below).
6898   MachineRegisterInfo &RegInfo = MF->getRegInfo();
6899   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
6900   X86FI->setGlobalBaseReg(GlobalBaseReg);
6901   return GlobalBaseReg;
6902 }
6903 
6904 // These are the replaceable SSE instructions. Some of these have Int variants
6905 // that we don't include here. We don't want to replace instructions selected
6906 // by intrinsics.
6907 static const uint16_t ReplaceableInstrs[][3] = {
6908   //PackedSingle     PackedDouble    PackedInt
6909   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
6910   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
6911   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
6912   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
6913   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
6914   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr  },
6915   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
6916   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
6917   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
6918   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
6919   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
6920   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
6921   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
6922   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
6923   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
6924   // AVX 128-bit support
6925   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
6926   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
6927   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
6928   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
6929   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
6930   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr  },
6931   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6932   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
6933   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
6934   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
6935   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
6936   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
6937   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
6938   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
6939   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
6940   // AVX 256-bit support
6941   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
6942   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
6943   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
6944   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
6945   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
6946   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
6947 };
6948 
6949 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6950   //PackedSingle       PackedDouble       PackedInt
6951   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
6952   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
6953   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
6954   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
6955   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
6956   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
6957   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
6958   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
6959   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6960   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6961   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
6962   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
6963   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
6964   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
6965   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6966   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6967   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6968   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6969   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6970   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
6971 };
6972 
6973 // FIXME: Some shuffle and unpack instructions have equivalents in different
6974 // domains, but they require a bit more work than just switching opcodes.
6975 
6976 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
6977   for (const uint16_t (&Row)[3] : ReplaceableInstrs)
6978     if (Row[domain-1] == opcode)
6979       return Row;
6980   return nullptr;
6981 }
6982 
6983 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
6984   for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
6985     if (Row[domain-1] == opcode)
6986       return Row;
6987   return nullptr;
6988 }
6989 
6990 std::pair<uint16_t, uint16_t>
6991 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
6992   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6993   bool hasAVX2 = Subtarget.hasAVX2();
6994   uint16_t validDomains = 0;
6995   if (domain && lookup(MI->getOpcode(), domain))
6996     validDomains = 0xe;
6997   else if (domain && lookupAVX2(MI->getOpcode(), domain))
6998     validDomains = hasAVX2 ? 0xe : 0x6;
6999   return std::make_pair(domain, validDomains);
7000 }
7001 
7002 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
7003   assert(Domain>0 && Domain<4 && "Invalid execution domain");
7004   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7005   assert(dom && "Not an SSE instruction");
7006   const uint16_t *table = lookup(MI->getOpcode(), dom);
7007   if (!table) { // try the other table
7008     assert((Subtarget.hasAVX2() || Domain < 3) &&
7009            "256-bit vector operations only available in AVX2");
7010     table = lookupAVX2(MI->getOpcode(), dom);
7011   }
7012   assert(table && "Cannot change domain");
7013   MI->setDesc(get(table[Domain-1]));
7014 }
7015 
7016 /// Return the noop instruction to use for a noop.
7017 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7018   NopInst.setOpcode(X86::NOOP);
7019 }
7020 
7021 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
7022 // In particular, getJumpInstrTableEntryBound must always return an upper bound
7023 // on the encoding lengths of the instructions generated by
7024 // getUnconditionalBranch and getTrap.
7025 void X86InstrInfo::getUnconditionalBranch(
7026     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
7027   Branch.setOpcode(X86::JMP_1);
7028   Branch.addOperand(MCOperand::createExpr(BranchTarget));
7029 }
7030 
7031 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
7032 // In particular, getJumpInstrTableEntryBound must always return an upper bound
7033 // on the encoding lengths of the instructions generated by
7034 // getUnconditionalBranch and getTrap.
7035 void X86InstrInfo::getTrap(MCInst &MI) const {
7036   MI.setOpcode(X86::TRAP);
7037 }
7038 
7039 // See getTrap and getUnconditionalBranch for conditions on the value returned
7040 // by this function.
7041 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7042   // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7043   // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7044   return 5;
7045 }
7046 
7047 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7048   switch (opc) {
7049   default: return false;
7050   case X86::DIVSDrm:
7051   case X86::DIVSDrm_Int:
7052   case X86::DIVSDrr:
7053   case X86::DIVSDrr_Int:
7054   case X86::DIVSSrm:
7055   case X86::DIVSSrm_Int:
7056   case X86::DIVSSrr:
7057   case X86::DIVSSrr_Int:
7058   case X86::SQRTPDm:
7059   case X86::SQRTPDr:
7060   case X86::SQRTPSm:
7061   case X86::SQRTPSr:
7062   case X86::SQRTSDm:
7063   case X86::SQRTSDm_Int:
7064   case X86::SQRTSDr:
7065   case X86::SQRTSDr_Int:
7066   case X86::SQRTSSm:
7067   case X86::SQRTSSm_Int:
7068   case X86::SQRTSSr:
7069   case X86::SQRTSSr_Int:
7070   // AVX instructions with high latency
7071   case X86::VDIVSDrm:
7072   case X86::VDIVSDrm_Int:
7073   case X86::VDIVSDrr:
7074   case X86::VDIVSDrr_Int:
7075   case X86::VDIVSSrm:
7076   case X86::VDIVSSrm_Int:
7077   case X86::VDIVSSrr:
7078   case X86::VDIVSSrr_Int:
7079   case X86::VSQRTPDm:
7080   case X86::VSQRTPDr:
7081   case X86::VSQRTPSm:
7082   case X86::VSQRTPSr:
7083   case X86::VSQRTSDm:
7084   case X86::VSQRTSDm_Int:
7085   case X86::VSQRTSDr:
7086   case X86::VSQRTSSm:
7087   case X86::VSQRTSSm_Int:
7088   case X86::VSQRTSSr:
7089   case X86::VSQRTPDZm:
7090   case X86::VSQRTPDZr:
7091   case X86::VSQRTPSZm:
7092   case X86::VSQRTPSZr:
7093   case X86::VSQRTSDZm:
7094   case X86::VSQRTSDZm_Int:
7095   case X86::VSQRTSDZr:
7096   case X86::VSQRTSSZm_Int:
7097   case X86::VSQRTSSZr:
7098   case X86::VSQRTSSZm:
7099   case X86::VDIVSDZrm:
7100   case X86::VDIVSDZrr:
7101   case X86::VDIVSSZrm:
7102   case X86::VDIVSSZrr:
7103 
7104   case X86::VGATHERQPSZrm:
7105   case X86::VGATHERQPDZrm:
7106   case X86::VGATHERDPDZrm:
7107   case X86::VGATHERDPSZrm:
7108   case X86::VPGATHERQDZrm:
7109   case X86::VPGATHERQQZrm:
7110   case X86::VPGATHERDDZrm:
7111   case X86::VPGATHERDQZrm:
7112   case X86::VSCATTERQPDZmr:
7113   case X86::VSCATTERQPSZmr:
7114   case X86::VSCATTERDPDZmr:
7115   case X86::VSCATTERDPSZmr:
7116   case X86::VPSCATTERQDZmr:
7117   case X86::VPSCATTERQQZmr:
7118   case X86::VPSCATTERDDZmr:
7119   case X86::VPSCATTERDQZmr:
7120     return true;
7121   }
7122 }
7123 
7124 bool X86InstrInfo::
7125 hasHighOperandLatency(const TargetSchedModel &SchedModel,
7126                       const MachineRegisterInfo *MRI,
7127                       const MachineInstr *DefMI, unsigned DefIdx,
7128                       const MachineInstr *UseMI, unsigned UseIdx) const {
7129   return isHighLatencyDef(DefMI->getOpcode());
7130 }
7131 
7132 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7133                                            const MachineBasicBlock *MBB) const {
7134   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7135          "Reassociation needs binary operators");
7136 
7137   // Integer binary math/logic instructions have a third source operand:
7138   // the EFLAGS register. That operand must be both defined here and never
7139   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7140   // not change anything because rearranging the operands could affect other
7141   // instructions that depend on the exact status flags (zero, sign, etc.)
7142   // that are set by using these particular operands with this operation.
7143   if (Inst.getNumOperands() == 4) {
7144     assert(Inst.getOperand(3).isReg() &&
7145            Inst.getOperand(3).getReg() == X86::EFLAGS &&
7146            "Unexpected operand in reassociable instruction");
7147     if (!Inst.getOperand(3).isDead())
7148       return false;
7149   }
7150 
7151   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7152 }
7153 
7154 // TODO: There are many more machine instruction opcodes to match:
7155 //       1. Other data types (integer, vectors)
7156 //       2. Other math / logic operations (xor, or)
7157 //       3. Other forms of the same operation (intrinsics and other variants)
7158 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7159   switch (Inst.getOpcode()) {
7160   case X86::AND8rr:
7161   case X86::AND16rr:
7162   case X86::AND32rr:
7163   case X86::AND64rr:
7164   case X86::OR8rr:
7165   case X86::OR16rr:
7166   case X86::OR32rr:
7167   case X86::OR64rr:
7168   case X86::XOR8rr:
7169   case X86::XOR16rr:
7170   case X86::XOR32rr:
7171   case X86::XOR64rr:
7172   case X86::IMUL16rr:
7173   case X86::IMUL32rr:
7174   case X86::IMUL64rr:
7175   case X86::PANDrr:
7176   case X86::PORrr:
7177   case X86::PXORrr:
7178   case X86::VPANDrr:
7179   case X86::VPANDYrr:
7180   case X86::VPORrr:
7181   case X86::VPORYrr:
7182   case X86::VPXORrr:
7183   case X86::VPXORYrr:
7184   // Normal min/max instructions are not commutative because of NaN and signed
7185   // zero semantics, but these are. Thus, there's no need to check for global
7186   // relaxed math; the instructions themselves have the properties we need.
7187   case X86::MAXCPDrr:
7188   case X86::MAXCPSrr:
7189   case X86::MAXCSDrr:
7190   case X86::MAXCSSrr:
7191   case X86::MINCPDrr:
7192   case X86::MINCPSrr:
7193   case X86::MINCSDrr:
7194   case X86::MINCSSrr:
7195   case X86::VMAXCPDrr:
7196   case X86::VMAXCPSrr:
7197   case X86::VMAXCPDYrr:
7198   case X86::VMAXCPSYrr:
7199   case X86::VMAXCSDrr:
7200   case X86::VMAXCSSrr:
7201   case X86::VMINCPDrr:
7202   case X86::VMINCPSrr:
7203   case X86::VMINCPDYrr:
7204   case X86::VMINCPSYrr:
7205   case X86::VMINCSDrr:
7206   case X86::VMINCSSrr:
7207     return true;
7208   case X86::ADDPDrr:
7209   case X86::ADDPSrr:
7210   case X86::ADDSDrr:
7211   case X86::ADDSSrr:
7212   case X86::MULPDrr:
7213   case X86::MULPSrr:
7214   case X86::MULSDrr:
7215   case X86::MULSSrr:
7216   case X86::VADDPDrr:
7217   case X86::VADDPSrr:
7218   case X86::VADDPDYrr:
7219   case X86::VADDPSYrr:
7220   case X86::VADDSDrr:
7221   case X86::VADDSSrr:
7222   case X86::VMULPDrr:
7223   case X86::VMULPSrr:
7224   case X86::VMULPDYrr:
7225   case X86::VMULPSYrr:
7226   case X86::VMULSDrr:
7227   case X86::VMULSSrr:
7228     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7229   default:
7230     return false;
7231   }
7232 }
7233 
7234 /// This is an architecture-specific helper function of reassociateOps.
7235 /// Set special operand attributes for new instructions after reassociation.
7236 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7237                                          MachineInstr &OldMI2,
7238                                          MachineInstr &NewMI1,
7239                                          MachineInstr &NewMI2) const {
7240   // Integer instructions define an implicit EFLAGS source register operand as
7241   // the third source (fourth total) operand.
7242   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7243     return;
7244 
7245   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7246          "Unexpected instruction type for reassociation");
7247 
7248   MachineOperand &OldOp1 = OldMI1.getOperand(3);
7249   MachineOperand &OldOp2 = OldMI2.getOperand(3);
7250   MachineOperand &NewOp1 = NewMI1.getOperand(3);
7251   MachineOperand &NewOp2 = NewMI2.getOperand(3);
7252 
7253   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7254          "Must have dead EFLAGS operand in reassociable instruction");
7255   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7256          "Must have dead EFLAGS operand in reassociable instruction");
7257 
7258   (void)OldOp1;
7259   (void)OldOp2;
7260 
7261   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7262          "Unexpected operand in reassociable instruction");
7263   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7264          "Unexpected operand in reassociable instruction");
7265 
7266   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7267   // of this pass or other passes. The EFLAGS operands must be dead in these new
7268   // instructions because the EFLAGS operands in the original instructions must
7269   // be dead in order for reassociation to occur.
7270   NewOp1.setIsDead();
7271   NewOp2.setIsDead();
7272 }
7273 
7274 std::pair<unsigned, unsigned>
7275 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7276   return std::make_pair(TF, 0u);
7277 }
7278 
7279 ArrayRef<std::pair<unsigned, const char *>>
7280 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7281   using namespace X86II;
7282   static const std::pair<unsigned, const char *> TargetFlags[] = {
7283       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7284       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7285       {MO_GOT, "x86-got"},
7286       {MO_GOTOFF, "x86-gotoff"},
7287       {MO_GOTPCREL, "x86-gotpcrel"},
7288       {MO_PLT, "x86-plt"},
7289       {MO_TLSGD, "x86-tlsgd"},
7290       {MO_TLSLD, "x86-tlsld"},
7291       {MO_TLSLDM, "x86-tlsldm"},
7292       {MO_GOTTPOFF, "x86-gottpoff"},
7293       {MO_INDNTPOFF, "x86-indntpoff"},
7294       {MO_TPOFF, "x86-tpoff"},
7295       {MO_DTPOFF, "x86-dtpoff"},
7296       {MO_NTPOFF, "x86-ntpoff"},
7297       {MO_GOTNTPOFF, "x86-gotntpoff"},
7298       {MO_DLLIMPORT, "x86-dllimport"},
7299       {MO_DARWIN_STUB, "x86-darwin-stub"},
7300       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7301       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7302       {MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, "x86-darwin-hidden-nonlazy-pic-base"},
7303       {MO_TLVP, "x86-tlvp"},
7304       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7305       {MO_SECREL, "x86-secrel"}};
7306   return makeArrayRef(TargetFlags);
7307 }
7308 
7309 namespace {
7310   /// Create Global Base Reg pass. This initializes the PIC
7311   /// global base register for x86-32.
7312   struct CGBR : public MachineFunctionPass {
7313     static char ID;
7314     CGBR() : MachineFunctionPass(ID) {}
7315 
7316     bool runOnMachineFunction(MachineFunction &MF) override {
7317       const X86TargetMachine *TM =
7318         static_cast<const X86TargetMachine *>(&MF.getTarget());
7319       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7320 
7321       // Don't do anything if this is 64-bit as 64-bit PIC
7322       // uses RIP relative addressing.
7323       if (STI.is64Bit())
7324         return false;
7325 
7326       // Only emit a global base reg in PIC mode.
7327       if (TM->getRelocationModel() != Reloc::PIC_)
7328         return false;
7329 
7330       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7331       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7332 
7333       // If we didn't need a GlobalBaseReg, don't insert code.
7334       if (GlobalBaseReg == 0)
7335         return false;
7336 
7337       // Insert the set of GlobalBaseReg into the first MBB of the function
7338       MachineBasicBlock &FirstMBB = MF.front();
7339       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7340       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7341       MachineRegisterInfo &RegInfo = MF.getRegInfo();
7342       const X86InstrInfo *TII = STI.getInstrInfo();
7343 
7344       unsigned PC;
7345       if (STI.isPICStyleGOT())
7346         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7347       else
7348         PC = GlobalBaseReg;
7349 
7350       // Operand of MovePCtoStack is completely ignored by asm printer. It's
7351       // only used in JIT code emission as displacement to pc.
7352       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7353 
7354       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
7355       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7356       if (STI.isPICStyleGOT()) {
7357         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
7358         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7359           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7360                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
7361       }
7362 
7363       return true;
7364     }
7365 
7366     const char *getPassName() const override {
7367       return "X86 PIC Global Base Reg Initialization";
7368     }
7369 
7370     void getAnalysisUsage(AnalysisUsage &AU) const override {
7371       AU.setPreservesCFG();
7372       MachineFunctionPass::getAnalysisUsage(AU);
7373     }
7374   };
7375 }
7376 
7377 char CGBR::ID = 0;
7378 FunctionPass*
7379 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
7380 
7381 namespace {
7382   struct LDTLSCleanup : public MachineFunctionPass {
7383     static char ID;
7384     LDTLSCleanup() : MachineFunctionPass(ID) {}
7385 
7386     bool runOnMachineFunction(MachineFunction &MF) override {
7387       if (skipFunction(*MF.getFunction()))
7388         return false;
7389 
7390       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
7391       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7392         // No point folding accesses if there isn't at least two.
7393         return false;
7394       }
7395 
7396       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7397       return VisitNode(DT->getRootNode(), 0);
7398     }
7399 
7400     // Visit the dominator subtree rooted at Node in pre-order.
7401     // If TLSBaseAddrReg is non-null, then use that to replace any
7402     // TLS_base_addr instructions. Otherwise, create the register
7403     // when the first such instruction is seen, and then use it
7404     // as we encounter more instructions.
7405     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7406       MachineBasicBlock *BB = Node->getBlock();
7407       bool Changed = false;
7408 
7409       // Traverse the current block.
7410       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7411            ++I) {
7412         switch (I->getOpcode()) {
7413           case X86::TLS_base_addr32:
7414           case X86::TLS_base_addr64:
7415             if (TLSBaseAddrReg)
7416               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
7417             else
7418               I = SetRegister(I, &TLSBaseAddrReg);
7419             Changed = true;
7420             break;
7421           default:
7422             break;
7423         }
7424       }
7425 
7426       // Visit the children of this block in the dominator tree.
7427       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7428            I != E; ++I) {
7429         Changed |= VisitNode(*I, TLSBaseAddrReg);
7430       }
7431 
7432       return Changed;
7433     }
7434 
7435     // Replace the TLS_base_addr instruction I with a copy from
7436     // TLSBaseAddrReg, returning the new instruction.
7437     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
7438                                          unsigned TLSBaseAddrReg) {
7439       MachineFunction *MF = I->getParent()->getParent();
7440       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7441       const bool is64Bit = STI.is64Bit();
7442       const X86InstrInfo *TII = STI.getInstrInfo();
7443 
7444       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7445       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
7446                                    TII->get(TargetOpcode::COPY),
7447                                    is64Bit ? X86::RAX : X86::EAX)
7448                                    .addReg(TLSBaseAddrReg);
7449 
7450       // Erase the TLS_base_addr instruction.
7451       I->eraseFromParent();
7452 
7453       return Copy;
7454     }
7455 
7456     // Create a virtal register in *TLSBaseAddrReg, and populate it by
7457     // inserting a copy instruction after I. Returns the new instruction.
7458     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
7459       MachineFunction *MF = I->getParent()->getParent();
7460       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7461       const bool is64Bit = STI.is64Bit();
7462       const X86InstrInfo *TII = STI.getInstrInfo();
7463 
7464       // Create a virtual register for the TLS base address.
7465       MachineRegisterInfo &RegInfo = MF->getRegInfo();
7466       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7467                                                       ? &X86::GR64RegClass
7468                                                       : &X86::GR32RegClass);
7469 
7470       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7471       MachineInstr *Next = I->getNextNode();
7472       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
7473                                    TII->get(TargetOpcode::COPY),
7474                                    *TLSBaseAddrReg)
7475                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
7476 
7477       return Copy;
7478     }
7479 
7480     const char *getPassName() const override {
7481       return "Local Dynamic TLS Access Clean-up";
7482     }
7483 
7484     void getAnalysisUsage(AnalysisUsage &AU) const override {
7485       AU.setPreservesCFG();
7486       AU.addRequired<MachineDominatorTree>();
7487       MachineFunctionPass::getAnalysisUsage(AU);
7488     }
7489   };
7490 }
7491 
7492 char LDTLSCleanup::ID = 0;
7493 FunctionPass*
7494 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
7495