1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "x86-instr-info"
45 
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
48 
49 static cl::opt<bool>
50     NoFusing("disable-spill-fusing",
51              cl::desc("Disable fusing of spill code into instructions"),
52              cl::Hidden);
53 static cl::opt<bool>
54 PrintFailedFusing("print-failed-fuse-candidates",
55                   cl::desc("Print instructions that the allocator wants to"
56                            " fuse, but the X86 backend currently can't"),
57                   cl::Hidden);
58 static cl::opt<bool>
59 ReMatPICStubLoad("remat-pic-stub-load",
60                  cl::desc("Re-materialize load from stub in PIC mode"),
61                  cl::init(false), cl::Hidden);
62 static cl::opt<unsigned>
63 PartialRegUpdateClearance("partial-reg-update-clearance",
64                           cl::desc("Clearance between two register writes "
65                                    "for inserting XOR to avoid partial "
66                                    "register update"),
67                           cl::init(64), cl::Hidden);
68 static cl::opt<unsigned>
69 UndefRegClearance("undef-reg-clearance",
70                   cl::desc("How many idle instructions we would like before "
71                            "certain undef register reads"),
72                   cl::init(128), cl::Hidden);
73 
74 enum {
75   // Select which memory operand is being unfolded.
76   // (stored in bits 0 - 3)
77   TB_INDEX_0    = 0,
78   TB_INDEX_1    = 1,
79   TB_INDEX_2    = 2,
80   TB_INDEX_3    = 3,
81   TB_INDEX_4    = 4,
82   TB_INDEX_MASK = 0xf,
83 
84   // Do not insert the reverse map (MemOp -> RegOp) into the table.
85   // This may be needed because there is a many -> one mapping.
86   TB_NO_REVERSE   = 1 << 4,
87 
88   // Do not insert the forward map (RegOp -> MemOp) into the table.
89   // This is needed for Native Client, which prohibits branch
90   // instructions from using a memory operand.
91   TB_NO_FORWARD   = 1 << 5,
92 
93   TB_FOLDED_LOAD  = 1 << 6,
94   TB_FOLDED_STORE = 1 << 7,
95 
96   // Minimum alignment required for load/store.
97   // Used for RegOp->MemOp conversion.
98   // (stored in bits 8 - 15)
99   TB_ALIGN_SHIFT = 8,
100   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
101   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
102   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
103   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
104   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
105 };
106 
107 struct X86MemoryFoldTableEntry {
108   uint16_t RegOp;
109   uint16_t MemOp;
110   uint16_t Flags;
111 };
112 
113 // Pin the vtable to this file.
114 void X86InstrInfo::anchor() {}
115 
116 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
117     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
118                                                : X86::ADJCALLSTACKDOWN32),
119                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
120                                                : X86::ADJCALLSTACKUP32),
121                       X86::CATCHRET,
122                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
123       Subtarget(STI), RI(STI.getTargetTriple()) {
124 
125   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
126     { X86::ADC16ri,     X86::ADC16mi,    0 },
127     { X86::ADC16ri8,    X86::ADC16mi8,   0 },
128     { X86::ADC16rr,     X86::ADC16mr,    0 },
129     { X86::ADC32ri,     X86::ADC32mi,    0 },
130     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
131     { X86::ADC32rr,     X86::ADC32mr,    0 },
132     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
133     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
134     { X86::ADC64rr,     X86::ADC64mr,    0 },
135     { X86::ADC8ri,      X86::ADC8mi,     0 },
136     { X86::ADC8ri8,     X86::ADC8mi8,    0 },
137     { X86::ADC8rr,      X86::ADC8mr,     0 },
138     { X86::ADD16ri,     X86::ADD16mi,    0 },
139     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
140     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
141     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
142     { X86::ADD16rr,     X86::ADD16mr,    0 },
143     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
144     { X86::ADD32ri,     X86::ADD32mi,    0 },
145     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
146     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
147     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
148     { X86::ADD32rr,     X86::ADD32mr,    0 },
149     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
150     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
151     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
152     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
153     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
154     { X86::ADD64rr,     X86::ADD64mr,    0 },
155     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
156     { X86::ADD8ri,      X86::ADD8mi,     0 },
157     { X86::ADD8ri8,     X86::ADD8mi8,    0 },
158     { X86::ADD8rr,      X86::ADD8mr,     0 },
159     { X86::AND16ri,     X86::AND16mi,    0 },
160     { X86::AND16ri8,    X86::AND16mi8,   0 },
161     { X86::AND16rr,     X86::AND16mr,    0 },
162     { X86::AND32ri,     X86::AND32mi,    0 },
163     { X86::AND32ri8,    X86::AND32mi8,   0 },
164     { X86::AND32rr,     X86::AND32mr,    0 },
165     { X86::AND64ri32,   X86::AND64mi32,  0 },
166     { X86::AND64ri8,    X86::AND64mi8,   0 },
167     { X86::AND64rr,     X86::AND64mr,    0 },
168     { X86::AND8ri,      X86::AND8mi,     0 },
169     { X86::AND8ri8,     X86::AND8mi8,    0 },
170     { X86::AND8rr,      X86::AND8mr,     0 },
171     { X86::BTC16ri8,    X86::BTC16mi8,   0 },
172     { X86::BTC32ri8,    X86::BTC32mi8,   0 },
173     { X86::BTC64ri8,    X86::BTC64mi8,   0 },
174     { X86::BTR16ri8,    X86::BTR16mi8,   0 },
175     { X86::BTR32ri8,    X86::BTR32mi8,   0 },
176     { X86::BTR64ri8,    X86::BTR64mi8,   0 },
177     { X86::BTS16ri8,    X86::BTS16mi8,   0 },
178     { X86::BTS32ri8,    X86::BTS32mi8,   0 },
179     { X86::BTS64ri8,    X86::BTS64mi8,   0 },
180     { X86::DEC16r,      X86::DEC16m,     0 },
181     { X86::DEC32r,      X86::DEC32m,     0 },
182     { X86::DEC64r,      X86::DEC64m,     0 },
183     { X86::DEC8r,       X86::DEC8m,      0 },
184     { X86::INC16r,      X86::INC16m,     0 },
185     { X86::INC32r,      X86::INC32m,     0 },
186     { X86::INC64r,      X86::INC64m,     0 },
187     { X86::INC8r,       X86::INC8m,      0 },
188     { X86::NEG16r,      X86::NEG16m,     0 },
189     { X86::NEG32r,      X86::NEG32m,     0 },
190     { X86::NEG64r,      X86::NEG64m,     0 },
191     { X86::NEG8r,       X86::NEG8m,      0 },
192     { X86::NOT16r,      X86::NOT16m,     0 },
193     { X86::NOT32r,      X86::NOT32m,     0 },
194     { X86::NOT64r,      X86::NOT64m,     0 },
195     { X86::NOT8r,       X86::NOT8m,      0 },
196     { X86::OR16ri,      X86::OR16mi,     0 },
197     { X86::OR16ri8,     X86::OR16mi8,    0 },
198     { X86::OR16rr,      X86::OR16mr,     0 },
199     { X86::OR32ri,      X86::OR32mi,     0 },
200     { X86::OR32ri8,     X86::OR32mi8,    0 },
201     { X86::OR32rr,      X86::OR32mr,     0 },
202     { X86::OR64ri32,    X86::OR64mi32,   0 },
203     { X86::OR64ri8,     X86::OR64mi8,    0 },
204     { X86::OR64rr,      X86::OR64mr,     0 },
205     { X86::OR8ri,       X86::OR8mi,      0 },
206     { X86::OR8ri8,      X86::OR8mi8,     0 },
207     { X86::OR8rr,       X86::OR8mr,      0 },
208     { X86::RCL16r1,     X86::RCL16m1,    0 },
209     { X86::RCL16rCL,    X86::RCL16mCL,   0 },
210     { X86::RCL16ri,     X86::RCL16mi,    0 },
211     { X86::RCL32r1,     X86::RCL32m1,    0 },
212     { X86::RCL32rCL,    X86::RCL32mCL,   0 },
213     { X86::RCL32ri,     X86::RCL32mi,    0 },
214     { X86::RCL64r1,     X86::RCL64m1,    0 },
215     { X86::RCL64rCL,    X86::RCL64mCL,   0 },
216     { X86::RCL64ri,     X86::RCL64mi,    0 },
217     { X86::RCL8r1,      X86::RCL8m1,     0 },
218     { X86::RCL8rCL,     X86::RCL8mCL,    0 },
219     { X86::RCL8ri,      X86::RCL8mi,     0 },
220     { X86::RCR16r1,     X86::RCR16m1,    0 },
221     { X86::RCR16rCL,    X86::RCR16mCL,   0 },
222     { X86::RCR16ri,     X86::RCR16mi,    0 },
223     { X86::RCR32r1,     X86::RCR32m1,    0 },
224     { X86::RCR32rCL,    X86::RCR32mCL,   0 },
225     { X86::RCR32ri,     X86::RCR32mi,    0 },
226     { X86::RCR64r1,     X86::RCR64m1,    0 },
227     { X86::RCR64rCL,    X86::RCR64mCL,   0 },
228     { X86::RCR64ri,     X86::RCR64mi,    0 },
229     { X86::RCR8r1,      X86::RCR8m1,     0 },
230     { X86::RCR8rCL,     X86::RCR8mCL,    0 },
231     { X86::RCR8ri,      X86::RCR8mi,     0 },
232     { X86::ROL16r1,     X86::ROL16m1,    0 },
233     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
234     { X86::ROL16ri,     X86::ROL16mi,    0 },
235     { X86::ROL32r1,     X86::ROL32m1,    0 },
236     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
237     { X86::ROL32ri,     X86::ROL32mi,    0 },
238     { X86::ROL64r1,     X86::ROL64m1,    0 },
239     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
240     { X86::ROL64ri,     X86::ROL64mi,    0 },
241     { X86::ROL8r1,      X86::ROL8m1,     0 },
242     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
243     { X86::ROL8ri,      X86::ROL8mi,     0 },
244     { X86::ROR16r1,     X86::ROR16m1,    0 },
245     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
246     { X86::ROR16ri,     X86::ROR16mi,    0 },
247     { X86::ROR32r1,     X86::ROR32m1,    0 },
248     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
249     { X86::ROR32ri,     X86::ROR32mi,    0 },
250     { X86::ROR64r1,     X86::ROR64m1,    0 },
251     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
252     { X86::ROR64ri,     X86::ROR64mi,    0 },
253     { X86::ROR8r1,      X86::ROR8m1,     0 },
254     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
255     { X86::ROR8ri,      X86::ROR8mi,     0 },
256     { X86::SAR16r1,     X86::SAR16m1,    0 },
257     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
258     { X86::SAR16ri,     X86::SAR16mi,    0 },
259     { X86::SAR32r1,     X86::SAR32m1,    0 },
260     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
261     { X86::SAR32ri,     X86::SAR32mi,    0 },
262     { X86::SAR64r1,     X86::SAR64m1,    0 },
263     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
264     { X86::SAR64ri,     X86::SAR64mi,    0 },
265     { X86::SAR8r1,      X86::SAR8m1,     0 },
266     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
267     { X86::SAR8ri,      X86::SAR8mi,     0 },
268     { X86::SBB16ri,     X86::SBB16mi,    0 },
269     { X86::SBB16ri8,    X86::SBB16mi8,   0 },
270     { X86::SBB16rr,     X86::SBB16mr,    0 },
271     { X86::SBB32ri,     X86::SBB32mi,    0 },
272     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
273     { X86::SBB32rr,     X86::SBB32mr,    0 },
274     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
275     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
276     { X86::SBB64rr,     X86::SBB64mr,    0 },
277     { X86::SBB8ri,      X86::SBB8mi,     0 },
278     { X86::SBB8ri8,     X86::SBB8mi8,    0 },
279     { X86::SBB8rr,      X86::SBB8mr,     0 },
280     { X86::SHL16r1,     X86::SHL16m1,    0 },
281     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
282     { X86::SHL16ri,     X86::SHL16mi,    0 },
283     { X86::SHL32r1,     X86::SHL32m1,    0 },
284     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
285     { X86::SHL32ri,     X86::SHL32mi,    0 },
286     { X86::SHL64r1,     X86::SHL64m1,    0 },
287     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
288     { X86::SHL64ri,     X86::SHL64mi,    0 },
289     { X86::SHL8r1,      X86::SHL8m1,     0 },
290     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
291     { X86::SHL8ri,      X86::SHL8mi,     0 },
292     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
293     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
294     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
295     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
296     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
297     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
298     { X86::SHR16r1,     X86::SHR16m1,    0 },
299     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
300     { X86::SHR16ri,     X86::SHR16mi,    0 },
301     { X86::SHR32r1,     X86::SHR32m1,    0 },
302     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
303     { X86::SHR32ri,     X86::SHR32mi,    0 },
304     { X86::SHR64r1,     X86::SHR64m1,    0 },
305     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
306     { X86::SHR64ri,     X86::SHR64mi,    0 },
307     { X86::SHR8r1,      X86::SHR8m1,     0 },
308     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
309     { X86::SHR8ri,      X86::SHR8mi,     0 },
310     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
311     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
312     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
313     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
314     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
315     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
316     { X86::SUB16ri,     X86::SUB16mi,    0 },
317     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
318     { X86::SUB16rr,     X86::SUB16mr,    0 },
319     { X86::SUB32ri,     X86::SUB32mi,    0 },
320     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
321     { X86::SUB32rr,     X86::SUB32mr,    0 },
322     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
323     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
324     { X86::SUB64rr,     X86::SUB64mr,    0 },
325     { X86::SUB8ri,      X86::SUB8mi,     0 },
326     { X86::SUB8ri8,     X86::SUB8mi8,    0 },
327     { X86::SUB8rr,      X86::SUB8mr,     0 },
328     { X86::XOR16ri,     X86::XOR16mi,    0 },
329     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
330     { X86::XOR16rr,     X86::XOR16mr,    0 },
331     { X86::XOR32ri,     X86::XOR32mi,    0 },
332     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
333     { X86::XOR32rr,     X86::XOR32mr,    0 },
334     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
335     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
336     { X86::XOR64rr,     X86::XOR64mr,    0 },
337     { X86::XOR8ri,      X86::XOR8mi,     0 },
338     { X86::XOR8ri8,     X86::XOR8mi8,    0 },
339     { X86::XOR8rr,      X86::XOR8mr,     0 }
340   };
341 
342   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
343     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
344                   Entry.RegOp, Entry.MemOp,
345                   // Index 0, folded load and store, no alignment requirement.
346                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
347   }
348 
349   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
350     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
351     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
352     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
353     { X86::CALL16r,     X86::CALL16m,       TB_FOLDED_LOAD },
354     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
355     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
356     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
357     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
358     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
359     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
360     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
361     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
362     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
363     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
364     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
365     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
366     { X86::CMP8ri8,     X86::CMP8mi8,       TB_FOLDED_LOAD },
367     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
368     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
369     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
370     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
371     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
372     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
373     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
374     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
375     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
376     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
377     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
378     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
379     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
380     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
381     { X86::JMP16r,      X86::JMP16m,        TB_FOLDED_LOAD },
382     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
383     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
384     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
385     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
386     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
387     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
388     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
389     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
390     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
391     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
392     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
393     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
394     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
395     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
396     { X86::MOVDQUrr,    X86::MOVDQUmr,      TB_FOLDED_STORE },
397     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
398     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
399     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
400     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
401     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
402     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
403     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
404     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
405     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
406     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
407     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
408     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
409     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
410     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
411     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
412     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
413     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
414     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
415     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
416     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
417     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
418     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
419     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
420     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
421     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
422     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
423     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
424     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
425     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
426     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
427     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
428     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
429     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
430     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
431     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
432     { X86::TEST16rr,    X86::TEST16mr,      TB_FOLDED_LOAD },
433     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
434     { X86::TEST32rr,    X86::TEST32mr,      TB_FOLDED_LOAD },
435     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
436     { X86::TEST64rr,    X86::TEST64mr,      TB_FOLDED_LOAD },
437     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
438     { X86::TEST8rr,     X86::TEST8mr,       TB_FOLDED_LOAD },
439 
440     // AVX 128-bit versions of foldable instructions
441     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
442     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
443     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
444     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
445     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
446     { X86::VMOVDQUrr,   X86::VMOVDQUmr,     TB_FOLDED_STORE },
447     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
448     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
449     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
450     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
451     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
452     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
453     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
454     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
455 
456     // AVX 256-bit foldable instructions
457     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
458     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
459     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
460     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
461     { X86::VMOVDQUYrr,  X86::VMOVDQUYmr,    TB_FOLDED_STORE },
462     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
463     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
464 
465     // AVX-512 foldable instructions
466     { X86::VEXTRACTF32x4Zrr,X86::VEXTRACTF32x4Zmr, TB_FOLDED_STORE },
467     { X86::VEXTRACTF32x8Zrr,X86::VEXTRACTF32x8Zmr, TB_FOLDED_STORE },
468     { X86::VEXTRACTF64x2Zrr,X86::VEXTRACTF64x2Zmr, TB_FOLDED_STORE },
469     { X86::VEXTRACTF64x4Zrr,X86::VEXTRACTF64x4Zmr, TB_FOLDED_STORE },
470     { X86::VEXTRACTI32x4Zrr,X86::VEXTRACTI32x4Zmr, TB_FOLDED_STORE },
471     { X86::VEXTRACTI32x8Zrr,X86::VEXTRACTI32x8Zmr, TB_FOLDED_STORE },
472     { X86::VEXTRACTI64x2Zrr,X86::VEXTRACTI64x2Zmr, TB_FOLDED_STORE },
473     { X86::VEXTRACTI64x4Zrr,X86::VEXTRACTI64x4Zmr, TB_FOLDED_STORE },
474     { X86::VEXTRACTPSZrr,   X86::VEXTRACTPSZmr,    TB_FOLDED_STORE },
475     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
476     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
477     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
478     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
479     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
480     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
481     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
482     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
483     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
484     { X86::VMOVPQIto64Zrr,  X86::VMOVPQI2QIZmr, TB_FOLDED_STORE },
485     { X86::VMOVSDto64Zrr,   X86::VMOVSDto64Zmr, TB_FOLDED_STORE },
486     { X86::VMOVSS2DIZrr,    X86::VMOVSS2DIZmr,  TB_FOLDED_STORE },
487     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
488     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
489     { X86::VPEXTRDZrr,      X86::VPEXTRDZmr,    TB_FOLDED_STORE },
490     { X86::VPEXTRQZrr,      X86::VPEXTRQZmr,    TB_FOLDED_STORE },
491     { X86::VPMOVDBZrr,      X86::VPMOVDBZmr,    TB_FOLDED_STORE },
492     { X86::VPMOVDWZrr,      X86::VPMOVDWZmr,    TB_FOLDED_STORE },
493     { X86::VPMOVQDZrr,      X86::VPMOVQDZmr,    TB_FOLDED_STORE },
494     { X86::VPMOVQWZrr,      X86::VPMOVQWZmr,    TB_FOLDED_STORE },
495     { X86::VPMOVWBZrr,      X86::VPMOVWBZmr,    TB_FOLDED_STORE },
496     { X86::VPMOVSDBZrr,     X86::VPMOVSDBZmr,   TB_FOLDED_STORE },
497     { X86::VPMOVSDWZrr,     X86::VPMOVSDWZmr,   TB_FOLDED_STORE },
498     { X86::VPMOVSQDZrr,     X86::VPMOVSQDZmr,   TB_FOLDED_STORE },
499     { X86::VPMOVSQWZrr,     X86::VPMOVSQWZmr,   TB_FOLDED_STORE },
500     { X86::VPMOVSWBZrr,     X86::VPMOVSWBZmr,   TB_FOLDED_STORE },
501     { X86::VPMOVUSDBZrr,    X86::VPMOVUSDBZmr,  TB_FOLDED_STORE },
502     { X86::VPMOVUSDWZrr,    X86::VPMOVUSDWZmr,  TB_FOLDED_STORE },
503     { X86::VPMOVUSQDZrr,    X86::VPMOVUSQDZmr,  TB_FOLDED_STORE },
504     { X86::VPMOVUSQWZrr,    X86::VPMOVUSQWZmr,  TB_FOLDED_STORE },
505     { X86::VPMOVUSWBZrr,    X86::VPMOVUSWBZmr,  TB_FOLDED_STORE },
506 
507     // AVX-512 foldable instructions (256-bit versions)
508     { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256mr, TB_FOLDED_STORE },
509     { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256mr, TB_FOLDED_STORE },
510     { X86::VEXTRACTI32x4Z256rr,X86::VEXTRACTI32x4Z256mr, TB_FOLDED_STORE },
511     { X86::VEXTRACTI64x2Z256rr,X86::VEXTRACTI64x2Z256mr, TB_FOLDED_STORE },
512     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
513     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
514     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
515     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
516     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
517     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
518     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
519     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
520     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
521     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
522     { X86::VPMOVDWZ256rr,      X86::VPMOVDWZ256mr,    TB_FOLDED_STORE },
523     { X86::VPMOVQDZ256rr,      X86::VPMOVQDZ256mr,    TB_FOLDED_STORE },
524     { X86::VPMOVWBZ256rr,      X86::VPMOVWBZ256mr,    TB_FOLDED_STORE },
525     { X86::VPMOVSDWZ256rr,     X86::VPMOVSDWZ256mr,   TB_FOLDED_STORE },
526     { X86::VPMOVSQDZ256rr,     X86::VPMOVSQDZ256mr,   TB_FOLDED_STORE },
527     { X86::VPMOVSWBZ256rr,     X86::VPMOVSWBZ256mr,   TB_FOLDED_STORE },
528     { X86::VPMOVUSDWZ256rr,    X86::VPMOVUSDWZ256mr,  TB_FOLDED_STORE },
529     { X86::VPMOVUSQDZ256rr,    X86::VPMOVUSQDZ256mr,  TB_FOLDED_STORE },
530     { X86::VPMOVUSWBZ256rr,    X86::VPMOVUSWBZ256mr,  TB_FOLDED_STORE },
531 
532     // AVX-512 foldable instructions (128-bit versions)
533     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
534     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
535     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
536     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
537     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
538     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
539     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
540     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
541     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
542     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
543 
544     // F16C foldable instructions
545     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE },
546     { X86::VCVTPS2PHZ256rr,    X86::VCVTPS2PHZ256mr,  TB_FOLDED_STORE },
547     { X86::VCVTPS2PHZrr,       X86::VCVTPS2PHZmr,     TB_FOLDED_STORE },
548   };
549 
550   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
551     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
552                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
553   }
554 
555   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
556     { X86::BSF16rr,         X86::BSF16rm,             0 },
557     { X86::BSF32rr,         X86::BSF32rm,             0 },
558     { X86::BSF64rr,         X86::BSF64rm,             0 },
559     { X86::BSR16rr,         X86::BSR16rm,             0 },
560     { X86::BSR32rr,         X86::BSR32rm,             0 },
561     { X86::BSR64rr,         X86::BSR64rm,             0 },
562     { X86::CMP16rr,         X86::CMP16rm,             0 },
563     { X86::CMP32rr,         X86::CMP32rm,             0 },
564     { X86::CMP64rr,         X86::CMP64rm,             0 },
565     { X86::CMP8rr,          X86::CMP8rm,              0 },
566     { X86::COMISDrr_Int,    X86::COMISDrm_Int,        TB_NO_REVERSE },
567     { X86::COMISSrr_Int,    X86::COMISSrm_Int,        TB_NO_REVERSE },
568     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_NO_REVERSE },
569     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
570     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
571     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
572     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
573     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_NO_REVERSE },
574     { X86::CVTSD2SI64rr_Int, X86::CVTSD2SI64rm_Int,   TB_NO_REVERSE },
575     { X86::CVTSD2SIrr_Int,  X86::CVTSD2SIrm_Int,      TB_NO_REVERSE },
576     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
577     { X86::CVTSI642SDrr,    X86::CVTSI642SDrm,        0 },
578     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
579     { X86::CVTSI642SSrr,    X86::CVTSI642SSrm,        0 },
580     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
581     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
582     { X86::CVTSS2SI64rr_Int, X86::CVTSS2SI64rm_Int,   TB_NO_REVERSE },
583     { X86::CVTSS2SIrr_Int,  X86::CVTSS2SIrm_Int,      TB_NO_REVERSE },
584     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
585     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
586     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
587     { X86::CVTTSD2SI64rr_Int,X86::CVTTSD2SI64rm_Int,  TB_NO_REVERSE },
588     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
589     { X86::CVTTSD2SIrr_Int, X86::CVTTSD2SIrm_Int,     TB_NO_REVERSE },
590     { X86::CVTTSS2SI64rr_Int,X86::CVTTSS2SI64rm_Int,  TB_NO_REVERSE },
591     { X86::CVTTSS2SIrr_Int, X86::CVTTSS2SIrm_Int,     TB_NO_REVERSE },
592     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
593     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
594     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
595     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
596     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
597     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
598     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
599     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
600     { X86::MOV16rr,         X86::MOV16rm,             0 },
601     { X86::MOV32rr,         X86::MOV32rm,             0 },
602     { X86::MOV64rr,         X86::MOV64rm,             0 },
603     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
604     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
605     { X86::MOV8rr,          X86::MOV8rm,              0 },
606     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
607     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
608     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           TB_NO_REVERSE },
609     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
610     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
611     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
612     { X86::MOVDQUrr,        X86::MOVDQUrm,            0 },
613     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
614     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
615     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
616     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
617     { X86::MOVSX32_NOREXrr8, X86::MOVSX32_NOREXrm8,   0 },
618     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
619     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
620     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
621     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
622     { X86::MOVUPDrr,        X86::MOVUPDrm,            0 },
623     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
624     { X86::MOVZPQILo2PQIrr, X86::MOVQI2PQIrm,         TB_NO_REVERSE },
625     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
626     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
627     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
628     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
629     { X86::MOVZX64rr16,     X86::MOVZX64rm16,         0 },
630     { X86::MOVZX64rr8,      X86::MOVZX64rm8,          0 },
631     { X86::PABSBrr,         X86::PABSBrm,             TB_ALIGN_16 },
632     { X86::PABSDrr,         X86::PABSDrm,             TB_ALIGN_16 },
633     { X86::PABSWrr,         X86::PABSWrm,             TB_ALIGN_16 },
634     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
635     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
636     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
637     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
638     { X86::PHMINPOSUWrr,    X86::PHMINPOSUWrm,        TB_ALIGN_16 },
639     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_NO_REVERSE },
640     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_NO_REVERSE },
641     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_NO_REVERSE },
642     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_NO_REVERSE },
643     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_NO_REVERSE },
644     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_NO_REVERSE },
645     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_NO_REVERSE },
646     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_NO_REVERSE },
647     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_NO_REVERSE },
648     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_NO_REVERSE },
649     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_NO_REVERSE },
650     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_NO_REVERSE },
651     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
652     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
653     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
654     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
655     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
656     { X86::RCPSSr,          X86::RCPSSm,              0 },
657     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          TB_NO_REVERSE },
658     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
659     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
660     { X86::ROUNDSDr,        X86::ROUNDSDm,            0 },
661     { X86::ROUNDSSr,        X86::ROUNDSSm,            0 },
662     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
663     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
664     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        TB_NO_REVERSE },
665     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
666     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
667     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
668     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         TB_NO_REVERSE },
669     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
670     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         TB_NO_REVERSE },
671     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
672     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
673     { X86::UCOMISDrr_Int,   X86::UCOMISDrm_Int,       TB_NO_REVERSE },
674     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
675     { X86::UCOMISSrr_Int,   X86::UCOMISSrm_Int,       TB_NO_REVERSE },
676 
677     // MMX version of foldable instructions
678     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   TB_ALIGN_16 },
679     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
680     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   TB_NO_REVERSE },
681     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  TB_ALIGN_16 },
682     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  TB_NO_REVERSE },
683     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
684     { X86::MMX_PABSBrr,       X86::MMX_PABSBrm,       0 },
685     { X86::MMX_PABSDrr,       X86::MMX_PABSDrm,       0 },
686     { X86::MMX_PABSWrr,       X86::MMX_PABSWrm,       0 },
687     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
688 
689     // 3DNow! version of foldable instructions
690     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
691     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
692     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
693     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
694     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
695     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
696     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
697 
698     // AVX 128-bit versions of foldable instructions
699     { X86::VCOMISDrr_Int,   X86::VCOMISDrm_Int,       TB_NO_REVERSE },
700     { X86::VCOMISSrr_Int,   X86::VCOMISSrm_Int,       TB_NO_REVERSE },
701     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
702     { X86::VCVTTSD2SI64rr_Int,X86::VCVTTSD2SI64rm_Int,TB_NO_REVERSE },
703     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
704     { X86::VCVTTSD2SIrr_Int,X86::VCVTTSD2SIrm_Int,    TB_NO_REVERSE },
705     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
706     { X86::VCVTTSS2SI64rr_Int,X86::VCVTTSS2SI64rm_Int,TB_NO_REVERSE },
707     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
708     { X86::VCVTTSS2SIrr_Int,X86::VCVTTSS2SIrm_Int,    TB_NO_REVERSE },
709     { X86::VCVTSD2SI64rr_Int, X86::VCVTSD2SI64rm_Int, TB_NO_REVERSE },
710     { X86::VCVTSD2SIrr_Int,   X86::VCVTSD2SIrm_Int,   TB_NO_REVERSE },
711     { X86::VCVTSS2SI64rr_Int, X86::VCVTSS2SI64rm_Int, TB_NO_REVERSE },
712     { X86::VCVTSS2SIrr_Int, X86::VCVTSS2SIrm_Int,     TB_NO_REVERSE },
713     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         TB_NO_REVERSE },
714     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
715     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQrm,         0 },
716     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSrm,         0 },
717     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
718     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         TB_NO_REVERSE },
719     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQrm,        0 },
720     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
721     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
722     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
723     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
724     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
725     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          TB_NO_REVERSE },
726     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
727     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
728     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
729     { X86::VMOVDQUrr,       X86::VMOVDQUrm,           0 },
730     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
731     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
732     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
733     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
734     { X86::VMOVZPQILo2PQIrr,X86::VMOVQI2PQIrm,        TB_NO_REVERSE },
735     { X86::VPABSBrr,        X86::VPABSBrm,            0 },
736     { X86::VPABSDrr,        X86::VPABSDrm,            0 },
737     { X86::VPABSWrr,        X86::VPABSWrm,            0 },
738     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
739     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
740     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
741     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
742     { X86::VPHMINPOSUWrr,   X86::VPHMINPOSUWrm,      0 },
743     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
744     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
745     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         TB_NO_REVERSE },
746     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         TB_NO_REVERSE },
747     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         TB_NO_REVERSE },
748     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         TB_NO_REVERSE },
749     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         TB_NO_REVERSE },
750     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         TB_NO_REVERSE },
751     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         TB_NO_REVERSE },
752     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         TB_NO_REVERSE },
753     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         TB_NO_REVERSE },
754     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         TB_NO_REVERSE },
755     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         TB_NO_REVERSE },
756     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         TB_NO_REVERSE },
757     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
758     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
759     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
760     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
761     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
762     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
763     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
764     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
765     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
766     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
767     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
768     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
769     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
770     { X86::VUCOMISDrr_Int,  X86::VUCOMISDrm_Int,      TB_NO_REVERSE },
771     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
772     { X86::VUCOMISSrr_Int,  X86::VUCOMISSrm_Int,      TB_NO_REVERSE },
773 
774     // AVX 256-bit foldable instructions
775     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
776     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
777     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
778     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
779     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
780     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
781     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
782     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
783     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
784     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
785     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
786     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
787     { X86::VMOVDQUYrr,      X86::VMOVDQUYrm,          0 },
788     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
789     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
790     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
791     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
792     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
793     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
794     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
795     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
796     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
797     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
798     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
799     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
800     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
801     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
802     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
803 
804     // AVX2 foldable instructions
805 
806     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
807     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
808     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
809     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
810     // so they don't need an equivalent limitation.
811     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
812     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
813     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
814     { X86::VPABSBYrr,       X86::VPABSBYrm,           0 },
815     { X86::VPABSDYrr,       X86::VPABSDYrm,           0 },
816     { X86::VPABSWYrr,       X86::VPABSWYrm,           0 },
817     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      TB_NO_REVERSE },
818     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     TB_NO_REVERSE },
819     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      TB_NO_REVERSE },
820     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     TB_NO_REVERSE },
821     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      TB_NO_REVERSE },
822     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     TB_NO_REVERSE },
823     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      TB_NO_REVERSE },
824     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     TB_NO_REVERSE },
825     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
826     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
827     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        TB_NO_REVERSE },
828     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        TB_NO_REVERSE },
829     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
830     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
831     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
832     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        TB_NO_REVERSE },
833     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        TB_NO_REVERSE },
834     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        TB_NO_REVERSE },
835     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
836     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
837     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
838     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        TB_NO_REVERSE },
839     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
840     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
841     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
842 
843     // XOP foldable instructions
844     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
845     { X86::VFRCZPDYrr,         X86::VFRCZPDYrm,       0 },
846     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
847     { X86::VFRCZPSYrr,         X86::VFRCZPSYrm,       0 },
848     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
849     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
850     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
851     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
852     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
853     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
854     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
855     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
856     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
857     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
858     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
859     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
860     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
861     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
862     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
863     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
864     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
865     { X86::VPROTBri,           X86::VPROTBmi,         0 },
866     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
867     { X86::VPROTDri,           X86::VPROTDmi,         0 },
868     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
869     { X86::VPROTQri,           X86::VPROTQmi,         0 },
870     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
871     { X86::VPROTWri,           X86::VPROTWmi,         0 },
872     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
873     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
874     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
875     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
876     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
877     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
878     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
879     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
880     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
881 
882     // LWP foldable instructions
883     { X86::LWPINS32rri,        X86::LWPINS32rmi,      0 },
884     { X86::LWPINS64rri,        X86::LWPINS64rmi,      0 },
885     { X86::LWPVAL32rri,        X86::LWPVAL32rmi,      0 },
886     { X86::LWPVAL64rri,        X86::LWPVAL64rmi,      0 },
887 
888     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
889     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
890     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
891     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
892     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
893     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
894     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
895     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
896     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
897     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
898     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
899     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
900     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
901     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
902     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
903     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
904     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
905     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
906     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
907     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
908     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
909     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
910     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
911     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
912     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
913     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
914     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
915     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
916     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
917     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
918     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
919     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
920     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
921     { X86::RORX32ri,        X86::RORX32mi,            0 },
922     { X86::RORX64ri,        X86::RORX64mi,            0 },
923     { X86::SARX32rr,        X86::SARX32rm,            0 },
924     { X86::SARX64rr,        X86::SARX64rm,            0 },
925     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
926     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
927     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
928     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
929     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
930     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
931     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
932     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
933     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
934     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
935     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
936 
937     // AVX-512 foldable instructions
938     { X86::VBROADCASTSSZr,   X86::VBROADCASTSSZm,     TB_NO_REVERSE },
939     { X86::VBROADCASTSDZr,   X86::VBROADCASTSDZm,     TB_NO_REVERSE },
940     { X86::VCVTDQ2PDZrr,     X86::VCVTDQ2PDZrm,       0 },
941     { X86::VCVTPD2PSZrr,     X86::VCVTPD2PSZrm,       0 },
942     { X86::VCVTUDQ2PDZrr,    X86::VCVTUDQ2PDZrm,      0 },
943     { X86::VMOV64toPQIZrr,   X86::VMOVQI2PQIZrm,      0 },
944     { X86::VMOV64toSDZrr,    X86::VMOV64toSDZrm,      0 },
945     { X86::VMOVDI2PDIZrr,    X86::VMOVDI2PDIZrm,      0 },
946     { X86::VMOVDI2SSZrr,     X86::VMOVDI2SSZrm,       0 },
947     { X86::VMOVAPDZrr,       X86::VMOVAPDZrm,         TB_ALIGN_64 },
948     { X86::VMOVAPSZrr,       X86::VMOVAPSZrm,         TB_ALIGN_64 },
949     { X86::VMOVDQA32Zrr,     X86::VMOVDQA32Zrm,       TB_ALIGN_64 },
950     { X86::VMOVDQA64Zrr,     X86::VMOVDQA64Zrm,       TB_ALIGN_64 },
951     { X86::VMOVDQU8Zrr,      X86::VMOVDQU8Zrm,        0 },
952     { X86::VMOVDQU16Zrr,     X86::VMOVDQU16Zrm,       0 },
953     { X86::VMOVDQU32Zrr,     X86::VMOVDQU32Zrm,       0 },
954     { X86::VMOVDQU64Zrr,     X86::VMOVDQU64Zrm,       0 },
955     { X86::VMOVUPDZrr,       X86::VMOVUPDZrm,         0 },
956     { X86::VMOVUPSZrr,       X86::VMOVUPSZrm,         0 },
957     { X86::VMOVZPQILo2PQIZrr,X86::VMOVQI2PQIZrm,      TB_NO_REVERSE },
958     { X86::VPABSBZrr,        X86::VPABSBZrm,          0 },
959     { X86::VPABSDZrr,        X86::VPABSDZrm,          0 },
960     { X86::VPABSQZrr,        X86::VPABSQZrm,          0 },
961     { X86::VPABSWZrr,        X86::VPABSWZrm,          0 },
962     { X86::VPCONFLICTDZrr,   X86::VPCONFLICTDZrm,     0 },
963     { X86::VPCONFLICTQZrr,   X86::VPCONFLICTQZrm,     0 },
964     { X86::VPERMILPDZri,     X86::VPERMILPDZmi,       0 },
965     { X86::VPERMILPSZri,     X86::VPERMILPSZmi,       0 },
966     { X86::VPERMPDZri,       X86::VPERMPDZmi,         0 },
967     { X86::VPERMQZri,        X86::VPERMQZmi,          0 },
968     { X86::VPLZCNTDZrr,      X86::VPLZCNTDZrm,        0 },
969     { X86::VPLZCNTQZrr,      X86::VPLZCNTQZrm,        0 },
970     { X86::VPMOVSXBDZrr,     X86::VPMOVSXBDZrm,       0 },
971     { X86::VPMOVSXBQZrr,     X86::VPMOVSXBQZrm,       TB_NO_REVERSE },
972     { X86::VPMOVSXBWZrr,     X86::VPMOVSXBWZrm,       0 },
973     { X86::VPMOVSXDQZrr,     X86::VPMOVSXDQZrm,       0 },
974     { X86::VPMOVSXWDZrr,     X86::VPMOVSXWDZrm,       0 },
975     { X86::VPMOVSXWQZrr,     X86::VPMOVSXWQZrm,       0 },
976     { X86::VPMOVZXBDZrr,     X86::VPMOVZXBDZrm,       0 },
977     { X86::VPMOVZXBQZrr,     X86::VPMOVZXBQZrm,       TB_NO_REVERSE },
978     { X86::VPMOVZXBWZrr,     X86::VPMOVZXBWZrm,       0 },
979     { X86::VPMOVZXDQZrr,     X86::VPMOVZXDQZrm,       0 },
980     { X86::VPMOVZXWDZrr,     X86::VPMOVZXWDZrm,       0 },
981     { X86::VPMOVZXWQZrr,     X86::VPMOVZXWQZrm,       0 },
982     { X86::VPOPCNTBZrr,      X86::VPOPCNTBZrm,        0 },
983     { X86::VPOPCNTDZrr,      X86::VPOPCNTDZrm,        0 },
984     { X86::VPOPCNTQZrr,      X86::VPOPCNTQZrm,        0 },
985     { X86::VPOPCNTWZrr,      X86::VPOPCNTWZrm,        0 },
986     { X86::VPSHUFDZri,       X86::VPSHUFDZmi,         0 },
987     { X86::VPSHUFHWZri,      X86::VPSHUFHWZmi,        0 },
988     { X86::VPSHUFLWZri,      X86::VPSHUFLWZmi,        0 },
989     { X86::VPSLLDQZrr,       X86::VPSLLDQZrm,         0 },
990     { X86::VPSLLDZri,        X86::VPSLLDZmi,          0 },
991     { X86::VPSLLQZri,        X86::VPSLLQZmi,          0 },
992     { X86::VPSLLWZri,        X86::VPSLLWZmi,          0 },
993     { X86::VPSRADZri,        X86::VPSRADZmi,          0 },
994     { X86::VPSRAQZri,        X86::VPSRAQZmi,          0 },
995     { X86::VPSRAWZri,        X86::VPSRAWZmi,          0 },
996     { X86::VPSRLDQZrr,       X86::VPSRLDQZrm,         0 },
997     { X86::VPSRLDZri,        X86::VPSRLDZmi,          0 },
998     { X86::VPSRLQZri,        X86::VPSRLQZmi,          0 },
999     { X86::VPSRLWZri,        X86::VPSRLWZmi,          0 },
1000 
1001     // AVX-512 foldable instructions (256-bit versions)
1002     { X86::VBROADCASTSSZ256r,    X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
1003     { X86::VBROADCASTSDZ256r,    X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
1004     { X86::VCVTDQ2PDZ256rr,      X86::VCVTDQ2PDZ256rm,      0 },
1005     { X86::VCVTPD2PSZ256rr,      X86::VCVTPD2PSZ256rm,      0 },
1006     { X86::VCVTUDQ2PDZ256rr,     X86::VCVTUDQ2PDZ256rm,     0 },
1007     { X86::VMOVAPDZ256rr,        X86::VMOVAPDZ256rm,        TB_ALIGN_32 },
1008     { X86::VMOVAPSZ256rr,        X86::VMOVAPSZ256rm,        TB_ALIGN_32 },
1009     { X86::VMOVDQA32Z256rr,      X86::VMOVDQA32Z256rm,      TB_ALIGN_32 },
1010     { X86::VMOVDQA64Z256rr,      X86::VMOVDQA64Z256rm,      TB_ALIGN_32 },
1011     { X86::VMOVDQU8Z256rr,       X86::VMOVDQU8Z256rm,       0 },
1012     { X86::VMOVDQU16Z256rr,      X86::VMOVDQU16Z256rm,      0 },
1013     { X86::VMOVDQU32Z256rr,      X86::VMOVDQU32Z256rm,      0 },
1014     { X86::VMOVDQU64Z256rr,      X86::VMOVDQU64Z256rm,      0 },
1015     { X86::VMOVUPDZ256rr,        X86::VMOVUPDZ256rm,        0 },
1016     { X86::VMOVUPSZ256rr,        X86::VMOVUPSZ256rm,        0 },
1017     { X86::VPABSBZ256rr,         X86::VPABSBZ256rm,         0 },
1018     { X86::VPABSDZ256rr,         X86::VPABSDZ256rm,         0 },
1019     { X86::VPABSQZ256rr,         X86::VPABSQZ256rm,         0 },
1020     { X86::VPABSWZ256rr,         X86::VPABSWZ256rm,         0 },
1021     { X86::VPCONFLICTDZ256rr,    X86::VPCONFLICTDZ256rm,    0 },
1022     { X86::VPCONFLICTQZ256rr,    X86::VPCONFLICTQZ256rm,    0 },
1023     { X86::VPERMILPDZ256ri,      X86::VPERMILPDZ256mi,      0 },
1024     { X86::VPERMILPSZ256ri,      X86::VPERMILPSZ256mi,      0 },
1025     { X86::VPERMPDZ256ri,        X86::VPERMPDZ256mi,        0 },
1026     { X86::VPERMQZ256ri,         X86::VPERMQZ256mi,         0 },
1027     { X86::VPLZCNTDZ256rr,       X86::VPLZCNTDZ256rm,       0 },
1028     { X86::VPLZCNTQZ256rr,       X86::VPLZCNTQZ256rm,       0 },
1029     { X86::VPMOVSXBDZ256rr,      X86::VPMOVSXBDZ256rm,      TB_NO_REVERSE },
1030     { X86::VPMOVSXBQZ256rr,      X86::VPMOVSXBQZ256rm,      TB_NO_REVERSE },
1031     { X86::VPMOVSXBWZ256rr,      X86::VPMOVSXBWZ256rm,      0 },
1032     { X86::VPMOVSXDQZ256rr,      X86::VPMOVSXDQZ256rm,      0 },
1033     { X86::VPMOVSXWDZ256rr,      X86::VPMOVSXWDZ256rm,      0 },
1034     { X86::VPMOVSXWQZ256rr,      X86::VPMOVSXWQZ256rm,      TB_NO_REVERSE },
1035     { X86::VPMOVZXBDZ256rr,      X86::VPMOVZXBDZ256rm,      TB_NO_REVERSE },
1036     { X86::VPMOVZXBQZ256rr,      X86::VPMOVZXBQZ256rm,      TB_NO_REVERSE },
1037     { X86::VPMOVZXBWZ256rr,      X86::VPMOVZXBWZ256rm,      0 },
1038     { X86::VPMOVZXDQZ256rr,      X86::VPMOVZXDQZ256rm,      0 },
1039     { X86::VPMOVZXWDZ256rr,      X86::VPMOVZXWDZ256rm,      0 },
1040     { X86::VPMOVZXWQZ256rr,      X86::VPMOVZXWQZ256rm,      TB_NO_REVERSE },
1041     { X86::VPOPCNTBZ256rr,       X86::VPOPCNTBZ256rm,       0 },
1042     { X86::VPOPCNTDZ256rr,       X86::VPOPCNTDZ256rm,       0 },
1043     { X86::VPOPCNTQZ256rr,       X86::VPOPCNTQZ256rm,       0 },
1044     { X86::VPOPCNTWZ256rr,       X86::VPOPCNTWZ256rm,       0 },
1045     { X86::VPSHUFDZ256ri,        X86::VPSHUFDZ256mi,        0 },
1046     { X86::VPSHUFHWZ256ri,       X86::VPSHUFHWZ256mi,       0 },
1047     { X86::VPSHUFLWZ256ri,       X86::VPSHUFLWZ256mi,       0 },
1048     { X86::VPSLLDQZ256rr,        X86::VPSLLDQZ256rm,        0 },
1049     { X86::VPSLLDZ256ri,         X86::VPSLLDZ256mi,         0 },
1050     { X86::VPSLLQZ256ri,         X86::VPSLLQZ256mi,         0 },
1051     { X86::VPSLLWZ256ri,         X86::VPSLLWZ256mi,         0 },
1052     { X86::VPSRADZ256ri,         X86::VPSRADZ256mi,         0 },
1053     { X86::VPSRAQZ256ri,         X86::VPSRAQZ256mi,         0 },
1054     { X86::VPSRAWZ256ri,         X86::VPSRAWZ256mi,         0 },
1055     { X86::VPSRLDQZ256rr,        X86::VPSRLDQZ256rm,        0 },
1056     { X86::VPSRLDZ256ri,         X86::VPSRLDZ256mi,         0 },
1057     { X86::VPSRLQZ256ri,         X86::VPSRLQZ256mi,         0 },
1058     { X86::VPSRLWZ256ri,         X86::VPSRLWZ256mi,         0 },
1059 
1060     // AVX-512 foldable instructions (128-bit versions)
1061     { X86::VBROADCASTSSZ128r,    X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
1062     { X86::VCVTDQ2PDZ128rr,      X86::VCVTDQ2PDZ128rm,      TB_NO_REVERSE },
1063     { X86::VCVTPD2PSZ128rr,      X86::VCVTPD2PSZ128rm,      0 },
1064     { X86::VCVTUDQ2PDZ128rr,     X86::VCVTUDQ2PDZ128rm,     TB_NO_REVERSE },
1065     { X86::VMOVAPDZ128rr,        X86::VMOVAPDZ128rm,        TB_ALIGN_16 },
1066     { X86::VMOVAPSZ128rr,        X86::VMOVAPSZ128rm,        TB_ALIGN_16 },
1067     { X86::VMOVDQA32Z128rr,      X86::VMOVDQA32Z128rm,      TB_ALIGN_16 },
1068     { X86::VMOVDQA64Z128rr,      X86::VMOVDQA64Z128rm,      TB_ALIGN_16 },
1069     { X86::VMOVDQU8Z128rr,       X86::VMOVDQU8Z128rm,       0 },
1070     { X86::VMOVDQU16Z128rr,      X86::VMOVDQU16Z128rm,      0 },
1071     { X86::VMOVDQU32Z128rr,      X86::VMOVDQU32Z128rm,      0 },
1072     { X86::VMOVDQU64Z128rr,      X86::VMOVDQU64Z128rm,      0 },
1073     { X86::VMOVUPDZ128rr,        X86::VMOVUPDZ128rm,        0 },
1074     { X86::VMOVUPSZ128rr,        X86::VMOVUPSZ128rm,        0 },
1075     { X86::VPABSBZ128rr,         X86::VPABSBZ128rm,         0 },
1076     { X86::VPABSDZ128rr,         X86::VPABSDZ128rm,         0 },
1077     { X86::VPABSQZ128rr,         X86::VPABSQZ128rm,         0 },
1078     { X86::VPABSWZ128rr,         X86::VPABSWZ128rm,         0 },
1079     { X86::VPCONFLICTDZ128rr,    X86::VPCONFLICTDZ128rm,    0 },
1080     { X86::VPCONFLICTQZ128rr,    X86::VPCONFLICTQZ128rm,    0 },
1081     { X86::VPERMILPDZ128ri,      X86::VPERMILPDZ128mi,      0 },
1082     { X86::VPERMILPSZ128ri,      X86::VPERMILPSZ128mi,      0 },
1083     { X86::VPLZCNTDZ128rr,       X86::VPLZCNTDZ128rm,       0 },
1084     { X86::VPLZCNTQZ128rr,       X86::VPLZCNTQZ128rm,       0 },
1085     { X86::VPMOVSXBDZ128rr,      X86::VPMOVSXBDZ128rm,      TB_NO_REVERSE },
1086     { X86::VPMOVSXBQZ128rr,      X86::VPMOVSXBQZ128rm,      TB_NO_REVERSE },
1087     { X86::VPMOVSXBWZ128rr,      X86::VPMOVSXBWZ128rm,      TB_NO_REVERSE },
1088     { X86::VPMOVSXDQZ128rr,      X86::VPMOVSXDQZ128rm,      TB_NO_REVERSE },
1089     { X86::VPMOVSXWDZ128rr,      X86::VPMOVSXWDZ128rm,      TB_NO_REVERSE },
1090     { X86::VPMOVSXWQZ128rr,      X86::VPMOVSXWQZ128rm,      TB_NO_REVERSE },
1091     { X86::VPMOVZXBDZ128rr,      X86::VPMOVZXBDZ128rm,      TB_NO_REVERSE },
1092     { X86::VPMOVZXBQZ128rr,      X86::VPMOVZXBQZ128rm,      TB_NO_REVERSE },
1093     { X86::VPMOVZXBWZ128rr,      X86::VPMOVZXBWZ128rm,      TB_NO_REVERSE },
1094     { X86::VPMOVZXDQZ128rr,      X86::VPMOVZXDQZ128rm,      TB_NO_REVERSE },
1095     { X86::VPMOVZXWDZ128rr,      X86::VPMOVZXWDZ128rm,      TB_NO_REVERSE },
1096     { X86::VPMOVZXWQZ128rr,      X86::VPMOVZXWQZ128rm,      TB_NO_REVERSE },
1097     { X86::VPOPCNTBZ128rr,       X86::VPOPCNTBZ128rm,       0 },
1098     { X86::VPOPCNTDZ128rr,       X86::VPOPCNTDZ128rm,       0 },
1099     { X86::VPOPCNTQZ128rr,       X86::VPOPCNTQZ128rm,       0 },
1100     { X86::VPOPCNTWZ128rr,       X86::VPOPCNTWZ128rm,       0 },
1101     { X86::VPSHUFDZ128ri,        X86::VPSHUFDZ128mi,        0 },
1102     { X86::VPSHUFHWZ128ri,       X86::VPSHUFHWZ128mi,       0 },
1103     { X86::VPSHUFLWZ128ri,       X86::VPSHUFLWZ128mi,       0 },
1104     { X86::VPSLLDQZ128rr,        X86::VPSLLDQZ128rm,        0 },
1105     { X86::VPSLLDZ128ri,         X86::VPSLLDZ128mi,         0 },
1106     { X86::VPSLLQZ128ri,         X86::VPSLLQZ128mi,         0 },
1107     { X86::VPSLLWZ128ri,         X86::VPSLLWZ128mi,         0 },
1108     { X86::VPSRADZ128ri,         X86::VPSRADZ128mi,         0 },
1109     { X86::VPSRAQZ128ri,         X86::VPSRAQZ128mi,         0 },
1110     { X86::VPSRAWZ128ri,         X86::VPSRAWZ128mi,         0 },
1111     { X86::VPSRLDQZ128rr,        X86::VPSRLDQZ128rm,        0 },
1112     { X86::VPSRLDZ128ri,         X86::VPSRLDZ128mi,         0 },
1113     { X86::VPSRLQZ128ri,         X86::VPSRLQZ128mi,         0 },
1114     { X86::VPSRLWZ128ri,         X86::VPSRLWZ128mi,         0 },
1115 
1116     // F16C foldable instructions
1117     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            TB_NO_REVERSE },
1118     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
1119     { X86::VCVTPH2PSZ128rr,    X86::VCVTPH2PSZ128rm,        TB_NO_REVERSE },
1120     { X86::VCVTPH2PSZ256rr,    X86::VCVTPH2PSZ256rm,        0 },
1121     { X86::VCVTPH2PSZrr,       X86::VCVTPH2PSZrm,           0 },
1122 
1123     // AES foldable instructions
1124     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
1125     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
1126     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
1127     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
1128   };
1129 
1130   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
1131     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
1132                   Entry.RegOp, Entry.MemOp,
1133                   // Index 1, folded load
1134                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
1135   }
1136 
1137   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
1138     { X86::ADC16rr,         X86::ADC16rm,       0 },
1139     { X86::ADC32rr,         X86::ADC32rm,       0 },
1140     { X86::ADC64rr,         X86::ADC64rm,       0 },
1141     { X86::ADC8rr,          X86::ADC8rm,        0 },
1142     { X86::ADD16rr,         X86::ADD16rm,       0 },
1143     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
1144     { X86::ADD32rr,         X86::ADD32rm,       0 },
1145     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
1146     { X86::ADD64rr,         X86::ADD64rm,       0 },
1147     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
1148     { X86::ADD8rr,          X86::ADD8rm,        0 },
1149     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
1150     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
1151     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
1152     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   TB_NO_REVERSE },
1153     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
1154     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   TB_NO_REVERSE },
1155     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
1156     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
1157     { X86::AND16rr,         X86::AND16rm,       0 },
1158     { X86::AND32rr,         X86::AND32rm,       0 },
1159     { X86::AND64rr,         X86::AND64rm,       0 },
1160     { X86::AND8rr,          X86::AND8rm,        0 },
1161     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
1162     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
1163     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
1164     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
1165     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
1166     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
1167     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
1168     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
1169     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
1170     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
1171     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
1172     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
1173     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
1174     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
1175     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
1176     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
1177     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
1178     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
1179     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
1180     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
1181     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
1182     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
1183     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
1184     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
1185     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
1186     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
1187     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
1188     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
1189     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
1190     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
1191     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
1192     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
1193     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
1194     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
1195     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
1196     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
1197     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
1198     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
1199     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
1200     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
1201     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
1202     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
1203     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
1204     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
1205     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
1206     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
1207     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
1208     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
1209     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
1210     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
1211     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
1212     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
1213     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
1214     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
1215     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
1216     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
1217     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
1218     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
1219     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
1220     { X86::CMPSDrr_Int,     X86::CMPSDrm_Int,   TB_NO_REVERSE },
1221     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
1222     { X86::CMPSSrr_Int,     X86::CMPSSrm_Int,   TB_NO_REVERSE },
1223     { X86::CRC32r32r16,     X86::CRC32r32m16,   0 },
1224     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
1225     { X86::CRC32r32r8,      X86::CRC32r32m8,    0 },
1226     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
1227     { X86::CRC32r64r8,      X86::CRC32r64m8,    0 },
1228     { X86::CVTSD2SSrr_Int,  X86::CVTSD2SSrm_Int,      TB_NO_REVERSE },
1229     { X86::CVTSS2SDrr_Int,  X86::CVTSS2SDrm_Int,      TB_NO_REVERSE },
1230     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
1231     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
1232     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
1233     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   TB_NO_REVERSE },
1234     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
1235     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   TB_NO_REVERSE },
1236     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
1237     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
1238     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
1239     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
1240     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
1241     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
1242     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
1243     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
1244     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
1245     { X86::CVTSI642SDrr_Int,X86::CVTSI642SDrm_Int,    0 },
1246     { X86::CVTSI2SDrr_Int,  X86::CVTSI2SDrm_Int,      0 },
1247     { X86::CVTSI642SSrr_Int,X86::CVTSI642SSrm_Int,    0 },
1248     { X86::CVTSI2SSrr_Int,  X86::CVTSI2SSrm_Int,      0 },
1249     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
1250     { X86::MAXCPDrr,        X86::MAXCPDrm,      TB_ALIGN_16 },
1251     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
1252     { X86::MAXCPSrr,        X86::MAXCPSrm,      TB_ALIGN_16 },
1253     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
1254     { X86::MAXCSDrr,        X86::MAXCSDrm,      0 },
1255     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   TB_NO_REVERSE },
1256     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
1257     { X86::MAXCSSrr,        X86::MAXCSSrm,      0 },
1258     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   TB_NO_REVERSE },
1259     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
1260     { X86::MINCPDrr,        X86::MINCPDrm,      TB_ALIGN_16 },
1261     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
1262     { X86::MINCPSrr,        X86::MINCPSrm,      TB_ALIGN_16 },
1263     { X86::MINSDrr,         X86::MINSDrm,       0 },
1264     { X86::MINCSDrr,        X86::MINCSDrm,      0 },
1265     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   TB_NO_REVERSE },
1266     { X86::MINSSrr,         X86::MINSSrm,       0 },
1267     { X86::MINCSSrr,        X86::MINCSSrm,      0 },
1268     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   TB_NO_REVERSE },
1269     { X86::MOVLHPSrr,       X86::MOVHPSrm,      TB_NO_REVERSE },
1270     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1271     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1272     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1273     { X86::MULSDrr,         X86::MULSDrm,       0 },
1274     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   TB_NO_REVERSE },
1275     { X86::MULSSrr,         X86::MULSSrm,       0 },
1276     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   TB_NO_REVERSE },
1277     { X86::OR16rr,          X86::OR16rm,        0 },
1278     { X86::OR32rr,          X86::OR32rm,        0 },
1279     { X86::OR64rr,          X86::OR64rm,        0 },
1280     { X86::OR8rr,           X86::OR8rm,         0 },
1281     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1282     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1283     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1284     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1285     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1286     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1287     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1288     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1289     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1290     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1291     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1292     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1293     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1294     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1295     { X86::PALIGNRrri,      X86::PALIGNRrmi,    TB_ALIGN_16 },
1296     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1297     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1298     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1299     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1300     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1301     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1302     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1303     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1304     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1305     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1306     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1307     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1308     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1309     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1310     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1311     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1312     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1313     { X86::PHADDSWrr,       X86::PHADDSWrm,     TB_ALIGN_16 },
1314     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1315     { X86::PHSUBSWrr,       X86::PHSUBSWrm,     TB_ALIGN_16 },
1316     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1317     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1318     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1319     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1320     { X86::PINSRWrr,        X86::PINSRWrm,      0 },
1321     { X86::PMADDUBSWrr,     X86::PMADDUBSWrm,   TB_ALIGN_16 },
1322     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1323     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1324     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1325     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1326     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1327     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1328     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1329     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1330     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1331     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1332     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1333     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1334     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1335     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1336     { X86::PMULHRSWrr,      X86::PMULHRSWrm,    TB_ALIGN_16 },
1337     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1338     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1339     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1340     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1341     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1342     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1343     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1344     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1345     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
1346     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
1347     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
1348     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1349     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1350     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1351     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1352     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1353     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1354     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1355     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1356     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1357     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1358     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1359     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1360     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1361     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1362     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1363     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1364     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1365     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1366     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1367     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1368     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1369     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1370     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1371     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1372     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1373     { X86::ROUNDSDr_Int,    X86::ROUNDSDm_Int,  TB_NO_REVERSE },
1374     { X86::ROUNDSSr_Int,    X86::ROUNDSSm_Int,  TB_NO_REVERSE },
1375     { X86::SBB16rr,         X86::SBB16rm,       0 },
1376     { X86::SBB32rr,         X86::SBB32rm,       0 },
1377     { X86::SBB64rr,         X86::SBB64rm,       0 },
1378     { X86::SBB8rr,          X86::SBB8rm,        0 },
1379     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1380     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1381     { X86::SUB16rr,         X86::SUB16rm,       0 },
1382     { X86::SUB32rr,         X86::SUB32rm,       0 },
1383     { X86::SUB64rr,         X86::SUB64rm,       0 },
1384     { X86::SUB8rr,          X86::SUB8rm,        0 },
1385     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1386     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1387     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1388     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   TB_NO_REVERSE },
1389     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1390     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   TB_NO_REVERSE },
1391     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1392     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1393     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1394     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1395     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1396     { X86::XOR16rr,         X86::XOR16rm,       0 },
1397     { X86::XOR32rr,         X86::XOR32rm,       0 },
1398     { X86::XOR64rr,         X86::XOR64rm,       0 },
1399     { X86::XOR8rr,          X86::XOR8rm,        0 },
1400     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1401     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1402 
1403     // MMX version of foldable instructions
1404     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1405     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1406     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1407     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1408     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1409     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1410     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1411     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1412     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1413     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1414     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1415     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1416     { X86::MMX_PALIGNRrri,    X86::MMX_PALIGNRrmi,    0 },
1417     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1418     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1419     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1420     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1421     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1422     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1423     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1424     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1425     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1426     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1427     { X86::MMX_PHADDDrr,      X86::MMX_PHADDDrm,      0 },
1428     { X86::MMX_PHADDSWrr,     X86::MMX_PHADDSWrm,     0 },
1429     { X86::MMX_PHADDWrr,      X86::MMX_PHADDWrm,      0 },
1430     { X86::MMX_PHSUBDrr,      X86::MMX_PHSUBDrm,      0 },
1431     { X86::MMX_PHSUBSWrr,     X86::MMX_PHSUBSWrm,     0 },
1432     { X86::MMX_PHSUBWrr,      X86::MMX_PHSUBWrm,      0 },
1433     { X86::MMX_PINSRWrr,      X86::MMX_PINSRWrm,      0 },
1434     { X86::MMX_PMADDUBSWrr,   X86::MMX_PMADDUBSWrm,   0 },
1435     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1436     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1437     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1438     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1439     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1440     { X86::MMX_PMULHRSWrr,    X86::MMX_PMULHRSWrm,    0 },
1441     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1442     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1443     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1444     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1445     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1446     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1447     { X86::MMX_PSHUFBrr,      X86::MMX_PSHUFBrm,      0 },
1448     { X86::MMX_PSIGNBrr,      X86::MMX_PSIGNBrm,      0 },
1449     { X86::MMX_PSIGNDrr,      X86::MMX_PSIGNDrm,      0 },
1450     { X86::MMX_PSIGNWrr,      X86::MMX_PSIGNWrm,      0 },
1451     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1452     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1453     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1454     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1455     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1456     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1457     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1458     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1459     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1460     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1461     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1462     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1463     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1464     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1465     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1466     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1467     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1468     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1469     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1470     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1471     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1472     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1473     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1474 
1475     // 3DNow! version of foldable instructions
1476     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1477     { X86::PFACCrr,           X86::PFACCrm,           0 },
1478     { X86::PFADDrr,           X86::PFADDrm,           0 },
1479     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1480     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1481     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1482     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1483     { X86::PFMINrr,           X86::PFMINrm,           0 },
1484     { X86::PFMULrr,           X86::PFMULrm,           0 },
1485     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1486     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1487     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1488     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1489     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1490     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1491     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1492     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1493 
1494     // AVX 128-bit versions of foldable instructions
1495     { X86::VCVTSI642SDrr,     X86::VCVTSI642SDrm,      0 },
1496     { X86::VCVTSI642SDrr_Int, X86::VCVTSI642SDrm_Int,  0 },
1497     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1498     { X86::VCVTSI2SDrr_Int,   X86::VCVTSI2SDrm_Int,    0 },
1499     { X86::VCVTSI642SSrr,     X86::VCVTSI642SSrm,      0 },
1500     { X86::VCVTSI642SSrr_Int, X86::VCVTSI642SSrm_Int,  0 },
1501     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1502     { X86::VCVTSI2SSrr_Int,   X86::VCVTSI2SSrm_Int,    0 },
1503     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1504     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1505     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1506     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       TB_NO_REVERSE },
1507     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1508     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       TB_NO_REVERSE },
1509     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1510     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1511     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1512     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1513     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1514     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1515     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1516     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1517     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1518     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1519     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1520     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1521     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1522     { X86::VCMPSDrr_Int,      X86::VCMPSDrm_Int,       TB_NO_REVERSE },
1523     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1524     { X86::VCMPSSrr_Int,      X86::VCMPSSrm_Int,       TB_NO_REVERSE },
1525     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1526     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1527     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1528     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       TB_NO_REVERSE },
1529     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1530     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       TB_NO_REVERSE },
1531     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1532     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1533     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1534     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1535     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1536     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1537     { X86::VMAXCPDrr,         X86::VMAXCPDrm,          0 },
1538     { X86::VMAXCPSrr,         X86::VMAXCPSrm,          0 },
1539     { X86::VMAXCSDrr,         X86::VMAXCSDrm,          0 },
1540     { X86::VMAXCSSrr,         X86::VMAXCSSrm,          0 },
1541     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1542     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1543     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1544     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       TB_NO_REVERSE },
1545     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1546     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       TB_NO_REVERSE },
1547     { X86::VMINCPDrr,         X86::VMINCPDrm,          0 },
1548     { X86::VMINCPSrr,         X86::VMINCPSrm,          0 },
1549     { X86::VMINCSDrr,         X86::VMINCSDrm,          0 },
1550     { X86::VMINCSSrr,         X86::VMINCSSrm,          0 },
1551     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1552     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1553     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1554     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       TB_NO_REVERSE },
1555     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1556     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       TB_NO_REVERSE },
1557     { X86::VMOVLHPSrr,        X86::VMOVHPSrm,          TB_NO_REVERSE },
1558     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1559     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1560     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1561     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1562     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       TB_NO_REVERSE },
1563     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1564     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       TB_NO_REVERSE },
1565     { X86::VORPDrr,           X86::VORPDrm,            0 },
1566     { X86::VORPSrr,           X86::VORPSrm,            0 },
1567     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1568     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1569     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1570     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1571     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1572     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1573     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1574     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1575     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1576     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1577     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1578     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1579     { X86::VPALIGNRrri,       X86::VPALIGNRrmi,        0 },
1580     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1581     { X86::VPANDrr,           X86::VPANDrm,            0 },
1582     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1583     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1584     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1585     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1586     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1587     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1588     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1589     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1590     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1591     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1592     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1593     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1594     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1595     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1596     { X86::VPHADDSWrr,        X86::VPHADDSWrm,         0 },
1597     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1598     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1599     { X86::VPHSUBSWrr,        X86::VPHSUBSWrm,         0 },
1600     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1601     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1602     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1603     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1604     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1605     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1606     { X86::VPINSRWrr,         X86::VPINSRWrm,          0 },
1607     { X86::VPMADDUBSWrr,      X86::VPMADDUBSWrm,       0 },
1608     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1609     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1610     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1611     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1612     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1613     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1614     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1615     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1616     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1617     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1618     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1619     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1620     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1621     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1622     { X86::VPMULHRSWrr,       X86::VPMULHRSWrm,        0 },
1623     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1624     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1625     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1626     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1627     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1628     { X86::VPORrr,            X86::VPORrm,             0 },
1629     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1630     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1631     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
1632     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
1633     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
1634     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1635     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1636     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1637     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1638     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1639     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1640     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1641     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1642     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1643     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1644     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1645     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1646     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1647     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1648     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1649     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1650     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1651     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1652     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1653     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1654     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1655     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1656     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1657     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1658     { X86::VPXORrr,           X86::VPXORrm,            0 },
1659     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1660     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        TB_NO_REVERSE },
1661     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1662     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      TB_NO_REVERSE },
1663     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1664     { X86::VROUNDSDr_Int,     X86::VROUNDSDm_Int,      TB_NO_REVERSE },
1665     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1666     { X86::VROUNDSSr_Int,     X86::VROUNDSSm_Int,      TB_NO_REVERSE },
1667     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1668     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1669     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1670     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       TB_NO_REVERSE },
1671     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1672     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       TB_NO_REVERSE },
1673     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1674     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1675     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1676     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       TB_NO_REVERSE },
1677     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1678     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       TB_NO_REVERSE },
1679     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1680     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1681     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1682     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1683     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1684     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1685 
1686     // AVX 256-bit foldable instructions
1687     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1688     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1689     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1690     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1691     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1692     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1693     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1694     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1695     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1696     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1697     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1698     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1699     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1700     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1701     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1702     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1703     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1704     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1705     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1706     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1707     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1708     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1709     { X86::VMAXCPDYrr,        X86::VMAXCPDYrm,         0 },
1710     { X86::VMAXCPSYrr,        X86::VMAXCPSYrm,         0 },
1711     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1712     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1713     { X86::VMINCPDYrr,        X86::VMINCPDYrm,         0 },
1714     { X86::VMINCPSYrr,        X86::VMINCPSYrm,         0 },
1715     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1716     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1717     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1718     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1719     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1720     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1721     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1722     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1723     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1724     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1725     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1726     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1727     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1728     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1729     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1730     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1731     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1732     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1733     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1734 
1735     // AVX2 foldable instructions
1736     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1737     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1738     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1739     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1740     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1741     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1742     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1743     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1744     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1745     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1746     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1747     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1748     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1749     { X86::VPALIGNRYrri,      X86::VPALIGNRYrmi,       0 },
1750     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1751     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1752     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1753     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1754     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1755     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1756     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1757     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1758     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1759     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1760     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1761     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1762     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1763     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1764     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1765     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1766     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1767     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1768     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1769     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1770     { X86::VPHADDSWYrr,       X86::VPHADDSWYrm,        0 },
1771     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1772     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1773     { X86::VPHSUBSWYrr,       X86::VPHSUBSWYrm,        0 },
1774     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1775     { X86::VPMADDUBSWYrr,     X86::VPMADDUBSWYrm,      0 },
1776     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1777     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1778     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1779     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1780     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1781     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1782     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1783     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1784     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1785     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1786     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1787     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1788     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1789     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1790     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1791     { X86::VPMULHRSWYrr,      X86::VPMULHRSWYrm,       0 },
1792     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1793     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1794     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1795     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1796     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1797     { X86::VPORYrr,           X86::VPORYrm,            0 },
1798     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1799     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1800     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1801     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1802     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1803     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1804     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1805     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1806     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1807     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1808     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1809     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1810     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1811     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1812     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1813     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1814     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1815     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1816     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1817     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1818     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1819     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1820     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1821     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1822     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1823     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1824     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1825     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1826     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1827     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1828     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1829     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1830     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1831     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1832     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1833     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1834     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1835     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1836     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1837     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1838 
1839     // FMA4 foldable patterns
1840     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1841     { X86::VFMADDSS4rr_Int,   X86::VFMADDSS4mr_Int,    TB_NO_REVERSE },
1842     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1843     { X86::VFMADDSD4rr_Int,   X86::VFMADDSD4mr_Int,    TB_NO_REVERSE },
1844     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1845     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1846     { X86::VFMADDPS4Yrr,      X86::VFMADDPS4Ymr,       TB_ALIGN_NONE },
1847     { X86::VFMADDPD4Yrr,      X86::VFMADDPD4Ymr,       TB_ALIGN_NONE },
1848     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1849     { X86::VFNMADDSS4rr_Int,  X86::VFNMADDSS4mr_Int,   TB_NO_REVERSE },
1850     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1851     { X86::VFNMADDSD4rr_Int,  X86::VFNMADDSD4mr_Int,   TB_NO_REVERSE },
1852     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1853     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1854     { X86::VFNMADDPS4Yrr,     X86::VFNMADDPS4Ymr,      TB_ALIGN_NONE },
1855     { X86::VFNMADDPD4Yrr,     X86::VFNMADDPD4Ymr,      TB_ALIGN_NONE },
1856     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1857     { X86::VFMSUBSS4rr_Int,   X86::VFMSUBSS4mr_Int,    TB_NO_REVERSE },
1858     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1859     { X86::VFMSUBSD4rr_Int,   X86::VFMSUBSD4mr_Int,    TB_NO_REVERSE },
1860     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1861     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1862     { X86::VFMSUBPS4Yrr,      X86::VFMSUBPS4Ymr,       TB_ALIGN_NONE },
1863     { X86::VFMSUBPD4Yrr,      X86::VFMSUBPD4Ymr,       TB_ALIGN_NONE },
1864     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1865     { X86::VFNMSUBSS4rr_Int,  X86::VFNMSUBSS4mr_Int,   TB_NO_REVERSE },
1866     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1867     { X86::VFNMSUBSD4rr_Int,  X86::VFNMSUBSD4mr_Int,   TB_NO_REVERSE },
1868     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1869     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1870     { X86::VFNMSUBPS4Yrr,     X86::VFNMSUBPS4Ymr,      TB_ALIGN_NONE },
1871     { X86::VFNMSUBPD4Yrr,     X86::VFNMSUBPD4Ymr,      TB_ALIGN_NONE },
1872     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1873     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1874     { X86::VFMADDSUBPS4Yrr,   X86::VFMADDSUBPS4Ymr,    TB_ALIGN_NONE },
1875     { X86::VFMADDSUBPD4Yrr,   X86::VFMADDSUBPD4Ymr,    TB_ALIGN_NONE },
1876     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1877     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1878     { X86::VFMSUBADDPS4Yrr,   X86::VFMSUBADDPS4Ymr,    TB_ALIGN_NONE },
1879     { X86::VFMSUBADDPD4Yrr,   X86::VFMSUBADDPD4Ymr,    TB_ALIGN_NONE },
1880 
1881     // XOP foldable instructions
1882     { X86::VPCMOVrrr,         X86::VPCMOVrmr,           0 },
1883     { X86::VPCMOVYrrr,        X86::VPCMOVYrmr,          0 },
1884     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1885     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1886     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1887     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1888     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1889     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1890     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1891     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1892     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1893     { X86::VPERMIL2PDYrr,     X86::VPERMIL2PDYmr,       0 },
1894     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1895     { X86::VPERMIL2PSYrr,     X86::VPERMIL2PSYmr,       0 },
1896     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1897     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1898     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1899     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1900     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1901     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1902     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1903     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1904     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1905     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1906     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1907     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1908     { X86::VPPERMrrr,         X86::VPPERMrmr,           0 },
1909     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1910     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1911     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1912     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1913     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1914     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1915     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1916     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1917     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1918     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1919     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1920     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1921 
1922     // BMI/BMI2 foldable instructions
1923     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1924     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1925     { X86::MULX32rr,          X86::MULX32rm,            0 },
1926     { X86::MULX64rr,          X86::MULX64rm,            0 },
1927     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1928     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1929     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1930     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1931 
1932     // ADX foldable instructions
1933     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1934     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1935     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1936     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1937 
1938     // AVX-512 foldable instructions
1939     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1940     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1941     { X86::VADDSDZrr,         X86::VADDSDZrm,           0 },
1942     { X86::VADDSDZrr_Int,     X86::VADDSDZrm_Int,       TB_NO_REVERSE },
1943     { X86::VADDSSZrr,         X86::VADDSSZrm,           0 },
1944     { X86::VADDSSZrr_Int,     X86::VADDSSZrm_Int,       TB_NO_REVERSE },
1945     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1946     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1947     { X86::VANDNPDZrr,        X86::VANDNPDZrm,          0 },
1948     { X86::VANDNPSZrr,        X86::VANDNPSZrm,          0 },
1949     { X86::VANDPDZrr,         X86::VANDPDZrm,           0 },
1950     { X86::VANDPSZrr,         X86::VANDPSZrm,           0 },
1951     { X86::VCMPPDZrri,        X86::VCMPPDZrmi,          0 },
1952     { X86::VCMPPSZrri,        X86::VCMPPSZrmi,          0 },
1953     { X86::VCMPSDZrr,         X86::VCMPSDZrm,           0 },
1954     { X86::VCMPSDZrr_Int,     X86::VCMPSDZrm_Int,       TB_NO_REVERSE },
1955     { X86::VCMPSSZrr,         X86::VCMPSSZrm,           0 },
1956     { X86::VCMPSSZrr_Int,     X86::VCMPSSZrm_Int,       TB_NO_REVERSE },
1957     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1958     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1959     { X86::VDIVSDZrr,         X86::VDIVSDZrm,           0 },
1960     { X86::VDIVSDZrr_Int,     X86::VDIVSDZrm_Int,       TB_NO_REVERSE },
1961     { X86::VDIVSSZrr,         X86::VDIVSSZrm,           0 },
1962     { X86::VDIVSSZrr_Int,     X86::VDIVSSZrm_Int,       TB_NO_REVERSE },
1963     { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrm,     0 },
1964     { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrm,     0 },
1965     { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrm,     0 },
1966     { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrm,     0 },
1967     { X86::VINSERTI32x4Zrr,   X86::VINSERTI32x4Zrm,     0 },
1968     { X86::VINSERTI32x8Zrr,   X86::VINSERTI32x8Zrm,     0 },
1969     { X86::VINSERTI64x2Zrr,   X86::VINSERTI64x2Zrm,     0 },
1970     { X86::VINSERTI64x4Zrr,   X86::VINSERTI64x4Zrm,     0 },
1971     { X86::VMAXCPDZrr,        X86::VMAXCPDZrm,          0 },
1972     { X86::VMAXCPSZrr,        X86::VMAXCPSZrm,          0 },
1973     { X86::VMAXCSDZrr,        X86::VMAXCSDZrm,          0 },
1974     { X86::VMAXCSSZrr,        X86::VMAXCSSZrm,          0 },
1975     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1976     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1977     { X86::VMAXSDZrr,         X86::VMAXSDZrm,           0 },
1978     { X86::VMAXSDZrr_Int,     X86::VMAXSDZrm_Int,       TB_NO_REVERSE },
1979     { X86::VMAXSSZrr,         X86::VMAXSSZrm,           0 },
1980     { X86::VMAXSSZrr_Int,     X86::VMAXSSZrm_Int,       TB_NO_REVERSE },
1981     { X86::VMINCPDZrr,        X86::VMINCPDZrm,          0 },
1982     { X86::VMINCPSZrr,        X86::VMINCPSZrm,          0 },
1983     { X86::VMINCSDZrr,        X86::VMINCSDZrm,          0 },
1984     { X86::VMINCSSZrr,        X86::VMINCSSZrm,          0 },
1985     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1986     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1987     { X86::VMINSDZrr,         X86::VMINSDZrm,           0 },
1988     { X86::VMINSDZrr_Int,     X86::VMINSDZrm_Int,       TB_NO_REVERSE },
1989     { X86::VMINSSZrr,         X86::VMINSSZrm,           0 },
1990     { X86::VMINSSZrr_Int,     X86::VMINSSZrm_Int,       TB_NO_REVERSE },
1991     { X86::VMOVLHPSZrr,       X86::VMOVHPSZ128rm,       TB_NO_REVERSE },
1992     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1993     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1994     { X86::VMULSDZrr,         X86::VMULSDZrm,           0 },
1995     { X86::VMULSDZrr_Int,     X86::VMULSDZrm_Int,       TB_NO_REVERSE },
1996     { X86::VMULSSZrr,         X86::VMULSSZrm,           0 },
1997     { X86::VMULSSZrr_Int,     X86::VMULSSZrm_Int,       TB_NO_REVERSE },
1998     { X86::VORPDZrr,          X86::VORPDZrm,            0 },
1999     { X86::VORPSZrr,          X86::VORPSZrm,            0 },
2000     { X86::VPACKSSDWZrr,      X86::VPACKSSDWZrm,        0 },
2001     { X86::VPACKSSWBZrr,      X86::VPACKSSWBZrm,        0 },
2002     { X86::VPACKUSDWZrr,      X86::VPACKUSDWZrm,        0 },
2003     { X86::VPACKUSWBZrr,      X86::VPACKUSWBZrm,        0 },
2004     { X86::VPADDBZrr,         X86::VPADDBZrm,           0 },
2005     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
2006     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
2007     { X86::VPADDSBZrr,        X86::VPADDSBZrm,          0 },
2008     { X86::VPADDSWZrr,        X86::VPADDSWZrm,          0 },
2009     { X86::VPADDUSBZrr,       X86::VPADDUSBZrm,         0 },
2010     { X86::VPADDUSWZrr,       X86::VPADDUSWZrm,         0 },
2011     { X86::VPADDWZrr,         X86::VPADDWZrm,           0 },
2012     { X86::VPALIGNRZrri,      X86::VPALIGNRZrmi,        0 },
2013     { X86::VPANDDZrr,         X86::VPANDDZrm,           0 },
2014     { X86::VPANDNDZrr,        X86::VPANDNDZrm,          0 },
2015     { X86::VPANDNQZrr,        X86::VPANDNQZrm,          0 },
2016     { X86::VPANDQZrr,         X86::VPANDQZrm,           0 },
2017     { X86::VPAVGBZrr,         X86::VPAVGBZrm,           0 },
2018     { X86::VPAVGWZrr,         X86::VPAVGWZrm,           0 },
2019     { X86::VPCMPBZrri,        X86::VPCMPBZrmi,          0 },
2020     { X86::VPCMPDZrri,        X86::VPCMPDZrmi,          0 },
2021     { X86::VPCMPEQBZrr,       X86::VPCMPEQBZrm,         0 },
2022     { X86::VPCMPEQDZrr,       X86::VPCMPEQDZrm,         0 },
2023     { X86::VPCMPEQQZrr,       X86::VPCMPEQQZrm,         0 },
2024     { X86::VPCMPEQWZrr,       X86::VPCMPEQWZrm,         0 },
2025     { X86::VPCMPGTBZrr,       X86::VPCMPGTBZrm,         0 },
2026     { X86::VPCMPGTDZrr,       X86::VPCMPGTDZrm,         0 },
2027     { X86::VPCMPGTQZrr,       X86::VPCMPGTQZrm,         0 },
2028     { X86::VPCMPGTWZrr,       X86::VPCMPGTWZrm,         0 },
2029     { X86::VPCMPQZrri,        X86::VPCMPQZrmi,          0 },
2030     { X86::VPCMPUBZrri,       X86::VPCMPUBZrmi,         0 },
2031     { X86::VPCMPUDZrri,       X86::VPCMPUDZrmi,         0 },
2032     { X86::VPCMPUQZrri,       X86::VPCMPUQZrmi,         0 },
2033     { X86::VPCMPUWZrri,       X86::VPCMPUWZrmi,         0 },
2034     { X86::VPCMPWZrri,        X86::VPCMPWZrmi,          0 },
2035     { X86::VPERMBZrr,         X86::VPERMBZrm,           0 },
2036     { X86::VPERMDZrr,         X86::VPERMDZrm,           0 },
2037     { X86::VPERMILPDZrr,      X86::VPERMILPDZrm,        0 },
2038     { X86::VPERMILPSZrr,      X86::VPERMILPSZrm,        0 },
2039     { X86::VPERMPDZrr,        X86::VPERMPDZrm,          0 },
2040     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
2041     { X86::VPERMQZrr,         X86::VPERMQZrm,           0 },
2042     { X86::VPERMWZrr,         X86::VPERMWZrm,           0 },
2043     { X86::VPINSRBZrr,        X86::VPINSRBZrm,          0 },
2044     { X86::VPINSRDZrr,        X86::VPINSRDZrm,          0 },
2045     { X86::VPINSRQZrr,        X86::VPINSRQZrm,          0 },
2046     { X86::VPINSRWZrr,        X86::VPINSRWZrm,          0 },
2047     { X86::VPMADDUBSWZrr,     X86::VPMADDUBSWZrm,       0 },
2048     { X86::VPMADDWDZrr,       X86::VPMADDWDZrm,         0 },
2049     { X86::VPMAXSBZrr,        X86::VPMAXSBZrm,          0 },
2050     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
2051     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
2052     { X86::VPMAXSWZrr,        X86::VPMAXSWZrm,          0 },
2053     { X86::VPMAXUBZrr,        X86::VPMAXUBZrm,          0 },
2054     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
2055     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
2056     { X86::VPMAXUWZrr,        X86::VPMAXUWZrm,          0 },
2057     { X86::VPMINSBZrr,        X86::VPMINSBZrm,          0 },
2058     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
2059     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
2060     { X86::VPMINSWZrr,        X86::VPMINSWZrm,          0 },
2061     { X86::VPMINUBZrr,        X86::VPMINUBZrm,          0 },
2062     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
2063     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
2064     { X86::VPMINUWZrr,        X86::VPMINUWZrm,          0 },
2065     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
2066     { X86::VPMULLDZrr,        X86::VPMULLDZrm,          0 },
2067     { X86::VPMULLQZrr,        X86::VPMULLQZrm,          0 },
2068     { X86::VPMULLWZrr,        X86::VPMULLWZrm,          0 },
2069     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
2070     { X86::VPORDZrr,          X86::VPORDZrm,            0 },
2071     { X86::VPORQZrr,          X86::VPORQZrm,            0 },
2072     { X86::VPSADBWZrr,        X86::VPSADBWZrm,          0 },
2073     { X86::VPSHUFBZrr,        X86::VPSHUFBZrm,          0 },
2074     { X86::VPSLLDZrr,         X86::VPSLLDZrm,           0 },
2075     { X86::VPSLLQZrr,         X86::VPSLLQZrm,           0 },
2076     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
2077     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
2078     { X86::VPSLLVWZrr,        X86::VPSLLVWZrm,          0 },
2079     { X86::VPSLLWZrr,         X86::VPSLLWZrm,           0 },
2080     { X86::VPSRADZrr,         X86::VPSRADZrm,           0 },
2081     { X86::VPSRAQZrr,         X86::VPSRAQZrm,           0 },
2082     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
2083     { X86::VPSRAVQZrr,        X86::VPSRAVQZrm,          0 },
2084     { X86::VPSRAVWZrr,        X86::VPSRAVWZrm,          0 },
2085     { X86::VPSRAWZrr,         X86::VPSRAWZrm,           0 },
2086     { X86::VPSRLDZrr,         X86::VPSRLDZrm,           0 },
2087     { X86::VPSRLQZrr,         X86::VPSRLQZrm,           0 },
2088     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
2089     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
2090     { X86::VPSRLVWZrr,        X86::VPSRLVWZrm,          0 },
2091     { X86::VPSRLWZrr,         X86::VPSRLWZrm,           0 },
2092     { X86::VPSUBBZrr,         X86::VPSUBBZrm,           0 },
2093     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
2094     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
2095     { X86::VPSUBSBZrr,        X86::VPSUBSBZrm,          0 },
2096     { X86::VPSUBSWZrr,        X86::VPSUBSWZrm,          0 },
2097     { X86::VPSUBUSBZrr,       X86::VPSUBUSBZrm,         0 },
2098     { X86::VPSUBUSWZrr,       X86::VPSUBUSWZrm,         0 },
2099     { X86::VPSUBWZrr,         X86::VPSUBWZrm,           0 },
2100     { X86::VPUNPCKHBWZrr,     X86::VPUNPCKHBWZrm,       0 },
2101     { X86::VPUNPCKHDQZrr,     X86::VPUNPCKHDQZrm,       0 },
2102     { X86::VPUNPCKHQDQZrr,    X86::VPUNPCKHQDQZrm,      0 },
2103     { X86::VPUNPCKHWDZrr,     X86::VPUNPCKHWDZrm,       0 },
2104     { X86::VPUNPCKLBWZrr,     X86::VPUNPCKLBWZrm,       0 },
2105     { X86::VPUNPCKLDQZrr,     X86::VPUNPCKLDQZrm,       0 },
2106     { X86::VPUNPCKLQDQZrr,    X86::VPUNPCKLQDQZrm,      0 },
2107     { X86::VPUNPCKLWDZrr,     X86::VPUNPCKLWDZrm,       0 },
2108     { X86::VPXORDZrr,         X86::VPXORDZrm,           0 },
2109     { X86::VPXORQZrr,         X86::VPXORQZrm,           0 },
2110     { X86::VSHUFF32X4Zrri,    X86::VSHUFF32X4Zrmi,      0 },
2111     { X86::VSHUFF64X2Zrri,    X86::VSHUFF64X2Zrmi,      0 },
2112     { X86::VSHUFI64X2Zrri,    X86::VSHUFI64X2Zrmi,      0 },
2113     { X86::VSHUFI32X4Zrri,    X86::VSHUFI32X4Zrmi,      0 },
2114     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
2115     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
2116     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
2117     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
2118     { X86::VSUBSDZrr,         X86::VSUBSDZrm,           0 },
2119     { X86::VSUBSDZrr_Int,     X86::VSUBSDZrm_Int,       TB_NO_REVERSE },
2120     { X86::VSUBSSZrr,         X86::VSUBSSZrm,           0 },
2121     { X86::VSUBSSZrr_Int,     X86::VSUBSSZrm_Int,       TB_NO_REVERSE },
2122     { X86::VUNPCKHPDZrr,      X86::VUNPCKHPDZrm,        0 },
2123     { X86::VUNPCKHPSZrr,      X86::VUNPCKHPSZrm,        0 },
2124     { X86::VUNPCKLPDZrr,      X86::VUNPCKLPDZrm,        0 },
2125     { X86::VUNPCKLPSZrr,      X86::VUNPCKLPSZrm,        0 },
2126     { X86::VXORPDZrr,         X86::VXORPDZrm,           0 },
2127     { X86::VXORPSZrr,         X86::VXORPSZrm,           0 },
2128 
2129     // AVX-512{F,VL} foldable instructions
2130     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
2131     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
2132     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
2133     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
2134     { X86::VALIGNDZ128rri,    X86::VALIGNDZ128rmi,      0 },
2135     { X86::VALIGNDZ256rri,    X86::VALIGNDZ256rmi,      0 },
2136     { X86::VALIGNQZ128rri,    X86::VALIGNQZ128rmi,      0 },
2137     { X86::VALIGNQZ256rri,    X86::VALIGNQZ256rmi,      0 },
2138     { X86::VANDNPDZ128rr,     X86::VANDNPDZ128rm,       0 },
2139     { X86::VANDNPDZ256rr,     X86::VANDNPDZ256rm,       0 },
2140     { X86::VANDNPSZ128rr,     X86::VANDNPSZ128rm,       0 },
2141     { X86::VANDNPSZ256rr,     X86::VANDNPSZ256rm,       0 },
2142     { X86::VANDPDZ128rr,      X86::VANDPDZ128rm,        0 },
2143     { X86::VANDPDZ256rr,      X86::VANDPDZ256rm,        0 },
2144     { X86::VANDPSZ128rr,      X86::VANDPSZ128rm,        0 },
2145     { X86::VANDPSZ256rr,      X86::VANDPSZ256rm,        0 },
2146     { X86::VCMPPDZ128rri,     X86::VCMPPDZ128rmi,       0 },
2147     { X86::VCMPPDZ256rri,     X86::VCMPPDZ256rmi,       0 },
2148     { X86::VCMPPSZ128rri,     X86::VCMPPSZ128rmi,       0 },
2149     { X86::VCMPPSZ256rri,     X86::VCMPPSZ256rmi,       0 },
2150     { X86::VDIVPDZ128rr,      X86::VDIVPDZ128rm,        0 },
2151     { X86::VDIVPDZ256rr,      X86::VDIVPDZ256rm,        0 },
2152     { X86::VDIVPSZ128rr,      X86::VDIVPSZ128rm,        0 },
2153     { X86::VDIVPSZ256rr,      X86::VDIVPSZ256rm,        0 },
2154     { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rm,  0 },
2155     { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rm,  0 },
2156     { X86::VINSERTI32x4Z256rr,X86::VINSERTI32x4Z256rm,  0 },
2157     { X86::VINSERTI64x2Z256rr,X86::VINSERTI64x2Z256rm,  0 },
2158     { X86::VMAXCPDZ128rr,     X86::VMAXCPDZ128rm,       0 },
2159     { X86::VMAXCPDZ256rr,     X86::VMAXCPDZ256rm,       0 },
2160     { X86::VMAXCPSZ128rr,     X86::VMAXCPSZ128rm,       0 },
2161     { X86::VMAXCPSZ256rr,     X86::VMAXCPSZ256rm,       0 },
2162     { X86::VMAXPDZ128rr,      X86::VMAXPDZ128rm,        0 },
2163     { X86::VMAXPDZ256rr,      X86::VMAXPDZ256rm,        0 },
2164     { X86::VMAXPSZ128rr,      X86::VMAXPSZ128rm,        0 },
2165     { X86::VMAXPSZ256rr,      X86::VMAXPSZ256rm,        0 },
2166     { X86::VMINCPDZ128rr,     X86::VMINCPDZ128rm,       0 },
2167     { X86::VMINCPDZ256rr,     X86::VMINCPDZ256rm,       0 },
2168     { X86::VMINCPSZ128rr,     X86::VMINCPSZ128rm,       0 },
2169     { X86::VMINCPSZ256rr,     X86::VMINCPSZ256rm,       0 },
2170     { X86::VMINPDZ128rr,      X86::VMINPDZ128rm,        0 },
2171     { X86::VMINPDZ256rr,      X86::VMINPDZ256rm,        0 },
2172     { X86::VMINPSZ128rr,      X86::VMINPSZ128rm,        0 },
2173     { X86::VMINPSZ256rr,      X86::VMINPSZ256rm,        0 },
2174     { X86::VMULPDZ128rr,      X86::VMULPDZ128rm,        0 },
2175     { X86::VMULPDZ256rr,      X86::VMULPDZ256rm,        0 },
2176     { X86::VMULPSZ128rr,      X86::VMULPSZ128rm,        0 },
2177     { X86::VMULPSZ256rr,      X86::VMULPSZ256rm,        0 },
2178     { X86::VORPDZ128rr,       X86::VORPDZ128rm,         0 },
2179     { X86::VORPDZ256rr,       X86::VORPDZ256rm,         0 },
2180     { X86::VORPSZ128rr,       X86::VORPSZ128rm,         0 },
2181     { X86::VORPSZ256rr,       X86::VORPSZ256rm,         0 },
2182     { X86::VPACKSSDWZ256rr,   X86::VPACKSSDWZ256rm,     0 },
2183     { X86::VPACKSSDWZ128rr,   X86::VPACKSSDWZ128rm,     0 },
2184     { X86::VPACKSSWBZ256rr,   X86::VPACKSSWBZ256rm,     0 },
2185     { X86::VPACKSSWBZ128rr,   X86::VPACKSSWBZ128rm,     0 },
2186     { X86::VPACKUSDWZ256rr,   X86::VPACKUSDWZ256rm,     0 },
2187     { X86::VPACKUSDWZ128rr,   X86::VPACKUSDWZ128rm,     0 },
2188     { X86::VPACKUSWBZ256rr,   X86::VPACKUSWBZ256rm,     0 },
2189     { X86::VPACKUSWBZ128rr,   X86::VPACKUSWBZ128rm,     0 },
2190     { X86::VPADDBZ128rr,      X86::VPADDBZ128rm,        0 },
2191     { X86::VPADDBZ256rr,      X86::VPADDBZ256rm,        0 },
2192     { X86::VPADDDZ128rr,      X86::VPADDDZ128rm,        0 },
2193     { X86::VPADDDZ256rr,      X86::VPADDDZ256rm,        0 },
2194     { X86::VPADDQZ128rr,      X86::VPADDQZ128rm,        0 },
2195     { X86::VPADDQZ256rr,      X86::VPADDQZ256rm,        0 },
2196     { X86::VPADDSBZ128rr,     X86::VPADDSBZ128rm,       0 },
2197     { X86::VPADDSBZ256rr,     X86::VPADDSBZ256rm,       0 },
2198     { X86::VPADDSWZ128rr,     X86::VPADDSWZ128rm,       0 },
2199     { X86::VPADDSWZ256rr,     X86::VPADDSWZ256rm,       0 },
2200     { X86::VPADDUSBZ128rr,    X86::VPADDUSBZ128rm,      0 },
2201     { X86::VPADDUSBZ256rr,    X86::VPADDUSBZ256rm,      0 },
2202     { X86::VPADDUSWZ128rr,    X86::VPADDUSWZ128rm,      0 },
2203     { X86::VPADDUSWZ256rr,    X86::VPADDUSWZ256rm,      0 },
2204     { X86::VPADDWZ128rr,      X86::VPADDWZ128rm,        0 },
2205     { X86::VPADDWZ256rr,      X86::VPADDWZ256rm,        0 },
2206     { X86::VPALIGNRZ128rri,   X86::VPALIGNRZ128rmi,     0 },
2207     { X86::VPALIGNRZ256rri,   X86::VPALIGNRZ256rmi,     0 },
2208     { X86::VPANDDZ128rr,      X86::VPANDDZ128rm,        0 },
2209     { X86::VPANDDZ256rr,      X86::VPANDDZ256rm,        0 },
2210     { X86::VPANDNDZ128rr,     X86::VPANDNDZ128rm,       0 },
2211     { X86::VPANDNDZ256rr,     X86::VPANDNDZ256rm,       0 },
2212     { X86::VPANDNQZ128rr,     X86::VPANDNQZ128rm,       0 },
2213     { X86::VPANDNQZ256rr,     X86::VPANDNQZ256rm,       0 },
2214     { X86::VPANDQZ128rr,      X86::VPANDQZ128rm,        0 },
2215     { X86::VPANDQZ256rr,      X86::VPANDQZ256rm,        0 },
2216     { X86::VPAVGBZ128rr,      X86::VPAVGBZ128rm,        0 },
2217     { X86::VPAVGBZ256rr,      X86::VPAVGBZ256rm,        0 },
2218     { X86::VPAVGWZ128rr,      X86::VPAVGWZ128rm,        0 },
2219     { X86::VPAVGWZ256rr,      X86::VPAVGWZ256rm,        0 },
2220     { X86::VPCMPBZ128rri,     X86::VPCMPBZ128rmi,       0 },
2221     { X86::VPCMPBZ256rri,     X86::VPCMPBZ256rmi,       0 },
2222     { X86::VPCMPDZ128rri,     X86::VPCMPDZ128rmi,       0 },
2223     { X86::VPCMPDZ256rri,     X86::VPCMPDZ256rmi,       0 },
2224     { X86::VPCMPEQBZ128rr,    X86::VPCMPEQBZ128rm,      0 },
2225     { X86::VPCMPEQBZ256rr,    X86::VPCMPEQBZ256rm,      0 },
2226     { X86::VPCMPEQDZ128rr,    X86::VPCMPEQDZ128rm,      0 },
2227     { X86::VPCMPEQDZ256rr,    X86::VPCMPEQDZ256rm,      0 },
2228     { X86::VPCMPEQQZ128rr,    X86::VPCMPEQQZ128rm,      0 },
2229     { X86::VPCMPEQQZ256rr,    X86::VPCMPEQQZ256rm,      0 },
2230     { X86::VPCMPEQWZ128rr,    X86::VPCMPEQWZ128rm,      0 },
2231     { X86::VPCMPEQWZ256rr,    X86::VPCMPEQWZ256rm,      0 },
2232     { X86::VPCMPGTBZ128rr,    X86::VPCMPGTBZ128rm,      0 },
2233     { X86::VPCMPGTBZ256rr,    X86::VPCMPGTBZ256rm,      0 },
2234     { X86::VPCMPGTDZ128rr,    X86::VPCMPGTDZ128rm,      0 },
2235     { X86::VPCMPGTDZ256rr,    X86::VPCMPGTDZ256rm,      0 },
2236     { X86::VPCMPGTQZ128rr,    X86::VPCMPGTQZ128rm,      0 },
2237     { X86::VPCMPGTQZ256rr,    X86::VPCMPGTQZ256rm,      0 },
2238     { X86::VPCMPGTWZ128rr,    X86::VPCMPGTWZ128rm,      0 },
2239     { X86::VPCMPGTWZ256rr,    X86::VPCMPGTWZ256rm,      0 },
2240     { X86::VPCMPQZ128rri,     X86::VPCMPQZ128rmi,       0 },
2241     { X86::VPCMPQZ256rri,     X86::VPCMPQZ256rmi,       0 },
2242     { X86::VPCMPUBZ128rri,    X86::VPCMPUBZ128rmi,      0 },
2243     { X86::VPCMPUBZ256rri,    X86::VPCMPUBZ256rmi,      0 },
2244     { X86::VPCMPUDZ128rri,    X86::VPCMPUDZ128rmi,      0 },
2245     { X86::VPCMPUDZ256rri,    X86::VPCMPUDZ256rmi,      0 },
2246     { X86::VPCMPUQZ128rri,    X86::VPCMPUQZ128rmi,      0 },
2247     { X86::VPCMPUQZ256rri,    X86::VPCMPUQZ256rmi,      0 },
2248     { X86::VPCMPUWZ128rri,    X86::VPCMPUWZ128rmi,      0 },
2249     { X86::VPCMPUWZ256rri,    X86::VPCMPUWZ256rmi,      0 },
2250     { X86::VPCMPWZ128rri,     X86::VPCMPWZ128rmi,       0 },
2251     { X86::VPCMPWZ256rri,     X86::VPCMPWZ256rmi,       0 },
2252     { X86::VPERMBZ128rr,      X86::VPERMBZ128rm,        0 },
2253     { X86::VPERMBZ256rr,      X86::VPERMBZ256rm,        0 },
2254     { X86::VPERMDZ256rr,      X86::VPERMDZ256rm,        0 },
2255     { X86::VPERMILPDZ128rr,   X86::VPERMILPDZ128rm,     0 },
2256     { X86::VPERMILPDZ256rr,   X86::VPERMILPDZ256rm,     0 },
2257     { X86::VPERMILPSZ128rr,   X86::VPERMILPSZ128rm,     0 },
2258     { X86::VPERMILPSZ256rr,   X86::VPERMILPSZ256rm,     0 },
2259     { X86::VPERMPDZ256rr,     X86::VPERMPDZ256rm,       0 },
2260     { X86::VPERMPSZ256rr,     X86::VPERMPSZ256rm,       0 },
2261     { X86::VPERMQZ256rr,      X86::VPERMQZ256rm,        0 },
2262     { X86::VPERMWZ128rr,      X86::VPERMWZ128rm,        0 },
2263     { X86::VPERMWZ256rr,      X86::VPERMWZ256rm,        0 },
2264     { X86::VPMADDUBSWZ128rr,  X86::VPMADDUBSWZ128rm,    0 },
2265     { X86::VPMADDUBSWZ256rr,  X86::VPMADDUBSWZ256rm,    0 },
2266     { X86::VPMADDWDZ128rr,    X86::VPMADDWDZ128rm,      0 },
2267     { X86::VPMADDWDZ256rr,    X86::VPMADDWDZ256rm,      0 },
2268     { X86::VPMAXSBZ128rr,     X86::VPMAXSBZ128rm,       0 },
2269     { X86::VPMAXSBZ256rr,     X86::VPMAXSBZ256rm,       0 },
2270     { X86::VPMAXSDZ128rr,     X86::VPMAXSDZ128rm,       0 },
2271     { X86::VPMAXSDZ256rr,     X86::VPMAXSDZ256rm,       0 },
2272     { X86::VPMAXSQZ128rr,     X86::VPMAXSQZ128rm,       0 },
2273     { X86::VPMAXSQZ256rr,     X86::VPMAXSQZ256rm,       0 },
2274     { X86::VPMAXSWZ128rr,     X86::VPMAXSWZ128rm,       0 },
2275     { X86::VPMAXSWZ256rr,     X86::VPMAXSWZ256rm,       0 },
2276     { X86::VPMAXUBZ128rr,     X86::VPMAXUBZ128rm,       0 },
2277     { X86::VPMAXUBZ256rr,     X86::VPMAXUBZ256rm,       0 },
2278     { X86::VPMAXUDZ128rr,     X86::VPMAXUDZ128rm,       0 },
2279     { X86::VPMAXUDZ256rr,     X86::VPMAXUDZ256rm,       0 },
2280     { X86::VPMAXUQZ128rr,     X86::VPMAXUQZ128rm,       0 },
2281     { X86::VPMAXUQZ256rr,     X86::VPMAXUQZ256rm,       0 },
2282     { X86::VPMAXUWZ128rr,     X86::VPMAXUWZ128rm,       0 },
2283     { X86::VPMAXUWZ256rr,     X86::VPMAXUWZ256rm,       0 },
2284     { X86::VPMINSBZ128rr,     X86::VPMINSBZ128rm,       0 },
2285     { X86::VPMINSBZ256rr,     X86::VPMINSBZ256rm,       0 },
2286     { X86::VPMINSDZ128rr,     X86::VPMINSDZ128rm,       0 },
2287     { X86::VPMINSDZ256rr,     X86::VPMINSDZ256rm,       0 },
2288     { X86::VPMINSQZ128rr,     X86::VPMINSQZ128rm,       0 },
2289     { X86::VPMINSQZ256rr,     X86::VPMINSQZ256rm,       0 },
2290     { X86::VPMINSWZ128rr,     X86::VPMINSWZ128rm,       0 },
2291     { X86::VPMINSWZ256rr,     X86::VPMINSWZ256rm,       0 },
2292     { X86::VPMINUBZ128rr,     X86::VPMINUBZ128rm,       0 },
2293     { X86::VPMINUBZ256rr,     X86::VPMINUBZ256rm,       0 },
2294     { X86::VPMINUDZ128rr,     X86::VPMINUDZ128rm,       0 },
2295     { X86::VPMINUDZ256rr,     X86::VPMINUDZ256rm,       0 },
2296     { X86::VPMINUQZ128rr,     X86::VPMINUQZ128rm,       0 },
2297     { X86::VPMINUQZ256rr,     X86::VPMINUQZ256rm,       0 },
2298     { X86::VPMINUWZ128rr,     X86::VPMINUWZ128rm,       0 },
2299     { X86::VPMINUWZ256rr,     X86::VPMINUWZ256rm,       0 },
2300     { X86::VPMULDQZ128rr,     X86::VPMULDQZ128rm,       0 },
2301     { X86::VPMULDQZ256rr,     X86::VPMULDQZ256rm,       0 },
2302     { X86::VPMULLDZ128rr,     X86::VPMULLDZ128rm,       0 },
2303     { X86::VPMULLDZ256rr,     X86::VPMULLDZ256rm,       0 },
2304     { X86::VPMULLQZ128rr,     X86::VPMULLQZ128rm,       0 },
2305     { X86::VPMULLQZ256rr,     X86::VPMULLQZ256rm,       0 },
2306     { X86::VPMULLWZ128rr,     X86::VPMULLWZ128rm,       0 },
2307     { X86::VPMULLWZ256rr,     X86::VPMULLWZ256rm,       0 },
2308     { X86::VPMULUDQZ128rr,    X86::VPMULUDQZ128rm,      0 },
2309     { X86::VPMULUDQZ256rr,    X86::VPMULUDQZ256rm,      0 },
2310     { X86::VPORDZ128rr,       X86::VPORDZ128rm,         0 },
2311     { X86::VPORDZ256rr,       X86::VPORDZ256rm,         0 },
2312     { X86::VPORQZ128rr,       X86::VPORQZ128rm,         0 },
2313     { X86::VPORQZ256rr,       X86::VPORQZ256rm,         0 },
2314     { X86::VPSADBWZ128rr,     X86::VPSADBWZ128rm,       0 },
2315     { X86::VPSADBWZ256rr,     X86::VPSADBWZ256rm,       0 },
2316     { X86::VPSHUFBZ128rr,     X86::VPSHUFBZ128rm,       0 },
2317     { X86::VPSHUFBZ256rr,     X86::VPSHUFBZ256rm,       0 },
2318     { X86::VPSLLDZ128rr,      X86::VPSLLDZ128rm,        0 },
2319     { X86::VPSLLDZ256rr,      X86::VPSLLDZ256rm,        0 },
2320     { X86::VPSLLQZ128rr,      X86::VPSLLQZ128rm,        0 },
2321     { X86::VPSLLQZ256rr,      X86::VPSLLQZ256rm,        0 },
2322     { X86::VPSLLVDZ128rr,     X86::VPSLLVDZ128rm,       0 },
2323     { X86::VPSLLVDZ256rr,     X86::VPSLLVDZ256rm,       0 },
2324     { X86::VPSLLVQZ128rr,     X86::VPSLLVQZ128rm,       0 },
2325     { X86::VPSLLVQZ256rr,     X86::VPSLLVQZ256rm,       0 },
2326     { X86::VPSLLVWZ128rr,     X86::VPSLLVWZ128rm,       0 },
2327     { X86::VPSLLVWZ256rr,     X86::VPSLLVWZ256rm,       0 },
2328     { X86::VPSLLWZ128rr,      X86::VPSLLWZ128rm,        0 },
2329     { X86::VPSLLWZ256rr,      X86::VPSLLWZ256rm,        0 },
2330     { X86::VPSRADZ128rr,      X86::VPSRADZ128rm,        0 },
2331     { X86::VPSRADZ256rr,      X86::VPSRADZ256rm,        0 },
2332     { X86::VPSRAQZ128rr,      X86::VPSRAQZ128rm,        0 },
2333     { X86::VPSRAQZ256rr,      X86::VPSRAQZ256rm,        0 },
2334     { X86::VPSRAVDZ128rr,     X86::VPSRAVDZ128rm,       0 },
2335     { X86::VPSRAVDZ256rr,     X86::VPSRAVDZ256rm,       0 },
2336     { X86::VPSRAVQZ128rr,     X86::VPSRAVQZ128rm,       0 },
2337     { X86::VPSRAVQZ256rr,     X86::VPSRAVQZ256rm,       0 },
2338     { X86::VPSRAVWZ128rr,     X86::VPSRAVWZ128rm,       0 },
2339     { X86::VPSRAVWZ256rr,     X86::VPSRAVWZ256rm,       0 },
2340     { X86::VPSRAWZ128rr,      X86::VPSRAWZ128rm,        0 },
2341     { X86::VPSRAWZ256rr,      X86::VPSRAWZ256rm,        0 },
2342     { X86::VPSRLDZ128rr,      X86::VPSRLDZ128rm,        0 },
2343     { X86::VPSRLDZ256rr,      X86::VPSRLDZ256rm,        0 },
2344     { X86::VPSRLQZ128rr,      X86::VPSRLQZ128rm,        0 },
2345     { X86::VPSRLQZ256rr,      X86::VPSRLQZ256rm,        0 },
2346     { X86::VPSRLVDZ128rr,     X86::VPSRLVDZ128rm,       0 },
2347     { X86::VPSRLVDZ256rr,     X86::VPSRLVDZ256rm,       0 },
2348     { X86::VPSRLVQZ128rr,     X86::VPSRLVQZ128rm,       0 },
2349     { X86::VPSRLVQZ256rr,     X86::VPSRLVQZ256rm,       0 },
2350     { X86::VPSRLVWZ128rr,     X86::VPSRLVWZ128rm,       0 },
2351     { X86::VPSRLVWZ256rr,     X86::VPSRLVWZ256rm,       0 },
2352     { X86::VPSRLWZ128rr,      X86::VPSRLWZ128rm,        0 },
2353     { X86::VPSRLWZ256rr,      X86::VPSRLWZ256rm,        0 },
2354     { X86::VPSUBBZ128rr,      X86::VPSUBBZ128rm,        0 },
2355     { X86::VPSUBBZ256rr,      X86::VPSUBBZ256rm,        0 },
2356     { X86::VPSUBDZ128rr,      X86::VPSUBDZ128rm,        0 },
2357     { X86::VPSUBDZ256rr,      X86::VPSUBDZ256rm,        0 },
2358     { X86::VPSUBQZ128rr,      X86::VPSUBQZ128rm,        0 },
2359     { X86::VPSUBQZ256rr,      X86::VPSUBQZ256rm,        0 },
2360     { X86::VPSUBSBZ128rr,     X86::VPSUBSBZ128rm,       0 },
2361     { X86::VPSUBSBZ256rr,     X86::VPSUBSBZ256rm,       0 },
2362     { X86::VPSUBSWZ128rr,     X86::VPSUBSWZ128rm,       0 },
2363     { X86::VPSUBSWZ256rr,     X86::VPSUBSWZ256rm,       0 },
2364     { X86::VPSUBUSBZ128rr,    X86::VPSUBUSBZ128rm,      0 },
2365     { X86::VPSUBUSBZ256rr,    X86::VPSUBUSBZ256rm,      0 },
2366     { X86::VPSUBUSWZ128rr,    X86::VPSUBUSWZ128rm,      0 },
2367     { X86::VPSUBUSWZ256rr,    X86::VPSUBUSWZ256rm,      0 },
2368     { X86::VPSUBWZ128rr,      X86::VPSUBWZ128rm,        0 },
2369     { X86::VPSUBWZ256rr,      X86::VPSUBWZ256rm,        0 },
2370     { X86::VPUNPCKHBWZ128rr,  X86::VPUNPCKHBWZ128rm,    0 },
2371     { X86::VPUNPCKHBWZ256rr,  X86::VPUNPCKHBWZ256rm,    0 },
2372     { X86::VPUNPCKHDQZ128rr,  X86::VPUNPCKHDQZ128rm,    0 },
2373     { X86::VPUNPCKHDQZ256rr,  X86::VPUNPCKHDQZ256rm,    0 },
2374     { X86::VPUNPCKHQDQZ128rr, X86::VPUNPCKHQDQZ128rm,   0 },
2375     { X86::VPUNPCKHQDQZ256rr, X86::VPUNPCKHQDQZ256rm,   0 },
2376     { X86::VPUNPCKHWDZ128rr,  X86::VPUNPCKHWDZ128rm,    0 },
2377     { X86::VPUNPCKHWDZ256rr,  X86::VPUNPCKHWDZ256rm,    0 },
2378     { X86::VPUNPCKLBWZ128rr,  X86::VPUNPCKLBWZ128rm,    0 },
2379     { X86::VPUNPCKLBWZ256rr,  X86::VPUNPCKLBWZ256rm,    0 },
2380     { X86::VPUNPCKLDQZ128rr,  X86::VPUNPCKLDQZ128rm,    0 },
2381     { X86::VPUNPCKLDQZ256rr,  X86::VPUNPCKLDQZ256rm,    0 },
2382     { X86::VPUNPCKLQDQZ128rr, X86::VPUNPCKLQDQZ128rm,   0 },
2383     { X86::VPUNPCKLQDQZ256rr, X86::VPUNPCKLQDQZ256rm,   0 },
2384     { X86::VPUNPCKLWDZ128rr,  X86::VPUNPCKLWDZ128rm,    0 },
2385     { X86::VPUNPCKLWDZ256rr,  X86::VPUNPCKLWDZ256rm,    0 },
2386     { X86::VPXORDZ128rr,      X86::VPXORDZ128rm,        0 },
2387     { X86::VPXORDZ256rr,      X86::VPXORDZ256rm,        0 },
2388     { X86::VPXORQZ128rr,      X86::VPXORQZ128rm,        0 },
2389     { X86::VPXORQZ256rr,      X86::VPXORQZ256rm,        0 },
2390     { X86::VSHUFF32X4Z256rri, X86::VSHUFF32X4Z256rmi,   0 },
2391     { X86::VSHUFF64X2Z256rri, X86::VSHUFF64X2Z256rmi,   0 },
2392     { X86::VSHUFI32X4Z256rri, X86::VSHUFI32X4Z256rmi,   0 },
2393     { X86::VSHUFI64X2Z256rri, X86::VSHUFI64X2Z256rmi,   0 },
2394     { X86::VSHUFPDZ128rri,    X86::VSHUFPDZ128rmi,      0 },
2395     { X86::VSHUFPDZ256rri,    X86::VSHUFPDZ256rmi,      0 },
2396     { X86::VSHUFPSZ128rri,    X86::VSHUFPSZ128rmi,      0 },
2397     { X86::VSHUFPSZ256rri,    X86::VSHUFPSZ256rmi,      0 },
2398     { X86::VSUBPDZ128rr,      X86::VSUBPDZ128rm,        0 },
2399     { X86::VSUBPDZ256rr,      X86::VSUBPDZ256rm,        0 },
2400     { X86::VSUBPSZ128rr,      X86::VSUBPSZ128rm,        0 },
2401     { X86::VSUBPSZ256rr,      X86::VSUBPSZ256rm,        0 },
2402     { X86::VUNPCKHPDZ128rr,   X86::VUNPCKHPDZ128rm,     0 },
2403     { X86::VUNPCKHPDZ256rr,   X86::VUNPCKHPDZ256rm,     0 },
2404     { X86::VUNPCKHPSZ128rr,   X86::VUNPCKHPSZ128rm,     0 },
2405     { X86::VUNPCKHPSZ256rr,   X86::VUNPCKHPSZ256rm,     0 },
2406     { X86::VUNPCKLPDZ128rr,   X86::VUNPCKLPDZ128rm,     0 },
2407     { X86::VUNPCKLPDZ256rr,   X86::VUNPCKLPDZ256rm,     0 },
2408     { X86::VUNPCKLPSZ128rr,   X86::VUNPCKLPSZ128rm,     0 },
2409     { X86::VUNPCKLPSZ256rr,   X86::VUNPCKLPSZ256rm,     0 },
2410     { X86::VXORPDZ128rr,      X86::VXORPDZ128rm,        0 },
2411     { X86::VXORPDZ256rr,      X86::VXORPDZ256rm,        0 },
2412     { X86::VXORPSZ128rr,      X86::VXORPSZ128rm,        0 },
2413     { X86::VXORPSZ256rr,      X86::VXORPSZ256rm,        0 },
2414 
2415     // AVX-512 masked foldable instructions
2416     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
2417     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
2418     { X86::VPABSBZrrkz,       X86::VPABSBZrmkz,         0 },
2419     { X86::VPABSDZrrkz,       X86::VPABSDZrmkz,         0 },
2420     { X86::VPABSQZrrkz,       X86::VPABSQZrmkz,         0 },
2421     { X86::VPABSWZrrkz,       X86::VPABSWZrmkz,         0 },
2422     { X86::VPCONFLICTDZrrkz,  X86::VPCONFLICTDZrmkz,    0 },
2423     { X86::VPCONFLICTQZrrkz,  X86::VPCONFLICTQZrmkz,    0 },
2424     { X86::VPERMILPDZrikz,    X86::VPERMILPDZmikz,      0 },
2425     { X86::VPERMILPSZrikz,    X86::VPERMILPSZmikz,      0 },
2426     { X86::VPERMPDZrikz,      X86::VPERMPDZmikz,        0 },
2427     { X86::VPERMQZrikz,       X86::VPERMQZmikz,         0 },
2428     { X86::VPLZCNTDZrrkz,     X86::VPLZCNTDZrmkz,       0 },
2429     { X86::VPLZCNTQZrrkz,     X86::VPLZCNTQZrmkz,       0 },
2430     { X86::VPMOVSXBDZrrkz,    X86::VPMOVSXBDZrmkz,      0 },
2431     { X86::VPMOVSXBQZrrkz,    X86::VPMOVSXBQZrmkz,      TB_NO_REVERSE },
2432     { X86::VPMOVSXBWZrrkz,    X86::VPMOVSXBWZrmkz,      0 },
2433     { X86::VPMOVSXDQZrrkz,    X86::VPMOVSXDQZrmkz,      0 },
2434     { X86::VPMOVSXWDZrrkz,    X86::VPMOVSXWDZrmkz,      0 },
2435     { X86::VPMOVSXWQZrrkz,    X86::VPMOVSXWQZrmkz,      0 },
2436     { X86::VPMOVZXBDZrrkz,    X86::VPMOVZXBDZrmkz,      0 },
2437     { X86::VPMOVZXBQZrrkz,    X86::VPMOVZXBQZrmkz,      TB_NO_REVERSE },
2438     { X86::VPMOVZXBWZrrkz,    X86::VPMOVZXBWZrmkz,      0 },
2439     { X86::VPMOVZXDQZrrkz,    X86::VPMOVZXDQZrmkz,      0 },
2440     { X86::VPMOVZXWDZrrkz,    X86::VPMOVZXWDZrmkz,      0 },
2441     { X86::VPMOVZXWQZrrkz,    X86::VPMOVZXWQZrmkz,      0 },
2442     { X86::VPOPCNTBZrrkz,     X86::VPOPCNTBZrmkz,       0 },
2443     { X86::VPOPCNTDZrrkz,     X86::VPOPCNTDZrmkz,       0 },
2444     { X86::VPOPCNTQZrrkz,     X86::VPOPCNTQZrmkz,       0 },
2445     { X86::VPOPCNTWZrrkz,     X86::VPOPCNTWZrmkz,       0 },
2446     { X86::VPSHUFDZrikz,      X86::VPSHUFDZmikz,        0 },
2447     { X86::VPSHUFHWZrikz,     X86::VPSHUFHWZmikz,       0 },
2448     { X86::VPSHUFLWZrikz,     X86::VPSHUFLWZmikz,       0 },
2449     { X86::VPSLLDZrikz,       X86::VPSLLDZmikz,         0 },
2450     { X86::VPSLLQZrikz,       X86::VPSLLQZmikz,         0 },
2451     { X86::VPSLLWZrikz,       X86::VPSLLWZmikz,         0 },
2452     { X86::VPSRADZrikz,       X86::VPSRADZmikz,         0 },
2453     { X86::VPSRAQZrikz,       X86::VPSRAQZmikz,         0 },
2454     { X86::VPSRAWZrikz,       X86::VPSRAWZmikz,         0 },
2455     { X86::VPSRLDZrikz,       X86::VPSRLDZmikz,         0 },
2456     { X86::VPSRLQZrikz,       X86::VPSRLQZmikz,         0 },
2457     { X86::VPSRLWZrikz,       X86::VPSRLWZmikz,         0 },
2458 
2459     // AVX-512VL 256-bit masked foldable instructions
2460     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
2461     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
2462     { X86::VPABSBZ256rrkz,    X86::VPABSBZ256rmkz,      0 },
2463     { X86::VPABSDZ256rrkz,    X86::VPABSDZ256rmkz,      0 },
2464     { X86::VPABSQZ256rrkz,    X86::VPABSQZ256rmkz,      0 },
2465     { X86::VPABSWZ256rrkz,    X86::VPABSWZ256rmkz,      0 },
2466     { X86::VPCONFLICTDZ256rrkz, X86::VPCONFLICTDZ256rmkz, 0 },
2467     { X86::VPCONFLICTQZ256rrkz, X86::VPCONFLICTQZ256rmkz, 0 },
2468     { X86::VPERMILPDZ256rikz, X86::VPERMILPDZ256mikz,   0 },
2469     { X86::VPERMILPSZ256rikz, X86::VPERMILPSZ256mikz,   0 },
2470     { X86::VPERMPDZ256rikz,   X86::VPERMPDZ256mikz,     0 },
2471     { X86::VPERMQZ256rikz,    X86::VPERMQZ256mikz,      0 },
2472     { X86::VPLZCNTDZ256rrkz,  X86::VPLZCNTDZ256rmkz,    0 },
2473     { X86::VPLZCNTQZ256rrkz,  X86::VPLZCNTQZ256rmkz,    0 },
2474     { X86::VPMOVSXBDZ256rrkz, X86::VPMOVSXBDZ256rmkz,   TB_NO_REVERSE },
2475     { X86::VPMOVSXBQZ256rrkz, X86::VPMOVSXBQZ256rmkz,   TB_NO_REVERSE },
2476     { X86::VPMOVSXBWZ256rrkz, X86::VPMOVSXBWZ256rmkz,   0 },
2477     { X86::VPMOVSXDQZ256rrkz, X86::VPMOVSXDQZ256rmkz,   0 },
2478     { X86::VPMOVSXWDZ256rrkz, X86::VPMOVSXWDZ256rmkz,   0 },
2479     { X86::VPMOVSXWQZ256rrkz, X86::VPMOVSXWQZ256rmkz,   TB_NO_REVERSE },
2480     { X86::VPMOVZXBDZ256rrkz, X86::VPMOVZXBDZ256rmkz,   TB_NO_REVERSE },
2481     { X86::VPMOVZXBQZ256rrkz, X86::VPMOVZXBQZ256rmkz,   TB_NO_REVERSE },
2482     { X86::VPMOVZXBWZ256rrkz, X86::VPMOVZXBWZ256rmkz,   0 },
2483     { X86::VPMOVZXDQZ256rrkz, X86::VPMOVZXDQZ256rmkz,   0 },
2484     { X86::VPMOVZXWDZ256rrkz, X86::VPMOVZXWDZ256rmkz,   0 },
2485     { X86::VPMOVZXWQZ256rrkz, X86::VPMOVZXWQZ256rmkz,   TB_NO_REVERSE },
2486     { X86::VPOPCNTBZ256rrkz,  X86::VPOPCNTBZ256rmkz,    0 },
2487     { X86::VPOPCNTDZ256rrkz,  X86::VPOPCNTDZ256rmkz,    0 },
2488     { X86::VPOPCNTQZ256rrkz,  X86::VPOPCNTQZ256rmkz,    0 },
2489     { X86::VPOPCNTWZ256rrkz,  X86::VPOPCNTWZ256rmkz,    0 },
2490     { X86::VPSHUFDZ256rikz,   X86::VPSHUFDZ256mikz,     0 },
2491     { X86::VPSHUFHWZ256rikz,  X86::VPSHUFHWZ256mikz,    0 },
2492     { X86::VPSHUFLWZ256rikz,  X86::VPSHUFLWZ256mikz,    0 },
2493     { X86::VPSLLDZ256rikz,    X86::VPSLLDZ256mikz,      0 },
2494     { X86::VPSLLQZ256rikz,    X86::VPSLLQZ256mikz,      0 },
2495     { X86::VPSLLWZ256rikz,    X86::VPSLLWZ256mikz,      0 },
2496     { X86::VPSRADZ256rikz,    X86::VPSRADZ256mikz,      0 },
2497     { X86::VPSRAQZ256rikz,    X86::VPSRAQZ256mikz,      0 },
2498     { X86::VPSRAWZ256rikz,    X86::VPSRAWZ256mikz,      0 },
2499     { X86::VPSRLDZ256rikz,    X86::VPSRLDZ256mikz,      0 },
2500     { X86::VPSRLQZ256rikz,    X86::VPSRLQZ256mikz,      0 },
2501     { X86::VPSRLWZ256rikz,    X86::VPSRLWZ256mikz,      0 },
2502 
2503     // AVX-512VL 128-bit masked foldable instructions
2504     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
2505     { X86::VPABSBZ128rrkz,    X86::VPABSBZ128rmkz,      0 },
2506     { X86::VPABSDZ128rrkz,    X86::VPABSDZ128rmkz,      0 },
2507     { X86::VPABSQZ128rrkz,    X86::VPABSQZ128rmkz,      0 },
2508     { X86::VPABSWZ128rrkz,    X86::VPABSWZ128rmkz,      0 },
2509     { X86::VPCONFLICTDZ128rrkz, X86::VPCONFLICTDZ128rmkz, 0 },
2510     { X86::VPCONFLICTQZ128rrkz, X86::VPCONFLICTQZ128rmkz, 0 },
2511     { X86::VPERMILPDZ128rikz, X86::VPERMILPDZ128mikz,   0 },
2512     { X86::VPERMILPSZ128rikz, X86::VPERMILPSZ128mikz,   0 },
2513     { X86::VPLZCNTDZ128rrkz,  X86::VPLZCNTDZ128rmkz,    0 },
2514     { X86::VPLZCNTQZ128rrkz,  X86::VPLZCNTQZ128rmkz,    0 },
2515     { X86::VPMOVSXBDZ128rrkz, X86::VPMOVSXBDZ128rmkz,   TB_NO_REVERSE },
2516     { X86::VPMOVSXBQZ128rrkz, X86::VPMOVSXBQZ128rmkz,   TB_NO_REVERSE },
2517     { X86::VPMOVSXBWZ128rrkz, X86::VPMOVSXBWZ128rmkz,   TB_NO_REVERSE },
2518     { X86::VPMOVSXDQZ128rrkz, X86::VPMOVSXDQZ128rmkz,   TB_NO_REVERSE },
2519     { X86::VPMOVSXWDZ128rrkz, X86::VPMOVSXWDZ128rmkz,   TB_NO_REVERSE },
2520     { X86::VPMOVSXWQZ128rrkz, X86::VPMOVSXWQZ128rmkz,   TB_NO_REVERSE },
2521     { X86::VPMOVZXBDZ128rrkz, X86::VPMOVZXBDZ128rmkz,   TB_NO_REVERSE },
2522     { X86::VPMOVZXBQZ128rrkz, X86::VPMOVZXBQZ128rmkz,   TB_NO_REVERSE },
2523     { X86::VPMOVZXBWZ128rrkz, X86::VPMOVZXBWZ128rmkz,   TB_NO_REVERSE },
2524     { X86::VPMOVZXDQZ128rrkz, X86::VPMOVZXDQZ128rmkz,   TB_NO_REVERSE },
2525     { X86::VPMOVZXWDZ128rrkz, X86::VPMOVZXWDZ128rmkz,   TB_NO_REVERSE },
2526     { X86::VPMOVZXWQZ128rrkz, X86::VPMOVZXWQZ128rmkz,   TB_NO_REVERSE },
2527     { X86::VPOPCNTBZ128rrkz,  X86::VPOPCNTBZ128rmkz,    0 },
2528     { X86::VPOPCNTDZ128rrkz,  X86::VPOPCNTDZ128rmkz,    0 },
2529     { X86::VPOPCNTQZ128rrkz,  X86::VPOPCNTQZ128rmkz,    0 },
2530     { X86::VPOPCNTWZ128rrkz,  X86::VPOPCNTWZ128rmkz,    0 },
2531     { X86::VPSHUFDZ128rikz,   X86::VPSHUFDZ128mikz,     0 },
2532     { X86::VPSHUFHWZ128rikz,  X86::VPSHUFHWZ128mikz,    0 },
2533     { X86::VPSHUFLWZ128rikz,  X86::VPSHUFLWZ128mikz,    0 },
2534     { X86::VPSLLDZ128rikz,    X86::VPSLLDZ128mikz,      0 },
2535     { X86::VPSLLQZ128rikz,    X86::VPSLLQZ128mikz,      0 },
2536     { X86::VPSLLWZ128rikz,    X86::VPSLLWZ128mikz,      0 },
2537     { X86::VPSRADZ128rikz,    X86::VPSRADZ128mikz,      0 },
2538     { X86::VPSRAQZ128rikz,    X86::VPSRAQZ128mikz,      0 },
2539     { X86::VPSRAWZ128rikz,    X86::VPSRAWZ128mikz,      0 },
2540     { X86::VPSRLDZ128rikz,    X86::VPSRLDZ128mikz,      0 },
2541     { X86::VPSRLQZ128rikz,    X86::VPSRLQZ128mikz,      0 },
2542     { X86::VPSRLWZ128rikz,    X86::VPSRLWZ128mikz,      0 },
2543 
2544     // AES foldable instructions
2545     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
2546     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
2547     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
2548     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
2549     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
2550     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
2551     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
2552     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
2553 
2554     // SHA foldable instructions
2555     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
2556     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
2557     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
2558     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
2559     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
2560     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
2561     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
2562   };
2563 
2564   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
2565     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
2566                   Entry.RegOp, Entry.MemOp,
2567                   // Index 2, folded load
2568                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
2569   }
2570 
2571   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
2572     // FMA4 foldable patterns
2573     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
2574     { X86::VFMADDSS4rr_Int,       X86::VFMADDSS4rm_Int,       TB_NO_REVERSE },
2575     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
2576     { X86::VFMADDSD4rr_Int,       X86::VFMADDSD4rm_Int,       TB_NO_REVERSE },
2577     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
2578     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
2579     { X86::VFMADDPS4Yrr,          X86::VFMADDPS4Yrm,          TB_ALIGN_NONE },
2580     { X86::VFMADDPD4Yrr,          X86::VFMADDPD4Yrm,          TB_ALIGN_NONE },
2581     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
2582     { X86::VFNMADDSS4rr_Int,      X86::VFNMADDSS4rm_Int,      TB_NO_REVERSE },
2583     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
2584     { X86::VFNMADDSD4rr_Int,      X86::VFNMADDSD4rm_Int,      TB_NO_REVERSE },
2585     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
2586     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
2587     { X86::VFNMADDPS4Yrr,         X86::VFNMADDPS4Yrm,         TB_ALIGN_NONE },
2588     { X86::VFNMADDPD4Yrr,         X86::VFNMADDPD4Yrm,         TB_ALIGN_NONE },
2589     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
2590     { X86::VFMSUBSS4rr_Int,       X86::VFMSUBSS4rm_Int,       TB_NO_REVERSE },
2591     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
2592     { X86::VFMSUBSD4rr_Int,       X86::VFMSUBSD4rm_Int,       TB_NO_REVERSE },
2593     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
2594     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
2595     { X86::VFMSUBPS4Yrr,          X86::VFMSUBPS4Yrm,          TB_ALIGN_NONE },
2596     { X86::VFMSUBPD4Yrr,          X86::VFMSUBPD4Yrm,          TB_ALIGN_NONE },
2597     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
2598     { X86::VFNMSUBSS4rr_Int,      X86::VFNMSUBSS4rm_Int,      TB_NO_REVERSE },
2599     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
2600     { X86::VFNMSUBSD4rr_Int,      X86::VFNMSUBSD4rm_Int,      TB_NO_REVERSE },
2601     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
2602     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
2603     { X86::VFNMSUBPS4Yrr,         X86::VFNMSUBPS4Yrm,         TB_ALIGN_NONE },
2604     { X86::VFNMSUBPD4Yrr,         X86::VFNMSUBPD4Yrm,         TB_ALIGN_NONE },
2605     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
2606     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
2607     { X86::VFMADDSUBPS4Yrr,       X86::VFMADDSUBPS4Yrm,       TB_ALIGN_NONE },
2608     { X86::VFMADDSUBPD4Yrr,       X86::VFMADDSUBPD4Yrm,       TB_ALIGN_NONE },
2609     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
2610     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
2611     { X86::VFMSUBADDPS4Yrr,       X86::VFMSUBADDPS4Yrm,       TB_ALIGN_NONE },
2612     { X86::VFMSUBADDPD4Yrr,       X86::VFMSUBADDPD4Yrm,       TB_ALIGN_NONE },
2613 
2614     // XOP foldable instructions
2615     { X86::VPCMOVrrr,             X86::VPCMOVrrm,             0 },
2616     { X86::VPCMOVYrrr,            X86::VPCMOVYrrm,            0 },
2617     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
2618     { X86::VPERMIL2PDYrr,         X86::VPERMIL2PDYrm,         0 },
2619     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
2620     { X86::VPERMIL2PSYrr,         X86::VPERMIL2PSYrm,         0 },
2621     { X86::VPPERMrrr,             X86::VPPERMrrm,             0 },
2622 
2623     // AVX-512 instructions with 3 source operands.
2624     { X86::VPERMI2Brr,            X86::VPERMI2Brm,            0 },
2625     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
2626     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
2627     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
2628     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
2629     { X86::VPERMI2Wrr,            X86::VPERMI2Wrm,            0 },
2630     { X86::VPERMT2Brr,            X86::VPERMT2Brm,            0 },
2631     { X86::VPERMT2Drr,            X86::VPERMT2Drm,            0 },
2632     { X86::VPERMT2PSrr,           X86::VPERMT2PSrm,           0 },
2633     { X86::VPERMT2PDrr,           X86::VPERMT2PDrm,           0 },
2634     { X86::VPERMT2Qrr,            X86::VPERMT2Qrm,            0 },
2635     { X86::VPERMT2Wrr,            X86::VPERMT2Wrm,            0 },
2636     { X86::VPMADD52HUQZr,         X86::VPMADD52HUQZm,         0 },
2637     { X86::VPMADD52LUQZr,         X86::VPMADD52LUQZm,         0 },
2638     { X86::VPTERNLOGDZrri,        X86::VPTERNLOGDZrmi,        0 },
2639     { X86::VPTERNLOGQZrri,        X86::VPTERNLOGQZrmi,        0 },
2640 
2641     // AVX-512VL 256-bit instructions with 3 source operands.
2642     { X86::VPERMI2B256rr,         X86::VPERMI2B256rm,         0 },
2643     { X86::VPERMI2D256rr,         X86::VPERMI2D256rm,         0 },
2644     { X86::VPERMI2PD256rr,        X86::VPERMI2PD256rm,        0 },
2645     { X86::VPERMI2PS256rr,        X86::VPERMI2PS256rm,        0 },
2646     { X86::VPERMI2Q256rr,         X86::VPERMI2Q256rm,         0 },
2647     { X86::VPERMI2W256rr,         X86::VPERMI2W256rm,         0 },
2648     { X86::VPERMT2B256rr,         X86::VPERMT2B256rm,         0 },
2649     { X86::VPERMT2D256rr,         X86::VPERMT2D256rm,         0 },
2650     { X86::VPERMT2PD256rr,        X86::VPERMT2PD256rm,        0 },
2651     { X86::VPERMT2PS256rr,        X86::VPERMT2PS256rm,        0 },
2652     { X86::VPERMT2Q256rr,         X86::VPERMT2Q256rm,         0 },
2653     { X86::VPERMT2W256rr,         X86::VPERMT2W256rm,         0 },
2654     { X86::VPMADD52HUQZ256r,      X86::VPMADD52HUQZ256m,      0 },
2655     { X86::VPMADD52LUQZ256r,      X86::VPMADD52LUQZ256m,      0 },
2656     { X86::VPTERNLOGDZ256rri,     X86::VPTERNLOGDZ256rmi,     0 },
2657     { X86::VPTERNLOGQZ256rri,     X86::VPTERNLOGQZ256rmi,     0 },
2658 
2659     // AVX-512VL 128-bit instructions with 3 source operands.
2660     { X86::VPERMI2B128rr,         X86::VPERMI2B128rm,         0 },
2661     { X86::VPERMI2D128rr,         X86::VPERMI2D128rm,         0 },
2662     { X86::VPERMI2PD128rr,        X86::VPERMI2PD128rm,        0 },
2663     { X86::VPERMI2PS128rr,        X86::VPERMI2PS128rm,        0 },
2664     { X86::VPERMI2Q128rr,         X86::VPERMI2Q128rm,         0 },
2665     { X86::VPERMI2W128rr,         X86::VPERMI2W128rm,         0 },
2666     { X86::VPERMT2B128rr,         X86::VPERMT2B128rm,         0 },
2667     { X86::VPERMT2D128rr,         X86::VPERMT2D128rm,         0 },
2668     { X86::VPERMT2PD128rr,        X86::VPERMT2PD128rm,        0 },
2669     { X86::VPERMT2PS128rr,        X86::VPERMT2PS128rm,        0 },
2670     { X86::VPERMT2Q128rr,         X86::VPERMT2Q128rm,         0 },
2671     { X86::VPERMT2W128rr,         X86::VPERMT2W128rm,         0 },
2672     { X86::VPMADD52HUQZ128r,      X86::VPMADD52HUQZ128m,      0 },
2673     { X86::VPMADD52LUQZ128r,      X86::VPMADD52LUQZ128m,      0 },
2674     { X86::VPTERNLOGDZ128rri,     X86::VPTERNLOGDZ128rmi,     0 },
2675     { X86::VPTERNLOGQZ128rri,     X86::VPTERNLOGQZ128rmi,     0 },
2676 
2677     // AVX-512 masked instructions
2678     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
2679     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
2680     { X86::VADDSDZrr_Intkz,       X86::VADDSDZrm_Intkz,       TB_NO_REVERSE },
2681     { X86::VADDSSZrr_Intkz,       X86::VADDSSZrm_Intkz,       TB_NO_REVERSE },
2682     { X86::VALIGNDZrrikz,         X86::VALIGNDZrmikz,         0 },
2683     { X86::VALIGNQZrrikz,         X86::VALIGNQZrmikz,         0 },
2684     { X86::VANDNPDZrrkz,          X86::VANDNPDZrmkz,          0 },
2685     { X86::VANDNPSZrrkz,          X86::VANDNPSZrmkz,          0 },
2686     { X86::VANDPDZrrkz,           X86::VANDPDZrmkz,           0 },
2687     { X86::VANDPSZrrkz,           X86::VANDPSZrmkz,           0 },
2688     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
2689     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
2690     { X86::VDIVSDZrr_Intkz,       X86::VDIVSDZrm_Intkz,       TB_NO_REVERSE },
2691     { X86::VDIVSSZrr_Intkz,       X86::VDIVSSZrm_Intkz,       TB_NO_REVERSE },
2692     { X86::VINSERTF32x4Zrrkz,     X86::VINSERTF32x4Zrmkz,     0 },
2693     { X86::VINSERTF32x8Zrrkz,     X86::VINSERTF32x8Zrmkz,     0 },
2694     { X86::VINSERTF64x2Zrrkz,     X86::VINSERTF64x2Zrmkz,     0 },
2695     { X86::VINSERTF64x4Zrrkz,     X86::VINSERTF64x4Zrmkz,     0 },
2696     { X86::VINSERTI32x4Zrrkz,     X86::VINSERTI32x4Zrmkz,     0 },
2697     { X86::VINSERTI32x8Zrrkz,     X86::VINSERTI32x8Zrmkz,     0 },
2698     { X86::VINSERTI64x2Zrrkz,     X86::VINSERTI64x2Zrmkz,     0 },
2699     { X86::VINSERTI64x4Zrrkz,     X86::VINSERTI64x4Zrmkz,     0 },
2700     { X86::VMAXCPDZrrkz,          X86::VMAXCPDZrmkz,          0 },
2701     { X86::VMAXCPSZrrkz,          X86::VMAXCPSZrmkz,          0 },
2702     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
2703     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
2704     { X86::VMAXSDZrr_Intkz,       X86::VMAXSDZrm_Intkz,       TB_NO_REVERSE },
2705     { X86::VMAXSSZrr_Intkz,       X86::VMAXSSZrm_Intkz,       TB_NO_REVERSE },
2706     { X86::VMINCPDZrrkz,          X86::VMINCPDZrmkz,          0 },
2707     { X86::VMINCPSZrrkz,          X86::VMINCPSZrmkz,          0 },
2708     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
2709     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
2710     { X86::VMINSDZrr_Intkz,       X86::VMINSDZrm_Intkz,       TB_NO_REVERSE },
2711     { X86::VMINSSZrr_Intkz,       X86::VMINSSZrm_Intkz,       TB_NO_REVERSE },
2712     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
2713     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
2714     { X86::VMULSDZrr_Intkz,       X86::VMULSDZrm_Intkz,       TB_NO_REVERSE },
2715     { X86::VMULSSZrr_Intkz,       X86::VMULSSZrm_Intkz,       TB_NO_REVERSE },
2716     { X86::VORPDZrrkz,            X86::VORPDZrmkz,            0 },
2717     { X86::VORPSZrrkz,            X86::VORPSZrmkz,            0 },
2718     { X86::VPACKSSDWZrrkz,        X86::VPACKSSDWZrmkz,        0 },
2719     { X86::VPACKSSWBZrrkz,        X86::VPACKSSWBZrmkz,        0 },
2720     { X86::VPACKUSDWZrrkz,        X86::VPACKUSDWZrmkz,        0 },
2721     { X86::VPACKUSWBZrrkz,        X86::VPACKUSWBZrmkz,        0 },
2722     { X86::VPADDBZrrkz,           X86::VPADDBZrmkz,           0 },
2723     { X86::VPADDDZrrkz,           X86::VPADDDZrmkz,           0 },
2724     { X86::VPADDQZrrkz,           X86::VPADDQZrmkz,           0 },
2725     { X86::VPADDSBZrrkz,          X86::VPADDSBZrmkz,          0 },
2726     { X86::VPADDSWZrrkz,          X86::VPADDSWZrmkz,          0 },
2727     { X86::VPADDUSBZrrkz,         X86::VPADDUSBZrmkz,         0 },
2728     { X86::VPADDUSWZrrkz,         X86::VPADDUSWZrmkz,         0 },
2729     { X86::VPADDWZrrkz,           X86::VPADDWZrmkz,           0 },
2730     { X86::VPALIGNRZrrikz,        X86::VPALIGNRZrmikz,        0 },
2731     { X86::VPANDDZrrkz,           X86::VPANDDZrmkz,           0 },
2732     { X86::VPANDNDZrrkz,          X86::VPANDNDZrmkz,          0 },
2733     { X86::VPANDNQZrrkz,          X86::VPANDNQZrmkz,          0 },
2734     { X86::VPANDQZrrkz,           X86::VPANDQZrmkz,           0 },
2735     { X86::VPAVGBZrrkz,           X86::VPAVGBZrmkz,           0 },
2736     { X86::VPAVGWZrrkz,           X86::VPAVGWZrmkz,           0 },
2737     { X86::VPERMBZrrkz,           X86::VPERMBZrmkz,           0 },
2738     { X86::VPERMDZrrkz,           X86::VPERMDZrmkz,           0 },
2739     { X86::VPERMILPDZrrkz,        X86::VPERMILPDZrmkz,        0 },
2740     { X86::VPERMILPSZrrkz,        X86::VPERMILPSZrmkz,        0 },
2741     { X86::VPERMPDZrrkz,          X86::VPERMPDZrmkz,          0 },
2742     { X86::VPERMPSZrrkz,          X86::VPERMPSZrmkz,          0 },
2743     { X86::VPERMQZrrkz,           X86::VPERMQZrmkz,           0 },
2744     { X86::VPERMWZrrkz,           X86::VPERMWZrmkz,           0 },
2745     { X86::VPMADDUBSWZrrkz,       X86::VPMADDUBSWZrmkz,       0 },
2746     { X86::VPMADDWDZrrkz,         X86::VPMADDWDZrmkz,         0 },
2747     { X86::VPMAXSBZrrkz,          X86::VPMAXSBZrmkz,          0 },
2748     { X86::VPMAXSDZrrkz,          X86::VPMAXSDZrmkz,          0 },
2749     { X86::VPMAXSQZrrkz,          X86::VPMAXSQZrmkz,          0 },
2750     { X86::VPMAXSWZrrkz,          X86::VPMAXSWZrmkz,          0 },
2751     { X86::VPMAXUBZrrkz,          X86::VPMAXUBZrmkz,          0 },
2752     { X86::VPMAXUDZrrkz,          X86::VPMAXUDZrmkz,          0 },
2753     { X86::VPMAXUQZrrkz,          X86::VPMAXUQZrmkz,          0 },
2754     { X86::VPMAXUWZrrkz,          X86::VPMAXUWZrmkz,          0 },
2755     { X86::VPMINSBZrrkz,          X86::VPMINSBZrmkz,          0 },
2756     { X86::VPMINSDZrrkz,          X86::VPMINSDZrmkz,          0 },
2757     { X86::VPMINSQZrrkz,          X86::VPMINSQZrmkz,          0 },
2758     { X86::VPMINSWZrrkz,          X86::VPMINSWZrmkz,          0 },
2759     { X86::VPMINUBZrrkz,          X86::VPMINUBZrmkz,          0 },
2760     { X86::VPMINUDZrrkz,          X86::VPMINUDZrmkz,          0 },
2761     { X86::VPMINUQZrrkz,          X86::VPMINUQZrmkz,          0 },
2762     { X86::VPMINUWZrrkz,          X86::VPMINUWZrmkz,          0 },
2763     { X86::VPMULLDZrrkz,          X86::VPMULLDZrmkz,          0 },
2764     { X86::VPMULLQZrrkz,          X86::VPMULLQZrmkz,          0 },
2765     { X86::VPMULLWZrrkz,          X86::VPMULLWZrmkz,          0 },
2766     { X86::VPMULDQZrrkz,          X86::VPMULDQZrmkz,          0 },
2767     { X86::VPMULUDQZrrkz,         X86::VPMULUDQZrmkz,         0 },
2768     { X86::VPORDZrrkz,            X86::VPORDZrmkz,            0 },
2769     { X86::VPORQZrrkz,            X86::VPORQZrmkz,            0 },
2770     { X86::VPSHUFBZrrkz,          X86::VPSHUFBZrmkz,          0 },
2771     { X86::VPSLLDZrrkz,           X86::VPSLLDZrmkz,           0 },
2772     { X86::VPSLLQZrrkz,           X86::VPSLLQZrmkz,           0 },
2773     { X86::VPSLLVDZrrkz,          X86::VPSLLVDZrmkz,          0 },
2774     { X86::VPSLLVQZrrkz,          X86::VPSLLVQZrmkz,          0 },
2775     { X86::VPSLLVWZrrkz,          X86::VPSLLVWZrmkz,          0 },
2776     { X86::VPSLLWZrrkz,           X86::VPSLLWZrmkz,           0 },
2777     { X86::VPSRADZrrkz,           X86::VPSRADZrmkz,           0 },
2778     { X86::VPSRAQZrrkz,           X86::VPSRAQZrmkz,           0 },
2779     { X86::VPSRAVDZrrkz,          X86::VPSRAVDZrmkz,          0 },
2780     { X86::VPSRAVQZrrkz,          X86::VPSRAVQZrmkz,          0 },
2781     { X86::VPSRAVWZrrkz,          X86::VPSRAVWZrmkz,          0 },
2782     { X86::VPSRAWZrrkz,           X86::VPSRAWZrmkz,           0 },
2783     { X86::VPSRLDZrrkz,           X86::VPSRLDZrmkz,           0 },
2784     { X86::VPSRLQZrrkz,           X86::VPSRLQZrmkz,           0 },
2785     { X86::VPSRLVDZrrkz,          X86::VPSRLVDZrmkz,          0 },
2786     { X86::VPSRLVQZrrkz,          X86::VPSRLVQZrmkz,          0 },
2787     { X86::VPSRLVWZrrkz,          X86::VPSRLVWZrmkz,          0 },
2788     { X86::VPSRLWZrrkz,           X86::VPSRLWZrmkz,           0 },
2789     { X86::VPSUBBZrrkz,           X86::VPSUBBZrmkz,           0 },
2790     { X86::VPSUBDZrrkz,           X86::VPSUBDZrmkz,           0 },
2791     { X86::VPSUBQZrrkz,           X86::VPSUBQZrmkz,           0 },
2792     { X86::VPSUBSBZrrkz,          X86::VPSUBSBZrmkz,          0 },
2793     { X86::VPSUBSWZrrkz,          X86::VPSUBSWZrmkz,          0 },
2794     { X86::VPSUBUSBZrrkz,         X86::VPSUBUSBZrmkz,         0 },
2795     { X86::VPSUBUSWZrrkz,         X86::VPSUBUSWZrmkz,         0 },
2796     { X86::VPSUBWZrrkz,           X86::VPSUBWZrmkz,           0 },
2797     { X86::VPUNPCKHBWZrrkz,       X86::VPUNPCKHBWZrmkz,       0 },
2798     { X86::VPUNPCKHDQZrrkz,       X86::VPUNPCKHDQZrmkz,       0 },
2799     { X86::VPUNPCKHQDQZrrkz,      X86::VPUNPCKHQDQZrmkz,      0 },
2800     { X86::VPUNPCKHWDZrrkz,       X86::VPUNPCKHWDZrmkz,       0 },
2801     { X86::VPUNPCKLBWZrrkz,       X86::VPUNPCKLBWZrmkz,       0 },
2802     { X86::VPUNPCKLDQZrrkz,       X86::VPUNPCKLDQZrmkz,       0 },
2803     { X86::VPUNPCKLQDQZrrkz,      X86::VPUNPCKLQDQZrmkz,      0 },
2804     { X86::VPUNPCKLWDZrrkz,       X86::VPUNPCKLWDZrmkz,       0 },
2805     { X86::VPXORDZrrkz,           X86::VPXORDZrmkz,           0 },
2806     { X86::VPXORQZrrkz,           X86::VPXORQZrmkz,           0 },
2807     { X86::VSHUFF32X4Zrrikz,      X86::VSHUFF32X4Zrmikz,      0 },
2808     { X86::VSHUFF64X2Zrrikz,      X86::VSHUFF64X2Zrmikz,      0 },
2809     { X86::VSHUFI32X4Zrrikz,      X86::VSHUFI32X4Zrmikz,      0 },
2810     { X86::VSHUFI64X2Zrrikz,      X86::VSHUFI64X2Zrmikz,      0 },
2811     { X86::VSHUFPDZrrikz,         X86::VSHUFPDZrmikz,         0 },
2812     { X86::VSHUFPSZrrikz,         X86::VSHUFPSZrmikz,         0 },
2813     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
2814     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
2815     { X86::VSUBSDZrr_Intkz,       X86::VSUBSDZrm_Intkz,       TB_NO_REVERSE },
2816     { X86::VSUBSSZrr_Intkz,       X86::VSUBSSZrm_Intkz,       TB_NO_REVERSE },
2817     { X86::VUNPCKHPDZrrkz,        X86::VUNPCKHPDZrmkz,        0 },
2818     { X86::VUNPCKHPSZrrkz,        X86::VUNPCKHPSZrmkz,        0 },
2819     { X86::VUNPCKLPDZrrkz,        X86::VUNPCKLPDZrmkz,        0 },
2820     { X86::VUNPCKLPSZrrkz,        X86::VUNPCKLPSZrmkz,        0 },
2821     { X86::VXORPDZrrkz,           X86::VXORPDZrmkz,           0 },
2822     { X86::VXORPSZrrkz,           X86::VXORPSZrmkz,           0 },
2823 
2824     // AVX-512{F,VL} masked arithmetic instructions 256-bit
2825     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
2826     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
2827     { X86::VALIGNDZ256rrikz,      X86::VALIGNDZ256rmikz,      0 },
2828     { X86::VALIGNQZ256rrikz,      X86::VALIGNQZ256rmikz,      0 },
2829     { X86::VANDNPDZ256rrkz,       X86::VANDNPDZ256rmkz,       0 },
2830     { X86::VANDNPSZ256rrkz,       X86::VANDNPSZ256rmkz,       0 },
2831     { X86::VANDPDZ256rrkz,        X86::VANDPDZ256rmkz,        0 },
2832     { X86::VANDPSZ256rrkz,        X86::VANDPSZ256rmkz,        0 },
2833     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
2834     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
2835     { X86::VINSERTF32x4Z256rrkz,  X86::VINSERTF32x4Z256rmkz,  0 },
2836     { X86::VINSERTF64x2Z256rrkz,  X86::VINSERTF64x2Z256rmkz,  0 },
2837     { X86::VINSERTI32x4Z256rrkz,  X86::VINSERTI32x4Z256rmkz,  0 },
2838     { X86::VINSERTI64x2Z256rrkz,  X86::VINSERTI64x2Z256rmkz,  0 },
2839     { X86::VMAXCPDZ256rrkz,       X86::VMAXCPDZ256rmkz,       0 },
2840     { X86::VMAXCPSZ256rrkz,       X86::VMAXCPSZ256rmkz,       0 },
2841     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
2842     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
2843     { X86::VMINCPDZ256rrkz,       X86::VMINCPDZ256rmkz,       0 },
2844     { X86::VMINCPSZ256rrkz,       X86::VMINCPSZ256rmkz,       0 },
2845     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
2846     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
2847     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
2848     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
2849     { X86::VORPDZ256rrkz,         X86::VORPDZ256rmkz,         0 },
2850     { X86::VORPSZ256rrkz,         X86::VORPSZ256rmkz,         0 },
2851     { X86::VPACKSSDWZ256rrkz,     X86::VPACKSSDWZ256rmkz,     0 },
2852     { X86::VPACKSSWBZ256rrkz,     X86::VPACKSSWBZ256rmkz,     0 },
2853     { X86::VPACKUSDWZ256rrkz,     X86::VPACKUSDWZ256rmkz,     0 },
2854     { X86::VPACKUSWBZ256rrkz,     X86::VPACKUSWBZ256rmkz,     0 },
2855     { X86::VPADDBZ256rrkz,        X86::VPADDBZ256rmkz,        0 },
2856     { X86::VPADDDZ256rrkz,        X86::VPADDDZ256rmkz,        0 },
2857     { X86::VPADDQZ256rrkz,        X86::VPADDQZ256rmkz,        0 },
2858     { X86::VPADDSBZ256rrkz,       X86::VPADDSBZ256rmkz,       0 },
2859     { X86::VPADDSWZ256rrkz,       X86::VPADDSWZ256rmkz,       0 },
2860     { X86::VPADDUSBZ256rrkz,      X86::VPADDUSBZ256rmkz,      0 },
2861     { X86::VPADDUSWZ256rrkz,      X86::VPADDUSWZ256rmkz,      0 },
2862     { X86::VPADDWZ256rrkz,        X86::VPADDWZ256rmkz,        0 },
2863     { X86::VPALIGNRZ256rrikz,     X86::VPALIGNRZ256rmikz,     0 },
2864     { X86::VPANDDZ256rrkz,        X86::VPANDDZ256rmkz,        0 },
2865     { X86::VPANDNDZ256rrkz,       X86::VPANDNDZ256rmkz,       0 },
2866     { X86::VPANDNQZ256rrkz,       X86::VPANDNQZ256rmkz,       0 },
2867     { X86::VPANDQZ256rrkz,        X86::VPANDQZ256rmkz,        0 },
2868     { X86::VPAVGBZ256rrkz,        X86::VPAVGBZ256rmkz,        0 },
2869     { X86::VPAVGWZ256rrkz,        X86::VPAVGWZ256rmkz,        0 },
2870     { X86::VPERMBZ256rrkz,        X86::VPERMBZ256rmkz,        0 },
2871     { X86::VPERMDZ256rrkz,        X86::VPERMDZ256rmkz,        0 },
2872     { X86::VPERMILPDZ256rrkz,     X86::VPERMILPDZ256rmkz,     0 },
2873     { X86::VPERMILPSZ256rrkz,     X86::VPERMILPSZ256rmkz,     0 },
2874     { X86::VPERMPDZ256rrkz,       X86::VPERMPDZ256rmkz,       0 },
2875     { X86::VPERMPSZ256rrkz,       X86::VPERMPSZ256rmkz,       0 },
2876     { X86::VPERMQZ256rrkz,        X86::VPERMQZ256rmkz,        0 },
2877     { X86::VPERMWZ256rrkz,        X86::VPERMWZ256rmkz,        0 },
2878     { X86::VPMADDUBSWZ256rrkz,    X86::VPMADDUBSWZ256rmkz,    0 },
2879     { X86::VPMADDWDZ256rrkz,      X86::VPMADDWDZ256rmkz,      0 },
2880     { X86::VPMAXSBZ256rrkz,       X86::VPMAXSBZ256rmkz,       0 },
2881     { X86::VPMAXSDZ256rrkz,       X86::VPMAXSDZ256rmkz,       0 },
2882     { X86::VPMAXSQZ256rrkz,       X86::VPMAXSQZ256rmkz,       0 },
2883     { X86::VPMAXSWZ256rrkz,       X86::VPMAXSWZ256rmkz,       0 },
2884     { X86::VPMAXUBZ256rrkz,       X86::VPMAXUBZ256rmkz,       0 },
2885     { X86::VPMAXUDZ256rrkz,       X86::VPMAXUDZ256rmkz,       0 },
2886     { X86::VPMAXUQZ256rrkz,       X86::VPMAXUQZ256rmkz,       0 },
2887     { X86::VPMAXUWZ256rrkz,       X86::VPMAXUWZ256rmkz,       0 },
2888     { X86::VPMINSBZ256rrkz,       X86::VPMINSBZ256rmkz,       0 },
2889     { X86::VPMINSDZ256rrkz,       X86::VPMINSDZ256rmkz,       0 },
2890     { X86::VPMINSQZ256rrkz,       X86::VPMINSQZ256rmkz,       0 },
2891     { X86::VPMINSWZ256rrkz,       X86::VPMINSWZ256rmkz,       0 },
2892     { X86::VPMINUBZ256rrkz,       X86::VPMINUBZ256rmkz,       0 },
2893     { X86::VPMINUDZ256rrkz,       X86::VPMINUDZ256rmkz,       0 },
2894     { X86::VPMINUQZ256rrkz,       X86::VPMINUQZ256rmkz,       0 },
2895     { X86::VPMINUWZ256rrkz,       X86::VPMINUWZ256rmkz,       0 },
2896     { X86::VPMULDQZ256rrkz,       X86::VPMULDQZ256rmkz,       0 },
2897     { X86::VPMULLDZ256rrkz,       X86::VPMULLDZ256rmkz,       0 },
2898     { X86::VPMULLQZ256rrkz,       X86::VPMULLQZ256rmkz,       0 },
2899     { X86::VPMULLWZ256rrkz,       X86::VPMULLWZ256rmkz,       0 },
2900     { X86::VPMULUDQZ256rrkz,      X86::VPMULUDQZ256rmkz,      0 },
2901     { X86::VPORDZ256rrkz,         X86::VPORDZ256rmkz,         0 },
2902     { X86::VPORQZ256rrkz,         X86::VPORQZ256rmkz,         0 },
2903     { X86::VPSHUFBZ256rrkz,       X86::VPSHUFBZ256rmkz,       0 },
2904     { X86::VPSLLDZ256rrkz,        X86::VPSLLDZ256rmkz,        0 },
2905     { X86::VPSLLQZ256rrkz,        X86::VPSLLQZ256rmkz,        0 },
2906     { X86::VPSLLVDZ256rrkz,       X86::VPSLLVDZ256rmkz,       0 },
2907     { X86::VPSLLVQZ256rrkz,       X86::VPSLLVQZ256rmkz,       0 },
2908     { X86::VPSLLVWZ256rrkz,       X86::VPSLLVWZ256rmkz,       0 },
2909     { X86::VPSLLWZ256rrkz,        X86::VPSLLWZ256rmkz,        0 },
2910     { X86::VPSRADZ256rrkz,        X86::VPSRADZ256rmkz,        0 },
2911     { X86::VPSRAQZ256rrkz,        X86::VPSRAQZ256rmkz,        0 },
2912     { X86::VPSRAVDZ256rrkz,       X86::VPSRAVDZ256rmkz,       0 },
2913     { X86::VPSRAVQZ256rrkz,       X86::VPSRAVQZ256rmkz,       0 },
2914     { X86::VPSRAVWZ256rrkz,       X86::VPSRAVWZ256rmkz,       0 },
2915     { X86::VPSRAWZ256rrkz,        X86::VPSRAWZ256rmkz,        0 },
2916     { X86::VPSRLDZ256rrkz,        X86::VPSRLDZ256rmkz,        0 },
2917     { X86::VPSRLQZ256rrkz,        X86::VPSRLQZ256rmkz,        0 },
2918     { X86::VPSRLVDZ256rrkz,       X86::VPSRLVDZ256rmkz,       0 },
2919     { X86::VPSRLVQZ256rrkz,       X86::VPSRLVQZ256rmkz,       0 },
2920     { X86::VPSRLVWZ256rrkz,       X86::VPSRLVWZ256rmkz,       0 },
2921     { X86::VPSRLWZ256rrkz,        X86::VPSRLWZ256rmkz,        0 },
2922     { X86::VPSUBBZ256rrkz,        X86::VPSUBBZ256rmkz,        0 },
2923     { X86::VPSUBDZ256rrkz,        X86::VPSUBDZ256rmkz,        0 },
2924     { X86::VPSUBQZ256rrkz,        X86::VPSUBQZ256rmkz,        0 },
2925     { X86::VPSUBSBZ256rrkz,       X86::VPSUBSBZ256rmkz,       0 },
2926     { X86::VPSUBSWZ256rrkz,       X86::VPSUBSWZ256rmkz,       0 },
2927     { X86::VPSUBUSBZ256rrkz,      X86::VPSUBUSBZ256rmkz,      0 },
2928     { X86::VPSUBUSWZ256rrkz,      X86::VPSUBUSWZ256rmkz,      0 },
2929     { X86::VPSUBWZ256rrkz,        X86::VPSUBWZ256rmkz,        0 },
2930     { X86::VPUNPCKHBWZ256rrkz,    X86::VPUNPCKHBWZ256rmkz,    0 },
2931     { X86::VPUNPCKHDQZ256rrkz,    X86::VPUNPCKHDQZ256rmkz,    0 },
2932     { X86::VPUNPCKHQDQZ256rrkz,   X86::VPUNPCKHQDQZ256rmkz,   0 },
2933     { X86::VPUNPCKHWDZ256rrkz,    X86::VPUNPCKHWDZ256rmkz,    0 },
2934     { X86::VPUNPCKLBWZ256rrkz,    X86::VPUNPCKLBWZ256rmkz,    0 },
2935     { X86::VPUNPCKLDQZ256rrkz,    X86::VPUNPCKLDQZ256rmkz,    0 },
2936     { X86::VPUNPCKLQDQZ256rrkz,   X86::VPUNPCKLQDQZ256rmkz,   0 },
2937     { X86::VPUNPCKLWDZ256rrkz,    X86::VPUNPCKLWDZ256rmkz,    0 },
2938     { X86::VPXORDZ256rrkz,        X86::VPXORDZ256rmkz,        0 },
2939     { X86::VPXORQZ256rrkz,        X86::VPXORQZ256rmkz,        0 },
2940     { X86::VSHUFF32X4Z256rrikz,   X86::VSHUFF32X4Z256rmikz,   0 },
2941     { X86::VSHUFF64X2Z256rrikz,   X86::VSHUFF64X2Z256rmikz,   0 },
2942     { X86::VSHUFI32X4Z256rrikz,   X86::VSHUFI32X4Z256rmikz,   0 },
2943     { X86::VSHUFI64X2Z256rrikz,   X86::VSHUFI64X2Z256rmikz,   0 },
2944     { X86::VSHUFPDZ256rrikz,      X86::VSHUFPDZ256rmikz,      0 },
2945     { X86::VSHUFPSZ256rrikz,      X86::VSHUFPSZ256rmikz,      0 },
2946     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
2947     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
2948     { X86::VUNPCKHPDZ256rrkz,     X86::VUNPCKHPDZ256rmkz,     0 },
2949     { X86::VUNPCKHPSZ256rrkz,     X86::VUNPCKHPSZ256rmkz,     0 },
2950     { X86::VUNPCKLPDZ256rrkz,     X86::VUNPCKLPDZ256rmkz,     0 },
2951     { X86::VUNPCKLPSZ256rrkz,     X86::VUNPCKLPSZ256rmkz,     0 },
2952     { X86::VXORPDZ256rrkz,        X86::VXORPDZ256rmkz,        0 },
2953     { X86::VXORPSZ256rrkz,        X86::VXORPSZ256rmkz,        0 },
2954 
2955     // AVX-512{F,VL} masked arithmetic instructions 128-bit
2956     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
2957     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
2958     { X86::VALIGNDZ128rrikz,      X86::VALIGNDZ128rmikz,      0 },
2959     { X86::VALIGNQZ128rrikz,      X86::VALIGNQZ128rmikz,      0 },
2960     { X86::VANDNPDZ128rrkz,       X86::VANDNPDZ128rmkz,       0 },
2961     { X86::VANDNPSZ128rrkz,       X86::VANDNPSZ128rmkz,       0 },
2962     { X86::VANDPDZ128rrkz,        X86::VANDPDZ128rmkz,        0 },
2963     { X86::VANDPSZ128rrkz,        X86::VANDPSZ128rmkz,        0 },
2964     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
2965     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
2966     { X86::VMAXCPDZ128rrkz,       X86::VMAXCPDZ128rmkz,       0 },
2967     { X86::VMAXCPSZ128rrkz,       X86::VMAXCPSZ128rmkz,       0 },
2968     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 },
2969     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
2970     { X86::VMINCPDZ128rrkz,       X86::VMINCPDZ128rmkz,       0 },
2971     { X86::VMINCPSZ128rrkz,       X86::VMINCPSZ128rmkz,       0 },
2972     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
2973     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
2974     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
2975     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
2976     { X86::VORPDZ128rrkz,         X86::VORPDZ128rmkz,         0 },
2977     { X86::VORPSZ128rrkz,         X86::VORPSZ128rmkz,         0 },
2978     { X86::VPACKSSDWZ128rrkz,     X86::VPACKSSDWZ128rmkz,     0 },
2979     { X86::VPACKSSWBZ128rrkz,     X86::VPACKSSWBZ128rmkz,     0 },
2980     { X86::VPACKUSDWZ128rrkz,     X86::VPACKUSDWZ128rmkz,     0 },
2981     { X86::VPACKUSWBZ128rrkz,     X86::VPACKUSWBZ128rmkz,     0 },
2982     { X86::VPADDBZ128rrkz,        X86::VPADDBZ128rmkz,        0 },
2983     { X86::VPADDDZ128rrkz,        X86::VPADDDZ128rmkz,        0 },
2984     { X86::VPADDQZ128rrkz,        X86::VPADDQZ128rmkz,        0 },
2985     { X86::VPADDSBZ128rrkz,       X86::VPADDSBZ128rmkz,       0 },
2986     { X86::VPADDSWZ128rrkz,       X86::VPADDSWZ128rmkz,       0 },
2987     { X86::VPADDUSBZ128rrkz,      X86::VPADDUSBZ128rmkz,      0 },
2988     { X86::VPADDUSWZ128rrkz,      X86::VPADDUSWZ128rmkz,      0 },
2989     { X86::VPADDWZ128rrkz,        X86::VPADDWZ128rmkz,        0 },
2990     { X86::VPALIGNRZ128rrikz,     X86::VPALIGNRZ128rmikz,     0 },
2991     { X86::VPANDDZ128rrkz,        X86::VPANDDZ128rmkz,        0 },
2992     { X86::VPANDNDZ128rrkz,       X86::VPANDNDZ128rmkz,       0 },
2993     { X86::VPANDNQZ128rrkz,       X86::VPANDNQZ128rmkz,       0 },
2994     { X86::VPANDQZ128rrkz,        X86::VPANDQZ128rmkz,        0 },
2995     { X86::VPAVGBZ128rrkz,        X86::VPAVGBZ128rmkz,        0 },
2996     { X86::VPAVGWZ128rrkz,        X86::VPAVGWZ128rmkz,        0 },
2997     { X86::VPERMBZ128rrkz,        X86::VPERMBZ128rmkz,        0 },
2998     { X86::VPERMILPDZ128rrkz,     X86::VPERMILPDZ128rmkz,     0 },
2999     { X86::VPERMILPSZ128rrkz,     X86::VPERMILPSZ128rmkz,     0 },
3000     { X86::VPERMWZ128rrkz,        X86::VPERMWZ128rmkz,        0 },
3001     { X86::VPMADDUBSWZ128rrkz,    X86::VPMADDUBSWZ128rmkz,    0 },
3002     { X86::VPMADDWDZ128rrkz,      X86::VPMADDWDZ128rmkz,      0 },
3003     { X86::VPMAXSBZ128rrkz,       X86::VPMAXSBZ128rmkz,       0 },
3004     { X86::VPMAXSDZ128rrkz,       X86::VPMAXSDZ128rmkz,       0 },
3005     { X86::VPMAXSQZ128rrkz,       X86::VPMAXSQZ128rmkz,       0 },
3006     { X86::VPMAXSWZ128rrkz,       X86::VPMAXSWZ128rmkz,       0 },
3007     { X86::VPMAXUBZ128rrkz,       X86::VPMAXUBZ128rmkz,       0 },
3008     { X86::VPMAXUDZ128rrkz,       X86::VPMAXUDZ128rmkz,       0 },
3009     { X86::VPMAXUQZ128rrkz,       X86::VPMAXUQZ128rmkz,       0 },
3010     { X86::VPMAXUWZ128rrkz,       X86::VPMAXUWZ128rmkz,       0 },
3011     { X86::VPMINSBZ128rrkz,       X86::VPMINSBZ128rmkz,       0 },
3012     { X86::VPMINSDZ128rrkz,       X86::VPMINSDZ128rmkz,       0 },
3013     { X86::VPMINSQZ128rrkz,       X86::VPMINSQZ128rmkz,       0 },
3014     { X86::VPMINSWZ128rrkz,       X86::VPMINSWZ128rmkz,       0 },
3015     { X86::VPMINUBZ128rrkz,       X86::VPMINUBZ128rmkz,       0 },
3016     { X86::VPMINUDZ128rrkz,       X86::VPMINUDZ128rmkz,       0 },
3017     { X86::VPMINUQZ128rrkz,       X86::VPMINUQZ128rmkz,       0 },
3018     { X86::VPMINUWZ128rrkz,       X86::VPMINUWZ128rmkz,       0 },
3019     { X86::VPMULDQZ128rrkz,       X86::VPMULDQZ128rmkz,       0 },
3020     { X86::VPMULLDZ128rrkz,       X86::VPMULLDZ128rmkz,       0 },
3021     { X86::VPMULLQZ128rrkz,       X86::VPMULLQZ128rmkz,       0 },
3022     { X86::VPMULLWZ128rrkz,       X86::VPMULLWZ128rmkz,       0 },
3023     { X86::VPMULUDQZ128rrkz,      X86::VPMULUDQZ128rmkz,      0 },
3024     { X86::VPORDZ128rrkz,         X86::VPORDZ128rmkz,         0 },
3025     { X86::VPORQZ128rrkz,         X86::VPORQZ128rmkz,         0 },
3026     { X86::VPSHUFBZ128rrkz,       X86::VPSHUFBZ128rmkz,       0 },
3027     { X86::VPSLLDZ128rrkz,        X86::VPSLLDZ128rmkz,        0 },
3028     { X86::VPSLLQZ128rrkz,        X86::VPSLLQZ128rmkz,        0 },
3029     { X86::VPSLLVDZ128rrkz,       X86::VPSLLVDZ128rmkz,       0 },
3030     { X86::VPSLLVQZ128rrkz,       X86::VPSLLVQZ128rmkz,       0 },
3031     { X86::VPSLLVWZ128rrkz,       X86::VPSLLVWZ128rmkz,       0 },
3032     { X86::VPSLLWZ128rrkz,        X86::VPSLLWZ128rmkz,        0 },
3033     { X86::VPSRADZ128rrkz,        X86::VPSRADZ128rmkz,        0 },
3034     { X86::VPSRAQZ128rrkz,        X86::VPSRAQZ128rmkz,        0 },
3035     { X86::VPSRAVDZ128rrkz,       X86::VPSRAVDZ128rmkz,       0 },
3036     { X86::VPSRAVQZ128rrkz,       X86::VPSRAVQZ128rmkz,       0 },
3037     { X86::VPSRAVWZ128rrkz,       X86::VPSRAVWZ128rmkz,       0 },
3038     { X86::VPSRAWZ128rrkz,        X86::VPSRAWZ128rmkz,        0 },
3039     { X86::VPSRLDZ128rrkz,        X86::VPSRLDZ128rmkz,        0 },
3040     { X86::VPSRLQZ128rrkz,        X86::VPSRLQZ128rmkz,        0 },
3041     { X86::VPSRLVDZ128rrkz,       X86::VPSRLVDZ128rmkz,       0 },
3042     { X86::VPSRLVQZ128rrkz,       X86::VPSRLVQZ128rmkz,       0 },
3043     { X86::VPSRLVWZ128rrkz,       X86::VPSRLVWZ128rmkz,       0 },
3044     { X86::VPSRLWZ128rrkz,        X86::VPSRLWZ128rmkz,        0 },
3045     { X86::VPSUBBZ128rrkz,        X86::VPSUBBZ128rmkz,        0 },
3046     { X86::VPSUBDZ128rrkz,        X86::VPSUBDZ128rmkz,        0 },
3047     { X86::VPSUBQZ128rrkz,        X86::VPSUBQZ128rmkz,        0 },
3048     { X86::VPSUBSBZ128rrkz,       X86::VPSUBSBZ128rmkz,       0 },
3049     { X86::VPSUBSWZ128rrkz,       X86::VPSUBSWZ128rmkz,       0 },
3050     { X86::VPSUBUSBZ128rrkz,      X86::VPSUBUSBZ128rmkz,      0 },
3051     { X86::VPSUBUSWZ128rrkz,      X86::VPSUBUSWZ128rmkz,      0 },
3052     { X86::VPSUBWZ128rrkz,        X86::VPSUBWZ128rmkz,        0 },
3053     { X86::VPUNPCKHBWZ128rrkz,    X86::VPUNPCKHBWZ128rmkz,    0 },
3054     { X86::VPUNPCKHDQZ128rrkz,    X86::VPUNPCKHDQZ128rmkz,    0 },
3055     { X86::VPUNPCKHQDQZ128rrkz,   X86::VPUNPCKHQDQZ128rmkz,   0 },
3056     { X86::VPUNPCKHWDZ128rrkz,    X86::VPUNPCKHWDZ128rmkz,    0 },
3057     { X86::VPUNPCKLBWZ128rrkz,    X86::VPUNPCKLBWZ128rmkz,    0 },
3058     { X86::VPUNPCKLDQZ128rrkz,    X86::VPUNPCKLDQZ128rmkz,    0 },
3059     { X86::VPUNPCKLQDQZ128rrkz,   X86::VPUNPCKLQDQZ128rmkz,   0 },
3060     { X86::VPUNPCKLWDZ128rrkz,    X86::VPUNPCKLWDZ128rmkz,    0 },
3061     { X86::VPXORDZ128rrkz,        X86::VPXORDZ128rmkz,        0 },
3062     { X86::VPXORQZ128rrkz,        X86::VPXORQZ128rmkz,        0 },
3063     { X86::VSHUFPDZ128rrikz,      X86::VSHUFPDZ128rmikz,      0 },
3064     { X86::VSHUFPSZ128rrikz,      X86::VSHUFPSZ128rmikz,      0 },
3065     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
3066     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
3067     { X86::VUNPCKHPDZ128rrkz,     X86::VUNPCKHPDZ128rmkz,     0 },
3068     { X86::VUNPCKHPSZ128rrkz,     X86::VUNPCKHPSZ128rmkz,     0 },
3069     { X86::VUNPCKLPDZ128rrkz,     X86::VUNPCKLPDZ128rmkz,     0 },
3070     { X86::VUNPCKLPSZ128rrkz,     X86::VUNPCKLPSZ128rmkz,     0 },
3071     { X86::VXORPDZ128rrkz,        X86::VXORPDZ128rmkz,        0 },
3072     { X86::VXORPSZ128rrkz,        X86::VXORPSZ128rmkz,        0 },
3073 
3074     // AVX-512 masked foldable instructions
3075     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
3076     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
3077     { X86::VPABSBZrrk,            X86::VPABSBZrmk,            0 },
3078     { X86::VPABSDZrrk,            X86::VPABSDZrmk,            0 },
3079     { X86::VPABSQZrrk,            X86::VPABSQZrmk,            0 },
3080     { X86::VPABSWZrrk,            X86::VPABSWZrmk,            0 },
3081     { X86::VPCONFLICTDZrrk,       X86::VPCONFLICTDZrmk,       0 },
3082     { X86::VPCONFLICTQZrrk,       X86::VPCONFLICTQZrmk,       0 },
3083     { X86::VPERMILPDZrik,         X86::VPERMILPDZmik,         0 },
3084     { X86::VPERMILPSZrik,         X86::VPERMILPSZmik,         0 },
3085     { X86::VPERMPDZrik,           X86::VPERMPDZmik,           0 },
3086     { X86::VPERMQZrik,            X86::VPERMQZmik,            0 },
3087     { X86::VPLZCNTDZrrk,          X86::VPLZCNTDZrmk,          0 },
3088     { X86::VPLZCNTQZrrk,          X86::VPLZCNTQZrmk,          0 },
3089     { X86::VPMOVSXBDZrrk,         X86::VPMOVSXBDZrmk,         0 },
3090     { X86::VPMOVSXBQZrrk,         X86::VPMOVSXBQZrmk,         TB_NO_REVERSE },
3091     { X86::VPMOVSXBWZrrk,         X86::VPMOVSXBWZrmk,         0 },
3092     { X86::VPMOVSXDQZrrk,         X86::VPMOVSXDQZrmk,         0 },
3093     { X86::VPMOVSXWDZrrk,         X86::VPMOVSXWDZrmk,         0 },
3094     { X86::VPMOVSXWQZrrk,         X86::VPMOVSXWQZrmk,         0 },
3095     { X86::VPMOVZXBDZrrk,         X86::VPMOVZXBDZrmk,         0 },
3096     { X86::VPMOVZXBQZrrk,         X86::VPMOVZXBQZrmk,         TB_NO_REVERSE },
3097     { X86::VPMOVZXBWZrrk,         X86::VPMOVZXBWZrmk,         0 },
3098     { X86::VPMOVZXDQZrrk,         X86::VPMOVZXDQZrmk,         0 },
3099     { X86::VPMOVZXWDZrrk,         X86::VPMOVZXWDZrmk,         0 },
3100     { X86::VPMOVZXWQZrrk,         X86::VPMOVZXWQZrmk,         0 },
3101     { X86::VPOPCNTBZrrk,          X86::VPOPCNTBZrmk,          0 },
3102     { X86::VPOPCNTDZrrk,          X86::VPOPCNTDZrmk,          0 },
3103     { X86::VPOPCNTQZrrk,          X86::VPOPCNTQZrmk,          0 },
3104     { X86::VPOPCNTWZrrk,          X86::VPOPCNTWZrmk,          0 },
3105     { X86::VPSHUFDZrik,           X86::VPSHUFDZmik,           0 },
3106     { X86::VPSHUFHWZrik,          X86::VPSHUFHWZmik,          0 },
3107     { X86::VPSHUFLWZrik,          X86::VPSHUFLWZmik,          0 },
3108     { X86::VPSLLDZrik,            X86::VPSLLDZmik,            0 },
3109     { X86::VPSLLQZrik,            X86::VPSLLQZmik,            0 },
3110     { X86::VPSLLWZrik,            X86::VPSLLWZmik,            0 },
3111     { X86::VPSRADZrik,            X86::VPSRADZmik,            0 },
3112     { X86::VPSRAQZrik,            X86::VPSRAQZmik,            0 },
3113     { X86::VPSRAWZrik,            X86::VPSRAWZmik,            0 },
3114     { X86::VPSRLDZrik,            X86::VPSRLDZmik,            0 },
3115     { X86::VPSRLQZrik,            X86::VPSRLQZmik,            0 },
3116     { X86::VPSRLWZrik,            X86::VPSRLWZmik,            0 },
3117 
3118     // AVX-512VL 256-bit masked foldable instructions
3119     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
3120     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
3121     { X86::VPABSBZ256rrk,         X86::VPABSBZ256rmk,         0 },
3122     { X86::VPABSDZ256rrk,         X86::VPABSDZ256rmk,         0 },
3123     { X86::VPABSQZ256rrk,         X86::VPABSQZ256rmk,         0 },
3124     { X86::VPABSWZ256rrk,         X86::VPABSWZ256rmk,         0 },
3125     { X86::VPCONFLICTDZ256rrk,    X86::VPCONFLICTDZ256rmk,    0 },
3126     { X86::VPCONFLICTQZ256rrk,    X86::VPCONFLICTQZ256rmk,    0 },
3127     { X86::VPERMILPDZ256rik,      X86::VPERMILPDZ256mik,      0 },
3128     { X86::VPERMILPSZ256rik,      X86::VPERMILPSZ256mik,      0 },
3129     { X86::VPERMPDZ256rik,        X86::VPERMPDZ256mik,        0 },
3130     { X86::VPERMQZ256rik,         X86::VPERMQZ256mik,         0 },
3131     { X86::VPLZCNTDZ256rrk,       X86::VPLZCNTDZ256rmk,       0 },
3132     { X86::VPLZCNTQZ256rrk,       X86::VPLZCNTQZ256rmk,       0 },
3133     { X86::VPMOVSXBDZ256rrk,      X86::VPMOVSXBDZ256rmk,      TB_NO_REVERSE },
3134     { X86::VPMOVSXBQZ256rrk,      X86::VPMOVSXBQZ256rmk,      TB_NO_REVERSE },
3135     { X86::VPMOVSXBWZ256rrk,      X86::VPMOVSXBWZ256rmk,      0 },
3136     { X86::VPMOVSXDQZ256rrk,      X86::VPMOVSXDQZ256rmk,      0 },
3137     { X86::VPMOVSXWDZ256rrk,      X86::VPMOVSXWDZ256rmk,      0 },
3138     { X86::VPMOVSXWQZ256rrk,      X86::VPMOVSXWQZ256rmk,      TB_NO_REVERSE },
3139     { X86::VPMOVZXBDZ256rrk,      X86::VPMOVZXBDZ256rmk,      TB_NO_REVERSE },
3140     { X86::VPMOVZXBQZ256rrk,      X86::VPMOVZXBQZ256rmk,      TB_NO_REVERSE },
3141     { X86::VPMOVZXBWZ256rrk,      X86::VPMOVZXBWZ256rmk,      0 },
3142     { X86::VPMOVZXDQZ256rrk,      X86::VPMOVZXDQZ256rmk,      0 },
3143     { X86::VPMOVZXWDZ256rrk,      X86::VPMOVZXWDZ256rmk,      0 },
3144     { X86::VPMOVZXWQZ256rrk,      X86::VPMOVZXWQZ256rmk,      TB_NO_REVERSE },
3145     { X86::VPOPCNTBZ256rrk,       X86::VPOPCNTBZ256rmk,       0 },
3146     { X86::VPOPCNTDZ256rrk,       X86::VPOPCNTDZ256rmk,       0 },
3147     { X86::VPOPCNTQZ256rrk,       X86::VPOPCNTQZ256rmk,       0 },
3148     { X86::VPOPCNTWZ256rrk,       X86::VPOPCNTWZ256rmk,       0 },
3149     { X86::VPSHUFDZ256rik,        X86::VPSHUFDZ256mik,        0 },
3150     { X86::VPSHUFHWZ256rik,       X86::VPSHUFHWZ256mik,       0 },
3151     { X86::VPSHUFLWZ256rik,       X86::VPSHUFLWZ256mik,       0 },
3152     { X86::VPSLLDZ256rik,         X86::VPSLLDZ256mik,         0 },
3153     { X86::VPSLLQZ256rik,         X86::VPSLLQZ256mik,         0 },
3154     { X86::VPSLLWZ256rik,         X86::VPSLLWZ256mik,         0 },
3155     { X86::VPSRADZ256rik,         X86::VPSRADZ256mik,         0 },
3156     { X86::VPSRAQZ256rik,         X86::VPSRAQZ256mik,         0 },
3157     { X86::VPSRAWZ256rik,         X86::VPSRAWZ256mik,         0 },
3158     { X86::VPSRLDZ256rik,         X86::VPSRLDZ256mik,         0 },
3159     { X86::VPSRLQZ256rik,         X86::VPSRLQZ256mik,         0 },
3160     { X86::VPSRLWZ256rik,         X86::VPSRLWZ256mik,         0 },
3161 
3162     // AVX-512VL 128-bit masked foldable instructions
3163     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
3164     { X86::VPABSBZ128rrk,         X86::VPABSBZ128rmk,         0 },
3165     { X86::VPABSDZ128rrk,         X86::VPABSDZ128rmk,         0 },
3166     { X86::VPABSQZ128rrk,         X86::VPABSQZ128rmk,         0 },
3167     { X86::VPABSWZ128rrk,         X86::VPABSWZ128rmk,         0 },
3168     { X86::VPCONFLICTDZ128rrk,    X86::VPCONFLICTDZ128rmk,    0 },
3169     { X86::VPCONFLICTQZ128rrk,    X86::VPCONFLICTQZ128rmk,    0 },
3170     { X86::VPERMILPDZ128rik,      X86::VPERMILPDZ128mik,      0 },
3171     { X86::VPERMILPSZ128rik,      X86::VPERMILPSZ128mik,      0 },
3172     { X86::VPLZCNTDZ128rrk,       X86::VPLZCNTDZ128rmk,       0 },
3173     { X86::VPLZCNTQZ128rrk,       X86::VPLZCNTQZ128rmk,       0 },
3174     { X86::VPMOVSXBDZ128rrk,      X86::VPMOVSXBDZ128rmk,      TB_NO_REVERSE },
3175     { X86::VPMOVSXBQZ128rrk,      X86::VPMOVSXBQZ128rmk,      TB_NO_REVERSE },
3176     { X86::VPMOVSXBWZ128rrk,      X86::VPMOVSXBWZ128rmk,      TB_NO_REVERSE },
3177     { X86::VPMOVSXDQZ128rrk,      X86::VPMOVSXDQZ128rmk,      TB_NO_REVERSE },
3178     { X86::VPMOVSXWDZ128rrk,      X86::VPMOVSXWDZ128rmk,      TB_NO_REVERSE },
3179     { X86::VPMOVSXWQZ128rrk,      X86::VPMOVSXWQZ128rmk,      TB_NO_REVERSE },
3180     { X86::VPMOVZXBDZ128rrk,      X86::VPMOVZXBDZ128rmk,      TB_NO_REVERSE },
3181     { X86::VPMOVZXBQZ128rrk,      X86::VPMOVZXBQZ128rmk,      TB_NO_REVERSE },
3182     { X86::VPMOVZXBWZ128rrk,      X86::VPMOVZXBWZ128rmk,      TB_NO_REVERSE },
3183     { X86::VPMOVZXDQZ128rrk,      X86::VPMOVZXDQZ128rmk,      TB_NO_REVERSE },
3184     { X86::VPMOVZXWDZ128rrk,      X86::VPMOVZXWDZ128rmk,      TB_NO_REVERSE },
3185     { X86::VPMOVZXWQZ128rrk,      X86::VPMOVZXWQZ128rmk,      TB_NO_REVERSE },
3186     { X86::VPOPCNTBZ128rrk,       X86::VPOPCNTBZ128rmk,       0 },
3187     { X86::VPOPCNTDZ128rrk,       X86::VPOPCNTDZ128rmk,       0 },
3188     { X86::VPOPCNTQZ128rrk,       X86::VPOPCNTQZ128rmk,       0 },
3189     { X86::VPOPCNTWZ128rrk,       X86::VPOPCNTWZ128rmk,       0 },
3190     { X86::VPSHUFDZ128rik,        X86::VPSHUFDZ128mik,        0 },
3191     { X86::VPSHUFHWZ128rik,       X86::VPSHUFHWZ128mik,       0 },
3192     { X86::VPSHUFLWZ128rik,       X86::VPSHUFLWZ128mik,       0 },
3193     { X86::VPSLLDZ128rik,         X86::VPSLLDZ128mik,         0 },
3194     { X86::VPSLLQZ128rik,         X86::VPSLLQZ128mik,         0 },
3195     { X86::VPSLLWZ128rik,         X86::VPSLLWZ128mik,         0 },
3196     { X86::VPSRADZ128rik,         X86::VPSRADZ128mik,         0 },
3197     { X86::VPSRAQZ128rik,         X86::VPSRAQZ128mik,         0 },
3198     { X86::VPSRAWZ128rik,         X86::VPSRAWZ128mik,         0 },
3199     { X86::VPSRLDZ128rik,         X86::VPSRLDZ128mik,         0 },
3200     { X86::VPSRLQZ128rik,         X86::VPSRLQZ128mik,         0 },
3201     { X86::VPSRLWZ128rik,         X86::VPSRLWZ128mik,         0 },
3202 
3203     // AVX-512 masked compare instructions
3204     { X86::VCMPPDZ128rrik,        X86::VCMPPDZ128rmik,        0 },
3205     { X86::VCMPPSZ128rrik,        X86::VCMPPSZ128rmik,        0 },
3206     { X86::VCMPPDZ256rrik,        X86::VCMPPDZ256rmik,        0 },
3207     { X86::VCMPPSZ256rrik,        X86::VCMPPSZ256rmik,        0 },
3208     { X86::VCMPPDZrrik,           X86::VCMPPDZrmik,           0 },
3209     { X86::VCMPPSZrrik,           X86::VCMPPSZrmik,           0 },
3210     { X86::VCMPSDZrr_Intk,        X86::VCMPSDZrm_Intk,        TB_NO_REVERSE },
3211     { X86::VCMPSSZrr_Intk,        X86::VCMPSSZrm_Intk,        TB_NO_REVERSE },
3212     { X86::VPCMPBZ128rrik,        X86::VPCMPBZ128rmik,        0 },
3213     { X86::VPCMPBZ256rrik,        X86::VPCMPBZ256rmik,        0 },
3214     { X86::VPCMPBZrrik,           X86::VPCMPBZrmik,           0 },
3215     { X86::VPCMPDZ128rrik,        X86::VPCMPDZ128rmik,        0 },
3216     { X86::VPCMPDZ256rrik,        X86::VPCMPDZ256rmik,        0 },
3217     { X86::VPCMPDZrrik,           X86::VPCMPDZrmik,           0 },
3218     { X86::VPCMPEQBZ128rrk,       X86::VPCMPEQBZ128rmk,       0 },
3219     { X86::VPCMPEQBZ256rrk,       X86::VPCMPEQBZ256rmk,       0 },
3220     { X86::VPCMPEQBZrrk,          X86::VPCMPEQBZrmk,          0 },
3221     { X86::VPCMPEQDZ128rrk,       X86::VPCMPEQDZ128rmk,       0 },
3222     { X86::VPCMPEQDZ256rrk,       X86::VPCMPEQDZ256rmk,       0 },
3223     { X86::VPCMPEQDZrrk,          X86::VPCMPEQDZrmk,          0 },
3224     { X86::VPCMPEQQZ128rrk,       X86::VPCMPEQQZ128rmk,       0 },
3225     { X86::VPCMPEQQZ256rrk,       X86::VPCMPEQQZ256rmk,       0 },
3226     { X86::VPCMPEQQZrrk,          X86::VPCMPEQQZrmk,          0 },
3227     { X86::VPCMPEQWZ128rrk,       X86::VPCMPEQWZ128rmk,       0 },
3228     { X86::VPCMPEQWZ256rrk,       X86::VPCMPEQWZ256rmk,       0 },
3229     { X86::VPCMPEQWZrrk,          X86::VPCMPEQWZrmk,          0 },
3230     { X86::VPCMPGTBZ128rrk,       X86::VPCMPGTBZ128rmk,       0 },
3231     { X86::VPCMPGTBZ256rrk,       X86::VPCMPGTBZ256rmk,       0 },
3232     { X86::VPCMPGTBZrrk,          X86::VPCMPGTBZrmk,          0 },
3233     { X86::VPCMPGTDZ128rrk,       X86::VPCMPGTDZ128rmk,       0 },
3234     { X86::VPCMPGTDZ256rrk,       X86::VPCMPGTDZ256rmk,       0 },
3235     { X86::VPCMPGTDZrrk,          X86::VPCMPGTDZrmk,          0 },
3236     { X86::VPCMPGTQZ128rrk,       X86::VPCMPGTQZ128rmk,       0 },
3237     { X86::VPCMPGTQZ256rrk,       X86::VPCMPGTQZ256rmk,       0 },
3238     { X86::VPCMPGTQZrrk,          X86::VPCMPGTQZrmk,          0 },
3239     { X86::VPCMPGTWZ128rrk,       X86::VPCMPGTWZ128rmk,       0 },
3240     { X86::VPCMPGTWZ256rrk,       X86::VPCMPGTWZ256rmk,       0 },
3241     { X86::VPCMPGTWZrrk,          X86::VPCMPGTWZrmk,          0 },
3242     { X86::VPCMPQZ128rrik,        X86::VPCMPQZ128rmik,        0 },
3243     { X86::VPCMPQZ256rrik,        X86::VPCMPQZ256rmik,        0 },
3244     { X86::VPCMPQZrrik,           X86::VPCMPQZrmik,           0 },
3245     { X86::VPCMPUBZ128rrik,       X86::VPCMPUBZ128rmik,       0 },
3246     { X86::VPCMPUBZ256rrik,       X86::VPCMPUBZ256rmik,       0 },
3247     { X86::VPCMPUBZrrik,          X86::VPCMPUBZrmik,          0 },
3248     { X86::VPCMPUDZ128rrik,       X86::VPCMPUDZ128rmik,       0 },
3249     { X86::VPCMPUDZ256rrik,       X86::VPCMPUDZ256rmik,       0 },
3250     { X86::VPCMPUDZrrik,          X86::VPCMPUDZrmik,          0 },
3251     { X86::VPCMPUQZ128rrik,       X86::VPCMPUQZ128rmik,       0 },
3252     { X86::VPCMPUQZ256rrik,       X86::VPCMPUQZ256rmik,       0 },
3253     { X86::VPCMPUQZrrik,          X86::VPCMPUQZrmik,          0 },
3254     { X86::VPCMPUWZ128rrik,       X86::VPCMPUWZ128rmik,       0 },
3255     { X86::VPCMPUWZ256rrik,       X86::VPCMPUWZ256rmik,       0 },
3256     { X86::VPCMPUWZrrik,          X86::VPCMPUWZrmik,          0 },
3257     { X86::VPCMPWZ128rrik,        X86::VPCMPWZ128rmik,        0 },
3258     { X86::VPCMPWZ256rrik,        X86::VPCMPWZ256rmik,        0 },
3259     { X86::VPCMPWZrrik,           X86::VPCMPWZrmik,           0 },
3260   };
3261 
3262   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
3263     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3264                   Entry.RegOp, Entry.MemOp,
3265                   // Index 3, folded load
3266                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
3267   }
3268   auto I = X86InstrFMA3Info::rm_begin();
3269   auto E = X86InstrFMA3Info::rm_end();
3270   for (; I != E; ++I) {
3271     if (!I.getGroup()->isKMasked()) {
3272       // Intrinsic forms need to pass TB_NO_REVERSE.
3273       if (I.getGroup()->isIntrinsic()) {
3274         AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3275                       I.getRegOpcode(), I.getMemOpcode(),
3276                       TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD | TB_NO_REVERSE);
3277       } else {
3278         AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3279                       I.getRegOpcode(), I.getMemOpcode(),
3280                       TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD);
3281       }
3282     }
3283   }
3284 
3285   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
3286     // AVX-512 foldable masked instructions
3287     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
3288     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
3289     { X86::VADDSDZrr_Intk,     X86::VADDSDZrm_Intk,       TB_NO_REVERSE },
3290     { X86::VADDSSZrr_Intk,     X86::VADDSSZrm_Intk,       TB_NO_REVERSE },
3291     { X86::VALIGNDZrrik,       X86::VALIGNDZrmik,         0 },
3292     { X86::VALIGNQZrrik,       X86::VALIGNQZrmik,         0 },
3293     { X86::VANDNPDZrrk,        X86::VANDNPDZrmk,          0 },
3294     { X86::VANDNPSZrrk,        X86::VANDNPSZrmk,          0 },
3295     { X86::VANDPDZrrk,         X86::VANDPDZrmk,           0 },
3296     { X86::VANDPSZrrk,         X86::VANDPSZrmk,           0 },
3297     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
3298     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
3299     { X86::VDIVSDZrr_Intk,     X86::VDIVSDZrm_Intk,       TB_NO_REVERSE },
3300     { X86::VDIVSSZrr_Intk,     X86::VDIVSSZrm_Intk,       TB_NO_REVERSE },
3301     { X86::VINSERTF32x4Zrrk,   X86::VINSERTF32x4Zrmk,     0 },
3302     { X86::VINSERTF32x8Zrrk,   X86::VINSERTF32x8Zrmk,     0 },
3303     { X86::VINSERTF64x2Zrrk,   X86::VINSERTF64x2Zrmk,     0 },
3304     { X86::VINSERTF64x4Zrrk,   X86::VINSERTF64x4Zrmk,     0 },
3305     { X86::VINSERTI32x4Zrrk,   X86::VINSERTI32x4Zrmk,     0 },
3306     { X86::VINSERTI32x8Zrrk,   X86::VINSERTI32x8Zrmk,     0 },
3307     { X86::VINSERTI64x2Zrrk,   X86::VINSERTI64x2Zrmk,     0 },
3308     { X86::VINSERTI64x4Zrrk,   X86::VINSERTI64x4Zrmk,     0 },
3309     { X86::VMAXCPDZrrk,        X86::VMAXCPDZrmk,          0 },
3310     { X86::VMAXCPSZrrk,        X86::VMAXCPSZrmk,          0 },
3311     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
3312     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
3313     { X86::VMAXSDZrr_Intk,     X86::VMAXSDZrm_Intk,       0 },
3314     { X86::VMAXSSZrr_Intk,     X86::VMAXSSZrm_Intk,       0 },
3315     { X86::VMINCPDZrrk,        X86::VMINCPDZrmk,          0 },
3316     { X86::VMINCPSZrrk,        X86::VMINCPSZrmk,          0 },
3317     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
3318     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
3319     { X86::VMINSDZrr_Intk,     X86::VMINSDZrm_Intk,       0 },
3320     { X86::VMINSSZrr_Intk,     X86::VMINSSZrm_Intk,       0 },
3321     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
3322     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
3323     { X86::VMULSDZrr_Intk,     X86::VMULSDZrm_Intk,       TB_NO_REVERSE },
3324     { X86::VMULSSZrr_Intk,     X86::VMULSSZrm_Intk,       TB_NO_REVERSE },
3325     { X86::VORPDZrrk,          X86::VORPDZrmk,            0 },
3326     { X86::VORPSZrrk,          X86::VORPSZrmk,            0 },
3327     { X86::VPACKSSDWZrrk,      X86::VPACKSSDWZrmk,        0 },
3328     { X86::VPACKSSWBZrrk,      X86::VPACKSSWBZrmk,        0 },
3329     { X86::VPACKUSDWZrrk,      X86::VPACKUSDWZrmk,        0 },
3330     { X86::VPACKUSWBZrrk,      X86::VPACKUSWBZrmk,        0 },
3331     { X86::VPADDBZrrk,         X86::VPADDBZrmk,           0 },
3332     { X86::VPADDDZrrk,         X86::VPADDDZrmk,           0 },
3333     { X86::VPADDQZrrk,         X86::VPADDQZrmk,           0 },
3334     { X86::VPADDSBZrrk,        X86::VPADDSBZrmk,          0 },
3335     { X86::VPADDSWZrrk,        X86::VPADDSWZrmk,          0 },
3336     { X86::VPADDUSBZrrk,       X86::VPADDUSBZrmk,         0 },
3337     { X86::VPADDUSWZrrk,       X86::VPADDUSWZrmk,         0 },
3338     { X86::VPADDWZrrk,         X86::VPADDWZrmk,           0 },
3339     { X86::VPALIGNRZrrik,      X86::VPALIGNRZrmik,        0 },
3340     { X86::VPANDDZrrk,         X86::VPANDDZrmk,           0 },
3341     { X86::VPANDNDZrrk,        X86::VPANDNDZrmk,          0 },
3342     { X86::VPANDNQZrrk,        X86::VPANDNQZrmk,          0 },
3343     { X86::VPANDQZrrk,         X86::VPANDQZrmk,           0 },
3344     { X86::VPAVGBZrrk,         X86::VPAVGBZrmk,           0 },
3345     { X86::VPAVGWZrrk,         X86::VPAVGWZrmk,           0 },
3346     { X86::VPERMBZrrk,         X86::VPERMBZrmk,           0 },
3347     { X86::VPERMDZrrk,         X86::VPERMDZrmk,           0 },
3348     { X86::VPERMI2Brrk,        X86::VPERMI2Brmk,          0 },
3349     { X86::VPERMI2Drrk,        X86::VPERMI2Drmk,          0 },
3350     { X86::VPERMI2PSrrk,       X86::VPERMI2PSrmk,         0 },
3351     { X86::VPERMI2PDrrk,       X86::VPERMI2PDrmk,         0 },
3352     { X86::VPERMI2Qrrk,        X86::VPERMI2Qrmk,          0 },
3353     { X86::VPERMI2Wrrk,        X86::VPERMI2Wrmk,          0 },
3354     { X86::VPERMILPDZrrk,      X86::VPERMILPDZrmk,        0 },
3355     { X86::VPERMILPSZrrk,      X86::VPERMILPSZrmk,        0 },
3356     { X86::VPERMPDZrrk,        X86::VPERMPDZrmk,          0 },
3357     { X86::VPERMPSZrrk,        X86::VPERMPSZrmk,          0 },
3358     { X86::VPERMQZrrk,         X86::VPERMQZrmk,           0 },
3359     { X86::VPERMT2Brrk,        X86::VPERMT2Brmk,          0 },
3360     { X86::VPERMT2Drrk,        X86::VPERMT2Drmk,          0 },
3361     { X86::VPERMT2PSrrk,       X86::VPERMT2PSrmk,         0 },
3362     { X86::VPERMT2PDrrk,       X86::VPERMT2PDrmk,         0 },
3363     { X86::VPERMT2Qrrk,        X86::VPERMT2Qrmk,          0 },
3364     { X86::VPERMT2Wrrk,        X86::VPERMT2Wrmk,          0 },
3365     { X86::VPERMWZrrk,         X86::VPERMWZrmk,           0 },
3366     { X86::VPMADD52HUQZrk,     X86::VPMADD52HUQZmk,       0 },
3367     { X86::VPMADD52LUQZrk,     X86::VPMADD52LUQZmk,       0 },
3368     { X86::VPMADDUBSWZrrk,     X86::VPMADDUBSWZrmk,       0 },
3369     { X86::VPMADDWDZrrk,       X86::VPMADDWDZrmk,         0 },
3370     { X86::VPMAXSBZrrk,        X86::VPMAXSBZrmk,          0 },
3371     { X86::VPMAXSDZrrk,        X86::VPMAXSDZrmk,          0 },
3372     { X86::VPMAXSQZrrk,        X86::VPMAXSQZrmk,          0 },
3373     { X86::VPMAXSWZrrk,        X86::VPMAXSWZrmk,          0 },
3374     { X86::VPMAXUBZrrk,        X86::VPMAXUBZrmk,          0 },
3375     { X86::VPMAXUDZrrk,        X86::VPMAXUDZrmk,          0 },
3376     { X86::VPMAXUQZrrk,        X86::VPMAXUQZrmk,          0 },
3377     { X86::VPMAXUWZrrk,        X86::VPMAXUWZrmk,          0 },
3378     { X86::VPMINSBZrrk,        X86::VPMINSBZrmk,          0 },
3379     { X86::VPMINSDZrrk,        X86::VPMINSDZrmk,          0 },
3380     { X86::VPMINSQZrrk,        X86::VPMINSQZrmk,          0 },
3381     { X86::VPMINSWZrrk,        X86::VPMINSWZrmk,          0 },
3382     { X86::VPMINUBZrrk,        X86::VPMINUBZrmk,          0 },
3383     { X86::VPMINUDZrrk,        X86::VPMINUDZrmk,          0 },
3384     { X86::VPMINUQZrrk,        X86::VPMINUQZrmk,          0 },
3385     { X86::VPMINUWZrrk,        X86::VPMINUWZrmk,          0 },
3386     { X86::VPMULDQZrrk,        X86::VPMULDQZrmk,          0 },
3387     { X86::VPMULLDZrrk,        X86::VPMULLDZrmk,          0 },
3388     { X86::VPMULLQZrrk,        X86::VPMULLQZrmk,          0 },
3389     { X86::VPMULLWZrrk,        X86::VPMULLWZrmk,          0 },
3390     { X86::VPMULUDQZrrk,       X86::VPMULUDQZrmk,         0 },
3391     { X86::VPORDZrrk,          X86::VPORDZrmk,            0 },
3392     { X86::VPORQZrrk,          X86::VPORQZrmk,            0 },
3393     { X86::VPSHUFBZrrk,        X86::VPSHUFBZrmk,          0 },
3394     { X86::VPSLLDZrrk,         X86::VPSLLDZrmk,           0 },
3395     { X86::VPSLLQZrrk,         X86::VPSLLQZrmk,           0 },
3396     { X86::VPSLLVDZrrk,        X86::VPSLLVDZrmk,          0 },
3397     { X86::VPSLLVQZrrk,        X86::VPSLLVQZrmk,          0 },
3398     { X86::VPSLLVWZrrk,        X86::VPSLLVWZrmk,          0 },
3399     { X86::VPSLLWZrrk,         X86::VPSLLWZrmk,           0 },
3400     { X86::VPSRADZrrk,         X86::VPSRADZrmk,           0 },
3401     { X86::VPSRAQZrrk,         X86::VPSRAQZrmk,           0 },
3402     { X86::VPSRAVDZrrk,        X86::VPSRAVDZrmk,          0 },
3403     { X86::VPSRAVQZrrk,        X86::VPSRAVQZrmk,          0 },
3404     { X86::VPSRAVWZrrk,        X86::VPSRAVWZrmk,          0 },
3405     { X86::VPSRAWZrrk,         X86::VPSRAWZrmk,           0 },
3406     { X86::VPSRLDZrrk,         X86::VPSRLDZrmk,           0 },
3407     { X86::VPSRLQZrrk,         X86::VPSRLQZrmk,           0 },
3408     { X86::VPSRLVDZrrk,        X86::VPSRLVDZrmk,          0 },
3409     { X86::VPSRLVQZrrk,        X86::VPSRLVQZrmk,          0 },
3410     { X86::VPSRLVWZrrk,        X86::VPSRLVWZrmk,          0 },
3411     { X86::VPSRLWZrrk,         X86::VPSRLWZrmk,           0 },
3412     { X86::VPSUBBZrrk,         X86::VPSUBBZrmk,           0 },
3413     { X86::VPSUBDZrrk,         X86::VPSUBDZrmk,           0 },
3414     { X86::VPSUBQZrrk,         X86::VPSUBQZrmk,           0 },
3415     { X86::VPSUBSBZrrk,        X86::VPSUBSBZrmk,          0 },
3416     { X86::VPSUBSWZrrk,        X86::VPSUBSWZrmk,          0 },
3417     { X86::VPSUBUSBZrrk,       X86::VPSUBUSBZrmk,         0 },
3418     { X86::VPSUBUSWZrrk,       X86::VPSUBUSWZrmk,         0 },
3419     { X86::VPSUBWZrrk,         X86::VPSUBWZrmk,           0 },
3420     { X86::VPTERNLOGDZrrik,    X86::VPTERNLOGDZrmik,      0 },
3421     { X86::VPTERNLOGQZrrik,    X86::VPTERNLOGQZrmik,      0 },
3422     { X86::VPUNPCKHBWZrrk,     X86::VPUNPCKHBWZrmk,       0 },
3423     { X86::VPUNPCKHDQZrrk,     X86::VPUNPCKHDQZrmk,       0 },
3424     { X86::VPUNPCKHQDQZrrk,    X86::VPUNPCKHQDQZrmk,      0 },
3425     { X86::VPUNPCKHWDZrrk,     X86::VPUNPCKHWDZrmk,       0 },
3426     { X86::VPUNPCKLBWZrrk,     X86::VPUNPCKLBWZrmk,       0 },
3427     { X86::VPUNPCKLDQZrrk,     X86::VPUNPCKLDQZrmk,       0 },
3428     { X86::VPUNPCKLQDQZrrk,    X86::VPUNPCKLQDQZrmk,      0 },
3429     { X86::VPUNPCKLWDZrrk,     X86::VPUNPCKLWDZrmk,       0 },
3430     { X86::VPXORDZrrk,         X86::VPXORDZrmk,           0 },
3431     { X86::VPXORQZrrk,         X86::VPXORQZrmk,           0 },
3432     { X86::VSHUFF32X4Zrrik,    X86::VSHUFF32X4Zrmik,      0 },
3433     { X86::VSHUFF64X2Zrrik,    X86::VSHUFF64X2Zrmik,      0 },
3434     { X86::VSHUFI32X4Zrrik,    X86::VSHUFI32X4Zrmik,      0 },
3435     { X86::VSHUFI64X2Zrrik,    X86::VSHUFI64X2Zrmik,      0 },
3436     { X86::VSHUFPDZrrik,       X86::VSHUFPDZrmik,         0 },
3437     { X86::VSHUFPSZrrik,       X86::VSHUFPSZrmik,         0 },
3438     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
3439     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
3440     { X86::VSUBSDZrr_Intk,     X86::VSUBSDZrm_Intk,       TB_NO_REVERSE },
3441     { X86::VSUBSSZrr_Intk,     X86::VSUBSSZrm_Intk,       TB_NO_REVERSE },
3442     { X86::VUNPCKHPDZrrk,      X86::VUNPCKHPDZrmk,        0 },
3443     { X86::VUNPCKHPSZrrk,      X86::VUNPCKHPSZrmk,        0 },
3444     { X86::VUNPCKLPDZrrk,      X86::VUNPCKLPDZrmk,        0 },
3445     { X86::VUNPCKLPSZrrk,      X86::VUNPCKLPSZrmk,        0 },
3446     { X86::VXORPDZrrk,         X86::VXORPDZrmk,           0 },
3447     { X86::VXORPSZrrk,         X86::VXORPSZrmk,           0 },
3448 
3449     // AVX-512{F,VL} foldable masked instructions 256-bit
3450     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
3451     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
3452     { X86::VALIGNDZ256rrik,    X86::VALIGNDZ256rmik,      0 },
3453     { X86::VALIGNQZ256rrik,    X86::VALIGNQZ256rmik,      0 },
3454     { X86::VANDNPDZ256rrk,     X86::VANDNPDZ256rmk,       0 },
3455     { X86::VANDNPSZ256rrk,     X86::VANDNPSZ256rmk,       0 },
3456     { X86::VANDPDZ256rrk,      X86::VANDPDZ256rmk,        0 },
3457     { X86::VANDPSZ256rrk,      X86::VANDPSZ256rmk,        0 },
3458     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
3459     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
3460     { X86::VINSERTF32x4Z256rrk,X86::VINSERTF32x4Z256rmk,  0 },
3461     { X86::VINSERTF64x2Z256rrk,X86::VINSERTF64x2Z256rmk,  0 },
3462     { X86::VINSERTI32x4Z256rrk,X86::VINSERTI32x4Z256rmk,  0 },
3463     { X86::VINSERTI64x2Z256rrk,X86::VINSERTI64x2Z256rmk,  0 },
3464     { X86::VMAXCPDZ256rrk,     X86::VMAXCPDZ256rmk,       0 },
3465     { X86::VMAXCPSZ256rrk,     X86::VMAXCPSZ256rmk,       0 },
3466     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
3467     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
3468     { X86::VMINCPDZ256rrk,     X86::VMINCPDZ256rmk,       0 },
3469     { X86::VMINCPSZ256rrk,     X86::VMINCPSZ256rmk,       0 },
3470     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
3471     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
3472     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
3473     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
3474     { X86::VORPDZ256rrk,       X86::VORPDZ256rmk,         0 },
3475     { X86::VORPSZ256rrk,       X86::VORPSZ256rmk,         0 },
3476     { X86::VPACKSSDWZ256rrk,   X86::VPACKSSDWZ256rmk,     0 },
3477     { X86::VPACKSSWBZ256rrk,   X86::VPACKSSWBZ256rmk,     0 },
3478     { X86::VPACKUSDWZ256rrk,   X86::VPACKUSDWZ256rmk,     0 },
3479     { X86::VPACKUSWBZ256rrk,   X86::VPACKUSWBZ256rmk,     0 },
3480     { X86::VPADDBZ256rrk,      X86::VPADDBZ256rmk,        0 },
3481     { X86::VPADDDZ256rrk,      X86::VPADDDZ256rmk,        0 },
3482     { X86::VPADDQZ256rrk,      X86::VPADDQZ256rmk,        0 },
3483     { X86::VPADDSBZ256rrk,     X86::VPADDSBZ256rmk,       0 },
3484     { X86::VPADDSWZ256rrk,     X86::VPADDSWZ256rmk,       0 },
3485     { X86::VPADDUSBZ256rrk,    X86::VPADDUSBZ256rmk,      0 },
3486     { X86::VPADDUSWZ256rrk,    X86::VPADDUSWZ256rmk,      0 },
3487     { X86::VPADDWZ256rrk,      X86::VPADDWZ256rmk,        0 },
3488     { X86::VPALIGNRZ256rrik,   X86::VPALIGNRZ256rmik,     0 },
3489     { X86::VPANDDZ256rrk,      X86::VPANDDZ256rmk,        0 },
3490     { X86::VPANDNDZ256rrk,     X86::VPANDNDZ256rmk,       0 },
3491     { X86::VPANDNQZ256rrk,     X86::VPANDNQZ256rmk,       0 },
3492     { X86::VPANDQZ256rrk,      X86::VPANDQZ256rmk,        0 },
3493     { X86::VPAVGBZ256rrk,      X86::VPAVGBZ256rmk,        0 },
3494     { X86::VPAVGWZ256rrk,      X86::VPAVGWZ256rmk,        0 },
3495     { X86::VPERMBZ256rrk,      X86::VPERMBZ256rmk,        0 },
3496     { X86::VPERMDZ256rrk,      X86::VPERMDZ256rmk,        0 },
3497     { X86::VPERMI2B256rrk,     X86::VPERMI2B256rmk,       0 },
3498     { X86::VPERMI2D256rrk,     X86::VPERMI2D256rmk,       0 },
3499     { X86::VPERMI2PD256rrk,    X86::VPERMI2PD256rmk,      0 },
3500     { X86::VPERMI2PS256rrk,    X86::VPERMI2PS256rmk,      0 },
3501     { X86::VPERMI2Q256rrk,     X86::VPERMI2Q256rmk,       0 },
3502     { X86::VPERMI2W256rrk,     X86::VPERMI2W256rmk,       0 },
3503     { X86::VPERMILPDZ256rrk,   X86::VPERMILPDZ256rmk,     0 },
3504     { X86::VPERMILPSZ256rrk,   X86::VPERMILPSZ256rmk,     0 },
3505     { X86::VPERMPDZ256rrk,     X86::VPERMPDZ256rmk,       0 },
3506     { X86::VPERMPSZ256rrk,     X86::VPERMPSZ256rmk,       0 },
3507     { X86::VPERMQZ256rrk,      X86::VPERMQZ256rmk,        0 },
3508     { X86::VPERMT2B256rrk,     X86::VPERMT2B256rmk,       0 },
3509     { X86::VPERMT2D256rrk,     X86::VPERMT2D256rmk,       0 },
3510     { X86::VPERMT2PD256rrk,    X86::VPERMT2PD256rmk,      0 },
3511     { X86::VPERMT2PS256rrk,    X86::VPERMT2PS256rmk,      0 },
3512     { X86::VPERMT2Q256rrk,     X86::VPERMT2Q256rmk,       0 },
3513     { X86::VPERMT2W256rrk,     X86::VPERMT2W256rmk,       0 },
3514     { X86::VPERMWZ256rrk,      X86::VPERMWZ256rmk,        0 },
3515     { X86::VPMADD52HUQZ256rk,  X86::VPMADD52HUQZ256mk,    0 },
3516     { X86::VPMADD52LUQZ256rk,  X86::VPMADD52LUQZ256mk,    0 },
3517     { X86::VPMADDUBSWZ256rrk,  X86::VPMADDUBSWZ256rmk,    0 },
3518     { X86::VPMADDWDZ256rrk,    X86::VPMADDWDZ256rmk,      0 },
3519     { X86::VPMAXSBZ256rrk,     X86::VPMAXSBZ256rmk,       0 },
3520     { X86::VPMAXSDZ256rrk,     X86::VPMAXSDZ256rmk,       0 },
3521     { X86::VPMAXSQZ256rrk,     X86::VPMAXSQZ256rmk,       0 },
3522     { X86::VPMAXSWZ256rrk,     X86::VPMAXSWZ256rmk,       0 },
3523     { X86::VPMAXUBZ256rrk,     X86::VPMAXUBZ256rmk,       0 },
3524     { X86::VPMAXUDZ256rrk,     X86::VPMAXUDZ256rmk,       0 },
3525     { X86::VPMAXUQZ256rrk,     X86::VPMAXUQZ256rmk,       0 },
3526     { X86::VPMAXUWZ256rrk,     X86::VPMAXUWZ256rmk,       0 },
3527     { X86::VPMINSBZ256rrk,     X86::VPMINSBZ256rmk,       0 },
3528     { X86::VPMINSDZ256rrk,     X86::VPMINSDZ256rmk,       0 },
3529     { X86::VPMINSQZ256rrk,     X86::VPMINSQZ256rmk,       0 },
3530     { X86::VPMINSWZ256rrk,     X86::VPMINSWZ256rmk,       0 },
3531     { X86::VPMINUBZ256rrk,     X86::VPMINUBZ256rmk,       0 },
3532     { X86::VPMINUDZ256rrk,     X86::VPMINUDZ256rmk,       0 },
3533     { X86::VPMINUQZ256rrk,     X86::VPMINUQZ256rmk,       0 },
3534     { X86::VPMINUWZ256rrk,     X86::VPMINUWZ256rmk,       0 },
3535     { X86::VPMULDQZ256rrk,     X86::VPMULDQZ256rmk,       0 },
3536     { X86::VPMULLDZ256rrk,     X86::VPMULLDZ256rmk,       0 },
3537     { X86::VPMULLQZ256rrk,     X86::VPMULLQZ256rmk,       0 },
3538     { X86::VPMULLWZ256rrk,     X86::VPMULLWZ256rmk,       0 },
3539     { X86::VPMULUDQZ256rrk,    X86::VPMULUDQZ256rmk,      0 },
3540     { X86::VPORDZ256rrk,       X86::VPORDZ256rmk,         0 },
3541     { X86::VPORQZ256rrk,       X86::VPORQZ256rmk,         0 },
3542     { X86::VPSHUFBZ256rrk,     X86::VPSHUFBZ256rmk,       0 },
3543     { X86::VPSLLDZ256rrk,      X86::VPSLLDZ256rmk,        0 },
3544     { X86::VPSLLQZ256rrk,      X86::VPSLLQZ256rmk,        0 },
3545     { X86::VPSLLVDZ256rrk,     X86::VPSLLVDZ256rmk,       0 },
3546     { X86::VPSLLVQZ256rrk,     X86::VPSLLVQZ256rmk,       0 },
3547     { X86::VPSLLVWZ256rrk,     X86::VPSLLVWZ256rmk,       0 },
3548     { X86::VPSLLWZ256rrk,      X86::VPSLLWZ256rmk,        0 },
3549     { X86::VPSRADZ256rrk,      X86::VPSRADZ256rmk,        0 },
3550     { X86::VPSRAQZ256rrk,      X86::VPSRAQZ256rmk,        0 },
3551     { X86::VPSRAVDZ256rrk,     X86::VPSRAVDZ256rmk,       0 },
3552     { X86::VPSRAVQZ256rrk,     X86::VPSRAVQZ256rmk,       0 },
3553     { X86::VPSRAVWZ256rrk,     X86::VPSRAVWZ256rmk,       0 },
3554     { X86::VPSRAWZ256rrk,      X86::VPSRAWZ256rmk,        0 },
3555     { X86::VPSRLDZ256rrk,      X86::VPSRLDZ256rmk,        0 },
3556     { X86::VPSRLQZ256rrk,      X86::VPSRLQZ256rmk,        0 },
3557     { X86::VPSRLVDZ256rrk,     X86::VPSRLVDZ256rmk,       0 },
3558     { X86::VPSRLVQZ256rrk,     X86::VPSRLVQZ256rmk,       0 },
3559     { X86::VPSRLVWZ256rrk,     X86::VPSRLVWZ256rmk,       0 },
3560     { X86::VPSRLWZ256rrk,      X86::VPSRLWZ256rmk,        0 },
3561     { X86::VPSUBBZ256rrk,      X86::VPSUBBZ256rmk,        0 },
3562     { X86::VPSUBDZ256rrk,      X86::VPSUBDZ256rmk,        0 },
3563     { X86::VPSUBQZ256rrk,      X86::VPSUBQZ256rmk,        0 },
3564     { X86::VPSUBSBZ256rrk,     X86::VPSUBSBZ256rmk,       0 },
3565     { X86::VPSUBSWZ256rrk,     X86::VPSUBSWZ256rmk,       0 },
3566     { X86::VPSUBUSBZ256rrk,    X86::VPSUBUSBZ256rmk,      0 },
3567     { X86::VPSUBUSWZ256rrk,    X86::VPSUBUSWZ256rmk,      0 },
3568     { X86::VPSUBWZ256rrk,      X86::VPSUBWZ256rmk,        0 },
3569     { X86::VPTERNLOGDZ256rrik, X86::VPTERNLOGDZ256rmik,   0 },
3570     { X86::VPTERNLOGQZ256rrik, X86::VPTERNLOGQZ256rmik,   0 },
3571     { X86::VPUNPCKHBWZ256rrk,  X86::VPUNPCKHBWZ256rmk,    0 },
3572     { X86::VPUNPCKHDQZ256rrk,  X86::VPUNPCKHDQZ256rmk,    0 },
3573     { X86::VPUNPCKHQDQZ256rrk, X86::VPUNPCKHQDQZ256rmk,   0 },
3574     { X86::VPUNPCKHWDZ256rrk,  X86::VPUNPCKHWDZ256rmk,    0 },
3575     { X86::VPUNPCKLBWZ256rrk,  X86::VPUNPCKLBWZ256rmk,    0 },
3576     { X86::VPUNPCKLDQZ256rrk,  X86::VPUNPCKLDQZ256rmk,    0 },
3577     { X86::VPUNPCKLQDQZ256rrk, X86::VPUNPCKLQDQZ256rmk,   0 },
3578     { X86::VPUNPCKLWDZ256rrk,  X86::VPUNPCKLWDZ256rmk,    0 },
3579     { X86::VPXORDZ256rrk,      X86::VPXORDZ256rmk,        0 },
3580     { X86::VPXORQZ256rrk,      X86::VPXORQZ256rmk,        0 },
3581     { X86::VSHUFF32X4Z256rrik, X86::VSHUFF32X4Z256rmik,   0 },
3582     { X86::VSHUFF64X2Z256rrik, X86::VSHUFF64X2Z256rmik,   0 },
3583     { X86::VSHUFI32X4Z256rrik, X86::VSHUFI32X4Z256rmik,   0 },
3584     { X86::VSHUFI64X2Z256rrik, X86::VSHUFI64X2Z256rmik,   0 },
3585     { X86::VSHUFPDZ256rrik,    X86::VSHUFPDZ256rmik,      0 },
3586     { X86::VSHUFPSZ256rrik,    X86::VSHUFPSZ256rmik,      0 },
3587     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
3588     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
3589     { X86::VUNPCKHPDZ256rrk,   X86::VUNPCKHPDZ256rmk,     0 },
3590     { X86::VUNPCKHPSZ256rrk,   X86::VUNPCKHPSZ256rmk,     0 },
3591     { X86::VUNPCKLPDZ256rrk,   X86::VUNPCKLPDZ256rmk,     0 },
3592     { X86::VUNPCKLPSZ256rrk,   X86::VUNPCKLPSZ256rmk,     0 },
3593     { X86::VXORPDZ256rrk,      X86::VXORPDZ256rmk,        0 },
3594     { X86::VXORPSZ256rrk,      X86::VXORPSZ256rmk,        0 },
3595 
3596     // AVX-512{F,VL} foldable instructions 128-bit
3597     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
3598     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
3599     { X86::VALIGNDZ128rrik,    X86::VALIGNDZ128rmik,      0 },
3600     { X86::VALIGNQZ128rrik,    X86::VALIGNQZ128rmik,      0 },
3601     { X86::VANDNPDZ128rrk,     X86::VANDNPDZ128rmk,       0 },
3602     { X86::VANDNPSZ128rrk,     X86::VANDNPSZ128rmk,       0 },
3603     { X86::VANDPDZ128rrk,      X86::VANDPDZ128rmk,        0 },
3604     { X86::VANDPSZ128rrk,      X86::VANDPSZ128rmk,        0 },
3605     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
3606     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
3607     { X86::VMAXCPDZ128rrk,     X86::VMAXCPDZ128rmk,       0 },
3608     { X86::VMAXCPSZ128rrk,     X86::VMAXCPSZ128rmk,       0 },
3609     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 },
3610     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
3611     { X86::VMINCPDZ128rrk,     X86::VMINCPDZ128rmk,       0 },
3612     { X86::VMINCPSZ128rrk,     X86::VMINCPSZ128rmk,       0 },
3613     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
3614     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
3615     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
3616     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
3617     { X86::VORPDZ128rrk,       X86::VORPDZ128rmk,         0 },
3618     { X86::VORPSZ128rrk,       X86::VORPSZ128rmk,         0 },
3619     { X86::VPACKSSDWZ128rrk,   X86::VPACKSSDWZ128rmk,     0 },
3620     { X86::VPACKSSWBZ128rrk,   X86::VPACKSSWBZ128rmk,     0 },
3621     { X86::VPACKUSDWZ128rrk,   X86::VPACKUSDWZ128rmk,     0 },
3622     { X86::VPACKUSWBZ128rrk,   X86::VPACKUSWBZ128rmk,     0 },
3623     { X86::VPADDBZ128rrk,      X86::VPADDBZ128rmk,        0 },
3624     { X86::VPADDDZ128rrk,      X86::VPADDDZ128rmk,        0 },
3625     { X86::VPADDQZ128rrk,      X86::VPADDQZ128rmk,        0 },
3626     { X86::VPADDSBZ128rrk,     X86::VPADDSBZ128rmk,       0 },
3627     { X86::VPADDSWZ128rrk,     X86::VPADDSWZ128rmk,       0 },
3628     { X86::VPADDUSBZ128rrk,    X86::VPADDUSBZ128rmk,      0 },
3629     { X86::VPADDUSWZ128rrk,    X86::VPADDUSWZ128rmk,      0 },
3630     { X86::VPADDWZ128rrk,      X86::VPADDWZ128rmk,        0 },
3631     { X86::VPALIGNRZ128rrik,   X86::VPALIGNRZ128rmik,     0 },
3632     { X86::VPANDDZ128rrk,      X86::VPANDDZ128rmk,        0 },
3633     { X86::VPANDNDZ128rrk,     X86::VPANDNDZ128rmk,       0 },
3634     { X86::VPANDNQZ128rrk,     X86::VPANDNQZ128rmk,       0 },
3635     { X86::VPANDQZ128rrk,      X86::VPANDQZ128rmk,        0 },
3636     { X86::VPAVGBZ128rrk,      X86::VPAVGBZ128rmk,        0 },
3637     { X86::VPAVGWZ128rrk,      X86::VPAVGWZ128rmk,        0 },
3638     { X86::VPERMBZ128rrk,      X86::VPERMBZ128rmk,        0 },
3639     { X86::VPERMI2B128rrk,     X86::VPERMI2B128rmk,       0 },
3640     { X86::VPERMI2D128rrk,     X86::VPERMI2D128rmk,       0 },
3641     { X86::VPERMI2PD128rrk,    X86::VPERMI2PD128rmk,      0 },
3642     { X86::VPERMI2PS128rrk,    X86::VPERMI2PS128rmk,      0 },
3643     { X86::VPERMI2Q128rrk,     X86::VPERMI2Q128rmk,       0 },
3644     { X86::VPERMI2W128rrk,     X86::VPERMI2W128rmk,       0 },
3645     { X86::VPERMILPDZ128rrk,   X86::VPERMILPDZ128rmk,     0 },
3646     { X86::VPERMILPSZ128rrk,   X86::VPERMILPSZ128rmk,     0 },
3647     { X86::VPERMT2B128rrk,     X86::VPERMT2B128rmk,       0 },
3648     { X86::VPERMT2D128rrk,     X86::VPERMT2D128rmk,       0 },
3649     { X86::VPERMT2PD128rrk,    X86::VPERMT2PD128rmk,      0 },
3650     { X86::VPERMT2PS128rrk,    X86::VPERMT2PS128rmk,      0 },
3651     { X86::VPERMT2Q128rrk,     X86::VPERMT2Q128rmk,       0 },
3652     { X86::VPERMT2W128rrk,     X86::VPERMT2W128rmk,       0 },
3653     { X86::VPERMWZ128rrk,      X86::VPERMWZ128rmk,        0 },
3654     { X86::VPMADD52HUQZ128rk,  X86::VPMADD52HUQZ128mk,    0 },
3655     { X86::VPMADD52LUQZ128rk,  X86::VPMADD52LUQZ128mk,    0 },
3656     { X86::VPMADDUBSWZ128rrk,  X86::VPMADDUBSWZ128rmk,    0 },
3657     { X86::VPMADDWDZ128rrk,    X86::VPMADDWDZ128rmk,      0 },
3658     { X86::VPMAXSBZ128rrk,     X86::VPMAXSBZ128rmk,       0 },
3659     { X86::VPMAXSDZ128rrk,     X86::VPMAXSDZ128rmk,       0 },
3660     { X86::VPMAXSQZ128rrk,     X86::VPMAXSQZ128rmk,       0 },
3661     { X86::VPMAXSWZ128rrk,     X86::VPMAXSWZ128rmk,       0 },
3662     { X86::VPMAXUBZ128rrk,     X86::VPMAXUBZ128rmk,       0 },
3663     { X86::VPMAXUDZ128rrk,     X86::VPMAXUDZ128rmk,       0 },
3664     { X86::VPMAXUQZ128rrk,     X86::VPMAXUQZ128rmk,       0 },
3665     { X86::VPMAXUWZ128rrk,     X86::VPMAXUWZ128rmk,       0 },
3666     { X86::VPMINSBZ128rrk,     X86::VPMINSBZ128rmk,       0 },
3667     { X86::VPMINSDZ128rrk,     X86::VPMINSDZ128rmk,       0 },
3668     { X86::VPMINSQZ128rrk,     X86::VPMINSQZ128rmk,       0 },
3669     { X86::VPMINSWZ128rrk,     X86::VPMINSWZ128rmk,       0 },
3670     { X86::VPMINUBZ128rrk,     X86::VPMINUBZ128rmk,       0 },
3671     { X86::VPMINUDZ128rrk,     X86::VPMINUDZ128rmk,       0 },
3672     { X86::VPMINUQZ128rrk,     X86::VPMINUQZ128rmk,       0 },
3673     { X86::VPMINUWZ128rrk,     X86::VPMINUWZ128rmk,       0 },
3674     { X86::VPMULDQZ128rrk,     X86::VPMULDQZ128rmk,       0 },
3675     { X86::VPMULLDZ128rrk,     X86::VPMULLDZ128rmk,       0 },
3676     { X86::VPMULLQZ128rrk,     X86::VPMULLQZ128rmk,       0 },
3677     { X86::VPMULLWZ128rrk,     X86::VPMULLWZ128rmk,       0 },
3678     { X86::VPMULUDQZ128rrk,    X86::VPMULUDQZ128rmk,      0 },
3679     { X86::VPORDZ128rrk,       X86::VPORDZ128rmk,         0 },
3680     { X86::VPORQZ128rrk,       X86::VPORQZ128rmk,         0 },
3681     { X86::VPSHUFBZ128rrk,     X86::VPSHUFBZ128rmk,       0 },
3682     { X86::VPSLLDZ128rrk,      X86::VPSLLDZ128rmk,        0 },
3683     { X86::VPSLLQZ128rrk,      X86::VPSLLQZ128rmk,        0 },
3684     { X86::VPSLLVDZ128rrk,     X86::VPSLLVDZ128rmk,       0 },
3685     { X86::VPSLLVQZ128rrk,     X86::VPSLLVQZ128rmk,       0 },
3686     { X86::VPSLLVWZ128rrk,     X86::VPSLLVWZ128rmk,       0 },
3687     { X86::VPSLLWZ128rrk,      X86::VPSLLWZ128rmk,        0 },
3688     { X86::VPSRADZ128rrk,      X86::VPSRADZ128rmk,        0 },
3689     { X86::VPSRAQZ128rrk,      X86::VPSRAQZ128rmk,        0 },
3690     { X86::VPSRAVDZ128rrk,     X86::VPSRAVDZ128rmk,       0 },
3691     { X86::VPSRAVQZ128rrk,     X86::VPSRAVQZ128rmk,       0 },
3692     { X86::VPSRAVWZ128rrk,     X86::VPSRAVWZ128rmk,       0 },
3693     { X86::VPSRAWZ128rrk,      X86::VPSRAWZ128rmk,        0 },
3694     { X86::VPSRLDZ128rrk,      X86::VPSRLDZ128rmk,        0 },
3695     { X86::VPSRLQZ128rrk,      X86::VPSRLQZ128rmk,        0 },
3696     { X86::VPSRLVDZ128rrk,     X86::VPSRLVDZ128rmk,       0 },
3697     { X86::VPSRLVQZ128rrk,     X86::VPSRLVQZ128rmk,       0 },
3698     { X86::VPSRLVWZ128rrk,     X86::VPSRLVWZ128rmk,       0 },
3699     { X86::VPSRLWZ128rrk,      X86::VPSRLWZ128rmk,        0 },
3700     { X86::VPSUBBZ128rrk,      X86::VPSUBBZ128rmk,        0 },
3701     { X86::VPSUBDZ128rrk,      X86::VPSUBDZ128rmk,        0 },
3702     { X86::VPSUBQZ128rrk,      X86::VPSUBQZ128rmk,        0 },
3703     { X86::VPSUBSBZ128rrk,     X86::VPSUBSBZ128rmk,       0 },
3704     { X86::VPSUBSWZ128rrk,     X86::VPSUBSWZ128rmk,       0 },
3705     { X86::VPSUBUSBZ128rrk,    X86::VPSUBUSBZ128rmk,      0 },
3706     { X86::VPSUBUSWZ128rrk,    X86::VPSUBUSWZ128rmk,      0 },
3707     { X86::VPSUBWZ128rrk,      X86::VPSUBWZ128rmk,        0 },
3708     { X86::VPTERNLOGDZ128rrik, X86::VPTERNLOGDZ128rmik,   0 },
3709     { X86::VPTERNLOGQZ128rrik, X86::VPTERNLOGQZ128rmik,   0 },
3710     { X86::VPUNPCKHBWZ128rrk,  X86::VPUNPCKHBWZ128rmk,    0 },
3711     { X86::VPUNPCKHDQZ128rrk,  X86::VPUNPCKHDQZ128rmk,    0 },
3712     { X86::VPUNPCKHQDQZ128rrk, X86::VPUNPCKHQDQZ128rmk,   0 },
3713     { X86::VPUNPCKHWDZ128rrk,  X86::VPUNPCKHWDZ128rmk,    0 },
3714     { X86::VPUNPCKLBWZ128rrk,  X86::VPUNPCKLBWZ128rmk,    0 },
3715     { X86::VPUNPCKLDQZ128rrk,  X86::VPUNPCKLDQZ128rmk,    0 },
3716     { X86::VPUNPCKLQDQZ128rrk, X86::VPUNPCKLQDQZ128rmk,   0 },
3717     { X86::VPUNPCKLWDZ128rrk,  X86::VPUNPCKLWDZ128rmk,    0 },
3718     { X86::VPXORDZ128rrk,      X86::VPXORDZ128rmk,        0 },
3719     { X86::VPXORQZ128rrk,      X86::VPXORQZ128rmk,        0 },
3720     { X86::VSHUFPDZ128rrik,    X86::VSHUFPDZ128rmik,      0 },
3721     { X86::VSHUFPSZ128rrik,    X86::VSHUFPSZ128rmik,      0 },
3722     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
3723     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
3724     { X86::VUNPCKHPDZ128rrk,   X86::VUNPCKHPDZ128rmk,     0 },
3725     { X86::VUNPCKHPSZ128rrk,   X86::VUNPCKHPSZ128rmk,     0 },
3726     { X86::VUNPCKLPDZ128rrk,   X86::VUNPCKLPDZ128rmk,     0 },
3727     { X86::VUNPCKLPSZ128rrk,   X86::VUNPCKLPSZ128rmk,     0 },
3728     { X86::VXORPDZ128rrk,      X86::VXORPDZ128rmk,        0 },
3729     { X86::VXORPSZ128rrk,      X86::VXORPSZ128rmk,        0 },
3730 
3731     // 512-bit three source instructions with zero masking.
3732     { X86::VPERMI2Brrkz,       X86::VPERMI2Brmkz,         0 },
3733     { X86::VPERMI2Drrkz,       X86::VPERMI2Drmkz,         0 },
3734     { X86::VPERMI2PSrrkz,      X86::VPERMI2PSrmkz,        0 },
3735     { X86::VPERMI2PDrrkz,      X86::VPERMI2PDrmkz,        0 },
3736     { X86::VPERMI2Qrrkz,       X86::VPERMI2Qrmkz,         0 },
3737     { X86::VPERMI2Wrrkz,       X86::VPERMI2Wrmkz,         0 },
3738     { X86::VPERMT2Brrkz,       X86::VPERMT2Brmkz,         0 },
3739     { X86::VPERMT2Drrkz,       X86::VPERMT2Drmkz,         0 },
3740     { X86::VPERMT2PSrrkz,      X86::VPERMT2PSrmkz,        0 },
3741     { X86::VPERMT2PDrrkz,      X86::VPERMT2PDrmkz,        0 },
3742     { X86::VPERMT2Qrrkz,       X86::VPERMT2Qrmkz,         0 },
3743     { X86::VPERMT2Wrrkz,       X86::VPERMT2Wrmkz,         0 },
3744     { X86::VPMADD52HUQZrkz,    X86::VPMADD52HUQZmkz,      0 },
3745     { X86::VPMADD52LUQZrkz,    X86::VPMADD52LUQZmkz,      0 },
3746     { X86::VPTERNLOGDZrrikz,   X86::VPTERNLOGDZrmikz,     0 },
3747     { X86::VPTERNLOGQZrrikz,   X86::VPTERNLOGQZrmikz,     0 },
3748 
3749     // 256-bit three source instructions with zero masking.
3750     { X86::VPERMI2B256rrkz,    X86::VPERMI2B256rmkz,      0 },
3751     { X86::VPERMI2D256rrkz,    X86::VPERMI2D256rmkz,      0 },
3752     { X86::VPERMI2PD256rrkz,   X86::VPERMI2PD256rmkz,     0 },
3753     { X86::VPERMI2PS256rrkz,   X86::VPERMI2PS256rmkz,     0 },
3754     { X86::VPERMI2Q256rrkz,    X86::VPERMI2Q256rmkz,      0 },
3755     { X86::VPERMI2W256rrkz,    X86::VPERMI2W256rmkz,      0 },
3756     { X86::VPERMT2B256rrkz,    X86::VPERMT2B256rmkz,      0 },
3757     { X86::VPERMT2D256rrkz,    X86::VPERMT2D256rmkz,      0 },
3758     { X86::VPERMT2PD256rrkz,   X86::VPERMT2PD256rmkz,     0 },
3759     { X86::VPERMT2PS256rrkz,   X86::VPERMT2PS256rmkz,     0 },
3760     { X86::VPERMT2Q256rrkz,    X86::VPERMT2Q256rmkz,      0 },
3761     { X86::VPERMT2W256rrkz,    X86::VPERMT2W256rmkz,      0 },
3762     { X86::VPMADD52HUQZ256rkz, X86::VPMADD52HUQZ256mkz,   0 },
3763     { X86::VPMADD52LUQZ256rkz, X86::VPMADD52LUQZ256mkz,   0 },
3764     { X86::VPTERNLOGDZ256rrikz,X86::VPTERNLOGDZ256rmikz,  0 },
3765     { X86::VPTERNLOGQZ256rrikz,X86::VPTERNLOGQZ256rmikz,  0 },
3766 
3767     // 128-bit three source instructions with zero masking.
3768     { X86::VPERMI2B128rrkz,    X86::VPERMI2B128rmkz,      0 },
3769     { X86::VPERMI2D128rrkz,    X86::VPERMI2D128rmkz,      0 },
3770     { X86::VPERMI2PD128rrkz,   X86::VPERMI2PD128rmkz,     0 },
3771     { X86::VPERMI2PS128rrkz,   X86::VPERMI2PS128rmkz,     0 },
3772     { X86::VPERMI2Q128rrkz,    X86::VPERMI2Q128rmkz,      0 },
3773     { X86::VPERMI2W128rrkz,    X86::VPERMI2W128rmkz,      0 },
3774     { X86::VPERMT2B128rrkz,    X86::VPERMT2B128rmkz,      0 },
3775     { X86::VPERMT2D128rrkz,    X86::VPERMT2D128rmkz,      0 },
3776     { X86::VPERMT2PD128rrkz,   X86::VPERMT2PD128rmkz,     0 },
3777     { X86::VPERMT2PS128rrkz,   X86::VPERMT2PS128rmkz,     0 },
3778     { X86::VPERMT2Q128rrkz,    X86::VPERMT2Q128rmkz,      0 },
3779     { X86::VPERMT2W128rrkz,    X86::VPERMT2W128rmkz,      0 },
3780     { X86::VPMADD52HUQZ128rkz, X86::VPMADD52HUQZ128mkz,   0 },
3781     { X86::VPMADD52LUQZ128rkz, X86::VPMADD52LUQZ128mkz,   0 },
3782     { X86::VPTERNLOGDZ128rrikz,X86::VPTERNLOGDZ128rmikz,  0 },
3783     { X86::VPTERNLOGQZ128rrikz,X86::VPTERNLOGQZ128rmikz,  0 },
3784   };
3785 
3786   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
3787     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3788                   Entry.RegOp, Entry.MemOp,
3789                   // Index 4, folded load
3790                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
3791   }
3792   for (I = X86InstrFMA3Info::rm_begin(); I != E; ++I) {
3793     if (I.getGroup()->isKMasked()) {
3794       // Intrinsics need to pass TB_NO_REVERSE.
3795       if (I.getGroup()->isIntrinsic()) {
3796         AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3797                       I.getRegOpcode(), I.getMemOpcode(),
3798                       TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD | TB_NO_REVERSE);
3799       } else {
3800         AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3801                       I.getRegOpcode(), I.getMemOpcode(),
3802                       TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD);
3803       }
3804     }
3805   }
3806 }
3807 
3808 void
3809 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
3810                             MemOp2RegOpTableType &M2RTable,
3811                             uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
3812   if ((Flags & TB_NO_FORWARD) == 0) {
3813     assert(!R2MTable.count(RegOp) && "Duplicate entry!");
3814     R2MTable[RegOp] = std::make_pair(MemOp, Flags);
3815   }
3816   if ((Flags & TB_NO_REVERSE) == 0) {
3817     assert(!M2RTable.count(MemOp) &&
3818          "Duplicated entries in unfolding maps?");
3819     M2RTable[MemOp] = std::make_pair(RegOp, Flags);
3820   }
3821 }
3822 
3823 bool
3824 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
3825                                     unsigned &SrcReg, unsigned &DstReg,
3826                                     unsigned &SubIdx) const {
3827   switch (MI.getOpcode()) {
3828   default: break;
3829   case X86::MOVSX16rr8:
3830   case X86::MOVZX16rr8:
3831   case X86::MOVSX32rr8:
3832   case X86::MOVZX32rr8:
3833   case X86::MOVSX64rr8:
3834     if (!Subtarget.is64Bit())
3835       // It's not always legal to reference the low 8-bit of the larger
3836       // register in 32-bit mode.
3837       return false;
3838     LLVM_FALLTHROUGH;
3839   case X86::MOVSX32rr16:
3840   case X86::MOVZX32rr16:
3841   case X86::MOVSX64rr16:
3842   case X86::MOVSX64rr32: {
3843     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
3844       // Be conservative.
3845       return false;
3846     SrcReg = MI.getOperand(1).getReg();
3847     DstReg = MI.getOperand(0).getReg();
3848     switch (MI.getOpcode()) {
3849     default: llvm_unreachable("Unreachable!");
3850     case X86::MOVSX16rr8:
3851     case X86::MOVZX16rr8:
3852     case X86::MOVSX32rr8:
3853     case X86::MOVZX32rr8:
3854     case X86::MOVSX64rr8:
3855       SubIdx = X86::sub_8bit;
3856       break;
3857     case X86::MOVSX32rr16:
3858     case X86::MOVZX32rr16:
3859     case X86::MOVSX64rr16:
3860       SubIdx = X86::sub_16bit;
3861       break;
3862     case X86::MOVSX64rr32:
3863       SubIdx = X86::sub_32bit;
3864       break;
3865     }
3866     return true;
3867   }
3868   }
3869   return false;
3870 }
3871 
3872 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
3873   const MachineFunction *MF = MI.getParent()->getParent();
3874   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
3875 
3876   if (isFrameInstr(MI)) {
3877     unsigned StackAlign = TFI->getStackAlignment();
3878     int SPAdj = alignTo(getFrameSize(MI), StackAlign);
3879     SPAdj -= getFrameAdjustment(MI);
3880     if (!isFrameSetup(MI))
3881       SPAdj = -SPAdj;
3882     return SPAdj;
3883   }
3884 
3885   // To know whether a call adjusts the stack, we need information
3886   // that is bound to the following ADJCALLSTACKUP pseudo.
3887   // Look for the next ADJCALLSTACKUP that follows the call.
3888   if (MI.isCall()) {
3889     const MachineBasicBlock *MBB = MI.getParent();
3890     auto I = ++MachineBasicBlock::const_iterator(MI);
3891     for (auto E = MBB->end(); I != E; ++I) {
3892       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
3893           I->isCall())
3894         break;
3895     }
3896 
3897     // If we could not find a frame destroy opcode, then it has already
3898     // been simplified, so we don't care.
3899     if (I->getOpcode() != getCallFrameDestroyOpcode())
3900       return 0;
3901 
3902     return -(I->getOperand(1).getImm());
3903   }
3904 
3905   // Currently handle only PUSHes we can reasonably expect to see
3906   // in call sequences
3907   switch (MI.getOpcode()) {
3908   default:
3909     return 0;
3910   case X86::PUSH32i8:
3911   case X86::PUSH32r:
3912   case X86::PUSH32rmm:
3913   case X86::PUSH32rmr:
3914   case X86::PUSHi32:
3915     return 4;
3916   case X86::PUSH64i8:
3917   case X86::PUSH64r:
3918   case X86::PUSH64rmm:
3919   case X86::PUSH64rmr:
3920   case X86::PUSH64i32:
3921     return 8;
3922   }
3923 }
3924 
3925 /// Return true and the FrameIndex if the specified
3926 /// operand and follow operands form a reference to the stack frame.
3927 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
3928                                   int &FrameIndex) const {
3929   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
3930       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
3931       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
3932       MI.getOperand(Op + X86::AddrDisp).isImm() &&
3933       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
3934       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
3935       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
3936     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
3937     return true;
3938   }
3939   return false;
3940 }
3941 
3942 static bool isFrameLoadOpcode(int Opcode) {
3943   switch (Opcode) {
3944   default:
3945     return false;
3946   case X86::MOV8rm:
3947   case X86::MOV16rm:
3948   case X86::MOV32rm:
3949   case X86::MOV64rm:
3950   case X86::LD_Fp64m:
3951   case X86::MOVSSrm:
3952   case X86::MOVSDrm:
3953   case X86::MOVAPSrm:
3954   case X86::MOVUPSrm:
3955   case X86::MOVAPDrm:
3956   case X86::MOVUPDrm:
3957   case X86::MOVDQArm:
3958   case X86::MOVDQUrm:
3959   case X86::VMOVSSrm:
3960   case X86::VMOVSDrm:
3961   case X86::VMOVAPSrm:
3962   case X86::VMOVUPSrm:
3963   case X86::VMOVAPDrm:
3964   case X86::VMOVUPDrm:
3965   case X86::VMOVDQArm:
3966   case X86::VMOVDQUrm:
3967   case X86::VMOVUPSYrm:
3968   case X86::VMOVAPSYrm:
3969   case X86::VMOVUPDYrm:
3970   case X86::VMOVAPDYrm:
3971   case X86::VMOVDQUYrm:
3972   case X86::VMOVDQAYrm:
3973   case X86::MMX_MOVD64rm:
3974   case X86::MMX_MOVQ64rm:
3975   case X86::VMOVSSZrm:
3976   case X86::VMOVSDZrm:
3977   case X86::VMOVAPSZrm:
3978   case X86::VMOVAPSZ128rm:
3979   case X86::VMOVAPSZ256rm:
3980   case X86::VMOVAPSZ128rm_NOVLX:
3981   case X86::VMOVAPSZ256rm_NOVLX:
3982   case X86::VMOVUPSZrm:
3983   case X86::VMOVUPSZ128rm:
3984   case X86::VMOVUPSZ256rm:
3985   case X86::VMOVUPSZ128rm_NOVLX:
3986   case X86::VMOVUPSZ256rm_NOVLX:
3987   case X86::VMOVAPDZrm:
3988   case X86::VMOVAPDZ128rm:
3989   case X86::VMOVAPDZ256rm:
3990   case X86::VMOVUPDZrm:
3991   case X86::VMOVUPDZ128rm:
3992   case X86::VMOVUPDZ256rm:
3993   case X86::VMOVDQA32Zrm:
3994   case X86::VMOVDQA32Z128rm:
3995   case X86::VMOVDQA32Z256rm:
3996   case X86::VMOVDQU32Zrm:
3997   case X86::VMOVDQU32Z128rm:
3998   case X86::VMOVDQU32Z256rm:
3999   case X86::VMOVDQA64Zrm:
4000   case X86::VMOVDQA64Z128rm:
4001   case X86::VMOVDQA64Z256rm:
4002   case X86::VMOVDQU64Zrm:
4003   case X86::VMOVDQU64Z128rm:
4004   case X86::VMOVDQU64Z256rm:
4005   case X86::VMOVDQU8Zrm:
4006   case X86::VMOVDQU8Z128rm:
4007   case X86::VMOVDQU8Z256rm:
4008   case X86::VMOVDQU16Zrm:
4009   case X86::VMOVDQU16Z128rm:
4010   case X86::VMOVDQU16Z256rm:
4011   case X86::KMOVBkm:
4012   case X86::KMOVWkm:
4013   case X86::KMOVDkm:
4014   case X86::KMOVQkm:
4015     return true;
4016   }
4017 }
4018 
4019 static bool isFrameStoreOpcode(int Opcode) {
4020   switch (Opcode) {
4021   default: break;
4022   case X86::MOV8mr:
4023   case X86::MOV16mr:
4024   case X86::MOV32mr:
4025   case X86::MOV64mr:
4026   case X86::ST_FpP64m:
4027   case X86::MOVSSmr:
4028   case X86::MOVSDmr:
4029   case X86::MOVAPSmr:
4030   case X86::MOVUPSmr:
4031   case X86::MOVAPDmr:
4032   case X86::MOVUPDmr:
4033   case X86::MOVDQAmr:
4034   case X86::MOVDQUmr:
4035   case X86::VMOVSSmr:
4036   case X86::VMOVSDmr:
4037   case X86::VMOVAPSmr:
4038   case X86::VMOVUPSmr:
4039   case X86::VMOVAPDmr:
4040   case X86::VMOVUPDmr:
4041   case X86::VMOVDQAmr:
4042   case X86::VMOVDQUmr:
4043   case X86::VMOVUPSYmr:
4044   case X86::VMOVAPSYmr:
4045   case X86::VMOVUPDYmr:
4046   case X86::VMOVAPDYmr:
4047   case X86::VMOVDQUYmr:
4048   case X86::VMOVDQAYmr:
4049   case X86::VMOVSSZmr:
4050   case X86::VMOVSDZmr:
4051   case X86::VMOVUPSZmr:
4052   case X86::VMOVUPSZ128mr:
4053   case X86::VMOVUPSZ256mr:
4054   case X86::VMOVUPSZ128mr_NOVLX:
4055   case X86::VMOVUPSZ256mr_NOVLX:
4056   case X86::VMOVAPSZmr:
4057   case X86::VMOVAPSZ128mr:
4058   case X86::VMOVAPSZ256mr:
4059   case X86::VMOVAPSZ128mr_NOVLX:
4060   case X86::VMOVAPSZ256mr_NOVLX:
4061   case X86::VMOVUPDZmr:
4062   case X86::VMOVUPDZ128mr:
4063   case X86::VMOVUPDZ256mr:
4064   case X86::VMOVAPDZmr:
4065   case X86::VMOVAPDZ128mr:
4066   case X86::VMOVAPDZ256mr:
4067   case X86::VMOVDQA32Zmr:
4068   case X86::VMOVDQA32Z128mr:
4069   case X86::VMOVDQA32Z256mr:
4070   case X86::VMOVDQU32Zmr:
4071   case X86::VMOVDQU32Z128mr:
4072   case X86::VMOVDQU32Z256mr:
4073   case X86::VMOVDQA64Zmr:
4074   case X86::VMOVDQA64Z128mr:
4075   case X86::VMOVDQA64Z256mr:
4076   case X86::VMOVDQU64Zmr:
4077   case X86::VMOVDQU64Z128mr:
4078   case X86::VMOVDQU64Z256mr:
4079   case X86::VMOVDQU8Zmr:
4080   case X86::VMOVDQU8Z128mr:
4081   case X86::VMOVDQU8Z256mr:
4082   case X86::VMOVDQU16Zmr:
4083   case X86::VMOVDQU16Z128mr:
4084   case X86::VMOVDQU16Z256mr:
4085   case X86::MMX_MOVD64mr:
4086   case X86::MMX_MOVQ64mr:
4087   case X86::MMX_MOVNTQmr:
4088   case X86::KMOVBmk:
4089   case X86::KMOVWmk:
4090   case X86::KMOVDmk:
4091   case X86::KMOVQmk:
4092     return true;
4093   }
4094   return false;
4095 }
4096 
4097 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
4098                                            int &FrameIndex) const {
4099   if (isFrameLoadOpcode(MI.getOpcode()))
4100     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
4101       return MI.getOperand(0).getReg();
4102   return 0;
4103 }
4104 
4105 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
4106                                                  int &FrameIndex) const {
4107   if (isFrameLoadOpcode(MI.getOpcode())) {
4108     unsigned Reg;
4109     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
4110       return Reg;
4111     // Check for post-frame index elimination operations
4112     const MachineMemOperand *Dummy;
4113     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
4114   }
4115   return 0;
4116 }
4117 
4118 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
4119                                           int &FrameIndex) const {
4120   if (isFrameStoreOpcode(MI.getOpcode()))
4121     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
4122         isFrameOperand(MI, 0, FrameIndex))
4123       return MI.getOperand(X86::AddrNumOperands).getReg();
4124   return 0;
4125 }
4126 
4127 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
4128                                                 int &FrameIndex) const {
4129   if (isFrameStoreOpcode(MI.getOpcode())) {
4130     unsigned Reg;
4131     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
4132       return Reg;
4133     // Check for post-frame index elimination operations
4134     const MachineMemOperand *Dummy;
4135     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
4136   }
4137   return 0;
4138 }
4139 
4140 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
4141 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
4142   // Don't waste compile time scanning use-def chains of physregs.
4143   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
4144     return false;
4145   bool isPICBase = false;
4146   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
4147          E = MRI.def_instr_end(); I != E; ++I) {
4148     MachineInstr *DefMI = &*I;
4149     if (DefMI->getOpcode() != X86::MOVPC32r)
4150       return false;
4151     assert(!isPICBase && "More than one PIC base?");
4152     isPICBase = true;
4153   }
4154   return isPICBase;
4155 }
4156 
4157 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
4158                                                      AliasAnalysis *AA) const {
4159   switch (MI.getOpcode()) {
4160   default: break;
4161   case X86::MOV8rm:
4162   case X86::MOV8rm_NOREX:
4163   case X86::MOV16rm:
4164   case X86::MOV32rm:
4165   case X86::MOV64rm:
4166   case X86::LD_Fp64m:
4167   case X86::MOVSSrm:
4168   case X86::MOVSDrm:
4169   case X86::MOVAPSrm:
4170   case X86::MOVUPSrm:
4171   case X86::MOVAPDrm:
4172   case X86::MOVUPDrm:
4173   case X86::MOVDQArm:
4174   case X86::MOVDQUrm:
4175   case X86::VMOVSSrm:
4176   case X86::VMOVSDrm:
4177   case X86::VMOVAPSrm:
4178   case X86::VMOVUPSrm:
4179   case X86::VMOVAPDrm:
4180   case X86::VMOVUPDrm:
4181   case X86::VMOVDQArm:
4182   case X86::VMOVDQUrm:
4183   case X86::VMOVAPSYrm:
4184   case X86::VMOVUPSYrm:
4185   case X86::VMOVAPDYrm:
4186   case X86::VMOVUPDYrm:
4187   case X86::VMOVDQAYrm:
4188   case X86::VMOVDQUYrm:
4189   case X86::MMX_MOVD64rm:
4190   case X86::MMX_MOVQ64rm:
4191   // AVX-512
4192   case X86::VMOVSSZrm:
4193   case X86::VMOVSDZrm:
4194   case X86::VMOVAPDZ128rm:
4195   case X86::VMOVAPDZ256rm:
4196   case X86::VMOVAPDZrm:
4197   case X86::VMOVAPSZ128rm:
4198   case X86::VMOVAPSZ256rm:
4199   case X86::VMOVAPSZ128rm_NOVLX:
4200   case X86::VMOVAPSZ256rm_NOVLX:
4201   case X86::VMOVAPSZrm:
4202   case X86::VMOVDQA32Z128rm:
4203   case X86::VMOVDQA32Z256rm:
4204   case X86::VMOVDQA32Zrm:
4205   case X86::VMOVDQA64Z128rm:
4206   case X86::VMOVDQA64Z256rm:
4207   case X86::VMOVDQA64Zrm:
4208   case X86::VMOVDQU16Z128rm:
4209   case X86::VMOVDQU16Z256rm:
4210   case X86::VMOVDQU16Zrm:
4211   case X86::VMOVDQU32Z128rm:
4212   case X86::VMOVDQU32Z256rm:
4213   case X86::VMOVDQU32Zrm:
4214   case X86::VMOVDQU64Z128rm:
4215   case X86::VMOVDQU64Z256rm:
4216   case X86::VMOVDQU64Zrm:
4217   case X86::VMOVDQU8Z128rm:
4218   case X86::VMOVDQU8Z256rm:
4219   case X86::VMOVDQU8Zrm:
4220   case X86::VMOVUPDZ128rm:
4221   case X86::VMOVUPDZ256rm:
4222   case X86::VMOVUPDZrm:
4223   case X86::VMOVUPSZ128rm:
4224   case X86::VMOVUPSZ256rm:
4225   case X86::VMOVUPSZ128rm_NOVLX:
4226   case X86::VMOVUPSZ256rm_NOVLX:
4227   case X86::VMOVUPSZrm: {
4228     // Loads from constant pools are trivially rematerializable.
4229     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
4230         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
4231         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
4232         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
4233         MI.isDereferenceableInvariantLoad(AA)) {
4234       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
4235       if (BaseReg == 0 || BaseReg == X86::RIP)
4236         return true;
4237       // Allow re-materialization of PIC load.
4238       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
4239         return false;
4240       const MachineFunction &MF = *MI.getParent()->getParent();
4241       const MachineRegisterInfo &MRI = MF.getRegInfo();
4242       return regIsPICBase(BaseReg, MRI);
4243     }
4244     return false;
4245   }
4246 
4247   case X86::LEA32r:
4248   case X86::LEA64r: {
4249     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
4250         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
4251         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
4252         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
4253       // lea fi#, lea GV, etc. are all rematerializable.
4254       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
4255         return true;
4256       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
4257       if (BaseReg == 0)
4258         return true;
4259       // Allow re-materialization of lea PICBase + x.
4260       const MachineFunction &MF = *MI.getParent()->getParent();
4261       const MachineRegisterInfo &MRI = MF.getRegInfo();
4262       return regIsPICBase(BaseReg, MRI);
4263     }
4264     return false;
4265   }
4266   }
4267 
4268   // All other instructions marked M_REMATERIALIZABLE are always trivially
4269   // rematerializable.
4270   return true;
4271 }
4272 
4273 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
4274                                          MachineBasicBlock::iterator I) const {
4275   MachineBasicBlock::iterator E = MBB.end();
4276 
4277   // For compile time consideration, if we are not able to determine the
4278   // safety after visiting 4 instructions in each direction, we will assume
4279   // it's not safe.
4280   MachineBasicBlock::iterator Iter = I;
4281   for (unsigned i = 0; Iter != E && i < 4; ++i) {
4282     bool SeenDef = false;
4283     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
4284       MachineOperand &MO = Iter->getOperand(j);
4285       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
4286         SeenDef = true;
4287       if (!MO.isReg())
4288         continue;
4289       if (MO.getReg() == X86::EFLAGS) {
4290         if (MO.isUse())
4291           return false;
4292         SeenDef = true;
4293       }
4294     }
4295 
4296     if (SeenDef)
4297       // This instruction defines EFLAGS, no need to look any further.
4298       return true;
4299     ++Iter;
4300     // Skip over DBG_VALUE.
4301     while (Iter != E && Iter->isDebugValue())
4302       ++Iter;
4303   }
4304 
4305   // It is safe to clobber EFLAGS at the end of a block of no successor has it
4306   // live in.
4307   if (Iter == E) {
4308     for (MachineBasicBlock *S : MBB.successors())
4309       if (S->isLiveIn(X86::EFLAGS))
4310         return false;
4311     return true;
4312   }
4313 
4314   MachineBasicBlock::iterator B = MBB.begin();
4315   Iter = I;
4316   for (unsigned i = 0; i < 4; ++i) {
4317     // If we make it to the beginning of the block, it's safe to clobber
4318     // EFLAGS iff EFLAGS is not live-in.
4319     if (Iter == B)
4320       return !MBB.isLiveIn(X86::EFLAGS);
4321 
4322     --Iter;
4323     // Skip over DBG_VALUE.
4324     while (Iter != B && Iter->isDebugValue())
4325       --Iter;
4326 
4327     bool SawKill = false;
4328     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
4329       MachineOperand &MO = Iter->getOperand(j);
4330       // A register mask may clobber EFLAGS, but we should still look for a
4331       // live EFLAGS def.
4332       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
4333         SawKill = true;
4334       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
4335         if (MO.isDef()) return MO.isDead();
4336         if (MO.isKill()) SawKill = true;
4337       }
4338     }
4339 
4340     if (SawKill)
4341       // This instruction kills EFLAGS and doesn't redefine it, so
4342       // there's no need to look further.
4343       return true;
4344   }
4345 
4346   // Conservative answer.
4347   return false;
4348 }
4349 
4350 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
4351                                  MachineBasicBlock::iterator I,
4352                                  unsigned DestReg, unsigned SubIdx,
4353                                  const MachineInstr &Orig,
4354                                  const TargetRegisterInfo &TRI) const {
4355   bool ClobbersEFLAGS = false;
4356   for (const MachineOperand &MO : Orig.operands()) {
4357     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4358       ClobbersEFLAGS = true;
4359       break;
4360     }
4361   }
4362 
4363   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
4364     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
4365     // effects.
4366     int Value;
4367     switch (Orig.getOpcode()) {
4368     case X86::MOV32r0:  Value = 0; break;
4369     case X86::MOV32r1:  Value = 1; break;
4370     case X86::MOV32r_1: Value = -1; break;
4371     default:
4372       llvm_unreachable("Unexpected instruction!");
4373     }
4374 
4375     const DebugLoc &DL = Orig.getDebugLoc();
4376     BuildMI(MBB, I, DL, get(X86::MOV32ri))
4377         .add(Orig.getOperand(0))
4378         .addImm(Value);
4379   } else {
4380     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
4381     MBB.insert(I, MI);
4382   }
4383 
4384   MachineInstr &NewMI = *std::prev(I);
4385   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
4386 }
4387 
4388 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
4389 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
4390   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4391     MachineOperand &MO = MI.getOperand(i);
4392     if (MO.isReg() && MO.isDef() &&
4393         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
4394       return true;
4395     }
4396   }
4397   return false;
4398 }
4399 
4400 /// Check whether the shift count for a machine operand is non-zero.
4401 inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
4402                                               unsigned ShiftAmtOperandIdx) {
4403   // The shift count is six bits with the REX.W prefix and five bits without.
4404   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
4405   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
4406   return Imm & ShiftCountMask;
4407 }
4408 
4409 /// Check whether the given shift count is appropriate
4410 /// can be represented by a LEA instruction.
4411 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
4412   // Left shift instructions can be transformed into load-effective-address
4413   // instructions if we can encode them appropriately.
4414   // A LEA instruction utilizes a SIB byte to encode its scale factor.
4415   // The SIB.scale field is two bits wide which means that we can encode any
4416   // shift amount less than 4.
4417   return ShAmt < 4 && ShAmt > 0;
4418 }
4419 
4420 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
4421                                   unsigned Opc, bool AllowSP, unsigned &NewSrc,
4422                                   bool &isKill, bool &isUndef,
4423                                   MachineOperand &ImplicitOp,
4424                                   LiveVariables *LV) const {
4425   MachineFunction &MF = *MI.getParent()->getParent();
4426   const TargetRegisterClass *RC;
4427   if (AllowSP) {
4428     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
4429   } else {
4430     RC = Opc != X86::LEA32r ?
4431       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
4432   }
4433   unsigned SrcReg = Src.getReg();
4434 
4435   // For both LEA64 and LEA32 the register already has essentially the right
4436   // type (32-bit or 64-bit) we may just need to forbid SP.
4437   if (Opc != X86::LEA64_32r) {
4438     NewSrc = SrcReg;
4439     isKill = Src.isKill();
4440     isUndef = Src.isUndef();
4441 
4442     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
4443         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
4444       return false;
4445 
4446     return true;
4447   }
4448 
4449   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
4450   // another we need to add 64-bit registers to the final MI.
4451   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
4452     ImplicitOp = Src;
4453     ImplicitOp.setImplicit();
4454 
4455     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
4456     isKill = Src.isKill();
4457     isUndef = Src.isUndef();
4458   } else {
4459     // Virtual register of the wrong class, we have to create a temporary 64-bit
4460     // vreg to feed into the LEA.
4461     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
4462     MachineInstr *Copy =
4463         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4464             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
4465             .add(Src);
4466 
4467     // Which is obviously going to be dead after we're done with it.
4468     isKill = true;
4469     isUndef = false;
4470 
4471     if (LV)
4472       LV->replaceKillInstruction(SrcReg, MI, *Copy);
4473   }
4474 
4475   // We've set all the parameters without issue.
4476   return true;
4477 }
4478 
4479 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
4480 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
4481 /// truncating back down to a 16-bit subregister.
4482 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
4483     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
4484     LiveVariables *LV) const {
4485   MachineBasicBlock::iterator MBBI = MI.getIterator();
4486   unsigned Dest = MI.getOperand(0).getReg();
4487   unsigned Src = MI.getOperand(1).getReg();
4488   bool isDead = MI.getOperand(0).isDead();
4489   bool isKill = MI.getOperand(1).isKill();
4490 
4491   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
4492   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
4493   unsigned Opc, leaInReg;
4494   if (Subtarget.is64Bit()) {
4495     Opc = X86::LEA64_32r;
4496     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
4497   } else {
4498     Opc = X86::LEA32r;
4499     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4500   }
4501 
4502   // Build and insert into an implicit UNDEF value. This is OK because
4503   // well be shifting and then extracting the lower 16-bits.
4504   // This has the potential to cause partial register stall. e.g.
4505   //   movw    (%rbp,%rcx,2), %dx
4506   //   leal    -65(%rdx), %esi
4507   // But testing has shown this *does* help performance in 64-bit mode (at
4508   // least on modern x86 machines).
4509   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
4510   MachineInstr *InsMI =
4511       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4512           .addReg(leaInReg, RegState::Define, X86::sub_16bit)
4513           .addReg(Src, getKillRegState(isKill));
4514 
4515   MachineInstrBuilder MIB =
4516       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
4517   switch (MIOpc) {
4518   default: llvm_unreachable("Unreachable!");
4519   case X86::SHL16ri: {
4520     unsigned ShAmt = MI.getOperand(2).getImm();
4521     MIB.addReg(0).addImm(1ULL << ShAmt)
4522        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
4523     break;
4524   }
4525   case X86::INC16r:
4526     addRegOffset(MIB, leaInReg, true, 1);
4527     break;
4528   case X86::DEC16r:
4529     addRegOffset(MIB, leaInReg, true, -1);
4530     break;
4531   case X86::ADD16ri:
4532   case X86::ADD16ri8:
4533   case X86::ADD16ri_DB:
4534   case X86::ADD16ri8_DB:
4535     addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
4536     break;
4537   case X86::ADD16rr:
4538   case X86::ADD16rr_DB: {
4539     unsigned Src2 = MI.getOperand(2).getReg();
4540     bool isKill2 = MI.getOperand(2).isKill();
4541     unsigned leaInReg2 = 0;
4542     MachineInstr *InsMI2 = nullptr;
4543     if (Src == Src2) {
4544       // ADD16rr killed %reg1028, %reg1028
4545       // just a single insert_subreg.
4546       addRegReg(MIB, leaInReg, true, leaInReg, false);
4547     } else {
4548       if (Subtarget.is64Bit())
4549         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
4550       else
4551         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4552       // Build and insert into an implicit UNDEF value. This is OK because
4553       // well be shifting and then extracting the lower 16-bits.
4554       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
4555       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
4556                    .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
4557                    .addReg(Src2, getKillRegState(isKill2));
4558       addRegReg(MIB, leaInReg, true, leaInReg2, true);
4559     }
4560     if (LV && isKill2 && InsMI2)
4561       LV->replaceKillInstruction(Src2, MI, *InsMI2);
4562     break;
4563   }
4564   }
4565 
4566   MachineInstr *NewMI = MIB;
4567   MachineInstr *ExtMI =
4568       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4569           .addReg(Dest, RegState::Define | getDeadRegState(isDead))
4570           .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
4571 
4572   if (LV) {
4573     // Update live variables
4574     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
4575     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
4576     if (isKill)
4577       LV->replaceKillInstruction(Src, MI, *InsMI);
4578     if (isDead)
4579       LV->replaceKillInstruction(Dest, MI, *ExtMI);
4580   }
4581 
4582   return ExtMI;
4583 }
4584 
4585 /// This method must be implemented by targets that
4586 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
4587 /// may be able to convert a two-address instruction into a true
4588 /// three-address instruction on demand.  This allows the X86 target (for
4589 /// example) to convert ADD and SHL instructions into LEA instructions if they
4590 /// would require register copies due to two-addressness.
4591 ///
4592 /// This method returns a null pointer if the transformation cannot be
4593 /// performed, otherwise it returns the new instruction.
4594 ///
4595 MachineInstr *
4596 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
4597                                     MachineInstr &MI, LiveVariables *LV) const {
4598   // The following opcodes also sets the condition code register(s). Only
4599   // convert them to equivalent lea if the condition code register def's
4600   // are dead!
4601   if (hasLiveCondCodeDef(MI))
4602     return nullptr;
4603 
4604   MachineFunction &MF = *MI.getParent()->getParent();
4605   // All instructions input are two-addr instructions.  Get the known operands.
4606   const MachineOperand &Dest = MI.getOperand(0);
4607   const MachineOperand &Src = MI.getOperand(1);
4608 
4609   MachineInstr *NewMI = nullptr;
4610   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
4611   // we have better subtarget support, enable the 16-bit LEA generation here.
4612   // 16-bit LEA is also slow on Core2.
4613   bool DisableLEA16 = true;
4614   bool is64Bit = Subtarget.is64Bit();
4615 
4616   unsigned MIOpc = MI.getOpcode();
4617   switch (MIOpc) {
4618   default: return nullptr;
4619   case X86::SHL64ri: {
4620     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
4621     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4622     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4623 
4624     // LEA can't handle RSP.
4625     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
4626         !MF.getRegInfo().constrainRegClass(Src.getReg(),
4627                                            &X86::GR64_NOSPRegClass))
4628       return nullptr;
4629 
4630     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
4631                 .add(Dest)
4632                 .addReg(0)
4633                 .addImm(1ULL << ShAmt)
4634                 .add(Src)
4635                 .addImm(0)
4636                 .addReg(0);
4637     break;
4638   }
4639   case X86::SHL32ri: {
4640     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
4641     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4642     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4643 
4644     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4645 
4646     // LEA can't handle ESP.
4647     bool isKill, isUndef;
4648     unsigned SrcReg;
4649     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4650     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4651                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4652       return nullptr;
4653 
4654     MachineInstrBuilder MIB =
4655         BuildMI(MF, MI.getDebugLoc(), get(Opc))
4656             .add(Dest)
4657             .addReg(0)
4658             .addImm(1ULL << ShAmt)
4659             .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
4660             .addImm(0)
4661             .addReg(0);
4662     if (ImplicitOp.getReg() != 0)
4663       MIB.add(ImplicitOp);
4664     NewMI = MIB;
4665 
4666     break;
4667   }
4668   case X86::SHL16ri: {
4669     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
4670     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4671     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4672 
4673     if (DisableLEA16)
4674       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4675                      : nullptr;
4676     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
4677                 .add(Dest)
4678                 .addReg(0)
4679                 .addImm(1ULL << ShAmt)
4680                 .add(Src)
4681                 .addImm(0)
4682                 .addReg(0);
4683     break;
4684   }
4685   case X86::INC64r:
4686   case X86::INC32r: {
4687     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
4688     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
4689       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
4690     bool isKill, isUndef;
4691     unsigned SrcReg;
4692     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4693     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4694                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4695       return nullptr;
4696 
4697     MachineInstrBuilder MIB =
4698         BuildMI(MF, MI.getDebugLoc(), get(Opc))
4699             .add(Dest)
4700             .addReg(SrcReg,
4701                     getKillRegState(isKill) | getUndefRegState(isUndef));
4702     if (ImplicitOp.getReg() != 0)
4703       MIB.add(ImplicitOp);
4704 
4705     NewMI = addOffset(MIB, 1);
4706     break;
4707   }
4708   case X86::INC16r:
4709     if (DisableLEA16)
4710       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4711                      : nullptr;
4712     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
4713     NewMI = addOffset(
4714         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), 1);
4715     break;
4716   case X86::DEC64r:
4717   case X86::DEC32r: {
4718     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
4719     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
4720       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
4721 
4722     bool isKill, isUndef;
4723     unsigned SrcReg;
4724     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4725     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4726                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4727       return nullptr;
4728 
4729     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4730                                   .add(Dest)
4731                                   .addReg(SrcReg, getUndefRegState(isUndef) |
4732                                                       getKillRegState(isKill));
4733     if (ImplicitOp.getReg() != 0)
4734       MIB.add(ImplicitOp);
4735 
4736     NewMI = addOffset(MIB, -1);
4737 
4738     break;
4739   }
4740   case X86::DEC16r:
4741     if (DisableLEA16)
4742       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4743                      : nullptr;
4744     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
4745     NewMI = addOffset(
4746         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), -1);
4747     break;
4748   case X86::ADD64rr:
4749   case X86::ADD64rr_DB:
4750   case X86::ADD32rr:
4751   case X86::ADD32rr_DB: {
4752     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4753     unsigned Opc;
4754     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
4755       Opc = X86::LEA64r;
4756     else
4757       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4758 
4759     bool isKill, isUndef;
4760     unsigned SrcReg;
4761     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4762     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
4763                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4764       return nullptr;
4765 
4766     const MachineOperand &Src2 = MI.getOperand(2);
4767     bool isKill2, isUndef2;
4768     unsigned SrcReg2;
4769     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
4770     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
4771                         SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
4772       return nullptr;
4773 
4774     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
4775     if (ImplicitOp.getReg() != 0)
4776       MIB.add(ImplicitOp);
4777     if (ImplicitOp2.getReg() != 0)
4778       MIB.add(ImplicitOp2);
4779 
4780     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
4781 
4782     // Preserve undefness of the operands.
4783     NewMI->getOperand(1).setIsUndef(isUndef);
4784     NewMI->getOperand(3).setIsUndef(isUndef2);
4785 
4786     if (LV && Src2.isKill())
4787       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
4788     break;
4789   }
4790   case X86::ADD16rr:
4791   case X86::ADD16rr_DB: {
4792     if (DisableLEA16)
4793       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4794                      : nullptr;
4795     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4796     unsigned Src2 = MI.getOperand(2).getReg();
4797     bool isKill2 = MI.getOperand(2).isKill();
4798     NewMI = addRegReg(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest),
4799                       Src.getReg(), Src.isKill(), Src2, isKill2);
4800 
4801     // Preserve undefness of the operands.
4802     bool isUndef = MI.getOperand(1).isUndef();
4803     bool isUndef2 = MI.getOperand(2).isUndef();
4804     NewMI->getOperand(1).setIsUndef(isUndef);
4805     NewMI->getOperand(3).setIsUndef(isUndef2);
4806 
4807     if (LV && isKill2)
4808       LV->replaceKillInstruction(Src2, MI, *NewMI);
4809     break;
4810   }
4811   case X86::ADD64ri32:
4812   case X86::ADD64ri8:
4813   case X86::ADD64ri32_DB:
4814   case X86::ADD64ri8_DB:
4815     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4816     NewMI = addOffset(
4817         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
4818         MI.getOperand(2));
4819     break;
4820   case X86::ADD32ri:
4821   case X86::ADD32ri8:
4822   case X86::ADD32ri_DB:
4823   case X86::ADD32ri8_DB: {
4824     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4825     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4826 
4827     bool isKill, isUndef;
4828     unsigned SrcReg;
4829     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4830     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
4831                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4832       return nullptr;
4833 
4834     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4835                                   .add(Dest)
4836                                   .addReg(SrcReg, getUndefRegState(isUndef) |
4837                                                       getKillRegState(isKill));
4838     if (ImplicitOp.getReg() != 0)
4839       MIB.add(ImplicitOp);
4840 
4841     NewMI = addOffset(MIB, MI.getOperand(2));
4842     break;
4843   }
4844   case X86::ADD16ri:
4845   case X86::ADD16ri8:
4846   case X86::ADD16ri_DB:
4847   case X86::ADD16ri8_DB:
4848     if (DisableLEA16)
4849       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4850                      : nullptr;
4851     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4852     NewMI = addOffset(
4853         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src),
4854         MI.getOperand(2));
4855     break;
4856 
4857   case X86::VMOVDQU8Z128rmk:
4858   case X86::VMOVDQU8Z256rmk:
4859   case X86::VMOVDQU8Zrmk:
4860   case X86::VMOVDQU16Z128rmk:
4861   case X86::VMOVDQU16Z256rmk:
4862   case X86::VMOVDQU16Zrmk:
4863   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
4864   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
4865   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
4866   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
4867   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
4868   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
4869   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
4870   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
4871   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
4872   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
4873   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
4874   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk: {
4875     unsigned Opc;
4876     switch (MIOpc) {
4877     default: llvm_unreachable("Unreachable!");
4878     case X86::VMOVDQU8Z128rmk:  Opc = X86::VPBLENDMBZ128rmk; break;
4879     case X86::VMOVDQU8Z256rmk:  Opc = X86::VPBLENDMBZ256rmk; break;
4880     case X86::VMOVDQU8Zrmk:     Opc = X86::VPBLENDMBZrmk;    break;
4881     case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
4882     case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
4883     case X86::VMOVDQU16Zrmk:    Opc = X86::VPBLENDMWZrmk;    break;
4884     case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
4885     case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
4886     case X86::VMOVDQU32Zrmk:    Opc = X86::VPBLENDMDZrmk;    break;
4887     case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
4888     case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
4889     case X86::VMOVDQU64Zrmk:    Opc = X86::VPBLENDMQZrmk;    break;
4890     case X86::VMOVUPDZ128rmk:   Opc = X86::VBLENDMPDZ128rmk; break;
4891     case X86::VMOVUPDZ256rmk:   Opc = X86::VBLENDMPDZ256rmk; break;
4892     case X86::VMOVUPDZrmk:      Opc = X86::VBLENDMPDZrmk;    break;
4893     case X86::VMOVUPSZ128rmk:   Opc = X86::VBLENDMPSZ128rmk; break;
4894     case X86::VMOVUPSZ256rmk:   Opc = X86::VBLENDMPSZ256rmk; break;
4895     case X86::VMOVUPSZrmk:      Opc = X86::VBLENDMPSZrmk;    break;
4896     case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
4897     case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
4898     case X86::VMOVDQA32Zrmk:    Opc = X86::VPBLENDMDZrmk;    break;
4899     case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
4900     case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
4901     case X86::VMOVDQA64Zrmk:    Opc = X86::VPBLENDMQZrmk;    break;
4902     case X86::VMOVAPDZ128rmk:   Opc = X86::VBLENDMPDZ128rmk; break;
4903     case X86::VMOVAPDZ256rmk:   Opc = X86::VBLENDMPDZ256rmk; break;
4904     case X86::VMOVAPDZrmk:      Opc = X86::VBLENDMPDZrmk;    break;
4905     case X86::VMOVAPSZ128rmk:   Opc = X86::VBLENDMPSZ128rmk; break;
4906     case X86::VMOVAPSZ256rmk:   Opc = X86::VBLENDMPSZ256rmk; break;
4907     case X86::VMOVAPSZrmk:      Opc = X86::VBLENDMPSZrmk;    break;
4908     }
4909 
4910     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4911               .add(Dest)
4912               .add(MI.getOperand(2))
4913               .add(Src)
4914               .add(MI.getOperand(3))
4915               .add(MI.getOperand(4))
4916               .add(MI.getOperand(5))
4917               .add(MI.getOperand(6))
4918               .add(MI.getOperand(7));
4919     break;
4920   }
4921   case X86::VMOVDQU8Z128rrk:
4922   case X86::VMOVDQU8Z256rrk:
4923   case X86::VMOVDQU8Zrrk:
4924   case X86::VMOVDQU16Z128rrk:
4925   case X86::VMOVDQU16Z256rrk:
4926   case X86::VMOVDQU16Zrrk:
4927   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
4928   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
4929   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
4930   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
4931   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
4932   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
4933   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
4934   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
4935   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
4936   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
4937   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
4938   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
4939     unsigned Opc;
4940     switch (MIOpc) {
4941     default: llvm_unreachable("Unreachable!");
4942     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
4943     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
4944     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
4945     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
4946     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
4947     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
4948     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
4949     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
4950     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
4951     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
4952     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
4953     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
4954     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
4955     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
4956     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
4957     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
4958     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
4959     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
4960     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
4961     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
4962     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
4963     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
4964     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
4965     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
4966     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
4967     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
4968     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
4969     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
4970     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
4971     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
4972     }
4973 
4974     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4975               .add(Dest)
4976               .add(MI.getOperand(2))
4977               .add(Src)
4978               .add(MI.getOperand(3));
4979     break;
4980   }
4981   }
4982 
4983   if (!NewMI) return nullptr;
4984 
4985   if (LV) {  // Update live variables
4986     if (Src.isKill())
4987       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
4988     if (Dest.isDead())
4989       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
4990   }
4991 
4992   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
4993   return NewMI;
4994 }
4995 
4996 /// This determines which of three possible cases of a three source commute
4997 /// the source indexes correspond to taking into account any mask operands.
4998 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
4999 /// possible.
5000 /// Case 0 - Possible to commute the first and second operands.
5001 /// Case 1 - Possible to commute the first and third operands.
5002 /// Case 2 - Possible to commute the second and third operands.
5003 static int getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
5004                                   unsigned SrcOpIdx2) {
5005   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
5006   if (SrcOpIdx1 > SrcOpIdx2)
5007     std::swap(SrcOpIdx1, SrcOpIdx2);
5008 
5009   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
5010   if (X86II::isKMasked(TSFlags)) {
5011     // The k-mask operand cannot be commuted.
5012     if (SrcOpIdx1 == 2)
5013       return -1;
5014 
5015     // For k-zero-masked operations it is Ok to commute the first vector
5016     // operand.
5017     // For regular k-masked operations a conservative choice is done as the
5018     // elements of the first vector operand, for which the corresponding bit
5019     // in the k-mask operand is set to 0, are copied to the result of the
5020     // instruction.
5021     // TODO/FIXME: The commute still may be legal if it is known that the
5022     // k-mask operand is set to either all ones or all zeroes.
5023     // It is also Ok to commute the 1st operand if all users of MI use only
5024     // the elements enabled by the k-mask operand. For example,
5025     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
5026     //                                                     : v1[i];
5027     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
5028     //                                  // Ok, to commute v1 in FMADD213PSZrk.
5029     if (X86II::isKMergeMasked(TSFlags) && SrcOpIdx1 == Op1)
5030       return -1;
5031     Op2++;
5032     Op3++;
5033   }
5034 
5035   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
5036     return 0;
5037   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
5038     return 1;
5039   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
5040     return 2;
5041   return -1;
5042 }
5043 
5044 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
5045     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
5046     const X86InstrFMA3Group &FMA3Group) const {
5047 
5048   unsigned Opc = MI.getOpcode();
5049 
5050   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
5051   if (SrcOpIdx1 > SrcOpIdx2)
5052     std::swap(SrcOpIdx1, SrcOpIdx2);
5053 
5054   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
5055   // analysis. The commute optimization is legal only if all users of FMA*_Int
5056   // use only the lowest element of the FMA*_Int instruction. Such analysis are
5057   // not implemented yet. So, just return 0 in that case.
5058   // When such analysis are available this place will be the right place for
5059   // calling it.
5060   if (FMA3Group.isIntrinsic() && SrcOpIdx1 == 1)
5061     return 0;
5062 
5063   // Determine which case this commute is or if it can't be done.
5064   int Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
5065   if (Case < 0)
5066     return 0;
5067 
5068   // Define the FMA forms mapping array that helps to map input FMA form
5069   // to output FMA form to preserve the operation semantics after
5070   // commuting the operands.
5071   const unsigned Form132Index = 0;
5072   const unsigned Form213Index = 1;
5073   const unsigned Form231Index = 2;
5074   static const unsigned FormMapping[][3] = {
5075     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
5076     // FMA132 A, C, b; ==> FMA231 C, A, b;
5077     // FMA213 B, A, c; ==> FMA213 A, B, c;
5078     // FMA231 C, A, b; ==> FMA132 A, C, b;
5079     { Form231Index, Form213Index, Form132Index },
5080     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
5081     // FMA132 A, c, B; ==> FMA132 B, c, A;
5082     // FMA213 B, a, C; ==> FMA231 C, a, B;
5083     // FMA231 C, a, B; ==> FMA213 B, a, C;
5084     { Form132Index, Form231Index, Form213Index },
5085     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
5086     // FMA132 a, C, B; ==> FMA213 a, B, C;
5087     // FMA213 b, A, C; ==> FMA132 b, C, A;
5088     // FMA231 c, A, B; ==> FMA231 c, B, A;
5089     { Form213Index, Form132Index, Form231Index }
5090   };
5091 
5092   unsigned FMAForms[3];
5093   if (FMA3Group.isRegOpcodeFromGroup(Opc)) {
5094     FMAForms[0] = FMA3Group.getReg132Opcode();
5095     FMAForms[1] = FMA3Group.getReg213Opcode();
5096     FMAForms[2] = FMA3Group.getReg231Opcode();
5097   } else {
5098     FMAForms[0] = FMA3Group.getMem132Opcode();
5099     FMAForms[1] = FMA3Group.getMem213Opcode();
5100     FMAForms[2] = FMA3Group.getMem231Opcode();
5101   }
5102   unsigned FormIndex;
5103   for (FormIndex = 0; FormIndex < 3; FormIndex++)
5104     if (Opc == FMAForms[FormIndex])
5105       break;
5106 
5107   // Everything is ready, just adjust the FMA opcode and return it.
5108   FormIndex = FormMapping[Case][FormIndex];
5109   return FMAForms[FormIndex];
5110 }
5111 
5112 static bool commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
5113                              unsigned SrcOpIdx2) {
5114   uint64_t TSFlags = MI.getDesc().TSFlags;
5115 
5116   // Determine which case this commute is or if it can't be done.
5117   int Case = getThreeSrcCommuteCase(TSFlags, SrcOpIdx1, SrcOpIdx2);
5118   if (Case < 0)
5119     return false;
5120 
5121   // For each case we need to swap two pairs of bits in the final immediate.
5122   static const uint8_t SwapMasks[3][4] = {
5123     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
5124     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
5125     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
5126   };
5127 
5128   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
5129   // Clear out the bits we are swapping.
5130   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
5131                            SwapMasks[Case][2] | SwapMasks[Case][3]);
5132   // If the immediate had a bit of the pair set, then set the opposite bit.
5133   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
5134   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
5135   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
5136   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
5137   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
5138 
5139   return true;
5140 }
5141 
5142 // Returns true if this is a VPERMI2 or VPERMT2 instrution that can be
5143 // commuted.
5144 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
5145 #define VPERM_CASES(Suffix) \
5146   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
5147   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
5148   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
5149   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
5150   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
5151   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
5152   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
5153   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
5154   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
5155   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
5156   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
5157   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
5158 
5159 #define VPERM_CASES_BROADCAST(Suffix) \
5160   VPERM_CASES(Suffix) \
5161   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
5162   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
5163   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
5164   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
5165   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
5166   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
5167 
5168   switch (Opcode) {
5169   default: return false;
5170   VPERM_CASES(B)
5171   VPERM_CASES_BROADCAST(D)
5172   VPERM_CASES_BROADCAST(PD)
5173   VPERM_CASES_BROADCAST(PS)
5174   VPERM_CASES_BROADCAST(Q)
5175   VPERM_CASES(W)
5176     return true;
5177   }
5178 #undef VPERM_CASES_BROADCAST
5179 #undef VPERM_CASES
5180 }
5181 
5182 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
5183 // from the I opcod to the T opcode and vice versa.
5184 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
5185 #define VPERM_CASES(Orig, New) \
5186   case X86::Orig##128rr:    return X86::New##128rr;   \
5187   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
5188   case X86::Orig##128rm:    return X86::New##128rm;   \
5189   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
5190   case X86::Orig##256rr:    return X86::New##256rr;   \
5191   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
5192   case X86::Orig##256rm:    return X86::New##256rm;   \
5193   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
5194   case X86::Orig##rr:       return X86::New##rr;      \
5195   case X86::Orig##rrkz:     return X86::New##rrkz;    \
5196   case X86::Orig##rm:       return X86::New##rm;      \
5197   case X86::Orig##rmkz:     return X86::New##rmkz;
5198 
5199 #define VPERM_CASES_BROADCAST(Orig, New) \
5200   VPERM_CASES(Orig, New) \
5201   case X86::Orig##128rmb:   return X86::New##128rmb;   \
5202   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
5203   case X86::Orig##256rmb:   return X86::New##256rmb;   \
5204   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
5205   case X86::Orig##rmb:      return X86::New##rmb;      \
5206   case X86::Orig##rmbkz:    return X86::New##rmbkz;
5207 
5208   switch (Opcode) {
5209   VPERM_CASES(VPERMI2B, VPERMT2B)
5210   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
5211   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
5212   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
5213   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
5214   VPERM_CASES(VPERMI2W, VPERMT2W)
5215   VPERM_CASES(VPERMT2B, VPERMI2B)
5216   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
5217   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
5218   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
5219   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
5220   VPERM_CASES(VPERMT2W, VPERMI2W)
5221   }
5222 
5223   llvm_unreachable("Unreachable!");
5224 #undef VPERM_CASES_BROADCAST
5225 #undef VPERM_CASES
5226 }
5227 
5228 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
5229                                                    unsigned OpIdx1,
5230                                                    unsigned OpIdx2) const {
5231   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
5232     if (NewMI)
5233       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
5234     return MI;
5235   };
5236 
5237   switch (MI.getOpcode()) {
5238   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
5239   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
5240   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
5241   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
5242   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
5243   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
5244     unsigned Opc;
5245     unsigned Size;
5246     switch (MI.getOpcode()) {
5247     default: llvm_unreachable("Unreachable!");
5248     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
5249     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
5250     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
5251     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
5252     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
5253     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
5254     }
5255     unsigned Amt = MI.getOperand(3).getImm();
5256     auto &WorkingMI = cloneIfNew(MI);
5257     WorkingMI.setDesc(get(Opc));
5258     WorkingMI.getOperand(3).setImm(Size - Amt);
5259     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5260                                                    OpIdx1, OpIdx2);
5261   }
5262   case X86::PFSUBrr:
5263   case X86::PFSUBRrr: {
5264     // PFSUB  x, y: x = x - y
5265     // PFSUBR x, y: x = y - x
5266     unsigned Opc =
5267         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
5268     auto &WorkingMI = cloneIfNew(MI);
5269     WorkingMI.setDesc(get(Opc));
5270     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5271                                                    OpIdx1, OpIdx2);
5272   }
5273   case X86::BLENDPDrri:
5274   case X86::BLENDPSrri:
5275   case X86::PBLENDWrri:
5276   case X86::VBLENDPDrri:
5277   case X86::VBLENDPSrri:
5278   case X86::VBLENDPDYrri:
5279   case X86::VBLENDPSYrri:
5280   case X86::VPBLENDDrri:
5281   case X86::VPBLENDWrri:
5282   case X86::VPBLENDDYrri:
5283   case X86::VPBLENDWYrri:{
5284     unsigned Mask;
5285     switch (MI.getOpcode()) {
5286     default: llvm_unreachable("Unreachable!");
5287     case X86::BLENDPDrri:    Mask = 0x03; break;
5288     case X86::BLENDPSrri:    Mask = 0x0F; break;
5289     case X86::PBLENDWrri:    Mask = 0xFF; break;
5290     case X86::VBLENDPDrri:   Mask = 0x03; break;
5291     case X86::VBLENDPSrri:   Mask = 0x0F; break;
5292     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
5293     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
5294     case X86::VPBLENDDrri:   Mask = 0x0F; break;
5295     case X86::VPBLENDWrri:   Mask = 0xFF; break;
5296     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
5297     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
5298     }
5299     // Only the least significant bits of Imm are used.
5300     unsigned Imm = MI.getOperand(3).getImm() & Mask;
5301     auto &WorkingMI = cloneIfNew(MI);
5302     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
5303     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5304                                                    OpIdx1, OpIdx2);
5305   }
5306   case X86::MOVSDrr:
5307   case X86::MOVSSrr:
5308   case X86::VMOVSDrr:
5309   case X86::VMOVSSrr:{
5310     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
5311     if (!Subtarget.hasSSE41())
5312       return nullptr;
5313 
5314     unsigned Mask, Opc;
5315     switch (MI.getOpcode()) {
5316     default: llvm_unreachable("Unreachable!");
5317     case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
5318     case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
5319     case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
5320     case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
5321     }
5322 
5323     auto &WorkingMI = cloneIfNew(MI);
5324     WorkingMI.setDesc(get(Opc));
5325     WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
5326     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5327                                                    OpIdx1, OpIdx2);
5328   }
5329   case X86::PCLMULQDQrr:
5330   case X86::VPCLMULQDQrr:
5331   case X86::VPCLMULQDQYrr:
5332   case X86::VPCLMULQDQZrr:
5333   case X86::VPCLMULQDQZ128rr:
5334   case X86::VPCLMULQDQZ256rr: {
5335     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
5336     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
5337     unsigned Imm = MI.getOperand(3).getImm();
5338     unsigned Src1Hi = Imm & 0x01;
5339     unsigned Src2Hi = Imm & 0x10;
5340     auto &WorkingMI = cloneIfNew(MI);
5341     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
5342     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5343                                                    OpIdx1, OpIdx2);
5344   }
5345   case X86::CMPSDrr:
5346   case X86::CMPSSrr:
5347   case X86::CMPPDrri:
5348   case X86::CMPPSrri:
5349   case X86::VCMPSDrr:
5350   case X86::VCMPSSrr:
5351   case X86::VCMPPDrri:
5352   case X86::VCMPPSrri:
5353   case X86::VCMPPDYrri:
5354   case X86::VCMPPSYrri:
5355   case X86::VCMPSDZrr:
5356   case X86::VCMPSSZrr:
5357   case X86::VCMPPDZrri:
5358   case X86::VCMPPSZrri:
5359   case X86::VCMPPDZ128rri:
5360   case X86::VCMPPSZ128rri:
5361   case X86::VCMPPDZ256rri:
5362   case X86::VCMPPSZ256rri: {
5363     // Float comparison can be safely commuted for
5364     // Ordered/Unordered/Equal/NotEqual tests
5365     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5366     switch (Imm) {
5367     case 0x00: // EQUAL
5368     case 0x03: // UNORDERED
5369     case 0x04: // NOT EQUAL
5370     case 0x07: // ORDERED
5371       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
5372     default:
5373       return nullptr;
5374     }
5375   }
5376   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
5377   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
5378   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
5379   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
5380   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
5381   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
5382   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
5383   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
5384   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
5385   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
5386   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
5387   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
5388   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
5389   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
5390   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
5391   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
5392   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
5393   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
5394   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
5395   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
5396   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
5397   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
5398   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
5399   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
5400     // Flip comparison mode immediate (if necessary).
5401     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
5402     switch (Imm) {
5403     default: llvm_unreachable("Unreachable!");
5404     case 0x01: Imm = 0x06; break; // LT  -> NLE
5405     case 0x02: Imm = 0x05; break; // LE  -> NLT
5406     case 0x05: Imm = 0x02; break; // NLT -> LE
5407     case 0x06: Imm = 0x01; break; // NLE -> LT
5408     case 0x00: // EQ
5409     case 0x03: // FALSE
5410     case 0x04: // NE
5411     case 0x07: // TRUE
5412       break;
5413     }
5414     auto &WorkingMI = cloneIfNew(MI);
5415     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
5416     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5417                                                    OpIdx1, OpIdx2);
5418   }
5419   case X86::VPCOMBri: case X86::VPCOMUBri:
5420   case X86::VPCOMDri: case X86::VPCOMUDri:
5421   case X86::VPCOMQri: case X86::VPCOMUQri:
5422   case X86::VPCOMWri: case X86::VPCOMUWri: {
5423     // Flip comparison mode immediate (if necessary).
5424     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5425     switch (Imm) {
5426     default: llvm_unreachable("Unreachable!");
5427     case 0x00: Imm = 0x02; break; // LT -> GT
5428     case 0x01: Imm = 0x03; break; // LE -> GE
5429     case 0x02: Imm = 0x00; break; // GT -> LT
5430     case 0x03: Imm = 0x01; break; // GE -> LE
5431     case 0x04: // EQ
5432     case 0x05: // NE
5433     case 0x06: // FALSE
5434     case 0x07: // TRUE
5435       break;
5436     }
5437     auto &WorkingMI = cloneIfNew(MI);
5438     WorkingMI.getOperand(3).setImm(Imm);
5439     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5440                                                    OpIdx1, OpIdx2);
5441   }
5442   case X86::VPERM2F128rr:
5443   case X86::VPERM2I128rr: {
5444     // Flip permute source immediate.
5445     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
5446     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
5447     unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
5448     auto &WorkingMI = cloneIfNew(MI);
5449     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
5450     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5451                                                    OpIdx1, OpIdx2);
5452   }
5453   case X86::MOVHLPSrr:
5454   case X86::UNPCKHPDrr: {
5455     if (!Subtarget.hasSSE2())
5456       return nullptr;
5457 
5458     unsigned Opc = MI.getOpcode();
5459     switch (Opc) {
5460       default: llvm_unreachable("Unreachable!");
5461       case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
5462       case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
5463     }
5464     auto &WorkingMI = cloneIfNew(MI);
5465     WorkingMI.setDesc(get(Opc));
5466     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5467                                                    OpIdx1, OpIdx2);
5468   }
5469   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
5470   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
5471   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
5472   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
5473   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
5474   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
5475   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
5476   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
5477   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
5478   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
5479   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
5480   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
5481   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
5482   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
5483   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
5484   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
5485     unsigned Opc;
5486     switch (MI.getOpcode()) {
5487     default: llvm_unreachable("Unreachable!");
5488     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
5489     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
5490     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
5491     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
5492     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
5493     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
5494     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
5495     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
5496     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
5497     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
5498     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
5499     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
5500     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
5501     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
5502     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
5503     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
5504     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
5505     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
5506     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
5507     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
5508     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
5509     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
5510     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
5511     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
5512     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
5513     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
5514     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
5515     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
5516     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
5517     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
5518     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
5519     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
5520     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
5521     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
5522     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
5523     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
5524     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
5525     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
5526     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
5527     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
5528     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
5529     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
5530     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
5531     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
5532     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
5533     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
5534     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
5535     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
5536     }
5537     auto &WorkingMI = cloneIfNew(MI);
5538     WorkingMI.setDesc(get(Opc));
5539     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5540                                                    OpIdx1, OpIdx2);
5541   }
5542   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
5543   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
5544   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
5545   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
5546   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
5547   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
5548   case X86::VPTERNLOGDZrrik:
5549   case X86::VPTERNLOGDZ128rrik:
5550   case X86::VPTERNLOGDZ256rrik:
5551   case X86::VPTERNLOGQZrrik:
5552   case X86::VPTERNLOGQZ128rrik:
5553   case X86::VPTERNLOGQZ256rrik:
5554   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
5555   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
5556   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
5557   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
5558   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
5559   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
5560   case X86::VPTERNLOGDZ128rmbi:
5561   case X86::VPTERNLOGDZ256rmbi:
5562   case X86::VPTERNLOGDZrmbi:
5563   case X86::VPTERNLOGQZ128rmbi:
5564   case X86::VPTERNLOGQZ256rmbi:
5565   case X86::VPTERNLOGQZrmbi:
5566   case X86::VPTERNLOGDZ128rmbikz:
5567   case X86::VPTERNLOGDZ256rmbikz:
5568   case X86::VPTERNLOGDZrmbikz:
5569   case X86::VPTERNLOGQZ128rmbikz:
5570   case X86::VPTERNLOGQZ256rmbikz:
5571   case X86::VPTERNLOGQZrmbikz: {
5572     auto &WorkingMI = cloneIfNew(MI);
5573     if (!commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2))
5574       return nullptr;
5575     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5576                                                    OpIdx1, OpIdx2);
5577   }
5578   default: {
5579     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
5580       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
5581       auto &WorkingMI = cloneIfNew(MI);
5582       WorkingMI.setDesc(get(Opc));
5583       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5584                                                      OpIdx1, OpIdx2);
5585     }
5586 
5587     const X86InstrFMA3Group *FMA3Group =
5588         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
5589     if (FMA3Group) {
5590       unsigned Opc =
5591         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
5592       if (Opc == 0)
5593         return nullptr;
5594       auto &WorkingMI = cloneIfNew(MI);
5595       WorkingMI.setDesc(get(Opc));
5596       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5597                                                      OpIdx1, OpIdx2);
5598     }
5599 
5600     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
5601   }
5602   }
5603 }
5604 
5605 bool X86InstrInfo::findFMA3CommutedOpIndices(
5606     const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2,
5607     const X86InstrFMA3Group &FMA3Group) const {
5608 
5609   if (!findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2))
5610     return false;
5611 
5612   // Check if we can adjust the opcode to preserve the semantics when
5613   // commute the register operands.
5614   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2, FMA3Group) != 0;
5615 }
5616 
5617 bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
5618                                                  unsigned &SrcOpIdx1,
5619                                                  unsigned &SrcOpIdx2) const {
5620   uint64_t TSFlags = MI.getDesc().TSFlags;
5621 
5622   unsigned FirstCommutableVecOp = 1;
5623   unsigned LastCommutableVecOp = 3;
5624   unsigned KMaskOp = 0;
5625   if (X86II::isKMasked(TSFlags)) {
5626     // The k-mask operand has index = 2 for masked and zero-masked operations.
5627     KMaskOp = 2;
5628 
5629     // The operand with index = 1 is used as a source for those elements for
5630     // which the corresponding bit in the k-mask is set to 0.
5631     if (X86II::isKMergeMasked(TSFlags))
5632       FirstCommutableVecOp = 3;
5633 
5634     LastCommutableVecOp++;
5635   }
5636 
5637   if (isMem(MI, LastCommutableVecOp))
5638     LastCommutableVecOp--;
5639 
5640   // Only the first RegOpsNum operands are commutable.
5641   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
5642   // that the operand is not specified/fixed.
5643   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
5644       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
5645        SrcOpIdx1 == KMaskOp))
5646     return false;
5647   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
5648       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
5649        SrcOpIdx2 == KMaskOp))
5650     return false;
5651 
5652   // Look for two different register operands assumed to be commutable
5653   // regardless of the FMA opcode. The FMA opcode is adjusted later.
5654   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
5655       SrcOpIdx2 == CommuteAnyOperandIndex) {
5656     unsigned CommutableOpIdx1 = SrcOpIdx1;
5657     unsigned CommutableOpIdx2 = SrcOpIdx2;
5658 
5659     // At least one of operands to be commuted is not specified and
5660     // this method is free to choose appropriate commutable operands.
5661     if (SrcOpIdx1 == SrcOpIdx2)
5662       // Both of operands are not fixed. By default set one of commutable
5663       // operands to the last register operand of the instruction.
5664       CommutableOpIdx2 = LastCommutableVecOp;
5665     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
5666       // Only one of operands is not fixed.
5667       CommutableOpIdx2 = SrcOpIdx1;
5668 
5669     // CommutableOpIdx2 is well defined now. Let's choose another commutable
5670     // operand and assign its index to CommutableOpIdx1.
5671     unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
5672     for (CommutableOpIdx1 = LastCommutableVecOp;
5673          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
5674       // Just ignore and skip the k-mask operand.
5675       if (CommutableOpIdx1 == KMaskOp)
5676         continue;
5677 
5678       // The commuted operands must have different registers.
5679       // Otherwise, the commute transformation does not change anything and
5680       // is useless then.
5681       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
5682         break;
5683     }
5684 
5685     // No appropriate commutable operands were found.
5686     if (CommutableOpIdx1 < FirstCommutableVecOp)
5687       return false;
5688 
5689     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
5690     // to return those values.
5691     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
5692                               CommutableOpIdx1, CommutableOpIdx2))
5693       return false;
5694   }
5695 
5696   return true;
5697 }
5698 
5699 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
5700                                          unsigned &SrcOpIdx2) const {
5701   const MCInstrDesc &Desc = MI.getDesc();
5702   if (!Desc.isCommutable())
5703     return false;
5704 
5705   switch (MI.getOpcode()) {
5706   case X86::CMPSDrr:
5707   case X86::CMPSSrr:
5708   case X86::CMPPDrri:
5709   case X86::CMPPSrri:
5710   case X86::VCMPSDrr:
5711   case X86::VCMPSSrr:
5712   case X86::VCMPPDrri:
5713   case X86::VCMPPSrri:
5714   case X86::VCMPPDYrri:
5715   case X86::VCMPPSYrri:
5716   case X86::VCMPSDZrr:
5717   case X86::VCMPSSZrr:
5718   case X86::VCMPPDZrri:
5719   case X86::VCMPPSZrri:
5720   case X86::VCMPPDZ128rri:
5721   case X86::VCMPPSZ128rri:
5722   case X86::VCMPPDZ256rri:
5723   case X86::VCMPPSZ256rri: {
5724     // Float comparison can be safely commuted for
5725     // Ordered/Unordered/Equal/NotEqual tests
5726     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5727     switch (Imm) {
5728     case 0x00: // EQUAL
5729     case 0x03: // UNORDERED
5730     case 0x04: // NOT EQUAL
5731     case 0x07: // ORDERED
5732       // The indices of the commutable operands are 1 and 2.
5733       // Assign them to the returned operand indices here.
5734       return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
5735     }
5736     return false;
5737   }
5738   case X86::MOVSDrr:
5739   case X86::MOVSSrr:
5740   case X86::VMOVSDrr:
5741   case X86::VMOVSSrr: {
5742     if (Subtarget.hasSSE41())
5743       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5744     return false;
5745   }
5746   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
5747   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
5748   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
5749   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
5750   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
5751   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
5752   case X86::VPTERNLOGDZrrik:
5753   case X86::VPTERNLOGDZ128rrik:
5754   case X86::VPTERNLOGDZ256rrik:
5755   case X86::VPTERNLOGQZrrik:
5756   case X86::VPTERNLOGQZ128rrik:
5757   case X86::VPTERNLOGQZ256rrik:
5758   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
5759   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
5760   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
5761   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
5762   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
5763   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
5764   case X86::VPTERNLOGDZ128rmbi:
5765   case X86::VPTERNLOGDZ256rmbi:
5766   case X86::VPTERNLOGDZrmbi:
5767   case X86::VPTERNLOGQZ128rmbi:
5768   case X86::VPTERNLOGQZ256rmbi:
5769   case X86::VPTERNLOGQZrmbi:
5770   case X86::VPTERNLOGDZ128rmbikz:
5771   case X86::VPTERNLOGDZ256rmbikz:
5772   case X86::VPTERNLOGDZrmbikz:
5773   case X86::VPTERNLOGQZ128rmbikz:
5774   case X86::VPTERNLOGQZ256rmbikz:
5775   case X86::VPTERNLOGQZrmbikz:
5776     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5777   case X86::VPMADD52HUQZ128r:
5778   case X86::VPMADD52HUQZ128rk:
5779   case X86::VPMADD52HUQZ128rkz:
5780   case X86::VPMADD52HUQZ256r:
5781   case X86::VPMADD52HUQZ256rk:
5782   case X86::VPMADD52HUQZ256rkz:
5783   case X86::VPMADD52HUQZr:
5784   case X86::VPMADD52HUQZrk:
5785   case X86::VPMADD52HUQZrkz:
5786   case X86::VPMADD52LUQZ128r:
5787   case X86::VPMADD52LUQZ128rk:
5788   case X86::VPMADD52LUQZ128rkz:
5789   case X86::VPMADD52LUQZ256r:
5790   case X86::VPMADD52LUQZ256rk:
5791   case X86::VPMADD52LUQZ256rkz:
5792   case X86::VPMADD52LUQZr:
5793   case X86::VPMADD52LUQZrk:
5794   case X86::VPMADD52LUQZrkz: {
5795     unsigned CommutableOpIdx1 = 2;
5796     unsigned CommutableOpIdx2 = 3;
5797     if (Desc.TSFlags & X86II::EVEX_K) {
5798       // Skip the mask register.
5799       ++CommutableOpIdx1;
5800       ++CommutableOpIdx2;
5801     }
5802     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
5803                               CommutableOpIdx1, CommutableOpIdx2))
5804       return false;
5805     if (!MI.getOperand(SrcOpIdx1).isReg() ||
5806         !MI.getOperand(SrcOpIdx2).isReg())
5807       // No idea.
5808       return false;
5809     return true;
5810   }
5811 
5812   default:
5813     const X86InstrFMA3Group *FMA3Group =
5814         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
5815     if (FMA3Group)
5816       return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2, *FMA3Group);
5817 
5818     // Handled masked instructions since we need to skip over the mask input
5819     // and the preserved input.
5820     if (Desc.TSFlags & X86II::EVEX_K) {
5821       // First assume that the first input is the mask operand and skip past it.
5822       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
5823       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
5824       // Check if the first input is tied. If there isn't one then we only
5825       // need to skip the mask operand which we did above.
5826       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
5827                                              MCOI::TIED_TO) != -1)) {
5828         // If this is zero masking instruction with a tied operand, we need to
5829         // move the first index back to the first input since this must
5830         // be a 3 input instruction and we want the first two non-mask inputs.
5831         // Otherwise this is a 2 input instruction with a preserved input and
5832         // mask, so we need to move the indices to skip one more input.
5833         if (Desc.TSFlags & X86II::EVEX_Z)
5834           --CommutableOpIdx1;
5835         else {
5836           ++CommutableOpIdx1;
5837           ++CommutableOpIdx2;
5838         }
5839       }
5840 
5841       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
5842                                 CommutableOpIdx1, CommutableOpIdx2))
5843         return false;
5844 
5845       if (!MI.getOperand(SrcOpIdx1).isReg() ||
5846           !MI.getOperand(SrcOpIdx2).isReg())
5847         // No idea.
5848         return false;
5849       return true;
5850     }
5851 
5852     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5853   }
5854   return false;
5855 }
5856 
5857 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
5858   switch (BrOpc) {
5859   default: return X86::COND_INVALID;
5860   case X86::JE_1:  return X86::COND_E;
5861   case X86::JNE_1: return X86::COND_NE;
5862   case X86::JL_1:  return X86::COND_L;
5863   case X86::JLE_1: return X86::COND_LE;
5864   case X86::JG_1:  return X86::COND_G;
5865   case X86::JGE_1: return X86::COND_GE;
5866   case X86::JB_1:  return X86::COND_B;
5867   case X86::JBE_1: return X86::COND_BE;
5868   case X86::JA_1:  return X86::COND_A;
5869   case X86::JAE_1: return X86::COND_AE;
5870   case X86::JS_1:  return X86::COND_S;
5871   case X86::JNS_1: return X86::COND_NS;
5872   case X86::JP_1:  return X86::COND_P;
5873   case X86::JNP_1: return X86::COND_NP;
5874   case X86::JO_1:  return X86::COND_O;
5875   case X86::JNO_1: return X86::COND_NO;
5876   }
5877 }
5878 
5879 /// Return condition code of a SET opcode.
5880 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
5881   switch (Opc) {
5882   default: return X86::COND_INVALID;
5883   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
5884   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
5885   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
5886   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
5887   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
5888   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
5889   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
5890   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
5891   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
5892   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
5893   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
5894   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
5895   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
5896   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
5897   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
5898   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
5899   }
5900 }
5901 
5902 /// Return condition code of a CMov opcode.
5903 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
5904   switch (Opc) {
5905   default: return X86::COND_INVALID;
5906   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
5907   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
5908     return X86::COND_A;
5909   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
5910   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
5911     return X86::COND_AE;
5912   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
5913   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
5914     return X86::COND_B;
5915   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
5916   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
5917     return X86::COND_BE;
5918   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
5919   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
5920     return X86::COND_E;
5921   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
5922   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
5923     return X86::COND_G;
5924   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
5925   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
5926     return X86::COND_GE;
5927   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
5928   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
5929     return X86::COND_L;
5930   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
5931   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
5932     return X86::COND_LE;
5933   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
5934   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
5935     return X86::COND_NE;
5936   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
5937   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
5938     return X86::COND_NO;
5939   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
5940   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
5941     return X86::COND_NP;
5942   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
5943   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
5944     return X86::COND_NS;
5945   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
5946   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
5947     return X86::COND_O;
5948   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
5949   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
5950     return X86::COND_P;
5951   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
5952   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
5953     return X86::COND_S;
5954   }
5955 }
5956 
5957 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
5958   switch (CC) {
5959   default: llvm_unreachable("Illegal condition code!");
5960   case X86::COND_E:  return X86::JE_1;
5961   case X86::COND_NE: return X86::JNE_1;
5962   case X86::COND_L:  return X86::JL_1;
5963   case X86::COND_LE: return X86::JLE_1;
5964   case X86::COND_G:  return X86::JG_1;
5965   case X86::COND_GE: return X86::JGE_1;
5966   case X86::COND_B:  return X86::JB_1;
5967   case X86::COND_BE: return X86::JBE_1;
5968   case X86::COND_A:  return X86::JA_1;
5969   case X86::COND_AE: return X86::JAE_1;
5970   case X86::COND_S:  return X86::JS_1;
5971   case X86::COND_NS: return X86::JNS_1;
5972   case X86::COND_P:  return X86::JP_1;
5973   case X86::COND_NP: return X86::JNP_1;
5974   case X86::COND_O:  return X86::JO_1;
5975   case X86::COND_NO: return X86::JNO_1;
5976   }
5977 }
5978 
5979 /// Return the inverse of the specified condition,
5980 /// e.g. turning COND_E to COND_NE.
5981 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
5982   switch (CC) {
5983   default: llvm_unreachable("Illegal condition code!");
5984   case X86::COND_E:  return X86::COND_NE;
5985   case X86::COND_NE: return X86::COND_E;
5986   case X86::COND_L:  return X86::COND_GE;
5987   case X86::COND_LE: return X86::COND_G;
5988   case X86::COND_G:  return X86::COND_LE;
5989   case X86::COND_GE: return X86::COND_L;
5990   case X86::COND_B:  return X86::COND_AE;
5991   case X86::COND_BE: return X86::COND_A;
5992   case X86::COND_A:  return X86::COND_BE;
5993   case X86::COND_AE: return X86::COND_B;
5994   case X86::COND_S:  return X86::COND_NS;
5995   case X86::COND_NS: return X86::COND_S;
5996   case X86::COND_P:  return X86::COND_NP;
5997   case X86::COND_NP: return X86::COND_P;
5998   case X86::COND_O:  return X86::COND_NO;
5999   case X86::COND_NO: return X86::COND_O;
6000   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
6001   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
6002   }
6003 }
6004 
6005 /// Assuming the flags are set by MI(a,b), return the condition code if we
6006 /// modify the instructions such that flags are set by MI(b,a).
6007 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
6008   switch (CC) {
6009   default: return X86::COND_INVALID;
6010   case X86::COND_E:  return X86::COND_E;
6011   case X86::COND_NE: return X86::COND_NE;
6012   case X86::COND_L:  return X86::COND_G;
6013   case X86::COND_LE: return X86::COND_GE;
6014   case X86::COND_G:  return X86::COND_L;
6015   case X86::COND_GE: return X86::COND_LE;
6016   case X86::COND_B:  return X86::COND_A;
6017   case X86::COND_BE: return X86::COND_AE;
6018   case X86::COND_A:  return X86::COND_B;
6019   case X86::COND_AE: return X86::COND_BE;
6020   }
6021 }
6022 
6023 std::pair<X86::CondCode, bool>
6024 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
6025   X86::CondCode CC = X86::COND_INVALID;
6026   bool NeedSwap = false;
6027   switch (Predicate) {
6028   default: break;
6029   // Floating-point Predicates
6030   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
6031   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
6032   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
6033   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
6034   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
6035   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
6036   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
6037   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
6038   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
6039   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
6040   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
6041   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
6042   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
6043   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
6044 
6045   // Integer Predicates
6046   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
6047   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
6048   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
6049   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
6050   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
6051   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
6052   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
6053   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
6054   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
6055   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
6056   }
6057 
6058   return std::make_pair(CC, NeedSwap);
6059 }
6060 
6061 /// Return a set opcode for the given condition and
6062 /// whether it has memory operand.
6063 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
6064   static const uint16_t Opc[16][2] = {
6065     { X86::SETAr,  X86::SETAm  },
6066     { X86::SETAEr, X86::SETAEm },
6067     { X86::SETBr,  X86::SETBm  },
6068     { X86::SETBEr, X86::SETBEm },
6069     { X86::SETEr,  X86::SETEm  },
6070     { X86::SETGr,  X86::SETGm  },
6071     { X86::SETGEr, X86::SETGEm },
6072     { X86::SETLr,  X86::SETLm  },
6073     { X86::SETLEr, X86::SETLEm },
6074     { X86::SETNEr, X86::SETNEm },
6075     { X86::SETNOr, X86::SETNOm },
6076     { X86::SETNPr, X86::SETNPm },
6077     { X86::SETNSr, X86::SETNSm },
6078     { X86::SETOr,  X86::SETOm  },
6079     { X86::SETPr,  X86::SETPm  },
6080     { X86::SETSr,  X86::SETSm  }
6081   };
6082 
6083   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
6084   return Opc[CC][HasMemoryOperand ? 1 : 0];
6085 }
6086 
6087 /// Return a cmov opcode for the given condition,
6088 /// register size in bytes, and operand type.
6089 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
6090                               bool HasMemoryOperand) {
6091   static const uint16_t Opc[32][3] = {
6092     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
6093     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
6094     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
6095     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
6096     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
6097     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
6098     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
6099     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
6100     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
6101     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
6102     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
6103     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
6104     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
6105     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
6106     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
6107     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
6108     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
6109     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
6110     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
6111     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
6112     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
6113     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
6114     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
6115     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
6116     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
6117     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
6118     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
6119     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
6120     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
6121     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
6122     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
6123     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
6124   };
6125 
6126   assert(CC < 16 && "Can only handle standard cond codes");
6127   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
6128   switch(RegBytes) {
6129   default: llvm_unreachable("Illegal register size!");
6130   case 2: return Opc[Idx][0];
6131   case 4: return Opc[Idx][1];
6132   case 8: return Opc[Idx][2];
6133   }
6134 }
6135 
6136 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
6137   if (!MI.isTerminator()) return false;
6138 
6139   // Conditional branch is a special case.
6140   if (MI.isBranch() && !MI.isBarrier())
6141     return true;
6142   if (!MI.isPredicable())
6143     return true;
6144   return !isPredicated(MI);
6145 }
6146 
6147 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
6148   switch (MI.getOpcode()) {
6149   case X86::TCRETURNdi:
6150   case X86::TCRETURNri:
6151   case X86::TCRETURNmi:
6152   case X86::TCRETURNdi64:
6153   case X86::TCRETURNri64:
6154   case X86::TCRETURNmi64:
6155     return true;
6156   default:
6157     return false;
6158   }
6159 }
6160 
6161 bool X86InstrInfo::canMakeTailCallConditional(
6162     SmallVectorImpl<MachineOperand> &BranchCond,
6163     const MachineInstr &TailCall) const {
6164   if (TailCall.getOpcode() != X86::TCRETURNdi &&
6165       TailCall.getOpcode() != X86::TCRETURNdi64) {
6166     // Only direct calls can be done with a conditional branch.
6167     return false;
6168   }
6169 
6170   const MachineFunction *MF = TailCall.getParent()->getParent();
6171   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
6172     // Conditional tail calls confuse the Win64 unwinder.
6173     return false;
6174   }
6175 
6176   assert(BranchCond.size() == 1);
6177   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
6178     // Can't make a conditional tail call with this condition.
6179     return false;
6180   }
6181 
6182   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6183   if (X86FI->getTCReturnAddrDelta() != 0 ||
6184       TailCall.getOperand(1).getImm() != 0) {
6185     // A conditional tail call cannot do any stack adjustment.
6186     return false;
6187   }
6188 
6189   return true;
6190 }
6191 
6192 void X86InstrInfo::replaceBranchWithTailCall(
6193     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
6194     const MachineInstr &TailCall) const {
6195   assert(canMakeTailCallConditional(BranchCond, TailCall));
6196 
6197   MachineBasicBlock::iterator I = MBB.end();
6198   while (I != MBB.begin()) {
6199     --I;
6200     if (I->isDebugValue())
6201       continue;
6202     if (!I->isBranch())
6203       assert(0 && "Can't find the branch to replace!");
6204 
6205     X86::CondCode CC = getCondFromBranchOpc(I->getOpcode());
6206     assert(BranchCond.size() == 1);
6207     if (CC != BranchCond[0].getImm())
6208       continue;
6209 
6210     break;
6211   }
6212 
6213   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
6214                                                          : X86::TCRETURNdi64cc;
6215 
6216   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
6217   MIB->addOperand(TailCall.getOperand(0)); // Destination.
6218   MIB.addImm(0); // Stack offset (not used).
6219   MIB->addOperand(BranchCond[0]); // Condition.
6220   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
6221 
6222   // Add implicit uses and defs of all live regs potentially clobbered by the
6223   // call. This way they still appear live across the call.
6224   LivePhysRegs LiveRegs(getRegisterInfo());
6225   LiveRegs.addLiveOuts(MBB);
6226   SmallVector<std::pair<unsigned, const MachineOperand *>, 8> Clobbers;
6227   LiveRegs.stepForward(*MIB, Clobbers);
6228   for (const auto &C : Clobbers) {
6229     MIB.addReg(C.first, RegState::Implicit);
6230     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
6231   }
6232 
6233   I->eraseFromParent();
6234 }
6235 
6236 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
6237 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
6238 // fallthrough MBB cannot be identified.
6239 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
6240                                             MachineBasicBlock *TBB) {
6241   // Look for non-EHPad successors other than TBB. If we find exactly one, it
6242   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
6243   // and fallthrough MBB. If we find more than one, we cannot identify the
6244   // fallthrough MBB and should return nullptr.
6245   MachineBasicBlock *FallthroughBB = nullptr;
6246   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
6247     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
6248       continue;
6249     // Return a nullptr if we found more than one fallthrough successor.
6250     if (FallthroughBB && FallthroughBB != TBB)
6251       return nullptr;
6252     FallthroughBB = *SI;
6253   }
6254   return FallthroughBB;
6255 }
6256 
6257 bool X86InstrInfo::AnalyzeBranchImpl(
6258     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
6259     SmallVectorImpl<MachineOperand> &Cond,
6260     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
6261 
6262   // Start from the bottom of the block and work up, examining the
6263   // terminator instructions.
6264   MachineBasicBlock::iterator I = MBB.end();
6265   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
6266   while (I != MBB.begin()) {
6267     --I;
6268     if (I->isDebugValue())
6269       continue;
6270 
6271     // Working from the bottom, when we see a non-terminator instruction, we're
6272     // done.
6273     if (!isUnpredicatedTerminator(*I))
6274       break;
6275 
6276     // A terminator that isn't a branch can't easily be handled by this
6277     // analysis.
6278     if (!I->isBranch())
6279       return true;
6280 
6281     // Handle unconditional branches.
6282     if (I->getOpcode() == X86::JMP_1) {
6283       UnCondBrIter = I;
6284 
6285       if (!AllowModify) {
6286         TBB = I->getOperand(0).getMBB();
6287         continue;
6288       }
6289 
6290       // If the block has any instructions after a JMP, delete them.
6291       while (std::next(I) != MBB.end())
6292         std::next(I)->eraseFromParent();
6293 
6294       Cond.clear();
6295       FBB = nullptr;
6296 
6297       // Delete the JMP if it's equivalent to a fall-through.
6298       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
6299         TBB = nullptr;
6300         I->eraseFromParent();
6301         I = MBB.end();
6302         UnCondBrIter = MBB.end();
6303         continue;
6304       }
6305 
6306       // TBB is used to indicate the unconditional destination.
6307       TBB = I->getOperand(0).getMBB();
6308       continue;
6309     }
6310 
6311     // Handle conditional branches.
6312     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
6313     if (BranchCode == X86::COND_INVALID)
6314       return true;  // Can't handle indirect branch.
6315 
6316     // Working from the bottom, handle the first conditional branch.
6317     if (Cond.empty()) {
6318       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
6319       if (AllowModify && UnCondBrIter != MBB.end() &&
6320           MBB.isLayoutSuccessor(TargetBB)) {
6321         // If we can modify the code and it ends in something like:
6322         //
6323         //     jCC L1
6324         //     jmp L2
6325         //   L1:
6326         //     ...
6327         //   L2:
6328         //
6329         // Then we can change this to:
6330         //
6331         //     jnCC L2
6332         //   L1:
6333         //     ...
6334         //   L2:
6335         //
6336         // Which is a bit more efficient.
6337         // We conditionally jump to the fall-through block.
6338         BranchCode = GetOppositeBranchCondition(BranchCode);
6339         unsigned JNCC = GetCondBranchFromCond(BranchCode);
6340         MachineBasicBlock::iterator OldInst = I;
6341 
6342         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
6343           .addMBB(UnCondBrIter->getOperand(0).getMBB());
6344         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
6345           .addMBB(TargetBB);
6346 
6347         OldInst->eraseFromParent();
6348         UnCondBrIter->eraseFromParent();
6349 
6350         // Restart the analysis.
6351         UnCondBrIter = MBB.end();
6352         I = MBB.end();
6353         continue;
6354       }
6355 
6356       FBB = TBB;
6357       TBB = I->getOperand(0).getMBB();
6358       Cond.push_back(MachineOperand::CreateImm(BranchCode));
6359       CondBranches.push_back(&*I);
6360       continue;
6361     }
6362 
6363     // Handle subsequent conditional branches. Only handle the case where all
6364     // conditional branches branch to the same destination and their condition
6365     // opcodes fit one of the special multi-branch idioms.
6366     assert(Cond.size() == 1);
6367     assert(TBB);
6368 
6369     // If the conditions are the same, we can leave them alone.
6370     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
6371     auto NewTBB = I->getOperand(0).getMBB();
6372     if (OldBranchCode == BranchCode && TBB == NewTBB)
6373       continue;
6374 
6375     // If they differ, see if they fit one of the known patterns. Theoretically,
6376     // we could handle more patterns here, but we shouldn't expect to see them
6377     // if instruction selection has done a reasonable job.
6378     if (TBB == NewTBB &&
6379                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
6380                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
6381       BranchCode = X86::COND_NE_OR_P;
6382     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
6383                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
6384       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
6385         return true;
6386 
6387       // X86::COND_E_AND_NP usually has two different branch destinations.
6388       //
6389       // JP B1
6390       // JE B2
6391       // JMP B1
6392       // B1:
6393       // B2:
6394       //
6395       // Here this condition branches to B2 only if NP && E. It has another
6396       // equivalent form:
6397       //
6398       // JNE B1
6399       // JNP B2
6400       // JMP B1
6401       // B1:
6402       // B2:
6403       //
6404       // Similarly it branches to B2 only if E && NP. That is why this condition
6405       // is named with COND_E_AND_NP.
6406       BranchCode = X86::COND_E_AND_NP;
6407     } else
6408       return true;
6409 
6410     // Update the MachineOperand.
6411     Cond[0].setImm(BranchCode);
6412     CondBranches.push_back(&*I);
6413   }
6414 
6415   return false;
6416 }
6417 
6418 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
6419                                  MachineBasicBlock *&TBB,
6420                                  MachineBasicBlock *&FBB,
6421                                  SmallVectorImpl<MachineOperand> &Cond,
6422                                  bool AllowModify) const {
6423   SmallVector<MachineInstr *, 4> CondBranches;
6424   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
6425 }
6426 
6427 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
6428                                           MachineBranchPredicate &MBP,
6429                                           bool AllowModify) const {
6430   using namespace std::placeholders;
6431 
6432   SmallVector<MachineOperand, 4> Cond;
6433   SmallVector<MachineInstr *, 4> CondBranches;
6434   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
6435                         AllowModify))
6436     return true;
6437 
6438   if (Cond.size() != 1)
6439     return true;
6440 
6441   assert(MBP.TrueDest && "expected!");
6442 
6443   if (!MBP.FalseDest)
6444     MBP.FalseDest = MBB.getNextNode();
6445 
6446   const TargetRegisterInfo *TRI = &getRegisterInfo();
6447 
6448   MachineInstr *ConditionDef = nullptr;
6449   bool SingleUseCondition = true;
6450 
6451   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
6452     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
6453       ConditionDef = &*I;
6454       break;
6455     }
6456 
6457     if (I->readsRegister(X86::EFLAGS, TRI))
6458       SingleUseCondition = false;
6459   }
6460 
6461   if (!ConditionDef)
6462     return true;
6463 
6464   if (SingleUseCondition) {
6465     for (auto *Succ : MBB.successors())
6466       if (Succ->isLiveIn(X86::EFLAGS))
6467         SingleUseCondition = false;
6468   }
6469 
6470   MBP.ConditionDef = ConditionDef;
6471   MBP.SingleUseCondition = SingleUseCondition;
6472 
6473   // Currently we only recognize the simple pattern:
6474   //
6475   //   test %reg, %reg
6476   //   je %label
6477   //
6478   const unsigned TestOpcode =
6479       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
6480 
6481   if (ConditionDef->getOpcode() == TestOpcode &&
6482       ConditionDef->getNumOperands() == 3 &&
6483       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
6484       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
6485     MBP.LHS = ConditionDef->getOperand(0);
6486     MBP.RHS = MachineOperand::CreateImm(0);
6487     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
6488                         ? MachineBranchPredicate::PRED_NE
6489                         : MachineBranchPredicate::PRED_EQ;
6490     return false;
6491   }
6492 
6493   return true;
6494 }
6495 
6496 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
6497                                     int *BytesRemoved) const {
6498   assert(!BytesRemoved && "code size not handled");
6499 
6500   MachineBasicBlock::iterator I = MBB.end();
6501   unsigned Count = 0;
6502 
6503   while (I != MBB.begin()) {
6504     --I;
6505     if (I->isDebugValue())
6506       continue;
6507     if (I->getOpcode() != X86::JMP_1 &&
6508         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
6509       break;
6510     // Remove the branch.
6511     I->eraseFromParent();
6512     I = MBB.end();
6513     ++Count;
6514   }
6515 
6516   return Count;
6517 }
6518 
6519 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
6520                                     MachineBasicBlock *TBB,
6521                                     MachineBasicBlock *FBB,
6522                                     ArrayRef<MachineOperand> Cond,
6523                                     const DebugLoc &DL,
6524                                     int *BytesAdded) const {
6525   // Shouldn't be a fall through.
6526   assert(TBB && "insertBranch must not be told to insert a fallthrough");
6527   assert((Cond.size() == 1 || Cond.size() == 0) &&
6528          "X86 branch conditions have one component!");
6529   assert(!BytesAdded && "code size not handled");
6530 
6531   if (Cond.empty()) {
6532     // Unconditional branch?
6533     assert(!FBB && "Unconditional branch with multiple successors!");
6534     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
6535     return 1;
6536   }
6537 
6538   // If FBB is null, it is implied to be a fall-through block.
6539   bool FallThru = FBB == nullptr;
6540 
6541   // Conditional branch.
6542   unsigned Count = 0;
6543   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
6544   switch (CC) {
6545   case X86::COND_NE_OR_P:
6546     // Synthesize NE_OR_P with two branches.
6547     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
6548     ++Count;
6549     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
6550     ++Count;
6551     break;
6552   case X86::COND_E_AND_NP:
6553     // Use the next block of MBB as FBB if it is null.
6554     if (FBB == nullptr) {
6555       FBB = getFallThroughMBB(&MBB, TBB);
6556       assert(FBB && "MBB cannot be the last block in function when the false "
6557                     "body is a fall-through.");
6558     }
6559     // Synthesize COND_E_AND_NP with two branches.
6560     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
6561     ++Count;
6562     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
6563     ++Count;
6564     break;
6565   default: {
6566     unsigned Opc = GetCondBranchFromCond(CC);
6567     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
6568     ++Count;
6569   }
6570   }
6571   if (!FallThru) {
6572     // Two-way Conditional branch. Insert the second branch.
6573     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
6574     ++Count;
6575   }
6576   return Count;
6577 }
6578 
6579 bool X86InstrInfo::
6580 canInsertSelect(const MachineBasicBlock &MBB,
6581                 ArrayRef<MachineOperand> Cond,
6582                 unsigned TrueReg, unsigned FalseReg,
6583                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
6584   // Not all subtargets have cmov instructions.
6585   if (!Subtarget.hasCMov())
6586     return false;
6587   if (Cond.size() != 1)
6588     return false;
6589   // We cannot do the composite conditions, at least not in SSA form.
6590   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
6591     return false;
6592 
6593   // Check register classes.
6594   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
6595   const TargetRegisterClass *RC =
6596     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
6597   if (!RC)
6598     return false;
6599 
6600   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
6601   if (X86::GR16RegClass.hasSubClassEq(RC) ||
6602       X86::GR32RegClass.hasSubClassEq(RC) ||
6603       X86::GR64RegClass.hasSubClassEq(RC)) {
6604     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
6605     // Bridge. Probably Ivy Bridge as well.
6606     CondCycles = 2;
6607     TrueCycles = 2;
6608     FalseCycles = 2;
6609     return true;
6610   }
6611 
6612   // Can't do vectors.
6613   return false;
6614 }
6615 
6616 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
6617                                 MachineBasicBlock::iterator I,
6618                                 const DebugLoc &DL, unsigned DstReg,
6619                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
6620                                 unsigned FalseReg) const {
6621   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
6622   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
6623   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
6624   assert(Cond.size() == 1 && "Invalid Cond array");
6625   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
6626                                  TRI.getRegSizeInBits(RC) / 8,
6627                                  false /*HasMemoryOperand*/);
6628   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
6629 }
6630 
6631 /// Test if the given register is a physical h register.
6632 static bool isHReg(unsigned Reg) {
6633   return X86::GR8_ABCD_HRegClass.contains(Reg);
6634 }
6635 
6636 // Try and copy between VR128/VR64 and GR64 registers.
6637 static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg,
6638                                         const X86Subtarget &Subtarget) {
6639   bool HasAVX = Subtarget.hasAVX();
6640   bool HasAVX512 = Subtarget.hasAVX512();
6641 
6642   // SrcReg(MaskReg) -> DestReg(GR64)
6643   // SrcReg(MaskReg) -> DestReg(GR32)
6644 
6645   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6646   if (X86::VK16RegClass.contains(SrcReg)) {
6647     if (X86::GR64RegClass.contains(DestReg)) {
6648       assert(Subtarget.hasBWI());
6649       return X86::KMOVQrk;
6650     }
6651     if (X86::GR32RegClass.contains(DestReg))
6652       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
6653   }
6654 
6655   // SrcReg(GR64) -> DestReg(MaskReg)
6656   // SrcReg(GR32) -> DestReg(MaskReg)
6657 
6658   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6659   if (X86::VK16RegClass.contains(DestReg)) {
6660     if (X86::GR64RegClass.contains(SrcReg)) {
6661       assert(Subtarget.hasBWI());
6662       return X86::KMOVQkr;
6663     }
6664     if (X86::GR32RegClass.contains(SrcReg))
6665       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
6666   }
6667 
6668 
6669   // SrcReg(VR128) -> DestReg(GR64)
6670   // SrcReg(VR64)  -> DestReg(GR64)
6671   // SrcReg(GR64)  -> DestReg(VR128)
6672   // SrcReg(GR64)  -> DestReg(VR64)
6673 
6674   if (X86::GR64RegClass.contains(DestReg)) {
6675     if (X86::VR128XRegClass.contains(SrcReg))
6676       // Copy from a VR128 register to a GR64 register.
6677       return HasAVX512 ? X86::VMOVPQIto64Zrr :
6678              HasAVX    ? X86::VMOVPQIto64rr  :
6679                          X86::MOVPQIto64rr;
6680     if (X86::VR64RegClass.contains(SrcReg))
6681       // Copy from a VR64 register to a GR64 register.
6682       return X86::MMX_MOVD64from64rr;
6683   } else if (X86::GR64RegClass.contains(SrcReg)) {
6684     // Copy from a GR64 register to a VR128 register.
6685     if (X86::VR128XRegClass.contains(DestReg))
6686       return HasAVX512 ? X86::VMOV64toPQIZrr :
6687              HasAVX    ? X86::VMOV64toPQIrr  :
6688                          X86::MOV64toPQIrr;
6689     // Copy from a GR64 register to a VR64 register.
6690     if (X86::VR64RegClass.contains(DestReg))
6691       return X86::MMX_MOVD64to64rr;
6692   }
6693 
6694   // SrcReg(FR32) -> DestReg(GR32)
6695   // SrcReg(GR32) -> DestReg(FR32)
6696 
6697   if (X86::GR32RegClass.contains(DestReg) &&
6698       X86::FR32XRegClass.contains(SrcReg))
6699     // Copy from a FR32 register to a GR32 register.
6700     return HasAVX512 ? X86::VMOVSS2DIZrr :
6701            HasAVX    ? X86::VMOVSS2DIrr  :
6702                        X86::MOVSS2DIrr;
6703 
6704   if (X86::FR32XRegClass.contains(DestReg) &&
6705       X86::GR32RegClass.contains(SrcReg))
6706     // Copy from a GR32 register to a FR32 register.
6707     return HasAVX512 ? X86::VMOVDI2SSZrr :
6708            HasAVX    ? X86::VMOVDI2SSrr  :
6709                        X86::MOVDI2SSrr;
6710   return 0;
6711 }
6712 
6713 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
6714                                MachineBasicBlock::iterator MI,
6715                                const DebugLoc &DL, unsigned DestReg,
6716                                unsigned SrcReg, bool KillSrc) const {
6717   // First deal with the normal symmetric copies.
6718   bool HasAVX = Subtarget.hasAVX();
6719   bool HasVLX = Subtarget.hasVLX();
6720   unsigned Opc = 0;
6721   if (X86::GR64RegClass.contains(DestReg, SrcReg))
6722     Opc = X86::MOV64rr;
6723   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
6724     Opc = X86::MOV32rr;
6725   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
6726     Opc = X86::MOV16rr;
6727   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
6728     // Copying to or from a physical H register on x86-64 requires a NOREX
6729     // move.  Otherwise use a normal move.
6730     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
6731         Subtarget.is64Bit()) {
6732       Opc = X86::MOV8rr_NOREX;
6733       // Both operands must be encodable without an REX prefix.
6734       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
6735              "8-bit H register can not be copied outside GR8_NOREX");
6736     } else
6737       Opc = X86::MOV8rr;
6738   }
6739   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
6740     Opc = X86::MMX_MOVQ64rr;
6741   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
6742     if (HasVLX)
6743       Opc = X86::VMOVAPSZ128rr;
6744     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
6745       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
6746     else {
6747       // If this an extended register and we don't have VLX we need to use a
6748       // 512-bit move.
6749       Opc = X86::VMOVAPSZrr;
6750       const TargetRegisterInfo *TRI = &getRegisterInfo();
6751       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
6752                                          &X86::VR512RegClass);
6753       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
6754                                         &X86::VR512RegClass);
6755     }
6756   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
6757     if (HasVLX)
6758       Opc = X86::VMOVAPSZ256rr;
6759     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
6760       Opc = X86::VMOVAPSYrr;
6761     else {
6762       // If this an extended register and we don't have VLX we need to use a
6763       // 512-bit move.
6764       Opc = X86::VMOVAPSZrr;
6765       const TargetRegisterInfo *TRI = &getRegisterInfo();
6766       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
6767                                          &X86::VR512RegClass);
6768       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
6769                                         &X86::VR512RegClass);
6770     }
6771   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
6772     Opc = X86::VMOVAPSZrr;
6773   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6774   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
6775     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
6776   if (!Opc)
6777     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
6778 
6779   if (Opc) {
6780     BuildMI(MBB, MI, DL, get(Opc), DestReg)
6781       .addReg(SrcReg, getKillRegState(KillSrc));
6782     return;
6783   }
6784 
6785   bool FromEFLAGS = SrcReg == X86::EFLAGS;
6786   bool ToEFLAGS = DestReg == X86::EFLAGS;
6787   int Reg = FromEFLAGS ? DestReg : SrcReg;
6788   bool is32 = X86::GR32RegClass.contains(Reg);
6789   bool is64 = X86::GR64RegClass.contains(Reg);
6790 
6791   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
6792     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
6793     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
6794     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
6795     int Pop = is64 ? X86::POP64r : X86::POP32r;
6796     int PopF = is64 ? X86::POPF64 : X86::POPF32;
6797     int AX = is64 ? X86::RAX : X86::EAX;
6798 
6799     if (!Subtarget.hasLAHFSAHF()) {
6800       assert(Subtarget.is64Bit() &&
6801              "Not having LAHF/SAHF only happens on 64-bit.");
6802       // Moving EFLAGS to / from another register requires a push and a pop.
6803       // Notice that we have to adjust the stack if we don't want to clobber the
6804       // first frame index. See X86FrameLowering.cpp - usesTheStack.
6805       if (FromEFLAGS) {
6806         BuildMI(MBB, MI, DL, get(PushF));
6807         BuildMI(MBB, MI, DL, get(Pop), DestReg);
6808       }
6809       if (ToEFLAGS) {
6810         BuildMI(MBB, MI, DL, get(Push))
6811             .addReg(SrcReg, getKillRegState(KillSrc));
6812         BuildMI(MBB, MI, DL, get(PopF));
6813       }
6814       return;
6815     }
6816 
6817     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
6818     // inefficient. Instead:
6819     //   - Save the overflow flag OF into AL using SETO, and restore it using a
6820     //     signed 8-bit addition of AL and INT8_MAX.
6821     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
6822     //     using LAHF/SAHF.
6823     //   - When RAX/EAX is live and isn't the destination register, make sure it
6824     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
6825     //     the flags.
6826     // This approach is ~2.25x faster than using PUSHF/POPF.
6827     //
6828     // This is still somewhat inefficient because we don't know which flags are
6829     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
6830     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
6831     //
6832     // PUSHF/POPF is also potentially incorrect because it affects other flags
6833     // such as TF/IF/DF, which LLVM doesn't model.
6834     //
6835     // Notice that we have to adjust the stack if we don't want to clobber the
6836     // first frame index.
6837     // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
6838 
6839     const TargetRegisterInfo &TRI = getRegisterInfo();
6840     MachineBasicBlock::LivenessQueryResult LQR =
6841         MBB.computeRegisterLiveness(&TRI, AX, MI);
6842     // We do not want to save and restore AX if we do not have to.
6843     // Moreover, if we do so whereas AX is dead, we would need to set
6844     // an undef flag on the use of AX, otherwise the verifier will
6845     // complain that we read an undef value.
6846     // We do not want to change the behavior of the machine verifier
6847     // as this is usually wrong to read an undef value.
6848     if (MachineBasicBlock::LQR_Unknown == LQR) {
6849       LivePhysRegs LPR(TRI);
6850       LPR.addLiveOuts(MBB);
6851       MachineBasicBlock::iterator I = MBB.end();
6852       while (I != MI) {
6853         --I;
6854         LPR.stepBackward(*I);
6855       }
6856       // AX contains the top most register in the aliasing hierarchy.
6857       // It may not be live, but one of its aliases may be.
6858       for (MCRegAliasIterator AI(AX, &TRI, true);
6859            AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
6860         LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
6861                                 : MachineBasicBlock::LQR_Dead;
6862     }
6863     bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
6864     if (!AXDead)
6865       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
6866     if (FromEFLAGS) {
6867       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
6868       BuildMI(MBB, MI, DL, get(X86::LAHF));
6869       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
6870     }
6871     if (ToEFLAGS) {
6872       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
6873       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
6874           .addReg(X86::AL)
6875           .addImm(INT8_MAX);
6876       BuildMI(MBB, MI, DL, get(X86::SAHF));
6877     }
6878     if (!AXDead)
6879       BuildMI(MBB, MI, DL, get(Pop), AX);
6880     return;
6881   }
6882 
6883   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
6884                << " to " << RI.getName(DestReg) << '\n');
6885   llvm_unreachable("Cannot emit physreg copy instruction");
6886 }
6887 
6888 static unsigned getLoadStoreRegOpcode(unsigned Reg,
6889                                       const TargetRegisterClass *RC,
6890                                       bool isStackAligned,
6891                                       const X86Subtarget &STI,
6892                                       bool load) {
6893   bool HasAVX = STI.hasAVX();
6894   bool HasAVX512 = STI.hasAVX512();
6895   bool HasVLX = STI.hasVLX();
6896 
6897   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
6898   default:
6899     llvm_unreachable("Unknown spill size");
6900   case 1:
6901     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
6902     if (STI.is64Bit())
6903       // Copying to or from a physical H register on x86-64 requires a NOREX
6904       // move.  Otherwise use a normal move.
6905       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
6906         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
6907     return load ? X86::MOV8rm : X86::MOV8mr;
6908   case 2:
6909     if (X86::VK16RegClass.hasSubClassEq(RC))
6910       return load ? X86::KMOVWkm : X86::KMOVWmk;
6911     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
6912     return load ? X86::MOV16rm : X86::MOV16mr;
6913   case 4:
6914     if (X86::GR32RegClass.hasSubClassEq(RC))
6915       return load ? X86::MOV32rm : X86::MOV32mr;
6916     if (X86::FR32XRegClass.hasSubClassEq(RC))
6917       return load ?
6918         (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
6919         (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
6920     if (X86::RFP32RegClass.hasSubClassEq(RC))
6921       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
6922     if (X86::VK32RegClass.hasSubClassEq(RC)) {
6923       assert(STI.hasBWI() && "KMOVD requires BWI");
6924       return load ? X86::KMOVDkm : X86::KMOVDmk;
6925     }
6926     llvm_unreachable("Unknown 4-byte regclass");
6927   case 8:
6928     if (X86::GR64RegClass.hasSubClassEq(RC))
6929       return load ? X86::MOV64rm : X86::MOV64mr;
6930     if (X86::FR64XRegClass.hasSubClassEq(RC))
6931       return load ?
6932         (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
6933         (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
6934     if (X86::VR64RegClass.hasSubClassEq(RC))
6935       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
6936     if (X86::RFP64RegClass.hasSubClassEq(RC))
6937       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
6938     if (X86::VK64RegClass.hasSubClassEq(RC)) {
6939       assert(STI.hasBWI() && "KMOVQ requires BWI");
6940       return load ? X86::KMOVQkm : X86::KMOVQmk;
6941     }
6942     llvm_unreachable("Unknown 8-byte regclass");
6943   case 10:
6944     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
6945     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
6946   case 16: {
6947     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
6948       // If stack is realigned we can use aligned stores.
6949       if (isStackAligned)
6950         return load ?
6951           (HasVLX    ? X86::VMOVAPSZ128rm :
6952            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
6953            HasAVX    ? X86::VMOVAPSrm :
6954                        X86::MOVAPSrm):
6955           (HasVLX    ? X86::VMOVAPSZ128mr :
6956            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
6957            HasAVX    ? X86::VMOVAPSmr :
6958                        X86::MOVAPSmr);
6959       else
6960         return load ?
6961           (HasVLX    ? X86::VMOVUPSZ128rm :
6962            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
6963            HasAVX    ? X86::VMOVUPSrm :
6964                        X86::MOVUPSrm):
6965           (HasVLX    ? X86::VMOVUPSZ128mr :
6966            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
6967            HasAVX    ? X86::VMOVUPSmr :
6968                        X86::MOVUPSmr);
6969     }
6970     if (X86::BNDRRegClass.hasSubClassEq(RC)) {
6971       if (STI.is64Bit())
6972         return load ? X86::BNDMOVRM64rm : X86::BNDMOVMR64mr;
6973       else
6974         return load ? X86::BNDMOVRM32rm : X86::BNDMOVMR32mr;
6975     }
6976     llvm_unreachable("Unknown 16-byte regclass");
6977   }
6978   case 32:
6979     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
6980     // If stack is realigned we can use aligned stores.
6981     if (isStackAligned)
6982       return load ?
6983         (HasVLX    ? X86::VMOVAPSZ256rm :
6984          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
6985                      X86::VMOVAPSYrm) :
6986         (HasVLX    ? X86::VMOVAPSZ256mr :
6987          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
6988                      X86::VMOVAPSYmr);
6989     else
6990       return load ?
6991         (HasVLX    ? X86::VMOVUPSZ256rm :
6992          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
6993                      X86::VMOVUPSYrm) :
6994         (HasVLX    ? X86::VMOVUPSZ256mr :
6995          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
6996                      X86::VMOVUPSYmr);
6997   case 64:
6998     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
6999     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
7000     if (isStackAligned)
7001       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
7002     else
7003       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
7004   }
7005 }
7006 
7007 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
7008                                          int64_t &Offset,
7009                                          const TargetRegisterInfo *TRI) const {
7010   const MCInstrDesc &Desc = MemOp.getDesc();
7011   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
7012   if (MemRefBegin < 0)
7013     return false;
7014 
7015   MemRefBegin += X86II::getOperandBias(Desc);
7016 
7017   MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
7018   if (!BaseMO.isReg()) // Can be an MO_FrameIndex
7019     return false;
7020 
7021   BaseReg = BaseMO.getReg();
7022   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
7023     return false;
7024 
7025   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
7026       X86::NoRegister)
7027     return false;
7028 
7029   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
7030 
7031   // Displacement can be symbolic
7032   if (!DispMO.isImm())
7033     return false;
7034 
7035   Offset = DispMO.getImm();
7036 
7037   return true;
7038 }
7039 
7040 static unsigned getStoreRegOpcode(unsigned SrcReg,
7041                                   const TargetRegisterClass *RC,
7042                                   bool isStackAligned,
7043                                   const X86Subtarget &STI) {
7044   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
7045 }
7046 
7047 
7048 static unsigned getLoadRegOpcode(unsigned DestReg,
7049                                  const TargetRegisterClass *RC,
7050                                  bool isStackAligned,
7051                                  const X86Subtarget &STI) {
7052   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
7053 }
7054 
7055 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
7056                                        MachineBasicBlock::iterator MI,
7057                                        unsigned SrcReg, bool isKill, int FrameIdx,
7058                                        const TargetRegisterClass *RC,
7059                                        const TargetRegisterInfo *TRI) const {
7060   const MachineFunction &MF = *MBB.getParent();
7061   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
7062          "Stack slot too small for store");
7063   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
7064   bool isAligned =
7065       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
7066       RI.canRealignStack(MF);
7067   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
7068   DebugLoc DL = MBB.findDebugLoc(MI);
7069   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
7070     .addReg(SrcReg, getKillRegState(isKill));
7071 }
7072 
7073 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
7074                                   bool isKill,
7075                                   SmallVectorImpl<MachineOperand> &Addr,
7076                                   const TargetRegisterClass *RC,
7077                                   MachineInstr::mmo_iterator MMOBegin,
7078                                   MachineInstr::mmo_iterator MMOEnd,
7079                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
7080   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7081   unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
7082   bool isAligned = MMOBegin != MMOEnd &&
7083                    (*MMOBegin)->getAlignment() >= Alignment;
7084   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
7085   DebugLoc DL;
7086   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
7087   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
7088     MIB.add(Addr[i]);
7089   MIB.addReg(SrcReg, getKillRegState(isKill));
7090   (*MIB).setMemRefs(MMOBegin, MMOEnd);
7091   NewMIs.push_back(MIB);
7092 }
7093 
7094 
7095 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
7096                                         MachineBasicBlock::iterator MI,
7097                                         unsigned DestReg, int FrameIdx,
7098                                         const TargetRegisterClass *RC,
7099                                         const TargetRegisterInfo *TRI) const {
7100   const MachineFunction &MF = *MBB.getParent();
7101   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
7102   bool isAligned =
7103       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
7104       RI.canRealignStack(MF);
7105   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
7106   DebugLoc DL = MBB.findDebugLoc(MI);
7107   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
7108 }
7109 
7110 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
7111                                  SmallVectorImpl<MachineOperand> &Addr,
7112                                  const TargetRegisterClass *RC,
7113                                  MachineInstr::mmo_iterator MMOBegin,
7114                                  MachineInstr::mmo_iterator MMOEnd,
7115                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
7116   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7117   unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
7118   bool isAligned = MMOBegin != MMOEnd &&
7119                    (*MMOBegin)->getAlignment() >= Alignment;
7120   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
7121   DebugLoc DL;
7122   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
7123   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
7124     MIB.add(Addr[i]);
7125   (*MIB).setMemRefs(MMOBegin, MMOEnd);
7126   NewMIs.push_back(MIB);
7127 }
7128 
7129 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
7130                                   unsigned &SrcReg2, int &CmpMask,
7131                                   int &CmpValue) const {
7132   switch (MI.getOpcode()) {
7133   default: break;
7134   case X86::CMP64ri32:
7135   case X86::CMP64ri8:
7136   case X86::CMP32ri:
7137   case X86::CMP32ri8:
7138   case X86::CMP16ri:
7139   case X86::CMP16ri8:
7140   case X86::CMP8ri:
7141     SrcReg = MI.getOperand(0).getReg();
7142     SrcReg2 = 0;
7143     if (MI.getOperand(1).isImm()) {
7144       CmpMask = ~0;
7145       CmpValue = MI.getOperand(1).getImm();
7146     } else {
7147       CmpMask = CmpValue = 0;
7148     }
7149     return true;
7150   // A SUB can be used to perform comparison.
7151   case X86::SUB64rm:
7152   case X86::SUB32rm:
7153   case X86::SUB16rm:
7154   case X86::SUB8rm:
7155     SrcReg = MI.getOperand(1).getReg();
7156     SrcReg2 = 0;
7157     CmpMask = 0;
7158     CmpValue = 0;
7159     return true;
7160   case X86::SUB64rr:
7161   case X86::SUB32rr:
7162   case X86::SUB16rr:
7163   case X86::SUB8rr:
7164     SrcReg = MI.getOperand(1).getReg();
7165     SrcReg2 = MI.getOperand(2).getReg();
7166     CmpMask = 0;
7167     CmpValue = 0;
7168     return true;
7169   case X86::SUB64ri32:
7170   case X86::SUB64ri8:
7171   case X86::SUB32ri:
7172   case X86::SUB32ri8:
7173   case X86::SUB16ri:
7174   case X86::SUB16ri8:
7175   case X86::SUB8ri:
7176     SrcReg = MI.getOperand(1).getReg();
7177     SrcReg2 = 0;
7178     if (MI.getOperand(2).isImm()) {
7179       CmpMask = ~0;
7180       CmpValue = MI.getOperand(2).getImm();
7181     } else {
7182       CmpMask = CmpValue = 0;
7183     }
7184     return true;
7185   case X86::CMP64rr:
7186   case X86::CMP32rr:
7187   case X86::CMP16rr:
7188   case X86::CMP8rr:
7189     SrcReg = MI.getOperand(0).getReg();
7190     SrcReg2 = MI.getOperand(1).getReg();
7191     CmpMask = 0;
7192     CmpValue = 0;
7193     return true;
7194   case X86::TEST8rr:
7195   case X86::TEST16rr:
7196   case X86::TEST32rr:
7197   case X86::TEST64rr:
7198     SrcReg = MI.getOperand(0).getReg();
7199     if (MI.getOperand(1).getReg() != SrcReg)
7200       return false;
7201     // Compare against zero.
7202     SrcReg2 = 0;
7203     CmpMask = ~0;
7204     CmpValue = 0;
7205     return true;
7206   }
7207   return false;
7208 }
7209 
7210 /// Check whether the first instruction, whose only
7211 /// purpose is to update flags, can be made redundant.
7212 /// CMPrr can be made redundant by SUBrr if the operands are the same.
7213 /// This function can be extended later on.
7214 /// SrcReg, SrcRegs: register operands for FlagI.
7215 /// ImmValue: immediate for FlagI if it takes an immediate.
7216 inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
7217                                         unsigned SrcReg2, int ImmMask,
7218                                         int ImmValue, MachineInstr &OI) {
7219   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
7220        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
7221        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
7222        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
7223       ((OI.getOperand(1).getReg() == SrcReg &&
7224         OI.getOperand(2).getReg() == SrcReg2) ||
7225        (OI.getOperand(1).getReg() == SrcReg2 &&
7226         OI.getOperand(2).getReg() == SrcReg)))
7227     return true;
7228 
7229   if (ImmMask != 0 &&
7230       ((FlagI.getOpcode() == X86::CMP64ri32 &&
7231         OI.getOpcode() == X86::SUB64ri32) ||
7232        (FlagI.getOpcode() == X86::CMP64ri8 &&
7233         OI.getOpcode() == X86::SUB64ri8) ||
7234        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
7235        (FlagI.getOpcode() == X86::CMP32ri8 &&
7236         OI.getOpcode() == X86::SUB32ri8) ||
7237        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
7238        (FlagI.getOpcode() == X86::CMP16ri8 &&
7239         OI.getOpcode() == X86::SUB16ri8) ||
7240        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
7241       OI.getOperand(1).getReg() == SrcReg &&
7242       OI.getOperand(2).getImm() == ImmValue)
7243     return true;
7244   return false;
7245 }
7246 
7247 /// Check whether the definition can be converted
7248 /// to remove a comparison against zero.
7249 inline static bool isDefConvertible(MachineInstr &MI) {
7250   switch (MI.getOpcode()) {
7251   default: return false;
7252 
7253   // The shift instructions only modify ZF if their shift count is non-zero.
7254   // N.B.: The processor truncates the shift count depending on the encoding.
7255   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
7256   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
7257      return getTruncatedShiftCount(MI, 2) != 0;
7258 
7259   // Some left shift instructions can be turned into LEA instructions but only
7260   // if their flags aren't used. Avoid transforming such instructions.
7261   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
7262     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
7263     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
7264     return ShAmt != 0;
7265   }
7266 
7267   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
7268   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
7269      return getTruncatedShiftCount(MI, 3) != 0;
7270 
7271   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
7272   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
7273   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
7274   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
7275   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
7276   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
7277   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
7278   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
7279   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
7280   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
7281   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
7282   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
7283   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
7284   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
7285   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
7286   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
7287   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
7288   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
7289   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
7290   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
7291   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
7292   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
7293   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
7294   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
7295   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
7296   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
7297   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
7298   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
7299   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
7300   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
7301   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
7302   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
7303   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
7304   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
7305   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
7306   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
7307   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
7308   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
7309   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
7310   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
7311   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
7312   case X86::ANDN32rr:  case X86::ANDN32rm:
7313   case X86::ANDN64rr:  case X86::ANDN64rm:
7314   case X86::BEXTR32rr: case X86::BEXTR64rr:
7315   case X86::BEXTR32rm: case X86::BEXTR64rm:
7316   case X86::BLSI32rr:  case X86::BLSI32rm:
7317   case X86::BLSI64rr:  case X86::BLSI64rm:
7318   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
7319   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
7320   case X86::BLSR32rr:  case X86::BLSR32rm:
7321   case X86::BLSR64rr:  case X86::BLSR64rm:
7322   case X86::BZHI32rr:  case X86::BZHI32rm:
7323   case X86::BZHI64rr:  case X86::BZHI64rm:
7324   case X86::LZCNT16rr: case X86::LZCNT16rm:
7325   case X86::LZCNT32rr: case X86::LZCNT32rm:
7326   case X86::LZCNT64rr: case X86::LZCNT64rm:
7327   case X86::POPCNT16rr:case X86::POPCNT16rm:
7328   case X86::POPCNT32rr:case X86::POPCNT32rm:
7329   case X86::POPCNT64rr:case X86::POPCNT64rm:
7330   case X86::TZCNT16rr: case X86::TZCNT16rm:
7331   case X86::TZCNT32rr: case X86::TZCNT32rm:
7332   case X86::TZCNT64rr: case X86::TZCNT64rm:
7333   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
7334   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
7335   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
7336   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
7337   case X86::BLCI32rr:    case X86::BLCI32rm:
7338   case X86::BLCI64rr:    case X86::BLCI64rm:
7339   case X86::BLCIC32rr:   case X86::BLCIC32rm:
7340   case X86::BLCIC64rr:   case X86::BLCIC64rm:
7341   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
7342   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
7343   case X86::BLCS32rr:    case X86::BLCS32rm:
7344   case X86::BLCS64rr:    case X86::BLCS64rm:
7345   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
7346   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
7347   case X86::BLSIC32rr:   case X86::BLSIC32rm:
7348   case X86::BLSIC64rr:   case X86::BLSIC64rm:
7349     return true;
7350   }
7351 }
7352 
7353 /// Check whether the use can be converted to remove a comparison against zero.
7354 static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
7355   switch (MI.getOpcode()) {
7356   default: return X86::COND_INVALID;
7357   case X86::LZCNT16rr: case X86::LZCNT16rm:
7358   case X86::LZCNT32rr: case X86::LZCNT32rm:
7359   case X86::LZCNT64rr: case X86::LZCNT64rm:
7360     return X86::COND_B;
7361   case X86::POPCNT16rr:case X86::POPCNT16rm:
7362   case X86::POPCNT32rr:case X86::POPCNT32rm:
7363   case X86::POPCNT64rr:case X86::POPCNT64rm:
7364     return X86::COND_E;
7365   case X86::TZCNT16rr: case X86::TZCNT16rm:
7366   case X86::TZCNT32rr: case X86::TZCNT32rm:
7367   case X86::TZCNT64rr: case X86::TZCNT64rm:
7368     return X86::COND_B;
7369   }
7370 }
7371 
7372 /// Check if there exists an earlier instruction that
7373 /// operates on the same source operands and sets flags in the same way as
7374 /// Compare; remove Compare if possible.
7375 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
7376                                         unsigned SrcReg2, int CmpMask,
7377                                         int CmpValue,
7378                                         const MachineRegisterInfo *MRI) const {
7379   // Check whether we can replace SUB with CMP.
7380   unsigned NewOpcode = 0;
7381   switch (CmpInstr.getOpcode()) {
7382   default: break;
7383   case X86::SUB64ri32:
7384   case X86::SUB64ri8:
7385   case X86::SUB32ri:
7386   case X86::SUB32ri8:
7387   case X86::SUB16ri:
7388   case X86::SUB16ri8:
7389   case X86::SUB8ri:
7390   case X86::SUB64rm:
7391   case X86::SUB32rm:
7392   case X86::SUB16rm:
7393   case X86::SUB8rm:
7394   case X86::SUB64rr:
7395   case X86::SUB32rr:
7396   case X86::SUB16rr:
7397   case X86::SUB8rr: {
7398     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
7399       return false;
7400     // There is no use of the destination register, we can replace SUB with CMP.
7401     switch (CmpInstr.getOpcode()) {
7402     default: llvm_unreachable("Unreachable!");
7403     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
7404     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
7405     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
7406     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
7407     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
7408     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
7409     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
7410     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
7411     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
7412     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
7413     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
7414     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
7415     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
7416     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
7417     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
7418     }
7419     CmpInstr.setDesc(get(NewOpcode));
7420     CmpInstr.RemoveOperand(0);
7421     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
7422     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
7423         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
7424       return false;
7425   }
7426   }
7427 
7428   // Get the unique definition of SrcReg.
7429   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
7430   if (!MI) return false;
7431 
7432   // CmpInstr is the first instruction of the BB.
7433   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
7434 
7435   // If we are comparing against zero, check whether we can use MI to update
7436   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
7437   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
7438   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
7439     return false;
7440 
7441   // If we have a use of the source register between the def and our compare
7442   // instruction we can eliminate the compare iff the use sets EFLAGS in the
7443   // right way.
7444   bool ShouldUpdateCC = false;
7445   X86::CondCode NewCC = X86::COND_INVALID;
7446   if (IsCmpZero && !isDefConvertible(*MI)) {
7447     // Scan forward from the use until we hit the use we're looking for or the
7448     // compare instruction.
7449     for (MachineBasicBlock::iterator J = MI;; ++J) {
7450       // Do we have a convertible instruction?
7451       NewCC = isUseDefConvertible(*J);
7452       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
7453           J->getOperand(1).getReg() == SrcReg) {
7454         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
7455         ShouldUpdateCC = true; // Update CC later on.
7456         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
7457         // with the new def.
7458         Def = J;
7459         MI = &*Def;
7460         break;
7461       }
7462 
7463       if (J == I)
7464         return false;
7465     }
7466   }
7467 
7468   // We are searching for an earlier instruction that can make CmpInstr
7469   // redundant and that instruction will be saved in Sub.
7470   MachineInstr *Sub = nullptr;
7471   const TargetRegisterInfo *TRI = &getRegisterInfo();
7472 
7473   // We iterate backward, starting from the instruction before CmpInstr and
7474   // stop when reaching the definition of a source register or done with the BB.
7475   // RI points to the instruction before CmpInstr.
7476   // If the definition is in this basic block, RE points to the definition;
7477   // otherwise, RE is the rend of the basic block.
7478   MachineBasicBlock::reverse_iterator
7479       RI = ++I.getReverse(),
7480       RE = CmpInstr.getParent() == MI->getParent()
7481                ? Def.getReverse() /* points to MI */
7482                : CmpInstr.getParent()->rend();
7483   MachineInstr *Movr0Inst = nullptr;
7484   for (; RI != RE; ++RI) {
7485     MachineInstr &Instr = *RI;
7486     // Check whether CmpInstr can be made redundant by the current instruction.
7487     if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
7488                                            CmpValue, Instr)) {
7489       Sub = &Instr;
7490       break;
7491     }
7492 
7493     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
7494         Instr.readsRegister(X86::EFLAGS, TRI)) {
7495       // This instruction modifies or uses EFLAGS.
7496 
7497       // MOV32r0 etc. are implemented with xor which clobbers condition code.
7498       // They are safe to move up, if the definition to EFLAGS is dead and
7499       // earlier instructions do not read or write EFLAGS.
7500       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
7501           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
7502         Movr0Inst = &Instr;
7503         continue;
7504       }
7505 
7506       // We can't remove CmpInstr.
7507       return false;
7508     }
7509   }
7510 
7511   // Return false if no candidates exist.
7512   if (!IsCmpZero && !Sub)
7513     return false;
7514 
7515   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
7516                     Sub->getOperand(2).getReg() == SrcReg);
7517 
7518   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
7519   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
7520   // If we are done with the basic block, we need to check whether EFLAGS is
7521   // live-out.
7522   bool IsSafe = false;
7523   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
7524   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
7525   for (++I; I != E; ++I) {
7526     const MachineInstr &Instr = *I;
7527     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
7528     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
7529     // We should check the usage if this instruction uses and updates EFLAGS.
7530     if (!UseEFLAGS && ModifyEFLAGS) {
7531       // It is safe to remove CmpInstr if EFLAGS is updated again.
7532       IsSafe = true;
7533       break;
7534     }
7535     if (!UseEFLAGS && !ModifyEFLAGS)
7536       continue;
7537 
7538     // EFLAGS is used by this instruction.
7539     X86::CondCode OldCC = X86::COND_INVALID;
7540     bool OpcIsSET = false;
7541     if (IsCmpZero || IsSwapped) {
7542       // We decode the condition code from opcode.
7543       if (Instr.isBranch())
7544         OldCC = getCondFromBranchOpc(Instr.getOpcode());
7545       else {
7546         OldCC = getCondFromSETOpc(Instr.getOpcode());
7547         if (OldCC != X86::COND_INVALID)
7548           OpcIsSET = true;
7549         else
7550           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
7551       }
7552       if (OldCC == X86::COND_INVALID) return false;
7553     }
7554     X86::CondCode ReplacementCC = X86::COND_INVALID;
7555     if (IsCmpZero) {
7556       switch (OldCC) {
7557       default: break;
7558       case X86::COND_A: case X86::COND_AE:
7559       case X86::COND_B: case X86::COND_BE:
7560       case X86::COND_G: case X86::COND_GE:
7561       case X86::COND_L: case X86::COND_LE:
7562       case X86::COND_O: case X86::COND_NO:
7563         // CF and OF are used, we can't perform this optimization.
7564         return false;
7565       }
7566 
7567       // If we're updating the condition code check if we have to reverse the
7568       // condition.
7569       if (ShouldUpdateCC)
7570         switch (OldCC) {
7571         default:
7572           return false;
7573         case X86::COND_E:
7574           ReplacementCC = NewCC;
7575           break;
7576         case X86::COND_NE:
7577           ReplacementCC = GetOppositeBranchCondition(NewCC);
7578           break;
7579         }
7580     } else if (IsSwapped) {
7581       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
7582       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
7583       // We swap the condition code and synthesize the new opcode.
7584       ReplacementCC = getSwappedCondition(OldCC);
7585       if (ReplacementCC == X86::COND_INVALID) return false;
7586     }
7587 
7588     if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
7589       // Synthesize the new opcode.
7590       bool HasMemoryOperand = Instr.hasOneMemOperand();
7591       unsigned NewOpc;
7592       if (Instr.isBranch())
7593         NewOpc = GetCondBranchFromCond(ReplacementCC);
7594       else if(OpcIsSET)
7595         NewOpc = getSETFromCond(ReplacementCC, HasMemoryOperand);
7596       else {
7597         unsigned DstReg = Instr.getOperand(0).getReg();
7598         const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
7599         NewOpc = getCMovFromCond(ReplacementCC, TRI->getRegSizeInBits(*DstRC)/8,
7600                                  HasMemoryOperand);
7601       }
7602 
7603       // Push the MachineInstr to OpsToUpdate.
7604       // If it is safe to remove CmpInstr, the condition code of these
7605       // instructions will be modified.
7606       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
7607     }
7608     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
7609       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
7610       IsSafe = true;
7611       break;
7612     }
7613   }
7614 
7615   // If EFLAGS is not killed nor re-defined, we should check whether it is
7616   // live-out. If it is live-out, do not optimize.
7617   if ((IsCmpZero || IsSwapped) && !IsSafe) {
7618     MachineBasicBlock *MBB = CmpInstr.getParent();
7619     for (MachineBasicBlock *Successor : MBB->successors())
7620       if (Successor->isLiveIn(X86::EFLAGS))
7621         return false;
7622   }
7623 
7624   // The instruction to be updated is either Sub or MI.
7625   Sub = IsCmpZero ? MI : Sub;
7626   // Move Movr0Inst to the appropriate place before Sub.
7627   if (Movr0Inst) {
7628     // Look backwards until we find a def that doesn't use the current EFLAGS.
7629     Def = Sub;
7630     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
7631                                         InsertE = Sub->getParent()->rend();
7632     for (; InsertI != InsertE; ++InsertI) {
7633       MachineInstr *Instr = &*InsertI;
7634       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
7635           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
7636         Sub->getParent()->remove(Movr0Inst);
7637         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
7638                                    Movr0Inst);
7639         break;
7640       }
7641     }
7642     if (InsertI == InsertE)
7643       return false;
7644   }
7645 
7646   // Make sure Sub instruction defines EFLAGS and mark the def live.
7647   unsigned i = 0, e = Sub->getNumOperands();
7648   for (; i != e; ++i) {
7649     MachineOperand &MO = Sub->getOperand(i);
7650     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
7651       MO.setIsDead(false);
7652       break;
7653     }
7654   }
7655   assert(i != e && "Unable to locate a def EFLAGS operand");
7656 
7657   CmpInstr.eraseFromParent();
7658 
7659   // Modify the condition code of instructions in OpsToUpdate.
7660   for (auto &Op : OpsToUpdate)
7661     Op.first->setDesc(get(Op.second));
7662   return true;
7663 }
7664 
7665 /// Try to remove the load by folding it to a register
7666 /// operand at the use. We fold the load instructions if load defines a virtual
7667 /// register, the virtual register is used once in the same BB, and the
7668 /// instructions in-between do not load or store, and have no side effects.
7669 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
7670                                               const MachineRegisterInfo *MRI,
7671                                               unsigned &FoldAsLoadDefReg,
7672                                               MachineInstr *&DefMI) const {
7673   // Check whether we can move DefMI here.
7674   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
7675   assert(DefMI);
7676   bool SawStore = false;
7677   if (!DefMI->isSafeToMove(nullptr, SawStore))
7678     return nullptr;
7679 
7680   // Collect information about virtual register operands of MI.
7681   SmallVector<unsigned, 1> SrcOperandIds;
7682   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
7683     MachineOperand &MO = MI.getOperand(i);
7684     if (!MO.isReg())
7685       continue;
7686     unsigned Reg = MO.getReg();
7687     if (Reg != FoldAsLoadDefReg)
7688       continue;
7689     // Do not fold if we have a subreg use or a def.
7690     if (MO.getSubReg() || MO.isDef())
7691       return nullptr;
7692     SrcOperandIds.push_back(i);
7693   }
7694   if (SrcOperandIds.empty())
7695     return nullptr;
7696 
7697   // Check whether we can fold the def into SrcOperandId.
7698   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
7699     FoldAsLoadDefReg = 0;
7700     return FoldMI;
7701   }
7702 
7703   return nullptr;
7704 }
7705 
7706 /// Expand a single-def pseudo instruction to a two-addr
7707 /// instruction with two undef reads of the register being defined.
7708 /// This is used for mapping:
7709 ///   %xmm4 = V_SET0
7710 /// to:
7711 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
7712 ///
7713 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
7714                              const MCInstrDesc &Desc) {
7715   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
7716   unsigned Reg = MIB->getOperand(0).getReg();
7717   MIB->setDesc(Desc);
7718 
7719   // MachineInstr::addOperand() will insert explicit operands before any
7720   // implicit operands.
7721   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
7722   // But we don't trust that.
7723   assert(MIB->getOperand(1).getReg() == Reg &&
7724          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
7725   return true;
7726 }
7727 
7728 /// Expand a single-def pseudo instruction to a two-addr
7729 /// instruction with two %k0 reads.
7730 /// This is used for mapping:
7731 ///   %k4 = K_SET1
7732 /// to:
7733 ///   %k4 = KXNORrr %k0, %k0
7734 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
7735                             const MCInstrDesc &Desc, unsigned Reg) {
7736   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
7737   MIB->setDesc(Desc);
7738   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
7739   return true;
7740 }
7741 
7742 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
7743                           bool MinusOne) {
7744   MachineBasicBlock &MBB = *MIB->getParent();
7745   DebugLoc DL = MIB->getDebugLoc();
7746   unsigned Reg = MIB->getOperand(0).getReg();
7747 
7748   // Insert the XOR.
7749   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
7750       .addReg(Reg, RegState::Undef)
7751       .addReg(Reg, RegState::Undef);
7752 
7753   // Turn the pseudo into an INC or DEC.
7754   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
7755   MIB.addReg(Reg);
7756 
7757   return true;
7758 }
7759 
7760 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
7761                                const TargetInstrInfo &TII,
7762                                const X86Subtarget &Subtarget) {
7763   MachineBasicBlock &MBB = *MIB->getParent();
7764   DebugLoc DL = MIB->getDebugLoc();
7765   int64_t Imm = MIB->getOperand(1).getImm();
7766   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
7767   MachineBasicBlock::iterator I = MIB.getInstr();
7768 
7769   int StackAdjustment;
7770 
7771   if (Subtarget.is64Bit()) {
7772     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
7773            MIB->getOpcode() == X86::MOV32ImmSExti8);
7774 
7775     // Can't use push/pop lowering if the function might write to the red zone.
7776     X86MachineFunctionInfo *X86FI =
7777         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
7778     if (X86FI->getUsesRedZone()) {
7779       MIB->setDesc(TII.get(MIB->getOpcode() ==
7780                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
7781       return true;
7782     }
7783 
7784     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
7785     // widen the register if necessary.
7786     StackAdjustment = 8;
7787     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
7788     MIB->setDesc(TII.get(X86::POP64r));
7789     MIB->getOperand(0)
7790         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
7791   } else {
7792     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
7793     StackAdjustment = 4;
7794     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
7795     MIB->setDesc(TII.get(X86::POP32r));
7796   }
7797 
7798   // Build CFI if necessary.
7799   MachineFunction &MF = *MBB.getParent();
7800   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
7801   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
7802   bool NeedsDwarfCFI =
7803       !IsWin64Prologue &&
7804       (MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry());
7805   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
7806   if (EmitCFI) {
7807     TFL->BuildCFI(MBB, I, DL,
7808         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
7809     TFL->BuildCFI(MBB, std::next(I), DL,
7810         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
7811   }
7812 
7813   return true;
7814 }
7815 
7816 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
7817 // code sequence is needed for other targets.
7818 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
7819                                  const TargetInstrInfo &TII) {
7820   MachineBasicBlock &MBB = *MIB->getParent();
7821   DebugLoc DL = MIB->getDebugLoc();
7822   unsigned Reg = MIB->getOperand(0).getReg();
7823   const GlobalValue *GV =
7824       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
7825   auto Flags = MachineMemOperand::MOLoad |
7826                MachineMemOperand::MODereferenceable |
7827                MachineMemOperand::MOInvariant;
7828   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
7829       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
7830   MachineBasicBlock::iterator I = MIB.getInstr();
7831 
7832   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
7833       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
7834       .addMemOperand(MMO);
7835   MIB->setDebugLoc(DL);
7836   MIB->setDesc(TII.get(X86::MOV64rm));
7837   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
7838 }
7839 
7840 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
7841   MachineBasicBlock &MBB = *MIB->getParent();
7842   MachineFunction &MF = *MBB.getParent();
7843   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
7844   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
7845   unsigned XorOp =
7846       MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
7847   MIB->setDesc(TII.get(XorOp));
7848   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
7849   return true;
7850 }
7851 
7852 // This is used to handle spills for 128/256-bit registers when we have AVX512,
7853 // but not VLX. If it uses an extended register we need to use an instruction
7854 // that loads the lower 128/256-bit, but is available with only AVX512F.
7855 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
7856                             const TargetRegisterInfo *TRI,
7857                             const MCInstrDesc &LoadDesc,
7858                             const MCInstrDesc &BroadcastDesc,
7859                             unsigned SubIdx) {
7860   unsigned DestReg = MIB->getOperand(0).getReg();
7861   // Check if DestReg is XMM16-31 or YMM16-31.
7862   if (TRI->getEncodingValue(DestReg) < 16) {
7863     // We can use a normal VEX encoded load.
7864     MIB->setDesc(LoadDesc);
7865   } else {
7866     // Use a 128/256-bit VBROADCAST instruction.
7867     MIB->setDesc(BroadcastDesc);
7868     // Change the destination to a 512-bit register.
7869     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
7870     MIB->getOperand(0).setReg(DestReg);
7871   }
7872   return true;
7873 }
7874 
7875 // This is used to handle spills for 128/256-bit registers when we have AVX512,
7876 // but not VLX. If it uses an extended register we need to use an instruction
7877 // that stores the lower 128/256-bit, but is available with only AVX512F.
7878 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
7879                              const TargetRegisterInfo *TRI,
7880                              const MCInstrDesc &StoreDesc,
7881                              const MCInstrDesc &ExtractDesc,
7882                              unsigned SubIdx) {
7883   unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
7884   // Check if DestReg is XMM16-31 or YMM16-31.
7885   if (TRI->getEncodingValue(SrcReg) < 16) {
7886     // We can use a normal VEX encoded store.
7887     MIB->setDesc(StoreDesc);
7888   } else {
7889     // Use a VEXTRACTF instruction.
7890     MIB->setDesc(ExtractDesc);
7891     // Change the destination to a 512-bit register.
7892     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
7893     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
7894     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
7895   }
7896 
7897   return true;
7898 }
7899 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
7900   bool HasAVX = Subtarget.hasAVX();
7901   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
7902   switch (MI.getOpcode()) {
7903   case X86::MOV32r0:
7904     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
7905   case X86::MOV32r1:
7906     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
7907   case X86::MOV32r_1:
7908     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
7909   case X86::MOV32ImmSExti8:
7910   case X86::MOV64ImmSExti8:
7911     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
7912   case X86::SETB_C8r:
7913     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
7914   case X86::SETB_C16r:
7915     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
7916   case X86::SETB_C32r:
7917     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
7918   case X86::SETB_C64r:
7919     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
7920   case X86::MMX_SET0:
7921     return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
7922   case X86::V_SET0:
7923   case X86::FsFLD0SS:
7924   case X86::FsFLD0SD:
7925     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
7926   case X86::AVX_SET0: {
7927     assert(HasAVX && "AVX not supported");
7928     const TargetRegisterInfo *TRI = &getRegisterInfo();
7929     unsigned SrcReg = MIB->getOperand(0).getReg();
7930     unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
7931     MIB->getOperand(0).setReg(XReg);
7932     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
7933     MIB.addReg(SrcReg, RegState::ImplicitDefine);
7934     return true;
7935   }
7936   case X86::AVX512_128_SET0:
7937   case X86::AVX512_FsFLD0SS:
7938   case X86::AVX512_FsFLD0SD: {
7939     bool HasVLX = Subtarget.hasVLX();
7940     unsigned SrcReg = MIB->getOperand(0).getReg();
7941     const TargetRegisterInfo *TRI = &getRegisterInfo();
7942     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
7943       return Expand2AddrUndef(MIB,
7944                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
7945     // Extended register without VLX. Use a larger XOR.
7946     SrcReg =
7947         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
7948     MIB->getOperand(0).setReg(SrcReg);
7949     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7950   }
7951   case X86::AVX512_256_SET0:
7952   case X86::AVX512_512_SET0: {
7953     bool HasVLX = Subtarget.hasVLX();
7954     unsigned SrcReg = MIB->getOperand(0).getReg();
7955     const TargetRegisterInfo *TRI = &getRegisterInfo();
7956     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
7957       unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
7958       MIB->getOperand(0).setReg(XReg);
7959       Expand2AddrUndef(MIB,
7960                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
7961       MIB.addReg(SrcReg, RegState::ImplicitDefine);
7962       return true;
7963     }
7964     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7965   }
7966   case X86::V_SETALLONES:
7967     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
7968   case X86::AVX2_SETALLONES:
7969     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
7970   case X86::AVX1_SETALLONES: {
7971     unsigned Reg = MIB->getOperand(0).getReg();
7972     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
7973     MIB->setDesc(get(X86::VCMPPSYrri));
7974     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
7975     return true;
7976   }
7977   case X86::AVX512_512_SETALLONES: {
7978     unsigned Reg = MIB->getOperand(0).getReg();
7979     MIB->setDesc(get(X86::VPTERNLOGDZrri));
7980     // VPTERNLOGD needs 3 register inputs and an immediate.
7981     // 0xff will return 1s for any input.
7982     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
7983        .addReg(Reg, RegState::Undef).addImm(0xff);
7984     return true;
7985   }
7986   case X86::AVX512_512_SEXT_MASK_32:
7987   case X86::AVX512_512_SEXT_MASK_64: {
7988     unsigned Reg = MIB->getOperand(0).getReg();
7989     unsigned MaskReg = MIB->getOperand(1).getReg();
7990     unsigned MaskState = getRegState(MIB->getOperand(1));
7991     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
7992                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
7993     MI.RemoveOperand(1);
7994     MIB->setDesc(get(Opc));
7995     // VPTERNLOG needs 3 register inputs and an immediate.
7996     // 0xff will return 1s for any input.
7997     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
7998        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
7999     return true;
8000   }
8001   case X86::VMOVAPSZ128rm_NOVLX:
8002     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
8003                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
8004   case X86::VMOVUPSZ128rm_NOVLX:
8005     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
8006                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
8007   case X86::VMOVAPSZ256rm_NOVLX:
8008     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
8009                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
8010   case X86::VMOVUPSZ256rm_NOVLX:
8011     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
8012                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
8013   case X86::VMOVAPSZ128mr_NOVLX:
8014     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
8015                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
8016   case X86::VMOVUPSZ128mr_NOVLX:
8017     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
8018                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
8019   case X86::VMOVAPSZ256mr_NOVLX:
8020     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
8021                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
8022   case X86::VMOVUPSZ256mr_NOVLX:
8023     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
8024                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
8025   case X86::MOV32ri64:
8026     MI.setDesc(get(X86::MOV32ri));
8027     return true;
8028 
8029   // KNL does not recognize dependency-breaking idioms for mask registers,
8030   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
8031   // Using %k0 as the undef input register is a performance heuristic based
8032   // on the assumption that %k0 is used less frequently than the other mask
8033   // registers, since it is not usable as a write mask.
8034   // FIXME: A more advanced approach would be to choose the best input mask
8035   // register based on context.
8036   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
8037   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
8038   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
8039   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
8040   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
8041   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
8042   case TargetOpcode::LOAD_STACK_GUARD:
8043     expandLoadStackGuard(MIB, *this);
8044     return true;
8045   case X86::XOR64_FP:
8046   case X86::XOR32_FP:
8047     return expandXorFP(MIB, *this);
8048   }
8049   return false;
8050 }
8051 
8052 /// Return true for all instructions that only update
8053 /// the first 32 or 64-bits of the destination register and leave the rest
8054 /// unmodified. This can be used to avoid folding loads if the instructions
8055 /// only update part of the destination register, and the non-updated part is
8056 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
8057 /// instructions breaks the partial register dependency and it can improve
8058 /// performance. e.g.:
8059 ///
8060 ///   movss (%rdi), %xmm0
8061 ///   cvtss2sd %xmm0, %xmm0
8062 ///
8063 /// Instead of
8064 ///   cvtss2sd (%rdi), %xmm0
8065 ///
8066 /// FIXME: This should be turned into a TSFlags.
8067 ///
8068 static bool hasPartialRegUpdate(unsigned Opcode,
8069                                 const X86Subtarget &Subtarget) {
8070   switch (Opcode) {
8071   case X86::CVTSI2SSrr:
8072   case X86::CVTSI2SSrm:
8073   case X86::CVTSI642SSrr:
8074   case X86::CVTSI642SSrm:
8075   case X86::CVTSI2SDrr:
8076   case X86::CVTSI2SDrm:
8077   case X86::CVTSI642SDrr:
8078   case X86::CVTSI642SDrm:
8079   case X86::CVTSD2SSrr:
8080   case X86::CVTSD2SSrm:
8081   case X86::CVTSS2SDrr:
8082   case X86::CVTSS2SDrm:
8083   case X86::MOVHPDrm:
8084   case X86::MOVHPSrm:
8085   case X86::MOVLPDrm:
8086   case X86::MOVLPSrm:
8087   case X86::RCPSSr:
8088   case X86::RCPSSm:
8089   case X86::RCPSSr_Int:
8090   case X86::RCPSSm_Int:
8091   case X86::ROUNDSDr:
8092   case X86::ROUNDSDm:
8093   case X86::ROUNDSSr:
8094   case X86::ROUNDSSm:
8095   case X86::RSQRTSSr:
8096   case X86::RSQRTSSm:
8097   case X86::RSQRTSSr_Int:
8098   case X86::RSQRTSSm_Int:
8099   case X86::SQRTSSr:
8100   case X86::SQRTSSm:
8101   case X86::SQRTSSr_Int:
8102   case X86::SQRTSSm_Int:
8103   case X86::SQRTSDr:
8104   case X86::SQRTSDm:
8105   case X86::SQRTSDr_Int:
8106   case X86::SQRTSDm_Int:
8107     return true;
8108   // GPR
8109   case X86::POPCNT32rm:
8110   case X86::POPCNT32rr:
8111   case X86::POPCNT64rm:
8112   case X86::POPCNT64rr:
8113     return Subtarget.hasPOPCNTFalseDeps();
8114   case X86::LZCNT32rm:
8115   case X86::LZCNT32rr:
8116   case X86::LZCNT64rm:
8117   case X86::LZCNT64rr:
8118   case X86::TZCNT32rm:
8119   case X86::TZCNT32rr:
8120   case X86::TZCNT64rm:
8121   case X86::TZCNT64rr:
8122     return Subtarget.hasLZCNTFalseDeps();
8123   }
8124 
8125   return false;
8126 }
8127 
8128 /// Inform the BreakFalseDeps pass how many idle
8129 /// instructions we would like before a partial register update.
8130 unsigned X86InstrInfo::getPartialRegUpdateClearance(
8131     const MachineInstr &MI, unsigned OpNum,
8132     const TargetRegisterInfo *TRI) const {
8133   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
8134     return 0;
8135 
8136   // If MI is marked as reading Reg, the partial register update is wanted.
8137   const MachineOperand &MO = MI.getOperand(0);
8138   unsigned Reg = MO.getReg();
8139   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
8140     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
8141       return 0;
8142   } else {
8143     if (MI.readsRegister(Reg, TRI))
8144       return 0;
8145   }
8146 
8147   // If any instructions in the clearance range are reading Reg, insert a
8148   // dependency breaking instruction, which is inexpensive and is likely to
8149   // be hidden in other instruction's cycles.
8150   return PartialRegUpdateClearance;
8151 }
8152 
8153 // Return true for any instruction the copies the high bits of the first source
8154 // operand into the unused high bits of the destination operand.
8155 static bool hasUndefRegUpdate(unsigned Opcode) {
8156   switch (Opcode) {
8157   case X86::VCVTSI2SSrr:
8158   case X86::VCVTSI2SSrm:
8159   case X86::VCVTSI2SSrr_Int:
8160   case X86::VCVTSI2SSrm_Int:
8161   case X86::VCVTSI642SSrr:
8162   case X86::VCVTSI642SSrm:
8163   case X86::VCVTSI642SSrr_Int:
8164   case X86::VCVTSI642SSrm_Int:
8165   case X86::VCVTSI2SDrr:
8166   case X86::VCVTSI2SDrm:
8167   case X86::VCVTSI2SDrr_Int:
8168   case X86::VCVTSI2SDrm_Int:
8169   case X86::VCVTSI642SDrr:
8170   case X86::VCVTSI642SDrm:
8171   case X86::VCVTSI642SDrr_Int:
8172   case X86::VCVTSI642SDrm_Int:
8173   case X86::VCVTSD2SSrr:
8174   case X86::VCVTSD2SSrm:
8175   case X86::VCVTSD2SSrr_Int:
8176   case X86::VCVTSD2SSrm_Int:
8177   case X86::VCVTSS2SDrr:
8178   case X86::VCVTSS2SDrm:
8179   case X86::VCVTSS2SDrr_Int:
8180   case X86::VCVTSS2SDrm_Int:
8181   case X86::VRCPSSr:
8182   case X86::VRCPSSr_Int:
8183   case X86::VRCPSSm:
8184   case X86::VRCPSSm_Int:
8185   case X86::VROUNDSDr:
8186   case X86::VROUNDSDm:
8187   case X86::VROUNDSDr_Int:
8188   case X86::VROUNDSDm_Int:
8189   case X86::VROUNDSSr:
8190   case X86::VROUNDSSm:
8191   case X86::VROUNDSSr_Int:
8192   case X86::VROUNDSSm_Int:
8193   case X86::VRSQRTSSr:
8194   case X86::VRSQRTSSr_Int:
8195   case X86::VRSQRTSSm:
8196   case X86::VRSQRTSSm_Int:
8197   case X86::VSQRTSSr:
8198   case X86::VSQRTSSr_Int:
8199   case X86::VSQRTSSm:
8200   case X86::VSQRTSSm_Int:
8201   case X86::VSQRTSDr:
8202   case X86::VSQRTSDr_Int:
8203   case X86::VSQRTSDm:
8204   case X86::VSQRTSDm_Int:
8205   // AVX-512
8206   case X86::VCVTSI2SSZrr:
8207   case X86::VCVTSI2SSZrm:
8208   case X86::VCVTSI2SSZrr_Int:
8209   case X86::VCVTSI2SSZrrb_Int:
8210   case X86::VCVTSI2SSZrm_Int:
8211   case X86::VCVTSI642SSZrr:
8212   case X86::VCVTSI642SSZrm:
8213   case X86::VCVTSI642SSZrr_Int:
8214   case X86::VCVTSI642SSZrrb_Int:
8215   case X86::VCVTSI642SSZrm_Int:
8216   case X86::VCVTSI2SDZrr:
8217   case X86::VCVTSI2SDZrm:
8218   case X86::VCVTSI2SDZrr_Int:
8219   case X86::VCVTSI2SDZrrb_Int:
8220   case X86::VCVTSI2SDZrm_Int:
8221   case X86::VCVTSI642SDZrr:
8222   case X86::VCVTSI642SDZrm:
8223   case X86::VCVTSI642SDZrr_Int:
8224   case X86::VCVTSI642SDZrrb_Int:
8225   case X86::VCVTSI642SDZrm_Int:
8226   case X86::VCVTUSI2SSZrr:
8227   case X86::VCVTUSI2SSZrm:
8228   case X86::VCVTUSI2SSZrr_Int:
8229   case X86::VCVTUSI2SSZrrb_Int:
8230   case X86::VCVTUSI2SSZrm_Int:
8231   case X86::VCVTUSI642SSZrr:
8232   case X86::VCVTUSI642SSZrm:
8233   case X86::VCVTUSI642SSZrr_Int:
8234   case X86::VCVTUSI642SSZrrb_Int:
8235   case X86::VCVTUSI642SSZrm_Int:
8236   case X86::VCVTUSI2SDZrr:
8237   case X86::VCVTUSI2SDZrm:
8238   case X86::VCVTUSI2SDZrr_Int:
8239   case X86::VCVTUSI2SDZrm_Int:
8240   case X86::VCVTUSI642SDZrr:
8241   case X86::VCVTUSI642SDZrm:
8242   case X86::VCVTUSI642SDZrr_Int:
8243   case X86::VCVTUSI642SDZrrb_Int:
8244   case X86::VCVTUSI642SDZrm_Int:
8245   case X86::VCVTSD2SSZrr:
8246   case X86::VCVTSD2SSZrr_Int:
8247   case X86::VCVTSD2SSZrrb_Int:
8248   case X86::VCVTSD2SSZrm:
8249   case X86::VCVTSD2SSZrm_Int:
8250   case X86::VCVTSS2SDZrr:
8251   case X86::VCVTSS2SDZrr_Int:
8252   case X86::VCVTSS2SDZrrb_Int:
8253   case X86::VCVTSS2SDZrm:
8254   case X86::VCVTSS2SDZrm_Int:
8255   case X86::VRNDSCALESDr:
8256   case X86::VRNDSCALESDr_Int:
8257   case X86::VRNDSCALESDrb_Int:
8258   case X86::VRNDSCALESDm:
8259   case X86::VRNDSCALESDm_Int:
8260   case X86::VRNDSCALESSr:
8261   case X86::VRNDSCALESSr_Int:
8262   case X86::VRNDSCALESSrb_Int:
8263   case X86::VRNDSCALESSm:
8264   case X86::VRNDSCALESSm_Int:
8265   case X86::VRCP14SSrr:
8266   case X86::VRCP14SSrm:
8267   case X86::VRSQRT14SSrr:
8268   case X86::VRSQRT14SSrm:
8269   case X86::VSQRTSSZr:
8270   case X86::VSQRTSSZr_Int:
8271   case X86::VSQRTSSZrb_Int:
8272   case X86::VSQRTSSZm:
8273   case X86::VSQRTSSZm_Int:
8274   case X86::VSQRTSDZr:
8275   case X86::VSQRTSDZr_Int:
8276   case X86::VSQRTSDZrb_Int:
8277   case X86::VSQRTSDZm:
8278   case X86::VSQRTSDZm_Int:
8279     return true;
8280   }
8281 
8282   return false;
8283 }
8284 
8285 /// Inform the BreakFalseDeps pass how many idle instructions we would like
8286 /// before certain undef register reads.
8287 ///
8288 /// This catches the VCVTSI2SD family of instructions:
8289 ///
8290 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
8291 ///
8292 /// We should to be careful *not* to catch VXOR idioms which are presumably
8293 /// handled specially in the pipeline:
8294 ///
8295 /// vxorps undef %xmm1, undef %xmm1, %xmm1
8296 ///
8297 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
8298 /// high bits that are passed-through are not live.
8299 unsigned
8300 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
8301                                    const TargetRegisterInfo *TRI) const {
8302   if (!hasUndefRegUpdate(MI.getOpcode()))
8303     return 0;
8304 
8305   // Set the OpNum parameter to the first source operand.
8306   OpNum = 1;
8307 
8308   const MachineOperand &MO = MI.getOperand(OpNum);
8309   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
8310     return UndefRegClearance;
8311   }
8312   return 0;
8313 }
8314 
8315 void X86InstrInfo::breakPartialRegDependency(
8316     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
8317   unsigned Reg = MI.getOperand(OpNum).getReg();
8318   // If MI kills this register, the false dependence is already broken.
8319   if (MI.killsRegister(Reg, TRI))
8320     return;
8321 
8322   if (X86::VR128RegClass.contains(Reg)) {
8323     // These instructions are all floating point domain, so xorps is the best
8324     // choice.
8325     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
8326     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
8327         .addReg(Reg, RegState::Undef)
8328         .addReg(Reg, RegState::Undef);
8329     MI.addRegisterKilled(Reg, TRI, true);
8330   } else if (X86::VR256RegClass.contains(Reg)) {
8331     // Use vxorps to clear the full ymm register.
8332     // It wants to read and write the xmm sub-register.
8333     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
8334     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
8335         .addReg(XReg, RegState::Undef)
8336         .addReg(XReg, RegState::Undef)
8337         .addReg(Reg, RegState::ImplicitDefine);
8338     MI.addRegisterKilled(Reg, TRI, true);
8339   } else if (X86::GR64RegClass.contains(Reg)) {
8340     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
8341     // as well.
8342     unsigned XReg = TRI->getSubReg(Reg, X86::sub_32bit);
8343     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
8344         .addReg(XReg, RegState::Undef)
8345         .addReg(XReg, RegState::Undef)
8346         .addReg(Reg, RegState::ImplicitDefine);
8347     MI.addRegisterKilled(Reg, TRI, true);
8348   } else if (X86::GR32RegClass.contains(Reg)) {
8349     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
8350         .addReg(Reg, RegState::Undef)
8351         .addReg(Reg, RegState::Undef);
8352     MI.addRegisterKilled(Reg, TRI, true);
8353   }
8354 }
8355 
8356 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
8357                         int PtrOffset = 0) {
8358   unsigned NumAddrOps = MOs.size();
8359 
8360   if (NumAddrOps < 4) {
8361     // FrameIndex only - add an immediate offset (whether its zero or not).
8362     for (unsigned i = 0; i != NumAddrOps; ++i)
8363       MIB.add(MOs[i]);
8364     addOffset(MIB, PtrOffset);
8365   } else {
8366     // General Memory Addressing - we need to add any offset to an existing
8367     // offset.
8368     assert(MOs.size() == 5 && "Unexpected memory operand list length");
8369     for (unsigned i = 0; i != NumAddrOps; ++i) {
8370       const MachineOperand &MO = MOs[i];
8371       if (i == 3 && PtrOffset != 0) {
8372         MIB.addDisp(MO, PtrOffset);
8373       } else {
8374         MIB.add(MO);
8375       }
8376     }
8377   }
8378 }
8379 
8380 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
8381                                      ArrayRef<MachineOperand> MOs,
8382                                      MachineBasicBlock::iterator InsertPt,
8383                                      MachineInstr &MI,
8384                                      const TargetInstrInfo &TII) {
8385   // Create the base instruction with the memory operand as the first part.
8386   // Omit the implicit operands, something BuildMI can't do.
8387   MachineInstr *NewMI =
8388       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
8389   MachineInstrBuilder MIB(MF, NewMI);
8390   addOperands(MIB, MOs);
8391 
8392   // Loop over the rest of the ri operands, converting them over.
8393   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
8394   for (unsigned i = 0; i != NumOps; ++i) {
8395     MachineOperand &MO = MI.getOperand(i + 2);
8396     MIB.add(MO);
8397   }
8398   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
8399     MachineOperand &MO = MI.getOperand(i);
8400     MIB.add(MO);
8401   }
8402 
8403   MachineBasicBlock *MBB = InsertPt->getParent();
8404   MBB->insert(InsertPt, NewMI);
8405 
8406   return MIB;
8407 }
8408 
8409 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
8410                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
8411                               MachineBasicBlock::iterator InsertPt,
8412                               MachineInstr &MI, const TargetInstrInfo &TII,
8413                               int PtrOffset = 0) {
8414   // Omit the implicit operands, something BuildMI can't do.
8415   MachineInstr *NewMI =
8416       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
8417   MachineInstrBuilder MIB(MF, NewMI);
8418 
8419   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
8420     MachineOperand &MO = MI.getOperand(i);
8421     if (i == OpNo) {
8422       assert(MO.isReg() && "Expected to fold into reg operand!");
8423       addOperands(MIB, MOs, PtrOffset);
8424     } else {
8425       MIB.add(MO);
8426     }
8427   }
8428 
8429   MachineBasicBlock *MBB = InsertPt->getParent();
8430   MBB->insert(InsertPt, NewMI);
8431 
8432   return MIB;
8433 }
8434 
8435 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
8436                                 ArrayRef<MachineOperand> MOs,
8437                                 MachineBasicBlock::iterator InsertPt,
8438                                 MachineInstr &MI) {
8439   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
8440                                     MI.getDebugLoc(), TII.get(Opcode));
8441   addOperands(MIB, MOs);
8442   return MIB.addImm(0);
8443 }
8444 
8445 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
8446     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
8447     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
8448     unsigned Size, unsigned Align) const {
8449   switch (MI.getOpcode()) {
8450   case X86::INSERTPSrr:
8451   case X86::VINSERTPSrr:
8452   case X86::VINSERTPSZrr:
8453     // Attempt to convert the load of inserted vector into a fold load
8454     // of a single float.
8455     if (OpNum == 2) {
8456       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
8457       unsigned ZMask = Imm & 15;
8458       unsigned DstIdx = (Imm >> 4) & 3;
8459       unsigned SrcIdx = (Imm >> 6) & 3;
8460 
8461       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8462       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
8463       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
8464       if (Size <= RCSize && 4 <= Align) {
8465         int PtrOffset = SrcIdx * 4;
8466         unsigned NewImm = (DstIdx << 4) | ZMask;
8467         unsigned NewOpCode =
8468             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
8469             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
8470                                                     X86::INSERTPSrm;
8471         MachineInstr *NewMI =
8472             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
8473         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
8474         return NewMI;
8475       }
8476     }
8477     break;
8478   case X86::MOVHLPSrr:
8479   case X86::VMOVHLPSrr:
8480   case X86::VMOVHLPSZrr:
8481     // Move the upper 64-bits of the second operand to the lower 64-bits.
8482     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
8483     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
8484     if (OpNum == 2) {
8485       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8486       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
8487       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
8488       if (Size <= RCSize && 8 <= Align) {
8489         unsigned NewOpCode =
8490             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
8491             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
8492                                                    X86::MOVLPSrm;
8493         MachineInstr *NewMI =
8494             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
8495         return NewMI;
8496       }
8497     }
8498     break;
8499   };
8500 
8501   return nullptr;
8502 }
8503 
8504 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
8505     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
8506     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
8507     unsigned Size, unsigned Align, bool AllowCommute) const {
8508   const DenseMap<unsigned,
8509                  std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
8510   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
8511   bool isTwoAddrFold = false;
8512 
8513   // For CPUs that favor the register form of a call or push,
8514   // do not fold loads into calls or pushes, unless optimizing for size
8515   // aggressively.
8516   if (isSlowTwoMemOps && !MF.getFunction().optForMinSize() &&
8517       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
8518        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
8519        MI.getOpcode() == X86::PUSH64r))
8520     return nullptr;
8521 
8522   // Avoid partial register update stalls unless optimizing for size.
8523   // TODO: we should block undef reg update as well.
8524   if (!MF.getFunction().optForSize() &&
8525       hasPartialRegUpdate(MI.getOpcode(), Subtarget))
8526     return nullptr;
8527 
8528   unsigned NumOps = MI.getDesc().getNumOperands();
8529   bool isTwoAddr =
8530       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
8531 
8532   // FIXME: AsmPrinter doesn't know how to handle
8533   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
8534   if (MI.getOpcode() == X86::ADD32ri &&
8535       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
8536     return nullptr;
8537 
8538   // GOTTPOFF relocation loads can only be folded into add instructions.
8539   // FIXME: Need to exclude other relocations that only support specific
8540   // instructions.
8541   if (MOs.size() == X86::AddrNumOperands &&
8542       MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
8543       MI.getOpcode() != X86::ADD64rr)
8544     return nullptr;
8545 
8546   MachineInstr *NewMI = nullptr;
8547 
8548   // Attempt to fold any custom cases we have.
8549   if (MachineInstr *CustomMI =
8550           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
8551     return CustomMI;
8552 
8553   // Folding a memory location into the two-address part of a two-address
8554   // instruction is different than folding it other places.  It requires
8555   // replacing the *two* registers with the memory location.
8556   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
8557       MI.getOperand(1).isReg() &&
8558       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
8559     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
8560     isTwoAddrFold = true;
8561   } else if (OpNum == 0) {
8562     if (MI.getOpcode() == X86::MOV32r0) {
8563       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
8564       if (NewMI)
8565         return NewMI;
8566     }
8567 
8568     OpcodeTablePtr = &RegOp2MemOpTable0;
8569   } else if (OpNum == 1) {
8570     OpcodeTablePtr = &RegOp2MemOpTable1;
8571   } else if (OpNum == 2) {
8572     OpcodeTablePtr = &RegOp2MemOpTable2;
8573   } else if (OpNum == 3) {
8574     OpcodeTablePtr = &RegOp2MemOpTable3;
8575   } else if (OpNum == 4) {
8576     OpcodeTablePtr = &RegOp2MemOpTable4;
8577   }
8578 
8579   // If table selected...
8580   if (OpcodeTablePtr) {
8581     // Find the Opcode to fuse
8582     auto I = OpcodeTablePtr->find(MI.getOpcode());
8583     if (I != OpcodeTablePtr->end()) {
8584       unsigned Opcode = I->second.first;
8585       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
8586       if (Align < MinAlign)
8587         return nullptr;
8588       bool NarrowToMOV32rm = false;
8589       if (Size) {
8590         const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8591         const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
8592                                                     &RI, MF);
8593         unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
8594         if (Size < RCSize) {
8595           // Check if it's safe to fold the load. If the size of the object is
8596           // narrower than the load width, then it's not.
8597           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
8598             return nullptr;
8599           // If this is a 64-bit load, but the spill slot is 32, then we can do
8600           // a 32-bit load which is implicitly zero-extended. This likely is
8601           // due to live interval analysis remat'ing a load from stack slot.
8602           if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
8603             return nullptr;
8604           Opcode = X86::MOV32rm;
8605           NarrowToMOV32rm = true;
8606         }
8607       }
8608 
8609       if (isTwoAddrFold)
8610         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
8611       else
8612         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
8613 
8614       if (NarrowToMOV32rm) {
8615         // If this is the special case where we use a MOV32rm to load a 32-bit
8616         // value and zero-extend the top bits. Change the destination register
8617         // to a 32-bit one.
8618         unsigned DstReg = NewMI->getOperand(0).getReg();
8619         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
8620           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
8621         else
8622           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
8623       }
8624       return NewMI;
8625     }
8626   }
8627 
8628   // If the instruction and target operand are commutable, commute the
8629   // instruction and try again.
8630   if (AllowCommute) {
8631     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
8632     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
8633       bool HasDef = MI.getDesc().getNumDefs();
8634       unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
8635       unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
8636       unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
8637       bool Tied1 =
8638           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
8639       bool Tied2 =
8640           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
8641 
8642       // If either of the commutable operands are tied to the destination
8643       // then we can not commute + fold.
8644       if ((HasDef && Reg0 == Reg1 && Tied1) ||
8645           (HasDef && Reg0 == Reg2 && Tied2))
8646         return nullptr;
8647 
8648       MachineInstr *CommutedMI =
8649           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
8650       if (!CommutedMI) {
8651         // Unable to commute.
8652         return nullptr;
8653       }
8654       if (CommutedMI != &MI) {
8655         // New instruction. We can't fold from this.
8656         CommutedMI->eraseFromParent();
8657         return nullptr;
8658       }
8659 
8660       // Attempt to fold with the commuted version of the instruction.
8661       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
8662                                     Size, Align, /*AllowCommute=*/false);
8663       if (NewMI)
8664         return NewMI;
8665 
8666       // Folding failed again - undo the commute before returning.
8667       MachineInstr *UncommutedMI =
8668           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
8669       if (!UncommutedMI) {
8670         // Unable to commute.
8671         return nullptr;
8672       }
8673       if (UncommutedMI != &MI) {
8674         // New instruction. It doesn't need to be kept.
8675         UncommutedMI->eraseFromParent();
8676         return nullptr;
8677       }
8678 
8679       // Return here to prevent duplicate fuse failure report.
8680       return nullptr;
8681     }
8682   }
8683 
8684   // No fusion
8685   if (PrintFailedFusing && !MI.isCopy())
8686     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
8687   return nullptr;
8688 }
8689 
8690 MachineInstr *
8691 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
8692                                     ArrayRef<unsigned> Ops,
8693                                     MachineBasicBlock::iterator InsertPt,
8694                                     int FrameIndex, LiveIntervals *LIS) const {
8695   // Check switch flag
8696   if (NoFusing)
8697     return nullptr;
8698 
8699   // Unless optimizing for size, don't fold to avoid partial
8700   // register update stalls
8701   // TODO: we should block undef reg update as well.
8702   if (!MF.getFunction().optForSize() &&
8703       hasPartialRegUpdate(MI.getOpcode(), Subtarget))
8704     return nullptr;
8705 
8706   // Don't fold subreg spills, or reloads that use a high subreg.
8707   for (auto Op : Ops) {
8708     MachineOperand &MO = MI.getOperand(Op);
8709     auto SubReg = MO.getSubReg();
8710     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
8711       return nullptr;
8712   }
8713 
8714   const MachineFrameInfo &MFI = MF.getFrameInfo();
8715   unsigned Size = MFI.getObjectSize(FrameIndex);
8716   unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
8717   // If the function stack isn't realigned we don't want to fold instructions
8718   // that need increased alignment.
8719   if (!RI.needsStackRealignment(MF))
8720     Alignment =
8721         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
8722   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
8723     unsigned NewOpc = 0;
8724     unsigned RCSize = 0;
8725     switch (MI.getOpcode()) {
8726     default: return nullptr;
8727     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
8728     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
8729     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
8730     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
8731     }
8732     // Check if it's safe to fold the load. If the size of the object is
8733     // narrower than the load width, then it's not.
8734     if (Size < RCSize)
8735       return nullptr;
8736     // Change to CMPXXri r, 0 first.
8737     MI.setDesc(get(NewOpc));
8738     MI.getOperand(1).ChangeToImmediate(0);
8739   } else if (Ops.size() != 1)
8740     return nullptr;
8741 
8742   return foldMemoryOperandImpl(MF, MI, Ops[0],
8743                                MachineOperand::CreateFI(FrameIndex), InsertPt,
8744                                Size, Alignment, /*AllowCommute=*/true);
8745 }
8746 
8747 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
8748 /// because the latter uses contents that wouldn't be defined in the folded
8749 /// version.  For instance, this transformation isn't legal:
8750 ///   movss (%rdi), %xmm0
8751 ///   addps %xmm0, %xmm0
8752 /// ->
8753 ///   addps (%rdi), %xmm0
8754 ///
8755 /// But this one is:
8756 ///   movss (%rdi), %xmm0
8757 ///   addss %xmm0, %xmm0
8758 /// ->
8759 ///   addss (%rdi), %xmm0
8760 ///
8761 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
8762                                              const MachineInstr &UserMI,
8763                                              const MachineFunction &MF) {
8764   unsigned Opc = LoadMI.getOpcode();
8765   unsigned UserOpc = UserMI.getOpcode();
8766   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
8767   const TargetRegisterClass *RC =
8768       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
8769   unsigned RegSize = TRI.getRegSizeInBits(*RC);
8770 
8771   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
8772       RegSize > 32) {
8773     // These instructions only load 32 bits, we can't fold them if the
8774     // destination register is wider than 32 bits (4 bytes), and its user
8775     // instruction isn't scalar (SS).
8776     switch (UserOpc) {
8777     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
8778     case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
8779     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
8780     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
8781     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
8782     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
8783     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
8784     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
8785     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
8786     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
8787     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
8788     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
8789     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
8790     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
8791     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
8792     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
8793     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
8794     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
8795     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
8796     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
8797     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
8798     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
8799     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
8800     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
8801     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
8802     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
8803     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
8804     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
8805     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
8806     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
8807     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
8808     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
8809     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
8810     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
8811     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
8812     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
8813     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
8814     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
8815     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
8816       return false;
8817     default:
8818       return true;
8819     }
8820   }
8821 
8822   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
8823       RegSize > 64) {
8824     // These instructions only load 64 bits, we can't fold them if the
8825     // destination register is wider than 64 bits (8 bytes), and its user
8826     // instruction isn't scalar (SD).
8827     switch (UserOpc) {
8828     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
8829     case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
8830     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
8831     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
8832     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
8833     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
8834     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
8835     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
8836     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
8837     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
8838     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
8839     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
8840     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
8841     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
8842     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
8843     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
8844     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
8845     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
8846     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
8847     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
8848     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
8849     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
8850     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
8851     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
8852     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
8853     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
8854     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
8855     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
8856     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
8857     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
8858     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
8859     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
8860     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
8861     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
8862     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
8863     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
8864     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
8865     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
8866     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
8867       return false;
8868     default:
8869       return true;
8870     }
8871   }
8872 
8873   return false;
8874 }
8875 
8876 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
8877     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
8878     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
8879     LiveIntervals *LIS) const {
8880 
8881   // TODO: Support the case where LoadMI loads a wide register, but MI
8882   // only uses a subreg.
8883   for (auto Op : Ops) {
8884     if (MI.getOperand(Op).getSubReg())
8885       return nullptr;
8886   }
8887 
8888   // If loading from a FrameIndex, fold directly from the FrameIndex.
8889   unsigned NumOps = LoadMI.getDesc().getNumOperands();
8890   int FrameIndex;
8891   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
8892     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
8893       return nullptr;
8894     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
8895   }
8896 
8897   // Check switch flag
8898   if (NoFusing) return nullptr;
8899 
8900   // Avoid partial register update stalls unless optimizing for size.
8901   // TODO: we should block undef reg update as well.
8902   if (!MF.getFunction().optForSize() &&
8903       hasPartialRegUpdate(MI.getOpcode(), Subtarget))
8904     return nullptr;
8905 
8906   // Determine the alignment of the load.
8907   unsigned Alignment = 0;
8908   if (LoadMI.hasOneMemOperand())
8909     Alignment = (*LoadMI.memoperands_begin())->getAlignment();
8910   else
8911     switch (LoadMI.getOpcode()) {
8912     case X86::AVX512_512_SET0:
8913     case X86::AVX512_512_SETALLONES:
8914       Alignment = 64;
8915       break;
8916     case X86::AVX2_SETALLONES:
8917     case X86::AVX1_SETALLONES:
8918     case X86::AVX_SET0:
8919     case X86::AVX512_256_SET0:
8920       Alignment = 32;
8921       break;
8922     case X86::V_SET0:
8923     case X86::V_SETALLONES:
8924     case X86::AVX512_128_SET0:
8925       Alignment = 16;
8926       break;
8927     case X86::MMX_SET0:
8928     case X86::FsFLD0SD:
8929     case X86::AVX512_FsFLD0SD:
8930       Alignment = 8;
8931       break;
8932     case X86::FsFLD0SS:
8933     case X86::AVX512_FsFLD0SS:
8934       Alignment = 4;
8935       break;
8936     default:
8937       return nullptr;
8938     }
8939   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
8940     unsigned NewOpc = 0;
8941     switch (MI.getOpcode()) {
8942     default: return nullptr;
8943     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
8944     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
8945     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
8946     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
8947     }
8948     // Change to CMPXXri r, 0 first.
8949     MI.setDesc(get(NewOpc));
8950     MI.getOperand(1).ChangeToImmediate(0);
8951   } else if (Ops.size() != 1)
8952     return nullptr;
8953 
8954   // Make sure the subregisters match.
8955   // Otherwise we risk changing the size of the load.
8956   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
8957     return nullptr;
8958 
8959   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
8960   switch (LoadMI.getOpcode()) {
8961   case X86::MMX_SET0:
8962   case X86::V_SET0:
8963   case X86::V_SETALLONES:
8964   case X86::AVX2_SETALLONES:
8965   case X86::AVX1_SETALLONES:
8966   case X86::AVX_SET0:
8967   case X86::AVX512_128_SET0:
8968   case X86::AVX512_256_SET0:
8969   case X86::AVX512_512_SET0:
8970   case X86::AVX512_512_SETALLONES:
8971   case X86::FsFLD0SD:
8972   case X86::AVX512_FsFLD0SD:
8973   case X86::FsFLD0SS:
8974   case X86::AVX512_FsFLD0SS: {
8975     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
8976     // Create a constant-pool entry and operands to load from it.
8977 
8978     // Medium and large mode can't fold loads this way.
8979     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
8980         MF.getTarget().getCodeModel() != CodeModel::Kernel)
8981       return nullptr;
8982 
8983     // x86-32 PIC requires a PIC base register for constant pools.
8984     unsigned PICBase = 0;
8985     if (MF.getTarget().isPositionIndependent()) {
8986       if (Subtarget.is64Bit())
8987         PICBase = X86::RIP;
8988       else
8989         // FIXME: PICBase = getGlobalBaseReg(&MF);
8990         // This doesn't work for several reasons.
8991         // 1. GlobalBaseReg may have been spilled.
8992         // 2. It may not be live at MI.
8993         return nullptr;
8994     }
8995 
8996     // Create a constant-pool entry.
8997     MachineConstantPool &MCP = *MF.getConstantPool();
8998     Type *Ty;
8999     unsigned Opc = LoadMI.getOpcode();
9000     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
9001       Ty = Type::getFloatTy(MF.getFunction().getContext());
9002     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
9003       Ty = Type::getDoubleTy(MF.getFunction().getContext());
9004     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
9005       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),16);
9006     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
9007              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
9008       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 8);
9009     else if (Opc == X86::MMX_SET0)
9010       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 2);
9011     else
9012       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 4);
9013 
9014     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
9015                       Opc == X86::AVX512_512_SETALLONES ||
9016                       Opc == X86::AVX1_SETALLONES);
9017     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
9018                                     Constant::getNullValue(Ty);
9019     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
9020 
9021     // Create operands to load from the constant pool entry.
9022     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
9023     MOs.push_back(MachineOperand::CreateImm(1));
9024     MOs.push_back(MachineOperand::CreateReg(0, false));
9025     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
9026     MOs.push_back(MachineOperand::CreateReg(0, false));
9027     break;
9028   }
9029   default: {
9030     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
9031       return nullptr;
9032 
9033     // Folding a normal load. Just copy the load's address operands.
9034     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
9035                LoadMI.operands_begin() + NumOps);
9036     break;
9037   }
9038   }
9039   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
9040                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
9041 }
9042 
9043 bool X86InstrInfo::unfoldMemoryOperand(
9044     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
9045     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
9046   auto I = MemOp2RegOpTable.find(MI.getOpcode());
9047   if (I == MemOp2RegOpTable.end())
9048     return false;
9049   unsigned Opc = I->second.first;
9050   unsigned Index = I->second.second & TB_INDEX_MASK;
9051   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
9052   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
9053   if (UnfoldLoad && !FoldedLoad)
9054     return false;
9055   UnfoldLoad &= FoldedLoad;
9056   if (UnfoldStore && !FoldedStore)
9057     return false;
9058   UnfoldStore &= FoldedStore;
9059 
9060   const MCInstrDesc &MCID = get(Opc);
9061   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
9062   // TODO: Check if 32-byte or greater accesses are slow too?
9063   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
9064       Subtarget.isUnalignedMem16Slow())
9065     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
9066     // conservatively assume the address is unaligned. That's bad for
9067     // performance.
9068     return false;
9069   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
9070   SmallVector<MachineOperand,2> BeforeOps;
9071   SmallVector<MachineOperand,2> AfterOps;
9072   SmallVector<MachineOperand,4> ImpOps;
9073   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
9074     MachineOperand &Op = MI.getOperand(i);
9075     if (i >= Index && i < Index + X86::AddrNumOperands)
9076       AddrOps.push_back(Op);
9077     else if (Op.isReg() && Op.isImplicit())
9078       ImpOps.push_back(Op);
9079     else if (i < Index)
9080       BeforeOps.push_back(Op);
9081     else if (i > Index)
9082       AfterOps.push_back(Op);
9083   }
9084 
9085   // Emit the load instruction.
9086   if (UnfoldLoad) {
9087     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
9088         MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
9089     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
9090     if (UnfoldStore) {
9091       // Address operands cannot be marked isKill.
9092       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
9093         MachineOperand &MO = NewMIs[0]->getOperand(i);
9094         if (MO.isReg())
9095           MO.setIsKill(false);
9096       }
9097     }
9098   }
9099 
9100   // Emit the data processing instruction.
9101   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
9102   MachineInstrBuilder MIB(MF, DataMI);
9103 
9104   if (FoldedStore)
9105     MIB.addReg(Reg, RegState::Define);
9106   for (MachineOperand &BeforeOp : BeforeOps)
9107     MIB.add(BeforeOp);
9108   if (FoldedLoad)
9109     MIB.addReg(Reg);
9110   for (MachineOperand &AfterOp : AfterOps)
9111     MIB.add(AfterOp);
9112   for (MachineOperand &ImpOp : ImpOps) {
9113     MIB.addReg(ImpOp.getReg(),
9114                getDefRegState(ImpOp.isDef()) |
9115                RegState::Implicit |
9116                getKillRegState(ImpOp.isKill()) |
9117                getDeadRegState(ImpOp.isDead()) |
9118                getUndefRegState(ImpOp.isUndef()));
9119   }
9120   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
9121   switch (DataMI->getOpcode()) {
9122   default: break;
9123   case X86::CMP64ri32:
9124   case X86::CMP64ri8:
9125   case X86::CMP32ri:
9126   case X86::CMP32ri8:
9127   case X86::CMP16ri:
9128   case X86::CMP16ri8:
9129   case X86::CMP8ri: {
9130     MachineOperand &MO0 = DataMI->getOperand(0);
9131     MachineOperand &MO1 = DataMI->getOperand(1);
9132     if (MO1.getImm() == 0) {
9133       unsigned NewOpc;
9134       switch (DataMI->getOpcode()) {
9135       default: llvm_unreachable("Unreachable!");
9136       case X86::CMP64ri8:
9137       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
9138       case X86::CMP32ri8:
9139       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
9140       case X86::CMP16ri8:
9141       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
9142       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
9143       }
9144       DataMI->setDesc(get(NewOpc));
9145       MO1.ChangeToRegister(MO0.getReg(), false);
9146     }
9147   }
9148   }
9149   NewMIs.push_back(DataMI);
9150 
9151   // Emit the store instruction.
9152   if (UnfoldStore) {
9153     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
9154     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
9155         MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
9156     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
9157   }
9158 
9159   return true;
9160 }
9161 
9162 bool
9163 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
9164                                   SmallVectorImpl<SDNode*> &NewNodes) const {
9165   if (!N->isMachineOpcode())
9166     return false;
9167 
9168   auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
9169   if (I == MemOp2RegOpTable.end())
9170     return false;
9171   unsigned Opc = I->second.first;
9172   unsigned Index = I->second.second & TB_INDEX_MASK;
9173   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
9174   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
9175   const MCInstrDesc &MCID = get(Opc);
9176   MachineFunction &MF = DAG.getMachineFunction();
9177   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
9178   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
9179   unsigned NumDefs = MCID.NumDefs;
9180   std::vector<SDValue> AddrOps;
9181   std::vector<SDValue> BeforeOps;
9182   std::vector<SDValue> AfterOps;
9183   SDLoc dl(N);
9184   unsigned NumOps = N->getNumOperands();
9185   for (unsigned i = 0; i != NumOps-1; ++i) {
9186     SDValue Op = N->getOperand(i);
9187     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
9188       AddrOps.push_back(Op);
9189     else if (i < Index-NumDefs)
9190       BeforeOps.push_back(Op);
9191     else if (i > Index-NumDefs)
9192       AfterOps.push_back(Op);
9193   }
9194   SDValue Chain = N->getOperand(NumOps-1);
9195   AddrOps.push_back(Chain);
9196 
9197   // Emit the load instruction.
9198   SDNode *Load = nullptr;
9199   if (FoldedLoad) {
9200     EVT VT = *TRI.legalclasstypes_begin(*RC);
9201     std::pair<MachineInstr::mmo_iterator,
9202               MachineInstr::mmo_iterator> MMOs =
9203       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
9204                             cast<MachineSDNode>(N)->memoperands_end());
9205     if (!(*MMOs.first) &&
9206         RC == &X86::VR128RegClass &&
9207         Subtarget.isUnalignedMem16Slow())
9208       // Do not introduce a slow unaligned load.
9209       return false;
9210     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
9211     // memory access is slow above.
9212     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
9213     bool isAligned = (*MMOs.first) &&
9214                      (*MMOs.first)->getAlignment() >= Alignment;
9215     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
9216                               VT, MVT::Other, AddrOps);
9217     NewNodes.push_back(Load);
9218 
9219     // Preserve memory reference information.
9220     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
9221   }
9222 
9223   // Emit the data processing instruction.
9224   std::vector<EVT> VTs;
9225   const TargetRegisterClass *DstRC = nullptr;
9226   if (MCID.getNumDefs() > 0) {
9227     DstRC = getRegClass(MCID, 0, &RI, MF);
9228     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
9229   }
9230   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
9231     EVT VT = N->getValueType(i);
9232     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
9233       VTs.push_back(VT);
9234   }
9235   if (Load)
9236     BeforeOps.push_back(SDValue(Load, 0));
9237   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
9238   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
9239   switch (Opc) {
9240     default: break;
9241     case X86::CMP64ri32:
9242     case X86::CMP64ri8:
9243     case X86::CMP32ri:
9244     case X86::CMP32ri8:
9245     case X86::CMP16ri:
9246     case X86::CMP16ri8:
9247     case X86::CMP8ri:
9248       if (isNullConstant(BeforeOps[1])) {
9249         switch (Opc) {
9250           default: llvm_unreachable("Unreachable!");
9251           case X86::CMP64ri8:
9252           case X86::CMP64ri32: Opc = X86::TEST64rr; break;
9253           case X86::CMP32ri8:
9254           case X86::CMP32ri:   Opc = X86::TEST32rr; break;
9255           case X86::CMP16ri8:
9256           case X86::CMP16ri:   Opc = X86::TEST16rr; break;
9257           case X86::CMP8ri:    Opc = X86::TEST8rr; break;
9258         }
9259         BeforeOps[1] = BeforeOps[0];
9260       }
9261   }
9262   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
9263   NewNodes.push_back(NewNode);
9264 
9265   // Emit the store instruction.
9266   if (FoldedStore) {
9267     AddrOps.pop_back();
9268     AddrOps.push_back(SDValue(NewNode, 0));
9269     AddrOps.push_back(Chain);
9270     std::pair<MachineInstr::mmo_iterator,
9271               MachineInstr::mmo_iterator> MMOs =
9272       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
9273                              cast<MachineSDNode>(N)->memoperands_end());
9274     if (!(*MMOs.first) &&
9275         RC == &X86::VR128RegClass &&
9276         Subtarget.isUnalignedMem16Slow())
9277       // Do not introduce a slow unaligned store.
9278       return false;
9279     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
9280     // memory access is slow above.
9281     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
9282     bool isAligned = (*MMOs.first) &&
9283                      (*MMOs.first)->getAlignment() >= Alignment;
9284     SDNode *Store =
9285         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
9286                            dl, MVT::Other, AddrOps);
9287     NewNodes.push_back(Store);
9288 
9289     // Preserve memory reference information.
9290     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
9291   }
9292 
9293   return true;
9294 }
9295 
9296 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
9297                                       bool UnfoldLoad, bool UnfoldStore,
9298                                       unsigned *LoadRegIndex) const {
9299   auto I = MemOp2RegOpTable.find(Opc);
9300   if (I == MemOp2RegOpTable.end())
9301     return 0;
9302   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
9303   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
9304   if (UnfoldLoad && !FoldedLoad)
9305     return 0;
9306   if (UnfoldStore && !FoldedStore)
9307     return 0;
9308   if (LoadRegIndex)
9309     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
9310   return I->second.first;
9311 }
9312 
9313 bool
9314 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
9315                                      int64_t &Offset1, int64_t &Offset2) const {
9316   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
9317     return false;
9318   unsigned Opc1 = Load1->getMachineOpcode();
9319   unsigned Opc2 = Load2->getMachineOpcode();
9320   switch (Opc1) {
9321   default: return false;
9322   case X86::MOV8rm:
9323   case X86::MOV16rm:
9324   case X86::MOV32rm:
9325   case X86::MOV64rm:
9326   case X86::LD_Fp32m:
9327   case X86::LD_Fp64m:
9328   case X86::LD_Fp80m:
9329   case X86::MOVSSrm:
9330   case X86::MOVSDrm:
9331   case X86::MMX_MOVD64rm:
9332   case X86::MMX_MOVQ64rm:
9333   case X86::MOVAPSrm:
9334   case X86::MOVUPSrm:
9335   case X86::MOVAPDrm:
9336   case X86::MOVUPDrm:
9337   case X86::MOVDQArm:
9338   case X86::MOVDQUrm:
9339   // AVX load instructions
9340   case X86::VMOVSSrm:
9341   case X86::VMOVSDrm:
9342   case X86::VMOVAPSrm:
9343   case X86::VMOVUPSrm:
9344   case X86::VMOVAPDrm:
9345   case X86::VMOVUPDrm:
9346   case X86::VMOVDQArm:
9347   case X86::VMOVDQUrm:
9348   case X86::VMOVAPSYrm:
9349   case X86::VMOVUPSYrm:
9350   case X86::VMOVAPDYrm:
9351   case X86::VMOVUPDYrm:
9352   case X86::VMOVDQAYrm:
9353   case X86::VMOVDQUYrm:
9354   // AVX512 load instructions
9355   case X86::VMOVSSZrm:
9356   case X86::VMOVSDZrm:
9357   case X86::VMOVAPSZ128rm:
9358   case X86::VMOVUPSZ128rm:
9359   case X86::VMOVAPSZ128rm_NOVLX:
9360   case X86::VMOVUPSZ128rm_NOVLX:
9361   case X86::VMOVAPDZ128rm:
9362   case X86::VMOVUPDZ128rm:
9363   case X86::VMOVDQU8Z128rm:
9364   case X86::VMOVDQU16Z128rm:
9365   case X86::VMOVDQA32Z128rm:
9366   case X86::VMOVDQU32Z128rm:
9367   case X86::VMOVDQA64Z128rm:
9368   case X86::VMOVDQU64Z128rm:
9369   case X86::VMOVAPSZ256rm:
9370   case X86::VMOVUPSZ256rm:
9371   case X86::VMOVAPSZ256rm_NOVLX:
9372   case X86::VMOVUPSZ256rm_NOVLX:
9373   case X86::VMOVAPDZ256rm:
9374   case X86::VMOVUPDZ256rm:
9375   case X86::VMOVDQU8Z256rm:
9376   case X86::VMOVDQU16Z256rm:
9377   case X86::VMOVDQA32Z256rm:
9378   case X86::VMOVDQU32Z256rm:
9379   case X86::VMOVDQA64Z256rm:
9380   case X86::VMOVDQU64Z256rm:
9381   case X86::VMOVAPSZrm:
9382   case X86::VMOVUPSZrm:
9383   case X86::VMOVAPDZrm:
9384   case X86::VMOVUPDZrm:
9385   case X86::VMOVDQU8Zrm:
9386   case X86::VMOVDQU16Zrm:
9387   case X86::VMOVDQA32Zrm:
9388   case X86::VMOVDQU32Zrm:
9389   case X86::VMOVDQA64Zrm:
9390   case X86::VMOVDQU64Zrm:
9391   case X86::KMOVBkm:
9392   case X86::KMOVWkm:
9393   case X86::KMOVDkm:
9394   case X86::KMOVQkm:
9395     break;
9396   }
9397   switch (Opc2) {
9398   default: return false;
9399   case X86::MOV8rm:
9400   case X86::MOV16rm:
9401   case X86::MOV32rm:
9402   case X86::MOV64rm:
9403   case X86::LD_Fp32m:
9404   case X86::LD_Fp64m:
9405   case X86::LD_Fp80m:
9406   case X86::MOVSSrm:
9407   case X86::MOVSDrm:
9408   case X86::MMX_MOVD64rm:
9409   case X86::MMX_MOVQ64rm:
9410   case X86::MOVAPSrm:
9411   case X86::MOVUPSrm:
9412   case X86::MOVAPDrm:
9413   case X86::MOVUPDrm:
9414   case X86::MOVDQArm:
9415   case X86::MOVDQUrm:
9416   // AVX load instructions
9417   case X86::VMOVSSrm:
9418   case X86::VMOVSDrm:
9419   case X86::VMOVAPSrm:
9420   case X86::VMOVUPSrm:
9421   case X86::VMOVAPDrm:
9422   case X86::VMOVUPDrm:
9423   case X86::VMOVDQArm:
9424   case X86::VMOVDQUrm:
9425   case X86::VMOVAPSYrm:
9426   case X86::VMOVUPSYrm:
9427   case X86::VMOVAPDYrm:
9428   case X86::VMOVUPDYrm:
9429   case X86::VMOVDQAYrm:
9430   case X86::VMOVDQUYrm:
9431   // AVX512 load instructions
9432   case X86::VMOVSSZrm:
9433   case X86::VMOVSDZrm:
9434   case X86::VMOVAPSZ128rm:
9435   case X86::VMOVUPSZ128rm:
9436   case X86::VMOVAPSZ128rm_NOVLX:
9437   case X86::VMOVUPSZ128rm_NOVLX:
9438   case X86::VMOVAPDZ128rm:
9439   case X86::VMOVUPDZ128rm:
9440   case X86::VMOVDQU8Z128rm:
9441   case X86::VMOVDQU16Z128rm:
9442   case X86::VMOVDQA32Z128rm:
9443   case X86::VMOVDQU32Z128rm:
9444   case X86::VMOVDQA64Z128rm:
9445   case X86::VMOVDQU64Z128rm:
9446   case X86::VMOVAPSZ256rm:
9447   case X86::VMOVUPSZ256rm:
9448   case X86::VMOVAPSZ256rm_NOVLX:
9449   case X86::VMOVUPSZ256rm_NOVLX:
9450   case X86::VMOVAPDZ256rm:
9451   case X86::VMOVUPDZ256rm:
9452   case X86::VMOVDQU8Z256rm:
9453   case X86::VMOVDQU16Z256rm:
9454   case X86::VMOVDQA32Z256rm:
9455   case X86::VMOVDQU32Z256rm:
9456   case X86::VMOVDQA64Z256rm:
9457   case X86::VMOVDQU64Z256rm:
9458   case X86::VMOVAPSZrm:
9459   case X86::VMOVUPSZrm:
9460   case X86::VMOVAPDZrm:
9461   case X86::VMOVUPDZrm:
9462   case X86::VMOVDQU8Zrm:
9463   case X86::VMOVDQU16Zrm:
9464   case X86::VMOVDQA32Zrm:
9465   case X86::VMOVDQU32Zrm:
9466   case X86::VMOVDQA64Zrm:
9467   case X86::VMOVDQU64Zrm:
9468   case X86::KMOVBkm:
9469   case X86::KMOVWkm:
9470   case X86::KMOVDkm:
9471   case X86::KMOVQkm:
9472     break;
9473   }
9474 
9475   // Lambda to check if both the loads have the same value for an operand index.
9476   auto HasSameOp = [&](int I) {
9477     return Load1->getOperand(I) == Load2->getOperand(I);
9478   };
9479 
9480   // All operands except the displacement should match.
9481   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
9482       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
9483     return false;
9484 
9485   // Chain Operand must be the same.
9486   if (!HasSameOp(5))
9487     return false;
9488 
9489   // Now let's examine if the displacements are constants.
9490   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
9491   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
9492   if (!Disp1 || !Disp2)
9493     return false;
9494 
9495   Offset1 = Disp1->getSExtValue();
9496   Offset2 = Disp2->getSExtValue();
9497   return true;
9498 }
9499 
9500 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
9501                                            int64_t Offset1, int64_t Offset2,
9502                                            unsigned NumLoads) const {
9503   assert(Offset2 > Offset1);
9504   if ((Offset2 - Offset1) / 8 > 64)
9505     return false;
9506 
9507   unsigned Opc1 = Load1->getMachineOpcode();
9508   unsigned Opc2 = Load2->getMachineOpcode();
9509   if (Opc1 != Opc2)
9510     return false;  // FIXME: overly conservative?
9511 
9512   switch (Opc1) {
9513   default: break;
9514   case X86::LD_Fp32m:
9515   case X86::LD_Fp64m:
9516   case X86::LD_Fp80m:
9517   case X86::MMX_MOVD64rm:
9518   case X86::MMX_MOVQ64rm:
9519     return false;
9520   }
9521 
9522   EVT VT = Load1->getValueType(0);
9523   switch (VT.getSimpleVT().SimpleTy) {
9524   default:
9525     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
9526     // have 16 of them to play with.
9527     if (Subtarget.is64Bit()) {
9528       if (NumLoads >= 3)
9529         return false;
9530     } else if (NumLoads) {
9531       return false;
9532     }
9533     break;
9534   case MVT::i8:
9535   case MVT::i16:
9536   case MVT::i32:
9537   case MVT::i64:
9538   case MVT::f32:
9539   case MVT::f64:
9540     if (NumLoads)
9541       return false;
9542     break;
9543   }
9544 
9545   return true;
9546 }
9547 
9548 bool X86InstrInfo::
9549 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
9550   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
9551   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
9552   Cond[0].setImm(GetOppositeBranchCondition(CC));
9553   return false;
9554 }
9555 
9556 bool X86InstrInfo::
9557 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
9558   // FIXME: Return false for x87 stack register classes for now. We can't
9559   // allow any loads of these registers before FpGet_ST0_80.
9560   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
9561            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
9562 }
9563 
9564 /// Return a virtual register initialized with the
9565 /// the global base register value. Output instructions required to
9566 /// initialize the register in the function entry block, if necessary.
9567 ///
9568 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
9569 ///
9570 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
9571   assert(!Subtarget.is64Bit() &&
9572          "X86-64 PIC uses RIP relative addressing");
9573 
9574   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
9575   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
9576   if (GlobalBaseReg != 0)
9577     return GlobalBaseReg;
9578 
9579   // Create the register. The code to initialize it is inserted
9580   // later, by the CGBR pass (below).
9581   MachineRegisterInfo &RegInfo = MF->getRegInfo();
9582   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
9583   X86FI->setGlobalBaseReg(GlobalBaseReg);
9584   return GlobalBaseReg;
9585 }
9586 
9587 // These are the replaceable SSE instructions. Some of these have Int variants
9588 // that we don't include here. We don't want to replace instructions selected
9589 // by intrinsics.
9590 static const uint16_t ReplaceableInstrs[][3] = {
9591   //PackedSingle     PackedDouble    PackedInt
9592   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
9593   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
9594   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
9595   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
9596   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
9597   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
9598   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
9599   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
9600   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
9601   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
9602   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
9603   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
9604   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
9605   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
9606   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
9607   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
9608   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
9609   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
9610   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
9611   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
9612   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
9613   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
9614   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
9615   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
9616   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
9617   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
9618   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
9619   { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
9620   { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
9621   // AVX 128-bit support
9622   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
9623   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
9624   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
9625   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
9626   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
9627   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
9628   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
9629   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
9630   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
9631   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
9632   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
9633   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
9634   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
9635   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
9636   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
9637   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
9638   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
9639   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
9640   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
9641   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
9642   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
9643   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
9644   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
9645   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
9646   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
9647   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
9648   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
9649   { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
9650   { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
9651   // AVX 256-bit support
9652   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
9653   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
9654   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
9655   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
9656   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
9657   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
9658   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
9659   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
9660   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
9661   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
9662   // AVX512 support
9663   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
9664   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
9665   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
9666   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
9667   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
9668   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
9669   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
9670   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
9671   { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
9672   { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
9673   { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
9674   { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
9675   { X86::VBROADCASTSSZr,    X86::VBROADCASTSSZr,    X86::VPBROADCASTDZr },
9676   { X86::VBROADCASTSSZm,    X86::VBROADCASTSSZm,    X86::VPBROADCASTDZm },
9677   { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
9678   { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
9679   { X86::VBROADCASTSDZr,    X86::VBROADCASTSDZr,    X86::VPBROADCASTQZr },
9680   { X86::VBROADCASTSDZm,    X86::VBROADCASTSDZm,    X86::VPBROADCASTQZm },
9681   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
9682   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
9683   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
9684   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
9685   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
9686   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
9687   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
9688   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
9689   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
9690   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
9691   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
9692   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
9693   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
9694   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
9695   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
9696   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
9697   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
9698   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
9699   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
9700   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
9701   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
9702   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
9703   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
9704   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
9705   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
9706   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
9707   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
9708   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
9709   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
9710   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
9711   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
9712   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
9713   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
9714   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
9715   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
9716   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
9717   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
9718   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
9719   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
9720   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
9721   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
9722   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
9723   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
9724   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
9725   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
9726   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
9727   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
9728   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
9729   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
9730   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
9731   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
9732   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
9733   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
9734   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
9735   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
9736   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
9737   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
9738   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
9739   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
9740   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
9741   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
9742   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
9743   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
9744   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
9745   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
9746   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
9747   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
9748   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
9749   { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
9750   { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
9751 };
9752 
9753 static const uint16_t ReplaceableInstrsAVX2[][3] = {
9754   //PackedSingle       PackedDouble       PackedInt
9755   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
9756   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
9757   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
9758   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
9759   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
9760   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
9761   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
9762   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
9763   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
9764   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
9765   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
9766   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
9767   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
9768   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
9769   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
9770   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
9771   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
9772   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
9773   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
9774   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
9775   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
9776   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
9777   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
9778   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
9779   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
9780   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
9781   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
9782   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
9783   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
9784 };
9785 
9786 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
9787   //PackedSingle       PackedDouble       PackedInt
9788   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
9789   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
9790   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
9791   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
9792 };
9793 
9794 static const uint16_t ReplaceableInstrsAVX512[][4] = {
9795   // Two integer columns for 64-bit and 32-bit elements.
9796   //PackedSingle        PackedDouble        PackedInt             PackedInt
9797   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
9798   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
9799   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
9800   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
9801   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
9802   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
9803   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
9804   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
9805   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
9806   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
9807   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
9808   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
9809   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
9810   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
9811   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
9812 };
9813 
9814 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
9815   // Two integer columns for 64-bit and 32-bit elements.
9816   //PackedSingle        PackedDouble        PackedInt           PackedInt
9817   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
9818   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
9819   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
9820   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
9821   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
9822   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
9823   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
9824   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
9825   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
9826   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
9827   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
9828   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
9829   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
9830   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
9831   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
9832   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
9833   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
9834   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
9835   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
9836   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
9837   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
9838   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
9839   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
9840   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
9841 };
9842 
9843 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
9844   // Two integer columns for 64-bit and 32-bit elements.
9845   //PackedSingle          PackedDouble
9846   //PackedInt             PackedInt
9847   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
9848     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
9849   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
9850     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
9851   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
9852     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
9853   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
9854     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
9855   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
9856     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
9857   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
9858     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
9859   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
9860     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
9861   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
9862     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
9863   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
9864     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
9865   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
9866     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
9867   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
9868     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
9869   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
9870     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
9871   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
9872     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
9873   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
9874     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
9875   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
9876     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
9877   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
9878     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
9879   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
9880     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
9881   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
9882     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
9883   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
9884     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
9885   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
9886     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
9887   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
9888     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
9889   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
9890     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
9891   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
9892     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
9893   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
9894     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
9895   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
9896     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
9897   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
9898     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
9899   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
9900     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
9901   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
9902     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
9903   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
9904     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
9905   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
9906     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
9907   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
9908     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
9909   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
9910     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
9911   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
9912     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
9913   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
9914     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
9915   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
9916     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
9917   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
9918     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
9919   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
9920     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
9921   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
9922     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
9923   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
9924     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
9925   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
9926     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
9927   { X86::VORPSZrmk,       X86::VORPDZrmk,
9928     X86::VPORQZrmk,       X86::VPORDZrmk       },
9929   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
9930     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
9931   { X86::VORPSZrrk,       X86::VORPDZrrk,
9932     X86::VPORQZrrk,       X86::VPORDZrrk       },
9933   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
9934     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
9935   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
9936     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
9937   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
9938     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
9939   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
9940     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
9941   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
9942     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
9943   // Broadcast loads can be handled the same as masked operations to avoid
9944   // changing element size.
9945   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
9946     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
9947   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
9948     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
9949   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
9950     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
9951   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
9952     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
9953   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
9954     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
9955   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
9956     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
9957   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
9958     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
9959   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
9960     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
9961   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
9962     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
9963   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
9964     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
9965   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
9966     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
9967   { X86::VORPSZrmb,       X86::VORPDZrmb,
9968     X86::VPORQZrmb,       X86::VPORDZrmb       },
9969   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
9970     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
9971   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
9972     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
9973   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
9974     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
9975   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
9976     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
9977   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
9978     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
9979   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
9980     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
9981   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
9982     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
9983   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
9984     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
9985   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
9986     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
9987   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
9988     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
9989   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
9990     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
9991   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
9992     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
9993   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
9994     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
9995   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
9996     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
9997   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
9998     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
9999   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
10000     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
10001   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
10002     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
10003   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
10004     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
10005   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
10006     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
10007   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
10008     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
10009   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
10010     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
10011   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
10012     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
10013   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
10014     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
10015   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
10016     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
10017   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
10018     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
10019   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
10020     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
10021   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
10022     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
10023 };
10024 
10025 // NOTE: These should only be used by the custom domain methods.
10026 static const uint16_t ReplaceableCustomInstrs[][3] = {
10027   //PackedSingle             PackedDouble             PackedInt
10028   { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
10029   { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
10030   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
10031   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
10032   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
10033   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
10034 };
10035 static const uint16_t ReplaceableCustomAVX2Instrs[][3] = {
10036   //PackedSingle             PackedDouble             PackedInt
10037   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
10038   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
10039   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
10040   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
10041 };
10042 
10043 // FIXME: Some shuffle and unpack instructions have equivalents in different
10044 // domains, but they require a bit more work than just switching opcodes.
10045 
10046 static const uint16_t *lookup(unsigned opcode, unsigned domain,
10047                               ArrayRef<uint16_t[3]> Table) {
10048   for (const uint16_t (&Row)[3] : Table)
10049     if (Row[domain-1] == opcode)
10050       return Row;
10051   return nullptr;
10052 }
10053 
10054 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
10055                                     ArrayRef<uint16_t[4]> Table) {
10056   // If this is the integer domain make sure to check both integer columns.
10057   for (const uint16_t (&Row)[4] : Table)
10058     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
10059       return Row;
10060   return nullptr;
10061 }
10062 
10063 // Helper to attempt to widen/narrow blend masks.
10064 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
10065                             unsigned NewWidth, unsigned *pNewMask = nullptr) {
10066   assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
10067          "Illegal blend mask scale");
10068   unsigned NewMask = 0;
10069 
10070   if ((OldWidth % NewWidth) == 0) {
10071     unsigned Scale = OldWidth / NewWidth;
10072     unsigned SubMask = (1u << Scale) - 1;
10073     for (unsigned i = 0; i != NewWidth; ++i) {
10074       unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
10075       if (Sub == SubMask)
10076         NewMask |= (1u << i);
10077       else if (Sub != 0x0)
10078         return false;
10079     }
10080   } else {
10081     unsigned Scale = NewWidth / OldWidth;
10082     unsigned SubMask = (1u << Scale) - 1;
10083     for (unsigned i = 0; i != OldWidth; ++i) {
10084       if (OldMask & (1 << i)) {
10085         NewMask |= (SubMask << (i * Scale));
10086       }
10087     }
10088   }
10089 
10090   if (pNewMask)
10091     *pNewMask = NewMask;
10092   return true;
10093 }
10094 
10095 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
10096   unsigned Opcode = MI.getOpcode();
10097   unsigned NumOperands = MI.getNumOperands();
10098 
10099   auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
10100     uint16_t validDomains = 0;
10101     if (MI.getOperand(NumOperands - 1).isImm()) {
10102       unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
10103       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
10104         validDomains |= 0x2; // PackedSingle
10105       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
10106         validDomains |= 0x4; // PackedDouble
10107       if (!Is256 || Subtarget.hasAVX2())
10108         validDomains |= 0x8; // PackedInt
10109     }
10110     return validDomains;
10111   };
10112 
10113   switch (Opcode) {
10114   case X86::BLENDPDrmi:
10115   case X86::BLENDPDrri:
10116   case X86::VBLENDPDrmi:
10117   case X86::VBLENDPDrri:
10118     return GetBlendDomains(2, false);
10119   case X86::VBLENDPDYrmi:
10120   case X86::VBLENDPDYrri:
10121     return GetBlendDomains(4, true);
10122   case X86::BLENDPSrmi:
10123   case X86::BLENDPSrri:
10124   case X86::VBLENDPSrmi:
10125   case X86::VBLENDPSrri:
10126   case X86::VPBLENDDrmi:
10127   case X86::VPBLENDDrri:
10128     return GetBlendDomains(4, false);
10129   case X86::VBLENDPSYrmi:
10130   case X86::VBLENDPSYrri:
10131   case X86::VPBLENDDYrmi:
10132   case X86::VPBLENDDYrri:
10133     return GetBlendDomains(8, true);
10134   case X86::PBLENDWrmi:
10135   case X86::PBLENDWrri:
10136   case X86::VPBLENDWrmi:
10137   case X86::VPBLENDWrri:
10138   // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
10139   case X86::VPBLENDWYrmi:
10140   case X86::VPBLENDWYrri:
10141     return GetBlendDomains(8, false);
10142   }
10143   return 0;
10144 }
10145 
10146 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
10147                                             unsigned Domain) const {
10148   assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
10149   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
10150   assert(dom && "Not an SSE instruction");
10151 
10152   unsigned Opcode = MI.getOpcode();
10153   unsigned NumOperands = MI.getNumOperands();
10154 
10155   auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
10156     if (MI.getOperand(NumOperands - 1).isImm()) {
10157       unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
10158       Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
10159       unsigned NewImm = Imm;
10160 
10161       const uint16_t *table = lookup(Opcode, dom, ReplaceableCustomInstrs);
10162       if (!table)
10163         table = lookup(Opcode, dom, ReplaceableCustomAVX2Instrs);
10164 
10165       if (Domain == 1) { // PackedSingle
10166         AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
10167       } else if (Domain == 2) { // PackedDouble
10168         AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
10169       } else if (Domain == 3) { // PackedInt
10170         if (Subtarget.hasAVX2()) {
10171           // If we are already VPBLENDW use that, else use VPBLENDD.
10172           if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
10173             table = lookup(Opcode, dom, ReplaceableCustomAVX2Instrs);
10174             AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
10175           }
10176         } else {
10177           assert(!Is256 && "128-bit vector expected");
10178           AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
10179         }
10180       }
10181 
10182       assert(table && table[Domain - 1] && "Unknown domain op");
10183       MI.setDesc(get(table[Domain - 1]));
10184       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
10185     }
10186     return true;
10187   };
10188 
10189   switch (Opcode) {
10190   case X86::BLENDPDrmi:
10191   case X86::BLENDPDrri:
10192   case X86::VBLENDPDrmi:
10193   case X86::VBLENDPDrri:
10194     return SetBlendDomain(2, false);
10195   case X86::VBLENDPDYrmi:
10196   case X86::VBLENDPDYrri:
10197     return SetBlendDomain(4, true);
10198   case X86::BLENDPSrmi:
10199   case X86::BLENDPSrri:
10200   case X86::VBLENDPSrmi:
10201   case X86::VBLENDPSrri:
10202   case X86::VPBLENDDrmi:
10203   case X86::VPBLENDDrri:
10204     return SetBlendDomain(4, false);
10205   case X86::VBLENDPSYrmi:
10206   case X86::VBLENDPSYrri:
10207   case X86::VPBLENDDYrmi:
10208   case X86::VPBLENDDYrri:
10209     return SetBlendDomain(8, true);
10210   case X86::PBLENDWrmi:
10211   case X86::PBLENDWrri:
10212   case X86::VPBLENDWrmi:
10213   case X86::VPBLENDWrri:
10214     return SetBlendDomain(8, false);
10215   case X86::VPBLENDWYrmi:
10216   case X86::VPBLENDWYrri:
10217     return SetBlendDomain(16, true);
10218   }
10219   return false;
10220 }
10221 
10222 std::pair<uint16_t, uint16_t>
10223 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
10224   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
10225   unsigned opcode = MI.getOpcode();
10226   uint16_t validDomains = 0;
10227   if (domain) {
10228     // Attempt to match for custom instructions.
10229     validDomains = getExecutionDomainCustom(MI);
10230     if (validDomains)
10231       return std::make_pair(domain, validDomains);
10232 
10233     if (lookup(opcode, domain, ReplaceableInstrs)) {
10234       validDomains = 0xe;
10235     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
10236       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
10237     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
10238       // Insert/extract instructions should only effect domain if AVX2
10239       // is enabled.
10240       if (!Subtarget.hasAVX2())
10241         return std::make_pair(0, 0);
10242       validDomains = 0xe;
10243     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
10244       validDomains = 0xe;
10245     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
10246                                                   ReplaceableInstrsAVX512DQ)) {
10247       validDomains = 0xe;
10248     } else if (Subtarget.hasDQI()) {
10249       if (const uint16_t *table = lookupAVX512(opcode, domain,
10250                                              ReplaceableInstrsAVX512DQMasked)) {
10251         if (domain == 1 || (domain == 3 && table[3] == opcode))
10252           validDomains = 0xa;
10253         else
10254           validDomains = 0xc;
10255       }
10256     }
10257   }
10258   return std::make_pair(domain, validDomains);
10259 }
10260 
10261 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
10262   assert(Domain>0 && Domain<4 && "Invalid execution domain");
10263   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
10264   assert(dom && "Not an SSE instruction");
10265 
10266   // Attempt to match for custom instructions.
10267   if (setExecutionDomainCustom(MI, Domain))
10268     return;
10269 
10270   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
10271   if (!table) { // try the other table
10272     assert((Subtarget.hasAVX2() || Domain < 3) &&
10273            "256-bit vector operations only available in AVX2");
10274     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
10275   }
10276   if (!table) { // try the other table
10277     assert(Subtarget.hasAVX2() &&
10278            "256-bit insert/extract only available in AVX2");
10279     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
10280   }
10281   if (!table) { // try the AVX512 table
10282     assert(Subtarget.hasAVX512() && "Requires AVX-512");
10283     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
10284     // Don't change integer Q instructions to D instructions.
10285     if (table && Domain == 3 && table[3] == MI.getOpcode())
10286       Domain = 4;
10287   }
10288   if (!table) { // try the AVX512DQ table
10289     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
10290     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
10291     // Don't change integer Q instructions to D instructions and
10292     // use D intructions if we started with a PS instruction.
10293     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
10294       Domain = 4;
10295   }
10296   if (!table) { // try the AVX512DQMasked table
10297     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
10298     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
10299     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
10300       Domain = 4;
10301   }
10302   assert(table && "Cannot change domain");
10303   MI.setDesc(get(table[Domain - 1]));
10304 }
10305 
10306 /// Return the noop instruction to use for a noop.
10307 void X86InstrInfo::getNoop(MCInst &NopInst) const {
10308   NopInst.setOpcode(X86::NOOP);
10309 }
10310 
10311 bool X86InstrInfo::isHighLatencyDef(int opc) const {
10312   switch (opc) {
10313   default: return false;
10314   case X86::DIVPDrm:
10315   case X86::DIVPDrr:
10316   case X86::DIVPSrm:
10317   case X86::DIVPSrr:
10318   case X86::DIVSDrm:
10319   case X86::DIVSDrm_Int:
10320   case X86::DIVSDrr:
10321   case X86::DIVSDrr_Int:
10322   case X86::DIVSSrm:
10323   case X86::DIVSSrm_Int:
10324   case X86::DIVSSrr:
10325   case X86::DIVSSrr_Int:
10326   case X86::SQRTPDm:
10327   case X86::SQRTPDr:
10328   case X86::SQRTPSm:
10329   case X86::SQRTPSr:
10330   case X86::SQRTSDm:
10331   case X86::SQRTSDm_Int:
10332   case X86::SQRTSDr:
10333   case X86::SQRTSDr_Int:
10334   case X86::SQRTSSm:
10335   case X86::SQRTSSm_Int:
10336   case X86::SQRTSSr:
10337   case X86::SQRTSSr_Int:
10338   // AVX instructions with high latency
10339   case X86::VDIVPDrm:
10340   case X86::VDIVPDrr:
10341   case X86::VDIVPDYrm:
10342   case X86::VDIVPDYrr:
10343   case X86::VDIVPSrm:
10344   case X86::VDIVPSrr:
10345   case X86::VDIVPSYrm:
10346   case X86::VDIVPSYrr:
10347   case X86::VDIVSDrm:
10348   case X86::VDIVSDrm_Int:
10349   case X86::VDIVSDrr:
10350   case X86::VDIVSDrr_Int:
10351   case X86::VDIVSSrm:
10352   case X86::VDIVSSrm_Int:
10353   case X86::VDIVSSrr:
10354   case X86::VDIVSSrr_Int:
10355   case X86::VSQRTPDm:
10356   case X86::VSQRTPDr:
10357   case X86::VSQRTPDYm:
10358   case X86::VSQRTPDYr:
10359   case X86::VSQRTPSm:
10360   case X86::VSQRTPSr:
10361   case X86::VSQRTPSYm:
10362   case X86::VSQRTPSYr:
10363   case X86::VSQRTSDm:
10364   case X86::VSQRTSDm_Int:
10365   case X86::VSQRTSDr:
10366   case X86::VSQRTSDr_Int:
10367   case X86::VSQRTSSm:
10368   case X86::VSQRTSSm_Int:
10369   case X86::VSQRTSSr:
10370   case X86::VSQRTSSr_Int:
10371   // AVX512 instructions with high latency
10372   case X86::VDIVPDZ128rm:
10373   case X86::VDIVPDZ128rmb:
10374   case X86::VDIVPDZ128rmbk:
10375   case X86::VDIVPDZ128rmbkz:
10376   case X86::VDIVPDZ128rmk:
10377   case X86::VDIVPDZ128rmkz:
10378   case X86::VDIVPDZ128rr:
10379   case X86::VDIVPDZ128rrk:
10380   case X86::VDIVPDZ128rrkz:
10381   case X86::VDIVPDZ256rm:
10382   case X86::VDIVPDZ256rmb:
10383   case X86::VDIVPDZ256rmbk:
10384   case X86::VDIVPDZ256rmbkz:
10385   case X86::VDIVPDZ256rmk:
10386   case X86::VDIVPDZ256rmkz:
10387   case X86::VDIVPDZ256rr:
10388   case X86::VDIVPDZ256rrk:
10389   case X86::VDIVPDZ256rrkz:
10390   case X86::VDIVPDZrrb:
10391   case X86::VDIVPDZrrbk:
10392   case X86::VDIVPDZrrbkz:
10393   case X86::VDIVPDZrm:
10394   case X86::VDIVPDZrmb:
10395   case X86::VDIVPDZrmbk:
10396   case X86::VDIVPDZrmbkz:
10397   case X86::VDIVPDZrmk:
10398   case X86::VDIVPDZrmkz:
10399   case X86::VDIVPDZrr:
10400   case X86::VDIVPDZrrk:
10401   case X86::VDIVPDZrrkz:
10402   case X86::VDIVPSZ128rm:
10403   case X86::VDIVPSZ128rmb:
10404   case X86::VDIVPSZ128rmbk:
10405   case X86::VDIVPSZ128rmbkz:
10406   case X86::VDIVPSZ128rmk:
10407   case X86::VDIVPSZ128rmkz:
10408   case X86::VDIVPSZ128rr:
10409   case X86::VDIVPSZ128rrk:
10410   case X86::VDIVPSZ128rrkz:
10411   case X86::VDIVPSZ256rm:
10412   case X86::VDIVPSZ256rmb:
10413   case X86::VDIVPSZ256rmbk:
10414   case X86::VDIVPSZ256rmbkz:
10415   case X86::VDIVPSZ256rmk:
10416   case X86::VDIVPSZ256rmkz:
10417   case X86::VDIVPSZ256rr:
10418   case X86::VDIVPSZ256rrk:
10419   case X86::VDIVPSZ256rrkz:
10420   case X86::VDIVPSZrrb:
10421   case X86::VDIVPSZrrbk:
10422   case X86::VDIVPSZrrbkz:
10423   case X86::VDIVPSZrm:
10424   case X86::VDIVPSZrmb:
10425   case X86::VDIVPSZrmbk:
10426   case X86::VDIVPSZrmbkz:
10427   case X86::VDIVPSZrmk:
10428   case X86::VDIVPSZrmkz:
10429   case X86::VDIVPSZrr:
10430   case X86::VDIVPSZrrk:
10431   case X86::VDIVPSZrrkz:
10432   case X86::VDIVSDZrm:
10433   case X86::VDIVSDZrr:
10434   case X86::VDIVSDZrm_Int:
10435   case X86::VDIVSDZrm_Intk:
10436   case X86::VDIVSDZrm_Intkz:
10437   case X86::VDIVSDZrr_Int:
10438   case X86::VDIVSDZrr_Intk:
10439   case X86::VDIVSDZrr_Intkz:
10440   case X86::VDIVSDZrrb_Int:
10441   case X86::VDIVSDZrrb_Intk:
10442   case X86::VDIVSDZrrb_Intkz:
10443   case X86::VDIVSSZrm:
10444   case X86::VDIVSSZrr:
10445   case X86::VDIVSSZrm_Int:
10446   case X86::VDIVSSZrm_Intk:
10447   case X86::VDIVSSZrm_Intkz:
10448   case X86::VDIVSSZrr_Int:
10449   case X86::VDIVSSZrr_Intk:
10450   case X86::VDIVSSZrr_Intkz:
10451   case X86::VDIVSSZrrb_Int:
10452   case X86::VDIVSSZrrb_Intk:
10453   case X86::VDIVSSZrrb_Intkz:
10454   case X86::VSQRTPDZ128m:
10455   case X86::VSQRTPDZ128mb:
10456   case X86::VSQRTPDZ128mbk:
10457   case X86::VSQRTPDZ128mbkz:
10458   case X86::VSQRTPDZ128mk:
10459   case X86::VSQRTPDZ128mkz:
10460   case X86::VSQRTPDZ128r:
10461   case X86::VSQRTPDZ128rk:
10462   case X86::VSQRTPDZ128rkz:
10463   case X86::VSQRTPDZ256m:
10464   case X86::VSQRTPDZ256mb:
10465   case X86::VSQRTPDZ256mbk:
10466   case X86::VSQRTPDZ256mbkz:
10467   case X86::VSQRTPDZ256mk:
10468   case X86::VSQRTPDZ256mkz:
10469   case X86::VSQRTPDZ256r:
10470   case X86::VSQRTPDZ256rk:
10471   case X86::VSQRTPDZ256rkz:
10472   case X86::VSQRTPDZm:
10473   case X86::VSQRTPDZmb:
10474   case X86::VSQRTPDZmbk:
10475   case X86::VSQRTPDZmbkz:
10476   case X86::VSQRTPDZmk:
10477   case X86::VSQRTPDZmkz:
10478   case X86::VSQRTPDZr:
10479   case X86::VSQRTPDZrb:
10480   case X86::VSQRTPDZrbk:
10481   case X86::VSQRTPDZrbkz:
10482   case X86::VSQRTPDZrk:
10483   case X86::VSQRTPDZrkz:
10484   case X86::VSQRTPSZ128m:
10485   case X86::VSQRTPSZ128mb:
10486   case X86::VSQRTPSZ128mbk:
10487   case X86::VSQRTPSZ128mbkz:
10488   case X86::VSQRTPSZ128mk:
10489   case X86::VSQRTPSZ128mkz:
10490   case X86::VSQRTPSZ128r:
10491   case X86::VSQRTPSZ128rk:
10492   case X86::VSQRTPSZ128rkz:
10493   case X86::VSQRTPSZ256m:
10494   case X86::VSQRTPSZ256mb:
10495   case X86::VSQRTPSZ256mbk:
10496   case X86::VSQRTPSZ256mbkz:
10497   case X86::VSQRTPSZ256mk:
10498   case X86::VSQRTPSZ256mkz:
10499   case X86::VSQRTPSZ256r:
10500   case X86::VSQRTPSZ256rk:
10501   case X86::VSQRTPSZ256rkz:
10502   case X86::VSQRTPSZm:
10503   case X86::VSQRTPSZmb:
10504   case X86::VSQRTPSZmbk:
10505   case X86::VSQRTPSZmbkz:
10506   case X86::VSQRTPSZmk:
10507   case X86::VSQRTPSZmkz:
10508   case X86::VSQRTPSZr:
10509   case X86::VSQRTPSZrb:
10510   case X86::VSQRTPSZrbk:
10511   case X86::VSQRTPSZrbkz:
10512   case X86::VSQRTPSZrk:
10513   case X86::VSQRTPSZrkz:
10514   case X86::VSQRTSDZm:
10515   case X86::VSQRTSDZm_Int:
10516   case X86::VSQRTSDZm_Intk:
10517   case X86::VSQRTSDZm_Intkz:
10518   case X86::VSQRTSDZr:
10519   case X86::VSQRTSDZr_Int:
10520   case X86::VSQRTSDZr_Intk:
10521   case X86::VSQRTSDZr_Intkz:
10522   case X86::VSQRTSDZrb_Int:
10523   case X86::VSQRTSDZrb_Intk:
10524   case X86::VSQRTSDZrb_Intkz:
10525   case X86::VSQRTSSZm:
10526   case X86::VSQRTSSZm_Int:
10527   case X86::VSQRTSSZm_Intk:
10528   case X86::VSQRTSSZm_Intkz:
10529   case X86::VSQRTSSZr:
10530   case X86::VSQRTSSZr_Int:
10531   case X86::VSQRTSSZr_Intk:
10532   case X86::VSQRTSSZr_Intkz:
10533   case X86::VSQRTSSZrb_Int:
10534   case X86::VSQRTSSZrb_Intk:
10535   case X86::VSQRTSSZrb_Intkz:
10536 
10537   case X86::VGATHERDPDYrm:
10538   case X86::VGATHERDPDZ128rm:
10539   case X86::VGATHERDPDZ256rm:
10540   case X86::VGATHERDPDZrm:
10541   case X86::VGATHERDPDrm:
10542   case X86::VGATHERDPSYrm:
10543   case X86::VGATHERDPSZ128rm:
10544   case X86::VGATHERDPSZ256rm:
10545   case X86::VGATHERDPSZrm:
10546   case X86::VGATHERDPSrm:
10547   case X86::VGATHERPF0DPDm:
10548   case X86::VGATHERPF0DPSm:
10549   case X86::VGATHERPF0QPDm:
10550   case X86::VGATHERPF0QPSm:
10551   case X86::VGATHERPF1DPDm:
10552   case X86::VGATHERPF1DPSm:
10553   case X86::VGATHERPF1QPDm:
10554   case X86::VGATHERPF1QPSm:
10555   case X86::VGATHERQPDYrm:
10556   case X86::VGATHERQPDZ128rm:
10557   case X86::VGATHERQPDZ256rm:
10558   case X86::VGATHERQPDZrm:
10559   case X86::VGATHERQPDrm:
10560   case X86::VGATHERQPSYrm:
10561   case X86::VGATHERQPSZ128rm:
10562   case X86::VGATHERQPSZ256rm:
10563   case X86::VGATHERQPSZrm:
10564   case X86::VGATHERQPSrm:
10565   case X86::VPGATHERDDYrm:
10566   case X86::VPGATHERDDZ128rm:
10567   case X86::VPGATHERDDZ256rm:
10568   case X86::VPGATHERDDZrm:
10569   case X86::VPGATHERDDrm:
10570   case X86::VPGATHERDQYrm:
10571   case X86::VPGATHERDQZ128rm:
10572   case X86::VPGATHERDQZ256rm:
10573   case X86::VPGATHERDQZrm:
10574   case X86::VPGATHERDQrm:
10575   case X86::VPGATHERQDYrm:
10576   case X86::VPGATHERQDZ128rm:
10577   case X86::VPGATHERQDZ256rm:
10578   case X86::VPGATHERQDZrm:
10579   case X86::VPGATHERQDrm:
10580   case X86::VPGATHERQQYrm:
10581   case X86::VPGATHERQQZ128rm:
10582   case X86::VPGATHERQQZ256rm:
10583   case X86::VPGATHERQQZrm:
10584   case X86::VPGATHERQQrm:
10585   case X86::VSCATTERDPDZ128mr:
10586   case X86::VSCATTERDPDZ256mr:
10587   case X86::VSCATTERDPDZmr:
10588   case X86::VSCATTERDPSZ128mr:
10589   case X86::VSCATTERDPSZ256mr:
10590   case X86::VSCATTERDPSZmr:
10591   case X86::VSCATTERPF0DPDm:
10592   case X86::VSCATTERPF0DPSm:
10593   case X86::VSCATTERPF0QPDm:
10594   case X86::VSCATTERPF0QPSm:
10595   case X86::VSCATTERPF1DPDm:
10596   case X86::VSCATTERPF1DPSm:
10597   case X86::VSCATTERPF1QPDm:
10598   case X86::VSCATTERPF1QPSm:
10599   case X86::VSCATTERQPDZ128mr:
10600   case X86::VSCATTERQPDZ256mr:
10601   case X86::VSCATTERQPDZmr:
10602   case X86::VSCATTERQPSZ128mr:
10603   case X86::VSCATTERQPSZ256mr:
10604   case X86::VSCATTERQPSZmr:
10605   case X86::VPSCATTERDDZ128mr:
10606   case X86::VPSCATTERDDZ256mr:
10607   case X86::VPSCATTERDDZmr:
10608   case X86::VPSCATTERDQZ128mr:
10609   case X86::VPSCATTERDQZ256mr:
10610   case X86::VPSCATTERDQZmr:
10611   case X86::VPSCATTERQDZ128mr:
10612   case X86::VPSCATTERQDZ256mr:
10613   case X86::VPSCATTERQDZmr:
10614   case X86::VPSCATTERQQZ128mr:
10615   case X86::VPSCATTERQQZ256mr:
10616   case X86::VPSCATTERQQZmr:
10617     return true;
10618   }
10619 }
10620 
10621 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
10622                                          const MachineRegisterInfo *MRI,
10623                                          const MachineInstr &DefMI,
10624                                          unsigned DefIdx,
10625                                          const MachineInstr &UseMI,
10626                                          unsigned UseIdx) const {
10627   return isHighLatencyDef(DefMI.getOpcode());
10628 }
10629 
10630 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
10631                                            const MachineBasicBlock *MBB) const {
10632   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
10633          "Reassociation needs binary operators");
10634 
10635   // Integer binary math/logic instructions have a third source operand:
10636   // the EFLAGS register. That operand must be both defined here and never
10637   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
10638   // not change anything because rearranging the operands could affect other
10639   // instructions that depend on the exact status flags (zero, sign, etc.)
10640   // that are set by using these particular operands with this operation.
10641   if (Inst.getNumOperands() == 4) {
10642     assert(Inst.getOperand(3).isReg() &&
10643            Inst.getOperand(3).getReg() == X86::EFLAGS &&
10644            "Unexpected operand in reassociable instruction");
10645     if (!Inst.getOperand(3).isDead())
10646       return false;
10647   }
10648 
10649   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
10650 }
10651 
10652 // TODO: There are many more machine instruction opcodes to match:
10653 //       1. Other data types (integer, vectors)
10654 //       2. Other math / logic operations (xor, or)
10655 //       3. Other forms of the same operation (intrinsics and other variants)
10656 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
10657   switch (Inst.getOpcode()) {
10658   case X86::AND8rr:
10659   case X86::AND16rr:
10660   case X86::AND32rr:
10661   case X86::AND64rr:
10662   case X86::OR8rr:
10663   case X86::OR16rr:
10664   case X86::OR32rr:
10665   case X86::OR64rr:
10666   case X86::XOR8rr:
10667   case X86::XOR16rr:
10668   case X86::XOR32rr:
10669   case X86::XOR64rr:
10670   case X86::IMUL16rr:
10671   case X86::IMUL32rr:
10672   case X86::IMUL64rr:
10673   case X86::PANDrr:
10674   case X86::PORrr:
10675   case X86::PXORrr:
10676   case X86::ANDPDrr:
10677   case X86::ANDPSrr:
10678   case X86::ORPDrr:
10679   case X86::ORPSrr:
10680   case X86::XORPDrr:
10681   case X86::XORPSrr:
10682   case X86::PADDBrr:
10683   case X86::PADDWrr:
10684   case X86::PADDDrr:
10685   case X86::PADDQrr:
10686   case X86::VPANDrr:
10687   case X86::VPANDYrr:
10688   case X86::VPANDDZ128rr:
10689   case X86::VPANDDZ256rr:
10690   case X86::VPANDDZrr:
10691   case X86::VPANDQZ128rr:
10692   case X86::VPANDQZ256rr:
10693   case X86::VPANDQZrr:
10694   case X86::VPORrr:
10695   case X86::VPORYrr:
10696   case X86::VPORDZ128rr:
10697   case X86::VPORDZ256rr:
10698   case X86::VPORDZrr:
10699   case X86::VPORQZ128rr:
10700   case X86::VPORQZ256rr:
10701   case X86::VPORQZrr:
10702   case X86::VPXORrr:
10703   case X86::VPXORYrr:
10704   case X86::VPXORDZ128rr:
10705   case X86::VPXORDZ256rr:
10706   case X86::VPXORDZrr:
10707   case X86::VPXORQZ128rr:
10708   case X86::VPXORQZ256rr:
10709   case X86::VPXORQZrr:
10710   case X86::VANDPDrr:
10711   case X86::VANDPSrr:
10712   case X86::VANDPDYrr:
10713   case X86::VANDPSYrr:
10714   case X86::VANDPDZ128rr:
10715   case X86::VANDPSZ128rr:
10716   case X86::VANDPDZ256rr:
10717   case X86::VANDPSZ256rr:
10718   case X86::VANDPDZrr:
10719   case X86::VANDPSZrr:
10720   case X86::VORPDrr:
10721   case X86::VORPSrr:
10722   case X86::VORPDYrr:
10723   case X86::VORPSYrr:
10724   case X86::VORPDZ128rr:
10725   case X86::VORPSZ128rr:
10726   case X86::VORPDZ256rr:
10727   case X86::VORPSZ256rr:
10728   case X86::VORPDZrr:
10729   case X86::VORPSZrr:
10730   case X86::VXORPDrr:
10731   case X86::VXORPSrr:
10732   case X86::VXORPDYrr:
10733   case X86::VXORPSYrr:
10734   case X86::VXORPDZ128rr:
10735   case X86::VXORPSZ128rr:
10736   case X86::VXORPDZ256rr:
10737   case X86::VXORPSZ256rr:
10738   case X86::VXORPDZrr:
10739   case X86::VXORPSZrr:
10740   case X86::KADDBrr:
10741   case X86::KADDWrr:
10742   case X86::KADDDrr:
10743   case X86::KADDQrr:
10744   case X86::KANDBrr:
10745   case X86::KANDWrr:
10746   case X86::KANDDrr:
10747   case X86::KANDQrr:
10748   case X86::KORBrr:
10749   case X86::KORWrr:
10750   case X86::KORDrr:
10751   case X86::KORQrr:
10752   case X86::KXORBrr:
10753   case X86::KXORWrr:
10754   case X86::KXORDrr:
10755   case X86::KXORQrr:
10756   case X86::VPADDBrr:
10757   case X86::VPADDWrr:
10758   case X86::VPADDDrr:
10759   case X86::VPADDQrr:
10760   case X86::VPADDBYrr:
10761   case X86::VPADDWYrr:
10762   case X86::VPADDDYrr:
10763   case X86::VPADDQYrr:
10764   case X86::VPADDBZ128rr:
10765   case X86::VPADDWZ128rr:
10766   case X86::VPADDDZ128rr:
10767   case X86::VPADDQZ128rr:
10768   case X86::VPADDBZ256rr:
10769   case X86::VPADDWZ256rr:
10770   case X86::VPADDDZ256rr:
10771   case X86::VPADDQZ256rr:
10772   case X86::VPADDBZrr:
10773   case X86::VPADDWZrr:
10774   case X86::VPADDDZrr:
10775   case X86::VPADDQZrr:
10776   case X86::VPMULLWrr:
10777   case X86::VPMULLWYrr:
10778   case X86::VPMULLWZ128rr:
10779   case X86::VPMULLWZ256rr:
10780   case X86::VPMULLWZrr:
10781   case X86::VPMULLDrr:
10782   case X86::VPMULLDYrr:
10783   case X86::VPMULLDZ128rr:
10784   case X86::VPMULLDZ256rr:
10785   case X86::VPMULLDZrr:
10786   case X86::VPMULLQZ128rr:
10787   case X86::VPMULLQZ256rr:
10788   case X86::VPMULLQZrr:
10789   // Normal min/max instructions are not commutative because of NaN and signed
10790   // zero semantics, but these are. Thus, there's no need to check for global
10791   // relaxed math; the instructions themselves have the properties we need.
10792   case X86::MAXCPDrr:
10793   case X86::MAXCPSrr:
10794   case X86::MAXCSDrr:
10795   case X86::MAXCSSrr:
10796   case X86::MINCPDrr:
10797   case X86::MINCPSrr:
10798   case X86::MINCSDrr:
10799   case X86::MINCSSrr:
10800   case X86::VMAXCPDrr:
10801   case X86::VMAXCPSrr:
10802   case X86::VMAXCPDYrr:
10803   case X86::VMAXCPSYrr:
10804   case X86::VMAXCPDZ128rr:
10805   case X86::VMAXCPSZ128rr:
10806   case X86::VMAXCPDZ256rr:
10807   case X86::VMAXCPSZ256rr:
10808   case X86::VMAXCPDZrr:
10809   case X86::VMAXCPSZrr:
10810   case X86::VMAXCSDrr:
10811   case X86::VMAXCSSrr:
10812   case X86::VMAXCSDZrr:
10813   case X86::VMAXCSSZrr:
10814   case X86::VMINCPDrr:
10815   case X86::VMINCPSrr:
10816   case X86::VMINCPDYrr:
10817   case X86::VMINCPSYrr:
10818   case X86::VMINCPDZ128rr:
10819   case X86::VMINCPSZ128rr:
10820   case X86::VMINCPDZ256rr:
10821   case X86::VMINCPSZ256rr:
10822   case X86::VMINCPDZrr:
10823   case X86::VMINCPSZrr:
10824   case X86::VMINCSDrr:
10825   case X86::VMINCSSrr:
10826   case X86::VMINCSDZrr:
10827   case X86::VMINCSSZrr:
10828     return true;
10829   case X86::ADDPDrr:
10830   case X86::ADDPSrr:
10831   case X86::ADDSDrr:
10832   case X86::ADDSSrr:
10833   case X86::MULPDrr:
10834   case X86::MULPSrr:
10835   case X86::MULSDrr:
10836   case X86::MULSSrr:
10837   case X86::VADDPDrr:
10838   case X86::VADDPSrr:
10839   case X86::VADDPDYrr:
10840   case X86::VADDPSYrr:
10841   case X86::VADDPDZ128rr:
10842   case X86::VADDPSZ128rr:
10843   case X86::VADDPDZ256rr:
10844   case X86::VADDPSZ256rr:
10845   case X86::VADDPDZrr:
10846   case X86::VADDPSZrr:
10847   case X86::VADDSDrr:
10848   case X86::VADDSSrr:
10849   case X86::VADDSDZrr:
10850   case X86::VADDSSZrr:
10851   case X86::VMULPDrr:
10852   case X86::VMULPSrr:
10853   case X86::VMULPDYrr:
10854   case X86::VMULPSYrr:
10855   case X86::VMULPDZ128rr:
10856   case X86::VMULPSZ128rr:
10857   case X86::VMULPDZ256rr:
10858   case X86::VMULPSZ256rr:
10859   case X86::VMULPDZrr:
10860   case X86::VMULPSZrr:
10861   case X86::VMULSDrr:
10862   case X86::VMULSSrr:
10863   case X86::VMULSDZrr:
10864   case X86::VMULSSZrr:
10865     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
10866   default:
10867     return false;
10868   }
10869 }
10870 
10871 /// This is an architecture-specific helper function of reassociateOps.
10872 /// Set special operand attributes for new instructions after reassociation.
10873 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
10874                                          MachineInstr &OldMI2,
10875                                          MachineInstr &NewMI1,
10876                                          MachineInstr &NewMI2) const {
10877   // Integer instructions define an implicit EFLAGS source register operand as
10878   // the third source (fourth total) operand.
10879   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
10880     return;
10881 
10882   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
10883          "Unexpected instruction type for reassociation");
10884 
10885   MachineOperand &OldOp1 = OldMI1.getOperand(3);
10886   MachineOperand &OldOp2 = OldMI2.getOperand(3);
10887   MachineOperand &NewOp1 = NewMI1.getOperand(3);
10888   MachineOperand &NewOp2 = NewMI2.getOperand(3);
10889 
10890   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
10891          "Must have dead EFLAGS operand in reassociable instruction");
10892   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
10893          "Must have dead EFLAGS operand in reassociable instruction");
10894 
10895   (void)OldOp1;
10896   (void)OldOp2;
10897 
10898   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
10899          "Unexpected operand in reassociable instruction");
10900   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
10901          "Unexpected operand in reassociable instruction");
10902 
10903   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
10904   // of this pass or other passes. The EFLAGS operands must be dead in these new
10905   // instructions because the EFLAGS operands in the original instructions must
10906   // be dead in order for reassociation to occur.
10907   NewOp1.setIsDead();
10908   NewOp2.setIsDead();
10909 }
10910 
10911 std::pair<unsigned, unsigned>
10912 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
10913   return std::make_pair(TF, 0u);
10914 }
10915 
10916 ArrayRef<std::pair<unsigned, const char *>>
10917 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
10918   using namespace X86II;
10919   static const std::pair<unsigned, const char *> TargetFlags[] = {
10920       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
10921       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
10922       {MO_GOT, "x86-got"},
10923       {MO_GOTOFF, "x86-gotoff"},
10924       {MO_GOTPCREL, "x86-gotpcrel"},
10925       {MO_PLT, "x86-plt"},
10926       {MO_TLSGD, "x86-tlsgd"},
10927       {MO_TLSLD, "x86-tlsld"},
10928       {MO_TLSLDM, "x86-tlsldm"},
10929       {MO_GOTTPOFF, "x86-gottpoff"},
10930       {MO_INDNTPOFF, "x86-indntpoff"},
10931       {MO_TPOFF, "x86-tpoff"},
10932       {MO_DTPOFF, "x86-dtpoff"},
10933       {MO_NTPOFF, "x86-ntpoff"},
10934       {MO_GOTNTPOFF, "x86-gotntpoff"},
10935       {MO_DLLIMPORT, "x86-dllimport"},
10936       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
10937       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
10938       {MO_TLVP, "x86-tlvp"},
10939       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
10940       {MO_SECREL, "x86-secrel"}};
10941   return makeArrayRef(TargetFlags);
10942 }
10943 
10944 namespace {
10945   /// Create Global Base Reg pass. This initializes the PIC
10946   /// global base register for x86-32.
10947   struct CGBR : public MachineFunctionPass {
10948     static char ID;
10949     CGBR() : MachineFunctionPass(ID) {}
10950 
10951     bool runOnMachineFunction(MachineFunction &MF) override {
10952       const X86TargetMachine *TM =
10953         static_cast<const X86TargetMachine *>(&MF.getTarget());
10954       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
10955 
10956       // Don't do anything if this is 64-bit as 64-bit PIC
10957       // uses RIP relative addressing.
10958       if (STI.is64Bit())
10959         return false;
10960 
10961       // Only emit a global base reg in PIC mode.
10962       if (!TM->isPositionIndependent())
10963         return false;
10964 
10965       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
10966       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
10967 
10968       // If we didn't need a GlobalBaseReg, don't insert code.
10969       if (GlobalBaseReg == 0)
10970         return false;
10971 
10972       // Insert the set of GlobalBaseReg into the first MBB of the function
10973       MachineBasicBlock &FirstMBB = MF.front();
10974       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
10975       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
10976       MachineRegisterInfo &RegInfo = MF.getRegInfo();
10977       const X86InstrInfo *TII = STI.getInstrInfo();
10978 
10979       unsigned PC;
10980       if (STI.isPICStyleGOT())
10981         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
10982       else
10983         PC = GlobalBaseReg;
10984 
10985       // Operand of MovePCtoStack is completely ignored by asm printer. It's
10986       // only used in JIT code emission as displacement to pc.
10987       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
10988 
10989       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
10990       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
10991       if (STI.isPICStyleGOT()) {
10992         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
10993         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
10994           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
10995                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
10996       }
10997 
10998       return true;
10999     }
11000 
11001     StringRef getPassName() const override {
11002       return "X86 PIC Global Base Reg Initialization";
11003     }
11004 
11005     void getAnalysisUsage(AnalysisUsage &AU) const override {
11006       AU.setPreservesCFG();
11007       MachineFunctionPass::getAnalysisUsage(AU);
11008     }
11009   };
11010 }
11011 
11012 char CGBR::ID = 0;
11013 FunctionPass*
11014 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
11015 
11016 namespace {
11017   struct LDTLSCleanup : public MachineFunctionPass {
11018     static char ID;
11019     LDTLSCleanup() : MachineFunctionPass(ID) {}
11020 
11021     bool runOnMachineFunction(MachineFunction &MF) override {
11022       if (skipFunction(MF.getFunction()))
11023         return false;
11024 
11025       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
11026       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
11027         // No point folding accesses if there isn't at least two.
11028         return false;
11029       }
11030 
11031       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
11032       return VisitNode(DT->getRootNode(), 0);
11033     }
11034 
11035     // Visit the dominator subtree rooted at Node in pre-order.
11036     // If TLSBaseAddrReg is non-null, then use that to replace any
11037     // TLS_base_addr instructions. Otherwise, create the register
11038     // when the first such instruction is seen, and then use it
11039     // as we encounter more instructions.
11040     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
11041       MachineBasicBlock *BB = Node->getBlock();
11042       bool Changed = false;
11043 
11044       // Traverse the current block.
11045       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
11046            ++I) {
11047         switch (I->getOpcode()) {
11048           case X86::TLS_base_addr32:
11049           case X86::TLS_base_addr64:
11050             if (TLSBaseAddrReg)
11051               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
11052             else
11053               I = SetRegister(*I, &TLSBaseAddrReg);
11054             Changed = true;
11055             break;
11056           default:
11057             break;
11058         }
11059       }
11060 
11061       // Visit the children of this block in the dominator tree.
11062       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
11063            I != E; ++I) {
11064         Changed |= VisitNode(*I, TLSBaseAddrReg);
11065       }
11066 
11067       return Changed;
11068     }
11069 
11070     // Replace the TLS_base_addr instruction I with a copy from
11071     // TLSBaseAddrReg, returning the new instruction.
11072     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
11073                                          unsigned TLSBaseAddrReg) {
11074       MachineFunction *MF = I.getParent()->getParent();
11075       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
11076       const bool is64Bit = STI.is64Bit();
11077       const X86InstrInfo *TII = STI.getInstrInfo();
11078 
11079       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
11080       MachineInstr *Copy =
11081           BuildMI(*I.getParent(), I, I.getDebugLoc(),
11082                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
11083               .addReg(TLSBaseAddrReg);
11084 
11085       // Erase the TLS_base_addr instruction.
11086       I.eraseFromParent();
11087 
11088       return Copy;
11089     }
11090 
11091     // Create a virtual register in *TLSBaseAddrReg, and populate it by
11092     // inserting a copy instruction after I. Returns the new instruction.
11093     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
11094       MachineFunction *MF = I.getParent()->getParent();
11095       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
11096       const bool is64Bit = STI.is64Bit();
11097       const X86InstrInfo *TII = STI.getInstrInfo();
11098 
11099       // Create a virtual register for the TLS base address.
11100       MachineRegisterInfo &RegInfo = MF->getRegInfo();
11101       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
11102                                                       ? &X86::GR64RegClass
11103                                                       : &X86::GR32RegClass);
11104 
11105       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
11106       MachineInstr *Next = I.getNextNode();
11107       MachineInstr *Copy =
11108           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
11109                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
11110               .addReg(is64Bit ? X86::RAX : X86::EAX);
11111 
11112       return Copy;
11113     }
11114 
11115     StringRef getPassName() const override {
11116       return "Local Dynamic TLS Access Clean-up";
11117     }
11118 
11119     void getAnalysisUsage(AnalysisUsage &AU) const override {
11120       AU.setPreservesCFG();
11121       AU.addRequired<MachineDominatorTree>();
11122       MachineFunctionPass::getAnalysisUsage(AU);
11123     }
11124   };
11125 }
11126 
11127 char LDTLSCleanup::ID = 0;
11128 FunctionPass*
11129 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
11130 
11131 /// Constants defining how certain sequences should be outlined.
11132 ///
11133 /// \p MachineOutlinerDefault implies that the function is called with a call
11134 /// instruction, and a return must be emitted for the outlined function frame.
11135 ///
11136 /// That is,
11137 ///
11138 /// I1                                 OUTLINED_FUNCTION:
11139 /// I2 --> call OUTLINED_FUNCTION       I1
11140 /// I3                                  I2
11141 ///                                     I3
11142 ///                                     ret
11143 ///
11144 /// * Call construction overhead: 1 (call instruction)
11145 /// * Frame construction overhead: 1 (return instruction)
11146 ///
11147 /// \p MachineOutlinerTailCall implies that the function is being tail called.
11148 /// A jump is emitted instead of a call, and the return is already present in
11149 /// the outlined sequence. That is,
11150 ///
11151 /// I1                                 OUTLINED_FUNCTION:
11152 /// I2 --> jmp OUTLINED_FUNCTION       I1
11153 /// ret                                I2
11154 ///                                    ret
11155 ///
11156 /// * Call construction overhead: 1 (jump instruction)
11157 /// * Frame construction overhead: 0 (don't need to return)
11158 ///
11159 enum MachineOutlinerClass {
11160   MachineOutlinerDefault,
11161   MachineOutlinerTailCall
11162 };
11163 
11164 X86GenInstrInfo::MachineOutlinerInfo
11165 X86InstrInfo::getOutlininingCandidateInfo(
11166   std::vector<
11167       std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
11168       &RepeatedSequenceLocs) const {
11169 
11170   if (RepeatedSequenceLocs[0].second->isTerminator())
11171     return MachineOutlinerInfo(1, // Number of instructions to emit call.
11172                                0, // Number of instructions to emit frame.
11173                                MachineOutlinerTailCall, // Type of call.
11174                                MachineOutlinerTailCall // Type of frame.
11175                               );
11176 
11177   return MachineOutlinerInfo(1, 1, MachineOutlinerDefault,
11178                              MachineOutlinerDefault);
11179 }
11180 
11181 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
11182                                            bool OutlineFromLinkOnceODRs) const {
11183   const Function &F = MF.getFunction();
11184 
11185   // Does the function use a red zone? If it does, then we can't risk messing
11186   // with the stack.
11187   if (!F.hasFnAttribute(Attribute::NoRedZone))
11188       return false;
11189 
11190   // If we *don't* want to outline from things that could potentially be deduped
11191   // then return false.
11192   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
11193       return false;
11194 
11195   // This function is viable for outlining, so return true.
11196   return true;
11197 }
11198 
11199 X86GenInstrInfo::MachineOutlinerInstrType
11200 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  unsigned Flags) const {
11201   MachineInstr &MI = *MIT;
11202   // Don't allow debug values to impact outlining type.
11203   if (MI.isDebugValue() || MI.isIndirectDebugValue())
11204     return MachineOutlinerInstrType::Invisible;
11205 
11206   // Is this a tail call? If yes, we can outline as a tail call.
11207   if (isTailCall(MI))
11208     return MachineOutlinerInstrType::Legal;
11209 
11210   // Is this the terminator of a basic block?
11211   if (MI.isTerminator() || MI.isReturn()) {
11212 
11213     // Does its parent have any successors in its MachineFunction?
11214     if (MI.getParent()->succ_empty())
11215         return MachineOutlinerInstrType::Legal;
11216 
11217     // It does, so we can't tail call it.
11218     return MachineOutlinerInstrType::Illegal;
11219   }
11220 
11221   // Don't outline anything that modifies or reads from the stack pointer.
11222   //
11223   // FIXME: There are instructions which are being manually built without
11224   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
11225   // able to remove the extra checks once those are fixed up. For example,
11226   // sometimes we might get something like %rax = POP64r 1. This won't be
11227   // caught by modifiesRegister or readsRegister even though the instruction
11228   // really ought to be formed so that modifiesRegister/readsRegister would
11229   // catch it.
11230   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
11231       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
11232       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
11233     return MachineOutlinerInstrType::Illegal;
11234 
11235   // Outlined calls change the instruction pointer, so don't read from it.
11236   if (MI.readsRegister(X86::RIP, &RI) ||
11237       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
11238       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
11239     return MachineOutlinerInstrType::Illegal;
11240 
11241   // Positions can't safely be outlined.
11242   if (MI.isPosition())
11243     return MachineOutlinerInstrType::Illegal;
11244 
11245   // Make sure none of the operands of this instruction do anything tricky.
11246   for (const MachineOperand &MOP : MI.operands())
11247     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
11248         MOP.isTargetIndex())
11249       return MachineOutlinerInstrType::Illegal;
11250 
11251   return MachineOutlinerInstrType::Legal;
11252 }
11253 
11254 void X86InstrInfo::insertOutlinerEpilogue(MachineBasicBlock &MBB,
11255                                           MachineFunction &MF,
11256                                           const MachineOutlinerInfo &MInfo)
11257                                           const {
11258   // If we're a tail call, we already have a return, so don't do anything.
11259   if (MInfo.FrameConstructionID == MachineOutlinerTailCall)
11260     return;
11261 
11262   // We're a normal call, so our sequence doesn't have a return instruction.
11263   // Add it in.
11264   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
11265   MBB.insert(MBB.end(), retq);
11266 }
11267 
11268 void X86InstrInfo::insertOutlinerPrologue(MachineBasicBlock &MBB,
11269                                           MachineFunction &MF,
11270                                           const MachineOutlinerInfo &MInfo)
11271                                           const {}
11272 
11273 MachineBasicBlock::iterator
11274 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
11275                                  MachineBasicBlock::iterator &It,
11276                                  MachineFunction &MF,
11277                                  const MachineOutlinerInfo &MInfo) const {
11278   // Is it a tail call?
11279   if (MInfo.CallConstructionID == MachineOutlinerTailCall) {
11280     // Yes, just insert a JMP.
11281     It = MBB.insert(It,
11282                   BuildMI(MF, DebugLoc(), get(X86::JMP_1))
11283                       .addGlobalAddress(M.getNamedValue(MF.getName())));
11284   } else {
11285     // No, insert a call.
11286     It = MBB.insert(It,
11287                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
11288                       .addGlobalAddress(M.getNamedValue(MF.getName())));
11289   }
11290 
11291   return It;
11292 }
11293