1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCInst.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include <limits>
38 
39 #define GET_INSTRINFO_CTOR_DTOR
40 #include "X86GenInstrInfo.inc"
41 
42 using namespace llvm;
43 
44 static cl::opt<bool>
45 NoFusing("disable-spill-fusing",
46          cl::desc("Disable fusing of spill code into instructions"));
47 static cl::opt<bool>
48 PrintFailedFusing("print-failed-fuse-candidates",
49                   cl::desc("Print instructions that the allocator wants to"
50                            " fuse, but the X86 backend currently can't"),
51                   cl::Hidden);
52 static cl::opt<bool>
53 ReMatPICStubLoad("remat-pic-stub-load",
54                  cl::desc("Re-materialize load from stub in PIC mode"),
55                  cl::init(false), cl::Hidden);
56 
57 enum {
58   // Select which memory operand is being unfolded.
59   // (stored in bits 0 - 3)
60   TB_INDEX_0    = 0,
61   TB_INDEX_1    = 1,
62   TB_INDEX_2    = 2,
63   TB_INDEX_3    = 3,
64   TB_INDEX_MASK = 0xf,
65 
66   // Do not insert the reverse map (MemOp -> RegOp) into the table.
67   // This may be needed because there is a many -> one mapping.
68   TB_NO_REVERSE   = 1 << 4,
69 
70   // Do not insert the forward map (RegOp -> MemOp) into the table.
71   // This is needed for Native Client, which prohibits branch
72   // instructions from using a memory operand.
73   TB_NO_FORWARD   = 1 << 5,
74 
75   TB_FOLDED_LOAD  = 1 << 6,
76   TB_FOLDED_STORE = 1 << 7,
77 
78   // Minimum alignment required for load/store.
79   // Used for RegOp->MemOp conversion.
80   // (stored in bits 8 - 15)
81   TB_ALIGN_SHIFT = 8,
82   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
83   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
84   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
85   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
86   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
87 };
88 
89 struct X86OpTblEntry {
90   uint16_t RegOp;
91   uint16_t MemOp;
92   uint16_t Flags;
93 };
94 
95 // Pin the vtable to this file.
96 void X86InstrInfo::anchor() {}
97 
98 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
99   : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
100                      ? X86::ADJCALLSTACKDOWN64
101                      : X86::ADJCALLSTACKDOWN32),
102                     (tm.getSubtarget<X86Subtarget>().is64Bit()
103                      ? X86::ADJCALLSTACKUP64
104                      : X86::ADJCALLSTACKUP32)),
105     TM(tm), RI(tm) {
106 
107   static const X86OpTblEntry OpTbl2Addr[] = {
108     { X86::ADC32ri,     X86::ADC32mi,    0 },
109     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
110     { X86::ADC32rr,     X86::ADC32mr,    0 },
111     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
112     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
113     { X86::ADC64rr,     X86::ADC64mr,    0 },
114     { X86::ADD16ri,     X86::ADD16mi,    0 },
115     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
116     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
117     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
118     { X86::ADD16rr,     X86::ADD16mr,    0 },
119     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
120     { X86::ADD32ri,     X86::ADD32mi,    0 },
121     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
122     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
123     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
124     { X86::ADD32rr,     X86::ADD32mr,    0 },
125     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
126     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
127     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
128     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
129     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
130     { X86::ADD64rr,     X86::ADD64mr,    0 },
131     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
132     { X86::ADD8ri,      X86::ADD8mi,     0 },
133     { X86::ADD8rr,      X86::ADD8mr,     0 },
134     { X86::AND16ri,     X86::AND16mi,    0 },
135     { X86::AND16ri8,    X86::AND16mi8,   0 },
136     { X86::AND16rr,     X86::AND16mr,    0 },
137     { X86::AND32ri,     X86::AND32mi,    0 },
138     { X86::AND32ri8,    X86::AND32mi8,   0 },
139     { X86::AND32rr,     X86::AND32mr,    0 },
140     { X86::AND64ri32,   X86::AND64mi32,  0 },
141     { X86::AND64ri8,    X86::AND64mi8,   0 },
142     { X86::AND64rr,     X86::AND64mr,    0 },
143     { X86::AND8ri,      X86::AND8mi,     0 },
144     { X86::AND8rr,      X86::AND8mr,     0 },
145     { X86::DEC16r,      X86::DEC16m,     0 },
146     { X86::DEC32r,      X86::DEC32m,     0 },
147     { X86::DEC64_16r,   X86::DEC64_16m,  0 },
148     { X86::DEC64_32r,   X86::DEC64_32m,  0 },
149     { X86::DEC64r,      X86::DEC64m,     0 },
150     { X86::DEC8r,       X86::DEC8m,      0 },
151     { X86::INC16r,      X86::INC16m,     0 },
152     { X86::INC32r,      X86::INC32m,     0 },
153     { X86::INC64_16r,   X86::INC64_16m,  0 },
154     { X86::INC64_32r,   X86::INC64_32m,  0 },
155     { X86::INC64r,      X86::INC64m,     0 },
156     { X86::INC8r,       X86::INC8m,      0 },
157     { X86::NEG16r,      X86::NEG16m,     0 },
158     { X86::NEG32r,      X86::NEG32m,     0 },
159     { X86::NEG64r,      X86::NEG64m,     0 },
160     { X86::NEG8r,       X86::NEG8m,      0 },
161     { X86::NOT16r,      X86::NOT16m,     0 },
162     { X86::NOT32r,      X86::NOT32m,     0 },
163     { X86::NOT64r,      X86::NOT64m,     0 },
164     { X86::NOT8r,       X86::NOT8m,      0 },
165     { X86::OR16ri,      X86::OR16mi,     0 },
166     { X86::OR16ri8,     X86::OR16mi8,    0 },
167     { X86::OR16rr,      X86::OR16mr,     0 },
168     { X86::OR32ri,      X86::OR32mi,     0 },
169     { X86::OR32ri8,     X86::OR32mi8,    0 },
170     { X86::OR32rr,      X86::OR32mr,     0 },
171     { X86::OR64ri32,    X86::OR64mi32,   0 },
172     { X86::OR64ri8,     X86::OR64mi8,    0 },
173     { X86::OR64rr,      X86::OR64mr,     0 },
174     { X86::OR8ri,       X86::OR8mi,      0 },
175     { X86::OR8rr,       X86::OR8mr,      0 },
176     { X86::ROL16r1,     X86::ROL16m1,    0 },
177     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
178     { X86::ROL16ri,     X86::ROL16mi,    0 },
179     { X86::ROL32r1,     X86::ROL32m1,    0 },
180     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
181     { X86::ROL32ri,     X86::ROL32mi,    0 },
182     { X86::ROL64r1,     X86::ROL64m1,    0 },
183     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
184     { X86::ROL64ri,     X86::ROL64mi,    0 },
185     { X86::ROL8r1,      X86::ROL8m1,     0 },
186     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
187     { X86::ROL8ri,      X86::ROL8mi,     0 },
188     { X86::ROR16r1,     X86::ROR16m1,    0 },
189     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
190     { X86::ROR16ri,     X86::ROR16mi,    0 },
191     { X86::ROR32r1,     X86::ROR32m1,    0 },
192     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
193     { X86::ROR32ri,     X86::ROR32mi,    0 },
194     { X86::ROR64r1,     X86::ROR64m1,    0 },
195     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
196     { X86::ROR64ri,     X86::ROR64mi,    0 },
197     { X86::ROR8r1,      X86::ROR8m1,     0 },
198     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
199     { X86::ROR8ri,      X86::ROR8mi,     0 },
200     { X86::SAR16r1,     X86::SAR16m1,    0 },
201     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
202     { X86::SAR16ri,     X86::SAR16mi,    0 },
203     { X86::SAR32r1,     X86::SAR32m1,    0 },
204     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
205     { X86::SAR32ri,     X86::SAR32mi,    0 },
206     { X86::SAR64r1,     X86::SAR64m1,    0 },
207     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
208     { X86::SAR64ri,     X86::SAR64mi,    0 },
209     { X86::SAR8r1,      X86::SAR8m1,     0 },
210     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
211     { X86::SAR8ri,      X86::SAR8mi,     0 },
212     { X86::SBB32ri,     X86::SBB32mi,    0 },
213     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
214     { X86::SBB32rr,     X86::SBB32mr,    0 },
215     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
216     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
217     { X86::SBB64rr,     X86::SBB64mr,    0 },
218     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
219     { X86::SHL16ri,     X86::SHL16mi,    0 },
220     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
221     { X86::SHL32ri,     X86::SHL32mi,    0 },
222     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
223     { X86::SHL64ri,     X86::SHL64mi,    0 },
224     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
225     { X86::SHL8ri,      X86::SHL8mi,     0 },
226     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
227     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
228     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
229     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
230     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
231     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
232     { X86::SHR16r1,     X86::SHR16m1,    0 },
233     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
234     { X86::SHR16ri,     X86::SHR16mi,    0 },
235     { X86::SHR32r1,     X86::SHR32m1,    0 },
236     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
237     { X86::SHR32ri,     X86::SHR32mi,    0 },
238     { X86::SHR64r1,     X86::SHR64m1,    0 },
239     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
240     { X86::SHR64ri,     X86::SHR64mi,    0 },
241     { X86::SHR8r1,      X86::SHR8m1,     0 },
242     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
243     { X86::SHR8ri,      X86::SHR8mi,     0 },
244     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
245     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
246     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
247     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
248     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
249     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
250     { X86::SUB16ri,     X86::SUB16mi,    0 },
251     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
252     { X86::SUB16rr,     X86::SUB16mr,    0 },
253     { X86::SUB32ri,     X86::SUB32mi,    0 },
254     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
255     { X86::SUB32rr,     X86::SUB32mr,    0 },
256     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
257     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
258     { X86::SUB64rr,     X86::SUB64mr,    0 },
259     { X86::SUB8ri,      X86::SUB8mi,     0 },
260     { X86::SUB8rr,      X86::SUB8mr,     0 },
261     { X86::XOR16ri,     X86::XOR16mi,    0 },
262     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
263     { X86::XOR16rr,     X86::XOR16mr,    0 },
264     { X86::XOR32ri,     X86::XOR32mi,    0 },
265     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
266     { X86::XOR32rr,     X86::XOR32mr,    0 },
267     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
268     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
269     { X86::XOR64rr,     X86::XOR64mr,    0 },
270     { X86::XOR8ri,      X86::XOR8mi,     0 },
271     { X86::XOR8rr,      X86::XOR8mr,     0 }
272   };
273 
274   for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
275     unsigned RegOp = OpTbl2Addr[i].RegOp;
276     unsigned MemOp = OpTbl2Addr[i].MemOp;
277     unsigned Flags = OpTbl2Addr[i].Flags;
278     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
279                   RegOp, MemOp,
280                   // Index 0, folded load and store, no alignment requirement.
281                   Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
282   }
283 
284   static const X86OpTblEntry OpTbl0[] = {
285     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
286     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
287     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
288     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
289     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
290     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
291     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
292     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
293     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
294     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
295     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
296     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
297     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
298     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
299     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
300     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
301     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
302     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
303     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
304     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
305     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
306     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
307     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
308     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
309     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
310     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
311     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
312     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
313     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
314     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
315     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
316     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
317     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
318     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
319     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
320     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
321     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
322     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
323     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
324     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
325     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
326     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
327     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
328     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
329     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
330     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
331     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
332     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
333     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
334     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
335     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
336     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
337     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
338     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
339     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
340     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
341     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
342     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
343     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
344     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
345     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
346     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
347     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
348     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
349     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
350     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
351     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
352     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
353     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
354     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
355     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
356     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
357     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
358     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
359     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
360     // AVX 128-bit versions of foldable instructions
361     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
362     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
363     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
364     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
365     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
366     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
367     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
368     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
369     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
370     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
371     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
372     // AVX 256-bit foldable instructions
373     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
374     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
375     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
376     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
377     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
378     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
379     // AVX-512 foldable instructions
380     { X86::VMOVPDI2DIZrr,X86::VMOVPDI2DIZmr,  TB_FOLDED_STORE }
381   };
382 
383   for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
384     unsigned RegOp      = OpTbl0[i].RegOp;
385     unsigned MemOp      = OpTbl0[i].MemOp;
386     unsigned Flags      = OpTbl0[i].Flags;
387     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
388                   RegOp, MemOp, TB_INDEX_0 | Flags);
389   }
390 
391   static const X86OpTblEntry OpTbl1[] = {
392     { X86::CMP16rr,         X86::CMP16rm,             0 },
393     { X86::CMP32rr,         X86::CMP32rm,             0 },
394     { X86::CMP64rr,         X86::CMP64rm,             0 },
395     { X86::CMP8rr,          X86::CMP8rm,              0 },
396     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
397     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
398     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
399     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
400     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
401     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
402     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
403     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
404     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
405     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
406     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
407     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
408     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
409     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
410     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
411     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
412     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
413     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
414     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
415     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
416     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
417     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
418     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
419     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
420     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
421     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
422     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
423     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
424     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
425     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
426     { X86::MOV16rr,         X86::MOV16rm,             0 },
427     { X86::MOV32rr,         X86::MOV32rm,             0 },
428     { X86::MOV64rr,         X86::MOV64rm,             0 },
429     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
430     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
431     { X86::MOV8rr,          X86::MOV8rm,              0 },
432     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
433     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
434     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
435     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
436     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
437     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
438     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
439     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
440     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
441     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
442     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
443     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
444     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
445     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
446     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
447     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
448     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
449     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
450     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
451     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
452     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
453     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
454     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
455     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
456     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
457     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
458     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
459     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
460     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
461     { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
462     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
463     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
464     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
465     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
466     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
467     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
468     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
469     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
470     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
471     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
472     { X86::TEST16rr,        X86::TEST16rm,            0 },
473     { X86::TEST32rr,        X86::TEST32rm,            0 },
474     { X86::TEST64rr,        X86::TEST64rm,            0 },
475     { X86::TEST8rr,         X86::TEST8rm,             0 },
476     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
477     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
478     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
479     // AVX 128-bit versions of foldable instructions
480     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
481     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
482     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
483     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
484     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
485     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
486     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
487     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
488     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
489     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
490     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
491     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
492     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
493     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
494     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
495     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
496     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
497     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
498     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
499     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
500     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
501     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
502     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
503     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
504     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
505     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
506     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
507     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
508     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
509     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
510     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
511     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
512     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
513     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
514     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
515     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
516     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
517     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
518     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
519     { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
520     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
521     { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
522     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
523     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
524     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
525     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
526     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
527 
528     // AVX 256-bit foldable instructions
529     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
530     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
531     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
532     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
533     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
534     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
535     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
536 
537     // AVX2 foldable instructions
538     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
539     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
540     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
541     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
542     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
543     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
544     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
545     { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
546     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
547     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
548     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
549     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
550     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
551 
552     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
553     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
554     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
555     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
556     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
557     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
558     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
559     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
560     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
561     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
562     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
563     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
564     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
565     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
566     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
567     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
568     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
569     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
570     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
571     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
572     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
573     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
574     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
575     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
576     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
577     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
578     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
579     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
580     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
581     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
582     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
583     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
584     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
585     { X86::RORX32ri,        X86::RORX32mi,            0 },
586     { X86::RORX64ri,        X86::RORX64mi,            0 },
587     { X86::SARX32rr,        X86::SARX32rm,            0 },
588     { X86::SARX64rr,        X86::SARX64rm,            0 },
589     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
590     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
591     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
592     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
593     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
594     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
595     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
596     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
597     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
598     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
599     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
600 
601     // AVX-512 foldable instructions
602     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
603     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
604     { X86::VMOVDQA32rr,     X86::VMOVDQA32rm,         TB_ALIGN_64 },
605     { X86::VMOVDQA64rr,     X86::VMOVDQA64rm,         TB_ALIGN_64 },
606     { X86::VMOVDQU32rr,     X86::VMOVDQU32rm,         0 },
607     { X86::VMOVDQU64rr,     X86::VMOVDQU64rm,         0 },
608 
609     // AES foldable instructions
610     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
611     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
612     { X86::VAESIMCrr,             X86::VAESIMCrm,             TB_ALIGN_16 },
613     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, TB_ALIGN_16 },
614   };
615 
616   for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
617     unsigned RegOp = OpTbl1[i].RegOp;
618     unsigned MemOp = OpTbl1[i].MemOp;
619     unsigned Flags = OpTbl1[i].Flags;
620     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
621                   RegOp, MemOp,
622                   // Index 1, folded load
623                   Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
624   }
625 
626   static const X86OpTblEntry OpTbl2[] = {
627     { X86::ADC32rr,         X86::ADC32rm,       0 },
628     { X86::ADC64rr,         X86::ADC64rm,       0 },
629     { X86::ADD16rr,         X86::ADD16rm,       0 },
630     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
631     { X86::ADD32rr,         X86::ADD32rm,       0 },
632     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
633     { X86::ADD64rr,         X86::ADD64rm,       0 },
634     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
635     { X86::ADD8rr,          X86::ADD8rm,        0 },
636     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
637     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
638     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
639     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
640     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
641     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
642     { X86::AND16rr,         X86::AND16rm,       0 },
643     { X86::AND32rr,         X86::AND32rm,       0 },
644     { X86::AND64rr,         X86::AND64rm,       0 },
645     { X86::AND8rr,          X86::AND8rm,        0 },
646     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
647     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
648     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
649     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
650     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
651     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
652     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
653     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
654     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
655     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
656     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
657     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
658     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
659     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
660     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
661     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
662     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
663     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
664     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
665     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
666     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
667     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
668     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
669     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
670     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
671     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
672     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
673     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
674     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
675     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
676     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
677     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
678     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
679     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
680     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
681     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
682     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
683     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
684     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
685     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
686     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
687     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
688     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
689     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
690     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
691     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
692     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
693     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
694     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
695     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
696     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
697     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
698     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
699     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
700     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
701     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
702     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
703     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
704     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
705     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
706     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
707     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
708     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
709     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
710     { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
711     { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
712     { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
713     { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
714     { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
715     { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
716     { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
717     { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
718     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
719     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
720     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
721     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
722     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
723     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
724     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
725     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
726     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
727     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
728     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
729     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
730     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
731     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
732     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
733     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
734     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
735     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
736     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
737     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
738     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
739     { X86::MINSDrr,         X86::MINSDrm,       0 },
740     { X86::MINSSrr,         X86::MINSSrm,       0 },
741     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
742     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
743     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
744     { X86::MULSDrr,         X86::MULSDrm,       0 },
745     { X86::MULSSrr,         X86::MULSSrm,       0 },
746     { X86::OR16rr,          X86::OR16rm,        0 },
747     { X86::OR32rr,          X86::OR32rm,        0 },
748     { X86::OR64rr,          X86::OR64rm,        0 },
749     { X86::OR8rr,           X86::OR8rm,         0 },
750     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
751     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
752     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
753     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
754     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
755     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
756     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
757     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
758     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
759     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
760     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
761     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
762     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
763     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
764     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
765     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
766     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
767     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
768     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
769     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
770     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
771     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
772     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
773     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
774     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
775     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
776     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
777     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
778     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
779     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
780     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
781     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
782     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
783     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
784     { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
785     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
786     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
787     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
788     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
789     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
790     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
791     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
792     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
793     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
794     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
795     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
796     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
797     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
798     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
799     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
800     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
801     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
802     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
803     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
804     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
805     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
806     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
807     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
808     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
809     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
810     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
811     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
812     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
813     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
814     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
815     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
816     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
817     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
818     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
819     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
820     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
821     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
822     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
823     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
824     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
825     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
826     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
827     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
828     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
829     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
830     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
831     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
832     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
833     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
834     { X86::SBB32rr,         X86::SBB32rm,       0 },
835     { X86::SBB64rr,         X86::SBB64rm,       0 },
836     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
837     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
838     { X86::SUB16rr,         X86::SUB16rm,       0 },
839     { X86::SUB32rr,         X86::SUB32rm,       0 },
840     { X86::SUB64rr,         X86::SUB64rm,       0 },
841     { X86::SUB8rr,          X86::SUB8rm,        0 },
842     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
843     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
844     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
845     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
846     // FIXME: TEST*rr -> swapped operand of TEST*mr.
847     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
848     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
849     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
850     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
851     { X86::XOR16rr,         X86::XOR16rm,       0 },
852     { X86::XOR32rr,         X86::XOR32rm,       0 },
853     { X86::XOR64rr,         X86::XOR64rm,       0 },
854     { X86::XOR8rr,          X86::XOR8rm,        0 },
855     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
856     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
857     // AVX 128-bit versions of foldable instructions
858     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
859     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
860     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
861     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
862     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
863     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
864     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
865     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
866     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
867     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
868     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
869     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
870     { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQXrm,      0 },
871     { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       0 },
872     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
873     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
874     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
875     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
876     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
877     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
878     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
879     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
880     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
881     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
882     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
883     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
884     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
885     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
886     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
887     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
888     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
889     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
890     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
891     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
892     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
893     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
894     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
895     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
896     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
897     { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
898     { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
899     { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
900     { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
901     { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
902     { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
903     { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
904     { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
905     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
906     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
907     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
908     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
909     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
910     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
911     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
912     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
913     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
914     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
915     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
916     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
917     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
918     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
919     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
920     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
921     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
922     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
923     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
924     { X86::VORPDrr,           X86::VORPDrm,            0 },
925     { X86::VORPSrr,           X86::VORPSrm,            0 },
926     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
927     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
928     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
929     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
930     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
931     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
932     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
933     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
934     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
935     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
936     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
937     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
938     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
939     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
940     { X86::VPANDrr,           X86::VPANDrm,            0 },
941     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
942     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
943     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
944     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
945     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
946     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
947     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
948     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
949     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
950     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
951     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
952     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
953     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
954     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
955     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
956     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
957     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
958     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
959     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
960     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
961     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
962     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
963     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
964     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
965     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
966     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
967     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
968     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
969     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
970     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
971     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
972     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
973     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
974     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
975     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
976     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
977     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
978     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
979     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
980     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
981     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
982     { X86::VPORrr,            X86::VPORrm,             0 },
983     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
984     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
985     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
986     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
987     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
988     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
989     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
990     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
991     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
992     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
993     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
994     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
995     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
996     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
997     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
998     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
999     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1000     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1001     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1002     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1003     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1004     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1005     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1006     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1007     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1008     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1009     { X86::VPXORrr,           X86::VPXORrm,            0 },
1010     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1011     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1012     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1013     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1014     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1015     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1016     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1017     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1018     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1019     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1020     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1021     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1022     // AVX 256-bit foldable instructions
1023     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1024     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1025     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1026     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1027     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1028     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1029     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1030     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1031     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1032     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1033     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1034     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1035     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1036     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1037     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1038     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1039     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1040     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1041     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1042     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1043     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1044     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1045     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1046     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1047     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1048     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1049     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1050     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1051     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1052     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1053     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1054     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1055     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1056     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1057     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1058     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1059     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1060     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1061     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1062     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1063     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1064     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1065     // AVX2 foldable instructions
1066     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1067     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1068     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1069     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1070     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1071     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1072     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1073     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1074     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1075     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1076     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1077     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1078     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1079     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1080     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1081     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1082     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1083     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1084     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1085     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1086     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1087     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1088     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1089     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1090     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1091     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1092     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1093     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1094     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1095     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1096     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1097     { X86::VPERMPDYri,        X86::VPERMPDYmi,         0 },
1098     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1099     { X86::VPERMQYri,         X86::VPERMQYmi,          0 },
1100     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1101     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1102     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1103     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1104     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1105     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1106     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1107     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1108     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1109     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1110     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1111     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1112     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1113     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1114     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1115     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1116     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1117     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1118     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1119     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1120     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1121     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1122     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1123     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1124     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1125     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1126     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1127     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1128     { X86::VPORYrr,           X86::VPORYrm,            0 },
1129     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1130     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1131     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1132     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1133     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1134     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1135     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1136     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1137     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1138     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1139     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1140     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1141     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1142     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1143     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1144     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1145     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1146     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1147     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1148     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1149     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1150     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1151     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1152     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1153     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1154     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1155     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1156     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1157     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1158     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1159     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1160     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1161     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1162     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1163     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1164     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1165     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1166     // FIXME: add AVX 256-bit foldable instructions
1167 
1168     // FMA4 foldable patterns
1169     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0           },
1170     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0           },
1171     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_16 },
1172     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_16 },
1173     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_32 },
1174     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_32 },
1175     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0           },
1176     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0           },
1177     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_16 },
1178     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_16 },
1179     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_32 },
1180     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_32 },
1181     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0           },
1182     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0           },
1183     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_16 },
1184     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_16 },
1185     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_32 },
1186     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_32 },
1187     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0           },
1188     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0           },
1189     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_16 },
1190     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_16 },
1191     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_32 },
1192     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_32 },
1193     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_16 },
1194     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_16 },
1195     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_32 },
1196     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_32 },
1197     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_16 },
1198     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_16 },
1199     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_32 },
1200     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_32 },
1201 
1202     // BMI/BMI2 foldable instructions
1203     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1204     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1205     { X86::MULX32rr,          X86::MULX32rm,            0 },
1206     { X86::MULX64rr,          X86::MULX64rm,            0 },
1207     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1208     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1209     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1210     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1211 
1212     // AVX-512 foldable instructions
1213     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1214     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1215     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1216     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1217     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1218     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1219     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1220     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1221     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1222     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1223     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1224     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1225     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1226     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1227     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1228     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1229     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1230     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1231     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1232     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1233     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1234     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1235     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1236     { X86::VALIGNQrri,        X86::VALIGNQrmi,          0 },
1237     { X86::VALIGNDrri,        X86::VALIGNDrmi,          0 },
1238 
1239     // AES foldable instructions
1240     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1241     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1242     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1243     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1244     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       TB_ALIGN_16 },
1245     { X86::VAESDECrr,         X86::VAESDECrm,           TB_ALIGN_16 },
1246     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       TB_ALIGN_16 },
1247     { X86::VAESENCrr,         X86::VAESENCrm,           TB_ALIGN_16 },
1248 
1249     // SHA foldable instructions
1250     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1251     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1252     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1253     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1254     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1255     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1256     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 },
1257   };
1258 
1259   for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1260     unsigned RegOp = OpTbl2[i].RegOp;
1261     unsigned MemOp = OpTbl2[i].MemOp;
1262     unsigned Flags = OpTbl2[i].Flags;
1263     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1264                   RegOp, MemOp,
1265                   // Index 2, folded load
1266                   Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1267   }
1268 
1269   static const X86OpTblEntry OpTbl3[] = {
1270     // FMA foldable instructions
1271     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         0 },
1272     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         0 },
1273     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         0 },
1274     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         0 },
1275     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         0 },
1276     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         0 },
1277     { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     0 },
1278     { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     0 },
1279 
1280     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_16 },
1281     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_16 },
1282     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_16 },
1283     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_16 },
1284     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_16 },
1285     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_16 },
1286     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_32 },
1287     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_32 },
1288     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_32 },
1289     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_32 },
1290     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_32 },
1291     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_32 },
1292 
1293     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        0 },
1294     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        0 },
1295     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        0 },
1296     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        0 },
1297     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        0 },
1298     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        0 },
1299     { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    0 },
1300     { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    0 },
1301 
1302     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_16 },
1303     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_16 },
1304     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_16 },
1305     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_16 },
1306     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_16 },
1307     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_16 },
1308     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_32 },
1309     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_32 },
1310     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_32 },
1311     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_32 },
1312     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_32 },
1313     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_32 },
1314 
1315     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         0 },
1316     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         0 },
1317     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         0 },
1318     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         0 },
1319     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         0 },
1320     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         0 },
1321     { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     0 },
1322     { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     0 },
1323 
1324     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_16 },
1325     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_16 },
1326     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_16 },
1327     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_16 },
1328     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_16 },
1329     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_16 },
1330     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_32 },
1331     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_32 },
1332     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_32 },
1333     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_32 },
1334     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_32 },
1335     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_32 },
1336 
1337     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        0 },
1338     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        0 },
1339     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        0 },
1340     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        0 },
1341     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        0 },
1342     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        0 },
1343     { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    0 },
1344     { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    0 },
1345 
1346     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_16 },
1347     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_16 },
1348     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_16 },
1349     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_16 },
1350     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_16 },
1351     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_16 },
1352     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_32 },
1353     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_32 },
1354     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_32 },
1355     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_32 },
1356     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_32 },
1357     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_32 },
1358 
1359     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_16 },
1360     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_16 },
1361     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_16 },
1362     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_16 },
1363     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_16 },
1364     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_16 },
1365     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_32 },
1366     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_32 },
1367     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_32 },
1368     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_32 },
1369     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_32 },
1370     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_32 },
1371 
1372     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_16 },
1373     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_16 },
1374     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_16 },
1375     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_16 },
1376     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_16 },
1377     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_16 },
1378     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_32 },
1379     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_32 },
1380     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_32 },
1381     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_32 },
1382     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_32 },
1383     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_32 },
1384 
1385     // FMA4 foldable patterns
1386     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1387     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1388     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1389     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1390     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1391     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1392     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1393     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1394     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1395     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1396     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1397     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1398     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1399     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1400     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1401     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1402     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1403     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1404     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1405     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1406     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1407     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1408     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1409     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1410     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1411     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1412     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1413     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1414     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1415     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1416     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1417     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1418     // AVX-512 VPERMI instructions with 3 source operands.
1419     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1420     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1421     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1422     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1423     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1424     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1425     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1426     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 }
1427   };
1428 
1429   for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1430     unsigned RegOp = OpTbl3[i].RegOp;
1431     unsigned MemOp = OpTbl3[i].MemOp;
1432     unsigned Flags = OpTbl3[i].Flags;
1433     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1434                   RegOp, MemOp,
1435                   // Index 3, folded load
1436                   Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1437   }
1438 
1439 }
1440 
1441 void
1442 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1443                             MemOp2RegOpTableType &M2RTable,
1444                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
1445     if ((Flags & TB_NO_FORWARD) == 0) {
1446       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1447       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1448     }
1449     if ((Flags & TB_NO_REVERSE) == 0) {
1450       assert(!M2RTable.count(MemOp) &&
1451            "Duplicated entries in unfolding maps?");
1452       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1453     }
1454 }
1455 
1456 bool
1457 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1458                                     unsigned &SrcReg, unsigned &DstReg,
1459                                     unsigned &SubIdx) const {
1460   switch (MI.getOpcode()) {
1461   default: break;
1462   case X86::MOVSX16rr8:
1463   case X86::MOVZX16rr8:
1464   case X86::MOVSX32rr8:
1465   case X86::MOVZX32rr8:
1466   case X86::MOVSX64rr8:
1467     if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1468       // It's not always legal to reference the low 8-bit of the larger
1469       // register in 32-bit mode.
1470       return false;
1471   case X86::MOVSX32rr16:
1472   case X86::MOVZX32rr16:
1473   case X86::MOVSX64rr16:
1474   case X86::MOVSX64rr32: {
1475     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1476       // Be conservative.
1477       return false;
1478     SrcReg = MI.getOperand(1).getReg();
1479     DstReg = MI.getOperand(0).getReg();
1480     switch (MI.getOpcode()) {
1481     default: llvm_unreachable("Unreachable!");
1482     case X86::MOVSX16rr8:
1483     case X86::MOVZX16rr8:
1484     case X86::MOVSX32rr8:
1485     case X86::MOVZX32rr8:
1486     case X86::MOVSX64rr8:
1487       SubIdx = X86::sub_8bit;
1488       break;
1489     case X86::MOVSX32rr16:
1490     case X86::MOVZX32rr16:
1491     case X86::MOVSX64rr16:
1492       SubIdx = X86::sub_16bit;
1493       break;
1494     case X86::MOVSX64rr32:
1495       SubIdx = X86::sub_32bit;
1496       break;
1497     }
1498     return true;
1499   }
1500   }
1501   return false;
1502 }
1503 
1504 /// isFrameOperand - Return true and the FrameIndex if the specified
1505 /// operand and follow operands form a reference to the stack frame.
1506 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1507                                   int &FrameIndex) const {
1508   if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1509       MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1510       MI->getOperand(Op+1).getImm() == 1 &&
1511       MI->getOperand(Op+2).getReg() == 0 &&
1512       MI->getOperand(Op+3).getImm() == 0) {
1513     FrameIndex = MI->getOperand(Op).getIndex();
1514     return true;
1515   }
1516   return false;
1517 }
1518 
1519 static bool isFrameLoadOpcode(int Opcode) {
1520   switch (Opcode) {
1521   default:
1522     return false;
1523   case X86::MOV8rm:
1524   case X86::MOV16rm:
1525   case X86::MOV32rm:
1526   case X86::MOV64rm:
1527   case X86::LD_Fp64m:
1528   case X86::MOVSSrm:
1529   case X86::MOVSDrm:
1530   case X86::MOVAPSrm:
1531   case X86::MOVAPDrm:
1532   case X86::MOVDQArm:
1533   case X86::VMOVSSrm:
1534   case X86::VMOVSDrm:
1535   case X86::VMOVAPSrm:
1536   case X86::VMOVAPDrm:
1537   case X86::VMOVDQArm:
1538   case X86::VMOVAPSYrm:
1539   case X86::VMOVAPDYrm:
1540   case X86::VMOVDQAYrm:
1541   case X86::MMX_MOVD64rm:
1542   case X86::MMX_MOVQ64rm:
1543   case X86::VMOVAPSZrm:
1544   case X86::VMOVUPSZrm:
1545     return true;
1546   }
1547 }
1548 
1549 static bool isFrameStoreOpcode(int Opcode) {
1550   switch (Opcode) {
1551   default: break;
1552   case X86::MOV8mr:
1553   case X86::MOV16mr:
1554   case X86::MOV32mr:
1555   case X86::MOV64mr:
1556   case X86::ST_FpP64m:
1557   case X86::MOVSSmr:
1558   case X86::MOVSDmr:
1559   case X86::MOVAPSmr:
1560   case X86::MOVAPDmr:
1561   case X86::MOVDQAmr:
1562   case X86::VMOVSSmr:
1563   case X86::VMOVSDmr:
1564   case X86::VMOVAPSmr:
1565   case X86::VMOVAPDmr:
1566   case X86::VMOVDQAmr:
1567   case X86::VMOVAPSYmr:
1568   case X86::VMOVAPDYmr:
1569   case X86::VMOVDQAYmr:
1570   case X86::VMOVUPSZmr:
1571   case X86::VMOVAPSZmr:
1572   case X86::MMX_MOVD64mr:
1573   case X86::MMX_MOVQ64mr:
1574   case X86::MMX_MOVNTQmr:
1575     return true;
1576   }
1577   return false;
1578 }
1579 
1580 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1581                                            int &FrameIndex) const {
1582   if (isFrameLoadOpcode(MI->getOpcode()))
1583     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1584       return MI->getOperand(0).getReg();
1585   return 0;
1586 }
1587 
1588 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1589                                                  int &FrameIndex) const {
1590   if (isFrameLoadOpcode(MI->getOpcode())) {
1591     unsigned Reg;
1592     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1593       return Reg;
1594     // Check for post-frame index elimination operations
1595     const MachineMemOperand *Dummy;
1596     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1597   }
1598   return 0;
1599 }
1600 
1601 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1602                                           int &FrameIndex) const {
1603   if (isFrameStoreOpcode(MI->getOpcode()))
1604     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1605         isFrameOperand(MI, 0, FrameIndex))
1606       return MI->getOperand(X86::AddrNumOperands).getReg();
1607   return 0;
1608 }
1609 
1610 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1611                                                 int &FrameIndex) const {
1612   if (isFrameStoreOpcode(MI->getOpcode())) {
1613     unsigned Reg;
1614     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1615       return Reg;
1616     // Check for post-frame index elimination operations
1617     const MachineMemOperand *Dummy;
1618     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1619   }
1620   return 0;
1621 }
1622 
1623 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1624 /// X86::MOVPC32r.
1625 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1626   // Don't waste compile time scanning use-def chains of physregs.
1627   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1628     return false;
1629   bool isPICBase = false;
1630   for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1631          E = MRI.def_end(); I != E; ++I) {
1632     MachineInstr *DefMI = I.getOperand().getParent();
1633     if (DefMI->getOpcode() != X86::MOVPC32r)
1634       return false;
1635     assert(!isPICBase && "More than one PIC base?");
1636     isPICBase = true;
1637   }
1638   return isPICBase;
1639 }
1640 
1641 bool
1642 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1643                                                 AliasAnalysis *AA) const {
1644   switch (MI->getOpcode()) {
1645   default: break;
1646   case X86::MOV8rm:
1647   case X86::MOV16rm:
1648   case X86::MOV32rm:
1649   case X86::MOV64rm:
1650   case X86::LD_Fp64m:
1651   case X86::MOVSSrm:
1652   case X86::MOVSDrm:
1653   case X86::MOVAPSrm:
1654   case X86::MOVUPSrm:
1655   case X86::MOVAPDrm:
1656   case X86::MOVDQArm:
1657   case X86::MOVDQUrm:
1658   case X86::VMOVSSrm:
1659   case X86::VMOVSDrm:
1660   case X86::VMOVAPSrm:
1661   case X86::VMOVUPSrm:
1662   case X86::VMOVAPDrm:
1663   case X86::VMOVDQArm:
1664   case X86::VMOVDQUrm:
1665   case X86::VMOVAPSYrm:
1666   case X86::VMOVUPSYrm:
1667   case X86::VMOVAPDYrm:
1668   case X86::VMOVDQAYrm:
1669   case X86::VMOVDQUYrm:
1670   case X86::MMX_MOVD64rm:
1671   case X86::MMX_MOVQ64rm:
1672   case X86::FsVMOVAPSrm:
1673   case X86::FsVMOVAPDrm:
1674   case X86::FsMOVAPSrm:
1675   case X86::FsMOVAPDrm: {
1676     // Loads from constant pools are trivially rematerializable.
1677     if (MI->getOperand(1).isReg() &&
1678         MI->getOperand(2).isImm() &&
1679         MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1680         MI->isInvariantLoad(AA)) {
1681       unsigned BaseReg = MI->getOperand(1).getReg();
1682       if (BaseReg == 0 || BaseReg == X86::RIP)
1683         return true;
1684       // Allow re-materialization of PIC load.
1685       if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1686         return false;
1687       const MachineFunction &MF = *MI->getParent()->getParent();
1688       const MachineRegisterInfo &MRI = MF.getRegInfo();
1689       return regIsPICBase(BaseReg, MRI);
1690     }
1691     return false;
1692   }
1693 
1694   case X86::LEA32r:
1695   case X86::LEA64r: {
1696     if (MI->getOperand(2).isImm() &&
1697         MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1698         !MI->getOperand(4).isReg()) {
1699       // lea fi#, lea GV, etc. are all rematerializable.
1700       if (!MI->getOperand(1).isReg())
1701         return true;
1702       unsigned BaseReg = MI->getOperand(1).getReg();
1703       if (BaseReg == 0)
1704         return true;
1705       // Allow re-materialization of lea PICBase + x.
1706       const MachineFunction &MF = *MI->getParent()->getParent();
1707       const MachineRegisterInfo &MRI = MF.getRegInfo();
1708       return regIsPICBase(BaseReg, MRI);
1709     }
1710     return false;
1711   }
1712   }
1713 
1714   // All other instructions marked M_REMATERIALIZABLE are always trivially
1715   // rematerializable.
1716   return true;
1717 }
1718 
1719 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1720 /// would clobber the EFLAGS condition register. Note the result may be
1721 /// conservative. If it cannot definitely determine the safety after visiting
1722 /// a few instructions in each direction it assumes it's not safe.
1723 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1724                                   MachineBasicBlock::iterator I) {
1725   MachineBasicBlock::iterator E = MBB.end();
1726 
1727   // For compile time consideration, if we are not able to determine the
1728   // safety after visiting 4 instructions in each direction, we will assume
1729   // it's not safe.
1730   MachineBasicBlock::iterator Iter = I;
1731   for (unsigned i = 0; Iter != E && i < 4; ++i) {
1732     bool SeenDef = false;
1733     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1734       MachineOperand &MO = Iter->getOperand(j);
1735       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1736         SeenDef = true;
1737       if (!MO.isReg())
1738         continue;
1739       if (MO.getReg() == X86::EFLAGS) {
1740         if (MO.isUse())
1741           return false;
1742         SeenDef = true;
1743       }
1744     }
1745 
1746     if (SeenDef)
1747       // This instruction defines EFLAGS, no need to look any further.
1748       return true;
1749     ++Iter;
1750     // Skip over DBG_VALUE.
1751     while (Iter != E && Iter->isDebugValue())
1752       ++Iter;
1753   }
1754 
1755   // It is safe to clobber EFLAGS at the end of a block of no successor has it
1756   // live in.
1757   if (Iter == E) {
1758     for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1759            SE = MBB.succ_end(); SI != SE; ++SI)
1760       if ((*SI)->isLiveIn(X86::EFLAGS))
1761         return false;
1762     return true;
1763   }
1764 
1765   MachineBasicBlock::iterator B = MBB.begin();
1766   Iter = I;
1767   for (unsigned i = 0; i < 4; ++i) {
1768     // If we make it to the beginning of the block, it's safe to clobber
1769     // EFLAGS iff EFLAGS is not live-in.
1770     if (Iter == B)
1771       return !MBB.isLiveIn(X86::EFLAGS);
1772 
1773     --Iter;
1774     // Skip over DBG_VALUE.
1775     while (Iter != B && Iter->isDebugValue())
1776       --Iter;
1777 
1778     bool SawKill = false;
1779     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1780       MachineOperand &MO = Iter->getOperand(j);
1781       // A register mask may clobber EFLAGS, but we should still look for a
1782       // live EFLAGS def.
1783       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1784         SawKill = true;
1785       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1786         if (MO.isDef()) return MO.isDead();
1787         if (MO.isKill()) SawKill = true;
1788       }
1789     }
1790 
1791     if (SawKill)
1792       // This instruction kills EFLAGS and doesn't redefine it, so
1793       // there's no need to look further.
1794       return true;
1795   }
1796 
1797   // Conservative answer.
1798   return false;
1799 }
1800 
1801 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1802                                  MachineBasicBlock::iterator I,
1803                                  unsigned DestReg, unsigned SubIdx,
1804                                  const MachineInstr *Orig,
1805                                  const TargetRegisterInfo &TRI) const {
1806   // MOV32r0 is implemented with a xor which clobbers condition code.
1807   // Re-materialize it as movri instructions to avoid side effects.
1808   unsigned Opc = Orig->getOpcode();
1809   if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
1810     DebugLoc DL = Orig->getDebugLoc();
1811     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
1812       .addImm(0);
1813   } else {
1814     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1815     MBB.insert(I, MI);
1816   }
1817 
1818   MachineInstr *NewMI = prior(I);
1819   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1820 }
1821 
1822 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1823 /// is not marked dead.
1824 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1825   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1826     MachineOperand &MO = MI->getOperand(i);
1827     if (MO.isReg() && MO.isDef() &&
1828         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1829       return true;
1830     }
1831   }
1832   return false;
1833 }
1834 
1835 /// getTruncatedShiftCount - check whether the shift count for a machine operand
1836 /// is non-zero.
1837 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
1838                                               unsigned ShiftAmtOperandIdx) {
1839   // The shift count is six bits with the REX.W prefix and five bits without.
1840   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1841   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
1842   return Imm & ShiftCountMask;
1843 }
1844 
1845 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
1846 /// can be represented by a LEA instruction.
1847 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1848   // Left shift instructions can be transformed into load-effective-address
1849   // instructions if we can encode them appropriately.
1850   // A LEA instruction utilizes a SIB byte to encode it's scale factor.
1851   // The SIB.scale field is two bits wide which means that we can encode any
1852   // shift amount less than 4.
1853   return ShAmt < 4 && ShAmt > 0;
1854 }
1855 
1856 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
1857                                   unsigned Opc, bool AllowSP,
1858                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
1859                                   MachineOperand &ImplicitOp) const {
1860   MachineFunction &MF = *MI->getParent()->getParent();
1861   const TargetRegisterClass *RC;
1862   if (AllowSP) {
1863     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1864   } else {
1865     RC = Opc != X86::LEA32r ?
1866       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1867   }
1868   unsigned SrcReg = Src.getReg();
1869 
1870   // For both LEA64 and LEA32 the register already has essentially the right
1871   // type (32-bit or 64-bit) we may just need to forbid SP.
1872   if (Opc != X86::LEA64_32r) {
1873     NewSrc = SrcReg;
1874     isKill = Src.isKill();
1875     isUndef = Src.isUndef();
1876 
1877     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
1878         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1879       return false;
1880 
1881     return true;
1882   }
1883 
1884   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1885   // another we need to add 64-bit registers to the final MI.
1886   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1887     ImplicitOp = Src;
1888     ImplicitOp.setImplicit();
1889 
1890     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
1891     MachineBasicBlock::LivenessQueryResult LQR =
1892       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
1893 
1894     switch (LQR) {
1895     case MachineBasicBlock::LQR_Unknown:
1896       // We can't give sane liveness flags to the instruction, abandon LEA
1897       // formation.
1898       return false;
1899     case MachineBasicBlock::LQR_Live:
1900       isKill = MI->killsRegister(SrcReg);
1901       isUndef = false;
1902       break;
1903     default:
1904       // The physreg itself is dead, so we have to use it as an <undef>.
1905       isKill = false;
1906       isUndef = true;
1907       break;
1908     }
1909   } else {
1910     // Virtual register of the wrong class, we have to create a temporary 64-bit
1911     // vreg to feed into the LEA.
1912     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1913     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1914             get(TargetOpcode::COPY))
1915       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1916         .addOperand(Src);
1917 
1918     // Which is obviously going to be dead after we're done with it.
1919     isKill = true;
1920     isUndef = false;
1921   }
1922 
1923   // We've set all the parameters without issue.
1924   return true;
1925 }
1926 
1927 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1928 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1929 /// to a 32-bit superregister and then truncating back down to a 16-bit
1930 /// subregister.
1931 MachineInstr *
1932 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1933                                            MachineFunction::iterator &MFI,
1934                                            MachineBasicBlock::iterator &MBBI,
1935                                            LiveVariables *LV) const {
1936   MachineInstr *MI = MBBI;
1937   unsigned Dest = MI->getOperand(0).getReg();
1938   unsigned Src = MI->getOperand(1).getReg();
1939   bool isDead = MI->getOperand(0).isDead();
1940   bool isKill = MI->getOperand(1).isKill();
1941 
1942   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1943   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1944   unsigned Opc, leaInReg;
1945   if (TM.getSubtarget<X86Subtarget>().is64Bit()) {
1946     Opc = X86::LEA64_32r;
1947     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1948   } else {
1949     Opc = X86::LEA32r;
1950     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1951   }
1952 
1953   // Build and insert into an implicit UNDEF value. This is OK because
1954   // well be shifting and then extracting the lower 16-bits.
1955   // This has the potential to cause partial register stall. e.g.
1956   //   movw    (%rbp,%rcx,2), %dx
1957   //   leal    -65(%rdx), %esi
1958   // But testing has shown this *does* help performance in 64-bit mode (at
1959   // least on modern x86 machines).
1960   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1961   MachineInstr *InsMI =
1962     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1963     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1964     .addReg(Src, getKillRegState(isKill));
1965 
1966   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1967                                     get(Opc), leaOutReg);
1968   switch (MIOpc) {
1969   default: llvm_unreachable("Unreachable!");
1970   case X86::SHL16ri: {
1971     unsigned ShAmt = MI->getOperand(2).getImm();
1972     MIB.addReg(0).addImm(1 << ShAmt)
1973        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1974     break;
1975   }
1976   case X86::INC16r:
1977   case X86::INC64_16r:
1978     addRegOffset(MIB, leaInReg, true, 1);
1979     break;
1980   case X86::DEC16r:
1981   case X86::DEC64_16r:
1982     addRegOffset(MIB, leaInReg, true, -1);
1983     break;
1984   case X86::ADD16ri:
1985   case X86::ADD16ri8:
1986   case X86::ADD16ri_DB:
1987   case X86::ADD16ri8_DB:
1988     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1989     break;
1990   case X86::ADD16rr:
1991   case X86::ADD16rr_DB: {
1992     unsigned Src2 = MI->getOperand(2).getReg();
1993     bool isKill2 = MI->getOperand(2).isKill();
1994     unsigned leaInReg2 = 0;
1995     MachineInstr *InsMI2 = 0;
1996     if (Src == Src2) {
1997       // ADD16rr %reg1028<kill>, %reg1028
1998       // just a single insert_subreg.
1999       addRegReg(MIB, leaInReg, true, leaInReg, false);
2000     } else {
2001       if (TM.getSubtarget<X86Subtarget>().is64Bit())
2002         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2003       else
2004         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2005       // Build and insert into an implicit UNDEF value. This is OK because
2006       // well be shifting and then extracting the lower 16-bits.
2007       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2008       InsMI2 =
2009         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2010         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2011         .addReg(Src2, getKillRegState(isKill2));
2012       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2013     }
2014     if (LV && isKill2 && InsMI2)
2015       LV->replaceKillInstruction(Src2, MI, InsMI2);
2016     break;
2017   }
2018   }
2019 
2020   MachineInstr *NewMI = MIB;
2021   MachineInstr *ExtMI =
2022     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2023     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2024     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2025 
2026   if (LV) {
2027     // Update live variables
2028     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2029     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2030     if (isKill)
2031       LV->replaceKillInstruction(Src, MI, InsMI);
2032     if (isDead)
2033       LV->replaceKillInstruction(Dest, MI, ExtMI);
2034   }
2035 
2036   return ExtMI;
2037 }
2038 
2039 /// convertToThreeAddress - This method must be implemented by targets that
2040 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2041 /// may be able to convert a two-address instruction into a true
2042 /// three-address instruction on demand.  This allows the X86 target (for
2043 /// example) to convert ADD and SHL instructions into LEA instructions if they
2044 /// would require register copies due to two-addressness.
2045 ///
2046 /// This method returns a null pointer if the transformation cannot be
2047 /// performed, otherwise it returns the new instruction.
2048 ///
2049 MachineInstr *
2050 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2051                                     MachineBasicBlock::iterator &MBBI,
2052                                     LiveVariables *LV) const {
2053   MachineInstr *MI = MBBI;
2054 
2055   // The following opcodes also sets the condition code register(s). Only
2056   // convert them to equivalent lea if the condition code register def's
2057   // are dead!
2058   if (hasLiveCondCodeDef(MI))
2059     return 0;
2060 
2061   MachineFunction &MF = *MI->getParent()->getParent();
2062   // All instructions input are two-addr instructions.  Get the known operands.
2063   const MachineOperand &Dest = MI->getOperand(0);
2064   const MachineOperand &Src = MI->getOperand(1);
2065 
2066   MachineInstr *NewMI = NULL;
2067   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2068   // we have better subtarget support, enable the 16-bit LEA generation here.
2069   // 16-bit LEA is also slow on Core2.
2070   bool DisableLEA16 = true;
2071   bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2072 
2073   unsigned MIOpc = MI->getOpcode();
2074   switch (MIOpc) {
2075   case X86::SHUFPSrri: {
2076     assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
2077     if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
2078 
2079     unsigned B = MI->getOperand(1).getReg();
2080     unsigned C = MI->getOperand(2).getReg();
2081     if (B != C) return 0;
2082     unsigned M = MI->getOperand(3).getImm();
2083     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2084       .addOperand(Dest).addOperand(Src).addImm(M);
2085     break;
2086   }
2087   case X86::SHUFPDrri: {
2088     assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
2089     if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
2090 
2091     unsigned B = MI->getOperand(1).getReg();
2092     unsigned C = MI->getOperand(2).getReg();
2093     if (B != C) return 0;
2094     unsigned M = MI->getOperand(3).getImm();
2095 
2096     // Convert to PSHUFD mask.
2097     M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
2098 
2099     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
2100       .addOperand(Dest).addOperand(Src).addImm(M);
2101     break;
2102   }
2103   case X86::SHL64ri: {
2104     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2105     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2106     if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2107 
2108     // LEA can't handle RSP.
2109     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2110         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2111                                            &X86::GR64_NOSPRegClass))
2112       return 0;
2113 
2114     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2115       .addOperand(Dest)
2116       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2117     break;
2118   }
2119   case X86::SHL32ri: {
2120     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2121     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2122     if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2123 
2124     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2125 
2126     // LEA can't handle ESP.
2127     bool isKill, isUndef;
2128     unsigned SrcReg;
2129     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2130     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2131                         SrcReg, isKill, isUndef, ImplicitOp))
2132       return 0;
2133 
2134     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2135       .addOperand(Dest)
2136       .addReg(0).addImm(1 << ShAmt)
2137       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2138       .addImm(0).addReg(0);
2139     if (ImplicitOp.getReg() != 0)
2140       MIB.addOperand(ImplicitOp);
2141     NewMI = MIB;
2142 
2143     break;
2144   }
2145   case X86::SHL16ri: {
2146     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2147     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2148     if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
2149 
2150     if (DisableLEA16)
2151       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2152     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2153       .addOperand(Dest)
2154       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2155     break;
2156   }
2157   default: {
2158 
2159     switch (MIOpc) {
2160     default: return 0;
2161     case X86::INC64r:
2162     case X86::INC32r:
2163     case X86::INC64_32r: {
2164       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2165       unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2166         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2167       bool isKill, isUndef;
2168       unsigned SrcReg;
2169       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2170       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2171                           SrcReg, isKill, isUndef, ImplicitOp))
2172         return 0;
2173 
2174       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2175           .addOperand(Dest)
2176           .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2177       if (ImplicitOp.getReg() != 0)
2178         MIB.addOperand(ImplicitOp);
2179 
2180       NewMI = addOffset(MIB, 1);
2181       break;
2182     }
2183     case X86::INC16r:
2184     case X86::INC64_16r:
2185       if (DisableLEA16)
2186         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2187       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2188       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2189                         .addOperand(Dest).addOperand(Src), 1);
2190       break;
2191     case X86::DEC64r:
2192     case X86::DEC32r:
2193     case X86::DEC64_32r: {
2194       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2195       unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2196         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2197 
2198       bool isKill, isUndef;
2199       unsigned SrcReg;
2200       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2201       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2202                           SrcReg, isKill, isUndef, ImplicitOp))
2203         return 0;
2204 
2205       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2206           .addOperand(Dest)
2207           .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2208       if (ImplicitOp.getReg() != 0)
2209         MIB.addOperand(ImplicitOp);
2210 
2211       NewMI = addOffset(MIB, -1);
2212 
2213       break;
2214     }
2215     case X86::DEC16r:
2216     case X86::DEC64_16r:
2217       if (DisableLEA16)
2218         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2219       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2220       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2221                         .addOperand(Dest).addOperand(Src), -1);
2222       break;
2223     case X86::ADD64rr:
2224     case X86::ADD64rr_DB:
2225     case X86::ADD32rr:
2226     case X86::ADD32rr_DB: {
2227       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2228       unsigned Opc;
2229       if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2230         Opc = X86::LEA64r;
2231       else
2232         Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2233 
2234       bool isKill, isUndef;
2235       unsigned SrcReg;
2236       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2237       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2238                           SrcReg, isKill, isUndef, ImplicitOp))
2239         return 0;
2240 
2241       const MachineOperand &Src2 = MI->getOperand(2);
2242       bool isKill2, isUndef2;
2243       unsigned SrcReg2;
2244       MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2245       if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2246                           SrcReg2, isKill2, isUndef2, ImplicitOp2))
2247         return 0;
2248 
2249       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2250         .addOperand(Dest);
2251       if (ImplicitOp.getReg() != 0)
2252         MIB.addOperand(ImplicitOp);
2253       if (ImplicitOp2.getReg() != 0)
2254         MIB.addOperand(ImplicitOp2);
2255 
2256       NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2257 
2258       // Preserve undefness of the operands.
2259       NewMI->getOperand(1).setIsUndef(isUndef);
2260       NewMI->getOperand(3).setIsUndef(isUndef2);
2261 
2262       if (LV && Src2.isKill())
2263         LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2264       break;
2265     }
2266     case X86::ADD16rr:
2267     case X86::ADD16rr_DB: {
2268       if (DisableLEA16)
2269         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2270       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2271       unsigned Src2 = MI->getOperand(2).getReg();
2272       bool isKill2 = MI->getOperand(2).isKill();
2273       NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2274                         .addOperand(Dest),
2275                         Src.getReg(), Src.isKill(), Src2, isKill2);
2276 
2277       // Preserve undefness of the operands.
2278       bool isUndef = MI->getOperand(1).isUndef();
2279       bool isUndef2 = MI->getOperand(2).isUndef();
2280       NewMI->getOperand(1).setIsUndef(isUndef);
2281       NewMI->getOperand(3).setIsUndef(isUndef2);
2282 
2283       if (LV && isKill2)
2284         LV->replaceKillInstruction(Src2, MI, NewMI);
2285       break;
2286     }
2287     case X86::ADD64ri32:
2288     case X86::ADD64ri8:
2289     case X86::ADD64ri32_DB:
2290     case X86::ADD64ri8_DB:
2291       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2292       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2293                         .addOperand(Dest).addOperand(Src),
2294                         MI->getOperand(2).getImm());
2295       break;
2296     case X86::ADD32ri:
2297     case X86::ADD32ri8:
2298     case X86::ADD32ri_DB:
2299     case X86::ADD32ri8_DB: {
2300       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2301       unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2302 
2303       bool isKill, isUndef;
2304       unsigned SrcReg;
2305       MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2306       if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2307                           SrcReg, isKill, isUndef, ImplicitOp))
2308         return 0;
2309 
2310       MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2311           .addOperand(Dest)
2312           .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2313       if (ImplicitOp.getReg() != 0)
2314         MIB.addOperand(ImplicitOp);
2315 
2316       NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2317       break;
2318     }
2319     case X86::ADD16ri:
2320     case X86::ADD16ri8:
2321     case X86::ADD16ri_DB:
2322     case X86::ADD16ri8_DB:
2323       if (DisableLEA16)
2324         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2325       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2326       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2327                         .addOperand(Dest).addOperand(Src),
2328                         MI->getOperand(2).getImm());
2329       break;
2330     }
2331   }
2332   }
2333 
2334   if (!NewMI) return 0;
2335 
2336   if (LV) {  // Update live variables
2337     if (Src.isKill())
2338       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2339     if (Dest.isDead())
2340       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2341   }
2342 
2343   MFI->insert(MBBI, NewMI);          // Insert the new inst
2344   return NewMI;
2345 }
2346 
2347 /// commuteInstruction - We have a few instructions that must be hacked on to
2348 /// commute them.
2349 ///
2350 MachineInstr *
2351 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2352   switch (MI->getOpcode()) {
2353   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2354   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2355   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2356   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2357   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2358   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2359     unsigned Opc;
2360     unsigned Size;
2361     switch (MI->getOpcode()) {
2362     default: llvm_unreachable("Unreachable!");
2363     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2364     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2365     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2366     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2367     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2368     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2369     }
2370     unsigned Amt = MI->getOperand(3).getImm();
2371     if (NewMI) {
2372       MachineFunction &MF = *MI->getParent()->getParent();
2373       MI = MF.CloneMachineInstr(MI);
2374       NewMI = false;
2375     }
2376     MI->setDesc(get(Opc));
2377     MI->getOperand(3).setImm(Size-Amt);
2378     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2379   }
2380   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
2381   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2382   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
2383   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2384   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2385   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
2386   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
2387   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2388   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2389   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
2390   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
2391   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2392   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
2393   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2394   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
2395   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2396     unsigned Opc;
2397     switch (MI->getOpcode()) {
2398     default: llvm_unreachable("Unreachable!");
2399     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2400     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2401     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2402     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2403     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2404     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2405     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2406     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2407     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2408     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2409     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2410     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2411     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2412     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2413     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2414     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2415     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2416     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2417     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2418     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2419     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2420     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2421     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2422     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2423     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2424     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2425     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2426     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2427     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2428     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2429     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2430     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2431     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2432     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2433     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2434     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2435     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2436     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2437     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2438     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2439     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2440     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2441     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2442     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2443     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2444     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2445     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2446     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2447     }
2448     if (NewMI) {
2449       MachineFunction &MF = *MI->getParent()->getParent();
2450       MI = MF.CloneMachineInstr(MI);
2451       NewMI = false;
2452     }
2453     MI->setDesc(get(Opc));
2454     // Fallthrough intended.
2455   }
2456   default:
2457     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2458   }
2459 }
2460 
2461 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2462   switch (BrOpc) {
2463   default: return X86::COND_INVALID;
2464   case X86::JE_4:  return X86::COND_E;
2465   case X86::JNE_4: return X86::COND_NE;
2466   case X86::JL_4:  return X86::COND_L;
2467   case X86::JLE_4: return X86::COND_LE;
2468   case X86::JG_4:  return X86::COND_G;
2469   case X86::JGE_4: return X86::COND_GE;
2470   case X86::JB_4:  return X86::COND_B;
2471   case X86::JBE_4: return X86::COND_BE;
2472   case X86::JA_4:  return X86::COND_A;
2473   case X86::JAE_4: return X86::COND_AE;
2474   case X86::JS_4:  return X86::COND_S;
2475   case X86::JNS_4: return X86::COND_NS;
2476   case X86::JP_4:  return X86::COND_P;
2477   case X86::JNP_4: return X86::COND_NP;
2478   case X86::JO_4:  return X86::COND_O;
2479   case X86::JNO_4: return X86::COND_NO;
2480   }
2481 }
2482 
2483 /// getCondFromSETOpc - return condition code of a SET opcode.
2484 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2485   switch (Opc) {
2486   default: return X86::COND_INVALID;
2487   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
2488   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2489   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
2490   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2491   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
2492   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
2493   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2494   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
2495   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2496   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2497   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2498   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2499   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2500   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
2501   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
2502   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
2503   }
2504 }
2505 
2506 /// getCondFromCmovOpc - return condition code of a CMov opcode.
2507 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2508   switch (Opc) {
2509   default: return X86::COND_INVALID;
2510   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
2511   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
2512     return X86::COND_A;
2513   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2514   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2515     return X86::COND_AE;
2516   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
2517   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
2518     return X86::COND_B;
2519   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2520   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2521     return X86::COND_BE;
2522   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
2523   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
2524     return X86::COND_E;
2525   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
2526   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
2527     return X86::COND_G;
2528   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2529   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2530     return X86::COND_GE;
2531   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
2532   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
2533     return X86::COND_L;
2534   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2535   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2536     return X86::COND_LE;
2537   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2538   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2539     return X86::COND_NE;
2540   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2541   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2542     return X86::COND_NO;
2543   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2544   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2545     return X86::COND_NP;
2546   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2547   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2548     return X86::COND_NS;
2549   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
2550   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
2551     return X86::COND_O;
2552   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
2553   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
2554     return X86::COND_P;
2555   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
2556   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
2557     return X86::COND_S;
2558   }
2559 }
2560 
2561 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2562   switch (CC) {
2563   default: llvm_unreachable("Illegal condition code!");
2564   case X86::COND_E:  return X86::JE_4;
2565   case X86::COND_NE: return X86::JNE_4;
2566   case X86::COND_L:  return X86::JL_4;
2567   case X86::COND_LE: return X86::JLE_4;
2568   case X86::COND_G:  return X86::JG_4;
2569   case X86::COND_GE: return X86::JGE_4;
2570   case X86::COND_B:  return X86::JB_4;
2571   case X86::COND_BE: return X86::JBE_4;
2572   case X86::COND_A:  return X86::JA_4;
2573   case X86::COND_AE: return X86::JAE_4;
2574   case X86::COND_S:  return X86::JS_4;
2575   case X86::COND_NS: return X86::JNS_4;
2576   case X86::COND_P:  return X86::JP_4;
2577   case X86::COND_NP: return X86::JNP_4;
2578   case X86::COND_O:  return X86::JO_4;
2579   case X86::COND_NO: return X86::JNO_4;
2580   }
2581 }
2582 
2583 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2584 /// e.g. turning COND_E to COND_NE.
2585 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2586   switch (CC) {
2587   default: llvm_unreachable("Illegal condition code!");
2588   case X86::COND_E:  return X86::COND_NE;
2589   case X86::COND_NE: return X86::COND_E;
2590   case X86::COND_L:  return X86::COND_GE;
2591   case X86::COND_LE: return X86::COND_G;
2592   case X86::COND_G:  return X86::COND_LE;
2593   case X86::COND_GE: return X86::COND_L;
2594   case X86::COND_B:  return X86::COND_AE;
2595   case X86::COND_BE: return X86::COND_A;
2596   case X86::COND_A:  return X86::COND_BE;
2597   case X86::COND_AE: return X86::COND_B;
2598   case X86::COND_S:  return X86::COND_NS;
2599   case X86::COND_NS: return X86::COND_S;
2600   case X86::COND_P:  return X86::COND_NP;
2601   case X86::COND_NP: return X86::COND_P;
2602   case X86::COND_O:  return X86::COND_NO;
2603   case X86::COND_NO: return X86::COND_O;
2604   }
2605 }
2606 
2607 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2608 /// the condition code if we modify the instructions such that flags are
2609 /// set by MI(b,a).
2610 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2611   switch (CC) {
2612   default: return X86::COND_INVALID;
2613   case X86::COND_E:  return X86::COND_E;
2614   case X86::COND_NE: return X86::COND_NE;
2615   case X86::COND_L:  return X86::COND_G;
2616   case X86::COND_LE: return X86::COND_GE;
2617   case X86::COND_G:  return X86::COND_L;
2618   case X86::COND_GE: return X86::COND_LE;
2619   case X86::COND_B:  return X86::COND_A;
2620   case X86::COND_BE: return X86::COND_AE;
2621   case X86::COND_A:  return X86::COND_B;
2622   case X86::COND_AE: return X86::COND_BE;
2623   }
2624 }
2625 
2626 /// getSETFromCond - Return a set opcode for the given condition and
2627 /// whether it has memory operand.
2628 static unsigned getSETFromCond(X86::CondCode CC,
2629                                bool HasMemoryOperand) {
2630   static const uint16_t Opc[16][2] = {
2631     { X86::SETAr,  X86::SETAm  },
2632     { X86::SETAEr, X86::SETAEm },
2633     { X86::SETBr,  X86::SETBm  },
2634     { X86::SETBEr, X86::SETBEm },
2635     { X86::SETEr,  X86::SETEm  },
2636     { X86::SETGr,  X86::SETGm  },
2637     { X86::SETGEr, X86::SETGEm },
2638     { X86::SETLr,  X86::SETLm  },
2639     { X86::SETLEr, X86::SETLEm },
2640     { X86::SETNEr, X86::SETNEm },
2641     { X86::SETNOr, X86::SETNOm },
2642     { X86::SETNPr, X86::SETNPm },
2643     { X86::SETNSr, X86::SETNSm },
2644     { X86::SETOr,  X86::SETOm  },
2645     { X86::SETPr,  X86::SETPm  },
2646     { X86::SETSr,  X86::SETSm  }
2647   };
2648 
2649   assert(CC < 16 && "Can only handle standard cond codes");
2650   return Opc[CC][HasMemoryOperand ? 1 : 0];
2651 }
2652 
2653 /// getCMovFromCond - Return a cmov opcode for the given condition,
2654 /// register size in bytes, and operand type.
2655 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes,
2656                                 bool HasMemoryOperand) {
2657   static const uint16_t Opc[32][3] = {
2658     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
2659     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2660     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
2661     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2662     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
2663     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
2664     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2665     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
2666     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2667     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2668     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2669     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2670     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2671     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
2672     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
2673     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
2674     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
2675     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2676     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
2677     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2678     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
2679     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
2680     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2681     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
2682     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2683     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2684     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2685     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2686     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2687     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
2688     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
2689     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
2690   };
2691 
2692   assert(CC < 16 && "Can only handle standard cond codes");
2693   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2694   switch(RegBytes) {
2695   default: llvm_unreachable("Illegal register size!");
2696   case 2: return Opc[Idx][0];
2697   case 4: return Opc[Idx][1];
2698   case 8: return Opc[Idx][2];
2699   }
2700 }
2701 
2702 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2703   if (!MI->isTerminator()) return false;
2704 
2705   // Conditional branch is a special case.
2706   if (MI->isBranch() && !MI->isBarrier())
2707     return true;
2708   if (!MI->isPredicable())
2709     return true;
2710   return !isPredicated(MI);
2711 }
2712 
2713 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2714                                  MachineBasicBlock *&TBB,
2715                                  MachineBasicBlock *&FBB,
2716                                  SmallVectorImpl<MachineOperand> &Cond,
2717                                  bool AllowModify) const {
2718   // Start from the bottom of the block and work up, examining the
2719   // terminator instructions.
2720   MachineBasicBlock::iterator I = MBB.end();
2721   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2722   while (I != MBB.begin()) {
2723     --I;
2724     if (I->isDebugValue())
2725       continue;
2726 
2727     // Working from the bottom, when we see a non-terminator instruction, we're
2728     // done.
2729     if (!isUnpredicatedTerminator(I))
2730       break;
2731 
2732     // A terminator that isn't a branch can't easily be handled by this
2733     // analysis.
2734     if (!I->isBranch())
2735       return true;
2736 
2737     // Handle unconditional branches.
2738     if (I->getOpcode() == X86::JMP_4) {
2739       UnCondBrIter = I;
2740 
2741       if (!AllowModify) {
2742         TBB = I->getOperand(0).getMBB();
2743         continue;
2744       }
2745 
2746       // If the block has any instructions after a JMP, delete them.
2747       while (llvm::next(I) != MBB.end())
2748         llvm::next(I)->eraseFromParent();
2749 
2750       Cond.clear();
2751       FBB = 0;
2752 
2753       // Delete the JMP if it's equivalent to a fall-through.
2754       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2755         TBB = 0;
2756         I->eraseFromParent();
2757         I = MBB.end();
2758         UnCondBrIter = MBB.end();
2759         continue;
2760       }
2761 
2762       // TBB is used to indicate the unconditional destination.
2763       TBB = I->getOperand(0).getMBB();
2764       continue;
2765     }
2766 
2767     // Handle conditional branches.
2768     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2769     if (BranchCode == X86::COND_INVALID)
2770       return true;  // Can't handle indirect branch.
2771 
2772     // Working from the bottom, handle the first conditional branch.
2773     if (Cond.empty()) {
2774       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2775       if (AllowModify && UnCondBrIter != MBB.end() &&
2776           MBB.isLayoutSuccessor(TargetBB)) {
2777         // If we can modify the code and it ends in something like:
2778         //
2779         //     jCC L1
2780         //     jmp L2
2781         //   L1:
2782         //     ...
2783         //   L2:
2784         //
2785         // Then we can change this to:
2786         //
2787         //     jnCC L2
2788         //   L1:
2789         //     ...
2790         //   L2:
2791         //
2792         // Which is a bit more efficient.
2793         // We conditionally jump to the fall-through block.
2794         BranchCode = GetOppositeBranchCondition(BranchCode);
2795         unsigned JNCC = GetCondBranchFromCond(BranchCode);
2796         MachineBasicBlock::iterator OldInst = I;
2797 
2798         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2799           .addMBB(UnCondBrIter->getOperand(0).getMBB());
2800         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2801           .addMBB(TargetBB);
2802 
2803         OldInst->eraseFromParent();
2804         UnCondBrIter->eraseFromParent();
2805 
2806         // Restart the analysis.
2807         UnCondBrIter = MBB.end();
2808         I = MBB.end();
2809         continue;
2810       }
2811 
2812       FBB = TBB;
2813       TBB = I->getOperand(0).getMBB();
2814       Cond.push_back(MachineOperand::CreateImm(BranchCode));
2815       continue;
2816     }
2817 
2818     // Handle subsequent conditional branches. Only handle the case where all
2819     // conditional branches branch to the same destination and their condition
2820     // opcodes fit one of the special multi-branch idioms.
2821     assert(Cond.size() == 1);
2822     assert(TBB);
2823 
2824     // Only handle the case where all conditional branches branch to the same
2825     // destination.
2826     if (TBB != I->getOperand(0).getMBB())
2827       return true;
2828 
2829     // If the conditions are the same, we can leave them alone.
2830     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2831     if (OldBranchCode == BranchCode)
2832       continue;
2833 
2834     // If they differ, see if they fit one of the known patterns. Theoretically,
2835     // we could handle more patterns here, but we shouldn't expect to see them
2836     // if instruction selection has done a reasonable job.
2837     if ((OldBranchCode == X86::COND_NP &&
2838          BranchCode == X86::COND_E) ||
2839         (OldBranchCode == X86::COND_E &&
2840          BranchCode == X86::COND_NP))
2841       BranchCode = X86::COND_NP_OR_E;
2842     else if ((OldBranchCode == X86::COND_P &&
2843               BranchCode == X86::COND_NE) ||
2844              (OldBranchCode == X86::COND_NE &&
2845               BranchCode == X86::COND_P))
2846       BranchCode = X86::COND_NE_OR_P;
2847     else
2848       return true;
2849 
2850     // Update the MachineOperand.
2851     Cond[0].setImm(BranchCode);
2852   }
2853 
2854   return false;
2855 }
2856 
2857 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2858   MachineBasicBlock::iterator I = MBB.end();
2859   unsigned Count = 0;
2860 
2861   while (I != MBB.begin()) {
2862     --I;
2863     if (I->isDebugValue())
2864       continue;
2865     if (I->getOpcode() != X86::JMP_4 &&
2866         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2867       break;
2868     // Remove the branch.
2869     I->eraseFromParent();
2870     I = MBB.end();
2871     ++Count;
2872   }
2873 
2874   return Count;
2875 }
2876 
2877 unsigned
2878 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2879                            MachineBasicBlock *FBB,
2880                            const SmallVectorImpl<MachineOperand> &Cond,
2881                            DebugLoc DL) const {
2882   // Shouldn't be a fall through.
2883   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2884   assert((Cond.size() == 1 || Cond.size() == 0) &&
2885          "X86 branch conditions have one component!");
2886 
2887   if (Cond.empty()) {
2888     // Unconditional branch?
2889     assert(!FBB && "Unconditional branch with multiple successors!");
2890     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2891     return 1;
2892   }
2893 
2894   // Conditional branch.
2895   unsigned Count = 0;
2896   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2897   switch (CC) {
2898   case X86::COND_NP_OR_E:
2899     // Synthesize NP_OR_E with two branches.
2900     BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2901     ++Count;
2902     BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2903     ++Count;
2904     break;
2905   case X86::COND_NE_OR_P:
2906     // Synthesize NE_OR_P with two branches.
2907     BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2908     ++Count;
2909     BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2910     ++Count;
2911     break;
2912   default: {
2913     unsigned Opc = GetCondBranchFromCond(CC);
2914     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2915     ++Count;
2916   }
2917   }
2918   if (FBB) {
2919     // Two-way Conditional branch. Insert the second branch.
2920     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2921     ++Count;
2922   }
2923   return Count;
2924 }
2925 
2926 bool X86InstrInfo::
2927 canInsertSelect(const MachineBasicBlock &MBB,
2928                 const SmallVectorImpl<MachineOperand> &Cond,
2929                 unsigned TrueReg, unsigned FalseReg,
2930                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2931   // Not all subtargets have cmov instructions.
2932   if (!TM.getSubtarget<X86Subtarget>().hasCMov())
2933     return false;
2934   if (Cond.size() != 1)
2935     return false;
2936   // We cannot do the composite conditions, at least not in SSA form.
2937   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2938     return false;
2939 
2940   // Check register classes.
2941   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2942   const TargetRegisterClass *RC =
2943     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2944   if (!RC)
2945     return false;
2946 
2947   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2948   if (X86::GR16RegClass.hasSubClassEq(RC) ||
2949       X86::GR32RegClass.hasSubClassEq(RC) ||
2950       X86::GR64RegClass.hasSubClassEq(RC)) {
2951     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2952     // Bridge. Probably Ivy Bridge as well.
2953     CondCycles = 2;
2954     TrueCycles = 2;
2955     FalseCycles = 2;
2956     return true;
2957   }
2958 
2959   // Can't do vectors.
2960   return false;
2961 }
2962 
2963 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2964                                 MachineBasicBlock::iterator I, DebugLoc DL,
2965                                 unsigned DstReg,
2966                                 const SmallVectorImpl<MachineOperand> &Cond,
2967                                 unsigned TrueReg, unsigned FalseReg) const {
2968    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2969    assert(Cond.size() == 1 && "Invalid Cond array");
2970    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
2971                                   MRI.getRegClass(DstReg)->getSize(),
2972                                   false/*HasMemoryOperand*/);
2973    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
2974 }
2975 
2976 /// isHReg - Test if the given register is a physical h register.
2977 static bool isHReg(unsigned Reg) {
2978   return X86::GR8_ABCD_HRegClass.contains(Reg);
2979 }
2980 
2981 // Try and copy between VR128/VR64 and GR64 registers.
2982 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2983                                         const X86Subtarget& Subtarget) {
2984 
2985 
2986   // SrcReg(VR128) -> DestReg(GR64)
2987   // SrcReg(VR64)  -> DestReg(GR64)
2988   // SrcReg(GR64)  -> DestReg(VR128)
2989   // SrcReg(GR64)  -> DestReg(VR64)
2990 
2991   bool HasAVX = Subtarget.hasAVX();
2992   bool HasAVX512 = Subtarget.hasAVX512();
2993   if (X86::GR64RegClass.contains(DestReg)) {
2994     if (X86::VR128XRegClass.contains(SrcReg))
2995       // Copy from a VR128 register to a GR64 register.
2996       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
2997                                                X86::MOVPQIto64rr);
2998     if (X86::VR64RegClass.contains(SrcReg))
2999       // Copy from a VR64 register to a GR64 register.
3000       return X86::MOVSDto64rr;
3001   } else if (X86::GR64RegClass.contains(SrcReg)) {
3002     // Copy from a GR64 register to a VR128 register.
3003     if (X86::VR128XRegClass.contains(DestReg))
3004       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3005                                                X86::MOV64toPQIrr);
3006     // Copy from a GR64 register to a VR64 register.
3007     if (X86::VR64RegClass.contains(DestReg))
3008       return X86::MOV64toSDrr;
3009   }
3010 
3011   // SrcReg(FR32) -> DestReg(GR32)
3012   // SrcReg(GR32) -> DestReg(FR32)
3013 
3014   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3015     // Copy from a FR32 register to a GR32 register.
3016     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3017 
3018   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3019     // Copy from a GR32 register to a FR32 register.
3020     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3021   return 0;
3022 }
3023 
3024 inline static bool MaskRegClassContains(unsigned Reg) {
3025   return X86::VK8RegClass.contains(Reg) ||
3026          X86::VK16RegClass.contains(Reg) ||
3027          X86::VK1RegClass.contains(Reg);
3028 }
3029 static
3030 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3031   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3032       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3033       X86::VR512RegClass.contains(DestReg, SrcReg)) {
3034      DestReg = get512BitSuperRegister(DestReg);
3035      SrcReg = get512BitSuperRegister(SrcReg);
3036      return X86::VMOVAPSZrr;
3037   }
3038   if (MaskRegClassContains(DestReg) &&
3039       MaskRegClassContains(SrcReg))
3040     return X86::KMOVWkk;
3041   if (MaskRegClassContains(DestReg) &&
3042       (X86::GR32RegClass.contains(SrcReg) ||
3043        X86::GR16RegClass.contains(SrcReg) ||
3044        X86::GR8RegClass.contains(SrcReg))) {
3045     SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3046     return X86::KMOVWkr;
3047   }
3048   if ((X86::GR32RegClass.contains(DestReg) ||
3049        X86::GR16RegClass.contains(DestReg) ||
3050        X86::GR8RegClass.contains(DestReg)) &&
3051        MaskRegClassContains(SrcReg)) {
3052     DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3053     return X86::KMOVWrk;
3054   }
3055   return 0;
3056 }
3057 
3058 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3059                                MachineBasicBlock::iterator MI, DebugLoc DL,
3060                                unsigned DestReg, unsigned SrcReg,
3061                                bool KillSrc) const {
3062   // First deal with the normal symmetric copies.
3063   bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3064   bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
3065   unsigned Opc = 0;
3066   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3067     Opc = X86::MOV64rr;
3068   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3069     Opc = X86::MOV32rr;
3070   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3071     Opc = X86::MOV16rr;
3072   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3073     // Copying to or from a physical H register on x86-64 requires a NOREX
3074     // move.  Otherwise use a normal move.
3075     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3076         TM.getSubtarget<X86Subtarget>().is64Bit()) {
3077       Opc = X86::MOV8rr_NOREX;
3078       // Both operands must be encodable without an REX prefix.
3079       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3080              "8-bit H register can not be copied outside GR8_NOREX");
3081     } else
3082       Opc = X86::MOV8rr;
3083   }
3084   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3085     Opc = X86::MMX_MOVQ64rr;
3086   else if (HasAVX512)
3087     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3088   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3089     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3090   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3091     Opc = X86::VMOVAPSYrr;
3092   if (!Opc)
3093     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, TM.getSubtarget<X86Subtarget>());
3094 
3095   if (Opc) {
3096     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3097       .addReg(SrcReg, getKillRegState(KillSrc));
3098     return;
3099   }
3100 
3101   // Moving EFLAGS to / from another register requires a push and a pop.
3102   // Notice that we have to adjust the stack if we don't want to clobber the
3103   // first frame index. See X86FrameLowering.cpp - colobbersTheStack.
3104   if (SrcReg == X86::EFLAGS) {
3105     if (X86::GR64RegClass.contains(DestReg)) {
3106       BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3107       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3108       return;
3109     }
3110     if (X86::GR32RegClass.contains(DestReg)) {
3111       BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3112       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3113       return;
3114     }
3115   }
3116   if (DestReg == X86::EFLAGS) {
3117     if (X86::GR64RegClass.contains(SrcReg)) {
3118       BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3119         .addReg(SrcReg, getKillRegState(KillSrc));
3120       BuildMI(MBB, MI, DL, get(X86::POPF64));
3121       return;
3122     }
3123     if (X86::GR32RegClass.contains(SrcReg)) {
3124       BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3125         .addReg(SrcReg, getKillRegState(KillSrc));
3126       BuildMI(MBB, MI, DL, get(X86::POPF32));
3127       return;
3128     }
3129   }
3130 
3131   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3132                << " to " << RI.getName(DestReg) << '\n');
3133   llvm_unreachable("Cannot emit physreg copy instruction");
3134 }
3135 
3136 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3137                                       const TargetRegisterClass *RC,
3138                                       bool isStackAligned,
3139                                       const TargetMachine &TM,
3140                                       bool load) {
3141   if (TM.getSubtarget<X86Subtarget>().hasAVX512()) {
3142     if (X86::VK8RegClass.hasSubClassEq(RC)  ||
3143       X86::VK16RegClass.hasSubClassEq(RC))
3144       return load ? X86::KMOVWkm : X86::KMOVWmk;
3145     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3146       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3147     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3148       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3149     if (X86::VR512RegClass.hasSubClassEq(RC))
3150       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3151   }
3152 
3153   bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3154   switch (RC->getSize()) {
3155   default:
3156     llvm_unreachable("Unknown spill size");
3157   case 1:
3158     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3159     if (TM.getSubtarget<X86Subtarget>().is64Bit())
3160       // Copying to or from a physical H register on x86-64 requires a NOREX
3161       // move.  Otherwise use a normal move.
3162       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3163         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3164     return load ? X86::MOV8rm : X86::MOV8mr;
3165   case 2:
3166     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3167     return load ? X86::MOV16rm : X86::MOV16mr;
3168   case 4:
3169     if (X86::GR32RegClass.hasSubClassEq(RC))
3170       return load ? X86::MOV32rm : X86::MOV32mr;
3171     if (X86::FR32RegClass.hasSubClassEq(RC))
3172       return load ?
3173         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3174         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3175     if (X86::RFP32RegClass.hasSubClassEq(RC))
3176       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3177     llvm_unreachable("Unknown 4-byte regclass");
3178   case 8:
3179     if (X86::GR64RegClass.hasSubClassEq(RC))
3180       return load ? X86::MOV64rm : X86::MOV64mr;
3181     if (X86::FR64RegClass.hasSubClassEq(RC))
3182       return load ?
3183         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3184         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3185     if (X86::VR64RegClass.hasSubClassEq(RC))
3186       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3187     if (X86::RFP64RegClass.hasSubClassEq(RC))
3188       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3189     llvm_unreachable("Unknown 8-byte regclass");
3190   case 10:
3191     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3192     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3193   case 16: {
3194     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3195             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
3196     // If stack is realigned we can use aligned stores.
3197     if (isStackAligned)
3198       return load ?
3199         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3200         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3201     else
3202       return load ?
3203         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3204         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3205   }
3206   case 32:
3207     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3208             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
3209     // If stack is realigned we can use aligned stores.
3210     if (isStackAligned)
3211       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3212     else
3213       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3214   case 64:
3215     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3216     if (isStackAligned)
3217       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3218     else
3219       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3220   }
3221 }
3222 
3223 static unsigned getStoreRegOpcode(unsigned SrcReg,
3224                                   const TargetRegisterClass *RC,
3225                                   bool isStackAligned,
3226                                   TargetMachine &TM) {
3227   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
3228 }
3229 
3230 
3231 static unsigned getLoadRegOpcode(unsigned DestReg,
3232                                  const TargetRegisterClass *RC,
3233                                  bool isStackAligned,
3234                                  const TargetMachine &TM) {
3235   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
3236 }
3237 
3238 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3239                                        MachineBasicBlock::iterator MI,
3240                                        unsigned SrcReg, bool isKill, int FrameIdx,
3241                                        const TargetRegisterClass *RC,
3242                                        const TargetRegisterInfo *TRI) const {
3243   const MachineFunction &MF = *MBB.getParent();
3244   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3245          "Stack slot too small for store");
3246   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3247   bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
3248     RI.canRealignStack(MF);
3249   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
3250   DebugLoc DL = MBB.findDebugLoc(MI);
3251   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3252     .addReg(SrcReg, getKillRegState(isKill));
3253 }
3254 
3255 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3256                                   bool isKill,
3257                                   SmallVectorImpl<MachineOperand> &Addr,
3258                                   const TargetRegisterClass *RC,
3259                                   MachineInstr::mmo_iterator MMOBegin,
3260                                   MachineInstr::mmo_iterator MMOEnd,
3261                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
3262   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3263   bool isAligned = MMOBegin != MMOEnd &&
3264                    (*MMOBegin)->getAlignment() >= Alignment;
3265   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
3266   DebugLoc DL;
3267   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3268   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3269     MIB.addOperand(Addr[i]);
3270   MIB.addReg(SrcReg, getKillRegState(isKill));
3271   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3272   NewMIs.push_back(MIB);
3273 }
3274 
3275 
3276 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3277                                         MachineBasicBlock::iterator MI,
3278                                         unsigned DestReg, int FrameIdx,
3279                                         const TargetRegisterClass *RC,
3280                                         const TargetRegisterInfo *TRI) const {
3281   const MachineFunction &MF = *MBB.getParent();
3282   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3283   bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
3284     RI.canRealignStack(MF);
3285   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
3286   DebugLoc DL = MBB.findDebugLoc(MI);
3287   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
3288 }
3289 
3290 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
3291                                  SmallVectorImpl<MachineOperand> &Addr,
3292                                  const TargetRegisterClass *RC,
3293                                  MachineInstr::mmo_iterator MMOBegin,
3294                                  MachineInstr::mmo_iterator MMOEnd,
3295                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
3296   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3297   bool isAligned = MMOBegin != MMOEnd &&
3298                    (*MMOBegin)->getAlignment() >= Alignment;
3299   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
3300   DebugLoc DL;
3301   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3302   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3303     MIB.addOperand(Addr[i]);
3304   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3305   NewMIs.push_back(MIB);
3306 }
3307 
3308 bool X86InstrInfo::
3309 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3310                int &CmpMask, int &CmpValue) const {
3311   switch (MI->getOpcode()) {
3312   default: break;
3313   case X86::CMP64ri32:
3314   case X86::CMP64ri8:
3315   case X86::CMP32ri:
3316   case X86::CMP32ri8:
3317   case X86::CMP16ri:
3318   case X86::CMP16ri8:
3319   case X86::CMP8ri:
3320     SrcReg = MI->getOperand(0).getReg();
3321     SrcReg2 = 0;
3322     CmpMask = ~0;
3323     CmpValue = MI->getOperand(1).getImm();
3324     return true;
3325   // A SUB can be used to perform comparison.
3326   case X86::SUB64rm:
3327   case X86::SUB32rm:
3328   case X86::SUB16rm:
3329   case X86::SUB8rm:
3330     SrcReg = MI->getOperand(1).getReg();
3331     SrcReg2 = 0;
3332     CmpMask = ~0;
3333     CmpValue = 0;
3334     return true;
3335   case X86::SUB64rr:
3336   case X86::SUB32rr:
3337   case X86::SUB16rr:
3338   case X86::SUB8rr:
3339     SrcReg = MI->getOperand(1).getReg();
3340     SrcReg2 = MI->getOperand(2).getReg();
3341     CmpMask = ~0;
3342     CmpValue = 0;
3343     return true;
3344   case X86::SUB64ri32:
3345   case X86::SUB64ri8:
3346   case X86::SUB32ri:
3347   case X86::SUB32ri8:
3348   case X86::SUB16ri:
3349   case X86::SUB16ri8:
3350   case X86::SUB8ri:
3351     SrcReg = MI->getOperand(1).getReg();
3352     SrcReg2 = 0;
3353     CmpMask = ~0;
3354     CmpValue = MI->getOperand(2).getImm();
3355     return true;
3356   case X86::CMP64rr:
3357   case X86::CMP32rr:
3358   case X86::CMP16rr:
3359   case X86::CMP8rr:
3360     SrcReg = MI->getOperand(0).getReg();
3361     SrcReg2 = MI->getOperand(1).getReg();
3362     CmpMask = ~0;
3363     CmpValue = 0;
3364     return true;
3365   case X86::TEST8rr:
3366   case X86::TEST16rr:
3367   case X86::TEST32rr:
3368   case X86::TEST64rr:
3369     SrcReg = MI->getOperand(0).getReg();
3370     if (MI->getOperand(1).getReg() != SrcReg) return false;
3371     // Compare against zero.
3372     SrcReg2 = 0;
3373     CmpMask = ~0;
3374     CmpValue = 0;
3375     return true;
3376   }
3377   return false;
3378 }
3379 
3380 /// isRedundantFlagInstr - check whether the first instruction, whose only
3381 /// purpose is to update flags, can be made redundant.
3382 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3383 /// This function can be extended later on.
3384 /// SrcReg, SrcRegs: register operands for FlagI.
3385 /// ImmValue: immediate for FlagI if it takes an immediate.
3386 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3387                                         unsigned SrcReg2, int ImmValue,
3388                                         MachineInstr *OI) {
3389   if (((FlagI->getOpcode() == X86::CMP64rr &&
3390         OI->getOpcode() == X86::SUB64rr) ||
3391        (FlagI->getOpcode() == X86::CMP32rr &&
3392         OI->getOpcode() == X86::SUB32rr)||
3393        (FlagI->getOpcode() == X86::CMP16rr &&
3394         OI->getOpcode() == X86::SUB16rr)||
3395        (FlagI->getOpcode() == X86::CMP8rr &&
3396         OI->getOpcode() == X86::SUB8rr)) &&
3397       ((OI->getOperand(1).getReg() == SrcReg &&
3398         OI->getOperand(2).getReg() == SrcReg2) ||
3399        (OI->getOperand(1).getReg() == SrcReg2 &&
3400         OI->getOperand(2).getReg() == SrcReg)))
3401     return true;
3402 
3403   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3404         OI->getOpcode() == X86::SUB64ri32) ||
3405        (FlagI->getOpcode() == X86::CMP64ri8 &&
3406         OI->getOpcode() == X86::SUB64ri8) ||
3407        (FlagI->getOpcode() == X86::CMP32ri &&
3408         OI->getOpcode() == X86::SUB32ri) ||
3409        (FlagI->getOpcode() == X86::CMP32ri8 &&
3410         OI->getOpcode() == X86::SUB32ri8) ||
3411        (FlagI->getOpcode() == X86::CMP16ri &&
3412         OI->getOpcode() == X86::SUB16ri) ||
3413        (FlagI->getOpcode() == X86::CMP16ri8 &&
3414         OI->getOpcode() == X86::SUB16ri8) ||
3415        (FlagI->getOpcode() == X86::CMP8ri &&
3416         OI->getOpcode() == X86::SUB8ri)) &&
3417       OI->getOperand(1).getReg() == SrcReg &&
3418       OI->getOperand(2).getImm() == ImmValue)
3419     return true;
3420   return false;
3421 }
3422 
3423 /// isDefConvertible - check whether the definition can be converted
3424 /// to remove a comparison against zero.
3425 inline static bool isDefConvertible(MachineInstr *MI) {
3426   switch (MI->getOpcode()) {
3427   default: return false;
3428 
3429   // The shift instructions only modify ZF if their shift count is non-zero.
3430   // N.B.: The processor truncates the shift count depending on the encoding.
3431   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3432   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3433      return getTruncatedShiftCount(MI, 2) != 0;
3434 
3435   // Some left shift instructions can be turned into LEA instructions but only
3436   // if their flags aren't used. Avoid transforming such instructions.
3437   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3438     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3439     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3440     return ShAmt != 0;
3441   }
3442 
3443   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3444   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3445      return getTruncatedShiftCount(MI, 3) != 0;
3446 
3447   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3448   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3449   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3450   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3451   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3452   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3453   case X86::DEC64_32r: case X86::DEC64_16r:
3454   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3455   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3456   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3457   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3458   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3459   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3460   case X86::INC64_32r: case X86::INC64_16r:
3461   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3462   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3463   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3464   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3465   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3466   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3467   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3468   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3469   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3470   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3471   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3472   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3473   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3474   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3475   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3476   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
3477   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
3478   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
3479   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
3480   case X86::ADC32ri:   case X86::ADC32ri8:
3481   case X86::ADC32rr:   case X86::ADC64ri32:
3482   case X86::ADC64ri8:  case X86::ADC64rr:
3483   case X86::SBB32ri:   case X86::SBB32ri8:
3484   case X86::SBB32rr:   case X86::SBB64ri32:
3485   case X86::SBB64ri8:  case X86::SBB64rr:
3486   case X86::ANDN32rr:  case X86::ANDN32rm:
3487   case X86::ANDN64rr:  case X86::ANDN64rm:
3488   case X86::BEXTR32rr: case X86::BEXTR64rr:
3489   case X86::BEXTR32rm: case X86::BEXTR64rm:
3490   case X86::BLSI32rr:  case X86::BLSI32rm:
3491   case X86::BLSI64rr:  case X86::BLSI64rm:
3492   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3493   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3494   case X86::BLSR32rr:  case X86::BLSR32rm:
3495   case X86::BLSR64rr:  case X86::BLSR64rm:
3496   case X86::BZHI32rr:  case X86::BZHI32rm:
3497   case X86::BZHI64rr:  case X86::BZHI64rm:
3498   case X86::LZCNT16rr: case X86::LZCNT16rm:
3499   case X86::LZCNT32rr: case X86::LZCNT32rm:
3500   case X86::LZCNT64rr: case X86::LZCNT64rm:
3501   case X86::POPCNT16rr:case X86::POPCNT16rm:
3502   case X86::POPCNT32rr:case X86::POPCNT32rm:
3503   case X86::POPCNT64rr:case X86::POPCNT64rm:
3504   case X86::TZCNT16rr: case X86::TZCNT16rm:
3505   case X86::TZCNT32rr: case X86::TZCNT32rm:
3506   case X86::TZCNT64rr: case X86::TZCNT64rm:
3507     return true;
3508   }
3509 }
3510 
3511 /// optimizeCompareInstr - Check if there exists an earlier instruction that
3512 /// operates on the same source operands and sets flags in the same way as
3513 /// Compare; remove Compare if possible.
3514 bool X86InstrInfo::
3515 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3516                      int CmpMask, int CmpValue,
3517                      const MachineRegisterInfo *MRI) const {
3518   // Check whether we can replace SUB with CMP.
3519   unsigned NewOpcode = 0;
3520   switch (CmpInstr->getOpcode()) {
3521   default: break;
3522   case X86::SUB64ri32:
3523   case X86::SUB64ri8:
3524   case X86::SUB32ri:
3525   case X86::SUB32ri8:
3526   case X86::SUB16ri:
3527   case X86::SUB16ri8:
3528   case X86::SUB8ri:
3529   case X86::SUB64rm:
3530   case X86::SUB32rm:
3531   case X86::SUB16rm:
3532   case X86::SUB8rm:
3533   case X86::SUB64rr:
3534   case X86::SUB32rr:
3535   case X86::SUB16rr:
3536   case X86::SUB8rr: {
3537     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3538       return false;
3539     // There is no use of the destination register, we can replace SUB with CMP.
3540     switch (CmpInstr->getOpcode()) {
3541     default: llvm_unreachable("Unreachable!");
3542     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
3543     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
3544     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
3545     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
3546     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
3547     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
3548     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
3549     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
3550     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3551     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
3552     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
3553     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
3554     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
3555     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
3556     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
3557     }
3558     CmpInstr->setDesc(get(NewOpcode));
3559     CmpInstr->RemoveOperand(0);
3560     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3561     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3562         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3563       return false;
3564   }
3565   }
3566 
3567   // Get the unique definition of SrcReg.
3568   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3569   if (!MI) return false;
3570 
3571   // CmpInstr is the first instruction of the BB.
3572   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3573 
3574   // If we are comparing against zero, check whether we can use MI to update
3575   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3576   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
3577   if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() ||
3578       !isDefConvertible(MI)))
3579     return false;
3580 
3581   // We are searching for an earlier instruction that can make CmpInstr
3582   // redundant and that instruction will be saved in Sub.
3583   MachineInstr *Sub = NULL;
3584   const TargetRegisterInfo *TRI = &getRegisterInfo();
3585 
3586   // We iterate backward, starting from the instruction before CmpInstr and
3587   // stop when reaching the definition of a source register or done with the BB.
3588   // RI points to the instruction before CmpInstr.
3589   // If the definition is in this basic block, RE points to the definition;
3590   // otherwise, RE is the rend of the basic block.
3591   MachineBasicBlock::reverse_iterator
3592       RI = MachineBasicBlock::reverse_iterator(I),
3593       RE = CmpInstr->getParent() == MI->getParent() ?
3594            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3595            CmpInstr->getParent()->rend();
3596   MachineInstr *Movr0Inst = 0;
3597   for (; RI != RE; ++RI) {
3598     MachineInstr *Instr = &*RI;
3599     // Check whether CmpInstr can be made redundant by the current instruction.
3600     if (!IsCmpZero &&
3601         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
3602       Sub = Instr;
3603       break;
3604     }
3605 
3606     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3607         Instr->readsRegister(X86::EFLAGS, TRI)) {
3608       // This instruction modifies or uses EFLAGS.
3609 
3610       // MOV32r0 etc. are implemented with xor which clobbers condition code.
3611       // They are safe to move up, if the definition to EFLAGS is dead and
3612       // earlier instructions do not read or write EFLAGS.
3613       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
3614           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3615         Movr0Inst = Instr;
3616         continue;
3617       }
3618 
3619       // We can't remove CmpInstr.
3620       return false;
3621     }
3622   }
3623 
3624   // Return false if no candidates exist.
3625   if (!IsCmpZero && !Sub)
3626     return false;
3627 
3628   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3629                     Sub->getOperand(2).getReg() == SrcReg);
3630 
3631   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3632   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3633   // If we are done with the basic block, we need to check whether EFLAGS is
3634   // live-out.
3635   bool IsSafe = false;
3636   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3637   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3638   for (++I; I != E; ++I) {
3639     const MachineInstr &Instr = *I;
3640     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3641     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3642     // We should check the usage if this instruction uses and updates EFLAGS.
3643     if (!UseEFLAGS && ModifyEFLAGS) {
3644       // It is safe to remove CmpInstr if EFLAGS is updated again.
3645       IsSafe = true;
3646       break;
3647     }
3648     if (!UseEFLAGS && !ModifyEFLAGS)
3649       continue;
3650 
3651     // EFLAGS is used by this instruction.
3652     X86::CondCode OldCC;
3653     bool OpcIsSET = false;
3654     if (IsCmpZero || IsSwapped) {
3655       // We decode the condition code from opcode.
3656       if (Instr.isBranch())
3657         OldCC = getCondFromBranchOpc(Instr.getOpcode());
3658       else {
3659         OldCC = getCondFromSETOpc(Instr.getOpcode());
3660         if (OldCC != X86::COND_INVALID)
3661           OpcIsSET = true;
3662         else
3663           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3664       }
3665       if (OldCC == X86::COND_INVALID) return false;
3666     }
3667     if (IsCmpZero) {
3668       switch (OldCC) {
3669       default: break;
3670       case X86::COND_A: case X86::COND_AE:
3671       case X86::COND_B: case X86::COND_BE:
3672       case X86::COND_G: case X86::COND_GE:
3673       case X86::COND_L: case X86::COND_LE:
3674       case X86::COND_O: case X86::COND_NO:
3675         // CF and OF are used, we can't perform this optimization.
3676         return false;
3677       }
3678     } else if (IsSwapped) {
3679       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3680       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3681       // We swap the condition code and synthesize the new opcode.
3682       X86::CondCode NewCC = getSwappedCondition(OldCC);
3683       if (NewCC == X86::COND_INVALID) return false;
3684 
3685       // Synthesize the new opcode.
3686       bool HasMemoryOperand = Instr.hasOneMemOperand();
3687       unsigned NewOpc;
3688       if (Instr.isBranch())
3689         NewOpc = GetCondBranchFromCond(NewCC);
3690       else if(OpcIsSET)
3691         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3692       else {
3693         unsigned DstReg = Instr.getOperand(0).getReg();
3694         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3695                                  HasMemoryOperand);
3696       }
3697 
3698       // Push the MachineInstr to OpsToUpdate.
3699       // If it is safe to remove CmpInstr, the condition code of these
3700       // instructions will be modified.
3701       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3702     }
3703     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3704       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3705       IsSafe = true;
3706       break;
3707     }
3708   }
3709 
3710   // If EFLAGS is not killed nor re-defined, we should check whether it is
3711   // live-out. If it is live-out, do not optimize.
3712   if ((IsCmpZero || IsSwapped) && !IsSafe) {
3713     MachineBasicBlock *MBB = CmpInstr->getParent();
3714     for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
3715              SE = MBB->succ_end(); SI != SE; ++SI)
3716       if ((*SI)->isLiveIn(X86::EFLAGS))
3717         return false;
3718   }
3719 
3720   // The instruction to be updated is either Sub or MI.
3721   Sub = IsCmpZero ? MI : Sub;
3722   // Move Movr0Inst to the appropriate place before Sub.
3723   if (Movr0Inst) {
3724     // Look backwards until we find a def that doesn't use the current EFLAGS.
3725     Def = Sub;
3726     MachineBasicBlock::reverse_iterator
3727       InsertI = MachineBasicBlock::reverse_iterator(++Def),
3728                 InsertE = Sub->getParent()->rend();
3729     for (; InsertI != InsertE; ++InsertI) {
3730       MachineInstr *Instr = &*InsertI;
3731       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3732           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3733         Sub->getParent()->remove(Movr0Inst);
3734         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3735                                    Movr0Inst);
3736         break;
3737       }
3738     }
3739     if (InsertI == InsertE)
3740       return false;
3741   }
3742 
3743   // Make sure Sub instruction defines EFLAGS and mark the def live.
3744   unsigned i = 0, e = Sub->getNumOperands();
3745   for (; i != e; ++i) {
3746     MachineOperand &MO = Sub->getOperand(i);
3747     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3748       MO.setIsDead(false);
3749       break;
3750     }
3751   }
3752   assert(i != e && "Unable to locate a def EFLAGS operand");
3753 
3754   CmpInstr->eraseFromParent();
3755 
3756   // Modify the condition code of instructions in OpsToUpdate.
3757   for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
3758     OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
3759   return true;
3760 }
3761 
3762 /// optimizeLoadInstr - Try to remove the load by folding it to a register
3763 /// operand at the use. We fold the load instructions if load defines a virtual
3764 /// register, the virtual register is used once in the same BB, and the
3765 /// instructions in-between do not load or store, and have no side effects.
3766 MachineInstr* X86InstrInfo::
3767 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,
3768                   unsigned &FoldAsLoadDefReg,
3769                   MachineInstr *&DefMI) const {
3770   if (FoldAsLoadDefReg == 0)
3771     return 0;
3772   // To be conservative, if there exists another load, clear the load candidate.
3773   if (MI->mayLoad()) {
3774     FoldAsLoadDefReg = 0;
3775     return 0;
3776   }
3777 
3778   // Check whether we can move DefMI here.
3779   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3780   assert(DefMI);
3781   bool SawStore = false;
3782   if (!DefMI->isSafeToMove(this, 0, SawStore))
3783     return 0;
3784 
3785   // We try to commute MI if possible.
3786   unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1;
3787   for (unsigned Idx = 0; Idx < IdxEnd; Idx++) {
3788     // Collect information about virtual register operands of MI.
3789     unsigned SrcOperandId = 0;
3790     bool FoundSrcOperand = false;
3791     for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
3792       MachineOperand &MO = MI->getOperand(i);
3793       if (!MO.isReg())
3794         continue;
3795       unsigned Reg = MO.getReg();
3796       if (Reg != FoldAsLoadDefReg)
3797         continue;
3798       // Do not fold if we have a subreg use or a def or multiple uses.
3799       if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
3800         return 0;
3801 
3802       SrcOperandId = i;
3803       FoundSrcOperand = true;
3804     }
3805     if (!FoundSrcOperand) return 0;
3806 
3807     // Check whether we can fold the def into SrcOperandId.
3808     SmallVector<unsigned, 8> Ops;
3809     Ops.push_back(SrcOperandId);
3810     MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
3811     if (FoldMI) {
3812       FoldAsLoadDefReg = 0;
3813       return FoldMI;
3814     }
3815 
3816     if (Idx == 1) {
3817       // MI was changed but it didn't help, commute it back!
3818       commuteInstruction(MI, false);
3819       return 0;
3820     }
3821 
3822     // Check whether we can commute MI and enable folding.
3823     if (MI->isCommutable()) {
3824       MachineInstr *NewMI = commuteInstruction(MI, false);
3825       // Unable to commute.
3826       if (!NewMI) return 0;
3827       if (NewMI != MI) {
3828         // New instruction. It doesn't need to be kept.
3829         NewMI->eraseFromParent();
3830         return 0;
3831       }
3832     }
3833   }
3834   return 0;
3835 }
3836 
3837 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
3838 /// instruction with two undef reads of the register being defined.  This is
3839 /// used for mapping:
3840 ///   %xmm4 = V_SET0
3841 /// to:
3842 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
3843 ///
3844 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3845                              const MCInstrDesc &Desc) {
3846   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3847   unsigned Reg = MIB->getOperand(0).getReg();
3848   MIB->setDesc(Desc);
3849 
3850   // MachineInstr::addOperand() will insert explicit operands before any
3851   // implicit operands.
3852   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3853   // But we don't trust that.
3854   assert(MIB->getOperand(1).getReg() == Reg &&
3855          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3856   return true;
3857 }
3858 
3859 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
3860   bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3861   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
3862   switch (MI->getOpcode()) {
3863   case X86::MOV32r0:
3864     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
3865   case X86::SETB_C8r:
3866     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
3867   case X86::SETB_C16r:
3868     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
3869   case X86::SETB_C32r:
3870     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
3871   case X86::SETB_C64r:
3872     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
3873   case X86::V_SET0:
3874   case X86::FsFLD0SS:
3875   case X86::FsFLD0SD:
3876     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
3877   case X86::AVX_SET0:
3878     assert(HasAVX && "AVX not supported");
3879     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
3880   case X86::AVX512_512_SET0:
3881     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
3882   case X86::V_SETALLONES:
3883     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
3884   case X86::AVX2_SETALLONES:
3885     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
3886   case X86::TEST8ri_NOREX:
3887     MI->setDesc(get(X86::TEST8ri));
3888     return true;
3889   case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
3890   case X86::KSET1B:
3891   case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
3892   }
3893   return false;
3894 }
3895 
3896 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
3897                                      const SmallVectorImpl<MachineOperand> &MOs,
3898                                      MachineInstr *MI,
3899                                      const TargetInstrInfo &TII) {
3900   // Create the base instruction with the memory operand as the first part.
3901   // Omit the implicit operands, something BuildMI can't do.
3902   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3903                                               MI->getDebugLoc(), true);
3904   MachineInstrBuilder MIB(MF, NewMI);
3905   unsigned NumAddrOps = MOs.size();
3906   for (unsigned i = 0; i != NumAddrOps; ++i)
3907     MIB.addOperand(MOs[i]);
3908   if (NumAddrOps < 4)  // FrameIndex only
3909     addOffset(MIB, 0);
3910 
3911   // Loop over the rest of the ri operands, converting them over.
3912   unsigned NumOps = MI->getDesc().getNumOperands()-2;
3913   for (unsigned i = 0; i != NumOps; ++i) {
3914     MachineOperand &MO = MI->getOperand(i+2);
3915     MIB.addOperand(MO);
3916   }
3917   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
3918     MachineOperand &MO = MI->getOperand(i);
3919     MIB.addOperand(MO);
3920   }
3921   return MIB;
3922 }
3923 
3924 static MachineInstr *FuseInst(MachineFunction &MF,
3925                               unsigned Opcode, unsigned OpNo,
3926                               const SmallVectorImpl<MachineOperand> &MOs,
3927                               MachineInstr *MI, const TargetInstrInfo &TII) {
3928   // Omit the implicit operands, something BuildMI can't do.
3929   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3930                                               MI->getDebugLoc(), true);
3931   MachineInstrBuilder MIB(MF, NewMI);
3932 
3933   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3934     MachineOperand &MO = MI->getOperand(i);
3935     if (i == OpNo) {
3936       assert(MO.isReg() && "Expected to fold into reg operand!");
3937       unsigned NumAddrOps = MOs.size();
3938       for (unsigned i = 0; i != NumAddrOps; ++i)
3939         MIB.addOperand(MOs[i]);
3940       if (NumAddrOps < 4)  // FrameIndex only
3941         addOffset(MIB, 0);
3942     } else {
3943       MIB.addOperand(MO);
3944     }
3945   }
3946   return MIB;
3947 }
3948 
3949 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
3950                                 const SmallVectorImpl<MachineOperand> &MOs,
3951                                 MachineInstr *MI) {
3952   MachineFunction &MF = *MI->getParent()->getParent();
3953   MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
3954 
3955   unsigned NumAddrOps = MOs.size();
3956   for (unsigned i = 0; i != NumAddrOps; ++i)
3957     MIB.addOperand(MOs[i]);
3958   if (NumAddrOps < 4)  // FrameIndex only
3959     addOffset(MIB, 0);
3960   return MIB.addImm(0);
3961 }
3962 
3963 MachineInstr*
3964 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3965                                     MachineInstr *MI, unsigned i,
3966                                     const SmallVectorImpl<MachineOperand> &MOs,
3967                                     unsigned Size, unsigned Align) const {
3968   const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
3969   bool isCallRegIndirect = TM.getSubtarget<X86Subtarget>().callRegIndirect();
3970   bool isTwoAddrFold = false;
3971 
3972   // Atom favors register form of call. So, we do not fold loads into calls
3973   // when X86Subtarget is Atom.
3974   if (isCallRegIndirect &&
3975     (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
3976     return NULL;
3977   }
3978 
3979   unsigned NumOps = MI->getDesc().getNumOperands();
3980   bool isTwoAddr = NumOps > 1 &&
3981     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3982 
3983   // FIXME: AsmPrinter doesn't know how to handle
3984   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3985   if (MI->getOpcode() == X86::ADD32ri &&
3986       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3987     return NULL;
3988 
3989   MachineInstr *NewMI = NULL;
3990   // Folding a memory location into the two-address part of a two-address
3991   // instruction is different than folding it other places.  It requires
3992   // replacing the *two* registers with the memory location.
3993   if (isTwoAddr && NumOps >= 2 && i < 2 &&
3994       MI->getOperand(0).isReg() &&
3995       MI->getOperand(1).isReg() &&
3996       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
3997     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3998     isTwoAddrFold = true;
3999   } else if (i == 0) { // If operand 0
4000     if (MI->getOpcode() == X86::MOV32r0) {
4001       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4002       if (NewMI)
4003         return NewMI;
4004     }
4005 
4006     OpcodeTablePtr = &RegOp2MemOpTable0;
4007   } else if (i == 1) {
4008     OpcodeTablePtr = &RegOp2MemOpTable1;
4009   } else if (i == 2) {
4010     OpcodeTablePtr = &RegOp2MemOpTable2;
4011   } else if (i == 3) {
4012     OpcodeTablePtr = &RegOp2MemOpTable3;
4013   }
4014 
4015   // If table selected...
4016   if (OpcodeTablePtr) {
4017     // Find the Opcode to fuse
4018     DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4019       OpcodeTablePtr->find(MI->getOpcode());
4020     if (I != OpcodeTablePtr->end()) {
4021       unsigned Opcode = I->second.first;
4022       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4023       if (Align < MinAlign)
4024         return NULL;
4025       bool NarrowToMOV32rm = false;
4026       if (Size) {
4027         unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
4028         if (Size < RCSize) {
4029           // Check if it's safe to fold the load. If the size of the object is
4030           // narrower than the load width, then it's not.
4031           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4032             return NULL;
4033           // If this is a 64-bit load, but the spill slot is 32, then we can do
4034           // a 32-bit load which is implicitly zero-extended. This likely is due
4035           // to liveintervalanalysis remat'ing a load from stack slot.
4036           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4037             return NULL;
4038           Opcode = X86::MOV32rm;
4039           NarrowToMOV32rm = true;
4040         }
4041       }
4042 
4043       if (isTwoAddrFold)
4044         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
4045       else
4046         NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
4047 
4048       if (NarrowToMOV32rm) {
4049         // If this is the special case where we use a MOV32rm to load a 32-bit
4050         // value and zero-extend the top bits. Change the destination register
4051         // to a 32-bit one.
4052         unsigned DstReg = NewMI->getOperand(0).getReg();
4053         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4054           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
4055                                                    X86::sub_32bit));
4056         else
4057           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4058       }
4059       return NewMI;
4060     }
4061   }
4062 
4063   // No fusion
4064   if (PrintFailedFusing && !MI->isCopy())
4065     dbgs() << "We failed to fuse operand " << i << " in " << *MI;
4066   return NULL;
4067 }
4068 
4069 /// hasPartialRegUpdate - Return true for all instructions that only update
4070 /// the first 32 or 64-bits of the destination register and leave the rest
4071 /// unmodified. This can be used to avoid folding loads if the instructions
4072 /// only update part of the destination register, and the non-updated part is
4073 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4074 /// instructions breaks the partial register dependency and it can improve
4075 /// performance. e.g.:
4076 ///
4077 ///   movss (%rdi), %xmm0
4078 ///   cvtss2sd %xmm0, %xmm0
4079 ///
4080 /// Instead of
4081 ///   cvtss2sd (%rdi), %xmm0
4082 ///
4083 /// FIXME: This should be turned into a TSFlags.
4084 ///
4085 static bool hasPartialRegUpdate(unsigned Opcode) {
4086   switch (Opcode) {
4087   case X86::CVTSI2SSrr:
4088   case X86::CVTSI2SS64rr:
4089   case X86::CVTSI2SDrr:
4090   case X86::CVTSI2SD64rr:
4091   case X86::CVTSD2SSrr:
4092   case X86::Int_CVTSD2SSrr:
4093   case X86::CVTSS2SDrr:
4094   case X86::Int_CVTSS2SDrr:
4095   case X86::RCPSSr:
4096   case X86::RCPSSr_Int:
4097   case X86::ROUNDSDr:
4098   case X86::ROUNDSDr_Int:
4099   case X86::ROUNDSSr:
4100   case X86::ROUNDSSr_Int:
4101   case X86::RSQRTSSr:
4102   case X86::RSQRTSSr_Int:
4103   case X86::SQRTSSr:
4104   case X86::SQRTSSr_Int:
4105     return true;
4106   }
4107 
4108   return false;
4109 }
4110 
4111 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
4112 /// instructions we would like before a partial register update.
4113 unsigned X86InstrInfo::
4114 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4115                              const TargetRegisterInfo *TRI) const {
4116   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4117     return 0;
4118 
4119   // If MI is marked as reading Reg, the partial register update is wanted.
4120   const MachineOperand &MO = MI->getOperand(0);
4121   unsigned Reg = MO.getReg();
4122   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4123     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4124       return 0;
4125   } else {
4126     if (MI->readsRegister(Reg, TRI))
4127       return 0;
4128   }
4129 
4130   // If any of the preceding 16 instructions are reading Reg, insert a
4131   // dependency breaking instruction.  The magic number is based on a few
4132   // Nehalem experiments.
4133   return 16;
4134 }
4135 
4136 // Return true for any instruction the copies the high bits of the first source
4137 // operand into the unused high bits of the destination operand.
4138 static bool hasUndefRegUpdate(unsigned Opcode) {
4139   switch (Opcode) {
4140   case X86::VCVTSI2SSrr:
4141   case X86::Int_VCVTSI2SSrr:
4142   case X86::VCVTSI2SS64rr:
4143   case X86::Int_VCVTSI2SS64rr:
4144   case X86::VCVTSI2SDrr:
4145   case X86::Int_VCVTSI2SDrr:
4146   case X86::VCVTSI2SD64rr:
4147   case X86::Int_VCVTSI2SD64rr:
4148   case X86::VCVTSD2SSrr:
4149   case X86::Int_VCVTSD2SSrr:
4150   case X86::VCVTSS2SDrr:
4151   case X86::Int_VCVTSS2SDrr:
4152   case X86::VRCPSSr:
4153   case X86::VROUNDSDr:
4154   case X86::VROUNDSDr_Int:
4155   case X86::VROUNDSSr:
4156   case X86::VROUNDSSr_Int:
4157   case X86::VRSQRTSSr:
4158   case X86::VSQRTSSr:
4159 
4160   // AVX-512
4161   case X86::VCVTSD2SSZrr:
4162   case X86::VCVTSS2SDZrr:
4163     return true;
4164   }
4165 
4166   return false;
4167 }
4168 
4169 /// Inform the ExeDepsFix pass how many idle instructions we would like before
4170 /// certain undef register reads.
4171 ///
4172 /// This catches the VCVTSI2SD family of instructions:
4173 ///
4174 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4175 ///
4176 /// We should to be careful *not* to catch VXOR idioms which are presumably
4177 /// handled specially in the pipeline:
4178 ///
4179 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4180 ///
4181 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4182 /// high bits that are passed-through are not live.
4183 unsigned X86InstrInfo::
4184 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4185                      const TargetRegisterInfo *TRI) const {
4186   if (!hasUndefRegUpdate(MI->getOpcode()))
4187     return 0;
4188 
4189   // Set the OpNum parameter to the first source operand.
4190   OpNum = 1;
4191 
4192   const MachineOperand &MO = MI->getOperand(OpNum);
4193   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4194     // Use the same magic number as getPartialRegUpdateClearance.
4195     return 16;
4196   }
4197   return 0;
4198 }
4199 
4200 void X86InstrInfo::
4201 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4202                           const TargetRegisterInfo *TRI) const {
4203   unsigned Reg = MI->getOperand(OpNum).getReg();
4204   // If MI kills this register, the false dependence is already broken.
4205   if (MI->killsRegister(Reg, TRI))
4206     return;
4207   if (X86::VR128RegClass.contains(Reg)) {
4208     // These instructions are all floating point domain, so xorps is the best
4209     // choice.
4210     bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
4211     unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
4212     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
4213       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4214   } else if (X86::VR256RegClass.contains(Reg)) {
4215     // Use vxorps to clear the full ymm register.
4216     // It wants to read and write the xmm sub-register.
4217     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4218     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
4219       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
4220       .addReg(Reg, RegState::ImplicitDefine);
4221   } else
4222     return;
4223   MI->addRegisterKilled(Reg, TRI, true);
4224 }
4225 
4226 MachineInstr*
4227 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
4228                                     const SmallVectorImpl<unsigned> &Ops,
4229                                     int FrameIndex) const {
4230   // Check switch flag
4231   if (NoFusing) return NULL;
4232 
4233   // Unless optimizing for size, don't fold to avoid partial
4234   // register update stalls
4235   if (!MF.getFunction()->getAttributes().
4236         hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4237       hasPartialRegUpdate(MI->getOpcode()))
4238     return 0;
4239 
4240   const MachineFrameInfo *MFI = MF.getFrameInfo();
4241   unsigned Size = MFI->getObjectSize(FrameIndex);
4242   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
4243   // If the function stack isn't realigned we don't want to fold instructions
4244   // that need increased alignment.
4245   if (!RI.needsStackRealignment(MF))
4246     Alignment = std::min(Alignment, TM.getFrameLowering()->getStackAlignment());
4247   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4248     unsigned NewOpc = 0;
4249     unsigned RCSize = 0;
4250     switch (MI->getOpcode()) {
4251     default: return NULL;
4252     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
4253     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
4254     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
4255     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
4256     }
4257     // Check if it's safe to fold the load. If the size of the object is
4258     // narrower than the load width, then it's not.
4259     if (Size < RCSize)
4260       return NULL;
4261     // Change to CMPXXri r, 0 first.
4262     MI->setDesc(get(NewOpc));
4263     MI->getOperand(1).ChangeToImmediate(0);
4264   } else if (Ops.size() != 1)
4265     return NULL;
4266 
4267   SmallVector<MachineOperand,4> MOs;
4268   MOs.push_back(MachineOperand::CreateFI(FrameIndex));
4269   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
4270 }
4271 
4272 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4273                                                   MachineInstr *MI,
4274                                            const SmallVectorImpl<unsigned> &Ops,
4275                                                   MachineInstr *LoadMI) const {
4276   // If loading from a FrameIndex, fold directly from the FrameIndex.
4277   unsigned NumOps = LoadMI->getDesc().getNumOperands();
4278   int FrameIndex;
4279   if (isLoadFromStackSlot(LoadMI, FrameIndex))
4280     return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
4281 
4282   // Check switch flag
4283   if (NoFusing) return NULL;
4284 
4285   // Unless optimizing for size, don't fold to avoid partial
4286   // register update stalls
4287   if (!MF.getFunction()->getAttributes().
4288         hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
4289       hasPartialRegUpdate(MI->getOpcode()))
4290     return 0;
4291 
4292   // Determine the alignment of the load.
4293   unsigned Alignment = 0;
4294   if (LoadMI->hasOneMemOperand())
4295     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
4296   else
4297     switch (LoadMI->getOpcode()) {
4298     case X86::AVX2_SETALLONES:
4299     case X86::AVX_SET0:
4300       Alignment = 32;
4301       break;
4302     case X86::V_SET0:
4303     case X86::V_SETALLONES:
4304       Alignment = 16;
4305       break;
4306     case X86::FsFLD0SD:
4307       Alignment = 8;
4308       break;
4309     case X86::FsFLD0SS:
4310       Alignment = 4;
4311       break;
4312     default:
4313       return 0;
4314     }
4315   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4316     unsigned NewOpc = 0;
4317     switch (MI->getOpcode()) {
4318     default: return NULL;
4319     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
4320     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
4321     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
4322     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
4323     }
4324     // Change to CMPXXri r, 0 first.
4325     MI->setDesc(get(NewOpc));
4326     MI->getOperand(1).ChangeToImmediate(0);
4327   } else if (Ops.size() != 1)
4328     return NULL;
4329 
4330   // Make sure the subregisters match.
4331   // Otherwise we risk changing the size of the load.
4332   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
4333     return NULL;
4334 
4335   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
4336   switch (LoadMI->getOpcode()) {
4337   case X86::V_SET0:
4338   case X86::V_SETALLONES:
4339   case X86::AVX2_SETALLONES:
4340   case X86::AVX_SET0:
4341   case X86::FsFLD0SD:
4342   case X86::FsFLD0SS: {
4343     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
4344     // Create a constant-pool entry and operands to load from it.
4345 
4346     // Medium and large mode can't fold loads this way.
4347     if (TM.getCodeModel() != CodeModel::Small &&
4348         TM.getCodeModel() != CodeModel::Kernel)
4349       return NULL;
4350 
4351     // x86-32 PIC requires a PIC base register for constant pools.
4352     unsigned PICBase = 0;
4353     if (TM.getRelocationModel() == Reloc::PIC_) {
4354       if (TM.getSubtarget<X86Subtarget>().is64Bit())
4355         PICBase = X86::RIP;
4356       else
4357         // FIXME: PICBase = getGlobalBaseReg(&MF);
4358         // This doesn't work for several reasons.
4359         // 1. GlobalBaseReg may have been spilled.
4360         // 2. It may not be live at MI.
4361         return NULL;
4362     }
4363 
4364     // Create a constant-pool entry.
4365     MachineConstantPool &MCP = *MF.getConstantPool();
4366     Type *Ty;
4367     unsigned Opc = LoadMI->getOpcode();
4368     if (Opc == X86::FsFLD0SS)
4369       Ty = Type::getFloatTy(MF.getFunction()->getContext());
4370     else if (Opc == X86::FsFLD0SD)
4371       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
4372     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
4373       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
4374     else
4375       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
4376 
4377     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
4378     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4379                                     Constant::getNullValue(Ty);
4380     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
4381 
4382     // Create operands to load from the constant pool entry.
4383     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4384     MOs.push_back(MachineOperand::CreateImm(1));
4385     MOs.push_back(MachineOperand::CreateReg(0, false));
4386     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
4387     MOs.push_back(MachineOperand::CreateReg(0, false));
4388     break;
4389   }
4390   default: {
4391     if ((LoadMI->getOpcode() == X86::MOVSSrm ||
4392          LoadMI->getOpcode() == X86::VMOVSSrm) &&
4393         MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4394           > 4)
4395       // These instructions only load 32 bits, we can't fold them if the
4396       // destination register is wider than 32 bits (4 bytes).
4397       return NULL;
4398     if ((LoadMI->getOpcode() == X86::MOVSDrm ||
4399          LoadMI->getOpcode() == X86::VMOVSDrm) &&
4400         MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4401           > 8)
4402       // These instructions only load 64 bits, we can't fold them if the
4403       // destination register is wider than 64 bits (8 bytes).
4404       return NULL;
4405 
4406     // Folding a normal load. Just copy the load's address operands.
4407     for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
4408       MOs.push_back(LoadMI->getOperand(i));
4409     break;
4410   }
4411   }
4412   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
4413 }
4414 
4415 
4416 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4417                                   const SmallVectorImpl<unsigned> &Ops) const {
4418   // Check switch flag
4419   if (NoFusing) return 0;
4420 
4421   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4422     switch (MI->getOpcode()) {
4423     default: return false;
4424     case X86::TEST8rr:
4425     case X86::TEST16rr:
4426     case X86::TEST32rr:
4427     case X86::TEST64rr:
4428       return true;
4429     case X86::ADD32ri:
4430       // FIXME: AsmPrinter doesn't know how to handle
4431       // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4432       if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4433         return false;
4434       break;
4435     }
4436   }
4437 
4438   if (Ops.size() != 1)
4439     return false;
4440 
4441   unsigned OpNum = Ops[0];
4442   unsigned Opc = MI->getOpcode();
4443   unsigned NumOps = MI->getDesc().getNumOperands();
4444   bool isTwoAddr = NumOps > 1 &&
4445     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4446 
4447   // Folding a memory location into the two-address part of a two-address
4448   // instruction is different than folding it other places.  It requires
4449   // replacing the *two* registers with the memory location.
4450   const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
4451   if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
4452     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4453   } else if (OpNum == 0) { // If operand 0
4454     if (Opc == X86::MOV32r0)
4455       return true;
4456 
4457     OpcodeTablePtr = &RegOp2MemOpTable0;
4458   } else if (OpNum == 1) {
4459     OpcodeTablePtr = &RegOp2MemOpTable1;
4460   } else if (OpNum == 2) {
4461     OpcodeTablePtr = &RegOp2MemOpTable2;
4462   } else if (OpNum == 3) {
4463     OpcodeTablePtr = &RegOp2MemOpTable3;
4464   }
4465 
4466   if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4467     return true;
4468   return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
4469 }
4470 
4471 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4472                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
4473                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
4474   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4475     MemOp2RegOpTable.find(MI->getOpcode());
4476   if (I == MemOp2RegOpTable.end())
4477     return false;
4478   unsigned Opc = I->second.first;
4479   unsigned Index = I->second.second & TB_INDEX_MASK;
4480   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4481   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4482   if (UnfoldLoad && !FoldedLoad)
4483     return false;
4484   UnfoldLoad &= FoldedLoad;
4485   if (UnfoldStore && !FoldedStore)
4486     return false;
4487   UnfoldStore &= FoldedStore;
4488 
4489   const MCInstrDesc &MCID = get(Opc);
4490   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4491   if (!MI->hasOneMemOperand() &&
4492       RC == &X86::VR128RegClass &&
4493       !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4494     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4495     // conservatively assume the address is unaligned. That's bad for
4496     // performance.
4497     return false;
4498   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
4499   SmallVector<MachineOperand,2> BeforeOps;
4500   SmallVector<MachineOperand,2> AfterOps;
4501   SmallVector<MachineOperand,4> ImpOps;
4502   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4503     MachineOperand &Op = MI->getOperand(i);
4504     if (i >= Index && i < Index + X86::AddrNumOperands)
4505       AddrOps.push_back(Op);
4506     else if (Op.isReg() && Op.isImplicit())
4507       ImpOps.push_back(Op);
4508     else if (i < Index)
4509       BeforeOps.push_back(Op);
4510     else if (i > Index)
4511       AfterOps.push_back(Op);
4512   }
4513 
4514   // Emit the load instruction.
4515   if (UnfoldLoad) {
4516     std::pair<MachineInstr::mmo_iterator,
4517               MachineInstr::mmo_iterator> MMOs =
4518       MF.extractLoadMemRefs(MI->memoperands_begin(),
4519                             MI->memoperands_end());
4520     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
4521     if (UnfoldStore) {
4522       // Address operands cannot be marked isKill.
4523       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
4524         MachineOperand &MO = NewMIs[0]->getOperand(i);
4525         if (MO.isReg())
4526           MO.setIsKill(false);
4527       }
4528     }
4529   }
4530 
4531   // Emit the data processing instruction.
4532   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
4533   MachineInstrBuilder MIB(MF, DataMI);
4534 
4535   if (FoldedStore)
4536     MIB.addReg(Reg, RegState::Define);
4537   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
4538     MIB.addOperand(BeforeOps[i]);
4539   if (FoldedLoad)
4540     MIB.addReg(Reg);
4541   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
4542     MIB.addOperand(AfterOps[i]);
4543   for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
4544     MachineOperand &MO = ImpOps[i];
4545     MIB.addReg(MO.getReg(),
4546                getDefRegState(MO.isDef()) |
4547                RegState::Implicit |
4548                getKillRegState(MO.isKill()) |
4549                getDeadRegState(MO.isDead()) |
4550                getUndefRegState(MO.isUndef()));
4551   }
4552   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
4553   switch (DataMI->getOpcode()) {
4554   default: break;
4555   case X86::CMP64ri32:
4556   case X86::CMP64ri8:
4557   case X86::CMP32ri:
4558   case X86::CMP32ri8:
4559   case X86::CMP16ri:
4560   case X86::CMP16ri8:
4561   case X86::CMP8ri: {
4562     MachineOperand &MO0 = DataMI->getOperand(0);
4563     MachineOperand &MO1 = DataMI->getOperand(1);
4564     if (MO1.getImm() == 0) {
4565       unsigned NewOpc;
4566       switch (DataMI->getOpcode()) {
4567       default: llvm_unreachable("Unreachable!");
4568       case X86::CMP64ri8:
4569       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
4570       case X86::CMP32ri8:
4571       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
4572       case X86::CMP16ri8:
4573       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
4574       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
4575       }
4576       DataMI->setDesc(get(NewOpc));
4577       MO1.ChangeToRegister(MO0.getReg(), false);
4578     }
4579   }
4580   }
4581   NewMIs.push_back(DataMI);
4582 
4583   // Emit the store instruction.
4584   if (UnfoldStore) {
4585     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
4586     std::pair<MachineInstr::mmo_iterator,
4587               MachineInstr::mmo_iterator> MMOs =
4588       MF.extractStoreMemRefs(MI->memoperands_begin(),
4589                              MI->memoperands_end());
4590     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
4591   }
4592 
4593   return true;
4594 }
4595 
4596 bool
4597 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
4598                                   SmallVectorImpl<SDNode*> &NewNodes) const {
4599   if (!N->isMachineOpcode())
4600     return false;
4601 
4602   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4603     MemOp2RegOpTable.find(N->getMachineOpcode());
4604   if (I == MemOp2RegOpTable.end())
4605     return false;
4606   unsigned Opc = I->second.first;
4607   unsigned Index = I->second.second & TB_INDEX_MASK;
4608   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4609   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4610   const MCInstrDesc &MCID = get(Opc);
4611   MachineFunction &MF = DAG.getMachineFunction();
4612   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4613   unsigned NumDefs = MCID.NumDefs;
4614   std::vector<SDValue> AddrOps;
4615   std::vector<SDValue> BeforeOps;
4616   std::vector<SDValue> AfterOps;
4617   SDLoc dl(N);
4618   unsigned NumOps = N->getNumOperands();
4619   for (unsigned i = 0; i != NumOps-1; ++i) {
4620     SDValue Op = N->getOperand(i);
4621     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
4622       AddrOps.push_back(Op);
4623     else if (i < Index-NumDefs)
4624       BeforeOps.push_back(Op);
4625     else if (i > Index-NumDefs)
4626       AfterOps.push_back(Op);
4627   }
4628   SDValue Chain = N->getOperand(NumOps-1);
4629   AddrOps.push_back(Chain);
4630 
4631   // Emit the load instruction.
4632   SDNode *Load = 0;
4633   if (FoldedLoad) {
4634     EVT VT = *RC->vt_begin();
4635     std::pair<MachineInstr::mmo_iterator,
4636               MachineInstr::mmo_iterator> MMOs =
4637       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4638                             cast<MachineSDNode>(N)->memoperands_end());
4639     if (!(*MMOs.first) &&
4640         RC == &X86::VR128RegClass &&
4641         !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4642       // Do not introduce a slow unaligned load.
4643       return false;
4644     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4645     bool isAligned = (*MMOs.first) &&
4646                      (*MMOs.first)->getAlignment() >= Alignment;
4647     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
4648                               VT, MVT::Other, AddrOps);
4649     NewNodes.push_back(Load);
4650 
4651     // Preserve memory reference information.
4652     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4653   }
4654 
4655   // Emit the data processing instruction.
4656   std::vector<EVT> VTs;
4657   const TargetRegisterClass *DstRC = 0;
4658   if (MCID.getNumDefs() > 0) {
4659     DstRC = getRegClass(MCID, 0, &RI, MF);
4660     VTs.push_back(*DstRC->vt_begin());
4661   }
4662   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
4663     EVT VT = N->getValueType(i);
4664     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
4665       VTs.push_back(VT);
4666   }
4667   if (Load)
4668     BeforeOps.push_back(SDValue(Load, 0));
4669   std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
4670   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
4671   NewNodes.push_back(NewNode);
4672 
4673   // Emit the store instruction.
4674   if (FoldedStore) {
4675     AddrOps.pop_back();
4676     AddrOps.push_back(SDValue(NewNode, 0));
4677     AddrOps.push_back(Chain);
4678     std::pair<MachineInstr::mmo_iterator,
4679               MachineInstr::mmo_iterator> MMOs =
4680       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4681                              cast<MachineSDNode>(N)->memoperands_end());
4682     if (!(*MMOs.first) &&
4683         RC == &X86::VR128RegClass &&
4684         !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4685       // Do not introduce a slow unaligned store.
4686       return false;
4687     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4688     bool isAligned = (*MMOs.first) &&
4689                      (*MMOs.first)->getAlignment() >= Alignment;
4690     SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
4691                                                          isAligned, TM),
4692                                        dl, MVT::Other, AddrOps);
4693     NewNodes.push_back(Store);
4694 
4695     // Preserve memory reference information.
4696     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4697   }
4698 
4699   return true;
4700 }
4701 
4702 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
4703                                       bool UnfoldLoad, bool UnfoldStore,
4704                                       unsigned *LoadRegIndex) const {
4705   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4706     MemOp2RegOpTable.find(Opc);
4707   if (I == MemOp2RegOpTable.end())
4708     return 0;
4709   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4710   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4711   if (UnfoldLoad && !FoldedLoad)
4712     return 0;
4713   if (UnfoldStore && !FoldedStore)
4714     return 0;
4715   if (LoadRegIndex)
4716     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
4717   return I->second.first;
4718 }
4719 
4720 bool
4721 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
4722                                      int64_t &Offset1, int64_t &Offset2) const {
4723   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
4724     return false;
4725   unsigned Opc1 = Load1->getMachineOpcode();
4726   unsigned Opc2 = Load2->getMachineOpcode();
4727   switch (Opc1) {
4728   default: return false;
4729   case X86::MOV8rm:
4730   case X86::MOV16rm:
4731   case X86::MOV32rm:
4732   case X86::MOV64rm:
4733   case X86::LD_Fp32m:
4734   case X86::LD_Fp64m:
4735   case X86::LD_Fp80m:
4736   case X86::MOVSSrm:
4737   case X86::MOVSDrm:
4738   case X86::MMX_MOVD64rm:
4739   case X86::MMX_MOVQ64rm:
4740   case X86::FsMOVAPSrm:
4741   case X86::FsMOVAPDrm:
4742   case X86::MOVAPSrm:
4743   case X86::MOVUPSrm:
4744   case X86::MOVAPDrm:
4745   case X86::MOVDQArm:
4746   case X86::MOVDQUrm:
4747   // AVX load instructions
4748   case X86::VMOVSSrm:
4749   case X86::VMOVSDrm:
4750   case X86::FsVMOVAPSrm:
4751   case X86::FsVMOVAPDrm:
4752   case X86::VMOVAPSrm:
4753   case X86::VMOVUPSrm:
4754   case X86::VMOVAPDrm:
4755   case X86::VMOVDQArm:
4756   case X86::VMOVDQUrm:
4757   case X86::VMOVAPSYrm:
4758   case X86::VMOVUPSYrm:
4759   case X86::VMOVAPDYrm:
4760   case X86::VMOVDQAYrm:
4761   case X86::VMOVDQUYrm:
4762     break;
4763   }
4764   switch (Opc2) {
4765   default: return false;
4766   case X86::MOV8rm:
4767   case X86::MOV16rm:
4768   case X86::MOV32rm:
4769   case X86::MOV64rm:
4770   case X86::LD_Fp32m:
4771   case X86::LD_Fp64m:
4772   case X86::LD_Fp80m:
4773   case X86::MOVSSrm:
4774   case X86::MOVSDrm:
4775   case X86::MMX_MOVD64rm:
4776   case X86::MMX_MOVQ64rm:
4777   case X86::FsMOVAPSrm:
4778   case X86::FsMOVAPDrm:
4779   case X86::MOVAPSrm:
4780   case X86::MOVUPSrm:
4781   case X86::MOVAPDrm:
4782   case X86::MOVDQArm:
4783   case X86::MOVDQUrm:
4784   // AVX load instructions
4785   case X86::VMOVSSrm:
4786   case X86::VMOVSDrm:
4787   case X86::FsVMOVAPSrm:
4788   case X86::FsVMOVAPDrm:
4789   case X86::VMOVAPSrm:
4790   case X86::VMOVUPSrm:
4791   case X86::VMOVAPDrm:
4792   case X86::VMOVDQArm:
4793   case X86::VMOVDQUrm:
4794   case X86::VMOVAPSYrm:
4795   case X86::VMOVUPSYrm:
4796   case X86::VMOVAPDYrm:
4797   case X86::VMOVDQAYrm:
4798   case X86::VMOVDQUYrm:
4799     break;
4800   }
4801 
4802   // Check if chain operands and base addresses match.
4803   if (Load1->getOperand(0) != Load2->getOperand(0) ||
4804       Load1->getOperand(5) != Load2->getOperand(5))
4805     return false;
4806   // Segment operands should match as well.
4807   if (Load1->getOperand(4) != Load2->getOperand(4))
4808     return false;
4809   // Scale should be 1, Index should be Reg0.
4810   if (Load1->getOperand(1) == Load2->getOperand(1) &&
4811       Load1->getOperand(2) == Load2->getOperand(2)) {
4812     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
4813       return false;
4814 
4815     // Now let's examine the displacements.
4816     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
4817         isa<ConstantSDNode>(Load2->getOperand(3))) {
4818       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
4819       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
4820       return true;
4821     }
4822   }
4823   return false;
4824 }
4825 
4826 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
4827                                            int64_t Offset1, int64_t Offset2,
4828                                            unsigned NumLoads) const {
4829   assert(Offset2 > Offset1);
4830   if ((Offset2 - Offset1) / 8 > 64)
4831     return false;
4832 
4833   unsigned Opc1 = Load1->getMachineOpcode();
4834   unsigned Opc2 = Load2->getMachineOpcode();
4835   if (Opc1 != Opc2)
4836     return false;  // FIXME: overly conservative?
4837 
4838   switch (Opc1) {
4839   default: break;
4840   case X86::LD_Fp32m:
4841   case X86::LD_Fp64m:
4842   case X86::LD_Fp80m:
4843   case X86::MMX_MOVD64rm:
4844   case X86::MMX_MOVQ64rm:
4845     return false;
4846   }
4847 
4848   EVT VT = Load1->getValueType(0);
4849   switch (VT.getSimpleVT().SimpleTy) {
4850   default:
4851     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
4852     // have 16 of them to play with.
4853     if (TM.getSubtargetImpl()->is64Bit()) {
4854       if (NumLoads >= 3)
4855         return false;
4856     } else if (NumLoads) {
4857       return false;
4858     }
4859     break;
4860   case MVT::i8:
4861   case MVT::i16:
4862   case MVT::i32:
4863   case MVT::i64:
4864   case MVT::f32:
4865   case MVT::f64:
4866     if (NumLoads)
4867       return false;
4868     break;
4869   }
4870 
4871   return true;
4872 }
4873 
4874 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
4875                                           MachineInstr *Second) const {
4876   // Check if this processor supports macro-fusion. Since this is a minor
4877   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
4878   // proxy for SandyBridge+.
4879   if (!TM.getSubtarget<X86Subtarget>().hasAVX())
4880     return false;
4881 
4882   enum {
4883     FuseTest,
4884     FuseCmp,
4885     FuseInc
4886   } FuseKind;
4887 
4888   switch(Second->getOpcode()) {
4889   default:
4890     return false;
4891   case X86::JE_4:
4892   case X86::JNE_4:
4893   case X86::JL_4:
4894   case X86::JLE_4:
4895   case X86::JG_4:
4896   case X86::JGE_4:
4897     FuseKind = FuseInc;
4898     break;
4899   case X86::JB_4:
4900   case X86::JBE_4:
4901   case X86::JA_4:
4902   case X86::JAE_4:
4903     FuseKind = FuseCmp;
4904     break;
4905   case X86::JS_4:
4906   case X86::JNS_4:
4907   case X86::JP_4:
4908   case X86::JNP_4:
4909   case X86::JO_4:
4910   case X86::JNO_4:
4911     FuseKind = FuseTest;
4912     break;
4913   }
4914   switch (First->getOpcode()) {
4915   default:
4916     return false;
4917   case X86::TEST8rr:
4918   case X86::TEST16rr:
4919   case X86::TEST32rr:
4920   case X86::TEST64rr:
4921   case X86::TEST8ri:
4922   case X86::TEST16ri:
4923   case X86::TEST32ri:
4924   case X86::TEST32i32:
4925   case X86::TEST64i32:
4926   case X86::TEST64ri32:
4927   case X86::TEST8rm:
4928   case X86::TEST16rm:
4929   case X86::TEST32rm:
4930   case X86::TEST64rm:
4931   case X86::AND16i16:
4932   case X86::AND16ri:
4933   case X86::AND16ri8:
4934   case X86::AND16rm:
4935   case X86::AND16rr:
4936   case X86::AND32i32:
4937   case X86::AND32ri:
4938   case X86::AND32ri8:
4939   case X86::AND32rm:
4940   case X86::AND32rr:
4941   case X86::AND64i32:
4942   case X86::AND64ri32:
4943   case X86::AND64ri8:
4944   case X86::AND64rm:
4945   case X86::AND64rr:
4946   case X86::AND8i8:
4947   case X86::AND8ri:
4948   case X86::AND8rm:
4949   case X86::AND8rr:
4950     return true;
4951   case X86::CMP16i16:
4952   case X86::CMP16ri:
4953   case X86::CMP16ri8:
4954   case X86::CMP16rm:
4955   case X86::CMP16rr:
4956   case X86::CMP32i32:
4957   case X86::CMP32ri:
4958   case X86::CMP32ri8:
4959   case X86::CMP32rm:
4960   case X86::CMP32rr:
4961   case X86::CMP64i32:
4962   case X86::CMP64ri32:
4963   case X86::CMP64ri8:
4964   case X86::CMP64rm:
4965   case X86::CMP64rr:
4966   case X86::CMP8i8:
4967   case X86::CMP8ri:
4968   case X86::CMP8rm:
4969   case X86::CMP8rr:
4970   case X86::ADD16i16:
4971   case X86::ADD16ri:
4972   case X86::ADD16ri8:
4973   case X86::ADD16ri8_DB:
4974   case X86::ADD16ri_DB:
4975   case X86::ADD16rm:
4976   case X86::ADD16rr:
4977   case X86::ADD16rr_DB:
4978   case X86::ADD32i32:
4979   case X86::ADD32ri:
4980   case X86::ADD32ri8:
4981   case X86::ADD32ri8_DB:
4982   case X86::ADD32ri_DB:
4983   case X86::ADD32rm:
4984   case X86::ADD32rr:
4985   case X86::ADD32rr_DB:
4986   case X86::ADD64i32:
4987   case X86::ADD64ri32:
4988   case X86::ADD64ri32_DB:
4989   case X86::ADD64ri8:
4990   case X86::ADD64ri8_DB:
4991   case X86::ADD64rm:
4992   case X86::ADD64rr:
4993   case X86::ADD64rr_DB:
4994   case X86::ADD8i8:
4995   case X86::ADD8mi:
4996   case X86::ADD8mr:
4997   case X86::ADD8ri:
4998   case X86::ADD8rm:
4999   case X86::ADD8rr:
5000   case X86::SUB16i16:
5001   case X86::SUB16ri:
5002   case X86::SUB16ri8:
5003   case X86::SUB16rm:
5004   case X86::SUB16rr:
5005   case X86::SUB32i32:
5006   case X86::SUB32ri:
5007   case X86::SUB32ri8:
5008   case X86::SUB32rm:
5009   case X86::SUB32rr:
5010   case X86::SUB64i32:
5011   case X86::SUB64ri32:
5012   case X86::SUB64ri8:
5013   case X86::SUB64rm:
5014   case X86::SUB64rr:
5015   case X86::SUB8i8:
5016   case X86::SUB8ri:
5017   case X86::SUB8rm:
5018   case X86::SUB8rr:
5019     return FuseKind == FuseCmp || FuseKind == FuseInc;
5020   case X86::INC16r:
5021   case X86::INC32r:
5022   case X86::INC64_16r:
5023   case X86::INC64_32r:
5024   case X86::INC64r:
5025   case X86::INC8r:
5026   case X86::DEC16r:
5027   case X86::DEC32r:
5028   case X86::DEC64_16r:
5029   case X86::DEC64_32r:
5030   case X86::DEC64r:
5031   case X86::DEC8r:
5032     return FuseKind == FuseInc;
5033   }
5034 }
5035 
5036 bool X86InstrInfo::
5037 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5038   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5039   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5040   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5041     return true;
5042   Cond[0].setImm(GetOppositeBranchCondition(CC));
5043   return false;
5044 }
5045 
5046 bool X86InstrInfo::
5047 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5048   // FIXME: Return false for x87 stack register classes for now. We can't
5049   // allow any loads of these registers before FpGet_ST0_80.
5050   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5051            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
5052 }
5053 
5054 /// getGlobalBaseReg - Return a virtual register initialized with the
5055 /// the global base register value. Output instructions required to
5056 /// initialize the register in the function entry block, if necessary.
5057 ///
5058 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5059 ///
5060 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5061   assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
5062          "X86-64 PIC uses RIP relative addressing");
5063 
5064   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5065   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5066   if (GlobalBaseReg != 0)
5067     return GlobalBaseReg;
5068 
5069   // Create the register. The code to initialize it is inserted
5070   // later, by the CGBR pass (below).
5071   MachineRegisterInfo &RegInfo = MF->getRegInfo();
5072   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
5073   X86FI->setGlobalBaseReg(GlobalBaseReg);
5074   return GlobalBaseReg;
5075 }
5076 
5077 // These are the replaceable SSE instructions. Some of these have Int variants
5078 // that we don't include here. We don't want to replace instructions selected
5079 // by intrinsics.
5080 static const uint16_t ReplaceableInstrs[][3] = {
5081   //PackedSingle     PackedDouble    PackedInt
5082   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
5083   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
5084   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
5085   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
5086   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
5087   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
5088   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
5089   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
5090   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
5091   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
5092   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
5093   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
5094   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
5095   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
5096   // AVX 128-bit support
5097   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
5098   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
5099   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
5100   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
5101   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
5102   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5103   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
5104   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
5105   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
5106   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
5107   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
5108   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
5109   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
5110   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
5111   // AVX 256-bit support
5112   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
5113   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
5114   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
5115   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
5116   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
5117   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
5118 };
5119 
5120 static const uint16_t ReplaceableInstrsAVX2[][3] = {
5121   //PackedSingle       PackedDouble       PackedInt
5122   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
5123   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
5124   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
5125   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
5126   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
5127   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
5128   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
5129   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
5130   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5131   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5132   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
5133   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
5134   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
5135   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr }
5136 };
5137 
5138 // FIXME: Some shuffle and unpack instructions have equivalents in different
5139 // domains, but they require a bit more work than just switching opcodes.
5140 
5141 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
5142   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
5143     if (ReplaceableInstrs[i][domain-1] == opcode)
5144       return ReplaceableInstrs[i];
5145   return 0;
5146 }
5147 
5148 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
5149   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5150     if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5151       return ReplaceableInstrsAVX2[i];
5152   return 0;
5153 }
5154 
5155 std::pair<uint16_t, uint16_t>
5156 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
5157   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5158   bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
5159   uint16_t validDomains = 0;
5160   if (domain && lookup(MI->getOpcode(), domain))
5161     validDomains = 0xe;
5162   else if (domain && lookupAVX2(MI->getOpcode(), domain))
5163     validDomains = hasAVX2 ? 0xe : 0x6;
5164   return std::make_pair(domain, validDomains);
5165 }
5166 
5167 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
5168   assert(Domain>0 && Domain<4 && "Invalid execution domain");
5169   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5170   assert(dom && "Not an SSE instruction");
5171   const uint16_t *table = lookup(MI->getOpcode(), dom);
5172   if (!table) { // try the other table
5173     assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
5174            "256-bit vector operations only available in AVX2");
5175     table = lookupAVX2(MI->getOpcode(), dom);
5176   }
5177   assert(table && "Cannot change domain");
5178   MI->setDesc(get(table[Domain-1]));
5179 }
5180 
5181 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
5182 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5183   NopInst.setOpcode(X86::NOOP);
5184 }
5185 
5186 bool X86InstrInfo::isHighLatencyDef(int opc) const {
5187   switch (opc) {
5188   default: return false;
5189   case X86::DIVSDrm:
5190   case X86::DIVSDrm_Int:
5191   case X86::DIVSDrr:
5192   case X86::DIVSDrr_Int:
5193   case X86::DIVSSrm:
5194   case X86::DIVSSrm_Int:
5195   case X86::DIVSSrr:
5196   case X86::DIVSSrr_Int:
5197   case X86::SQRTPDm:
5198   case X86::SQRTPDr:
5199   case X86::SQRTPSm:
5200   case X86::SQRTPSr:
5201   case X86::SQRTSDm:
5202   case X86::SQRTSDm_Int:
5203   case X86::SQRTSDr:
5204   case X86::SQRTSDr_Int:
5205   case X86::SQRTSSm:
5206   case X86::SQRTSSm_Int:
5207   case X86::SQRTSSr:
5208   case X86::SQRTSSr_Int:
5209   // AVX instructions with high latency
5210   case X86::VDIVSDrm:
5211   case X86::VDIVSDrm_Int:
5212   case X86::VDIVSDrr:
5213   case X86::VDIVSDrr_Int:
5214   case X86::VDIVSSrm:
5215   case X86::VDIVSSrm_Int:
5216   case X86::VDIVSSrr:
5217   case X86::VDIVSSrr_Int:
5218   case X86::VSQRTPDm:
5219   case X86::VSQRTPDr:
5220   case X86::VSQRTPSm:
5221   case X86::VSQRTPSr:
5222   case X86::VSQRTSDm:
5223   case X86::VSQRTSDm_Int:
5224   case X86::VSQRTSDr:
5225   case X86::VSQRTSSm:
5226   case X86::VSQRTSSm_Int:
5227   case X86::VSQRTSSr:
5228   case X86::VSQRTPDZrm:
5229   case X86::VSQRTPDZrr:
5230   case X86::VSQRTPSZrm:
5231   case X86::VSQRTPSZrr:
5232   case X86::VSQRTSDZm:
5233   case X86::VSQRTSDZm_Int:
5234   case X86::VSQRTSDZr:
5235   case X86::VSQRTSSZm_Int:
5236   case X86::VSQRTSSZr:
5237   case X86::VSQRTSSZm:
5238   case X86::VDIVSDZrm:
5239   case X86::VDIVSDZrr:
5240   case X86::VDIVSSZrm:
5241   case X86::VDIVSSZrr:
5242 
5243   case X86::VGATHERQPSZrm:
5244   case X86::VGATHERQPDZrm:
5245   case X86::VGATHERDPDZrm:
5246   case X86::VGATHERDPSZrm:
5247   case X86::VPGATHERQDZrm:
5248   case X86::VPGATHERQQZrm:
5249   case X86::VPGATHERDDZrm:
5250   case X86::VPGATHERDQZrm:
5251   case X86::VSCATTERQPDZmr:
5252   case X86::VSCATTERQPSZmr:
5253   case X86::VSCATTERDPDZmr:
5254   case X86::VSCATTERDPSZmr:
5255   case X86::VPSCATTERQDZmr:
5256   case X86::VPSCATTERQQZmr:
5257   case X86::VPSCATTERDDZmr:
5258   case X86::VPSCATTERDQZmr:
5259     return true;
5260   }
5261 }
5262 
5263 bool X86InstrInfo::
5264 hasHighOperandLatency(const InstrItineraryData *ItinData,
5265                       const MachineRegisterInfo *MRI,
5266                       const MachineInstr *DefMI, unsigned DefIdx,
5267                       const MachineInstr *UseMI, unsigned UseIdx) const {
5268   return isHighLatencyDef(DefMI->getOpcode());
5269 }
5270 
5271 namespace {
5272   /// CGBR - Create Global Base Reg pass. This initializes the PIC
5273   /// global base register for x86-32.
5274   struct CGBR : public MachineFunctionPass {
5275     static char ID;
5276     CGBR() : MachineFunctionPass(ID) {}
5277 
5278     virtual bool runOnMachineFunction(MachineFunction &MF) {
5279       const X86TargetMachine *TM =
5280         static_cast<const X86TargetMachine *>(&MF.getTarget());
5281 
5282       assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
5283              "X86-64 PIC uses RIP relative addressing");
5284 
5285       // Only emit a global base reg in PIC mode.
5286       if (TM->getRelocationModel() != Reloc::PIC_)
5287         return false;
5288 
5289       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
5290       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5291 
5292       // If we didn't need a GlobalBaseReg, don't insert code.
5293       if (GlobalBaseReg == 0)
5294         return false;
5295 
5296       // Insert the set of GlobalBaseReg into the first MBB of the function
5297       MachineBasicBlock &FirstMBB = MF.front();
5298       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
5299       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
5300       MachineRegisterInfo &RegInfo = MF.getRegInfo();
5301       const X86InstrInfo *TII = TM->getInstrInfo();
5302 
5303       unsigned PC;
5304       if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
5305         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
5306       else
5307         PC = GlobalBaseReg;
5308 
5309       // Operand of MovePCtoStack is completely ignored by asm printer. It's
5310       // only used in JIT code emission as displacement to pc.
5311       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
5312 
5313       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
5314       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
5315       if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
5316         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
5317         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
5318           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
5319                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
5320       }
5321 
5322       return true;
5323     }
5324 
5325     virtual const char *getPassName() const {
5326       return "X86 PIC Global Base Reg Initialization";
5327     }
5328 
5329     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
5330       AU.setPreservesCFG();
5331       MachineFunctionPass::getAnalysisUsage(AU);
5332     }
5333   };
5334 }
5335 
5336 char CGBR::ID = 0;
5337 FunctionPass*
5338 llvm::createGlobalBaseRegPass() { return new CGBR(); }
5339 
5340 namespace {
5341   struct LDTLSCleanup : public MachineFunctionPass {
5342     static char ID;
5343     LDTLSCleanup() : MachineFunctionPass(ID) {}
5344 
5345     virtual bool runOnMachineFunction(MachineFunction &MF) {
5346       X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
5347       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
5348         // No point folding accesses if there isn't at least two.
5349         return false;
5350       }
5351 
5352       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
5353       return VisitNode(DT->getRootNode(), 0);
5354     }
5355 
5356     // Visit the dominator subtree rooted at Node in pre-order.
5357     // If TLSBaseAddrReg is non-null, then use that to replace any
5358     // TLS_base_addr instructions. Otherwise, create the register
5359     // when the first such instruction is seen, and then use it
5360     // as we encounter more instructions.
5361     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
5362       MachineBasicBlock *BB = Node->getBlock();
5363       bool Changed = false;
5364 
5365       // Traverse the current block.
5366       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
5367            ++I) {
5368         switch (I->getOpcode()) {
5369           case X86::TLS_base_addr32:
5370           case X86::TLS_base_addr64:
5371             if (TLSBaseAddrReg)
5372               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
5373             else
5374               I = SetRegister(I, &TLSBaseAddrReg);
5375             Changed = true;
5376             break;
5377           default:
5378             break;
5379         }
5380       }
5381 
5382       // Visit the children of this block in the dominator tree.
5383       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
5384            I != E; ++I) {
5385         Changed |= VisitNode(*I, TLSBaseAddrReg);
5386       }
5387 
5388       return Changed;
5389     }
5390 
5391     // Replace the TLS_base_addr instruction I with a copy from
5392     // TLSBaseAddrReg, returning the new instruction.
5393     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
5394                                          unsigned TLSBaseAddrReg) {
5395       MachineFunction *MF = I->getParent()->getParent();
5396       const X86TargetMachine *TM =
5397           static_cast<const X86TargetMachine *>(&MF->getTarget());
5398       const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5399       const X86InstrInfo *TII = TM->getInstrInfo();
5400 
5401       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
5402       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
5403                                    TII->get(TargetOpcode::COPY),
5404                                    is64Bit ? X86::RAX : X86::EAX)
5405                                    .addReg(TLSBaseAddrReg);
5406 
5407       // Erase the TLS_base_addr instruction.
5408       I->eraseFromParent();
5409 
5410       return Copy;
5411     }
5412 
5413     // Create a virtal register in *TLSBaseAddrReg, and populate it by
5414     // inserting a copy instruction after I. Returns the new instruction.
5415     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
5416       MachineFunction *MF = I->getParent()->getParent();
5417       const X86TargetMachine *TM =
5418           static_cast<const X86TargetMachine *>(&MF->getTarget());
5419       const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
5420       const X86InstrInfo *TII = TM->getInstrInfo();
5421 
5422       // Create a virtual register for the TLS base address.
5423       MachineRegisterInfo &RegInfo = MF->getRegInfo();
5424       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
5425                                                       ? &X86::GR64RegClass
5426                                                       : &X86::GR32RegClass);
5427 
5428       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
5429       MachineInstr *Next = I->getNextNode();
5430       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
5431                                    TII->get(TargetOpcode::COPY),
5432                                    *TLSBaseAddrReg)
5433                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
5434 
5435       return Copy;
5436     }
5437 
5438     virtual const char *getPassName() const {
5439       return "Local Dynamic TLS Access Clean-up";
5440     }
5441 
5442     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
5443       AU.setPreservesCFG();
5444       AU.addRequired<MachineDominatorTree>();
5445       MachineFunctionPass::getAnalysisUsage(AU);
5446     }
5447   };
5448 }
5449 
5450 char LDTLSCleanup::ID = 0;
5451 FunctionPass*
5452 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
5453