1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "x86-instr-info"
45 
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
48 
49 static cl::opt<bool>
50 NoFusing("disable-spill-fusing",
51          cl::desc("Disable fusing of spill code into instructions"));
52 static cl::opt<bool>
53 PrintFailedFusing("print-failed-fuse-candidates",
54                   cl::desc("Print instructions that the allocator wants to"
55                            " fuse, but the X86 backend currently can't"),
56                   cl::Hidden);
57 static cl::opt<bool>
58 ReMatPICStubLoad("remat-pic-stub-load",
59                  cl::desc("Re-materialize load from stub in PIC mode"),
60                  cl::init(false), cl::Hidden);
61 static cl::opt<unsigned>
62 PartialRegUpdateClearance("partial-reg-update-clearance",
63                           cl::desc("Clearance between two register writes "
64                                    "for inserting XOR to avoid partial "
65                                    "register update"),
66                           cl::init(64), cl::Hidden);
67 static cl::opt<unsigned>
68 UndefRegClearance("undef-reg-clearance",
69                   cl::desc("How many idle instructions we would like before "
70                            "certain undef register reads"),
71                   cl::init(128), cl::Hidden);
72 
73 enum {
74   // Select which memory operand is being unfolded.
75   // (stored in bits 0 - 3)
76   TB_INDEX_0    = 0,
77   TB_INDEX_1    = 1,
78   TB_INDEX_2    = 2,
79   TB_INDEX_3    = 3,
80   TB_INDEX_4    = 4,
81   TB_INDEX_MASK = 0xf,
82 
83   // Do not insert the reverse map (MemOp -> RegOp) into the table.
84   // This may be needed because there is a many -> one mapping.
85   TB_NO_REVERSE   = 1 << 4,
86 
87   // Do not insert the forward map (RegOp -> MemOp) into the table.
88   // This is needed for Native Client, which prohibits branch
89   // instructions from using a memory operand.
90   TB_NO_FORWARD   = 1 << 5,
91 
92   TB_FOLDED_LOAD  = 1 << 6,
93   TB_FOLDED_STORE = 1 << 7,
94 
95   // Minimum alignment required for load/store.
96   // Used for RegOp->MemOp conversion.
97   // (stored in bits 8 - 15)
98   TB_ALIGN_SHIFT = 8,
99   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
100   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
101   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
102   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
103   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
104 };
105 
106 struct X86MemoryFoldTableEntry {
107   uint16_t RegOp;
108   uint16_t MemOp;
109   uint16_t Flags;
110 };
111 
112 // Pin the vtable to this file.
113 void X86InstrInfo::anchor() {}
114 
115 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
116     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117                                                : X86::ADJCALLSTACKDOWN32),
118                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119                                                : X86::ADJCALLSTACKUP32),
120                       X86::CATCHRET,
121                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
122       Subtarget(STI), RI(STI.getTargetTriple()) {
123 
124   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
125     { X86::ADC32ri,     X86::ADC32mi,    0 },
126     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
127     { X86::ADC32rr,     X86::ADC32mr,    0 },
128     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
129     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
130     { X86::ADC64rr,     X86::ADC64mr,    0 },
131     { X86::ADD16ri,     X86::ADD16mi,    0 },
132     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
133     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
134     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
135     { X86::ADD16rr,     X86::ADD16mr,    0 },
136     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
137     { X86::ADD32ri,     X86::ADD32mi,    0 },
138     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
139     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
140     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
141     { X86::ADD32rr,     X86::ADD32mr,    0 },
142     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
143     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
144     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
145     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
146     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
147     { X86::ADD64rr,     X86::ADD64mr,    0 },
148     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
149     { X86::ADD8ri,      X86::ADD8mi,     0 },
150     { X86::ADD8rr,      X86::ADD8mr,     0 },
151     { X86::AND16ri,     X86::AND16mi,    0 },
152     { X86::AND16ri8,    X86::AND16mi8,   0 },
153     { X86::AND16rr,     X86::AND16mr,    0 },
154     { X86::AND32ri,     X86::AND32mi,    0 },
155     { X86::AND32ri8,    X86::AND32mi8,   0 },
156     { X86::AND32rr,     X86::AND32mr,    0 },
157     { X86::AND64ri32,   X86::AND64mi32,  0 },
158     { X86::AND64ri8,    X86::AND64mi8,   0 },
159     { X86::AND64rr,     X86::AND64mr,    0 },
160     { X86::AND8ri,      X86::AND8mi,     0 },
161     { X86::AND8rr,      X86::AND8mr,     0 },
162     { X86::DEC16r,      X86::DEC16m,     0 },
163     { X86::DEC32r,      X86::DEC32m,     0 },
164     { X86::DEC64r,      X86::DEC64m,     0 },
165     { X86::DEC8r,       X86::DEC8m,      0 },
166     { X86::INC16r,      X86::INC16m,     0 },
167     { X86::INC32r,      X86::INC32m,     0 },
168     { X86::INC64r,      X86::INC64m,     0 },
169     { X86::INC8r,       X86::INC8m,      0 },
170     { X86::NEG16r,      X86::NEG16m,     0 },
171     { X86::NEG32r,      X86::NEG32m,     0 },
172     { X86::NEG64r,      X86::NEG64m,     0 },
173     { X86::NEG8r,       X86::NEG8m,      0 },
174     { X86::NOT16r,      X86::NOT16m,     0 },
175     { X86::NOT32r,      X86::NOT32m,     0 },
176     { X86::NOT64r,      X86::NOT64m,     0 },
177     { X86::NOT8r,       X86::NOT8m,      0 },
178     { X86::OR16ri,      X86::OR16mi,     0 },
179     { X86::OR16ri8,     X86::OR16mi8,    0 },
180     { X86::OR16rr,      X86::OR16mr,     0 },
181     { X86::OR32ri,      X86::OR32mi,     0 },
182     { X86::OR32ri8,     X86::OR32mi8,    0 },
183     { X86::OR32rr,      X86::OR32mr,     0 },
184     { X86::OR64ri32,    X86::OR64mi32,   0 },
185     { X86::OR64ri8,     X86::OR64mi8,    0 },
186     { X86::OR64rr,      X86::OR64mr,     0 },
187     { X86::OR8ri,       X86::OR8mi,      0 },
188     { X86::OR8rr,       X86::OR8mr,      0 },
189     { X86::ROL16r1,     X86::ROL16m1,    0 },
190     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
191     { X86::ROL16ri,     X86::ROL16mi,    0 },
192     { X86::ROL32r1,     X86::ROL32m1,    0 },
193     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
194     { X86::ROL32ri,     X86::ROL32mi,    0 },
195     { X86::ROL64r1,     X86::ROL64m1,    0 },
196     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
197     { X86::ROL64ri,     X86::ROL64mi,    0 },
198     { X86::ROL8r1,      X86::ROL8m1,     0 },
199     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
200     { X86::ROL8ri,      X86::ROL8mi,     0 },
201     { X86::ROR16r1,     X86::ROR16m1,    0 },
202     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
203     { X86::ROR16ri,     X86::ROR16mi,    0 },
204     { X86::ROR32r1,     X86::ROR32m1,    0 },
205     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
206     { X86::ROR32ri,     X86::ROR32mi,    0 },
207     { X86::ROR64r1,     X86::ROR64m1,    0 },
208     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
209     { X86::ROR64ri,     X86::ROR64mi,    0 },
210     { X86::ROR8r1,      X86::ROR8m1,     0 },
211     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
212     { X86::ROR8ri,      X86::ROR8mi,     0 },
213     { X86::SAR16r1,     X86::SAR16m1,    0 },
214     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
215     { X86::SAR16ri,     X86::SAR16mi,    0 },
216     { X86::SAR32r1,     X86::SAR32m1,    0 },
217     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
218     { X86::SAR32ri,     X86::SAR32mi,    0 },
219     { X86::SAR64r1,     X86::SAR64m1,    0 },
220     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
221     { X86::SAR64ri,     X86::SAR64mi,    0 },
222     { X86::SAR8r1,      X86::SAR8m1,     0 },
223     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
224     { X86::SAR8ri,      X86::SAR8mi,     0 },
225     { X86::SBB32ri,     X86::SBB32mi,    0 },
226     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
227     { X86::SBB32rr,     X86::SBB32mr,    0 },
228     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
229     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
230     { X86::SBB64rr,     X86::SBB64mr,    0 },
231     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
232     { X86::SHL16ri,     X86::SHL16mi,    0 },
233     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
234     { X86::SHL32ri,     X86::SHL32mi,    0 },
235     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
236     { X86::SHL64ri,     X86::SHL64mi,    0 },
237     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
238     { X86::SHL8ri,      X86::SHL8mi,     0 },
239     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
240     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
241     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
242     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
243     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
244     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
245     { X86::SHR16r1,     X86::SHR16m1,    0 },
246     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
247     { X86::SHR16ri,     X86::SHR16mi,    0 },
248     { X86::SHR32r1,     X86::SHR32m1,    0 },
249     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
250     { X86::SHR32ri,     X86::SHR32mi,    0 },
251     { X86::SHR64r1,     X86::SHR64m1,    0 },
252     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
253     { X86::SHR64ri,     X86::SHR64mi,    0 },
254     { X86::SHR8r1,      X86::SHR8m1,     0 },
255     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
256     { X86::SHR8ri,      X86::SHR8mi,     0 },
257     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
258     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
259     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
260     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
261     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
262     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
263     { X86::SUB16ri,     X86::SUB16mi,    0 },
264     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
265     { X86::SUB16rr,     X86::SUB16mr,    0 },
266     { X86::SUB32ri,     X86::SUB32mi,    0 },
267     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
268     { X86::SUB32rr,     X86::SUB32mr,    0 },
269     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
270     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
271     { X86::SUB64rr,     X86::SUB64mr,    0 },
272     { X86::SUB8ri,      X86::SUB8mi,     0 },
273     { X86::SUB8rr,      X86::SUB8mr,     0 },
274     { X86::XOR16ri,     X86::XOR16mi,    0 },
275     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
276     { X86::XOR16rr,     X86::XOR16mr,    0 },
277     { X86::XOR32ri,     X86::XOR32mi,    0 },
278     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
279     { X86::XOR32rr,     X86::XOR32mr,    0 },
280     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
281     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
282     { X86::XOR64rr,     X86::XOR64mr,    0 },
283     { X86::XOR8ri,      X86::XOR8mi,     0 },
284     { X86::XOR8rr,      X86::XOR8mr,     0 }
285   };
286 
287   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
288     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
289                   Entry.RegOp, Entry.MemOp,
290                   // Index 0, folded load and store, no alignment requirement.
291                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
292   }
293 
294   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
295     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
296     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
297     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
298     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
299     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
300     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
301     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
302     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
303     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
304     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
305     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
306     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
307     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
308     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
309     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
310     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
311     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
312     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
313     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
314     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
315     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
316     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
317     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
318     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
319     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
320     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
321     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
322     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
323     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
324     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
325     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
326     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
327     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
328     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
329     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
330     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
331     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
332     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
333     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
334     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
335     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
336     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
337     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
338     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
339     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
340     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
341     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
342     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
343     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
344     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
345     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
346     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
347     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
348     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
349     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
350     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
351     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
352     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
353     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
354     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
355     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
356     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
357     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
358     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
359     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
360     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
361     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
362     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
363     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
364     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
365     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
366     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
367     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
368     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
369     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
370     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
371     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
372     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
373     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
374     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
375     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
376 
377     // AVX 128-bit versions of foldable instructions
378     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
379     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
380     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
381     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
382     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
383     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
384     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
385     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
386     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
387     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
388     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
389     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
390     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
391 
392     // AVX 256-bit foldable instructions
393     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
394     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
395     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
396     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
397     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
398     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
399 
400     // AVX-512 foldable instructions
401     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
402     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
403     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
404     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
405     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
406     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
407     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
408     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
409     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
410     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
411     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
412     { X86::VPMOVDBZrr,      X86::VPMOVDBZmr,    TB_FOLDED_STORE },
413     { X86::VPMOVDWZrr,      X86::VPMOVDWZmr,    TB_FOLDED_STORE },
414     { X86::VPMOVQDZrr,      X86::VPMOVQDZmr,    TB_FOLDED_STORE },
415     { X86::VPMOVQWZrr,      X86::VPMOVQWZmr,    TB_FOLDED_STORE },
416     { X86::VPMOVWBZrr,      X86::VPMOVWBZmr,    TB_FOLDED_STORE },
417     { X86::VPMOVSDBZrr,     X86::VPMOVSDBZmr,   TB_FOLDED_STORE },
418     { X86::VPMOVSDWZrr,     X86::VPMOVSDWZmr,   TB_FOLDED_STORE },
419     { X86::VPMOVSQDZrr,     X86::VPMOVSQDZmr,   TB_FOLDED_STORE },
420     { X86::VPMOVSQWZrr,     X86::VPMOVSQWZmr,   TB_FOLDED_STORE },
421     { X86::VPMOVSWBZrr,     X86::VPMOVSWBZmr,   TB_FOLDED_STORE },
422     { X86::VPMOVUSDBZrr,    X86::VPMOVUSDBZmr,  TB_FOLDED_STORE },
423     { X86::VPMOVUSDWZrr,    X86::VPMOVUSDWZmr,  TB_FOLDED_STORE },
424     { X86::VPMOVUSQDZrr,    X86::VPMOVUSQDZmr,  TB_FOLDED_STORE },
425     { X86::VPMOVUSQWZrr,    X86::VPMOVUSQWZmr,  TB_FOLDED_STORE },
426     { X86::VPMOVUSWBZrr,    X86::VPMOVUSWBZmr,  TB_FOLDED_STORE },
427     { X86::VEXTRACTF32x4Zrr,X86::VEXTRACTF32x4Zmr, TB_FOLDED_STORE },
428     { X86::VEXTRACTF32x8Zrr,X86::VEXTRACTF32x8Zmr, TB_FOLDED_STORE },
429     { X86::VEXTRACTF64x2Zrr,X86::VEXTRACTF64x2Zmr, TB_FOLDED_STORE },
430     { X86::VEXTRACTF64x4Zrr,X86::VEXTRACTF64x4Zmr, TB_FOLDED_STORE },
431     { X86::VEXTRACTI32x4Zrr,X86::VEXTRACTI32x4Zmr, TB_FOLDED_STORE },
432     { X86::VEXTRACTI32x8Zrr,X86::VEXTRACTI32x8Zmr, TB_FOLDED_STORE },
433     { X86::VEXTRACTI64x2Zrr,X86::VEXTRACTI64x2Zmr, TB_FOLDED_STORE },
434     { X86::VEXTRACTI64x4Zrr,X86::VEXTRACTI64x4Zmr, TB_FOLDED_STORE },
435     { X86::VEXTRACTPSZrr,   X86::VEXTRACTPSZmr,    TB_FOLDED_STORE },
436 
437     // AVX-512 foldable instructions (256-bit versions)
438     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
439     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
440     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
441     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
442     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
443     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
444     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
445     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
446     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
447     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
448     { X86::VPMOVDWZ256rr,      X86::VPMOVDWZ256mr,    TB_FOLDED_STORE },
449     { X86::VPMOVQDZ256rr,      X86::VPMOVQDZ256mr,    TB_FOLDED_STORE },
450     { X86::VPMOVWBZ256rr,      X86::VPMOVWBZ256mr,    TB_FOLDED_STORE },
451     { X86::VPMOVSDWZ256rr,     X86::VPMOVSDWZ256mr,   TB_FOLDED_STORE },
452     { X86::VPMOVSQDZ256rr,     X86::VPMOVSQDZ256mr,   TB_FOLDED_STORE },
453     { X86::VPMOVSWBZ256rr,     X86::VPMOVSWBZ256mr,   TB_FOLDED_STORE },
454     { X86::VPMOVUSDWZ256rr,    X86::VPMOVUSDWZ256mr,  TB_FOLDED_STORE },
455     { X86::VPMOVUSQDZ256rr,    X86::VPMOVUSQDZ256mr,  TB_FOLDED_STORE },
456     { X86::VPMOVUSWBZ256rr,    X86::VPMOVUSWBZ256mr,  TB_FOLDED_STORE },
457     { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256mr, TB_FOLDED_STORE },
458     { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256mr, TB_FOLDED_STORE },
459     { X86::VEXTRACTI32x4Z256rr,X86::VEXTRACTI32x4Z256mr, TB_FOLDED_STORE },
460     { X86::VEXTRACTI64x2Z256rr,X86::VEXTRACTI64x2Z256mr, TB_FOLDED_STORE },
461 
462     // AVX-512 foldable instructions (128-bit versions)
463     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
464     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
465     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
466     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
467     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
468     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
469     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
470     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
471     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
472     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
473 
474     // F16C foldable instructions
475     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
476     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
477   };
478 
479   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
480     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
481                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
482   }
483 
484   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
485     { X86::BSF16rr,         X86::BSF16rm,             0 },
486     { X86::BSF32rr,         X86::BSF32rm,             0 },
487     { X86::BSF64rr,         X86::BSF64rm,             0 },
488     { X86::BSR16rr,         X86::BSR16rm,             0 },
489     { X86::BSR32rr,         X86::BSR32rm,             0 },
490     { X86::BSR64rr,         X86::BSR64rm,             0 },
491     { X86::CMP16rr,         X86::CMP16rm,             0 },
492     { X86::CMP32rr,         X86::CMP32rm,             0 },
493     { X86::CMP64rr,         X86::CMP64rm,             0 },
494     { X86::CMP8rr,          X86::CMP8rm,              0 },
495     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
496     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
497     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
498     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
499     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
500     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
501     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
502     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
503     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
504     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
505     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
506     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
507     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
508     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
509     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
510     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
511     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
512     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
513     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
514     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
515     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
516     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
517     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          0 },
518     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
519     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
520     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
521     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
522     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          0 },
523     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
524     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
525     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
526     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
527     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
528     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
529     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
530     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
531     { X86::MOV16rr,         X86::MOV16rm,             0 },
532     { X86::MOV32rr,         X86::MOV32rm,             0 },
533     { X86::MOV64rr,         X86::MOV64rm,             0 },
534     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
535     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
536     { X86::MOV8rr,          X86::MOV8rm,              0 },
537     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
538     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
539     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
540     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
541     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
542     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
543     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
544     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
545     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
546     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
547     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
548     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
549     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
550     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
551     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
552     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
553     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
554     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
555     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
556     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
557     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
558     { X86::PABSBrr,         X86::PABSBrm,             TB_ALIGN_16 },
559     { X86::PABSDrr,         X86::PABSDrm,             TB_ALIGN_16 },
560     { X86::PABSWrr,         X86::PABSWrm,             TB_ALIGN_16 },
561     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
562     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
563     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
564     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
565     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
566     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
567     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
568     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
569     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
570     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
571     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
572     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
573     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
574     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
575     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
576     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
577     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
578     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
579     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
580     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
581     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
582     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
583     { X86::RCPSSr,          X86::RCPSSm,              0 },
584     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          0 },
585     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
586     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
587     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
588     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
589     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
590     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
591     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
592     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
593     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
594     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
595     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
596     { X86::TEST16rr,        X86::TEST16rm,            0 },
597     { X86::TEST32rr,        X86::TEST32rm,            0 },
598     { X86::TEST64rr,        X86::TEST64rm,            0 },
599     { X86::TEST8rr,         X86::TEST8rm,             0 },
600     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
601     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
602     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
603 
604     // MMX version of foldable instructions
605     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
606     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
607     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
608     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
609     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
610     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
611     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
612     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
613     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
614     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
615 
616     // 3DNow! version of foldable instructions
617     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
618     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
619     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
620     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
621     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
622     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
623     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
624 
625     // AVX 128-bit versions of foldable instructions
626     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
627     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
628     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
629     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
630     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
631     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
632     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
633     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
634     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
635     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
636     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
637     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
638     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
639     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
640     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
641     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
642     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
643     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
644     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQrm,         0 },
645     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSrm,         0 },
646     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
647     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
648     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQrm,        0 },
649     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
650     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
651     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
652     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
653     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
654     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
655     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
656     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
657     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
658     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
659     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
660     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
661     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
662     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
663     { X86::VPABSBrr,        X86::VPABSBrm,            0 },
664     { X86::VPABSDrr,        X86::VPABSDrm,            0 },
665     { X86::VPABSWrr,        X86::VPABSWrm,            0 },
666     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
667     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
668     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
669     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
670     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
671     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
672     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
673     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
674     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
675     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
676     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
677     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
678     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
679     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
680     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
681     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
682     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
683     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
684     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
685     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
686     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
687     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
688     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
689     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
690     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
691     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
692     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
693     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
694     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
695     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
696     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
697     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
698     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
699 
700     // AVX 256-bit foldable instructions
701     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
702     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
703     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
704     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
705     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
706     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
707     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
708     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
709     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
710     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
711     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
712     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
713     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
714     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
715     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
716     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
717     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
718     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
719     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
720     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
721     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
722     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
723     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
724     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
725     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
726     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
727     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
728 
729     // AVX2 foldable instructions
730 
731     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
732     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
733     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
734     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
735     // so they don't need an equivalent limitation.
736     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
737     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
738     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
739     { X86::VPABSBYrr,       X86::VPABSBYrm,           0 },
740     { X86::VPABSDYrr,       X86::VPABSDYrm,           0 },
741     { X86::VPABSWYrr,       X86::VPABSWYrm,           0 },
742     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      TB_NO_REVERSE },
743     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     TB_NO_REVERSE },
744     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      TB_NO_REVERSE },
745     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     TB_NO_REVERSE },
746     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      TB_NO_REVERSE },
747     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     TB_NO_REVERSE },
748     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      TB_NO_REVERSE },
749     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     TB_NO_REVERSE },
750     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
751     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
752     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        0 },
753     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        0 },
754     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
755     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
756     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
757     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        0 },
758     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        0 },
759     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        0 },
760     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
761     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
762     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
763     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        0 },
764     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
765     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
766     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
767 
768     // XOP foldable instructions
769     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
770     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
771     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
772     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
773     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
774     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
775     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
776     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
777     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
778     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
779     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
780     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
781     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
782     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
783     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
784     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
785     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
786     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
787     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
788     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
789     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
790     { X86::VPROTBri,           X86::VPROTBmi,         0 },
791     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
792     { X86::VPROTDri,           X86::VPROTDmi,         0 },
793     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
794     { X86::VPROTQri,           X86::VPROTQmi,         0 },
795     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
796     { X86::VPROTWri,           X86::VPROTWmi,         0 },
797     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
798     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
799     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
800     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
801     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
802     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
803     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
804     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
805     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
806 
807     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
808     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
809     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
810     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
811     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
812     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
813     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
814     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
815     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
816     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
817     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
818     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
819     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
820     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
821     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
822     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
823     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
824     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
825     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
826     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
827     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
828     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
829     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
830     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
831     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
832     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
833     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
834     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
835     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
836     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
837     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
838     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
839     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
840     { X86::RORX32ri,        X86::RORX32mi,            0 },
841     { X86::RORX64ri,        X86::RORX64mi,            0 },
842     { X86::SARX32rr,        X86::SARX32rm,            0 },
843     { X86::SARX64rr,        X86::SARX64rm,            0 },
844     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
845     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
846     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
847     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
848     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
849     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
850     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
851     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
852     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
853     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
854     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
855 
856     // AVX-512 foldable instructions
857     { X86::VMOV64toPQIZrr,   X86::VMOVQI2PQIZrm,      0 },
858     { X86::VMOVDI2SSZrr,     X86::VMOVDI2SSZrm,       0 },
859     { X86::VMOVAPDZrr,       X86::VMOVAPDZrm,         TB_ALIGN_64 },
860     { X86::VMOVAPSZrr,       X86::VMOVAPSZrm,         TB_ALIGN_64 },
861     { X86::VMOVDQA32Zrr,     X86::VMOVDQA32Zrm,       TB_ALIGN_64 },
862     { X86::VMOVDQA64Zrr,     X86::VMOVDQA64Zrm,       TB_ALIGN_64 },
863     { X86::VMOVDQU8Zrr,      X86::VMOVDQU8Zrm,        0 },
864     { X86::VMOVDQU16Zrr,     X86::VMOVDQU16Zrm,       0 },
865     { X86::VMOVDQU32Zrr,     X86::VMOVDQU32Zrm,       0 },
866     { X86::VMOVDQU64Zrr,     X86::VMOVDQU64Zrm,       0 },
867     { X86::VMOVUPDZrr,       X86::VMOVUPDZrm,         0 },
868     { X86::VMOVUPSZrr,       X86::VMOVUPSZrm,         0 },
869     { X86::VPABSDZrr,        X86::VPABSDZrm,          0 },
870     { X86::VPABSQZrr,        X86::VPABSQZrm,          0 },
871     { X86::VBROADCASTSSZr,   X86::VBROADCASTSSZm,     TB_NO_REVERSE },
872     { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm,     TB_NO_REVERSE },
873     { X86::VBROADCASTSDZr,   X86::VBROADCASTSDZm,     TB_NO_REVERSE },
874     { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm,     TB_NO_REVERSE },
875 
876     // AVX-512 foldable instructions (256-bit versions)
877     { X86::VMOVAPDZ256rr,        X86::VMOVAPDZ256rm,        TB_ALIGN_32 },
878     { X86::VMOVAPSZ256rr,        X86::VMOVAPSZ256rm,        TB_ALIGN_32 },
879     { X86::VMOVDQA32Z256rr,      X86::VMOVDQA32Z256rm,      TB_ALIGN_32 },
880     { X86::VMOVDQA64Z256rr,      X86::VMOVDQA64Z256rm,      TB_ALIGN_32 },
881     { X86::VMOVDQU8Z256rr,       X86::VMOVDQU8Z256rm,       0 },
882     { X86::VMOVDQU16Z256rr,      X86::VMOVDQU16Z256rm,      0 },
883     { X86::VMOVDQU32Z256rr,      X86::VMOVDQU32Z256rm,      0 },
884     { X86::VMOVDQU64Z256rr,      X86::VMOVDQU64Z256rm,      0 },
885     { X86::VMOVUPDZ256rr,        X86::VMOVUPDZ256rm,        0 },
886     { X86::VMOVUPSZ256rr,        X86::VMOVUPSZ256rm,        0 },
887     { X86::VBROADCASTSSZ256r,    X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
888     { X86::VBROADCASTSSZ256r_s,  X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
889     { X86::VBROADCASTSDZ256r,    X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
890     { X86::VBROADCASTSDZ256r_s,  X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
891 
892     // AVX-512 foldable instructions (128-bit versions)
893     { X86::VMOVAPDZ128rr,        X86::VMOVAPDZ128rm,        TB_ALIGN_16 },
894     { X86::VMOVAPSZ128rr,        X86::VMOVAPSZ128rm,        TB_ALIGN_16 },
895     { X86::VMOVDQA32Z128rr,      X86::VMOVDQA32Z128rm,      TB_ALIGN_16 },
896     { X86::VMOVDQA64Z128rr,      X86::VMOVDQA64Z128rm,      TB_ALIGN_16 },
897     { X86::VMOVDQU8Z128rr,       X86::VMOVDQU8Z128rm,       0 },
898     { X86::VMOVDQU16Z128rr,      X86::VMOVDQU16Z128rm,      0 },
899     { X86::VMOVDQU32Z128rr,      X86::VMOVDQU32Z128rm,      0 },
900     { X86::VMOVDQU64Z128rr,      X86::VMOVDQU64Z128rm,      0 },
901     { X86::VMOVUPDZ128rr,        X86::VMOVUPDZ128rm,        0 },
902     { X86::VMOVUPSZ128rr,        X86::VMOVUPSZ128rm,        0 },
903     { X86::VBROADCASTSSZ128r,    X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
904     { X86::VBROADCASTSSZ128r_s,  X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
905     // F16C foldable instructions
906     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
907     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
908 
909     // AES foldable instructions
910     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
911     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
912     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
913     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
914   };
915 
916   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
917     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
918                   Entry.RegOp, Entry.MemOp,
919                   // Index 1, folded load
920                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
921   }
922 
923   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
924     { X86::ADC32rr,         X86::ADC32rm,       0 },
925     { X86::ADC64rr,         X86::ADC64rm,       0 },
926     { X86::ADD16rr,         X86::ADD16rm,       0 },
927     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
928     { X86::ADD32rr,         X86::ADD32rm,       0 },
929     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
930     { X86::ADD64rr,         X86::ADD64rm,       0 },
931     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
932     { X86::ADD8rr,          X86::ADD8rm,        0 },
933     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
934     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
935     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
936     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
937     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
938     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
939     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
940     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
941     { X86::AND16rr,         X86::AND16rm,       0 },
942     { X86::AND32rr,         X86::AND32rm,       0 },
943     { X86::AND64rr,         X86::AND64rm,       0 },
944     { X86::AND8rr,          X86::AND8rm,        0 },
945     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
946     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
947     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
948     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
949     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
950     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
951     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
952     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
953     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
954     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
955     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
956     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
957     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
958     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
959     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
960     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
961     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
962     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
963     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
964     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
965     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
966     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
967     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
968     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
969     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
970     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
971     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
972     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
973     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
974     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
975     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
976     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
977     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
978     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
979     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
980     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
981     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
982     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
983     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
984     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
985     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
986     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
987     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
988     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
989     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
990     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
991     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
992     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
993     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
994     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
995     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
996     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
997     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
998     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
999     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
1000     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
1001     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
1002     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
1003     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
1004     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
1005     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
1006     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
1007     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
1008     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
1009     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
1010     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
1011     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
1012     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
1013     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
1014     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
1015     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
1016     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
1017     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
1018     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
1019     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
1020     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
1021     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
1022     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
1023     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
1024     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
1025     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
1026     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
1027     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
1028     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
1029     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
1030     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
1031     { X86::MAXCPDrr,        X86::MAXCPDrm,      TB_ALIGN_16 },
1032     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
1033     { X86::MAXCPSrr,        X86::MAXCPSrm,      TB_ALIGN_16 },
1034     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
1035     { X86::MAXCSDrr,        X86::MAXCSDrm,      0 },
1036     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
1037     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
1038     { X86::MAXCSSrr,        X86::MAXCSSrm,      0 },
1039     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
1040     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
1041     { X86::MINCPDrr,        X86::MINCPDrm,      TB_ALIGN_16 },
1042     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
1043     { X86::MINCPSrr,        X86::MINCPSrm,      TB_ALIGN_16 },
1044     { X86::MINSDrr,         X86::MINSDrm,       0 },
1045     { X86::MINCSDrr,        X86::MINCSDrm,      0 },
1046     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
1047     { X86::MINSSrr,         X86::MINSSrm,       0 },
1048     { X86::MINCSSrr,        X86::MINCSSrm,      0 },
1049     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
1050     { X86::MOVLHPSrr,       X86::MOVHPSrm,      TB_NO_REVERSE },
1051     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1052     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1053     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1054     { X86::MULSDrr,         X86::MULSDrm,       0 },
1055     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
1056     { X86::MULSSrr,         X86::MULSSrm,       0 },
1057     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
1058     { X86::OR16rr,          X86::OR16rm,        0 },
1059     { X86::OR32rr,          X86::OR32rm,        0 },
1060     { X86::OR64rr,          X86::OR64rm,        0 },
1061     { X86::OR8rr,           X86::OR8rm,         0 },
1062     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1063     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1064     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1065     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1066     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1067     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1068     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1069     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1070     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1071     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1072     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1073     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1074     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1075     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1076     { X86::PALIGNRrri,      X86::PALIGNRrmi,    TB_ALIGN_16 },
1077     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1078     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1079     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1080     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1081     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1082     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1083     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1084     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1085     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1086     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1087     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1088     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1089     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1090     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1091     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1092     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1093     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1094     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1095     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1096     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1097     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1098     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1099     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1100     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1101     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1102     { X86::PMADDUBSWrr,     X86::PMADDUBSWrm,   TB_ALIGN_16 },
1103     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1104     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1105     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1106     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1107     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1108     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1109     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1110     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1111     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1112     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1113     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1114     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1115     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1116     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1117     { X86::PMULHRSWrr,      X86::PMULHRSWrm,    TB_ALIGN_16 },
1118     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1119     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1120     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1121     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1122     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1123     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1124     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1125     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1126     { X86::PSIGNBrr128,     X86::PSIGNBrm128,   TB_ALIGN_16 },
1127     { X86::PSIGNWrr128,     X86::PSIGNWrm128,   TB_ALIGN_16 },
1128     { X86::PSIGNDrr128,     X86::PSIGNDrm128,   TB_ALIGN_16 },
1129     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1130     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1131     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1132     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1133     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1134     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1135     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1136     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1137     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1138     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1139     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1140     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1141     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1142     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1143     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1144     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1145     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1146     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1147     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1148     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1149     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1150     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1151     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1152     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1153     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1154     { X86::ROUNDSDr,        X86::ROUNDSDm,      0 },
1155     { X86::ROUNDSSr,        X86::ROUNDSSm,      0 },
1156     { X86::ROUNDSDr_Int,    X86::ROUNDSDm_Int,  0 },
1157     { X86::ROUNDSSr_Int,    X86::ROUNDSSm_Int,  0 },
1158     { X86::SBB32rr,         X86::SBB32rm,       0 },
1159     { X86::SBB64rr,         X86::SBB64rm,       0 },
1160     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1161     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1162     { X86::SUB16rr,         X86::SUB16rm,       0 },
1163     { X86::SUB32rr,         X86::SUB32rm,       0 },
1164     { X86::SUB64rr,         X86::SUB64rm,       0 },
1165     { X86::SUB8rr,          X86::SUB8rm,        0 },
1166     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1167     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1168     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1169     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1170     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1171     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1172     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1173     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1174     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1175     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1176     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1177     { X86::XOR16rr,         X86::XOR16rm,       0 },
1178     { X86::XOR32rr,         X86::XOR32rm,       0 },
1179     { X86::XOR64rr,         X86::XOR64rm,       0 },
1180     { X86::XOR8rr,          X86::XOR8rm,        0 },
1181     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1182     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1183 
1184     // MMX version of foldable instructions
1185     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1186     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1187     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1188     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1189     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1190     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1191     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1192     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1193     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1194     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1195     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1196     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1197     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1198     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1199     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1200     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1201     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1202     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1203     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1204     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1205     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1206     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1207     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1208     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1209     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1210     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1211     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1212     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1213     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1214     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1215     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1216     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1217     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1218     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1219     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1220     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1221     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1222     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1223     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1224     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1225     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1226     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1227     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1228     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1229     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1230     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1231     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1232     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1233     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1234     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1235     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1236     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1237     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1238     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1239     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1240     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1241     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1242     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1243     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1244     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1245     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1246     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1247     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1248     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1249     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1250     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1251     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1252     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1253     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1254     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1255 
1256     // 3DNow! version of foldable instructions
1257     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1258     { X86::PFACCrr,           X86::PFACCrm,           0 },
1259     { X86::PFADDrr,           X86::PFADDrm,           0 },
1260     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1261     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1262     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1263     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1264     { X86::PFMINrr,           X86::PFMINrm,           0 },
1265     { X86::PFMULrr,           X86::PFMULrm,           0 },
1266     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1267     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1268     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1269     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1270     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1271     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1272     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1273     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1274 
1275     // AVX 128-bit versions of foldable instructions
1276     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1277     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1278     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1279     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1280     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1281     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1282     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1283     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1284     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1285     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1286     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1287     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1288     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1289     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        0 },
1290     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1291     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      0 },
1292     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1293     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       0 },
1294     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1295     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       0 },
1296     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1297     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1298     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1299     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1300     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1301     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1302     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1303     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1304     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1305     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1306     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1307     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1308     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1309     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1310     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1311     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1312     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1313     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1314     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1315     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1316     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1317     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1318     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1319     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1320     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1321     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1322     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1323     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1324     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1325     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1326     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1327     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1328     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1329     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1330     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1331     { X86::VMAXCPDrr,         X86::VMAXCPDrm,          0 },
1332     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1333     { X86::VMAXCPSrr,         X86::VMAXCPSrm,          0 },
1334     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1335     { X86::VMAXCSDrr,         X86::VMAXCSDrm,          0 },
1336     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1337     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1338     { X86::VMAXCSSrr,         X86::VMAXCSSrm,          0 },
1339     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1340     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1341     { X86::VMINCPDrr,         X86::VMINCPDrm,          0 },
1342     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1343     { X86::VMINCPSrr,         X86::VMINCPSrm,          0 },
1344     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1345     { X86::VMINCSDrr,         X86::VMINCSDrm,          0 },
1346     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1347     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1348     { X86::VMINCSSrr,         X86::VMINCSSrm,          0 },
1349     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1350     { X86::VMOVLHPSrr,        X86::VMOVHPSrm,          TB_NO_REVERSE },
1351     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1352     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1353     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1354     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1355     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1356     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1357     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1358     { X86::VORPDrr,           X86::VORPDrm,            0 },
1359     { X86::VORPSrr,           X86::VORPSrm,            0 },
1360     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1361     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1362     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1363     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1364     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1365     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1366     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1367     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1368     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1369     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1370     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1371     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1372     { X86::VPALIGNRrri,       X86::VPALIGNRrmi,        0 },
1373     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1374     { X86::VPANDrr,           X86::VPANDrm,            0 },
1375     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1376     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1377     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1378     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1379     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1380     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1381     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1382     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1383     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1384     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1385     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1386     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1387     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1388     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1389     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1390     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1391     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1392     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1393     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1394     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1395     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1396     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1397     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1398     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1399     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1400     { X86::VPMADDUBSWrr,      X86::VPMADDUBSWrm,       0 },
1401     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1402     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1403     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1404     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1405     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1406     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1407     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1408     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1409     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1410     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1411     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1412     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1413     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1414     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1415     { X86::VPMULHRSWrr,       X86::VPMULHRSWrm,        0 },
1416     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1417     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1418     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1419     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1420     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1421     { X86::VPORrr,            X86::VPORrm,             0 },
1422     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1423     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1424     { X86::VPSIGNBrr128,      X86::VPSIGNBrm128,       0 },
1425     { X86::VPSIGNWrr128,      X86::VPSIGNWrm128,       0 },
1426     { X86::VPSIGNDrr128,      X86::VPSIGNDrm128,       0 },
1427     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1428     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1429     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1430     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1431     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1432     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1433     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1434     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1435     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1436     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1437     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1438     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1439     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1440     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1441     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1442     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1443     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1444     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1445     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1446     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1447     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1448     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1449     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1450     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1451     { X86::VPXORrr,           X86::VPXORrm,            0 },
1452     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1453     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1454     { X86::VROUNDSDr_Int,     X86::VROUNDSDm_Int,      0 },
1455     { X86::VROUNDSSr_Int,     X86::VROUNDSSm_Int,      0 },
1456     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1457     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1458     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1459     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1460     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1461     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1462     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1463     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1464     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1465     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1466     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1467     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1468     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1469     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1470 
1471     // AVX 256-bit foldable instructions
1472     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1473     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1474     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1475     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1476     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1477     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1478     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1479     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1480     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1481     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1482     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1483     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1484     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1485     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1486     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1487     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1488     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1489     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1490     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1491     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1492     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1493     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1494     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1495     { X86::VMAXCPDYrr,        X86::VMAXCPDYrm,         0 },
1496     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1497     { X86::VMAXCPSYrr,        X86::VMAXCPSYrm,         0 },
1498     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1499     { X86::VMINCPDYrr,        X86::VMINCPDYrm,         0 },
1500     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1501     { X86::VMINCPSYrr,        X86::VMINCPSYrm,         0 },
1502     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1503     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1504     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1505     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1506     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1507     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1508     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1509     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1510     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1511     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1512     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1513     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1514     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1515     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1516     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1517     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1518     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1519 
1520     // AVX2 foldable instructions
1521     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1522     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1523     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1524     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1525     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1526     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1527     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1528     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1529     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1530     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1531     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1532     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1533     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1534     { X86::VPALIGNRYrri,      X86::VPALIGNRYrmi,       0 },
1535     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1536     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1537     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1538     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1539     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1540     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1541     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1542     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1543     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1544     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1545     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1546     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1547     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1548     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1549     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1550     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1551     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1552     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1553     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1554     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1555     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1556     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1557     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1558     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1559     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1560     { X86::VPMADDUBSWYrr,     X86::VPMADDUBSWYrm,      0 },
1561     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1562     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1563     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1564     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1565     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1566     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1567     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1568     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1569     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1570     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1571     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1572     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1573     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1574     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1575     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1576     { X86::VPMULHRSWYrr,      X86::VPMULHRSWYrm,       0 },
1577     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1578     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1579     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1580     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1581     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1582     { X86::VPORYrr,           X86::VPORYrm,            0 },
1583     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1584     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1585     { X86::VPSIGNBYrr256,     X86::VPSIGNBYrm256,      0 },
1586     { X86::VPSIGNWYrr256,     X86::VPSIGNWYrm256,      0 },
1587     { X86::VPSIGNDYrr256,     X86::VPSIGNDYrm256,      0 },
1588     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1589     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1590     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1591     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1592     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1593     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1594     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1595     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1596     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1597     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1598     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1599     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1600     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1601     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1602     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1603     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1604     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1605     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1606     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1607     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1608     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1609     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1610     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1611     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1612     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1613     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1614     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1615     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1616     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1617     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1618     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1619     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1620     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1621     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1622     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1623 
1624     // FMA4 foldable patterns
1625     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1626     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1627     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1628     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1629     { X86::VFMADDPS4Yrr,      X86::VFMADDPS4Ymr,       TB_ALIGN_NONE },
1630     { X86::VFMADDPD4Yrr,      X86::VFMADDPD4Ymr,       TB_ALIGN_NONE },
1631     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1632     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1633     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1634     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1635     { X86::VFNMADDPS4Yrr,     X86::VFNMADDPS4Ymr,      TB_ALIGN_NONE },
1636     { X86::VFNMADDPD4Yrr,     X86::VFNMADDPD4Ymr,      TB_ALIGN_NONE },
1637     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1638     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1639     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1640     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1641     { X86::VFMSUBPS4Yrr,      X86::VFMSUBPS4Ymr,       TB_ALIGN_NONE },
1642     { X86::VFMSUBPD4Yrr,      X86::VFMSUBPD4Ymr,       TB_ALIGN_NONE },
1643     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1644     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1645     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1646     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1647     { X86::VFNMSUBPS4Yrr,     X86::VFNMSUBPS4Ymr,      TB_ALIGN_NONE },
1648     { X86::VFNMSUBPD4Yrr,     X86::VFNMSUBPD4Ymr,      TB_ALIGN_NONE },
1649     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1650     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1651     { X86::VFMADDSUBPS4Yrr,   X86::VFMADDSUBPS4Ymr,    TB_ALIGN_NONE },
1652     { X86::VFMADDSUBPD4Yrr,   X86::VFMADDSUBPD4Ymr,    TB_ALIGN_NONE },
1653     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1654     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1655     { X86::VFMSUBADDPS4Yrr,   X86::VFMSUBADDPS4Ymr,    TB_ALIGN_NONE },
1656     { X86::VFMSUBADDPD4Yrr,   X86::VFMSUBADDPD4Ymr,    TB_ALIGN_NONE },
1657 
1658     // XOP foldable instructions
1659     { X86::VPCMOVrrr,         X86::VPCMOVrmr,           0 },
1660     { X86::VPCMOVrrrY,        X86::VPCMOVrmrY,          0 },
1661     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1662     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1663     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1664     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1665     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1666     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1667     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1668     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1669     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1670     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1671     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1672     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1673     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1674     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1675     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1676     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1677     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1678     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1679     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1680     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1681     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1682     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1683     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1684     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1685     { X86::VPPERMrrr,         X86::VPPERMrmr,           0 },
1686     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1687     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1688     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1689     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1690     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1691     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1692     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1693     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1694     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1695     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1696     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1697     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1698 
1699     // BMI/BMI2 foldable instructions
1700     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1701     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1702     { X86::MULX32rr,          X86::MULX32rm,            0 },
1703     { X86::MULX64rr,          X86::MULX64rm,            0 },
1704     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1705     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1706     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1707     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1708 
1709     // ADX foldable instructions
1710     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1711     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1712     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1713     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1714 
1715     // AVX-512 foldable instructions
1716     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1717     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1718     { X86::VADDSSZrr,         X86::VADDSSZrm,           0 },
1719     { X86::VADDSSZrr_Int,     X86::VADDSSZrm_Int,       0 },
1720     { X86::VADDSDZrr,         X86::VADDSDZrm,           0 },
1721     { X86::VADDSDZrr_Int,     X86::VADDSDZrm_Int,       0 },
1722     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1723     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1724     { X86::VSUBSSZrr,         X86::VSUBSSZrm,           0 },
1725     { X86::VSUBSSZrr_Int,     X86::VSUBSSZrm_Int,       0 },
1726     { X86::VSUBSDZrr,         X86::VSUBSDZrm,           0 },
1727     { X86::VSUBSDZrr_Int,     X86::VSUBSDZrm_Int,       0 },
1728     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1729     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1730     { X86::VMULSSZrr,         X86::VMULSSZrm,           0 },
1731     { X86::VMULSSZrr_Int,     X86::VMULSSZrm_Int,       0 },
1732     { X86::VMULSDZrr,         X86::VMULSDZrm,           0 },
1733     { X86::VMULSDZrr_Int,     X86::VMULSDZrm_Int,       0 },
1734     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1735     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1736     { X86::VDIVSSZrr,         X86::VDIVSSZrm,           0 },
1737     { X86::VDIVSSZrr_Int,     X86::VDIVSSZrm_Int,       0 },
1738     { X86::VDIVSDZrr,         X86::VDIVSDZrm,           0 },
1739     { X86::VDIVSDZrr_Int,     X86::VDIVSDZrm_Int,       0 },
1740     { X86::VCMPPDZrri,        X86::VCMPPDZrmi,          0 },
1741     { X86::VCMPPSZrri,        X86::VCMPPSZrmi,          0 },
1742     { X86::VCMPSDZrr,         X86::VCMPSDZrm,           0 },
1743     { X86::VCMPSSZrr,         X86::VCMPSSZrm,           0 },
1744     { X86::VCMPSDZrr_Int,     X86::VCMPSDZrm_Int,       0 },
1745     { X86::VCMPSSZrr_Int,     X86::VCMPSSZrm_Int,       0 },
1746     { X86::VANDPDZrr,         X86::VANDPDZrm,           0 },
1747     { X86::VANDPSZrr,         X86::VANDPSZrm,           0 },
1748     { X86::VANDNPDZrr,        X86::VANDNPDZrm,          0 },
1749     { X86::VANDNPSZrr,        X86::VANDNPSZrm,          0 },
1750     { X86::VORPDZrr,          X86::VORPDZrm,            0 },
1751     { X86::VORPSZrr,          X86::VORPSZrm,            0 },
1752     { X86::VXORPDZrr,         X86::VXORPDZrm,           0 },
1753     { X86::VXORPSZrr,         X86::VXORPSZrm,           0 },
1754     { X86::VPANDDZrr,         X86::VPANDDZrm,           0 },
1755     { X86::VPANDQZrr,         X86::VPANDQZrm,           0 },
1756     { X86::VPANDNDZrr,        X86::VPANDNDZrm,          0 },
1757     { X86::VPANDNQZrr,        X86::VPANDNQZrm,          0 },
1758     { X86::VPORDZrr,          X86::VPORDZrm,            0 },
1759     { X86::VPORQZrr,          X86::VPORQZrm,            0 },
1760     { X86::VPXORDZrr,         X86::VPXORDZrm,           0 },
1761     { X86::VPXORQZrr,         X86::VPXORQZrm,           0 },
1762     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1763     { X86::VMAXCPDZrr,        X86::VMAXCPDZrm,          0 },
1764     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1765     { X86::VMAXCPSZrr,        X86::VMAXCPSZrm,          0 },
1766     { X86::VMAXSDZrr,         X86::VMAXSDZrm,           0 },
1767     { X86::VMAXCSDZrr,        X86::VMAXCSDZrm,          0 },
1768     { X86::VMAXSDZrr_Int,     X86::VMAXSDZrm_Int,       0 },
1769     { X86::VMAXSSZrr,         X86::VMAXSSZrm,           0 },
1770     { X86::VMAXCSSZrr,        X86::VMAXCSSZrm,          0 },
1771     { X86::VMAXSSZrr_Int,     X86::VMAXSSZrm_Int,       0 },
1772     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1773     { X86::VMINCPDZrr,        X86::VMINCPDZrm,          0 },
1774     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1775     { X86::VMINCPSZrr,        X86::VMINCPSZrm,          0 },
1776     { X86::VMINSDZrr,         X86::VMINSDZrm,           0 },
1777     { X86::VMINCSDZrr,        X86::VMINCSDZrm,          0 },
1778     { X86::VMINSDZrr_Int,     X86::VMINSDZrm_Int,       0 },
1779     { X86::VMINSSZrr,         X86::VMINSSZrm,           0 },
1780     { X86::VMINCSSZrr,        X86::VMINCSSZrm,          0 },
1781     { X86::VMINSSZrr_Int,     X86::VMINSSZrm_Int,       0 },
1782     { X86::VPADDBZrr,         X86::VPADDBZrm,           0 },
1783     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1784     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1785     { X86::VPADDSBZrr,        X86::VPADDSBZrm,          0 },
1786     { X86::VPADDSWZrr,        X86::VPADDSWZrm,          0 },
1787     { X86::VPADDUSBZrr,       X86::VPADDUSBZrm,         0 },
1788     { X86::VPADDUSWZrr,       X86::VPADDUSWZrm,         0 },
1789     { X86::VPADDWZrr,         X86::VPADDWZrm,           0 },
1790     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1791     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1792     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1793     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1794     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1795     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1796     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1797     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1798     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1799     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1800     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1801     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1802     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1803     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1804     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1805     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1806     { X86::VPSUBBZrr,         X86::VPSUBBZrm,           0 },
1807     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1808     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1809     { X86::VPSUBSBZrr,        X86::VPSUBSBZrm,          0 },
1810     { X86::VPSUBSWZrr,        X86::VPSUBSWZrm,          0 },
1811     { X86::VPSUBUSBZrr,       X86::VPSUBUSBZrm,         0 },
1812     { X86::VPSUBUSWZrr,       X86::VPSUBUSWZrm,         0 },
1813     { X86::VPSUBWZrr,         X86::VPSUBWZrm,           0 },
1814     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1815     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1816     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1817     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1818     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1819     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1820     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1821     { X86::VPCMPEQBZrr,       X86::VPCMPEQBZrm,         0 },
1822     { X86::VPCMPEQDZrr,       X86::VPCMPEQDZrm,         0 },
1823     { X86::VPCMPEQQZrr,       X86::VPCMPEQQZrm,         0 },
1824     { X86::VPCMPEQWZrr,       X86::VPCMPEQWZrm,         0 },
1825     { X86::VPCMPGTBZrr,       X86::VPCMPGTBZrm,         0 },
1826     { X86::VPCMPGTDZrr,       X86::VPCMPGTDZrm,         0 },
1827     { X86::VPCMPGTQZrr,       X86::VPCMPGTQZrm,         0 },
1828     { X86::VPCMPGTWZrr,       X86::VPCMPGTWZrm,         0 },
1829     { X86::VPCMPBZrri,        X86::VPCMPBZrmi,          0 },
1830     { X86::VPCMPDZrri,        X86::VPCMPDZrmi,          0 },
1831     { X86::VPCMPQZrri,        X86::VPCMPQZrmi,          0 },
1832     { X86::VPCMPWZrri,        X86::VPCMPWZrmi,          0 },
1833     { X86::VPCMPUBZrri,       X86::VPCMPUBZrmi,         0 },
1834     { X86::VPCMPUDZrri,       X86::VPCMPUDZrmi,         0 },
1835     { X86::VPCMPUQZrri,       X86::VPCMPUQZrmi,         0 },
1836     { X86::VPCMPUWZrri,       X86::VPCMPUWZrmi,         0 },
1837     { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrm,     0 },
1838     { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrm,     0 },
1839     { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrm,     0 },
1840     { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrm,     0 },
1841     { X86::VINSERTI32x4Zrr,   X86::VINSERTI32x4Zrm,     0 },
1842     { X86::VINSERTI32x8Zrr,   X86::VINSERTI32x8Zrm,     0 },
1843     { X86::VINSERTI64x2Zrr,   X86::VINSERTI64x2Zrm,     0 },
1844     { X86::VINSERTI64x4Zrr,   X86::VINSERTI64x4Zrm,     0 },
1845 
1846     // AVX-512{F,VL} foldable instructions
1847     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1848     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1849     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1850 
1851     // AVX-512{F,VL} foldable instructions
1852     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1853     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1854     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1855     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1856     { X86::VANDPDZ128rr,      X86::VANDPDZ128rm,        0 },
1857     { X86::VANDPDZ256rr,      X86::VANDPDZ256rm,        0 },
1858     { X86::VANDPSZ128rr,      X86::VANDPSZ128rm,        0 },
1859     { X86::VANDPSZ256rr,      X86::VANDPSZ256rm,        0 },
1860     { X86::VANDNPDZ128rr,     X86::VANDNPDZ128rm,       0 },
1861     { X86::VANDNPDZ256rr,     X86::VANDNPDZ256rm,       0 },
1862     { X86::VANDNPSZ128rr,     X86::VANDNPSZ128rm,       0 },
1863     { X86::VANDNPSZ256rr,     X86::VANDNPSZ256rm,       0 },
1864     { X86::VORPDZ128rr,       X86::VORPDZ128rm,         0 },
1865     { X86::VORPDZ256rr,       X86::VORPDZ256rm,         0 },
1866     { X86::VORPSZ128rr,       X86::VORPSZ128rm,         0 },
1867     { X86::VORPSZ256rr,       X86::VORPSZ256rm,         0 },
1868     { X86::VPANDDZ128rr,      X86::VPANDDZ128rm,        0 },
1869     { X86::VPANDDZ256rr,      X86::VPANDDZ256rm,        0 },
1870     { X86::VPANDQZ128rr,      X86::VPANDQZ128rm,        0 },
1871     { X86::VPANDQZ256rr,      X86::VPANDQZ256rm,        0 },
1872     { X86::VPANDNDZ128rr,     X86::VPANDNDZ128rm,       0 },
1873     { X86::VPANDNDZ256rr,     X86::VPANDNDZ256rm,       0 },
1874     { X86::VPANDNQZ128rr,     X86::VPANDNQZ128rm,       0 },
1875     { X86::VPANDNQZ256rr,     X86::VPANDNQZ256rm,       0 },
1876     { X86::VPORDZ128rr,       X86::VPORDZ128rm,         0 },
1877     { X86::VPORDZ256rr,       X86::VPORDZ256rm,         0 },
1878     { X86::VPORQZ128rr,       X86::VPORQZ128rm,         0 },
1879     { X86::VPORQZ256rr,       X86::VPORQZ256rm,         0 },
1880     { X86::VPXORDZ128rr,      X86::VPXORDZ128rm,        0 },
1881     { X86::VPXORDZ256rr,      X86::VPXORDZ256rm,        0 },
1882     { X86::VPXORQZ128rr,      X86::VPXORQZ128rm,        0 },
1883     { X86::VPXORQZ256rr,      X86::VPXORQZ256rm,        0 },
1884     { X86::VSUBPDZ128rr,      X86::VSUBPDZ128rm,        0 },
1885     { X86::VSUBPDZ256rr,      X86::VSUBPDZ256rm,        0 },
1886     { X86::VSUBPSZ128rr,      X86::VSUBPSZ128rm,        0 },
1887     { X86::VSUBPSZ256rr,      X86::VSUBPSZ256rm,        0 },
1888     { X86::VXORPDZ128rr,      X86::VXORPDZ128rm,        0 },
1889     { X86::VXORPDZ256rr,      X86::VXORPDZ256rm,        0 },
1890     { X86::VXORPSZ128rr,      X86::VXORPSZ128rm,        0 },
1891     { X86::VXORPSZ256rr,      X86::VXORPSZ256rm,        0 },
1892     { X86::VMAXPDZ128rr,      X86::VMAXPDZ128rm,        0 },
1893     { X86::VMAXPDZ256rr,      X86::VMAXPDZ256rm,        0 },
1894     { X86::VMAXCPDZ128rr,     X86::VMAXCPDZ128rm,       0 },
1895     { X86::VMAXCPDZ256rr,     X86::VMAXCPDZ256rm,       0 },
1896     { X86::VMAXPSZ128rr,      X86::VMAXPSZ128rm,        0 },
1897     { X86::VMAXPSZ256rr,      X86::VMAXPSZ256rm,        0 },
1898     { X86::VMAXCPSZ128rr,     X86::VMAXCPSZ128rm,       0 },
1899     { X86::VMAXCPSZ256rr,     X86::VMAXCPSZ256rm,       0 },
1900     { X86::VMINPDZ128rr,      X86::VMINPDZ128rm,        0 },
1901     { X86::VMINPDZ256rr,      X86::VMINPDZ256rm,        0 },
1902     { X86::VMINCPDZ128rr,     X86::VMINCPDZ128rm,       0 },
1903     { X86::VMINCPDZ256rr,     X86::VMINCPDZ256rm,       0 },
1904     { X86::VMINPSZ128rr,      X86::VMINPSZ128rm,        0 },
1905     { X86::VMINPSZ256rr,      X86::VMINPSZ256rm,        0 },
1906     { X86::VMINCPSZ128rr,     X86::VMINCPSZ128rm,       0 },
1907     { X86::VMINCPSZ256rr,     X86::VMINCPSZ256rm,       0 },
1908     { X86::VCMPPDZ128rri,     X86::VCMPPDZ128rmi,       0 },
1909     { X86::VCMPPDZ256rri,     X86::VCMPPDZ256rmi,       0 },
1910     { X86::VCMPPSZ128rri,     X86::VCMPPSZ128rmi,       0 },
1911     { X86::VCMPPSZ256rri,     X86::VCMPPSZ256rmi,       0 },
1912     { X86::VPCMPEQBZ128rr,    X86::VPCMPEQBZ128rm,      0 },
1913     { X86::VPCMPEQBZ256rr,    X86::VPCMPEQBZ256rm,      0 },
1914     { X86::VPCMPEQDZ128rr,    X86::VPCMPEQDZ128rm,      0 },
1915     { X86::VPCMPEQDZ256rr,    X86::VPCMPEQDZ256rm,      0 },
1916     { X86::VPCMPEQQZ128rr,    X86::VPCMPEQQZ128rm,      0 },
1917     { X86::VPCMPEQQZ256rr,    X86::VPCMPEQQZ256rm,      0 },
1918     { X86::VPCMPEQWZ128rr,    X86::VPCMPEQWZ128rm,      0 },
1919     { X86::VPCMPEQWZ256rr,    X86::VPCMPEQWZ256rm,      0 },
1920     { X86::VPCMPGTBZ128rr,    X86::VPCMPGTBZ128rm,      0 },
1921     { X86::VPCMPGTBZ256rr,    X86::VPCMPGTBZ256rm,      0 },
1922     { X86::VPCMPGTDZ128rr,    X86::VPCMPGTDZ128rm,      0 },
1923     { X86::VPCMPGTDZ256rr,    X86::VPCMPGTDZ256rm,      0 },
1924     { X86::VPCMPGTQZ128rr,    X86::VPCMPGTQZ128rm,      0 },
1925     { X86::VPCMPGTQZ256rr,    X86::VPCMPGTQZ256rm,      0 },
1926     { X86::VPCMPGTWZ128rr,    X86::VPCMPGTWZ128rm,      0 },
1927     { X86::VPCMPGTWZ256rr,    X86::VPCMPGTWZ256rm,      0 },
1928     { X86::VPCMPBZ128rri,     X86::VPCMPBZ128rmi,       0 },
1929     { X86::VPCMPBZ256rri,     X86::VPCMPBZ256rmi,       0 },
1930     { X86::VPCMPDZ128rri,     X86::VPCMPDZ128rmi,       0 },
1931     { X86::VPCMPDZ256rri,     X86::VPCMPDZ256rmi,       0 },
1932     { X86::VPCMPQZ128rri,     X86::VPCMPQZ128rmi,       0 },
1933     { X86::VPCMPQZ256rri,     X86::VPCMPQZ256rmi,       0 },
1934     { X86::VPCMPWZ128rri,     X86::VPCMPWZ128rmi,       0 },
1935     { X86::VPCMPWZ256rri,     X86::VPCMPWZ256rmi,       0 },
1936     { X86::VPCMPUBZ128rri,    X86::VPCMPUBZ128rmi,      0 },
1937     { X86::VPCMPUBZ256rri,    X86::VPCMPUBZ256rmi,      0 },
1938     { X86::VPCMPUDZ128rri,    X86::VPCMPUDZ128rmi,      0 },
1939     { X86::VPCMPUDZ256rri,    X86::VPCMPUDZ256rmi,      0 },
1940     { X86::VPCMPUQZ128rri,    X86::VPCMPUQZ128rmi,      0 },
1941     { X86::VPCMPUQZ256rri,    X86::VPCMPUQZ256rmi,      0 },
1942     { X86::VPCMPUWZ128rri,    X86::VPCMPUWZ128rmi,      0 },
1943     { X86::VPCMPUWZ256rri,    X86::VPCMPUWZ256rmi,      0 },
1944     { X86::VPADDBZ128rr,      X86::VPADDBZ128rm,        0 },
1945     { X86::VPADDBZ256rr,      X86::VPADDBZ256rm,        0 },
1946     { X86::VPADDDZ128rr,      X86::VPADDDZ128rm,        0 },
1947     { X86::VPADDDZ256rr,      X86::VPADDDZ256rm,        0 },
1948     { X86::VPADDQZ128rr,      X86::VPADDQZ128rm,        0 },
1949     { X86::VPADDQZ256rr,      X86::VPADDQZ256rm,        0 },
1950     { X86::VPADDSBZ128rr,     X86::VPADDSBZ128rm,       0 },
1951     { X86::VPADDSBZ256rr,     X86::VPADDSBZ256rm,       0 },
1952     { X86::VPADDSWZ128rr,     X86::VPADDSWZ128rm,       0 },
1953     { X86::VPADDSWZ256rr,     X86::VPADDSWZ256rm,       0 },
1954     { X86::VPADDUSBZ128rr,    X86::VPADDUSBZ128rm,      0 },
1955     { X86::VPADDUSBZ256rr,    X86::VPADDUSBZ256rm,      0 },
1956     { X86::VPADDUSWZ128rr,    X86::VPADDUSWZ128rm,      0 },
1957     { X86::VPADDUSWZ256rr,    X86::VPADDUSWZ256rm,      0 },
1958     { X86::VPADDWZ128rr,      X86::VPADDWZ128rm,        0 },
1959     { X86::VPADDWZ256rr,      X86::VPADDWZ256rm,        0 },
1960     { X86::VPSUBBZ128rr,      X86::VPSUBBZ128rm,        0 },
1961     { X86::VPSUBBZ256rr,      X86::VPSUBBZ256rm,        0 },
1962     { X86::VPSUBDZ128rr,      X86::VPSUBDZ128rm,        0 },
1963     { X86::VPSUBDZ256rr,      X86::VPSUBDZ256rm,        0 },
1964     { X86::VPSUBQZ128rr,      X86::VPSUBQZ128rm,        0 },
1965     { X86::VPSUBQZ256rr,      X86::VPSUBQZ256rm,        0 },
1966     { X86::VPSUBSBZ128rr,     X86::VPSUBSBZ128rm,       0 },
1967     { X86::VPSUBSBZ256rr,     X86::VPSUBSBZ256rm,       0 },
1968     { X86::VPSUBSWZ128rr,     X86::VPSUBSWZ128rm,       0 },
1969     { X86::VPSUBSWZ256rr,     X86::VPSUBSWZ256rm,       0 },
1970     { X86::VPSUBUSBZ128rr,    X86::VPSUBUSBZ128rm,      0 },
1971     { X86::VPSUBUSBZ256rr,    X86::VPSUBUSBZ256rm,      0 },
1972     { X86::VPSUBUSWZ128rr,    X86::VPSUBUSWZ128rm,      0 },
1973     { X86::VPSUBUSWZ256rr,    X86::VPSUBUSWZ256rm,      0 },
1974     { X86::VPSUBWZ128rr,      X86::VPSUBWZ128rm,        0 },
1975     { X86::VPSUBWZ256rr,      X86::VPSUBWZ256rm,        0 },
1976     { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rm,  0 },
1977     { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rm,  0 },
1978     { X86::VINSERTI32x4Z256rr,X86::VINSERTI32x4Z256rm,  0 },
1979     { X86::VINSERTI64x2Z256rr,X86::VINSERTI64x2Z256rm,  0 },
1980 
1981     // AES foldable instructions
1982     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1983     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1984     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1985     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1986     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
1987     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
1988     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
1989     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
1990 
1991     // SHA foldable instructions
1992     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1993     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1994     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1995     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1996     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1997     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1998     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
1999   };
2000 
2001   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
2002     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
2003                   Entry.RegOp, Entry.MemOp,
2004                   // Index 2, folded load
2005                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
2006   }
2007 
2008   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
2009     // FMA4 foldable patterns
2010     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
2011     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
2012     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
2013     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
2014     { X86::VFMADDPS4Yrr,          X86::VFMADDPS4Yrm,          TB_ALIGN_NONE },
2015     { X86::VFMADDPD4Yrr,          X86::VFMADDPD4Yrm,          TB_ALIGN_NONE },
2016     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
2017     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
2018     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
2019     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
2020     { X86::VFNMADDPS4Yrr,         X86::VFNMADDPS4Yrm,         TB_ALIGN_NONE },
2021     { X86::VFNMADDPD4Yrr,         X86::VFNMADDPD4Yrm,         TB_ALIGN_NONE },
2022     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
2023     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
2024     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
2025     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
2026     { X86::VFMSUBPS4Yrr,          X86::VFMSUBPS4Yrm,          TB_ALIGN_NONE },
2027     { X86::VFMSUBPD4Yrr,          X86::VFMSUBPD4Yrm,          TB_ALIGN_NONE },
2028     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
2029     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
2030     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
2031     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
2032     { X86::VFNMSUBPS4Yrr,         X86::VFNMSUBPS4Yrm,         TB_ALIGN_NONE },
2033     { X86::VFNMSUBPD4Yrr,         X86::VFNMSUBPD4Yrm,         TB_ALIGN_NONE },
2034     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
2035     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
2036     { X86::VFMADDSUBPS4Yrr,       X86::VFMADDSUBPS4Yrm,       TB_ALIGN_NONE },
2037     { X86::VFMADDSUBPD4Yrr,       X86::VFMADDSUBPD4Yrm,       TB_ALIGN_NONE },
2038     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
2039     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
2040     { X86::VFMSUBADDPS4Yrr,       X86::VFMSUBADDPS4Yrm,       TB_ALIGN_NONE },
2041     { X86::VFMSUBADDPD4Yrr,       X86::VFMSUBADDPD4Yrm,       TB_ALIGN_NONE },
2042 
2043     // XOP foldable instructions
2044     { X86::VPCMOVrrr,             X86::VPCMOVrrm,             0 },
2045     { X86::VPCMOVrrrY,            X86::VPCMOVrrmY,            0 },
2046     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
2047     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
2048     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
2049     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
2050     { X86::VPPERMrrr,             X86::VPPERMrrm,             0 },
2051 
2052     // AVX-512 VPERMI instructions with 3 source operands.
2053     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
2054     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
2055     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
2056     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
2057     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
2058     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
2059     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
2060     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
2061     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
2062     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
2063     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
2064     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
2065     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
2066      // AVX-512 arithmetic instructions
2067     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
2068     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
2069     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
2070     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
2071     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
2072     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
2073     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
2074     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
2075     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
2076     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
2077     { X86::VMINCPSZrrkz,          X86::VMINCPSZrmkz,          0 },
2078     { X86::VMINCPDZrrkz,          X86::VMINCPDZrmkz,          0 },
2079     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
2080     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
2081     { X86::VMAXCPSZrrkz,          X86::VMAXCPSZrmkz,          0 },
2082     { X86::VMAXCPDZrrkz,          X86::VMAXCPDZrmkz,          0 },
2083     { X86::VANDPDZrrkz,           X86::VANDPDZrmkz,           0 },
2084     { X86::VANDPSZrrkz,           X86::VANDPSZrmkz,           0 },
2085     { X86::VANDNPDZrrkz,          X86::VANDNPDZrmkz,          0 },
2086     { X86::VANDNPSZrrkz,          X86::VANDNPSZrmkz,          0 },
2087     { X86::VORPDZrrkz,            X86::VORPDZrmkz,            0 },
2088     { X86::VORPSZrrkz,            X86::VORPSZrmkz,            0 },
2089     { X86::VXORPDZrrkz,           X86::VXORPDZrmkz,           0 },
2090     { X86::VXORPSZrrkz,           X86::VXORPSZrmkz,           0 },
2091     { X86::VPANDDZrrkz,           X86::VPANDDZrmkz,           0 },
2092     { X86::VPANDQZrrkz,           X86::VPANDQZrmkz,           0 },
2093     { X86::VPANDNDZrrkz,          X86::VPANDNDZrmkz,          0 },
2094     { X86::VPANDNQZrrkz,          X86::VPANDNQZrmkz,          0 },
2095     { X86::VPORDZrrkz,            X86::VPORDZrmkz,            0 },
2096     { X86::VPORQZrrkz,            X86::VPORQZrmkz,            0 },
2097     { X86::VPXORDZrrkz,           X86::VPXORDZrmkz,           0 },
2098     { X86::VPXORQZrrkz,           X86::VPXORQZrmkz,           0 },
2099     { X86::VPTERNLOGDZrri,        X86::VPTERNLOGDZrmi,        0 },
2100     { X86::VPTERNLOGQZrri,        X86::VPTERNLOGQZrmi,        0 },
2101     // AVX-512{F,VL} arithmetic instructions 256-bit
2102     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
2103     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
2104     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
2105     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
2106     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
2107     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
2108     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
2109     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
2110     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
2111     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
2112     { X86::VMINCPSZ256rrkz,       X86::VMINCPSZ256rmkz,       0 },
2113     { X86::VMINCPDZ256rrkz,       X86::VMINCPDZ256rmkz,       0 },
2114     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
2115     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
2116     { X86::VMAXCPSZ256rrkz,       X86::VMAXCPSZ256rmkz,       0 },
2117     { X86::VMAXCPDZ256rrkz,       X86::VMAXCPDZ256rmkz,       0 },
2118     { X86::VANDPDZ256rrkz,        X86::VANDPDZ256rmkz,        0 },
2119     { X86::VANDPSZ256rrkz,        X86::VANDPSZ256rmkz,        0 },
2120     { X86::VANDNPDZ256rrkz,       X86::VANDNPDZ256rmkz,       0 },
2121     { X86::VANDNPSZ256rrkz,       X86::VANDNPSZ256rmkz,       0 },
2122     { X86::VORPDZ256rrkz,         X86::VORPDZ256rmkz,         0 },
2123     { X86::VORPSZ256rrkz,         X86::VORPSZ256rmkz,         0 },
2124     { X86::VXORPDZ256rrkz,        X86::VXORPDZ256rmkz,        0 },
2125     { X86::VXORPSZ256rrkz,        X86::VXORPSZ256rmkz,        0 },
2126     { X86::VPANDDZ256rrkz,        X86::VPANDDZ256rmkz,        0 },
2127     { X86::VPANDQZ256rrkz,        X86::VPANDQZ256rmkz,        0 },
2128     { X86::VPANDNDZ256rrkz,       X86::VPANDNDZ256rmkz,       0 },
2129     { X86::VPANDNQZ256rrkz,       X86::VPANDNQZ256rmkz,       0 },
2130     { X86::VPORDZ256rrkz,         X86::VPORDZ256rmkz,         0 },
2131     { X86::VPORQZ256rrkz,         X86::VPORQZ256rmkz,         0 },
2132     { X86::VPXORDZ256rrkz,        X86::VPXORDZ256rmkz,        0 },
2133     { X86::VPXORQZ256rrkz,        X86::VPXORQZ256rmkz,        0 },
2134     { X86::VPTERNLOGDZ256rri,     X86::VPTERNLOGDZ256rmi,     0 },
2135     { X86::VPTERNLOGQZ256rri,     X86::VPTERNLOGQZ256rmi,     0 },
2136     // AVX-512{F,VL} arithmetic instructions 128-bit
2137     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
2138     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
2139     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
2140     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
2141     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
2142     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
2143     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
2144     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
2145     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
2146     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
2147     { X86::VMINCPSZ128rrkz,       X86::VMINCPSZ128rmkz,       0 },
2148     { X86::VMINCPDZ128rrkz,       X86::VMINCPDZ128rmkz,       0 },
2149     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
2150     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 },
2151     { X86::VMAXCPSZ128rrkz,       X86::VMAXCPSZ128rmkz,       0 },
2152     { X86::VMAXCPDZ128rrkz,       X86::VMAXCPDZ128rmkz,       0 },
2153     { X86::VANDPDZ128rrkz,        X86::VANDPDZ128rmkz,        0 },
2154     { X86::VANDPSZ128rrkz,        X86::VANDPSZ128rmkz,        0 },
2155     { X86::VANDNPDZ128rrkz,       X86::VANDNPDZ128rmkz,       0 },
2156     { X86::VANDNPSZ128rrkz,       X86::VANDNPSZ128rmkz,       0 },
2157     { X86::VORPDZ128rrkz,         X86::VORPDZ128rmkz,         0 },
2158     { X86::VORPSZ128rrkz,         X86::VORPSZ128rmkz,         0 },
2159     { X86::VXORPDZ128rrkz,        X86::VXORPDZ128rmkz,        0 },
2160     { X86::VXORPSZ128rrkz,        X86::VXORPSZ128rmkz,        0 },
2161     { X86::VPANDDZ128rrkz,        X86::VPANDDZ128rmkz,        0 },
2162     { X86::VPANDQZ128rrkz,        X86::VPANDQZ128rmkz,        0 },
2163     { X86::VPANDNDZ128rrkz,       X86::VPANDNDZ128rmkz,       0 },
2164     { X86::VPANDNQZ128rrkz,       X86::VPANDNQZ128rmkz,       0 },
2165     { X86::VPORDZ128rrkz,         X86::VPORDZ128rmkz,         0 },
2166     { X86::VPORQZ128rrkz,         X86::VPORQZ128rmkz,         0 },
2167     { X86::VPXORDZ128rrkz,        X86::VPXORDZ128rmkz,        0 },
2168     { X86::VPXORQZ128rrkz,        X86::VPXORQZ128rmkz,        0 },
2169     { X86::VPTERNLOGDZ128rri,     X86::VPTERNLOGDZ128rmi,     0 },
2170     { X86::VPTERNLOGQZ128rri,     X86::VPTERNLOGQZ128rmi,     0 },
2171   };
2172 
2173   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
2174     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2175                   Entry.RegOp, Entry.MemOp,
2176                   // Index 3, folded load
2177                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
2178   }
2179   auto I = X86InstrFMA3Info::rm_begin();
2180   auto E = X86InstrFMA3Info::rm_end();
2181   for (; I != E; ++I)
2182     if (!I.getGroup()->isKMasked())
2183       AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
2184                     I.getRegOpcode(), I.getMemOpcode(),
2185                     TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD);
2186 
2187   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
2188      // AVX-512 foldable instructions
2189     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
2190     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
2191     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
2192     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
2193     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
2194     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
2195     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
2196     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
2197     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
2198     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
2199     { X86::VMINCPSZrrk,        X86::VMINCPSZrmk,          0 },
2200     { X86::VMINCPDZrrk,        X86::VMINCPDZrmk,          0 },
2201     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
2202     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
2203     { X86::VMAXCPSZrrk,        X86::VMAXCPSZrmk,          0 },
2204     { X86::VMAXCPDZrrk,        X86::VMAXCPDZrmk,          0 },
2205     { X86::VANDPDZrrk,         X86::VANDPDZrmk,           0 },
2206     { X86::VANDPSZrrk,         X86::VANDPSZrmk,           0 },
2207     { X86::VANDNPDZrrk,        X86::VANDNPDZrmk,          0 },
2208     { X86::VANDNPSZrrk,        X86::VANDNPSZrmk,          0 },
2209     { X86::VORPDZrrk,          X86::VORPDZrmk,            0 },
2210     { X86::VORPSZrrk,          X86::VORPSZrmk,            0 },
2211     { X86::VXORPDZrrk,         X86::VXORPDZrmk,           0 },
2212     { X86::VXORPSZrrk,         X86::VXORPSZrmk,           0 },
2213     { X86::VPANDDZrrk,         X86::VPANDDZrmk,           0 },
2214     { X86::VPANDQZrrk,         X86::VPANDQZrmk,           0 },
2215     { X86::VPANDNDZrrk,        X86::VPANDNDZrmk,          0 },
2216     { X86::VPANDNQZrrk,        X86::VPANDNQZrmk,          0 },
2217     { X86::VPORDZrrk,          X86::VPORDZrmk,            0 },
2218     { X86::VPORQZrrk,          X86::VPORQZrmk,            0 },
2219     { X86::VPXORDZrrk,         X86::VPXORDZrmk,           0 },
2220     { X86::VPXORQZrrk,         X86::VPXORQZrmk,           0 },
2221     { X86::VPTERNLOGDZrrik,    X86::VPTERNLOGDZrmik,      0 },
2222     { X86::VPTERNLOGDZrrikz,   X86::VPTERNLOGDZrmikz,     0 },
2223     { X86::VPTERNLOGQZrrik,    X86::VPTERNLOGQZrmik,      0 },
2224     { X86::VPTERNLOGQZrrikz,   X86::VPTERNLOGQZrmikz,     0 },
2225     // AVX-512{F,VL} foldable instructions 256-bit
2226     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
2227     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
2228     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
2229     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
2230     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
2231     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
2232     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
2233     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
2234     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
2235     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
2236     { X86::VMINCPSZ256rrk,     X86::VMINCPSZ256rmk,       0 },
2237     { X86::VMINCPDZ256rrk,     X86::VMINCPDZ256rmk,       0 },
2238     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
2239     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
2240     { X86::VMAXCPSZ256rrk,     X86::VMAXCPSZ256rmk,       0 },
2241     { X86::VMAXCPDZ256rrk,     X86::VMAXCPDZ256rmk,       0 },
2242     { X86::VANDPDZ256rrk,      X86::VANDPDZ256rmk,        0 },
2243     { X86::VANDPSZ256rrk,      X86::VANDPSZ256rmk,        0 },
2244     { X86::VANDNPDZ256rrk,     X86::VANDNPDZ256rmk,       0 },
2245     { X86::VANDNPSZ256rrk,     X86::VANDNPSZ256rmk,       0 },
2246     { X86::VORPDZ256rrk,       X86::VORPDZ256rmk,         0 },
2247     { X86::VORPSZ256rrk,       X86::VORPSZ256rmk,         0 },
2248     { X86::VXORPDZ256rrk,      X86::VXORPDZ256rmk,        0 },
2249     { X86::VXORPSZ256rrk,      X86::VXORPSZ256rmk,        0 },
2250     { X86::VPANDDZ256rrk,      X86::VPANDDZ256rmk,        0 },
2251     { X86::VPANDQZ256rrk,      X86::VPANDQZ256rmk,        0 },
2252     { X86::VPANDNDZ256rrk,     X86::VPANDNDZ256rmk,       0 },
2253     { X86::VPANDNQZ256rrk,     X86::VPANDNQZ256rmk,       0 },
2254     { X86::VPORDZ256rrk,       X86::VPORDZ256rmk,         0 },
2255     { X86::VPORQZ256rrk,       X86::VPORQZ256rmk,         0 },
2256     { X86::VPXORDZ256rrk,      X86::VPXORDZ256rmk,        0 },
2257     { X86::VPXORQZ256rrk,      X86::VPXORQZ256rmk,        0 },
2258     { X86::VPTERNLOGDZ256rrik, X86::VPTERNLOGDZ256rmik,   0 },
2259     { X86::VPTERNLOGDZ256rrikz,X86::VPTERNLOGDZ256rmikz,  0 },
2260     { X86::VPTERNLOGQZ256rrik, X86::VPTERNLOGQZ256rmik,   0 },
2261     { X86::VPTERNLOGQZ256rrikz,X86::VPTERNLOGQZ256rmikz,  0 },
2262     // AVX-512{F,VL} foldable instructions 128-bit
2263     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
2264     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
2265     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
2266     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
2267     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
2268     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
2269     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
2270     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
2271     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
2272     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
2273     { X86::VMINCPSZ128rrk,     X86::VMINCPSZ128rmk,       0 },
2274     { X86::VMINCPDZ128rrk,     X86::VMINCPDZ128rmk,       0 },
2275     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
2276     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 },
2277     { X86::VMAXCPSZ128rrk,     X86::VMAXCPSZ128rmk,       0 },
2278     { X86::VMAXCPDZ128rrk,     X86::VMAXCPDZ128rmk,       0 },
2279     { X86::VANDPDZ128rrk,      X86::VANDPDZ128rmk,        0 },
2280     { X86::VANDPSZ128rrk,      X86::VANDPSZ128rmk,        0 },
2281     { X86::VANDNPDZ128rrk,     X86::VANDNPDZ128rmk,       0 },
2282     { X86::VANDNPSZ128rrk,     X86::VANDNPSZ128rmk,       0 },
2283     { X86::VORPDZ128rrk,       X86::VORPDZ128rmk,         0 },
2284     { X86::VORPSZ128rrk,       X86::VORPSZ128rmk,         0 },
2285     { X86::VXORPDZ128rrk,      X86::VXORPDZ128rmk,        0 },
2286     { X86::VXORPSZ128rrk,      X86::VXORPSZ128rmk,        0 },
2287     { X86::VPANDDZ128rrk,      X86::VPANDDZ128rmk,        0 },
2288     { X86::VPANDQZ128rrk,      X86::VPANDQZ128rmk,        0 },
2289     { X86::VPANDNDZ128rrk,     X86::VPANDNDZ128rmk,       0 },
2290     { X86::VPANDNQZ128rrk,     X86::VPANDNQZ128rmk,       0 },
2291     { X86::VPORDZ128rrk,       X86::VPORDZ128rmk,         0 },
2292     { X86::VPORQZ128rrk,       X86::VPORQZ128rmk,         0 },
2293     { X86::VPXORDZ128rrk,      X86::VPXORDZ128rmk,        0 },
2294     { X86::VPXORQZ128rrk,      X86::VPXORQZ128rmk,        0 },
2295     { X86::VPTERNLOGDZ128rrik, X86::VPTERNLOGDZ128rmik,   0 },
2296     { X86::VPTERNLOGDZ128rrikz,X86::VPTERNLOGDZ128rmikz,  0 },
2297     { X86::VPTERNLOGQZ128rrik, X86::VPTERNLOGQZ128rmik,   0 },
2298     { X86::VPTERNLOGQZ128rrikz,X86::VPTERNLOGQZ128rmikz,  0 },
2299   };
2300 
2301   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
2302     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2303                   Entry.RegOp, Entry.MemOp,
2304                   // Index 4, folded load
2305                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
2306   }
2307   for (I = X86InstrFMA3Info::rm_begin(); I != E; ++I)
2308     if (I.getGroup()->isKMasked())
2309       AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
2310                     I.getRegOpcode(), I.getMemOpcode(),
2311                     TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD);
2312 }
2313 
2314 void
2315 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2316                             MemOp2RegOpTableType &M2RTable,
2317                             uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
2318   if ((Flags & TB_NO_FORWARD) == 0) {
2319     assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2320     R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2321   }
2322   if ((Flags & TB_NO_REVERSE) == 0) {
2323     assert(!M2RTable.count(MemOp) &&
2324          "Duplicated entries in unfolding maps?");
2325     M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2326   }
2327 }
2328 
2329 bool
2330 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2331                                     unsigned &SrcReg, unsigned &DstReg,
2332                                     unsigned &SubIdx) const {
2333   switch (MI.getOpcode()) {
2334   default: break;
2335   case X86::MOVSX16rr8:
2336   case X86::MOVZX16rr8:
2337   case X86::MOVSX32rr8:
2338   case X86::MOVZX32rr8:
2339   case X86::MOVSX64rr8:
2340     if (!Subtarget.is64Bit())
2341       // It's not always legal to reference the low 8-bit of the larger
2342       // register in 32-bit mode.
2343       return false;
2344   case X86::MOVSX32rr16:
2345   case X86::MOVZX32rr16:
2346   case X86::MOVSX64rr16:
2347   case X86::MOVSX64rr32: {
2348     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2349       // Be conservative.
2350       return false;
2351     SrcReg = MI.getOperand(1).getReg();
2352     DstReg = MI.getOperand(0).getReg();
2353     switch (MI.getOpcode()) {
2354     default: llvm_unreachable("Unreachable!");
2355     case X86::MOVSX16rr8:
2356     case X86::MOVZX16rr8:
2357     case X86::MOVSX32rr8:
2358     case X86::MOVZX32rr8:
2359     case X86::MOVSX64rr8:
2360       SubIdx = X86::sub_8bit;
2361       break;
2362     case X86::MOVSX32rr16:
2363     case X86::MOVZX32rr16:
2364     case X86::MOVSX64rr16:
2365       SubIdx = X86::sub_16bit;
2366       break;
2367     case X86::MOVSX64rr32:
2368       SubIdx = X86::sub_32bit;
2369       break;
2370     }
2371     return true;
2372   }
2373   }
2374   return false;
2375 }
2376 
2377 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
2378   const MachineFunction *MF = MI.getParent()->getParent();
2379   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2380 
2381   if (MI.getOpcode() == getCallFrameSetupOpcode() ||
2382       MI.getOpcode() == getCallFrameDestroyOpcode()) {
2383     unsigned StackAlign = TFI->getStackAlignment();
2384     int SPAdj =
2385         (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
2386 
2387     SPAdj -= MI.getOperand(1).getImm();
2388 
2389     if (MI.getOpcode() == getCallFrameSetupOpcode())
2390       return SPAdj;
2391     else
2392       return -SPAdj;
2393   }
2394 
2395   // To know whether a call adjusts the stack, we need information
2396   // that is bound to the following ADJCALLSTACKUP pseudo.
2397   // Look for the next ADJCALLSTACKUP that follows the call.
2398   if (MI.isCall()) {
2399     const MachineBasicBlock *MBB = MI.getParent();
2400     auto I = ++MachineBasicBlock::const_iterator(MI);
2401     for (auto E = MBB->end(); I != E; ++I) {
2402       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2403           I->isCall())
2404         break;
2405     }
2406 
2407     // If we could not find a frame destroy opcode, then it has already
2408     // been simplified, so we don't care.
2409     if (I->getOpcode() != getCallFrameDestroyOpcode())
2410       return 0;
2411 
2412     return -(I->getOperand(1).getImm());
2413   }
2414 
2415   // Currently handle only PUSHes we can reasonably expect to see
2416   // in call sequences
2417   switch (MI.getOpcode()) {
2418   default:
2419     return 0;
2420   case X86::PUSH32i8:
2421   case X86::PUSH32r:
2422   case X86::PUSH32rmm:
2423   case X86::PUSH32rmr:
2424   case X86::PUSHi32:
2425     return 4;
2426   case X86::PUSH64i8:
2427   case X86::PUSH64r:
2428   case X86::PUSH64rmm:
2429   case X86::PUSH64rmr:
2430   case X86::PUSH64i32:
2431     return 8;
2432   }
2433 }
2434 
2435 /// Return true and the FrameIndex if the specified
2436 /// operand and follow operands form a reference to the stack frame.
2437 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
2438                                   int &FrameIndex) const {
2439   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
2440       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
2441       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
2442       MI.getOperand(Op + X86::AddrDisp).isImm() &&
2443       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
2444       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
2445       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
2446     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
2447     return true;
2448   }
2449   return false;
2450 }
2451 
2452 static bool isFrameLoadOpcode(int Opcode) {
2453   switch (Opcode) {
2454   default:
2455     return false;
2456   case X86::MOV8rm:
2457   case X86::MOV16rm:
2458   case X86::MOV32rm:
2459   case X86::MOV64rm:
2460   case X86::LD_Fp64m:
2461   case X86::MOVSSrm:
2462   case X86::MOVSDrm:
2463   case X86::MOVAPSrm:
2464   case X86::MOVUPSrm:
2465   case X86::MOVAPDrm:
2466   case X86::MOVUPDrm:
2467   case X86::MOVDQArm:
2468   case X86::MOVDQUrm:
2469   case X86::VMOVSSrm:
2470   case X86::VMOVSDrm:
2471   case X86::VMOVAPSrm:
2472   case X86::VMOVUPSrm:
2473   case X86::VMOVAPDrm:
2474   case X86::VMOVUPDrm:
2475   case X86::VMOVDQArm:
2476   case X86::VMOVDQUrm:
2477   case X86::VMOVUPSYrm:
2478   case X86::VMOVAPSYrm:
2479   case X86::VMOVUPDYrm:
2480   case X86::VMOVAPDYrm:
2481   case X86::VMOVDQUYrm:
2482   case X86::VMOVDQAYrm:
2483   case X86::MMX_MOVD64rm:
2484   case X86::MMX_MOVQ64rm:
2485   case X86::VMOVSSZrm:
2486   case X86::VMOVSDZrm:
2487   case X86::VMOVAPSZrm:
2488   case X86::VMOVAPSZ128rm:
2489   case X86::VMOVAPSZ256rm:
2490   case X86::VMOVAPSZ128rm_NOVLX:
2491   case X86::VMOVAPSZ256rm_NOVLX:
2492   case X86::VMOVUPSZrm:
2493   case X86::VMOVUPSZ128rm:
2494   case X86::VMOVUPSZ256rm:
2495   case X86::VMOVUPSZ128rm_NOVLX:
2496   case X86::VMOVUPSZ256rm_NOVLX:
2497   case X86::VMOVAPDZrm:
2498   case X86::VMOVAPDZ128rm:
2499   case X86::VMOVAPDZ256rm:
2500   case X86::VMOVUPDZrm:
2501   case X86::VMOVUPDZ128rm:
2502   case X86::VMOVUPDZ256rm:
2503   case X86::VMOVDQA32Zrm:
2504   case X86::VMOVDQA32Z128rm:
2505   case X86::VMOVDQA32Z256rm:
2506   case X86::VMOVDQU32Zrm:
2507   case X86::VMOVDQU32Z128rm:
2508   case X86::VMOVDQU32Z256rm:
2509   case X86::VMOVDQA64Zrm:
2510   case X86::VMOVDQA64Z128rm:
2511   case X86::VMOVDQA64Z256rm:
2512   case X86::VMOVDQU64Zrm:
2513   case X86::VMOVDQU64Z128rm:
2514   case X86::VMOVDQU64Z256rm:
2515   case X86::VMOVDQU8Zrm:
2516   case X86::VMOVDQU8Z128rm:
2517   case X86::VMOVDQU8Z256rm:
2518   case X86::VMOVDQU16Zrm:
2519   case X86::VMOVDQU16Z128rm:
2520   case X86::VMOVDQU16Z256rm:
2521   case X86::KMOVBkm:
2522   case X86::KMOVWkm:
2523   case X86::KMOVDkm:
2524   case X86::KMOVQkm:
2525     return true;
2526   }
2527 }
2528 
2529 static bool isFrameStoreOpcode(int Opcode) {
2530   switch (Opcode) {
2531   default: break;
2532   case X86::MOV8mr:
2533   case X86::MOV16mr:
2534   case X86::MOV32mr:
2535   case X86::MOV64mr:
2536   case X86::ST_FpP64m:
2537   case X86::MOVSSmr:
2538   case X86::MOVSDmr:
2539   case X86::MOVAPSmr:
2540   case X86::MOVUPSmr:
2541   case X86::MOVAPDmr:
2542   case X86::MOVUPDmr:
2543   case X86::MOVDQAmr:
2544   case X86::MOVDQUmr:
2545   case X86::VMOVSSmr:
2546   case X86::VMOVSDmr:
2547   case X86::VMOVAPSmr:
2548   case X86::VMOVUPSmr:
2549   case X86::VMOVAPDmr:
2550   case X86::VMOVUPDmr:
2551   case X86::VMOVDQAmr:
2552   case X86::VMOVDQUmr:
2553   case X86::VMOVUPSYmr:
2554   case X86::VMOVAPSYmr:
2555   case X86::VMOVUPDYmr:
2556   case X86::VMOVAPDYmr:
2557   case X86::VMOVDQUYmr:
2558   case X86::VMOVDQAYmr:
2559   case X86::VMOVSSZmr:
2560   case X86::VMOVSDZmr:
2561   case X86::VMOVUPSZmr:
2562   case X86::VMOVUPSZ128mr:
2563   case X86::VMOVUPSZ256mr:
2564   case X86::VMOVUPSZ128mr_NOVLX:
2565   case X86::VMOVUPSZ256mr_NOVLX:
2566   case X86::VMOVAPSZmr:
2567   case X86::VMOVAPSZ128mr:
2568   case X86::VMOVAPSZ256mr:
2569   case X86::VMOVAPSZ128mr_NOVLX:
2570   case X86::VMOVAPSZ256mr_NOVLX:
2571   case X86::VMOVUPDZmr:
2572   case X86::VMOVUPDZ128mr:
2573   case X86::VMOVUPDZ256mr:
2574   case X86::VMOVAPDZmr:
2575   case X86::VMOVAPDZ128mr:
2576   case X86::VMOVAPDZ256mr:
2577   case X86::VMOVDQA32Zmr:
2578   case X86::VMOVDQA32Z128mr:
2579   case X86::VMOVDQA32Z256mr:
2580   case X86::VMOVDQU32Zmr:
2581   case X86::VMOVDQU32Z128mr:
2582   case X86::VMOVDQU32Z256mr:
2583   case X86::VMOVDQA64Zmr:
2584   case X86::VMOVDQA64Z128mr:
2585   case X86::VMOVDQA64Z256mr:
2586   case X86::VMOVDQU64Zmr:
2587   case X86::VMOVDQU64Z128mr:
2588   case X86::VMOVDQU64Z256mr:
2589   case X86::VMOVDQU8Zmr:
2590   case X86::VMOVDQU8Z128mr:
2591   case X86::VMOVDQU8Z256mr:
2592   case X86::VMOVDQU16Zmr:
2593   case X86::VMOVDQU16Z128mr:
2594   case X86::VMOVDQU16Z256mr:
2595   case X86::MMX_MOVD64mr:
2596   case X86::MMX_MOVQ64mr:
2597   case X86::MMX_MOVNTQmr:
2598   case X86::KMOVBmk:
2599   case X86::KMOVWmk:
2600   case X86::KMOVDmk:
2601   case X86::KMOVQmk:
2602     return true;
2603   }
2604   return false;
2605 }
2606 
2607 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
2608                                            int &FrameIndex) const {
2609   if (isFrameLoadOpcode(MI.getOpcode()))
2610     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2611       return MI.getOperand(0).getReg();
2612   return 0;
2613 }
2614 
2615 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
2616                                                  int &FrameIndex) const {
2617   if (isFrameLoadOpcode(MI.getOpcode())) {
2618     unsigned Reg;
2619     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2620       return Reg;
2621     // Check for post-frame index elimination operations
2622     const MachineMemOperand *Dummy;
2623     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2624   }
2625   return 0;
2626 }
2627 
2628 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
2629                                           int &FrameIndex) const {
2630   if (isFrameStoreOpcode(MI.getOpcode()))
2631     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2632         isFrameOperand(MI, 0, FrameIndex))
2633       return MI.getOperand(X86::AddrNumOperands).getReg();
2634   return 0;
2635 }
2636 
2637 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
2638                                                 int &FrameIndex) const {
2639   if (isFrameStoreOpcode(MI.getOpcode())) {
2640     unsigned Reg;
2641     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2642       return Reg;
2643     // Check for post-frame index elimination operations
2644     const MachineMemOperand *Dummy;
2645     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2646   }
2647   return 0;
2648 }
2649 
2650 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2651 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2652   // Don't waste compile time scanning use-def chains of physregs.
2653   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2654     return false;
2655   bool isPICBase = false;
2656   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2657          E = MRI.def_instr_end(); I != E; ++I) {
2658     MachineInstr *DefMI = &*I;
2659     if (DefMI->getOpcode() != X86::MOVPC32r)
2660       return false;
2661     assert(!isPICBase && "More than one PIC base?");
2662     isPICBase = true;
2663   }
2664   return isPICBase;
2665 }
2666 
2667 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
2668                                                      AliasAnalysis *AA) const {
2669   switch (MI.getOpcode()) {
2670   default: break;
2671   case X86::MOV8rm:
2672   case X86::MOV8rm_NOREX:
2673   case X86::MOV16rm:
2674   case X86::MOV32rm:
2675   case X86::MOV64rm:
2676   case X86::LD_Fp64m:
2677   case X86::MOVSSrm:
2678   case X86::MOVSDrm:
2679   case X86::MOVAPSrm:
2680   case X86::MOVUPSrm:
2681   case X86::MOVAPDrm:
2682   case X86::MOVUPDrm:
2683   case X86::MOVDQArm:
2684   case X86::MOVDQUrm:
2685   case X86::VMOVSSrm:
2686   case X86::VMOVSDrm:
2687   case X86::VMOVAPSrm:
2688   case X86::VMOVUPSrm:
2689   case X86::VMOVAPDrm:
2690   case X86::VMOVUPDrm:
2691   case X86::VMOVDQArm:
2692   case X86::VMOVDQUrm:
2693   case X86::VMOVAPSYrm:
2694   case X86::VMOVUPSYrm:
2695   case X86::VMOVAPDYrm:
2696   case X86::VMOVUPDYrm:
2697   case X86::VMOVDQAYrm:
2698   case X86::VMOVDQUYrm:
2699   case X86::MMX_MOVD64rm:
2700   case X86::MMX_MOVQ64rm:
2701   // AVX-512
2702   case X86::VMOVSSZrm:
2703   case X86::VMOVSDZrm:
2704   case X86::VMOVAPDZ128rm:
2705   case X86::VMOVAPDZ256rm:
2706   case X86::VMOVAPDZrm:
2707   case X86::VMOVAPSZ128rm:
2708   case X86::VMOVAPSZ256rm:
2709   case X86::VMOVAPSZ128rm_NOVLX:
2710   case X86::VMOVAPSZ256rm_NOVLX:
2711   case X86::VMOVAPSZrm:
2712   case X86::VMOVDQA32Z128rm:
2713   case X86::VMOVDQA32Z256rm:
2714   case X86::VMOVDQA32Zrm:
2715   case X86::VMOVDQA64Z128rm:
2716   case X86::VMOVDQA64Z256rm:
2717   case X86::VMOVDQA64Zrm:
2718   case X86::VMOVDQU16Z128rm:
2719   case X86::VMOVDQU16Z256rm:
2720   case X86::VMOVDQU16Zrm:
2721   case X86::VMOVDQU32Z128rm:
2722   case X86::VMOVDQU32Z256rm:
2723   case X86::VMOVDQU32Zrm:
2724   case X86::VMOVDQU64Z128rm:
2725   case X86::VMOVDQU64Z256rm:
2726   case X86::VMOVDQU64Zrm:
2727   case X86::VMOVDQU8Z128rm:
2728   case X86::VMOVDQU8Z256rm:
2729   case X86::VMOVDQU8Zrm:
2730   case X86::VMOVUPDZ128rm:
2731   case X86::VMOVUPDZ256rm:
2732   case X86::VMOVUPDZrm:
2733   case X86::VMOVUPSZ128rm:
2734   case X86::VMOVUPSZ256rm:
2735   case X86::VMOVUPSZ128rm_NOVLX:
2736   case X86::VMOVUPSZ256rm_NOVLX:
2737   case X86::VMOVUPSZrm: {
2738     // Loads from constant pools are trivially rematerializable.
2739     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
2740         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2741         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2742         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2743         MI.isDereferenceableInvariantLoad(AA)) {
2744       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
2745       if (BaseReg == 0 || BaseReg == X86::RIP)
2746         return true;
2747       // Allow re-materialization of PIC load.
2748       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
2749         return false;
2750       const MachineFunction &MF = *MI.getParent()->getParent();
2751       const MachineRegisterInfo &MRI = MF.getRegInfo();
2752       return regIsPICBase(BaseReg, MRI);
2753     }
2754     return false;
2755   }
2756 
2757   case X86::LEA32r:
2758   case X86::LEA64r: {
2759     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2760         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2761         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2762         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
2763       // lea fi#, lea GV, etc. are all rematerializable.
2764       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
2765         return true;
2766       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
2767       if (BaseReg == 0)
2768         return true;
2769       // Allow re-materialization of lea PICBase + x.
2770       const MachineFunction &MF = *MI.getParent()->getParent();
2771       const MachineRegisterInfo &MRI = MF.getRegInfo();
2772       return regIsPICBase(BaseReg, MRI);
2773     }
2774     return false;
2775   }
2776   }
2777 
2778   // All other instructions marked M_REMATERIALIZABLE are always trivially
2779   // rematerializable.
2780   return true;
2781 }
2782 
2783 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2784                                          MachineBasicBlock::iterator I) const {
2785   MachineBasicBlock::iterator E = MBB.end();
2786 
2787   // For compile time consideration, if we are not able to determine the
2788   // safety after visiting 4 instructions in each direction, we will assume
2789   // it's not safe.
2790   MachineBasicBlock::iterator Iter = I;
2791   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2792     bool SeenDef = false;
2793     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2794       MachineOperand &MO = Iter->getOperand(j);
2795       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2796         SeenDef = true;
2797       if (!MO.isReg())
2798         continue;
2799       if (MO.getReg() == X86::EFLAGS) {
2800         if (MO.isUse())
2801           return false;
2802         SeenDef = true;
2803       }
2804     }
2805 
2806     if (SeenDef)
2807       // This instruction defines EFLAGS, no need to look any further.
2808       return true;
2809     ++Iter;
2810     // Skip over DBG_VALUE.
2811     while (Iter != E && Iter->isDebugValue())
2812       ++Iter;
2813   }
2814 
2815   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2816   // live in.
2817   if (Iter == E) {
2818     for (MachineBasicBlock *S : MBB.successors())
2819       if (S->isLiveIn(X86::EFLAGS))
2820         return false;
2821     return true;
2822   }
2823 
2824   MachineBasicBlock::iterator B = MBB.begin();
2825   Iter = I;
2826   for (unsigned i = 0; i < 4; ++i) {
2827     // If we make it to the beginning of the block, it's safe to clobber
2828     // EFLAGS iff EFLAGS is not live-in.
2829     if (Iter == B)
2830       return !MBB.isLiveIn(X86::EFLAGS);
2831 
2832     --Iter;
2833     // Skip over DBG_VALUE.
2834     while (Iter != B && Iter->isDebugValue())
2835       --Iter;
2836 
2837     bool SawKill = false;
2838     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2839       MachineOperand &MO = Iter->getOperand(j);
2840       // A register mask may clobber EFLAGS, but we should still look for a
2841       // live EFLAGS def.
2842       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2843         SawKill = true;
2844       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2845         if (MO.isDef()) return MO.isDead();
2846         if (MO.isKill()) SawKill = true;
2847       }
2848     }
2849 
2850     if (SawKill)
2851       // This instruction kills EFLAGS and doesn't redefine it, so
2852       // there's no need to look further.
2853       return true;
2854   }
2855 
2856   // Conservative answer.
2857   return false;
2858 }
2859 
2860 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2861                                  MachineBasicBlock::iterator I,
2862                                  unsigned DestReg, unsigned SubIdx,
2863                                  const MachineInstr &Orig,
2864                                  const TargetRegisterInfo &TRI) const {
2865   bool ClobbersEFLAGS = false;
2866   for (const MachineOperand &MO : Orig.operands()) {
2867     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2868       ClobbersEFLAGS = true;
2869       break;
2870     }
2871   }
2872 
2873   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2874     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2875     // effects.
2876     int Value;
2877     switch (Orig.getOpcode()) {
2878     case X86::MOV32r0:  Value = 0; break;
2879     case X86::MOV32r1:  Value = 1; break;
2880     case X86::MOV32r_1: Value = -1; break;
2881     default:
2882       llvm_unreachable("Unexpected instruction!");
2883     }
2884 
2885     const DebugLoc &DL = Orig.getDebugLoc();
2886     BuildMI(MBB, I, DL, get(X86::MOV32ri))
2887         .addOperand(Orig.getOperand(0))
2888         .addImm(Value);
2889   } else {
2890     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
2891     MBB.insert(I, MI);
2892   }
2893 
2894   MachineInstr &NewMI = *std::prev(I);
2895   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
2896 }
2897 
2898 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2899 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
2900   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2901     MachineOperand &MO = MI.getOperand(i);
2902     if (MO.isReg() && MO.isDef() &&
2903         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2904       return true;
2905     }
2906   }
2907   return false;
2908 }
2909 
2910 /// Check whether the shift count for a machine operand is non-zero.
2911 inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
2912                                               unsigned ShiftAmtOperandIdx) {
2913   // The shift count is six bits with the REX.W prefix and five bits without.
2914   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2915   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
2916   return Imm & ShiftCountMask;
2917 }
2918 
2919 /// Check whether the given shift count is appropriate
2920 /// can be represented by a LEA instruction.
2921 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2922   // Left shift instructions can be transformed into load-effective-address
2923   // instructions if we can encode them appropriately.
2924   // A LEA instruction utilizes a SIB byte to encode its scale factor.
2925   // The SIB.scale field is two bits wide which means that we can encode any
2926   // shift amount less than 4.
2927   return ShAmt < 4 && ShAmt > 0;
2928 }
2929 
2930 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
2931                                   unsigned Opc, bool AllowSP, unsigned &NewSrc,
2932                                   bool &isKill, bool &isUndef,
2933                                   MachineOperand &ImplicitOp,
2934                                   LiveVariables *LV) const {
2935   MachineFunction &MF = *MI.getParent()->getParent();
2936   const TargetRegisterClass *RC;
2937   if (AllowSP) {
2938     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2939   } else {
2940     RC = Opc != X86::LEA32r ?
2941       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2942   }
2943   unsigned SrcReg = Src.getReg();
2944 
2945   // For both LEA64 and LEA32 the register already has essentially the right
2946   // type (32-bit or 64-bit) we may just need to forbid SP.
2947   if (Opc != X86::LEA64_32r) {
2948     NewSrc = SrcReg;
2949     isKill = Src.isKill();
2950     isUndef = Src.isUndef();
2951 
2952     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2953         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2954       return false;
2955 
2956     return true;
2957   }
2958 
2959   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2960   // another we need to add 64-bit registers to the final MI.
2961   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2962     ImplicitOp = Src;
2963     ImplicitOp.setImplicit();
2964 
2965     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
2966     isKill = Src.isKill();
2967     isUndef = Src.isUndef();
2968   } else {
2969     // Virtual register of the wrong class, we have to create a temporary 64-bit
2970     // vreg to feed into the LEA.
2971     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2972     MachineInstr *Copy = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
2973                                  get(TargetOpcode::COPY))
2974         .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2975         .addOperand(Src);
2976 
2977     // Which is obviously going to be dead after we're done with it.
2978     isKill = true;
2979     isUndef = false;
2980 
2981     if (LV)
2982       LV->replaceKillInstruction(SrcReg, MI, *Copy);
2983   }
2984 
2985   // We've set all the parameters without issue.
2986   return true;
2987 }
2988 
2989 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2990 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2991 /// truncating back down to a 16-bit subregister.
2992 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
2993     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
2994     LiveVariables *LV) const {
2995   MachineBasicBlock::iterator MBBI = MI.getIterator();
2996   unsigned Dest = MI.getOperand(0).getReg();
2997   unsigned Src = MI.getOperand(1).getReg();
2998   bool isDead = MI.getOperand(0).isDead();
2999   bool isKill = MI.getOperand(1).isKill();
3000 
3001   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
3002   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
3003   unsigned Opc, leaInReg;
3004   if (Subtarget.is64Bit()) {
3005     Opc = X86::LEA64_32r;
3006     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3007   } else {
3008     Opc = X86::LEA32r;
3009     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
3010   }
3011 
3012   // Build and insert into an implicit UNDEF value. This is OK because
3013   // well be shifting and then extracting the lower 16-bits.
3014   // This has the potential to cause partial register stall. e.g.
3015   //   movw    (%rbp,%rcx,2), %dx
3016   //   leal    -65(%rdx), %esi
3017   // But testing has shown this *does* help performance in 64-bit mode (at
3018   // least on modern x86 machines).
3019   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
3020   MachineInstr *InsMI =
3021       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
3022           .addReg(leaInReg, RegState::Define, X86::sub_16bit)
3023           .addReg(Src, getKillRegState(isKill));
3024 
3025   MachineInstrBuilder MIB =
3026       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
3027   switch (MIOpc) {
3028   default: llvm_unreachable("Unreachable!");
3029   case X86::SHL16ri: {
3030     unsigned ShAmt = MI.getOperand(2).getImm();
3031     MIB.addReg(0).addImm(1ULL << ShAmt)
3032        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
3033     break;
3034   }
3035   case X86::INC16r:
3036     addRegOffset(MIB, leaInReg, true, 1);
3037     break;
3038   case X86::DEC16r:
3039     addRegOffset(MIB, leaInReg, true, -1);
3040     break;
3041   case X86::ADD16ri:
3042   case X86::ADD16ri8:
3043   case X86::ADD16ri_DB:
3044   case X86::ADD16ri8_DB:
3045     addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
3046     break;
3047   case X86::ADD16rr:
3048   case X86::ADD16rr_DB: {
3049     unsigned Src2 = MI.getOperand(2).getReg();
3050     bool isKill2 = MI.getOperand(2).isKill();
3051     unsigned leaInReg2 = 0;
3052     MachineInstr *InsMI2 = nullptr;
3053     if (Src == Src2) {
3054       // ADD16rr %reg1028<kill>, %reg1028
3055       // just a single insert_subreg.
3056       addRegReg(MIB, leaInReg, true, leaInReg, false);
3057     } else {
3058       if (Subtarget.is64Bit())
3059         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
3060       else
3061         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
3062       // Build and insert into an implicit UNDEF value. This is OK because
3063       // well be shifting and then extracting the lower 16-bits.
3064       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
3065       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
3066                    .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
3067                    .addReg(Src2, getKillRegState(isKill2));
3068       addRegReg(MIB, leaInReg, true, leaInReg2, true);
3069     }
3070     if (LV && isKill2 && InsMI2)
3071       LV->replaceKillInstruction(Src2, MI, *InsMI2);
3072     break;
3073   }
3074   }
3075 
3076   MachineInstr *NewMI = MIB;
3077   MachineInstr *ExtMI =
3078       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
3079           .addReg(Dest, RegState::Define | getDeadRegState(isDead))
3080           .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
3081 
3082   if (LV) {
3083     // Update live variables
3084     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
3085     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
3086     if (isKill)
3087       LV->replaceKillInstruction(Src, MI, *InsMI);
3088     if (isDead)
3089       LV->replaceKillInstruction(Dest, MI, *ExtMI);
3090   }
3091 
3092   return ExtMI;
3093 }
3094 
3095 /// This method must be implemented by targets that
3096 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
3097 /// may be able to convert a two-address instruction into a true
3098 /// three-address instruction on demand.  This allows the X86 target (for
3099 /// example) to convert ADD and SHL instructions into LEA instructions if they
3100 /// would require register copies due to two-addressness.
3101 ///
3102 /// This method returns a null pointer if the transformation cannot be
3103 /// performed, otherwise it returns the new instruction.
3104 ///
3105 MachineInstr *
3106 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
3107                                     MachineInstr &MI, LiveVariables *LV) const {
3108   // The following opcodes also sets the condition code register(s). Only
3109   // convert them to equivalent lea if the condition code register def's
3110   // are dead!
3111   if (hasLiveCondCodeDef(MI))
3112     return nullptr;
3113 
3114   MachineFunction &MF = *MI.getParent()->getParent();
3115   // All instructions input are two-addr instructions.  Get the known operands.
3116   const MachineOperand &Dest = MI.getOperand(0);
3117   const MachineOperand &Src = MI.getOperand(1);
3118 
3119   MachineInstr *NewMI = nullptr;
3120   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
3121   // we have better subtarget support, enable the 16-bit LEA generation here.
3122   // 16-bit LEA is also slow on Core2.
3123   bool DisableLEA16 = true;
3124   bool is64Bit = Subtarget.is64Bit();
3125 
3126   unsigned MIOpc = MI.getOpcode();
3127   switch (MIOpc) {
3128   default: return nullptr;
3129   case X86::SHL64ri: {
3130     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
3131     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3132     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
3133 
3134     // LEA can't handle RSP.
3135     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
3136         !MF.getRegInfo().constrainRegClass(Src.getReg(),
3137                                            &X86::GR64_NOSPRegClass))
3138       return nullptr;
3139 
3140     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3141                 .addOperand(Dest)
3142                 .addReg(0)
3143                 .addImm(1ULL << ShAmt)
3144                 .addOperand(Src)
3145                 .addImm(0)
3146                 .addReg(0);
3147     break;
3148   }
3149   case X86::SHL32ri: {
3150     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
3151     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3152     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
3153 
3154     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3155 
3156     // LEA can't handle ESP.
3157     bool isKill, isUndef;
3158     unsigned SrcReg;
3159     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3160     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
3161                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3162       return nullptr;
3163 
3164     MachineInstrBuilder MIB =
3165         BuildMI(MF, MI.getDebugLoc(), get(Opc))
3166             .addOperand(Dest)
3167             .addReg(0)
3168             .addImm(1ULL << ShAmt)
3169             .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
3170             .addImm(0)
3171             .addReg(0);
3172     if (ImplicitOp.getReg() != 0)
3173       MIB.addOperand(ImplicitOp);
3174     NewMI = MIB;
3175 
3176     break;
3177   }
3178   case X86::SHL16ri: {
3179     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
3180     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3181     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
3182 
3183     if (DisableLEA16)
3184       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3185                      : nullptr;
3186     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3187                 .addOperand(Dest)
3188                 .addReg(0)
3189                 .addImm(1ULL << ShAmt)
3190                 .addOperand(Src)
3191                 .addImm(0)
3192                 .addReg(0);
3193     break;
3194   }
3195   case X86::INC64r:
3196   case X86::INC32r: {
3197     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
3198     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
3199       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3200     bool isKill, isUndef;
3201     unsigned SrcReg;
3202     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3203     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
3204                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3205       return nullptr;
3206 
3207     MachineInstrBuilder MIB =
3208         BuildMI(MF, MI.getDebugLoc(), get(Opc))
3209             .addOperand(Dest)
3210             .addReg(SrcReg,
3211                     getKillRegState(isKill) | getUndefRegState(isUndef));
3212     if (ImplicitOp.getReg() != 0)
3213       MIB.addOperand(ImplicitOp);
3214 
3215     NewMI = addOffset(MIB, 1);
3216     break;
3217   }
3218   case X86::INC16r:
3219     if (DisableLEA16)
3220       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3221                      : nullptr;
3222     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
3223     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3224                           .addOperand(Dest)
3225                           .addOperand(Src),
3226                       1);
3227     break;
3228   case X86::DEC64r:
3229   case X86::DEC32r: {
3230     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
3231     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
3232       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
3233 
3234     bool isKill, isUndef;
3235     unsigned SrcReg;
3236     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3237     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
3238                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3239       return nullptr;
3240 
3241     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3242                                   .addOperand(Dest)
3243                                   .addReg(SrcReg, getUndefRegState(isUndef) |
3244                                                       getKillRegState(isKill));
3245     if (ImplicitOp.getReg() != 0)
3246       MIB.addOperand(ImplicitOp);
3247 
3248     NewMI = addOffset(MIB, -1);
3249 
3250     break;
3251   }
3252   case X86::DEC16r:
3253     if (DisableLEA16)
3254       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3255                      : nullptr;
3256     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
3257     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3258                           .addOperand(Dest)
3259                           .addOperand(Src),
3260                       -1);
3261     break;
3262   case X86::ADD64rr:
3263   case X86::ADD64rr_DB:
3264   case X86::ADD32rr:
3265   case X86::ADD32rr_DB: {
3266     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3267     unsigned Opc;
3268     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
3269       Opc = X86::LEA64r;
3270     else
3271       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3272 
3273     bool isKill, isUndef;
3274     unsigned SrcReg;
3275     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3276     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3277                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3278       return nullptr;
3279 
3280     const MachineOperand &Src2 = MI.getOperand(2);
3281     bool isKill2, isUndef2;
3282     unsigned SrcReg2;
3283     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
3284     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
3285                         SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
3286       return nullptr;
3287 
3288     MachineInstrBuilder MIB =
3289         BuildMI(MF, MI.getDebugLoc(), get(Opc)).addOperand(Dest);
3290     if (ImplicitOp.getReg() != 0)
3291       MIB.addOperand(ImplicitOp);
3292     if (ImplicitOp2.getReg() != 0)
3293       MIB.addOperand(ImplicitOp2);
3294 
3295     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
3296 
3297     // Preserve undefness of the operands.
3298     NewMI->getOperand(1).setIsUndef(isUndef);
3299     NewMI->getOperand(3).setIsUndef(isUndef2);
3300 
3301     if (LV && Src2.isKill())
3302       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
3303     break;
3304   }
3305   case X86::ADD16rr:
3306   case X86::ADD16rr_DB: {
3307     if (DisableLEA16)
3308       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3309                      : nullptr;
3310     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3311     unsigned Src2 = MI.getOperand(2).getReg();
3312     bool isKill2 = MI.getOperand(2).isKill();
3313     NewMI = addRegReg(
3314         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).addOperand(Dest),
3315         Src.getReg(), Src.isKill(), Src2, isKill2);
3316 
3317     // Preserve undefness of the operands.
3318     bool isUndef = MI.getOperand(1).isUndef();
3319     bool isUndef2 = MI.getOperand(2).isUndef();
3320     NewMI->getOperand(1).setIsUndef(isUndef);
3321     NewMI->getOperand(3).setIsUndef(isUndef2);
3322 
3323     if (LV && isKill2)
3324       LV->replaceKillInstruction(Src2, MI, *NewMI);
3325     break;
3326   }
3327   case X86::ADD64ri32:
3328   case X86::ADD64ri8:
3329   case X86::ADD64ri32_DB:
3330   case X86::ADD64ri8_DB:
3331     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3332     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
3333                           .addOperand(Dest)
3334                           .addOperand(Src),
3335                       MI.getOperand(2).getImm());
3336     break;
3337   case X86::ADD32ri:
3338   case X86::ADD32ri8:
3339   case X86::ADD32ri_DB:
3340   case X86::ADD32ri8_DB: {
3341     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3342     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
3343 
3344     bool isKill, isUndef;
3345     unsigned SrcReg;
3346     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
3347     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
3348                         SrcReg, isKill, isUndef, ImplicitOp, LV))
3349       return nullptr;
3350 
3351     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
3352                                   .addOperand(Dest)
3353                                   .addReg(SrcReg, getUndefRegState(isUndef) |
3354                                                       getKillRegState(isKill));
3355     if (ImplicitOp.getReg() != 0)
3356       MIB.addOperand(ImplicitOp);
3357 
3358     NewMI = addOffset(MIB, MI.getOperand(2).getImm());
3359     break;
3360   }
3361   case X86::ADD16ri:
3362   case X86::ADD16ri8:
3363   case X86::ADD16ri_DB:
3364   case X86::ADD16ri8_DB:
3365     if (DisableLEA16)
3366       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
3367                      : nullptr;
3368     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3369     NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3370                           .addOperand(Dest)
3371                           .addOperand(Src),
3372                       MI.getOperand(2).getImm());
3373     break;
3374   }
3375 
3376   if (!NewMI) return nullptr;
3377 
3378   if (LV) {  // Update live variables
3379     if (Src.isKill())
3380       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
3381     if (Dest.isDead())
3382       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
3383   }
3384 
3385   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
3386   return NewMI;
3387 }
3388 
3389 /// This determines which of three possible cases of a three source commute
3390 /// the source indexes correspond to taking into account any mask operands.
3391 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
3392 /// possible.
3393 /// Case 0 - Possible to commute the first and second operands.
3394 /// Case 1 - Possible to commute the first and third operands.
3395 /// Case 2 - Possible to commute the second and third operands.
3396 static int getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
3397                                   unsigned SrcOpIdx2) {
3398   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3399   if (SrcOpIdx1 > SrcOpIdx2)
3400     std::swap(SrcOpIdx1, SrcOpIdx2);
3401 
3402   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
3403   if (X86II::isKMasked(TSFlags)) {
3404     // The k-mask operand cannot be commuted.
3405     if (SrcOpIdx1 == 2)
3406       return -1;
3407 
3408     // For k-zero-masked operations it is Ok to commute the first vector
3409     // operand.
3410     // For regular k-masked operations a conservative choice is done as the
3411     // elements of the first vector operand, for which the corresponding bit
3412     // in the k-mask operand is set to 0, are copied to the result of the
3413     // instruction.
3414     // TODO/FIXME: The commute still may be legal if it is known that the
3415     // k-mask operand is set to either all ones or all zeroes.
3416     // It is also Ok to commute the 1st operand if all users of MI use only
3417     // the elements enabled by the k-mask operand. For example,
3418     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
3419     //                                                     : v1[i];
3420     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
3421     //                                  // Ok, to commute v1 in FMADD213PSZrk.
3422     if (X86II::isKMergeMasked(TSFlags) && SrcOpIdx1 == Op1)
3423       return -1;
3424     Op2++;
3425     Op3++;
3426   }
3427 
3428   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
3429     return 0;
3430   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
3431     return 1;
3432   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
3433     return 2;
3434   return -1;
3435 }
3436 
3437 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
3438     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
3439     const X86InstrFMA3Group &FMA3Group) const {
3440 
3441   unsigned Opc = MI.getOpcode();
3442 
3443   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3444   if (SrcOpIdx1 > SrcOpIdx2)
3445     std::swap(SrcOpIdx1, SrcOpIdx2);
3446 
3447   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3448   // analysis. The commute optimization is legal only if all users of FMA*_Int
3449   // use only the lowest element of the FMA*_Int instruction. Such analysis are
3450   // not implemented yet. So, just return 0 in that case.
3451   // When such analysis are available this place will be the right place for
3452   // calling it.
3453   if (FMA3Group.isIntrinsic() && SrcOpIdx1 == 1)
3454     return 0;
3455 
3456   // Determine which case this commute is or if it can't be done.
3457   int Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
3458   if (Case < 0)
3459     return 0;
3460 
3461   // Define the FMA forms mapping array that helps to map input FMA form
3462   // to output FMA form to preserve the operation semantics after
3463   // commuting the operands.
3464   const unsigned Form132Index = 0;
3465   const unsigned Form213Index = 1;
3466   const unsigned Form231Index = 2;
3467   static const unsigned FormMapping[][3] = {
3468     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3469     // FMA132 A, C, b; ==> FMA231 C, A, b;
3470     // FMA213 B, A, c; ==> FMA213 A, B, c;
3471     // FMA231 C, A, b; ==> FMA132 A, C, b;
3472     { Form231Index, Form213Index, Form132Index },
3473     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3474     // FMA132 A, c, B; ==> FMA132 B, c, A;
3475     // FMA213 B, a, C; ==> FMA231 C, a, B;
3476     // FMA231 C, a, B; ==> FMA213 B, a, C;
3477     { Form132Index, Form231Index, Form213Index },
3478     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3479     // FMA132 a, C, B; ==> FMA213 a, B, C;
3480     // FMA213 b, A, C; ==> FMA132 b, C, A;
3481     // FMA231 c, A, B; ==> FMA231 c, B, A;
3482     { Form213Index, Form132Index, Form231Index }
3483   };
3484 
3485   unsigned FMAForms[3];
3486   if (FMA3Group.isRegOpcodeFromGroup(Opc)) {
3487     FMAForms[0] = FMA3Group.getReg132Opcode();
3488     FMAForms[1] = FMA3Group.getReg213Opcode();
3489     FMAForms[2] = FMA3Group.getReg231Opcode();
3490   } else {
3491     FMAForms[0] = FMA3Group.getMem132Opcode();
3492     FMAForms[1] = FMA3Group.getMem213Opcode();
3493     FMAForms[2] = FMA3Group.getMem231Opcode();
3494   }
3495   unsigned FormIndex;
3496   for (FormIndex = 0; FormIndex < 3; FormIndex++)
3497     if (Opc == FMAForms[FormIndex])
3498       break;
3499 
3500   // Everything is ready, just adjust the FMA opcode and return it.
3501   FormIndex = FormMapping[Case][FormIndex];
3502   return FMAForms[FormIndex];
3503 }
3504 
3505 static bool commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
3506                              unsigned SrcOpIdx2) {
3507   uint64_t TSFlags = MI.getDesc().TSFlags;
3508 
3509   // Determine which case this commute is or if it can't be done.
3510   int Case = getThreeSrcCommuteCase(TSFlags, SrcOpIdx1, SrcOpIdx2);
3511   if (Case < 0)
3512     return false;
3513 
3514   // For each case we need to swap two pairs of bits in the final immediate.
3515   static const uint8_t SwapMasks[3][4] = {
3516     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
3517     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
3518     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
3519   };
3520 
3521   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
3522   // Clear out the bits we are swapping.
3523   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
3524                            SwapMasks[Case][2] | SwapMasks[Case][3]);
3525   // If the immediate had a bit of the pair set, then set the opposite bit.
3526   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
3527   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
3528   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
3529   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
3530   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
3531 
3532   return true;
3533 }
3534 
3535 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
3536                                                    unsigned OpIdx1,
3537                                                    unsigned OpIdx2) const {
3538   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
3539     if (NewMI)
3540       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
3541     return MI;
3542   };
3543 
3544   switch (MI.getOpcode()) {
3545   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3546   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
3547   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
3548   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3549   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3550   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
3551     unsigned Opc;
3552     unsigned Size;
3553     switch (MI.getOpcode()) {
3554     default: llvm_unreachable("Unreachable!");
3555     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3556     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3557     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3558     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
3559     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3560     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
3561     }
3562     unsigned Amt = MI.getOperand(3).getImm();
3563     auto &WorkingMI = cloneIfNew(MI);
3564     WorkingMI.setDesc(get(Opc));
3565     WorkingMI.getOperand(3).setImm(Size - Amt);
3566     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3567                                                    OpIdx1, OpIdx2);
3568   }
3569   case X86::BLENDPDrri:
3570   case X86::BLENDPSrri:
3571   case X86::PBLENDWrri:
3572   case X86::VBLENDPDrri:
3573   case X86::VBLENDPSrri:
3574   case X86::VBLENDPDYrri:
3575   case X86::VBLENDPSYrri:
3576   case X86::VPBLENDDrri:
3577   case X86::VPBLENDWrri:
3578   case X86::VPBLENDDYrri:
3579   case X86::VPBLENDWYrri:{
3580     unsigned Mask;
3581     switch (MI.getOpcode()) {
3582     default: llvm_unreachable("Unreachable!");
3583     case X86::BLENDPDrri:    Mask = 0x03; break;
3584     case X86::BLENDPSrri:    Mask = 0x0F; break;
3585     case X86::PBLENDWrri:    Mask = 0xFF; break;
3586     case X86::VBLENDPDrri:   Mask = 0x03; break;
3587     case X86::VBLENDPSrri:   Mask = 0x0F; break;
3588     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
3589     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
3590     case X86::VPBLENDDrri:   Mask = 0x0F; break;
3591     case X86::VPBLENDWrri:   Mask = 0xFF; break;
3592     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
3593     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
3594     }
3595     // Only the least significant bits of Imm are used.
3596     unsigned Imm = MI.getOperand(3).getImm() & Mask;
3597     auto &WorkingMI = cloneIfNew(MI);
3598     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
3599     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3600                                                    OpIdx1, OpIdx2);
3601   }
3602   case X86::MOVSDrr:
3603   case X86::MOVSSrr:
3604   case X86::VMOVSDrr:
3605   case X86::VMOVSSrr:{
3606     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
3607     if (!Subtarget.hasSSE41())
3608       return nullptr;
3609 
3610     unsigned Mask, Opc;
3611     switch (MI.getOpcode()) {
3612     default: llvm_unreachable("Unreachable!");
3613     case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
3614     case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
3615     case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
3616     case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
3617     }
3618 
3619     // MOVSD/MOVSS's 2nd operand is a FR64/FR32 reg class - we need to copy
3620     // this over to a VR128 class like the 1st operand to use a BLENDPD/BLENDPS.
3621     auto &MRI = MI.getParent()->getParent()->getRegInfo();
3622     auto VR128RC = MRI.getRegClass(MI.getOperand(1).getReg());
3623     unsigned VR128 = MRI.createVirtualRegister(VR128RC);
3624     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY),
3625             VR128)
3626         .addReg(MI.getOperand(2).getReg());
3627 
3628     auto &WorkingMI = cloneIfNew(MI);
3629     WorkingMI.setDesc(get(Opc));
3630     WorkingMI.getOperand(2).setReg(VR128);
3631     WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
3632     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3633                                                    OpIdx1, OpIdx2);
3634   }
3635   case X86::PCLMULQDQrr:
3636   case X86::VPCLMULQDQrr:{
3637     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3638     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3639     unsigned Imm = MI.getOperand(3).getImm();
3640     unsigned Src1Hi = Imm & 0x01;
3641     unsigned Src2Hi = Imm & 0x10;
3642     auto &WorkingMI = cloneIfNew(MI);
3643     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3644     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3645                                                    OpIdx1, OpIdx2);
3646   }
3647   case X86::CMPSDrr:
3648   case X86::CMPSSrr:
3649   case X86::CMPPDrri:
3650   case X86::CMPPSrri:
3651   case X86::VCMPSDrr:
3652   case X86::VCMPSSrr:
3653   case X86::VCMPPDrri:
3654   case X86::VCMPPSrri:
3655   case X86::VCMPPDYrri:
3656   case X86::VCMPPSYrri:
3657   case X86::VCMPSDZrr:
3658   case X86::VCMPSSZrr:
3659   case X86::VCMPPDZrri:
3660   case X86::VCMPPSZrri:
3661   case X86::VCMPPDZ128rri:
3662   case X86::VCMPPSZ128rri:
3663   case X86::VCMPPDZ256rri:
3664   case X86::VCMPPSZ256rri: {
3665     // Float comparison can be safely commuted for
3666     // Ordered/Unordered/Equal/NotEqual tests
3667     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3668     switch (Imm) {
3669     case 0x00: // EQUAL
3670     case 0x03: // UNORDERED
3671     case 0x04: // NOT EQUAL
3672     case 0x07: // ORDERED
3673       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3674     default:
3675       return nullptr;
3676     }
3677   }
3678   case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
3679   case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
3680   case X86::VPCMPBZrri:    case X86::VPCMPUBZrri:
3681   case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
3682   case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
3683   case X86::VPCMPDZrri:    case X86::VPCMPUDZrri:
3684   case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
3685   case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
3686   case X86::VPCMPQZrri:    case X86::VPCMPUQZrri:
3687   case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
3688   case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
3689   case X86::VPCMPWZrri:    case X86::VPCMPUWZrri: {
3690     // Flip comparison mode immediate (if necessary).
3691     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3692     switch (Imm) {
3693     default: llvm_unreachable("Unreachable!");
3694     case 0x01: Imm = 0x06; break; // LT  -> NLE
3695     case 0x02: Imm = 0x05; break; // LE  -> NLT
3696     case 0x05: Imm = 0x02; break; // NLT -> LE
3697     case 0x06: Imm = 0x01; break; // NLE -> LT
3698     case 0x00: // EQ
3699     case 0x03: // FALSE
3700     case 0x04: // NE
3701     case 0x07: // TRUE
3702       break;
3703     }
3704     auto &WorkingMI = cloneIfNew(MI);
3705     WorkingMI.getOperand(3).setImm(Imm);
3706     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3707                                                    OpIdx1, OpIdx2);
3708   }
3709   case X86::VPCOMBri: case X86::VPCOMUBri:
3710   case X86::VPCOMDri: case X86::VPCOMUDri:
3711   case X86::VPCOMQri: case X86::VPCOMUQri:
3712   case X86::VPCOMWri: case X86::VPCOMUWri: {
3713     // Flip comparison mode immediate (if necessary).
3714     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3715     switch (Imm) {
3716     default: llvm_unreachable("Unreachable!");
3717     case 0x00: Imm = 0x02; break; // LT -> GT
3718     case 0x01: Imm = 0x03; break; // LE -> GE
3719     case 0x02: Imm = 0x00; break; // GT -> LT
3720     case 0x03: Imm = 0x01; break; // GE -> LE
3721     case 0x04: // EQ
3722     case 0x05: // NE
3723     case 0x06: // FALSE
3724     case 0x07: // TRUE
3725       break;
3726     }
3727     auto &WorkingMI = cloneIfNew(MI);
3728     WorkingMI.getOperand(3).setImm(Imm);
3729     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3730                                                    OpIdx1, OpIdx2);
3731   }
3732   case X86::VPERM2F128rr:
3733   case X86::VPERM2I128rr: {
3734     // Flip permute source immediate.
3735     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3736     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
3737     unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
3738     auto &WorkingMI = cloneIfNew(MI);
3739     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
3740     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3741                                                    OpIdx1, OpIdx2);
3742   }
3743   case X86::MOVHLPSrr:
3744   case X86::UNPCKHPDrr: {
3745     if (!Subtarget.hasSSE2())
3746       return nullptr;
3747 
3748     unsigned Opc = MI.getOpcode();
3749     switch (Opc) {
3750       default: llvm_unreachable("Unreachable!");
3751       case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
3752       case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
3753     }
3754     auto &WorkingMI = cloneIfNew(MI);
3755     WorkingMI.setDesc(get(Opc));
3756     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3757                                                    OpIdx1, OpIdx2);
3758   }
3759   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
3760   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3761   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
3762   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3763   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3764   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
3765   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
3766   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3767   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3768   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
3769   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
3770   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3771   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
3772   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3773   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
3774   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3775     unsigned Opc;
3776     switch (MI.getOpcode()) {
3777     default: llvm_unreachable("Unreachable!");
3778     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
3779     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
3780     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
3781     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3782     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3783     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3784     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
3785     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
3786     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
3787     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3788     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3789     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
3790     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3791     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3792     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3793     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
3794     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
3795     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
3796     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
3797     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
3798     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
3799     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3800     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3801     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3802     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3803     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3804     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3805     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
3806     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
3807     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
3808     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
3809     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
3810     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
3811     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3812     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3813     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3814     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
3815     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
3816     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
3817     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3818     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3819     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3820     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
3821     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
3822     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
3823     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3824     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3825     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3826     }
3827     auto &WorkingMI = cloneIfNew(MI);
3828     WorkingMI.setDesc(get(Opc));
3829     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3830                                                    OpIdx1, OpIdx2);
3831   }
3832   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
3833   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
3834   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
3835   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
3836   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
3837   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
3838   case X86::VPTERNLOGDZrrik:     case X86::VPTERNLOGDZrmik:
3839   case X86::VPTERNLOGDZ128rrik:  case X86::VPTERNLOGDZ128rmik:
3840   case X86::VPTERNLOGDZ256rrik:  case X86::VPTERNLOGDZ256rmik:
3841   case X86::VPTERNLOGQZrrik:     case X86::VPTERNLOGQZrmik:
3842   case X86::VPTERNLOGQZ128rrik:  case X86::VPTERNLOGQZ128rmik:
3843   case X86::VPTERNLOGQZ256rrik:  case X86::VPTERNLOGQZ256rmik:
3844   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
3845   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
3846   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
3847   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
3848   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
3849   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz: {
3850     auto &WorkingMI = cloneIfNew(MI);
3851     if (!commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2))
3852       return nullptr;
3853     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3854                                                    OpIdx1, OpIdx2);
3855   }
3856   default:
3857     const X86InstrFMA3Group *FMA3Group =
3858         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
3859     if (FMA3Group) {
3860       unsigned Opc =
3861         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
3862       if (Opc == 0)
3863         return nullptr;
3864       auto &WorkingMI = cloneIfNew(MI);
3865       WorkingMI.setDesc(get(Opc));
3866       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3867                                                      OpIdx1, OpIdx2);
3868     }
3869 
3870     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3871   }
3872 }
3873 
3874 bool X86InstrInfo::findFMA3CommutedOpIndices(
3875     const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2,
3876     const X86InstrFMA3Group &FMA3Group) const {
3877 
3878   if (!findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2))
3879     return false;
3880 
3881   // Check if we can adjust the opcode to preserve the semantics when
3882   // commute the register operands.
3883   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2, FMA3Group) != 0;
3884 }
3885 
3886 bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
3887                                                  unsigned &SrcOpIdx1,
3888                                                  unsigned &SrcOpIdx2) const {
3889   uint64_t TSFlags = MI.getDesc().TSFlags;
3890 
3891   unsigned FirstCommutableVecOp = 1;
3892   unsigned LastCommutableVecOp = 3;
3893   unsigned KMaskOp = 0;
3894   if (X86II::isKMasked(TSFlags)) {
3895     // The k-mask operand has index = 2 for masked and zero-masked operations.
3896     KMaskOp = 2;
3897 
3898     // The operand with index = 1 is used as a source for those elements for
3899     // which the corresponding bit in the k-mask is set to 0.
3900     if (X86II::isKMergeMasked(TSFlags))
3901       FirstCommutableVecOp = 3;
3902 
3903     LastCommutableVecOp++;
3904   }
3905 
3906   if (isMem(MI, LastCommutableVecOp))
3907     LastCommutableVecOp--;
3908 
3909   // Only the first RegOpsNum operands are commutable.
3910   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3911   // that the operand is not specified/fixed.
3912   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3913       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
3914        SrcOpIdx1 == KMaskOp))
3915     return false;
3916   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3917       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
3918        SrcOpIdx2 == KMaskOp))
3919     return false;
3920 
3921   // Look for two different register operands assumed to be commutable
3922   // regardless of the FMA opcode. The FMA opcode is adjusted later.
3923   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3924       SrcOpIdx2 == CommuteAnyOperandIndex) {
3925     unsigned CommutableOpIdx1 = SrcOpIdx1;
3926     unsigned CommutableOpIdx2 = SrcOpIdx2;
3927 
3928     // At least one of operands to be commuted is not specified and
3929     // this method is free to choose appropriate commutable operands.
3930     if (SrcOpIdx1 == SrcOpIdx2)
3931       // Both of operands are not fixed. By default set one of commutable
3932       // operands to the last register operand of the instruction.
3933       CommutableOpIdx2 = LastCommutableVecOp;
3934     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3935       // Only one of operands is not fixed.
3936       CommutableOpIdx2 = SrcOpIdx1;
3937 
3938     // CommutableOpIdx2 is well defined now. Let's choose another commutable
3939     // operand and assign its index to CommutableOpIdx1.
3940     unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
3941     for (CommutableOpIdx1 = LastCommutableVecOp;
3942          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
3943       // Just ignore and skip the k-mask operand.
3944       if (CommutableOpIdx1 == KMaskOp)
3945         continue;
3946 
3947       // The commuted operands must have different registers.
3948       // Otherwise, the commute transformation does not change anything and
3949       // is useless then.
3950       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
3951         break;
3952     }
3953 
3954     // No appropriate commutable operands were found.
3955     if (CommutableOpIdx1 < FirstCommutableVecOp)
3956       return false;
3957 
3958     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3959     // to return those values.
3960     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3961                               CommutableOpIdx1, CommutableOpIdx2))
3962       return false;
3963   }
3964 
3965   return true;
3966 }
3967 
3968 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
3969                                          unsigned &SrcOpIdx2) const {
3970   const MCInstrDesc &Desc = MI.getDesc();
3971   if (!Desc.isCommutable())
3972     return false;
3973 
3974   switch (MI.getOpcode()) {
3975   case X86::CMPSDrr:
3976   case X86::CMPSSrr:
3977   case X86::CMPPDrri:
3978   case X86::CMPPSrri:
3979   case X86::VCMPSDrr:
3980   case X86::VCMPSSrr:
3981   case X86::VCMPPDrri:
3982   case X86::VCMPPSrri:
3983   case X86::VCMPPDYrri:
3984   case X86::VCMPPSYrri:
3985   case X86::VCMPSDZrr:
3986   case X86::VCMPSSZrr:
3987   case X86::VCMPPDZrri:
3988   case X86::VCMPPSZrri:
3989   case X86::VCMPPDZ128rri:
3990   case X86::VCMPPSZ128rri:
3991   case X86::VCMPPDZ256rri:
3992   case X86::VCMPPSZ256rri: {
3993     // Float comparison can be safely commuted for
3994     // Ordered/Unordered/Equal/NotEqual tests
3995     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3996     switch (Imm) {
3997     case 0x00: // EQUAL
3998     case 0x03: // UNORDERED
3999     case 0x04: // NOT EQUAL
4000     case 0x07: // ORDERED
4001       // The indices of the commutable operands are 1 and 2.
4002       // Assign them to the returned operand indices here.
4003       return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
4004     }
4005     return false;
4006   }
4007   case X86::MOVSDrr:
4008   case X86::MOVSSrr:
4009   case X86::VMOVSDrr:
4010   case X86::VMOVSSrr: {
4011     if (Subtarget.hasSSE41())
4012       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
4013     return false;
4014   }
4015   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
4016   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
4017   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
4018   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
4019   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
4020   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
4021   case X86::VPTERNLOGDZrrik:     case X86::VPTERNLOGDZrmik:
4022   case X86::VPTERNLOGDZ128rrik:  case X86::VPTERNLOGDZ128rmik:
4023   case X86::VPTERNLOGDZ256rrik:  case X86::VPTERNLOGDZ256rmik:
4024   case X86::VPTERNLOGQZrrik:     case X86::VPTERNLOGQZrmik:
4025   case X86::VPTERNLOGQZ128rrik:  case X86::VPTERNLOGQZ128rmik:
4026   case X86::VPTERNLOGQZ256rrik:  case X86::VPTERNLOGQZ256rmik:
4027   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
4028   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
4029   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
4030   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
4031   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
4032   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
4033     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
4034   default:
4035     const X86InstrFMA3Group *FMA3Group =
4036         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
4037     if (FMA3Group)
4038       return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2, *FMA3Group);
4039 
4040     // Handled masked instructions since we need to skip over the mask input
4041     // and the preserved input.
4042     if (Desc.TSFlags & X86II::EVEX_K) {
4043       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
4044       // If there is no preserved input we only need to skip 1 operand.
4045       if (MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
4046                                             MCOI::TIED_TO) != -1)
4047         ++CommutableOpIdx1;
4048       unsigned CommutableOpIdx2 = CommutableOpIdx1 + 1;
4049       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
4050                                 CommutableOpIdx1, CommutableOpIdx2))
4051         return false;
4052 
4053       if (!MI.getOperand(SrcOpIdx1).isReg() ||
4054           !MI.getOperand(SrcOpIdx2).isReg())
4055         // No idea.
4056         return false;
4057       return true;
4058     }
4059 
4060     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
4061   }
4062   return false;
4063 }
4064 
4065 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
4066   switch (BrOpc) {
4067   default: return X86::COND_INVALID;
4068   case X86::JE_1:  return X86::COND_E;
4069   case X86::JNE_1: return X86::COND_NE;
4070   case X86::JL_1:  return X86::COND_L;
4071   case X86::JLE_1: return X86::COND_LE;
4072   case X86::JG_1:  return X86::COND_G;
4073   case X86::JGE_1: return X86::COND_GE;
4074   case X86::JB_1:  return X86::COND_B;
4075   case X86::JBE_1: return X86::COND_BE;
4076   case X86::JA_1:  return X86::COND_A;
4077   case X86::JAE_1: return X86::COND_AE;
4078   case X86::JS_1:  return X86::COND_S;
4079   case X86::JNS_1: return X86::COND_NS;
4080   case X86::JP_1:  return X86::COND_P;
4081   case X86::JNP_1: return X86::COND_NP;
4082   case X86::JO_1:  return X86::COND_O;
4083   case X86::JNO_1: return X86::COND_NO;
4084   }
4085 }
4086 
4087 /// Return condition code of a SET opcode.
4088 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
4089   switch (Opc) {
4090   default: return X86::COND_INVALID;
4091   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
4092   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
4093   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
4094   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
4095   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
4096   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
4097   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
4098   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
4099   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
4100   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
4101   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
4102   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
4103   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
4104   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
4105   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
4106   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
4107   }
4108 }
4109 
4110 /// Return condition code of a CMov opcode.
4111 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
4112   switch (Opc) {
4113   default: return X86::COND_INVALID;
4114   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
4115   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
4116     return X86::COND_A;
4117   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
4118   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
4119     return X86::COND_AE;
4120   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
4121   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
4122     return X86::COND_B;
4123   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
4124   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
4125     return X86::COND_BE;
4126   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
4127   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
4128     return X86::COND_E;
4129   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
4130   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
4131     return X86::COND_G;
4132   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
4133   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
4134     return X86::COND_GE;
4135   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
4136   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
4137     return X86::COND_L;
4138   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
4139   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
4140     return X86::COND_LE;
4141   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
4142   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
4143     return X86::COND_NE;
4144   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
4145   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
4146     return X86::COND_NO;
4147   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
4148   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
4149     return X86::COND_NP;
4150   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
4151   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
4152     return X86::COND_NS;
4153   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
4154   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
4155     return X86::COND_O;
4156   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
4157   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
4158     return X86::COND_P;
4159   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
4160   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
4161     return X86::COND_S;
4162   }
4163 }
4164 
4165 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
4166   switch (CC) {
4167   default: llvm_unreachable("Illegal condition code!");
4168   case X86::COND_E:  return X86::JE_1;
4169   case X86::COND_NE: return X86::JNE_1;
4170   case X86::COND_L:  return X86::JL_1;
4171   case X86::COND_LE: return X86::JLE_1;
4172   case X86::COND_G:  return X86::JG_1;
4173   case X86::COND_GE: return X86::JGE_1;
4174   case X86::COND_B:  return X86::JB_1;
4175   case X86::COND_BE: return X86::JBE_1;
4176   case X86::COND_A:  return X86::JA_1;
4177   case X86::COND_AE: return X86::JAE_1;
4178   case X86::COND_S:  return X86::JS_1;
4179   case X86::COND_NS: return X86::JNS_1;
4180   case X86::COND_P:  return X86::JP_1;
4181   case X86::COND_NP: return X86::JNP_1;
4182   case X86::COND_O:  return X86::JO_1;
4183   case X86::COND_NO: return X86::JNO_1;
4184   }
4185 }
4186 
4187 /// Return the inverse of the specified condition,
4188 /// e.g. turning COND_E to COND_NE.
4189 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
4190   switch (CC) {
4191   default: llvm_unreachable("Illegal condition code!");
4192   case X86::COND_E:  return X86::COND_NE;
4193   case X86::COND_NE: return X86::COND_E;
4194   case X86::COND_L:  return X86::COND_GE;
4195   case X86::COND_LE: return X86::COND_G;
4196   case X86::COND_G:  return X86::COND_LE;
4197   case X86::COND_GE: return X86::COND_L;
4198   case X86::COND_B:  return X86::COND_AE;
4199   case X86::COND_BE: return X86::COND_A;
4200   case X86::COND_A:  return X86::COND_BE;
4201   case X86::COND_AE: return X86::COND_B;
4202   case X86::COND_S:  return X86::COND_NS;
4203   case X86::COND_NS: return X86::COND_S;
4204   case X86::COND_P:  return X86::COND_NP;
4205   case X86::COND_NP: return X86::COND_P;
4206   case X86::COND_O:  return X86::COND_NO;
4207   case X86::COND_NO: return X86::COND_O;
4208   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
4209   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
4210   }
4211 }
4212 
4213 /// Assuming the flags are set by MI(a,b), return the condition code if we
4214 /// modify the instructions such that flags are set by MI(b,a).
4215 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
4216   switch (CC) {
4217   default: return X86::COND_INVALID;
4218   case X86::COND_E:  return X86::COND_E;
4219   case X86::COND_NE: return X86::COND_NE;
4220   case X86::COND_L:  return X86::COND_G;
4221   case X86::COND_LE: return X86::COND_GE;
4222   case X86::COND_G:  return X86::COND_L;
4223   case X86::COND_GE: return X86::COND_LE;
4224   case X86::COND_B:  return X86::COND_A;
4225   case X86::COND_BE: return X86::COND_AE;
4226   case X86::COND_A:  return X86::COND_B;
4227   case X86::COND_AE: return X86::COND_BE;
4228   }
4229 }
4230 
4231 /// Return a set opcode for the given condition and
4232 /// whether it has memory operand.
4233 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
4234   static const uint16_t Opc[16][2] = {
4235     { X86::SETAr,  X86::SETAm  },
4236     { X86::SETAEr, X86::SETAEm },
4237     { X86::SETBr,  X86::SETBm  },
4238     { X86::SETBEr, X86::SETBEm },
4239     { X86::SETEr,  X86::SETEm  },
4240     { X86::SETGr,  X86::SETGm  },
4241     { X86::SETGEr, X86::SETGEm },
4242     { X86::SETLr,  X86::SETLm  },
4243     { X86::SETLEr, X86::SETLEm },
4244     { X86::SETNEr, X86::SETNEm },
4245     { X86::SETNOr, X86::SETNOm },
4246     { X86::SETNPr, X86::SETNPm },
4247     { X86::SETNSr, X86::SETNSm },
4248     { X86::SETOr,  X86::SETOm  },
4249     { X86::SETPr,  X86::SETPm  },
4250     { X86::SETSr,  X86::SETSm  }
4251   };
4252 
4253   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
4254   return Opc[CC][HasMemoryOperand ? 1 : 0];
4255 }
4256 
4257 /// Return a cmov opcode for the given condition,
4258 /// register size in bytes, and operand type.
4259 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
4260                               bool HasMemoryOperand) {
4261   static const uint16_t Opc[32][3] = {
4262     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
4263     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
4264     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
4265     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
4266     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
4267     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
4268     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
4269     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
4270     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
4271     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
4272     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
4273     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
4274     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
4275     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
4276     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
4277     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
4278     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
4279     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
4280     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
4281     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
4282     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
4283     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
4284     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
4285     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
4286     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
4287     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
4288     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
4289     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
4290     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
4291     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
4292     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
4293     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
4294   };
4295 
4296   assert(CC < 16 && "Can only handle standard cond codes");
4297   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
4298   switch(RegBytes) {
4299   default: llvm_unreachable("Illegal register size!");
4300   case 2: return Opc[Idx][0];
4301   case 4: return Opc[Idx][1];
4302   case 8: return Opc[Idx][2];
4303   }
4304 }
4305 
4306 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
4307   if (!MI.isTerminator()) return false;
4308 
4309   // Conditional branch is a special case.
4310   if (MI.isBranch() && !MI.isBarrier())
4311     return true;
4312   if (!MI.isPredicable())
4313     return true;
4314   return !isPredicated(MI);
4315 }
4316 
4317 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
4318   switch (MI.getOpcode()) {
4319   case X86::TCRETURNdi:
4320   case X86::TCRETURNri:
4321   case X86::TCRETURNmi:
4322   case X86::TCRETURNdi64:
4323   case X86::TCRETURNri64:
4324   case X86::TCRETURNmi64:
4325     return true;
4326   default:
4327     return false;
4328   }
4329 }
4330 
4331 bool X86InstrInfo::canMakeTailCallConditional(
4332     SmallVectorImpl<MachineOperand> &BranchCond,
4333     const MachineInstr &TailCall) const {
4334   if (TailCall.getOpcode() != X86::TCRETURNdi &&
4335       TailCall.getOpcode() != X86::TCRETURNdi64) {
4336     // Only direct calls can be done with a conditional branch.
4337     return false;
4338   }
4339 
4340   if (Subtarget.isTargetWin64()) {
4341     // Conditional tail calls confuse the Win64 unwinder.
4342     // TODO: Allow them for "leaf" functions; PR30337.
4343     return false;
4344   }
4345 
4346   assert(BranchCond.size() == 1);
4347   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
4348     // Can't make a conditional tail call with this condition.
4349     return false;
4350   }
4351 
4352   const X86MachineFunctionInfo *X86FI =
4353       TailCall.getParent()->getParent()->getInfo<X86MachineFunctionInfo>();
4354   if (X86FI->getTCReturnAddrDelta() != 0 ||
4355       TailCall.getOperand(1).getImm() != 0) {
4356     // A conditional tail call cannot do any stack adjustment.
4357     return false;
4358   }
4359 
4360   return true;
4361 }
4362 
4363 void X86InstrInfo::replaceBranchWithTailCall(
4364     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
4365     const MachineInstr &TailCall) const {
4366   assert(canMakeTailCallConditional(BranchCond, TailCall));
4367 
4368   MachineBasicBlock::iterator I = MBB.end();
4369   while (I != MBB.begin()) {
4370     --I;
4371     if (I->isDebugValue())
4372       continue;
4373     if (!I->isBranch())
4374       assert(0 && "Can't find the branch to replace!");
4375 
4376     X86::CondCode CC = getCondFromBranchOpc(I->getOpcode());
4377     assert(BranchCond.size() == 1);
4378     if (CC != BranchCond[0].getImm())
4379       continue;
4380 
4381     break;
4382   }
4383 
4384   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
4385                                                          : X86::TCRETURNdi64cc;
4386 
4387   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
4388   MIB->addOperand(TailCall.getOperand(0)); // Destination.
4389   MIB.addImm(0); // Stack offset (not used).
4390   MIB->addOperand(BranchCond[0]); // Condition.
4391   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
4392 
4393   I->eraseFromParent();
4394 }
4395 
4396 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
4397 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
4398 // fallthrough MBB cannot be identified.
4399 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
4400                                             MachineBasicBlock *TBB) {
4401   // Look for non-EHPad successors other than TBB. If we find exactly one, it
4402   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
4403   // and fallthrough MBB. If we find more than one, we cannot identify the
4404   // fallthrough MBB and should return nullptr.
4405   MachineBasicBlock *FallthroughBB = nullptr;
4406   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
4407     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
4408       continue;
4409     // Return a nullptr if we found more than one fallthrough successor.
4410     if (FallthroughBB && FallthroughBB != TBB)
4411       return nullptr;
4412     FallthroughBB = *SI;
4413   }
4414   return FallthroughBB;
4415 }
4416 
4417 bool X86InstrInfo::AnalyzeBranchImpl(
4418     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
4419     SmallVectorImpl<MachineOperand> &Cond,
4420     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
4421 
4422   // Start from the bottom of the block and work up, examining the
4423   // terminator instructions.
4424   MachineBasicBlock::iterator I = MBB.end();
4425   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
4426   while (I != MBB.begin()) {
4427     --I;
4428     if (I->isDebugValue())
4429       continue;
4430 
4431     // Working from the bottom, when we see a non-terminator instruction, we're
4432     // done.
4433     if (!isUnpredicatedTerminator(*I))
4434       break;
4435 
4436     // A terminator that isn't a branch can't easily be handled by this
4437     // analysis.
4438     if (!I->isBranch())
4439       return true;
4440 
4441     // Handle unconditional branches.
4442     if (I->getOpcode() == X86::JMP_1) {
4443       UnCondBrIter = I;
4444 
4445       if (!AllowModify) {
4446         TBB = I->getOperand(0).getMBB();
4447         continue;
4448       }
4449 
4450       // If the block has any instructions after a JMP, delete them.
4451       while (std::next(I) != MBB.end())
4452         std::next(I)->eraseFromParent();
4453 
4454       Cond.clear();
4455       FBB = nullptr;
4456 
4457       // Delete the JMP if it's equivalent to a fall-through.
4458       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
4459         TBB = nullptr;
4460         I->eraseFromParent();
4461         I = MBB.end();
4462         UnCondBrIter = MBB.end();
4463         continue;
4464       }
4465 
4466       // TBB is used to indicate the unconditional destination.
4467       TBB = I->getOperand(0).getMBB();
4468       continue;
4469     }
4470 
4471     // Handle conditional branches.
4472     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
4473     if (BranchCode == X86::COND_INVALID)
4474       return true;  // Can't handle indirect branch.
4475 
4476     // Working from the bottom, handle the first conditional branch.
4477     if (Cond.empty()) {
4478       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4479       if (AllowModify && UnCondBrIter != MBB.end() &&
4480           MBB.isLayoutSuccessor(TargetBB)) {
4481         // If we can modify the code and it ends in something like:
4482         //
4483         //     jCC L1
4484         //     jmp L2
4485         //   L1:
4486         //     ...
4487         //   L2:
4488         //
4489         // Then we can change this to:
4490         //
4491         //     jnCC L2
4492         //   L1:
4493         //     ...
4494         //   L2:
4495         //
4496         // Which is a bit more efficient.
4497         // We conditionally jump to the fall-through block.
4498         BranchCode = GetOppositeBranchCondition(BranchCode);
4499         unsigned JNCC = GetCondBranchFromCond(BranchCode);
4500         MachineBasicBlock::iterator OldInst = I;
4501 
4502         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
4503           .addMBB(UnCondBrIter->getOperand(0).getMBB());
4504         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
4505           .addMBB(TargetBB);
4506 
4507         OldInst->eraseFromParent();
4508         UnCondBrIter->eraseFromParent();
4509 
4510         // Restart the analysis.
4511         UnCondBrIter = MBB.end();
4512         I = MBB.end();
4513         continue;
4514       }
4515 
4516       FBB = TBB;
4517       TBB = I->getOperand(0).getMBB();
4518       Cond.push_back(MachineOperand::CreateImm(BranchCode));
4519       CondBranches.push_back(&*I);
4520       continue;
4521     }
4522 
4523     // Handle subsequent conditional branches. Only handle the case where all
4524     // conditional branches branch to the same destination and their condition
4525     // opcodes fit one of the special multi-branch idioms.
4526     assert(Cond.size() == 1);
4527     assert(TBB);
4528 
4529     // If the conditions are the same, we can leave them alone.
4530     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
4531     auto NewTBB = I->getOperand(0).getMBB();
4532     if (OldBranchCode == BranchCode && TBB == NewTBB)
4533       continue;
4534 
4535     // If they differ, see if they fit one of the known patterns. Theoretically,
4536     // we could handle more patterns here, but we shouldn't expect to see them
4537     // if instruction selection has done a reasonable job.
4538     if (TBB == NewTBB &&
4539                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4540                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
4541       BranchCode = X86::COND_NE_OR_P;
4542     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4543                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4544       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4545         return true;
4546 
4547       // X86::COND_E_AND_NP usually has two different branch destinations.
4548       //
4549       // JP B1
4550       // JE B2
4551       // JMP B1
4552       // B1:
4553       // B2:
4554       //
4555       // Here this condition branches to B2 only if NP && E. It has another
4556       // equivalent form:
4557       //
4558       // JNE B1
4559       // JNP B2
4560       // JMP B1
4561       // B1:
4562       // B2:
4563       //
4564       // Similarly it branches to B2 only if E && NP. That is why this condition
4565       // is named with COND_E_AND_NP.
4566       BranchCode = X86::COND_E_AND_NP;
4567     } else
4568       return true;
4569 
4570     // Update the MachineOperand.
4571     Cond[0].setImm(BranchCode);
4572     CondBranches.push_back(&*I);
4573   }
4574 
4575   return false;
4576 }
4577 
4578 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
4579                                  MachineBasicBlock *&TBB,
4580                                  MachineBasicBlock *&FBB,
4581                                  SmallVectorImpl<MachineOperand> &Cond,
4582                                  bool AllowModify) const {
4583   SmallVector<MachineInstr *, 4> CondBranches;
4584   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4585 }
4586 
4587 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
4588                                           MachineBranchPredicate &MBP,
4589                                           bool AllowModify) const {
4590   using namespace std::placeholders;
4591 
4592   SmallVector<MachineOperand, 4> Cond;
4593   SmallVector<MachineInstr *, 4> CondBranches;
4594   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4595                         AllowModify))
4596     return true;
4597 
4598   if (Cond.size() != 1)
4599     return true;
4600 
4601   assert(MBP.TrueDest && "expected!");
4602 
4603   if (!MBP.FalseDest)
4604     MBP.FalseDest = MBB.getNextNode();
4605 
4606   const TargetRegisterInfo *TRI = &getRegisterInfo();
4607 
4608   MachineInstr *ConditionDef = nullptr;
4609   bool SingleUseCondition = true;
4610 
4611   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4612     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4613       ConditionDef = &*I;
4614       break;
4615     }
4616 
4617     if (I->readsRegister(X86::EFLAGS, TRI))
4618       SingleUseCondition = false;
4619   }
4620 
4621   if (!ConditionDef)
4622     return true;
4623 
4624   if (SingleUseCondition) {
4625     for (auto *Succ : MBB.successors())
4626       if (Succ->isLiveIn(X86::EFLAGS))
4627         SingleUseCondition = false;
4628   }
4629 
4630   MBP.ConditionDef = ConditionDef;
4631   MBP.SingleUseCondition = SingleUseCondition;
4632 
4633   // Currently we only recognize the simple pattern:
4634   //
4635   //   test %reg, %reg
4636   //   je %label
4637   //
4638   const unsigned TestOpcode =
4639       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4640 
4641   if (ConditionDef->getOpcode() == TestOpcode &&
4642       ConditionDef->getNumOperands() == 3 &&
4643       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4644       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4645     MBP.LHS = ConditionDef->getOperand(0);
4646     MBP.RHS = MachineOperand::CreateImm(0);
4647     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4648                         ? MachineBranchPredicate::PRED_NE
4649                         : MachineBranchPredicate::PRED_EQ;
4650     return false;
4651   }
4652 
4653   return true;
4654 }
4655 
4656 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
4657                                     int *BytesRemoved) const {
4658   assert(!BytesRemoved && "code size not handled");
4659 
4660   MachineBasicBlock::iterator I = MBB.end();
4661   unsigned Count = 0;
4662 
4663   while (I != MBB.begin()) {
4664     --I;
4665     if (I->isDebugValue())
4666       continue;
4667     if (I->getOpcode() != X86::JMP_1 &&
4668         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
4669       break;
4670     // Remove the branch.
4671     I->eraseFromParent();
4672     I = MBB.end();
4673     ++Count;
4674   }
4675 
4676   return Count;
4677 }
4678 
4679 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
4680                                     MachineBasicBlock *TBB,
4681                                     MachineBasicBlock *FBB,
4682                                     ArrayRef<MachineOperand> Cond,
4683                                     const DebugLoc &DL,
4684                                     int *BytesAdded) const {
4685   // Shouldn't be a fall through.
4686   assert(TBB && "insertBranch must not be told to insert a fallthrough");
4687   assert((Cond.size() == 1 || Cond.size() == 0) &&
4688          "X86 branch conditions have one component!");
4689   assert(!BytesAdded && "code size not handled");
4690 
4691   if (Cond.empty()) {
4692     // Unconditional branch?
4693     assert(!FBB && "Unconditional branch with multiple successors!");
4694     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
4695     return 1;
4696   }
4697 
4698   // If FBB is null, it is implied to be a fall-through block.
4699   bool FallThru = FBB == nullptr;
4700 
4701   // Conditional branch.
4702   unsigned Count = 0;
4703   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4704   switch (CC) {
4705   case X86::COND_NE_OR_P:
4706     // Synthesize NE_OR_P with two branches.
4707     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
4708     ++Count;
4709     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
4710     ++Count;
4711     break;
4712   case X86::COND_E_AND_NP:
4713     // Use the next block of MBB as FBB if it is null.
4714     if (FBB == nullptr) {
4715       FBB = getFallThroughMBB(&MBB, TBB);
4716       assert(FBB && "MBB cannot be the last block in function when the false "
4717                     "body is a fall-through.");
4718     }
4719     // Synthesize COND_E_AND_NP with two branches.
4720     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4721     ++Count;
4722     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4723     ++Count;
4724     break;
4725   default: {
4726     unsigned Opc = GetCondBranchFromCond(CC);
4727     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
4728     ++Count;
4729   }
4730   }
4731   if (!FallThru) {
4732     // Two-way Conditional branch. Insert the second branch.
4733     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
4734     ++Count;
4735   }
4736   return Count;
4737 }
4738 
4739 bool X86InstrInfo::
4740 canInsertSelect(const MachineBasicBlock &MBB,
4741                 ArrayRef<MachineOperand> Cond,
4742                 unsigned TrueReg, unsigned FalseReg,
4743                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4744   // Not all subtargets have cmov instructions.
4745   if (!Subtarget.hasCMov())
4746     return false;
4747   if (Cond.size() != 1)
4748     return false;
4749   // We cannot do the composite conditions, at least not in SSA form.
4750   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4751     return false;
4752 
4753   // Check register classes.
4754   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4755   const TargetRegisterClass *RC =
4756     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4757   if (!RC)
4758     return false;
4759 
4760   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4761   if (X86::GR16RegClass.hasSubClassEq(RC) ||
4762       X86::GR32RegClass.hasSubClassEq(RC) ||
4763       X86::GR64RegClass.hasSubClassEq(RC)) {
4764     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4765     // Bridge. Probably Ivy Bridge as well.
4766     CondCycles = 2;
4767     TrueCycles = 2;
4768     FalseCycles = 2;
4769     return true;
4770   }
4771 
4772   // Can't do vectors.
4773   return false;
4774 }
4775 
4776 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4777                                 MachineBasicBlock::iterator I,
4778                                 const DebugLoc &DL, unsigned DstReg,
4779                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
4780                                 unsigned FalseReg) const {
4781   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4782   assert(Cond.size() == 1 && "Invalid Cond array");
4783   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4784                                  MRI.getRegClass(DstReg)->getSize(),
4785                                  false /*HasMemoryOperand*/);
4786   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
4787 }
4788 
4789 /// Test if the given register is a physical h register.
4790 static bool isHReg(unsigned Reg) {
4791   return X86::GR8_ABCD_HRegClass.contains(Reg);
4792 }
4793 
4794 // Try and copy between VR128/VR64 and GR64 registers.
4795 static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg,
4796                                         const X86Subtarget &Subtarget) {
4797   bool HasAVX = Subtarget.hasAVX();
4798   bool HasAVX512 = Subtarget.hasAVX512();
4799 
4800   // SrcReg(MaskReg) -> DestReg(GR64)
4801   // SrcReg(MaskReg) -> DestReg(GR32)
4802   // SrcReg(MaskReg) -> DestReg(GR16)
4803   // SrcReg(MaskReg) -> DestReg(GR8)
4804 
4805   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4806   if (X86::VK16RegClass.contains(SrcReg)) {
4807     if (X86::GR64RegClass.contains(DestReg)) {
4808       assert(Subtarget.hasBWI());
4809       return X86::KMOVQrk;
4810     }
4811     if (X86::GR32RegClass.contains(DestReg))
4812       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
4813     if (X86::GR16RegClass.contains(DestReg)) {
4814       DestReg = getX86SubSuperRegister(DestReg, 32);
4815       return X86::KMOVWrk;
4816     }
4817     if (X86::GR8RegClass.contains(DestReg)) {
4818       DestReg = getX86SubSuperRegister(DestReg, 32);
4819       return Subtarget.hasDQI() ? X86::KMOVBrk : X86::KMOVWrk;
4820     }
4821   }
4822 
4823   // SrcReg(GR64) -> DestReg(MaskReg)
4824   // SrcReg(GR32) -> DestReg(MaskReg)
4825   // SrcReg(GR16) -> DestReg(MaskReg)
4826   // SrcReg(GR8)  -> DestReg(MaskReg)
4827 
4828   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4829   if (X86::VK16RegClass.contains(DestReg)) {
4830     if (X86::GR64RegClass.contains(SrcReg)) {
4831       assert(Subtarget.hasBWI());
4832       return X86::KMOVQkr;
4833     }
4834     if (X86::GR32RegClass.contains(SrcReg))
4835       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
4836     if (X86::GR16RegClass.contains(SrcReg)) {
4837       SrcReg = getX86SubSuperRegister(SrcReg, 32);
4838       return X86::KMOVWkr;
4839     }
4840     if (X86::GR8RegClass.contains(SrcReg)) {
4841       SrcReg = getX86SubSuperRegister(SrcReg, 32);
4842       return Subtarget.hasDQI() ? X86::KMOVBkr : X86::KMOVWkr;
4843     }
4844   }
4845 
4846 
4847   // SrcReg(VR128) -> DestReg(GR64)
4848   // SrcReg(VR64)  -> DestReg(GR64)
4849   // SrcReg(GR64)  -> DestReg(VR128)
4850   // SrcReg(GR64)  -> DestReg(VR64)
4851 
4852   if (X86::GR64RegClass.contains(DestReg)) {
4853     if (X86::VR128XRegClass.contains(SrcReg))
4854       // Copy from a VR128 register to a GR64 register.
4855       return HasAVX512 ? X86::VMOVPQIto64Zrr :
4856              HasAVX    ? X86::VMOVPQIto64rr  :
4857                          X86::MOVPQIto64rr;
4858     if (X86::VR64RegClass.contains(SrcReg))
4859       // Copy from a VR64 register to a GR64 register.
4860       return X86::MMX_MOVD64from64rr;
4861   } else if (X86::GR64RegClass.contains(SrcReg)) {
4862     // Copy from a GR64 register to a VR128 register.
4863     if (X86::VR128XRegClass.contains(DestReg))
4864       return HasAVX512 ? X86::VMOV64toPQIZrr :
4865              HasAVX    ? X86::VMOV64toPQIrr  :
4866                          X86::MOV64toPQIrr;
4867     // Copy from a GR64 register to a VR64 register.
4868     if (X86::VR64RegClass.contains(DestReg))
4869       return X86::MMX_MOVD64to64rr;
4870   }
4871 
4872   // SrcReg(FR32) -> DestReg(GR32)
4873   // SrcReg(GR32) -> DestReg(FR32)
4874 
4875   if (X86::GR32RegClass.contains(DestReg) &&
4876       X86::FR32XRegClass.contains(SrcReg))
4877     // Copy from a FR32 register to a GR32 register.
4878     return HasAVX512 ? X86::VMOVSS2DIZrr :
4879            HasAVX    ? X86::VMOVSS2DIrr  :
4880                        X86::MOVSS2DIrr;
4881 
4882   if (X86::FR32XRegClass.contains(DestReg) &&
4883       X86::GR32RegClass.contains(SrcReg))
4884     // Copy from a GR32 register to a FR32 register.
4885     return HasAVX512 ? X86::VMOVDI2SSZrr :
4886            HasAVX    ? X86::VMOVDI2SSrr  :
4887                        X86::MOVDI2SSrr;
4888   return 0;
4889 }
4890 
4891 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4892                                MachineBasicBlock::iterator MI,
4893                                const DebugLoc &DL, unsigned DestReg,
4894                                unsigned SrcReg, bool KillSrc) const {
4895   // First deal with the normal symmetric copies.
4896   bool HasAVX = Subtarget.hasAVX();
4897   bool HasVLX = Subtarget.hasVLX();
4898   unsigned Opc = 0;
4899   if (X86::GR64RegClass.contains(DestReg, SrcReg))
4900     Opc = X86::MOV64rr;
4901   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4902     Opc = X86::MOV32rr;
4903   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4904     Opc = X86::MOV16rr;
4905   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4906     // Copying to or from a physical H register on x86-64 requires a NOREX
4907     // move.  Otherwise use a normal move.
4908     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
4909         Subtarget.is64Bit()) {
4910       Opc = X86::MOV8rr_NOREX;
4911       // Both operands must be encodable without an REX prefix.
4912       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4913              "8-bit H register can not be copied outside GR8_NOREX");
4914     } else
4915       Opc = X86::MOV8rr;
4916   }
4917   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4918     Opc = X86::MMX_MOVQ64rr;
4919   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
4920     if (HasVLX)
4921       Opc = X86::VMOVAPSZ128rr;
4922     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
4923       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
4924     else {
4925       // If this an extended register and we don't have VLX we need to use a
4926       // 512-bit move.
4927       Opc = X86::VMOVAPSZrr;
4928       const TargetRegisterInfo *TRI = &getRegisterInfo();
4929       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
4930                                          &X86::VR512RegClass);
4931       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
4932                                         &X86::VR512RegClass);
4933     }
4934   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
4935     if (HasVLX)
4936       Opc = X86::VMOVAPSZ256rr;
4937     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4938       Opc = X86::VMOVAPSYrr;
4939     else {
4940       // If this an extended register and we don't have VLX we need to use a
4941       // 512-bit move.
4942       Opc = X86::VMOVAPSZrr;
4943       const TargetRegisterInfo *TRI = &getRegisterInfo();
4944       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
4945                                          &X86::VR512RegClass);
4946       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
4947                                         &X86::VR512RegClass);
4948     }
4949   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
4950     Opc = X86::VMOVAPSZrr;
4951   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4952   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
4953     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
4954   if (!Opc)
4955     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4956 
4957   if (Opc) {
4958     BuildMI(MBB, MI, DL, get(Opc), DestReg)
4959       .addReg(SrcReg, getKillRegState(KillSrc));
4960     return;
4961   }
4962 
4963   bool FromEFLAGS = SrcReg == X86::EFLAGS;
4964   bool ToEFLAGS = DestReg == X86::EFLAGS;
4965   int Reg = FromEFLAGS ? DestReg : SrcReg;
4966   bool is32 = X86::GR32RegClass.contains(Reg);
4967   bool is64 = X86::GR64RegClass.contains(Reg);
4968 
4969   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
4970     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4971     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4972     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4973     int Pop = is64 ? X86::POP64r : X86::POP32r;
4974     int PopF = is64 ? X86::POPF64 : X86::POPF32;
4975     int AX = is64 ? X86::RAX : X86::EAX;
4976 
4977     if (!Subtarget.hasLAHFSAHF()) {
4978       assert(Subtarget.is64Bit() &&
4979              "Not having LAHF/SAHF only happens on 64-bit.");
4980       // Moving EFLAGS to / from another register requires a push and a pop.
4981       // Notice that we have to adjust the stack if we don't want to clobber the
4982       // first frame index. See X86FrameLowering.cpp - usesTheStack.
4983       if (FromEFLAGS) {
4984         BuildMI(MBB, MI, DL, get(PushF));
4985         BuildMI(MBB, MI, DL, get(Pop), DestReg);
4986       }
4987       if (ToEFLAGS) {
4988         BuildMI(MBB, MI, DL, get(Push))
4989             .addReg(SrcReg, getKillRegState(KillSrc));
4990         BuildMI(MBB, MI, DL, get(PopF));
4991       }
4992       return;
4993     }
4994 
4995     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4996     // inefficient. Instead:
4997     //   - Save the overflow flag OF into AL using SETO, and restore it using a
4998     //     signed 8-bit addition of AL and INT8_MAX.
4999     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
5000     //     using LAHF/SAHF.
5001     //   - When RAX/EAX is live and isn't the destination register, make sure it
5002     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
5003     //     the flags.
5004     // This approach is ~2.25x faster than using PUSHF/POPF.
5005     //
5006     // This is still somewhat inefficient because we don't know which flags are
5007     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
5008     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
5009     //
5010     // PUSHF/POPF is also potentially incorrect because it affects other flags
5011     // such as TF/IF/DF, which LLVM doesn't model.
5012     //
5013     // Notice that we have to adjust the stack if we don't want to clobber the
5014     // first frame index.
5015     // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
5016 
5017     const TargetRegisterInfo *TRI = &getRegisterInfo();
5018     MachineBasicBlock::LivenessQueryResult LQR =
5019         MBB.computeRegisterLiveness(TRI, AX, MI);
5020     // We do not want to save and restore AX if we do not have to.
5021     // Moreover, if we do so whereas AX is dead, we would need to set
5022     // an undef flag on the use of AX, otherwise the verifier will
5023     // complain that we read an undef value.
5024     // We do not want to change the behavior of the machine verifier
5025     // as this is usually wrong to read an undef value.
5026     if (MachineBasicBlock::LQR_Unknown == LQR) {
5027       LivePhysRegs LPR(TRI);
5028       LPR.addLiveOuts(MBB);
5029       MachineBasicBlock::iterator I = MBB.end();
5030       while (I != MI) {
5031         --I;
5032         LPR.stepBackward(*I);
5033       }
5034       // AX contains the top most register in the aliasing hierarchy.
5035       // It may not be live, but one of its aliases may be.
5036       for (MCRegAliasIterator AI(AX, TRI, true);
5037            AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
5038         LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
5039                                 : MachineBasicBlock::LQR_Dead;
5040     }
5041     bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
5042     if (!AXDead)
5043       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
5044     if (FromEFLAGS) {
5045       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
5046       BuildMI(MBB, MI, DL, get(X86::LAHF));
5047       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
5048     }
5049     if (ToEFLAGS) {
5050       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
5051       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
5052           .addReg(X86::AL)
5053           .addImm(INT8_MAX);
5054       BuildMI(MBB, MI, DL, get(X86::SAHF));
5055     }
5056     if (!AXDead)
5057       BuildMI(MBB, MI, DL, get(Pop), AX);
5058     return;
5059   }
5060 
5061   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
5062                << " to " << RI.getName(DestReg) << '\n');
5063   llvm_unreachable("Cannot emit physreg copy instruction");
5064 }
5065 
5066 static unsigned getLoadStoreRegOpcode(unsigned Reg,
5067                                       const TargetRegisterClass *RC,
5068                                       bool isStackAligned,
5069                                       const X86Subtarget &STI,
5070                                       bool load) {
5071   bool HasAVX = STI.hasAVX();
5072   bool HasAVX512 = STI.hasAVX512();
5073   bool HasVLX = STI.hasVLX();
5074 
5075   switch (RC->getSize()) {
5076   default:
5077     llvm_unreachable("Unknown spill size");
5078   case 1:
5079     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
5080     if (STI.is64Bit())
5081       // Copying to or from a physical H register on x86-64 requires a NOREX
5082       // move.  Otherwise use a normal move.
5083       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
5084         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
5085     return load ? X86::MOV8rm : X86::MOV8mr;
5086   case 2:
5087     if (X86::VK16RegClass.hasSubClassEq(RC))
5088       return load ? X86::KMOVWkm : X86::KMOVWmk;
5089     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
5090     return load ? X86::MOV16rm : X86::MOV16mr;
5091   case 4:
5092     if (X86::GR32RegClass.hasSubClassEq(RC))
5093       return load ? X86::MOV32rm : X86::MOV32mr;
5094     if (X86::FR32XRegClass.hasSubClassEq(RC))
5095       return load ?
5096         (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
5097         (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
5098     if (X86::RFP32RegClass.hasSubClassEq(RC))
5099       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
5100     if (X86::VK32RegClass.hasSubClassEq(RC))
5101       return load ? X86::KMOVDkm : X86::KMOVDmk;
5102     llvm_unreachable("Unknown 4-byte regclass");
5103   case 8:
5104     if (X86::GR64RegClass.hasSubClassEq(RC))
5105       return load ? X86::MOV64rm : X86::MOV64mr;
5106     if (X86::FR64XRegClass.hasSubClassEq(RC))
5107       return load ?
5108         (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
5109         (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
5110     if (X86::VR64RegClass.hasSubClassEq(RC))
5111       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
5112     if (X86::RFP64RegClass.hasSubClassEq(RC))
5113       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
5114     if (X86::VK64RegClass.hasSubClassEq(RC))
5115       return load ? X86::KMOVQkm : X86::KMOVQmk;
5116     llvm_unreachable("Unknown 8-byte regclass");
5117   case 10:
5118     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
5119     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
5120   case 16: {
5121     assert(X86::VR128XRegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
5122     // If stack is realigned we can use aligned stores.
5123     if (isStackAligned)
5124       return load ?
5125         (HasVLX    ? X86::VMOVAPSZ128rm :
5126          HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
5127          HasAVX    ? X86::VMOVAPSrm :
5128                      X86::MOVAPSrm):
5129         (HasVLX    ? X86::VMOVAPSZ128mr :
5130          HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
5131          HasAVX    ? X86::VMOVAPSmr :
5132                      X86::MOVAPSmr);
5133     else
5134       return load ?
5135         (HasVLX    ? X86::VMOVUPSZ128rm :
5136          HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
5137          HasAVX    ? X86::VMOVUPSrm :
5138                      X86::MOVUPSrm):
5139         (HasVLX    ? X86::VMOVUPSZ128mr :
5140          HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
5141          HasAVX    ? X86::VMOVUPSmr :
5142                      X86::MOVUPSmr);
5143   }
5144   case 32:
5145     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
5146     // If stack is realigned we can use aligned stores.
5147     if (isStackAligned)
5148       return load ?
5149         (HasVLX    ? X86::VMOVAPSZ256rm :
5150          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
5151                      X86::VMOVAPSYrm) :
5152         (HasVLX    ? X86::VMOVAPSZ256mr :
5153          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
5154                      X86::VMOVAPSYmr);
5155     else
5156       return load ?
5157         (HasVLX    ? X86::VMOVUPSZ256rm :
5158          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
5159                      X86::VMOVUPSYrm) :
5160         (HasVLX    ? X86::VMOVUPSZ256mr :
5161          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
5162                      X86::VMOVUPSYmr);
5163   case 64:
5164     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
5165     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
5166     if (isStackAligned)
5167       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
5168     else
5169       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
5170   }
5171 }
5172 
5173 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
5174                                          int64_t &Offset,
5175                                          const TargetRegisterInfo *TRI) const {
5176   const MCInstrDesc &Desc = MemOp.getDesc();
5177   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
5178   if (MemRefBegin < 0)
5179     return false;
5180 
5181   MemRefBegin += X86II::getOperandBias(Desc);
5182 
5183   MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
5184   if (!BaseMO.isReg()) // Can be an MO_FrameIndex
5185     return false;
5186 
5187   BaseReg = BaseMO.getReg();
5188   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
5189     return false;
5190 
5191   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
5192       X86::NoRegister)
5193     return false;
5194 
5195   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
5196 
5197   // Displacement can be symbolic
5198   if (!DispMO.isImm())
5199     return false;
5200 
5201   Offset = DispMO.getImm();
5202 
5203   return MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
5204          X86::NoRegister;
5205 }
5206 
5207 static unsigned getStoreRegOpcode(unsigned SrcReg,
5208                                   const TargetRegisterClass *RC,
5209                                   bool isStackAligned,
5210                                   const X86Subtarget &STI) {
5211   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
5212 }
5213 
5214 
5215 static unsigned getLoadRegOpcode(unsigned DestReg,
5216                                  const TargetRegisterClass *RC,
5217                                  bool isStackAligned,
5218                                  const X86Subtarget &STI) {
5219   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
5220 }
5221 
5222 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
5223                                        MachineBasicBlock::iterator MI,
5224                                        unsigned SrcReg, bool isKill, int FrameIdx,
5225                                        const TargetRegisterClass *RC,
5226                                        const TargetRegisterInfo *TRI) const {
5227   const MachineFunction &MF = *MBB.getParent();
5228   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= RC->getSize() &&
5229          "Stack slot too small for store");
5230   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
5231   bool isAligned =
5232       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
5233       RI.canRealignStack(MF);
5234   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
5235   DebugLoc DL = MBB.findDebugLoc(MI);
5236   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
5237     .addReg(SrcReg, getKillRegState(isKill));
5238 }
5239 
5240 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
5241                                   bool isKill,
5242                                   SmallVectorImpl<MachineOperand> &Addr,
5243                                   const TargetRegisterClass *RC,
5244                                   MachineInstr::mmo_iterator MMOBegin,
5245                                   MachineInstr::mmo_iterator MMOEnd,
5246                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
5247   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
5248   bool isAligned = MMOBegin != MMOEnd &&
5249                    (*MMOBegin)->getAlignment() >= Alignment;
5250   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
5251   DebugLoc DL;
5252   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
5253   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
5254     MIB.addOperand(Addr[i]);
5255   MIB.addReg(SrcReg, getKillRegState(isKill));
5256   (*MIB).setMemRefs(MMOBegin, MMOEnd);
5257   NewMIs.push_back(MIB);
5258 }
5259 
5260 
5261 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
5262                                         MachineBasicBlock::iterator MI,
5263                                         unsigned DestReg, int FrameIdx,
5264                                         const TargetRegisterClass *RC,
5265                                         const TargetRegisterInfo *TRI) const {
5266   const MachineFunction &MF = *MBB.getParent();
5267   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
5268   bool isAligned =
5269       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
5270       RI.canRealignStack(MF);
5271   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
5272   DebugLoc DL = MBB.findDebugLoc(MI);
5273   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
5274 }
5275 
5276 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
5277                                  SmallVectorImpl<MachineOperand> &Addr,
5278                                  const TargetRegisterClass *RC,
5279                                  MachineInstr::mmo_iterator MMOBegin,
5280                                  MachineInstr::mmo_iterator MMOEnd,
5281                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
5282   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
5283   bool isAligned = MMOBegin != MMOEnd &&
5284                    (*MMOBegin)->getAlignment() >= Alignment;
5285   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
5286   DebugLoc DL;
5287   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
5288   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
5289     MIB.addOperand(Addr[i]);
5290   (*MIB).setMemRefs(MMOBegin, MMOEnd);
5291   NewMIs.push_back(MIB);
5292 }
5293 
5294 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
5295                                   unsigned &SrcReg2, int &CmpMask,
5296                                   int &CmpValue) const {
5297   switch (MI.getOpcode()) {
5298   default: break;
5299   case X86::CMP64ri32:
5300   case X86::CMP64ri8:
5301   case X86::CMP32ri:
5302   case X86::CMP32ri8:
5303   case X86::CMP16ri:
5304   case X86::CMP16ri8:
5305   case X86::CMP8ri:
5306     if (!MI.getOperand(1).isImm())
5307       return false;
5308     SrcReg = MI.getOperand(0).getReg();
5309     SrcReg2 = 0;
5310     CmpMask = ~0;
5311     CmpValue = MI.getOperand(1).getImm();
5312     return true;
5313   // A SUB can be used to perform comparison.
5314   case X86::SUB64rm:
5315   case X86::SUB32rm:
5316   case X86::SUB16rm:
5317   case X86::SUB8rm:
5318     SrcReg = MI.getOperand(1).getReg();
5319     SrcReg2 = 0;
5320     CmpMask = ~0;
5321     CmpValue = 0;
5322     return true;
5323   case X86::SUB64rr:
5324   case X86::SUB32rr:
5325   case X86::SUB16rr:
5326   case X86::SUB8rr:
5327     SrcReg = MI.getOperand(1).getReg();
5328     SrcReg2 = MI.getOperand(2).getReg();
5329     CmpMask = ~0;
5330     CmpValue = 0;
5331     return true;
5332   case X86::SUB64ri32:
5333   case X86::SUB64ri8:
5334   case X86::SUB32ri:
5335   case X86::SUB32ri8:
5336   case X86::SUB16ri:
5337   case X86::SUB16ri8:
5338   case X86::SUB8ri:
5339     if (!MI.getOperand(2).isImm())
5340       return false;
5341     SrcReg = MI.getOperand(1).getReg();
5342     SrcReg2 = 0;
5343     CmpMask = ~0;
5344     CmpValue = MI.getOperand(2).getImm();
5345     return true;
5346   case X86::CMP64rr:
5347   case X86::CMP32rr:
5348   case X86::CMP16rr:
5349   case X86::CMP8rr:
5350     SrcReg = MI.getOperand(0).getReg();
5351     SrcReg2 = MI.getOperand(1).getReg();
5352     CmpMask = ~0;
5353     CmpValue = 0;
5354     return true;
5355   case X86::TEST8rr:
5356   case X86::TEST16rr:
5357   case X86::TEST32rr:
5358   case X86::TEST64rr:
5359     SrcReg = MI.getOperand(0).getReg();
5360     if (MI.getOperand(1).getReg() != SrcReg)
5361       return false;
5362     // Compare against zero.
5363     SrcReg2 = 0;
5364     CmpMask = ~0;
5365     CmpValue = 0;
5366     return true;
5367   }
5368   return false;
5369 }
5370 
5371 /// Check whether the first instruction, whose only
5372 /// purpose is to update flags, can be made redundant.
5373 /// CMPrr can be made redundant by SUBrr if the operands are the same.
5374 /// This function can be extended later on.
5375 /// SrcReg, SrcRegs: register operands for FlagI.
5376 /// ImmValue: immediate for FlagI if it takes an immediate.
5377 inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
5378                                         unsigned SrcReg2, int ImmValue,
5379                                         MachineInstr &OI) {
5380   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
5381        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
5382        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
5383        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
5384       ((OI.getOperand(1).getReg() == SrcReg &&
5385         OI.getOperand(2).getReg() == SrcReg2) ||
5386        (OI.getOperand(1).getReg() == SrcReg2 &&
5387         OI.getOperand(2).getReg() == SrcReg)))
5388     return true;
5389 
5390   if (((FlagI.getOpcode() == X86::CMP64ri32 &&
5391         OI.getOpcode() == X86::SUB64ri32) ||
5392        (FlagI.getOpcode() == X86::CMP64ri8 &&
5393         OI.getOpcode() == X86::SUB64ri8) ||
5394        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
5395        (FlagI.getOpcode() == X86::CMP32ri8 &&
5396         OI.getOpcode() == X86::SUB32ri8) ||
5397        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
5398        (FlagI.getOpcode() == X86::CMP16ri8 &&
5399         OI.getOpcode() == X86::SUB16ri8) ||
5400        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
5401       OI.getOperand(1).getReg() == SrcReg &&
5402       OI.getOperand(2).getImm() == ImmValue)
5403     return true;
5404   return false;
5405 }
5406 
5407 /// Check whether the definition can be converted
5408 /// to remove a comparison against zero.
5409 inline static bool isDefConvertible(MachineInstr &MI) {
5410   switch (MI.getOpcode()) {
5411   default: return false;
5412 
5413   // The shift instructions only modify ZF if their shift count is non-zero.
5414   // N.B.: The processor truncates the shift count depending on the encoding.
5415   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
5416   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
5417      return getTruncatedShiftCount(MI, 2) != 0;
5418 
5419   // Some left shift instructions can be turned into LEA instructions but only
5420   // if their flags aren't used. Avoid transforming such instructions.
5421   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
5422     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
5423     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
5424     return ShAmt != 0;
5425   }
5426 
5427   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
5428   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
5429      return getTruncatedShiftCount(MI, 3) != 0;
5430 
5431   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
5432   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
5433   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
5434   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
5435   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
5436   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
5437   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
5438   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
5439   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
5440   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
5441   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
5442   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
5443   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
5444   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
5445   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
5446   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
5447   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
5448   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
5449   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
5450   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
5451   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
5452   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
5453   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
5454   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
5455   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
5456   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
5457   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
5458   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
5459   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
5460   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
5461   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
5462   case X86::ADC32ri:   case X86::ADC32ri8:
5463   case X86::ADC32rr:   case X86::ADC64ri32:
5464   case X86::ADC64ri8:  case X86::ADC64rr:
5465   case X86::SBB32ri:   case X86::SBB32ri8:
5466   case X86::SBB32rr:   case X86::SBB64ri32:
5467   case X86::SBB64ri8:  case X86::SBB64rr:
5468   case X86::ANDN32rr:  case X86::ANDN32rm:
5469   case X86::ANDN64rr:  case X86::ANDN64rm:
5470   case X86::BEXTR32rr: case X86::BEXTR64rr:
5471   case X86::BEXTR32rm: case X86::BEXTR64rm:
5472   case X86::BLSI32rr:  case X86::BLSI32rm:
5473   case X86::BLSI64rr:  case X86::BLSI64rm:
5474   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
5475   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
5476   case X86::BLSR32rr:  case X86::BLSR32rm:
5477   case X86::BLSR64rr:  case X86::BLSR64rm:
5478   case X86::BZHI32rr:  case X86::BZHI32rm:
5479   case X86::BZHI64rr:  case X86::BZHI64rm:
5480   case X86::LZCNT16rr: case X86::LZCNT16rm:
5481   case X86::LZCNT32rr: case X86::LZCNT32rm:
5482   case X86::LZCNT64rr: case X86::LZCNT64rm:
5483   case X86::POPCNT16rr:case X86::POPCNT16rm:
5484   case X86::POPCNT32rr:case X86::POPCNT32rm:
5485   case X86::POPCNT64rr:case X86::POPCNT64rm:
5486   case X86::TZCNT16rr: case X86::TZCNT16rm:
5487   case X86::TZCNT32rr: case X86::TZCNT32rm:
5488   case X86::TZCNT64rr: case X86::TZCNT64rm:
5489     return true;
5490   }
5491 }
5492 
5493 /// Check whether the use can be converted to remove a comparison against zero.
5494 static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
5495   switch (MI.getOpcode()) {
5496   default: return X86::COND_INVALID;
5497   case X86::LZCNT16rr: case X86::LZCNT16rm:
5498   case X86::LZCNT32rr: case X86::LZCNT32rm:
5499   case X86::LZCNT64rr: case X86::LZCNT64rm:
5500     return X86::COND_B;
5501   case X86::POPCNT16rr:case X86::POPCNT16rm:
5502   case X86::POPCNT32rr:case X86::POPCNT32rm:
5503   case X86::POPCNT64rr:case X86::POPCNT64rm:
5504     return X86::COND_E;
5505   case X86::TZCNT16rr: case X86::TZCNT16rm:
5506   case X86::TZCNT32rr: case X86::TZCNT32rm:
5507   case X86::TZCNT64rr: case X86::TZCNT64rm:
5508     return X86::COND_B;
5509   }
5510 }
5511 
5512 /// Check if there exists an earlier instruction that
5513 /// operates on the same source operands and sets flags in the same way as
5514 /// Compare; remove Compare if possible.
5515 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
5516                                         unsigned SrcReg2, int CmpMask,
5517                                         int CmpValue,
5518                                         const MachineRegisterInfo *MRI) const {
5519   // Check whether we can replace SUB with CMP.
5520   unsigned NewOpcode = 0;
5521   switch (CmpInstr.getOpcode()) {
5522   default: break;
5523   case X86::SUB64ri32:
5524   case X86::SUB64ri8:
5525   case X86::SUB32ri:
5526   case X86::SUB32ri8:
5527   case X86::SUB16ri:
5528   case X86::SUB16ri8:
5529   case X86::SUB8ri:
5530   case X86::SUB64rm:
5531   case X86::SUB32rm:
5532   case X86::SUB16rm:
5533   case X86::SUB8rm:
5534   case X86::SUB64rr:
5535   case X86::SUB32rr:
5536   case X86::SUB16rr:
5537   case X86::SUB8rr: {
5538     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
5539       return false;
5540     // There is no use of the destination register, we can replace SUB with CMP.
5541     switch (CmpInstr.getOpcode()) {
5542     default: llvm_unreachable("Unreachable!");
5543     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
5544     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
5545     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
5546     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
5547     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
5548     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
5549     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
5550     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
5551     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5552     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
5553     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
5554     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
5555     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
5556     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
5557     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
5558     }
5559     CmpInstr.setDesc(get(NewOpcode));
5560     CmpInstr.RemoveOperand(0);
5561     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5562     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5563         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5564       return false;
5565   }
5566   }
5567 
5568   // Get the unique definition of SrcReg.
5569   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5570   if (!MI) return false;
5571 
5572   // CmpInstr is the first instruction of the BB.
5573   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5574 
5575   // If we are comparing against zero, check whether we can use MI to update
5576   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5577   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
5578   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
5579     return false;
5580 
5581   // If we have a use of the source register between the def and our compare
5582   // instruction we can eliminate the compare iff the use sets EFLAGS in the
5583   // right way.
5584   bool ShouldUpdateCC = false;
5585   X86::CondCode NewCC = X86::COND_INVALID;
5586   if (IsCmpZero && !isDefConvertible(*MI)) {
5587     // Scan forward from the use until we hit the use we're looking for or the
5588     // compare instruction.
5589     for (MachineBasicBlock::iterator J = MI;; ++J) {
5590       // Do we have a convertible instruction?
5591       NewCC = isUseDefConvertible(*J);
5592       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5593           J->getOperand(1).getReg() == SrcReg) {
5594         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5595         ShouldUpdateCC = true; // Update CC later on.
5596         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5597         // with the new def.
5598         Def = J;
5599         MI = &*Def;
5600         break;
5601       }
5602 
5603       if (J == I)
5604         return false;
5605     }
5606   }
5607 
5608   // We are searching for an earlier instruction that can make CmpInstr
5609   // redundant and that instruction will be saved in Sub.
5610   MachineInstr *Sub = nullptr;
5611   const TargetRegisterInfo *TRI = &getRegisterInfo();
5612 
5613   // We iterate backward, starting from the instruction before CmpInstr and
5614   // stop when reaching the definition of a source register or done with the BB.
5615   // RI points to the instruction before CmpInstr.
5616   // If the definition is in this basic block, RE points to the definition;
5617   // otherwise, RE is the rend of the basic block.
5618   MachineBasicBlock::reverse_iterator
5619       RI = ++I.getReverse(),
5620       RE = CmpInstr.getParent() == MI->getParent()
5621                ? Def.getReverse() /* points to MI */
5622                : CmpInstr.getParent()->rend();
5623   MachineInstr *Movr0Inst = nullptr;
5624   for (; RI != RE; ++RI) {
5625     MachineInstr &Instr = *RI;
5626     // Check whether CmpInstr can be made redundant by the current instruction.
5627     if (!IsCmpZero &&
5628         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
5629       Sub = &Instr;
5630       break;
5631     }
5632 
5633     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
5634         Instr.readsRegister(X86::EFLAGS, TRI)) {
5635       // This instruction modifies or uses EFLAGS.
5636 
5637       // MOV32r0 etc. are implemented with xor which clobbers condition code.
5638       // They are safe to move up, if the definition to EFLAGS is dead and
5639       // earlier instructions do not read or write EFLAGS.
5640       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
5641           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
5642         Movr0Inst = &Instr;
5643         continue;
5644       }
5645 
5646       // We can't remove CmpInstr.
5647       return false;
5648     }
5649   }
5650 
5651   // Return false if no candidates exist.
5652   if (!IsCmpZero && !Sub)
5653     return false;
5654 
5655   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5656                     Sub->getOperand(2).getReg() == SrcReg);
5657 
5658   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
5659   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5660   // If we are done with the basic block, we need to check whether EFLAGS is
5661   // live-out.
5662   bool IsSafe = false;
5663   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
5664   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
5665   for (++I; I != E; ++I) {
5666     const MachineInstr &Instr = *I;
5667     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5668     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5669     // We should check the usage if this instruction uses and updates EFLAGS.
5670     if (!UseEFLAGS && ModifyEFLAGS) {
5671       // It is safe to remove CmpInstr if EFLAGS is updated again.
5672       IsSafe = true;
5673       break;
5674     }
5675     if (!UseEFLAGS && !ModifyEFLAGS)
5676       continue;
5677 
5678     // EFLAGS is used by this instruction.
5679     X86::CondCode OldCC = X86::COND_INVALID;
5680     bool OpcIsSET = false;
5681     if (IsCmpZero || IsSwapped) {
5682       // We decode the condition code from opcode.
5683       if (Instr.isBranch())
5684         OldCC = getCondFromBranchOpc(Instr.getOpcode());
5685       else {
5686         OldCC = getCondFromSETOpc(Instr.getOpcode());
5687         if (OldCC != X86::COND_INVALID)
5688           OpcIsSET = true;
5689         else
5690           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
5691       }
5692       if (OldCC == X86::COND_INVALID) return false;
5693     }
5694     if (IsCmpZero) {
5695       switch (OldCC) {
5696       default: break;
5697       case X86::COND_A: case X86::COND_AE:
5698       case X86::COND_B: case X86::COND_BE:
5699       case X86::COND_G: case X86::COND_GE:
5700       case X86::COND_L: case X86::COND_LE:
5701       case X86::COND_O: case X86::COND_NO:
5702         // CF and OF are used, we can't perform this optimization.
5703         return false;
5704       }
5705 
5706       // If we're updating the condition code check if we have to reverse the
5707       // condition.
5708       if (ShouldUpdateCC)
5709         switch (OldCC) {
5710         default:
5711           return false;
5712         case X86::COND_E:
5713           break;
5714         case X86::COND_NE:
5715           NewCC = GetOppositeBranchCondition(NewCC);
5716           break;
5717         }
5718     } else if (IsSwapped) {
5719       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5720       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5721       // We swap the condition code and synthesize the new opcode.
5722       NewCC = getSwappedCondition(OldCC);
5723       if (NewCC == X86::COND_INVALID) return false;
5724     }
5725 
5726     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
5727       // Synthesize the new opcode.
5728       bool HasMemoryOperand = Instr.hasOneMemOperand();
5729       unsigned NewOpc;
5730       if (Instr.isBranch())
5731         NewOpc = GetCondBranchFromCond(NewCC);
5732       else if(OpcIsSET)
5733         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5734       else {
5735         unsigned DstReg = Instr.getOperand(0).getReg();
5736         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5737                                  HasMemoryOperand);
5738       }
5739 
5740       // Push the MachineInstr to OpsToUpdate.
5741       // If it is safe to remove CmpInstr, the condition code of these
5742       // instructions will be modified.
5743       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5744     }
5745     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5746       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
5747       IsSafe = true;
5748       break;
5749     }
5750   }
5751 
5752   // If EFLAGS is not killed nor re-defined, we should check whether it is
5753   // live-out. If it is live-out, do not optimize.
5754   if ((IsCmpZero || IsSwapped) && !IsSafe) {
5755     MachineBasicBlock *MBB = CmpInstr.getParent();
5756     for (MachineBasicBlock *Successor : MBB->successors())
5757       if (Successor->isLiveIn(X86::EFLAGS))
5758         return false;
5759   }
5760 
5761   // The instruction to be updated is either Sub or MI.
5762   Sub = IsCmpZero ? MI : Sub;
5763   // Move Movr0Inst to the appropriate place before Sub.
5764   if (Movr0Inst) {
5765     // Look backwards until we find a def that doesn't use the current EFLAGS.
5766     Def = Sub;
5767     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
5768                                         InsertE = Sub->getParent()->rend();
5769     for (; InsertI != InsertE; ++InsertI) {
5770       MachineInstr *Instr = &*InsertI;
5771       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5772           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5773         Sub->getParent()->remove(Movr0Inst);
5774         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5775                                    Movr0Inst);
5776         break;
5777       }
5778     }
5779     if (InsertI == InsertE)
5780       return false;
5781   }
5782 
5783   // Make sure Sub instruction defines EFLAGS and mark the def live.
5784   unsigned i = 0, e = Sub->getNumOperands();
5785   for (; i != e; ++i) {
5786     MachineOperand &MO = Sub->getOperand(i);
5787     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5788       MO.setIsDead(false);
5789       break;
5790     }
5791   }
5792   assert(i != e && "Unable to locate a def EFLAGS operand");
5793 
5794   CmpInstr.eraseFromParent();
5795 
5796   // Modify the condition code of instructions in OpsToUpdate.
5797   for (auto &Op : OpsToUpdate)
5798     Op.first->setDesc(get(Op.second));
5799   return true;
5800 }
5801 
5802 /// Try to remove the load by folding it to a register
5803 /// operand at the use. We fold the load instructions if load defines a virtual
5804 /// register, the virtual register is used once in the same BB, and the
5805 /// instructions in-between do not load or store, and have no side effects.
5806 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
5807                                               const MachineRegisterInfo *MRI,
5808                                               unsigned &FoldAsLoadDefReg,
5809                                               MachineInstr *&DefMI) const {
5810   if (FoldAsLoadDefReg == 0)
5811     return nullptr;
5812   // To be conservative, if there exists another load, clear the load candidate.
5813   if (MI.mayLoad()) {
5814     FoldAsLoadDefReg = 0;
5815     return nullptr;
5816   }
5817 
5818   // Check whether we can move DefMI here.
5819   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5820   assert(DefMI);
5821   bool SawStore = false;
5822   if (!DefMI->isSafeToMove(nullptr, SawStore))
5823     return nullptr;
5824 
5825   // Collect information about virtual register operands of MI.
5826   unsigned SrcOperandId = 0;
5827   bool FoundSrcOperand = false;
5828   for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
5829     MachineOperand &MO = MI.getOperand(i);
5830     if (!MO.isReg())
5831       continue;
5832     unsigned Reg = MO.getReg();
5833     if (Reg != FoldAsLoadDefReg)
5834       continue;
5835     // Do not fold if we have a subreg use or a def or multiple uses.
5836     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
5837       return nullptr;
5838 
5839     SrcOperandId = i;
5840     FoundSrcOperand = true;
5841   }
5842   if (!FoundSrcOperand)
5843     return nullptr;
5844 
5845   // Check whether we can fold the def into SrcOperandId.
5846   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, *DefMI)) {
5847     FoldAsLoadDefReg = 0;
5848     return FoldMI;
5849   }
5850 
5851   return nullptr;
5852 }
5853 
5854 /// Expand a single-def pseudo instruction to a two-addr
5855 /// instruction with two undef reads of the register being defined.
5856 /// This is used for mapping:
5857 ///   %xmm4 = V_SET0
5858 /// to:
5859 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5860 ///
5861 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5862                              const MCInstrDesc &Desc) {
5863   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5864   unsigned Reg = MIB->getOperand(0).getReg();
5865   MIB->setDesc(Desc);
5866 
5867   // MachineInstr::addOperand() will insert explicit operands before any
5868   // implicit operands.
5869   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5870   // But we don't trust that.
5871   assert(MIB->getOperand(1).getReg() == Reg &&
5872          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
5873   return true;
5874 }
5875 
5876 /// Expand a single-def pseudo instruction to a two-addr
5877 /// instruction with two %k0 reads.
5878 /// This is used for mapping:
5879 ///   %k4 = K_SET1
5880 /// to:
5881 ///   %k4 = KXNORrr %k0, %k0
5882 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5883                             const MCInstrDesc &Desc, unsigned Reg) {
5884   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5885   MIB->setDesc(Desc);
5886   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5887   return true;
5888 }
5889 
5890 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5891                           bool MinusOne) {
5892   MachineBasicBlock &MBB = *MIB->getParent();
5893   DebugLoc DL = MIB->getDebugLoc();
5894   unsigned Reg = MIB->getOperand(0).getReg();
5895 
5896   // Insert the XOR.
5897   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5898       .addReg(Reg, RegState::Undef)
5899       .addReg(Reg, RegState::Undef);
5900 
5901   // Turn the pseudo into an INC or DEC.
5902   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5903   MIB.addReg(Reg);
5904 
5905   return true;
5906 }
5907 
5908 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
5909                                const TargetInstrInfo &TII,
5910                                const X86Subtarget &Subtarget) {
5911   MachineBasicBlock &MBB = *MIB->getParent();
5912   DebugLoc DL = MIB->getDebugLoc();
5913   int64_t Imm = MIB->getOperand(1).getImm();
5914   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5915   MachineBasicBlock::iterator I = MIB.getInstr();
5916 
5917   int StackAdjustment;
5918 
5919   if (Subtarget.is64Bit()) {
5920     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5921            MIB->getOpcode() == X86::MOV32ImmSExti8);
5922 
5923     // Can't use push/pop lowering if the function might write to the red zone.
5924     X86MachineFunctionInfo *X86FI =
5925         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5926     if (X86FI->getUsesRedZone()) {
5927       MIB->setDesc(TII.get(MIB->getOpcode() ==
5928                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
5929       return true;
5930     }
5931 
5932     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5933     // widen the register if necessary.
5934     StackAdjustment = 8;
5935     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
5936     MIB->setDesc(TII.get(X86::POP64r));
5937     MIB->getOperand(0)
5938         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5939   } else {
5940     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5941     StackAdjustment = 4;
5942     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
5943     MIB->setDesc(TII.get(X86::POP32r));
5944   }
5945 
5946   // Build CFI if necessary.
5947   MachineFunction &MF = *MBB.getParent();
5948   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5949   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5950   bool NeedsDwarfCFI =
5951       !IsWin64Prologue &&
5952       (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5953   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5954   if (EmitCFI) {
5955     TFL->BuildCFI(MBB, I, DL,
5956         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5957     TFL->BuildCFI(MBB, std::next(I), DL,
5958         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5959   }
5960 
5961   return true;
5962 }
5963 
5964 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5965 // code sequence is needed for other targets.
5966 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5967                                  const TargetInstrInfo &TII) {
5968   MachineBasicBlock &MBB = *MIB->getParent();
5969   DebugLoc DL = MIB->getDebugLoc();
5970   unsigned Reg = MIB->getOperand(0).getReg();
5971   const GlobalValue *GV =
5972       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
5973   auto Flags = MachineMemOperand::MOLoad |
5974                MachineMemOperand::MODereferenceable |
5975                MachineMemOperand::MOInvariant;
5976   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
5977       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
5978   MachineBasicBlock::iterator I = MIB.getInstr();
5979 
5980   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5981       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5982       .addMemOperand(MMO);
5983   MIB->setDebugLoc(DL);
5984   MIB->setDesc(TII.get(X86::MOV64rm));
5985   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5986 }
5987 
5988 // This is used to handle spills for 128/256-bit registers when we have AVX512,
5989 // but not VLX. If it uses an extended register we need to use an instruction
5990 // that loads the lower 128/256-bit, but is available with only AVX512F.
5991 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
5992                             const TargetRegisterInfo *TRI,
5993                             const MCInstrDesc &LoadDesc,
5994                             const MCInstrDesc &BroadcastDesc,
5995                             unsigned SubIdx) {
5996   unsigned DestReg = MIB->getOperand(0).getReg();
5997   // Check if DestReg is XMM16-31 or YMM16-31.
5998   if (TRI->getEncodingValue(DestReg) < 16) {
5999     // We can use a normal VEX encoded load.
6000     MIB->setDesc(LoadDesc);
6001   } else {
6002     // Use a 128/256-bit VBROADCAST instruction.
6003     MIB->setDesc(BroadcastDesc);
6004     // Change the destination to a 512-bit register.
6005     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
6006     MIB->getOperand(0).setReg(DestReg);
6007   }
6008   return true;
6009 }
6010 
6011 // This is used to handle spills for 128/256-bit registers when we have AVX512,
6012 // but not VLX. If it uses an extended register we need to use an instruction
6013 // that stores the lower 128/256-bit, but is available with only AVX512F.
6014 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
6015                              const TargetRegisterInfo *TRI,
6016                              const MCInstrDesc &StoreDesc,
6017                              const MCInstrDesc &ExtractDesc,
6018                              unsigned SubIdx) {
6019   unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
6020   // Check if DestReg is XMM16-31 or YMM16-31.
6021   if (TRI->getEncodingValue(SrcReg) < 16) {
6022     // We can use a normal VEX encoded store.
6023     MIB->setDesc(StoreDesc);
6024   } else {
6025     // Use a VEXTRACTF instruction.
6026     MIB->setDesc(ExtractDesc);
6027     // Change the destination to a 512-bit register.
6028     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
6029     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
6030     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
6031   }
6032 
6033   return true;
6034 }
6035 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
6036   bool HasAVX = Subtarget.hasAVX();
6037   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
6038   switch (MI.getOpcode()) {
6039   case X86::MOV32r0:
6040     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
6041   case X86::MOV32r1:
6042     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
6043   case X86::MOV32r_1:
6044     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
6045   case X86::MOV32ImmSExti8:
6046   case X86::MOV64ImmSExti8:
6047     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
6048   case X86::SETB_C8r:
6049     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
6050   case X86::SETB_C16r:
6051     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
6052   case X86::SETB_C32r:
6053     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
6054   case X86::SETB_C64r:
6055     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
6056   case X86::V_SET0:
6057   case X86::FsFLD0SS:
6058   case X86::FsFLD0SD:
6059     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
6060   case X86::AVX_SET0:
6061     assert(HasAVX && "AVX not supported");
6062     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
6063   case X86::AVX512_128_SET0:
6064     return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
6065   case X86::AVX512_256_SET0:
6066     return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
6067   case X86::AVX512_512_SET0:
6068     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
6069   case X86::V_SETALLONES:
6070     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
6071   case X86::AVX2_SETALLONES:
6072     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
6073   case X86::AVX512_512_SETALLONES: {
6074     unsigned Reg = MIB->getOperand(0).getReg();
6075     MIB->setDesc(get(X86::VPTERNLOGDZrri));
6076     // VPTERNLOGD needs 3 register inputs and an immediate.
6077     // 0xff will return 1s for any input.
6078     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
6079        .addReg(Reg, RegState::Undef).addImm(0xff);
6080     return true;
6081   }
6082   case X86::VMOVAPSZ128rm_NOVLX:
6083     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
6084                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
6085   case X86::VMOVUPSZ128rm_NOVLX:
6086     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
6087                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
6088   case X86::VMOVAPSZ256rm_NOVLX:
6089     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
6090                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
6091   case X86::VMOVUPSZ256rm_NOVLX:
6092     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
6093                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
6094   case X86::VMOVAPSZ128mr_NOVLX:
6095     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
6096                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
6097   case X86::VMOVUPSZ128mr_NOVLX:
6098     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
6099                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
6100   case X86::VMOVAPSZ256mr_NOVLX:
6101     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
6102                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
6103   case X86::VMOVUPSZ256mr_NOVLX:
6104     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
6105                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
6106   case X86::TEST8ri_NOREX:
6107     MI.setDesc(get(X86::TEST8ri));
6108     return true;
6109   case X86::MOV32ri64:
6110     MI.setDesc(get(X86::MOV32ri));
6111     return true;
6112 
6113   // KNL does not recognize dependency-breaking idioms for mask registers,
6114   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
6115   // Using %k0 as the undef input register is a performance heuristic based
6116   // on the assumption that %k0 is used less frequently than the other mask
6117   // registers, since it is not usable as a write mask.
6118   // FIXME: A more advanced approach would be to choose the best input mask
6119   // register based on context.
6120   case X86::KSET0B:
6121   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
6122   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
6123   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
6124   case X86::KSET1B:
6125   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
6126   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
6127   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
6128   case TargetOpcode::LOAD_STACK_GUARD:
6129     expandLoadStackGuard(MIB, *this);
6130     return true;
6131   }
6132   return false;
6133 }
6134 
6135 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
6136                         int PtrOffset = 0) {
6137   unsigned NumAddrOps = MOs.size();
6138 
6139   if (NumAddrOps < 4) {
6140     // FrameIndex only - add an immediate offset (whether its zero or not).
6141     for (unsigned i = 0; i != NumAddrOps; ++i)
6142       MIB.addOperand(MOs[i]);
6143     addOffset(MIB, PtrOffset);
6144   } else {
6145     // General Memory Addressing - we need to add any offset to an existing
6146     // offset.
6147     assert(MOs.size() == 5 && "Unexpected memory operand list length");
6148     for (unsigned i = 0; i != NumAddrOps; ++i) {
6149       const MachineOperand &MO = MOs[i];
6150       if (i == 3 && PtrOffset != 0) {
6151         MIB.addDisp(MO, PtrOffset);
6152       } else {
6153         MIB.addOperand(MO);
6154       }
6155     }
6156   }
6157 }
6158 
6159 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
6160                                      ArrayRef<MachineOperand> MOs,
6161                                      MachineBasicBlock::iterator InsertPt,
6162                                      MachineInstr &MI,
6163                                      const TargetInstrInfo &TII) {
6164   // Create the base instruction with the memory operand as the first part.
6165   // Omit the implicit operands, something BuildMI can't do.
6166   MachineInstr *NewMI =
6167       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
6168   MachineInstrBuilder MIB(MF, NewMI);
6169   addOperands(MIB, MOs);
6170 
6171   // Loop over the rest of the ri operands, converting them over.
6172   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
6173   for (unsigned i = 0; i != NumOps; ++i) {
6174     MachineOperand &MO = MI.getOperand(i + 2);
6175     MIB.addOperand(MO);
6176   }
6177   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
6178     MachineOperand &MO = MI.getOperand(i);
6179     MIB.addOperand(MO);
6180   }
6181 
6182   MachineBasicBlock *MBB = InsertPt->getParent();
6183   MBB->insert(InsertPt, NewMI);
6184 
6185   return MIB;
6186 }
6187 
6188 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
6189                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
6190                               MachineBasicBlock::iterator InsertPt,
6191                               MachineInstr &MI, const TargetInstrInfo &TII,
6192                               int PtrOffset = 0) {
6193   // Omit the implicit operands, something BuildMI can't do.
6194   MachineInstr *NewMI =
6195       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
6196   MachineInstrBuilder MIB(MF, NewMI);
6197 
6198   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6199     MachineOperand &MO = MI.getOperand(i);
6200     if (i == OpNo) {
6201       assert(MO.isReg() && "Expected to fold into reg operand!");
6202       addOperands(MIB, MOs, PtrOffset);
6203     } else {
6204       MIB.addOperand(MO);
6205     }
6206   }
6207 
6208   MachineBasicBlock *MBB = InsertPt->getParent();
6209   MBB->insert(InsertPt, NewMI);
6210 
6211   return MIB;
6212 }
6213 
6214 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
6215                                 ArrayRef<MachineOperand> MOs,
6216                                 MachineBasicBlock::iterator InsertPt,
6217                                 MachineInstr &MI) {
6218   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
6219                                     MI.getDebugLoc(), TII.get(Opcode));
6220   addOperands(MIB, MOs);
6221   return MIB.addImm(0);
6222 }
6223 
6224 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
6225     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
6226     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
6227     unsigned Size, unsigned Align) const {
6228   switch (MI.getOpcode()) {
6229   case X86::INSERTPSrr:
6230   case X86::VINSERTPSrr:
6231   case X86::VINSERTPSZrr:
6232     // Attempt to convert the load of inserted vector into a fold load
6233     // of a single float.
6234     if (OpNum == 2) {
6235       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
6236       unsigned ZMask = Imm & 15;
6237       unsigned DstIdx = (Imm >> 4) & 3;
6238       unsigned SrcIdx = (Imm >> 6) & 3;
6239 
6240       unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
6241       if (Size <= RCSize && 4 <= Align) {
6242         int PtrOffset = SrcIdx * 4;
6243         unsigned NewImm = (DstIdx << 4) | ZMask;
6244         unsigned NewOpCode =
6245             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
6246             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
6247                                                     X86::INSERTPSrm;
6248         MachineInstr *NewMI =
6249             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
6250         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
6251         return NewMI;
6252       }
6253     }
6254     break;
6255   case X86::MOVHLPSrr:
6256   case X86::VMOVHLPSrr:
6257   case X86::VMOVHLPSZrr:
6258     // Move the upper 64-bits of the second operand to the lower 64-bits.
6259     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
6260     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
6261     if (OpNum == 2) {
6262       unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
6263       if (Size <= RCSize && 8 <= Align) {
6264         unsigned NewOpCode =
6265             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
6266             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
6267                                                    X86::MOVLPSrm;
6268         MachineInstr *NewMI =
6269             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
6270         return NewMI;
6271       }
6272     }
6273     break;
6274   };
6275 
6276   return nullptr;
6277 }
6278 
6279 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6280     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
6281     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
6282     unsigned Size, unsigned Align, bool AllowCommute) const {
6283   const DenseMap<unsigned,
6284                  std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
6285   bool isCallRegIndirect = Subtarget.callRegIndirect();
6286   bool isTwoAddrFold = false;
6287 
6288   // For CPUs that favor the register form of a call or push,
6289   // do not fold loads into calls or pushes, unless optimizing for size
6290   // aggressively.
6291   if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
6292       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
6293        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
6294        MI.getOpcode() == X86::PUSH64r))
6295     return nullptr;
6296 
6297   unsigned NumOps = MI.getDesc().getNumOperands();
6298   bool isTwoAddr =
6299       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
6300 
6301   // FIXME: AsmPrinter doesn't know how to handle
6302   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
6303   if (MI.getOpcode() == X86::ADD32ri &&
6304       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
6305     return nullptr;
6306 
6307   MachineInstr *NewMI = nullptr;
6308 
6309   // Attempt to fold any custom cases we have.
6310   if (MachineInstr *CustomMI =
6311           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
6312     return CustomMI;
6313 
6314   // Folding a memory location into the two-address part of a two-address
6315   // instruction is different than folding it other places.  It requires
6316   // replacing the *two* registers with the memory location.
6317   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
6318       MI.getOperand(1).isReg() &&
6319       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
6320     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
6321     isTwoAddrFold = true;
6322   } else if (OpNum == 0) {
6323     if (MI.getOpcode() == X86::MOV32r0) {
6324       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
6325       if (NewMI)
6326         return NewMI;
6327     }
6328 
6329     OpcodeTablePtr = &RegOp2MemOpTable0;
6330   } else if (OpNum == 1) {
6331     OpcodeTablePtr = &RegOp2MemOpTable1;
6332   } else if (OpNum == 2) {
6333     OpcodeTablePtr = &RegOp2MemOpTable2;
6334   } else if (OpNum == 3) {
6335     OpcodeTablePtr = &RegOp2MemOpTable3;
6336   } else if (OpNum == 4) {
6337     OpcodeTablePtr = &RegOp2MemOpTable4;
6338   }
6339 
6340   // If table selected...
6341   if (OpcodeTablePtr) {
6342     // Find the Opcode to fuse
6343     auto I = OpcodeTablePtr->find(MI.getOpcode());
6344     if (I != OpcodeTablePtr->end()) {
6345       unsigned Opcode = I->second.first;
6346       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
6347       if (Align < MinAlign)
6348         return nullptr;
6349       bool NarrowToMOV32rm = false;
6350       if (Size) {
6351         unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
6352         if (Size < RCSize) {
6353           // Check if it's safe to fold the load. If the size of the object is
6354           // narrower than the load width, then it's not.
6355           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
6356             return nullptr;
6357           // If this is a 64-bit load, but the spill slot is 32, then we can do
6358           // a 32-bit load which is implicitly zero-extended. This likely is
6359           // due to live interval analysis remat'ing a load from stack slot.
6360           if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
6361             return nullptr;
6362           Opcode = X86::MOV32rm;
6363           NarrowToMOV32rm = true;
6364         }
6365       }
6366 
6367       if (isTwoAddrFold)
6368         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
6369       else
6370         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
6371 
6372       if (NarrowToMOV32rm) {
6373         // If this is the special case where we use a MOV32rm to load a 32-bit
6374         // value and zero-extend the top bits. Change the destination register
6375         // to a 32-bit one.
6376         unsigned DstReg = NewMI->getOperand(0).getReg();
6377         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
6378           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
6379         else
6380           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
6381       }
6382       return NewMI;
6383     }
6384   }
6385 
6386   // If the instruction and target operand are commutable, commute the
6387   // instruction and try again.
6388   if (AllowCommute) {
6389     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
6390     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
6391       bool HasDef = MI.getDesc().getNumDefs();
6392       unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
6393       unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
6394       unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
6395       bool Tied1 =
6396           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
6397       bool Tied2 =
6398           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
6399 
6400       // If either of the commutable operands are tied to the destination
6401       // then we can not commute + fold.
6402       if ((HasDef && Reg0 == Reg1 && Tied1) ||
6403           (HasDef && Reg0 == Reg2 && Tied2))
6404         return nullptr;
6405 
6406       MachineInstr *CommutedMI =
6407           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
6408       if (!CommutedMI) {
6409         // Unable to commute.
6410         return nullptr;
6411       }
6412       if (CommutedMI != &MI) {
6413         // New instruction. We can't fold from this.
6414         CommutedMI->eraseFromParent();
6415         return nullptr;
6416       }
6417 
6418       // Attempt to fold with the commuted version of the instruction.
6419       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
6420                                     Size, Align, /*AllowCommute=*/false);
6421       if (NewMI)
6422         return NewMI;
6423 
6424       // Folding failed again - undo the commute before returning.
6425       MachineInstr *UncommutedMI =
6426           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
6427       if (!UncommutedMI) {
6428         // Unable to commute.
6429         return nullptr;
6430       }
6431       if (UncommutedMI != &MI) {
6432         // New instruction. It doesn't need to be kept.
6433         UncommutedMI->eraseFromParent();
6434         return nullptr;
6435       }
6436 
6437       // Return here to prevent duplicate fuse failure report.
6438       return nullptr;
6439     }
6440   }
6441 
6442   // No fusion
6443   if (PrintFailedFusing && !MI.isCopy())
6444     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
6445   return nullptr;
6446 }
6447 
6448 /// Return true for all instructions that only update
6449 /// the first 32 or 64-bits of the destination register and leave the rest
6450 /// unmodified. This can be used to avoid folding loads if the instructions
6451 /// only update part of the destination register, and the non-updated part is
6452 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
6453 /// instructions breaks the partial register dependency and it can improve
6454 /// performance. e.g.:
6455 ///
6456 ///   movss (%rdi), %xmm0
6457 ///   cvtss2sd %xmm0, %xmm0
6458 ///
6459 /// Instead of
6460 ///   cvtss2sd (%rdi), %xmm0
6461 ///
6462 /// FIXME: This should be turned into a TSFlags.
6463 ///
6464 static bool hasPartialRegUpdate(unsigned Opcode) {
6465   switch (Opcode) {
6466   case X86::CVTSI2SSrr:
6467   case X86::CVTSI2SSrm:
6468   case X86::CVTSI2SS64rr:
6469   case X86::CVTSI2SS64rm:
6470   case X86::CVTSI2SDrr:
6471   case X86::CVTSI2SDrm:
6472   case X86::CVTSI2SD64rr:
6473   case X86::CVTSI2SD64rm:
6474   case X86::CVTSD2SSrr:
6475   case X86::CVTSD2SSrm:
6476   case X86::Int_CVTSD2SSrr:
6477   case X86::Int_CVTSD2SSrm:
6478   case X86::CVTSS2SDrr:
6479   case X86::CVTSS2SDrm:
6480   case X86::Int_CVTSS2SDrr:
6481   case X86::Int_CVTSS2SDrm:
6482   case X86::MOVHPDrm:
6483   case X86::MOVHPSrm:
6484   case X86::MOVLPDrm:
6485   case X86::MOVLPSrm:
6486   case X86::RCPSSr:
6487   case X86::RCPSSm:
6488   case X86::RCPSSr_Int:
6489   case X86::RCPSSm_Int:
6490   case X86::ROUNDSDr:
6491   case X86::ROUNDSDm:
6492   case X86::ROUNDSDr_Int:
6493   case X86::ROUNDSDm_Int:
6494   case X86::ROUNDSSr:
6495   case X86::ROUNDSSm:
6496   case X86::ROUNDSSr_Int:
6497   case X86::ROUNDSSm_Int:
6498   case X86::RSQRTSSr:
6499   case X86::RSQRTSSm:
6500   case X86::RSQRTSSr_Int:
6501   case X86::RSQRTSSm_Int:
6502   case X86::SQRTSSr:
6503   case X86::SQRTSSm:
6504   case X86::SQRTSSr_Int:
6505   case X86::SQRTSSm_Int:
6506   case X86::SQRTSDr:
6507   case X86::SQRTSDm:
6508   case X86::SQRTSDr_Int:
6509   case X86::SQRTSDm_Int:
6510     return true;
6511   }
6512 
6513   return false;
6514 }
6515 
6516 /// Inform the ExeDepsFix pass how many idle
6517 /// instructions we would like before a partial register update.
6518 unsigned X86InstrInfo::getPartialRegUpdateClearance(
6519     const MachineInstr &MI, unsigned OpNum,
6520     const TargetRegisterInfo *TRI) const {
6521   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
6522     return 0;
6523 
6524   // If MI is marked as reading Reg, the partial register update is wanted.
6525   const MachineOperand &MO = MI.getOperand(0);
6526   unsigned Reg = MO.getReg();
6527   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6528     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
6529       return 0;
6530   } else {
6531     if (MI.readsRegister(Reg, TRI))
6532       return 0;
6533   }
6534 
6535   // If any instructions in the clearance range are reading Reg, insert a
6536   // dependency breaking instruction, which is inexpensive and is likely to
6537   // be hidden in other instruction's cycles.
6538   return PartialRegUpdateClearance;
6539 }
6540 
6541 // Return true for any instruction the copies the high bits of the first source
6542 // operand into the unused high bits of the destination operand.
6543 static bool hasUndefRegUpdate(unsigned Opcode) {
6544   switch (Opcode) {
6545   case X86::VCVTSI2SSrr:
6546   case X86::VCVTSI2SSrm:
6547   case X86::Int_VCVTSI2SSrr:
6548   case X86::Int_VCVTSI2SSrm:
6549   case X86::VCVTSI2SS64rr:
6550   case X86::VCVTSI2SS64rm:
6551   case X86::Int_VCVTSI2SS64rr:
6552   case X86::Int_VCVTSI2SS64rm:
6553   case X86::VCVTSI2SDrr:
6554   case X86::VCVTSI2SDrm:
6555   case X86::Int_VCVTSI2SDrr:
6556   case X86::Int_VCVTSI2SDrm:
6557   case X86::VCVTSI2SD64rr:
6558   case X86::VCVTSI2SD64rm:
6559   case X86::Int_VCVTSI2SD64rr:
6560   case X86::Int_VCVTSI2SD64rm:
6561   case X86::VCVTSD2SSrr:
6562   case X86::VCVTSD2SSrm:
6563   case X86::Int_VCVTSD2SSrr:
6564   case X86::Int_VCVTSD2SSrm:
6565   case X86::VCVTSS2SDrr:
6566   case X86::VCVTSS2SDrm:
6567   case X86::Int_VCVTSS2SDrr:
6568   case X86::Int_VCVTSS2SDrm:
6569   case X86::VRCPSSr:
6570   case X86::VRCPSSr_Int:
6571   case X86::VRCPSSm:
6572   case X86::VRCPSSm_Int:
6573   case X86::VROUNDSDr:
6574   case X86::VROUNDSDm:
6575   case X86::VROUNDSDr_Int:
6576   case X86::VROUNDSDm_Int:
6577   case X86::VROUNDSSr:
6578   case X86::VROUNDSSm:
6579   case X86::VROUNDSSr_Int:
6580   case X86::VROUNDSSm_Int:
6581   case X86::VRSQRTSSr:
6582   case X86::VRSQRTSSr_Int:
6583   case X86::VRSQRTSSm:
6584   case X86::VRSQRTSSm_Int:
6585   case X86::VSQRTSSr:
6586   case X86::VSQRTSSr_Int:
6587   case X86::VSQRTSSm:
6588   case X86::VSQRTSSm_Int:
6589   case X86::VSQRTSDr:
6590   case X86::VSQRTSDr_Int:
6591   case X86::VSQRTSDm:
6592   case X86::VSQRTSDm_Int:
6593   // AVX-512
6594   case X86::VCVTSI2SSZrr:
6595   case X86::VCVTSI2SSZrm:
6596   case X86::VCVTSI2SSZrr_Int:
6597   case X86::VCVTSI2SSZrrb_Int:
6598   case X86::VCVTSI2SSZrm_Int:
6599   case X86::VCVTSI642SSZrr:
6600   case X86::VCVTSI642SSZrm:
6601   case X86::VCVTSI642SSZrr_Int:
6602   case X86::VCVTSI642SSZrrb_Int:
6603   case X86::VCVTSI642SSZrm_Int:
6604   case X86::VCVTSI2SDZrr:
6605   case X86::VCVTSI2SDZrm:
6606   case X86::VCVTSI2SDZrr_Int:
6607   case X86::VCVTSI2SDZrrb_Int:
6608   case X86::VCVTSI2SDZrm_Int:
6609   case X86::VCVTSI642SDZrr:
6610   case X86::VCVTSI642SDZrm:
6611   case X86::VCVTSI642SDZrr_Int:
6612   case X86::VCVTSI642SDZrrb_Int:
6613   case X86::VCVTSI642SDZrm_Int:
6614   case X86::VCVTUSI2SSZrr:
6615   case X86::VCVTUSI2SSZrm:
6616   case X86::VCVTUSI2SSZrr_Int:
6617   case X86::VCVTUSI2SSZrrb_Int:
6618   case X86::VCVTUSI2SSZrm_Int:
6619   case X86::VCVTUSI642SSZrr:
6620   case X86::VCVTUSI642SSZrm:
6621   case X86::VCVTUSI642SSZrr_Int:
6622   case X86::VCVTUSI642SSZrrb_Int:
6623   case X86::VCVTUSI642SSZrm_Int:
6624   case X86::VCVTUSI2SDZrr:
6625   case X86::VCVTUSI2SDZrm:
6626   case X86::VCVTUSI2SDZrr_Int:
6627   case X86::VCVTUSI2SDZrm_Int:
6628   case X86::VCVTUSI642SDZrr:
6629   case X86::VCVTUSI642SDZrm:
6630   case X86::VCVTUSI642SDZrr_Int:
6631   case X86::VCVTUSI642SDZrrb_Int:
6632   case X86::VCVTUSI642SDZrm_Int:
6633   case X86::VCVTSD2SSZrr:
6634   case X86::VCVTSD2SSZrrb:
6635   case X86::VCVTSD2SSZrm:
6636   case X86::VCVTSS2SDZrr:
6637   case X86::VCVTSS2SDZrrb:
6638   case X86::VCVTSS2SDZrm:
6639   case X86::VRNDSCALESDr:
6640   case X86::VRNDSCALESDrb:
6641   case X86::VRNDSCALESDm:
6642   case X86::VRNDSCALESSr:
6643   case X86::VRNDSCALESSrb:
6644   case X86::VRNDSCALESSm:
6645   case X86::VRCP14SSrr:
6646   case X86::VRCP14SSrm:
6647   case X86::VRSQRT14SSrr:
6648   case X86::VRSQRT14SSrm:
6649   case X86::VSQRTSSZr:
6650   case X86::VSQRTSSZr_Int:
6651   case X86::VSQRTSSZrb_Int:
6652   case X86::VSQRTSSZm:
6653   case X86::VSQRTSSZm_Int:
6654   case X86::VSQRTSDZr:
6655   case X86::VSQRTSDZr_Int:
6656   case X86::VSQRTSDZrb_Int:
6657   case X86::VSQRTSDZm:
6658   case X86::VSQRTSDZm_Int:
6659     return true;
6660   }
6661 
6662   return false;
6663 }
6664 
6665 /// Inform the ExeDepsFix pass how many idle instructions we would like before
6666 /// certain undef register reads.
6667 ///
6668 /// This catches the VCVTSI2SD family of instructions:
6669 ///
6670 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6671 ///
6672 /// We should to be careful *not* to catch VXOR idioms which are presumably
6673 /// handled specially in the pipeline:
6674 ///
6675 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6676 ///
6677 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6678 /// high bits that are passed-through are not live.
6679 unsigned
6680 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
6681                                    const TargetRegisterInfo *TRI) const {
6682   if (!hasUndefRegUpdate(MI.getOpcode()))
6683     return 0;
6684 
6685   // Set the OpNum parameter to the first source operand.
6686   OpNum = 1;
6687 
6688   const MachineOperand &MO = MI.getOperand(OpNum);
6689   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
6690     return UndefRegClearance;
6691   }
6692   return 0;
6693 }
6694 
6695 void X86InstrInfo::breakPartialRegDependency(
6696     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
6697   unsigned Reg = MI.getOperand(OpNum).getReg();
6698   // If MI kills this register, the false dependence is already broken.
6699   if (MI.killsRegister(Reg, TRI))
6700     return;
6701 
6702   if (X86::VR128RegClass.contains(Reg)) {
6703     // These instructions are all floating point domain, so xorps is the best
6704     // choice.
6705     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
6706     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
6707         .addReg(Reg, RegState::Undef)
6708         .addReg(Reg, RegState::Undef);
6709     MI.addRegisterKilled(Reg, TRI, true);
6710   } else if (X86::VR256RegClass.contains(Reg)) {
6711     // Use vxorps to clear the full ymm register.
6712     // It wants to read and write the xmm sub-register.
6713     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
6714     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
6715         .addReg(XReg, RegState::Undef)
6716         .addReg(XReg, RegState::Undef)
6717         .addReg(Reg, RegState::ImplicitDefine);
6718     MI.addRegisterKilled(Reg, TRI, true);
6719   }
6720 }
6721 
6722 MachineInstr *
6723 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
6724                                     ArrayRef<unsigned> Ops,
6725                                     MachineBasicBlock::iterator InsertPt,
6726                                     int FrameIndex, LiveIntervals *LIS) const {
6727   // Check switch flag
6728   if (NoFusing)
6729     return nullptr;
6730 
6731   // Unless optimizing for size, don't fold to avoid partial
6732   // register update stalls
6733   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
6734     return nullptr;
6735 
6736   const MachineFrameInfo &MFI = MF.getFrameInfo();
6737   unsigned Size = MFI.getObjectSize(FrameIndex);
6738   unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
6739   // If the function stack isn't realigned we don't want to fold instructions
6740   // that need increased alignment.
6741   if (!RI.needsStackRealignment(MF))
6742     Alignment =
6743         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
6744   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6745     unsigned NewOpc = 0;
6746     unsigned RCSize = 0;
6747     switch (MI.getOpcode()) {
6748     default: return nullptr;
6749     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
6750     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6751     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6752     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
6753     }
6754     // Check if it's safe to fold the load. If the size of the object is
6755     // narrower than the load width, then it's not.
6756     if (Size < RCSize)
6757       return nullptr;
6758     // Change to CMPXXri r, 0 first.
6759     MI.setDesc(get(NewOpc));
6760     MI.getOperand(1).ChangeToImmediate(0);
6761   } else if (Ops.size() != 1)
6762     return nullptr;
6763 
6764   return foldMemoryOperandImpl(MF, MI, Ops[0],
6765                                MachineOperand::CreateFI(FrameIndex), InsertPt,
6766                                Size, Alignment, /*AllowCommute=*/true);
6767 }
6768 
6769 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6770 /// because the latter uses contents that wouldn't be defined in the folded
6771 /// version.  For instance, this transformation isn't legal:
6772 ///   movss (%rdi), %xmm0
6773 ///   addps %xmm0, %xmm0
6774 /// ->
6775 ///   addps (%rdi), %xmm0
6776 ///
6777 /// But this one is:
6778 ///   movss (%rdi), %xmm0
6779 ///   addss %xmm0, %xmm0
6780 /// ->
6781 ///   addss (%rdi), %xmm0
6782 ///
6783 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6784                                              const MachineInstr &UserMI,
6785                                              const MachineFunction &MF) {
6786   unsigned Opc = LoadMI.getOpcode();
6787   unsigned UserOpc = UserMI.getOpcode();
6788   unsigned RegSize =
6789       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6790 
6791   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
6792       RegSize > 4) {
6793     // These instructions only load 32 bits, we can't fold them if the
6794     // destination register is wider than 32 bits (4 bytes), and its user
6795     // instruction isn't scalar (SS).
6796     switch (UserOpc) {
6797     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
6798     case X86::Int_CMPSSrr: case X86::Int_VCMPSSrr: case X86::VCMPSSZrr_Int:
6799     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
6800     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
6801     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
6802     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
6803     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
6804     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
6805     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
6806     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
6807     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
6808     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
6809     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
6810     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
6811     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
6812     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
6813     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
6814     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
6815     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
6816       return false;
6817     default:
6818       return true;
6819     }
6820   }
6821 
6822   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
6823       RegSize > 8) {
6824     // These instructions only load 64 bits, we can't fold them if the
6825     // destination register is wider than 64 bits (8 bytes), and its user
6826     // instruction isn't scalar (SD).
6827     switch (UserOpc) {
6828     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
6829     case X86::Int_CMPSDrr: case X86::Int_VCMPSDrr: case X86::VCMPSDZrr_Int:
6830     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
6831     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
6832     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
6833     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
6834     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
6835     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
6836     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
6837     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
6838     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
6839     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
6840     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
6841     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
6842     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
6843     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
6844     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
6845     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
6846     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
6847       return false;
6848     default:
6849       return true;
6850     }
6851   }
6852 
6853   return false;
6854 }
6855 
6856 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6857     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6858     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
6859     LiveIntervals *LIS) const {
6860   // If loading from a FrameIndex, fold directly from the FrameIndex.
6861   unsigned NumOps = LoadMI.getDesc().getNumOperands();
6862   int FrameIndex;
6863   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
6864     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6865       return nullptr;
6866     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
6867   }
6868 
6869   // Check switch flag
6870   if (NoFusing) return nullptr;
6871 
6872   // Avoid partial register update stalls unless optimizing for size.
6873   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
6874     return nullptr;
6875 
6876   // Determine the alignment of the load.
6877   unsigned Alignment = 0;
6878   if (LoadMI.hasOneMemOperand())
6879     Alignment = (*LoadMI.memoperands_begin())->getAlignment();
6880   else
6881     switch (LoadMI.getOpcode()) {
6882     case X86::AVX512_512_SET0:
6883     case X86::AVX512_512_SETALLONES:
6884       Alignment = 64;
6885       break;
6886     case X86::AVX2_SETALLONES:
6887     case X86::AVX_SET0:
6888     case X86::AVX512_256_SET0:
6889       Alignment = 32;
6890       break;
6891     case X86::V_SET0:
6892     case X86::V_SETALLONES:
6893     case X86::AVX512_128_SET0:
6894       Alignment = 16;
6895       break;
6896     case X86::FsFLD0SD:
6897       Alignment = 8;
6898       break;
6899     case X86::FsFLD0SS:
6900       Alignment = 4;
6901       break;
6902     default:
6903       return nullptr;
6904     }
6905   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6906     unsigned NewOpc = 0;
6907     switch (MI.getOpcode()) {
6908     default: return nullptr;
6909     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6910     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6911     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6912     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6913     }
6914     // Change to CMPXXri r, 0 first.
6915     MI.setDesc(get(NewOpc));
6916     MI.getOperand(1).ChangeToImmediate(0);
6917   } else if (Ops.size() != 1)
6918     return nullptr;
6919 
6920   // Make sure the subregisters match.
6921   // Otherwise we risk changing the size of the load.
6922   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6923     return nullptr;
6924 
6925   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6926   switch (LoadMI.getOpcode()) {
6927   case X86::V_SET0:
6928   case X86::V_SETALLONES:
6929   case X86::AVX2_SETALLONES:
6930   case X86::AVX_SET0:
6931   case X86::AVX512_128_SET0:
6932   case X86::AVX512_256_SET0:
6933   case X86::AVX512_512_SET0:
6934   case X86::AVX512_512_SETALLONES:
6935   case X86::FsFLD0SD:
6936   case X86::FsFLD0SS: {
6937     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6938     // Create a constant-pool entry and operands to load from it.
6939 
6940     // Medium and large mode can't fold loads this way.
6941     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6942         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6943       return nullptr;
6944 
6945     // x86-32 PIC requires a PIC base register for constant pools.
6946     unsigned PICBase = 0;
6947     if (MF.getTarget().isPositionIndependent()) {
6948       if (Subtarget.is64Bit())
6949         PICBase = X86::RIP;
6950       else
6951         // FIXME: PICBase = getGlobalBaseReg(&MF);
6952         // This doesn't work for several reasons.
6953         // 1. GlobalBaseReg may have been spilled.
6954         // 2. It may not be live at MI.
6955         return nullptr;
6956     }
6957 
6958     // Create a constant-pool entry.
6959     MachineConstantPool &MCP = *MF.getConstantPool();
6960     Type *Ty;
6961     unsigned Opc = LoadMI.getOpcode();
6962     if (Opc == X86::FsFLD0SS)
6963       Ty = Type::getFloatTy(MF.getFunction()->getContext());
6964     else if (Opc == X86::FsFLD0SD)
6965       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
6966     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
6967       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
6968     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6969              Opc == X86::AVX512_256_SET0)
6970       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
6971     else
6972       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
6973 
6974     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6975                       Opc == X86::AVX512_512_SETALLONES);
6976     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6977                                     Constant::getNullValue(Ty);
6978     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6979 
6980     // Create operands to load from the constant pool entry.
6981     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6982     MOs.push_back(MachineOperand::CreateImm(1));
6983     MOs.push_back(MachineOperand::CreateReg(0, false));
6984     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6985     MOs.push_back(MachineOperand::CreateReg(0, false));
6986     break;
6987   }
6988   default: {
6989     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6990       return nullptr;
6991 
6992     // Folding a normal load. Just copy the load's address operands.
6993     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6994                LoadMI.operands_begin() + NumOps);
6995     break;
6996   }
6997   }
6998   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6999                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
7000 }
7001 
7002 bool X86InstrInfo::unfoldMemoryOperand(
7003     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
7004     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
7005   auto I = MemOp2RegOpTable.find(MI.getOpcode());
7006   if (I == MemOp2RegOpTable.end())
7007     return false;
7008   unsigned Opc = I->second.first;
7009   unsigned Index = I->second.second & TB_INDEX_MASK;
7010   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
7011   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
7012   if (UnfoldLoad && !FoldedLoad)
7013     return false;
7014   UnfoldLoad &= FoldedLoad;
7015   if (UnfoldStore && !FoldedStore)
7016     return false;
7017   UnfoldStore &= FoldedStore;
7018 
7019   const MCInstrDesc &MCID = get(Opc);
7020   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
7021   // TODO: Check if 32-byte or greater accesses are slow too?
7022   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
7023       Subtarget.isUnalignedMem16Slow())
7024     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
7025     // conservatively assume the address is unaligned. That's bad for
7026     // performance.
7027     return false;
7028   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
7029   SmallVector<MachineOperand,2> BeforeOps;
7030   SmallVector<MachineOperand,2> AfterOps;
7031   SmallVector<MachineOperand,4> ImpOps;
7032   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
7033     MachineOperand &Op = MI.getOperand(i);
7034     if (i >= Index && i < Index + X86::AddrNumOperands)
7035       AddrOps.push_back(Op);
7036     else if (Op.isReg() && Op.isImplicit())
7037       ImpOps.push_back(Op);
7038     else if (i < Index)
7039       BeforeOps.push_back(Op);
7040     else if (i > Index)
7041       AfterOps.push_back(Op);
7042   }
7043 
7044   // Emit the load instruction.
7045   if (UnfoldLoad) {
7046     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
7047         MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
7048     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
7049     if (UnfoldStore) {
7050       // Address operands cannot be marked isKill.
7051       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
7052         MachineOperand &MO = NewMIs[0]->getOperand(i);
7053         if (MO.isReg())
7054           MO.setIsKill(false);
7055       }
7056     }
7057   }
7058 
7059   // Emit the data processing instruction.
7060   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
7061   MachineInstrBuilder MIB(MF, DataMI);
7062 
7063   if (FoldedStore)
7064     MIB.addReg(Reg, RegState::Define);
7065   for (MachineOperand &BeforeOp : BeforeOps)
7066     MIB.addOperand(BeforeOp);
7067   if (FoldedLoad)
7068     MIB.addReg(Reg);
7069   for (MachineOperand &AfterOp : AfterOps)
7070     MIB.addOperand(AfterOp);
7071   for (MachineOperand &ImpOp : ImpOps) {
7072     MIB.addReg(ImpOp.getReg(),
7073                getDefRegState(ImpOp.isDef()) |
7074                RegState::Implicit |
7075                getKillRegState(ImpOp.isKill()) |
7076                getDeadRegState(ImpOp.isDead()) |
7077                getUndefRegState(ImpOp.isUndef()));
7078   }
7079   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
7080   switch (DataMI->getOpcode()) {
7081   default: break;
7082   case X86::CMP64ri32:
7083   case X86::CMP64ri8:
7084   case X86::CMP32ri:
7085   case X86::CMP32ri8:
7086   case X86::CMP16ri:
7087   case X86::CMP16ri8:
7088   case X86::CMP8ri: {
7089     MachineOperand &MO0 = DataMI->getOperand(0);
7090     MachineOperand &MO1 = DataMI->getOperand(1);
7091     if (MO1.getImm() == 0) {
7092       unsigned NewOpc;
7093       switch (DataMI->getOpcode()) {
7094       default: llvm_unreachable("Unreachable!");
7095       case X86::CMP64ri8:
7096       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
7097       case X86::CMP32ri8:
7098       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
7099       case X86::CMP16ri8:
7100       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
7101       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
7102       }
7103       DataMI->setDesc(get(NewOpc));
7104       MO1.ChangeToRegister(MO0.getReg(), false);
7105     }
7106   }
7107   }
7108   NewMIs.push_back(DataMI);
7109 
7110   // Emit the store instruction.
7111   if (UnfoldStore) {
7112     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
7113     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
7114         MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
7115     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
7116   }
7117 
7118   return true;
7119 }
7120 
7121 bool
7122 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
7123                                   SmallVectorImpl<SDNode*> &NewNodes) const {
7124   if (!N->isMachineOpcode())
7125     return false;
7126 
7127   auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
7128   if (I == MemOp2RegOpTable.end())
7129     return false;
7130   unsigned Opc = I->second.first;
7131   unsigned Index = I->second.second & TB_INDEX_MASK;
7132   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
7133   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
7134   const MCInstrDesc &MCID = get(Opc);
7135   MachineFunction &MF = DAG.getMachineFunction();
7136   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
7137   unsigned NumDefs = MCID.NumDefs;
7138   std::vector<SDValue> AddrOps;
7139   std::vector<SDValue> BeforeOps;
7140   std::vector<SDValue> AfterOps;
7141   SDLoc dl(N);
7142   unsigned NumOps = N->getNumOperands();
7143   for (unsigned i = 0; i != NumOps-1; ++i) {
7144     SDValue Op = N->getOperand(i);
7145     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
7146       AddrOps.push_back(Op);
7147     else if (i < Index-NumDefs)
7148       BeforeOps.push_back(Op);
7149     else if (i > Index-NumDefs)
7150       AfterOps.push_back(Op);
7151   }
7152   SDValue Chain = N->getOperand(NumOps-1);
7153   AddrOps.push_back(Chain);
7154 
7155   // Emit the load instruction.
7156   SDNode *Load = nullptr;
7157   if (FoldedLoad) {
7158     EVT VT = *RC->vt_begin();
7159     std::pair<MachineInstr::mmo_iterator,
7160               MachineInstr::mmo_iterator> MMOs =
7161       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
7162                             cast<MachineSDNode>(N)->memoperands_end());
7163     if (!(*MMOs.first) &&
7164         RC == &X86::VR128RegClass &&
7165         Subtarget.isUnalignedMem16Slow())
7166       // Do not introduce a slow unaligned load.
7167       return false;
7168     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
7169     // memory access is slow above.
7170     unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
7171     bool isAligned = (*MMOs.first) &&
7172                      (*MMOs.first)->getAlignment() >= Alignment;
7173     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
7174                               VT, MVT::Other, AddrOps);
7175     NewNodes.push_back(Load);
7176 
7177     // Preserve memory reference information.
7178     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
7179   }
7180 
7181   // Emit the data processing instruction.
7182   std::vector<EVT> VTs;
7183   const TargetRegisterClass *DstRC = nullptr;
7184   if (MCID.getNumDefs() > 0) {
7185     DstRC = getRegClass(MCID, 0, &RI, MF);
7186     VTs.push_back(*DstRC->vt_begin());
7187   }
7188   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
7189     EVT VT = N->getValueType(i);
7190     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
7191       VTs.push_back(VT);
7192   }
7193   if (Load)
7194     BeforeOps.push_back(SDValue(Load, 0));
7195   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
7196   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
7197   NewNodes.push_back(NewNode);
7198 
7199   // Emit the store instruction.
7200   if (FoldedStore) {
7201     AddrOps.pop_back();
7202     AddrOps.push_back(SDValue(NewNode, 0));
7203     AddrOps.push_back(Chain);
7204     std::pair<MachineInstr::mmo_iterator,
7205               MachineInstr::mmo_iterator> MMOs =
7206       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
7207                              cast<MachineSDNode>(N)->memoperands_end());
7208     if (!(*MMOs.first) &&
7209         RC == &X86::VR128RegClass &&
7210         Subtarget.isUnalignedMem16Slow())
7211       // Do not introduce a slow unaligned store.
7212       return false;
7213     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
7214     // memory access is slow above.
7215     unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
7216     bool isAligned = (*MMOs.first) &&
7217                      (*MMOs.first)->getAlignment() >= Alignment;
7218     SDNode *Store =
7219         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
7220                            dl, MVT::Other, AddrOps);
7221     NewNodes.push_back(Store);
7222 
7223     // Preserve memory reference information.
7224     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
7225   }
7226 
7227   return true;
7228 }
7229 
7230 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
7231                                       bool UnfoldLoad, bool UnfoldStore,
7232                                       unsigned *LoadRegIndex) const {
7233   auto I = MemOp2RegOpTable.find(Opc);
7234   if (I == MemOp2RegOpTable.end())
7235     return 0;
7236   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
7237   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
7238   if (UnfoldLoad && !FoldedLoad)
7239     return 0;
7240   if (UnfoldStore && !FoldedStore)
7241     return 0;
7242   if (LoadRegIndex)
7243     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
7244   return I->second.first;
7245 }
7246 
7247 bool
7248 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
7249                                      int64_t &Offset1, int64_t &Offset2) const {
7250   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
7251     return false;
7252   unsigned Opc1 = Load1->getMachineOpcode();
7253   unsigned Opc2 = Load2->getMachineOpcode();
7254   switch (Opc1) {
7255   default: return false;
7256   case X86::MOV8rm:
7257   case X86::MOV16rm:
7258   case X86::MOV32rm:
7259   case X86::MOV64rm:
7260   case X86::LD_Fp32m:
7261   case X86::LD_Fp64m:
7262   case X86::LD_Fp80m:
7263   case X86::MOVSSrm:
7264   case X86::MOVSDrm:
7265   case X86::MMX_MOVD64rm:
7266   case X86::MMX_MOVQ64rm:
7267   case X86::MOVAPSrm:
7268   case X86::MOVUPSrm:
7269   case X86::MOVAPDrm:
7270   case X86::MOVUPDrm:
7271   case X86::MOVDQArm:
7272   case X86::MOVDQUrm:
7273   // AVX load instructions
7274   case X86::VMOVSSrm:
7275   case X86::VMOVSDrm:
7276   case X86::VMOVAPSrm:
7277   case X86::VMOVUPSrm:
7278   case X86::VMOVAPDrm:
7279   case X86::VMOVUPDrm:
7280   case X86::VMOVDQArm:
7281   case X86::VMOVDQUrm:
7282   case X86::VMOVAPSYrm:
7283   case X86::VMOVUPSYrm:
7284   case X86::VMOVAPDYrm:
7285   case X86::VMOVUPDYrm:
7286   case X86::VMOVDQAYrm:
7287   case X86::VMOVDQUYrm:
7288   // AVX512 load instructions
7289   case X86::VMOVSSZrm:
7290   case X86::VMOVSDZrm:
7291   case X86::VMOVAPSZ128rm:
7292   case X86::VMOVUPSZ128rm:
7293   case X86::VMOVAPSZ128rm_NOVLX:
7294   case X86::VMOVUPSZ128rm_NOVLX:
7295   case X86::VMOVAPDZ128rm:
7296   case X86::VMOVUPDZ128rm:
7297   case X86::VMOVDQU8Z128rm:
7298   case X86::VMOVDQU16Z128rm:
7299   case X86::VMOVDQA32Z128rm:
7300   case X86::VMOVDQU32Z128rm:
7301   case X86::VMOVDQA64Z128rm:
7302   case X86::VMOVDQU64Z128rm:
7303   case X86::VMOVAPSZ256rm:
7304   case X86::VMOVUPSZ256rm:
7305   case X86::VMOVAPSZ256rm_NOVLX:
7306   case X86::VMOVUPSZ256rm_NOVLX:
7307   case X86::VMOVAPDZ256rm:
7308   case X86::VMOVUPDZ256rm:
7309   case X86::VMOVDQU8Z256rm:
7310   case X86::VMOVDQU16Z256rm:
7311   case X86::VMOVDQA32Z256rm:
7312   case X86::VMOVDQU32Z256rm:
7313   case X86::VMOVDQA64Z256rm:
7314   case X86::VMOVDQU64Z256rm:
7315   case X86::VMOVAPSZrm:
7316   case X86::VMOVUPSZrm:
7317   case X86::VMOVAPDZrm:
7318   case X86::VMOVUPDZrm:
7319   case X86::VMOVDQU8Zrm:
7320   case X86::VMOVDQU16Zrm:
7321   case X86::VMOVDQA32Zrm:
7322   case X86::VMOVDQU32Zrm:
7323   case X86::VMOVDQA64Zrm:
7324   case X86::VMOVDQU64Zrm:
7325   case X86::KMOVBkm:
7326   case X86::KMOVWkm:
7327   case X86::KMOVDkm:
7328   case X86::KMOVQkm:
7329     break;
7330   }
7331   switch (Opc2) {
7332   default: return false;
7333   case X86::MOV8rm:
7334   case X86::MOV16rm:
7335   case X86::MOV32rm:
7336   case X86::MOV64rm:
7337   case X86::LD_Fp32m:
7338   case X86::LD_Fp64m:
7339   case X86::LD_Fp80m:
7340   case X86::MOVSSrm:
7341   case X86::MOVSDrm:
7342   case X86::MMX_MOVD64rm:
7343   case X86::MMX_MOVQ64rm:
7344   case X86::MOVAPSrm:
7345   case X86::MOVUPSrm:
7346   case X86::MOVAPDrm:
7347   case X86::MOVUPDrm:
7348   case X86::MOVDQArm:
7349   case X86::MOVDQUrm:
7350   // AVX load instructions
7351   case X86::VMOVSSrm:
7352   case X86::VMOVSDrm:
7353   case X86::VMOVAPSrm:
7354   case X86::VMOVUPSrm:
7355   case X86::VMOVAPDrm:
7356   case X86::VMOVUPDrm:
7357   case X86::VMOVDQArm:
7358   case X86::VMOVDQUrm:
7359   case X86::VMOVAPSYrm:
7360   case X86::VMOVUPSYrm:
7361   case X86::VMOVAPDYrm:
7362   case X86::VMOVUPDYrm:
7363   case X86::VMOVDQAYrm:
7364   case X86::VMOVDQUYrm:
7365   // AVX512 load instructions
7366   case X86::VMOVSSZrm:
7367   case X86::VMOVSDZrm:
7368   case X86::VMOVAPSZ128rm:
7369   case X86::VMOVUPSZ128rm:
7370   case X86::VMOVAPSZ128rm_NOVLX:
7371   case X86::VMOVUPSZ128rm_NOVLX:
7372   case X86::VMOVAPDZ128rm:
7373   case X86::VMOVUPDZ128rm:
7374   case X86::VMOVDQU8Z128rm:
7375   case X86::VMOVDQU16Z128rm:
7376   case X86::VMOVDQA32Z128rm:
7377   case X86::VMOVDQU32Z128rm:
7378   case X86::VMOVDQA64Z128rm:
7379   case X86::VMOVDQU64Z128rm:
7380   case X86::VMOVAPSZ256rm:
7381   case X86::VMOVUPSZ256rm:
7382   case X86::VMOVAPSZ256rm_NOVLX:
7383   case X86::VMOVUPSZ256rm_NOVLX:
7384   case X86::VMOVAPDZ256rm:
7385   case X86::VMOVUPDZ256rm:
7386   case X86::VMOVDQU8Z256rm:
7387   case X86::VMOVDQU16Z256rm:
7388   case X86::VMOVDQA32Z256rm:
7389   case X86::VMOVDQU32Z256rm:
7390   case X86::VMOVDQA64Z256rm:
7391   case X86::VMOVDQU64Z256rm:
7392   case X86::VMOVAPSZrm:
7393   case X86::VMOVUPSZrm:
7394   case X86::VMOVAPDZrm:
7395   case X86::VMOVUPDZrm:
7396   case X86::VMOVDQU8Zrm:
7397   case X86::VMOVDQU16Zrm:
7398   case X86::VMOVDQA32Zrm:
7399   case X86::VMOVDQU32Zrm:
7400   case X86::VMOVDQA64Zrm:
7401   case X86::VMOVDQU64Zrm:
7402   case X86::KMOVBkm:
7403   case X86::KMOVWkm:
7404   case X86::KMOVDkm:
7405   case X86::KMOVQkm:
7406     break;
7407   }
7408 
7409   // Check if chain operands and base addresses match.
7410   if (Load1->getOperand(0) != Load2->getOperand(0) ||
7411       Load1->getOperand(5) != Load2->getOperand(5))
7412     return false;
7413   // Segment operands should match as well.
7414   if (Load1->getOperand(4) != Load2->getOperand(4))
7415     return false;
7416   // Scale should be 1, Index should be Reg0.
7417   if (Load1->getOperand(1) == Load2->getOperand(1) &&
7418       Load1->getOperand(2) == Load2->getOperand(2)) {
7419     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
7420       return false;
7421 
7422     // Now let's examine the displacements.
7423     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
7424         isa<ConstantSDNode>(Load2->getOperand(3))) {
7425       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
7426       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
7427       return true;
7428     }
7429   }
7430   return false;
7431 }
7432 
7433 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
7434                                            int64_t Offset1, int64_t Offset2,
7435                                            unsigned NumLoads) const {
7436   assert(Offset2 > Offset1);
7437   if ((Offset2 - Offset1) / 8 > 64)
7438     return false;
7439 
7440   unsigned Opc1 = Load1->getMachineOpcode();
7441   unsigned Opc2 = Load2->getMachineOpcode();
7442   if (Opc1 != Opc2)
7443     return false;  // FIXME: overly conservative?
7444 
7445   switch (Opc1) {
7446   default: break;
7447   case X86::LD_Fp32m:
7448   case X86::LD_Fp64m:
7449   case X86::LD_Fp80m:
7450   case X86::MMX_MOVD64rm:
7451   case X86::MMX_MOVQ64rm:
7452     return false;
7453   }
7454 
7455   EVT VT = Load1->getValueType(0);
7456   switch (VT.getSimpleVT().SimpleTy) {
7457   default:
7458     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
7459     // have 16 of them to play with.
7460     if (Subtarget.is64Bit()) {
7461       if (NumLoads >= 3)
7462         return false;
7463     } else if (NumLoads) {
7464       return false;
7465     }
7466     break;
7467   case MVT::i8:
7468   case MVT::i16:
7469   case MVT::i32:
7470   case MVT::i64:
7471   case MVT::f32:
7472   case MVT::f64:
7473     if (NumLoads)
7474       return false;
7475     break;
7476   }
7477 
7478   return true;
7479 }
7480 
7481 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr &First,
7482                                           MachineInstr &Second) const {
7483   // Check if this processor supports macro-fusion. Since this is a minor
7484   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
7485   // proxy for SandyBridge+.
7486   if (!Subtarget.hasAVX())
7487     return false;
7488 
7489   enum {
7490     FuseTest,
7491     FuseCmp,
7492     FuseInc
7493   } FuseKind;
7494 
7495   switch (Second.getOpcode()) {
7496   default:
7497     return false;
7498   case X86::JE_1:
7499   case X86::JNE_1:
7500   case X86::JL_1:
7501   case X86::JLE_1:
7502   case X86::JG_1:
7503   case X86::JGE_1:
7504     FuseKind = FuseInc;
7505     break;
7506   case X86::JB_1:
7507   case X86::JBE_1:
7508   case X86::JA_1:
7509   case X86::JAE_1:
7510     FuseKind = FuseCmp;
7511     break;
7512   case X86::JS_1:
7513   case X86::JNS_1:
7514   case X86::JP_1:
7515   case X86::JNP_1:
7516   case X86::JO_1:
7517   case X86::JNO_1:
7518     FuseKind = FuseTest;
7519     break;
7520   }
7521   switch (First.getOpcode()) {
7522   default:
7523     return false;
7524   case X86::TEST8rr:
7525   case X86::TEST16rr:
7526   case X86::TEST32rr:
7527   case X86::TEST64rr:
7528   case X86::TEST8ri:
7529   case X86::TEST16ri:
7530   case X86::TEST32ri:
7531   case X86::TEST32i32:
7532   case X86::TEST64i32:
7533   case X86::TEST64ri32:
7534   case X86::TEST8rm:
7535   case X86::TEST16rm:
7536   case X86::TEST32rm:
7537   case X86::TEST64rm:
7538   case X86::TEST8ri_NOREX:
7539   case X86::AND16i16:
7540   case X86::AND16ri:
7541   case X86::AND16ri8:
7542   case X86::AND16rm:
7543   case X86::AND16rr:
7544   case X86::AND32i32:
7545   case X86::AND32ri:
7546   case X86::AND32ri8:
7547   case X86::AND32rm:
7548   case X86::AND32rr:
7549   case X86::AND64i32:
7550   case X86::AND64ri32:
7551   case X86::AND64ri8:
7552   case X86::AND64rm:
7553   case X86::AND64rr:
7554   case X86::AND8i8:
7555   case X86::AND8ri:
7556   case X86::AND8rm:
7557   case X86::AND8rr:
7558     return true;
7559   case X86::CMP16i16:
7560   case X86::CMP16ri:
7561   case X86::CMP16ri8:
7562   case X86::CMP16rm:
7563   case X86::CMP16rr:
7564   case X86::CMP32i32:
7565   case X86::CMP32ri:
7566   case X86::CMP32ri8:
7567   case X86::CMP32rm:
7568   case X86::CMP32rr:
7569   case X86::CMP64i32:
7570   case X86::CMP64ri32:
7571   case X86::CMP64ri8:
7572   case X86::CMP64rm:
7573   case X86::CMP64rr:
7574   case X86::CMP8i8:
7575   case X86::CMP8ri:
7576   case X86::CMP8rm:
7577   case X86::CMP8rr:
7578   case X86::ADD16i16:
7579   case X86::ADD16ri:
7580   case X86::ADD16ri8:
7581   case X86::ADD16ri8_DB:
7582   case X86::ADD16ri_DB:
7583   case X86::ADD16rm:
7584   case X86::ADD16rr:
7585   case X86::ADD16rr_DB:
7586   case X86::ADD32i32:
7587   case X86::ADD32ri:
7588   case X86::ADD32ri8:
7589   case X86::ADD32ri8_DB:
7590   case X86::ADD32ri_DB:
7591   case X86::ADD32rm:
7592   case X86::ADD32rr:
7593   case X86::ADD32rr_DB:
7594   case X86::ADD64i32:
7595   case X86::ADD64ri32:
7596   case X86::ADD64ri32_DB:
7597   case X86::ADD64ri8:
7598   case X86::ADD64ri8_DB:
7599   case X86::ADD64rm:
7600   case X86::ADD64rr:
7601   case X86::ADD64rr_DB:
7602   case X86::ADD8i8:
7603   case X86::ADD8mi:
7604   case X86::ADD8mr:
7605   case X86::ADD8ri:
7606   case X86::ADD8rm:
7607   case X86::ADD8rr:
7608   case X86::SUB16i16:
7609   case X86::SUB16ri:
7610   case X86::SUB16ri8:
7611   case X86::SUB16rm:
7612   case X86::SUB16rr:
7613   case X86::SUB32i32:
7614   case X86::SUB32ri:
7615   case X86::SUB32ri8:
7616   case X86::SUB32rm:
7617   case X86::SUB32rr:
7618   case X86::SUB64i32:
7619   case X86::SUB64ri32:
7620   case X86::SUB64ri8:
7621   case X86::SUB64rm:
7622   case X86::SUB64rr:
7623   case X86::SUB8i8:
7624   case X86::SUB8ri:
7625   case X86::SUB8rm:
7626   case X86::SUB8rr:
7627     return FuseKind == FuseCmp || FuseKind == FuseInc;
7628   case X86::INC16r:
7629   case X86::INC32r:
7630   case X86::INC64r:
7631   case X86::INC8r:
7632   case X86::DEC16r:
7633   case X86::DEC32r:
7634   case X86::DEC64r:
7635   case X86::DEC8r:
7636     return FuseKind == FuseInc;
7637   }
7638 }
7639 
7640 bool X86InstrInfo::
7641 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
7642   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
7643   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
7644   Cond[0].setImm(GetOppositeBranchCondition(CC));
7645   return false;
7646 }
7647 
7648 bool X86InstrInfo::
7649 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
7650   // FIXME: Return false for x87 stack register classes for now. We can't
7651   // allow any loads of these registers before FpGet_ST0_80.
7652   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
7653            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
7654 }
7655 
7656 /// Return a virtual register initialized with the
7657 /// the global base register value. Output instructions required to
7658 /// initialize the register in the function entry block, if necessary.
7659 ///
7660 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
7661 ///
7662 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
7663   assert(!Subtarget.is64Bit() &&
7664          "X86-64 PIC uses RIP relative addressing");
7665 
7666   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
7667   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7668   if (GlobalBaseReg != 0)
7669     return GlobalBaseReg;
7670 
7671   // Create the register. The code to initialize it is inserted
7672   // later, by the CGBR pass (below).
7673   MachineRegisterInfo &RegInfo = MF->getRegInfo();
7674   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
7675   X86FI->setGlobalBaseReg(GlobalBaseReg);
7676   return GlobalBaseReg;
7677 }
7678 
7679 // These are the replaceable SSE instructions. Some of these have Int variants
7680 // that we don't include here. We don't want to replace instructions selected
7681 // by intrinsics.
7682 static const uint16_t ReplaceableInstrs[][3] = {
7683   //PackedSingle     PackedDouble    PackedInt
7684   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
7685   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
7686   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
7687   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
7688   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
7689   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr  },
7690   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
7691   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
7692   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
7693   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
7694   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
7695   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
7696   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
7697   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
7698   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
7699   // AVX 128-bit support
7700   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
7701   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
7702   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
7703   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
7704   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
7705   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr  },
7706   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
7707   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
7708   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
7709   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
7710   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
7711   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
7712   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
7713   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
7714   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
7715   // AVX 256-bit support
7716   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
7717   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
7718   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
7719   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
7720   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
7721   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
7722   // AVX512 support
7723   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
7724   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7725   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
7726   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
7727   { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
7728   { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
7729   { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
7730   { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
7731   { X86::VBROADCASTSSZr,    X86::VBROADCASTSSZr,    X86::VPBROADCASTDZr },
7732   { X86::VBROADCASTSSZm,    X86::VBROADCASTSSZm,    X86::VPBROADCASTDZm },
7733   { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
7734   { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
7735   { X86::VBROADCASTSDZr,    X86::VBROADCASTSDZr,    X86::VPBROADCASTQZr },
7736   { X86::VBROADCASTSDZm,    X86::VBROADCASTSDZm,    X86::VPBROADCASTQZm },
7737 };
7738 
7739 static const uint16_t ReplaceableInstrsAVX2[][3] = {
7740   //PackedSingle       PackedDouble       PackedInt
7741   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
7742   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
7743   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
7744   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
7745   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
7746   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
7747   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
7748   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
7749   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7750   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7751   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
7752   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
7753   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
7754   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
7755   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
7756   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
7757   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7758   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7759   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7760   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
7761   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
7762 };
7763 
7764 static const uint16_t ReplaceableInstrsAVX512[][4] = {
7765   // Two integer columns for 64-bit and 32-bit elements.
7766   //PackedSingle        PackedDouble        PackedInt             PackedInt
7767   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
7768   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
7769   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
7770   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
7771   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
7772   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
7773   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
7774   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
7775   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
7776   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
7777   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
7778   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
7779   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
7780   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
7781   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
7782 };
7783 
7784 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7785   // Two integer columns for 64-bit and 32-bit elements.
7786   //PackedSingle        PackedDouble        PackedInt           PackedInt
7787   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7788   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7789   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7790   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7791   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7792   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7793   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7794   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7795   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7796   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7797   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7798   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7799   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7800   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7801   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7802   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7803   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
7804   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
7805   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
7806   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
7807   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
7808   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
7809   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
7810   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
7811 };
7812 
7813 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
7814   // Two integer columns for 64-bit and 32-bit elements.
7815   //PackedSingle          PackedDouble
7816   //PackedInt             PackedInt
7817   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
7818     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
7819   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
7820     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
7821   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
7822     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
7823   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
7824     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
7825   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
7826     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
7827   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
7828     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
7829   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
7830     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
7831   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
7832     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
7833   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
7834     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
7835   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
7836     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
7837   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
7838     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
7839   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
7840     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
7841   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
7842     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
7843   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
7844     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
7845   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
7846     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
7847   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
7848     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
7849   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
7850     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
7851   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
7852     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
7853   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
7854     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
7855   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
7856     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
7857   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
7858     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
7859   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
7860     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
7861   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
7862     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
7863   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
7864     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
7865   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
7866     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
7867   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
7868     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
7869   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
7870     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
7871   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
7872     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
7873   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
7874     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
7875   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
7876     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
7877   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
7878     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
7879   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
7880     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
7881   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
7882     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
7883   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
7884     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
7885   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
7886     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
7887   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
7888     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
7889   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
7890     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
7891   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
7892     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
7893   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
7894     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
7895   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
7896     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
7897   { X86::VORPSZrmk,       X86::VORPDZrmk,
7898     X86::VPORQZrmk,       X86::VPORDZrmk       },
7899   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
7900     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
7901   { X86::VORPSZrrk,       X86::VORPDZrrk,
7902     X86::VPORQZrrk,       X86::VPORDZrrk       },
7903   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
7904     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
7905   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
7906     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
7907   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
7908     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
7909   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
7910     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
7911   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
7912     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
7913   // Broadcast loads can be handled the same as masked operations to avoid
7914   // changing element size.
7915   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
7916     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
7917   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
7918     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
7919   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
7920     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
7921   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
7922     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
7923   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
7924     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
7925   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
7926     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
7927   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
7928     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
7929   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
7930     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
7931   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
7932     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
7933   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7934     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7935   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7936     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7937   { X86::VORPSZrmb,       X86::VORPDZrmb,
7938     X86::VPORQZrmb,       X86::VPORDZrmb       },
7939   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
7940     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
7941   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
7942     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
7943   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
7944     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
7945   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
7946     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
7947   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
7948     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
7949   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
7950     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
7951   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
7952     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
7953   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
7954     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
7955   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
7956     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
7957   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
7958     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
7959   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7960     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7961   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7962     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7963   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
7964     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
7965   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
7966     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
7967   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
7968     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
7969   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
7970     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
7971   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
7972     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
7973   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
7974     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
7975   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
7976     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
7977   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
7978     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
7979   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
7980     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
7981   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
7982     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
7983   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
7984     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
7985   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7986     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7987   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7988     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7989   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
7990     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
7991   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
7992     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
7993 };
7994 
7995 // FIXME: Some shuffle and unpack instructions have equivalents in different
7996 // domains, but they require a bit more work than just switching opcodes.
7997 
7998 static const uint16_t *lookup(unsigned opcode, unsigned domain,
7999                               ArrayRef<uint16_t[3]> Table) {
8000   for (const uint16_t (&Row)[3] : Table)
8001     if (Row[domain-1] == opcode)
8002       return Row;
8003   return nullptr;
8004 }
8005 
8006 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
8007                                     ArrayRef<uint16_t[4]> Table) {
8008   // If this is the integer domain make sure to check both integer columns.
8009   for (const uint16_t (&Row)[4] : Table)
8010     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
8011       return Row;
8012   return nullptr;
8013 }
8014 
8015 std::pair<uint16_t, uint16_t>
8016 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
8017   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
8018   unsigned opcode = MI.getOpcode();
8019   uint16_t validDomains = 0;
8020   if (domain) {
8021     if (lookup(MI.getOpcode(), domain, ReplaceableInstrs)) {
8022       validDomains = 0xe;
8023     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
8024       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
8025     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
8026       validDomains = 0xe;
8027     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512DQ)) {
8028       validDomains = Subtarget.hasDQI() ? 0xe : 0x8;
8029     } else if (const uint16_t *table = lookupAVX512(opcode, domain,
8030                                              ReplaceableInstrsAVX512DQMasked)) {
8031       if (domain == 1 || (domain == 3 && table[3] == opcode))
8032         validDomains = Subtarget.hasDQI() ? 0xa : 0x8;
8033       else
8034         validDomains = Subtarget.hasDQI() ? 0xc : 0x8;
8035     }
8036   }
8037   return std::make_pair(domain, validDomains);
8038 }
8039 
8040 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
8041   assert(Domain>0 && Domain<4 && "Invalid execution domain");
8042   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
8043   assert(dom && "Not an SSE instruction");
8044   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
8045   if (!table) { // try the other table
8046     assert((Subtarget.hasAVX2() || Domain < 3) &&
8047            "256-bit vector operations only available in AVX2");
8048     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
8049   }
8050   if (!table) { // try the AVX512 table
8051     assert(Subtarget.hasAVX512() && "Requires AVX-512");
8052     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
8053     // Don't change integer Q instructions to D instructions.
8054     if (table && Domain == 3 && table[3] == MI.getOpcode())
8055       Domain = 4;
8056   }
8057   if (!table) { // try the AVX512DQ table
8058     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
8059     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
8060     // Don't change integer Q instructions to D instructions and
8061     // use D intructions if we started with a PS instruction.
8062     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
8063       Domain = 4;
8064   }
8065   if (!table) { // try the AVX512DQMasked table
8066     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
8067     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
8068     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
8069       Domain = 4;
8070   }
8071   assert(table && "Cannot change domain");
8072   MI.setDesc(get(table[Domain - 1]));
8073 }
8074 
8075 /// Return the noop instruction to use for a noop.
8076 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
8077   NopInst.setOpcode(X86::NOOP);
8078 }
8079 
8080 bool X86InstrInfo::isHighLatencyDef(int opc) const {
8081   switch (opc) {
8082   default: return false;
8083   case X86::DIVPDrm:
8084   case X86::DIVPDrr:
8085   case X86::DIVPSrm:
8086   case X86::DIVPSrr:
8087   case X86::DIVSDrm:
8088   case X86::DIVSDrm_Int:
8089   case X86::DIVSDrr:
8090   case X86::DIVSDrr_Int:
8091   case X86::DIVSSrm:
8092   case X86::DIVSSrm_Int:
8093   case X86::DIVSSrr:
8094   case X86::DIVSSrr_Int:
8095   case X86::SQRTPDm:
8096   case X86::SQRTPDr:
8097   case X86::SQRTPSm:
8098   case X86::SQRTPSr:
8099   case X86::SQRTSDm:
8100   case X86::SQRTSDm_Int:
8101   case X86::SQRTSDr:
8102   case X86::SQRTSDr_Int:
8103   case X86::SQRTSSm:
8104   case X86::SQRTSSm_Int:
8105   case X86::SQRTSSr:
8106   case X86::SQRTSSr_Int:
8107   // AVX instructions with high latency
8108   case X86::VDIVPDrm:
8109   case X86::VDIVPDrr:
8110   case X86::VDIVPDYrm:
8111   case X86::VDIVPDYrr:
8112   case X86::VDIVPSrm:
8113   case X86::VDIVPSrr:
8114   case X86::VDIVPSYrm:
8115   case X86::VDIVPSYrr:
8116   case X86::VDIVSDrm:
8117   case X86::VDIVSDrm_Int:
8118   case X86::VDIVSDrr:
8119   case X86::VDIVSDrr_Int:
8120   case X86::VDIVSSrm:
8121   case X86::VDIVSSrm_Int:
8122   case X86::VDIVSSrr:
8123   case X86::VDIVSSrr_Int:
8124   case X86::VSQRTPDm:
8125   case X86::VSQRTPDr:
8126   case X86::VSQRTPDYm:
8127   case X86::VSQRTPDYr:
8128   case X86::VSQRTPSm:
8129   case X86::VSQRTPSr:
8130   case X86::VSQRTPSYm:
8131   case X86::VSQRTPSYr:
8132   case X86::VSQRTSDm:
8133   case X86::VSQRTSDm_Int:
8134   case X86::VSQRTSDr:
8135   case X86::VSQRTSDr_Int:
8136   case X86::VSQRTSSm:
8137   case X86::VSQRTSSm_Int:
8138   case X86::VSQRTSSr:
8139   case X86::VSQRTSSr_Int:
8140   // AVX512 instructions with high latency
8141   case X86::VDIVPDZ128rm:
8142   case X86::VDIVPDZ128rmb:
8143   case X86::VDIVPDZ128rmbk:
8144   case X86::VDIVPDZ128rmbkz:
8145   case X86::VDIVPDZ128rmk:
8146   case X86::VDIVPDZ128rmkz:
8147   case X86::VDIVPDZ128rr:
8148   case X86::VDIVPDZ128rrk:
8149   case X86::VDIVPDZ128rrkz:
8150   case X86::VDIVPDZ256rm:
8151   case X86::VDIVPDZ256rmb:
8152   case X86::VDIVPDZ256rmbk:
8153   case X86::VDIVPDZ256rmbkz:
8154   case X86::VDIVPDZ256rmk:
8155   case X86::VDIVPDZ256rmkz:
8156   case X86::VDIVPDZ256rr:
8157   case X86::VDIVPDZ256rrk:
8158   case X86::VDIVPDZ256rrkz:
8159   case X86::VDIVPDZrb:
8160   case X86::VDIVPDZrbk:
8161   case X86::VDIVPDZrbkz:
8162   case X86::VDIVPDZrm:
8163   case X86::VDIVPDZrmb:
8164   case X86::VDIVPDZrmbk:
8165   case X86::VDIVPDZrmbkz:
8166   case X86::VDIVPDZrmk:
8167   case X86::VDIVPDZrmkz:
8168   case X86::VDIVPDZrr:
8169   case X86::VDIVPDZrrk:
8170   case X86::VDIVPDZrrkz:
8171   case X86::VDIVPSZ128rm:
8172   case X86::VDIVPSZ128rmb:
8173   case X86::VDIVPSZ128rmbk:
8174   case X86::VDIVPSZ128rmbkz:
8175   case X86::VDIVPSZ128rmk:
8176   case X86::VDIVPSZ128rmkz:
8177   case X86::VDIVPSZ128rr:
8178   case X86::VDIVPSZ128rrk:
8179   case X86::VDIVPSZ128rrkz:
8180   case X86::VDIVPSZ256rm:
8181   case X86::VDIVPSZ256rmb:
8182   case X86::VDIVPSZ256rmbk:
8183   case X86::VDIVPSZ256rmbkz:
8184   case X86::VDIVPSZ256rmk:
8185   case X86::VDIVPSZ256rmkz:
8186   case X86::VDIVPSZ256rr:
8187   case X86::VDIVPSZ256rrk:
8188   case X86::VDIVPSZ256rrkz:
8189   case X86::VDIVPSZrb:
8190   case X86::VDIVPSZrbk:
8191   case X86::VDIVPSZrbkz:
8192   case X86::VDIVPSZrm:
8193   case X86::VDIVPSZrmb:
8194   case X86::VDIVPSZrmbk:
8195   case X86::VDIVPSZrmbkz:
8196   case X86::VDIVPSZrmk:
8197   case X86::VDIVPSZrmkz:
8198   case X86::VDIVPSZrr:
8199   case X86::VDIVPSZrrk:
8200   case X86::VDIVPSZrrkz:
8201   case X86::VDIVSDZrm:
8202   case X86::VDIVSDZrr:
8203   case X86::VDIVSDZrm_Int:
8204   case X86::VDIVSDZrm_Intk:
8205   case X86::VDIVSDZrm_Intkz:
8206   case X86::VDIVSDZrr_Int:
8207   case X86::VDIVSDZrr_Intk:
8208   case X86::VDIVSDZrr_Intkz:
8209   case X86::VDIVSDZrrb:
8210   case X86::VDIVSDZrrbk:
8211   case X86::VDIVSDZrrbkz:
8212   case X86::VDIVSSZrm:
8213   case X86::VDIVSSZrr:
8214   case X86::VDIVSSZrm_Int:
8215   case X86::VDIVSSZrm_Intk:
8216   case X86::VDIVSSZrm_Intkz:
8217   case X86::VDIVSSZrr_Int:
8218   case X86::VDIVSSZrr_Intk:
8219   case X86::VDIVSSZrr_Intkz:
8220   case X86::VDIVSSZrrb:
8221   case X86::VDIVSSZrrbk:
8222   case X86::VDIVSSZrrbkz:
8223   case X86::VSQRTPDZ128m:
8224   case X86::VSQRTPDZ128mb:
8225   case X86::VSQRTPDZ128mbk:
8226   case X86::VSQRTPDZ128mbkz:
8227   case X86::VSQRTPDZ128mk:
8228   case X86::VSQRTPDZ128mkz:
8229   case X86::VSQRTPDZ128r:
8230   case X86::VSQRTPDZ128rk:
8231   case X86::VSQRTPDZ128rkz:
8232   case X86::VSQRTPDZ256m:
8233   case X86::VSQRTPDZ256mb:
8234   case X86::VSQRTPDZ256mbk:
8235   case X86::VSQRTPDZ256mbkz:
8236   case X86::VSQRTPDZ256mk:
8237   case X86::VSQRTPDZ256mkz:
8238   case X86::VSQRTPDZ256r:
8239   case X86::VSQRTPDZ256rk:
8240   case X86::VSQRTPDZ256rkz:
8241   case X86::VSQRTPDZm:
8242   case X86::VSQRTPDZmb:
8243   case X86::VSQRTPDZmbk:
8244   case X86::VSQRTPDZmbkz:
8245   case X86::VSQRTPDZmk:
8246   case X86::VSQRTPDZmkz:
8247   case X86::VSQRTPDZr:
8248   case X86::VSQRTPDZrb:
8249   case X86::VSQRTPDZrbk:
8250   case X86::VSQRTPDZrbkz:
8251   case X86::VSQRTPDZrk:
8252   case X86::VSQRTPDZrkz:
8253   case X86::VSQRTPSZ128m:
8254   case X86::VSQRTPSZ128mb:
8255   case X86::VSQRTPSZ128mbk:
8256   case X86::VSQRTPSZ128mbkz:
8257   case X86::VSQRTPSZ128mk:
8258   case X86::VSQRTPSZ128mkz:
8259   case X86::VSQRTPSZ128r:
8260   case X86::VSQRTPSZ128rk:
8261   case X86::VSQRTPSZ128rkz:
8262   case X86::VSQRTPSZ256m:
8263   case X86::VSQRTPSZ256mb:
8264   case X86::VSQRTPSZ256mbk:
8265   case X86::VSQRTPSZ256mbkz:
8266   case X86::VSQRTPSZ256mk:
8267   case X86::VSQRTPSZ256mkz:
8268   case X86::VSQRTPSZ256r:
8269   case X86::VSQRTPSZ256rk:
8270   case X86::VSQRTPSZ256rkz:
8271   case X86::VSQRTPSZm:
8272   case X86::VSQRTPSZmb:
8273   case X86::VSQRTPSZmbk:
8274   case X86::VSQRTPSZmbkz:
8275   case X86::VSQRTPSZmk:
8276   case X86::VSQRTPSZmkz:
8277   case X86::VSQRTPSZr:
8278   case X86::VSQRTPSZrb:
8279   case X86::VSQRTPSZrbk:
8280   case X86::VSQRTPSZrbkz:
8281   case X86::VSQRTPSZrk:
8282   case X86::VSQRTPSZrkz:
8283   case X86::VSQRTSDZm:
8284   case X86::VSQRTSDZm_Int:
8285   case X86::VSQRTSDZm_Intk:
8286   case X86::VSQRTSDZm_Intkz:
8287   case X86::VSQRTSDZr:
8288   case X86::VSQRTSDZr_Int:
8289   case X86::VSQRTSDZr_Intk:
8290   case X86::VSQRTSDZr_Intkz:
8291   case X86::VSQRTSDZrb_Int:
8292   case X86::VSQRTSDZrb_Intk:
8293   case X86::VSQRTSDZrb_Intkz:
8294   case X86::VSQRTSSZm:
8295   case X86::VSQRTSSZm_Int:
8296   case X86::VSQRTSSZm_Intk:
8297   case X86::VSQRTSSZm_Intkz:
8298   case X86::VSQRTSSZr:
8299   case X86::VSQRTSSZr_Int:
8300   case X86::VSQRTSSZr_Intk:
8301   case X86::VSQRTSSZr_Intkz:
8302   case X86::VSQRTSSZrb_Int:
8303   case X86::VSQRTSSZrb_Intk:
8304   case X86::VSQRTSSZrb_Intkz:
8305 
8306   case X86::VGATHERDPDYrm:
8307   case X86::VGATHERDPDZ128rm:
8308   case X86::VGATHERDPDZ256rm:
8309   case X86::VGATHERDPDZrm:
8310   case X86::VGATHERDPDrm:
8311   case X86::VGATHERDPSYrm:
8312   case X86::VGATHERDPSZ128rm:
8313   case X86::VGATHERDPSZ256rm:
8314   case X86::VGATHERDPSZrm:
8315   case X86::VGATHERDPSrm:
8316   case X86::VGATHERPF0DPDm:
8317   case X86::VGATHERPF0DPSm:
8318   case X86::VGATHERPF0QPDm:
8319   case X86::VGATHERPF0QPSm:
8320   case X86::VGATHERPF1DPDm:
8321   case X86::VGATHERPF1DPSm:
8322   case X86::VGATHERPF1QPDm:
8323   case X86::VGATHERPF1QPSm:
8324   case X86::VGATHERQPDYrm:
8325   case X86::VGATHERQPDZ128rm:
8326   case X86::VGATHERQPDZ256rm:
8327   case X86::VGATHERQPDZrm:
8328   case X86::VGATHERQPDrm:
8329   case X86::VGATHERQPSYrm:
8330   case X86::VGATHERQPSZ128rm:
8331   case X86::VGATHERQPSZ256rm:
8332   case X86::VGATHERQPSZrm:
8333   case X86::VGATHERQPSrm:
8334   case X86::VPGATHERDDYrm:
8335   case X86::VPGATHERDDZ128rm:
8336   case X86::VPGATHERDDZ256rm:
8337   case X86::VPGATHERDDZrm:
8338   case X86::VPGATHERDDrm:
8339   case X86::VPGATHERDQYrm:
8340   case X86::VPGATHERDQZ128rm:
8341   case X86::VPGATHERDQZ256rm:
8342   case X86::VPGATHERDQZrm:
8343   case X86::VPGATHERDQrm:
8344   case X86::VPGATHERQDYrm:
8345   case X86::VPGATHERQDZ128rm:
8346   case X86::VPGATHERQDZ256rm:
8347   case X86::VPGATHERQDZrm:
8348   case X86::VPGATHERQDrm:
8349   case X86::VPGATHERQQYrm:
8350   case X86::VPGATHERQQZ128rm:
8351   case X86::VPGATHERQQZ256rm:
8352   case X86::VPGATHERQQZrm:
8353   case X86::VPGATHERQQrm:
8354   case X86::VSCATTERDPDZ128mr:
8355   case X86::VSCATTERDPDZ256mr:
8356   case X86::VSCATTERDPDZmr:
8357   case X86::VSCATTERDPSZ128mr:
8358   case X86::VSCATTERDPSZ256mr:
8359   case X86::VSCATTERDPSZmr:
8360   case X86::VSCATTERPF0DPDm:
8361   case X86::VSCATTERPF0DPSm:
8362   case X86::VSCATTERPF0QPDm:
8363   case X86::VSCATTERPF0QPSm:
8364   case X86::VSCATTERPF1DPDm:
8365   case X86::VSCATTERPF1DPSm:
8366   case X86::VSCATTERPF1QPDm:
8367   case X86::VSCATTERPF1QPSm:
8368   case X86::VSCATTERQPDZ128mr:
8369   case X86::VSCATTERQPDZ256mr:
8370   case X86::VSCATTERQPDZmr:
8371   case X86::VSCATTERQPSZ128mr:
8372   case X86::VSCATTERQPSZ256mr:
8373   case X86::VSCATTERQPSZmr:
8374   case X86::VPSCATTERDDZ128mr:
8375   case X86::VPSCATTERDDZ256mr:
8376   case X86::VPSCATTERDDZmr:
8377   case X86::VPSCATTERDQZ128mr:
8378   case X86::VPSCATTERDQZ256mr:
8379   case X86::VPSCATTERDQZmr:
8380   case X86::VPSCATTERQDZ128mr:
8381   case X86::VPSCATTERQDZ256mr:
8382   case X86::VPSCATTERQDZmr:
8383   case X86::VPSCATTERQQZ128mr:
8384   case X86::VPSCATTERQQZ256mr:
8385   case X86::VPSCATTERQQZmr:
8386     return true;
8387   }
8388 }
8389 
8390 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
8391                                          const MachineRegisterInfo *MRI,
8392                                          const MachineInstr &DefMI,
8393                                          unsigned DefIdx,
8394                                          const MachineInstr &UseMI,
8395                                          unsigned UseIdx) const {
8396   return isHighLatencyDef(DefMI.getOpcode());
8397 }
8398 
8399 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
8400                                            const MachineBasicBlock *MBB) const {
8401   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
8402          "Reassociation needs binary operators");
8403 
8404   // Integer binary math/logic instructions have a third source operand:
8405   // the EFLAGS register. That operand must be both defined here and never
8406   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
8407   // not change anything because rearranging the operands could affect other
8408   // instructions that depend on the exact status flags (zero, sign, etc.)
8409   // that are set by using these particular operands with this operation.
8410   if (Inst.getNumOperands() == 4) {
8411     assert(Inst.getOperand(3).isReg() &&
8412            Inst.getOperand(3).getReg() == X86::EFLAGS &&
8413            "Unexpected operand in reassociable instruction");
8414     if (!Inst.getOperand(3).isDead())
8415       return false;
8416   }
8417 
8418   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
8419 }
8420 
8421 // TODO: There are many more machine instruction opcodes to match:
8422 //       1. Other data types (integer, vectors)
8423 //       2. Other math / logic operations (xor, or)
8424 //       3. Other forms of the same operation (intrinsics and other variants)
8425 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
8426   switch (Inst.getOpcode()) {
8427   case X86::AND8rr:
8428   case X86::AND16rr:
8429   case X86::AND32rr:
8430   case X86::AND64rr:
8431   case X86::OR8rr:
8432   case X86::OR16rr:
8433   case X86::OR32rr:
8434   case X86::OR64rr:
8435   case X86::XOR8rr:
8436   case X86::XOR16rr:
8437   case X86::XOR32rr:
8438   case X86::XOR64rr:
8439   case X86::IMUL16rr:
8440   case X86::IMUL32rr:
8441   case X86::IMUL64rr:
8442   case X86::PANDrr:
8443   case X86::PORrr:
8444   case X86::PXORrr:
8445   case X86::ANDPDrr:
8446   case X86::ANDPSrr:
8447   case X86::ORPDrr:
8448   case X86::ORPSrr:
8449   case X86::XORPDrr:
8450   case X86::XORPSrr:
8451   case X86::PADDBrr:
8452   case X86::PADDWrr:
8453   case X86::PADDDrr:
8454   case X86::PADDQrr:
8455   case X86::VPANDrr:
8456   case X86::VPANDYrr:
8457   case X86::VPANDDZ128rr:
8458   case X86::VPANDDZ256rr:
8459   case X86::VPANDDZrr:
8460   case X86::VPANDQZ128rr:
8461   case X86::VPANDQZ256rr:
8462   case X86::VPANDQZrr:
8463   case X86::VPORrr:
8464   case X86::VPORYrr:
8465   case X86::VPORDZ128rr:
8466   case X86::VPORDZ256rr:
8467   case X86::VPORDZrr:
8468   case X86::VPORQZ128rr:
8469   case X86::VPORQZ256rr:
8470   case X86::VPORQZrr:
8471   case X86::VPXORrr:
8472   case X86::VPXORYrr:
8473   case X86::VPXORDZ128rr:
8474   case X86::VPXORDZ256rr:
8475   case X86::VPXORDZrr:
8476   case X86::VPXORQZ128rr:
8477   case X86::VPXORQZ256rr:
8478   case X86::VPXORQZrr:
8479   case X86::VANDPDrr:
8480   case X86::VANDPSrr:
8481   case X86::VANDPDYrr:
8482   case X86::VANDPSYrr:
8483   case X86::VANDPDZ128rr:
8484   case X86::VANDPSZ128rr:
8485   case X86::VANDPDZ256rr:
8486   case X86::VANDPSZ256rr:
8487   case X86::VANDPDZrr:
8488   case X86::VANDPSZrr:
8489   case X86::VORPDrr:
8490   case X86::VORPSrr:
8491   case X86::VORPDYrr:
8492   case X86::VORPSYrr:
8493   case X86::VORPDZ128rr:
8494   case X86::VORPSZ128rr:
8495   case X86::VORPDZ256rr:
8496   case X86::VORPSZ256rr:
8497   case X86::VORPDZrr:
8498   case X86::VORPSZrr:
8499   case X86::VXORPDrr:
8500   case X86::VXORPSrr:
8501   case X86::VXORPDYrr:
8502   case X86::VXORPSYrr:
8503   case X86::VXORPDZ128rr:
8504   case X86::VXORPSZ128rr:
8505   case X86::VXORPDZ256rr:
8506   case X86::VXORPSZ256rr:
8507   case X86::VXORPDZrr:
8508   case X86::VXORPSZrr:
8509   case X86::KADDBrr:
8510   case X86::KADDWrr:
8511   case X86::KADDDrr:
8512   case X86::KADDQrr:
8513   case X86::KANDBrr:
8514   case X86::KANDWrr:
8515   case X86::KANDDrr:
8516   case X86::KANDQrr:
8517   case X86::KORBrr:
8518   case X86::KORWrr:
8519   case X86::KORDrr:
8520   case X86::KORQrr:
8521   case X86::KXORBrr:
8522   case X86::KXORWrr:
8523   case X86::KXORDrr:
8524   case X86::KXORQrr:
8525   case X86::VPADDBrr:
8526   case X86::VPADDWrr:
8527   case X86::VPADDDrr:
8528   case X86::VPADDQrr:
8529   case X86::VPADDBYrr:
8530   case X86::VPADDWYrr:
8531   case X86::VPADDDYrr:
8532   case X86::VPADDQYrr:
8533   case X86::VPADDBZ128rr:
8534   case X86::VPADDWZ128rr:
8535   case X86::VPADDDZ128rr:
8536   case X86::VPADDQZ128rr:
8537   case X86::VPADDBZ256rr:
8538   case X86::VPADDWZ256rr:
8539   case X86::VPADDDZ256rr:
8540   case X86::VPADDQZ256rr:
8541   case X86::VPADDBZrr:
8542   case X86::VPADDWZrr:
8543   case X86::VPADDDZrr:
8544   case X86::VPADDQZrr:
8545   case X86::VPMULLWrr:
8546   case X86::VPMULLWYrr:
8547   case X86::VPMULLWZ128rr:
8548   case X86::VPMULLWZ256rr:
8549   case X86::VPMULLWZrr:
8550   case X86::VPMULLDrr:
8551   case X86::VPMULLDYrr:
8552   case X86::VPMULLDZ128rr:
8553   case X86::VPMULLDZ256rr:
8554   case X86::VPMULLDZrr:
8555   case X86::VPMULLQZ128rr:
8556   case X86::VPMULLQZ256rr:
8557   case X86::VPMULLQZrr:
8558   // Normal min/max instructions are not commutative because of NaN and signed
8559   // zero semantics, but these are. Thus, there's no need to check for global
8560   // relaxed math; the instructions themselves have the properties we need.
8561   case X86::MAXCPDrr:
8562   case X86::MAXCPSrr:
8563   case X86::MAXCSDrr:
8564   case X86::MAXCSSrr:
8565   case X86::MINCPDrr:
8566   case X86::MINCPSrr:
8567   case X86::MINCSDrr:
8568   case X86::MINCSSrr:
8569   case X86::VMAXCPDrr:
8570   case X86::VMAXCPSrr:
8571   case X86::VMAXCPDYrr:
8572   case X86::VMAXCPSYrr:
8573   case X86::VMAXCPDZ128rr:
8574   case X86::VMAXCPSZ128rr:
8575   case X86::VMAXCPDZ256rr:
8576   case X86::VMAXCPSZ256rr:
8577   case X86::VMAXCPDZrr:
8578   case X86::VMAXCPSZrr:
8579   case X86::VMAXCSDrr:
8580   case X86::VMAXCSSrr:
8581   case X86::VMAXCSDZrr:
8582   case X86::VMAXCSSZrr:
8583   case X86::VMINCPDrr:
8584   case X86::VMINCPSrr:
8585   case X86::VMINCPDYrr:
8586   case X86::VMINCPSYrr:
8587   case X86::VMINCPDZ128rr:
8588   case X86::VMINCPSZ128rr:
8589   case X86::VMINCPDZ256rr:
8590   case X86::VMINCPSZ256rr:
8591   case X86::VMINCPDZrr:
8592   case X86::VMINCPSZrr:
8593   case X86::VMINCSDrr:
8594   case X86::VMINCSSrr:
8595   case X86::VMINCSDZrr:
8596   case X86::VMINCSSZrr:
8597     return true;
8598   case X86::ADDPDrr:
8599   case X86::ADDPSrr:
8600   case X86::ADDSDrr:
8601   case X86::ADDSSrr:
8602   case X86::MULPDrr:
8603   case X86::MULPSrr:
8604   case X86::MULSDrr:
8605   case X86::MULSSrr:
8606   case X86::VADDPDrr:
8607   case X86::VADDPSrr:
8608   case X86::VADDPDYrr:
8609   case X86::VADDPSYrr:
8610   case X86::VADDPDZ128rr:
8611   case X86::VADDPSZ128rr:
8612   case X86::VADDPDZ256rr:
8613   case X86::VADDPSZ256rr:
8614   case X86::VADDPDZrr:
8615   case X86::VADDPSZrr:
8616   case X86::VADDSDrr:
8617   case X86::VADDSSrr:
8618   case X86::VADDSDZrr:
8619   case X86::VADDSSZrr:
8620   case X86::VMULPDrr:
8621   case X86::VMULPSrr:
8622   case X86::VMULPDYrr:
8623   case X86::VMULPSYrr:
8624   case X86::VMULPDZ128rr:
8625   case X86::VMULPSZ128rr:
8626   case X86::VMULPDZ256rr:
8627   case X86::VMULPSZ256rr:
8628   case X86::VMULPDZrr:
8629   case X86::VMULPSZrr:
8630   case X86::VMULSDrr:
8631   case X86::VMULSSrr:
8632   case X86::VMULSDZrr:
8633   case X86::VMULSSZrr:
8634     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
8635   default:
8636     return false;
8637   }
8638 }
8639 
8640 /// This is an architecture-specific helper function of reassociateOps.
8641 /// Set special operand attributes for new instructions after reassociation.
8642 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
8643                                          MachineInstr &OldMI2,
8644                                          MachineInstr &NewMI1,
8645                                          MachineInstr &NewMI2) const {
8646   // Integer instructions define an implicit EFLAGS source register operand as
8647   // the third source (fourth total) operand.
8648   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
8649     return;
8650 
8651   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
8652          "Unexpected instruction type for reassociation");
8653 
8654   MachineOperand &OldOp1 = OldMI1.getOperand(3);
8655   MachineOperand &OldOp2 = OldMI2.getOperand(3);
8656   MachineOperand &NewOp1 = NewMI1.getOperand(3);
8657   MachineOperand &NewOp2 = NewMI2.getOperand(3);
8658 
8659   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
8660          "Must have dead EFLAGS operand in reassociable instruction");
8661   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
8662          "Must have dead EFLAGS operand in reassociable instruction");
8663 
8664   (void)OldOp1;
8665   (void)OldOp2;
8666 
8667   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
8668          "Unexpected operand in reassociable instruction");
8669   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
8670          "Unexpected operand in reassociable instruction");
8671 
8672   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8673   // of this pass or other passes. The EFLAGS operands must be dead in these new
8674   // instructions because the EFLAGS operands in the original instructions must
8675   // be dead in order for reassociation to occur.
8676   NewOp1.setIsDead();
8677   NewOp2.setIsDead();
8678 }
8679 
8680 std::pair<unsigned, unsigned>
8681 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8682   return std::make_pair(TF, 0u);
8683 }
8684 
8685 ArrayRef<std::pair<unsigned, const char *>>
8686 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8687   using namespace X86II;
8688   static const std::pair<unsigned, const char *> TargetFlags[] = {
8689       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8690       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
8691       {MO_GOT, "x86-got"},
8692       {MO_GOTOFF, "x86-gotoff"},
8693       {MO_GOTPCREL, "x86-gotpcrel"},
8694       {MO_PLT, "x86-plt"},
8695       {MO_TLSGD, "x86-tlsgd"},
8696       {MO_TLSLD, "x86-tlsld"},
8697       {MO_TLSLDM, "x86-tlsldm"},
8698       {MO_GOTTPOFF, "x86-gottpoff"},
8699       {MO_INDNTPOFF, "x86-indntpoff"},
8700       {MO_TPOFF, "x86-tpoff"},
8701       {MO_DTPOFF, "x86-dtpoff"},
8702       {MO_NTPOFF, "x86-ntpoff"},
8703       {MO_GOTNTPOFF, "x86-gotntpoff"},
8704       {MO_DLLIMPORT, "x86-dllimport"},
8705       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
8706       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
8707       {MO_TLVP, "x86-tlvp"},
8708       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
8709       {MO_SECREL, "x86-secrel"}};
8710   return makeArrayRef(TargetFlags);
8711 }
8712 
8713 bool X86InstrInfo::isTailCall(const MachineInstr &Inst) const {
8714   switch (Inst.getOpcode()) {
8715     case X86::TCRETURNdi:
8716     case X86::TCRETURNmi:
8717     case X86::TCRETURNri:
8718     case X86::TCRETURNdi64:
8719     case X86::TCRETURNmi64:
8720     case X86::TCRETURNri64:
8721     case X86::TAILJMPd:
8722     case X86::TAILJMPm:
8723     case X86::TAILJMPr:
8724     case X86::TAILJMPd64:
8725     case X86::TAILJMPm64:
8726     case X86::TAILJMPr64:
8727     case X86::TAILJMPm64_REX:
8728     case X86::TAILJMPr64_REX:
8729       return true;
8730     default:
8731       return false;
8732   }
8733 }
8734 
8735 namespace {
8736   /// Create Global Base Reg pass. This initializes the PIC
8737   /// global base register for x86-32.
8738   struct CGBR : public MachineFunctionPass {
8739     static char ID;
8740     CGBR() : MachineFunctionPass(ID) {}
8741 
8742     bool runOnMachineFunction(MachineFunction &MF) override {
8743       const X86TargetMachine *TM =
8744         static_cast<const X86TargetMachine *>(&MF.getTarget());
8745       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
8746 
8747       // Don't do anything if this is 64-bit as 64-bit PIC
8748       // uses RIP relative addressing.
8749       if (STI.is64Bit())
8750         return false;
8751 
8752       // Only emit a global base reg in PIC mode.
8753       if (!TM->isPositionIndependent())
8754         return false;
8755 
8756       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8757       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
8758 
8759       // If we didn't need a GlobalBaseReg, don't insert code.
8760       if (GlobalBaseReg == 0)
8761         return false;
8762 
8763       // Insert the set of GlobalBaseReg into the first MBB of the function
8764       MachineBasicBlock &FirstMBB = MF.front();
8765       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
8766       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
8767       MachineRegisterInfo &RegInfo = MF.getRegInfo();
8768       const X86InstrInfo *TII = STI.getInstrInfo();
8769 
8770       unsigned PC;
8771       if (STI.isPICStyleGOT())
8772         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
8773       else
8774         PC = GlobalBaseReg;
8775 
8776       // Operand of MovePCtoStack is completely ignored by asm printer. It's
8777       // only used in JIT code emission as displacement to pc.
8778       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
8779 
8780       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
8781       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
8782       if (STI.isPICStyleGOT()) {
8783         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
8784         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
8785           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8786                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
8787       }
8788 
8789       return true;
8790     }
8791 
8792     StringRef getPassName() const override {
8793       return "X86 PIC Global Base Reg Initialization";
8794     }
8795 
8796     void getAnalysisUsage(AnalysisUsage &AU) const override {
8797       AU.setPreservesCFG();
8798       MachineFunctionPass::getAnalysisUsage(AU);
8799     }
8800   };
8801 }
8802 
8803 char CGBR::ID = 0;
8804 FunctionPass*
8805 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
8806 
8807 namespace {
8808   struct LDTLSCleanup : public MachineFunctionPass {
8809     static char ID;
8810     LDTLSCleanup() : MachineFunctionPass(ID) {}
8811 
8812     bool runOnMachineFunction(MachineFunction &MF) override {
8813       if (skipFunction(*MF.getFunction()))
8814         return false;
8815 
8816       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
8817       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8818         // No point folding accesses if there isn't at least two.
8819         return false;
8820       }
8821 
8822       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8823       return VisitNode(DT->getRootNode(), 0);
8824     }
8825 
8826     // Visit the dominator subtree rooted at Node in pre-order.
8827     // If TLSBaseAddrReg is non-null, then use that to replace any
8828     // TLS_base_addr instructions. Otherwise, create the register
8829     // when the first such instruction is seen, and then use it
8830     // as we encounter more instructions.
8831     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8832       MachineBasicBlock *BB = Node->getBlock();
8833       bool Changed = false;
8834 
8835       // Traverse the current block.
8836       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8837            ++I) {
8838         switch (I->getOpcode()) {
8839           case X86::TLS_base_addr32:
8840           case X86::TLS_base_addr64:
8841             if (TLSBaseAddrReg)
8842               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
8843             else
8844               I = SetRegister(*I, &TLSBaseAddrReg);
8845             Changed = true;
8846             break;
8847           default:
8848             break;
8849         }
8850       }
8851 
8852       // Visit the children of this block in the dominator tree.
8853       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
8854            I != E; ++I) {
8855         Changed |= VisitNode(*I, TLSBaseAddrReg);
8856       }
8857 
8858       return Changed;
8859     }
8860 
8861     // Replace the TLS_base_addr instruction I with a copy from
8862     // TLSBaseAddrReg, returning the new instruction.
8863     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
8864                                          unsigned TLSBaseAddrReg) {
8865       MachineFunction *MF = I.getParent()->getParent();
8866       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8867       const bool is64Bit = STI.is64Bit();
8868       const X86InstrInfo *TII = STI.getInstrInfo();
8869 
8870       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
8871       MachineInstr *Copy =
8872           BuildMI(*I.getParent(), I, I.getDebugLoc(),
8873                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8874               .addReg(TLSBaseAddrReg);
8875 
8876       // Erase the TLS_base_addr instruction.
8877       I.eraseFromParent();
8878 
8879       return Copy;
8880     }
8881 
8882     // Create a virtal register in *TLSBaseAddrReg, and populate it by
8883     // inserting a copy instruction after I. Returns the new instruction.
8884     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8885       MachineFunction *MF = I.getParent()->getParent();
8886       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8887       const bool is64Bit = STI.is64Bit();
8888       const X86InstrInfo *TII = STI.getInstrInfo();
8889 
8890       // Create a virtual register for the TLS base address.
8891       MachineRegisterInfo &RegInfo = MF->getRegInfo();
8892       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8893                                                       ? &X86::GR64RegClass
8894                                                       : &X86::GR32RegClass);
8895 
8896       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
8897       MachineInstr *Next = I.getNextNode();
8898       MachineInstr *Copy =
8899           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8900                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8901               .addReg(is64Bit ? X86::RAX : X86::EAX);
8902 
8903       return Copy;
8904     }
8905 
8906     StringRef getPassName() const override {
8907       return "Local Dynamic TLS Access Clean-up";
8908     }
8909 
8910     void getAnalysisUsage(AnalysisUsage &AU) const override {
8911       AU.setPreservesCFG();
8912       AU.addRequired<MachineDominatorTree>();
8913       MachineFunctionPass::getAnalysisUsage(AU);
8914     }
8915   };
8916 }
8917 
8918 char LDTLSCleanup::ID = 0;
8919 FunctionPass*
8920 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
8921