1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86InstrInfo.h" 15 #include "X86.h" 16 #include "X86InstrBuilder.h" 17 #include "X86MachineFunctionInfo.h" 18 #include "X86Subtarget.h" 19 #include "X86TargetMachine.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/CodeGen/LiveVariables.h" 22 #include "llvm/CodeGen/MachineConstantPool.h" 23 #include "llvm/CodeGen/MachineDominators.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/IR/DerivedTypes.h" 28 #include "llvm/IR/LLVMContext.h" 29 #include "llvm/MC/MCAsmInfo.h" 30 #include "llvm/MC/MCInst.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/raw_ostream.h" 35 #include "llvm/Target/TargetOptions.h" 36 #include <limits> 37 38 #define GET_INSTRINFO_CTOR 39 #include "X86GenInstrInfo.inc" 40 41 using namespace llvm; 42 43 static cl::opt<bool> 44 NoFusing("disable-spill-fusing", 45 cl::desc("Disable fusing of spill code into instructions")); 46 static cl::opt<bool> 47 PrintFailedFusing("print-failed-fuse-candidates", 48 cl::desc("Print instructions that the allocator wants to" 49 " fuse, but the X86 backend currently can't"), 50 cl::Hidden); 51 static cl::opt<bool> 52 ReMatPICStubLoad("remat-pic-stub-load", 53 cl::desc("Re-materialize load from stub in PIC mode"), 54 cl::init(false), cl::Hidden); 55 56 enum { 57 // Select which memory operand is being unfolded. 58 // (stored in bits 0 - 3) 59 TB_INDEX_0 = 0, 60 TB_INDEX_1 = 1, 61 TB_INDEX_2 = 2, 62 TB_INDEX_3 = 3, 63 TB_INDEX_MASK = 0xf, 64 65 // Do not insert the reverse map (MemOp -> RegOp) into the table. 66 // This may be needed because there is a many -> one mapping. 67 TB_NO_REVERSE = 1 << 4, 68 69 // Do not insert the forward map (RegOp -> MemOp) into the table. 70 // This is needed for Native Client, which prohibits branch 71 // instructions from using a memory operand. 72 TB_NO_FORWARD = 1 << 5, 73 74 TB_FOLDED_LOAD = 1 << 6, 75 TB_FOLDED_STORE = 1 << 7, 76 77 // Minimum alignment required for load/store. 78 // Used for RegOp->MemOp conversion. 79 // (stored in bits 8 - 15) 80 TB_ALIGN_SHIFT = 8, 81 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, 82 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT, 83 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, 84 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT 85 }; 86 87 struct X86OpTblEntry { 88 uint16_t RegOp; 89 uint16_t MemOp; 90 uint16_t Flags; 91 }; 92 93 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 94 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit() 95 ? X86::ADJCALLSTACKDOWN64 96 : X86::ADJCALLSTACKDOWN32), 97 (tm.getSubtarget<X86Subtarget>().is64Bit() 98 ? X86::ADJCALLSTACKUP64 99 : X86::ADJCALLSTACKUP32)), 100 TM(tm), RI(tm) { 101 102 static const X86OpTblEntry OpTbl2Addr[] = { 103 { X86::ADC32ri, X86::ADC32mi, 0 }, 104 { X86::ADC32ri8, X86::ADC32mi8, 0 }, 105 { X86::ADC32rr, X86::ADC32mr, 0 }, 106 { X86::ADC64ri32, X86::ADC64mi32, 0 }, 107 { X86::ADC64ri8, X86::ADC64mi8, 0 }, 108 { X86::ADC64rr, X86::ADC64mr, 0 }, 109 { X86::ADD16ri, X86::ADD16mi, 0 }, 110 { X86::ADD16ri8, X86::ADD16mi8, 0 }, 111 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE }, 112 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE }, 113 { X86::ADD16rr, X86::ADD16mr, 0 }, 114 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE }, 115 { X86::ADD32ri, X86::ADD32mi, 0 }, 116 { X86::ADD32ri8, X86::ADD32mi8, 0 }, 117 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE }, 118 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }, 119 { X86::ADD32rr, X86::ADD32mr, 0 }, 120 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE }, 121 { X86::ADD64ri32, X86::ADD64mi32, 0 }, 122 { X86::ADD64ri8, X86::ADD64mi8, 0 }, 123 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE }, 124 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE }, 125 { X86::ADD64rr, X86::ADD64mr, 0 }, 126 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE }, 127 { X86::ADD8ri, X86::ADD8mi, 0 }, 128 { X86::ADD8rr, X86::ADD8mr, 0 }, 129 { X86::AND16ri, X86::AND16mi, 0 }, 130 { X86::AND16ri8, X86::AND16mi8, 0 }, 131 { X86::AND16rr, X86::AND16mr, 0 }, 132 { X86::AND32ri, X86::AND32mi, 0 }, 133 { X86::AND32ri8, X86::AND32mi8, 0 }, 134 { X86::AND32rr, X86::AND32mr, 0 }, 135 { X86::AND64ri32, X86::AND64mi32, 0 }, 136 { X86::AND64ri8, X86::AND64mi8, 0 }, 137 { X86::AND64rr, X86::AND64mr, 0 }, 138 { X86::AND8ri, X86::AND8mi, 0 }, 139 { X86::AND8rr, X86::AND8mr, 0 }, 140 { X86::DEC16r, X86::DEC16m, 0 }, 141 { X86::DEC32r, X86::DEC32m, 0 }, 142 { X86::DEC64_16r, X86::DEC64_16m, 0 }, 143 { X86::DEC64_32r, X86::DEC64_32m, 0 }, 144 { X86::DEC64r, X86::DEC64m, 0 }, 145 { X86::DEC8r, X86::DEC8m, 0 }, 146 { X86::INC16r, X86::INC16m, 0 }, 147 { X86::INC32r, X86::INC32m, 0 }, 148 { X86::INC64_16r, X86::INC64_16m, 0 }, 149 { X86::INC64_32r, X86::INC64_32m, 0 }, 150 { X86::INC64r, X86::INC64m, 0 }, 151 { X86::INC8r, X86::INC8m, 0 }, 152 { X86::NEG16r, X86::NEG16m, 0 }, 153 { X86::NEG32r, X86::NEG32m, 0 }, 154 { X86::NEG64r, X86::NEG64m, 0 }, 155 { X86::NEG8r, X86::NEG8m, 0 }, 156 { X86::NOT16r, X86::NOT16m, 0 }, 157 { X86::NOT32r, X86::NOT32m, 0 }, 158 { X86::NOT64r, X86::NOT64m, 0 }, 159 { X86::NOT8r, X86::NOT8m, 0 }, 160 { X86::OR16ri, X86::OR16mi, 0 }, 161 { X86::OR16ri8, X86::OR16mi8, 0 }, 162 { X86::OR16rr, X86::OR16mr, 0 }, 163 { X86::OR32ri, X86::OR32mi, 0 }, 164 { X86::OR32ri8, X86::OR32mi8, 0 }, 165 { X86::OR32rr, X86::OR32mr, 0 }, 166 { X86::OR64ri32, X86::OR64mi32, 0 }, 167 { X86::OR64ri8, X86::OR64mi8, 0 }, 168 { X86::OR64rr, X86::OR64mr, 0 }, 169 { X86::OR8ri, X86::OR8mi, 0 }, 170 { X86::OR8rr, X86::OR8mr, 0 }, 171 { X86::ROL16r1, X86::ROL16m1, 0 }, 172 { X86::ROL16rCL, X86::ROL16mCL, 0 }, 173 { X86::ROL16ri, X86::ROL16mi, 0 }, 174 { X86::ROL32r1, X86::ROL32m1, 0 }, 175 { X86::ROL32rCL, X86::ROL32mCL, 0 }, 176 { X86::ROL32ri, X86::ROL32mi, 0 }, 177 { X86::ROL64r1, X86::ROL64m1, 0 }, 178 { X86::ROL64rCL, X86::ROL64mCL, 0 }, 179 { X86::ROL64ri, X86::ROL64mi, 0 }, 180 { X86::ROL8r1, X86::ROL8m1, 0 }, 181 { X86::ROL8rCL, X86::ROL8mCL, 0 }, 182 { X86::ROL8ri, X86::ROL8mi, 0 }, 183 { X86::ROR16r1, X86::ROR16m1, 0 }, 184 { X86::ROR16rCL, X86::ROR16mCL, 0 }, 185 { X86::ROR16ri, X86::ROR16mi, 0 }, 186 { X86::ROR32r1, X86::ROR32m1, 0 }, 187 { X86::ROR32rCL, X86::ROR32mCL, 0 }, 188 { X86::ROR32ri, X86::ROR32mi, 0 }, 189 { X86::ROR64r1, X86::ROR64m1, 0 }, 190 { X86::ROR64rCL, X86::ROR64mCL, 0 }, 191 { X86::ROR64ri, X86::ROR64mi, 0 }, 192 { X86::ROR8r1, X86::ROR8m1, 0 }, 193 { X86::ROR8rCL, X86::ROR8mCL, 0 }, 194 { X86::ROR8ri, X86::ROR8mi, 0 }, 195 { X86::SAR16r1, X86::SAR16m1, 0 }, 196 { X86::SAR16rCL, X86::SAR16mCL, 0 }, 197 { X86::SAR16ri, X86::SAR16mi, 0 }, 198 { X86::SAR32r1, X86::SAR32m1, 0 }, 199 { X86::SAR32rCL, X86::SAR32mCL, 0 }, 200 { X86::SAR32ri, X86::SAR32mi, 0 }, 201 { X86::SAR64r1, X86::SAR64m1, 0 }, 202 { X86::SAR64rCL, X86::SAR64mCL, 0 }, 203 { X86::SAR64ri, X86::SAR64mi, 0 }, 204 { X86::SAR8r1, X86::SAR8m1, 0 }, 205 { X86::SAR8rCL, X86::SAR8mCL, 0 }, 206 { X86::SAR8ri, X86::SAR8mi, 0 }, 207 { X86::SBB32ri, X86::SBB32mi, 0 }, 208 { X86::SBB32ri8, X86::SBB32mi8, 0 }, 209 { X86::SBB32rr, X86::SBB32mr, 0 }, 210 { X86::SBB64ri32, X86::SBB64mi32, 0 }, 211 { X86::SBB64ri8, X86::SBB64mi8, 0 }, 212 { X86::SBB64rr, X86::SBB64mr, 0 }, 213 { X86::SHL16rCL, X86::SHL16mCL, 0 }, 214 { X86::SHL16ri, X86::SHL16mi, 0 }, 215 { X86::SHL32rCL, X86::SHL32mCL, 0 }, 216 { X86::SHL32ri, X86::SHL32mi, 0 }, 217 { X86::SHL64rCL, X86::SHL64mCL, 0 }, 218 { X86::SHL64ri, X86::SHL64mi, 0 }, 219 { X86::SHL8rCL, X86::SHL8mCL, 0 }, 220 { X86::SHL8ri, X86::SHL8mi, 0 }, 221 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 }, 222 { X86::SHLD16rri8, X86::SHLD16mri8, 0 }, 223 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 }, 224 { X86::SHLD32rri8, X86::SHLD32mri8, 0 }, 225 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 }, 226 { X86::SHLD64rri8, X86::SHLD64mri8, 0 }, 227 { X86::SHR16r1, X86::SHR16m1, 0 }, 228 { X86::SHR16rCL, X86::SHR16mCL, 0 }, 229 { X86::SHR16ri, X86::SHR16mi, 0 }, 230 { X86::SHR32r1, X86::SHR32m1, 0 }, 231 { X86::SHR32rCL, X86::SHR32mCL, 0 }, 232 { X86::SHR32ri, X86::SHR32mi, 0 }, 233 { X86::SHR64r1, X86::SHR64m1, 0 }, 234 { X86::SHR64rCL, X86::SHR64mCL, 0 }, 235 { X86::SHR64ri, X86::SHR64mi, 0 }, 236 { X86::SHR8r1, X86::SHR8m1, 0 }, 237 { X86::SHR8rCL, X86::SHR8mCL, 0 }, 238 { X86::SHR8ri, X86::SHR8mi, 0 }, 239 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 }, 240 { X86::SHRD16rri8, X86::SHRD16mri8, 0 }, 241 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 }, 242 { X86::SHRD32rri8, X86::SHRD32mri8, 0 }, 243 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 }, 244 { X86::SHRD64rri8, X86::SHRD64mri8, 0 }, 245 { X86::SUB16ri, X86::SUB16mi, 0 }, 246 { X86::SUB16ri8, X86::SUB16mi8, 0 }, 247 { X86::SUB16rr, X86::SUB16mr, 0 }, 248 { X86::SUB32ri, X86::SUB32mi, 0 }, 249 { X86::SUB32ri8, X86::SUB32mi8, 0 }, 250 { X86::SUB32rr, X86::SUB32mr, 0 }, 251 { X86::SUB64ri32, X86::SUB64mi32, 0 }, 252 { X86::SUB64ri8, X86::SUB64mi8, 0 }, 253 { X86::SUB64rr, X86::SUB64mr, 0 }, 254 { X86::SUB8ri, X86::SUB8mi, 0 }, 255 { X86::SUB8rr, X86::SUB8mr, 0 }, 256 { X86::XOR16ri, X86::XOR16mi, 0 }, 257 { X86::XOR16ri8, X86::XOR16mi8, 0 }, 258 { X86::XOR16rr, X86::XOR16mr, 0 }, 259 { X86::XOR32ri, X86::XOR32mi, 0 }, 260 { X86::XOR32ri8, X86::XOR32mi8, 0 }, 261 { X86::XOR32rr, X86::XOR32mr, 0 }, 262 { X86::XOR64ri32, X86::XOR64mi32, 0 }, 263 { X86::XOR64ri8, X86::XOR64mi8, 0 }, 264 { X86::XOR64rr, X86::XOR64mr, 0 }, 265 { X86::XOR8ri, X86::XOR8mi, 0 }, 266 { X86::XOR8rr, X86::XOR8mr, 0 } 267 }; 268 269 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 270 unsigned RegOp = OpTbl2Addr[i].RegOp; 271 unsigned MemOp = OpTbl2Addr[i].MemOp; 272 unsigned Flags = OpTbl2Addr[i].Flags; 273 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable, 274 RegOp, MemOp, 275 // Index 0, folded load and store, no alignment requirement. 276 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE); 277 } 278 279 static const X86OpTblEntry OpTbl0[] = { 280 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD }, 281 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD }, 282 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD }, 283 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD }, 284 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD }, 285 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD }, 286 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD }, 287 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD }, 288 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD }, 289 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD }, 290 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD }, 291 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD }, 292 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD }, 293 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD }, 294 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD }, 295 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD }, 296 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD }, 297 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD }, 298 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD }, 299 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD }, 300 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE }, 301 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 302 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 303 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD }, 304 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD }, 305 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD }, 306 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD }, 307 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD }, 308 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD }, 309 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD }, 310 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD }, 311 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD }, 312 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD }, 313 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE }, 314 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE }, 315 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE }, 316 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE }, 317 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE }, 318 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE }, 319 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE }, 320 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE }, 321 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE }, 322 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 323 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 324 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 325 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE }, 326 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE }, 327 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE }, 328 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE }, 329 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE }, 330 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE }, 331 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD }, 332 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD }, 333 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD }, 334 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD }, 335 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE }, 336 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE }, 337 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE }, 338 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE }, 339 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE }, 340 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE }, 341 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE }, 342 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE }, 343 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE }, 344 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE }, 345 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE }, 346 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE }, 347 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE }, 348 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE }, 349 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE }, 350 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE }, 351 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD }, 352 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD }, 353 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD }, 354 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD }, 355 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD }, 356 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }, 357 // AVX 128-bit versions of foldable instructions 358 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE }, 359 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 360 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 361 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 362 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 363 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 364 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 365 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE }, 366 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE }, 367 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE }, 368 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE }, 369 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE }, 370 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE }, 371 // AVX 256-bit foldable instructions 372 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 373 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 374 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 375 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 376 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE }, 377 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE } 378 }; 379 380 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 381 unsigned RegOp = OpTbl0[i].RegOp; 382 unsigned MemOp = OpTbl0[i].MemOp; 383 unsigned Flags = OpTbl0[i].Flags; 384 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable, 385 RegOp, MemOp, TB_INDEX_0 | Flags); 386 } 387 388 static const X86OpTblEntry OpTbl1[] = { 389 { X86::CMP16rr, X86::CMP16rm, 0 }, 390 { X86::CMP32rr, X86::CMP32rm, 0 }, 391 { X86::CMP64rr, X86::CMP64rm, 0 }, 392 { X86::CMP8rr, X86::CMP8rm, 0 }, 393 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 394 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 395 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 396 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 397 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 398 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 399 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 400 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 401 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 402 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 403 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE }, 404 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE }, 405 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 406 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 407 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 408 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 409 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 410 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 411 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 412 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 413 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 }, 414 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 }, 415 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 }, 416 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 }, 417 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 }, 418 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 }, 419 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 420 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 421 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 422 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 423 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 424 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 425 { X86::MOV16rr, X86::MOV16rm, 0 }, 426 { X86::MOV32rr, X86::MOV32rm, 0 }, 427 { X86::MOV64rr, X86::MOV64rm, 0 }, 428 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 429 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 430 { X86::MOV8rr, X86::MOV8rm, 0 }, 431 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 }, 432 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 }, 433 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 434 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 435 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 436 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 }, 437 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 }, 438 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 }, 439 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 440 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 441 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 442 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 443 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 444 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 445 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 }, 446 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 447 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 448 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 449 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 }, 450 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 451 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 452 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 453 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 454 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 }, 455 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 }, 456 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 }, 457 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 }, 458 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 }, 459 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 }, 460 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 }, 461 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 }, 462 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 }, 463 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 }, 464 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 465 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 466 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 }, 467 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 }, 468 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 469 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 470 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 471 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 472 { X86::TEST16rr, X86::TEST16rm, 0 }, 473 { X86::TEST32rr, X86::TEST32rm, 0 }, 474 { X86::TEST64rr, X86::TEST64rm, 0 }, 475 { X86::TEST8rr, X86::TEST8rm, 0 }, 476 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 477 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 478 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, 479 // AVX 128-bit versions of foldable instructions 480 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 }, 481 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 }, 482 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 }, 483 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 }, 484 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 }, 485 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 }, 486 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 }, 487 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 }, 488 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 }, 489 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 }, 490 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 }, 491 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 }, 492 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 }, 493 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 }, 494 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 }, 495 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 }, 496 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE }, 497 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE }, 498 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 }, 499 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 }, 500 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 }, 501 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 }, 502 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 }, 503 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 }, 504 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 }, 505 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 }, 506 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 }, 507 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 }, 508 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 }, 509 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 }, 510 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 }, 511 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 }, 512 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 }, 513 { X86::VPABSBrr128, X86::VPABSBrm128, 0 }, 514 { X86::VPABSDrr128, X86::VPABSDrm128, 0 }, 515 { X86::VPABSWrr128, X86::VPABSWrm128, 0 }, 516 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 }, 517 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 }, 518 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 }, 519 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 }, 520 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 }, 521 { X86::VRCPPSr, X86::VRCPPSm, 0 }, 522 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, 0 }, 523 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 }, 524 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, 0 }, 525 { X86::VSQRTPDr, X86::VSQRTPDm, 0 }, 526 { X86::VSQRTPSr, X86::VSQRTPSm, 0 }, 527 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 }, 528 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }, 529 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE }, 530 531 // AVX 256-bit foldable instructions 532 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 }, 533 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 }, 534 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 }, 535 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 }, 536 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }, 537 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 }, 538 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 }, 539 540 // AVX2 foldable instructions 541 { X86::VPABSBrr256, X86::VPABSBrm256, 0 }, 542 { X86::VPABSDrr256, X86::VPABSDrm256, 0 }, 543 { X86::VPABSWrr256, X86::VPABSWrm256, 0 }, 544 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 }, 545 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 }, 546 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 }, 547 { X86::VRCPPSYr, X86::VRCPPSYm, 0 }, 548 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, 0 }, 549 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 }, 550 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 }, 551 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 }, 552 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE }, 553 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE }, 554 555 // BMI/BMI2/LZCNT/POPCNT foldable instructions 556 { X86::BEXTR32rr, X86::BEXTR32rm, 0 }, 557 { X86::BEXTR64rr, X86::BEXTR64rm, 0 }, 558 { X86::BLSI32rr, X86::BLSI32rm, 0 }, 559 { X86::BLSI64rr, X86::BLSI64rm, 0 }, 560 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 }, 561 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 }, 562 { X86::BLSR32rr, X86::BLSR32rm, 0 }, 563 { X86::BLSR64rr, X86::BLSR64rm, 0 }, 564 { X86::BZHI32rr, X86::BZHI32rm, 0 }, 565 { X86::BZHI64rr, X86::BZHI64rm, 0 }, 566 { X86::LZCNT16rr, X86::LZCNT16rm, 0 }, 567 { X86::LZCNT32rr, X86::LZCNT32rm, 0 }, 568 { X86::LZCNT64rr, X86::LZCNT64rm, 0 }, 569 { X86::POPCNT16rr, X86::POPCNT16rm, 0 }, 570 { X86::POPCNT32rr, X86::POPCNT32rm, 0 }, 571 { X86::POPCNT64rr, X86::POPCNT64rm, 0 }, 572 { X86::RORX32ri, X86::RORX32mi, 0 }, 573 { X86::RORX64ri, X86::RORX64mi, 0 }, 574 { X86::SARX32rr, X86::SARX32rm, 0 }, 575 { X86::SARX64rr, X86::SARX64rm, 0 }, 576 { X86::SHRX32rr, X86::SHRX32rm, 0 }, 577 { X86::SHRX64rr, X86::SHRX64rm, 0 }, 578 { X86::SHLX32rr, X86::SHLX32rm, 0 }, 579 { X86::SHLX64rr, X86::SHLX64rm, 0 }, 580 { X86::TZCNT16rr, X86::TZCNT16rm, 0 }, 581 { X86::TZCNT32rr, X86::TZCNT32rm, 0 }, 582 { X86::TZCNT64rr, X86::TZCNT64rm, 0 }, 583 }; 584 585 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 586 unsigned RegOp = OpTbl1[i].RegOp; 587 unsigned MemOp = OpTbl1[i].MemOp; 588 unsigned Flags = OpTbl1[i].Flags; 589 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable, 590 RegOp, MemOp, 591 // Index 1, folded load 592 Flags | TB_INDEX_1 | TB_FOLDED_LOAD); 593 } 594 595 static const X86OpTblEntry OpTbl2[] = { 596 { X86::ADC32rr, X86::ADC32rm, 0 }, 597 { X86::ADC64rr, X86::ADC64rm, 0 }, 598 { X86::ADD16rr, X86::ADD16rm, 0 }, 599 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE }, 600 { X86::ADD32rr, X86::ADD32rm, 0 }, 601 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE }, 602 { X86::ADD64rr, X86::ADD64rm, 0 }, 603 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE }, 604 { X86::ADD8rr, X86::ADD8rm, 0 }, 605 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 }, 606 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 }, 607 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 608 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 609 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 }, 610 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 }, 611 { X86::AND16rr, X86::AND16rm, 0 }, 612 { X86::AND32rr, X86::AND32rm, 0 }, 613 { X86::AND64rr, X86::AND64rm, 0 }, 614 { X86::AND8rr, X86::AND8rm, 0 }, 615 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 }, 616 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 }, 617 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 }, 618 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 }, 619 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 }, 620 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 }, 621 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 }, 622 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 }, 623 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 624 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 625 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 626 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 627 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 628 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 629 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 630 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 631 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 632 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 633 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 634 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 635 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 636 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 637 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 638 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 639 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 640 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 641 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 642 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 643 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 644 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 645 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 646 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 647 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 648 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 649 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 650 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 651 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 652 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 653 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 654 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 655 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 656 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 657 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 658 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 659 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 660 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 661 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 662 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 663 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 664 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 665 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 666 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 667 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 668 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 669 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 670 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 671 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 }, 672 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 }, 673 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 674 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 675 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 }, 676 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 }, 677 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 678 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 679 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 }, 680 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 }, 681 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 }, 682 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 }, 683 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 }, 684 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 }, 685 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 }, 686 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 }, 687 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 }, 688 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 }, 689 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 }, 690 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 }, 691 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 692 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 693 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 694 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 695 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 696 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 697 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 698 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 699 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 700 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 701 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 702 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 }, 703 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 }, 704 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 705 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 706 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 }, 707 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 }, 708 { X86::MINSDrr, X86::MINSDrm, 0 }, 709 { X86::MINSSrr, X86::MINSSrm, 0 }, 710 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 }, 711 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 }, 712 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 }, 713 { X86::MULSDrr, X86::MULSDrm, 0 }, 714 { X86::MULSSrr, X86::MULSSrm, 0 }, 715 { X86::OR16rr, X86::OR16rm, 0 }, 716 { X86::OR32rr, X86::OR32rm, 0 }, 717 { X86::OR64rr, X86::OR64rm, 0 }, 718 { X86::OR8rr, X86::OR8rm, 0 }, 719 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 }, 720 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 }, 721 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 }, 722 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 }, 723 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 }, 724 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 }, 725 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 }, 726 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 }, 727 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 }, 728 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 }, 729 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 }, 730 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 }, 731 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 }, 732 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 }, 733 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 }, 734 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 }, 735 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 }, 736 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 }, 737 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 }, 738 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 }, 739 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 }, 740 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 }, 741 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 }, 742 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 }, 743 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 }, 744 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 }, 745 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 }, 746 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 }, 747 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 }, 748 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 }, 749 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 }, 750 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 }, 751 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 }, 752 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 }, 753 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 }, 754 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 }, 755 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 }, 756 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 }, 757 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 }, 758 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 }, 759 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 }, 760 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 }, 761 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 }, 762 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 }, 763 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 }, 764 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 }, 765 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 }, 766 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 }, 767 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 }, 768 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 }, 769 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 }, 770 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 }, 771 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 }, 772 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 }, 773 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 }, 774 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 }, 775 { X86::PORrr, X86::PORrm, TB_ALIGN_16 }, 776 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 }, 777 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 }, 778 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 }, 779 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 }, 780 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 }, 781 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 }, 782 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 }, 783 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 }, 784 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 }, 785 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 }, 786 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 }, 787 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 }, 788 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 }, 789 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 }, 790 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 }, 791 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 }, 792 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 }, 793 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 }, 794 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 }, 795 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 }, 796 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 }, 797 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 }, 798 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 }, 799 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 }, 800 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 }, 801 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 }, 802 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 }, 803 { X86::SBB32rr, X86::SBB32rm, 0 }, 804 { X86::SBB64rr, X86::SBB64rm, 0 }, 805 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 }, 806 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 }, 807 { X86::SUB16rr, X86::SUB16rm, 0 }, 808 { X86::SUB32rr, X86::SUB32rm, 0 }, 809 { X86::SUB64rr, X86::SUB64rm, 0 }, 810 { X86::SUB8rr, X86::SUB8rm, 0 }, 811 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 }, 812 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 }, 813 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 814 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 815 // FIXME: TEST*rr -> swapped operand of TEST*mr. 816 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 }, 817 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 }, 818 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 }, 819 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 }, 820 { X86::XOR16rr, X86::XOR16rm, 0 }, 821 { X86::XOR32rr, X86::XOR32rm, 0 }, 822 { X86::XOR64rr, X86::XOR64rm, 0 }, 823 { X86::XOR8rr, X86::XOR8rm, 0 }, 824 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 }, 825 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 }, 826 // AVX 128-bit versions of foldable instructions 827 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 }, 828 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 }, 829 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 }, 830 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 }, 831 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 }, 832 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 }, 833 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 }, 834 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 }, 835 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 }, 836 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 }, 837 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 }, 838 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 }, 839 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 }, 840 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 }, 841 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 }, 842 { X86::VSQRTSDr, X86::VSQRTSDm, 0 }, 843 { X86::VSQRTSSr, X86::VSQRTSSm, 0 }, 844 { X86::VADDPDrr, X86::VADDPDrm, 0 }, 845 { X86::VADDPSrr, X86::VADDPSrm, 0 }, 846 { X86::VADDSDrr, X86::VADDSDrm, 0 }, 847 { X86::VADDSSrr, X86::VADDSSrm, 0 }, 848 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 }, 849 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 }, 850 { X86::VANDNPDrr, X86::VANDNPDrm, 0 }, 851 { X86::VANDNPSrr, X86::VANDNPSrm, 0 }, 852 { X86::VANDPDrr, X86::VANDPDrm, 0 }, 853 { X86::VANDPSrr, X86::VANDPSrm, 0 }, 854 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 }, 855 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 }, 856 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 }, 857 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 }, 858 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 }, 859 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 }, 860 { X86::VCMPSDrr, X86::VCMPSDrm, 0 }, 861 { X86::VCMPSSrr, X86::VCMPSSrm, 0 }, 862 { X86::VDIVPDrr, X86::VDIVPDrm, 0 }, 863 { X86::VDIVPSrr, X86::VDIVPSrm, 0 }, 864 { X86::VDIVSDrr, X86::VDIVSDrm, 0 }, 865 { X86::VDIVSSrr, X86::VDIVSSrm, 0 }, 866 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 }, 867 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 }, 868 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 }, 869 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 }, 870 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 }, 871 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 }, 872 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 }, 873 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 }, 874 { X86::VHADDPDrr, X86::VHADDPDrm, 0 }, 875 { X86::VHADDPSrr, X86::VHADDPSrm, 0 }, 876 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 }, 877 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 }, 878 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 }, 879 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 }, 880 { X86::VMAXPDrr, X86::VMAXPDrm, 0 }, 881 { X86::VMAXPSrr, X86::VMAXPSrm, 0 }, 882 { X86::VMAXSDrr, X86::VMAXSDrm, 0 }, 883 { X86::VMAXSSrr, X86::VMAXSSrm, 0 }, 884 { X86::VMINPDrr, X86::VMINPDrm, 0 }, 885 { X86::VMINPSrr, X86::VMINPSrm, 0 }, 886 { X86::VMINSDrr, X86::VMINSDrm, 0 }, 887 { X86::VMINSSrr, X86::VMINSSrm, 0 }, 888 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 }, 889 { X86::VMULPDrr, X86::VMULPDrm, 0 }, 890 { X86::VMULPSrr, X86::VMULPSrm, 0 }, 891 { X86::VMULSDrr, X86::VMULSDrm, 0 }, 892 { X86::VMULSSrr, X86::VMULSSrm, 0 }, 893 { X86::VORPDrr, X86::VORPDrm, 0 }, 894 { X86::VORPSrr, X86::VORPSrm, 0 }, 895 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 }, 896 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 }, 897 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 }, 898 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 }, 899 { X86::VPADDBrr, X86::VPADDBrm, 0 }, 900 { X86::VPADDDrr, X86::VPADDDrm, 0 }, 901 { X86::VPADDQrr, X86::VPADDQrm, 0 }, 902 { X86::VPADDSBrr, X86::VPADDSBrm, 0 }, 903 { X86::VPADDSWrr, X86::VPADDSWrm, 0 }, 904 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 }, 905 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 }, 906 { X86::VPADDWrr, X86::VPADDWrm, 0 }, 907 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 }, 908 { X86::VPANDNrr, X86::VPANDNrm, 0 }, 909 { X86::VPANDrr, X86::VPANDrm, 0 }, 910 { X86::VPAVGBrr, X86::VPAVGBrm, 0 }, 911 { X86::VPAVGWrr, X86::VPAVGWrm, 0 }, 912 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 }, 913 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 }, 914 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 }, 915 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 }, 916 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 }, 917 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 }, 918 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 }, 919 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 }, 920 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 }, 921 { X86::VPHADDDrr, X86::VPHADDDrm, 0 }, 922 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 }, 923 { X86::VPHADDWrr, X86::VPHADDWrm, 0 }, 924 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 }, 925 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 }, 926 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 }, 927 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 }, 928 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 }, 929 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 }, 930 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 }, 931 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 }, 932 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 }, 933 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 }, 934 { X86::VPMINSWrr, X86::VPMINSWrm, 0 }, 935 { X86::VPMINUBrr, X86::VPMINUBrm, 0 }, 936 { X86::VPMINSBrr, X86::VPMINSBrm, 0 }, 937 { X86::VPMINSDrr, X86::VPMINSDrm, 0 }, 938 { X86::VPMINUDrr, X86::VPMINUDrm, 0 }, 939 { X86::VPMINUWrr, X86::VPMINUWrm, 0 }, 940 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 }, 941 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 }, 942 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 }, 943 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 }, 944 { X86::VPMULDQrr, X86::VPMULDQrm, 0 }, 945 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 }, 946 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 }, 947 { X86::VPMULHWrr, X86::VPMULHWrm, 0 }, 948 { X86::VPMULLDrr, X86::VPMULLDrm, 0 }, 949 { X86::VPMULLWrr, X86::VPMULLWrm, 0 }, 950 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 }, 951 { X86::VPORrr, X86::VPORrm, 0 }, 952 { X86::VPSADBWrr, X86::VPSADBWrm, 0 }, 953 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 }, 954 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 }, 955 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 }, 956 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 }, 957 { X86::VPSLLDrr, X86::VPSLLDrm, 0 }, 958 { X86::VPSLLQrr, X86::VPSLLQrm, 0 }, 959 { X86::VPSLLWrr, X86::VPSLLWrm, 0 }, 960 { X86::VPSRADrr, X86::VPSRADrm, 0 }, 961 { X86::VPSRAWrr, X86::VPSRAWrm, 0 }, 962 { X86::VPSRLDrr, X86::VPSRLDrm, 0 }, 963 { X86::VPSRLQrr, X86::VPSRLQrm, 0 }, 964 { X86::VPSRLWrr, X86::VPSRLWrm, 0 }, 965 { X86::VPSUBBrr, X86::VPSUBBrm, 0 }, 966 { X86::VPSUBDrr, X86::VPSUBDrm, 0 }, 967 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 }, 968 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 }, 969 { X86::VPSUBWrr, X86::VPSUBWrm, 0 }, 970 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 }, 971 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 }, 972 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 }, 973 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 }, 974 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 }, 975 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 }, 976 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 }, 977 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 }, 978 { X86::VPXORrr, X86::VPXORrm, 0 }, 979 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 }, 980 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 }, 981 { X86::VSUBPDrr, X86::VSUBPDrm, 0 }, 982 { X86::VSUBPSrr, X86::VSUBPSrm, 0 }, 983 { X86::VSUBSDrr, X86::VSUBSDrm, 0 }, 984 { X86::VSUBSSrr, X86::VSUBSSrm, 0 }, 985 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 }, 986 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 }, 987 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 }, 988 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 }, 989 { X86::VXORPDrr, X86::VXORPDrm, 0 }, 990 { X86::VXORPSrr, X86::VXORPSrm, 0 }, 991 // AVX 256-bit foldable instructions 992 { X86::VADDPDYrr, X86::VADDPDYrm, 0 }, 993 { X86::VADDPSYrr, X86::VADDPSYrm, 0 }, 994 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 }, 995 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 }, 996 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 }, 997 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 }, 998 { X86::VANDPDYrr, X86::VANDPDYrm, 0 }, 999 { X86::VANDPSYrr, X86::VANDPSYrm, 0 }, 1000 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 }, 1001 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 }, 1002 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 }, 1003 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 }, 1004 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 }, 1005 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 }, 1006 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 }, 1007 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 }, 1008 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 }, 1009 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 }, 1010 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 }, 1011 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 }, 1012 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 }, 1013 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 }, 1014 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 }, 1015 { X86::VMINPDYrr, X86::VMINPDYrm, 0 }, 1016 { X86::VMINPSYrr, X86::VMINPSYrm, 0 }, 1017 { X86::VMULPDYrr, X86::VMULPDYrm, 0 }, 1018 { X86::VMULPSYrr, X86::VMULPSYrm, 0 }, 1019 { X86::VORPDYrr, X86::VORPDYrm, 0 }, 1020 { X86::VORPSYrr, X86::VORPSYrm, 0 }, 1021 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 }, 1022 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 }, 1023 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 }, 1024 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 }, 1025 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 }, 1026 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 }, 1027 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 }, 1028 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 }, 1029 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 }, 1030 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 }, 1031 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 }, 1032 { X86::VXORPDYrr, X86::VXORPDYrm, 0 }, 1033 { X86::VXORPSYrr, X86::VXORPSYrm, 0 }, 1034 // AVX2 foldable instructions 1035 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 }, 1036 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 }, 1037 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 }, 1038 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 }, 1039 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 }, 1040 { X86::VPADDBYrr, X86::VPADDBYrm, 0 }, 1041 { X86::VPADDDYrr, X86::VPADDDYrm, 0 }, 1042 { X86::VPADDQYrr, X86::VPADDQYrm, 0 }, 1043 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 }, 1044 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 }, 1045 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 }, 1046 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 }, 1047 { X86::VPADDWYrr, X86::VPADDWYrm, 0 }, 1048 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 }, 1049 { X86::VPANDNYrr, X86::VPANDNYrm, 0 }, 1050 { X86::VPANDYrr, X86::VPANDYrm, 0 }, 1051 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 }, 1052 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 }, 1053 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 }, 1054 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 }, 1055 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 }, 1056 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 }, 1057 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 }, 1058 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 }, 1059 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 }, 1060 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 }, 1061 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 }, 1062 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 }, 1063 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 }, 1064 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 }, 1065 { X86::VPERMDYrr, X86::VPERMDYrm, 0 }, 1066 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 }, 1067 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 }, 1068 { X86::VPERMQYri, X86::VPERMQYmi, 0 }, 1069 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 }, 1070 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 }, 1071 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 }, 1072 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 }, 1073 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 }, 1074 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 }, 1075 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 }, 1076 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 }, 1077 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 }, 1078 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 }, 1079 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 }, 1080 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 }, 1081 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 }, 1082 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 }, 1083 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 }, 1084 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 }, 1085 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 }, 1086 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 }, 1087 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 }, 1088 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 }, 1089 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 }, 1090 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 }, 1091 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 }, 1092 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 }, 1093 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 }, 1094 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 }, 1095 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 }, 1096 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 }, 1097 { X86::VPORYrr, X86::VPORYrm, 0 }, 1098 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 }, 1099 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 }, 1100 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 }, 1101 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 }, 1102 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 }, 1103 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 }, 1104 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 }, 1105 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 }, 1106 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 }, 1107 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 }, 1108 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 }, 1109 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 }, 1110 { X86::VPSRADYrr, X86::VPSRADYrm, 0 }, 1111 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 }, 1112 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 }, 1113 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 }, 1114 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 }, 1115 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 }, 1116 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 }, 1117 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 }, 1118 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 }, 1119 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 }, 1120 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 }, 1121 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 }, 1122 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 }, 1123 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 }, 1124 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 }, 1125 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 }, 1126 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 }, 1127 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 }, 1128 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 }, 1129 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 }, 1130 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 }, 1131 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 }, 1132 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 }, 1133 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 }, 1134 { X86::VPXORYrr, X86::VPXORYrm, 0 }, 1135 // FIXME: add AVX 256-bit foldable instructions 1136 1137 // FMA4 foldable patterns 1138 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, 0 }, 1139 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, 0 }, 1140 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 }, 1141 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 }, 1142 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 }, 1143 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 }, 1144 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, 0 }, 1145 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, 0 }, 1146 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 }, 1147 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 }, 1148 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 }, 1149 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 }, 1150 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, 0 }, 1151 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, 0 }, 1152 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 }, 1153 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 }, 1154 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 }, 1155 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 }, 1156 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, 0 }, 1157 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, 0 }, 1158 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 }, 1159 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 }, 1160 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 }, 1161 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 }, 1162 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 }, 1163 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 }, 1164 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 }, 1165 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 }, 1166 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 }, 1167 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 }, 1168 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 }, 1169 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 }, 1170 1171 // BMI/BMI2 foldable instructions 1172 { X86::ANDN32rr, X86::ANDN32rm, 0 }, 1173 { X86::ANDN64rr, X86::ANDN64rm, 0 }, 1174 { X86::MULX32rr, X86::MULX32rm, 0 }, 1175 { X86::MULX64rr, X86::MULX64rm, 0 }, 1176 { X86::PDEP32rr, X86::PDEP32rm, 0 }, 1177 { X86::PDEP64rr, X86::PDEP64rm, 0 }, 1178 { X86::PEXT32rr, X86::PEXT32rm, 0 }, 1179 { X86::PEXT64rr, X86::PEXT64rm, 0 }, 1180 }; 1181 1182 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 1183 unsigned RegOp = OpTbl2[i].RegOp; 1184 unsigned MemOp = OpTbl2[i].MemOp; 1185 unsigned Flags = OpTbl2[i].Flags; 1186 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable, 1187 RegOp, MemOp, 1188 // Index 2, folded load 1189 Flags | TB_INDEX_2 | TB_FOLDED_LOAD); 1190 } 1191 1192 static const X86OpTblEntry OpTbl3[] = { 1193 // FMA foldable instructions 1194 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, 0 }, 1195 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, 0 }, 1196 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, 0 }, 1197 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, 0 }, 1198 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, 0 }, 1199 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, 0 }, 1200 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, 0 }, 1201 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, 0 }, 1202 1203 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_16 }, 1204 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_16 }, 1205 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_16 }, 1206 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_16 }, 1207 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_16 }, 1208 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_16 }, 1209 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_32 }, 1210 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_32 }, 1211 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_32 }, 1212 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_32 }, 1213 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_32 }, 1214 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_32 }, 1215 1216 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, 0 }, 1217 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, 0 }, 1218 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, 0 }, 1219 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, 0 }, 1220 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, 0 }, 1221 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, 0 }, 1222 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, 0 }, 1223 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, 0 }, 1224 1225 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_16 }, 1226 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_16 }, 1227 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_16 }, 1228 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_16 }, 1229 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_16 }, 1230 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_16 }, 1231 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_32 }, 1232 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_32 }, 1233 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_32 }, 1234 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_32 }, 1235 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_32 }, 1236 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_32 }, 1237 1238 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, 0 }, 1239 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, 0 }, 1240 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, 0 }, 1241 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, 0 }, 1242 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, 0 }, 1243 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, 0 }, 1244 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, 0 }, 1245 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, 0 }, 1246 1247 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_16 }, 1248 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_16 }, 1249 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_16 }, 1250 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_16 }, 1251 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_16 }, 1252 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_16 }, 1253 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_32 }, 1254 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_32 }, 1255 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_32 }, 1256 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_32 }, 1257 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_32 }, 1258 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_32 }, 1259 1260 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, 0 }, 1261 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, 0 }, 1262 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, 0 }, 1263 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, 0 }, 1264 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, 0 }, 1265 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, 0 }, 1266 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, 0 }, 1267 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, 0 }, 1268 1269 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_16 }, 1270 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_16 }, 1271 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_16 }, 1272 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_16 }, 1273 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_16 }, 1274 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_16 }, 1275 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_32 }, 1276 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_32 }, 1277 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_32 }, 1278 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_32 }, 1279 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_32 }, 1280 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_32 }, 1281 1282 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_16 }, 1283 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_16 }, 1284 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_16 }, 1285 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_16 }, 1286 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_16 }, 1287 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_16 }, 1288 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_32 }, 1289 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_32 }, 1290 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_32 }, 1291 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_32 }, 1292 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_32 }, 1293 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_32 }, 1294 1295 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_16 }, 1296 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_16 }, 1297 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_16 }, 1298 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_16 }, 1299 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_16 }, 1300 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_16 }, 1301 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_32 }, 1302 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_32 }, 1303 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_32 }, 1304 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_32 }, 1305 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_32 }, 1306 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_32 }, 1307 1308 // FMA4 foldable patterns 1309 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, 0 }, 1310 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, 0 }, 1311 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 }, 1312 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 }, 1313 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 }, 1314 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 }, 1315 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, 0 }, 1316 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, 0 }, 1317 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 }, 1318 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 }, 1319 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 }, 1320 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 }, 1321 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, 0 }, 1322 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, 0 }, 1323 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 }, 1324 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 }, 1325 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 }, 1326 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 }, 1327 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, 0 }, 1328 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, 0 }, 1329 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 }, 1330 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 }, 1331 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 }, 1332 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 }, 1333 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 }, 1334 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 }, 1335 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 }, 1336 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 }, 1337 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 }, 1338 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 }, 1339 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 }, 1340 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 }, 1341 }; 1342 1343 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) { 1344 unsigned RegOp = OpTbl3[i].RegOp; 1345 unsigned MemOp = OpTbl3[i].MemOp; 1346 unsigned Flags = OpTbl3[i].Flags; 1347 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable, 1348 RegOp, MemOp, 1349 // Index 3, folded load 1350 Flags | TB_INDEX_3 | TB_FOLDED_LOAD); 1351 } 1352 1353 } 1354 1355 void 1356 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable, 1357 MemOp2RegOpTableType &M2RTable, 1358 unsigned RegOp, unsigned MemOp, unsigned Flags) { 1359 if ((Flags & TB_NO_FORWARD) == 0) { 1360 assert(!R2MTable.count(RegOp) && "Duplicate entry!"); 1361 R2MTable[RegOp] = std::make_pair(MemOp, Flags); 1362 } 1363 if ((Flags & TB_NO_REVERSE) == 0) { 1364 assert(!M2RTable.count(MemOp) && 1365 "Duplicated entries in unfolding maps?"); 1366 M2RTable[MemOp] = std::make_pair(RegOp, Flags); 1367 } 1368 } 1369 1370 bool 1371 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 1372 unsigned &SrcReg, unsigned &DstReg, 1373 unsigned &SubIdx) const { 1374 switch (MI.getOpcode()) { 1375 default: break; 1376 case X86::MOVSX16rr8: 1377 case X86::MOVZX16rr8: 1378 case X86::MOVSX32rr8: 1379 case X86::MOVZX32rr8: 1380 case X86::MOVSX64rr8: 1381 if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 1382 // It's not always legal to reference the low 8-bit of the larger 1383 // register in 32-bit mode. 1384 return false; 1385 case X86::MOVSX32rr16: 1386 case X86::MOVZX32rr16: 1387 case X86::MOVSX64rr16: 1388 case X86::MOVSX64rr32: { 1389 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 1390 // Be conservative. 1391 return false; 1392 SrcReg = MI.getOperand(1).getReg(); 1393 DstReg = MI.getOperand(0).getReg(); 1394 switch (MI.getOpcode()) { 1395 default: llvm_unreachable("Unreachable!"); 1396 case X86::MOVSX16rr8: 1397 case X86::MOVZX16rr8: 1398 case X86::MOVSX32rr8: 1399 case X86::MOVZX32rr8: 1400 case X86::MOVSX64rr8: 1401 SubIdx = X86::sub_8bit; 1402 break; 1403 case X86::MOVSX32rr16: 1404 case X86::MOVZX32rr16: 1405 case X86::MOVSX64rr16: 1406 SubIdx = X86::sub_16bit; 1407 break; 1408 case X86::MOVSX64rr32: 1409 SubIdx = X86::sub_32bit; 1410 break; 1411 } 1412 return true; 1413 } 1414 } 1415 return false; 1416 } 1417 1418 /// isFrameOperand - Return true and the FrameIndex if the specified 1419 /// operand and follow operands form a reference to the stack frame. 1420 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 1421 int &FrameIndex) const { 1422 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() && 1423 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() && 1424 MI->getOperand(Op+1).getImm() == 1 && 1425 MI->getOperand(Op+2).getReg() == 0 && 1426 MI->getOperand(Op+3).getImm() == 0) { 1427 FrameIndex = MI->getOperand(Op).getIndex(); 1428 return true; 1429 } 1430 return false; 1431 } 1432 1433 static bool isFrameLoadOpcode(int Opcode) { 1434 switch (Opcode) { 1435 default: 1436 return false; 1437 case X86::MOV8rm: 1438 case X86::MOV16rm: 1439 case X86::MOV32rm: 1440 case X86::MOV64rm: 1441 case X86::LD_Fp64m: 1442 case X86::MOVSSrm: 1443 case X86::MOVSDrm: 1444 case X86::MOVAPSrm: 1445 case X86::MOVAPDrm: 1446 case X86::MOVDQArm: 1447 case X86::VMOVSSrm: 1448 case X86::VMOVSDrm: 1449 case X86::VMOVAPSrm: 1450 case X86::VMOVAPDrm: 1451 case X86::VMOVDQArm: 1452 case X86::VMOVAPSYrm: 1453 case X86::VMOVAPDYrm: 1454 case X86::VMOVDQAYrm: 1455 case X86::MMX_MOVD64rm: 1456 case X86::MMX_MOVQ64rm: 1457 return true; 1458 } 1459 } 1460 1461 static bool isFrameStoreOpcode(int Opcode) { 1462 switch (Opcode) { 1463 default: break; 1464 case X86::MOV8mr: 1465 case X86::MOV16mr: 1466 case X86::MOV32mr: 1467 case X86::MOV64mr: 1468 case X86::ST_FpP64m: 1469 case X86::MOVSSmr: 1470 case X86::MOVSDmr: 1471 case X86::MOVAPSmr: 1472 case X86::MOVAPDmr: 1473 case X86::MOVDQAmr: 1474 case X86::VMOVSSmr: 1475 case X86::VMOVSDmr: 1476 case X86::VMOVAPSmr: 1477 case X86::VMOVAPDmr: 1478 case X86::VMOVDQAmr: 1479 case X86::VMOVAPSYmr: 1480 case X86::VMOVAPDYmr: 1481 case X86::VMOVDQAYmr: 1482 case X86::MMX_MOVD64mr: 1483 case X86::MMX_MOVQ64mr: 1484 case X86::MMX_MOVNTQmr: 1485 return true; 1486 } 1487 return false; 1488 } 1489 1490 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1491 int &FrameIndex) const { 1492 if (isFrameLoadOpcode(MI->getOpcode())) 1493 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) 1494 return MI->getOperand(0).getReg(); 1495 return 0; 1496 } 1497 1498 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1499 int &FrameIndex) const { 1500 if (isFrameLoadOpcode(MI->getOpcode())) { 1501 unsigned Reg; 1502 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 1503 return Reg; 1504 // Check for post-frame index elimination operations 1505 const MachineMemOperand *Dummy; 1506 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1507 } 1508 return 0; 1509 } 1510 1511 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 1512 int &FrameIndex) const { 1513 if (isFrameStoreOpcode(MI->getOpcode())) 1514 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 && 1515 isFrameOperand(MI, 0, FrameIndex)) 1516 return MI->getOperand(X86::AddrNumOperands).getReg(); 1517 return 0; 1518 } 1519 1520 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 1521 int &FrameIndex) const { 1522 if (isFrameStoreOpcode(MI->getOpcode())) { 1523 unsigned Reg; 1524 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 1525 return Reg; 1526 // Check for post-frame index elimination operations 1527 const MachineMemOperand *Dummy; 1528 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 1529 } 1530 return 0; 1531 } 1532 1533 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by 1534 /// X86::MOVPC32r. 1535 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 1536 // Don't waste compile time scanning use-def chains of physregs. 1537 if (!TargetRegisterInfo::isVirtualRegister(BaseReg)) 1538 return false; 1539 bool isPICBase = false; 1540 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 1541 E = MRI.def_end(); I != E; ++I) { 1542 MachineInstr *DefMI = I.getOperand().getParent(); 1543 if (DefMI->getOpcode() != X86::MOVPC32r) 1544 return false; 1545 assert(!isPICBase && "More than one PIC base?"); 1546 isPICBase = true; 1547 } 1548 return isPICBase; 1549 } 1550 1551 bool 1552 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 1553 AliasAnalysis *AA) const { 1554 switch (MI->getOpcode()) { 1555 default: break; 1556 case X86::MOV8rm: 1557 case X86::MOV16rm: 1558 case X86::MOV32rm: 1559 case X86::MOV64rm: 1560 case X86::LD_Fp64m: 1561 case X86::MOVSSrm: 1562 case X86::MOVSDrm: 1563 case X86::MOVAPSrm: 1564 case X86::MOVUPSrm: 1565 case X86::MOVAPDrm: 1566 case X86::MOVDQArm: 1567 case X86::MOVDQUrm: 1568 case X86::VMOVSSrm: 1569 case X86::VMOVSDrm: 1570 case X86::VMOVAPSrm: 1571 case X86::VMOVUPSrm: 1572 case X86::VMOVAPDrm: 1573 case X86::VMOVDQArm: 1574 case X86::VMOVDQUrm: 1575 case X86::VMOVAPSYrm: 1576 case X86::VMOVUPSYrm: 1577 case X86::VMOVAPDYrm: 1578 case X86::VMOVDQAYrm: 1579 case X86::VMOVDQUYrm: 1580 case X86::MMX_MOVD64rm: 1581 case X86::MMX_MOVQ64rm: 1582 case X86::FsVMOVAPSrm: 1583 case X86::FsVMOVAPDrm: 1584 case X86::FsMOVAPSrm: 1585 case X86::FsMOVAPDrm: { 1586 // Loads from constant pools are trivially rematerializable. 1587 if (MI->getOperand(1).isReg() && 1588 MI->getOperand(2).isImm() && 1589 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 1590 MI->isInvariantLoad(AA)) { 1591 unsigned BaseReg = MI->getOperand(1).getReg(); 1592 if (BaseReg == 0 || BaseReg == X86::RIP) 1593 return true; 1594 // Allow re-materialization of PIC load. 1595 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 1596 return false; 1597 const MachineFunction &MF = *MI->getParent()->getParent(); 1598 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1599 return regIsPICBase(BaseReg, MRI); 1600 } 1601 return false; 1602 } 1603 1604 case X86::LEA32r: 1605 case X86::LEA64r: { 1606 if (MI->getOperand(2).isImm() && 1607 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 1608 !MI->getOperand(4).isReg()) { 1609 // lea fi#, lea GV, etc. are all rematerializable. 1610 if (!MI->getOperand(1).isReg()) 1611 return true; 1612 unsigned BaseReg = MI->getOperand(1).getReg(); 1613 if (BaseReg == 0) 1614 return true; 1615 // Allow re-materialization of lea PICBase + x. 1616 const MachineFunction &MF = *MI->getParent()->getParent(); 1617 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1618 return regIsPICBase(BaseReg, MRI); 1619 } 1620 return false; 1621 } 1622 } 1623 1624 // All other instructions marked M_REMATERIALIZABLE are always trivially 1625 // rematerializable. 1626 return true; 1627 } 1628 1629 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 1630 /// would clobber the EFLAGS condition register. Note the result may be 1631 /// conservative. If it cannot definitely determine the safety after visiting 1632 /// a few instructions in each direction it assumes it's not safe. 1633 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 1634 MachineBasicBlock::iterator I) { 1635 MachineBasicBlock::iterator E = MBB.end(); 1636 1637 // For compile time consideration, if we are not able to determine the 1638 // safety after visiting 4 instructions in each direction, we will assume 1639 // it's not safe. 1640 MachineBasicBlock::iterator Iter = I; 1641 for (unsigned i = 0; Iter != E && i < 4; ++i) { 1642 bool SeenDef = false; 1643 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1644 MachineOperand &MO = Iter->getOperand(j); 1645 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1646 SeenDef = true; 1647 if (!MO.isReg()) 1648 continue; 1649 if (MO.getReg() == X86::EFLAGS) { 1650 if (MO.isUse()) 1651 return false; 1652 SeenDef = true; 1653 } 1654 } 1655 1656 if (SeenDef) 1657 // This instruction defines EFLAGS, no need to look any further. 1658 return true; 1659 ++Iter; 1660 // Skip over DBG_VALUE. 1661 while (Iter != E && Iter->isDebugValue()) 1662 ++Iter; 1663 } 1664 1665 // It is safe to clobber EFLAGS at the end of a block of no successor has it 1666 // live in. 1667 if (Iter == E) { 1668 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(), 1669 SE = MBB.succ_end(); SI != SE; ++SI) 1670 if ((*SI)->isLiveIn(X86::EFLAGS)) 1671 return false; 1672 return true; 1673 } 1674 1675 MachineBasicBlock::iterator B = MBB.begin(); 1676 Iter = I; 1677 for (unsigned i = 0; i < 4; ++i) { 1678 // If we make it to the beginning of the block, it's safe to clobber 1679 // EFLAGS iff EFLAGS is not live-in. 1680 if (Iter == B) 1681 return !MBB.isLiveIn(X86::EFLAGS); 1682 1683 --Iter; 1684 // Skip over DBG_VALUE. 1685 while (Iter != B && Iter->isDebugValue()) 1686 --Iter; 1687 1688 bool SawKill = false; 1689 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1690 MachineOperand &MO = Iter->getOperand(j); 1691 // A register mask may clobber EFLAGS, but we should still look for a 1692 // live EFLAGS def. 1693 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1694 SawKill = true; 1695 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1696 if (MO.isDef()) return MO.isDead(); 1697 if (MO.isKill()) SawKill = true; 1698 } 1699 } 1700 1701 if (SawKill) 1702 // This instruction kills EFLAGS and doesn't redefine it, so 1703 // there's no need to look further. 1704 return true; 1705 } 1706 1707 // Conservative answer. 1708 return false; 1709 } 1710 1711 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1712 MachineBasicBlock::iterator I, 1713 unsigned DestReg, unsigned SubIdx, 1714 const MachineInstr *Orig, 1715 const TargetRegisterInfo &TRI) const { 1716 // MOV32r0 is implemented with a xor which clobbers condition code. 1717 // Re-materialize it as movri instructions to avoid side effects. 1718 unsigned Opc = Orig->getOpcode(); 1719 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) { 1720 DebugLoc DL = Orig->getDebugLoc(); 1721 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0)) 1722 .addImm(0); 1723 } else { 1724 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1725 MBB.insert(I, MI); 1726 } 1727 1728 MachineInstr *NewMI = prior(I); 1729 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1730 } 1731 1732 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1733 /// is not marked dead. 1734 static bool hasLiveCondCodeDef(MachineInstr *MI) { 1735 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1736 MachineOperand &MO = MI->getOperand(i); 1737 if (MO.isReg() && MO.isDef() && 1738 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1739 return true; 1740 } 1741 } 1742 return false; 1743 } 1744 1745 /// getTruncatedShiftCount - check whether the shift count for a machine operand 1746 /// is non-zero. 1747 inline static unsigned getTruncatedShiftCount(MachineInstr *MI, 1748 unsigned ShiftAmtOperandIdx) { 1749 // The shift count is six bits with the REX.W prefix and five bits without. 1750 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31; 1751 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm(); 1752 return Imm & ShiftCountMask; 1753 } 1754 1755 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate 1756 /// can be represented by a LEA instruction. 1757 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) { 1758 // Left shift instructions can be transformed into load-effective-address 1759 // instructions if we can encode them appropriately. 1760 // A LEA instruction utilizes a SIB byte to encode it's scale factor. 1761 // The SIB.scale field is two bits wide which means that we can encode any 1762 // shift amount less than 4. 1763 return ShAmt < 4 && ShAmt > 0; 1764 } 1765 1766 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, 1767 unsigned Opc, bool AllowSP, 1768 unsigned &NewSrc, bool &isKill, bool &isUndef, 1769 MachineOperand &ImplicitOp) const { 1770 MachineFunction &MF = *MI->getParent()->getParent(); 1771 const TargetRegisterClass *RC; 1772 if (AllowSP) { 1773 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass; 1774 } else { 1775 RC = Opc != X86::LEA32r ? 1776 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass; 1777 } 1778 unsigned SrcReg = Src.getReg(); 1779 1780 // For both LEA64 and LEA32 the register already has essentially the right 1781 // type (32-bit or 64-bit) we may just need to forbid SP. 1782 if (Opc != X86::LEA64_32r) { 1783 NewSrc = SrcReg; 1784 isKill = Src.isKill(); 1785 isUndef = Src.isUndef(); 1786 1787 if (TargetRegisterInfo::isVirtualRegister(NewSrc) && 1788 !MF.getRegInfo().constrainRegClass(NewSrc, RC)) 1789 return false; 1790 1791 return true; 1792 } 1793 1794 // This is for an LEA64_32r and incoming registers are 32-bit. One way or 1795 // another we need to add 64-bit registers to the final MI. 1796 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) { 1797 ImplicitOp = Src; 1798 ImplicitOp.setImplicit(); 1799 1800 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64); 1801 MachineBasicBlock::LivenessQueryResult LQR = 1802 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI); 1803 1804 switch (LQR) { 1805 case MachineBasicBlock::LQR_Unknown: 1806 // We can't give sane liveness flags to the instruction, abandon LEA 1807 // formation. 1808 return false; 1809 case MachineBasicBlock::LQR_Live: 1810 isKill = MI->killsRegister(SrcReg); 1811 isUndef = false; 1812 break; 1813 default: 1814 // The physreg itself is dead, so we have to use it as an <undef>. 1815 isKill = false; 1816 isUndef = true; 1817 break; 1818 } 1819 } else { 1820 // Virtual register of the wrong class, we have to create a temporary 64-bit 1821 // vreg to feed into the LEA. 1822 NewSrc = MF.getRegInfo().createVirtualRegister(RC); 1823 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), 1824 get(TargetOpcode::COPY)) 1825 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit) 1826 .addOperand(Src); 1827 1828 // Which is obviously going to be dead after we're done with it. 1829 isKill = true; 1830 isUndef = false; 1831 } 1832 1833 // We've set all the parameters without issue. 1834 return true; 1835 } 1836 1837 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1838 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1839 /// to a 32-bit superregister and then truncating back down to a 16-bit 1840 /// subregister. 1841 MachineInstr * 1842 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1843 MachineFunction::iterator &MFI, 1844 MachineBasicBlock::iterator &MBBI, 1845 LiveVariables *LV) const { 1846 MachineInstr *MI = MBBI; 1847 unsigned Dest = MI->getOperand(0).getReg(); 1848 unsigned Src = MI->getOperand(1).getReg(); 1849 bool isDead = MI->getOperand(0).isDead(); 1850 bool isKill = MI->getOperand(1).isKill(); 1851 1852 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1853 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1854 unsigned Opc, leaInReg; 1855 if (TM.getSubtarget<X86Subtarget>().is64Bit()) { 1856 Opc = X86::LEA64_32r; 1857 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); 1858 } else { 1859 Opc = X86::LEA32r; 1860 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1861 } 1862 1863 // Build and insert into an implicit UNDEF value. This is OK because 1864 // well be shifting and then extracting the lower 16-bits. 1865 // This has the potential to cause partial register stall. e.g. 1866 // movw (%rbp,%rcx,2), %dx 1867 // leal -65(%rdx), %esi 1868 // But testing has shown this *does* help performance in 64-bit mode (at 1869 // least on modern x86 machines). 1870 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1871 MachineInstr *InsMI = 1872 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1873 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1874 .addReg(Src, getKillRegState(isKill)); 1875 1876 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1877 get(Opc), leaOutReg); 1878 switch (MIOpc) { 1879 default: llvm_unreachable("Unreachable!"); 1880 case X86::SHL16ri: { 1881 unsigned ShAmt = MI->getOperand(2).getImm(); 1882 MIB.addReg(0).addImm(1 << ShAmt) 1883 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 1884 break; 1885 } 1886 case X86::INC16r: 1887 case X86::INC64_16r: 1888 addRegOffset(MIB, leaInReg, true, 1); 1889 break; 1890 case X86::DEC16r: 1891 case X86::DEC64_16r: 1892 addRegOffset(MIB, leaInReg, true, -1); 1893 break; 1894 case X86::ADD16ri: 1895 case X86::ADD16ri8: 1896 case X86::ADD16ri_DB: 1897 case X86::ADD16ri8_DB: 1898 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1899 break; 1900 case X86::ADD16rr: 1901 case X86::ADD16rr_DB: { 1902 unsigned Src2 = MI->getOperand(2).getReg(); 1903 bool isKill2 = MI->getOperand(2).isKill(); 1904 unsigned leaInReg2 = 0; 1905 MachineInstr *InsMI2 = 0; 1906 if (Src == Src2) { 1907 // ADD16rr %reg1028<kill>, %reg1028 1908 // just a single insert_subreg. 1909 addRegReg(MIB, leaInReg, true, leaInReg, false); 1910 } else { 1911 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 1912 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); 1913 else 1914 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1915 // Build and insert into an implicit UNDEF value. This is OK because 1916 // well be shifting and then extracting the lower 16-bits. 1917 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); 1918 InsMI2 = 1919 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1920 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 1921 .addReg(Src2, getKillRegState(isKill2)); 1922 addRegReg(MIB, leaInReg, true, leaInReg2, true); 1923 } 1924 if (LV && isKill2 && InsMI2) 1925 LV->replaceKillInstruction(Src2, MI, InsMI2); 1926 break; 1927 } 1928 } 1929 1930 MachineInstr *NewMI = MIB; 1931 MachineInstr *ExtMI = 1932 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1933 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1934 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 1935 1936 if (LV) { 1937 // Update live variables 1938 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1939 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1940 if (isKill) 1941 LV->replaceKillInstruction(Src, MI, InsMI); 1942 if (isDead) 1943 LV->replaceKillInstruction(Dest, MI, ExtMI); 1944 } 1945 1946 return ExtMI; 1947 } 1948 1949 /// convertToThreeAddress - This method must be implemented by targets that 1950 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1951 /// may be able to convert a two-address instruction into a true 1952 /// three-address instruction on demand. This allows the X86 target (for 1953 /// example) to convert ADD and SHL instructions into LEA instructions if they 1954 /// would require register copies due to two-addressness. 1955 /// 1956 /// This method returns a null pointer if the transformation cannot be 1957 /// performed, otherwise it returns the new instruction. 1958 /// 1959 MachineInstr * 1960 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1961 MachineBasicBlock::iterator &MBBI, 1962 LiveVariables *LV) const { 1963 MachineInstr *MI = MBBI; 1964 1965 // The following opcodes also sets the condition code register(s). Only 1966 // convert them to equivalent lea if the condition code register def's 1967 // are dead! 1968 if (hasLiveCondCodeDef(MI)) 1969 return 0; 1970 1971 MachineFunction &MF = *MI->getParent()->getParent(); 1972 // All instructions input are two-addr instructions. Get the known operands. 1973 const MachineOperand &Dest = MI->getOperand(0); 1974 const MachineOperand &Src = MI->getOperand(1); 1975 1976 MachineInstr *NewMI = NULL; 1977 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1978 // we have better subtarget support, enable the 16-bit LEA generation here. 1979 // 16-bit LEA is also slow on Core2. 1980 bool DisableLEA16 = true; 1981 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1982 1983 unsigned MIOpc = MI->getOpcode(); 1984 switch (MIOpc) { 1985 case X86::SHUFPSrri: { 1986 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1987 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1988 1989 unsigned B = MI->getOperand(1).getReg(); 1990 unsigned C = MI->getOperand(2).getReg(); 1991 if (B != C) return 0; 1992 unsigned M = MI->getOperand(3).getImm(); 1993 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1994 .addOperand(Dest).addOperand(Src).addImm(M); 1995 break; 1996 } 1997 case X86::SHUFPDrri: { 1998 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!"); 1999 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 2000 2001 unsigned B = MI->getOperand(1).getReg(); 2002 unsigned C = MI->getOperand(2).getReg(); 2003 if (B != C) return 0; 2004 unsigned M = MI->getOperand(3).getImm(); 2005 2006 // Convert to PSHUFD mask. 2007 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44; 2008 2009 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 2010 .addOperand(Dest).addOperand(Src).addImm(M); 2011 break; 2012 } 2013 case X86::SHL64ri: { 2014 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 2015 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 2016 if (!isTruncatedShiftCountForLEA(ShAmt)) return 0; 2017 2018 // LEA can't handle RSP. 2019 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 2020 !MF.getRegInfo().constrainRegClass(Src.getReg(), 2021 &X86::GR64_NOSPRegClass)) 2022 return 0; 2023 2024 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2025 .addOperand(Dest) 2026 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 2027 break; 2028 } 2029 case X86::SHL32ri: { 2030 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 2031 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 2032 if (!isTruncatedShiftCountForLEA(ShAmt)) return 0; 2033 2034 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2035 2036 // LEA can't handle ESP. 2037 bool isKill, isUndef; 2038 unsigned SrcReg; 2039 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2040 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 2041 SrcReg, isKill, isUndef, ImplicitOp)) 2042 return 0; 2043 2044 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2045 .addOperand(Dest) 2046 .addReg(0).addImm(1 << ShAmt) 2047 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) 2048 .addImm(0).addReg(0); 2049 if (ImplicitOp.getReg() != 0) 2050 MIB.addOperand(ImplicitOp); 2051 NewMI = MIB; 2052 2053 break; 2054 } 2055 case X86::SHL16ri: { 2056 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 2057 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 2058 if (!isTruncatedShiftCountForLEA(ShAmt)) return 0; 2059 2060 if (DisableLEA16) 2061 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2062 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2063 .addOperand(Dest) 2064 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 2065 break; 2066 } 2067 default: { 2068 2069 switch (MIOpc) { 2070 default: return 0; 2071 case X86::INC64r: 2072 case X86::INC32r: 2073 case X86::INC64_32r: { 2074 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 2075 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 2076 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2077 bool isKill, isUndef; 2078 unsigned SrcReg; 2079 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2080 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 2081 SrcReg, isKill, isUndef, ImplicitOp)) 2082 return 0; 2083 2084 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2085 .addOperand(Dest) 2086 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)); 2087 if (ImplicitOp.getReg() != 0) 2088 MIB.addOperand(ImplicitOp); 2089 2090 NewMI = addOffset(MIB, 1); 2091 break; 2092 } 2093 case X86::INC16r: 2094 case X86::INC64_16r: 2095 if (DisableLEA16) 2096 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2097 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 2098 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2099 .addOperand(Dest).addOperand(Src), 1); 2100 break; 2101 case X86::DEC64r: 2102 case X86::DEC32r: 2103 case X86::DEC64_32r: { 2104 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2105 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 2106 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 2107 2108 bool isKill, isUndef; 2109 unsigned SrcReg; 2110 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2111 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 2112 SrcReg, isKill, isUndef, ImplicitOp)) 2113 return 0; 2114 2115 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2116 .addOperand(Dest) 2117 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill)); 2118 if (ImplicitOp.getReg() != 0) 2119 MIB.addOperand(ImplicitOp); 2120 2121 NewMI = addOffset(MIB, -1); 2122 2123 break; 2124 } 2125 case X86::DEC16r: 2126 case X86::DEC64_16r: 2127 if (DisableLEA16) 2128 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2129 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2130 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2131 .addOperand(Dest).addOperand(Src), -1); 2132 break; 2133 case X86::ADD64rr: 2134 case X86::ADD64rr_DB: 2135 case X86::ADD32rr: 2136 case X86::ADD32rr_DB: { 2137 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2138 unsigned Opc; 2139 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) 2140 Opc = X86::LEA64r; 2141 else 2142 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2143 2144 bool isKill, isUndef; 2145 unsigned SrcReg; 2146 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2147 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 2148 SrcReg, isKill, isUndef, ImplicitOp)) 2149 return 0; 2150 2151 const MachineOperand &Src2 = MI->getOperand(2); 2152 bool isKill2, isUndef2; 2153 unsigned SrcReg2; 2154 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false); 2155 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, 2156 SrcReg2, isKill2, isUndef2, ImplicitOp2)) 2157 return 0; 2158 2159 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2160 .addOperand(Dest); 2161 if (ImplicitOp.getReg() != 0) 2162 MIB.addOperand(ImplicitOp); 2163 if (ImplicitOp2.getReg() != 0) 2164 MIB.addOperand(ImplicitOp2); 2165 2166 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2); 2167 2168 // Preserve undefness of the operands. 2169 NewMI->getOperand(1).setIsUndef(isUndef); 2170 NewMI->getOperand(3).setIsUndef(isUndef2); 2171 2172 if (LV && Src2.isKill()) 2173 LV->replaceKillInstruction(SrcReg2, MI, NewMI); 2174 break; 2175 } 2176 case X86::ADD16rr: 2177 case X86::ADD16rr_DB: { 2178 if (DisableLEA16) 2179 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2180 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2181 unsigned Src2 = MI->getOperand(2).getReg(); 2182 bool isKill2 = MI->getOperand(2).isKill(); 2183 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2184 .addOperand(Dest), 2185 Src.getReg(), Src.isKill(), Src2, isKill2); 2186 2187 // Preserve undefness of the operands. 2188 bool isUndef = MI->getOperand(1).isUndef(); 2189 bool isUndef2 = MI->getOperand(2).isUndef(); 2190 NewMI->getOperand(1).setIsUndef(isUndef); 2191 NewMI->getOperand(3).setIsUndef(isUndef2); 2192 2193 if (LV && isKill2) 2194 LV->replaceKillInstruction(Src2, MI, NewMI); 2195 break; 2196 } 2197 case X86::ADD64ri32: 2198 case X86::ADD64ri8: 2199 case X86::ADD64ri32_DB: 2200 case X86::ADD64ri8_DB: 2201 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2202 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2203 .addOperand(Dest).addOperand(Src), 2204 MI->getOperand(2).getImm()); 2205 break; 2206 case X86::ADD32ri: 2207 case X86::ADD32ri8: 2208 case X86::ADD32ri_DB: 2209 case X86::ADD32ri8_DB: { 2210 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2211 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2212 2213 bool isKill, isUndef; 2214 unsigned SrcReg; 2215 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); 2216 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 2217 SrcReg, isKill, isUndef, ImplicitOp)) 2218 return 0; 2219 2220 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2221 .addOperand(Dest) 2222 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill)); 2223 if (ImplicitOp.getReg() != 0) 2224 MIB.addOperand(ImplicitOp); 2225 2226 NewMI = addOffset(MIB, MI->getOperand(2).getImm()); 2227 break; 2228 } 2229 case X86::ADD16ri: 2230 case X86::ADD16ri8: 2231 case X86::ADD16ri_DB: 2232 case X86::ADD16ri8_DB: 2233 if (DisableLEA16) 2234 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2235 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2236 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2237 .addOperand(Dest).addOperand(Src), 2238 MI->getOperand(2).getImm()); 2239 break; 2240 } 2241 } 2242 } 2243 2244 if (!NewMI) return 0; 2245 2246 if (LV) { // Update live variables 2247 if (Src.isKill()) 2248 LV->replaceKillInstruction(Src.getReg(), MI, NewMI); 2249 if (Dest.isDead()) 2250 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI); 2251 } 2252 2253 MFI->insert(MBBI, NewMI); // Insert the new inst 2254 return NewMI; 2255 } 2256 2257 /// commuteInstruction - We have a few instructions that must be hacked on to 2258 /// commute them. 2259 /// 2260 MachineInstr * 2261 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 2262 switch (MI->getOpcode()) { 2263 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 2264 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 2265 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 2266 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 2267 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 2268 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 2269 unsigned Opc; 2270 unsigned Size; 2271 switch (MI->getOpcode()) { 2272 default: llvm_unreachable("Unreachable!"); 2273 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 2274 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 2275 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 2276 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 2277 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 2278 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 2279 } 2280 unsigned Amt = MI->getOperand(3).getImm(); 2281 if (NewMI) { 2282 MachineFunction &MF = *MI->getParent()->getParent(); 2283 MI = MF.CloneMachineInstr(MI); 2284 NewMI = false; 2285 } 2286 MI->setDesc(get(Opc)); 2287 MI->getOperand(3).setImm(Size-Amt); 2288 return TargetInstrInfo::commuteInstruction(MI, NewMI); 2289 } 2290 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr: 2291 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr: 2292 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr: 2293 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr: 2294 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr: 2295 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr: 2296 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr: 2297 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr: 2298 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr: 2299 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr: 2300 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr: 2301 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr: 2302 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr: 2303 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr: 2304 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr: 2305 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: { 2306 unsigned Opc; 2307 switch (MI->getOpcode()) { 2308 default: llvm_unreachable("Unreachable!"); 2309 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 2310 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 2311 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 2312 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 2313 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 2314 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 2315 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 2316 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 2317 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 2318 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 2319 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 2320 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 2321 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 2322 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 2323 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 2324 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 2325 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 2326 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 2327 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 2328 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 2329 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 2330 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 2331 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 2332 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 2333 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 2334 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 2335 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 2336 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 2337 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 2338 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 2339 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 2340 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 2341 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 2342 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 2343 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 2344 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 2345 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 2346 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 2347 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 2348 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 2349 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 2350 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 2351 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 2352 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 2353 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 2354 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 2355 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 2356 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 2357 } 2358 if (NewMI) { 2359 MachineFunction &MF = *MI->getParent()->getParent(); 2360 MI = MF.CloneMachineInstr(MI); 2361 NewMI = false; 2362 } 2363 MI->setDesc(get(Opc)); 2364 // Fallthrough intended. 2365 } 2366 default: 2367 return TargetInstrInfo::commuteInstruction(MI, NewMI); 2368 } 2369 } 2370 2371 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { 2372 switch (BrOpc) { 2373 default: return X86::COND_INVALID; 2374 case X86::JE_4: return X86::COND_E; 2375 case X86::JNE_4: return X86::COND_NE; 2376 case X86::JL_4: return X86::COND_L; 2377 case X86::JLE_4: return X86::COND_LE; 2378 case X86::JG_4: return X86::COND_G; 2379 case X86::JGE_4: return X86::COND_GE; 2380 case X86::JB_4: return X86::COND_B; 2381 case X86::JBE_4: return X86::COND_BE; 2382 case X86::JA_4: return X86::COND_A; 2383 case X86::JAE_4: return X86::COND_AE; 2384 case X86::JS_4: return X86::COND_S; 2385 case X86::JNS_4: return X86::COND_NS; 2386 case X86::JP_4: return X86::COND_P; 2387 case X86::JNP_4: return X86::COND_NP; 2388 case X86::JO_4: return X86::COND_O; 2389 case X86::JNO_4: return X86::COND_NO; 2390 } 2391 } 2392 2393 /// getCondFromSETOpc - return condition code of a SET opcode. 2394 static X86::CondCode getCondFromSETOpc(unsigned Opc) { 2395 switch (Opc) { 2396 default: return X86::COND_INVALID; 2397 case X86::SETAr: case X86::SETAm: return X86::COND_A; 2398 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE; 2399 case X86::SETBr: case X86::SETBm: return X86::COND_B; 2400 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE; 2401 case X86::SETEr: case X86::SETEm: return X86::COND_E; 2402 case X86::SETGr: case X86::SETGm: return X86::COND_G; 2403 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE; 2404 case X86::SETLr: case X86::SETLm: return X86::COND_L; 2405 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE; 2406 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE; 2407 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO; 2408 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP; 2409 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS; 2410 case X86::SETOr: case X86::SETOm: return X86::COND_O; 2411 case X86::SETPr: case X86::SETPm: return X86::COND_P; 2412 case X86::SETSr: case X86::SETSm: return X86::COND_S; 2413 } 2414 } 2415 2416 /// getCondFromCmovOpc - return condition code of a CMov opcode. 2417 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) { 2418 switch (Opc) { 2419 default: return X86::COND_INVALID; 2420 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm: 2421 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr: 2422 return X86::COND_A; 2423 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm: 2424 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr: 2425 return X86::COND_AE; 2426 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm: 2427 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr: 2428 return X86::COND_B; 2429 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm: 2430 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr: 2431 return X86::COND_BE; 2432 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm: 2433 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr: 2434 return X86::COND_E; 2435 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm: 2436 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr: 2437 return X86::COND_G; 2438 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm: 2439 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr: 2440 return X86::COND_GE; 2441 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm: 2442 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr: 2443 return X86::COND_L; 2444 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm: 2445 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr: 2446 return X86::COND_LE; 2447 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm: 2448 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr: 2449 return X86::COND_NE; 2450 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm: 2451 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr: 2452 return X86::COND_NO; 2453 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm: 2454 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr: 2455 return X86::COND_NP; 2456 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm: 2457 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr: 2458 return X86::COND_NS; 2459 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm: 2460 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr: 2461 return X86::COND_O; 2462 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm: 2463 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr: 2464 return X86::COND_P; 2465 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm: 2466 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr: 2467 return X86::COND_S; 2468 } 2469 } 2470 2471 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 2472 switch (CC) { 2473 default: llvm_unreachable("Illegal condition code!"); 2474 case X86::COND_E: return X86::JE_4; 2475 case X86::COND_NE: return X86::JNE_4; 2476 case X86::COND_L: return X86::JL_4; 2477 case X86::COND_LE: return X86::JLE_4; 2478 case X86::COND_G: return X86::JG_4; 2479 case X86::COND_GE: return X86::JGE_4; 2480 case X86::COND_B: return X86::JB_4; 2481 case X86::COND_BE: return X86::JBE_4; 2482 case X86::COND_A: return X86::JA_4; 2483 case X86::COND_AE: return X86::JAE_4; 2484 case X86::COND_S: return X86::JS_4; 2485 case X86::COND_NS: return X86::JNS_4; 2486 case X86::COND_P: return X86::JP_4; 2487 case X86::COND_NP: return X86::JNP_4; 2488 case X86::COND_O: return X86::JO_4; 2489 case X86::COND_NO: return X86::JNO_4; 2490 } 2491 } 2492 2493 /// GetOppositeBranchCondition - Return the inverse of the specified condition, 2494 /// e.g. turning COND_E to COND_NE. 2495 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 2496 switch (CC) { 2497 default: llvm_unreachable("Illegal condition code!"); 2498 case X86::COND_E: return X86::COND_NE; 2499 case X86::COND_NE: return X86::COND_E; 2500 case X86::COND_L: return X86::COND_GE; 2501 case X86::COND_LE: return X86::COND_G; 2502 case X86::COND_G: return X86::COND_LE; 2503 case X86::COND_GE: return X86::COND_L; 2504 case X86::COND_B: return X86::COND_AE; 2505 case X86::COND_BE: return X86::COND_A; 2506 case X86::COND_A: return X86::COND_BE; 2507 case X86::COND_AE: return X86::COND_B; 2508 case X86::COND_S: return X86::COND_NS; 2509 case X86::COND_NS: return X86::COND_S; 2510 case X86::COND_P: return X86::COND_NP; 2511 case X86::COND_NP: return X86::COND_P; 2512 case X86::COND_O: return X86::COND_NO; 2513 case X86::COND_NO: return X86::COND_O; 2514 } 2515 } 2516 2517 /// getSwappedCondition - assume the flags are set by MI(a,b), return 2518 /// the condition code if we modify the instructions such that flags are 2519 /// set by MI(b,a). 2520 static X86::CondCode getSwappedCondition(X86::CondCode CC) { 2521 switch (CC) { 2522 default: return X86::COND_INVALID; 2523 case X86::COND_E: return X86::COND_E; 2524 case X86::COND_NE: return X86::COND_NE; 2525 case X86::COND_L: return X86::COND_G; 2526 case X86::COND_LE: return X86::COND_GE; 2527 case X86::COND_G: return X86::COND_L; 2528 case X86::COND_GE: return X86::COND_LE; 2529 case X86::COND_B: return X86::COND_A; 2530 case X86::COND_BE: return X86::COND_AE; 2531 case X86::COND_A: return X86::COND_B; 2532 case X86::COND_AE: return X86::COND_BE; 2533 } 2534 } 2535 2536 /// getSETFromCond - Return a set opcode for the given condition and 2537 /// whether it has memory operand. 2538 static unsigned getSETFromCond(X86::CondCode CC, 2539 bool HasMemoryOperand) { 2540 static const uint16_t Opc[16][2] = { 2541 { X86::SETAr, X86::SETAm }, 2542 { X86::SETAEr, X86::SETAEm }, 2543 { X86::SETBr, X86::SETBm }, 2544 { X86::SETBEr, X86::SETBEm }, 2545 { X86::SETEr, X86::SETEm }, 2546 { X86::SETGr, X86::SETGm }, 2547 { X86::SETGEr, X86::SETGEm }, 2548 { X86::SETLr, X86::SETLm }, 2549 { X86::SETLEr, X86::SETLEm }, 2550 { X86::SETNEr, X86::SETNEm }, 2551 { X86::SETNOr, X86::SETNOm }, 2552 { X86::SETNPr, X86::SETNPm }, 2553 { X86::SETNSr, X86::SETNSm }, 2554 { X86::SETOr, X86::SETOm }, 2555 { X86::SETPr, X86::SETPm }, 2556 { X86::SETSr, X86::SETSm } 2557 }; 2558 2559 assert(CC < 16 && "Can only handle standard cond codes"); 2560 return Opc[CC][HasMemoryOperand ? 1 : 0]; 2561 } 2562 2563 /// getCMovFromCond - Return a cmov opcode for the given condition, 2564 /// register size in bytes, and operand type. 2565 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes, 2566 bool HasMemoryOperand) { 2567 static const uint16_t Opc[32][3] = { 2568 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr }, 2569 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr }, 2570 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr }, 2571 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr }, 2572 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr }, 2573 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr }, 2574 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr }, 2575 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr }, 2576 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr }, 2577 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr }, 2578 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr }, 2579 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr }, 2580 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr }, 2581 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr }, 2582 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr }, 2583 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr }, 2584 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm }, 2585 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm }, 2586 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm }, 2587 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm }, 2588 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm }, 2589 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm }, 2590 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm }, 2591 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm }, 2592 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm }, 2593 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm }, 2594 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm }, 2595 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm }, 2596 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm }, 2597 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm }, 2598 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm }, 2599 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm } 2600 }; 2601 2602 assert(CC < 16 && "Can only handle standard cond codes"); 2603 unsigned Idx = HasMemoryOperand ? 16+CC : CC; 2604 switch(RegBytes) { 2605 default: llvm_unreachable("Illegal register size!"); 2606 case 2: return Opc[Idx][0]; 2607 case 4: return Opc[Idx][1]; 2608 case 8: return Opc[Idx][2]; 2609 } 2610 } 2611 2612 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 2613 if (!MI->isTerminator()) return false; 2614 2615 // Conditional branch is a special case. 2616 if (MI->isBranch() && !MI->isBarrier()) 2617 return true; 2618 if (!MI->isPredicable()) 2619 return true; 2620 return !isPredicated(MI); 2621 } 2622 2623 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 2624 MachineBasicBlock *&TBB, 2625 MachineBasicBlock *&FBB, 2626 SmallVectorImpl<MachineOperand> &Cond, 2627 bool AllowModify) const { 2628 // Start from the bottom of the block and work up, examining the 2629 // terminator instructions. 2630 MachineBasicBlock::iterator I = MBB.end(); 2631 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 2632 while (I != MBB.begin()) { 2633 --I; 2634 if (I->isDebugValue()) 2635 continue; 2636 2637 // Working from the bottom, when we see a non-terminator instruction, we're 2638 // done. 2639 if (!isUnpredicatedTerminator(I)) 2640 break; 2641 2642 // A terminator that isn't a branch can't easily be handled by this 2643 // analysis. 2644 if (!I->isBranch()) 2645 return true; 2646 2647 // Handle unconditional branches. 2648 if (I->getOpcode() == X86::JMP_4) { 2649 UnCondBrIter = I; 2650 2651 if (!AllowModify) { 2652 TBB = I->getOperand(0).getMBB(); 2653 continue; 2654 } 2655 2656 // If the block has any instructions after a JMP, delete them. 2657 while (llvm::next(I) != MBB.end()) 2658 llvm::next(I)->eraseFromParent(); 2659 2660 Cond.clear(); 2661 FBB = 0; 2662 2663 // Delete the JMP if it's equivalent to a fall-through. 2664 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 2665 TBB = 0; 2666 I->eraseFromParent(); 2667 I = MBB.end(); 2668 UnCondBrIter = MBB.end(); 2669 continue; 2670 } 2671 2672 // TBB is used to indicate the unconditional destination. 2673 TBB = I->getOperand(0).getMBB(); 2674 continue; 2675 } 2676 2677 // Handle conditional branches. 2678 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); 2679 if (BranchCode == X86::COND_INVALID) 2680 return true; // Can't handle indirect branch. 2681 2682 // Working from the bottom, handle the first conditional branch. 2683 if (Cond.empty()) { 2684 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 2685 if (AllowModify && UnCondBrIter != MBB.end() && 2686 MBB.isLayoutSuccessor(TargetBB)) { 2687 // If we can modify the code and it ends in something like: 2688 // 2689 // jCC L1 2690 // jmp L2 2691 // L1: 2692 // ... 2693 // L2: 2694 // 2695 // Then we can change this to: 2696 // 2697 // jnCC L2 2698 // L1: 2699 // ... 2700 // L2: 2701 // 2702 // Which is a bit more efficient. 2703 // We conditionally jump to the fall-through block. 2704 BranchCode = GetOppositeBranchCondition(BranchCode); 2705 unsigned JNCC = GetCondBranchFromCond(BranchCode); 2706 MachineBasicBlock::iterator OldInst = I; 2707 2708 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 2709 .addMBB(UnCondBrIter->getOperand(0).getMBB()); 2710 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4)) 2711 .addMBB(TargetBB); 2712 2713 OldInst->eraseFromParent(); 2714 UnCondBrIter->eraseFromParent(); 2715 2716 // Restart the analysis. 2717 UnCondBrIter = MBB.end(); 2718 I = MBB.end(); 2719 continue; 2720 } 2721 2722 FBB = TBB; 2723 TBB = I->getOperand(0).getMBB(); 2724 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 2725 continue; 2726 } 2727 2728 // Handle subsequent conditional branches. Only handle the case where all 2729 // conditional branches branch to the same destination and their condition 2730 // opcodes fit one of the special multi-branch idioms. 2731 assert(Cond.size() == 1); 2732 assert(TBB); 2733 2734 // Only handle the case where all conditional branches branch to the same 2735 // destination. 2736 if (TBB != I->getOperand(0).getMBB()) 2737 return true; 2738 2739 // If the conditions are the same, we can leave them alone. 2740 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 2741 if (OldBranchCode == BranchCode) 2742 continue; 2743 2744 // If they differ, see if they fit one of the known patterns. Theoretically, 2745 // we could handle more patterns here, but we shouldn't expect to see them 2746 // if instruction selection has done a reasonable job. 2747 if ((OldBranchCode == X86::COND_NP && 2748 BranchCode == X86::COND_E) || 2749 (OldBranchCode == X86::COND_E && 2750 BranchCode == X86::COND_NP)) 2751 BranchCode = X86::COND_NP_OR_E; 2752 else if ((OldBranchCode == X86::COND_P && 2753 BranchCode == X86::COND_NE) || 2754 (OldBranchCode == X86::COND_NE && 2755 BranchCode == X86::COND_P)) 2756 BranchCode = X86::COND_NE_OR_P; 2757 else 2758 return true; 2759 2760 // Update the MachineOperand. 2761 Cond[0].setImm(BranchCode); 2762 } 2763 2764 return false; 2765 } 2766 2767 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 2768 MachineBasicBlock::iterator I = MBB.end(); 2769 unsigned Count = 0; 2770 2771 while (I != MBB.begin()) { 2772 --I; 2773 if (I->isDebugValue()) 2774 continue; 2775 if (I->getOpcode() != X86::JMP_4 && 2776 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 2777 break; 2778 // Remove the branch. 2779 I->eraseFromParent(); 2780 I = MBB.end(); 2781 ++Count; 2782 } 2783 2784 return Count; 2785 } 2786 2787 unsigned 2788 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 2789 MachineBasicBlock *FBB, 2790 const SmallVectorImpl<MachineOperand> &Cond, 2791 DebugLoc DL) const { 2792 // Shouldn't be a fall through. 2793 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 2794 assert((Cond.size() == 1 || Cond.size() == 0) && 2795 "X86 branch conditions have one component!"); 2796 2797 if (Cond.empty()) { 2798 // Unconditional branch? 2799 assert(!FBB && "Unconditional branch with multiple successors!"); 2800 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB); 2801 return 1; 2802 } 2803 2804 // Conditional branch. 2805 unsigned Count = 0; 2806 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 2807 switch (CC) { 2808 case X86::COND_NP_OR_E: 2809 // Synthesize NP_OR_E with two branches. 2810 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB); 2811 ++Count; 2812 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB); 2813 ++Count; 2814 break; 2815 case X86::COND_NE_OR_P: 2816 // Synthesize NE_OR_P with two branches. 2817 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB); 2818 ++Count; 2819 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB); 2820 ++Count; 2821 break; 2822 default: { 2823 unsigned Opc = GetCondBranchFromCond(CC); 2824 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 2825 ++Count; 2826 } 2827 } 2828 if (FBB) { 2829 // Two-way Conditional branch. Insert the second branch. 2830 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB); 2831 ++Count; 2832 } 2833 return Count; 2834 } 2835 2836 bool X86InstrInfo:: 2837 canInsertSelect(const MachineBasicBlock &MBB, 2838 const SmallVectorImpl<MachineOperand> &Cond, 2839 unsigned TrueReg, unsigned FalseReg, 2840 int &CondCycles, int &TrueCycles, int &FalseCycles) const { 2841 // Not all subtargets have cmov instructions. 2842 if (!TM.getSubtarget<X86Subtarget>().hasCMov()) 2843 return false; 2844 if (Cond.size() != 1) 2845 return false; 2846 // We cannot do the composite conditions, at least not in SSA form. 2847 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S) 2848 return false; 2849 2850 // Check register classes. 2851 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2852 const TargetRegisterClass *RC = 2853 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 2854 if (!RC) 2855 return false; 2856 2857 // We have cmov instructions for 16, 32, and 64 bit general purpose registers. 2858 if (X86::GR16RegClass.hasSubClassEq(RC) || 2859 X86::GR32RegClass.hasSubClassEq(RC) || 2860 X86::GR64RegClass.hasSubClassEq(RC)) { 2861 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy 2862 // Bridge. Probably Ivy Bridge as well. 2863 CondCycles = 2; 2864 TrueCycles = 2; 2865 FalseCycles = 2; 2866 return true; 2867 } 2868 2869 // Can't do vectors. 2870 return false; 2871 } 2872 2873 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB, 2874 MachineBasicBlock::iterator I, DebugLoc DL, 2875 unsigned DstReg, 2876 const SmallVectorImpl<MachineOperand> &Cond, 2877 unsigned TrueReg, unsigned FalseReg) const { 2878 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2879 assert(Cond.size() == 1 && "Invalid Cond array"); 2880 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(), 2881 MRI.getRegClass(DstReg)->getSize(), 2882 false/*HasMemoryOperand*/); 2883 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); 2884 } 2885 2886 /// isHReg - Test if the given register is a physical h register. 2887 static bool isHReg(unsigned Reg) { 2888 return X86::GR8_ABCD_HRegClass.contains(Reg); 2889 } 2890 2891 // Try and copy between VR128/VR64 and GR64 registers. 2892 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, 2893 bool HasAVX) { 2894 // SrcReg(VR128) -> DestReg(GR64) 2895 // SrcReg(VR64) -> DestReg(GR64) 2896 // SrcReg(GR64) -> DestReg(VR128) 2897 // SrcReg(GR64) -> DestReg(VR64) 2898 2899 if (X86::GR64RegClass.contains(DestReg)) { 2900 if (X86::VR128RegClass.contains(SrcReg)) 2901 // Copy from a VR128 register to a GR64 register. 2902 return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr; 2903 if (X86::VR64RegClass.contains(SrcReg)) 2904 // Copy from a VR64 register to a GR64 register. 2905 return X86::MOVSDto64rr; 2906 } else if (X86::GR64RegClass.contains(SrcReg)) { 2907 // Copy from a GR64 register to a VR128 register. 2908 if (X86::VR128RegClass.contains(DestReg)) 2909 return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr; 2910 // Copy from a GR64 register to a VR64 register. 2911 if (X86::VR64RegClass.contains(DestReg)) 2912 return X86::MOV64toSDrr; 2913 } 2914 2915 // SrcReg(FR32) -> DestReg(GR32) 2916 // SrcReg(GR32) -> DestReg(FR32) 2917 2918 if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg)) 2919 // Copy from a FR32 register to a GR32 register. 2920 return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr; 2921 2922 if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg)) 2923 // Copy from a GR32 register to a FR32 register. 2924 return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr; 2925 2926 return 0; 2927 } 2928 2929 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 2930 MachineBasicBlock::iterator MI, DebugLoc DL, 2931 unsigned DestReg, unsigned SrcReg, 2932 bool KillSrc) const { 2933 // First deal with the normal symmetric copies. 2934 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 2935 unsigned Opc; 2936 if (X86::GR64RegClass.contains(DestReg, SrcReg)) 2937 Opc = X86::MOV64rr; 2938 else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 2939 Opc = X86::MOV32rr; 2940 else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 2941 Opc = X86::MOV16rr; 2942 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 2943 // Copying to or from a physical H register on x86-64 requires a NOREX 2944 // move. Otherwise use a normal move. 2945 if ((isHReg(DestReg) || isHReg(SrcReg)) && 2946 TM.getSubtarget<X86Subtarget>().is64Bit()) { 2947 Opc = X86::MOV8rr_NOREX; 2948 // Both operands must be encodable without an REX prefix. 2949 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && 2950 "8-bit H register can not be copied outside GR8_NOREX"); 2951 } else 2952 Opc = X86::MOV8rr; 2953 } else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 2954 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr; 2955 else if (X86::VR256RegClass.contains(DestReg, SrcReg)) 2956 Opc = X86::VMOVAPSYrr; 2957 else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 2958 Opc = X86::MMX_MOVQ64rr; 2959 else 2960 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX); 2961 2962 if (Opc) { 2963 BuildMI(MBB, MI, DL, get(Opc), DestReg) 2964 .addReg(SrcReg, getKillRegState(KillSrc)); 2965 return; 2966 } 2967 2968 // Moving EFLAGS to / from another register requires a push and a pop. 2969 // Notice that we have to adjust the stack if we don't want to clobber the 2970 // first frame index. See X86FrameLowering.cpp - colobbersTheStack. 2971 if (SrcReg == X86::EFLAGS) { 2972 if (X86::GR64RegClass.contains(DestReg)) { 2973 BuildMI(MBB, MI, DL, get(X86::PUSHF64)); 2974 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 2975 return; 2976 } 2977 if (X86::GR32RegClass.contains(DestReg)) { 2978 BuildMI(MBB, MI, DL, get(X86::PUSHF32)); 2979 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 2980 return; 2981 } 2982 } 2983 if (DestReg == X86::EFLAGS) { 2984 if (X86::GR64RegClass.contains(SrcReg)) { 2985 BuildMI(MBB, MI, DL, get(X86::PUSH64r)) 2986 .addReg(SrcReg, getKillRegState(KillSrc)); 2987 BuildMI(MBB, MI, DL, get(X86::POPF64)); 2988 return; 2989 } 2990 if (X86::GR32RegClass.contains(SrcReg)) { 2991 BuildMI(MBB, MI, DL, get(X86::PUSH32r)) 2992 .addReg(SrcReg, getKillRegState(KillSrc)); 2993 BuildMI(MBB, MI, DL, get(X86::POPF32)); 2994 return; 2995 } 2996 } 2997 2998 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 2999 << " to " << RI.getName(DestReg) << '\n'); 3000 llvm_unreachable("Cannot emit physreg copy instruction"); 3001 } 3002 3003 static unsigned getLoadStoreRegOpcode(unsigned Reg, 3004 const TargetRegisterClass *RC, 3005 bool isStackAligned, 3006 const TargetMachine &TM, 3007 bool load) { 3008 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 3009 switch (RC->getSize()) { 3010 default: 3011 llvm_unreachable("Unknown spill size"); 3012 case 1: 3013 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); 3014 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 3015 // Copying to or from a physical H register on x86-64 requires a NOREX 3016 // move. Otherwise use a normal move. 3017 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) 3018 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 3019 return load ? X86::MOV8rm : X86::MOV8mr; 3020 case 2: 3021 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); 3022 return load ? X86::MOV16rm : X86::MOV16mr; 3023 case 4: 3024 if (X86::GR32RegClass.hasSubClassEq(RC)) 3025 return load ? X86::MOV32rm : X86::MOV32mr; 3026 if (X86::FR32RegClass.hasSubClassEq(RC)) 3027 return load ? 3028 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) : 3029 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr); 3030 if (X86::RFP32RegClass.hasSubClassEq(RC)) 3031 return load ? X86::LD_Fp32m : X86::ST_Fp32m; 3032 llvm_unreachable("Unknown 4-byte regclass"); 3033 case 8: 3034 if (X86::GR64RegClass.hasSubClassEq(RC)) 3035 return load ? X86::MOV64rm : X86::MOV64mr; 3036 if (X86::FR64RegClass.hasSubClassEq(RC)) 3037 return load ? 3038 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) : 3039 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr); 3040 if (X86::VR64RegClass.hasSubClassEq(RC)) 3041 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 3042 if (X86::RFP64RegClass.hasSubClassEq(RC)) 3043 return load ? X86::LD_Fp64m : X86::ST_Fp64m; 3044 llvm_unreachable("Unknown 8-byte regclass"); 3045 case 10: 3046 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); 3047 return load ? X86::LD_Fp80m : X86::ST_FpP80m; 3048 case 16: { 3049 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass"); 3050 // If stack is realigned we can use aligned stores. 3051 if (isStackAligned) 3052 return load ? 3053 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) : 3054 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr); 3055 else 3056 return load ? 3057 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) : 3058 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); 3059 } 3060 case 32: 3061 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"); 3062 // If stack is realigned we can use aligned stores. 3063 if (isStackAligned) 3064 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr; 3065 else 3066 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr; 3067 } 3068 } 3069 3070 static unsigned getStoreRegOpcode(unsigned SrcReg, 3071 const TargetRegisterClass *RC, 3072 bool isStackAligned, 3073 TargetMachine &TM) { 3074 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false); 3075 } 3076 3077 3078 static unsigned getLoadRegOpcode(unsigned DestReg, 3079 const TargetRegisterClass *RC, 3080 bool isStackAligned, 3081 const TargetMachine &TM) { 3082 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true); 3083 } 3084 3085 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 3086 MachineBasicBlock::iterator MI, 3087 unsigned SrcReg, bool isKill, int FrameIdx, 3088 const TargetRegisterClass *RC, 3089 const TargetRegisterInfo *TRI) const { 3090 const MachineFunction &MF = *MBB.getParent(); 3091 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() && 3092 "Stack slot too small for store"); 3093 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3094 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) || 3095 RI.canRealignStack(MF); 3096 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 3097 DebugLoc DL = MBB.findDebugLoc(MI); 3098 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 3099 .addReg(SrcReg, getKillRegState(isKill)); 3100 } 3101 3102 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 3103 bool isKill, 3104 SmallVectorImpl<MachineOperand> &Addr, 3105 const TargetRegisterClass *RC, 3106 MachineInstr::mmo_iterator MMOBegin, 3107 MachineInstr::mmo_iterator MMOEnd, 3108 SmallVectorImpl<MachineInstr*> &NewMIs) const { 3109 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3110 bool isAligned = MMOBegin != MMOEnd && 3111 (*MMOBegin)->getAlignment() >= Alignment; 3112 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 3113 DebugLoc DL; 3114 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 3115 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 3116 MIB.addOperand(Addr[i]); 3117 MIB.addReg(SrcReg, getKillRegState(isKill)); 3118 (*MIB).setMemRefs(MMOBegin, MMOEnd); 3119 NewMIs.push_back(MIB); 3120 } 3121 3122 3123 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 3124 MachineBasicBlock::iterator MI, 3125 unsigned DestReg, int FrameIdx, 3126 const TargetRegisterClass *RC, 3127 const TargetRegisterInfo *TRI) const { 3128 const MachineFunction &MF = *MBB.getParent(); 3129 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3130 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) || 3131 RI.canRealignStack(MF); 3132 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 3133 DebugLoc DL = MBB.findDebugLoc(MI); 3134 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 3135 } 3136 3137 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 3138 SmallVectorImpl<MachineOperand> &Addr, 3139 const TargetRegisterClass *RC, 3140 MachineInstr::mmo_iterator MMOBegin, 3141 MachineInstr::mmo_iterator MMOEnd, 3142 SmallVectorImpl<MachineInstr*> &NewMIs) const { 3143 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3144 bool isAligned = MMOBegin != MMOEnd && 3145 (*MMOBegin)->getAlignment() >= Alignment; 3146 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 3147 DebugLoc DL; 3148 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 3149 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 3150 MIB.addOperand(Addr[i]); 3151 (*MIB).setMemRefs(MMOBegin, MMOEnd); 3152 NewMIs.push_back(MIB); 3153 } 3154 3155 bool X86InstrInfo:: 3156 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 3157 int &CmpMask, int &CmpValue) const { 3158 switch (MI->getOpcode()) { 3159 default: break; 3160 case X86::CMP64ri32: 3161 case X86::CMP64ri8: 3162 case X86::CMP32ri: 3163 case X86::CMP32ri8: 3164 case X86::CMP16ri: 3165 case X86::CMP16ri8: 3166 case X86::CMP8ri: 3167 SrcReg = MI->getOperand(0).getReg(); 3168 SrcReg2 = 0; 3169 CmpMask = ~0; 3170 CmpValue = MI->getOperand(1).getImm(); 3171 return true; 3172 // A SUB can be used to perform comparison. 3173 case X86::SUB64rm: 3174 case X86::SUB32rm: 3175 case X86::SUB16rm: 3176 case X86::SUB8rm: 3177 SrcReg = MI->getOperand(1).getReg(); 3178 SrcReg2 = 0; 3179 CmpMask = ~0; 3180 CmpValue = 0; 3181 return true; 3182 case X86::SUB64rr: 3183 case X86::SUB32rr: 3184 case X86::SUB16rr: 3185 case X86::SUB8rr: 3186 SrcReg = MI->getOperand(1).getReg(); 3187 SrcReg2 = MI->getOperand(2).getReg(); 3188 CmpMask = ~0; 3189 CmpValue = 0; 3190 return true; 3191 case X86::SUB64ri32: 3192 case X86::SUB64ri8: 3193 case X86::SUB32ri: 3194 case X86::SUB32ri8: 3195 case X86::SUB16ri: 3196 case X86::SUB16ri8: 3197 case X86::SUB8ri: 3198 SrcReg = MI->getOperand(1).getReg(); 3199 SrcReg2 = 0; 3200 CmpMask = ~0; 3201 CmpValue = MI->getOperand(2).getImm(); 3202 return true; 3203 case X86::CMP64rr: 3204 case X86::CMP32rr: 3205 case X86::CMP16rr: 3206 case X86::CMP8rr: 3207 SrcReg = MI->getOperand(0).getReg(); 3208 SrcReg2 = MI->getOperand(1).getReg(); 3209 CmpMask = ~0; 3210 CmpValue = 0; 3211 return true; 3212 case X86::TEST8rr: 3213 case X86::TEST16rr: 3214 case X86::TEST32rr: 3215 case X86::TEST64rr: 3216 SrcReg = MI->getOperand(0).getReg(); 3217 if (MI->getOperand(1).getReg() != SrcReg) return false; 3218 // Compare against zero. 3219 SrcReg2 = 0; 3220 CmpMask = ~0; 3221 CmpValue = 0; 3222 return true; 3223 } 3224 return false; 3225 } 3226 3227 /// isRedundantFlagInstr - check whether the first instruction, whose only 3228 /// purpose is to update flags, can be made redundant. 3229 /// CMPrr can be made redundant by SUBrr if the operands are the same. 3230 /// This function can be extended later on. 3231 /// SrcReg, SrcRegs: register operands for FlagI. 3232 /// ImmValue: immediate for FlagI if it takes an immediate. 3233 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg, 3234 unsigned SrcReg2, int ImmValue, 3235 MachineInstr *OI) { 3236 if (((FlagI->getOpcode() == X86::CMP64rr && 3237 OI->getOpcode() == X86::SUB64rr) || 3238 (FlagI->getOpcode() == X86::CMP32rr && 3239 OI->getOpcode() == X86::SUB32rr)|| 3240 (FlagI->getOpcode() == X86::CMP16rr && 3241 OI->getOpcode() == X86::SUB16rr)|| 3242 (FlagI->getOpcode() == X86::CMP8rr && 3243 OI->getOpcode() == X86::SUB8rr)) && 3244 ((OI->getOperand(1).getReg() == SrcReg && 3245 OI->getOperand(2).getReg() == SrcReg2) || 3246 (OI->getOperand(1).getReg() == SrcReg2 && 3247 OI->getOperand(2).getReg() == SrcReg))) 3248 return true; 3249 3250 if (((FlagI->getOpcode() == X86::CMP64ri32 && 3251 OI->getOpcode() == X86::SUB64ri32) || 3252 (FlagI->getOpcode() == X86::CMP64ri8 && 3253 OI->getOpcode() == X86::SUB64ri8) || 3254 (FlagI->getOpcode() == X86::CMP32ri && 3255 OI->getOpcode() == X86::SUB32ri) || 3256 (FlagI->getOpcode() == X86::CMP32ri8 && 3257 OI->getOpcode() == X86::SUB32ri8) || 3258 (FlagI->getOpcode() == X86::CMP16ri && 3259 OI->getOpcode() == X86::SUB16ri) || 3260 (FlagI->getOpcode() == X86::CMP16ri8 && 3261 OI->getOpcode() == X86::SUB16ri8) || 3262 (FlagI->getOpcode() == X86::CMP8ri && 3263 OI->getOpcode() == X86::SUB8ri)) && 3264 OI->getOperand(1).getReg() == SrcReg && 3265 OI->getOperand(2).getImm() == ImmValue) 3266 return true; 3267 return false; 3268 } 3269 3270 /// isDefConvertible - check whether the definition can be converted 3271 /// to remove a comparison against zero. 3272 inline static bool isDefConvertible(MachineInstr *MI) { 3273 switch (MI->getOpcode()) { 3274 default: return false; 3275 3276 // The shift instructions only modify ZF if their shift count is non-zero. 3277 // N.B.: The processor truncates the shift count depending on the encoding. 3278 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri: 3279 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri: 3280 return getTruncatedShiftCount(MI, 2) != 0; 3281 3282 // Some left shift instructions can be turned into LEA instructions but only 3283 // if their flags aren't used. Avoid transforming such instructions. 3284 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{ 3285 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 3286 if (isTruncatedShiftCountForLEA(ShAmt)) return false; 3287 return ShAmt != 0; 3288 } 3289 3290 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8: 3291 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8: 3292 return getTruncatedShiftCount(MI, 3) != 0; 3293 3294 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri: 3295 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8: 3296 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr: 3297 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm: 3298 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm: 3299 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r: 3300 case X86::DEC64_32r: case X86::DEC64_16r: 3301 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri: 3302 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8: 3303 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr: 3304 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm: 3305 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm: 3306 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r: 3307 case X86::INC64_32r: case X86::INC64_16r: 3308 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri: 3309 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8: 3310 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr: 3311 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm: 3312 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm: 3313 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri: 3314 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8: 3315 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr: 3316 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm: 3317 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm: 3318 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri: 3319 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8: 3320 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr: 3321 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm: 3322 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm: 3323 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r: 3324 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1: 3325 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1: 3326 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1: 3327 case X86::ADC32ri: case X86::ADC32ri8: 3328 case X86::ADC32rr: case X86::ADC64ri32: 3329 case X86::ADC64ri8: case X86::ADC64rr: 3330 case X86::SBB32ri: case X86::SBB32ri8: 3331 case X86::SBB32rr: case X86::SBB64ri32: 3332 case X86::SBB64ri8: case X86::SBB64rr: 3333 case X86::ANDN32rr: case X86::ANDN32rm: 3334 case X86::ANDN64rr: case X86::ANDN64rm: 3335 case X86::BEXTR32rr: case X86::BEXTR64rr: 3336 case X86::BEXTR32rm: case X86::BEXTR64rm: 3337 case X86::BLSI32rr: case X86::BLSI32rm: 3338 case X86::BLSI64rr: case X86::BLSI64rm: 3339 case X86::BLSMSK32rr:case X86::BLSMSK32rm: 3340 case X86::BLSMSK64rr:case X86::BLSMSK64rm: 3341 case X86::BLSR32rr: case X86::BLSR32rm: 3342 case X86::BLSR64rr: case X86::BLSR64rm: 3343 case X86::BZHI32rr: case X86::BZHI32rm: 3344 case X86::BZHI64rr: case X86::BZHI64rm: 3345 case X86::LZCNT16rr: case X86::LZCNT16rm: 3346 case X86::LZCNT32rr: case X86::LZCNT32rm: 3347 case X86::LZCNT64rr: case X86::LZCNT64rm: 3348 case X86::POPCNT16rr:case X86::POPCNT16rm: 3349 case X86::POPCNT32rr:case X86::POPCNT32rm: 3350 case X86::POPCNT64rr:case X86::POPCNT64rm: 3351 case X86::TZCNT16rr: case X86::TZCNT16rm: 3352 case X86::TZCNT32rr: case X86::TZCNT32rm: 3353 case X86::TZCNT64rr: case X86::TZCNT64rm: 3354 return true; 3355 } 3356 } 3357 3358 /// optimizeCompareInstr - Check if there exists an earlier instruction that 3359 /// operates on the same source operands and sets flags in the same way as 3360 /// Compare; remove Compare if possible. 3361 bool X86InstrInfo:: 3362 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 3363 int CmpMask, int CmpValue, 3364 const MachineRegisterInfo *MRI) const { 3365 // Check whether we can replace SUB with CMP. 3366 unsigned NewOpcode = 0; 3367 switch (CmpInstr->getOpcode()) { 3368 default: break; 3369 case X86::SUB64ri32: 3370 case X86::SUB64ri8: 3371 case X86::SUB32ri: 3372 case X86::SUB32ri8: 3373 case X86::SUB16ri: 3374 case X86::SUB16ri8: 3375 case X86::SUB8ri: 3376 case X86::SUB64rm: 3377 case X86::SUB32rm: 3378 case X86::SUB16rm: 3379 case X86::SUB8rm: 3380 case X86::SUB64rr: 3381 case X86::SUB32rr: 3382 case X86::SUB16rr: 3383 case X86::SUB8rr: { 3384 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg())) 3385 return false; 3386 // There is no use of the destination register, we can replace SUB with CMP. 3387 switch (CmpInstr->getOpcode()) { 3388 default: llvm_unreachable("Unreachable!"); 3389 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 3390 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 3391 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 3392 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 3393 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 3394 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 3395 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 3396 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 3397 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; 3398 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break; 3399 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break; 3400 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break; 3401 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break; 3402 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break; 3403 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break; 3404 } 3405 CmpInstr->setDesc(get(NewOpcode)); 3406 CmpInstr->RemoveOperand(0); 3407 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri. 3408 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || 3409 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm) 3410 return false; 3411 } 3412 } 3413 3414 // Get the unique definition of SrcReg. 3415 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 3416 if (!MI) return false; 3417 3418 // CmpInstr is the first instruction of the BB. 3419 MachineBasicBlock::iterator I = CmpInstr, Def = MI; 3420 3421 // If we are comparing against zero, check whether we can use MI to update 3422 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize. 3423 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0); 3424 if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() || 3425 !isDefConvertible(MI))) 3426 return false; 3427 3428 // We are searching for an earlier instruction that can make CmpInstr 3429 // redundant and that instruction will be saved in Sub. 3430 MachineInstr *Sub = NULL; 3431 const TargetRegisterInfo *TRI = &getRegisterInfo(); 3432 3433 // We iterate backward, starting from the instruction before CmpInstr and 3434 // stop when reaching the definition of a source register or done with the BB. 3435 // RI points to the instruction before CmpInstr. 3436 // If the definition is in this basic block, RE points to the definition; 3437 // otherwise, RE is the rend of the basic block. 3438 MachineBasicBlock::reverse_iterator 3439 RI = MachineBasicBlock::reverse_iterator(I), 3440 RE = CmpInstr->getParent() == MI->getParent() ? 3441 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ : 3442 CmpInstr->getParent()->rend(); 3443 MachineInstr *Movr0Inst = 0; 3444 for (; RI != RE; ++RI) { 3445 MachineInstr *Instr = &*RI; 3446 // Check whether CmpInstr can be made redundant by the current instruction. 3447 if (!IsCmpZero && 3448 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) { 3449 Sub = Instr; 3450 break; 3451 } 3452 3453 if (Instr->modifiesRegister(X86::EFLAGS, TRI) || 3454 Instr->readsRegister(X86::EFLAGS, TRI)) { 3455 // This instruction modifies or uses EFLAGS. 3456 3457 // MOV32r0 etc. are implemented with xor which clobbers condition code. 3458 // They are safe to move up, if the definition to EFLAGS is dead and 3459 // earlier instructions do not read or write EFLAGS. 3460 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 && 3461 Instr->registerDefIsDead(X86::EFLAGS, TRI)) { 3462 Movr0Inst = Instr; 3463 continue; 3464 } 3465 3466 // We can't remove CmpInstr. 3467 return false; 3468 } 3469 } 3470 3471 // Return false if no candidates exist. 3472 if (!IsCmpZero && !Sub) 3473 return false; 3474 3475 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 3476 Sub->getOperand(2).getReg() == SrcReg); 3477 3478 // Scan forward from the instruction after CmpInstr for uses of EFLAGS. 3479 // It is safe to remove CmpInstr if EFLAGS is redefined or killed. 3480 // If we are done with the basic block, we need to check whether EFLAGS is 3481 // live-out. 3482 bool IsSafe = false; 3483 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate; 3484 MachineBasicBlock::iterator E = CmpInstr->getParent()->end(); 3485 for (++I; I != E; ++I) { 3486 const MachineInstr &Instr = *I; 3487 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI); 3488 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI); 3489 // We should check the usage if this instruction uses and updates EFLAGS. 3490 if (!UseEFLAGS && ModifyEFLAGS) { 3491 // It is safe to remove CmpInstr if EFLAGS is updated again. 3492 IsSafe = true; 3493 break; 3494 } 3495 if (!UseEFLAGS && !ModifyEFLAGS) 3496 continue; 3497 3498 // EFLAGS is used by this instruction. 3499 X86::CondCode OldCC; 3500 bool OpcIsSET = false; 3501 if (IsCmpZero || IsSwapped) { 3502 // We decode the condition code from opcode. 3503 if (Instr.isBranch()) 3504 OldCC = getCondFromBranchOpc(Instr.getOpcode()); 3505 else { 3506 OldCC = getCondFromSETOpc(Instr.getOpcode()); 3507 if (OldCC != X86::COND_INVALID) 3508 OpcIsSET = true; 3509 else 3510 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode()); 3511 } 3512 if (OldCC == X86::COND_INVALID) return false; 3513 } 3514 if (IsCmpZero) { 3515 switch (OldCC) { 3516 default: break; 3517 case X86::COND_A: case X86::COND_AE: 3518 case X86::COND_B: case X86::COND_BE: 3519 case X86::COND_G: case X86::COND_GE: 3520 case X86::COND_L: case X86::COND_LE: 3521 case X86::COND_O: case X86::COND_NO: 3522 // CF and OF are used, we can't perform this optimization. 3523 return false; 3524 } 3525 } else if (IsSwapped) { 3526 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs 3527 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 3528 // We swap the condition code and synthesize the new opcode. 3529 X86::CondCode NewCC = getSwappedCondition(OldCC); 3530 if (NewCC == X86::COND_INVALID) return false; 3531 3532 // Synthesize the new opcode. 3533 bool HasMemoryOperand = Instr.hasOneMemOperand(); 3534 unsigned NewOpc; 3535 if (Instr.isBranch()) 3536 NewOpc = GetCondBranchFromCond(NewCC); 3537 else if(OpcIsSET) 3538 NewOpc = getSETFromCond(NewCC, HasMemoryOperand); 3539 else { 3540 unsigned DstReg = Instr.getOperand(0).getReg(); 3541 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), 3542 HasMemoryOperand); 3543 } 3544 3545 // Push the MachineInstr to OpsToUpdate. 3546 // If it is safe to remove CmpInstr, the condition code of these 3547 // instructions will be modified. 3548 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); 3549 } 3550 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) { 3551 // It is safe to remove CmpInstr if EFLAGS is updated again or killed. 3552 IsSafe = true; 3553 break; 3554 } 3555 } 3556 3557 // If EFLAGS is not killed nor re-defined, we should check whether it is 3558 // live-out. If it is live-out, do not optimize. 3559 if ((IsCmpZero || IsSwapped) && !IsSafe) { 3560 MachineBasicBlock *MBB = CmpInstr->getParent(); 3561 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 3562 SE = MBB->succ_end(); SI != SE; ++SI) 3563 if ((*SI)->isLiveIn(X86::EFLAGS)) 3564 return false; 3565 } 3566 3567 // The instruction to be updated is either Sub or MI. 3568 Sub = IsCmpZero ? MI : Sub; 3569 // Move Movr0Inst to the appropriate place before Sub. 3570 if (Movr0Inst) { 3571 // Look backwards until we find a def that doesn't use the current EFLAGS. 3572 Def = Sub; 3573 MachineBasicBlock::reverse_iterator 3574 InsertI = MachineBasicBlock::reverse_iterator(++Def), 3575 InsertE = Sub->getParent()->rend(); 3576 for (; InsertI != InsertE; ++InsertI) { 3577 MachineInstr *Instr = &*InsertI; 3578 if (!Instr->readsRegister(X86::EFLAGS, TRI) && 3579 Instr->modifiesRegister(X86::EFLAGS, TRI)) { 3580 Sub->getParent()->remove(Movr0Inst); 3581 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr), 3582 Movr0Inst); 3583 break; 3584 } 3585 } 3586 if (InsertI == InsertE) 3587 return false; 3588 } 3589 3590 // Make sure Sub instruction defines EFLAGS and mark the def live. 3591 unsigned i = 0, e = Sub->getNumOperands(); 3592 for (; i != e; ++i) { 3593 MachineOperand &MO = Sub->getOperand(i); 3594 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) { 3595 MO.setIsDead(false); 3596 break; 3597 } 3598 } 3599 assert(i != e && "Unable to locate a def EFLAGS operand"); 3600 3601 CmpInstr->eraseFromParent(); 3602 3603 // Modify the condition code of instructions in OpsToUpdate. 3604 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++) 3605 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second)); 3606 return true; 3607 } 3608 3609 /// optimizeLoadInstr - Try to remove the load by folding it to a register 3610 /// operand at the use. We fold the load instructions if load defines a virtual 3611 /// register, the virtual register is used once in the same BB, and the 3612 /// instructions in-between do not load or store, and have no side effects. 3613 MachineInstr* X86InstrInfo:: 3614 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, 3615 unsigned &FoldAsLoadDefReg, 3616 MachineInstr *&DefMI) const { 3617 if (FoldAsLoadDefReg == 0) 3618 return 0; 3619 // To be conservative, if there exists another load, clear the load candidate. 3620 if (MI->mayLoad()) { 3621 FoldAsLoadDefReg = 0; 3622 return 0; 3623 } 3624 3625 // Check whether we can move DefMI here. 3626 DefMI = MRI->getVRegDef(FoldAsLoadDefReg); 3627 assert(DefMI); 3628 bool SawStore = false; 3629 if (!DefMI->isSafeToMove(this, 0, SawStore)) 3630 return 0; 3631 3632 // We try to commute MI if possible. 3633 unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1; 3634 for (unsigned Idx = 0; Idx < IdxEnd; Idx++) { 3635 // Collect information about virtual register operands of MI. 3636 unsigned SrcOperandId = 0; 3637 bool FoundSrcOperand = false; 3638 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { 3639 MachineOperand &MO = MI->getOperand(i); 3640 if (!MO.isReg()) 3641 continue; 3642 unsigned Reg = MO.getReg(); 3643 if (Reg != FoldAsLoadDefReg) 3644 continue; 3645 // Do not fold if we have a subreg use or a def or multiple uses. 3646 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand) 3647 return 0; 3648 3649 SrcOperandId = i; 3650 FoundSrcOperand = true; 3651 } 3652 if (!FoundSrcOperand) return 0; 3653 3654 // Check whether we can fold the def into SrcOperandId. 3655 SmallVector<unsigned, 8> Ops; 3656 Ops.push_back(SrcOperandId); 3657 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI); 3658 if (FoldMI) { 3659 FoldAsLoadDefReg = 0; 3660 return FoldMI; 3661 } 3662 3663 if (Idx == 1) { 3664 // MI was changed but it didn't help, commute it back! 3665 commuteInstruction(MI, false); 3666 return 0; 3667 } 3668 3669 // Check whether we can commute MI and enable folding. 3670 if (MI->isCommutable()) { 3671 MachineInstr *NewMI = commuteInstruction(MI, false); 3672 // Unable to commute. 3673 if (!NewMI) return 0; 3674 if (NewMI != MI) { 3675 // New instruction. It doesn't need to be kept. 3676 NewMI->eraseFromParent(); 3677 return 0; 3678 } 3679 } 3680 } 3681 return 0; 3682 } 3683 3684 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr 3685 /// instruction with two undef reads of the register being defined. This is 3686 /// used for mapping: 3687 /// %xmm4 = V_SET0 3688 /// to: 3689 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef> 3690 /// 3691 static bool Expand2AddrUndef(MachineInstrBuilder &MIB, 3692 const MCInstrDesc &Desc) { 3693 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); 3694 unsigned Reg = MIB->getOperand(0).getReg(); 3695 MIB->setDesc(Desc); 3696 3697 // MachineInstr::addOperand() will insert explicit operands before any 3698 // implicit operands. 3699 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 3700 // But we don't trust that. 3701 assert(MIB->getOperand(1).getReg() == Reg && 3702 MIB->getOperand(2).getReg() == Reg && "Misplaced operand"); 3703 return true; 3704 } 3705 3706 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 3707 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 3708 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 3709 switch (MI->getOpcode()) { 3710 case X86::SETB_C8r: 3711 return Expand2AddrUndef(MIB, get(X86::SBB8rr)); 3712 case X86::SETB_C16r: 3713 return Expand2AddrUndef(MIB, get(X86::SBB16rr)); 3714 case X86::SETB_C32r: 3715 return Expand2AddrUndef(MIB, get(X86::SBB32rr)); 3716 case X86::SETB_C64r: 3717 return Expand2AddrUndef(MIB, get(X86::SBB64rr)); 3718 case X86::V_SET0: 3719 case X86::FsFLD0SS: 3720 case X86::FsFLD0SD: 3721 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); 3722 case X86::AVX_SET0: 3723 assert(HasAVX && "AVX not supported"); 3724 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr)); 3725 case X86::V_SETALLONES: 3726 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); 3727 case X86::AVX2_SETALLONES: 3728 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr)); 3729 case X86::TEST8ri_NOREX: 3730 MI->setDesc(get(X86::TEST8ri)); 3731 return true; 3732 } 3733 return false; 3734 } 3735 3736 MachineInstr* 3737 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 3738 int FrameIx, uint64_t Offset, 3739 const MDNode *MDPtr, 3740 DebugLoc DL) const { 3741 X86AddressMode AM; 3742 AM.BaseType = X86AddressMode::FrameIndexBase; 3743 AM.Base.FrameIndex = FrameIx; 3744 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); 3745 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr); 3746 return &*MIB; 3747 } 3748 3749 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 3750 const SmallVectorImpl<MachineOperand> &MOs, 3751 MachineInstr *MI, 3752 const TargetInstrInfo &TII) { 3753 // Create the base instruction with the memory operand as the first part. 3754 // Omit the implicit operands, something BuildMI can't do. 3755 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 3756 MI->getDebugLoc(), true); 3757 MachineInstrBuilder MIB(MF, NewMI); 3758 unsigned NumAddrOps = MOs.size(); 3759 for (unsigned i = 0; i != NumAddrOps; ++i) 3760 MIB.addOperand(MOs[i]); 3761 if (NumAddrOps < 4) // FrameIndex only 3762 addOffset(MIB, 0); 3763 3764 // Loop over the rest of the ri operands, converting them over. 3765 unsigned NumOps = MI->getDesc().getNumOperands()-2; 3766 for (unsigned i = 0; i != NumOps; ++i) { 3767 MachineOperand &MO = MI->getOperand(i+2); 3768 MIB.addOperand(MO); 3769 } 3770 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 3771 MachineOperand &MO = MI->getOperand(i); 3772 MIB.addOperand(MO); 3773 } 3774 return MIB; 3775 } 3776 3777 static MachineInstr *FuseInst(MachineFunction &MF, 3778 unsigned Opcode, unsigned OpNo, 3779 const SmallVectorImpl<MachineOperand> &MOs, 3780 MachineInstr *MI, const TargetInstrInfo &TII) { 3781 // Omit the implicit operands, something BuildMI can't do. 3782 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 3783 MI->getDebugLoc(), true); 3784 MachineInstrBuilder MIB(MF, NewMI); 3785 3786 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 3787 MachineOperand &MO = MI->getOperand(i); 3788 if (i == OpNo) { 3789 assert(MO.isReg() && "Expected to fold into reg operand!"); 3790 unsigned NumAddrOps = MOs.size(); 3791 for (unsigned i = 0; i != NumAddrOps; ++i) 3792 MIB.addOperand(MOs[i]); 3793 if (NumAddrOps < 4) // FrameIndex only 3794 addOffset(MIB, 0); 3795 } else { 3796 MIB.addOperand(MO); 3797 } 3798 } 3799 return MIB; 3800 } 3801 3802 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 3803 const SmallVectorImpl<MachineOperand> &MOs, 3804 MachineInstr *MI) { 3805 MachineFunction &MF = *MI->getParent()->getParent(); 3806 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 3807 3808 unsigned NumAddrOps = MOs.size(); 3809 for (unsigned i = 0; i != NumAddrOps; ++i) 3810 MIB.addOperand(MOs[i]); 3811 if (NumAddrOps < 4) // FrameIndex only 3812 addOffset(MIB, 0); 3813 return MIB.addImm(0); 3814 } 3815 3816 MachineInstr* 3817 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3818 MachineInstr *MI, unsigned i, 3819 const SmallVectorImpl<MachineOperand> &MOs, 3820 unsigned Size, unsigned Align) const { 3821 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 3822 bool isCallRegIndirect = TM.getSubtarget<X86Subtarget>().callRegIndirect(); 3823 bool isTwoAddrFold = false; 3824 3825 // Atom favors register form of call. So, we do not fold loads into calls 3826 // when X86Subtarget is Atom. 3827 if (isCallRegIndirect && 3828 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) { 3829 return NULL; 3830 } 3831 3832 unsigned NumOps = MI->getDesc().getNumOperands(); 3833 bool isTwoAddr = NumOps > 1 && 3834 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 3835 3836 // FIXME: AsmPrinter doesn't know how to handle 3837 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 3838 if (MI->getOpcode() == X86::ADD32ri && 3839 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 3840 return NULL; 3841 3842 MachineInstr *NewMI = NULL; 3843 // Folding a memory location into the two-address part of a two-address 3844 // instruction is different than folding it other places. It requires 3845 // replacing the *two* registers with the memory location. 3846 if (isTwoAddr && NumOps >= 2 && i < 2 && 3847 MI->getOperand(0).isReg() && 3848 MI->getOperand(1).isReg() && 3849 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 3850 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 3851 isTwoAddrFold = true; 3852 } else if (i == 0) { // If operand 0 3853 if (MI->getOpcode() == X86::MOV32r0) { 3854 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 3855 if (NewMI) 3856 return NewMI; 3857 } 3858 3859 OpcodeTablePtr = &RegOp2MemOpTable0; 3860 } else if (i == 1) { 3861 OpcodeTablePtr = &RegOp2MemOpTable1; 3862 } else if (i == 2) { 3863 OpcodeTablePtr = &RegOp2MemOpTable2; 3864 } else if (i == 3) { 3865 OpcodeTablePtr = &RegOp2MemOpTable3; 3866 } 3867 3868 // If table selected... 3869 if (OpcodeTablePtr) { 3870 // Find the Opcode to fuse 3871 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 3872 OpcodeTablePtr->find(MI->getOpcode()); 3873 if (I != OpcodeTablePtr->end()) { 3874 unsigned Opcode = I->second.first; 3875 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT; 3876 if (Align < MinAlign) 3877 return NULL; 3878 bool NarrowToMOV32rm = false; 3879 if (Size) { 3880 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize(); 3881 if (Size < RCSize) { 3882 // Check if it's safe to fold the load. If the size of the object is 3883 // narrower than the load width, then it's not. 3884 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 3885 return NULL; 3886 // If this is a 64-bit load, but the spill slot is 32, then we can do 3887 // a 32-bit load which is implicitly zero-extended. This likely is due 3888 // to liveintervalanalysis remat'ing a load from stack slot. 3889 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 3890 return NULL; 3891 Opcode = X86::MOV32rm; 3892 NarrowToMOV32rm = true; 3893 } 3894 } 3895 3896 if (isTwoAddrFold) 3897 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 3898 else 3899 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 3900 3901 if (NarrowToMOV32rm) { 3902 // If this is the special case where we use a MOV32rm to load a 32-bit 3903 // value and zero-extend the top bits. Change the destination register 3904 // to a 32-bit one. 3905 unsigned DstReg = NewMI->getOperand(0).getReg(); 3906 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 3907 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 3908 X86::sub_32bit)); 3909 else 3910 NewMI->getOperand(0).setSubReg(X86::sub_32bit); 3911 } 3912 return NewMI; 3913 } 3914 } 3915 3916 // No fusion 3917 if (PrintFailedFusing && !MI->isCopy()) 3918 dbgs() << "We failed to fuse operand " << i << " in " << *MI; 3919 return NULL; 3920 } 3921 3922 /// hasPartialRegUpdate - Return true for all instructions that only update 3923 /// the first 32 or 64-bits of the destination register and leave the rest 3924 /// unmodified. This can be used to avoid folding loads if the instructions 3925 /// only update part of the destination register, and the non-updated part is 3926 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these 3927 /// instructions breaks the partial register dependency and it can improve 3928 /// performance. e.g.: 3929 /// 3930 /// movss (%rdi), %xmm0 3931 /// cvtss2sd %xmm0, %xmm0 3932 /// 3933 /// Instead of 3934 /// cvtss2sd (%rdi), %xmm0 3935 /// 3936 /// FIXME: This should be turned into a TSFlags. 3937 /// 3938 static bool hasPartialRegUpdate(unsigned Opcode) { 3939 switch (Opcode) { 3940 case X86::CVTSI2SSrr: 3941 case X86::CVTSI2SS64rr: 3942 case X86::CVTSI2SDrr: 3943 case X86::CVTSI2SD64rr: 3944 case X86::CVTSD2SSrr: 3945 case X86::Int_CVTSD2SSrr: 3946 case X86::CVTSS2SDrr: 3947 case X86::Int_CVTSS2SDrr: 3948 case X86::RCPSSr: 3949 case X86::RCPSSr_Int: 3950 case X86::ROUNDSDr: 3951 case X86::ROUNDSDr_Int: 3952 case X86::ROUNDSSr: 3953 case X86::ROUNDSSr_Int: 3954 case X86::RSQRTSSr: 3955 case X86::RSQRTSSr_Int: 3956 case X86::SQRTSSr: 3957 case X86::SQRTSSr_Int: 3958 // AVX encoded versions 3959 case X86::VCVTSD2SSrr: 3960 case X86::Int_VCVTSD2SSrr: 3961 case X86::VCVTSS2SDrr: 3962 case X86::Int_VCVTSS2SDrr: 3963 case X86::VRCPSSr: 3964 case X86::VROUNDSDr: 3965 case X86::VROUNDSDr_Int: 3966 case X86::VROUNDSSr: 3967 case X86::VROUNDSSr_Int: 3968 case X86::VRSQRTSSr: 3969 case X86::VSQRTSSr: 3970 return true; 3971 } 3972 3973 return false; 3974 } 3975 3976 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle 3977 /// instructions we would like before a partial register update. 3978 unsigned X86InstrInfo:: 3979 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 3980 const TargetRegisterInfo *TRI) const { 3981 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode())) 3982 return 0; 3983 3984 // If MI is marked as reading Reg, the partial register update is wanted. 3985 const MachineOperand &MO = MI->getOperand(0); 3986 unsigned Reg = MO.getReg(); 3987 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 3988 if (MO.readsReg() || MI->readsVirtualRegister(Reg)) 3989 return 0; 3990 } else { 3991 if (MI->readsRegister(Reg, TRI)) 3992 return 0; 3993 } 3994 3995 // If any of the preceding 16 instructions are reading Reg, insert a 3996 // dependency breaking instruction. The magic number is based on a few 3997 // Nehalem experiments. 3998 return 16; 3999 } 4000 4001 void X86InstrInfo:: 4002 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 4003 const TargetRegisterInfo *TRI) const { 4004 unsigned Reg = MI->getOperand(OpNum).getReg(); 4005 if (X86::VR128RegClass.contains(Reg)) { 4006 // These instructions are all floating point domain, so xorps is the best 4007 // choice. 4008 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 4009 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr; 4010 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg) 4011 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 4012 } else if (X86::VR256RegClass.contains(Reg)) { 4013 // Use vxorps to clear the full ymm register. 4014 // It wants to read and write the xmm sub-register. 4015 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm); 4016 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg) 4017 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef) 4018 .addReg(Reg, RegState::ImplicitDefine); 4019 } else 4020 return; 4021 MI->addRegisterKilled(Reg, TRI, true); 4022 } 4023 4024 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 4025 MachineInstr *MI, 4026 const SmallVectorImpl<unsigned> &Ops, 4027 int FrameIndex) const { 4028 // Check switch flag 4029 if (NoFusing) return NULL; 4030 4031 // Unless optimizing for size, don't fold to avoid partial 4032 // register update stalls 4033 if (!MF.getFunction()->getAttributes(). 4034 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) && 4035 hasPartialRegUpdate(MI->getOpcode())) 4036 return 0; 4037 4038 const MachineFrameInfo *MFI = MF.getFrameInfo(); 4039 unsigned Size = MFI->getObjectSize(FrameIndex); 4040 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 4041 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 4042 unsigned NewOpc = 0; 4043 unsigned RCSize = 0; 4044 switch (MI->getOpcode()) { 4045 default: return NULL; 4046 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 4047 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 4048 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 4049 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 4050 } 4051 // Check if it's safe to fold the load. If the size of the object is 4052 // narrower than the load width, then it's not. 4053 if (Size < RCSize) 4054 return NULL; 4055 // Change to CMPXXri r, 0 first. 4056 MI->setDesc(get(NewOpc)); 4057 MI->getOperand(1).ChangeToImmediate(0); 4058 } else if (Ops.size() != 1) 4059 return NULL; 4060 4061 SmallVector<MachineOperand,4> MOs; 4062 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 4063 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 4064 } 4065 4066 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 4067 MachineInstr *MI, 4068 const SmallVectorImpl<unsigned> &Ops, 4069 MachineInstr *LoadMI) const { 4070 // Check switch flag 4071 if (NoFusing) return NULL; 4072 4073 // Unless optimizing for size, don't fold to avoid partial 4074 // register update stalls 4075 if (!MF.getFunction()->getAttributes(). 4076 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) && 4077 hasPartialRegUpdate(MI->getOpcode())) 4078 return 0; 4079 4080 // Determine the alignment of the load. 4081 unsigned Alignment = 0; 4082 if (LoadMI->hasOneMemOperand()) 4083 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 4084 else 4085 switch (LoadMI->getOpcode()) { 4086 case X86::AVX2_SETALLONES: 4087 case X86::AVX_SET0: 4088 Alignment = 32; 4089 break; 4090 case X86::V_SET0: 4091 case X86::V_SETALLONES: 4092 Alignment = 16; 4093 break; 4094 case X86::FsFLD0SD: 4095 Alignment = 8; 4096 break; 4097 case X86::FsFLD0SS: 4098 Alignment = 4; 4099 break; 4100 default: 4101 return 0; 4102 } 4103 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 4104 unsigned NewOpc = 0; 4105 switch (MI->getOpcode()) { 4106 default: return NULL; 4107 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 4108 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 4109 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 4110 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 4111 } 4112 // Change to CMPXXri r, 0 first. 4113 MI->setDesc(get(NewOpc)); 4114 MI->getOperand(1).ChangeToImmediate(0); 4115 } else if (Ops.size() != 1) 4116 return NULL; 4117 4118 // Make sure the subregisters match. 4119 // Otherwise we risk changing the size of the load. 4120 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg()) 4121 return NULL; 4122 4123 SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 4124 switch (LoadMI->getOpcode()) { 4125 case X86::V_SET0: 4126 case X86::V_SETALLONES: 4127 case X86::AVX2_SETALLONES: 4128 case X86::AVX_SET0: 4129 case X86::FsFLD0SD: 4130 case X86::FsFLD0SS: { 4131 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 4132 // Create a constant-pool entry and operands to load from it. 4133 4134 // Medium and large mode can't fold loads this way. 4135 if (TM.getCodeModel() != CodeModel::Small && 4136 TM.getCodeModel() != CodeModel::Kernel) 4137 return NULL; 4138 4139 // x86-32 PIC requires a PIC base register for constant pools. 4140 unsigned PICBase = 0; 4141 if (TM.getRelocationModel() == Reloc::PIC_) { 4142 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 4143 PICBase = X86::RIP; 4144 else 4145 // FIXME: PICBase = getGlobalBaseReg(&MF); 4146 // This doesn't work for several reasons. 4147 // 1. GlobalBaseReg may have been spilled. 4148 // 2. It may not be live at MI. 4149 return NULL; 4150 } 4151 4152 // Create a constant-pool entry. 4153 MachineConstantPool &MCP = *MF.getConstantPool(); 4154 Type *Ty; 4155 unsigned Opc = LoadMI->getOpcode(); 4156 if (Opc == X86::FsFLD0SS) 4157 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 4158 else if (Opc == X86::FsFLD0SD) 4159 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 4160 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0) 4161 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8); 4162 else 4163 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 4164 4165 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES); 4166 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) : 4167 Constant::getNullValue(Ty); 4168 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 4169 4170 // Create operands to load from the constant pool entry. 4171 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 4172 MOs.push_back(MachineOperand::CreateImm(1)); 4173 MOs.push_back(MachineOperand::CreateReg(0, false)); 4174 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 4175 MOs.push_back(MachineOperand::CreateReg(0, false)); 4176 break; 4177 } 4178 default: { 4179 if ((LoadMI->getOpcode() == X86::MOVSSrm || 4180 LoadMI->getOpcode() == X86::VMOVSSrm) && 4181 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize() 4182 > 4) 4183 // These instructions only load 32 bits, we can't fold them if the 4184 // destination register is wider than 32 bits (4 bytes). 4185 return NULL; 4186 if ((LoadMI->getOpcode() == X86::MOVSDrm || 4187 LoadMI->getOpcode() == X86::VMOVSDrm) && 4188 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize() 4189 > 8) 4190 // These instructions only load 64 bits, we can't fold them if the 4191 // destination register is wider than 64 bits (8 bytes). 4192 return NULL; 4193 4194 // Folding a normal load. Just copy the load's address operands. 4195 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 4196 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i) 4197 MOs.push_back(LoadMI->getOperand(i)); 4198 break; 4199 } 4200 } 4201 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 4202 } 4203 4204 4205 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 4206 const SmallVectorImpl<unsigned> &Ops) const { 4207 // Check switch flag 4208 if (NoFusing) return 0; 4209 4210 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 4211 switch (MI->getOpcode()) { 4212 default: return false; 4213 case X86::TEST8rr: 4214 case X86::TEST16rr: 4215 case X86::TEST32rr: 4216 case X86::TEST64rr: 4217 return true; 4218 case X86::ADD32ri: 4219 // FIXME: AsmPrinter doesn't know how to handle 4220 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 4221 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 4222 return false; 4223 break; 4224 } 4225 } 4226 4227 if (Ops.size() != 1) 4228 return false; 4229 4230 unsigned OpNum = Ops[0]; 4231 unsigned Opc = MI->getOpcode(); 4232 unsigned NumOps = MI->getDesc().getNumOperands(); 4233 bool isTwoAddr = NumOps > 1 && 4234 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 4235 4236 // Folding a memory location into the two-address part of a two-address 4237 // instruction is different than folding it other places. It requires 4238 // replacing the *two* registers with the memory location. 4239 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 4240 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 4241 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 4242 } else if (OpNum == 0) { // If operand 0 4243 if (Opc == X86::MOV32r0) 4244 return true; 4245 4246 OpcodeTablePtr = &RegOp2MemOpTable0; 4247 } else if (OpNum == 1) { 4248 OpcodeTablePtr = &RegOp2MemOpTable1; 4249 } else if (OpNum == 2) { 4250 OpcodeTablePtr = &RegOp2MemOpTable2; 4251 } else if (OpNum == 3) { 4252 OpcodeTablePtr = &RegOp2MemOpTable3; 4253 } 4254 4255 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc)) 4256 return true; 4257 return TargetInstrInfo::canFoldMemoryOperand(MI, Ops); 4258 } 4259 4260 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 4261 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 4262 SmallVectorImpl<MachineInstr*> &NewMIs) const { 4263 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4264 MemOp2RegOpTable.find(MI->getOpcode()); 4265 if (I == MemOp2RegOpTable.end()) 4266 return false; 4267 unsigned Opc = I->second.first; 4268 unsigned Index = I->second.second & TB_INDEX_MASK; 4269 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4270 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4271 if (UnfoldLoad && !FoldedLoad) 4272 return false; 4273 UnfoldLoad &= FoldedLoad; 4274 if (UnfoldStore && !FoldedStore) 4275 return false; 4276 UnfoldStore &= FoldedStore; 4277 4278 const MCInstrDesc &MCID = get(Opc); 4279 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4280 if (!MI->hasOneMemOperand() && 4281 RC == &X86::VR128RegClass && 4282 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4283 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 4284 // conservatively assume the address is unaligned. That's bad for 4285 // performance. 4286 return false; 4287 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 4288 SmallVector<MachineOperand,2> BeforeOps; 4289 SmallVector<MachineOperand,2> AfterOps; 4290 SmallVector<MachineOperand,4> ImpOps; 4291 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 4292 MachineOperand &Op = MI->getOperand(i); 4293 if (i >= Index && i < Index + X86::AddrNumOperands) 4294 AddrOps.push_back(Op); 4295 else if (Op.isReg() && Op.isImplicit()) 4296 ImpOps.push_back(Op); 4297 else if (i < Index) 4298 BeforeOps.push_back(Op); 4299 else if (i > Index) 4300 AfterOps.push_back(Op); 4301 } 4302 4303 // Emit the load instruction. 4304 if (UnfoldLoad) { 4305 std::pair<MachineInstr::mmo_iterator, 4306 MachineInstr::mmo_iterator> MMOs = 4307 MF.extractLoadMemRefs(MI->memoperands_begin(), 4308 MI->memoperands_end()); 4309 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 4310 if (UnfoldStore) { 4311 // Address operands cannot be marked isKill. 4312 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 4313 MachineOperand &MO = NewMIs[0]->getOperand(i); 4314 if (MO.isReg()) 4315 MO.setIsKill(false); 4316 } 4317 } 4318 } 4319 4320 // Emit the data processing instruction. 4321 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true); 4322 MachineInstrBuilder MIB(MF, DataMI); 4323 4324 if (FoldedStore) 4325 MIB.addReg(Reg, RegState::Define); 4326 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 4327 MIB.addOperand(BeforeOps[i]); 4328 if (FoldedLoad) 4329 MIB.addReg(Reg); 4330 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 4331 MIB.addOperand(AfterOps[i]); 4332 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 4333 MachineOperand &MO = ImpOps[i]; 4334 MIB.addReg(MO.getReg(), 4335 getDefRegState(MO.isDef()) | 4336 RegState::Implicit | 4337 getKillRegState(MO.isKill()) | 4338 getDeadRegState(MO.isDead()) | 4339 getUndefRegState(MO.isUndef())); 4340 } 4341 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 4342 switch (DataMI->getOpcode()) { 4343 default: break; 4344 case X86::CMP64ri32: 4345 case X86::CMP64ri8: 4346 case X86::CMP32ri: 4347 case X86::CMP32ri8: 4348 case X86::CMP16ri: 4349 case X86::CMP16ri8: 4350 case X86::CMP8ri: { 4351 MachineOperand &MO0 = DataMI->getOperand(0); 4352 MachineOperand &MO1 = DataMI->getOperand(1); 4353 if (MO1.getImm() == 0) { 4354 unsigned NewOpc; 4355 switch (DataMI->getOpcode()) { 4356 default: llvm_unreachable("Unreachable!"); 4357 case X86::CMP64ri8: 4358 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 4359 case X86::CMP32ri8: 4360 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 4361 case X86::CMP16ri8: 4362 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 4363 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 4364 } 4365 DataMI->setDesc(get(NewOpc)); 4366 MO1.ChangeToRegister(MO0.getReg(), false); 4367 } 4368 } 4369 } 4370 NewMIs.push_back(DataMI); 4371 4372 // Emit the store instruction. 4373 if (UnfoldStore) { 4374 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); 4375 std::pair<MachineInstr::mmo_iterator, 4376 MachineInstr::mmo_iterator> MMOs = 4377 MF.extractStoreMemRefs(MI->memoperands_begin(), 4378 MI->memoperands_end()); 4379 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 4380 } 4381 4382 return true; 4383 } 4384 4385 bool 4386 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 4387 SmallVectorImpl<SDNode*> &NewNodes) const { 4388 if (!N->isMachineOpcode()) 4389 return false; 4390 4391 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4392 MemOp2RegOpTable.find(N->getMachineOpcode()); 4393 if (I == MemOp2RegOpTable.end()) 4394 return false; 4395 unsigned Opc = I->second.first; 4396 unsigned Index = I->second.second & TB_INDEX_MASK; 4397 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4398 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4399 const MCInstrDesc &MCID = get(Opc); 4400 MachineFunction &MF = DAG.getMachineFunction(); 4401 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4402 unsigned NumDefs = MCID.NumDefs; 4403 std::vector<SDValue> AddrOps; 4404 std::vector<SDValue> BeforeOps; 4405 std::vector<SDValue> AfterOps; 4406 SDLoc dl(N); 4407 unsigned NumOps = N->getNumOperands(); 4408 for (unsigned i = 0; i != NumOps-1; ++i) { 4409 SDValue Op = N->getOperand(i); 4410 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 4411 AddrOps.push_back(Op); 4412 else if (i < Index-NumDefs) 4413 BeforeOps.push_back(Op); 4414 else if (i > Index-NumDefs) 4415 AfterOps.push_back(Op); 4416 } 4417 SDValue Chain = N->getOperand(NumOps-1); 4418 AddrOps.push_back(Chain); 4419 4420 // Emit the load instruction. 4421 SDNode *Load = 0; 4422 if (FoldedLoad) { 4423 EVT VT = *RC->vt_begin(); 4424 std::pair<MachineInstr::mmo_iterator, 4425 MachineInstr::mmo_iterator> MMOs = 4426 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4427 cast<MachineSDNode>(N)->memoperands_end()); 4428 if (!(*MMOs.first) && 4429 RC == &X86::VR128RegClass && 4430 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4431 // Do not introduce a slow unaligned load. 4432 return false; 4433 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4434 bool isAligned = (*MMOs.first) && 4435 (*MMOs.first)->getAlignment() >= Alignment; 4436 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, 4437 VT, MVT::Other, AddrOps); 4438 NewNodes.push_back(Load); 4439 4440 // Preserve memory reference information. 4441 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4442 } 4443 4444 // Emit the data processing instruction. 4445 std::vector<EVT> VTs; 4446 const TargetRegisterClass *DstRC = 0; 4447 if (MCID.getNumDefs() > 0) { 4448 DstRC = getRegClass(MCID, 0, &RI, MF); 4449 VTs.push_back(*DstRC->vt_begin()); 4450 } 4451 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 4452 EVT VT = N->getValueType(i); 4453 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) 4454 VTs.push_back(VT); 4455 } 4456 if (Load) 4457 BeforeOps.push_back(SDValue(Load, 0)); 4458 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 4459 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps); 4460 NewNodes.push_back(NewNode); 4461 4462 // Emit the store instruction. 4463 if (FoldedStore) { 4464 AddrOps.pop_back(); 4465 AddrOps.push_back(SDValue(NewNode, 0)); 4466 AddrOps.push_back(Chain); 4467 std::pair<MachineInstr::mmo_iterator, 4468 MachineInstr::mmo_iterator> MMOs = 4469 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4470 cast<MachineSDNode>(N)->memoperands_end()); 4471 if (!(*MMOs.first) && 4472 RC == &X86::VR128RegClass && 4473 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4474 // Do not introduce a slow unaligned store. 4475 return false; 4476 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4477 bool isAligned = (*MMOs.first) && 4478 (*MMOs.first)->getAlignment() >= Alignment; 4479 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, 4480 isAligned, TM), 4481 dl, MVT::Other, AddrOps); 4482 NewNodes.push_back(Store); 4483 4484 // Preserve memory reference information. 4485 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4486 } 4487 4488 return true; 4489 } 4490 4491 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 4492 bool UnfoldLoad, bool UnfoldStore, 4493 unsigned *LoadRegIndex) const { 4494 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4495 MemOp2RegOpTable.find(Opc); 4496 if (I == MemOp2RegOpTable.end()) 4497 return 0; 4498 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4499 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4500 if (UnfoldLoad && !FoldedLoad) 4501 return 0; 4502 if (UnfoldStore && !FoldedStore) 4503 return 0; 4504 if (LoadRegIndex) 4505 *LoadRegIndex = I->second.second & TB_INDEX_MASK; 4506 return I->second.first; 4507 } 4508 4509 bool 4510 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 4511 int64_t &Offset1, int64_t &Offset2) const { 4512 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 4513 return false; 4514 unsigned Opc1 = Load1->getMachineOpcode(); 4515 unsigned Opc2 = Load2->getMachineOpcode(); 4516 switch (Opc1) { 4517 default: return false; 4518 case X86::MOV8rm: 4519 case X86::MOV16rm: 4520 case X86::MOV32rm: 4521 case X86::MOV64rm: 4522 case X86::LD_Fp32m: 4523 case X86::LD_Fp64m: 4524 case X86::LD_Fp80m: 4525 case X86::MOVSSrm: 4526 case X86::MOVSDrm: 4527 case X86::MMX_MOVD64rm: 4528 case X86::MMX_MOVQ64rm: 4529 case X86::FsMOVAPSrm: 4530 case X86::FsMOVAPDrm: 4531 case X86::MOVAPSrm: 4532 case X86::MOVUPSrm: 4533 case X86::MOVAPDrm: 4534 case X86::MOVDQArm: 4535 case X86::MOVDQUrm: 4536 // AVX load instructions 4537 case X86::VMOVSSrm: 4538 case X86::VMOVSDrm: 4539 case X86::FsVMOVAPSrm: 4540 case X86::FsVMOVAPDrm: 4541 case X86::VMOVAPSrm: 4542 case X86::VMOVUPSrm: 4543 case X86::VMOVAPDrm: 4544 case X86::VMOVDQArm: 4545 case X86::VMOVDQUrm: 4546 case X86::VMOVAPSYrm: 4547 case X86::VMOVUPSYrm: 4548 case X86::VMOVAPDYrm: 4549 case X86::VMOVDQAYrm: 4550 case X86::VMOVDQUYrm: 4551 break; 4552 } 4553 switch (Opc2) { 4554 default: return false; 4555 case X86::MOV8rm: 4556 case X86::MOV16rm: 4557 case X86::MOV32rm: 4558 case X86::MOV64rm: 4559 case X86::LD_Fp32m: 4560 case X86::LD_Fp64m: 4561 case X86::LD_Fp80m: 4562 case X86::MOVSSrm: 4563 case X86::MOVSDrm: 4564 case X86::MMX_MOVD64rm: 4565 case X86::MMX_MOVQ64rm: 4566 case X86::FsMOVAPSrm: 4567 case X86::FsMOVAPDrm: 4568 case X86::MOVAPSrm: 4569 case X86::MOVUPSrm: 4570 case X86::MOVAPDrm: 4571 case X86::MOVDQArm: 4572 case X86::MOVDQUrm: 4573 // AVX load instructions 4574 case X86::VMOVSSrm: 4575 case X86::VMOVSDrm: 4576 case X86::FsVMOVAPSrm: 4577 case X86::FsVMOVAPDrm: 4578 case X86::VMOVAPSrm: 4579 case X86::VMOVUPSrm: 4580 case X86::VMOVAPDrm: 4581 case X86::VMOVDQArm: 4582 case X86::VMOVDQUrm: 4583 case X86::VMOVAPSYrm: 4584 case X86::VMOVUPSYrm: 4585 case X86::VMOVAPDYrm: 4586 case X86::VMOVDQAYrm: 4587 case X86::VMOVDQUYrm: 4588 break; 4589 } 4590 4591 // Check if chain operands and base addresses match. 4592 if (Load1->getOperand(0) != Load2->getOperand(0) || 4593 Load1->getOperand(5) != Load2->getOperand(5)) 4594 return false; 4595 // Segment operands should match as well. 4596 if (Load1->getOperand(4) != Load2->getOperand(4)) 4597 return false; 4598 // Scale should be 1, Index should be Reg0. 4599 if (Load1->getOperand(1) == Load2->getOperand(1) && 4600 Load1->getOperand(2) == Load2->getOperand(2)) { 4601 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 4602 return false; 4603 4604 // Now let's examine the displacements. 4605 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 4606 isa<ConstantSDNode>(Load2->getOperand(3))) { 4607 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 4608 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 4609 return true; 4610 } 4611 } 4612 return false; 4613 } 4614 4615 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 4616 int64_t Offset1, int64_t Offset2, 4617 unsigned NumLoads) const { 4618 assert(Offset2 > Offset1); 4619 if ((Offset2 - Offset1) / 8 > 64) 4620 return false; 4621 4622 unsigned Opc1 = Load1->getMachineOpcode(); 4623 unsigned Opc2 = Load2->getMachineOpcode(); 4624 if (Opc1 != Opc2) 4625 return false; // FIXME: overly conservative? 4626 4627 switch (Opc1) { 4628 default: break; 4629 case X86::LD_Fp32m: 4630 case X86::LD_Fp64m: 4631 case X86::LD_Fp80m: 4632 case X86::MMX_MOVD64rm: 4633 case X86::MMX_MOVQ64rm: 4634 return false; 4635 } 4636 4637 EVT VT = Load1->getValueType(0); 4638 switch (VT.getSimpleVT().SimpleTy) { 4639 default: 4640 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 4641 // have 16 of them to play with. 4642 if (TM.getSubtargetImpl()->is64Bit()) { 4643 if (NumLoads >= 3) 4644 return false; 4645 } else if (NumLoads) { 4646 return false; 4647 } 4648 break; 4649 case MVT::i8: 4650 case MVT::i16: 4651 case MVT::i32: 4652 case MVT::i64: 4653 case MVT::f32: 4654 case MVT::f64: 4655 if (NumLoads) 4656 return false; 4657 break; 4658 } 4659 4660 return true; 4661 } 4662 4663 4664 bool X86InstrInfo:: 4665 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 4666 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 4667 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 4668 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 4669 return true; 4670 Cond[0].setImm(GetOppositeBranchCondition(CC)); 4671 return false; 4672 } 4673 4674 bool X86InstrInfo:: 4675 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 4676 // FIXME: Return false for x87 stack register classes for now. We can't 4677 // allow any loads of these registers before FpGet_ST0_80. 4678 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 4679 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 4680 } 4681 4682 /// getGlobalBaseReg - Return a virtual register initialized with the 4683 /// the global base register value. Output instructions required to 4684 /// initialize the register in the function entry block, if necessary. 4685 /// 4686 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 4687 /// 4688 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 4689 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 4690 "X86-64 PIC uses RIP relative addressing"); 4691 4692 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 4693 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 4694 if (GlobalBaseReg != 0) 4695 return GlobalBaseReg; 4696 4697 // Create the register. The code to initialize it is inserted 4698 // later, by the CGBR pass (below). 4699 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 4700 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 4701 X86FI->setGlobalBaseReg(GlobalBaseReg); 4702 return GlobalBaseReg; 4703 } 4704 4705 // These are the replaceable SSE instructions. Some of these have Int variants 4706 // that we don't include here. We don't want to replace instructions selected 4707 // by intrinsics. 4708 static const uint16_t ReplaceableInstrs[][3] = { 4709 //PackedSingle PackedDouble PackedInt 4710 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 4711 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 4712 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 4713 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 4714 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 4715 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 4716 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 4717 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 4718 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 4719 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 4720 { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 4721 { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 4722 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 4723 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 4724 // AVX 128-bit support 4725 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr }, 4726 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm }, 4727 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr }, 4728 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr }, 4729 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm }, 4730 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr }, 4731 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm }, 4732 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr }, 4733 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm }, 4734 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr }, 4735 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm }, 4736 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr }, 4737 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm }, 4738 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr }, 4739 // AVX 256-bit support 4740 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr }, 4741 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm }, 4742 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr }, 4743 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr }, 4744 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm }, 4745 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr } 4746 }; 4747 4748 static const uint16_t ReplaceableInstrsAVX2[][3] = { 4749 //PackedSingle PackedDouble PackedInt 4750 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm }, 4751 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr }, 4752 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm }, 4753 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr }, 4754 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm }, 4755 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr }, 4756 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm }, 4757 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }, 4758 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr }, 4759 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr }, 4760 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm }, 4761 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr }, 4762 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm }, 4763 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr } 4764 }; 4765 4766 // FIXME: Some shuffle and unpack instructions have equivalents in different 4767 // domains, but they require a bit more work than just switching opcodes. 4768 4769 static const uint16_t *lookup(unsigned opcode, unsigned domain) { 4770 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i) 4771 if (ReplaceableInstrs[i][domain-1] == opcode) 4772 return ReplaceableInstrs[i]; 4773 return 0; 4774 } 4775 4776 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) { 4777 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i) 4778 if (ReplaceableInstrsAVX2[i][domain-1] == opcode) 4779 return ReplaceableInstrsAVX2[i]; 4780 return 0; 4781 } 4782 4783 std::pair<uint16_t, uint16_t> 4784 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const { 4785 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 4786 bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2(); 4787 uint16_t validDomains = 0; 4788 if (domain && lookup(MI->getOpcode(), domain)) 4789 validDomains = 0xe; 4790 else if (domain && lookupAVX2(MI->getOpcode(), domain)) 4791 validDomains = hasAVX2 ? 0xe : 0x6; 4792 return std::make_pair(domain, validDomains); 4793 } 4794 4795 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 4796 assert(Domain>0 && Domain<4 && "Invalid execution domain"); 4797 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 4798 assert(dom && "Not an SSE instruction"); 4799 const uint16_t *table = lookup(MI->getOpcode(), dom); 4800 if (!table) { // try the other table 4801 assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) && 4802 "256-bit vector operations only available in AVX2"); 4803 table = lookupAVX2(MI->getOpcode(), dom); 4804 } 4805 assert(table && "Cannot change domain"); 4806 MI->setDesc(get(table[Domain-1])); 4807 } 4808 4809 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 4810 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 4811 NopInst.setOpcode(X86::NOOP); 4812 } 4813 4814 bool X86InstrInfo::isHighLatencyDef(int opc) const { 4815 switch (opc) { 4816 default: return false; 4817 case X86::DIVSDrm: 4818 case X86::DIVSDrm_Int: 4819 case X86::DIVSDrr: 4820 case X86::DIVSDrr_Int: 4821 case X86::DIVSSrm: 4822 case X86::DIVSSrm_Int: 4823 case X86::DIVSSrr: 4824 case X86::DIVSSrr_Int: 4825 case X86::SQRTPDm: 4826 case X86::SQRTPDr: 4827 case X86::SQRTPSm: 4828 case X86::SQRTPSr: 4829 case X86::SQRTSDm: 4830 case X86::SQRTSDm_Int: 4831 case X86::SQRTSDr: 4832 case X86::SQRTSDr_Int: 4833 case X86::SQRTSSm: 4834 case X86::SQRTSSm_Int: 4835 case X86::SQRTSSr: 4836 case X86::SQRTSSr_Int: 4837 // AVX instructions with high latency 4838 case X86::VDIVSDrm: 4839 case X86::VDIVSDrm_Int: 4840 case X86::VDIVSDrr: 4841 case X86::VDIVSDrr_Int: 4842 case X86::VDIVSSrm: 4843 case X86::VDIVSSrm_Int: 4844 case X86::VDIVSSrr: 4845 case X86::VDIVSSrr_Int: 4846 case X86::VSQRTPDm: 4847 case X86::VSQRTPDr: 4848 case X86::VSQRTPSm: 4849 case X86::VSQRTPSr: 4850 case X86::VSQRTSDm: 4851 case X86::VSQRTSDm_Int: 4852 case X86::VSQRTSDr: 4853 case X86::VSQRTSSm: 4854 case X86::VSQRTSSm_Int: 4855 case X86::VSQRTSSr: 4856 return true; 4857 } 4858 } 4859 4860 bool X86InstrInfo:: 4861 hasHighOperandLatency(const InstrItineraryData *ItinData, 4862 const MachineRegisterInfo *MRI, 4863 const MachineInstr *DefMI, unsigned DefIdx, 4864 const MachineInstr *UseMI, unsigned UseIdx) const { 4865 return isHighLatencyDef(DefMI->getOpcode()); 4866 } 4867 4868 namespace { 4869 /// CGBR - Create Global Base Reg pass. This initializes the PIC 4870 /// global base register for x86-32. 4871 struct CGBR : public MachineFunctionPass { 4872 static char ID; 4873 CGBR() : MachineFunctionPass(ID) {} 4874 4875 virtual bool runOnMachineFunction(MachineFunction &MF) { 4876 const X86TargetMachine *TM = 4877 static_cast<const X86TargetMachine *>(&MF.getTarget()); 4878 4879 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() && 4880 "X86-64 PIC uses RIP relative addressing"); 4881 4882 // Only emit a global base reg in PIC mode. 4883 if (TM->getRelocationModel() != Reloc::PIC_) 4884 return false; 4885 4886 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 4887 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 4888 4889 // If we didn't need a GlobalBaseReg, don't insert code. 4890 if (GlobalBaseReg == 0) 4891 return false; 4892 4893 // Insert the set of GlobalBaseReg into the first MBB of the function 4894 MachineBasicBlock &FirstMBB = MF.front(); 4895 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 4896 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 4897 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4898 const X86InstrInfo *TII = TM->getInstrInfo(); 4899 4900 unsigned PC; 4901 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) 4902 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass); 4903 else 4904 PC = GlobalBaseReg; 4905 4906 // Operand of MovePCtoStack is completely ignored by asm printer. It's 4907 // only used in JIT code emission as displacement to pc. 4908 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 4909 4910 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 4911 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 4912 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) { 4913 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 4914 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 4915 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 4916 X86II::MO_GOT_ABSOLUTE_ADDRESS); 4917 } 4918 4919 return true; 4920 } 4921 4922 virtual const char *getPassName() const { 4923 return "X86 PIC Global Base Reg Initialization"; 4924 } 4925 4926 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 4927 AU.setPreservesCFG(); 4928 MachineFunctionPass::getAnalysisUsage(AU); 4929 } 4930 }; 4931 } 4932 4933 char CGBR::ID = 0; 4934 FunctionPass* 4935 llvm::createGlobalBaseRegPass() { return new CGBR(); } 4936 4937 namespace { 4938 struct LDTLSCleanup : public MachineFunctionPass { 4939 static char ID; 4940 LDTLSCleanup() : MachineFunctionPass(ID) {} 4941 4942 virtual bool runOnMachineFunction(MachineFunction &MF) { 4943 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>(); 4944 if (MFI->getNumLocalDynamicTLSAccesses() < 2) { 4945 // No point folding accesses if there isn't at least two. 4946 return false; 4947 } 4948 4949 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>(); 4950 return VisitNode(DT->getRootNode(), 0); 4951 } 4952 4953 // Visit the dominator subtree rooted at Node in pre-order. 4954 // If TLSBaseAddrReg is non-null, then use that to replace any 4955 // TLS_base_addr instructions. Otherwise, create the register 4956 // when the first such instruction is seen, and then use it 4957 // as we encounter more instructions. 4958 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) { 4959 MachineBasicBlock *BB = Node->getBlock(); 4960 bool Changed = false; 4961 4962 // Traverse the current block. 4963 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; 4964 ++I) { 4965 switch (I->getOpcode()) { 4966 case X86::TLS_base_addr32: 4967 case X86::TLS_base_addr64: 4968 if (TLSBaseAddrReg) 4969 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg); 4970 else 4971 I = SetRegister(I, &TLSBaseAddrReg); 4972 Changed = true; 4973 break; 4974 default: 4975 break; 4976 } 4977 } 4978 4979 // Visit the children of this block in the dominator tree. 4980 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end(); 4981 I != E; ++I) { 4982 Changed |= VisitNode(*I, TLSBaseAddrReg); 4983 } 4984 4985 return Changed; 4986 } 4987 4988 // Replace the TLS_base_addr instruction I with a copy from 4989 // TLSBaseAddrReg, returning the new instruction. 4990 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I, 4991 unsigned TLSBaseAddrReg) { 4992 MachineFunction *MF = I->getParent()->getParent(); 4993 const X86TargetMachine *TM = 4994 static_cast<const X86TargetMachine *>(&MF->getTarget()); 4995 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 4996 const X86InstrInfo *TII = TM->getInstrInfo(); 4997 4998 // Insert a Copy from TLSBaseAddrReg to RAX/EAX. 4999 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(), 5000 TII->get(TargetOpcode::COPY), 5001 is64Bit ? X86::RAX : X86::EAX) 5002 .addReg(TLSBaseAddrReg); 5003 5004 // Erase the TLS_base_addr instruction. 5005 I->eraseFromParent(); 5006 5007 return Copy; 5008 } 5009 5010 // Create a virtal register in *TLSBaseAddrReg, and populate it by 5011 // inserting a copy instruction after I. Returns the new instruction. 5012 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) { 5013 MachineFunction *MF = I->getParent()->getParent(); 5014 const X86TargetMachine *TM = 5015 static_cast<const X86TargetMachine *>(&MF->getTarget()); 5016 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 5017 const X86InstrInfo *TII = TM->getInstrInfo(); 5018 5019 // Create a virtual register for the TLS base address. 5020 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 5021 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit 5022 ? &X86::GR64RegClass 5023 : &X86::GR32RegClass); 5024 5025 // Insert a copy from RAX/EAX to TLSBaseAddrReg. 5026 MachineInstr *Next = I->getNextNode(); 5027 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(), 5028 TII->get(TargetOpcode::COPY), 5029 *TLSBaseAddrReg) 5030 .addReg(is64Bit ? X86::RAX : X86::EAX); 5031 5032 return Copy; 5033 } 5034 5035 virtual const char *getPassName() const { 5036 return "Local Dynamic TLS Access Clean-up"; 5037 } 5038 5039 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 5040 AU.setPreservesCFG(); 5041 AU.addRequired<MachineDominatorTree>(); 5042 MachineFunctionPass::getAnalysisUsage(AU); 5043 } 5044 }; 5045 } 5046 5047 char LDTLSCleanup::ID = 0; 5048 FunctionPass* 5049 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); } 5050