1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetAsmInfo.h"
31 
32 using namespace llvm;
33 
34 namespace {
35   cl::opt<bool>
36   NoFusing("disable-spill-fusing",
37            cl::desc("Disable fusing of spill code into instructions"));
38   cl::opt<bool>
39   PrintFailedFusing("print-failed-fuse-candidates",
40                     cl::desc("Print instructions that the allocator wants to"
41                              " fuse, but the X86 backend currently can't"),
42                     cl::Hidden);
43   cl::opt<bool>
44   ReMatPICStubLoad("remat-pic-stub-load",
45                    cl::desc("Re-materialize load from stub in PIC mode"),
46                    cl::init(false), cl::Hidden);
47 }
48 
49 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
50   : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
51     TM(tm), RI(tm, *this) {
52   SmallVector<unsigned,16> AmbEntries;
53   static const unsigned OpTbl2Addr[][2] = {
54     { X86::ADC32ri,     X86::ADC32mi },
55     { X86::ADC32ri8,    X86::ADC32mi8 },
56     { X86::ADC32rr,     X86::ADC32mr },
57     { X86::ADC64ri32,   X86::ADC64mi32 },
58     { X86::ADC64ri8,    X86::ADC64mi8 },
59     { X86::ADC64rr,     X86::ADC64mr },
60     { X86::ADD16ri,     X86::ADD16mi },
61     { X86::ADD16ri8,    X86::ADD16mi8 },
62     { X86::ADD16rr,     X86::ADD16mr },
63     { X86::ADD32ri,     X86::ADD32mi },
64     { X86::ADD32ri8,    X86::ADD32mi8 },
65     { X86::ADD32rr,     X86::ADD32mr },
66     { X86::ADD64ri32,   X86::ADD64mi32 },
67     { X86::ADD64ri8,    X86::ADD64mi8 },
68     { X86::ADD64rr,     X86::ADD64mr },
69     { X86::ADD8ri,      X86::ADD8mi },
70     { X86::ADD8rr,      X86::ADD8mr },
71     { X86::AND16ri,     X86::AND16mi },
72     { X86::AND16ri8,    X86::AND16mi8 },
73     { X86::AND16rr,     X86::AND16mr },
74     { X86::AND32ri,     X86::AND32mi },
75     { X86::AND32ri8,    X86::AND32mi8 },
76     { X86::AND32rr,     X86::AND32mr },
77     { X86::AND64ri32,   X86::AND64mi32 },
78     { X86::AND64ri8,    X86::AND64mi8 },
79     { X86::AND64rr,     X86::AND64mr },
80     { X86::AND8ri,      X86::AND8mi },
81     { X86::AND8rr,      X86::AND8mr },
82     { X86::DEC16r,      X86::DEC16m },
83     { X86::DEC32r,      X86::DEC32m },
84     { X86::DEC64_16r,   X86::DEC64_16m },
85     { X86::DEC64_32r,   X86::DEC64_32m },
86     { X86::DEC64r,      X86::DEC64m },
87     { X86::DEC8r,       X86::DEC8m },
88     { X86::INC16r,      X86::INC16m },
89     { X86::INC32r,      X86::INC32m },
90     { X86::INC64_16r,   X86::INC64_16m },
91     { X86::INC64_32r,   X86::INC64_32m },
92     { X86::INC64r,      X86::INC64m },
93     { X86::INC8r,       X86::INC8m },
94     { X86::NEG16r,      X86::NEG16m },
95     { X86::NEG32r,      X86::NEG32m },
96     { X86::NEG64r,      X86::NEG64m },
97     { X86::NEG8r,       X86::NEG8m },
98     { X86::NOT16r,      X86::NOT16m },
99     { X86::NOT32r,      X86::NOT32m },
100     { X86::NOT64r,      X86::NOT64m },
101     { X86::NOT8r,       X86::NOT8m },
102     { X86::OR16ri,      X86::OR16mi },
103     { X86::OR16ri8,     X86::OR16mi8 },
104     { X86::OR16rr,      X86::OR16mr },
105     { X86::OR32ri,      X86::OR32mi },
106     { X86::OR32ri8,     X86::OR32mi8 },
107     { X86::OR32rr,      X86::OR32mr },
108     { X86::OR64ri32,    X86::OR64mi32 },
109     { X86::OR64ri8,     X86::OR64mi8 },
110     { X86::OR64rr,      X86::OR64mr },
111     { X86::OR8ri,       X86::OR8mi },
112     { X86::OR8rr,       X86::OR8mr },
113     { X86::ROL16r1,     X86::ROL16m1 },
114     { X86::ROL16rCL,    X86::ROL16mCL },
115     { X86::ROL16ri,     X86::ROL16mi },
116     { X86::ROL32r1,     X86::ROL32m1 },
117     { X86::ROL32rCL,    X86::ROL32mCL },
118     { X86::ROL32ri,     X86::ROL32mi },
119     { X86::ROL64r1,     X86::ROL64m1 },
120     { X86::ROL64rCL,    X86::ROL64mCL },
121     { X86::ROL64ri,     X86::ROL64mi },
122     { X86::ROL8r1,      X86::ROL8m1 },
123     { X86::ROL8rCL,     X86::ROL8mCL },
124     { X86::ROL8ri,      X86::ROL8mi },
125     { X86::ROR16r1,     X86::ROR16m1 },
126     { X86::ROR16rCL,    X86::ROR16mCL },
127     { X86::ROR16ri,     X86::ROR16mi },
128     { X86::ROR32r1,     X86::ROR32m1 },
129     { X86::ROR32rCL,    X86::ROR32mCL },
130     { X86::ROR32ri,     X86::ROR32mi },
131     { X86::ROR64r1,     X86::ROR64m1 },
132     { X86::ROR64rCL,    X86::ROR64mCL },
133     { X86::ROR64ri,     X86::ROR64mi },
134     { X86::ROR8r1,      X86::ROR8m1 },
135     { X86::ROR8rCL,     X86::ROR8mCL },
136     { X86::ROR8ri,      X86::ROR8mi },
137     { X86::SAR16r1,     X86::SAR16m1 },
138     { X86::SAR16rCL,    X86::SAR16mCL },
139     { X86::SAR16ri,     X86::SAR16mi },
140     { X86::SAR32r1,     X86::SAR32m1 },
141     { X86::SAR32rCL,    X86::SAR32mCL },
142     { X86::SAR32ri,     X86::SAR32mi },
143     { X86::SAR64r1,     X86::SAR64m1 },
144     { X86::SAR64rCL,    X86::SAR64mCL },
145     { X86::SAR64ri,     X86::SAR64mi },
146     { X86::SAR8r1,      X86::SAR8m1 },
147     { X86::SAR8rCL,     X86::SAR8mCL },
148     { X86::SAR8ri,      X86::SAR8mi },
149     { X86::SBB32ri,     X86::SBB32mi },
150     { X86::SBB32ri8,    X86::SBB32mi8 },
151     { X86::SBB32rr,     X86::SBB32mr },
152     { X86::SBB64ri32,   X86::SBB64mi32 },
153     { X86::SBB64ri8,    X86::SBB64mi8 },
154     { X86::SBB64rr,     X86::SBB64mr },
155     { X86::SHL16rCL,    X86::SHL16mCL },
156     { X86::SHL16ri,     X86::SHL16mi },
157     { X86::SHL32rCL,    X86::SHL32mCL },
158     { X86::SHL32ri,     X86::SHL32mi },
159     { X86::SHL64rCL,    X86::SHL64mCL },
160     { X86::SHL64ri,     X86::SHL64mi },
161     { X86::SHL8rCL,     X86::SHL8mCL },
162     { X86::SHL8ri,      X86::SHL8mi },
163     { X86::SHLD16rrCL,  X86::SHLD16mrCL },
164     { X86::SHLD16rri8,  X86::SHLD16mri8 },
165     { X86::SHLD32rrCL,  X86::SHLD32mrCL },
166     { X86::SHLD32rri8,  X86::SHLD32mri8 },
167     { X86::SHLD64rrCL,  X86::SHLD64mrCL },
168     { X86::SHLD64rri8,  X86::SHLD64mri8 },
169     { X86::SHR16r1,     X86::SHR16m1 },
170     { X86::SHR16rCL,    X86::SHR16mCL },
171     { X86::SHR16ri,     X86::SHR16mi },
172     { X86::SHR32r1,     X86::SHR32m1 },
173     { X86::SHR32rCL,    X86::SHR32mCL },
174     { X86::SHR32ri,     X86::SHR32mi },
175     { X86::SHR64r1,     X86::SHR64m1 },
176     { X86::SHR64rCL,    X86::SHR64mCL },
177     { X86::SHR64ri,     X86::SHR64mi },
178     { X86::SHR8r1,      X86::SHR8m1 },
179     { X86::SHR8rCL,     X86::SHR8mCL },
180     { X86::SHR8ri,      X86::SHR8mi },
181     { X86::SHRD16rrCL,  X86::SHRD16mrCL },
182     { X86::SHRD16rri8,  X86::SHRD16mri8 },
183     { X86::SHRD32rrCL,  X86::SHRD32mrCL },
184     { X86::SHRD32rri8,  X86::SHRD32mri8 },
185     { X86::SHRD64rrCL,  X86::SHRD64mrCL },
186     { X86::SHRD64rri8,  X86::SHRD64mri8 },
187     { X86::SUB16ri,     X86::SUB16mi },
188     { X86::SUB16ri8,    X86::SUB16mi8 },
189     { X86::SUB16rr,     X86::SUB16mr },
190     { X86::SUB32ri,     X86::SUB32mi },
191     { X86::SUB32ri8,    X86::SUB32mi8 },
192     { X86::SUB32rr,     X86::SUB32mr },
193     { X86::SUB64ri32,   X86::SUB64mi32 },
194     { X86::SUB64ri8,    X86::SUB64mi8 },
195     { X86::SUB64rr,     X86::SUB64mr },
196     { X86::SUB8ri,      X86::SUB8mi },
197     { X86::SUB8rr,      X86::SUB8mr },
198     { X86::XOR16ri,     X86::XOR16mi },
199     { X86::XOR16ri8,    X86::XOR16mi8 },
200     { X86::XOR16rr,     X86::XOR16mr },
201     { X86::XOR32ri,     X86::XOR32mi },
202     { X86::XOR32ri8,    X86::XOR32mi8 },
203     { X86::XOR32rr,     X86::XOR32mr },
204     { X86::XOR64ri32,   X86::XOR64mi32 },
205     { X86::XOR64ri8,    X86::XOR64mi8 },
206     { X86::XOR64rr,     X86::XOR64mr },
207     { X86::XOR8ri,      X86::XOR8mi },
208     { X86::XOR8rr,      X86::XOR8mr }
209   };
210 
211   for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
212     unsigned RegOp = OpTbl2Addr[i][0];
213     unsigned MemOp = OpTbl2Addr[i][1];
214     if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
215                                                      MemOp)).second)
216       assert(false && "Duplicated entries?");
217     unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
218     if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
219                                                 std::make_pair(RegOp,
220                                                               AuxInfo))).second)
221       AmbEntries.push_back(MemOp);
222   }
223 
224   // If the third value is 1, then it's folding either a load or a store.
225   static const unsigned OpTbl0[][3] = {
226     { X86::BT16ri8,     X86::BT16mi8, 1 },
227     { X86::BT32ri8,     X86::BT32mi8, 1 },
228     { X86::BT64ri8,     X86::BT64mi8, 1 },
229     { X86::CALL32r,     X86::CALL32m, 1 },
230     { X86::CALL64r,     X86::CALL64m, 1 },
231     { X86::CMP16ri,     X86::CMP16mi, 1 },
232     { X86::CMP16ri8,    X86::CMP16mi8, 1 },
233     { X86::CMP16rr,     X86::CMP16mr, 1 },
234     { X86::CMP32ri,     X86::CMP32mi, 1 },
235     { X86::CMP32ri8,    X86::CMP32mi8, 1 },
236     { X86::CMP32rr,     X86::CMP32mr, 1 },
237     { X86::CMP64ri32,   X86::CMP64mi32, 1 },
238     { X86::CMP64ri8,    X86::CMP64mi8, 1 },
239     { X86::CMP64rr,     X86::CMP64mr, 1 },
240     { X86::CMP8ri,      X86::CMP8mi, 1 },
241     { X86::CMP8rr,      X86::CMP8mr, 1 },
242     { X86::DIV16r,      X86::DIV16m, 1 },
243     { X86::DIV32r,      X86::DIV32m, 1 },
244     { X86::DIV64r,      X86::DIV64m, 1 },
245     { X86::DIV8r,       X86::DIV8m, 1 },
246     { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0 },
247     { X86::FsMOVAPDrr,  X86::MOVSDmr, 0 },
248     { X86::FsMOVAPSrr,  X86::MOVSSmr, 0 },
249     { X86::IDIV16r,     X86::IDIV16m, 1 },
250     { X86::IDIV32r,     X86::IDIV32m, 1 },
251     { X86::IDIV64r,     X86::IDIV64m, 1 },
252     { X86::IDIV8r,      X86::IDIV8m, 1 },
253     { X86::IMUL16r,     X86::IMUL16m, 1 },
254     { X86::IMUL32r,     X86::IMUL32m, 1 },
255     { X86::IMUL64r,     X86::IMUL64m, 1 },
256     { X86::IMUL8r,      X86::IMUL8m, 1 },
257     { X86::JMP32r,      X86::JMP32m, 1 },
258     { X86::JMP64r,      X86::JMP64m, 1 },
259     { X86::MOV16ri,     X86::MOV16mi, 0 },
260     { X86::MOV16rr,     X86::MOV16mr, 0 },
261     { X86::MOV32ri,     X86::MOV32mi, 0 },
262     { X86::MOV32rr,     X86::MOV32mr, 0 },
263     { X86::MOV64ri32,   X86::MOV64mi32, 0 },
264     { X86::MOV64rr,     X86::MOV64mr, 0 },
265     { X86::MOV8ri,      X86::MOV8mi, 0 },
266     { X86::MOV8rr,      X86::MOV8mr, 0 },
267     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0 },
268     { X86::MOVAPDrr,    X86::MOVAPDmr, 0 },
269     { X86::MOVAPSrr,    X86::MOVAPSmr, 0 },
270     { X86::MOVDQArr,    X86::MOVDQAmr, 0 },
271     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
272     { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 },
273     { X86::MOVPS2SSrr,  X86::MOVPS2SSmr, 0 },
274     { X86::MOVSDrr,     X86::MOVSDmr, 0 },
275     { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
276     { X86::MOVSS2DIrr,  X86::MOVSS2DImr, 0 },
277     { X86::MOVSSrr,     X86::MOVSSmr, 0 },
278     { X86::MOVUPDrr,    X86::MOVUPDmr, 0 },
279     { X86::MOVUPSrr,    X86::MOVUPSmr, 0 },
280     { X86::MUL16r,      X86::MUL16m, 1 },
281     { X86::MUL32r,      X86::MUL32m, 1 },
282     { X86::MUL64r,      X86::MUL64m, 1 },
283     { X86::MUL8r,       X86::MUL8m, 1 },
284     { X86::SETAEr,      X86::SETAEm, 0 },
285     { X86::SETAr,       X86::SETAm, 0 },
286     { X86::SETBEr,      X86::SETBEm, 0 },
287     { X86::SETBr,       X86::SETBm, 0 },
288     { X86::SETEr,       X86::SETEm, 0 },
289     { X86::SETGEr,      X86::SETGEm, 0 },
290     { X86::SETGr,       X86::SETGm, 0 },
291     { X86::SETLEr,      X86::SETLEm, 0 },
292     { X86::SETLr,       X86::SETLm, 0 },
293     { X86::SETNEr,      X86::SETNEm, 0 },
294     { X86::SETNOr,      X86::SETNOm, 0 },
295     { X86::SETNPr,      X86::SETNPm, 0 },
296     { X86::SETNSr,      X86::SETNSm, 0 },
297     { X86::SETOr,       X86::SETOm, 0 },
298     { X86::SETPr,       X86::SETPm, 0 },
299     { X86::SETSr,       X86::SETSm, 0 },
300     { X86::TAILJMPr,    X86::TAILJMPm, 1 },
301     { X86::TEST16ri,    X86::TEST16mi, 1 },
302     { X86::TEST32ri,    X86::TEST32mi, 1 },
303     { X86::TEST64ri32,  X86::TEST64mi32, 1 },
304     { X86::TEST8ri,     X86::TEST8mi, 1 }
305   };
306 
307   for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
308     unsigned RegOp = OpTbl0[i][0];
309     unsigned MemOp = OpTbl0[i][1];
310     if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
311                                                  MemOp)).second)
312       assert(false && "Duplicated entries?");
313     unsigned FoldedLoad = OpTbl0[i][2];
314     // Index 0, folded load or store.
315     unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
316     if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
317       if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
318                                      std::make_pair(RegOp, AuxInfo))).second)
319         AmbEntries.push_back(MemOp);
320   }
321 
322   static const unsigned OpTbl1[][2] = {
323     { X86::CMP16rr,         X86::CMP16rm },
324     { X86::CMP32rr,         X86::CMP32rm },
325     { X86::CMP64rr,         X86::CMP64rm },
326     { X86::CMP8rr,          X86::CMP8rm },
327     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm },
328     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm },
329     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm },
330     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm },
331     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm },
332     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm },
333     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm },
334     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm },
335     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm },
336     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm },
337     { X86::FsMOVAPDrr,      X86::MOVSDrm },
338     { X86::FsMOVAPSrr,      X86::MOVSSrm },
339     { X86::IMUL16rri,       X86::IMUL16rmi },
340     { X86::IMUL16rri8,      X86::IMUL16rmi8 },
341     { X86::IMUL32rri,       X86::IMUL32rmi },
342     { X86::IMUL32rri8,      X86::IMUL32rmi8 },
343     { X86::IMUL64rri32,     X86::IMUL64rmi32 },
344     { X86::IMUL64rri8,      X86::IMUL64rmi8 },
345     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm },
346     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm },
347     { X86::Int_COMISDrr,    X86::Int_COMISDrm },
348     { X86::Int_COMISSrr,    X86::Int_COMISSrm },
349     { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm },
350     { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm },
351     { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm },
352     { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm },
353     { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm },
354     { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm },
355     { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
356     { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm },
357     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm },
358     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
359     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm },
360     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
361     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm },
362     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm },
363     { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
364     { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm },
365     { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
366     { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
367     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
368     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
369     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
370     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
371     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm },
372     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm },
373     { X86::MOV16rr,         X86::MOV16rm },
374     { X86::MOV32rr,         X86::MOV32rm },
375     { X86::MOV64rr,         X86::MOV64rm },
376     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm },
377     { X86::MOV64toSDrr,     X86::MOV64toSDrm },
378     { X86::MOV8rr,          X86::MOV8rm },
379     { X86::MOVAPDrr,        X86::MOVAPDrm },
380     { X86::MOVAPSrr,        X86::MOVAPSrm },
381     { X86::MOVDDUPrr,       X86::MOVDDUPrm },
382     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm },
383     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm },
384     { X86::MOVDQArr,        X86::MOVDQArm },
385     { X86::MOVSD2PDrr,      X86::MOVSD2PDrm },
386     { X86::MOVSDrr,         X86::MOVSDrm },
387     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm },
388     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm },
389     { X86::MOVSS2PSrr,      X86::MOVSS2PSrm },
390     { X86::MOVSSrr,         X86::MOVSSrm },
391     { X86::MOVSX16rr8,      X86::MOVSX16rm8 },
392     { X86::MOVSX32rr16,     X86::MOVSX32rm16 },
393     { X86::MOVSX32rr8,      X86::MOVSX32rm8 },
394     { X86::MOVSX64rr16,     X86::MOVSX64rm16 },
395     { X86::MOVSX64rr32,     X86::MOVSX64rm32 },
396     { X86::MOVSX64rr8,      X86::MOVSX64rm8 },
397     { X86::MOVUPDrr,        X86::MOVUPDrm },
398     { X86::MOVUPSrr,        X86::MOVUPSrm },
399     { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm },
400     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm },
401     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm },
402     { X86::MOVZX16rr8,      X86::MOVZX16rm8 },
403     { X86::MOVZX32rr16,     X86::MOVZX32rm16 },
404     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8 },
405     { X86::MOVZX32rr8,      X86::MOVZX32rm8 },
406     { X86::MOVZX64rr16,     X86::MOVZX64rm16 },
407     { X86::MOVZX64rr32,     X86::MOVZX64rm32 },
408     { X86::MOVZX64rr8,      X86::MOVZX64rm8 },
409     { X86::PSHUFDri,        X86::PSHUFDmi },
410     { X86::PSHUFHWri,       X86::PSHUFHWmi },
411     { X86::PSHUFLWri,       X86::PSHUFLWmi },
412     { X86::RCPPSr,          X86::RCPPSm },
413     { X86::RCPPSr_Int,      X86::RCPPSm_Int },
414     { X86::RSQRTPSr,        X86::RSQRTPSm },
415     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int },
416     { X86::RSQRTSSr,        X86::RSQRTSSm },
417     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int },
418     { X86::SQRTPDr,         X86::SQRTPDm },
419     { X86::SQRTPDr_Int,     X86::SQRTPDm_Int },
420     { X86::SQRTPSr,         X86::SQRTPSm },
421     { X86::SQRTPSr_Int,     X86::SQRTPSm_Int },
422     { X86::SQRTSDr,         X86::SQRTSDm },
423     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int },
424     { X86::SQRTSSr,         X86::SQRTSSm },
425     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int },
426     { X86::TEST16rr,        X86::TEST16rm },
427     { X86::TEST32rr,        X86::TEST32rm },
428     { X86::TEST64rr,        X86::TEST64rm },
429     { X86::TEST8rr,         X86::TEST8rm },
430     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
431     { X86::UCOMISDrr,       X86::UCOMISDrm },
432     { X86::UCOMISSrr,       X86::UCOMISSrm }
433   };
434 
435   for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
436     unsigned RegOp = OpTbl1[i][0];
437     unsigned MemOp = OpTbl1[i][1];
438     if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
439                                                  MemOp)).second)
440       assert(false && "Duplicated entries?");
441     unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
442     if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
443       if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
444                                      std::make_pair(RegOp, AuxInfo))).second)
445         AmbEntries.push_back(MemOp);
446   }
447 
448   static const unsigned OpTbl2[][2] = {
449     { X86::ADC32rr,         X86::ADC32rm },
450     { X86::ADC64rr,         X86::ADC64rm },
451     { X86::ADD16rr,         X86::ADD16rm },
452     { X86::ADD32rr,         X86::ADD32rm },
453     { X86::ADD64rr,         X86::ADD64rm },
454     { X86::ADD8rr,          X86::ADD8rm },
455     { X86::ADDPDrr,         X86::ADDPDrm },
456     { X86::ADDPSrr,         X86::ADDPSrm },
457     { X86::ADDSDrr,         X86::ADDSDrm },
458     { X86::ADDSSrr,         X86::ADDSSrm },
459     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm },
460     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm },
461     { X86::AND16rr,         X86::AND16rm },
462     { X86::AND32rr,         X86::AND32rm },
463     { X86::AND64rr,         X86::AND64rm },
464     { X86::AND8rr,          X86::AND8rm },
465     { X86::ANDNPDrr,        X86::ANDNPDrm },
466     { X86::ANDNPSrr,        X86::ANDNPSrm },
467     { X86::ANDPDrr,         X86::ANDPDrm },
468     { X86::ANDPSrr,         X86::ANDPSrm },
469     { X86::CMOVA16rr,       X86::CMOVA16rm },
470     { X86::CMOVA32rr,       X86::CMOVA32rm },
471     { X86::CMOVA64rr,       X86::CMOVA64rm },
472     { X86::CMOVAE16rr,      X86::CMOVAE16rm },
473     { X86::CMOVAE32rr,      X86::CMOVAE32rm },
474     { X86::CMOVAE64rr,      X86::CMOVAE64rm },
475     { X86::CMOVB16rr,       X86::CMOVB16rm },
476     { X86::CMOVB32rr,       X86::CMOVB32rm },
477     { X86::CMOVB64rr,       X86::CMOVB64rm },
478     { X86::CMOVBE16rr,      X86::CMOVBE16rm },
479     { X86::CMOVBE32rr,      X86::CMOVBE32rm },
480     { X86::CMOVBE64rr,      X86::CMOVBE64rm },
481     { X86::CMOVE16rr,       X86::CMOVE16rm },
482     { X86::CMOVE32rr,       X86::CMOVE32rm },
483     { X86::CMOVE64rr,       X86::CMOVE64rm },
484     { X86::CMOVG16rr,       X86::CMOVG16rm },
485     { X86::CMOVG32rr,       X86::CMOVG32rm },
486     { X86::CMOVG64rr,       X86::CMOVG64rm },
487     { X86::CMOVGE16rr,      X86::CMOVGE16rm },
488     { X86::CMOVGE32rr,      X86::CMOVGE32rm },
489     { X86::CMOVGE64rr,      X86::CMOVGE64rm },
490     { X86::CMOVL16rr,       X86::CMOVL16rm },
491     { X86::CMOVL32rr,       X86::CMOVL32rm },
492     { X86::CMOVL64rr,       X86::CMOVL64rm },
493     { X86::CMOVLE16rr,      X86::CMOVLE16rm },
494     { X86::CMOVLE32rr,      X86::CMOVLE32rm },
495     { X86::CMOVLE64rr,      X86::CMOVLE64rm },
496     { X86::CMOVNE16rr,      X86::CMOVNE16rm },
497     { X86::CMOVNE32rr,      X86::CMOVNE32rm },
498     { X86::CMOVNE64rr,      X86::CMOVNE64rm },
499     { X86::CMOVNO16rr,      X86::CMOVNO16rm },
500     { X86::CMOVNO32rr,      X86::CMOVNO32rm },
501     { X86::CMOVNO64rr,      X86::CMOVNO64rm },
502     { X86::CMOVNP16rr,      X86::CMOVNP16rm },
503     { X86::CMOVNP32rr,      X86::CMOVNP32rm },
504     { X86::CMOVNP64rr,      X86::CMOVNP64rm },
505     { X86::CMOVNS16rr,      X86::CMOVNS16rm },
506     { X86::CMOVNS32rr,      X86::CMOVNS32rm },
507     { X86::CMOVNS64rr,      X86::CMOVNS64rm },
508     { X86::CMOVO16rr,       X86::CMOVO16rm },
509     { X86::CMOVO32rr,       X86::CMOVO32rm },
510     { X86::CMOVO64rr,       X86::CMOVO64rm },
511     { X86::CMOVP16rr,       X86::CMOVP16rm },
512     { X86::CMOVP32rr,       X86::CMOVP32rm },
513     { X86::CMOVP64rr,       X86::CMOVP64rm },
514     { X86::CMOVS16rr,       X86::CMOVS16rm },
515     { X86::CMOVS32rr,       X86::CMOVS32rm },
516     { X86::CMOVS64rr,       X86::CMOVS64rm },
517     { X86::CMPPDrri,        X86::CMPPDrmi },
518     { X86::CMPPSrri,        X86::CMPPSrmi },
519     { X86::CMPSDrr,         X86::CMPSDrm },
520     { X86::CMPSSrr,         X86::CMPSSrm },
521     { X86::DIVPDrr,         X86::DIVPDrm },
522     { X86::DIVPSrr,         X86::DIVPSrm },
523     { X86::DIVSDrr,         X86::DIVSDrm },
524     { X86::DIVSSrr,         X86::DIVSSrm },
525     { X86::FsANDNPDrr,      X86::FsANDNPDrm },
526     { X86::FsANDNPSrr,      X86::FsANDNPSrm },
527     { X86::FsANDPDrr,       X86::FsANDPDrm },
528     { X86::FsANDPSrr,       X86::FsANDPSrm },
529     { X86::FsORPDrr,        X86::FsORPDrm },
530     { X86::FsORPSrr,        X86::FsORPSrm },
531     { X86::FsXORPDrr,       X86::FsXORPDrm },
532     { X86::FsXORPSrr,       X86::FsXORPSrm },
533     { X86::HADDPDrr,        X86::HADDPDrm },
534     { X86::HADDPSrr,        X86::HADDPSrm },
535     { X86::HSUBPDrr,        X86::HSUBPDrm },
536     { X86::HSUBPSrr,        X86::HSUBPSrm },
537     { X86::IMUL16rr,        X86::IMUL16rm },
538     { X86::IMUL32rr,        X86::IMUL32rm },
539     { X86::IMUL64rr,        X86::IMUL64rm },
540     { X86::MAXPDrr,         X86::MAXPDrm },
541     { X86::MAXPDrr_Int,     X86::MAXPDrm_Int },
542     { X86::MAXPSrr,         X86::MAXPSrm },
543     { X86::MAXPSrr_Int,     X86::MAXPSrm_Int },
544     { X86::MAXSDrr,         X86::MAXSDrm },
545     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int },
546     { X86::MAXSSrr,         X86::MAXSSrm },
547     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int },
548     { X86::MINPDrr,         X86::MINPDrm },
549     { X86::MINPDrr_Int,     X86::MINPDrm_Int },
550     { X86::MINPSrr,         X86::MINPSrm },
551     { X86::MINPSrr_Int,     X86::MINPSrm_Int },
552     { X86::MINSDrr,         X86::MINSDrm },
553     { X86::MINSDrr_Int,     X86::MINSDrm_Int },
554     { X86::MINSSrr,         X86::MINSSrm },
555     { X86::MINSSrr_Int,     X86::MINSSrm_Int },
556     { X86::MULPDrr,         X86::MULPDrm },
557     { X86::MULPSrr,         X86::MULPSrm },
558     { X86::MULSDrr,         X86::MULSDrm },
559     { X86::MULSSrr,         X86::MULSSrm },
560     { X86::OR16rr,          X86::OR16rm },
561     { X86::OR32rr,          X86::OR32rm },
562     { X86::OR64rr,          X86::OR64rm },
563     { X86::OR8rr,           X86::OR8rm },
564     { X86::ORPDrr,          X86::ORPDrm },
565     { X86::ORPSrr,          X86::ORPSrm },
566     { X86::PACKSSDWrr,      X86::PACKSSDWrm },
567     { X86::PACKSSWBrr,      X86::PACKSSWBrm },
568     { X86::PACKUSWBrr,      X86::PACKUSWBrm },
569     { X86::PADDBrr,         X86::PADDBrm },
570     { X86::PADDDrr,         X86::PADDDrm },
571     { X86::PADDQrr,         X86::PADDQrm },
572     { X86::PADDSBrr,        X86::PADDSBrm },
573     { X86::PADDSWrr,        X86::PADDSWrm },
574     { X86::PADDWrr,         X86::PADDWrm },
575     { X86::PANDNrr,         X86::PANDNrm },
576     { X86::PANDrr,          X86::PANDrm },
577     { X86::PAVGBrr,         X86::PAVGBrm },
578     { X86::PAVGWrr,         X86::PAVGWrm },
579     { X86::PCMPEQBrr,       X86::PCMPEQBrm },
580     { X86::PCMPEQDrr,       X86::PCMPEQDrm },
581     { X86::PCMPEQWrr,       X86::PCMPEQWrm },
582     { X86::PCMPGTBrr,       X86::PCMPGTBrm },
583     { X86::PCMPGTDrr,       X86::PCMPGTDrm },
584     { X86::PCMPGTWrr,       X86::PCMPGTWrm },
585     { X86::PINSRWrri,       X86::PINSRWrmi },
586     { X86::PMADDWDrr,       X86::PMADDWDrm },
587     { X86::PMAXSWrr,        X86::PMAXSWrm },
588     { X86::PMAXUBrr,        X86::PMAXUBrm },
589     { X86::PMINSWrr,        X86::PMINSWrm },
590     { X86::PMINUBrr,        X86::PMINUBrm },
591     { X86::PMULDQrr,        X86::PMULDQrm },
592     { X86::PMULHUWrr,       X86::PMULHUWrm },
593     { X86::PMULHWrr,        X86::PMULHWrm },
594     { X86::PMULLDrr,        X86::PMULLDrm },
595     { X86::PMULLDrr_int,    X86::PMULLDrm_int },
596     { X86::PMULLWrr,        X86::PMULLWrm },
597     { X86::PMULUDQrr,       X86::PMULUDQrm },
598     { X86::PORrr,           X86::PORrm },
599     { X86::PSADBWrr,        X86::PSADBWrm },
600     { X86::PSLLDrr,         X86::PSLLDrm },
601     { X86::PSLLQrr,         X86::PSLLQrm },
602     { X86::PSLLWrr,         X86::PSLLWrm },
603     { X86::PSRADrr,         X86::PSRADrm },
604     { X86::PSRAWrr,         X86::PSRAWrm },
605     { X86::PSRLDrr,         X86::PSRLDrm },
606     { X86::PSRLQrr,         X86::PSRLQrm },
607     { X86::PSRLWrr,         X86::PSRLWrm },
608     { X86::PSUBBrr,         X86::PSUBBrm },
609     { X86::PSUBDrr,         X86::PSUBDrm },
610     { X86::PSUBSBrr,        X86::PSUBSBrm },
611     { X86::PSUBSWrr,        X86::PSUBSWrm },
612     { X86::PSUBWrr,         X86::PSUBWrm },
613     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm },
614     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm },
615     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm },
616     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm },
617     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm },
618     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm },
619     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm },
620     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm },
621     { X86::PXORrr,          X86::PXORrm },
622     { X86::SBB32rr,         X86::SBB32rm },
623     { X86::SBB64rr,         X86::SBB64rm },
624     { X86::SHUFPDrri,       X86::SHUFPDrmi },
625     { X86::SHUFPSrri,       X86::SHUFPSrmi },
626     { X86::SUB16rr,         X86::SUB16rm },
627     { X86::SUB32rr,         X86::SUB32rm },
628     { X86::SUB64rr,         X86::SUB64rm },
629     { X86::SUB8rr,          X86::SUB8rm },
630     { X86::SUBPDrr,         X86::SUBPDrm },
631     { X86::SUBPSrr,         X86::SUBPSrm },
632     { X86::SUBSDrr,         X86::SUBSDrm },
633     { X86::SUBSSrr,         X86::SUBSSrm },
634     // FIXME: TEST*rr -> swapped operand of TEST*mr.
635     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm },
636     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm },
637     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm },
638     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm },
639     { X86::XOR16rr,         X86::XOR16rm },
640     { X86::XOR32rr,         X86::XOR32rm },
641     { X86::XOR64rr,         X86::XOR64rm },
642     { X86::XOR8rr,          X86::XOR8rm },
643     { X86::XORPDrr,         X86::XORPDrm },
644     { X86::XORPSrr,         X86::XORPSrm }
645   };
646 
647   for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
648     unsigned RegOp = OpTbl2[i][0];
649     unsigned MemOp = OpTbl2[i][1];
650     if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
651                                                  MemOp)).second)
652       assert(false && "Duplicated entries?");
653     unsigned AuxInfo = 2 | (1 << 4); // Index 2, folded load
654     if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
655                                    std::make_pair(RegOp, AuxInfo))).second)
656       AmbEntries.push_back(MemOp);
657   }
658 
659   // Remove ambiguous entries.
660   assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
661 }
662 
663 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
664                                unsigned &SrcReg, unsigned &DstReg,
665                                unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
666   switch (MI.getOpcode()) {
667   default:
668     return false;
669   case X86::MOV8rr:
670   case X86::MOV8rr_NOREX:
671   case X86::MOV16rr:
672   case X86::MOV32rr:
673   case X86::MOV64rr:
674   case X86::MOVSSrr:
675   case X86::MOVSDrr:
676 
677   // FP Stack register class copies
678   case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
679   case X86::MOV_Fp3264: case X86::MOV_Fp3280:
680   case X86::MOV_Fp6432: case X86::MOV_Fp8032:
681 
682   case X86::FsMOVAPSrr:
683   case X86::FsMOVAPDrr:
684   case X86::MOVAPSrr:
685   case X86::MOVAPDrr:
686   case X86::MOVDQArr:
687   case X86::MOVSS2PSrr:
688   case X86::MOVSD2PDrr:
689   case X86::MOVPS2SSrr:
690   case X86::MOVPD2SDrr:
691   case X86::MMX_MOVQ64rr:
692     assert(MI.getNumOperands() >= 2 &&
693            MI.getOperand(0).isReg() &&
694            MI.getOperand(1).isReg() &&
695            "invalid register-register move instruction");
696     SrcReg = MI.getOperand(1).getReg();
697     DstReg = MI.getOperand(0).getReg();
698     SrcSubIdx = MI.getOperand(1).getSubReg();
699     DstSubIdx = MI.getOperand(0).getSubReg();
700     return true;
701   }
702 }
703 
704 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
705                                            int &FrameIndex) const {
706   switch (MI->getOpcode()) {
707   default: break;
708   case X86::MOV8rm:
709   case X86::MOV16rm:
710   case X86::MOV32rm:
711   case X86::MOV64rm:
712   case X86::LD_Fp64m:
713   case X86::MOVSSrm:
714   case X86::MOVSDrm:
715   case X86::MOVAPSrm:
716   case X86::MOVAPDrm:
717   case X86::MOVDQArm:
718   case X86::MMX_MOVD64rm:
719   case X86::MMX_MOVQ64rm:
720     if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
721         MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
722         MI->getOperand(2).getImm() == 1 &&
723         MI->getOperand(3).getReg() == 0 &&
724         MI->getOperand(4).getImm() == 0) {
725       FrameIndex = MI->getOperand(1).getIndex();
726       return MI->getOperand(0).getReg();
727     }
728     break;
729   }
730   return 0;
731 }
732 
733 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
734                                           int &FrameIndex) const {
735   switch (MI->getOpcode()) {
736   default: break;
737   case X86::MOV8mr:
738   case X86::MOV16mr:
739   case X86::MOV32mr:
740   case X86::MOV64mr:
741   case X86::ST_FpP64m:
742   case X86::MOVSSmr:
743   case X86::MOVSDmr:
744   case X86::MOVAPSmr:
745   case X86::MOVAPDmr:
746   case X86::MOVDQAmr:
747   case X86::MMX_MOVD64mr:
748   case X86::MMX_MOVQ64mr:
749   case X86::MMX_MOVNTQmr:
750     if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
751         MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
752         MI->getOperand(1).getImm() == 1 &&
753         MI->getOperand(2).getReg() == 0 &&
754         MI->getOperand(3).getImm() == 0) {
755       FrameIndex = MI->getOperand(0).getIndex();
756       return MI->getOperand(X86AddrNumOperands).getReg();
757     }
758     break;
759   }
760   return 0;
761 }
762 
763 
764 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
765 /// X86::MOVPC32r.
766 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
767   bool isPICBase = false;
768   for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
769          E = MRI.def_end(); I != E; ++I) {
770     MachineInstr *DefMI = I.getOperand().getParent();
771     if (DefMI->getOpcode() != X86::MOVPC32r)
772       return false;
773     assert(!isPICBase && "More than one PIC base?");
774     isPICBase = true;
775   }
776   return isPICBase;
777 }
778 
779 /// isGVStub - Return true if the GV requires an extra load to get the
780 /// real address.
781 static inline bool isGVStub(GlobalValue *GV, X86TargetMachine &TM) {
782   return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
783 }
784 
785 bool
786 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
787   switch (MI->getOpcode()) {
788   default: break;
789     case X86::MOV8rm:
790     case X86::MOV16rm:
791     case X86::MOV32rm:
792     case X86::MOV64rm:
793     case X86::LD_Fp64m:
794     case X86::MOVSSrm:
795     case X86::MOVSDrm:
796     case X86::MOVAPSrm:
797     case X86::MOVAPDrm:
798     case X86::MOVDQArm:
799     case X86::MMX_MOVD64rm:
800     case X86::MMX_MOVQ64rm: {
801       // Loads from constant pools are trivially rematerializable.
802       if (MI->getOperand(1).isReg() &&
803           MI->getOperand(2).isImm() &&
804           MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
805           (MI->getOperand(4).isCPI() ||
806            (MI->getOperand(4).isGlobal() &&
807             isGVStub(MI->getOperand(4).getGlobal(), TM)))) {
808         unsigned BaseReg = MI->getOperand(1).getReg();
809         if (BaseReg == 0)
810           return true;
811         // Allow re-materialization of PIC load.
812         if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
813           return false;
814         const MachineFunction &MF = *MI->getParent()->getParent();
815         const MachineRegisterInfo &MRI = MF.getRegInfo();
816         bool isPICBase = false;
817         for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
818                E = MRI.def_end(); I != E; ++I) {
819           MachineInstr *DefMI = I.getOperand().getParent();
820           if (DefMI->getOpcode() != X86::MOVPC32r)
821             return false;
822           assert(!isPICBase && "More than one PIC base?");
823           isPICBase = true;
824         }
825         return isPICBase;
826       }
827       return false;
828     }
829 
830      case X86::LEA32r:
831      case X86::LEA64r: {
832        if (MI->getOperand(2).isImm() &&
833            MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
834            !MI->getOperand(4).isReg()) {
835          // lea fi#, lea GV, etc. are all rematerializable.
836          if (!MI->getOperand(1).isReg())
837            return true;
838          unsigned BaseReg = MI->getOperand(1).getReg();
839          if (BaseReg == 0)
840            return true;
841          // Allow re-materialization of lea PICBase + x.
842          const MachineFunction &MF = *MI->getParent()->getParent();
843          const MachineRegisterInfo &MRI = MF.getRegInfo();
844          return regIsPICBase(BaseReg, MRI);
845        }
846        return false;
847      }
848   }
849 
850   // All other instructions marked M_REMATERIALIZABLE are always trivially
851   // rematerializable.
852   return true;
853 }
854 
855 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
856 /// would clobber the EFLAGS condition register. Note the result may be
857 /// conservative. If it cannot definitely determine the safety after visiting
858 /// two instructions it assumes it's not safe.
859 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
860                                   MachineBasicBlock::iterator I) {
861   // It's always safe to clobber EFLAGS at the end of a block.
862   if (I == MBB.end())
863     return true;
864 
865   // For compile time consideration, if we are not able to determine the
866   // safety after visiting 2 instructions, we will assume it's not safe.
867   for (unsigned i = 0; i < 2; ++i) {
868     bool SeenDef = false;
869     for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
870       MachineOperand &MO = I->getOperand(j);
871       if (!MO.isReg())
872         continue;
873       if (MO.getReg() == X86::EFLAGS) {
874         if (MO.isUse())
875           return false;
876         SeenDef = true;
877       }
878     }
879 
880     if (SeenDef)
881       // This instruction defines EFLAGS, no need to look any further.
882       return true;
883     ++I;
884 
885     // If we make it to the end of the block, it's safe to clobber EFLAGS.
886     if (I == MBB.end())
887       return true;
888   }
889 
890   // Conservative answer.
891   return false;
892 }
893 
894 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
895                                  MachineBasicBlock::iterator I,
896                                  unsigned DestReg,
897                                  const MachineInstr *Orig) const {
898   DebugLoc DL = DebugLoc::getUnknownLoc();
899   if (I != MBB.end()) DL = I->getDebugLoc();
900 
901   unsigned SubIdx = Orig->getOperand(0).isReg()
902     ? Orig->getOperand(0).getSubReg() : 0;
903   bool ChangeSubIdx = SubIdx != 0;
904   if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
905     DestReg = RI.getSubReg(DestReg, SubIdx);
906     SubIdx = 0;
907   }
908 
909   // MOV32r0 etc. are implemented with xor which clobbers condition code.
910   // Re-materialize them as movri instructions to avoid side effects.
911   bool Emitted = false;
912   switch (Orig->getOpcode()) {
913   default: break;
914   case X86::MOV8r0:
915   case X86::MOV16r0:
916   case X86::MOV32r0:
917   case X86::MOV64r0: {
918     if (!isSafeToClobberEFLAGS(MBB, I)) {
919       unsigned Opc = 0;
920       switch (Orig->getOpcode()) {
921       default: break;
922       case X86::MOV8r0:  Opc = X86::MOV8ri;  break;
923       case X86::MOV16r0: Opc = X86::MOV16ri; break;
924       case X86::MOV32r0: Opc = X86::MOV32ri; break;
925       case X86::MOV64r0: Opc = X86::MOV64ri32; break;
926       }
927       BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
928       Emitted = true;
929     }
930     break;
931   }
932   }
933 
934   if (!Emitted) {
935     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
936     MI->getOperand(0).setReg(DestReg);
937     MBB.insert(I, MI);
938   }
939 
940   if (ChangeSubIdx) {
941     MachineInstr *NewMI = prior(I);
942     NewMI->getOperand(0).setSubReg(SubIdx);
943   }
944 }
945 
946 /// isInvariantLoad - Return true if the specified instruction (which is marked
947 /// mayLoad) is loading from a location whose value is invariant across the
948 /// function.  For example, loading a value from the constant pool or from
949 /// from the argument area of a function if it does not change.  This should
950 /// only return true of *all* loads the instruction does are invariant (if it
951 /// does multiple loads).
952 bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const {
953   // This code cares about loads from three cases: constant pool entries,
954   // invariant argument slots, and global stubs.  In order to handle these cases
955   // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
956   // operand and base our analysis on it.  This is safe because the address of
957   // none of these three cases is ever used as anything other than a load base
958   // and X86 doesn't have any instructions that load from multiple places.
959 
960   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
961     const MachineOperand &MO = MI->getOperand(i);
962     // Loads from constant pools are trivially invariant.
963     if (MO.isCPI())
964       return true;
965 
966     if (MO.isGlobal())
967       return isGVStub(MO.getGlobal(), TM);
968 
969     // If this is a load from an invariant stack slot, the load is a constant.
970     if (MO.isFI()) {
971       const MachineFrameInfo &MFI =
972         *MI->getParent()->getParent()->getFrameInfo();
973       int Idx = MO.getIndex();
974       return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
975     }
976   }
977 
978   // All other instances of these instructions are presumed to have other
979   // issues.
980   return false;
981 }
982 
983 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
984 /// is not marked dead.
985 static bool hasLiveCondCodeDef(MachineInstr *MI) {
986   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
987     MachineOperand &MO = MI->getOperand(i);
988     if (MO.isReg() && MO.isDef() &&
989         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
990       return true;
991     }
992   }
993   return false;
994 }
995 
996 /// convertToThreeAddress - This method must be implemented by targets that
997 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
998 /// may be able to convert a two-address instruction into a true
999 /// three-address instruction on demand.  This allows the X86 target (for
1000 /// example) to convert ADD and SHL instructions into LEA instructions if they
1001 /// would require register copies due to two-addressness.
1002 ///
1003 /// This method returns a null pointer if the transformation cannot be
1004 /// performed, otherwise it returns the new instruction.
1005 ///
1006 MachineInstr *
1007 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1008                                     MachineBasicBlock::iterator &MBBI,
1009                                     LiveVariables *LV) const {
1010   MachineInstr *MI = MBBI;
1011   MachineFunction &MF = *MI->getParent()->getParent();
1012   // All instructions input are two-addr instructions.  Get the known operands.
1013   unsigned Dest = MI->getOperand(0).getReg();
1014   unsigned Src = MI->getOperand(1).getReg();
1015   bool isDead = MI->getOperand(0).isDead();
1016   bool isKill = MI->getOperand(1).isKill();
1017 
1018   MachineInstr *NewMI = NULL;
1019   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
1020   // we have better subtarget support, enable the 16-bit LEA generation here.
1021   bool DisableLEA16 = true;
1022 
1023   unsigned MIOpc = MI->getOpcode();
1024   switch (MIOpc) {
1025   case X86::SHUFPSrri: {
1026     assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1027     if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1028 
1029     unsigned B = MI->getOperand(1).getReg();
1030     unsigned C = MI->getOperand(2).getReg();
1031     if (B != C) return 0;
1032     unsigned A = MI->getOperand(0).getReg();
1033     unsigned M = MI->getOperand(3).getImm();
1034     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1035       .addReg(A, RegState::Define | getDeadRegState(isDead))
1036       .addReg(B, getKillRegState(isKill)).addImm(M);
1037     break;
1038   }
1039   case X86::SHL64ri: {
1040     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1041     // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1042     // the flags produced by a shift yet, so this is safe.
1043     unsigned ShAmt = MI->getOperand(2).getImm();
1044     if (ShAmt == 0 || ShAmt >= 4) return 0;
1045 
1046     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1047       .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1048       .addReg(0).addImm(1 << ShAmt)
1049       .addReg(Src, getKillRegState(isKill))
1050       .addImm(0);
1051     break;
1052   }
1053   case X86::SHL32ri: {
1054     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1055     // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1056     // the flags produced by a shift yet, so this is safe.
1057     unsigned ShAmt = MI->getOperand(2).getImm();
1058     if (ShAmt == 0 || ShAmt >= 4) return 0;
1059 
1060     unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1061       X86::LEA64_32r : X86::LEA32r;
1062     NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1063       .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1064       .addReg(0).addImm(1 << ShAmt)
1065       .addReg(Src, getKillRegState(isKill)).addImm(0);
1066     break;
1067   }
1068   case X86::SHL16ri: {
1069     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1070     // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1071     // the flags produced by a shift yet, so this is safe.
1072     unsigned ShAmt = MI->getOperand(2).getImm();
1073     if (ShAmt == 0 || ShAmt >= 4) return 0;
1074 
1075     if (DisableLEA16) {
1076       // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1077       MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1078       unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1079         ? X86::LEA64_32r : X86::LEA32r;
1080       unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1081       unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1082 
1083       // Build and insert into an implicit UNDEF value. This is OK because
1084       // well be shifting and then extracting the lower 16-bits.
1085       BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1086       MachineInstr *InsMI =
1087         BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1088         .addReg(leaInReg)
1089         .addReg(Src, getKillRegState(isKill))
1090         .addImm(X86::SUBREG_16BIT);
1091 
1092       NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
1093         .addReg(0).addImm(1 << ShAmt)
1094         .addReg(leaInReg, RegState::Kill)
1095         .addImm(0);
1096 
1097       MachineInstr *ExtMI =
1098         BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1099         .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1100         .addReg(leaOutReg, RegState::Kill)
1101         .addImm(X86::SUBREG_16BIT);
1102 
1103       if (LV) {
1104         // Update live variables
1105         LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1106         LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1107         if (isKill)
1108           LV->replaceKillInstruction(Src, MI, InsMI);
1109         if (isDead)
1110           LV->replaceKillInstruction(Dest, MI, ExtMI);
1111       }
1112       return ExtMI;
1113     } else {
1114       NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1115         .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1116         .addReg(0).addImm(1 << ShAmt)
1117         .addReg(Src, getKillRegState(isKill))
1118         .addImm(0);
1119     }
1120     break;
1121   }
1122   default: {
1123     // The following opcodes also sets the condition code register(s). Only
1124     // convert them to equivalent lea if the condition code register def's
1125     // are dead!
1126     if (hasLiveCondCodeDef(MI))
1127       return 0;
1128 
1129     bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1130     switch (MIOpc) {
1131     default: return 0;
1132     case X86::INC64r:
1133     case X86::INC32r:
1134     case X86::INC64_32r: {
1135       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1136       unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1137         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1138       NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1139                               .addReg(Dest, RegState::Define |
1140                                       getDeadRegState(isDead)),
1141                               Src, isKill, 1);
1142       break;
1143     }
1144     case X86::INC16r:
1145     case X86::INC64_16r:
1146       if (DisableLEA16) return 0;
1147       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1148       NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1149                            .addReg(Dest, RegState::Define |
1150                                    getDeadRegState(isDead)),
1151                            Src, isKill, 1);
1152       break;
1153     case X86::DEC64r:
1154     case X86::DEC32r:
1155     case X86::DEC64_32r: {
1156       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1157       unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1158         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1159       NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1160                               .addReg(Dest, RegState::Define |
1161                                       getDeadRegState(isDead)),
1162                               Src, isKill, -1);
1163       break;
1164     }
1165     case X86::DEC16r:
1166     case X86::DEC64_16r:
1167       if (DisableLEA16) return 0;
1168       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1169       NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1170                            .addReg(Dest, RegState::Define |
1171                                    getDeadRegState(isDead)),
1172                            Src, isKill, -1);
1173       break;
1174     case X86::ADD64rr:
1175     case X86::ADD32rr: {
1176       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1177       unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1178         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1179       unsigned Src2 = MI->getOperand(2).getReg();
1180       bool isKill2 = MI->getOperand(2).isKill();
1181       NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1182                         .addReg(Dest, RegState::Define |
1183                                 getDeadRegState(isDead)),
1184                         Src, isKill, Src2, isKill2);
1185       if (LV && isKill2)
1186         LV->replaceKillInstruction(Src2, MI, NewMI);
1187       break;
1188     }
1189     case X86::ADD16rr: {
1190       if (DisableLEA16) return 0;
1191       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1192       unsigned Src2 = MI->getOperand(2).getReg();
1193       bool isKill2 = MI->getOperand(2).isKill();
1194       NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1195                         .addReg(Dest, RegState::Define |
1196                                 getDeadRegState(isDead)),
1197                         Src, isKill, Src2, isKill2);
1198       if (LV && isKill2)
1199         LV->replaceKillInstruction(Src2, MI, NewMI);
1200       break;
1201     }
1202     case X86::ADD64ri32:
1203     case X86::ADD64ri8:
1204       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1205       if (MI->getOperand(2).isImm())
1206         NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1207                                 .addReg(Dest, RegState::Define |
1208                                         getDeadRegState(isDead)),
1209                                 Src, isKill, MI->getOperand(2).getImm());
1210       break;
1211     case X86::ADD32ri:
1212     case X86::ADD32ri8:
1213       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1214       if (MI->getOperand(2).isImm()) {
1215         unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1216         NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1217                                 .addReg(Dest, RegState::Define |
1218                                         getDeadRegState(isDead)),
1219                                 Src, isKill, MI->getOperand(2).getImm());
1220       }
1221       break;
1222     case X86::ADD16ri:
1223     case X86::ADD16ri8:
1224       if (DisableLEA16) return 0;
1225       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1226       if (MI->getOperand(2).isImm())
1227         NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1228                              .addReg(Dest, RegState::Define |
1229                                      getDeadRegState(isDead)),
1230                              Src, isKill, MI->getOperand(2).getImm());
1231       break;
1232     case X86::SHL16ri:
1233       if (DisableLEA16) return 0;
1234     case X86::SHL32ri:
1235     case X86::SHL64ri: {
1236       assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
1237              "Unknown shl instruction!");
1238       unsigned ShAmt = MI->getOperand(2).getImm();
1239       if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1240         X86AddressMode AM;
1241         AM.Scale = 1 << ShAmt;
1242         AM.IndexReg = Src;
1243         unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1244           : (MIOpc == X86::SHL32ri
1245              ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1246         NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1247                                .addReg(Dest, RegState::Define |
1248                                        getDeadRegState(isDead)), AM);
1249         if (isKill)
1250           NewMI->getOperand(3).setIsKill(true);
1251       }
1252       break;
1253     }
1254     }
1255   }
1256   }
1257 
1258   if (!NewMI) return 0;
1259 
1260   if (LV) {  // Update live variables
1261     if (isKill)
1262       LV->replaceKillInstruction(Src, MI, NewMI);
1263     if (isDead)
1264       LV->replaceKillInstruction(Dest, MI, NewMI);
1265   }
1266 
1267   MFI->insert(MBBI, NewMI);          // Insert the new inst
1268   return NewMI;
1269 }
1270 
1271 /// commuteInstruction - We have a few instructions that must be hacked on to
1272 /// commute them.
1273 ///
1274 MachineInstr *
1275 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1276   switch (MI->getOpcode()) {
1277   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1278   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1279   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1280   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1281   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1282   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1283     unsigned Opc;
1284     unsigned Size;
1285     switch (MI->getOpcode()) {
1286     default: assert(0 && "Unreachable!");
1287     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1288     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1289     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1290     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1291     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1292     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1293     }
1294     unsigned Amt = MI->getOperand(3).getImm();
1295     if (NewMI) {
1296       MachineFunction &MF = *MI->getParent()->getParent();
1297       MI = MF.CloneMachineInstr(MI);
1298       NewMI = false;
1299     }
1300     MI->setDesc(get(Opc));
1301     MI->getOperand(3).setImm(Size-Amt);
1302     return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1303   }
1304   case X86::CMOVB16rr:
1305   case X86::CMOVB32rr:
1306   case X86::CMOVB64rr:
1307   case X86::CMOVAE16rr:
1308   case X86::CMOVAE32rr:
1309   case X86::CMOVAE64rr:
1310   case X86::CMOVE16rr:
1311   case X86::CMOVE32rr:
1312   case X86::CMOVE64rr:
1313   case X86::CMOVNE16rr:
1314   case X86::CMOVNE32rr:
1315   case X86::CMOVNE64rr:
1316   case X86::CMOVBE16rr:
1317   case X86::CMOVBE32rr:
1318   case X86::CMOVBE64rr:
1319   case X86::CMOVA16rr:
1320   case X86::CMOVA32rr:
1321   case X86::CMOVA64rr:
1322   case X86::CMOVL16rr:
1323   case X86::CMOVL32rr:
1324   case X86::CMOVL64rr:
1325   case X86::CMOVGE16rr:
1326   case X86::CMOVGE32rr:
1327   case X86::CMOVGE64rr:
1328   case X86::CMOVLE16rr:
1329   case X86::CMOVLE32rr:
1330   case X86::CMOVLE64rr:
1331   case X86::CMOVG16rr:
1332   case X86::CMOVG32rr:
1333   case X86::CMOVG64rr:
1334   case X86::CMOVS16rr:
1335   case X86::CMOVS32rr:
1336   case X86::CMOVS64rr:
1337   case X86::CMOVNS16rr:
1338   case X86::CMOVNS32rr:
1339   case X86::CMOVNS64rr:
1340   case X86::CMOVP16rr:
1341   case X86::CMOVP32rr:
1342   case X86::CMOVP64rr:
1343   case X86::CMOVNP16rr:
1344   case X86::CMOVNP32rr:
1345   case X86::CMOVNP64rr:
1346   case X86::CMOVO16rr:
1347   case X86::CMOVO32rr:
1348   case X86::CMOVO64rr:
1349   case X86::CMOVNO16rr:
1350   case X86::CMOVNO32rr:
1351   case X86::CMOVNO64rr: {
1352     unsigned Opc = 0;
1353     switch (MI->getOpcode()) {
1354     default: break;
1355     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
1356     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
1357     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
1358     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1359     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1360     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1361     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
1362     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
1363     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
1364     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1365     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1366     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1367     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1368     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1369     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1370     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
1371     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
1372     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
1373     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
1374     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
1375     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
1376     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1377     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1378     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1379     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1380     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1381     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1382     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
1383     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
1384     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
1385     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
1386     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
1387     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
1388     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1389     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1390     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1391     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
1392     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
1393     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
1394     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1395     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1396     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1397     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
1398     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
1399     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
1400     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1401     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1402     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1403     }
1404     if (NewMI) {
1405       MachineFunction &MF = *MI->getParent()->getParent();
1406       MI = MF.CloneMachineInstr(MI);
1407       NewMI = false;
1408     }
1409     MI->setDesc(get(Opc));
1410     // Fallthrough intended.
1411   }
1412   default:
1413     return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1414   }
1415 }
1416 
1417 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1418   switch (BrOpc) {
1419   default: return X86::COND_INVALID;
1420   case X86::JE:  return X86::COND_E;
1421   case X86::JNE: return X86::COND_NE;
1422   case X86::JL:  return X86::COND_L;
1423   case X86::JLE: return X86::COND_LE;
1424   case X86::JG:  return X86::COND_G;
1425   case X86::JGE: return X86::COND_GE;
1426   case X86::JB:  return X86::COND_B;
1427   case X86::JBE: return X86::COND_BE;
1428   case X86::JA:  return X86::COND_A;
1429   case X86::JAE: return X86::COND_AE;
1430   case X86::JS:  return X86::COND_S;
1431   case X86::JNS: return X86::COND_NS;
1432   case X86::JP:  return X86::COND_P;
1433   case X86::JNP: return X86::COND_NP;
1434   case X86::JO:  return X86::COND_O;
1435   case X86::JNO: return X86::COND_NO;
1436   }
1437 }
1438 
1439 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1440   switch (CC) {
1441   default: assert(0 && "Illegal condition code!");
1442   case X86::COND_E:  return X86::JE;
1443   case X86::COND_NE: return X86::JNE;
1444   case X86::COND_L:  return X86::JL;
1445   case X86::COND_LE: return X86::JLE;
1446   case X86::COND_G:  return X86::JG;
1447   case X86::COND_GE: return X86::JGE;
1448   case X86::COND_B:  return X86::JB;
1449   case X86::COND_BE: return X86::JBE;
1450   case X86::COND_A:  return X86::JA;
1451   case X86::COND_AE: return X86::JAE;
1452   case X86::COND_S:  return X86::JS;
1453   case X86::COND_NS: return X86::JNS;
1454   case X86::COND_P:  return X86::JP;
1455   case X86::COND_NP: return X86::JNP;
1456   case X86::COND_O:  return X86::JO;
1457   case X86::COND_NO: return X86::JNO;
1458   }
1459 }
1460 
1461 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1462 /// e.g. turning COND_E to COND_NE.
1463 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1464   switch (CC) {
1465   default: assert(0 && "Illegal condition code!");
1466   case X86::COND_E:  return X86::COND_NE;
1467   case X86::COND_NE: return X86::COND_E;
1468   case X86::COND_L:  return X86::COND_GE;
1469   case X86::COND_LE: return X86::COND_G;
1470   case X86::COND_G:  return X86::COND_LE;
1471   case X86::COND_GE: return X86::COND_L;
1472   case X86::COND_B:  return X86::COND_AE;
1473   case X86::COND_BE: return X86::COND_A;
1474   case X86::COND_A:  return X86::COND_BE;
1475   case X86::COND_AE: return X86::COND_B;
1476   case X86::COND_S:  return X86::COND_NS;
1477   case X86::COND_NS: return X86::COND_S;
1478   case X86::COND_P:  return X86::COND_NP;
1479   case X86::COND_NP: return X86::COND_P;
1480   case X86::COND_O:  return X86::COND_NO;
1481   case X86::COND_NO: return X86::COND_O;
1482   }
1483 }
1484 
1485 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1486   const TargetInstrDesc &TID = MI->getDesc();
1487   if (!TID.isTerminator()) return false;
1488 
1489   // Conditional branch is a special case.
1490   if (TID.isBranch() && !TID.isBarrier())
1491     return true;
1492   if (!TID.isPredicable())
1493     return true;
1494   return !isPredicated(MI);
1495 }
1496 
1497 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1498 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1499                                                const X86InstrInfo &TII) {
1500   if (MI->getOpcode() == X86::FP_REG_KILL)
1501     return false;
1502   return TII.isUnpredicatedTerminator(MI);
1503 }
1504 
1505 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1506                                  MachineBasicBlock *&TBB,
1507                                  MachineBasicBlock *&FBB,
1508                                  SmallVectorImpl<MachineOperand> &Cond,
1509                                  bool AllowModify) const {
1510   // Start from the bottom of the block and work up, examining the
1511   // terminator instructions.
1512   MachineBasicBlock::iterator I = MBB.end();
1513   while (I != MBB.begin()) {
1514     --I;
1515     // Working from the bottom, when we see a non-terminator
1516     // instruction, we're done.
1517     if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1518       break;
1519     // A terminator that isn't a branch can't easily be handled
1520     // by this analysis.
1521     if (!I->getDesc().isBranch())
1522       return true;
1523     // Handle unconditional branches.
1524     if (I->getOpcode() == X86::JMP) {
1525       if (!AllowModify) {
1526         TBB = I->getOperand(0).getMBB();
1527         continue;
1528       }
1529 
1530       // If the block has any instructions after a JMP, delete them.
1531       while (next(I) != MBB.end())
1532         next(I)->eraseFromParent();
1533       Cond.clear();
1534       FBB = 0;
1535       // Delete the JMP if it's equivalent to a fall-through.
1536       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1537         TBB = 0;
1538         I->eraseFromParent();
1539         I = MBB.end();
1540         continue;
1541       }
1542       // TBB is used to indicate the unconditinal destination.
1543       TBB = I->getOperand(0).getMBB();
1544       continue;
1545     }
1546     // Handle conditional branches.
1547     X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1548     if (BranchCode == X86::COND_INVALID)
1549       return true;  // Can't handle indirect branch.
1550     // Working from the bottom, handle the first conditional branch.
1551     if (Cond.empty()) {
1552       FBB = TBB;
1553       TBB = I->getOperand(0).getMBB();
1554       Cond.push_back(MachineOperand::CreateImm(BranchCode));
1555       continue;
1556     }
1557     // Handle subsequent conditional branches. Only handle the case
1558     // where all conditional branches branch to the same destination
1559     // and their condition opcodes fit one of the special
1560     // multi-branch idioms.
1561     assert(Cond.size() == 1);
1562     assert(TBB);
1563     // Only handle the case where all conditional branches branch to
1564     // the same destination.
1565     if (TBB != I->getOperand(0).getMBB())
1566       return true;
1567     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1568     // If the conditions are the same, we can leave them alone.
1569     if (OldBranchCode == BranchCode)
1570       continue;
1571     // If they differ, see if they fit one of the known patterns.
1572     // Theoretically we could handle more patterns here, but
1573     // we shouldn't expect to see them if instruction selection
1574     // has done a reasonable job.
1575     if ((OldBranchCode == X86::COND_NP &&
1576          BranchCode == X86::COND_E) ||
1577         (OldBranchCode == X86::COND_E &&
1578          BranchCode == X86::COND_NP))
1579       BranchCode = X86::COND_NP_OR_E;
1580     else if ((OldBranchCode == X86::COND_P &&
1581               BranchCode == X86::COND_NE) ||
1582              (OldBranchCode == X86::COND_NE &&
1583               BranchCode == X86::COND_P))
1584       BranchCode = X86::COND_NE_OR_P;
1585     else
1586       return true;
1587     // Update the MachineOperand.
1588     Cond[0].setImm(BranchCode);
1589   }
1590 
1591   return false;
1592 }
1593 
1594 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1595   MachineBasicBlock::iterator I = MBB.end();
1596   unsigned Count = 0;
1597 
1598   while (I != MBB.begin()) {
1599     --I;
1600     if (I->getOpcode() != X86::JMP &&
1601         GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1602       break;
1603     // Remove the branch.
1604     I->eraseFromParent();
1605     I = MBB.end();
1606     ++Count;
1607   }
1608 
1609   return Count;
1610 }
1611 
1612 unsigned
1613 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1614                            MachineBasicBlock *FBB,
1615                            const SmallVectorImpl<MachineOperand> &Cond) const {
1616   // FIXME this should probably have a DebugLoc operand
1617   DebugLoc dl = DebugLoc::getUnknownLoc();
1618   // Shouldn't be a fall through.
1619   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1620   assert((Cond.size() == 1 || Cond.size() == 0) &&
1621          "X86 branch conditions have one component!");
1622 
1623   if (Cond.empty()) {
1624     // Unconditional branch?
1625     assert(!FBB && "Unconditional branch with multiple successors!");
1626     BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
1627     return 1;
1628   }
1629 
1630   // Conditional branch.
1631   unsigned Count = 0;
1632   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1633   switch (CC) {
1634   case X86::COND_NP_OR_E:
1635     // Synthesize NP_OR_E with two branches.
1636     BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
1637     ++Count;
1638     BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
1639     ++Count;
1640     break;
1641   case X86::COND_NE_OR_P:
1642     // Synthesize NE_OR_P with two branches.
1643     BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
1644     ++Count;
1645     BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
1646     ++Count;
1647     break;
1648   default: {
1649     unsigned Opc = GetCondBranchFromCond(CC);
1650     BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1651     ++Count;
1652   }
1653   }
1654   if (FBB) {
1655     // Two-way Conditional branch. Insert the second branch.
1656     BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
1657     ++Count;
1658   }
1659   return Count;
1660 }
1661 
1662 /// isHReg - Test if the given register is a physical h register.
1663 static bool isHReg(unsigned Reg) {
1664   return X86::GR8_ABCD_HRegClass.contains(Reg);
1665 }
1666 
1667 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1668                                 MachineBasicBlock::iterator MI,
1669                                 unsigned DestReg, unsigned SrcReg,
1670                                 const TargetRegisterClass *DestRC,
1671                                 const TargetRegisterClass *SrcRC) const {
1672   DebugLoc DL = DebugLoc::getUnknownLoc();
1673   if (MI != MBB.end()) DL = MI->getDebugLoc();
1674 
1675   // Determine if DstRC and SrcRC have a common superclass in common.
1676   const TargetRegisterClass *CommonRC = DestRC;
1677   if (DestRC == SrcRC)
1678     /* Source and destination have the same register class. */;
1679   else if (CommonRC->hasSuperClass(SrcRC))
1680     CommonRC = SrcRC;
1681   else if (!DestRC->hasSubClass(SrcRC))
1682     CommonRC = 0;
1683 
1684   if (CommonRC) {
1685     unsigned Opc;
1686     if (CommonRC == &X86::GR64RegClass) {
1687       Opc = X86::MOV64rr;
1688     } else if (CommonRC == &X86::GR32RegClass) {
1689       Opc = X86::MOV32rr;
1690     } else if (CommonRC == &X86::GR16RegClass) {
1691       Opc = X86::MOV16rr;
1692     } else if (CommonRC == &X86::GR8RegClass) {
1693       // Copying to or from a physical H register on x86-64 requires a NOREX
1694       // move.  Otherwise use a normal move.
1695       if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1696           TM.getSubtarget<X86Subtarget>().is64Bit())
1697         Opc = X86::MOV8rr_NOREX;
1698       else
1699         Opc = X86::MOV8rr;
1700     } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1701       Opc = X86::MOV64rr;
1702     } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1703       Opc = X86::MOV32rr;
1704     } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1705       Opc = X86::MOV16rr;
1706     } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1707       Opc = X86::MOV8rr;
1708     } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1709       if (TM.getSubtarget<X86Subtarget>().is64Bit())
1710         Opc = X86::MOV8rr_NOREX;
1711       else
1712         Opc = X86::MOV8rr;
1713     } else if (CommonRC == &X86::GR64_NOREXRegClass) {
1714       Opc = X86::MOV64rr;
1715     } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1716       Opc = X86::MOV32rr;
1717     } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1718       Opc = X86::MOV16rr;
1719     } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1720       Opc = X86::MOV8rr;
1721     } else if (CommonRC == &X86::RFP32RegClass) {
1722       Opc = X86::MOV_Fp3232;
1723     } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1724       Opc = X86::MOV_Fp6464;
1725     } else if (CommonRC == &X86::RFP80RegClass) {
1726       Opc = X86::MOV_Fp8080;
1727     } else if (CommonRC == &X86::FR32RegClass) {
1728       Opc = X86::FsMOVAPSrr;
1729     } else if (CommonRC == &X86::FR64RegClass) {
1730       Opc = X86::FsMOVAPDrr;
1731     } else if (CommonRC == &X86::VR128RegClass) {
1732       Opc = X86::MOVAPSrr;
1733     } else if (CommonRC == &X86::VR64RegClass) {
1734       Opc = X86::MMX_MOVQ64rr;
1735     } else {
1736       return false;
1737     }
1738     BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1739     return true;
1740   }
1741 
1742   // Moving EFLAGS to / from another register requires a push and a pop.
1743   if (SrcRC == &X86::CCRRegClass) {
1744     if (SrcReg != X86::EFLAGS)
1745       return false;
1746     if (DestRC == &X86::GR64RegClass) {
1747       BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
1748       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1749       return true;
1750     } else if (DestRC == &X86::GR32RegClass) {
1751       BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1752       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1753       return true;
1754     }
1755   } else if (DestRC == &X86::CCRRegClass) {
1756     if (DestReg != X86::EFLAGS)
1757       return false;
1758     if (SrcRC == &X86::GR64RegClass) {
1759       BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1760       BuildMI(MBB, MI, DL, get(X86::POPFQ));
1761       return true;
1762     } else if (SrcRC == &X86::GR32RegClass) {
1763       BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1764       BuildMI(MBB, MI, DL, get(X86::POPFD));
1765       return true;
1766     }
1767   }
1768 
1769   // Moving from ST(0) turns into FpGET_ST0_32 etc.
1770   if (SrcRC == &X86::RSTRegClass) {
1771     // Copying from ST(0)/ST(1).
1772     if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1773       // Can only copy from ST(0)/ST(1) right now
1774       return false;
1775     bool isST0 = SrcReg == X86::ST0;
1776     unsigned Opc;
1777     if (DestRC == &X86::RFP32RegClass)
1778       Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1779     else if (DestRC == &X86::RFP64RegClass)
1780       Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1781     else {
1782       if (DestRC != &X86::RFP80RegClass)
1783         return false;
1784       Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1785     }
1786     BuildMI(MBB, MI, DL, get(Opc), DestReg);
1787     return true;
1788   }
1789 
1790   // Moving to ST(0) turns into FpSET_ST0_32 etc.
1791   if (DestRC == &X86::RSTRegClass) {
1792     // Copying to ST(0) / ST(1).
1793     if (DestReg != X86::ST0 && DestReg != X86::ST1)
1794       // Can only copy to TOS right now
1795       return false;
1796     bool isST0 = DestReg == X86::ST0;
1797     unsigned Opc;
1798     if (SrcRC == &X86::RFP32RegClass)
1799       Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1800     else if (SrcRC == &X86::RFP64RegClass)
1801       Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1802     else {
1803       if (SrcRC != &X86::RFP80RegClass)
1804         return false;
1805       Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1806     }
1807     BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1808     return true;
1809   }
1810 
1811   // Not yet supported!
1812   return false;
1813 }
1814 
1815 static unsigned getStoreRegOpcode(unsigned SrcReg,
1816                                   const TargetRegisterClass *RC,
1817                                   bool isStackAligned,
1818                                   TargetMachine &TM) {
1819   unsigned Opc = 0;
1820   if (RC == &X86::GR64RegClass) {
1821     Opc = X86::MOV64mr;
1822   } else if (RC == &X86::GR32RegClass) {
1823     Opc = X86::MOV32mr;
1824   } else if (RC == &X86::GR16RegClass) {
1825     Opc = X86::MOV16mr;
1826   } else if (RC == &X86::GR8RegClass) {
1827     // Copying to or from a physical H register on x86-64 requires a NOREX
1828     // move.  Otherwise use a normal move.
1829     if (isHReg(SrcReg) &&
1830         TM.getSubtarget<X86Subtarget>().is64Bit())
1831       Opc = X86::MOV8mr_NOREX;
1832     else
1833       Opc = X86::MOV8mr;
1834   } else if (RC == &X86::GR64_ABCDRegClass) {
1835     Opc = X86::MOV64mr;
1836   } else if (RC == &X86::GR32_ABCDRegClass) {
1837     Opc = X86::MOV32mr;
1838   } else if (RC == &X86::GR16_ABCDRegClass) {
1839     Opc = X86::MOV16mr;
1840   } else if (RC == &X86::GR8_ABCD_LRegClass) {
1841     Opc = X86::MOV8mr;
1842   } else if (RC == &X86::GR8_ABCD_HRegClass) {
1843     if (TM.getSubtarget<X86Subtarget>().is64Bit())
1844       Opc = X86::MOV8mr_NOREX;
1845     else
1846       Opc = X86::MOV8mr;
1847   } else if (RC == &X86::GR64_NOREXRegClass) {
1848     Opc = X86::MOV64mr;
1849   } else if (RC == &X86::GR32_NOREXRegClass) {
1850     Opc = X86::MOV32mr;
1851   } else if (RC == &X86::GR16_NOREXRegClass) {
1852     Opc = X86::MOV16mr;
1853   } else if (RC == &X86::GR8_NOREXRegClass) {
1854     Opc = X86::MOV8mr;
1855   } else if (RC == &X86::RFP80RegClass) {
1856     Opc = X86::ST_FpP80m;   // pops
1857   } else if (RC == &X86::RFP64RegClass) {
1858     Opc = X86::ST_Fp64m;
1859   } else if (RC == &X86::RFP32RegClass) {
1860     Opc = X86::ST_Fp32m;
1861   } else if (RC == &X86::FR32RegClass) {
1862     Opc = X86::MOVSSmr;
1863   } else if (RC == &X86::FR64RegClass) {
1864     Opc = X86::MOVSDmr;
1865   } else if (RC == &X86::VR128RegClass) {
1866     // If stack is realigned we can use aligned stores.
1867     Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1868   } else if (RC == &X86::VR64RegClass) {
1869     Opc = X86::MMX_MOVQ64mr;
1870   } else {
1871     assert(0 && "Unknown regclass");
1872     abort();
1873   }
1874 
1875   return Opc;
1876 }
1877 
1878 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1879                                        MachineBasicBlock::iterator MI,
1880                                        unsigned SrcReg, bool isKill, int FrameIdx,
1881                                        const TargetRegisterClass *RC) const {
1882   const MachineFunction &MF = *MBB.getParent();
1883   bool isAligned = (RI.getStackAlignment() >= 16) ||
1884     RI.needsStackRealignment(MF);
1885   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1886   DebugLoc DL = DebugLoc::getUnknownLoc();
1887   if (MI != MBB.end()) DL = MI->getDebugLoc();
1888   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
1889     .addReg(SrcReg, getKillRegState(isKill));
1890 }
1891 
1892 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1893                                   bool isKill,
1894                                   SmallVectorImpl<MachineOperand> &Addr,
1895                                   const TargetRegisterClass *RC,
1896                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
1897   bool isAligned = (RI.getStackAlignment() >= 16) ||
1898     RI.needsStackRealignment(MF);
1899   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1900   DebugLoc DL = DebugLoc::getUnknownLoc();
1901   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
1902   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1903     MIB.addOperand(Addr[i]);
1904   MIB.addReg(SrcReg, getKillRegState(isKill));
1905   NewMIs.push_back(MIB);
1906 }
1907 
1908 static unsigned getLoadRegOpcode(unsigned DestReg,
1909                                  const TargetRegisterClass *RC,
1910                                  bool isStackAligned,
1911                                  const TargetMachine &TM) {
1912   unsigned Opc = 0;
1913   if (RC == &X86::GR64RegClass) {
1914     Opc = X86::MOV64rm;
1915   } else if (RC == &X86::GR32RegClass) {
1916     Opc = X86::MOV32rm;
1917   } else if (RC == &X86::GR16RegClass) {
1918     Opc = X86::MOV16rm;
1919   } else if (RC == &X86::GR8RegClass) {
1920     // Copying to or from a physical H register on x86-64 requires a NOREX
1921     // move.  Otherwise use a normal move.
1922     if (isHReg(DestReg) &&
1923         TM.getSubtarget<X86Subtarget>().is64Bit())
1924       Opc = X86::MOV8rm_NOREX;
1925     else
1926       Opc = X86::MOV8rm;
1927   } else if (RC == &X86::GR64_ABCDRegClass) {
1928     Opc = X86::MOV64rm;
1929   } else if (RC == &X86::GR32_ABCDRegClass) {
1930     Opc = X86::MOV32rm;
1931   } else if (RC == &X86::GR16_ABCDRegClass) {
1932     Opc = X86::MOV16rm;
1933   } else if (RC == &X86::GR8_ABCD_LRegClass) {
1934     Opc = X86::MOV8rm;
1935   } else if (RC == &X86::GR8_ABCD_HRegClass) {
1936     if (TM.getSubtarget<X86Subtarget>().is64Bit())
1937       Opc = X86::MOV8rm_NOREX;
1938     else
1939       Opc = X86::MOV8rm;
1940   } else if (RC == &X86::GR64_NOREXRegClass) {
1941     Opc = X86::MOV64rm;
1942   } else if (RC == &X86::GR32_NOREXRegClass) {
1943     Opc = X86::MOV32rm;
1944   } else if (RC == &X86::GR16_NOREXRegClass) {
1945     Opc = X86::MOV16rm;
1946   } else if (RC == &X86::GR8_NOREXRegClass) {
1947     Opc = X86::MOV8rm;
1948   } else if (RC == &X86::RFP80RegClass) {
1949     Opc = X86::LD_Fp80m;
1950   } else if (RC == &X86::RFP64RegClass) {
1951     Opc = X86::LD_Fp64m;
1952   } else if (RC == &X86::RFP32RegClass) {
1953     Opc = X86::LD_Fp32m;
1954   } else if (RC == &X86::FR32RegClass) {
1955     Opc = X86::MOVSSrm;
1956   } else if (RC == &X86::FR64RegClass) {
1957     Opc = X86::MOVSDrm;
1958   } else if (RC == &X86::VR128RegClass) {
1959     // If stack is realigned we can use aligned loads.
1960     Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
1961   } else if (RC == &X86::VR64RegClass) {
1962     Opc = X86::MMX_MOVQ64rm;
1963   } else {
1964     assert(0 && "Unknown regclass");
1965     abort();
1966   }
1967 
1968   return Opc;
1969 }
1970 
1971 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1972                                         MachineBasicBlock::iterator MI,
1973                                         unsigned DestReg, int FrameIdx,
1974                                         const TargetRegisterClass *RC) const{
1975   const MachineFunction &MF = *MBB.getParent();
1976   bool isAligned = (RI.getStackAlignment() >= 16) ||
1977     RI.needsStackRealignment(MF);
1978   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
1979   DebugLoc DL = DebugLoc::getUnknownLoc();
1980   if (MI != MBB.end()) DL = MI->getDebugLoc();
1981   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
1982 }
1983 
1984 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
1985                                  SmallVectorImpl<MachineOperand> &Addr,
1986                                  const TargetRegisterClass *RC,
1987                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
1988   bool isAligned = (RI.getStackAlignment() >= 16) ||
1989     RI.needsStackRealignment(MF);
1990   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
1991   DebugLoc DL = DebugLoc::getUnknownLoc();
1992   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
1993   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1994     MIB.addOperand(Addr[i]);
1995   NewMIs.push_back(MIB);
1996 }
1997 
1998 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1999                                              MachineBasicBlock::iterator MI,
2000                                 const std::vector<CalleeSavedInfo> &CSI) const {
2001   if (CSI.empty())
2002     return false;
2003 
2004   DebugLoc DL = DebugLoc::getUnknownLoc();
2005   if (MI != MBB.end()) DL = MI->getDebugLoc();
2006 
2007   bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2008   unsigned SlotSize = is64Bit ? 8 : 4;
2009 
2010   MachineFunction &MF = *MBB.getParent();
2011   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2012   unsigned CalleeFrameSize = 0;
2013 
2014   unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2015   for (unsigned i = CSI.size(); i != 0; --i) {
2016     unsigned Reg = CSI[i-1].getReg();
2017     const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2018     // Add the callee-saved register as live-in. It's killed at the spill.
2019     MBB.addLiveIn(Reg);
2020     if (RegClass != &X86::VR128RegClass) {
2021       CalleeFrameSize += SlotSize;
2022       BuildMI(MBB, MI, DL, get(Opc))
2023         .addReg(Reg, RegState::Kill);
2024     } else {
2025       storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2026     }
2027   }
2028 
2029   X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2030   return true;
2031 }
2032 
2033 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2034                                                MachineBasicBlock::iterator MI,
2035                                 const std::vector<CalleeSavedInfo> &CSI) const {
2036   if (CSI.empty())
2037     return false;
2038 
2039   DebugLoc DL = DebugLoc::getUnknownLoc();
2040   if (MI != MBB.end()) DL = MI->getDebugLoc();
2041 
2042   bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2043 
2044   unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2045   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2046     unsigned Reg = CSI[i].getReg();
2047     const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2048     if (RegClass != &X86::VR128RegClass) {
2049       BuildMI(MBB, MI, DL, get(Opc), Reg);
2050     } else {
2051       loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2052     }
2053   }
2054   return true;
2055 }
2056 
2057 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2058                                      const SmallVectorImpl<MachineOperand> &MOs,
2059                                      MachineInstr *MI,
2060                                      const TargetInstrInfo &TII) {
2061   // Create the base instruction with the memory operand as the first part.
2062   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2063                                               MI->getDebugLoc(), true);
2064   MachineInstrBuilder MIB(NewMI);
2065   unsigned NumAddrOps = MOs.size();
2066   for (unsigned i = 0; i != NumAddrOps; ++i)
2067     MIB.addOperand(MOs[i]);
2068   if (NumAddrOps < 4)  // FrameIndex only
2069     addOffset(MIB, 0);
2070 
2071   // Loop over the rest of the ri operands, converting them over.
2072   unsigned NumOps = MI->getDesc().getNumOperands()-2;
2073   for (unsigned i = 0; i != NumOps; ++i) {
2074     MachineOperand &MO = MI->getOperand(i+2);
2075     MIB.addOperand(MO);
2076   }
2077   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2078     MachineOperand &MO = MI->getOperand(i);
2079     MIB.addOperand(MO);
2080   }
2081   return MIB;
2082 }
2083 
2084 static MachineInstr *FuseInst(MachineFunction &MF,
2085                               unsigned Opcode, unsigned OpNo,
2086                               const SmallVectorImpl<MachineOperand> &MOs,
2087                               MachineInstr *MI, const TargetInstrInfo &TII) {
2088   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2089                                               MI->getDebugLoc(), true);
2090   MachineInstrBuilder MIB(NewMI);
2091 
2092   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2093     MachineOperand &MO = MI->getOperand(i);
2094     if (i == OpNo) {
2095       assert(MO.isReg() && "Expected to fold into reg operand!");
2096       unsigned NumAddrOps = MOs.size();
2097       for (unsigned i = 0; i != NumAddrOps; ++i)
2098         MIB.addOperand(MOs[i]);
2099       if (NumAddrOps < 4)  // FrameIndex only
2100         addOffset(MIB, 0);
2101     } else {
2102       MIB.addOperand(MO);
2103     }
2104   }
2105   return MIB;
2106 }
2107 
2108 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2109                                 const SmallVectorImpl<MachineOperand> &MOs,
2110                                 MachineInstr *MI) {
2111   MachineFunction &MF = *MI->getParent()->getParent();
2112   MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2113 
2114   unsigned NumAddrOps = MOs.size();
2115   for (unsigned i = 0; i != NumAddrOps; ++i)
2116     MIB.addOperand(MOs[i]);
2117   if (NumAddrOps < 4)  // FrameIndex only
2118     addOffset(MIB, 0);
2119   return MIB.addImm(0);
2120 }
2121 
2122 MachineInstr*
2123 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2124                                     MachineInstr *MI, unsigned i,
2125                                     const SmallVectorImpl<MachineOperand> &MOs) const{
2126   const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
2127   bool isTwoAddrFold = false;
2128   unsigned NumOps = MI->getDesc().getNumOperands();
2129   bool isTwoAddr = NumOps > 1 &&
2130     MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2131 
2132   MachineInstr *NewMI = NULL;
2133   // Folding a memory location into the two-address part of a two-address
2134   // instruction is different than folding it other places.  It requires
2135   // replacing the *two* registers with the memory location.
2136   if (isTwoAddr && NumOps >= 2 && i < 2 &&
2137       MI->getOperand(0).isReg() &&
2138       MI->getOperand(1).isReg() &&
2139       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2140     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2141     isTwoAddrFold = true;
2142   } else if (i == 0) { // If operand 0
2143     if (MI->getOpcode() == X86::MOV16r0)
2144       NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2145     else if (MI->getOpcode() == X86::MOV32r0)
2146       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2147     else if (MI->getOpcode() == X86::MOV64r0)
2148       NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2149     else if (MI->getOpcode() == X86::MOV8r0)
2150       NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2151     if (NewMI)
2152       return NewMI;
2153 
2154     OpcodeTablePtr = &RegOp2MemOpTable0;
2155   } else if (i == 1) {
2156     OpcodeTablePtr = &RegOp2MemOpTable1;
2157   } else if (i == 2) {
2158     OpcodeTablePtr = &RegOp2MemOpTable2;
2159   }
2160 
2161   // If table selected...
2162   if (OpcodeTablePtr) {
2163     // Find the Opcode to fuse
2164     DenseMap<unsigned*, unsigned>::iterator I =
2165       OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2166     if (I != OpcodeTablePtr->end()) {
2167       if (isTwoAddrFold)
2168         NewMI = FuseTwoAddrInst(MF, I->second, MOs, MI, *this);
2169       else
2170         NewMI = FuseInst(MF, I->second, i, MOs, MI, *this);
2171       return NewMI;
2172     }
2173   }
2174 
2175   // No fusion
2176   if (PrintFailedFusing)
2177     cerr << "We failed to fuse operand " << i << " in " << *MI;
2178   return NULL;
2179 }
2180 
2181 
2182 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2183                                                   MachineInstr *MI,
2184                                                   const SmallVectorImpl<unsigned> &Ops,
2185                                                   int FrameIndex) const {
2186   // Check switch flag
2187   if (NoFusing) return NULL;
2188 
2189   const MachineFrameInfo *MFI = MF.getFrameInfo();
2190   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2191   // FIXME: Move alignment requirement into tables?
2192   if (Alignment < 16) {
2193     switch (MI->getOpcode()) {
2194     default: break;
2195     // Not always safe to fold movsd into these instructions since their load
2196     // folding variants expects the address to be 16 byte aligned.
2197     case X86::FsANDNPDrr:
2198     case X86::FsANDNPSrr:
2199     case X86::FsANDPDrr:
2200     case X86::FsANDPSrr:
2201     case X86::FsORPDrr:
2202     case X86::FsORPSrr:
2203     case X86::FsXORPDrr:
2204     case X86::FsXORPSrr:
2205       return NULL;
2206     }
2207   }
2208 
2209   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2210     unsigned NewOpc = 0;
2211     switch (MI->getOpcode()) {
2212     default: return NULL;
2213     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
2214     case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2215     case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2216     case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2217     }
2218     // Change to CMPXXri r, 0 first.
2219     MI->setDesc(get(NewOpc));
2220     MI->getOperand(1).ChangeToImmediate(0);
2221   } else if (Ops.size() != 1)
2222     return NULL;
2223 
2224   SmallVector<MachineOperand,4> MOs;
2225   MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2226   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs);
2227 }
2228 
2229 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2230                                                   MachineInstr *MI,
2231                                             const SmallVectorImpl<unsigned> &Ops,
2232                                                   MachineInstr *LoadMI) const {
2233   // Check switch flag
2234   if (NoFusing) return NULL;
2235 
2236   // Determine the alignment of the load.
2237   unsigned Alignment = 0;
2238   if (LoadMI->hasOneMemOperand())
2239     Alignment = LoadMI->memoperands_begin()->getAlignment();
2240 
2241   // FIXME: Move alignment requirement into tables?
2242   if (Alignment < 16) {
2243     switch (MI->getOpcode()) {
2244     default: break;
2245     // Not always safe to fold movsd into these instructions since their load
2246     // folding variants expects the address to be 16 byte aligned.
2247     case X86::FsANDNPDrr:
2248     case X86::FsANDNPSrr:
2249     case X86::FsANDPDrr:
2250     case X86::FsANDPSrr:
2251     case X86::FsORPDrr:
2252     case X86::FsORPSrr:
2253     case X86::FsXORPDrr:
2254     case X86::FsXORPSrr:
2255       return NULL;
2256     }
2257   }
2258 
2259   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2260     unsigned NewOpc = 0;
2261     switch (MI->getOpcode()) {
2262     default: return NULL;
2263     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
2264     case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2265     case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2266     case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2267     }
2268     // Change to CMPXXri r, 0 first.
2269     MI->setDesc(get(NewOpc));
2270     MI->getOperand(1).ChangeToImmediate(0);
2271   } else if (Ops.size() != 1)
2272     return NULL;
2273 
2274   SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2275   if (LoadMI->getOpcode() == X86::V_SET0 ||
2276       LoadMI->getOpcode() == X86::V_SETALLONES) {
2277     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2278     // Create a constant-pool entry and operands to load from it.
2279 
2280     // x86-32 PIC requires a PIC base register for constant pools.
2281     unsigned PICBase = 0;
2282     if (TM.getRelocationModel() == Reloc::PIC_ &&
2283         !TM.getSubtarget<X86Subtarget>().is64Bit())
2284       // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2285       // This doesn't work for several reasons.
2286       // 1. GlobalBaseReg may have been spilled.
2287       // 2. It may not be live at MI.
2288       return false;
2289 
2290     // Create a v4i32 constant-pool entry.
2291     MachineConstantPool &MCP = *MF.getConstantPool();
2292     const VectorType *Ty = VectorType::get(Type::Int32Ty, 4);
2293     Constant *C = LoadMI->getOpcode() == X86::V_SET0 ?
2294                     ConstantVector::getNullValue(Ty) :
2295                     ConstantVector::getAllOnesValue(Ty);
2296     unsigned CPI = MCP.getConstantPoolIndex(C, 16);
2297 
2298     // Create operands to load from the constant pool entry.
2299     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2300     MOs.push_back(MachineOperand::CreateImm(1));
2301     MOs.push_back(MachineOperand::CreateReg(0, false));
2302     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2303     MOs.push_back(MachineOperand::CreateReg(0, false));
2304   } else {
2305     // Folding a normal load. Just copy the load's address operands.
2306     unsigned NumOps = LoadMI->getDesc().getNumOperands();
2307     for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2308       MOs.push_back(LoadMI->getOperand(i));
2309   }
2310   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs);
2311 }
2312 
2313 
2314 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2315                                   const SmallVectorImpl<unsigned> &Ops) const {
2316   // Check switch flag
2317   if (NoFusing) return 0;
2318 
2319   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2320     switch (MI->getOpcode()) {
2321     default: return false;
2322     case X86::TEST8rr:
2323     case X86::TEST16rr:
2324     case X86::TEST32rr:
2325     case X86::TEST64rr:
2326       return true;
2327     }
2328   }
2329 
2330   if (Ops.size() != 1)
2331     return false;
2332 
2333   unsigned OpNum = Ops[0];
2334   unsigned Opc = MI->getOpcode();
2335   unsigned NumOps = MI->getDesc().getNumOperands();
2336   bool isTwoAddr = NumOps > 1 &&
2337     MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2338 
2339   // Folding a memory location into the two-address part of a two-address
2340   // instruction is different than folding it other places.  It requires
2341   // replacing the *two* registers with the memory location.
2342   const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
2343   if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2344     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2345   } else if (OpNum == 0) { // If operand 0
2346     switch (Opc) {
2347     case X86::MOV16r0:
2348     case X86::MOV32r0:
2349     case X86::MOV64r0:
2350     case X86::MOV8r0:
2351       return true;
2352     default: break;
2353     }
2354     OpcodeTablePtr = &RegOp2MemOpTable0;
2355   } else if (OpNum == 1) {
2356     OpcodeTablePtr = &RegOp2MemOpTable1;
2357   } else if (OpNum == 2) {
2358     OpcodeTablePtr = &RegOp2MemOpTable2;
2359   }
2360 
2361   if (OpcodeTablePtr) {
2362     // Find the Opcode to fuse
2363     DenseMap<unsigned*, unsigned>::iterator I =
2364       OpcodeTablePtr->find((unsigned*)Opc);
2365     if (I != OpcodeTablePtr->end())
2366       return true;
2367   }
2368   return false;
2369 }
2370 
2371 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2372                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2373                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2374   DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2375     MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2376   if (I == MemOp2RegOpTable.end())
2377     return false;
2378   DebugLoc dl = MI->getDebugLoc();
2379   unsigned Opc = I->second.first;
2380   unsigned Index = I->second.second & 0xf;
2381   bool FoldedLoad = I->second.second & (1 << 4);
2382   bool FoldedStore = I->second.second & (1 << 5);
2383   if (UnfoldLoad && !FoldedLoad)
2384     return false;
2385   UnfoldLoad &= FoldedLoad;
2386   if (UnfoldStore && !FoldedStore)
2387     return false;
2388   UnfoldStore &= FoldedStore;
2389 
2390   const TargetInstrDesc &TID = get(Opc);
2391   const TargetOperandInfo &TOI = TID.OpInfo[Index];
2392   const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2393     ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2394   SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2395   SmallVector<MachineOperand,2> BeforeOps;
2396   SmallVector<MachineOperand,2> AfterOps;
2397   SmallVector<MachineOperand,4> ImpOps;
2398   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2399     MachineOperand &Op = MI->getOperand(i);
2400     if (i >= Index && i < Index + X86AddrNumOperands)
2401       AddrOps.push_back(Op);
2402     else if (Op.isReg() && Op.isImplicit())
2403       ImpOps.push_back(Op);
2404     else if (i < Index)
2405       BeforeOps.push_back(Op);
2406     else if (i > Index)
2407       AfterOps.push_back(Op);
2408   }
2409 
2410   // Emit the load instruction.
2411   if (UnfoldLoad) {
2412     loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
2413     if (UnfoldStore) {
2414       // Address operands cannot be marked isKill.
2415       for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2416         MachineOperand &MO = NewMIs[0]->getOperand(i);
2417         if (MO.isReg())
2418           MO.setIsKill(false);
2419       }
2420     }
2421   }
2422 
2423   // Emit the data processing instruction.
2424   MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2425   MachineInstrBuilder MIB(DataMI);
2426 
2427   if (FoldedStore)
2428     MIB.addReg(Reg, RegState::Define);
2429   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2430     MIB.addOperand(BeforeOps[i]);
2431   if (FoldedLoad)
2432     MIB.addReg(Reg);
2433   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2434     MIB.addOperand(AfterOps[i]);
2435   for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2436     MachineOperand &MO = ImpOps[i];
2437     MIB.addReg(MO.getReg(),
2438                getDefRegState(MO.isDef()) |
2439                RegState::Implicit |
2440                getKillRegState(MO.isKill()) |
2441                getDeadRegState(MO.isDead()));
2442   }
2443   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2444   unsigned NewOpc = 0;
2445   switch (DataMI->getOpcode()) {
2446   default: break;
2447   case X86::CMP64ri32:
2448   case X86::CMP32ri:
2449   case X86::CMP16ri:
2450   case X86::CMP8ri: {
2451     MachineOperand &MO0 = DataMI->getOperand(0);
2452     MachineOperand &MO1 = DataMI->getOperand(1);
2453     if (MO1.getImm() == 0) {
2454       switch (DataMI->getOpcode()) {
2455       default: break;
2456       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2457       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
2458       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
2459       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
2460       }
2461       DataMI->setDesc(get(NewOpc));
2462       MO1.ChangeToRegister(MO0.getReg(), false);
2463     }
2464   }
2465   }
2466   NewMIs.push_back(DataMI);
2467 
2468   // Emit the store instruction.
2469   if (UnfoldStore) {
2470     const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2471     const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
2472       ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2473     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
2474   }
2475 
2476   return true;
2477 }
2478 
2479 bool
2480 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2481                                   SmallVectorImpl<SDNode*> &NewNodes) const {
2482   if (!N->isMachineOpcode())
2483     return false;
2484 
2485   DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2486     MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2487   if (I == MemOp2RegOpTable.end())
2488     return false;
2489   unsigned Opc = I->second.first;
2490   unsigned Index = I->second.second & 0xf;
2491   bool FoldedLoad = I->second.second & (1 << 4);
2492   bool FoldedStore = I->second.second & (1 << 5);
2493   const TargetInstrDesc &TID = get(Opc);
2494   const TargetOperandInfo &TOI = TID.OpInfo[Index];
2495   const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2496     ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2497   unsigned NumDefs = TID.NumDefs;
2498   std::vector<SDValue> AddrOps;
2499   std::vector<SDValue> BeforeOps;
2500   std::vector<SDValue> AfterOps;
2501   DebugLoc dl = N->getDebugLoc();
2502   unsigned NumOps = N->getNumOperands();
2503   for (unsigned i = 0; i != NumOps-1; ++i) {
2504     SDValue Op = N->getOperand(i);
2505     if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2506       AddrOps.push_back(Op);
2507     else if (i < Index-NumDefs)
2508       BeforeOps.push_back(Op);
2509     else if (i > Index-NumDefs)
2510       AfterOps.push_back(Op);
2511   }
2512   SDValue Chain = N->getOperand(NumOps-1);
2513   AddrOps.push_back(Chain);
2514 
2515   // Emit the load instruction.
2516   SDNode *Load = 0;
2517   const MachineFunction &MF = DAG.getMachineFunction();
2518   if (FoldedLoad) {
2519     MVT VT = *RC->vt_begin();
2520     bool isAligned = (RI.getStackAlignment() >= 16) ||
2521       RI.needsStackRealignment(MF);
2522     Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2523                              VT, MVT::Other, &AddrOps[0], AddrOps.size());
2524     NewNodes.push_back(Load);
2525   }
2526 
2527   // Emit the data processing instruction.
2528   std::vector<MVT> VTs;
2529   const TargetRegisterClass *DstRC = 0;
2530   if (TID.getNumDefs() > 0) {
2531     const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2532     DstRC = DstTOI.isLookupPtrRegClass()
2533       ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2534     VTs.push_back(*DstRC->vt_begin());
2535   }
2536   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2537     MVT VT = N->getValueType(i);
2538     if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2539       VTs.push_back(VT);
2540   }
2541   if (Load)
2542     BeforeOps.push_back(SDValue(Load, 0));
2543   std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2544   SDNode *NewNode= DAG.getTargetNode(Opc, dl, VTs, &BeforeOps[0],
2545                                      BeforeOps.size());
2546   NewNodes.push_back(NewNode);
2547 
2548   // Emit the store instruction.
2549   if (FoldedStore) {
2550     AddrOps.pop_back();
2551     AddrOps.push_back(SDValue(NewNode, 0));
2552     AddrOps.push_back(Chain);
2553     bool isAligned = (RI.getStackAlignment() >= 16) ||
2554       RI.needsStackRealignment(MF);
2555     SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC,
2556                                                         isAligned, TM),
2557                                       dl, MVT::Other,
2558                                       &AddrOps[0], AddrOps.size());
2559     NewNodes.push_back(Store);
2560   }
2561 
2562   return true;
2563 }
2564 
2565 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2566                                       bool UnfoldLoad, bool UnfoldStore) const {
2567   DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2568     MemOp2RegOpTable.find((unsigned*)Opc);
2569   if (I == MemOp2RegOpTable.end())
2570     return 0;
2571   bool FoldedLoad = I->second.second & (1 << 4);
2572   bool FoldedStore = I->second.second & (1 << 5);
2573   if (UnfoldLoad && !FoldedLoad)
2574     return 0;
2575   if (UnfoldStore && !FoldedStore)
2576     return 0;
2577   return I->second.first;
2578 }
2579 
2580 bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
2581   if (MBB.empty()) return false;
2582 
2583   switch (MBB.back().getOpcode()) {
2584   case X86::TCRETURNri:
2585   case X86::TCRETURNdi:
2586   case X86::RET:     // Return.
2587   case X86::RETI:
2588   case X86::TAILJMPd:
2589   case X86::TAILJMPr:
2590   case X86::TAILJMPm:
2591   case X86::JMP:     // Uncond branch.
2592   case X86::JMP32r:  // Indirect branch.
2593   case X86::JMP64r:  // Indirect branch (64-bit).
2594   case X86::JMP32m:  // Indirect branch through mem.
2595   case X86::JMP64m:  // Indirect branch through mem (64-bit).
2596     return true;
2597   default: return false;
2598   }
2599 }
2600 
2601 bool X86InstrInfo::
2602 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2603   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2604   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2605   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2606     return true;
2607   Cond[0].setImm(GetOppositeBranchCondition(CC));
2608   return false;
2609 }
2610 
2611 bool X86InstrInfo::
2612 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2613   // FIXME: Return false for x87 stack register classes for now. We can't
2614   // allow any loads of these registers before FpGet_ST0_80.
2615   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2616            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2617 }
2618 
2619 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2620   switch (Desc->TSFlags & X86II::ImmMask) {
2621   case X86II::Imm8:   return 1;
2622   case X86II::Imm16:  return 2;
2623   case X86II::Imm32:  return 4;
2624   case X86II::Imm64:  return 8;
2625   default: assert(0 && "Immediate size not set!");
2626     return 0;
2627   }
2628 }
2629 
2630 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2631 /// e.g. r8, xmm8, etc.
2632 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2633   if (!MO.isReg()) return false;
2634   switch (MO.getReg()) {
2635   default: break;
2636   case X86::R8:    case X86::R9:    case X86::R10:   case X86::R11:
2637   case X86::R12:   case X86::R13:   case X86::R14:   case X86::R15:
2638   case X86::R8D:   case X86::R9D:   case X86::R10D:  case X86::R11D:
2639   case X86::R12D:  case X86::R13D:  case X86::R14D:  case X86::R15D:
2640   case X86::R8W:   case X86::R9W:   case X86::R10W:  case X86::R11W:
2641   case X86::R12W:  case X86::R13W:  case X86::R14W:  case X86::R15W:
2642   case X86::R8B:   case X86::R9B:   case X86::R10B:  case X86::R11B:
2643   case X86::R12B:  case X86::R13B:  case X86::R14B:  case X86::R15B:
2644   case X86::XMM8:  case X86::XMM9:  case X86::XMM10: case X86::XMM11:
2645   case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2646     return true;
2647   }
2648   return false;
2649 }
2650 
2651 
2652 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2653 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2654 /// size, and 3) use of X86-64 extended registers.
2655 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2656   unsigned REX = 0;
2657   const TargetInstrDesc &Desc = MI.getDesc();
2658 
2659   // Pseudo instructions do not need REX prefix byte.
2660   if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2661     return 0;
2662   if (Desc.TSFlags & X86II::REX_W)
2663     REX |= 1 << 3;
2664 
2665   unsigned NumOps = Desc.getNumOperands();
2666   if (NumOps) {
2667     bool isTwoAddr = NumOps > 1 &&
2668       Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2669 
2670     // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2671     unsigned i = isTwoAddr ? 1 : 0;
2672     for (unsigned e = NumOps; i != e; ++i) {
2673       const MachineOperand& MO = MI.getOperand(i);
2674       if (MO.isReg()) {
2675         unsigned Reg = MO.getReg();
2676         if (isX86_64NonExtLowByteReg(Reg))
2677           REX |= 0x40;
2678       }
2679     }
2680 
2681     switch (Desc.TSFlags & X86II::FormMask) {
2682     case X86II::MRMInitReg:
2683       if (isX86_64ExtendedReg(MI.getOperand(0)))
2684         REX |= (1 << 0) | (1 << 2);
2685       break;
2686     case X86II::MRMSrcReg: {
2687       if (isX86_64ExtendedReg(MI.getOperand(0)))
2688         REX |= 1 << 2;
2689       i = isTwoAddr ? 2 : 1;
2690       for (unsigned e = NumOps; i != e; ++i) {
2691         const MachineOperand& MO = MI.getOperand(i);
2692         if (isX86_64ExtendedReg(MO))
2693           REX |= 1 << 0;
2694       }
2695       break;
2696     }
2697     case X86II::MRMSrcMem: {
2698       if (isX86_64ExtendedReg(MI.getOperand(0)))
2699         REX |= 1 << 2;
2700       unsigned Bit = 0;
2701       i = isTwoAddr ? 2 : 1;
2702       for (; i != NumOps; ++i) {
2703         const MachineOperand& MO = MI.getOperand(i);
2704         if (MO.isReg()) {
2705           if (isX86_64ExtendedReg(MO))
2706             REX |= 1 << Bit;
2707           Bit++;
2708         }
2709       }
2710       break;
2711     }
2712     case X86II::MRM0m: case X86II::MRM1m:
2713     case X86II::MRM2m: case X86II::MRM3m:
2714     case X86II::MRM4m: case X86II::MRM5m:
2715     case X86II::MRM6m: case X86II::MRM7m:
2716     case X86II::MRMDestMem: {
2717       unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
2718       i = isTwoAddr ? 1 : 0;
2719       if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2720         REX |= 1 << 2;
2721       unsigned Bit = 0;
2722       for (; i != e; ++i) {
2723         const MachineOperand& MO = MI.getOperand(i);
2724         if (MO.isReg()) {
2725           if (isX86_64ExtendedReg(MO))
2726             REX |= 1 << Bit;
2727           Bit++;
2728         }
2729       }
2730       break;
2731     }
2732     default: {
2733       if (isX86_64ExtendedReg(MI.getOperand(0)))
2734         REX |= 1 << 0;
2735       i = isTwoAddr ? 2 : 1;
2736       for (unsigned e = NumOps; i != e; ++i) {
2737         const MachineOperand& MO = MI.getOperand(i);
2738         if (isX86_64ExtendedReg(MO))
2739           REX |= 1 << 2;
2740       }
2741       break;
2742     }
2743     }
2744   }
2745   return REX;
2746 }
2747 
2748 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2749 /// relative block address instruction
2750 ///
2751 static unsigned sizePCRelativeBlockAddress() {
2752   return 4;
2753 }
2754 
2755 /// sizeGlobalAddress - Give the size of the emission of this global address
2756 ///
2757 static unsigned sizeGlobalAddress(bool dword) {
2758   return dword ? 8 : 4;
2759 }
2760 
2761 /// sizeConstPoolAddress - Give the size of the emission of this constant
2762 /// pool address
2763 ///
2764 static unsigned sizeConstPoolAddress(bool dword) {
2765   return dword ? 8 : 4;
2766 }
2767 
2768 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2769 /// symbol
2770 ///
2771 static unsigned sizeExternalSymbolAddress(bool dword) {
2772   return dword ? 8 : 4;
2773 }
2774 
2775 /// sizeJumpTableAddress - Give the size of the emission of this jump
2776 /// table address
2777 ///
2778 static unsigned sizeJumpTableAddress(bool dword) {
2779   return dword ? 8 : 4;
2780 }
2781 
2782 static unsigned sizeConstant(unsigned Size) {
2783   return Size;
2784 }
2785 
2786 static unsigned sizeRegModRMByte(){
2787   return 1;
2788 }
2789 
2790 static unsigned sizeSIBByte(){
2791   return 1;
2792 }
2793 
2794 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2795   unsigned FinalSize = 0;
2796   // If this is a simple integer displacement that doesn't require a relocation.
2797   if (!RelocOp) {
2798     FinalSize += sizeConstant(4);
2799     return FinalSize;
2800   }
2801 
2802   // Otherwise, this is something that requires a relocation.
2803   if (RelocOp->isGlobal()) {
2804     FinalSize += sizeGlobalAddress(false);
2805   } else if (RelocOp->isCPI()) {
2806     FinalSize += sizeConstPoolAddress(false);
2807   } else if (RelocOp->isJTI()) {
2808     FinalSize += sizeJumpTableAddress(false);
2809   } else {
2810     assert(0 && "Unknown value to relocate!");
2811   }
2812   return FinalSize;
2813 }
2814 
2815 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2816                                     bool IsPIC, bool Is64BitMode) {
2817   const MachineOperand &Op3 = MI.getOperand(Op+3);
2818   int DispVal = 0;
2819   const MachineOperand *DispForReloc = 0;
2820   unsigned FinalSize = 0;
2821 
2822   // Figure out what sort of displacement we have to handle here.
2823   if (Op3.isGlobal()) {
2824     DispForReloc = &Op3;
2825   } else if (Op3.isCPI()) {
2826     if (Is64BitMode || IsPIC) {
2827       DispForReloc = &Op3;
2828     } else {
2829       DispVal = 1;
2830     }
2831   } else if (Op3.isJTI()) {
2832     if (Is64BitMode || IsPIC) {
2833       DispForReloc = &Op3;
2834     } else {
2835       DispVal = 1;
2836     }
2837   } else {
2838     DispVal = 1;
2839   }
2840 
2841   const MachineOperand &Base     = MI.getOperand(Op);
2842   const MachineOperand &IndexReg = MI.getOperand(Op+2);
2843 
2844   unsigned BaseReg = Base.getReg();
2845 
2846   // Is a SIB byte needed?
2847   if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
2848       IndexReg.getReg() == 0 &&
2849       (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2850     if (BaseReg == 0) {  // Just a displacement?
2851       // Emit special case [disp32] encoding
2852       ++FinalSize;
2853       FinalSize += getDisplacementFieldSize(DispForReloc);
2854     } else {
2855       unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2856       if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2857         // Emit simple indirect register encoding... [EAX] f.e.
2858         ++FinalSize;
2859       // Be pessimistic and assume it's a disp32, not a disp8
2860       } else {
2861         // Emit the most general non-SIB encoding: [REG+disp32]
2862         ++FinalSize;
2863         FinalSize += getDisplacementFieldSize(DispForReloc);
2864       }
2865     }
2866 
2867   } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
2868     assert(IndexReg.getReg() != X86::ESP &&
2869            IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2870 
2871     bool ForceDisp32 = false;
2872     if (BaseReg == 0 || DispForReloc) {
2873       // Emit the normal disp32 encoding.
2874       ++FinalSize;
2875       ForceDisp32 = true;
2876     } else {
2877       ++FinalSize;
2878     }
2879 
2880     FinalSize += sizeSIBByte();
2881 
2882     // Do we need to output a displacement?
2883     if (DispVal != 0 || ForceDisp32) {
2884       FinalSize += getDisplacementFieldSize(DispForReloc);
2885     }
2886   }
2887   return FinalSize;
2888 }
2889 
2890 
2891 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2892                                     const TargetInstrDesc *Desc,
2893                                     bool IsPIC, bool Is64BitMode) {
2894 
2895   unsigned Opcode = Desc->Opcode;
2896   unsigned FinalSize = 0;
2897 
2898   // Emit the lock opcode prefix as needed.
2899   if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2900 
2901   // Emit segment override opcode prefix as needed.
2902   switch (Desc->TSFlags & X86II::SegOvrMask) {
2903   case X86II::FS:
2904   case X86II::GS:
2905    ++FinalSize;
2906    break;
2907   default: assert(0 && "Invalid segment!");
2908   case 0: break;  // No segment override!
2909   }
2910 
2911   // Emit the repeat opcode prefix as needed.
2912   if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2913 
2914   // Emit the operand size opcode prefix as needed.
2915   if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2916 
2917   // Emit the address size opcode prefix as needed.
2918   if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2919 
2920   bool Need0FPrefix = false;
2921   switch (Desc->TSFlags & X86II::Op0Mask) {
2922   case X86II::TB:  // Two-byte opcode prefix
2923   case X86II::T8:  // 0F 38
2924   case X86II::TA:  // 0F 3A
2925     Need0FPrefix = true;
2926     break;
2927   case X86II::REP: break; // already handled.
2928   case X86II::XS:   // F3 0F
2929     ++FinalSize;
2930     Need0FPrefix = true;
2931     break;
2932   case X86II::XD:   // F2 0F
2933     ++FinalSize;
2934     Need0FPrefix = true;
2935     break;
2936   case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
2937   case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
2938     ++FinalSize;
2939     break; // Two-byte opcode prefix
2940   default: assert(0 && "Invalid prefix!");
2941   case 0: break;  // No prefix!
2942   }
2943 
2944   if (Is64BitMode) {
2945     // REX prefix
2946     unsigned REX = X86InstrInfo::determineREX(MI);
2947     if (REX)
2948       ++FinalSize;
2949   }
2950 
2951   // 0x0F escape code must be emitted just before the opcode.
2952   if (Need0FPrefix)
2953     ++FinalSize;
2954 
2955   switch (Desc->TSFlags & X86II::Op0Mask) {
2956   case X86II::T8:  // 0F 38
2957     ++FinalSize;
2958     break;
2959   case X86II::TA:  // 0F 3A
2960     ++FinalSize;
2961     break;
2962   }
2963 
2964   // If this is a two-address instruction, skip one of the register operands.
2965   unsigned NumOps = Desc->getNumOperands();
2966   unsigned CurOp = 0;
2967   if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
2968     CurOp++;
2969   else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
2970     // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
2971     --NumOps;
2972 
2973   switch (Desc->TSFlags & X86II::FormMask) {
2974   default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
2975   case X86II::Pseudo:
2976     // Remember the current PC offset, this is the PIC relocation
2977     // base address.
2978     switch (Opcode) {
2979     default:
2980       break;
2981     case TargetInstrInfo::INLINEASM: {
2982       const MachineFunction *MF = MI.getParent()->getParent();
2983       const char *AsmStr = MI.getOperand(0).getSymbolName();
2984       const TargetAsmInfo* AI = MF->getTarget().getTargetAsmInfo();
2985       FinalSize += AI->getInlineAsmLength(AsmStr);
2986       break;
2987     }
2988     case TargetInstrInfo::DBG_LABEL:
2989     case TargetInstrInfo::EH_LABEL:
2990       break;
2991     case TargetInstrInfo::IMPLICIT_DEF:
2992     case TargetInstrInfo::DECLARE:
2993     case X86::DWARF_LOC:
2994     case X86::FP_REG_KILL:
2995       break;
2996     case X86::MOVPC32r: {
2997       // This emits the "call" portion of this pseudo instruction.
2998       ++FinalSize;
2999       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3000       break;
3001     }
3002     }
3003     CurOp = NumOps;
3004     break;
3005   case X86II::RawFrm:
3006     ++FinalSize;
3007 
3008     if (CurOp != NumOps) {
3009       const MachineOperand &MO = MI.getOperand(CurOp++);
3010       if (MO.isMBB()) {
3011         FinalSize += sizePCRelativeBlockAddress();
3012       } else if (MO.isGlobal()) {
3013         FinalSize += sizeGlobalAddress(false);
3014       } else if (MO.isSymbol()) {
3015         FinalSize += sizeExternalSymbolAddress(false);
3016       } else if (MO.isImm()) {
3017         FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3018       } else {
3019         assert(0 && "Unknown RawFrm operand!");
3020       }
3021     }
3022     break;
3023 
3024   case X86II::AddRegFrm:
3025     ++FinalSize;
3026     ++CurOp;
3027 
3028     if (CurOp != NumOps) {
3029       const MachineOperand &MO1 = MI.getOperand(CurOp++);
3030       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3031       if (MO1.isImm())
3032         FinalSize += sizeConstant(Size);
3033       else {
3034         bool dword = false;
3035         if (Opcode == X86::MOV64ri)
3036           dword = true;
3037         if (MO1.isGlobal()) {
3038           FinalSize += sizeGlobalAddress(dword);
3039         } else if (MO1.isSymbol())
3040           FinalSize += sizeExternalSymbolAddress(dword);
3041         else if (MO1.isCPI())
3042           FinalSize += sizeConstPoolAddress(dword);
3043         else if (MO1.isJTI())
3044           FinalSize += sizeJumpTableAddress(dword);
3045       }
3046     }
3047     break;
3048 
3049   case X86II::MRMDestReg: {
3050     ++FinalSize;
3051     FinalSize += sizeRegModRMByte();
3052     CurOp += 2;
3053     if (CurOp != NumOps) {
3054       ++CurOp;
3055       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3056     }
3057     break;
3058   }
3059   case X86II::MRMDestMem: {
3060     ++FinalSize;
3061     FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3062     CurOp +=  X86AddrNumOperands + 1;
3063     if (CurOp != NumOps) {
3064       ++CurOp;
3065       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3066     }
3067     break;
3068   }
3069 
3070   case X86II::MRMSrcReg:
3071     ++FinalSize;
3072     FinalSize += sizeRegModRMByte();
3073     CurOp += 2;
3074     if (CurOp != NumOps) {
3075       ++CurOp;
3076       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3077     }
3078     break;
3079 
3080   case X86II::MRMSrcMem: {
3081     int AddrOperands;
3082     if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3083         Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3084       AddrOperands = X86AddrNumOperands - 1; // No segment register
3085     else
3086       AddrOperands = X86AddrNumOperands;
3087 
3088     ++FinalSize;
3089     FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3090     CurOp += AddrOperands + 1;
3091     if (CurOp != NumOps) {
3092       ++CurOp;
3093       FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3094     }
3095     break;
3096   }
3097 
3098   case X86II::MRM0r: case X86II::MRM1r:
3099   case X86II::MRM2r: case X86II::MRM3r:
3100   case X86II::MRM4r: case X86II::MRM5r:
3101   case X86II::MRM6r: case X86II::MRM7r:
3102     ++FinalSize;
3103     if (Desc->getOpcode() == X86::LFENCE ||
3104         Desc->getOpcode() == X86::MFENCE) {
3105       // Special handling of lfence and mfence;
3106       FinalSize += sizeRegModRMByte();
3107     } else if (Desc->getOpcode() == X86::MONITOR ||
3108                Desc->getOpcode() == X86::MWAIT) {
3109       // Special handling of monitor and mwait.
3110       FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3111     } else {
3112       ++CurOp;
3113       FinalSize += sizeRegModRMByte();
3114     }
3115 
3116     if (CurOp != NumOps) {
3117       const MachineOperand &MO1 = MI.getOperand(CurOp++);
3118       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3119       if (MO1.isImm())
3120         FinalSize += sizeConstant(Size);
3121       else {
3122         bool dword = false;
3123         if (Opcode == X86::MOV64ri32)
3124           dword = true;
3125         if (MO1.isGlobal()) {
3126           FinalSize += sizeGlobalAddress(dword);
3127         } else if (MO1.isSymbol())
3128           FinalSize += sizeExternalSymbolAddress(dword);
3129         else if (MO1.isCPI())
3130           FinalSize += sizeConstPoolAddress(dword);
3131         else if (MO1.isJTI())
3132           FinalSize += sizeJumpTableAddress(dword);
3133       }
3134     }
3135     break;
3136 
3137   case X86II::MRM0m: case X86II::MRM1m:
3138   case X86II::MRM2m: case X86II::MRM3m:
3139   case X86II::MRM4m: case X86II::MRM5m:
3140   case X86II::MRM6m: case X86II::MRM7m: {
3141 
3142     ++FinalSize;
3143     FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3144     CurOp += X86AddrNumOperands;
3145 
3146     if (CurOp != NumOps) {
3147       const MachineOperand &MO = MI.getOperand(CurOp++);
3148       unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3149       if (MO.isImm())
3150         FinalSize += sizeConstant(Size);
3151       else {
3152         bool dword = false;
3153         if (Opcode == X86::MOV64mi32)
3154           dword = true;
3155         if (MO.isGlobal()) {
3156           FinalSize += sizeGlobalAddress(dword);
3157         } else if (MO.isSymbol())
3158           FinalSize += sizeExternalSymbolAddress(dword);
3159         else if (MO.isCPI())
3160           FinalSize += sizeConstPoolAddress(dword);
3161         else if (MO.isJTI())
3162           FinalSize += sizeJumpTableAddress(dword);
3163       }
3164     }
3165     break;
3166   }
3167 
3168   case X86II::MRMInitReg:
3169     ++FinalSize;
3170     // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3171     FinalSize += sizeRegModRMByte();
3172     ++CurOp;
3173     break;
3174   }
3175 
3176   if (!Desc->isVariadic() && CurOp != NumOps) {
3177     cerr << "Cannot determine size: ";
3178     MI.dump();
3179     cerr << '\n';
3180     abort();
3181   }
3182 
3183 
3184   return FinalSize;
3185 }
3186 
3187 
3188 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3189   const TargetInstrDesc &Desc = MI->getDesc();
3190   bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_);
3191   bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3192   unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3193   if (Desc.getOpcode() == X86::MOVPC32r) {
3194     Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3195   }
3196   return Size;
3197 }
3198 
3199 /// getGlobalBaseReg - Return a virtual register initialized with the
3200 /// the global base register value. Output instructions required to
3201 /// initialize the register in the function entry block, if necessary.
3202 ///
3203 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3204   assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3205          "X86-64 PIC uses RIP relative addressing");
3206 
3207   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3208   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3209   if (GlobalBaseReg != 0)
3210     return GlobalBaseReg;
3211 
3212   // Insert the set of GlobalBaseReg into the first MBB of the function
3213   MachineBasicBlock &FirstMBB = MF->front();
3214   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3215   DebugLoc DL = DebugLoc::getUnknownLoc();
3216   if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
3217   MachineRegisterInfo &RegInfo = MF->getRegInfo();
3218   unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3219 
3220   const TargetInstrInfo *TII = TM.getInstrInfo();
3221   // Operand of MovePCtoStack is completely ignored by asm printer. It's
3222   // only used in JIT code emission as displacement to pc.
3223   BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC)
3224     .addImm(0);
3225 
3226   // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3227   // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
3228   if (TM.getRelocationModel() == Reloc::PIC_ &&
3229       TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3230     GlobalBaseReg =
3231       RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3232     BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3233       .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
3234   } else {
3235     GlobalBaseReg = PC;
3236   }
3237 
3238   X86FI->setGlobalBaseReg(GlobalBaseReg);
3239   return GlobalBaseReg;
3240 }
3241