1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LivePhysRegs.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DebugInfoMetadata.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "x86-instr-info"
46 
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "X86GenInstrInfo.inc"
49 
50 static cl::opt<bool>
51     NoFusing("disable-spill-fusing",
52              cl::desc("Disable fusing of spill code into instructions"),
53              cl::Hidden);
54 static cl::opt<bool>
55 PrintFailedFusing("print-failed-fuse-candidates",
56                   cl::desc("Print instructions that the allocator wants to"
57                            " fuse, but the X86 backend currently can't"),
58                   cl::Hidden);
59 static cl::opt<bool>
60 ReMatPICStubLoad("remat-pic-stub-load",
61                  cl::desc("Re-materialize load from stub in PIC mode"),
62                  cl::init(false), cl::Hidden);
63 static cl::opt<unsigned>
64 PartialRegUpdateClearance("partial-reg-update-clearance",
65                           cl::desc("Clearance between two register writes "
66                                    "for inserting XOR to avoid partial "
67                                    "register update"),
68                           cl::init(64), cl::Hidden);
69 static cl::opt<unsigned>
70 UndefRegClearance("undef-reg-clearance",
71                   cl::desc("How many idle instructions we would like before "
72                            "certain undef register reads"),
73                   cl::init(128), cl::Hidden);
74 
75 
76 // Pin the vtable to this file.
77 void X86InstrInfo::anchor() {}
78 
79 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81                                                : X86::ADJCALLSTACKDOWN32),
82                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83                                                : X86::ADJCALLSTACKUP32),
84                       X86::CATCHRET,
85                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86       Subtarget(STI), RI(STI.getTargetTriple()) {
87 }
88 
89 bool
90 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91                                     Register &SrcReg, Register &DstReg,
92                                     unsigned &SubIdx) const {
93   switch (MI.getOpcode()) {
94   default: break;
95   case X86::MOVSX16rr8:
96   case X86::MOVZX16rr8:
97   case X86::MOVSX32rr8:
98   case X86::MOVZX32rr8:
99   case X86::MOVSX64rr8:
100     if (!Subtarget.is64Bit())
101       // It's not always legal to reference the low 8-bit of the larger
102       // register in 32-bit mode.
103       return false;
104     LLVM_FALLTHROUGH;
105   case X86::MOVSX32rr16:
106   case X86::MOVZX32rr16:
107   case X86::MOVSX64rr16:
108   case X86::MOVSX64rr32: {
109     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110       // Be conservative.
111       return false;
112     SrcReg = MI.getOperand(1).getReg();
113     DstReg = MI.getOperand(0).getReg();
114     switch (MI.getOpcode()) {
115     default: llvm_unreachable("Unreachable!");
116     case X86::MOVSX16rr8:
117     case X86::MOVZX16rr8:
118     case X86::MOVSX32rr8:
119     case X86::MOVZX32rr8:
120     case X86::MOVSX64rr8:
121       SubIdx = X86::sub_8bit;
122       break;
123     case X86::MOVSX32rr16:
124     case X86::MOVZX32rr16:
125     case X86::MOVSX64rr16:
126       SubIdx = X86::sub_16bit;
127       break;
128     case X86::MOVSX64rr32:
129       SubIdx = X86::sub_32bit;
130       break;
131     }
132     return true;
133   }
134   }
135   return false;
136 }
137 
138 bool X86InstrInfo::isDataInvariant(MachineInstr &MI) {
139   switch (MI.getOpcode()) {
140   default:
141     // By default, assume that the instruction is not data invariant.
142     return false;
143 
144     // Some target-independent operations that trivially lower to data-invariant
145     // instructions.
146   case TargetOpcode::COPY:
147   case TargetOpcode::INSERT_SUBREG:
148   case TargetOpcode::SUBREG_TO_REG:
149     return true;
150 
151   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
152   // However, they set flags and are perhaps the most surprisingly constant
153   // time operations so we call them out here separately.
154   case X86::IMUL16rr:
155   case X86::IMUL16rri8:
156   case X86::IMUL16rri:
157   case X86::IMUL32rr:
158   case X86::IMUL32rri8:
159   case X86::IMUL32rri:
160   case X86::IMUL64rr:
161   case X86::IMUL64rri32:
162   case X86::IMUL64rri8:
163 
164   // Bit scanning and counting instructions that are somewhat surprisingly
165   // constant time as they scan across bits and do other fairly complex
166   // operations like popcnt, but are believed to be constant time on x86.
167   // However, these set flags.
168   case X86::BSF16rr:
169   case X86::BSF32rr:
170   case X86::BSF64rr:
171   case X86::BSR16rr:
172   case X86::BSR32rr:
173   case X86::BSR64rr:
174   case X86::LZCNT16rr:
175   case X86::LZCNT32rr:
176   case X86::LZCNT64rr:
177   case X86::POPCNT16rr:
178   case X86::POPCNT32rr:
179   case X86::POPCNT64rr:
180   case X86::TZCNT16rr:
181   case X86::TZCNT32rr:
182   case X86::TZCNT64rr:
183 
184   // Bit manipulation instructions are effectively combinations of basic
185   // arithmetic ops, and should still execute in constant time. These also
186   // set flags.
187   case X86::BLCFILL32rr:
188   case X86::BLCFILL64rr:
189   case X86::BLCI32rr:
190   case X86::BLCI64rr:
191   case X86::BLCIC32rr:
192   case X86::BLCIC64rr:
193   case X86::BLCMSK32rr:
194   case X86::BLCMSK64rr:
195   case X86::BLCS32rr:
196   case X86::BLCS64rr:
197   case X86::BLSFILL32rr:
198   case X86::BLSFILL64rr:
199   case X86::BLSI32rr:
200   case X86::BLSI64rr:
201   case X86::BLSIC32rr:
202   case X86::BLSIC64rr:
203   case X86::BLSMSK32rr:
204   case X86::BLSMSK64rr:
205   case X86::BLSR32rr:
206   case X86::BLSR64rr:
207   case X86::TZMSK32rr:
208   case X86::TZMSK64rr:
209 
210   // Bit extracting and clearing instructions should execute in constant time,
211   // and set flags.
212   case X86::BEXTR32rr:
213   case X86::BEXTR64rr:
214   case X86::BEXTRI32ri:
215   case X86::BEXTRI64ri:
216   case X86::BZHI32rr:
217   case X86::BZHI64rr:
218 
219   // Shift and rotate.
220   case X86::ROL8r1:
221   case X86::ROL16r1:
222   case X86::ROL32r1:
223   case X86::ROL64r1:
224   case X86::ROL8rCL:
225   case X86::ROL16rCL:
226   case X86::ROL32rCL:
227   case X86::ROL64rCL:
228   case X86::ROL8ri:
229   case X86::ROL16ri:
230   case X86::ROL32ri:
231   case X86::ROL64ri:
232   case X86::ROR8r1:
233   case X86::ROR16r1:
234   case X86::ROR32r1:
235   case X86::ROR64r1:
236   case X86::ROR8rCL:
237   case X86::ROR16rCL:
238   case X86::ROR32rCL:
239   case X86::ROR64rCL:
240   case X86::ROR8ri:
241   case X86::ROR16ri:
242   case X86::ROR32ri:
243   case X86::ROR64ri:
244   case X86::SAR8r1:
245   case X86::SAR16r1:
246   case X86::SAR32r1:
247   case X86::SAR64r1:
248   case X86::SAR8rCL:
249   case X86::SAR16rCL:
250   case X86::SAR32rCL:
251   case X86::SAR64rCL:
252   case X86::SAR8ri:
253   case X86::SAR16ri:
254   case X86::SAR32ri:
255   case X86::SAR64ri:
256   case X86::SHL8r1:
257   case X86::SHL16r1:
258   case X86::SHL32r1:
259   case X86::SHL64r1:
260   case X86::SHL8rCL:
261   case X86::SHL16rCL:
262   case X86::SHL32rCL:
263   case X86::SHL64rCL:
264   case X86::SHL8ri:
265   case X86::SHL16ri:
266   case X86::SHL32ri:
267   case X86::SHL64ri:
268   case X86::SHR8r1:
269   case X86::SHR16r1:
270   case X86::SHR32r1:
271   case X86::SHR64r1:
272   case X86::SHR8rCL:
273   case X86::SHR16rCL:
274   case X86::SHR32rCL:
275   case X86::SHR64rCL:
276   case X86::SHR8ri:
277   case X86::SHR16ri:
278   case X86::SHR32ri:
279   case X86::SHR64ri:
280   case X86::SHLD16rrCL:
281   case X86::SHLD32rrCL:
282   case X86::SHLD64rrCL:
283   case X86::SHLD16rri8:
284   case X86::SHLD32rri8:
285   case X86::SHLD64rri8:
286   case X86::SHRD16rrCL:
287   case X86::SHRD32rrCL:
288   case X86::SHRD64rrCL:
289   case X86::SHRD16rri8:
290   case X86::SHRD32rri8:
291   case X86::SHRD64rri8:
292 
293   // Basic arithmetic is constant time on the input but does set flags.
294   case X86::ADC8rr:
295   case X86::ADC8ri:
296   case X86::ADC16rr:
297   case X86::ADC16ri:
298   case X86::ADC16ri8:
299   case X86::ADC32rr:
300   case X86::ADC32ri:
301   case X86::ADC32ri8:
302   case X86::ADC64rr:
303   case X86::ADC64ri8:
304   case X86::ADC64ri32:
305   case X86::ADD8rr:
306   case X86::ADD8ri:
307   case X86::ADD16rr:
308   case X86::ADD16ri:
309   case X86::ADD16ri8:
310   case X86::ADD32rr:
311   case X86::ADD32ri:
312   case X86::ADD32ri8:
313   case X86::ADD64rr:
314   case X86::ADD64ri8:
315   case X86::ADD64ri32:
316   case X86::AND8rr:
317   case X86::AND8ri:
318   case X86::AND16rr:
319   case X86::AND16ri:
320   case X86::AND16ri8:
321   case X86::AND32rr:
322   case X86::AND32ri:
323   case X86::AND32ri8:
324   case X86::AND64rr:
325   case X86::AND64ri8:
326   case X86::AND64ri32:
327   case X86::OR8rr:
328   case X86::OR8ri:
329   case X86::OR16rr:
330   case X86::OR16ri:
331   case X86::OR16ri8:
332   case X86::OR32rr:
333   case X86::OR32ri:
334   case X86::OR32ri8:
335   case X86::OR64rr:
336   case X86::OR64ri8:
337   case X86::OR64ri32:
338   case X86::SBB8rr:
339   case X86::SBB8ri:
340   case X86::SBB16rr:
341   case X86::SBB16ri:
342   case X86::SBB16ri8:
343   case X86::SBB32rr:
344   case X86::SBB32ri:
345   case X86::SBB32ri8:
346   case X86::SBB64rr:
347   case X86::SBB64ri8:
348   case X86::SBB64ri32:
349   case X86::SUB8rr:
350   case X86::SUB8ri:
351   case X86::SUB16rr:
352   case X86::SUB16ri:
353   case X86::SUB16ri8:
354   case X86::SUB32rr:
355   case X86::SUB32ri:
356   case X86::SUB32ri8:
357   case X86::SUB64rr:
358   case X86::SUB64ri8:
359   case X86::SUB64ri32:
360   case X86::XOR8rr:
361   case X86::XOR8ri:
362   case X86::XOR16rr:
363   case X86::XOR16ri:
364   case X86::XOR16ri8:
365   case X86::XOR32rr:
366   case X86::XOR32ri:
367   case X86::XOR32ri8:
368   case X86::XOR64rr:
369   case X86::XOR64ri8:
370   case X86::XOR64ri32:
371   // Arithmetic with just 32-bit and 64-bit variants and no immediates.
372   case X86::ADCX32rr:
373   case X86::ADCX64rr:
374   case X86::ADOX32rr:
375   case X86::ADOX64rr:
376   case X86::ANDN32rr:
377   case X86::ANDN64rr:
378   // Unary arithmetic operations.
379   case X86::DEC8r:
380   case X86::DEC16r:
381   case X86::DEC32r:
382   case X86::DEC64r:
383   case X86::INC8r:
384   case X86::INC16r:
385   case X86::INC32r:
386   case X86::INC64r:
387   case X86::NEG8r:
388   case X86::NEG16r:
389   case X86::NEG32r:
390   case X86::NEG64r:
391 
392   // Unlike other arithmetic, NOT doesn't set EFLAGS.
393   case X86::NOT8r:
394   case X86::NOT16r:
395   case X86::NOT32r:
396   case X86::NOT64r:
397 
398   // Various move instructions used to zero or sign extend things. Note that we
399   // intentionally don't support the _NOREX variants as we can't handle that
400   // register constraint anyways.
401   case X86::MOVSX16rr8:
402   case X86::MOVSX32rr8:
403   case X86::MOVSX32rr16:
404   case X86::MOVSX64rr8:
405   case X86::MOVSX64rr16:
406   case X86::MOVSX64rr32:
407   case X86::MOVZX16rr8:
408   case X86::MOVZX32rr8:
409   case X86::MOVZX32rr16:
410   case X86::MOVZX64rr8:
411   case X86::MOVZX64rr16:
412   case X86::MOV32rr:
413 
414   // Arithmetic instructions that are both constant time and don't set flags.
415   case X86::RORX32ri:
416   case X86::RORX64ri:
417   case X86::SARX32rr:
418   case X86::SARX64rr:
419   case X86::SHLX32rr:
420   case X86::SHLX64rr:
421   case X86::SHRX32rr:
422   case X86::SHRX64rr:
423 
424   // LEA doesn't actually access memory, and its arithmetic is constant time.
425   case X86::LEA16r:
426   case X86::LEA32r:
427   case X86::LEA64_32r:
428   case X86::LEA64r:
429     return true;
430   }
431 }
432 
433 bool X86InstrInfo::isDataInvariantLoad(MachineInstr &MI) {
434   switch (MI.getOpcode()) {
435   default:
436     // By default, assume that the load will immediately leak.
437     return false;
438 
439   // On x86 it is believed that imul is constant time w.r.t. the loaded data.
440   // However, they set flags and are perhaps the most surprisingly constant
441   // time operations so we call them out here separately.
442   case X86::IMUL16rm:
443   case X86::IMUL16rmi8:
444   case X86::IMUL16rmi:
445   case X86::IMUL32rm:
446   case X86::IMUL32rmi8:
447   case X86::IMUL32rmi:
448   case X86::IMUL64rm:
449   case X86::IMUL64rmi32:
450   case X86::IMUL64rmi8:
451 
452   // Bit scanning and counting instructions that are somewhat surprisingly
453   // constant time as they scan across bits and do other fairly complex
454   // operations like popcnt, but are believed to be constant time on x86.
455   // However, these set flags.
456   case X86::BSF16rm:
457   case X86::BSF32rm:
458   case X86::BSF64rm:
459   case X86::BSR16rm:
460   case X86::BSR32rm:
461   case X86::BSR64rm:
462   case X86::LZCNT16rm:
463   case X86::LZCNT32rm:
464   case X86::LZCNT64rm:
465   case X86::POPCNT16rm:
466   case X86::POPCNT32rm:
467   case X86::POPCNT64rm:
468   case X86::TZCNT16rm:
469   case X86::TZCNT32rm:
470   case X86::TZCNT64rm:
471 
472   // Bit manipulation instructions are effectively combinations of basic
473   // arithmetic ops, and should still execute in constant time. These also
474   // set flags.
475   case X86::BLCFILL32rm:
476   case X86::BLCFILL64rm:
477   case X86::BLCI32rm:
478   case X86::BLCI64rm:
479   case X86::BLCIC32rm:
480   case X86::BLCIC64rm:
481   case X86::BLCMSK32rm:
482   case X86::BLCMSK64rm:
483   case X86::BLCS32rm:
484   case X86::BLCS64rm:
485   case X86::BLSFILL32rm:
486   case X86::BLSFILL64rm:
487   case X86::BLSI32rm:
488   case X86::BLSI64rm:
489   case X86::BLSIC32rm:
490   case X86::BLSIC64rm:
491   case X86::BLSMSK32rm:
492   case X86::BLSMSK64rm:
493   case X86::BLSR32rm:
494   case X86::BLSR64rm:
495   case X86::TZMSK32rm:
496   case X86::TZMSK64rm:
497 
498   // Bit extracting and clearing instructions should execute in constant time,
499   // and set flags.
500   case X86::BEXTR32rm:
501   case X86::BEXTR64rm:
502   case X86::BEXTRI32mi:
503   case X86::BEXTRI64mi:
504   case X86::BZHI32rm:
505   case X86::BZHI64rm:
506 
507   // Basic arithmetic is constant time on the input but does set flags.
508   case X86::ADC8rm:
509   case X86::ADC16rm:
510   case X86::ADC32rm:
511   case X86::ADC64rm:
512   case X86::ADCX32rm:
513   case X86::ADCX64rm:
514   case X86::ADD8rm:
515   case X86::ADD16rm:
516   case X86::ADD32rm:
517   case X86::ADD64rm:
518   case X86::ADOX32rm:
519   case X86::ADOX64rm:
520   case X86::AND8rm:
521   case X86::AND16rm:
522   case X86::AND32rm:
523   case X86::AND64rm:
524   case X86::ANDN32rm:
525   case X86::ANDN64rm:
526   case X86::OR8rm:
527   case X86::OR16rm:
528   case X86::OR32rm:
529   case X86::OR64rm:
530   case X86::SBB8rm:
531   case X86::SBB16rm:
532   case X86::SBB32rm:
533   case X86::SBB64rm:
534   case X86::SUB8rm:
535   case X86::SUB16rm:
536   case X86::SUB32rm:
537   case X86::SUB64rm:
538   case X86::XOR8rm:
539   case X86::XOR16rm:
540   case X86::XOR32rm:
541   case X86::XOR64rm:
542 
543   // Integer multiply w/o affecting flags is still believed to be constant
544   // time on x86. Called out separately as this is among the most surprising
545   // instructions to exhibit that behavior.
546   case X86::MULX32rm:
547   case X86::MULX64rm:
548 
549   // Arithmetic instructions that are both constant time and don't set flags.
550   case X86::RORX32mi:
551   case X86::RORX64mi:
552   case X86::SARX32rm:
553   case X86::SARX64rm:
554   case X86::SHLX32rm:
555   case X86::SHLX64rm:
556   case X86::SHRX32rm:
557   case X86::SHRX64rm:
558 
559   // Conversions are believed to be constant time and don't set flags.
560   case X86::CVTTSD2SI64rm:
561   case X86::VCVTTSD2SI64rm:
562   case X86::VCVTTSD2SI64Zrm:
563   case X86::CVTTSD2SIrm:
564   case X86::VCVTTSD2SIrm:
565   case X86::VCVTTSD2SIZrm:
566   case X86::CVTTSS2SI64rm:
567   case X86::VCVTTSS2SI64rm:
568   case X86::VCVTTSS2SI64Zrm:
569   case X86::CVTTSS2SIrm:
570   case X86::VCVTTSS2SIrm:
571   case X86::VCVTTSS2SIZrm:
572   case X86::CVTSI2SDrm:
573   case X86::VCVTSI2SDrm:
574   case X86::VCVTSI2SDZrm:
575   case X86::CVTSI2SSrm:
576   case X86::VCVTSI2SSrm:
577   case X86::VCVTSI2SSZrm:
578   case X86::CVTSI642SDrm:
579   case X86::VCVTSI642SDrm:
580   case X86::VCVTSI642SDZrm:
581   case X86::CVTSI642SSrm:
582   case X86::VCVTSI642SSrm:
583   case X86::VCVTSI642SSZrm:
584   case X86::CVTSS2SDrm:
585   case X86::VCVTSS2SDrm:
586   case X86::VCVTSS2SDZrm:
587   case X86::CVTSD2SSrm:
588   case X86::VCVTSD2SSrm:
589   case X86::VCVTSD2SSZrm:
590   // AVX512 added unsigned integer conversions.
591   case X86::VCVTTSD2USI64Zrm:
592   case X86::VCVTTSD2USIZrm:
593   case X86::VCVTTSS2USI64Zrm:
594   case X86::VCVTTSS2USIZrm:
595   case X86::VCVTUSI2SDZrm:
596   case X86::VCVTUSI642SDZrm:
597   case X86::VCVTUSI2SSZrm:
598   case X86::VCVTUSI642SSZrm:
599 
600   // Loads to register don't set flags.
601   case X86::MOV8rm:
602   case X86::MOV8rm_NOREX:
603   case X86::MOV16rm:
604   case X86::MOV32rm:
605   case X86::MOV64rm:
606   case X86::MOVSX16rm8:
607   case X86::MOVSX32rm16:
608   case X86::MOVSX32rm8:
609   case X86::MOVSX32rm8_NOREX:
610   case X86::MOVSX64rm16:
611   case X86::MOVSX64rm32:
612   case X86::MOVSX64rm8:
613   case X86::MOVZX16rm8:
614   case X86::MOVZX32rm16:
615   case X86::MOVZX32rm8:
616   case X86::MOVZX32rm8_NOREX:
617   case X86::MOVZX64rm16:
618   case X86::MOVZX64rm8:
619     return true;
620   }
621 }
622 
623 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
624   const MachineFunction *MF = MI.getParent()->getParent();
625   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
626 
627   if (isFrameInstr(MI)) {
628     int SPAdj = alignTo(getFrameSize(MI), TFI->getStackAlign());
629     SPAdj -= getFrameAdjustment(MI);
630     if (!isFrameSetup(MI))
631       SPAdj = -SPAdj;
632     return SPAdj;
633   }
634 
635   // To know whether a call adjusts the stack, we need information
636   // that is bound to the following ADJCALLSTACKUP pseudo.
637   // Look for the next ADJCALLSTACKUP that follows the call.
638   if (MI.isCall()) {
639     const MachineBasicBlock *MBB = MI.getParent();
640     auto I = ++MachineBasicBlock::const_iterator(MI);
641     for (auto E = MBB->end(); I != E; ++I) {
642       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
643           I->isCall())
644         break;
645     }
646 
647     // If we could not find a frame destroy opcode, then it has already
648     // been simplified, so we don't care.
649     if (I->getOpcode() != getCallFrameDestroyOpcode())
650       return 0;
651 
652     return -(I->getOperand(1).getImm());
653   }
654 
655   // Currently handle only PUSHes we can reasonably expect to see
656   // in call sequences
657   switch (MI.getOpcode()) {
658   default:
659     return 0;
660   case X86::PUSH32i8:
661   case X86::PUSH32r:
662   case X86::PUSH32rmm:
663   case X86::PUSH32rmr:
664   case X86::PUSHi32:
665     return 4;
666   case X86::PUSH64i8:
667   case X86::PUSH64r:
668   case X86::PUSH64rmm:
669   case X86::PUSH64rmr:
670   case X86::PUSH64i32:
671     return 8;
672   }
673 }
674 
675 /// Return true and the FrameIndex if the specified
676 /// operand and follow operands form a reference to the stack frame.
677 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
678                                   int &FrameIndex) const {
679   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
680       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
681       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
682       MI.getOperand(Op + X86::AddrDisp).isImm() &&
683       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
684       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
685       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
686     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
687     return true;
688   }
689   return false;
690 }
691 
692 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
693   switch (Opcode) {
694   default:
695     return false;
696   case X86::MOV8rm:
697   case X86::KMOVBkm:
698     MemBytes = 1;
699     return true;
700   case X86::MOV16rm:
701   case X86::KMOVWkm:
702     MemBytes = 2;
703     return true;
704   case X86::MOV32rm:
705   case X86::MOVSSrm:
706   case X86::MOVSSrm_alt:
707   case X86::VMOVSSrm:
708   case X86::VMOVSSrm_alt:
709   case X86::VMOVSSZrm:
710   case X86::VMOVSSZrm_alt:
711   case X86::KMOVDkm:
712     MemBytes = 4;
713     return true;
714   case X86::MOV64rm:
715   case X86::LD_Fp64m:
716   case X86::MOVSDrm:
717   case X86::MOVSDrm_alt:
718   case X86::VMOVSDrm:
719   case X86::VMOVSDrm_alt:
720   case X86::VMOVSDZrm:
721   case X86::VMOVSDZrm_alt:
722   case X86::MMX_MOVD64rm:
723   case X86::MMX_MOVQ64rm:
724   case X86::KMOVQkm:
725     MemBytes = 8;
726     return true;
727   case X86::MOVAPSrm:
728   case X86::MOVUPSrm:
729   case X86::MOVAPDrm:
730   case X86::MOVUPDrm:
731   case X86::MOVDQArm:
732   case X86::MOVDQUrm:
733   case X86::VMOVAPSrm:
734   case X86::VMOVUPSrm:
735   case X86::VMOVAPDrm:
736   case X86::VMOVUPDrm:
737   case X86::VMOVDQArm:
738   case X86::VMOVDQUrm:
739   case X86::VMOVAPSZ128rm:
740   case X86::VMOVUPSZ128rm:
741   case X86::VMOVAPSZ128rm_NOVLX:
742   case X86::VMOVUPSZ128rm_NOVLX:
743   case X86::VMOVAPDZ128rm:
744   case X86::VMOVUPDZ128rm:
745   case X86::VMOVDQU8Z128rm:
746   case X86::VMOVDQU16Z128rm:
747   case X86::VMOVDQA32Z128rm:
748   case X86::VMOVDQU32Z128rm:
749   case X86::VMOVDQA64Z128rm:
750   case X86::VMOVDQU64Z128rm:
751     MemBytes = 16;
752     return true;
753   case X86::VMOVAPSYrm:
754   case X86::VMOVUPSYrm:
755   case X86::VMOVAPDYrm:
756   case X86::VMOVUPDYrm:
757   case X86::VMOVDQAYrm:
758   case X86::VMOVDQUYrm:
759   case X86::VMOVAPSZ256rm:
760   case X86::VMOVUPSZ256rm:
761   case X86::VMOVAPSZ256rm_NOVLX:
762   case X86::VMOVUPSZ256rm_NOVLX:
763   case X86::VMOVAPDZ256rm:
764   case X86::VMOVUPDZ256rm:
765   case X86::VMOVDQU8Z256rm:
766   case X86::VMOVDQU16Z256rm:
767   case X86::VMOVDQA32Z256rm:
768   case X86::VMOVDQU32Z256rm:
769   case X86::VMOVDQA64Z256rm:
770   case X86::VMOVDQU64Z256rm:
771     MemBytes = 32;
772     return true;
773   case X86::VMOVAPSZrm:
774   case X86::VMOVUPSZrm:
775   case X86::VMOVAPDZrm:
776   case X86::VMOVUPDZrm:
777   case X86::VMOVDQU8Zrm:
778   case X86::VMOVDQU16Zrm:
779   case X86::VMOVDQA32Zrm:
780   case X86::VMOVDQU32Zrm:
781   case X86::VMOVDQA64Zrm:
782   case X86::VMOVDQU64Zrm:
783     MemBytes = 64;
784     return true;
785   }
786 }
787 
788 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
789   switch (Opcode) {
790   default:
791     return false;
792   case X86::MOV8mr:
793   case X86::KMOVBmk:
794     MemBytes = 1;
795     return true;
796   case X86::MOV16mr:
797   case X86::KMOVWmk:
798     MemBytes = 2;
799     return true;
800   case X86::MOV32mr:
801   case X86::MOVSSmr:
802   case X86::VMOVSSmr:
803   case X86::VMOVSSZmr:
804   case X86::KMOVDmk:
805     MemBytes = 4;
806     return true;
807   case X86::MOV64mr:
808   case X86::ST_FpP64m:
809   case X86::MOVSDmr:
810   case X86::VMOVSDmr:
811   case X86::VMOVSDZmr:
812   case X86::MMX_MOVD64mr:
813   case X86::MMX_MOVQ64mr:
814   case X86::MMX_MOVNTQmr:
815   case X86::KMOVQmk:
816     MemBytes = 8;
817     return true;
818   case X86::MOVAPSmr:
819   case X86::MOVUPSmr:
820   case X86::MOVAPDmr:
821   case X86::MOVUPDmr:
822   case X86::MOVDQAmr:
823   case X86::MOVDQUmr:
824   case X86::VMOVAPSmr:
825   case X86::VMOVUPSmr:
826   case X86::VMOVAPDmr:
827   case X86::VMOVUPDmr:
828   case X86::VMOVDQAmr:
829   case X86::VMOVDQUmr:
830   case X86::VMOVUPSZ128mr:
831   case X86::VMOVAPSZ128mr:
832   case X86::VMOVUPSZ128mr_NOVLX:
833   case X86::VMOVAPSZ128mr_NOVLX:
834   case X86::VMOVUPDZ128mr:
835   case X86::VMOVAPDZ128mr:
836   case X86::VMOVDQA32Z128mr:
837   case X86::VMOVDQU32Z128mr:
838   case X86::VMOVDQA64Z128mr:
839   case X86::VMOVDQU64Z128mr:
840   case X86::VMOVDQU8Z128mr:
841   case X86::VMOVDQU16Z128mr:
842     MemBytes = 16;
843     return true;
844   case X86::VMOVUPSYmr:
845   case X86::VMOVAPSYmr:
846   case X86::VMOVUPDYmr:
847   case X86::VMOVAPDYmr:
848   case X86::VMOVDQUYmr:
849   case X86::VMOVDQAYmr:
850   case X86::VMOVUPSZ256mr:
851   case X86::VMOVAPSZ256mr:
852   case X86::VMOVUPSZ256mr_NOVLX:
853   case X86::VMOVAPSZ256mr_NOVLX:
854   case X86::VMOVUPDZ256mr:
855   case X86::VMOVAPDZ256mr:
856   case X86::VMOVDQU8Z256mr:
857   case X86::VMOVDQU16Z256mr:
858   case X86::VMOVDQA32Z256mr:
859   case X86::VMOVDQU32Z256mr:
860   case X86::VMOVDQA64Z256mr:
861   case X86::VMOVDQU64Z256mr:
862     MemBytes = 32;
863     return true;
864   case X86::VMOVUPSZmr:
865   case X86::VMOVAPSZmr:
866   case X86::VMOVUPDZmr:
867   case X86::VMOVAPDZmr:
868   case X86::VMOVDQU8Zmr:
869   case X86::VMOVDQU16Zmr:
870   case X86::VMOVDQA32Zmr:
871   case X86::VMOVDQU32Zmr:
872   case X86::VMOVDQA64Zmr:
873   case X86::VMOVDQU64Zmr:
874     MemBytes = 64;
875     return true;
876   }
877   return false;
878 }
879 
880 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
881                                            int &FrameIndex) const {
882   unsigned Dummy;
883   return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
884 }
885 
886 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
887                                            int &FrameIndex,
888                                            unsigned &MemBytes) const {
889   if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
890     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
891       return MI.getOperand(0).getReg();
892   return 0;
893 }
894 
895 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
896                                                  int &FrameIndex) const {
897   unsigned Dummy;
898   if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
899     unsigned Reg;
900     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
901       return Reg;
902     // Check for post-frame index elimination operations
903     SmallVector<const MachineMemOperand *, 1> Accesses;
904     if (hasLoadFromStackSlot(MI, Accesses)) {
905       FrameIndex =
906           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
907               ->getFrameIndex();
908       return 1;
909     }
910   }
911   return 0;
912 }
913 
914 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
915                                           int &FrameIndex) const {
916   unsigned Dummy;
917   return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
918 }
919 
920 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
921                                           int &FrameIndex,
922                                           unsigned &MemBytes) const {
923   if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
924     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
925         isFrameOperand(MI, 0, FrameIndex))
926       return MI.getOperand(X86::AddrNumOperands).getReg();
927   return 0;
928 }
929 
930 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
931                                                 int &FrameIndex) const {
932   unsigned Dummy;
933   if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
934     unsigned Reg;
935     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
936       return Reg;
937     // Check for post-frame index elimination operations
938     SmallVector<const MachineMemOperand *, 1> Accesses;
939     if (hasStoreToStackSlot(MI, Accesses)) {
940       FrameIndex =
941           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
942               ->getFrameIndex();
943       return 1;
944     }
945   }
946   return 0;
947 }
948 
949 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
950 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
951   // Don't waste compile time scanning use-def chains of physregs.
952   if (!Register::isVirtualRegister(BaseReg))
953     return false;
954   bool isPICBase = false;
955   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
956          E = MRI.def_instr_end(); I != E; ++I) {
957     MachineInstr *DefMI = &*I;
958     if (DefMI->getOpcode() != X86::MOVPC32r)
959       return false;
960     assert(!isPICBase && "More than one PIC base?");
961     isPICBase = true;
962   }
963   return isPICBase;
964 }
965 
966 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
967                                                      AAResults *AA) const {
968   switch (MI.getOpcode()) {
969   default:
970     // This function should only be called for opcodes with the ReMaterializable
971     // flag set.
972     llvm_unreachable("Unknown rematerializable operation!");
973     break;
974 
975   case X86::LOAD_STACK_GUARD:
976   case X86::AVX1_SETALLONES:
977   case X86::AVX2_SETALLONES:
978   case X86::AVX512_128_SET0:
979   case X86::AVX512_256_SET0:
980   case X86::AVX512_512_SET0:
981   case X86::AVX512_512_SETALLONES:
982   case X86::AVX512_FsFLD0SD:
983   case X86::AVX512_FsFLD0SS:
984   case X86::AVX512_FsFLD0F128:
985   case X86::AVX_SET0:
986   case X86::FsFLD0SD:
987   case X86::FsFLD0SS:
988   case X86::FsFLD0F128:
989   case X86::KSET0D:
990   case X86::KSET0Q:
991   case X86::KSET0W:
992   case X86::KSET1D:
993   case X86::KSET1Q:
994   case X86::KSET1W:
995   case X86::MMX_SET0:
996   case X86::MOV32ImmSExti8:
997   case X86::MOV32r0:
998   case X86::MOV32r1:
999   case X86::MOV32r_1:
1000   case X86::MOV32ri64:
1001   case X86::MOV64ImmSExti8:
1002   case X86::V_SET0:
1003   case X86::V_SETALLONES:
1004   case X86::MOV16ri:
1005   case X86::MOV32ri:
1006   case X86::MOV64ri:
1007   case X86::MOV64ri32:
1008   case X86::MOV8ri:
1009     return true;
1010 
1011   case X86::MOV8rm:
1012   case X86::MOV8rm_NOREX:
1013   case X86::MOV16rm:
1014   case X86::MOV32rm:
1015   case X86::MOV64rm:
1016   case X86::MOVSSrm:
1017   case X86::MOVSSrm_alt:
1018   case X86::MOVSDrm:
1019   case X86::MOVSDrm_alt:
1020   case X86::MOVAPSrm:
1021   case X86::MOVUPSrm:
1022   case X86::MOVAPDrm:
1023   case X86::MOVUPDrm:
1024   case X86::MOVDQArm:
1025   case X86::MOVDQUrm:
1026   case X86::VMOVSSrm:
1027   case X86::VMOVSSrm_alt:
1028   case X86::VMOVSDrm:
1029   case X86::VMOVSDrm_alt:
1030   case X86::VMOVAPSrm:
1031   case X86::VMOVUPSrm:
1032   case X86::VMOVAPDrm:
1033   case X86::VMOVUPDrm:
1034   case X86::VMOVDQArm:
1035   case X86::VMOVDQUrm:
1036   case X86::VMOVAPSYrm:
1037   case X86::VMOVUPSYrm:
1038   case X86::VMOVAPDYrm:
1039   case X86::VMOVUPDYrm:
1040   case X86::VMOVDQAYrm:
1041   case X86::VMOVDQUYrm:
1042   case X86::MMX_MOVD64rm:
1043   case X86::MMX_MOVQ64rm:
1044   // AVX-512
1045   case X86::VMOVSSZrm:
1046   case X86::VMOVSSZrm_alt:
1047   case X86::VMOVSDZrm:
1048   case X86::VMOVSDZrm_alt:
1049   case X86::VMOVAPDZ128rm:
1050   case X86::VMOVAPDZ256rm:
1051   case X86::VMOVAPDZrm:
1052   case X86::VMOVAPSZ128rm:
1053   case X86::VMOVAPSZ256rm:
1054   case X86::VMOVAPSZ128rm_NOVLX:
1055   case X86::VMOVAPSZ256rm_NOVLX:
1056   case X86::VMOVAPSZrm:
1057   case X86::VMOVDQA32Z128rm:
1058   case X86::VMOVDQA32Z256rm:
1059   case X86::VMOVDQA32Zrm:
1060   case X86::VMOVDQA64Z128rm:
1061   case X86::VMOVDQA64Z256rm:
1062   case X86::VMOVDQA64Zrm:
1063   case X86::VMOVDQU16Z128rm:
1064   case X86::VMOVDQU16Z256rm:
1065   case X86::VMOVDQU16Zrm:
1066   case X86::VMOVDQU32Z128rm:
1067   case X86::VMOVDQU32Z256rm:
1068   case X86::VMOVDQU32Zrm:
1069   case X86::VMOVDQU64Z128rm:
1070   case X86::VMOVDQU64Z256rm:
1071   case X86::VMOVDQU64Zrm:
1072   case X86::VMOVDQU8Z128rm:
1073   case X86::VMOVDQU8Z256rm:
1074   case X86::VMOVDQU8Zrm:
1075   case X86::VMOVUPDZ128rm:
1076   case X86::VMOVUPDZ256rm:
1077   case X86::VMOVUPDZrm:
1078   case X86::VMOVUPSZ128rm:
1079   case X86::VMOVUPSZ256rm:
1080   case X86::VMOVUPSZ128rm_NOVLX:
1081   case X86::VMOVUPSZ256rm_NOVLX:
1082   case X86::VMOVUPSZrm: {
1083     // Loads from constant pools are trivially rematerializable.
1084     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
1085         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1086         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1087         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1088         MI.isDereferenceableInvariantLoad(AA)) {
1089       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1090       if (BaseReg == 0 || BaseReg == X86::RIP)
1091         return true;
1092       // Allow re-materialization of PIC load.
1093       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
1094         return false;
1095       const MachineFunction &MF = *MI.getParent()->getParent();
1096       const MachineRegisterInfo &MRI = MF.getRegInfo();
1097       return regIsPICBase(BaseReg, MRI);
1098     }
1099     return false;
1100   }
1101 
1102   case X86::LEA32r:
1103   case X86::LEA64r: {
1104     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
1105         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
1106         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
1107         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
1108       // lea fi#, lea GV, etc. are all rematerializable.
1109       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
1110         return true;
1111       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
1112       if (BaseReg == 0)
1113         return true;
1114       // Allow re-materialization of lea PICBase + x.
1115       const MachineFunction &MF = *MI.getParent()->getParent();
1116       const MachineRegisterInfo &MRI = MF.getRegInfo();
1117       return regIsPICBase(BaseReg, MRI);
1118     }
1119     return false;
1120   }
1121   }
1122 }
1123 
1124 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1125                                  MachineBasicBlock::iterator I,
1126                                  Register DestReg, unsigned SubIdx,
1127                                  const MachineInstr &Orig,
1128                                  const TargetRegisterInfo &TRI) const {
1129   bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
1130   if (ClobbersEFLAGS && MBB.computeRegisterLiveness(&TRI, X86::EFLAGS, I) !=
1131                             MachineBasicBlock::LQR_Dead) {
1132     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
1133     // effects.
1134     int Value;
1135     switch (Orig.getOpcode()) {
1136     case X86::MOV32r0:  Value = 0; break;
1137     case X86::MOV32r1:  Value = 1; break;
1138     case X86::MOV32r_1: Value = -1; break;
1139     default:
1140       llvm_unreachable("Unexpected instruction!");
1141     }
1142 
1143     const DebugLoc &DL = Orig.getDebugLoc();
1144     BuildMI(MBB, I, DL, get(X86::MOV32ri))
1145         .add(Orig.getOperand(0))
1146         .addImm(Value);
1147   } else {
1148     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1149     MBB.insert(I, MI);
1150   }
1151 
1152   MachineInstr &NewMI = *std::prev(I);
1153   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1154 }
1155 
1156 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
1157 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
1158   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1159     MachineOperand &MO = MI.getOperand(i);
1160     if (MO.isReg() && MO.isDef() &&
1161         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1162       return true;
1163     }
1164   }
1165   return false;
1166 }
1167 
1168 /// Check whether the shift count for a machine operand is non-zero.
1169 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
1170                                               unsigned ShiftAmtOperandIdx) {
1171   // The shift count is six bits with the REX.W prefix and five bits without.
1172   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
1173   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
1174   return Imm & ShiftCountMask;
1175 }
1176 
1177 /// Check whether the given shift count is appropriate
1178 /// can be represented by a LEA instruction.
1179 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
1180   // Left shift instructions can be transformed into load-effective-address
1181   // instructions if we can encode them appropriately.
1182   // A LEA instruction utilizes a SIB byte to encode its scale factor.
1183   // The SIB.scale field is two bits wide which means that we can encode any
1184   // shift amount less than 4.
1185   return ShAmt < 4 && ShAmt > 0;
1186 }
1187 
1188 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
1189                                   unsigned Opc, bool AllowSP, Register &NewSrc,
1190                                   bool &isKill, MachineOperand &ImplicitOp,
1191                                   LiveVariables *LV) const {
1192   MachineFunction &MF = *MI.getParent()->getParent();
1193   const TargetRegisterClass *RC;
1194   if (AllowSP) {
1195     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
1196   } else {
1197     RC = Opc != X86::LEA32r ?
1198       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
1199   }
1200   Register SrcReg = Src.getReg();
1201 
1202   // For both LEA64 and LEA32 the register already has essentially the right
1203   // type (32-bit or 64-bit) we may just need to forbid SP.
1204   if (Opc != X86::LEA64_32r) {
1205     NewSrc = SrcReg;
1206     isKill = Src.isKill();
1207     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1208 
1209     if (Register::isVirtualRegister(NewSrc) &&
1210         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
1211       return false;
1212 
1213     return true;
1214   }
1215 
1216   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
1217   // another we need to add 64-bit registers to the final MI.
1218   if (Register::isPhysicalRegister(SrcReg)) {
1219     ImplicitOp = Src;
1220     ImplicitOp.setImplicit();
1221 
1222     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
1223     isKill = Src.isKill();
1224     assert(!Src.isUndef() && "Undef op doesn't need optimization");
1225   } else {
1226     // Virtual register of the wrong class, we have to create a temporary 64-bit
1227     // vreg to feed into the LEA.
1228     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
1229     MachineInstr *Copy =
1230         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1231             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
1232             .add(Src);
1233 
1234     // Which is obviously going to be dead after we're done with it.
1235     isKill = true;
1236 
1237     if (LV)
1238       LV->replaceKillInstruction(SrcReg, MI, *Copy);
1239   }
1240 
1241   // We've set all the parameters without issue.
1242   return true;
1243 }
1244 
1245 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
1246     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
1247     LiveVariables *LV, bool Is8BitOp) const {
1248   // We handle 8-bit adds and various 16-bit opcodes in the switch below.
1249   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1250   assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
1251               *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
1252          "Unexpected type for LEA transform");
1253 
1254   // TODO: For a 32-bit target, we need to adjust the LEA variables with
1255   // something like this:
1256   //   Opcode = X86::LEA32r;
1257   //   InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1258   //   OutRegLEA =
1259   //       Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
1260   //                : RegInfo.createVirtualRegister(&X86::GR32RegClass);
1261   if (!Subtarget.is64Bit())
1262     return nullptr;
1263 
1264   unsigned Opcode = X86::LEA64_32r;
1265   Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1266   Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1267 
1268   // Build and insert into an implicit UNDEF value. This is OK because
1269   // we will be shifting and then extracting the lower 8/16-bits.
1270   // This has the potential to cause partial register stall. e.g.
1271   //   movw    (%rbp,%rcx,2), %dx
1272   //   leal    -65(%rdx), %esi
1273   // But testing has shown this *does* help performance in 64-bit mode (at
1274   // least on modern x86 machines).
1275   MachineBasicBlock::iterator MBBI = MI.getIterator();
1276   Register Dest = MI.getOperand(0).getReg();
1277   Register Src = MI.getOperand(1).getReg();
1278   bool IsDead = MI.getOperand(0).isDead();
1279   bool IsKill = MI.getOperand(1).isKill();
1280   unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
1281   assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
1282   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
1283   MachineInstr *InsMI =
1284       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1285           .addReg(InRegLEA, RegState::Define, SubReg)
1286           .addReg(Src, getKillRegState(IsKill));
1287 
1288   MachineInstrBuilder MIB =
1289       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
1290   switch (MIOpc) {
1291   default: llvm_unreachable("Unreachable!");
1292   case X86::SHL8ri:
1293   case X86::SHL16ri: {
1294     unsigned ShAmt = MI.getOperand(2).getImm();
1295     MIB.addReg(0).addImm(1ULL << ShAmt)
1296        .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
1297     break;
1298   }
1299   case X86::INC8r:
1300   case X86::INC16r:
1301     addRegOffset(MIB, InRegLEA, true, 1);
1302     break;
1303   case X86::DEC8r:
1304   case X86::DEC16r:
1305     addRegOffset(MIB, InRegLEA, true, -1);
1306     break;
1307   case X86::ADD8ri:
1308   case X86::ADD8ri_DB:
1309   case X86::ADD16ri:
1310   case X86::ADD16ri8:
1311   case X86::ADD16ri_DB:
1312   case X86::ADD16ri8_DB:
1313     addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
1314     break;
1315   case X86::ADD8rr:
1316   case X86::ADD8rr_DB:
1317   case X86::ADD16rr:
1318   case X86::ADD16rr_DB: {
1319     Register Src2 = MI.getOperand(2).getReg();
1320     bool IsKill2 = MI.getOperand(2).isKill();
1321     assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
1322     unsigned InRegLEA2 = 0;
1323     MachineInstr *InsMI2 = nullptr;
1324     if (Src == Src2) {
1325       // ADD8rr/ADD16rr killed %reg1028, %reg1028
1326       // just a single insert_subreg.
1327       addRegReg(MIB, InRegLEA, true, InRegLEA, false);
1328     } else {
1329       if (Subtarget.is64Bit())
1330         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
1331       else
1332         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1333       // Build and insert into an implicit UNDEF value. This is OK because
1334       // we will be shifting and then extracting the lower 8/16-bits.
1335       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
1336       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
1337                    .addReg(InRegLEA2, RegState::Define, SubReg)
1338                    .addReg(Src2, getKillRegState(IsKill2));
1339       addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
1340     }
1341     if (LV && IsKill2 && InsMI2)
1342       LV->replaceKillInstruction(Src2, MI, *InsMI2);
1343     break;
1344   }
1345   }
1346 
1347   MachineInstr *NewMI = MIB;
1348   MachineInstr *ExtMI =
1349       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
1350           .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
1351           .addReg(OutRegLEA, RegState::Kill, SubReg);
1352 
1353   if (LV) {
1354     // Update live variables.
1355     LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
1356     LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
1357     if (IsKill)
1358       LV->replaceKillInstruction(Src, MI, *InsMI);
1359     if (IsDead)
1360       LV->replaceKillInstruction(Dest, MI, *ExtMI);
1361   }
1362 
1363   return ExtMI;
1364 }
1365 
1366 /// This method must be implemented by targets that
1367 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1368 /// may be able to convert a two-address instruction into a true
1369 /// three-address instruction on demand.  This allows the X86 target (for
1370 /// example) to convert ADD and SHL instructions into LEA instructions if they
1371 /// would require register copies due to two-addressness.
1372 ///
1373 /// This method returns a null pointer if the transformation cannot be
1374 /// performed, otherwise it returns the new instruction.
1375 ///
1376 MachineInstr *
1377 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1378                                     MachineInstr &MI, LiveVariables *LV) const {
1379   // The following opcodes also sets the condition code register(s). Only
1380   // convert them to equivalent lea if the condition code register def's
1381   // are dead!
1382   if (hasLiveCondCodeDef(MI))
1383     return nullptr;
1384 
1385   MachineFunction &MF = *MI.getParent()->getParent();
1386   // All instructions input are two-addr instructions.  Get the known operands.
1387   const MachineOperand &Dest = MI.getOperand(0);
1388   const MachineOperand &Src = MI.getOperand(1);
1389 
1390   // Ideally, operations with undef should be folded before we get here, but we
1391   // can't guarantee it. Bail out because optimizing undefs is a waste of time.
1392   // Without this, we have to forward undef state to new register operands to
1393   // avoid machine verifier errors.
1394   if (Src.isUndef())
1395     return nullptr;
1396   if (MI.getNumOperands() > 2)
1397     if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
1398       return nullptr;
1399 
1400   MachineInstr *NewMI = nullptr;
1401   bool Is64Bit = Subtarget.is64Bit();
1402 
1403   bool Is8BitOp = false;
1404   unsigned MIOpc = MI.getOpcode();
1405   switch (MIOpc) {
1406   default: llvm_unreachable("Unreachable!");
1407   case X86::SHL64ri: {
1408     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1409     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1410     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1411 
1412     // LEA can't handle RSP.
1413     if (Register::isVirtualRegister(Src.getReg()) &&
1414         !MF.getRegInfo().constrainRegClass(Src.getReg(),
1415                                            &X86::GR64_NOSPRegClass))
1416       return nullptr;
1417 
1418     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
1419                 .add(Dest)
1420                 .addReg(0)
1421                 .addImm(1ULL << ShAmt)
1422                 .add(Src)
1423                 .addImm(0)
1424                 .addReg(0);
1425     break;
1426   }
1427   case X86::SHL32ri: {
1428     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1429     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1430     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
1431 
1432     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1433 
1434     // LEA can't handle ESP.
1435     bool isKill;
1436     Register SrcReg;
1437     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1438     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
1439                         SrcReg, isKill, ImplicitOp, LV))
1440       return nullptr;
1441 
1442     MachineInstrBuilder MIB =
1443         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1444             .add(Dest)
1445             .addReg(0)
1446             .addImm(1ULL << ShAmt)
1447             .addReg(SrcReg, getKillRegState(isKill))
1448             .addImm(0)
1449             .addReg(0);
1450     if (ImplicitOp.getReg() != 0)
1451       MIB.add(ImplicitOp);
1452     NewMI = MIB;
1453 
1454     break;
1455   }
1456   case X86::SHL8ri:
1457     Is8BitOp = true;
1458     LLVM_FALLTHROUGH;
1459   case X86::SHL16ri: {
1460     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
1461     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
1462     if (!isTruncatedShiftCountForLEA(ShAmt))
1463       return nullptr;
1464     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1465   }
1466   case X86::INC64r:
1467   case X86::INC32r: {
1468     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1469     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
1470         (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1471     bool isKill;
1472     Register SrcReg;
1473     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1474     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1475                         ImplicitOp, LV))
1476       return nullptr;
1477 
1478     MachineInstrBuilder MIB =
1479         BuildMI(MF, MI.getDebugLoc(), get(Opc))
1480             .add(Dest)
1481             .addReg(SrcReg, getKillRegState(isKill));
1482     if (ImplicitOp.getReg() != 0)
1483       MIB.add(ImplicitOp);
1484 
1485     NewMI = addOffset(MIB, 1);
1486     break;
1487   }
1488   case X86::DEC64r:
1489   case X86::DEC32r: {
1490     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1491     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1492         : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
1493 
1494     bool isKill;
1495     Register SrcReg;
1496     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1497     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
1498                         ImplicitOp, LV))
1499       return nullptr;
1500 
1501     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1502                                   .add(Dest)
1503                                   .addReg(SrcReg, getKillRegState(isKill));
1504     if (ImplicitOp.getReg() != 0)
1505       MIB.add(ImplicitOp);
1506 
1507     NewMI = addOffset(MIB, -1);
1508 
1509     break;
1510   }
1511   case X86::DEC8r:
1512   case X86::INC8r:
1513     Is8BitOp = true;
1514     LLVM_FALLTHROUGH;
1515   case X86::DEC16r:
1516   case X86::INC16r:
1517     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1518   case X86::ADD64rr:
1519   case X86::ADD64rr_DB:
1520   case X86::ADD32rr:
1521   case X86::ADD32rr_DB: {
1522     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1523     unsigned Opc;
1524     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1525       Opc = X86::LEA64r;
1526     else
1527       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1528 
1529     bool isKill;
1530     Register SrcReg;
1531     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1532     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1533                         SrcReg, isKill, ImplicitOp, LV))
1534       return nullptr;
1535 
1536     const MachineOperand &Src2 = MI.getOperand(2);
1537     bool isKill2;
1538     Register SrcReg2;
1539     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1540     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1541                         SrcReg2, isKill2, ImplicitOp2, LV))
1542       return nullptr;
1543 
1544     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1545     if (ImplicitOp.getReg() != 0)
1546       MIB.add(ImplicitOp);
1547     if (ImplicitOp2.getReg() != 0)
1548       MIB.add(ImplicitOp2);
1549 
1550     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1551     if (LV && Src2.isKill())
1552       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1553     break;
1554   }
1555   case X86::ADD8rr:
1556   case X86::ADD8rr_DB:
1557     Is8BitOp = true;
1558     LLVM_FALLTHROUGH;
1559   case X86::ADD16rr:
1560   case X86::ADD16rr_DB:
1561     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1562   case X86::ADD64ri32:
1563   case X86::ADD64ri8:
1564   case X86::ADD64ri32_DB:
1565   case X86::ADD64ri8_DB:
1566     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1567     NewMI = addOffset(
1568         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1569         MI.getOperand(2));
1570     break;
1571   case X86::ADD32ri:
1572   case X86::ADD32ri8:
1573   case X86::ADD32ri_DB:
1574   case X86::ADD32ri8_DB: {
1575     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1576     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1577 
1578     bool isKill;
1579     Register SrcReg;
1580     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1581     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1582                         SrcReg, isKill, ImplicitOp, LV))
1583       return nullptr;
1584 
1585     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1586                                   .add(Dest)
1587                                   .addReg(SrcReg, getKillRegState(isKill));
1588     if (ImplicitOp.getReg() != 0)
1589       MIB.add(ImplicitOp);
1590 
1591     NewMI = addOffset(MIB, MI.getOperand(2));
1592     break;
1593   }
1594   case X86::ADD8ri:
1595   case X86::ADD8ri_DB:
1596     Is8BitOp = true;
1597     LLVM_FALLTHROUGH;
1598   case X86::ADD16ri:
1599   case X86::ADD16ri8:
1600   case X86::ADD16ri_DB:
1601   case X86::ADD16ri8_DB:
1602     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1603   case X86::SUB8ri:
1604   case X86::SUB16ri8:
1605   case X86::SUB16ri:
1606     /// FIXME: Support these similar to ADD8ri/ADD16ri*.
1607     return nullptr;
1608   case X86::SUB32ri8:
1609   case X86::SUB32ri: {
1610     if (!MI.getOperand(2).isImm())
1611       return nullptr;
1612     int64_t Imm = MI.getOperand(2).getImm();
1613     if (!isInt<32>(-Imm))
1614       return nullptr;
1615 
1616     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1617     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1618 
1619     bool isKill;
1620     Register SrcReg;
1621     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1622     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1623                         SrcReg, isKill, ImplicitOp, LV))
1624       return nullptr;
1625 
1626     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1627                                   .add(Dest)
1628                                   .addReg(SrcReg, getKillRegState(isKill));
1629     if (ImplicitOp.getReg() != 0)
1630       MIB.add(ImplicitOp);
1631 
1632     NewMI = addOffset(MIB, -Imm);
1633     break;
1634   }
1635 
1636   case X86::SUB64ri8:
1637   case X86::SUB64ri32: {
1638     if (!MI.getOperand(2).isImm())
1639       return nullptr;
1640     int64_t Imm = MI.getOperand(2).getImm();
1641     if (!isInt<32>(-Imm))
1642       return nullptr;
1643 
1644     assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!");
1645 
1646     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
1647                                       get(X86::LEA64r)).add(Dest).add(Src);
1648     NewMI = addOffset(MIB, -Imm);
1649     break;
1650   }
1651 
1652   case X86::VMOVDQU8Z128rmk:
1653   case X86::VMOVDQU8Z256rmk:
1654   case X86::VMOVDQU8Zrmk:
1655   case X86::VMOVDQU16Z128rmk:
1656   case X86::VMOVDQU16Z256rmk:
1657   case X86::VMOVDQU16Zrmk:
1658   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1659   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1660   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
1661   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1662   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1663   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
1664   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
1665   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
1666   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
1667   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
1668   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
1669   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk:
1670   case X86::VBROADCASTSDZ256rmk:
1671   case X86::VBROADCASTSDZrmk:
1672   case X86::VBROADCASTSSZ128rmk:
1673   case X86::VBROADCASTSSZ256rmk:
1674   case X86::VBROADCASTSSZrmk:
1675   case X86::VPBROADCASTDZ128rmk:
1676   case X86::VPBROADCASTDZ256rmk:
1677   case X86::VPBROADCASTDZrmk:
1678   case X86::VPBROADCASTQZ128rmk:
1679   case X86::VPBROADCASTQZ256rmk:
1680   case X86::VPBROADCASTQZrmk: {
1681     unsigned Opc;
1682     switch (MIOpc) {
1683     default: llvm_unreachable("Unreachable!");
1684     case X86::VMOVDQU8Z128rmk:     Opc = X86::VPBLENDMBZ128rmk; break;
1685     case X86::VMOVDQU8Z256rmk:     Opc = X86::VPBLENDMBZ256rmk; break;
1686     case X86::VMOVDQU8Zrmk:        Opc = X86::VPBLENDMBZrmk;    break;
1687     case X86::VMOVDQU16Z128rmk:    Opc = X86::VPBLENDMWZ128rmk; break;
1688     case X86::VMOVDQU16Z256rmk:    Opc = X86::VPBLENDMWZ256rmk; break;
1689     case X86::VMOVDQU16Zrmk:       Opc = X86::VPBLENDMWZrmk;    break;
1690     case X86::VMOVDQU32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1691     case X86::VMOVDQU32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1692     case X86::VMOVDQU32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1693     case X86::VMOVDQU64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1694     case X86::VMOVDQU64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1695     case X86::VMOVDQU64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1696     case X86::VMOVUPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1697     case X86::VMOVUPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1698     case X86::VMOVUPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1699     case X86::VMOVUPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1700     case X86::VMOVUPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1701     case X86::VMOVUPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1702     case X86::VMOVDQA32Z128rmk:    Opc = X86::VPBLENDMDZ128rmk; break;
1703     case X86::VMOVDQA32Z256rmk:    Opc = X86::VPBLENDMDZ256rmk; break;
1704     case X86::VMOVDQA32Zrmk:       Opc = X86::VPBLENDMDZrmk;    break;
1705     case X86::VMOVDQA64Z128rmk:    Opc = X86::VPBLENDMQZ128rmk; break;
1706     case X86::VMOVDQA64Z256rmk:    Opc = X86::VPBLENDMQZ256rmk; break;
1707     case X86::VMOVDQA64Zrmk:       Opc = X86::VPBLENDMQZrmk;    break;
1708     case X86::VMOVAPDZ128rmk:      Opc = X86::VBLENDMPDZ128rmk; break;
1709     case X86::VMOVAPDZ256rmk:      Opc = X86::VBLENDMPDZ256rmk; break;
1710     case X86::VMOVAPDZrmk:         Opc = X86::VBLENDMPDZrmk;    break;
1711     case X86::VMOVAPSZ128rmk:      Opc = X86::VBLENDMPSZ128rmk; break;
1712     case X86::VMOVAPSZ256rmk:      Opc = X86::VBLENDMPSZ256rmk; break;
1713     case X86::VMOVAPSZrmk:         Opc = X86::VBLENDMPSZrmk;    break;
1714     case X86::VBROADCASTSDZ256rmk: Opc = X86::VBLENDMPDZ256rmbk; break;
1715     case X86::VBROADCASTSDZrmk:    Opc = X86::VBLENDMPDZrmbk;    break;
1716     case X86::VBROADCASTSSZ128rmk: Opc = X86::VBLENDMPSZ128rmbk; break;
1717     case X86::VBROADCASTSSZ256rmk: Opc = X86::VBLENDMPSZ256rmbk; break;
1718     case X86::VBROADCASTSSZrmk:    Opc = X86::VBLENDMPSZrmbk;    break;
1719     case X86::VPBROADCASTDZ128rmk: Opc = X86::VPBLENDMDZ128rmbk; break;
1720     case X86::VPBROADCASTDZ256rmk: Opc = X86::VPBLENDMDZ256rmbk; break;
1721     case X86::VPBROADCASTDZrmk:    Opc = X86::VPBLENDMDZrmbk;    break;
1722     case X86::VPBROADCASTQZ128rmk: Opc = X86::VPBLENDMQZ128rmbk; break;
1723     case X86::VPBROADCASTQZ256rmk: Opc = X86::VPBLENDMQZ256rmbk; break;
1724     case X86::VPBROADCASTQZrmk:    Opc = X86::VPBLENDMQZrmbk;    break;
1725     }
1726 
1727     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1728               .add(Dest)
1729               .add(MI.getOperand(2))
1730               .add(Src)
1731               .add(MI.getOperand(3))
1732               .add(MI.getOperand(4))
1733               .add(MI.getOperand(5))
1734               .add(MI.getOperand(6))
1735               .add(MI.getOperand(7));
1736     break;
1737   }
1738 
1739   case X86::VMOVDQU8Z128rrk:
1740   case X86::VMOVDQU8Z256rrk:
1741   case X86::VMOVDQU8Zrrk:
1742   case X86::VMOVDQU16Z128rrk:
1743   case X86::VMOVDQU16Z256rrk:
1744   case X86::VMOVDQU16Zrrk:
1745   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1746   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1747   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
1748   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1749   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1750   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
1751   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
1752   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
1753   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
1754   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
1755   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
1756   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
1757     unsigned Opc;
1758     switch (MIOpc) {
1759     default: llvm_unreachable("Unreachable!");
1760     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
1761     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
1762     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
1763     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1764     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1765     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
1766     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1767     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1768     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1769     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1770     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1771     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1772     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1773     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1774     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1775     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1776     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1777     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1778     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1779     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1780     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1781     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1782     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1783     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1784     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1785     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1786     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1787     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1788     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1789     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1790     }
1791 
1792     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1793               .add(Dest)
1794               .add(MI.getOperand(2))
1795               .add(Src)
1796               .add(MI.getOperand(3));
1797     break;
1798   }
1799   }
1800 
1801   if (!NewMI) return nullptr;
1802 
1803   if (LV) {  // Update live variables
1804     if (Src.isKill())
1805       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1806     if (Dest.isDead())
1807       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1808   }
1809 
1810   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1811   return NewMI;
1812 }
1813 
1814 /// This determines which of three possible cases of a three source commute
1815 /// the source indexes correspond to taking into account any mask operands.
1816 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1817 /// possible.
1818 /// Case 0 - Possible to commute the first and second operands.
1819 /// Case 1 - Possible to commute the first and third operands.
1820 /// Case 2 - Possible to commute the second and third operands.
1821 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1822                                        unsigned SrcOpIdx2) {
1823   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1824   if (SrcOpIdx1 > SrcOpIdx2)
1825     std::swap(SrcOpIdx1, SrcOpIdx2);
1826 
1827   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1828   if (X86II::isKMasked(TSFlags)) {
1829     Op2++;
1830     Op3++;
1831   }
1832 
1833   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1834     return 0;
1835   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1836     return 1;
1837   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1838     return 2;
1839   llvm_unreachable("Unknown three src commute case.");
1840 }
1841 
1842 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1843     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1844     const X86InstrFMA3Group &FMA3Group) const {
1845 
1846   unsigned Opc = MI.getOpcode();
1847 
1848   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1849   // analysis. The commute optimization is legal only if all users of FMA*_Int
1850   // use only the lowest element of the FMA*_Int instruction. Such analysis are
1851   // not implemented yet. So, just return 0 in that case.
1852   // When such analysis are available this place will be the right place for
1853   // calling it.
1854   assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1855          "Intrinsic instructions can't commute operand 1");
1856 
1857   // Determine which case this commute is or if it can't be done.
1858   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1859                                          SrcOpIdx2);
1860   assert(Case < 3 && "Unexpected case number!");
1861 
1862   // Define the FMA forms mapping array that helps to map input FMA form
1863   // to output FMA form to preserve the operation semantics after
1864   // commuting the operands.
1865   const unsigned Form132Index = 0;
1866   const unsigned Form213Index = 1;
1867   const unsigned Form231Index = 2;
1868   static const unsigned FormMapping[][3] = {
1869     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1870     // FMA132 A, C, b; ==> FMA231 C, A, b;
1871     // FMA213 B, A, c; ==> FMA213 A, B, c;
1872     // FMA231 C, A, b; ==> FMA132 A, C, b;
1873     { Form231Index, Form213Index, Form132Index },
1874     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1875     // FMA132 A, c, B; ==> FMA132 B, c, A;
1876     // FMA213 B, a, C; ==> FMA231 C, a, B;
1877     // FMA231 C, a, B; ==> FMA213 B, a, C;
1878     { Form132Index, Form231Index, Form213Index },
1879     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1880     // FMA132 a, C, B; ==> FMA213 a, B, C;
1881     // FMA213 b, A, C; ==> FMA132 b, C, A;
1882     // FMA231 c, A, B; ==> FMA231 c, B, A;
1883     { Form213Index, Form132Index, Form231Index }
1884   };
1885 
1886   unsigned FMAForms[3];
1887   FMAForms[0] = FMA3Group.get132Opcode();
1888   FMAForms[1] = FMA3Group.get213Opcode();
1889   FMAForms[2] = FMA3Group.get231Opcode();
1890   unsigned FormIndex;
1891   for (FormIndex = 0; FormIndex < 3; FormIndex++)
1892     if (Opc == FMAForms[FormIndex])
1893       break;
1894 
1895   // Everything is ready, just adjust the FMA opcode and return it.
1896   FormIndex = FormMapping[Case][FormIndex];
1897   return FMAForms[FormIndex];
1898 }
1899 
1900 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1901                              unsigned SrcOpIdx2) {
1902   // Determine which case this commute is or if it can't be done.
1903   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1904                                          SrcOpIdx2);
1905   assert(Case < 3 && "Unexpected case value!");
1906 
1907   // For each case we need to swap two pairs of bits in the final immediate.
1908   static const uint8_t SwapMasks[3][4] = {
1909     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1910     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1911     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1912   };
1913 
1914   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1915   // Clear out the bits we are swapping.
1916   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1917                            SwapMasks[Case][2] | SwapMasks[Case][3]);
1918   // If the immediate had a bit of the pair set, then set the opposite bit.
1919   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1920   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1921   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1922   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1923   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1924 }
1925 
1926 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1927 // commuted.
1928 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1929 #define VPERM_CASES(Suffix) \
1930   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
1931   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
1932   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
1933   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
1934   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
1935   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
1936   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
1937   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
1938   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
1939   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
1940   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
1941   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
1942 
1943 #define VPERM_CASES_BROADCAST(Suffix) \
1944   VPERM_CASES(Suffix) \
1945   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
1946   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
1947   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
1948   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1949   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1950   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
1951 
1952   switch (Opcode) {
1953   default: return false;
1954   VPERM_CASES(B)
1955   VPERM_CASES_BROADCAST(D)
1956   VPERM_CASES_BROADCAST(PD)
1957   VPERM_CASES_BROADCAST(PS)
1958   VPERM_CASES_BROADCAST(Q)
1959   VPERM_CASES(W)
1960     return true;
1961   }
1962 #undef VPERM_CASES_BROADCAST
1963 #undef VPERM_CASES
1964 }
1965 
1966 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1967 // from the I opcode to the T opcode and vice versa.
1968 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1969 #define VPERM_CASES(Orig, New) \
1970   case X86::Orig##128rr:    return X86::New##128rr;   \
1971   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
1972   case X86::Orig##128rm:    return X86::New##128rm;   \
1973   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
1974   case X86::Orig##256rr:    return X86::New##256rr;   \
1975   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
1976   case X86::Orig##256rm:    return X86::New##256rm;   \
1977   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
1978   case X86::Orig##rr:       return X86::New##rr;      \
1979   case X86::Orig##rrkz:     return X86::New##rrkz;    \
1980   case X86::Orig##rm:       return X86::New##rm;      \
1981   case X86::Orig##rmkz:     return X86::New##rmkz;
1982 
1983 #define VPERM_CASES_BROADCAST(Orig, New) \
1984   VPERM_CASES(Orig, New) \
1985   case X86::Orig##128rmb:   return X86::New##128rmb;   \
1986   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1987   case X86::Orig##256rmb:   return X86::New##256rmb;   \
1988   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1989   case X86::Orig##rmb:      return X86::New##rmb;      \
1990   case X86::Orig##rmbkz:    return X86::New##rmbkz;
1991 
1992   switch (Opcode) {
1993   VPERM_CASES(VPERMI2B, VPERMT2B)
1994   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
1995   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1996   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1997   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
1998   VPERM_CASES(VPERMI2W, VPERMT2W)
1999   VPERM_CASES(VPERMT2B, VPERMI2B)
2000   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
2001   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
2002   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
2003   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
2004   VPERM_CASES(VPERMT2W, VPERMI2W)
2005   }
2006 
2007   llvm_unreachable("Unreachable!");
2008 #undef VPERM_CASES_BROADCAST
2009 #undef VPERM_CASES
2010 }
2011 
2012 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
2013                                                    unsigned OpIdx1,
2014                                                    unsigned OpIdx2) const {
2015   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
2016     if (NewMI)
2017       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
2018     return MI;
2019   };
2020 
2021   switch (MI.getOpcode()) {
2022   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2023   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2024   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2025   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2026   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2027   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2028     unsigned Opc;
2029     unsigned Size;
2030     switch (MI.getOpcode()) {
2031     default: llvm_unreachable("Unreachable!");
2032     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2033     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2034     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2035     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2036     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2037     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2038     }
2039     unsigned Amt = MI.getOperand(3).getImm();
2040     auto &WorkingMI = cloneIfNew(MI);
2041     WorkingMI.setDesc(get(Opc));
2042     WorkingMI.getOperand(3).setImm(Size - Amt);
2043     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2044                                                    OpIdx1, OpIdx2);
2045   }
2046   case X86::PFSUBrr:
2047   case X86::PFSUBRrr: {
2048     // PFSUB  x, y: x = x - y
2049     // PFSUBR x, y: x = y - x
2050     unsigned Opc =
2051         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
2052     auto &WorkingMI = cloneIfNew(MI);
2053     WorkingMI.setDesc(get(Opc));
2054     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2055                                                    OpIdx1, OpIdx2);
2056   }
2057   case X86::BLENDPDrri:
2058   case X86::BLENDPSrri:
2059   case X86::VBLENDPDrri:
2060   case X86::VBLENDPSrri:
2061     // If we're optimizing for size, try to use MOVSD/MOVSS.
2062     if (MI.getParent()->getParent()->getFunction().hasOptSize()) {
2063       unsigned Mask, Opc;
2064       switch (MI.getOpcode()) {
2065       default: llvm_unreachable("Unreachable!");
2066       case X86::BLENDPDrri:  Opc = X86::MOVSDrr;  Mask = 0x03; break;
2067       case X86::BLENDPSrri:  Opc = X86::MOVSSrr;  Mask = 0x0F; break;
2068       case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
2069       case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
2070       }
2071       if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
2072         auto &WorkingMI = cloneIfNew(MI);
2073         WorkingMI.setDesc(get(Opc));
2074         WorkingMI.RemoveOperand(3);
2075         return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
2076                                                        /*NewMI=*/false,
2077                                                        OpIdx1, OpIdx2);
2078       }
2079     }
2080     LLVM_FALLTHROUGH;
2081   case X86::PBLENDWrri:
2082   case X86::VBLENDPDYrri:
2083   case X86::VBLENDPSYrri:
2084   case X86::VPBLENDDrri:
2085   case X86::VPBLENDWrri:
2086   case X86::VPBLENDDYrri:
2087   case X86::VPBLENDWYrri:{
2088     int8_t Mask;
2089     switch (MI.getOpcode()) {
2090     default: llvm_unreachable("Unreachable!");
2091     case X86::BLENDPDrri:    Mask = (int8_t)0x03; break;
2092     case X86::BLENDPSrri:    Mask = (int8_t)0x0F; break;
2093     case X86::PBLENDWrri:    Mask = (int8_t)0xFF; break;
2094     case X86::VBLENDPDrri:   Mask = (int8_t)0x03; break;
2095     case X86::VBLENDPSrri:   Mask = (int8_t)0x0F; break;
2096     case X86::VBLENDPDYrri:  Mask = (int8_t)0x0F; break;
2097     case X86::VBLENDPSYrri:  Mask = (int8_t)0xFF; break;
2098     case X86::VPBLENDDrri:   Mask = (int8_t)0x0F; break;
2099     case X86::VPBLENDWrri:   Mask = (int8_t)0xFF; break;
2100     case X86::VPBLENDDYrri:  Mask = (int8_t)0xFF; break;
2101     case X86::VPBLENDWYrri:  Mask = (int8_t)0xFF; break;
2102     }
2103     // Only the least significant bits of Imm are used.
2104     // Using int8_t to ensure it will be sign extended to the int64_t that
2105     // setImm takes in order to match isel behavior.
2106     int8_t Imm = MI.getOperand(3).getImm() & Mask;
2107     auto &WorkingMI = cloneIfNew(MI);
2108     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
2109     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2110                                                    OpIdx1, OpIdx2);
2111   }
2112   case X86::INSERTPSrr:
2113   case X86::VINSERTPSrr:
2114   case X86::VINSERTPSZrr: {
2115     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
2116     unsigned ZMask = Imm & 15;
2117     unsigned DstIdx = (Imm >> 4) & 3;
2118     unsigned SrcIdx = (Imm >> 6) & 3;
2119 
2120     // We can commute insertps if we zero 2 of the elements, the insertion is
2121     // "inline" and we don't override the insertion with a zero.
2122     if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
2123         countPopulation(ZMask) == 2) {
2124       unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
2125       assert(AltIdx < 4 && "Illegal insertion index");
2126       unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
2127       auto &WorkingMI = cloneIfNew(MI);
2128       WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
2129       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2130                                                      OpIdx1, OpIdx2);
2131     }
2132     return nullptr;
2133   }
2134   case X86::MOVSDrr:
2135   case X86::MOVSSrr:
2136   case X86::VMOVSDrr:
2137   case X86::VMOVSSrr:{
2138     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
2139     if (Subtarget.hasSSE41()) {
2140       unsigned Mask, Opc;
2141       switch (MI.getOpcode()) {
2142       default: llvm_unreachable("Unreachable!");
2143       case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
2144       case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
2145       case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
2146       case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
2147       }
2148 
2149       auto &WorkingMI = cloneIfNew(MI);
2150       WorkingMI.setDesc(get(Opc));
2151       WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
2152       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2153                                                      OpIdx1, OpIdx2);
2154     }
2155 
2156     // Convert to SHUFPD.
2157     assert(MI.getOpcode() == X86::MOVSDrr &&
2158            "Can only commute MOVSDrr without SSE4.1");
2159 
2160     auto &WorkingMI = cloneIfNew(MI);
2161     WorkingMI.setDesc(get(X86::SHUFPDrri));
2162     WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2163     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2164                                                    OpIdx1, OpIdx2);
2165   }
2166   case X86::SHUFPDrri: {
2167     // Commute to MOVSD.
2168     assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
2169     auto &WorkingMI = cloneIfNew(MI);
2170     WorkingMI.setDesc(get(X86::MOVSDrr));
2171     WorkingMI.RemoveOperand(3);
2172     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2173                                                    OpIdx1, OpIdx2);
2174   }
2175   case X86::PCLMULQDQrr:
2176   case X86::VPCLMULQDQrr:
2177   case X86::VPCLMULQDQYrr:
2178   case X86::VPCLMULQDQZrr:
2179   case X86::VPCLMULQDQZ128rr:
2180   case X86::VPCLMULQDQZ256rr: {
2181     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2182     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2183     unsigned Imm = MI.getOperand(3).getImm();
2184     unsigned Src1Hi = Imm & 0x01;
2185     unsigned Src2Hi = Imm & 0x10;
2186     auto &WorkingMI = cloneIfNew(MI);
2187     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2188     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2189                                                    OpIdx1, OpIdx2);
2190   }
2191   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
2192   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
2193   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
2194   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
2195   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
2196   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
2197   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
2198   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
2199   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
2200   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
2201   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
2202   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
2203   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
2204   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
2205   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
2206   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
2207   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
2208   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
2209   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
2210   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
2211   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
2212   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
2213   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
2214   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
2215     // Flip comparison mode immediate (if necessary).
2216     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
2217     Imm = X86::getSwappedVPCMPImm(Imm);
2218     auto &WorkingMI = cloneIfNew(MI);
2219     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
2220     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2221                                                    OpIdx1, OpIdx2);
2222   }
2223   case X86::VPCOMBri: case X86::VPCOMUBri:
2224   case X86::VPCOMDri: case X86::VPCOMUDri:
2225   case X86::VPCOMQri: case X86::VPCOMUQri:
2226   case X86::VPCOMWri: case X86::VPCOMUWri: {
2227     // Flip comparison mode immediate (if necessary).
2228     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
2229     Imm = X86::getSwappedVPCOMImm(Imm);
2230     auto &WorkingMI = cloneIfNew(MI);
2231     WorkingMI.getOperand(3).setImm(Imm);
2232     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2233                                                    OpIdx1, OpIdx2);
2234   }
2235   case X86::VCMPSDZrr:
2236   case X86::VCMPSSZrr:
2237   case X86::VCMPPDZrri:
2238   case X86::VCMPPSZrri:
2239   case X86::VCMPPDZ128rri:
2240   case X86::VCMPPSZ128rri:
2241   case X86::VCMPPDZ256rri:
2242   case X86::VCMPPSZ256rri:
2243   case X86::VCMPPDZrrik:
2244   case X86::VCMPPSZrrik:
2245   case X86::VCMPPDZ128rrik:
2246   case X86::VCMPPSZ128rrik:
2247   case X86::VCMPPDZ256rrik:
2248   case X86::VCMPPSZ256rrik: {
2249     unsigned Imm =
2250                 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f;
2251     Imm = X86::getSwappedVCMPImm(Imm);
2252     auto &WorkingMI = cloneIfNew(MI);
2253     WorkingMI.getOperand(MI.getNumExplicitOperands() - 1).setImm(Imm);
2254     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2255                                                    OpIdx1, OpIdx2);
2256   }
2257   case X86::VPERM2F128rr:
2258   case X86::VPERM2I128rr: {
2259     // Flip permute source immediate.
2260     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
2261     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
2262     int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
2263     auto &WorkingMI = cloneIfNew(MI);
2264     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
2265     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2266                                                    OpIdx1, OpIdx2);
2267   }
2268   case X86::MOVHLPSrr:
2269   case X86::UNPCKHPDrr:
2270   case X86::VMOVHLPSrr:
2271   case X86::VUNPCKHPDrr:
2272   case X86::VMOVHLPSZrr:
2273   case X86::VUNPCKHPDZ128rr: {
2274     assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
2275 
2276     unsigned Opc = MI.getOpcode();
2277     switch (Opc) {
2278     default: llvm_unreachable("Unreachable!");
2279     case X86::MOVHLPSrr:       Opc = X86::UNPCKHPDrr;      break;
2280     case X86::UNPCKHPDrr:      Opc = X86::MOVHLPSrr;       break;
2281     case X86::VMOVHLPSrr:      Opc = X86::VUNPCKHPDrr;     break;
2282     case X86::VUNPCKHPDrr:     Opc = X86::VMOVHLPSrr;      break;
2283     case X86::VMOVHLPSZrr:     Opc = X86::VUNPCKHPDZ128rr; break;
2284     case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr;     break;
2285     }
2286     auto &WorkingMI = cloneIfNew(MI);
2287     WorkingMI.setDesc(get(Opc));
2288     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2289                                                    OpIdx1, OpIdx2);
2290   }
2291   case X86::CMOV16rr:  case X86::CMOV32rr:  case X86::CMOV64rr: {
2292     auto &WorkingMI = cloneIfNew(MI);
2293     unsigned OpNo = MI.getDesc().getNumOperands() - 1;
2294     X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
2295     WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2296     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2297                                                    OpIdx1, OpIdx2);
2298   }
2299   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2300   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2301   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2302   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2303   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2304   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2305   case X86::VPTERNLOGDZrrik:
2306   case X86::VPTERNLOGDZ128rrik:
2307   case X86::VPTERNLOGDZ256rrik:
2308   case X86::VPTERNLOGQZrrik:
2309   case X86::VPTERNLOGQZ128rrik:
2310   case X86::VPTERNLOGQZ256rrik:
2311   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2312   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2313   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2314   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2315   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2316   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2317   case X86::VPTERNLOGDZ128rmbi:
2318   case X86::VPTERNLOGDZ256rmbi:
2319   case X86::VPTERNLOGDZrmbi:
2320   case X86::VPTERNLOGQZ128rmbi:
2321   case X86::VPTERNLOGQZ256rmbi:
2322   case X86::VPTERNLOGQZrmbi:
2323   case X86::VPTERNLOGDZ128rmbikz:
2324   case X86::VPTERNLOGDZ256rmbikz:
2325   case X86::VPTERNLOGDZrmbikz:
2326   case X86::VPTERNLOGQZ128rmbikz:
2327   case X86::VPTERNLOGQZ256rmbikz:
2328   case X86::VPTERNLOGQZrmbikz: {
2329     auto &WorkingMI = cloneIfNew(MI);
2330     commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
2331     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2332                                                    OpIdx1, OpIdx2);
2333   }
2334   default: {
2335     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
2336       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
2337       auto &WorkingMI = cloneIfNew(MI);
2338       WorkingMI.setDesc(get(Opc));
2339       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2340                                                      OpIdx1, OpIdx2);
2341     }
2342 
2343     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2344                                                       MI.getDesc().TSFlags);
2345     if (FMA3Group) {
2346       unsigned Opc =
2347         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
2348       auto &WorkingMI = cloneIfNew(MI);
2349       WorkingMI.setDesc(get(Opc));
2350       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
2351                                                      OpIdx1, OpIdx2);
2352     }
2353 
2354     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2355   }
2356   }
2357 }
2358 
2359 bool
2360 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
2361                                             unsigned &SrcOpIdx1,
2362                                             unsigned &SrcOpIdx2,
2363                                             bool IsIntrinsic) const {
2364   uint64_t TSFlags = MI.getDesc().TSFlags;
2365 
2366   unsigned FirstCommutableVecOp = 1;
2367   unsigned LastCommutableVecOp = 3;
2368   unsigned KMaskOp = -1U;
2369   if (X86II::isKMasked(TSFlags)) {
2370     // For k-zero-masked operations it is Ok to commute the first vector
2371     // operand. Unless this is an intrinsic instruction.
2372     // For regular k-masked operations a conservative choice is done as the
2373     // elements of the first vector operand, for which the corresponding bit
2374     // in the k-mask operand is set to 0, are copied to the result of the
2375     // instruction.
2376     // TODO/FIXME: The commute still may be legal if it is known that the
2377     // k-mask operand is set to either all ones or all zeroes.
2378     // It is also Ok to commute the 1st operand if all users of MI use only
2379     // the elements enabled by the k-mask operand. For example,
2380     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
2381     //                                                     : v1[i];
2382     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
2383     //                                  // Ok, to commute v1 in FMADD213PSZrk.
2384 
2385     // The k-mask operand has index = 2 for masked and zero-masked operations.
2386     KMaskOp = 2;
2387 
2388     // The operand with index = 1 is used as a source for those elements for
2389     // which the corresponding bit in the k-mask is set to 0.
2390     if (X86II::isKMergeMasked(TSFlags) || IsIntrinsic)
2391       FirstCommutableVecOp = 3;
2392 
2393     LastCommutableVecOp++;
2394   } else if (IsIntrinsic) {
2395     // Commuting the first operand of an intrinsic instruction isn't possible
2396     // unless we can prove that only the lowest element of the result is used.
2397     FirstCommutableVecOp = 2;
2398   }
2399 
2400   if (isMem(MI, LastCommutableVecOp))
2401     LastCommutableVecOp--;
2402 
2403   // Only the first RegOpsNum operands are commutable.
2404   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
2405   // that the operand is not specified/fixed.
2406   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
2407       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
2408        SrcOpIdx1 == KMaskOp))
2409     return false;
2410   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
2411       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
2412        SrcOpIdx2 == KMaskOp))
2413     return false;
2414 
2415   // Look for two different register operands assumed to be commutable
2416   // regardless of the FMA opcode. The FMA opcode is adjusted later.
2417   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
2418       SrcOpIdx2 == CommuteAnyOperandIndex) {
2419     unsigned CommutableOpIdx2 = SrcOpIdx2;
2420 
2421     // At least one of operands to be commuted is not specified and
2422     // this method is free to choose appropriate commutable operands.
2423     if (SrcOpIdx1 == SrcOpIdx2)
2424       // Both of operands are not fixed. By default set one of commutable
2425       // operands to the last register operand of the instruction.
2426       CommutableOpIdx2 = LastCommutableVecOp;
2427     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
2428       // Only one of operands is not fixed.
2429       CommutableOpIdx2 = SrcOpIdx1;
2430 
2431     // CommutableOpIdx2 is well defined now. Let's choose another commutable
2432     // operand and assign its index to CommutableOpIdx1.
2433     Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
2434 
2435     unsigned CommutableOpIdx1;
2436     for (CommutableOpIdx1 = LastCommutableVecOp;
2437          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
2438       // Just ignore and skip the k-mask operand.
2439       if (CommutableOpIdx1 == KMaskOp)
2440         continue;
2441 
2442       // The commuted operands must have different registers.
2443       // Otherwise, the commute transformation does not change anything and
2444       // is useless then.
2445       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
2446         break;
2447     }
2448 
2449     // No appropriate commutable operands were found.
2450     if (CommutableOpIdx1 < FirstCommutableVecOp)
2451       return false;
2452 
2453     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
2454     // to return those values.
2455     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2456                               CommutableOpIdx1, CommutableOpIdx2))
2457       return false;
2458   }
2459 
2460   return true;
2461 }
2462 
2463 bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI,
2464                                          unsigned &SrcOpIdx1,
2465                                          unsigned &SrcOpIdx2) const {
2466   const MCInstrDesc &Desc = MI.getDesc();
2467   if (!Desc.isCommutable())
2468     return false;
2469 
2470   switch (MI.getOpcode()) {
2471   case X86::CMPSDrr:
2472   case X86::CMPSSrr:
2473   case X86::CMPPDrri:
2474   case X86::CMPPSrri:
2475   case X86::VCMPSDrr:
2476   case X86::VCMPSSrr:
2477   case X86::VCMPPDrri:
2478   case X86::VCMPPSrri:
2479   case X86::VCMPPDYrri:
2480   case X86::VCMPPSYrri:
2481   case X86::VCMPSDZrr:
2482   case X86::VCMPSSZrr:
2483   case X86::VCMPPDZrri:
2484   case X86::VCMPPSZrri:
2485   case X86::VCMPPDZ128rri:
2486   case X86::VCMPPSZ128rri:
2487   case X86::VCMPPDZ256rri:
2488   case X86::VCMPPSZ256rri:
2489   case X86::VCMPPDZrrik:
2490   case X86::VCMPPSZrrik:
2491   case X86::VCMPPDZ128rrik:
2492   case X86::VCMPPSZ128rrik:
2493   case X86::VCMPPDZ256rrik:
2494   case X86::VCMPPSZ256rrik: {
2495     unsigned OpOffset = X86II::isKMasked(Desc.TSFlags) ? 1 : 0;
2496 
2497     // Float comparison can be safely commuted for
2498     // Ordered/Unordered/Equal/NotEqual tests
2499     unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2500     switch (Imm) {
2501     default:
2502       // EVEX versions can be commuted.
2503       if ((Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX)
2504         break;
2505       return false;
2506     case 0x00: // EQUAL
2507     case 0x03: // UNORDERED
2508     case 0x04: // NOT EQUAL
2509     case 0x07: // ORDERED
2510       break;
2511     }
2512 
2513     // The indices of the commutable operands are 1 and 2 (or 2 and 3
2514     // when masked).
2515     // Assign them to the returned operand indices here.
2516     return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1 + OpOffset,
2517                                 2 + OpOffset);
2518   }
2519   case X86::MOVSSrr:
2520     // X86::MOVSDrr is always commutable. MOVSS is only commutable if we can
2521     // form sse4.1 blend. We assume VMOVSSrr/VMOVSDrr is always commutable since
2522     // AVX implies sse4.1.
2523     if (Subtarget.hasSSE41())
2524       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2525     return false;
2526   case X86::SHUFPDrri:
2527     // We can commute this to MOVSD.
2528     if (MI.getOperand(3).getImm() == 0x02)
2529       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2530     return false;
2531   case X86::MOVHLPSrr:
2532   case X86::UNPCKHPDrr:
2533   case X86::VMOVHLPSrr:
2534   case X86::VUNPCKHPDrr:
2535   case X86::VMOVHLPSZrr:
2536   case X86::VUNPCKHPDZ128rr:
2537     if (Subtarget.hasSSE2())
2538       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2539     return false;
2540   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
2541   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
2542   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
2543   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
2544   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
2545   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
2546   case X86::VPTERNLOGDZrrik:
2547   case X86::VPTERNLOGDZ128rrik:
2548   case X86::VPTERNLOGDZ256rrik:
2549   case X86::VPTERNLOGQZrrik:
2550   case X86::VPTERNLOGQZ128rrik:
2551   case X86::VPTERNLOGQZ256rrik:
2552   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
2553   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
2554   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
2555   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
2556   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
2557   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
2558   case X86::VPTERNLOGDZ128rmbi:
2559   case X86::VPTERNLOGDZ256rmbi:
2560   case X86::VPTERNLOGDZrmbi:
2561   case X86::VPTERNLOGQZ128rmbi:
2562   case X86::VPTERNLOGQZ256rmbi:
2563   case X86::VPTERNLOGQZrmbi:
2564   case X86::VPTERNLOGDZ128rmbikz:
2565   case X86::VPTERNLOGDZ256rmbikz:
2566   case X86::VPTERNLOGDZrmbikz:
2567   case X86::VPTERNLOGQZ128rmbikz:
2568   case X86::VPTERNLOGQZ256rmbikz:
2569   case X86::VPTERNLOGQZrmbikz:
2570     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2571   case X86::VPDPWSSDYrr:
2572   case X86::VPDPWSSDrr:
2573   case X86::VPDPWSSDSYrr:
2574   case X86::VPDPWSSDSrr:
2575   case X86::VPDPWSSDZ128r:
2576   case X86::VPDPWSSDZ128rk:
2577   case X86::VPDPWSSDZ128rkz:
2578   case X86::VPDPWSSDZ256r:
2579   case X86::VPDPWSSDZ256rk:
2580   case X86::VPDPWSSDZ256rkz:
2581   case X86::VPDPWSSDZr:
2582   case X86::VPDPWSSDZrk:
2583   case X86::VPDPWSSDZrkz:
2584   case X86::VPDPWSSDSZ128r:
2585   case X86::VPDPWSSDSZ128rk:
2586   case X86::VPDPWSSDSZ128rkz:
2587   case X86::VPDPWSSDSZ256r:
2588   case X86::VPDPWSSDSZ256rk:
2589   case X86::VPDPWSSDSZ256rkz:
2590   case X86::VPDPWSSDSZr:
2591   case X86::VPDPWSSDSZrk:
2592   case X86::VPDPWSSDSZrkz:
2593   case X86::VPMADD52HUQZ128r:
2594   case X86::VPMADD52HUQZ128rk:
2595   case X86::VPMADD52HUQZ128rkz:
2596   case X86::VPMADD52HUQZ256r:
2597   case X86::VPMADD52HUQZ256rk:
2598   case X86::VPMADD52HUQZ256rkz:
2599   case X86::VPMADD52HUQZr:
2600   case X86::VPMADD52HUQZrk:
2601   case X86::VPMADD52HUQZrkz:
2602   case X86::VPMADD52LUQZ128r:
2603   case X86::VPMADD52LUQZ128rk:
2604   case X86::VPMADD52LUQZ128rkz:
2605   case X86::VPMADD52LUQZ256r:
2606   case X86::VPMADD52LUQZ256rk:
2607   case X86::VPMADD52LUQZ256rkz:
2608   case X86::VPMADD52LUQZr:
2609   case X86::VPMADD52LUQZrk:
2610   case X86::VPMADD52LUQZrkz: {
2611     unsigned CommutableOpIdx1 = 2;
2612     unsigned CommutableOpIdx2 = 3;
2613     if (X86II::isKMasked(Desc.TSFlags)) {
2614       // Skip the mask register.
2615       ++CommutableOpIdx1;
2616       ++CommutableOpIdx2;
2617     }
2618     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2619                               CommutableOpIdx1, CommutableOpIdx2))
2620       return false;
2621     if (!MI.getOperand(SrcOpIdx1).isReg() ||
2622         !MI.getOperand(SrcOpIdx2).isReg())
2623       // No idea.
2624       return false;
2625     return true;
2626   }
2627 
2628   default:
2629     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2630                                                       MI.getDesc().TSFlags);
2631     if (FMA3Group)
2632       return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2633                                            FMA3Group->isIntrinsic());
2634 
2635     // Handled masked instructions since we need to skip over the mask input
2636     // and the preserved input.
2637     if (X86II::isKMasked(Desc.TSFlags)) {
2638       // First assume that the first input is the mask operand and skip past it.
2639       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2640       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2641       // Check if the first input is tied. If there isn't one then we only
2642       // need to skip the mask operand which we did above.
2643       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2644                                              MCOI::TIED_TO) != -1)) {
2645         // If this is zero masking instruction with a tied operand, we need to
2646         // move the first index back to the first input since this must
2647         // be a 3 input instruction and we want the first two non-mask inputs.
2648         // Otherwise this is a 2 input instruction with a preserved input and
2649         // mask, so we need to move the indices to skip one more input.
2650         if (X86II::isKMergeMasked(Desc.TSFlags)) {
2651           ++CommutableOpIdx1;
2652           ++CommutableOpIdx2;
2653         } else {
2654           --CommutableOpIdx1;
2655         }
2656       }
2657 
2658       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2659                                 CommutableOpIdx1, CommutableOpIdx2))
2660         return false;
2661 
2662       if (!MI.getOperand(SrcOpIdx1).isReg() ||
2663           !MI.getOperand(SrcOpIdx2).isReg())
2664         // No idea.
2665         return false;
2666       return true;
2667     }
2668 
2669     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2670   }
2671   return false;
2672 }
2673 
2674 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
2675   switch (MI.getOpcode()) {
2676   default: return X86::COND_INVALID;
2677   case X86::JCC_1:
2678     return static_cast<X86::CondCode>(
2679         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2680   }
2681 }
2682 
2683 /// Return condition code of a SETCC opcode.
2684 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {
2685   switch (MI.getOpcode()) {
2686   default: return X86::COND_INVALID;
2687   case X86::SETCCr: case X86::SETCCm:
2688     return static_cast<X86::CondCode>(
2689         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2690   }
2691 }
2692 
2693 /// Return condition code of a CMov opcode.
2694 X86::CondCode X86::getCondFromCMov(const MachineInstr &MI) {
2695   switch (MI.getOpcode()) {
2696   default: return X86::COND_INVALID;
2697   case X86::CMOV16rr: case X86::CMOV32rr: case X86::CMOV64rr:
2698   case X86::CMOV16rm: case X86::CMOV32rm: case X86::CMOV64rm:
2699     return static_cast<X86::CondCode>(
2700         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2701   }
2702 }
2703 
2704 /// Return the inverse of the specified condition,
2705 /// e.g. turning COND_E to COND_NE.
2706 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2707   switch (CC) {
2708   default: llvm_unreachable("Illegal condition code!");
2709   case X86::COND_E:  return X86::COND_NE;
2710   case X86::COND_NE: return X86::COND_E;
2711   case X86::COND_L:  return X86::COND_GE;
2712   case X86::COND_LE: return X86::COND_G;
2713   case X86::COND_G:  return X86::COND_LE;
2714   case X86::COND_GE: return X86::COND_L;
2715   case X86::COND_B:  return X86::COND_AE;
2716   case X86::COND_BE: return X86::COND_A;
2717   case X86::COND_A:  return X86::COND_BE;
2718   case X86::COND_AE: return X86::COND_B;
2719   case X86::COND_S:  return X86::COND_NS;
2720   case X86::COND_NS: return X86::COND_S;
2721   case X86::COND_P:  return X86::COND_NP;
2722   case X86::COND_NP: return X86::COND_P;
2723   case X86::COND_O:  return X86::COND_NO;
2724   case X86::COND_NO: return X86::COND_O;
2725   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
2726   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2727   }
2728 }
2729 
2730 /// Assuming the flags are set by MI(a,b), return the condition code if we
2731 /// modify the instructions such that flags are set by MI(b,a).
2732 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2733   switch (CC) {
2734   default: return X86::COND_INVALID;
2735   case X86::COND_E:  return X86::COND_E;
2736   case X86::COND_NE: return X86::COND_NE;
2737   case X86::COND_L:  return X86::COND_G;
2738   case X86::COND_LE: return X86::COND_GE;
2739   case X86::COND_G:  return X86::COND_L;
2740   case X86::COND_GE: return X86::COND_LE;
2741   case X86::COND_B:  return X86::COND_A;
2742   case X86::COND_BE: return X86::COND_AE;
2743   case X86::COND_A:  return X86::COND_B;
2744   case X86::COND_AE: return X86::COND_BE;
2745   }
2746 }
2747 
2748 std::pair<X86::CondCode, bool>
2749 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2750   X86::CondCode CC = X86::COND_INVALID;
2751   bool NeedSwap = false;
2752   switch (Predicate) {
2753   default: break;
2754   // Floating-point Predicates
2755   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
2756   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
2757   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
2758   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
2759   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
2760   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
2761   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
2762   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
2763   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
2764   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
2765   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
2766   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
2767   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
2768   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2769 
2770   // Integer Predicates
2771   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
2772   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
2773   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
2774   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
2775   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
2776   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
2777   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
2778   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
2779   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
2780   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
2781   }
2782 
2783   return std::make_pair(CC, NeedSwap);
2784 }
2785 
2786 /// Return a setcc opcode based on whether it has memory operand.
2787 unsigned X86::getSETOpc(bool HasMemoryOperand) {
2788   return HasMemoryOperand ? X86::SETCCr : X86::SETCCm;
2789 }
2790 
2791 /// Return a cmov opcode for the given register size in bytes, and operand type.
2792 unsigned X86::getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand) {
2793   switch(RegBytes) {
2794   default: llvm_unreachable("Illegal register size!");
2795   case 2: return HasMemoryOperand ? X86::CMOV16rm : X86::CMOV16rr;
2796   case 4: return HasMemoryOperand ? X86::CMOV32rm : X86::CMOV32rr;
2797   case 8: return HasMemoryOperand ? X86::CMOV64rm : X86::CMOV64rr;
2798   }
2799 }
2800 
2801 /// Get the VPCMP immediate for the given condition.
2802 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2803   switch (CC) {
2804   default: llvm_unreachable("Unexpected SETCC condition");
2805   case ISD::SETNE:  return 4;
2806   case ISD::SETEQ:  return 0;
2807   case ISD::SETULT:
2808   case ISD::SETLT: return 1;
2809   case ISD::SETUGT:
2810   case ISD::SETGT: return 6;
2811   case ISD::SETUGE:
2812   case ISD::SETGE: return 5;
2813   case ISD::SETULE:
2814   case ISD::SETLE: return 2;
2815   }
2816 }
2817 
2818 /// Get the VPCMP immediate if the operands are swapped.
2819 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2820   switch (Imm) {
2821   default: llvm_unreachable("Unreachable!");
2822   case 0x01: Imm = 0x06; break; // LT  -> NLE
2823   case 0x02: Imm = 0x05; break; // LE  -> NLT
2824   case 0x05: Imm = 0x02; break; // NLT -> LE
2825   case 0x06: Imm = 0x01; break; // NLE -> LT
2826   case 0x00: // EQ
2827   case 0x03: // FALSE
2828   case 0x04: // NE
2829   case 0x07: // TRUE
2830     break;
2831   }
2832 
2833   return Imm;
2834 }
2835 
2836 /// Get the VPCOM immediate if the operands are swapped.
2837 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2838   switch (Imm) {
2839   default: llvm_unreachable("Unreachable!");
2840   case 0x00: Imm = 0x02; break; // LT -> GT
2841   case 0x01: Imm = 0x03; break; // LE -> GE
2842   case 0x02: Imm = 0x00; break; // GT -> LT
2843   case 0x03: Imm = 0x01; break; // GE -> LE
2844   case 0x04: // EQ
2845   case 0x05: // NE
2846   case 0x06: // FALSE
2847   case 0x07: // TRUE
2848     break;
2849   }
2850 
2851   return Imm;
2852 }
2853 
2854 /// Get the VCMP immediate if the operands are swapped.
2855 unsigned X86::getSwappedVCMPImm(unsigned Imm) {
2856   // Only need the lower 2 bits to distinquish.
2857   switch (Imm & 0x3) {
2858   default: llvm_unreachable("Unreachable!");
2859   case 0x00: case 0x03:
2860     // EQ/NE/TRUE/FALSE/ORD/UNORD don't change immediate when commuted.
2861     break;
2862   case 0x01: case 0x02:
2863     // Need to toggle bits 3:0. Bit 4 stays the same.
2864     Imm ^= 0xf;
2865     break;
2866   }
2867 
2868   return Imm;
2869 }
2870 
2871 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2872   switch (MI.getOpcode()) {
2873   case X86::TCRETURNdi:
2874   case X86::TCRETURNri:
2875   case X86::TCRETURNmi:
2876   case X86::TCRETURNdi64:
2877   case X86::TCRETURNri64:
2878   case X86::TCRETURNmi64:
2879     return true;
2880   default:
2881     return false;
2882   }
2883 }
2884 
2885 bool X86InstrInfo::canMakeTailCallConditional(
2886     SmallVectorImpl<MachineOperand> &BranchCond,
2887     const MachineInstr &TailCall) const {
2888   if (TailCall.getOpcode() != X86::TCRETURNdi &&
2889       TailCall.getOpcode() != X86::TCRETURNdi64) {
2890     // Only direct calls can be done with a conditional branch.
2891     return false;
2892   }
2893 
2894   const MachineFunction *MF = TailCall.getParent()->getParent();
2895   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2896     // Conditional tail calls confuse the Win64 unwinder.
2897     return false;
2898   }
2899 
2900   assert(BranchCond.size() == 1);
2901   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2902     // Can't make a conditional tail call with this condition.
2903     return false;
2904   }
2905 
2906   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2907   if (X86FI->getTCReturnAddrDelta() != 0 ||
2908       TailCall.getOperand(1).getImm() != 0) {
2909     // A conditional tail call cannot do any stack adjustment.
2910     return false;
2911   }
2912 
2913   return true;
2914 }
2915 
2916 void X86InstrInfo::replaceBranchWithTailCall(
2917     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2918     const MachineInstr &TailCall) const {
2919   assert(canMakeTailCallConditional(BranchCond, TailCall));
2920 
2921   MachineBasicBlock::iterator I = MBB.end();
2922   while (I != MBB.begin()) {
2923     --I;
2924     if (I->isDebugInstr())
2925       continue;
2926     if (!I->isBranch())
2927       assert(0 && "Can't find the branch to replace!");
2928 
2929     X86::CondCode CC = X86::getCondFromBranch(*I);
2930     assert(BranchCond.size() == 1);
2931     if (CC != BranchCond[0].getImm())
2932       continue;
2933 
2934     break;
2935   }
2936 
2937   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2938                                                          : X86::TCRETURNdi64cc;
2939 
2940   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2941   MIB->addOperand(TailCall.getOperand(0)); // Destination.
2942   MIB.addImm(0); // Stack offset (not used).
2943   MIB->addOperand(BranchCond[0]); // Condition.
2944   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2945 
2946   // Add implicit uses and defs of all live regs potentially clobbered by the
2947   // call. This way they still appear live across the call.
2948   LivePhysRegs LiveRegs(getRegisterInfo());
2949   LiveRegs.addLiveOuts(MBB);
2950   SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2951   LiveRegs.stepForward(*MIB, Clobbers);
2952   for (const auto &C : Clobbers) {
2953     MIB.addReg(C.first, RegState::Implicit);
2954     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2955   }
2956 
2957   I->eraseFromParent();
2958 }
2959 
2960 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2961 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2962 // fallthrough MBB cannot be identified.
2963 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2964                                             MachineBasicBlock *TBB) {
2965   // Look for non-EHPad successors other than TBB. If we find exactly one, it
2966   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2967   // and fallthrough MBB. If we find more than one, we cannot identify the
2968   // fallthrough MBB and should return nullptr.
2969   MachineBasicBlock *FallthroughBB = nullptr;
2970   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2971     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2972       continue;
2973     // Return a nullptr if we found more than one fallthrough successor.
2974     if (FallthroughBB && FallthroughBB != TBB)
2975       return nullptr;
2976     FallthroughBB = *SI;
2977   }
2978   return FallthroughBB;
2979 }
2980 
2981 bool X86InstrInfo::AnalyzeBranchImpl(
2982     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2983     SmallVectorImpl<MachineOperand> &Cond,
2984     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2985 
2986   // Start from the bottom of the block and work up, examining the
2987   // terminator instructions.
2988   MachineBasicBlock::iterator I = MBB.end();
2989   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2990   while (I != MBB.begin()) {
2991     --I;
2992     if (I->isDebugInstr())
2993       continue;
2994 
2995     // Working from the bottom, when we see a non-terminator instruction, we're
2996     // done.
2997     if (!isUnpredicatedTerminator(*I))
2998       break;
2999 
3000     // A terminator that isn't a branch can't easily be handled by this
3001     // analysis.
3002     if (!I->isBranch())
3003       return true;
3004 
3005     // Handle unconditional branches.
3006     if (I->getOpcode() == X86::JMP_1) {
3007       UnCondBrIter = I;
3008 
3009       if (!AllowModify) {
3010         TBB = I->getOperand(0).getMBB();
3011         continue;
3012       }
3013 
3014       // If the block has any instructions after a JMP, delete them.
3015       while (std::next(I) != MBB.end())
3016         std::next(I)->eraseFromParent();
3017 
3018       Cond.clear();
3019       FBB = nullptr;
3020 
3021       // Delete the JMP if it's equivalent to a fall-through.
3022       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3023         TBB = nullptr;
3024         I->eraseFromParent();
3025         I = MBB.end();
3026         UnCondBrIter = MBB.end();
3027         continue;
3028       }
3029 
3030       // TBB is used to indicate the unconditional destination.
3031       TBB = I->getOperand(0).getMBB();
3032       continue;
3033     }
3034 
3035     // Handle conditional branches.
3036     X86::CondCode BranchCode = X86::getCondFromBranch(*I);
3037     if (BranchCode == X86::COND_INVALID)
3038       return true;  // Can't handle indirect branch.
3039 
3040     // In practice we should never have an undef eflags operand, if we do
3041     // abort here as we are not prepared to preserve the flag.
3042     if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
3043       return true;
3044 
3045     // Working from the bottom, handle the first conditional branch.
3046     if (Cond.empty()) {
3047       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3048       if (AllowModify && UnCondBrIter != MBB.end() &&
3049           MBB.isLayoutSuccessor(TargetBB)) {
3050         // If we can modify the code and it ends in something like:
3051         //
3052         //     jCC L1
3053         //     jmp L2
3054         //   L1:
3055         //     ...
3056         //   L2:
3057         //
3058         // Then we can change this to:
3059         //
3060         //     jnCC L2
3061         //   L1:
3062         //     ...
3063         //   L2:
3064         //
3065         // Which is a bit more efficient.
3066         // We conditionally jump to the fall-through block.
3067         BranchCode = GetOppositeBranchCondition(BranchCode);
3068         MachineBasicBlock::iterator OldInst = I;
3069 
3070         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
3071           .addMBB(UnCondBrIter->getOperand(0).getMBB())
3072           .addImm(BranchCode);
3073         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3074           .addMBB(TargetBB);
3075 
3076         OldInst->eraseFromParent();
3077         UnCondBrIter->eraseFromParent();
3078 
3079         // Restart the analysis.
3080         UnCondBrIter = MBB.end();
3081         I = MBB.end();
3082         continue;
3083       }
3084 
3085       FBB = TBB;
3086       TBB = I->getOperand(0).getMBB();
3087       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3088       CondBranches.push_back(&*I);
3089       continue;
3090     }
3091 
3092     // Handle subsequent conditional branches. Only handle the case where all
3093     // conditional branches branch to the same destination and their condition
3094     // opcodes fit one of the special multi-branch idioms.
3095     assert(Cond.size() == 1);
3096     assert(TBB);
3097 
3098     // If the conditions are the same, we can leave them alone.
3099     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3100     auto NewTBB = I->getOperand(0).getMBB();
3101     if (OldBranchCode == BranchCode && TBB == NewTBB)
3102       continue;
3103 
3104     // If they differ, see if they fit one of the known patterns. Theoretically,
3105     // we could handle more patterns here, but we shouldn't expect to see them
3106     // if instruction selection has done a reasonable job.
3107     if (TBB == NewTBB &&
3108                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
3109                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
3110       BranchCode = X86::COND_NE_OR_P;
3111     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
3112                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
3113       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
3114         return true;
3115 
3116       // X86::COND_E_AND_NP usually has two different branch destinations.
3117       //
3118       // JP B1
3119       // JE B2
3120       // JMP B1
3121       // B1:
3122       // B2:
3123       //
3124       // Here this condition branches to B2 only if NP && E. It has another
3125       // equivalent form:
3126       //
3127       // JNE B1
3128       // JNP B2
3129       // JMP B1
3130       // B1:
3131       // B2:
3132       //
3133       // Similarly it branches to B2 only if E && NP. That is why this condition
3134       // is named with COND_E_AND_NP.
3135       BranchCode = X86::COND_E_AND_NP;
3136     } else
3137       return true;
3138 
3139     // Update the MachineOperand.
3140     Cond[0].setImm(BranchCode);
3141     CondBranches.push_back(&*I);
3142   }
3143 
3144   return false;
3145 }
3146 
3147 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
3148                                  MachineBasicBlock *&TBB,
3149                                  MachineBasicBlock *&FBB,
3150                                  SmallVectorImpl<MachineOperand> &Cond,
3151                                  bool AllowModify) const {
3152   SmallVector<MachineInstr *, 4> CondBranches;
3153   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3154 }
3155 
3156 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
3157                                           MachineBranchPredicate &MBP,
3158                                           bool AllowModify) const {
3159   using namespace std::placeholders;
3160 
3161   SmallVector<MachineOperand, 4> Cond;
3162   SmallVector<MachineInstr *, 4> CondBranches;
3163   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3164                         AllowModify))
3165     return true;
3166 
3167   if (Cond.size() != 1)
3168     return true;
3169 
3170   assert(MBP.TrueDest && "expected!");
3171 
3172   if (!MBP.FalseDest)
3173     MBP.FalseDest = MBB.getNextNode();
3174 
3175   const TargetRegisterInfo *TRI = &getRegisterInfo();
3176 
3177   MachineInstr *ConditionDef = nullptr;
3178   bool SingleUseCondition = true;
3179 
3180   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
3181     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
3182       ConditionDef = &*I;
3183       break;
3184     }
3185 
3186     if (I->readsRegister(X86::EFLAGS, TRI))
3187       SingleUseCondition = false;
3188   }
3189 
3190   if (!ConditionDef)
3191     return true;
3192 
3193   if (SingleUseCondition) {
3194     for (auto *Succ : MBB.successors())
3195       if (Succ->isLiveIn(X86::EFLAGS))
3196         SingleUseCondition = false;
3197   }
3198 
3199   MBP.ConditionDef = ConditionDef;
3200   MBP.SingleUseCondition = SingleUseCondition;
3201 
3202   // Currently we only recognize the simple pattern:
3203   //
3204   //   test %reg, %reg
3205   //   je %label
3206   //
3207   const unsigned TestOpcode =
3208       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3209 
3210   if (ConditionDef->getOpcode() == TestOpcode &&
3211       ConditionDef->getNumOperands() == 3 &&
3212       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3213       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3214     MBP.LHS = ConditionDef->getOperand(0);
3215     MBP.RHS = MachineOperand::CreateImm(0);
3216     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3217                         ? MachineBranchPredicate::PRED_NE
3218                         : MachineBranchPredicate::PRED_EQ;
3219     return false;
3220   }
3221 
3222   return true;
3223 }
3224 
3225 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
3226                                     int *BytesRemoved) const {
3227   assert(!BytesRemoved && "code size not handled");
3228 
3229   MachineBasicBlock::iterator I = MBB.end();
3230   unsigned Count = 0;
3231 
3232   while (I != MBB.begin()) {
3233     --I;
3234     if (I->isDebugInstr())
3235       continue;
3236     if (I->getOpcode() != X86::JMP_1 &&
3237         X86::getCondFromBranch(*I) == X86::COND_INVALID)
3238       break;
3239     // Remove the branch.
3240     I->eraseFromParent();
3241     I = MBB.end();
3242     ++Count;
3243   }
3244 
3245   return Count;
3246 }
3247 
3248 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
3249                                     MachineBasicBlock *TBB,
3250                                     MachineBasicBlock *FBB,
3251                                     ArrayRef<MachineOperand> Cond,
3252                                     const DebugLoc &DL,
3253                                     int *BytesAdded) const {
3254   // Shouldn't be a fall through.
3255   assert(TBB && "insertBranch must not be told to insert a fallthrough");
3256   assert((Cond.size() == 1 || Cond.size() == 0) &&
3257          "X86 branch conditions have one component!");
3258   assert(!BytesAdded && "code size not handled");
3259 
3260   if (Cond.empty()) {
3261     // Unconditional branch?
3262     assert(!FBB && "Unconditional branch with multiple successors!");
3263     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3264     return 1;
3265   }
3266 
3267   // If FBB is null, it is implied to be a fall-through block.
3268   bool FallThru = FBB == nullptr;
3269 
3270   // Conditional branch.
3271   unsigned Count = 0;
3272   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3273   switch (CC) {
3274   case X86::COND_NE_OR_P:
3275     // Synthesize NE_OR_P with two branches.
3276     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
3277     ++Count;
3278     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
3279     ++Count;
3280     break;
3281   case X86::COND_E_AND_NP:
3282     // Use the next block of MBB as FBB if it is null.
3283     if (FBB == nullptr) {
3284       FBB = getFallThroughMBB(&MBB, TBB);
3285       assert(FBB && "MBB cannot be the last block in function when the false "
3286                     "body is a fall-through.");
3287     }
3288     // Synthesize COND_E_AND_NP with two branches.
3289     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
3290     ++Count;
3291     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
3292     ++Count;
3293     break;
3294   default: {
3295     BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
3296     ++Count;
3297   }
3298   }
3299   if (!FallThru) {
3300     // Two-way Conditional branch. Insert the second branch.
3301     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3302     ++Count;
3303   }
3304   return Count;
3305 }
3306 
3307 bool X86InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
3308                                    ArrayRef<MachineOperand> Cond,
3309                                    Register DstReg, Register TrueReg,
3310                                    Register FalseReg, int &CondCycles,
3311                                    int &TrueCycles, int &FalseCycles) const {
3312   // Not all subtargets have cmov instructions.
3313   if (!Subtarget.hasCMov())
3314     return false;
3315   if (Cond.size() != 1)
3316     return false;
3317   // We cannot do the composite conditions, at least not in SSA form.
3318   if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
3319     return false;
3320 
3321   // Check register classes.
3322   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3323   const TargetRegisterClass *RC =
3324     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3325   if (!RC)
3326     return false;
3327 
3328   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3329   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3330       X86::GR32RegClass.hasSubClassEq(RC) ||
3331       X86::GR64RegClass.hasSubClassEq(RC)) {
3332     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3333     // Bridge. Probably Ivy Bridge as well.
3334     CondCycles = 2;
3335     TrueCycles = 2;
3336     FalseCycles = 2;
3337     return true;
3338   }
3339 
3340   // Can't do vectors.
3341   return false;
3342 }
3343 
3344 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3345                                 MachineBasicBlock::iterator I,
3346                                 const DebugLoc &DL, Register DstReg,
3347                                 ArrayRef<MachineOperand> Cond, Register TrueReg,
3348                                 Register FalseReg) const {
3349   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3350   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3351   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
3352   assert(Cond.size() == 1 && "Invalid Cond array");
3353   unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(RC) / 8,
3354                                     false /*HasMemoryOperand*/);
3355   BuildMI(MBB, I, DL, get(Opc), DstReg)
3356       .addReg(FalseReg)
3357       .addReg(TrueReg)
3358       .addImm(Cond[0].getImm());
3359 }
3360 
3361 /// Test if the given register is a physical h register.
3362 static bool isHReg(unsigned Reg) {
3363   return X86::GR8_ABCD_HRegClass.contains(Reg);
3364 }
3365 
3366 // Try and copy between VR128/VR64 and GR64 registers.
3367 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3368                                         const X86Subtarget &Subtarget) {
3369   bool HasAVX = Subtarget.hasAVX();
3370   bool HasAVX512 = Subtarget.hasAVX512();
3371 
3372   // SrcReg(MaskReg) -> DestReg(GR64)
3373   // SrcReg(MaskReg) -> DestReg(GR32)
3374 
3375   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3376   if (X86::VK16RegClass.contains(SrcReg)) {
3377     if (X86::GR64RegClass.contains(DestReg)) {
3378       assert(Subtarget.hasBWI());
3379       return X86::KMOVQrk;
3380     }
3381     if (X86::GR32RegClass.contains(DestReg))
3382       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
3383   }
3384 
3385   // SrcReg(GR64) -> DestReg(MaskReg)
3386   // SrcReg(GR32) -> DestReg(MaskReg)
3387 
3388   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3389   if (X86::VK16RegClass.contains(DestReg)) {
3390     if (X86::GR64RegClass.contains(SrcReg)) {
3391       assert(Subtarget.hasBWI());
3392       return X86::KMOVQkr;
3393     }
3394     if (X86::GR32RegClass.contains(SrcReg))
3395       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
3396   }
3397 
3398 
3399   // SrcReg(VR128) -> DestReg(GR64)
3400   // SrcReg(VR64)  -> DestReg(GR64)
3401   // SrcReg(GR64)  -> DestReg(VR128)
3402   // SrcReg(GR64)  -> DestReg(VR64)
3403 
3404   if (X86::GR64RegClass.contains(DestReg)) {
3405     if (X86::VR128XRegClass.contains(SrcReg))
3406       // Copy from a VR128 register to a GR64 register.
3407       return HasAVX512 ? X86::VMOVPQIto64Zrr :
3408              HasAVX    ? X86::VMOVPQIto64rr  :
3409                          X86::MOVPQIto64rr;
3410     if (X86::VR64RegClass.contains(SrcReg))
3411       // Copy from a VR64 register to a GR64 register.
3412       return X86::MMX_MOVD64from64rr;
3413   } else if (X86::GR64RegClass.contains(SrcReg)) {
3414     // Copy from a GR64 register to a VR128 register.
3415     if (X86::VR128XRegClass.contains(DestReg))
3416       return HasAVX512 ? X86::VMOV64toPQIZrr :
3417              HasAVX    ? X86::VMOV64toPQIrr  :
3418                          X86::MOV64toPQIrr;
3419     // Copy from a GR64 register to a VR64 register.
3420     if (X86::VR64RegClass.contains(DestReg))
3421       return X86::MMX_MOVD64to64rr;
3422   }
3423 
3424   // SrcReg(VR128) -> DestReg(GR32)
3425   // SrcReg(GR32)  -> DestReg(VR128)
3426 
3427   if (X86::GR32RegClass.contains(DestReg) &&
3428       X86::VR128XRegClass.contains(SrcReg))
3429     // Copy from a VR128 register to a GR32 register.
3430     return HasAVX512 ? X86::VMOVPDI2DIZrr :
3431            HasAVX    ? X86::VMOVPDI2DIrr  :
3432                        X86::MOVPDI2DIrr;
3433 
3434   if (X86::VR128XRegClass.contains(DestReg) &&
3435       X86::GR32RegClass.contains(SrcReg))
3436     // Copy from a VR128 register to a VR128 register.
3437     return HasAVX512 ? X86::VMOVDI2PDIZrr :
3438            HasAVX    ? X86::VMOVDI2PDIrr  :
3439                        X86::MOVDI2PDIrr;
3440   return 0;
3441 }
3442 
3443 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3444                                MachineBasicBlock::iterator MI,
3445                                const DebugLoc &DL, MCRegister DestReg,
3446                                MCRegister SrcReg, bool KillSrc) const {
3447   // First deal with the normal symmetric copies.
3448   bool HasAVX = Subtarget.hasAVX();
3449   bool HasVLX = Subtarget.hasVLX();
3450   unsigned Opc = 0;
3451   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3452     Opc = X86::MOV64rr;
3453   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3454     Opc = X86::MOV32rr;
3455   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3456     Opc = X86::MOV16rr;
3457   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3458     // Copying to or from a physical H register on x86-64 requires a NOREX
3459     // move.  Otherwise use a normal move.
3460     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3461         Subtarget.is64Bit()) {
3462       Opc = X86::MOV8rr_NOREX;
3463       // Both operands must be encodable without an REX prefix.
3464       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3465              "8-bit H register can not be copied outside GR8_NOREX");
3466     } else
3467       Opc = X86::MOV8rr;
3468   }
3469   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3470     Opc = X86::MMX_MOVQ64rr;
3471   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
3472     if (HasVLX)
3473       Opc = X86::VMOVAPSZ128rr;
3474     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3475       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3476     else {
3477       // If this an extended register and we don't have VLX we need to use a
3478       // 512-bit move.
3479       Opc = X86::VMOVAPSZrr;
3480       const TargetRegisterInfo *TRI = &getRegisterInfo();
3481       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3482                                          &X86::VR512RegClass);
3483       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3484                                         &X86::VR512RegClass);
3485     }
3486   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3487     if (HasVLX)
3488       Opc = X86::VMOVAPSZ256rr;
3489     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3490       Opc = X86::VMOVAPSYrr;
3491     else {
3492       // If this an extended register and we don't have VLX we need to use a
3493       // 512-bit move.
3494       Opc = X86::VMOVAPSZrr;
3495       const TargetRegisterInfo *TRI = &getRegisterInfo();
3496       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3497                                          &X86::VR512RegClass);
3498       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3499                                         &X86::VR512RegClass);
3500     }
3501   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3502     Opc = X86::VMOVAPSZrr;
3503   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3504   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3505     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3506   if (!Opc)
3507     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3508 
3509   if (Opc) {
3510     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3511       .addReg(SrcReg, getKillRegState(KillSrc));
3512     return;
3513   }
3514 
3515   if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3516     // FIXME: We use a fatal error here because historically LLVM has tried
3517     // lower some of these physreg copies and we want to ensure we get
3518     // reasonable bug reports if someone encounters a case no other testing
3519     // found. This path should be removed after the LLVM 7 release.
3520     report_fatal_error("Unable to copy EFLAGS physical register!");
3521   }
3522 
3523   LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3524                     << RI.getName(DestReg) << '\n');
3525   report_fatal_error("Cannot emit physreg copy instruction");
3526 }
3527 
3528 Optional<DestSourcePair>
3529 X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
3530   if (MI.isMoveReg())
3531     return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
3532   return None;
3533 }
3534 
3535 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3536                                       const TargetRegisterClass *RC,
3537                                       bool isStackAligned,
3538                                       const X86Subtarget &STI,
3539                                       bool load) {
3540   bool HasAVX = STI.hasAVX();
3541   bool HasAVX512 = STI.hasAVX512();
3542   bool HasVLX = STI.hasVLX();
3543 
3544   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3545   default:
3546     llvm_unreachable("Unknown spill size");
3547   case 1:
3548     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3549     if (STI.is64Bit())
3550       // Copying to or from a physical H register on x86-64 requires a NOREX
3551       // move.  Otherwise use a normal move.
3552       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3553         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3554     return load ? X86::MOV8rm : X86::MOV8mr;
3555   case 2:
3556     if (X86::VK16RegClass.hasSubClassEq(RC))
3557       return load ? X86::KMOVWkm : X86::KMOVWmk;
3558     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3559     return load ? X86::MOV16rm : X86::MOV16mr;
3560   case 4:
3561     if (X86::GR32RegClass.hasSubClassEq(RC))
3562       return load ? X86::MOV32rm : X86::MOV32mr;
3563     if (X86::FR32XRegClass.hasSubClassEq(RC))
3564       return load ?
3565         (HasAVX512 ? X86::VMOVSSZrm_alt :
3566          HasAVX    ? X86::VMOVSSrm_alt :
3567                      X86::MOVSSrm_alt) :
3568         (HasAVX512 ? X86::VMOVSSZmr :
3569          HasAVX    ? X86::VMOVSSmr :
3570                      X86::MOVSSmr);
3571     if (X86::RFP32RegClass.hasSubClassEq(RC))
3572       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3573     if (X86::VK32RegClass.hasSubClassEq(RC)) {
3574       assert(STI.hasBWI() && "KMOVD requires BWI");
3575       return load ? X86::KMOVDkm : X86::KMOVDmk;
3576     }
3577     // All of these mask pair classes have the same spill size, the same kind
3578     // of kmov instructions can be used with all of them.
3579     if (X86::VK1PAIRRegClass.hasSubClassEq(RC) ||
3580         X86::VK2PAIRRegClass.hasSubClassEq(RC) ||
3581         X86::VK4PAIRRegClass.hasSubClassEq(RC) ||
3582         X86::VK8PAIRRegClass.hasSubClassEq(RC) ||
3583         X86::VK16PAIRRegClass.hasSubClassEq(RC))
3584       return load ? X86::MASKPAIR16LOAD : X86::MASKPAIR16STORE;
3585     llvm_unreachable("Unknown 4-byte regclass");
3586   case 8:
3587     if (X86::GR64RegClass.hasSubClassEq(RC))
3588       return load ? X86::MOV64rm : X86::MOV64mr;
3589     if (X86::FR64XRegClass.hasSubClassEq(RC))
3590       return load ?
3591         (HasAVX512 ? X86::VMOVSDZrm_alt :
3592          HasAVX    ? X86::VMOVSDrm_alt :
3593                      X86::MOVSDrm_alt) :
3594         (HasAVX512 ? X86::VMOVSDZmr :
3595          HasAVX    ? X86::VMOVSDmr :
3596                      X86::MOVSDmr);
3597     if (X86::VR64RegClass.hasSubClassEq(RC))
3598       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3599     if (X86::RFP64RegClass.hasSubClassEq(RC))
3600       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3601     if (X86::VK64RegClass.hasSubClassEq(RC)) {
3602       assert(STI.hasBWI() && "KMOVQ requires BWI");
3603       return load ? X86::KMOVQkm : X86::KMOVQmk;
3604     }
3605     llvm_unreachable("Unknown 8-byte regclass");
3606   case 10:
3607     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3608     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3609   case 16: {
3610     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3611       // If stack is realigned we can use aligned stores.
3612       if (isStackAligned)
3613         return load ?
3614           (HasVLX    ? X86::VMOVAPSZ128rm :
3615            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3616            HasAVX    ? X86::VMOVAPSrm :
3617                        X86::MOVAPSrm):
3618           (HasVLX    ? X86::VMOVAPSZ128mr :
3619            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3620            HasAVX    ? X86::VMOVAPSmr :
3621                        X86::MOVAPSmr);
3622       else
3623         return load ?
3624           (HasVLX    ? X86::VMOVUPSZ128rm :
3625            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3626            HasAVX    ? X86::VMOVUPSrm :
3627                        X86::MOVUPSrm):
3628           (HasVLX    ? X86::VMOVUPSZ128mr :
3629            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3630            HasAVX    ? X86::VMOVUPSmr :
3631                        X86::MOVUPSmr);
3632     }
3633     if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3634       if (STI.is64Bit())
3635         return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3636       else
3637         return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3638     }
3639     llvm_unreachable("Unknown 16-byte regclass");
3640   }
3641   case 32:
3642     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3643     // If stack is realigned we can use aligned stores.
3644     if (isStackAligned)
3645       return load ?
3646         (HasVLX    ? X86::VMOVAPSZ256rm :
3647          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3648                      X86::VMOVAPSYrm) :
3649         (HasVLX    ? X86::VMOVAPSZ256mr :
3650          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3651                      X86::VMOVAPSYmr);
3652     else
3653       return load ?
3654         (HasVLX    ? X86::VMOVUPSZ256rm :
3655          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3656                      X86::VMOVUPSYrm) :
3657         (HasVLX    ? X86::VMOVUPSZ256mr :
3658          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3659                      X86::VMOVUPSYmr);
3660   case 64:
3661     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3662     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3663     if (isStackAligned)
3664       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3665     else
3666       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3667   }
3668 }
3669 
3670 Optional<ExtAddrMode>
3671 X86InstrInfo::getAddrModeFromMemoryOp(const MachineInstr &MemI,
3672                                       const TargetRegisterInfo *TRI) const {
3673   const MCInstrDesc &Desc = MemI.getDesc();
3674   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3675   if (MemRefBegin < 0)
3676     return None;
3677 
3678   MemRefBegin += X86II::getOperandBias(Desc);
3679 
3680   auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg);
3681   if (!BaseOp.isReg()) // Can be an MO_FrameIndex
3682     return None;
3683 
3684   const MachineOperand &DispMO = MemI.getOperand(MemRefBegin + X86::AddrDisp);
3685   // Displacement can be symbolic
3686   if (!DispMO.isImm())
3687     return None;
3688 
3689   ExtAddrMode AM;
3690   AM.BaseReg = BaseOp.getReg();
3691   AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg();
3692   AM.Scale = MemI.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm();
3693   AM.Displacement = DispMO.getImm();
3694   return AM;
3695 }
3696 
3697 bool X86InstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
3698                                            const Register Reg,
3699                                            int64_t &ImmVal) const {
3700   if (MI.getOpcode() != X86::MOV32ri && MI.getOpcode() != X86::MOV64ri)
3701     return false;
3702   // Mov Src can be a global address.
3703   if (!MI.getOperand(1).isImm() || MI.getOperand(0).getReg() != Reg)
3704     return false;
3705   ImmVal = MI.getOperand(1).getImm();
3706   return true;
3707 }
3708 
3709 bool X86InstrInfo::preservesZeroValueInReg(
3710     const MachineInstr *MI, const Register NullValueReg,
3711     const TargetRegisterInfo *TRI) const {
3712   if (!MI->modifiesRegister(NullValueReg, TRI))
3713     return true;
3714   switch (MI->getOpcode()) {
3715   // Shift right/left of a null unto itself is still a null, i.e. rax = shl rax
3716   // X.
3717   case X86::SHR64ri:
3718   case X86::SHR32ri:
3719   case X86::SHL64ri:
3720   case X86::SHL32ri:
3721     assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() &&
3722            "expected for shift opcode!");
3723     return MI->getOperand(0).getReg() == NullValueReg &&
3724            MI->getOperand(1).getReg() == NullValueReg;
3725   // Zero extend of a sub-reg of NullValueReg into itself does not change the
3726   // null value.
3727   case X86::MOV32rr:
3728     return llvm::all_of(MI->operands(), [&](const MachineOperand &MO) {
3729       return TRI->isSubRegisterEq(NullValueReg, MO.getReg());
3730     });
3731   default:
3732     return false;
3733   }
3734   llvm_unreachable("Should be handled above!");
3735 }
3736 
3737 bool X86InstrInfo::getMemOperandsWithOffsetWidth(
3738     const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
3739     int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3740     const TargetRegisterInfo *TRI) const {
3741   const MCInstrDesc &Desc = MemOp.getDesc();
3742   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3743   if (MemRefBegin < 0)
3744     return false;
3745 
3746   MemRefBegin += X86II::getOperandBias(Desc);
3747 
3748   const MachineOperand *BaseOp =
3749       &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3750   if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3751     return false;
3752 
3753   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3754     return false;
3755 
3756   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3757       X86::NoRegister)
3758     return false;
3759 
3760   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3761 
3762   // Displacement can be symbolic
3763   if (!DispMO.isImm())
3764     return false;
3765 
3766   Offset = DispMO.getImm();
3767 
3768   if (!BaseOp->isReg())
3769     return false;
3770 
3771   OffsetIsScalable = false;
3772   // FIXME: Relying on memoperands() may not be right thing to do here. Check
3773   // with X86 maintainers, and fix it accordingly. For now, it is ok, since
3774   // there is no use of `Width` for X86 back-end at the moment.
3775   Width =
3776       !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0;
3777   BaseOps.push_back(BaseOp);
3778   return true;
3779 }
3780 
3781 static unsigned getStoreRegOpcode(unsigned SrcReg,
3782                                   const TargetRegisterClass *RC,
3783                                   bool isStackAligned,
3784                                   const X86Subtarget &STI) {
3785   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3786 }
3787 
3788 
3789 static unsigned getLoadRegOpcode(unsigned DestReg,
3790                                  const TargetRegisterClass *RC,
3791                                  bool isStackAligned,
3792                                  const X86Subtarget &STI) {
3793   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3794 }
3795 
3796 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3797                                        MachineBasicBlock::iterator MI,
3798                                        Register SrcReg, bool isKill, int FrameIdx,
3799                                        const TargetRegisterClass *RC,
3800                                        const TargetRegisterInfo *TRI) const {
3801   const MachineFunction &MF = *MBB.getParent();
3802   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3803          "Stack slot too small for store");
3804   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3805   bool isAligned =
3806       (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3807       RI.canRealignStack(MF);
3808   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3809   addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3810     .addReg(SrcReg, getKillRegState(isKill));
3811 }
3812 
3813 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3814                                         MachineBasicBlock::iterator MI,
3815                                         Register DestReg, int FrameIdx,
3816                                         const TargetRegisterClass *RC,
3817                                         const TargetRegisterInfo *TRI) const {
3818   const MachineFunction &MF = *MBB.getParent();
3819   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3820   bool isAligned =
3821       (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) ||
3822       RI.canRealignStack(MF);
3823   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3824   addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3825 }
3826 
3827 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
3828                                   Register &SrcReg2, int &CmpMask,
3829                                   int &CmpValue) const {
3830   switch (MI.getOpcode()) {
3831   default: break;
3832   case X86::CMP64ri32:
3833   case X86::CMP64ri8:
3834   case X86::CMP32ri:
3835   case X86::CMP32ri8:
3836   case X86::CMP16ri:
3837   case X86::CMP16ri8:
3838   case X86::CMP8ri:
3839     SrcReg = MI.getOperand(0).getReg();
3840     SrcReg2 = 0;
3841     if (MI.getOperand(1).isImm()) {
3842       CmpMask = ~0;
3843       CmpValue = MI.getOperand(1).getImm();
3844     } else {
3845       CmpMask = CmpValue = 0;
3846     }
3847     return true;
3848   // A SUB can be used to perform comparison.
3849   case X86::SUB64rm:
3850   case X86::SUB32rm:
3851   case X86::SUB16rm:
3852   case X86::SUB8rm:
3853     SrcReg = MI.getOperand(1).getReg();
3854     SrcReg2 = 0;
3855     CmpMask = 0;
3856     CmpValue = 0;
3857     return true;
3858   case X86::SUB64rr:
3859   case X86::SUB32rr:
3860   case X86::SUB16rr:
3861   case X86::SUB8rr:
3862     SrcReg = MI.getOperand(1).getReg();
3863     SrcReg2 = MI.getOperand(2).getReg();
3864     CmpMask = 0;
3865     CmpValue = 0;
3866     return true;
3867   case X86::SUB64ri32:
3868   case X86::SUB64ri8:
3869   case X86::SUB32ri:
3870   case X86::SUB32ri8:
3871   case X86::SUB16ri:
3872   case X86::SUB16ri8:
3873   case X86::SUB8ri:
3874     SrcReg = MI.getOperand(1).getReg();
3875     SrcReg2 = 0;
3876     if (MI.getOperand(2).isImm()) {
3877       CmpMask = ~0;
3878       CmpValue = MI.getOperand(2).getImm();
3879     } else {
3880       CmpMask = CmpValue = 0;
3881     }
3882     return true;
3883   case X86::CMP64rr:
3884   case X86::CMP32rr:
3885   case X86::CMP16rr:
3886   case X86::CMP8rr:
3887     SrcReg = MI.getOperand(0).getReg();
3888     SrcReg2 = MI.getOperand(1).getReg();
3889     CmpMask = 0;
3890     CmpValue = 0;
3891     return true;
3892   case X86::TEST8rr:
3893   case X86::TEST16rr:
3894   case X86::TEST32rr:
3895   case X86::TEST64rr:
3896     SrcReg = MI.getOperand(0).getReg();
3897     if (MI.getOperand(1).getReg() != SrcReg)
3898       return false;
3899     // Compare against zero.
3900     SrcReg2 = 0;
3901     CmpMask = ~0;
3902     CmpValue = 0;
3903     return true;
3904   }
3905   return false;
3906 }
3907 
3908 /// Check whether the first instruction, whose only
3909 /// purpose is to update flags, can be made redundant.
3910 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3911 /// This function can be extended later on.
3912 /// SrcReg, SrcRegs: register operands for FlagI.
3913 /// ImmValue: immediate for FlagI if it takes an immediate.
3914 inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3915                                         Register SrcReg, Register SrcReg2,
3916                                         int ImmMask, int ImmValue,
3917                                         const MachineInstr &OI) {
3918   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3919        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3920        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3921        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3922       ((OI.getOperand(1).getReg() == SrcReg &&
3923         OI.getOperand(2).getReg() == SrcReg2) ||
3924        (OI.getOperand(1).getReg() == SrcReg2 &&
3925         OI.getOperand(2).getReg() == SrcReg)))
3926     return true;
3927 
3928   if (ImmMask != 0 &&
3929       ((FlagI.getOpcode() == X86::CMP64ri32 &&
3930         OI.getOpcode() == X86::SUB64ri32) ||
3931        (FlagI.getOpcode() == X86::CMP64ri8 &&
3932         OI.getOpcode() == X86::SUB64ri8) ||
3933        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3934        (FlagI.getOpcode() == X86::CMP32ri8 &&
3935         OI.getOpcode() == X86::SUB32ri8) ||
3936        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3937        (FlagI.getOpcode() == X86::CMP16ri8 &&
3938         OI.getOpcode() == X86::SUB16ri8) ||
3939        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3940       OI.getOperand(1).getReg() == SrcReg &&
3941       OI.getOperand(2).getImm() == ImmValue)
3942     return true;
3943   return false;
3944 }
3945 
3946 /// Check whether the definition can be converted
3947 /// to remove a comparison against zero.
3948 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3949   NoSignFlag = false;
3950 
3951   switch (MI.getOpcode()) {
3952   default: return false;
3953 
3954   // The shift instructions only modify ZF if their shift count is non-zero.
3955   // N.B.: The processor truncates the shift count depending on the encoding.
3956   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3957   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3958      return getTruncatedShiftCount(MI, 2) != 0;
3959 
3960   // Some left shift instructions can be turned into LEA instructions but only
3961   // if their flags aren't used. Avoid transforming such instructions.
3962   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3963     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3964     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3965     return ShAmt != 0;
3966   }
3967 
3968   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3969   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3970      return getTruncatedShiftCount(MI, 3) != 0;
3971 
3972   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3973   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3974   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3975   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3976   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3977   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3978   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3979   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3980   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3981   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3982   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3983   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3984   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3985   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3986   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3987   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3988   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3989   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3990   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3991   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3992   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3993   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3994   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3995   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3996   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3997   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3998   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3999   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
4000   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
4001   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
4002   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
4003   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
4004   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
4005   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
4006   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
4007   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
4008   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
4009   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4010   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
4011   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
4012   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
4013   case X86::ANDN32rr:  case X86::ANDN32rm:
4014   case X86::ANDN64rr:  case X86::ANDN64rm:
4015   case X86::BLSI32rr:  case X86::BLSI32rm:
4016   case X86::BLSI64rr:  case X86::BLSI64rm:
4017   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4018   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4019   case X86::BLSR32rr:  case X86::BLSR32rm:
4020   case X86::BLSR64rr:  case X86::BLSR64rm:
4021   case X86::BZHI32rr:  case X86::BZHI32rm:
4022   case X86::BZHI64rr:  case X86::BZHI64rm:
4023   case X86::LZCNT16rr: case X86::LZCNT16rm:
4024   case X86::LZCNT32rr: case X86::LZCNT32rm:
4025   case X86::LZCNT64rr: case X86::LZCNT64rm:
4026   case X86::POPCNT16rr:case X86::POPCNT16rm:
4027   case X86::POPCNT32rr:case X86::POPCNT32rm:
4028   case X86::POPCNT64rr:case X86::POPCNT64rm:
4029   case X86::TZCNT16rr: case X86::TZCNT16rm:
4030   case X86::TZCNT32rr: case X86::TZCNT32rm:
4031   case X86::TZCNT64rr: case X86::TZCNT64rm:
4032   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
4033   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
4034   case X86::BLCI32rr:    case X86::BLCI32rm:
4035   case X86::BLCI64rr:    case X86::BLCI64rm:
4036   case X86::BLCIC32rr:   case X86::BLCIC32rm:
4037   case X86::BLCIC64rr:   case X86::BLCIC64rm:
4038   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
4039   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
4040   case X86::BLCS32rr:    case X86::BLCS32rm:
4041   case X86::BLCS64rr:    case X86::BLCS64rm:
4042   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
4043   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
4044   case X86::BLSIC32rr:   case X86::BLSIC32rm:
4045   case X86::BLSIC64rr:   case X86::BLSIC64rm:
4046   case X86::T1MSKC32rr:  case X86::T1MSKC32rm:
4047   case X86::T1MSKC64rr:  case X86::T1MSKC64rm:
4048   case X86::TZMSK32rr:   case X86::TZMSK32rm:
4049   case X86::TZMSK64rr:   case X86::TZMSK64rm:
4050     return true;
4051   case X86::BEXTR32rr:   case X86::BEXTR64rr:
4052   case X86::BEXTR32rm:   case X86::BEXTR64rm:
4053   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
4054   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
4055     // BEXTR doesn't update the sign flag so we can't use it.
4056     NoSignFlag = true;
4057     return true;
4058   }
4059 }
4060 
4061 /// Check whether the use can be converted to remove a comparison against zero.
4062 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
4063   switch (MI.getOpcode()) {
4064   default: return X86::COND_INVALID;
4065   case X86::NEG8r:
4066   case X86::NEG16r:
4067   case X86::NEG32r:
4068   case X86::NEG64r:
4069     return X86::COND_AE;
4070   case X86::LZCNT16rr:
4071   case X86::LZCNT32rr:
4072   case X86::LZCNT64rr:
4073     return X86::COND_B;
4074   case X86::POPCNT16rr:
4075   case X86::POPCNT32rr:
4076   case X86::POPCNT64rr:
4077     return X86::COND_E;
4078   case X86::TZCNT16rr:
4079   case X86::TZCNT32rr:
4080   case X86::TZCNT64rr:
4081     return X86::COND_B;
4082   case X86::BSF16rr:
4083   case X86::BSF32rr:
4084   case X86::BSF64rr:
4085   case X86::BSR16rr:
4086   case X86::BSR32rr:
4087   case X86::BSR64rr:
4088     return X86::COND_E;
4089   case X86::BLSI32rr:
4090   case X86::BLSI64rr:
4091     return X86::COND_AE;
4092   case X86::BLSR32rr:
4093   case X86::BLSR64rr:
4094   case X86::BLSMSK32rr:
4095   case X86::BLSMSK64rr:
4096     return X86::COND_B;
4097   // TODO: TBM instructions.
4098   }
4099 }
4100 
4101 /// Check if there exists an earlier instruction that
4102 /// operates on the same source operands and sets flags in the same way as
4103 /// Compare; remove Compare if possible.
4104 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
4105                                         Register SrcReg2, int CmpMask,
4106                                         int CmpValue,
4107                                         const MachineRegisterInfo *MRI) const {
4108   // Check whether we can replace SUB with CMP.
4109   switch (CmpInstr.getOpcode()) {
4110   default: break;
4111   case X86::SUB64ri32:
4112   case X86::SUB64ri8:
4113   case X86::SUB32ri:
4114   case X86::SUB32ri8:
4115   case X86::SUB16ri:
4116   case X86::SUB16ri8:
4117   case X86::SUB8ri:
4118   case X86::SUB64rm:
4119   case X86::SUB32rm:
4120   case X86::SUB16rm:
4121   case X86::SUB8rm:
4122   case X86::SUB64rr:
4123   case X86::SUB32rr:
4124   case X86::SUB16rr:
4125   case X86::SUB8rr: {
4126     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
4127       return false;
4128     // There is no use of the destination register, we can replace SUB with CMP.
4129     unsigned NewOpcode = 0;
4130     switch (CmpInstr.getOpcode()) {
4131     default: llvm_unreachable("Unreachable!");
4132     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4133     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4134     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4135     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4136     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4137     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4138     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4139     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4140     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4141     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4142     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4143     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4144     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4145     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4146     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4147     }
4148     CmpInstr.setDesc(get(NewOpcode));
4149     CmpInstr.RemoveOperand(0);
4150     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4151     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4152         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4153       return false;
4154   }
4155   }
4156 
4157   // Get the unique definition of SrcReg.
4158   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4159   if (!MI) return false;
4160 
4161   // CmpInstr is the first instruction of the BB.
4162   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4163 
4164   // If we are comparing against zero, check whether we can use MI to update
4165   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4166   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
4167   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
4168     return false;
4169 
4170   // If we have a use of the source register between the def and our compare
4171   // instruction we can eliminate the compare iff the use sets EFLAGS in the
4172   // right way.
4173   bool ShouldUpdateCC = false;
4174   bool NoSignFlag = false;
4175   X86::CondCode NewCC = X86::COND_INVALID;
4176   if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
4177     // Scan forward from the use until we hit the use we're looking for or the
4178     // compare instruction.
4179     for (MachineBasicBlock::iterator J = MI;; ++J) {
4180       // Do we have a convertible instruction?
4181       NewCC = isUseDefConvertible(*J);
4182       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4183           J->getOperand(1).getReg() == SrcReg) {
4184         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4185         ShouldUpdateCC = true; // Update CC later on.
4186         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4187         // with the new def.
4188         Def = J;
4189         MI = &*Def;
4190         break;
4191       }
4192 
4193       if (J == I)
4194         return false;
4195     }
4196   }
4197 
4198   // We are searching for an earlier instruction that can make CmpInstr
4199   // redundant and that instruction will be saved in Sub.
4200   MachineInstr *Sub = nullptr;
4201   const TargetRegisterInfo *TRI = &getRegisterInfo();
4202 
4203   // We iterate backward, starting from the instruction before CmpInstr and
4204   // stop when reaching the definition of a source register or done with the BB.
4205   // RI points to the instruction before CmpInstr.
4206   // If the definition is in this basic block, RE points to the definition;
4207   // otherwise, RE is the rend of the basic block.
4208   MachineBasicBlock::reverse_iterator
4209       RI = ++I.getReverse(),
4210       RE = CmpInstr.getParent() == MI->getParent()
4211                ? Def.getReverse() /* points to MI */
4212                : CmpInstr.getParent()->rend();
4213   MachineInstr *Movr0Inst = nullptr;
4214   for (; RI != RE; ++RI) {
4215     MachineInstr &Instr = *RI;
4216     // Check whether CmpInstr can be made redundant by the current instruction.
4217     if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
4218                                            CmpValue, Instr)) {
4219       Sub = &Instr;
4220       break;
4221     }
4222 
4223     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
4224         Instr.readsRegister(X86::EFLAGS, TRI)) {
4225       // This instruction modifies or uses EFLAGS.
4226 
4227       // MOV32r0 etc. are implemented with xor which clobbers condition code.
4228       // They are safe to move up, if the definition to EFLAGS is dead and
4229       // earlier instructions do not read or write EFLAGS.
4230       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
4231           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
4232         Movr0Inst = &Instr;
4233         continue;
4234       }
4235 
4236       // We can't remove CmpInstr.
4237       return false;
4238     }
4239   }
4240 
4241   // Return false if no candidates exist.
4242   if (!IsCmpZero && !Sub)
4243     return false;
4244 
4245   bool IsSwapped =
4246       (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
4247        Sub->getOperand(2).getReg() == SrcReg);
4248 
4249   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4250   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4251   // If we are done with the basic block, we need to check whether EFLAGS is
4252   // live-out.
4253   bool IsSafe = false;
4254   SmallVector<std::pair<MachineInstr*, X86::CondCode>, 4> OpsToUpdate;
4255   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
4256   for (++I; I != E; ++I) {
4257     const MachineInstr &Instr = *I;
4258     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4259     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4260     // We should check the usage if this instruction uses and updates EFLAGS.
4261     if (!UseEFLAGS && ModifyEFLAGS) {
4262       // It is safe to remove CmpInstr if EFLAGS is updated again.
4263       IsSafe = true;
4264       break;
4265     }
4266     if (!UseEFLAGS && !ModifyEFLAGS)
4267       continue;
4268 
4269     // EFLAGS is used by this instruction.
4270     X86::CondCode OldCC = X86::COND_INVALID;
4271     if (IsCmpZero || IsSwapped) {
4272       // We decode the condition code from opcode.
4273       if (Instr.isBranch())
4274         OldCC = X86::getCondFromBranch(Instr);
4275       else {
4276         OldCC = X86::getCondFromSETCC(Instr);
4277         if (OldCC == X86::COND_INVALID)
4278           OldCC = X86::getCondFromCMov(Instr);
4279       }
4280       if (OldCC == X86::COND_INVALID) return false;
4281     }
4282     X86::CondCode ReplacementCC = X86::COND_INVALID;
4283     if (IsCmpZero) {
4284       switch (OldCC) {
4285       default: break;
4286       case X86::COND_A: case X86::COND_AE:
4287       case X86::COND_B: case X86::COND_BE:
4288       case X86::COND_G: case X86::COND_GE:
4289       case X86::COND_L: case X86::COND_LE:
4290       case X86::COND_O: case X86::COND_NO:
4291         // CF and OF are used, we can't perform this optimization.
4292         return false;
4293       case X86::COND_S: case X86::COND_NS:
4294         // If SF is used, but the instruction doesn't update the SF, then we
4295         // can't do the optimization.
4296         if (NoSignFlag)
4297           return false;
4298         break;
4299       }
4300 
4301       // If we're updating the condition code check if we have to reverse the
4302       // condition.
4303       if (ShouldUpdateCC)
4304         switch (OldCC) {
4305         default:
4306           return false;
4307         case X86::COND_E:
4308           ReplacementCC = NewCC;
4309           break;
4310         case X86::COND_NE:
4311           ReplacementCC = GetOppositeBranchCondition(NewCC);
4312           break;
4313         }
4314     } else if (IsSwapped) {
4315       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4316       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4317       // We swap the condition code and synthesize the new opcode.
4318       ReplacementCC = getSwappedCondition(OldCC);
4319       if (ReplacementCC == X86::COND_INVALID) return false;
4320     }
4321 
4322     if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
4323       // Push the MachineInstr to OpsToUpdate.
4324       // If it is safe to remove CmpInstr, the condition code of these
4325       // instructions will be modified.
4326       OpsToUpdate.push_back(std::make_pair(&*I, ReplacementCC));
4327     }
4328     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4329       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4330       IsSafe = true;
4331       break;
4332     }
4333   }
4334 
4335   // If EFLAGS is not killed nor re-defined, we should check whether it is
4336   // live-out. If it is live-out, do not optimize.
4337   if ((IsCmpZero || IsSwapped) && !IsSafe) {
4338     MachineBasicBlock *MBB = CmpInstr.getParent();
4339     for (MachineBasicBlock *Successor : MBB->successors())
4340       if (Successor->isLiveIn(X86::EFLAGS))
4341         return false;
4342   }
4343 
4344   // The instruction to be updated is either Sub or MI.
4345   Sub = IsCmpZero ? MI : Sub;
4346   // Move Movr0Inst to the appropriate place before Sub.
4347   if (Movr0Inst) {
4348     // Look backwards until we find a def that doesn't use the current EFLAGS.
4349     Def = Sub;
4350     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
4351                                         InsertE = Sub->getParent()->rend();
4352     for (; InsertI != InsertE; ++InsertI) {
4353       MachineInstr *Instr = &*InsertI;
4354       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4355           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4356         Sub->getParent()->remove(Movr0Inst);
4357         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4358                                    Movr0Inst);
4359         break;
4360       }
4361     }
4362     if (InsertI == InsertE)
4363       return false;
4364   }
4365 
4366   // Make sure Sub instruction defines EFLAGS and mark the def live.
4367   MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
4368   assert(FlagDef && "Unable to locate a def EFLAGS operand");
4369   FlagDef->setIsDead(false);
4370 
4371   CmpInstr.eraseFromParent();
4372 
4373   // Modify the condition code of instructions in OpsToUpdate.
4374   for (auto &Op : OpsToUpdate) {
4375     Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
4376         .setImm(Op.second);
4377   }
4378   return true;
4379 }
4380 
4381 /// Try to remove the load by folding it to a register
4382 /// operand at the use. We fold the load instructions if load defines a virtual
4383 /// register, the virtual register is used once in the same BB, and the
4384 /// instructions in-between do not load or store, and have no side effects.
4385 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
4386                                               const MachineRegisterInfo *MRI,
4387                                               Register &FoldAsLoadDefReg,
4388                                               MachineInstr *&DefMI) const {
4389   // Check whether we can move DefMI here.
4390   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4391   assert(DefMI);
4392   bool SawStore = false;
4393   if (!DefMI->isSafeToMove(nullptr, SawStore))
4394     return nullptr;
4395 
4396   // Collect information about virtual register operands of MI.
4397   SmallVector<unsigned, 1> SrcOperandIds;
4398   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4399     MachineOperand &MO = MI.getOperand(i);
4400     if (!MO.isReg())
4401       continue;
4402     Register Reg = MO.getReg();
4403     if (Reg != FoldAsLoadDefReg)
4404       continue;
4405     // Do not fold if we have a subreg use or a def.
4406     if (MO.getSubReg() || MO.isDef())
4407       return nullptr;
4408     SrcOperandIds.push_back(i);
4409   }
4410   if (SrcOperandIds.empty())
4411     return nullptr;
4412 
4413   // Check whether we can fold the def into SrcOperandId.
4414   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
4415     FoldAsLoadDefReg = 0;
4416     return FoldMI;
4417   }
4418 
4419   return nullptr;
4420 }
4421 
4422 /// Expand a single-def pseudo instruction to a two-addr
4423 /// instruction with two undef reads of the register being defined.
4424 /// This is used for mapping:
4425 ///   %xmm4 = V_SET0
4426 /// to:
4427 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
4428 ///
4429 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4430                              const MCInstrDesc &Desc) {
4431   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4432   Register Reg = MIB.getReg(0);
4433   MIB->setDesc(Desc);
4434 
4435   // MachineInstr::addOperand() will insert explicit operands before any
4436   // implicit operands.
4437   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4438   // But we don't trust that.
4439   assert(MIB.getReg(1) == Reg &&
4440          MIB.getReg(2) == Reg && "Misplaced operand");
4441   return true;
4442 }
4443 
4444 /// Expand a single-def pseudo instruction to a two-addr
4445 /// instruction with two %k0 reads.
4446 /// This is used for mapping:
4447 ///   %k4 = K_SET1
4448 /// to:
4449 ///   %k4 = KXNORrr %k0, %k0
4450 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
4451                             const MCInstrDesc &Desc, unsigned Reg) {
4452   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4453   MIB->setDesc(Desc);
4454   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4455   return true;
4456 }
4457 
4458 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
4459                           bool MinusOne) {
4460   MachineBasicBlock &MBB = *MIB->getParent();
4461   DebugLoc DL = MIB->getDebugLoc();
4462   Register Reg = MIB.getReg(0);
4463 
4464   // Insert the XOR.
4465   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
4466       .addReg(Reg, RegState::Undef)
4467       .addReg(Reg, RegState::Undef);
4468 
4469   // Turn the pseudo into an INC or DEC.
4470   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
4471   MIB.addReg(Reg);
4472 
4473   return true;
4474 }
4475 
4476 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
4477                                const TargetInstrInfo &TII,
4478                                const X86Subtarget &Subtarget) {
4479   MachineBasicBlock &MBB = *MIB->getParent();
4480   DebugLoc DL = MIB->getDebugLoc();
4481   int64_t Imm = MIB->getOperand(1).getImm();
4482   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
4483   MachineBasicBlock::iterator I = MIB.getInstr();
4484 
4485   int StackAdjustment;
4486 
4487   if (Subtarget.is64Bit()) {
4488     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
4489            MIB->getOpcode() == X86::MOV32ImmSExti8);
4490 
4491     // Can't use push/pop lowering if the function might write to the red zone.
4492     X86MachineFunctionInfo *X86FI =
4493         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
4494     if (X86FI->getUsesRedZone()) {
4495       MIB->setDesc(TII.get(MIB->getOpcode() ==
4496                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
4497       return true;
4498     }
4499 
4500     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
4501     // widen the register if necessary.
4502     StackAdjustment = 8;
4503     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
4504     MIB->setDesc(TII.get(X86::POP64r));
4505     MIB->getOperand(0)
4506         .setReg(getX86SubSuperRegister(MIB.getReg(0), 64));
4507   } else {
4508     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
4509     StackAdjustment = 4;
4510     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
4511     MIB->setDesc(TII.get(X86::POP32r));
4512   }
4513   MIB->RemoveOperand(1);
4514   MIB->addImplicitDefUseOperands(*MBB.getParent());
4515 
4516   // Build CFI if necessary.
4517   MachineFunction &MF = *MBB.getParent();
4518   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
4519   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
4520   bool NeedsDwarfCFI = !IsWin64Prologue && MF.needsFrameMoves();
4521   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
4522   if (EmitCFI) {
4523     TFL->BuildCFI(MBB, I, DL,
4524         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
4525     TFL->BuildCFI(MBB, std::next(I), DL,
4526         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
4527   }
4528 
4529   return true;
4530 }
4531 
4532 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4533 // code sequence is needed for other targets.
4534 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4535                                  const TargetInstrInfo &TII) {
4536   MachineBasicBlock &MBB = *MIB->getParent();
4537   DebugLoc DL = MIB->getDebugLoc();
4538   Register Reg = MIB.getReg(0);
4539   const GlobalValue *GV =
4540       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4541   auto Flags = MachineMemOperand::MOLoad |
4542                MachineMemOperand::MODereferenceable |
4543                MachineMemOperand::MOInvariant;
4544   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4545       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, Align(8));
4546   MachineBasicBlock::iterator I = MIB.getInstr();
4547 
4548   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4549       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4550       .addMemOperand(MMO);
4551   MIB->setDebugLoc(DL);
4552   MIB->setDesc(TII.get(X86::MOV64rm));
4553   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4554 }
4555 
4556 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4557   MachineBasicBlock &MBB = *MIB->getParent();
4558   MachineFunction &MF = *MBB.getParent();
4559   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4560   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4561   unsigned XorOp =
4562       MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4563   MIB->setDesc(TII.get(XorOp));
4564   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4565   return true;
4566 }
4567 
4568 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4569 // but not VLX. If it uses an extended register we need to use an instruction
4570 // that loads the lower 128/256-bit, but is available with only AVX512F.
4571 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4572                             const TargetRegisterInfo *TRI,
4573                             const MCInstrDesc &LoadDesc,
4574                             const MCInstrDesc &BroadcastDesc,
4575                             unsigned SubIdx) {
4576   Register DestReg = MIB.getReg(0);
4577   // Check if DestReg is XMM16-31 or YMM16-31.
4578   if (TRI->getEncodingValue(DestReg) < 16) {
4579     // We can use a normal VEX encoded load.
4580     MIB->setDesc(LoadDesc);
4581   } else {
4582     // Use a 128/256-bit VBROADCAST instruction.
4583     MIB->setDesc(BroadcastDesc);
4584     // Change the destination to a 512-bit register.
4585     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4586     MIB->getOperand(0).setReg(DestReg);
4587   }
4588   return true;
4589 }
4590 
4591 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4592 // but not VLX. If it uses an extended register we need to use an instruction
4593 // that stores the lower 128/256-bit, but is available with only AVX512F.
4594 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4595                              const TargetRegisterInfo *TRI,
4596                              const MCInstrDesc &StoreDesc,
4597                              const MCInstrDesc &ExtractDesc,
4598                              unsigned SubIdx) {
4599   Register SrcReg = MIB.getReg(X86::AddrNumOperands);
4600   // Check if DestReg is XMM16-31 or YMM16-31.
4601   if (TRI->getEncodingValue(SrcReg) < 16) {
4602     // We can use a normal VEX encoded store.
4603     MIB->setDesc(StoreDesc);
4604   } else {
4605     // Use a VEXTRACTF instruction.
4606     MIB->setDesc(ExtractDesc);
4607     // Change the destination to a 512-bit register.
4608     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4609     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4610     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4611   }
4612 
4613   return true;
4614 }
4615 
4616 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4617   MIB->setDesc(Desc);
4618   int64_t ShiftAmt = MIB->getOperand(2).getImm();
4619   // Temporarily remove the immediate so we can add another source register.
4620   MIB->RemoveOperand(2);
4621   // Add the register. Don't copy the kill flag if there is one.
4622   MIB.addReg(MIB.getReg(1),
4623              getUndefRegState(MIB->getOperand(1).isUndef()));
4624   // Add back the immediate.
4625   MIB.addImm(ShiftAmt);
4626   return true;
4627 }
4628 
4629 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4630   bool HasAVX = Subtarget.hasAVX();
4631   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4632   switch (MI.getOpcode()) {
4633   case X86::MOV32r0:
4634     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4635   case X86::MOV32r1:
4636     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4637   case X86::MOV32r_1:
4638     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4639   case X86::MOV32ImmSExti8:
4640   case X86::MOV64ImmSExti8:
4641     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4642   case X86::SETB_C32r:
4643     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4644   case X86::SETB_C64r:
4645     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4646   case X86::MMX_SET0:
4647     return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4648   case X86::V_SET0:
4649   case X86::FsFLD0SS:
4650   case X86::FsFLD0SD:
4651   case X86::FsFLD0F128:
4652     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4653   case X86::AVX_SET0: {
4654     assert(HasAVX && "AVX not supported");
4655     const TargetRegisterInfo *TRI = &getRegisterInfo();
4656     Register SrcReg = MIB.getReg(0);
4657     Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4658     MIB->getOperand(0).setReg(XReg);
4659     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4660     MIB.addReg(SrcReg, RegState::ImplicitDefine);
4661     return true;
4662   }
4663   case X86::AVX512_128_SET0:
4664   case X86::AVX512_FsFLD0SS:
4665   case X86::AVX512_FsFLD0SD:
4666   case X86::AVX512_FsFLD0F128: {
4667     bool HasVLX = Subtarget.hasVLX();
4668     Register SrcReg = MIB.getReg(0);
4669     const TargetRegisterInfo *TRI = &getRegisterInfo();
4670     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4671       return Expand2AddrUndef(MIB,
4672                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4673     // Extended register without VLX. Use a larger XOR.
4674     SrcReg =
4675         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4676     MIB->getOperand(0).setReg(SrcReg);
4677     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4678   }
4679   case X86::AVX512_256_SET0:
4680   case X86::AVX512_512_SET0: {
4681     bool HasVLX = Subtarget.hasVLX();
4682     Register SrcReg = MIB.getReg(0);
4683     const TargetRegisterInfo *TRI = &getRegisterInfo();
4684     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4685       Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4686       MIB->getOperand(0).setReg(XReg);
4687       Expand2AddrUndef(MIB,
4688                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4689       MIB.addReg(SrcReg, RegState::ImplicitDefine);
4690       return true;
4691     }
4692     if (MI.getOpcode() == X86::AVX512_256_SET0) {
4693       // No VLX so we must reference a zmm.
4694       unsigned ZReg =
4695         TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
4696       MIB->getOperand(0).setReg(ZReg);
4697     }
4698     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4699   }
4700   case X86::V_SETALLONES:
4701     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4702   case X86::AVX2_SETALLONES:
4703     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4704   case X86::AVX1_SETALLONES: {
4705     Register Reg = MIB.getReg(0);
4706     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4707     MIB->setDesc(get(X86::VCMPPSYrri));
4708     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4709     return true;
4710   }
4711   case X86::AVX512_512_SETALLONES: {
4712     Register Reg = MIB.getReg(0);
4713     MIB->setDesc(get(X86::VPTERNLOGDZrri));
4714     // VPTERNLOGD needs 3 register inputs and an immediate.
4715     // 0xff will return 1s for any input.
4716     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4717        .addReg(Reg, RegState::Undef).addImm(0xff);
4718     return true;
4719   }
4720   case X86::AVX512_512_SEXT_MASK_32:
4721   case X86::AVX512_512_SEXT_MASK_64: {
4722     Register Reg = MIB.getReg(0);
4723     Register MaskReg = MIB.getReg(1);
4724     unsigned MaskState = getRegState(MIB->getOperand(1));
4725     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4726                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4727     MI.RemoveOperand(1);
4728     MIB->setDesc(get(Opc));
4729     // VPTERNLOG needs 3 register inputs and an immediate.
4730     // 0xff will return 1s for any input.
4731     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4732        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4733     return true;
4734   }
4735   case X86::VMOVAPSZ128rm_NOVLX:
4736     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4737                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4738   case X86::VMOVUPSZ128rm_NOVLX:
4739     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4740                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4741   case X86::VMOVAPSZ256rm_NOVLX:
4742     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4743                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4744   case X86::VMOVUPSZ256rm_NOVLX:
4745     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4746                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4747   case X86::VMOVAPSZ128mr_NOVLX:
4748     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4749                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4750   case X86::VMOVUPSZ128mr_NOVLX:
4751     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4752                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4753   case X86::VMOVAPSZ256mr_NOVLX:
4754     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4755                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4756   case X86::VMOVUPSZ256mr_NOVLX:
4757     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4758                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4759   case X86::MOV32ri64: {
4760     Register Reg = MIB.getReg(0);
4761     Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4762     MI.setDesc(get(X86::MOV32ri));
4763     MIB->getOperand(0).setReg(Reg32);
4764     MIB.addReg(Reg, RegState::ImplicitDefine);
4765     return true;
4766   }
4767 
4768   // KNL does not recognize dependency-breaking idioms for mask registers,
4769   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4770   // Using %k0 as the undef input register is a performance heuristic based
4771   // on the assumption that %k0 is used less frequently than the other mask
4772   // registers, since it is not usable as a write mask.
4773   // FIXME: A more advanced approach would be to choose the best input mask
4774   // register based on context.
4775   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4776   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4777   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4778   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4779   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4780   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4781   case TargetOpcode::LOAD_STACK_GUARD:
4782     expandLoadStackGuard(MIB, *this);
4783     return true;
4784   case X86::XOR64_FP:
4785   case X86::XOR32_FP:
4786     return expandXorFP(MIB, *this);
4787   case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4788   case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4789   case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4790   case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4791   case X86::ADD8rr_DB:    MIB->setDesc(get(X86::OR8rr));    break;
4792   case X86::ADD16rr_DB:   MIB->setDesc(get(X86::OR16rr));   break;
4793   case X86::ADD32rr_DB:   MIB->setDesc(get(X86::OR32rr));   break;
4794   case X86::ADD64rr_DB:   MIB->setDesc(get(X86::OR64rr));   break;
4795   case X86::ADD8ri_DB:    MIB->setDesc(get(X86::OR8ri));    break;
4796   case X86::ADD16ri_DB:   MIB->setDesc(get(X86::OR16ri));   break;
4797   case X86::ADD32ri_DB:   MIB->setDesc(get(X86::OR32ri));   break;
4798   case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4799   case X86::ADD16ri8_DB:  MIB->setDesc(get(X86::OR16ri8));  break;
4800   case X86::ADD32ri8_DB:  MIB->setDesc(get(X86::OR32ri8));  break;
4801   case X86::ADD64ri8_DB:  MIB->setDesc(get(X86::OR64ri8));  break;
4802   }
4803   return false;
4804 }
4805 
4806 /// Return true for all instructions that only update
4807 /// the first 32 or 64-bits of the destination register and leave the rest
4808 /// unmodified. This can be used to avoid folding loads if the instructions
4809 /// only update part of the destination register, and the non-updated part is
4810 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4811 /// instructions breaks the partial register dependency and it can improve
4812 /// performance. e.g.:
4813 ///
4814 ///   movss (%rdi), %xmm0
4815 ///   cvtss2sd %xmm0, %xmm0
4816 ///
4817 /// Instead of
4818 ///   cvtss2sd (%rdi), %xmm0
4819 ///
4820 /// FIXME: This should be turned into a TSFlags.
4821 ///
4822 static bool hasPartialRegUpdate(unsigned Opcode,
4823                                 const X86Subtarget &Subtarget,
4824                                 bool ForLoadFold = false) {
4825   switch (Opcode) {
4826   case X86::CVTSI2SSrr:
4827   case X86::CVTSI2SSrm:
4828   case X86::CVTSI642SSrr:
4829   case X86::CVTSI642SSrm:
4830   case X86::CVTSI2SDrr:
4831   case X86::CVTSI2SDrm:
4832   case X86::CVTSI642SDrr:
4833   case X86::CVTSI642SDrm:
4834     // Load folding won't effect the undef register update since the input is
4835     // a GPR.
4836     return !ForLoadFold;
4837   case X86::CVTSD2SSrr:
4838   case X86::CVTSD2SSrm:
4839   case X86::CVTSS2SDrr:
4840   case X86::CVTSS2SDrm:
4841   case X86::MOVHPDrm:
4842   case X86::MOVHPSrm:
4843   case X86::MOVLPDrm:
4844   case X86::MOVLPSrm:
4845   case X86::RCPSSr:
4846   case X86::RCPSSm:
4847   case X86::RCPSSr_Int:
4848   case X86::RCPSSm_Int:
4849   case X86::ROUNDSDr:
4850   case X86::ROUNDSDm:
4851   case X86::ROUNDSSr:
4852   case X86::ROUNDSSm:
4853   case X86::RSQRTSSr:
4854   case X86::RSQRTSSm:
4855   case X86::RSQRTSSr_Int:
4856   case X86::RSQRTSSm_Int:
4857   case X86::SQRTSSr:
4858   case X86::SQRTSSm:
4859   case X86::SQRTSSr_Int:
4860   case X86::SQRTSSm_Int:
4861   case X86::SQRTSDr:
4862   case X86::SQRTSDm:
4863   case X86::SQRTSDr_Int:
4864   case X86::SQRTSDm_Int:
4865     return true;
4866   // GPR
4867   case X86::POPCNT32rm:
4868   case X86::POPCNT32rr:
4869   case X86::POPCNT64rm:
4870   case X86::POPCNT64rr:
4871     return Subtarget.hasPOPCNTFalseDeps();
4872   case X86::LZCNT32rm:
4873   case X86::LZCNT32rr:
4874   case X86::LZCNT64rm:
4875   case X86::LZCNT64rr:
4876   case X86::TZCNT32rm:
4877   case X86::TZCNT32rr:
4878   case X86::TZCNT64rm:
4879   case X86::TZCNT64rr:
4880     return Subtarget.hasLZCNTFalseDeps();
4881   }
4882 
4883   return false;
4884 }
4885 
4886 /// Inform the BreakFalseDeps pass how many idle
4887 /// instructions we would like before a partial register update.
4888 unsigned X86InstrInfo::getPartialRegUpdateClearance(
4889     const MachineInstr &MI, unsigned OpNum,
4890     const TargetRegisterInfo *TRI) const {
4891   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4892     return 0;
4893 
4894   // If MI is marked as reading Reg, the partial register update is wanted.
4895   const MachineOperand &MO = MI.getOperand(0);
4896   Register Reg = MO.getReg();
4897   if (Register::isVirtualRegister(Reg)) {
4898     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4899       return 0;
4900   } else {
4901     if (MI.readsRegister(Reg, TRI))
4902       return 0;
4903   }
4904 
4905   // If any instructions in the clearance range are reading Reg, insert a
4906   // dependency breaking instruction, which is inexpensive and is likely to
4907   // be hidden in other instruction's cycles.
4908   return PartialRegUpdateClearance;
4909 }
4910 
4911 // Return true for any instruction the copies the high bits of the first source
4912 // operand into the unused high bits of the destination operand.
4913 // Also returns true for instructions that have two inputs where one may
4914 // be undef and we want it to use the same register as the other input.
4915 static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
4916                               bool ForLoadFold = false) {
4917   // Set the OpNum parameter to the first source operand.
4918   switch (Opcode) {
4919   case X86::MMX_PUNPCKHBWirr:
4920   case X86::MMX_PUNPCKHWDirr:
4921   case X86::MMX_PUNPCKHDQirr:
4922   case X86::MMX_PUNPCKLBWirr:
4923   case X86::MMX_PUNPCKLWDirr:
4924   case X86::MMX_PUNPCKLDQirr:
4925   case X86::MOVHLPSrr:
4926   case X86::PACKSSWBrr:
4927   case X86::PACKUSWBrr:
4928   case X86::PACKSSDWrr:
4929   case X86::PACKUSDWrr:
4930   case X86::PUNPCKHBWrr:
4931   case X86::PUNPCKLBWrr:
4932   case X86::PUNPCKHWDrr:
4933   case X86::PUNPCKLWDrr:
4934   case X86::PUNPCKHDQrr:
4935   case X86::PUNPCKLDQrr:
4936   case X86::PUNPCKHQDQrr:
4937   case X86::PUNPCKLQDQrr:
4938   case X86::SHUFPDrri:
4939   case X86::SHUFPSrri:
4940     // These instructions are sometimes used with an undef first or second
4941     // source. Return true here so BreakFalseDeps will assign this source to the
4942     // same register as the first source to avoid a false dependency.
4943     // Operand 1 of these instructions is tied so they're separate from their
4944     // VEX counterparts.
4945     return OpNum == 2 && !ForLoadFold;
4946 
4947   case X86::VMOVLHPSrr:
4948   case X86::VMOVLHPSZrr:
4949   case X86::VPACKSSWBrr:
4950   case X86::VPACKUSWBrr:
4951   case X86::VPACKSSDWrr:
4952   case X86::VPACKUSDWrr:
4953   case X86::VPACKSSWBZ128rr:
4954   case X86::VPACKUSWBZ128rr:
4955   case X86::VPACKSSDWZ128rr:
4956   case X86::VPACKUSDWZ128rr:
4957   case X86::VPERM2F128rr:
4958   case X86::VPERM2I128rr:
4959   case X86::VSHUFF32X4Z256rri:
4960   case X86::VSHUFF32X4Zrri:
4961   case X86::VSHUFF64X2Z256rri:
4962   case X86::VSHUFF64X2Zrri:
4963   case X86::VSHUFI32X4Z256rri:
4964   case X86::VSHUFI32X4Zrri:
4965   case X86::VSHUFI64X2Z256rri:
4966   case X86::VSHUFI64X2Zrri:
4967   case X86::VPUNPCKHBWrr:
4968   case X86::VPUNPCKLBWrr:
4969   case X86::VPUNPCKHBWYrr:
4970   case X86::VPUNPCKLBWYrr:
4971   case X86::VPUNPCKHBWZ128rr:
4972   case X86::VPUNPCKLBWZ128rr:
4973   case X86::VPUNPCKHBWZ256rr:
4974   case X86::VPUNPCKLBWZ256rr:
4975   case X86::VPUNPCKHBWZrr:
4976   case X86::VPUNPCKLBWZrr:
4977   case X86::VPUNPCKHWDrr:
4978   case X86::VPUNPCKLWDrr:
4979   case X86::VPUNPCKHWDYrr:
4980   case X86::VPUNPCKLWDYrr:
4981   case X86::VPUNPCKHWDZ128rr:
4982   case X86::VPUNPCKLWDZ128rr:
4983   case X86::VPUNPCKHWDZ256rr:
4984   case X86::VPUNPCKLWDZ256rr:
4985   case X86::VPUNPCKHWDZrr:
4986   case X86::VPUNPCKLWDZrr:
4987   case X86::VPUNPCKHDQrr:
4988   case X86::VPUNPCKLDQrr:
4989   case X86::VPUNPCKHDQYrr:
4990   case X86::VPUNPCKLDQYrr:
4991   case X86::VPUNPCKHDQZ128rr:
4992   case X86::VPUNPCKLDQZ128rr:
4993   case X86::VPUNPCKHDQZ256rr:
4994   case X86::VPUNPCKLDQZ256rr:
4995   case X86::VPUNPCKHDQZrr:
4996   case X86::VPUNPCKLDQZrr:
4997   case X86::VPUNPCKHQDQrr:
4998   case X86::VPUNPCKLQDQrr:
4999   case X86::VPUNPCKHQDQYrr:
5000   case X86::VPUNPCKLQDQYrr:
5001   case X86::VPUNPCKHQDQZ128rr:
5002   case X86::VPUNPCKLQDQZ128rr:
5003   case X86::VPUNPCKHQDQZ256rr:
5004   case X86::VPUNPCKLQDQZ256rr:
5005   case X86::VPUNPCKHQDQZrr:
5006   case X86::VPUNPCKLQDQZrr:
5007     // These instructions are sometimes used with an undef first or second
5008     // source. Return true here so BreakFalseDeps will assign this source to the
5009     // same register as the first source to avoid a false dependency.
5010     return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
5011 
5012   case X86::VCVTSI2SSrr:
5013   case X86::VCVTSI2SSrm:
5014   case X86::VCVTSI2SSrr_Int:
5015   case X86::VCVTSI2SSrm_Int:
5016   case X86::VCVTSI642SSrr:
5017   case X86::VCVTSI642SSrm:
5018   case X86::VCVTSI642SSrr_Int:
5019   case X86::VCVTSI642SSrm_Int:
5020   case X86::VCVTSI2SDrr:
5021   case X86::VCVTSI2SDrm:
5022   case X86::VCVTSI2SDrr_Int:
5023   case X86::VCVTSI2SDrm_Int:
5024   case X86::VCVTSI642SDrr:
5025   case X86::VCVTSI642SDrm:
5026   case X86::VCVTSI642SDrr_Int:
5027   case X86::VCVTSI642SDrm_Int:
5028   // AVX-512
5029   case X86::VCVTSI2SSZrr:
5030   case X86::VCVTSI2SSZrm:
5031   case X86::VCVTSI2SSZrr_Int:
5032   case X86::VCVTSI2SSZrrb_Int:
5033   case X86::VCVTSI2SSZrm_Int:
5034   case X86::VCVTSI642SSZrr:
5035   case X86::VCVTSI642SSZrm:
5036   case X86::VCVTSI642SSZrr_Int:
5037   case X86::VCVTSI642SSZrrb_Int:
5038   case X86::VCVTSI642SSZrm_Int:
5039   case X86::VCVTSI2SDZrr:
5040   case X86::VCVTSI2SDZrm:
5041   case X86::VCVTSI2SDZrr_Int:
5042   case X86::VCVTSI2SDZrm_Int:
5043   case X86::VCVTSI642SDZrr:
5044   case X86::VCVTSI642SDZrm:
5045   case X86::VCVTSI642SDZrr_Int:
5046   case X86::VCVTSI642SDZrrb_Int:
5047   case X86::VCVTSI642SDZrm_Int:
5048   case X86::VCVTUSI2SSZrr:
5049   case X86::VCVTUSI2SSZrm:
5050   case X86::VCVTUSI2SSZrr_Int:
5051   case X86::VCVTUSI2SSZrrb_Int:
5052   case X86::VCVTUSI2SSZrm_Int:
5053   case X86::VCVTUSI642SSZrr:
5054   case X86::VCVTUSI642SSZrm:
5055   case X86::VCVTUSI642SSZrr_Int:
5056   case X86::VCVTUSI642SSZrrb_Int:
5057   case X86::VCVTUSI642SSZrm_Int:
5058   case X86::VCVTUSI2SDZrr:
5059   case X86::VCVTUSI2SDZrm:
5060   case X86::VCVTUSI2SDZrr_Int:
5061   case X86::VCVTUSI2SDZrm_Int:
5062   case X86::VCVTUSI642SDZrr:
5063   case X86::VCVTUSI642SDZrm:
5064   case X86::VCVTUSI642SDZrr_Int:
5065   case X86::VCVTUSI642SDZrrb_Int:
5066   case X86::VCVTUSI642SDZrm_Int:
5067     // Load folding won't effect the undef register update since the input is
5068     // a GPR.
5069     return OpNum == 1 && !ForLoadFold;
5070   case X86::VCVTSD2SSrr:
5071   case X86::VCVTSD2SSrm:
5072   case X86::VCVTSD2SSrr_Int:
5073   case X86::VCVTSD2SSrm_Int:
5074   case X86::VCVTSS2SDrr:
5075   case X86::VCVTSS2SDrm:
5076   case X86::VCVTSS2SDrr_Int:
5077   case X86::VCVTSS2SDrm_Int:
5078   case X86::VRCPSSr:
5079   case X86::VRCPSSr_Int:
5080   case X86::VRCPSSm:
5081   case X86::VRCPSSm_Int:
5082   case X86::VROUNDSDr:
5083   case X86::VROUNDSDm:
5084   case X86::VROUNDSDr_Int:
5085   case X86::VROUNDSDm_Int:
5086   case X86::VROUNDSSr:
5087   case X86::VROUNDSSm:
5088   case X86::VROUNDSSr_Int:
5089   case X86::VROUNDSSm_Int:
5090   case X86::VRSQRTSSr:
5091   case X86::VRSQRTSSr_Int:
5092   case X86::VRSQRTSSm:
5093   case X86::VRSQRTSSm_Int:
5094   case X86::VSQRTSSr:
5095   case X86::VSQRTSSr_Int:
5096   case X86::VSQRTSSm:
5097   case X86::VSQRTSSm_Int:
5098   case X86::VSQRTSDr:
5099   case X86::VSQRTSDr_Int:
5100   case X86::VSQRTSDm:
5101   case X86::VSQRTSDm_Int:
5102   // AVX-512
5103   case X86::VCVTSD2SSZrr:
5104   case X86::VCVTSD2SSZrr_Int:
5105   case X86::VCVTSD2SSZrrb_Int:
5106   case X86::VCVTSD2SSZrm:
5107   case X86::VCVTSD2SSZrm_Int:
5108   case X86::VCVTSS2SDZrr:
5109   case X86::VCVTSS2SDZrr_Int:
5110   case X86::VCVTSS2SDZrrb_Int:
5111   case X86::VCVTSS2SDZrm:
5112   case X86::VCVTSS2SDZrm_Int:
5113   case X86::VGETEXPSDZr:
5114   case X86::VGETEXPSDZrb:
5115   case X86::VGETEXPSDZm:
5116   case X86::VGETEXPSSZr:
5117   case X86::VGETEXPSSZrb:
5118   case X86::VGETEXPSSZm:
5119   case X86::VGETMANTSDZrri:
5120   case X86::VGETMANTSDZrrib:
5121   case X86::VGETMANTSDZrmi:
5122   case X86::VGETMANTSSZrri:
5123   case X86::VGETMANTSSZrrib:
5124   case X86::VGETMANTSSZrmi:
5125   case X86::VRNDSCALESDZr:
5126   case X86::VRNDSCALESDZr_Int:
5127   case X86::VRNDSCALESDZrb_Int:
5128   case X86::VRNDSCALESDZm:
5129   case X86::VRNDSCALESDZm_Int:
5130   case X86::VRNDSCALESSZr:
5131   case X86::VRNDSCALESSZr_Int:
5132   case X86::VRNDSCALESSZrb_Int:
5133   case X86::VRNDSCALESSZm:
5134   case X86::VRNDSCALESSZm_Int:
5135   case X86::VRCP14SDZrr:
5136   case X86::VRCP14SDZrm:
5137   case X86::VRCP14SSZrr:
5138   case X86::VRCP14SSZrm:
5139   case X86::VRCP28SDZr:
5140   case X86::VRCP28SDZrb:
5141   case X86::VRCP28SDZm:
5142   case X86::VRCP28SSZr:
5143   case X86::VRCP28SSZrb:
5144   case X86::VRCP28SSZm:
5145   case X86::VREDUCESSZrmi:
5146   case X86::VREDUCESSZrri:
5147   case X86::VREDUCESSZrrib:
5148   case X86::VRSQRT14SDZrr:
5149   case X86::VRSQRT14SDZrm:
5150   case X86::VRSQRT14SSZrr:
5151   case X86::VRSQRT14SSZrm:
5152   case X86::VRSQRT28SDZr:
5153   case X86::VRSQRT28SDZrb:
5154   case X86::VRSQRT28SDZm:
5155   case X86::VRSQRT28SSZr:
5156   case X86::VRSQRT28SSZrb:
5157   case X86::VRSQRT28SSZm:
5158   case X86::VSQRTSSZr:
5159   case X86::VSQRTSSZr_Int:
5160   case X86::VSQRTSSZrb_Int:
5161   case X86::VSQRTSSZm:
5162   case X86::VSQRTSSZm_Int:
5163   case X86::VSQRTSDZr:
5164   case X86::VSQRTSDZr_Int:
5165   case X86::VSQRTSDZrb_Int:
5166   case X86::VSQRTSDZm:
5167   case X86::VSQRTSDZm_Int:
5168     return OpNum == 1;
5169   case X86::VMOVSSZrrk:
5170   case X86::VMOVSDZrrk:
5171     return OpNum == 3 && !ForLoadFold;
5172   case X86::VMOVSSZrrkz:
5173   case X86::VMOVSDZrrkz:
5174     return OpNum == 2 && !ForLoadFold;
5175   }
5176 
5177   return false;
5178 }
5179 
5180 /// Inform the BreakFalseDeps pass how many idle instructions we would like
5181 /// before certain undef register reads.
5182 ///
5183 /// This catches the VCVTSI2SD family of instructions:
5184 ///
5185 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
5186 ///
5187 /// We should to be careful *not* to catch VXOR idioms which are presumably
5188 /// handled specially in the pipeline:
5189 ///
5190 /// vxorps undef %xmm1, undef %xmm1, %xmm1
5191 ///
5192 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5193 /// high bits that are passed-through are not live.
5194 unsigned
5195 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
5196                                    const TargetRegisterInfo *TRI) const {
5197   const MachineOperand &MO = MI.getOperand(OpNum);
5198   if (Register::isPhysicalRegister(MO.getReg()) &&
5199       hasUndefRegUpdate(MI.getOpcode(), OpNum))
5200     return UndefRegClearance;
5201 
5202   return 0;
5203 }
5204 
5205 void X86InstrInfo::breakPartialRegDependency(
5206     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5207   Register Reg = MI.getOperand(OpNum).getReg();
5208   // If MI kills this register, the false dependence is already broken.
5209   if (MI.killsRegister(Reg, TRI))
5210     return;
5211 
5212   if (X86::VR128RegClass.contains(Reg)) {
5213     // These instructions are all floating point domain, so xorps is the best
5214     // choice.
5215     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
5216     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
5217         .addReg(Reg, RegState::Undef)
5218         .addReg(Reg, RegState::Undef);
5219     MI.addRegisterKilled(Reg, TRI, true);
5220   } else if (X86::VR256RegClass.contains(Reg)) {
5221     // Use vxorps to clear the full ymm register.
5222     // It wants to read and write the xmm sub-register.
5223     Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5224     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
5225         .addReg(XReg, RegState::Undef)
5226         .addReg(XReg, RegState::Undef)
5227         .addReg(Reg, RegState::ImplicitDefine);
5228     MI.addRegisterKilled(Reg, TRI, true);
5229   } else if (X86::GR64RegClass.contains(Reg)) {
5230     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
5231     // as well.
5232     Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
5233     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
5234         .addReg(XReg, RegState::Undef)
5235         .addReg(XReg, RegState::Undef)
5236         .addReg(Reg, RegState::ImplicitDefine);
5237     MI.addRegisterKilled(Reg, TRI, true);
5238   } else if (X86::GR32RegClass.contains(Reg)) {
5239     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
5240         .addReg(Reg, RegState::Undef)
5241         .addReg(Reg, RegState::Undef);
5242     MI.addRegisterKilled(Reg, TRI, true);
5243   }
5244 }
5245 
5246 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5247                         int PtrOffset = 0) {
5248   unsigned NumAddrOps = MOs.size();
5249 
5250   if (NumAddrOps < 4) {
5251     // FrameIndex only - add an immediate offset (whether its zero or not).
5252     for (unsigned i = 0; i != NumAddrOps; ++i)
5253       MIB.add(MOs[i]);
5254     addOffset(MIB, PtrOffset);
5255   } else {
5256     // General Memory Addressing - we need to add any offset to an existing
5257     // offset.
5258     assert(MOs.size() == 5 && "Unexpected memory operand list length");
5259     for (unsigned i = 0; i != NumAddrOps; ++i) {
5260       const MachineOperand &MO = MOs[i];
5261       if (i == 3 && PtrOffset != 0) {
5262         MIB.addDisp(MO, PtrOffset);
5263       } else {
5264         MIB.add(MO);
5265       }
5266     }
5267   }
5268 }
5269 
5270 static void updateOperandRegConstraints(MachineFunction &MF,
5271                                         MachineInstr &NewMI,
5272                                         const TargetInstrInfo &TII) {
5273   MachineRegisterInfo &MRI = MF.getRegInfo();
5274   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
5275 
5276   for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
5277     MachineOperand &MO = NewMI.getOperand(Idx);
5278     // We only need to update constraints on virtual register operands.
5279     if (!MO.isReg())
5280       continue;
5281     Register Reg = MO.getReg();
5282     if (!Register::isVirtualRegister(Reg))
5283       continue;
5284 
5285     auto *NewRC = MRI.constrainRegClass(
5286         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
5287     if (!NewRC) {
5288       LLVM_DEBUG(
5289           dbgs() << "WARNING: Unable to update register constraint for operand "
5290                  << Idx << " of instruction:\n";
5291           NewMI.dump(); dbgs() << "\n");
5292     }
5293   }
5294 }
5295 
5296 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
5297                                      ArrayRef<MachineOperand> MOs,
5298                                      MachineBasicBlock::iterator InsertPt,
5299                                      MachineInstr &MI,
5300                                      const TargetInstrInfo &TII) {
5301   // Create the base instruction with the memory operand as the first part.
5302   // Omit the implicit operands, something BuildMI can't do.
5303   MachineInstr *NewMI =
5304       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5305   MachineInstrBuilder MIB(MF, NewMI);
5306   addOperands(MIB, MOs);
5307 
5308   // Loop over the rest of the ri operands, converting them over.
5309   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
5310   for (unsigned i = 0; i != NumOps; ++i) {
5311     MachineOperand &MO = MI.getOperand(i + 2);
5312     MIB.add(MO);
5313   }
5314   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5315     MachineOperand &MO = MI.getOperand(i);
5316     MIB.add(MO);
5317   }
5318 
5319   updateOperandRegConstraints(MF, *NewMI, TII);
5320 
5321   MachineBasicBlock *MBB = InsertPt->getParent();
5322   MBB->insert(InsertPt, NewMI);
5323 
5324   return MIB;
5325 }
5326 
5327 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5328                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
5329                               MachineBasicBlock::iterator InsertPt,
5330                               MachineInstr &MI, const TargetInstrInfo &TII,
5331                               int PtrOffset = 0) {
5332   // Omit the implicit operands, something BuildMI can't do.
5333   MachineInstr *NewMI =
5334       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
5335   MachineInstrBuilder MIB(MF, NewMI);
5336 
5337   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5338     MachineOperand &MO = MI.getOperand(i);
5339     if (i == OpNo) {
5340       assert(MO.isReg() && "Expected to fold into reg operand!");
5341       addOperands(MIB, MOs, PtrOffset);
5342     } else {
5343       MIB.add(MO);
5344     }
5345   }
5346 
5347   updateOperandRegConstraints(MF, *NewMI, TII);
5348 
5349   // Copy the NoFPExcept flag from the instruction we're fusing.
5350   if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
5351     NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept);
5352 
5353   MachineBasicBlock *MBB = InsertPt->getParent();
5354   MBB->insert(InsertPt, NewMI);
5355 
5356   return MIB;
5357 }
5358 
5359 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
5360                                 ArrayRef<MachineOperand> MOs,
5361                                 MachineBasicBlock::iterator InsertPt,
5362                                 MachineInstr &MI) {
5363   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5364                                     MI.getDebugLoc(), TII.get(Opcode));
5365   addOperands(MIB, MOs);
5366   return MIB.addImm(0);
5367 }
5368 
5369 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5370     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5371     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5372     unsigned Size, Align Alignment) const {
5373   switch (MI.getOpcode()) {
5374   case X86::INSERTPSrr:
5375   case X86::VINSERTPSrr:
5376   case X86::VINSERTPSZrr:
5377     // Attempt to convert the load of inserted vector into a fold load
5378     // of a single float.
5379     if (OpNum == 2) {
5380       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
5381       unsigned ZMask = Imm & 15;
5382       unsigned DstIdx = (Imm >> 4) & 3;
5383       unsigned SrcIdx = (Imm >> 6) & 3;
5384 
5385       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5386       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5387       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5388       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(4)) {
5389         int PtrOffset = SrcIdx * 4;
5390         unsigned NewImm = (DstIdx << 4) | ZMask;
5391         unsigned NewOpCode =
5392             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
5393             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
5394                                                     X86::INSERTPSrm;
5395         MachineInstr *NewMI =
5396             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5397         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5398         return NewMI;
5399       }
5400     }
5401     break;
5402   case X86::MOVHLPSrr:
5403   case X86::VMOVHLPSrr:
5404   case X86::VMOVHLPSZrr:
5405     // Move the upper 64-bits of the second operand to the lower 64-bits.
5406     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5407     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5408     if (OpNum == 2) {
5409       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5410       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5411       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5412       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment >= Align(8)) {
5413         unsigned NewOpCode =
5414             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
5415             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
5416                                                    X86::MOVLPSrm;
5417         MachineInstr *NewMI =
5418             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5419         return NewMI;
5420       }
5421     }
5422     break;
5423   case X86::UNPCKLPDrr:
5424     // If we won't be able to fold this to the memory form of UNPCKL, use
5425     // MOVHPD instead. Done as custom because we can't have this in the load
5426     // table twice.
5427     if (OpNum == 2) {
5428       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5429       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
5430       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5431       if ((Size == 0 || Size >= 16) && RCSize >= 16 && Alignment < Align(16)) {
5432         MachineInstr *NewMI =
5433             FuseInst(MF, X86::MOVHPDrm, OpNum, MOs, InsertPt, MI, *this);
5434         return NewMI;
5435       }
5436     }
5437     break;
5438   }
5439 
5440   return nullptr;
5441 }
5442 
5443 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
5444                                                MachineInstr &MI) {
5445   if (!hasUndefRegUpdate(MI.getOpcode(), 1, /*ForLoadFold*/true) ||
5446       !MI.getOperand(1).isReg())
5447     return false;
5448 
5449   // The are two cases we need to handle depending on where in the pipeline
5450   // the folding attempt is being made.
5451   // -Register has the undef flag set.
5452   // -Register is produced by the IMPLICIT_DEF instruction.
5453 
5454   if (MI.getOperand(1).isUndef())
5455     return true;
5456 
5457   MachineRegisterInfo &RegInfo = MF.getRegInfo();
5458   MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
5459   return VRegDef && VRegDef->isImplicitDef();
5460 }
5461 
5462 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5463     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
5464     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5465     unsigned Size, Align Alignment, bool AllowCommute) const {
5466   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
5467   bool isTwoAddrFold = false;
5468 
5469   // For CPUs that favor the register form of a call or push,
5470   // do not fold loads into calls or pushes, unless optimizing for size
5471   // aggressively.
5472   if (isSlowTwoMemOps && !MF.getFunction().hasMinSize() &&
5473       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5474        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5475        MI.getOpcode() == X86::PUSH64r))
5476     return nullptr;
5477 
5478   // Avoid partial and undef register update stalls unless optimizing for size.
5479   if (!MF.getFunction().hasOptSize() &&
5480       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5481        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5482     return nullptr;
5483 
5484   unsigned NumOps = MI.getDesc().getNumOperands();
5485   bool isTwoAddr =
5486       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5487 
5488   // FIXME: AsmPrinter doesn't know how to handle
5489   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5490   if (MI.getOpcode() == X86::ADD32ri &&
5491       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5492     return nullptr;
5493 
5494   // GOTTPOFF relocation loads can only be folded into add instructions.
5495   // FIXME: Need to exclude other relocations that only support specific
5496   // instructions.
5497   if (MOs.size() == X86::AddrNumOperands &&
5498       MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
5499       MI.getOpcode() != X86::ADD64rr)
5500     return nullptr;
5501 
5502   MachineInstr *NewMI = nullptr;
5503 
5504   // Attempt to fold any custom cases we have.
5505   if (MachineInstr *CustomMI = foldMemoryOperandCustom(
5506           MF, MI, OpNum, MOs, InsertPt, Size, Alignment))
5507     return CustomMI;
5508 
5509   const X86MemoryFoldTableEntry *I = nullptr;
5510 
5511   // Folding a memory location into the two-address part of a two-address
5512   // instruction is different than folding it other places.  It requires
5513   // replacing the *two* registers with the memory location.
5514   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5515       MI.getOperand(1).isReg() &&
5516       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
5517     I = lookupTwoAddrFoldTable(MI.getOpcode());
5518     isTwoAddrFold = true;
5519   } else {
5520     if (OpNum == 0) {
5521       if (MI.getOpcode() == X86::MOV32r0) {
5522         NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
5523         if (NewMI)
5524           return NewMI;
5525       }
5526     }
5527 
5528     I = lookupFoldTable(MI.getOpcode(), OpNum);
5529   }
5530 
5531   if (I != nullptr) {
5532     unsigned Opcode = I->DstOp;
5533     bool FoldedLoad =
5534         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_LOAD) || OpNum > 0;
5535     bool FoldedStore =
5536         isTwoAddrFold || (OpNum == 0 && I->Flags & TB_FOLDED_STORE);
5537     MaybeAlign MinAlign =
5538         decodeMaybeAlign((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT);
5539     if (MinAlign && Alignment < *MinAlign)
5540       return nullptr;
5541     bool NarrowToMOV32rm = false;
5542     if (Size) {
5543       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5544       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
5545                                                   &RI, MF);
5546       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
5547       // Check if it's safe to fold the load. If the size of the object is
5548       // narrower than the load width, then it's not.
5549       // FIXME: Allow scalar intrinsic instructions like ADDSSrm_Int.
5550       if (FoldedLoad && Size < RCSize) {
5551         // If this is a 64-bit load, but the spill slot is 32, then we can do
5552         // a 32-bit load which is implicitly zero-extended. This likely is
5553         // due to live interval analysis remat'ing a load from stack slot.
5554         if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
5555           return nullptr;
5556         if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
5557           return nullptr;
5558         Opcode = X86::MOV32rm;
5559         NarrowToMOV32rm = true;
5560       }
5561       // For stores, make sure the size of the object is equal to the size of
5562       // the store. If the object is larger, the extra bits would be garbage. If
5563       // the object is smaller we might overwrite another object or fault.
5564       if (FoldedStore && Size != RCSize)
5565         return nullptr;
5566     }
5567 
5568     if (isTwoAddrFold)
5569       NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
5570     else
5571       NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
5572 
5573     if (NarrowToMOV32rm) {
5574       // If this is the special case where we use a MOV32rm to load a 32-bit
5575       // value and zero-extend the top bits. Change the destination register
5576       // to a 32-bit one.
5577       Register DstReg = NewMI->getOperand(0).getReg();
5578       if (Register::isPhysicalRegister(DstReg))
5579         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
5580       else
5581         NewMI->getOperand(0).setSubReg(X86::sub_32bit);
5582     }
5583     return NewMI;
5584   }
5585 
5586   // If the instruction and target operand are commutable, commute the
5587   // instruction and try again.
5588   if (AllowCommute) {
5589     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
5590     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5591       bool HasDef = MI.getDesc().getNumDefs();
5592       Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
5593       Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5594       Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5595       bool Tied1 =
5596           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5597       bool Tied2 =
5598           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5599 
5600       // If either of the commutable operands are tied to the destination
5601       // then we can not commute + fold.
5602       if ((HasDef && Reg0 == Reg1 && Tied1) ||
5603           (HasDef && Reg0 == Reg2 && Tied2))
5604         return nullptr;
5605 
5606       MachineInstr *CommutedMI =
5607           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5608       if (!CommutedMI) {
5609         // Unable to commute.
5610         return nullptr;
5611       }
5612       if (CommutedMI != &MI) {
5613         // New instruction. We can't fold from this.
5614         CommutedMI->eraseFromParent();
5615         return nullptr;
5616       }
5617 
5618       // Attempt to fold with the commuted version of the instruction.
5619       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt, Size,
5620                                     Alignment, /*AllowCommute=*/false);
5621       if (NewMI)
5622         return NewMI;
5623 
5624       // Folding failed again - undo the commute before returning.
5625       MachineInstr *UncommutedMI =
5626           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5627       if (!UncommutedMI) {
5628         // Unable to commute.
5629         return nullptr;
5630       }
5631       if (UncommutedMI != &MI) {
5632         // New instruction. It doesn't need to be kept.
5633         UncommutedMI->eraseFromParent();
5634         return nullptr;
5635       }
5636 
5637       // Return here to prevent duplicate fuse failure report.
5638       return nullptr;
5639     }
5640   }
5641 
5642   // No fusion
5643   if (PrintFailedFusing && !MI.isCopy())
5644     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
5645   return nullptr;
5646 }
5647 
5648 MachineInstr *
5649 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
5650                                     ArrayRef<unsigned> Ops,
5651                                     MachineBasicBlock::iterator InsertPt,
5652                                     int FrameIndex, LiveIntervals *LIS,
5653                                     VirtRegMap *VRM) const {
5654   // Check switch flag
5655   if (NoFusing)
5656     return nullptr;
5657 
5658   // Avoid partial and undef register update stalls unless optimizing for size.
5659   if (!MF.getFunction().hasOptSize() &&
5660       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5661        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5662     return nullptr;
5663 
5664   // Don't fold subreg spills, or reloads that use a high subreg.
5665   for (auto Op : Ops) {
5666     MachineOperand &MO = MI.getOperand(Op);
5667     auto SubReg = MO.getSubReg();
5668     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
5669       return nullptr;
5670   }
5671 
5672   const MachineFrameInfo &MFI = MF.getFrameInfo();
5673   unsigned Size = MFI.getObjectSize(FrameIndex);
5674   Align Alignment = MFI.getObjectAlign(FrameIndex);
5675   // If the function stack isn't realigned we don't want to fold instructions
5676   // that need increased alignment.
5677   if (!RI.needsStackRealignment(MF))
5678     Alignment =
5679         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlign());
5680   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5681     unsigned NewOpc = 0;
5682     unsigned RCSize = 0;
5683     switch (MI.getOpcode()) {
5684     default: return nullptr;
5685     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5686     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5687     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5688     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5689     }
5690     // Check if it's safe to fold the load. If the size of the object is
5691     // narrower than the load width, then it's not.
5692     if (Size < RCSize)
5693       return nullptr;
5694     // Change to CMPXXri r, 0 first.
5695     MI.setDesc(get(NewOpc));
5696     MI.getOperand(1).ChangeToImmediate(0);
5697   } else if (Ops.size() != 1)
5698     return nullptr;
5699 
5700   return foldMemoryOperandImpl(MF, MI, Ops[0],
5701                                MachineOperand::CreateFI(FrameIndex), InsertPt,
5702                                Size, Alignment, /*AllowCommute=*/true);
5703 }
5704 
5705 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5706 /// because the latter uses contents that wouldn't be defined in the folded
5707 /// version.  For instance, this transformation isn't legal:
5708 ///   movss (%rdi), %xmm0
5709 ///   addps %xmm0, %xmm0
5710 /// ->
5711 ///   addps (%rdi), %xmm0
5712 ///
5713 /// But this one is:
5714 ///   movss (%rdi), %xmm0
5715 ///   addss %xmm0, %xmm0
5716 /// ->
5717 ///   addss (%rdi), %xmm0
5718 ///
5719 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5720                                              const MachineInstr &UserMI,
5721                                              const MachineFunction &MF) {
5722   unsigned Opc = LoadMI.getOpcode();
5723   unsigned UserOpc = UserMI.getOpcode();
5724   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5725   const TargetRegisterClass *RC =
5726       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5727   unsigned RegSize = TRI.getRegSizeInBits(*RC);
5728 
5729   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm ||
5730        Opc == X86::MOVSSrm_alt || Opc == X86::VMOVSSrm_alt ||
5731        Opc == X86::VMOVSSZrm_alt) &&
5732       RegSize > 32) {
5733     // These instructions only load 32 bits, we can't fold them if the
5734     // destination register is wider than 32 bits (4 bytes), and its user
5735     // instruction isn't scalar (SS).
5736     switch (UserOpc) {
5737     case X86::CVTSS2SDrr_Int:
5738     case X86::VCVTSS2SDrr_Int:
5739     case X86::VCVTSS2SDZrr_Int:
5740     case X86::VCVTSS2SDZrr_Intk:
5741     case X86::VCVTSS2SDZrr_Intkz:
5742     case X86::CVTSS2SIrr_Int:     case X86::CVTSS2SI64rr_Int:
5743     case X86::VCVTSS2SIrr_Int:    case X86::VCVTSS2SI64rr_Int:
5744     case X86::VCVTSS2SIZrr_Int:   case X86::VCVTSS2SI64Zrr_Int:
5745     case X86::CVTTSS2SIrr_Int:    case X86::CVTTSS2SI64rr_Int:
5746     case X86::VCVTTSS2SIrr_Int:   case X86::VCVTTSS2SI64rr_Int:
5747     case X86::VCVTTSS2SIZrr_Int:  case X86::VCVTTSS2SI64Zrr_Int:
5748     case X86::VCVTSS2USIZrr_Int:  case X86::VCVTSS2USI64Zrr_Int:
5749     case X86::VCVTTSS2USIZrr_Int: case X86::VCVTTSS2USI64Zrr_Int:
5750     case X86::RCPSSr_Int:   case X86::VRCPSSr_Int:
5751     case X86::RSQRTSSr_Int: case X86::VRSQRTSSr_Int:
5752     case X86::ROUNDSSr_Int: case X86::VROUNDSSr_Int:
5753     case X86::COMISSrr_Int: case X86::VCOMISSrr_Int: case X86::VCOMISSZrr_Int:
5754     case X86::UCOMISSrr_Int:case X86::VUCOMISSrr_Int:case X86::VUCOMISSZrr_Int:
5755     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5756     case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5757     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5758     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5759     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5760     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5761     case X86::SQRTSSr_Int: case X86::VSQRTSSr_Int: case X86::VSQRTSSZr_Int:
5762     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5763     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5764     case X86::VCMPSSZrr_Intk:
5765     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5766     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5767     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5768     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5769     case X86::VSQRTSSZr_Intk: case X86::VSQRTSSZr_Intkz:
5770     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5771     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
5772     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
5773     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
5774     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
5775     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
5776     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
5777     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
5778     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
5779     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5780     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5781     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5782     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5783     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5784     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5785     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5786     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5787     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5788     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5789     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5790     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5791     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5792     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5793     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5794     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5795     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5796     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5797     case X86::VFIXUPIMMSSZrri:
5798     case X86::VFIXUPIMMSSZrrik:
5799     case X86::VFIXUPIMMSSZrrikz:
5800     case X86::VFPCLASSSSZrr:
5801     case X86::VFPCLASSSSZrrk:
5802     case X86::VGETEXPSSZr:
5803     case X86::VGETEXPSSZrk:
5804     case X86::VGETEXPSSZrkz:
5805     case X86::VGETMANTSSZrri:
5806     case X86::VGETMANTSSZrrik:
5807     case X86::VGETMANTSSZrrikz:
5808     case X86::VRANGESSZrri:
5809     case X86::VRANGESSZrrik:
5810     case X86::VRANGESSZrrikz:
5811     case X86::VRCP14SSZrr:
5812     case X86::VRCP14SSZrrk:
5813     case X86::VRCP14SSZrrkz:
5814     case X86::VRCP28SSZr:
5815     case X86::VRCP28SSZrk:
5816     case X86::VRCP28SSZrkz:
5817     case X86::VREDUCESSZrri:
5818     case X86::VREDUCESSZrrik:
5819     case X86::VREDUCESSZrrikz:
5820     case X86::VRNDSCALESSZr_Int:
5821     case X86::VRNDSCALESSZr_Intk:
5822     case X86::VRNDSCALESSZr_Intkz:
5823     case X86::VRSQRT14SSZrr:
5824     case X86::VRSQRT14SSZrrk:
5825     case X86::VRSQRT14SSZrrkz:
5826     case X86::VRSQRT28SSZr:
5827     case X86::VRSQRT28SSZrk:
5828     case X86::VRSQRT28SSZrkz:
5829     case X86::VSCALEFSSZrr:
5830     case X86::VSCALEFSSZrrk:
5831     case X86::VSCALEFSSZrrkz:
5832       return false;
5833     default:
5834       return true;
5835     }
5836   }
5837 
5838   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm ||
5839        Opc == X86::MOVSDrm_alt || Opc == X86::VMOVSDrm_alt ||
5840        Opc == X86::VMOVSDZrm_alt) &&
5841       RegSize > 64) {
5842     // These instructions only load 64 bits, we can't fold them if the
5843     // destination register is wider than 64 bits (8 bytes), and its user
5844     // instruction isn't scalar (SD).
5845     switch (UserOpc) {
5846     case X86::CVTSD2SSrr_Int:
5847     case X86::VCVTSD2SSrr_Int:
5848     case X86::VCVTSD2SSZrr_Int:
5849     case X86::VCVTSD2SSZrr_Intk:
5850     case X86::VCVTSD2SSZrr_Intkz:
5851     case X86::CVTSD2SIrr_Int:     case X86::CVTSD2SI64rr_Int:
5852     case X86::VCVTSD2SIrr_Int:    case X86::VCVTSD2SI64rr_Int:
5853     case X86::VCVTSD2SIZrr_Int:   case X86::VCVTSD2SI64Zrr_Int:
5854     case X86::CVTTSD2SIrr_Int:    case X86::CVTTSD2SI64rr_Int:
5855     case X86::VCVTTSD2SIrr_Int:   case X86::VCVTTSD2SI64rr_Int:
5856     case X86::VCVTTSD2SIZrr_Int:  case X86::VCVTTSD2SI64Zrr_Int:
5857     case X86::VCVTSD2USIZrr_Int:  case X86::VCVTSD2USI64Zrr_Int:
5858     case X86::VCVTTSD2USIZrr_Int: case X86::VCVTTSD2USI64Zrr_Int:
5859     case X86::ROUNDSDr_Int: case X86::VROUNDSDr_Int:
5860     case X86::COMISDrr_Int: case X86::VCOMISDrr_Int: case X86::VCOMISDZrr_Int:
5861     case X86::UCOMISDrr_Int:case X86::VUCOMISDrr_Int:case X86::VUCOMISDZrr_Int:
5862     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5863     case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5864     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5865     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
5866     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
5867     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
5868     case X86::SQRTSDr_Int: case X86::VSQRTSDr_Int: case X86::VSQRTSDZr_Int:
5869     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5870     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5871     case X86::VCMPSDZrr_Intk:
5872     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5873     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5874     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5875     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5876     case X86::VSQRTSDZr_Intk: case X86::VSQRTSDZr_Intkz:
5877     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5878     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
5879     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
5880     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
5881     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
5882     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
5883     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
5884     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
5885     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
5886     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5887     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5888     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5889     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5890     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5891     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5892     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5893     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5894     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5895     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5896     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5897     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5898     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5899     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5900     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5901     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5902     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5903     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5904     case X86::VFIXUPIMMSDZrri:
5905     case X86::VFIXUPIMMSDZrrik:
5906     case X86::VFIXUPIMMSDZrrikz:
5907     case X86::VFPCLASSSDZrr:
5908     case X86::VFPCLASSSDZrrk:
5909     case X86::VGETEXPSDZr:
5910     case X86::VGETEXPSDZrk:
5911     case X86::VGETEXPSDZrkz:
5912     case X86::VGETMANTSDZrri:
5913     case X86::VGETMANTSDZrrik:
5914     case X86::VGETMANTSDZrrikz:
5915     case X86::VRANGESDZrri:
5916     case X86::VRANGESDZrrik:
5917     case X86::VRANGESDZrrikz:
5918     case X86::VRCP14SDZrr:
5919     case X86::VRCP14SDZrrk:
5920     case X86::VRCP14SDZrrkz:
5921     case X86::VRCP28SDZr:
5922     case X86::VRCP28SDZrk:
5923     case X86::VRCP28SDZrkz:
5924     case X86::VREDUCESDZrri:
5925     case X86::VREDUCESDZrrik:
5926     case X86::VREDUCESDZrrikz:
5927     case X86::VRNDSCALESDZr_Int:
5928     case X86::VRNDSCALESDZr_Intk:
5929     case X86::VRNDSCALESDZr_Intkz:
5930     case X86::VRSQRT14SDZrr:
5931     case X86::VRSQRT14SDZrrk:
5932     case X86::VRSQRT14SDZrrkz:
5933     case X86::VRSQRT28SDZr:
5934     case X86::VRSQRT28SDZrk:
5935     case X86::VRSQRT28SDZrkz:
5936     case X86::VSCALEFSDZrr:
5937     case X86::VSCALEFSDZrrk:
5938     case X86::VSCALEFSDZrrkz:
5939       return false;
5940     default:
5941       return true;
5942     }
5943   }
5944 
5945   return false;
5946 }
5947 
5948 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5949     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
5950     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5951     LiveIntervals *LIS) const {
5952 
5953   // TODO: Support the case where LoadMI loads a wide register, but MI
5954   // only uses a subreg.
5955   for (auto Op : Ops) {
5956     if (MI.getOperand(Op).getSubReg())
5957       return nullptr;
5958   }
5959 
5960   // If loading from a FrameIndex, fold directly from the FrameIndex.
5961   unsigned NumOps = LoadMI.getDesc().getNumOperands();
5962   int FrameIndex;
5963   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5964     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5965       return nullptr;
5966     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5967   }
5968 
5969   // Check switch flag
5970   if (NoFusing) return nullptr;
5971 
5972   // Avoid partial and undef register update stalls unless optimizing for size.
5973   if (!MF.getFunction().hasOptSize() &&
5974       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5975        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5976     return nullptr;
5977 
5978   // Determine the alignment of the load.
5979   Align Alignment;
5980   if (LoadMI.hasOneMemOperand())
5981     Alignment = (*LoadMI.memoperands_begin())->getAlign();
5982   else
5983     switch (LoadMI.getOpcode()) {
5984     case X86::AVX512_512_SET0:
5985     case X86::AVX512_512_SETALLONES:
5986       Alignment = Align(64);
5987       break;
5988     case X86::AVX2_SETALLONES:
5989     case X86::AVX1_SETALLONES:
5990     case X86::AVX_SET0:
5991     case X86::AVX512_256_SET0:
5992       Alignment = Align(32);
5993       break;
5994     case X86::V_SET0:
5995     case X86::V_SETALLONES:
5996     case X86::AVX512_128_SET0:
5997     case X86::FsFLD0F128:
5998     case X86::AVX512_FsFLD0F128:
5999       Alignment = Align(16);
6000       break;
6001     case X86::MMX_SET0:
6002     case X86::FsFLD0SD:
6003     case X86::AVX512_FsFLD0SD:
6004       Alignment = Align(8);
6005       break;
6006     case X86::FsFLD0SS:
6007     case X86::AVX512_FsFLD0SS:
6008       Alignment = Align(4);
6009       break;
6010     default:
6011       return nullptr;
6012     }
6013   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6014     unsigned NewOpc = 0;
6015     switch (MI.getOpcode()) {
6016     default: return nullptr;
6017     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
6018     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6019     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6020     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
6021     }
6022     // Change to CMPXXri r, 0 first.
6023     MI.setDesc(get(NewOpc));
6024     MI.getOperand(1).ChangeToImmediate(0);
6025   } else if (Ops.size() != 1)
6026     return nullptr;
6027 
6028   // Make sure the subregisters match.
6029   // Otherwise we risk changing the size of the load.
6030   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
6031     return nullptr;
6032 
6033   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
6034   switch (LoadMI.getOpcode()) {
6035   case X86::MMX_SET0:
6036   case X86::V_SET0:
6037   case X86::V_SETALLONES:
6038   case X86::AVX2_SETALLONES:
6039   case X86::AVX1_SETALLONES:
6040   case X86::AVX_SET0:
6041   case X86::AVX512_128_SET0:
6042   case X86::AVX512_256_SET0:
6043   case X86::AVX512_512_SET0:
6044   case X86::AVX512_512_SETALLONES:
6045   case X86::FsFLD0SD:
6046   case X86::AVX512_FsFLD0SD:
6047   case X86::FsFLD0SS:
6048   case X86::AVX512_FsFLD0SS:
6049   case X86::FsFLD0F128:
6050   case X86::AVX512_FsFLD0F128: {
6051     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
6052     // Create a constant-pool entry and operands to load from it.
6053 
6054     // Medium and large mode can't fold loads this way.
6055     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6056         MF.getTarget().getCodeModel() != CodeModel::Kernel)
6057       return nullptr;
6058 
6059     // x86-32 PIC requires a PIC base register for constant pools.
6060     unsigned PICBase = 0;
6061     if (MF.getTarget().isPositionIndependent()) {
6062       if (Subtarget.is64Bit())
6063         PICBase = X86::RIP;
6064       else
6065         // FIXME: PICBase = getGlobalBaseReg(&MF);
6066         // This doesn't work for several reasons.
6067         // 1. GlobalBaseReg may have been spilled.
6068         // 2. It may not be live at MI.
6069         return nullptr;
6070     }
6071 
6072     // Create a constant-pool entry.
6073     MachineConstantPool &MCP = *MF.getConstantPool();
6074     Type *Ty;
6075     unsigned Opc = LoadMI.getOpcode();
6076     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
6077       Ty = Type::getFloatTy(MF.getFunction().getContext());
6078     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
6079       Ty = Type::getDoubleTy(MF.getFunction().getContext());
6080     else if (Opc == X86::FsFLD0F128 || Opc == X86::AVX512_FsFLD0F128)
6081       Ty = Type::getFP128Ty(MF.getFunction().getContext());
6082     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
6083       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6084                                 16);
6085     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
6086              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
6087       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6088                                 8);
6089     else if (Opc == X86::MMX_SET0)
6090       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6091                                 2);
6092     else
6093       Ty = FixedVectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),
6094                                 4);
6095 
6096     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
6097                       Opc == X86::AVX512_512_SETALLONES ||
6098                       Opc == X86::AVX1_SETALLONES);
6099     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6100                                     Constant::getNullValue(Ty);
6101     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
6102 
6103     // Create operands to load from the constant pool entry.
6104     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6105     MOs.push_back(MachineOperand::CreateImm(1));
6106     MOs.push_back(MachineOperand::CreateReg(0, false));
6107     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
6108     MOs.push_back(MachineOperand::CreateReg(0, false));
6109     break;
6110   }
6111   default: {
6112     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
6113       return nullptr;
6114 
6115     // Folding a normal load. Just copy the load's address operands.
6116     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6117                LoadMI.operands_begin() + NumOps);
6118     break;
6119   }
6120   }
6121   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
6122                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
6123 }
6124 
6125 static SmallVector<MachineMemOperand *, 2>
6126 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6127   SmallVector<MachineMemOperand *, 2> LoadMMOs;
6128 
6129   for (MachineMemOperand *MMO : MMOs) {
6130     if (!MMO->isLoad())
6131       continue;
6132 
6133     if (!MMO->isStore()) {
6134       // Reuse the MMO.
6135       LoadMMOs.push_back(MMO);
6136     } else {
6137       // Clone the MMO and unset the store flag.
6138       LoadMMOs.push_back(MF.getMachineMemOperand(
6139           MMO, MMO->getFlags() & ~MachineMemOperand::MOStore));
6140     }
6141   }
6142 
6143   return LoadMMOs;
6144 }
6145 
6146 static SmallVector<MachineMemOperand *, 2>
6147 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
6148   SmallVector<MachineMemOperand *, 2> StoreMMOs;
6149 
6150   for (MachineMemOperand *MMO : MMOs) {
6151     if (!MMO->isStore())
6152       continue;
6153 
6154     if (!MMO->isLoad()) {
6155       // Reuse the MMO.
6156       StoreMMOs.push_back(MMO);
6157     } else {
6158       // Clone the MMO and unset the load flag.
6159       StoreMMOs.push_back(MF.getMachineMemOperand(
6160           MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad));
6161     }
6162   }
6163 
6164   return StoreMMOs;
6165 }
6166 
6167 static unsigned getBroadcastOpcode(const X86MemoryFoldTableEntry *I,
6168                                    const TargetRegisterClass *RC,
6169                                    const X86Subtarget &STI) {
6170   assert(STI.hasAVX512() && "Expected at least AVX512!");
6171   unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
6172   assert((SpillSize == 64 || STI.hasVLX()) &&
6173          "Can't broadcast less than 64 bytes without AVX512VL!");
6174 
6175   switch (I->Flags & TB_BCAST_MASK) {
6176   default: llvm_unreachable("Unexpected broadcast type!");
6177   case TB_BCAST_D:
6178     switch (SpillSize) {
6179     default: llvm_unreachable("Unknown spill size");
6180     case 16: return X86::VPBROADCASTDZ128rm;
6181     case 32: return X86::VPBROADCASTDZ256rm;
6182     case 64: return X86::VPBROADCASTDZrm;
6183     }
6184     break;
6185   case TB_BCAST_Q:
6186     switch (SpillSize) {
6187     default: llvm_unreachable("Unknown spill size");
6188     case 16: return X86::VPBROADCASTQZ128rm;
6189     case 32: return X86::VPBROADCASTQZ256rm;
6190     case 64: return X86::VPBROADCASTQZrm;
6191     }
6192     break;
6193   case TB_BCAST_SS:
6194     switch (SpillSize) {
6195     default: llvm_unreachable("Unknown spill size");
6196     case 16: return X86::VBROADCASTSSZ128rm;
6197     case 32: return X86::VBROADCASTSSZ256rm;
6198     case 64: return X86::VBROADCASTSSZrm;
6199     }
6200     break;
6201   case TB_BCAST_SD:
6202     switch (SpillSize) {
6203     default: llvm_unreachable("Unknown spill size");
6204     case 16: return X86::VMOVDDUPZ128rm;
6205     case 32: return X86::VBROADCASTSDZ256rm;
6206     case 64: return X86::VBROADCASTSDZrm;
6207     }
6208     break;
6209   }
6210 }
6211 
6212 bool X86InstrInfo::unfoldMemoryOperand(
6213     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6214     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6215   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
6216   if (I == nullptr)
6217     return false;
6218   unsigned Opc = I->DstOp;
6219   unsigned Index = I->Flags & TB_INDEX_MASK;
6220   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6221   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6222   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6223   if (UnfoldLoad && !FoldedLoad)
6224     return false;
6225   UnfoldLoad &= FoldedLoad;
6226   if (UnfoldStore && !FoldedStore)
6227     return false;
6228   UnfoldStore &= FoldedStore;
6229 
6230   const MCInstrDesc &MCID = get(Opc);
6231 
6232   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6233   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6234   // TODO: Check if 32-byte or greater accesses are slow too?
6235   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
6236       Subtarget.isUnalignedMem16Slow())
6237     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6238     // conservatively assume the address is unaligned. That's bad for
6239     // performance.
6240     return false;
6241   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
6242   SmallVector<MachineOperand,2> BeforeOps;
6243   SmallVector<MachineOperand,2> AfterOps;
6244   SmallVector<MachineOperand,4> ImpOps;
6245   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6246     MachineOperand &Op = MI.getOperand(i);
6247     if (i >= Index && i < Index + X86::AddrNumOperands)
6248       AddrOps.push_back(Op);
6249     else if (Op.isReg() && Op.isImplicit())
6250       ImpOps.push_back(Op);
6251     else if (i < Index)
6252       BeforeOps.push_back(Op);
6253     else if (i > Index)
6254       AfterOps.push_back(Op);
6255   }
6256 
6257   // Emit the load or broadcast instruction.
6258   if (UnfoldLoad) {
6259     auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
6260 
6261     unsigned Opc;
6262     if (FoldedBCast) {
6263       Opc = getBroadcastOpcode(I, RC, Subtarget);
6264     } else {
6265       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6266       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6267       Opc = getLoadRegOpcode(Reg, RC, isAligned, Subtarget);
6268     }
6269 
6270     DebugLoc DL;
6271     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
6272     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6273       MIB.add(AddrOps[i]);
6274     MIB.setMemRefs(MMOs);
6275     NewMIs.push_back(MIB);
6276 
6277     if (UnfoldStore) {
6278       // Address operands cannot be marked isKill.
6279       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
6280         MachineOperand &MO = NewMIs[0]->getOperand(i);
6281         if (MO.isReg())
6282           MO.setIsKill(false);
6283       }
6284     }
6285   }
6286 
6287   // Emit the data processing instruction.
6288   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
6289   MachineInstrBuilder MIB(MF, DataMI);
6290 
6291   if (FoldedStore)
6292     MIB.addReg(Reg, RegState::Define);
6293   for (MachineOperand &BeforeOp : BeforeOps)
6294     MIB.add(BeforeOp);
6295   if (FoldedLoad)
6296     MIB.addReg(Reg);
6297   for (MachineOperand &AfterOp : AfterOps)
6298     MIB.add(AfterOp);
6299   for (MachineOperand &ImpOp : ImpOps) {
6300     MIB.addReg(ImpOp.getReg(),
6301                getDefRegState(ImpOp.isDef()) |
6302                RegState::Implicit |
6303                getKillRegState(ImpOp.isKill()) |
6304                getDeadRegState(ImpOp.isDead()) |
6305                getUndefRegState(ImpOp.isUndef()));
6306   }
6307   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6308   switch (DataMI->getOpcode()) {
6309   default: break;
6310   case X86::CMP64ri32:
6311   case X86::CMP64ri8:
6312   case X86::CMP32ri:
6313   case X86::CMP32ri8:
6314   case X86::CMP16ri:
6315   case X86::CMP16ri8:
6316   case X86::CMP8ri: {
6317     MachineOperand &MO0 = DataMI->getOperand(0);
6318     MachineOperand &MO1 = DataMI->getOperand(1);
6319     if (MO1.getImm() == 0) {
6320       unsigned NewOpc;
6321       switch (DataMI->getOpcode()) {
6322       default: llvm_unreachable("Unreachable!");
6323       case X86::CMP64ri8:
6324       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
6325       case X86::CMP32ri8:
6326       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
6327       case X86::CMP16ri8:
6328       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
6329       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
6330       }
6331       DataMI->setDesc(get(NewOpc));
6332       MO1.ChangeToRegister(MO0.getReg(), false);
6333     }
6334   }
6335   }
6336   NewMIs.push_back(DataMI);
6337 
6338   // Emit the store instruction.
6339   if (UnfoldStore) {
6340     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
6341     auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
6342     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*DstRC), 16);
6343     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6344     unsigned Opc = getStoreRegOpcode(Reg, DstRC, isAligned, Subtarget);
6345     DebugLoc DL;
6346     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6347     for (unsigned i = 0, e = AddrOps.size(); i != e; ++i)
6348       MIB.add(AddrOps[i]);
6349     MIB.addReg(Reg, RegState::Kill);
6350     MIB.setMemRefs(MMOs);
6351     NewMIs.push_back(MIB);
6352   }
6353 
6354   return true;
6355 }
6356 
6357 bool
6358 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
6359                                   SmallVectorImpl<SDNode*> &NewNodes) const {
6360   if (!N->isMachineOpcode())
6361     return false;
6362 
6363   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
6364   if (I == nullptr)
6365     return false;
6366   unsigned Opc = I->DstOp;
6367   unsigned Index = I->Flags & TB_INDEX_MASK;
6368   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6369   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6370   bool FoldedBCast = I->Flags & TB_FOLDED_BCAST;
6371   const MCInstrDesc &MCID = get(Opc);
6372   MachineFunction &MF = DAG.getMachineFunction();
6373   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
6374   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
6375   unsigned NumDefs = MCID.NumDefs;
6376   std::vector<SDValue> AddrOps;
6377   std::vector<SDValue> BeforeOps;
6378   std::vector<SDValue> AfterOps;
6379   SDLoc dl(N);
6380   unsigned NumOps = N->getNumOperands();
6381   for (unsigned i = 0; i != NumOps-1; ++i) {
6382     SDValue Op = N->getOperand(i);
6383     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
6384       AddrOps.push_back(Op);
6385     else if (i < Index-NumDefs)
6386       BeforeOps.push_back(Op);
6387     else if (i > Index-NumDefs)
6388       AfterOps.push_back(Op);
6389   }
6390   SDValue Chain = N->getOperand(NumOps-1);
6391   AddrOps.push_back(Chain);
6392 
6393   // Emit the load instruction.
6394   SDNode *Load = nullptr;
6395   if (FoldedLoad) {
6396     EVT VT = *TRI.legalclasstypes_begin(*RC);
6397     auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6398     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6399         Subtarget.isUnalignedMem16Slow())
6400       // Do not introduce a slow unaligned load.
6401       return false;
6402     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6403     // memory access is slow above.
6404 
6405     unsigned Opc;
6406     if (FoldedBCast) {
6407       Opc = getBroadcastOpcode(I, RC, Subtarget);
6408     } else {
6409       unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6410       bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6411       Opc = getLoadRegOpcode(0, RC, isAligned, Subtarget);
6412     }
6413 
6414     Load = DAG.getMachineNode(Opc, dl, VT, MVT::Other, AddrOps);
6415     NewNodes.push_back(Load);
6416 
6417     // Preserve memory reference information.
6418     DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
6419   }
6420 
6421   // Emit the data processing instruction.
6422   std::vector<EVT> VTs;
6423   const TargetRegisterClass *DstRC = nullptr;
6424   if (MCID.getNumDefs() > 0) {
6425     DstRC = getRegClass(MCID, 0, &RI, MF);
6426     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
6427   }
6428   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
6429     EVT VT = N->getValueType(i);
6430     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
6431       VTs.push_back(VT);
6432   }
6433   if (Load)
6434     BeforeOps.push_back(SDValue(Load, 0));
6435   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
6436   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
6437   switch (Opc) {
6438     default: break;
6439     case X86::CMP64ri32:
6440     case X86::CMP64ri8:
6441     case X86::CMP32ri:
6442     case X86::CMP32ri8:
6443     case X86::CMP16ri:
6444     case X86::CMP16ri8:
6445     case X86::CMP8ri:
6446       if (isNullConstant(BeforeOps[1])) {
6447         switch (Opc) {
6448           default: llvm_unreachable("Unreachable!");
6449           case X86::CMP64ri8:
6450           case X86::CMP64ri32: Opc = X86::TEST64rr; break;
6451           case X86::CMP32ri8:
6452           case X86::CMP32ri:   Opc = X86::TEST32rr; break;
6453           case X86::CMP16ri8:
6454           case X86::CMP16ri:   Opc = X86::TEST16rr; break;
6455           case X86::CMP8ri:    Opc = X86::TEST8rr; break;
6456         }
6457         BeforeOps[1] = BeforeOps[0];
6458       }
6459   }
6460   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
6461   NewNodes.push_back(NewNode);
6462 
6463   // Emit the store instruction.
6464   if (FoldedStore) {
6465     AddrOps.pop_back();
6466     AddrOps.push_back(SDValue(NewNode, 0));
6467     AddrOps.push_back(Chain);
6468     auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
6469     if (MMOs.empty() && RC == &X86::VR128RegClass &&
6470         Subtarget.isUnalignedMem16Slow())
6471       // Do not introduce a slow unaligned store.
6472       return false;
6473     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6474     // memory access is slow above.
6475     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
6476     bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment;
6477     SDNode *Store =
6478         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6479                            dl, MVT::Other, AddrOps);
6480     NewNodes.push_back(Store);
6481 
6482     // Preserve memory reference information.
6483     DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
6484   }
6485 
6486   return true;
6487 }
6488 
6489 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
6490                                       bool UnfoldLoad, bool UnfoldStore,
6491                                       unsigned *LoadRegIndex) const {
6492   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
6493   if (I == nullptr)
6494     return 0;
6495   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
6496   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
6497   if (UnfoldLoad && !FoldedLoad)
6498     return 0;
6499   if (UnfoldStore && !FoldedStore)
6500     return 0;
6501   if (LoadRegIndex)
6502     *LoadRegIndex = I->Flags & TB_INDEX_MASK;
6503   return I->DstOp;
6504 }
6505 
6506 bool
6507 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6508                                      int64_t &Offset1, int64_t &Offset2) const {
6509   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6510     return false;
6511   unsigned Opc1 = Load1->getMachineOpcode();
6512   unsigned Opc2 = Load2->getMachineOpcode();
6513   switch (Opc1) {
6514   default: return false;
6515   case X86::MOV8rm:
6516   case X86::MOV16rm:
6517   case X86::MOV32rm:
6518   case X86::MOV64rm:
6519   case X86::LD_Fp32m:
6520   case X86::LD_Fp64m:
6521   case X86::LD_Fp80m:
6522   case X86::MOVSSrm:
6523   case X86::MOVSSrm_alt:
6524   case X86::MOVSDrm:
6525   case X86::MOVSDrm_alt:
6526   case X86::MMX_MOVD64rm:
6527   case X86::MMX_MOVQ64rm:
6528   case X86::MOVAPSrm:
6529   case X86::MOVUPSrm:
6530   case X86::MOVAPDrm:
6531   case X86::MOVUPDrm:
6532   case X86::MOVDQArm:
6533   case X86::MOVDQUrm:
6534   // AVX load instructions
6535   case X86::VMOVSSrm:
6536   case X86::VMOVSSrm_alt:
6537   case X86::VMOVSDrm:
6538   case X86::VMOVSDrm_alt:
6539   case X86::VMOVAPSrm:
6540   case X86::VMOVUPSrm:
6541   case X86::VMOVAPDrm:
6542   case X86::VMOVUPDrm:
6543   case X86::VMOVDQArm:
6544   case X86::VMOVDQUrm:
6545   case X86::VMOVAPSYrm:
6546   case X86::VMOVUPSYrm:
6547   case X86::VMOVAPDYrm:
6548   case X86::VMOVUPDYrm:
6549   case X86::VMOVDQAYrm:
6550   case X86::VMOVDQUYrm:
6551   // AVX512 load instructions
6552   case X86::VMOVSSZrm:
6553   case X86::VMOVSSZrm_alt:
6554   case X86::VMOVSDZrm:
6555   case X86::VMOVSDZrm_alt:
6556   case X86::VMOVAPSZ128rm:
6557   case X86::VMOVUPSZ128rm:
6558   case X86::VMOVAPSZ128rm_NOVLX:
6559   case X86::VMOVUPSZ128rm_NOVLX:
6560   case X86::VMOVAPDZ128rm:
6561   case X86::VMOVUPDZ128rm:
6562   case X86::VMOVDQU8Z128rm:
6563   case X86::VMOVDQU16Z128rm:
6564   case X86::VMOVDQA32Z128rm:
6565   case X86::VMOVDQU32Z128rm:
6566   case X86::VMOVDQA64Z128rm:
6567   case X86::VMOVDQU64Z128rm:
6568   case X86::VMOVAPSZ256rm:
6569   case X86::VMOVUPSZ256rm:
6570   case X86::VMOVAPSZ256rm_NOVLX:
6571   case X86::VMOVUPSZ256rm_NOVLX:
6572   case X86::VMOVAPDZ256rm:
6573   case X86::VMOVUPDZ256rm:
6574   case X86::VMOVDQU8Z256rm:
6575   case X86::VMOVDQU16Z256rm:
6576   case X86::VMOVDQA32Z256rm:
6577   case X86::VMOVDQU32Z256rm:
6578   case X86::VMOVDQA64Z256rm:
6579   case X86::VMOVDQU64Z256rm:
6580   case X86::VMOVAPSZrm:
6581   case X86::VMOVUPSZrm:
6582   case X86::VMOVAPDZrm:
6583   case X86::VMOVUPDZrm:
6584   case X86::VMOVDQU8Zrm:
6585   case X86::VMOVDQU16Zrm:
6586   case X86::VMOVDQA32Zrm:
6587   case X86::VMOVDQU32Zrm:
6588   case X86::VMOVDQA64Zrm:
6589   case X86::VMOVDQU64Zrm:
6590   case X86::KMOVBkm:
6591   case X86::KMOVWkm:
6592   case X86::KMOVDkm:
6593   case X86::KMOVQkm:
6594     break;
6595   }
6596   switch (Opc2) {
6597   default: return false;
6598   case X86::MOV8rm:
6599   case X86::MOV16rm:
6600   case X86::MOV32rm:
6601   case X86::MOV64rm:
6602   case X86::LD_Fp32m:
6603   case X86::LD_Fp64m:
6604   case X86::LD_Fp80m:
6605   case X86::MOVSSrm:
6606   case X86::MOVSSrm_alt:
6607   case X86::MOVSDrm:
6608   case X86::MOVSDrm_alt:
6609   case X86::MMX_MOVD64rm:
6610   case X86::MMX_MOVQ64rm:
6611   case X86::MOVAPSrm:
6612   case X86::MOVUPSrm:
6613   case X86::MOVAPDrm:
6614   case X86::MOVUPDrm:
6615   case X86::MOVDQArm:
6616   case X86::MOVDQUrm:
6617   // AVX load instructions
6618   case X86::VMOVSSrm:
6619   case X86::VMOVSSrm_alt:
6620   case X86::VMOVSDrm:
6621   case X86::VMOVSDrm_alt:
6622   case X86::VMOVAPSrm:
6623   case X86::VMOVUPSrm:
6624   case X86::VMOVAPDrm:
6625   case X86::VMOVUPDrm:
6626   case X86::VMOVDQArm:
6627   case X86::VMOVDQUrm:
6628   case X86::VMOVAPSYrm:
6629   case X86::VMOVUPSYrm:
6630   case X86::VMOVAPDYrm:
6631   case X86::VMOVUPDYrm:
6632   case X86::VMOVDQAYrm:
6633   case X86::VMOVDQUYrm:
6634   // AVX512 load instructions
6635   case X86::VMOVSSZrm:
6636   case X86::VMOVSSZrm_alt:
6637   case X86::VMOVSDZrm:
6638   case X86::VMOVSDZrm_alt:
6639   case X86::VMOVAPSZ128rm:
6640   case X86::VMOVUPSZ128rm:
6641   case X86::VMOVAPSZ128rm_NOVLX:
6642   case X86::VMOVUPSZ128rm_NOVLX:
6643   case X86::VMOVAPDZ128rm:
6644   case X86::VMOVUPDZ128rm:
6645   case X86::VMOVDQU8Z128rm:
6646   case X86::VMOVDQU16Z128rm:
6647   case X86::VMOVDQA32Z128rm:
6648   case X86::VMOVDQU32Z128rm:
6649   case X86::VMOVDQA64Z128rm:
6650   case X86::VMOVDQU64Z128rm:
6651   case X86::VMOVAPSZ256rm:
6652   case X86::VMOVUPSZ256rm:
6653   case X86::VMOVAPSZ256rm_NOVLX:
6654   case X86::VMOVUPSZ256rm_NOVLX:
6655   case X86::VMOVAPDZ256rm:
6656   case X86::VMOVUPDZ256rm:
6657   case X86::VMOVDQU8Z256rm:
6658   case X86::VMOVDQU16Z256rm:
6659   case X86::VMOVDQA32Z256rm:
6660   case X86::VMOVDQU32Z256rm:
6661   case X86::VMOVDQA64Z256rm:
6662   case X86::VMOVDQU64Z256rm:
6663   case X86::VMOVAPSZrm:
6664   case X86::VMOVUPSZrm:
6665   case X86::VMOVAPDZrm:
6666   case X86::VMOVUPDZrm:
6667   case X86::VMOVDQU8Zrm:
6668   case X86::VMOVDQU16Zrm:
6669   case X86::VMOVDQA32Zrm:
6670   case X86::VMOVDQU32Zrm:
6671   case X86::VMOVDQA64Zrm:
6672   case X86::VMOVDQU64Zrm:
6673   case X86::KMOVBkm:
6674   case X86::KMOVWkm:
6675   case X86::KMOVDkm:
6676   case X86::KMOVQkm:
6677     break;
6678   }
6679 
6680   // Lambda to check if both the loads have the same value for an operand index.
6681   auto HasSameOp = [&](int I) {
6682     return Load1->getOperand(I) == Load2->getOperand(I);
6683   };
6684 
6685   // All operands except the displacement should match.
6686   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
6687       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
6688     return false;
6689 
6690   // Chain Operand must be the same.
6691   if (!HasSameOp(5))
6692     return false;
6693 
6694   // Now let's examine if the displacements are constants.
6695   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
6696   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
6697   if (!Disp1 || !Disp2)
6698     return false;
6699 
6700   Offset1 = Disp1->getSExtValue();
6701   Offset2 = Disp2->getSExtValue();
6702   return true;
6703 }
6704 
6705 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6706                                            int64_t Offset1, int64_t Offset2,
6707                                            unsigned NumLoads) const {
6708   assert(Offset2 > Offset1);
6709   if ((Offset2 - Offset1) / 8 > 64)
6710     return false;
6711 
6712   unsigned Opc1 = Load1->getMachineOpcode();
6713   unsigned Opc2 = Load2->getMachineOpcode();
6714   if (Opc1 != Opc2)
6715     return false;  // FIXME: overly conservative?
6716 
6717   switch (Opc1) {
6718   default: break;
6719   case X86::LD_Fp32m:
6720   case X86::LD_Fp64m:
6721   case X86::LD_Fp80m:
6722   case X86::MMX_MOVD64rm:
6723   case X86::MMX_MOVQ64rm:
6724     return false;
6725   }
6726 
6727   EVT VT = Load1->getValueType(0);
6728   switch (VT.getSimpleVT().SimpleTy) {
6729   default:
6730     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6731     // have 16 of them to play with.
6732     if (Subtarget.is64Bit()) {
6733       if (NumLoads >= 3)
6734         return false;
6735     } else if (NumLoads) {
6736       return false;
6737     }
6738     break;
6739   case MVT::i8:
6740   case MVT::i16:
6741   case MVT::i32:
6742   case MVT::i64:
6743   case MVT::f32:
6744   case MVT::f64:
6745     if (NumLoads)
6746       return false;
6747     break;
6748   }
6749 
6750   return true;
6751 }
6752 
6753 bool X86InstrInfo::isSchedulingBoundary(const MachineInstr &MI,
6754                                         const MachineBasicBlock *MBB,
6755                                         const MachineFunction &MF) const {
6756 
6757   // ENDBR instructions should not be scheduled around.
6758   unsigned Opcode = MI.getOpcode();
6759   if (Opcode == X86::ENDBR64 || Opcode == X86::ENDBR32)
6760     return true;
6761 
6762   return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
6763 }
6764 
6765 bool X86InstrInfo::
6766 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
6767   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
6768   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6769   Cond[0].setImm(GetOppositeBranchCondition(CC));
6770   return false;
6771 }
6772 
6773 bool X86InstrInfo::
6774 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6775   // FIXME: Return false for x87 stack register classes for now. We can't
6776   // allow any loads of these registers before FpGet_ST0_80.
6777   return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
6778            RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
6779            RC == &X86::RFP80RegClass);
6780 }
6781 
6782 /// Return a virtual register initialized with the
6783 /// the global base register value. Output instructions required to
6784 /// initialize the register in the function entry block, if necessary.
6785 ///
6786 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6787 ///
6788 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
6789   assert((!Subtarget.is64Bit() ||
6790           MF->getTarget().getCodeModel() == CodeModel::Medium ||
6791           MF->getTarget().getCodeModel() == CodeModel::Large) &&
6792          "X86-64 PIC uses RIP relative addressing");
6793 
6794   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6795   Register GlobalBaseReg = X86FI->getGlobalBaseReg();
6796   if (GlobalBaseReg != 0)
6797     return GlobalBaseReg;
6798 
6799   // Create the register. The code to initialize it is inserted
6800   // later, by the CGBR pass (below).
6801   MachineRegisterInfo &RegInfo = MF->getRegInfo();
6802   GlobalBaseReg = RegInfo.createVirtualRegister(
6803       Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
6804   X86FI->setGlobalBaseReg(GlobalBaseReg);
6805   return GlobalBaseReg;
6806 }
6807 
6808 // These are the replaceable SSE instructions. Some of these have Int variants
6809 // that we don't include here. We don't want to replace instructions selected
6810 // by intrinsics.
6811 static const uint16_t ReplaceableInstrs[][3] = {
6812   //PackedSingle     PackedDouble    PackedInt
6813   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
6814   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
6815   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
6816   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
6817   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
6818   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
6819   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
6820   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
6821   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
6822   { X86::MOVSDrm_alt,X86::MOVSDrm_alt,X86::MOVQI2PQIrm },
6823   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
6824   { X86::MOVSSrm_alt,X86::MOVSSrm_alt,X86::MOVDI2PDIrm },
6825   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
6826   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
6827   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
6828   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
6829   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
6830   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
6831   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
6832   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
6833   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
6834   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
6835   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
6836   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
6837   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
6838   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
6839   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
6840   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
6841   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
6842   { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
6843   { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
6844   // AVX 128-bit support
6845   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
6846   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
6847   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
6848   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
6849   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
6850   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
6851   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
6852   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
6853   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
6854   { X86::VMOVSDrm_alt,X86::VMOVSDrm_alt,X86::VMOVQI2PQIrm },
6855   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
6856   { X86::VMOVSSrm_alt,X86::VMOVSSrm_alt,X86::VMOVDI2PDIrm },
6857   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6858   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
6859   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
6860   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
6861   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
6862   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
6863   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
6864   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
6865   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
6866   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
6867   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
6868   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
6869   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
6870   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
6871   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
6872   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
6873   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
6874   { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
6875   { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
6876   // AVX 256-bit support
6877   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
6878   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
6879   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
6880   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
6881   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
6882   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
6883   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
6884   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
6885   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
6886   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
6887   // AVX512 support
6888   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
6889   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
6890   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
6891   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
6892   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
6893   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
6894   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
6895   { X86::VMOVSDZrm_alt,  X86::VMOVSDZrm_alt,  X86::VMOVQI2PQIZrm  },
6896   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
6897   { X86::VMOVSSZrm_alt,  X86::VMOVSSZrm_alt,  X86::VMOVDI2PDIZrm  },
6898   { X86::VBROADCASTSSZ128rr,X86::VBROADCASTSSZ128rr,X86::VPBROADCASTDZ128rr },
6899   { X86::VBROADCASTSSZ128rm,X86::VBROADCASTSSZ128rm,X86::VPBROADCASTDZ128rm },
6900   { X86::VBROADCASTSSZ256rr,X86::VBROADCASTSSZ256rr,X86::VPBROADCASTDZ256rr },
6901   { X86::VBROADCASTSSZ256rm,X86::VBROADCASTSSZ256rm,X86::VPBROADCASTDZ256rm },
6902   { X86::VBROADCASTSSZrr,   X86::VBROADCASTSSZrr,   X86::VPBROADCASTDZrr },
6903   { X86::VBROADCASTSSZrm,   X86::VBROADCASTSSZrm,   X86::VPBROADCASTDZrm },
6904   { X86::VMOVDDUPZ128rr,    X86::VMOVDDUPZ128rr,    X86::VPBROADCASTQZ128rr },
6905   { X86::VMOVDDUPZ128rm,    X86::VMOVDDUPZ128rm,    X86::VPBROADCASTQZ128rm },
6906   { X86::VBROADCASTSDZ256rr,X86::VBROADCASTSDZ256rr,X86::VPBROADCASTQZ256rr },
6907   { X86::VBROADCASTSDZ256rm,X86::VBROADCASTSDZ256rm,X86::VPBROADCASTQZ256rm },
6908   { X86::VBROADCASTSDZrr,   X86::VBROADCASTSDZrr,   X86::VPBROADCASTQZrr },
6909   { X86::VBROADCASTSDZrm,   X86::VBROADCASTSDZrm,   X86::VPBROADCASTQZrm },
6910   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
6911   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
6912   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
6913   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
6914   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
6915   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
6916   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
6917   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
6918   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
6919   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
6920   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
6921   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
6922   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
6923   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
6924   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
6925   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
6926   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
6927   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
6928   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
6929   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
6930   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
6931   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
6932   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
6933   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
6934   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
6935   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
6936   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
6937   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
6938   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
6939   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
6940   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
6941   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
6942   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
6943   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
6944   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
6945   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
6946   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
6947   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
6948   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
6949   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
6950   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
6951   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
6952   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
6953   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
6954   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
6955   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
6956   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
6957   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
6958   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
6959   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
6960   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
6961   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
6962   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
6963   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
6964   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
6965   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
6966   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
6967   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
6968   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
6969   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
6970   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
6971   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
6972   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
6973   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
6974   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
6975   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
6976   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
6977   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
6978   { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
6979   { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
6980 };
6981 
6982 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6983   //PackedSingle       PackedDouble       PackedInt
6984   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
6985   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
6986   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
6987   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
6988   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
6989   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
6990   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
6991   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
6992   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
6993   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
6994   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6995   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6996   { X86::VMOVDDUPrm,     X86::VMOVDDUPrm,     X86::VPBROADCASTQrm},
6997   { X86::VMOVDDUPrr,     X86::VMOVDDUPrr,     X86::VPBROADCASTQrr},
6998   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6999   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7000   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7001   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
7002   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
7003   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
7004   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
7005   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
7006   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
7007   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
7008   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
7009   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
7010   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
7011   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
7012   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
7013   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
7014   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
7015 };
7016 
7017 static const uint16_t ReplaceableInstrsFP[][3] = {
7018   //PackedSingle         PackedDouble
7019   { X86::MOVLPSrm,       X86::MOVLPDrm,      X86::INSTRUCTION_LIST_END },
7020   { X86::MOVHPSrm,       X86::MOVHPDrm,      X86::INSTRUCTION_LIST_END },
7021   { X86::MOVHPSmr,       X86::MOVHPDmr,      X86::INSTRUCTION_LIST_END },
7022   { X86::VMOVLPSrm,      X86::VMOVLPDrm,     X86::INSTRUCTION_LIST_END },
7023   { X86::VMOVHPSrm,      X86::VMOVHPDrm,     X86::INSTRUCTION_LIST_END },
7024   { X86::VMOVHPSmr,      X86::VMOVHPDmr,     X86::INSTRUCTION_LIST_END },
7025   { X86::VMOVLPSZ128rm,  X86::VMOVLPDZ128rm, X86::INSTRUCTION_LIST_END },
7026   { X86::VMOVHPSZ128rm,  X86::VMOVHPDZ128rm, X86::INSTRUCTION_LIST_END },
7027   { X86::VMOVHPSZ128mr,  X86::VMOVHPDZ128mr, X86::INSTRUCTION_LIST_END },
7028 };
7029 
7030 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
7031   //PackedSingle       PackedDouble       PackedInt
7032   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
7033   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
7034   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
7035   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
7036 };
7037 
7038 static const uint16_t ReplaceableInstrsAVX512[][4] = {
7039   // Two integer columns for 64-bit and 32-bit elements.
7040   //PackedSingle        PackedDouble        PackedInt             PackedInt
7041   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
7042   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
7043   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
7044   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
7045   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
7046   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
7047   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
7048   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
7049   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
7050   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
7051   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
7052   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
7053   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
7054   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
7055   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
7056 };
7057 
7058 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
7059   // Two integer columns for 64-bit and 32-bit elements.
7060   //PackedSingle        PackedDouble        PackedInt           PackedInt
7061   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7062   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7063   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7064   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7065   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7066   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7067   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7068   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7069   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7070   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7071   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7072   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7073   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7074   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7075   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7076   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7077   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
7078   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
7079   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
7080   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
7081   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
7082   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
7083   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
7084   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
7085 };
7086 
7087 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
7088   // Two integer columns for 64-bit and 32-bit elements.
7089   //PackedSingle          PackedDouble
7090   //PackedInt             PackedInt
7091   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
7092     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
7093   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
7094     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
7095   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
7096     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
7097   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
7098     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
7099   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
7100     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
7101   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
7102     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
7103   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
7104     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
7105   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
7106     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
7107   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
7108     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
7109   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
7110     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
7111   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
7112     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
7113   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
7114     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
7115   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
7116     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
7117   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
7118     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
7119   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
7120     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
7121   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
7122     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
7123   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
7124     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
7125   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
7126     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
7127   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
7128     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
7129   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
7130     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
7131   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
7132     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
7133   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
7134     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
7135   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
7136     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
7137   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
7138     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
7139   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
7140     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
7141   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
7142     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
7143   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
7144     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
7145   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
7146     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
7147   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
7148     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
7149   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
7150     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
7151   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
7152     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
7153   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
7154     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
7155   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
7156     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
7157   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
7158     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
7159   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
7160     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
7161   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
7162     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
7163   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
7164     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
7165   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
7166     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
7167   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
7168     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
7169   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
7170     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
7171   { X86::VORPSZrmk,       X86::VORPDZrmk,
7172     X86::VPORQZrmk,       X86::VPORDZrmk       },
7173   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
7174     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
7175   { X86::VORPSZrrk,       X86::VORPDZrrk,
7176     X86::VPORQZrrk,       X86::VPORDZrrk       },
7177   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
7178     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
7179   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
7180     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
7181   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
7182     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
7183   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
7184     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
7185   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
7186     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
7187   // Broadcast loads can be handled the same as masked operations to avoid
7188   // changing element size.
7189   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
7190     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
7191   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
7192     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
7193   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
7194     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
7195   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
7196     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
7197   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
7198     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
7199   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
7200     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
7201   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
7202     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
7203   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
7204     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
7205   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
7206     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
7207   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7208     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7209   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
7210     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
7211   { X86::VORPSZrmb,       X86::VORPDZrmb,
7212     X86::VPORQZrmb,       X86::VPORDZrmb       },
7213   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
7214     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
7215   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
7216     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
7217   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
7218     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
7219   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
7220     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
7221   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
7222     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
7223   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
7224     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
7225   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
7226     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
7227   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
7228     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
7229   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
7230     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
7231   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
7232     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
7233   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7234     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7235   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
7236     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
7237   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
7238     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
7239   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
7240     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
7241   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
7242     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
7243   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
7244     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
7245   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
7246     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
7247   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
7248     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
7249   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
7250     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
7251   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
7252     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
7253   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
7254     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
7255   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
7256     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
7257   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
7258     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
7259   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7260     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7261   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
7262     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
7263   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
7264     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
7265   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
7266     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
7267 };
7268 
7269 // NOTE: These should only be used by the custom domain methods.
7270 static const uint16_t ReplaceableBlendInstrs[][3] = {
7271   //PackedSingle             PackedDouble             PackedInt
7272   { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
7273   { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
7274   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
7275   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
7276   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
7277   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
7278 };
7279 static const uint16_t ReplaceableBlendAVX2Instrs[][3] = {
7280   //PackedSingle             PackedDouble             PackedInt
7281   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
7282   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
7283   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
7284   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
7285 };
7286 
7287 // Special table for changing EVEX logic instructions to VEX.
7288 // TODO: Should we run EVEX->VEX earlier?
7289 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
7290   // Two integer columns for 64-bit and 32-bit elements.
7291   //PackedSingle     PackedDouble     PackedInt           PackedInt
7292   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
7293   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
7294   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
7295   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
7296   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORQZ128rm,   X86::VPORDZ128rm   },
7297   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORQZ128rr,   X86::VPORDZ128rr   },
7298   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
7299   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
7300   { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
7301   { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
7302   { X86::VANDPSYrm,  X86::VANDPDYrm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
7303   { X86::VANDPSYrr,  X86::VANDPDYrr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
7304   { X86::VORPSYrm,   X86::VORPDYrm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
7305   { X86::VORPSYrr,   X86::VORPDYrr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
7306   { X86::VXORPSYrm,  X86::VXORPDYrm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
7307   { X86::VXORPSYrr,  X86::VXORPDYrr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
7308 };
7309 
7310 // FIXME: Some shuffle and unpack instructions have equivalents in different
7311 // domains, but they require a bit more work than just switching opcodes.
7312 
7313 static const uint16_t *lookup(unsigned opcode, unsigned domain,
7314                               ArrayRef<uint16_t[3]> Table) {
7315   for (const uint16_t (&Row)[3] : Table)
7316     if (Row[domain-1] == opcode)
7317       return Row;
7318   return nullptr;
7319 }
7320 
7321 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
7322                                     ArrayRef<uint16_t[4]> Table) {
7323   // If this is the integer domain make sure to check both integer columns.
7324   for (const uint16_t (&Row)[4] : Table)
7325     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
7326       return Row;
7327   return nullptr;
7328 }
7329 
7330 // Helper to attempt to widen/narrow blend masks.
7331 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
7332                             unsigned NewWidth, unsigned *pNewMask = nullptr) {
7333   assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
7334          "Illegal blend mask scale");
7335   unsigned NewMask = 0;
7336 
7337   if ((OldWidth % NewWidth) == 0) {
7338     unsigned Scale = OldWidth / NewWidth;
7339     unsigned SubMask = (1u << Scale) - 1;
7340     for (unsigned i = 0; i != NewWidth; ++i) {
7341       unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
7342       if (Sub == SubMask)
7343         NewMask |= (1u << i);
7344       else if (Sub != 0x0)
7345         return false;
7346     }
7347   } else {
7348     unsigned Scale = NewWidth / OldWidth;
7349     unsigned SubMask = (1u << Scale) - 1;
7350     for (unsigned i = 0; i != OldWidth; ++i) {
7351       if (OldMask & (1 << i)) {
7352         NewMask |= (SubMask << (i * Scale));
7353       }
7354     }
7355   }
7356 
7357   if (pNewMask)
7358     *pNewMask = NewMask;
7359   return true;
7360 }
7361 
7362 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
7363   unsigned Opcode = MI.getOpcode();
7364   unsigned NumOperands = MI.getDesc().getNumOperands();
7365 
7366   auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
7367     uint16_t validDomains = 0;
7368     if (MI.getOperand(NumOperands - 1).isImm()) {
7369       unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
7370       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
7371         validDomains |= 0x2; // PackedSingle
7372       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
7373         validDomains |= 0x4; // PackedDouble
7374       if (!Is256 || Subtarget.hasAVX2())
7375         validDomains |= 0x8; // PackedInt
7376     }
7377     return validDomains;
7378   };
7379 
7380   switch (Opcode) {
7381   case X86::BLENDPDrmi:
7382   case X86::BLENDPDrri:
7383   case X86::VBLENDPDrmi:
7384   case X86::VBLENDPDrri:
7385     return GetBlendDomains(2, false);
7386   case X86::VBLENDPDYrmi:
7387   case X86::VBLENDPDYrri:
7388     return GetBlendDomains(4, true);
7389   case X86::BLENDPSrmi:
7390   case X86::BLENDPSrri:
7391   case X86::VBLENDPSrmi:
7392   case X86::VBLENDPSrri:
7393   case X86::VPBLENDDrmi:
7394   case X86::VPBLENDDrri:
7395     return GetBlendDomains(4, false);
7396   case X86::VBLENDPSYrmi:
7397   case X86::VBLENDPSYrri:
7398   case X86::VPBLENDDYrmi:
7399   case X86::VPBLENDDYrri:
7400     return GetBlendDomains(8, true);
7401   case X86::PBLENDWrmi:
7402   case X86::PBLENDWrri:
7403   case X86::VPBLENDWrmi:
7404   case X86::VPBLENDWrri:
7405   // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
7406   case X86::VPBLENDWYrmi:
7407   case X86::VPBLENDWYrri:
7408     return GetBlendDomains(8, false);
7409   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7410   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7411   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7412   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7413   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7414   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7415   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7416   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7417   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7418   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7419   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7420   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7421   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7422   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7423   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7424   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm:
7425     // If we don't have DQI see if we can still switch from an EVEX integer
7426     // instruction to a VEX floating point instruction.
7427     if (Subtarget.hasDQI())
7428       return 0;
7429 
7430     if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
7431       return 0;
7432     if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
7433       return 0;
7434     // Register forms will have 3 operands. Memory form will have more.
7435     if (NumOperands == 3 &&
7436         RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
7437       return 0;
7438 
7439     // All domains are valid.
7440     return 0xe;
7441   case X86::MOVHLPSrr:
7442     // We can swap domains when both inputs are the same register.
7443     // FIXME: This doesn't catch all the cases we would like. If the input
7444     // register isn't KILLed by the instruction, the two address instruction
7445     // pass puts a COPY on one input. The other input uses the original
7446     // register. This prevents the same physical register from being used by
7447     // both inputs.
7448     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7449         MI.getOperand(0).getSubReg() == 0 &&
7450         MI.getOperand(1).getSubReg() == 0 &&
7451         MI.getOperand(2).getSubReg() == 0)
7452       return 0x6;
7453     return 0;
7454   case X86::SHUFPDrri:
7455     return 0x6;
7456   }
7457   return 0;
7458 }
7459 
7460 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
7461                                             unsigned Domain) const {
7462   assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
7463   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7464   assert(dom && "Not an SSE instruction");
7465 
7466   unsigned Opcode = MI.getOpcode();
7467   unsigned NumOperands = MI.getDesc().getNumOperands();
7468 
7469   auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
7470     if (MI.getOperand(NumOperands - 1).isImm()) {
7471       unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
7472       Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
7473       unsigned NewImm = Imm;
7474 
7475       const uint16_t *table = lookup(Opcode, dom, ReplaceableBlendInstrs);
7476       if (!table)
7477         table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7478 
7479       if (Domain == 1) { // PackedSingle
7480         AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7481       } else if (Domain == 2) { // PackedDouble
7482         AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
7483       } else if (Domain == 3) { // PackedInt
7484         if (Subtarget.hasAVX2()) {
7485           // If we are already VPBLENDW use that, else use VPBLENDD.
7486           if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
7487             table = lookup(Opcode, dom, ReplaceableBlendAVX2Instrs);
7488             AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
7489           }
7490         } else {
7491           assert(!Is256 && "128-bit vector expected");
7492           AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
7493         }
7494       }
7495 
7496       assert(table && table[Domain - 1] && "Unknown domain op");
7497       MI.setDesc(get(table[Domain - 1]));
7498       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
7499     }
7500     return true;
7501   };
7502 
7503   switch (Opcode) {
7504   case X86::BLENDPDrmi:
7505   case X86::BLENDPDrri:
7506   case X86::VBLENDPDrmi:
7507   case X86::VBLENDPDrri:
7508     return SetBlendDomain(2, false);
7509   case X86::VBLENDPDYrmi:
7510   case X86::VBLENDPDYrri:
7511     return SetBlendDomain(4, true);
7512   case X86::BLENDPSrmi:
7513   case X86::BLENDPSrri:
7514   case X86::VBLENDPSrmi:
7515   case X86::VBLENDPSrri:
7516   case X86::VPBLENDDrmi:
7517   case X86::VPBLENDDrri:
7518     return SetBlendDomain(4, false);
7519   case X86::VBLENDPSYrmi:
7520   case X86::VBLENDPSYrri:
7521   case X86::VPBLENDDYrmi:
7522   case X86::VPBLENDDYrri:
7523     return SetBlendDomain(8, true);
7524   case X86::PBLENDWrmi:
7525   case X86::PBLENDWrri:
7526   case X86::VPBLENDWrmi:
7527   case X86::VPBLENDWrri:
7528     return SetBlendDomain(8, false);
7529   case X86::VPBLENDWYrmi:
7530   case X86::VPBLENDWYrri:
7531     return SetBlendDomain(16, true);
7532   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
7533   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
7534   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
7535   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
7536   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
7537   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
7538   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
7539   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
7540   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
7541   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
7542   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
7543   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
7544   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
7545   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
7546   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
7547   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm: {
7548     // Without DQI, convert EVEX instructions to VEX instructions.
7549     if (Subtarget.hasDQI())
7550       return false;
7551 
7552     const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
7553                                          ReplaceableCustomAVX512LogicInstrs);
7554     assert(table && "Instruction not found in table?");
7555     // Don't change integer Q instructions to D instructions and
7556     // use D intructions if we started with a PS instruction.
7557     if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7558       Domain = 4;
7559     MI.setDesc(get(table[Domain - 1]));
7560     return true;
7561   }
7562   case X86::UNPCKHPDrr:
7563   case X86::MOVHLPSrr:
7564     // We just need to commute the instruction which will switch the domains.
7565     if (Domain != dom && Domain != 3 &&
7566         MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7567         MI.getOperand(0).getSubReg() == 0 &&
7568         MI.getOperand(1).getSubReg() == 0 &&
7569         MI.getOperand(2).getSubReg() == 0) {
7570       commuteInstruction(MI, false);
7571       return true;
7572     }
7573     // We must always return true for MOVHLPSrr.
7574     if (Opcode == X86::MOVHLPSrr)
7575       return true;
7576     break;
7577   case X86::SHUFPDrri: {
7578     if (Domain == 1) {
7579       unsigned Imm = MI.getOperand(3).getImm();
7580       unsigned NewImm = 0x44;
7581       if (Imm & 1) NewImm |= 0x0a;
7582       if (Imm & 2) NewImm |= 0xa0;
7583       MI.getOperand(3).setImm(NewImm);
7584       MI.setDesc(get(X86::SHUFPSrri));
7585     }
7586     return true;
7587   }
7588   }
7589   return false;
7590 }
7591 
7592 std::pair<uint16_t, uint16_t>
7593 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7594   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7595   unsigned opcode = MI.getOpcode();
7596   uint16_t validDomains = 0;
7597   if (domain) {
7598     // Attempt to match for custom instructions.
7599     validDomains = getExecutionDomainCustom(MI);
7600     if (validDomains)
7601       return std::make_pair(domain, validDomains);
7602 
7603     if (lookup(opcode, domain, ReplaceableInstrs)) {
7604       validDomains = 0xe;
7605     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
7606       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
7607     } else if (lookup(opcode, domain, ReplaceableInstrsFP)) {
7608       validDomains = 0x6;
7609     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
7610       // Insert/extract instructions should only effect domain if AVX2
7611       // is enabled.
7612       if (!Subtarget.hasAVX2())
7613         return std::make_pair(0, 0);
7614       validDomains = 0xe;
7615     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
7616       validDomains = 0xe;
7617     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
7618                                                   ReplaceableInstrsAVX512DQ)) {
7619       validDomains = 0xe;
7620     } else if (Subtarget.hasDQI()) {
7621       if (const uint16_t *table = lookupAVX512(opcode, domain,
7622                                              ReplaceableInstrsAVX512DQMasked)) {
7623         if (domain == 1 || (domain == 3 && table[3] == opcode))
7624           validDomains = 0xa;
7625         else
7626           validDomains = 0xc;
7627       }
7628     }
7629   }
7630   return std::make_pair(domain, validDomains);
7631 }
7632 
7633 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
7634   assert(Domain>0 && Domain<4 && "Invalid execution domain");
7635   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7636   assert(dom && "Not an SSE instruction");
7637 
7638   // Attempt to match for custom instructions.
7639   if (setExecutionDomainCustom(MI, Domain))
7640     return;
7641 
7642   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
7643   if (!table) { // try the other table
7644     assert((Subtarget.hasAVX2() || Domain < 3) &&
7645            "256-bit vector operations only available in AVX2");
7646     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
7647   }
7648   if (!table) { // try the FP table
7649     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsFP);
7650     assert((!table || Domain < 3) &&
7651            "Can only select PackedSingle or PackedDouble");
7652   }
7653   if (!table) { // try the other table
7654     assert(Subtarget.hasAVX2() &&
7655            "256-bit insert/extract only available in AVX2");
7656     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
7657   }
7658   if (!table) { // try the AVX512 table
7659     assert(Subtarget.hasAVX512() && "Requires AVX-512");
7660     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
7661     // Don't change integer Q instructions to D instructions.
7662     if (table && Domain == 3 && table[3] == MI.getOpcode())
7663       Domain = 4;
7664   }
7665   if (!table) { // try the AVX512DQ table
7666     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7667     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
7668     // Don't change integer Q instructions to D instructions and
7669     // use D instructions if we started with a PS instruction.
7670     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7671       Domain = 4;
7672   }
7673   if (!table) { // try the AVX512DQMasked table
7674     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
7675     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
7676     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
7677       Domain = 4;
7678   }
7679   assert(table && "Cannot change domain");
7680   MI.setDesc(get(table[Domain - 1]));
7681 }
7682 
7683 /// Return the noop instruction to use for a noop.
7684 void X86InstrInfo::getNoop(MCInst &NopInst) const {
7685   NopInst.setOpcode(X86::NOOP);
7686 }
7687 
7688 bool X86InstrInfo::isHighLatencyDef(int opc) const {
7689   switch (opc) {
7690   default: return false;
7691   case X86::DIVPDrm:
7692   case X86::DIVPDrr:
7693   case X86::DIVPSrm:
7694   case X86::DIVPSrr:
7695   case X86::DIVSDrm:
7696   case X86::DIVSDrm_Int:
7697   case X86::DIVSDrr:
7698   case X86::DIVSDrr_Int:
7699   case X86::DIVSSrm:
7700   case X86::DIVSSrm_Int:
7701   case X86::DIVSSrr:
7702   case X86::DIVSSrr_Int:
7703   case X86::SQRTPDm:
7704   case X86::SQRTPDr:
7705   case X86::SQRTPSm:
7706   case X86::SQRTPSr:
7707   case X86::SQRTSDm:
7708   case X86::SQRTSDm_Int:
7709   case X86::SQRTSDr:
7710   case X86::SQRTSDr_Int:
7711   case X86::SQRTSSm:
7712   case X86::SQRTSSm_Int:
7713   case X86::SQRTSSr:
7714   case X86::SQRTSSr_Int:
7715   // AVX instructions with high latency
7716   case X86::VDIVPDrm:
7717   case X86::VDIVPDrr:
7718   case X86::VDIVPDYrm:
7719   case X86::VDIVPDYrr:
7720   case X86::VDIVPSrm:
7721   case X86::VDIVPSrr:
7722   case X86::VDIVPSYrm:
7723   case X86::VDIVPSYrr:
7724   case X86::VDIVSDrm:
7725   case X86::VDIVSDrm_Int:
7726   case X86::VDIVSDrr:
7727   case X86::VDIVSDrr_Int:
7728   case X86::VDIVSSrm:
7729   case X86::VDIVSSrm_Int:
7730   case X86::VDIVSSrr:
7731   case X86::VDIVSSrr_Int:
7732   case X86::VSQRTPDm:
7733   case X86::VSQRTPDr:
7734   case X86::VSQRTPDYm:
7735   case X86::VSQRTPDYr:
7736   case X86::VSQRTPSm:
7737   case X86::VSQRTPSr:
7738   case X86::VSQRTPSYm:
7739   case X86::VSQRTPSYr:
7740   case X86::VSQRTSDm:
7741   case X86::VSQRTSDm_Int:
7742   case X86::VSQRTSDr:
7743   case X86::VSQRTSDr_Int:
7744   case X86::VSQRTSSm:
7745   case X86::VSQRTSSm_Int:
7746   case X86::VSQRTSSr:
7747   case X86::VSQRTSSr_Int:
7748   // AVX512 instructions with high latency
7749   case X86::VDIVPDZ128rm:
7750   case X86::VDIVPDZ128rmb:
7751   case X86::VDIVPDZ128rmbk:
7752   case X86::VDIVPDZ128rmbkz:
7753   case X86::VDIVPDZ128rmk:
7754   case X86::VDIVPDZ128rmkz:
7755   case X86::VDIVPDZ128rr:
7756   case X86::VDIVPDZ128rrk:
7757   case X86::VDIVPDZ128rrkz:
7758   case X86::VDIVPDZ256rm:
7759   case X86::VDIVPDZ256rmb:
7760   case X86::VDIVPDZ256rmbk:
7761   case X86::VDIVPDZ256rmbkz:
7762   case X86::VDIVPDZ256rmk:
7763   case X86::VDIVPDZ256rmkz:
7764   case X86::VDIVPDZ256rr:
7765   case X86::VDIVPDZ256rrk:
7766   case X86::VDIVPDZ256rrkz:
7767   case X86::VDIVPDZrrb:
7768   case X86::VDIVPDZrrbk:
7769   case X86::VDIVPDZrrbkz:
7770   case X86::VDIVPDZrm:
7771   case X86::VDIVPDZrmb:
7772   case X86::VDIVPDZrmbk:
7773   case X86::VDIVPDZrmbkz:
7774   case X86::VDIVPDZrmk:
7775   case X86::VDIVPDZrmkz:
7776   case X86::VDIVPDZrr:
7777   case X86::VDIVPDZrrk:
7778   case X86::VDIVPDZrrkz:
7779   case X86::VDIVPSZ128rm:
7780   case X86::VDIVPSZ128rmb:
7781   case X86::VDIVPSZ128rmbk:
7782   case X86::VDIVPSZ128rmbkz:
7783   case X86::VDIVPSZ128rmk:
7784   case X86::VDIVPSZ128rmkz:
7785   case X86::VDIVPSZ128rr:
7786   case X86::VDIVPSZ128rrk:
7787   case X86::VDIVPSZ128rrkz:
7788   case X86::VDIVPSZ256rm:
7789   case X86::VDIVPSZ256rmb:
7790   case X86::VDIVPSZ256rmbk:
7791   case X86::VDIVPSZ256rmbkz:
7792   case X86::VDIVPSZ256rmk:
7793   case X86::VDIVPSZ256rmkz:
7794   case X86::VDIVPSZ256rr:
7795   case X86::VDIVPSZ256rrk:
7796   case X86::VDIVPSZ256rrkz:
7797   case X86::VDIVPSZrrb:
7798   case X86::VDIVPSZrrbk:
7799   case X86::VDIVPSZrrbkz:
7800   case X86::VDIVPSZrm:
7801   case X86::VDIVPSZrmb:
7802   case X86::VDIVPSZrmbk:
7803   case X86::VDIVPSZrmbkz:
7804   case X86::VDIVPSZrmk:
7805   case X86::VDIVPSZrmkz:
7806   case X86::VDIVPSZrr:
7807   case X86::VDIVPSZrrk:
7808   case X86::VDIVPSZrrkz:
7809   case X86::VDIVSDZrm:
7810   case X86::VDIVSDZrr:
7811   case X86::VDIVSDZrm_Int:
7812   case X86::VDIVSDZrm_Intk:
7813   case X86::VDIVSDZrm_Intkz:
7814   case X86::VDIVSDZrr_Int:
7815   case X86::VDIVSDZrr_Intk:
7816   case X86::VDIVSDZrr_Intkz:
7817   case X86::VDIVSDZrrb_Int:
7818   case X86::VDIVSDZrrb_Intk:
7819   case X86::VDIVSDZrrb_Intkz:
7820   case X86::VDIVSSZrm:
7821   case X86::VDIVSSZrr:
7822   case X86::VDIVSSZrm_Int:
7823   case X86::VDIVSSZrm_Intk:
7824   case X86::VDIVSSZrm_Intkz:
7825   case X86::VDIVSSZrr_Int:
7826   case X86::VDIVSSZrr_Intk:
7827   case X86::VDIVSSZrr_Intkz:
7828   case X86::VDIVSSZrrb_Int:
7829   case X86::VDIVSSZrrb_Intk:
7830   case X86::VDIVSSZrrb_Intkz:
7831   case X86::VSQRTPDZ128m:
7832   case X86::VSQRTPDZ128mb:
7833   case X86::VSQRTPDZ128mbk:
7834   case X86::VSQRTPDZ128mbkz:
7835   case X86::VSQRTPDZ128mk:
7836   case X86::VSQRTPDZ128mkz:
7837   case X86::VSQRTPDZ128r:
7838   case X86::VSQRTPDZ128rk:
7839   case X86::VSQRTPDZ128rkz:
7840   case X86::VSQRTPDZ256m:
7841   case X86::VSQRTPDZ256mb:
7842   case X86::VSQRTPDZ256mbk:
7843   case X86::VSQRTPDZ256mbkz:
7844   case X86::VSQRTPDZ256mk:
7845   case X86::VSQRTPDZ256mkz:
7846   case X86::VSQRTPDZ256r:
7847   case X86::VSQRTPDZ256rk:
7848   case X86::VSQRTPDZ256rkz:
7849   case X86::VSQRTPDZm:
7850   case X86::VSQRTPDZmb:
7851   case X86::VSQRTPDZmbk:
7852   case X86::VSQRTPDZmbkz:
7853   case X86::VSQRTPDZmk:
7854   case X86::VSQRTPDZmkz:
7855   case X86::VSQRTPDZr:
7856   case X86::VSQRTPDZrb:
7857   case X86::VSQRTPDZrbk:
7858   case X86::VSQRTPDZrbkz:
7859   case X86::VSQRTPDZrk:
7860   case X86::VSQRTPDZrkz:
7861   case X86::VSQRTPSZ128m:
7862   case X86::VSQRTPSZ128mb:
7863   case X86::VSQRTPSZ128mbk:
7864   case X86::VSQRTPSZ128mbkz:
7865   case X86::VSQRTPSZ128mk:
7866   case X86::VSQRTPSZ128mkz:
7867   case X86::VSQRTPSZ128r:
7868   case X86::VSQRTPSZ128rk:
7869   case X86::VSQRTPSZ128rkz:
7870   case X86::VSQRTPSZ256m:
7871   case X86::VSQRTPSZ256mb:
7872   case X86::VSQRTPSZ256mbk:
7873   case X86::VSQRTPSZ256mbkz:
7874   case X86::VSQRTPSZ256mk:
7875   case X86::VSQRTPSZ256mkz:
7876   case X86::VSQRTPSZ256r:
7877   case X86::VSQRTPSZ256rk:
7878   case X86::VSQRTPSZ256rkz:
7879   case X86::VSQRTPSZm:
7880   case X86::VSQRTPSZmb:
7881   case X86::VSQRTPSZmbk:
7882   case X86::VSQRTPSZmbkz:
7883   case X86::VSQRTPSZmk:
7884   case X86::VSQRTPSZmkz:
7885   case X86::VSQRTPSZr:
7886   case X86::VSQRTPSZrb:
7887   case X86::VSQRTPSZrbk:
7888   case X86::VSQRTPSZrbkz:
7889   case X86::VSQRTPSZrk:
7890   case X86::VSQRTPSZrkz:
7891   case X86::VSQRTSDZm:
7892   case X86::VSQRTSDZm_Int:
7893   case X86::VSQRTSDZm_Intk:
7894   case X86::VSQRTSDZm_Intkz:
7895   case X86::VSQRTSDZr:
7896   case X86::VSQRTSDZr_Int:
7897   case X86::VSQRTSDZr_Intk:
7898   case X86::VSQRTSDZr_Intkz:
7899   case X86::VSQRTSDZrb_Int:
7900   case X86::VSQRTSDZrb_Intk:
7901   case X86::VSQRTSDZrb_Intkz:
7902   case X86::VSQRTSSZm:
7903   case X86::VSQRTSSZm_Int:
7904   case X86::VSQRTSSZm_Intk:
7905   case X86::VSQRTSSZm_Intkz:
7906   case X86::VSQRTSSZr:
7907   case X86::VSQRTSSZr_Int:
7908   case X86::VSQRTSSZr_Intk:
7909   case X86::VSQRTSSZr_Intkz:
7910   case X86::VSQRTSSZrb_Int:
7911   case X86::VSQRTSSZrb_Intk:
7912   case X86::VSQRTSSZrb_Intkz:
7913 
7914   case X86::VGATHERDPDYrm:
7915   case X86::VGATHERDPDZ128rm:
7916   case X86::VGATHERDPDZ256rm:
7917   case X86::VGATHERDPDZrm:
7918   case X86::VGATHERDPDrm:
7919   case X86::VGATHERDPSYrm:
7920   case X86::VGATHERDPSZ128rm:
7921   case X86::VGATHERDPSZ256rm:
7922   case X86::VGATHERDPSZrm:
7923   case X86::VGATHERDPSrm:
7924   case X86::VGATHERPF0DPDm:
7925   case X86::VGATHERPF0DPSm:
7926   case X86::VGATHERPF0QPDm:
7927   case X86::VGATHERPF0QPSm:
7928   case X86::VGATHERPF1DPDm:
7929   case X86::VGATHERPF1DPSm:
7930   case X86::VGATHERPF1QPDm:
7931   case X86::VGATHERPF1QPSm:
7932   case X86::VGATHERQPDYrm:
7933   case X86::VGATHERQPDZ128rm:
7934   case X86::VGATHERQPDZ256rm:
7935   case X86::VGATHERQPDZrm:
7936   case X86::VGATHERQPDrm:
7937   case X86::VGATHERQPSYrm:
7938   case X86::VGATHERQPSZ128rm:
7939   case X86::VGATHERQPSZ256rm:
7940   case X86::VGATHERQPSZrm:
7941   case X86::VGATHERQPSrm:
7942   case X86::VPGATHERDDYrm:
7943   case X86::VPGATHERDDZ128rm:
7944   case X86::VPGATHERDDZ256rm:
7945   case X86::VPGATHERDDZrm:
7946   case X86::VPGATHERDDrm:
7947   case X86::VPGATHERDQYrm:
7948   case X86::VPGATHERDQZ128rm:
7949   case X86::VPGATHERDQZ256rm:
7950   case X86::VPGATHERDQZrm:
7951   case X86::VPGATHERDQrm:
7952   case X86::VPGATHERQDYrm:
7953   case X86::VPGATHERQDZ128rm:
7954   case X86::VPGATHERQDZ256rm:
7955   case X86::VPGATHERQDZrm:
7956   case X86::VPGATHERQDrm:
7957   case X86::VPGATHERQQYrm:
7958   case X86::VPGATHERQQZ128rm:
7959   case X86::VPGATHERQQZ256rm:
7960   case X86::VPGATHERQQZrm:
7961   case X86::VPGATHERQQrm:
7962   case X86::VSCATTERDPDZ128mr:
7963   case X86::VSCATTERDPDZ256mr:
7964   case X86::VSCATTERDPDZmr:
7965   case X86::VSCATTERDPSZ128mr:
7966   case X86::VSCATTERDPSZ256mr:
7967   case X86::VSCATTERDPSZmr:
7968   case X86::VSCATTERPF0DPDm:
7969   case X86::VSCATTERPF0DPSm:
7970   case X86::VSCATTERPF0QPDm:
7971   case X86::VSCATTERPF0QPSm:
7972   case X86::VSCATTERPF1DPDm:
7973   case X86::VSCATTERPF1DPSm:
7974   case X86::VSCATTERPF1QPDm:
7975   case X86::VSCATTERPF1QPSm:
7976   case X86::VSCATTERQPDZ128mr:
7977   case X86::VSCATTERQPDZ256mr:
7978   case X86::VSCATTERQPDZmr:
7979   case X86::VSCATTERQPSZ128mr:
7980   case X86::VSCATTERQPSZ256mr:
7981   case X86::VSCATTERQPSZmr:
7982   case X86::VPSCATTERDDZ128mr:
7983   case X86::VPSCATTERDDZ256mr:
7984   case X86::VPSCATTERDDZmr:
7985   case X86::VPSCATTERDQZ128mr:
7986   case X86::VPSCATTERDQZ256mr:
7987   case X86::VPSCATTERDQZmr:
7988   case X86::VPSCATTERQDZ128mr:
7989   case X86::VPSCATTERQDZ256mr:
7990   case X86::VPSCATTERQDZmr:
7991   case X86::VPSCATTERQQZ128mr:
7992   case X86::VPSCATTERQQZ256mr:
7993   case X86::VPSCATTERQQZmr:
7994     return true;
7995   }
7996 }
7997 
7998 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7999                                          const MachineRegisterInfo *MRI,
8000                                          const MachineInstr &DefMI,
8001                                          unsigned DefIdx,
8002                                          const MachineInstr &UseMI,
8003                                          unsigned UseIdx) const {
8004   return isHighLatencyDef(DefMI.getOpcode());
8005 }
8006 
8007 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
8008                                            const MachineBasicBlock *MBB) const {
8009   assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 &&
8010          Inst.getNumDefs() <= 2 && "Reassociation needs binary operators");
8011 
8012   // Integer binary math/logic instructions have a third source operand:
8013   // the EFLAGS register. That operand must be both defined here and never
8014   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
8015   // not change anything because rearranging the operands could affect other
8016   // instructions that depend on the exact status flags (zero, sign, etc.)
8017   // that are set by using these particular operands with this operation.
8018   const MachineOperand *FlagDef = Inst.findRegisterDefOperand(X86::EFLAGS);
8019   assert((Inst.getNumDefs() == 1 || FlagDef) &&
8020          "Implicit def isn't flags?");
8021   if (FlagDef && !FlagDef->isDead())
8022     return false;
8023 
8024   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
8025 }
8026 
8027 // TODO: There are many more machine instruction opcodes to match:
8028 //       1. Other data types (integer, vectors)
8029 //       2. Other math / logic operations (xor, or)
8030 //       3. Other forms of the same operation (intrinsics and other variants)
8031 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
8032   switch (Inst.getOpcode()) {
8033   case X86::AND8rr:
8034   case X86::AND16rr:
8035   case X86::AND32rr:
8036   case X86::AND64rr:
8037   case X86::OR8rr:
8038   case X86::OR16rr:
8039   case X86::OR32rr:
8040   case X86::OR64rr:
8041   case X86::XOR8rr:
8042   case X86::XOR16rr:
8043   case X86::XOR32rr:
8044   case X86::XOR64rr:
8045   case X86::IMUL16rr:
8046   case X86::IMUL32rr:
8047   case X86::IMUL64rr:
8048   case X86::PANDrr:
8049   case X86::PORrr:
8050   case X86::PXORrr:
8051   case X86::ANDPDrr:
8052   case X86::ANDPSrr:
8053   case X86::ORPDrr:
8054   case X86::ORPSrr:
8055   case X86::XORPDrr:
8056   case X86::XORPSrr:
8057   case X86::PADDBrr:
8058   case X86::PADDWrr:
8059   case X86::PADDDrr:
8060   case X86::PADDQrr:
8061   case X86::PMULLWrr:
8062   case X86::PMULLDrr:
8063   case X86::PMAXSBrr:
8064   case X86::PMAXSDrr:
8065   case X86::PMAXSWrr:
8066   case X86::PMAXUBrr:
8067   case X86::PMAXUDrr:
8068   case X86::PMAXUWrr:
8069   case X86::PMINSBrr:
8070   case X86::PMINSDrr:
8071   case X86::PMINSWrr:
8072   case X86::PMINUBrr:
8073   case X86::PMINUDrr:
8074   case X86::PMINUWrr:
8075   case X86::VPANDrr:
8076   case X86::VPANDYrr:
8077   case X86::VPANDDZ128rr:
8078   case X86::VPANDDZ256rr:
8079   case X86::VPANDDZrr:
8080   case X86::VPANDQZ128rr:
8081   case X86::VPANDQZ256rr:
8082   case X86::VPANDQZrr:
8083   case X86::VPORrr:
8084   case X86::VPORYrr:
8085   case X86::VPORDZ128rr:
8086   case X86::VPORDZ256rr:
8087   case X86::VPORDZrr:
8088   case X86::VPORQZ128rr:
8089   case X86::VPORQZ256rr:
8090   case X86::VPORQZrr:
8091   case X86::VPXORrr:
8092   case X86::VPXORYrr:
8093   case X86::VPXORDZ128rr:
8094   case X86::VPXORDZ256rr:
8095   case X86::VPXORDZrr:
8096   case X86::VPXORQZ128rr:
8097   case X86::VPXORQZ256rr:
8098   case X86::VPXORQZrr:
8099   case X86::VANDPDrr:
8100   case X86::VANDPSrr:
8101   case X86::VANDPDYrr:
8102   case X86::VANDPSYrr:
8103   case X86::VANDPDZ128rr:
8104   case X86::VANDPSZ128rr:
8105   case X86::VANDPDZ256rr:
8106   case X86::VANDPSZ256rr:
8107   case X86::VANDPDZrr:
8108   case X86::VANDPSZrr:
8109   case X86::VORPDrr:
8110   case X86::VORPSrr:
8111   case X86::VORPDYrr:
8112   case X86::VORPSYrr:
8113   case X86::VORPDZ128rr:
8114   case X86::VORPSZ128rr:
8115   case X86::VORPDZ256rr:
8116   case X86::VORPSZ256rr:
8117   case X86::VORPDZrr:
8118   case X86::VORPSZrr:
8119   case X86::VXORPDrr:
8120   case X86::VXORPSrr:
8121   case X86::VXORPDYrr:
8122   case X86::VXORPSYrr:
8123   case X86::VXORPDZ128rr:
8124   case X86::VXORPSZ128rr:
8125   case X86::VXORPDZ256rr:
8126   case X86::VXORPSZ256rr:
8127   case X86::VXORPDZrr:
8128   case X86::VXORPSZrr:
8129   case X86::KADDBrr:
8130   case X86::KADDWrr:
8131   case X86::KADDDrr:
8132   case X86::KADDQrr:
8133   case X86::KANDBrr:
8134   case X86::KANDWrr:
8135   case X86::KANDDrr:
8136   case X86::KANDQrr:
8137   case X86::KORBrr:
8138   case X86::KORWrr:
8139   case X86::KORDrr:
8140   case X86::KORQrr:
8141   case X86::KXORBrr:
8142   case X86::KXORWrr:
8143   case X86::KXORDrr:
8144   case X86::KXORQrr:
8145   case X86::VPADDBrr:
8146   case X86::VPADDWrr:
8147   case X86::VPADDDrr:
8148   case X86::VPADDQrr:
8149   case X86::VPADDBYrr:
8150   case X86::VPADDWYrr:
8151   case X86::VPADDDYrr:
8152   case X86::VPADDQYrr:
8153   case X86::VPADDBZ128rr:
8154   case X86::VPADDWZ128rr:
8155   case X86::VPADDDZ128rr:
8156   case X86::VPADDQZ128rr:
8157   case X86::VPADDBZ256rr:
8158   case X86::VPADDWZ256rr:
8159   case X86::VPADDDZ256rr:
8160   case X86::VPADDQZ256rr:
8161   case X86::VPADDBZrr:
8162   case X86::VPADDWZrr:
8163   case X86::VPADDDZrr:
8164   case X86::VPADDQZrr:
8165   case X86::VPMULLWrr:
8166   case X86::VPMULLWYrr:
8167   case X86::VPMULLWZ128rr:
8168   case X86::VPMULLWZ256rr:
8169   case X86::VPMULLWZrr:
8170   case X86::VPMULLDrr:
8171   case X86::VPMULLDYrr:
8172   case X86::VPMULLDZ128rr:
8173   case X86::VPMULLDZ256rr:
8174   case X86::VPMULLDZrr:
8175   case X86::VPMULLQZ128rr:
8176   case X86::VPMULLQZ256rr:
8177   case X86::VPMULLQZrr:
8178   case X86::VPMAXSBrr:
8179   case X86::VPMAXSBYrr:
8180   case X86::VPMAXSBZ128rr:
8181   case X86::VPMAXSBZ256rr:
8182   case X86::VPMAXSBZrr:
8183   case X86::VPMAXSDrr:
8184   case X86::VPMAXSDYrr:
8185   case X86::VPMAXSDZ128rr:
8186   case X86::VPMAXSDZ256rr:
8187   case X86::VPMAXSDZrr:
8188   case X86::VPMAXSQZ128rr:
8189   case X86::VPMAXSQZ256rr:
8190   case X86::VPMAXSQZrr:
8191   case X86::VPMAXSWrr:
8192   case X86::VPMAXSWYrr:
8193   case X86::VPMAXSWZ128rr:
8194   case X86::VPMAXSWZ256rr:
8195   case X86::VPMAXSWZrr:
8196   case X86::VPMAXUBrr:
8197   case X86::VPMAXUBYrr:
8198   case X86::VPMAXUBZ128rr:
8199   case X86::VPMAXUBZ256rr:
8200   case X86::VPMAXUBZrr:
8201   case X86::VPMAXUDrr:
8202   case X86::VPMAXUDYrr:
8203   case X86::VPMAXUDZ128rr:
8204   case X86::VPMAXUDZ256rr:
8205   case X86::VPMAXUDZrr:
8206   case X86::VPMAXUQZ128rr:
8207   case X86::VPMAXUQZ256rr:
8208   case X86::VPMAXUQZrr:
8209   case X86::VPMAXUWrr:
8210   case X86::VPMAXUWYrr:
8211   case X86::VPMAXUWZ128rr:
8212   case X86::VPMAXUWZ256rr:
8213   case X86::VPMAXUWZrr:
8214   case X86::VPMINSBrr:
8215   case X86::VPMINSBYrr:
8216   case X86::VPMINSBZ128rr:
8217   case X86::VPMINSBZ256rr:
8218   case X86::VPMINSBZrr:
8219   case X86::VPMINSDrr:
8220   case X86::VPMINSDYrr:
8221   case X86::VPMINSDZ128rr:
8222   case X86::VPMINSDZ256rr:
8223   case X86::VPMINSDZrr:
8224   case X86::VPMINSQZ128rr:
8225   case X86::VPMINSQZ256rr:
8226   case X86::VPMINSQZrr:
8227   case X86::VPMINSWrr:
8228   case X86::VPMINSWYrr:
8229   case X86::VPMINSWZ128rr:
8230   case X86::VPMINSWZ256rr:
8231   case X86::VPMINSWZrr:
8232   case X86::VPMINUBrr:
8233   case X86::VPMINUBYrr:
8234   case X86::VPMINUBZ128rr:
8235   case X86::VPMINUBZ256rr:
8236   case X86::VPMINUBZrr:
8237   case X86::VPMINUDrr:
8238   case X86::VPMINUDYrr:
8239   case X86::VPMINUDZ128rr:
8240   case X86::VPMINUDZ256rr:
8241   case X86::VPMINUDZrr:
8242   case X86::VPMINUQZ128rr:
8243   case X86::VPMINUQZ256rr:
8244   case X86::VPMINUQZrr:
8245   case X86::VPMINUWrr:
8246   case X86::VPMINUWYrr:
8247   case X86::VPMINUWZ128rr:
8248   case X86::VPMINUWZ256rr:
8249   case X86::VPMINUWZrr:
8250   // Normal min/max instructions are not commutative because of NaN and signed
8251   // zero semantics, but these are. Thus, there's no need to check for global
8252   // relaxed math; the instructions themselves have the properties we need.
8253   case X86::MAXCPDrr:
8254   case X86::MAXCPSrr:
8255   case X86::MAXCSDrr:
8256   case X86::MAXCSSrr:
8257   case X86::MINCPDrr:
8258   case X86::MINCPSrr:
8259   case X86::MINCSDrr:
8260   case X86::MINCSSrr:
8261   case X86::VMAXCPDrr:
8262   case X86::VMAXCPSrr:
8263   case X86::VMAXCPDYrr:
8264   case X86::VMAXCPSYrr:
8265   case X86::VMAXCPDZ128rr:
8266   case X86::VMAXCPSZ128rr:
8267   case X86::VMAXCPDZ256rr:
8268   case X86::VMAXCPSZ256rr:
8269   case X86::VMAXCPDZrr:
8270   case X86::VMAXCPSZrr:
8271   case X86::VMAXCSDrr:
8272   case X86::VMAXCSSrr:
8273   case X86::VMAXCSDZrr:
8274   case X86::VMAXCSSZrr:
8275   case X86::VMINCPDrr:
8276   case X86::VMINCPSrr:
8277   case X86::VMINCPDYrr:
8278   case X86::VMINCPSYrr:
8279   case X86::VMINCPDZ128rr:
8280   case X86::VMINCPSZ128rr:
8281   case X86::VMINCPDZ256rr:
8282   case X86::VMINCPSZ256rr:
8283   case X86::VMINCPDZrr:
8284   case X86::VMINCPSZrr:
8285   case X86::VMINCSDrr:
8286   case X86::VMINCSSrr:
8287   case X86::VMINCSDZrr:
8288   case X86::VMINCSSZrr:
8289     return true;
8290   case X86::ADDPDrr:
8291   case X86::ADDPSrr:
8292   case X86::ADDSDrr:
8293   case X86::ADDSSrr:
8294   case X86::MULPDrr:
8295   case X86::MULPSrr:
8296   case X86::MULSDrr:
8297   case X86::MULSSrr:
8298   case X86::VADDPDrr:
8299   case X86::VADDPSrr:
8300   case X86::VADDPDYrr:
8301   case X86::VADDPSYrr:
8302   case X86::VADDPDZ128rr:
8303   case X86::VADDPSZ128rr:
8304   case X86::VADDPDZ256rr:
8305   case X86::VADDPSZ256rr:
8306   case X86::VADDPDZrr:
8307   case X86::VADDPSZrr:
8308   case X86::VADDSDrr:
8309   case X86::VADDSSrr:
8310   case X86::VADDSDZrr:
8311   case X86::VADDSSZrr:
8312   case X86::VMULPDrr:
8313   case X86::VMULPSrr:
8314   case X86::VMULPDYrr:
8315   case X86::VMULPSYrr:
8316   case X86::VMULPDZ128rr:
8317   case X86::VMULPSZ128rr:
8318   case X86::VMULPDZ256rr:
8319   case X86::VMULPSZ256rr:
8320   case X86::VMULPDZrr:
8321   case X86::VMULPSZrr:
8322   case X86::VMULSDrr:
8323   case X86::VMULSSrr:
8324   case X86::VMULSDZrr:
8325   case X86::VMULSSZrr:
8326     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
8327            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
8328   default:
8329     return false;
8330   }
8331 }
8332 
8333 /// If \p DescribedReg overlaps with the MOVrr instruction's destination
8334 /// register then, if possible, describe the value in terms of the source
8335 /// register.
8336 static Optional<ParamLoadedValue>
8337 describeMOVrrLoadedValue(const MachineInstr &MI, Register DescribedReg,
8338                          const TargetRegisterInfo *TRI) {
8339   Register DestReg = MI.getOperand(0).getReg();
8340   Register SrcReg = MI.getOperand(1).getReg();
8341 
8342   auto Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8343 
8344   // If the described register is the destination, just return the source.
8345   if (DestReg == DescribedReg)
8346     return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8347 
8348   // If the described register is a sub-register of the destination register,
8349   // then pick out the source register's corresponding sub-register.
8350   if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) {
8351     Register SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx);
8352     return ParamLoadedValue(MachineOperand::CreateReg(SrcSubReg, false), Expr);
8353   }
8354 
8355   // The remaining case to consider is when the described register is a
8356   // super-register of the destination register. MOV8rr and MOV16rr does not
8357   // write to any of the other bytes in the register, meaning that we'd have to
8358   // describe the value using a combination of the source register and the
8359   // non-overlapping bits in the described register, which is not currently
8360   // possible.
8361   if (MI.getOpcode() == X86::MOV8rr || MI.getOpcode() == X86::MOV16rr ||
8362       !TRI->isSuperRegister(DestReg, DescribedReg))
8363     return None;
8364 
8365   assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case");
8366   return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
8367 }
8368 
8369 Optional<ParamLoadedValue>
8370 X86InstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const {
8371   const MachineOperand *Op = nullptr;
8372   DIExpression *Expr = nullptr;
8373 
8374   const TargetRegisterInfo *TRI = &getRegisterInfo();
8375 
8376   switch (MI.getOpcode()) {
8377   case X86::LEA32r:
8378   case X86::LEA64r:
8379   case X86::LEA64_32r: {
8380     // We may need to describe a 64-bit parameter with a 32-bit LEA.
8381     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8382       return None;
8383 
8384     // Operand 4 could be global address. For now we do not support
8385     // such situation.
8386     if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
8387       return None;
8388 
8389     const MachineOperand &Op1 = MI.getOperand(1);
8390     const MachineOperand &Op2 = MI.getOperand(3);
8391     assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
8392                            Register::isPhysicalRegister(Op2.getReg())));
8393 
8394     // Omit situations like:
8395     // %rsi = lea %rsi, 4, ...
8396     if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
8397         Op2.getReg() == MI.getOperand(0).getReg())
8398       return None;
8399     else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
8400               TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
8401              (Op2.getReg() != X86::NoRegister &&
8402               TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
8403       return None;
8404 
8405     int64_t Coef = MI.getOperand(2).getImm();
8406     int64_t Offset = MI.getOperand(4).getImm();
8407     SmallVector<uint64_t, 8> Ops;
8408 
8409     if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
8410       Op = &Op1;
8411     } else if (Op1.isFI())
8412       Op = &Op1;
8413 
8414     if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
8415       Ops.push_back(dwarf::DW_OP_constu);
8416       Ops.push_back(Coef + 1);
8417       Ops.push_back(dwarf::DW_OP_mul);
8418     } else {
8419       if (Op && Op2.getReg() != X86::NoRegister) {
8420         int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
8421         if (dwarfReg < 0)
8422           return None;
8423         else if (dwarfReg < 32) {
8424           Ops.push_back(dwarf::DW_OP_breg0 + dwarfReg);
8425           Ops.push_back(0);
8426         } else {
8427           Ops.push_back(dwarf::DW_OP_bregx);
8428           Ops.push_back(dwarfReg);
8429           Ops.push_back(0);
8430         }
8431       } else if (!Op) {
8432         assert(Op2.getReg() != X86::NoRegister);
8433         Op = &Op2;
8434       }
8435 
8436       if (Coef > 1) {
8437         assert(Op2.getReg() != X86::NoRegister);
8438         Ops.push_back(dwarf::DW_OP_constu);
8439         Ops.push_back(Coef);
8440         Ops.push_back(dwarf::DW_OP_mul);
8441       }
8442 
8443       if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
8444           Op2.getReg() != X86::NoRegister) {
8445         Ops.push_back(dwarf::DW_OP_plus);
8446       }
8447     }
8448 
8449     DIExpression::appendOffset(Ops, Offset);
8450     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops);
8451 
8452     return ParamLoadedValue(*Op, Expr);;
8453   }
8454   case X86::MOV8ri:
8455   case X86::MOV16ri:
8456     // TODO: Handle MOV8ri and MOV16ri.
8457     return None;
8458   case X86::MOV32ri:
8459   case X86::MOV64ri:
8460   case X86::MOV64ri32:
8461     // MOV32ri may be used for producing zero-extended 32-bit immediates in
8462     // 64-bit parameters, so we need to consider super-registers.
8463     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8464       return None;
8465     return ParamLoadedValue(MI.getOperand(1), Expr);
8466   case X86::MOV8rr:
8467   case X86::MOV16rr:
8468   case X86::MOV32rr:
8469   case X86::MOV64rr:
8470     return describeMOVrrLoadedValue(MI, Reg, TRI);
8471   case X86::XOR32rr: {
8472     // 64-bit parameters are zero-materialized using XOR32rr, so also consider
8473     // super-registers.
8474     if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg))
8475       return None;
8476     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
8477       return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
8478     return None;
8479   }
8480   case X86::MOVSX64rr32: {
8481     // We may need to describe the lower 32 bits of the MOVSX; for example, in
8482     // cases like this:
8483     //
8484     //  $ebx = [...]
8485     //  $rdi = MOVSX64rr32 $ebx
8486     //  $esi = MOV32rr $edi
8487     if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg))
8488       return None;
8489 
8490     Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
8491 
8492     // If the described register is the destination register we need to
8493     // sign-extend the source register from 32 bits. The other case we handle
8494     // is when the described register is the 32-bit sub-register of the
8495     // destination register, in case we just need to return the source
8496     // register.
8497     if (Reg == MI.getOperand(0).getReg())
8498       Expr = DIExpression::appendExt(Expr, 32, 64, true);
8499     else
8500       assert(X86MCRegisterClasses[X86::GR32RegClassID].contains(Reg) &&
8501              "Unhandled sub-register case for MOVSX64rr32");
8502 
8503     return ParamLoadedValue(MI.getOperand(1), Expr);
8504   }
8505   default:
8506     assert(!MI.isMoveImmediate() && "Unexpected MoveImm instruction");
8507     return TargetInstrInfo::describeLoadedValue(MI, Reg);
8508   }
8509 }
8510 
8511 /// This is an architecture-specific helper function of reassociateOps.
8512 /// Set special operand attributes for new instructions after reassociation.
8513 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
8514                                          MachineInstr &OldMI2,
8515                                          MachineInstr &NewMI1,
8516                                          MachineInstr &NewMI2) const {
8517   // Propagate FP flags from the original instructions.
8518   // But clear poison-generating flags because those may not be valid now.
8519   // TODO: There should be a helper function for copying only fast-math-flags.
8520   uint16_t IntersectedFlags = OldMI1.getFlags() & OldMI2.getFlags();
8521   NewMI1.setFlags(IntersectedFlags);
8522   NewMI1.clearFlag(MachineInstr::MIFlag::NoSWrap);
8523   NewMI1.clearFlag(MachineInstr::MIFlag::NoUWrap);
8524   NewMI1.clearFlag(MachineInstr::MIFlag::IsExact);
8525 
8526   NewMI2.setFlags(IntersectedFlags);
8527   NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
8528   NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
8529   NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
8530 
8531   // Integer instructions may define an implicit EFLAGS dest register operand.
8532   MachineOperand *OldFlagDef1 = OldMI1.findRegisterDefOperand(X86::EFLAGS);
8533   MachineOperand *OldFlagDef2 = OldMI2.findRegisterDefOperand(X86::EFLAGS);
8534 
8535   assert(!OldFlagDef1 == !OldFlagDef2 &&
8536          "Unexpected instruction type for reassociation");
8537 
8538   if (!OldFlagDef1 || !OldFlagDef2)
8539     return;
8540 
8541   assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() &&
8542          "Must have dead EFLAGS operand in reassociable instruction");
8543 
8544   MachineOperand *NewFlagDef1 = NewMI1.findRegisterDefOperand(X86::EFLAGS);
8545   MachineOperand *NewFlagDef2 = NewMI2.findRegisterDefOperand(X86::EFLAGS);
8546 
8547   assert(NewFlagDef1 && NewFlagDef2 &&
8548          "Unexpected operand in reassociable instruction");
8549 
8550   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
8551   // of this pass or other passes. The EFLAGS operands must be dead in these new
8552   // instructions because the EFLAGS operands in the original instructions must
8553   // be dead in order for reassociation to occur.
8554   NewFlagDef1->setIsDead();
8555   NewFlagDef2->setIsDead();
8556 }
8557 
8558 std::pair<unsigned, unsigned>
8559 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
8560   return std::make_pair(TF, 0u);
8561 }
8562 
8563 ArrayRef<std::pair<unsigned, const char *>>
8564 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
8565   using namespace X86II;
8566   static const std::pair<unsigned, const char *> TargetFlags[] = {
8567       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
8568       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
8569       {MO_GOT, "x86-got"},
8570       {MO_GOTOFF, "x86-gotoff"},
8571       {MO_GOTPCREL, "x86-gotpcrel"},
8572       {MO_PLT, "x86-plt"},
8573       {MO_TLSGD, "x86-tlsgd"},
8574       {MO_TLSLD, "x86-tlsld"},
8575       {MO_TLSLDM, "x86-tlsldm"},
8576       {MO_GOTTPOFF, "x86-gottpoff"},
8577       {MO_INDNTPOFF, "x86-indntpoff"},
8578       {MO_TPOFF, "x86-tpoff"},
8579       {MO_DTPOFF, "x86-dtpoff"},
8580       {MO_NTPOFF, "x86-ntpoff"},
8581       {MO_GOTNTPOFF, "x86-gotntpoff"},
8582       {MO_DLLIMPORT, "x86-dllimport"},
8583       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
8584       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
8585       {MO_TLVP, "x86-tlvp"},
8586       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
8587       {MO_SECREL, "x86-secrel"},
8588       {MO_COFFSTUB, "x86-coffstub"}};
8589   return makeArrayRef(TargetFlags);
8590 }
8591 
8592 namespace {
8593   /// Create Global Base Reg pass. This initializes the PIC
8594   /// global base register for x86-32.
8595   struct CGBR : public MachineFunctionPass {
8596     static char ID;
8597     CGBR() : MachineFunctionPass(ID) {}
8598 
8599     bool runOnMachineFunction(MachineFunction &MF) override {
8600       const X86TargetMachine *TM =
8601         static_cast<const X86TargetMachine *>(&MF.getTarget());
8602       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
8603 
8604       // Don't do anything in the 64-bit small and kernel code models. They use
8605       // RIP-relative addressing for everything.
8606       if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
8607                             TM->getCodeModel() == CodeModel::Kernel))
8608         return false;
8609 
8610       // Only emit a global base reg in PIC mode.
8611       if (!TM->isPositionIndependent())
8612         return false;
8613 
8614       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8615       Register GlobalBaseReg = X86FI->getGlobalBaseReg();
8616 
8617       // If we didn't need a GlobalBaseReg, don't insert code.
8618       if (GlobalBaseReg == 0)
8619         return false;
8620 
8621       // Insert the set of GlobalBaseReg into the first MBB of the function
8622       MachineBasicBlock &FirstMBB = MF.front();
8623       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
8624       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
8625       MachineRegisterInfo &RegInfo = MF.getRegInfo();
8626       const X86InstrInfo *TII = STI.getInstrInfo();
8627 
8628       Register PC;
8629       if (STI.isPICStyleGOT())
8630         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
8631       else
8632         PC = GlobalBaseReg;
8633 
8634       if (STI.is64Bit()) {
8635         if (TM->getCodeModel() == CodeModel::Medium) {
8636           // In the medium code model, use a RIP-relative LEA to materialize the
8637           // GOT.
8638           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
8639               .addReg(X86::RIP)
8640               .addImm(0)
8641               .addReg(0)
8642               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
8643               .addReg(0);
8644         } else if (TM->getCodeModel() == CodeModel::Large) {
8645           // In the large code model, we are aiming for this code, though the
8646           // register allocation may vary:
8647           //   leaq .LN$pb(%rip), %rax
8648           //   movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
8649           //   addq %rcx, %rax
8650           // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
8651           Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8652           Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
8653           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
8654               .addReg(X86::RIP)
8655               .addImm(0)
8656               .addReg(0)
8657               .addSym(MF.getPICBaseSymbol())
8658               .addReg(0);
8659           std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
8660           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
8661               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8662                                  X86II::MO_PIC_BASE_OFFSET);
8663           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
8664               .addReg(PBReg, RegState::Kill)
8665               .addReg(GOTReg, RegState::Kill);
8666         } else {
8667           llvm_unreachable("unexpected code model");
8668         }
8669       } else {
8670         // Operand of MovePCtoStack is completely ignored by asm printer. It's
8671         // only used in JIT code emission as displacement to pc.
8672         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
8673 
8674         // If we're using vanilla 'GOT' PIC style, we should use relative
8675         // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
8676         if (STI.isPICStyleGOT()) {
8677           // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
8678           // %some_register
8679           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
8680               .addReg(PC)
8681               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
8682                                  X86II::MO_GOT_ABSOLUTE_ADDRESS);
8683         }
8684       }
8685 
8686       return true;
8687     }
8688 
8689     StringRef getPassName() const override {
8690       return "X86 PIC Global Base Reg Initialization";
8691     }
8692 
8693     void getAnalysisUsage(AnalysisUsage &AU) const override {
8694       AU.setPreservesCFG();
8695       MachineFunctionPass::getAnalysisUsage(AU);
8696     }
8697   };
8698 } // namespace
8699 
8700 char CGBR::ID = 0;
8701 FunctionPass*
8702 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
8703 
8704 namespace {
8705   struct LDTLSCleanup : public MachineFunctionPass {
8706     static char ID;
8707     LDTLSCleanup() : MachineFunctionPass(ID) {}
8708 
8709     bool runOnMachineFunction(MachineFunction &MF) override {
8710       if (skipFunction(MF.getFunction()))
8711         return false;
8712 
8713       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
8714       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
8715         // No point folding accesses if there isn't at least two.
8716         return false;
8717       }
8718 
8719       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
8720       return VisitNode(DT->getRootNode(), 0);
8721     }
8722 
8723     // Visit the dominator subtree rooted at Node in pre-order.
8724     // If TLSBaseAddrReg is non-null, then use that to replace any
8725     // TLS_base_addr instructions. Otherwise, create the register
8726     // when the first such instruction is seen, and then use it
8727     // as we encounter more instructions.
8728     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
8729       MachineBasicBlock *BB = Node->getBlock();
8730       bool Changed = false;
8731 
8732       // Traverse the current block.
8733       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
8734            ++I) {
8735         switch (I->getOpcode()) {
8736           case X86::TLS_base_addr32:
8737           case X86::TLS_base_addr64:
8738             if (TLSBaseAddrReg)
8739               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
8740             else
8741               I = SetRegister(*I, &TLSBaseAddrReg);
8742             Changed = true;
8743             break;
8744           default:
8745             break;
8746         }
8747       }
8748 
8749       // Visit the children of this block in the dominator tree.
8750       for (auto I = Node->begin(), E = Node->end(); I != E; ++I) {
8751         Changed |= VisitNode(*I, TLSBaseAddrReg);
8752       }
8753 
8754       return Changed;
8755     }
8756 
8757     // Replace the TLS_base_addr instruction I with a copy from
8758     // TLSBaseAddrReg, returning the new instruction.
8759     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
8760                                          unsigned TLSBaseAddrReg) {
8761       MachineFunction *MF = I.getParent()->getParent();
8762       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8763       const bool is64Bit = STI.is64Bit();
8764       const X86InstrInfo *TII = STI.getInstrInfo();
8765 
8766       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
8767       MachineInstr *Copy =
8768           BuildMI(*I.getParent(), I, I.getDebugLoc(),
8769                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
8770               .addReg(TLSBaseAddrReg);
8771 
8772       // Erase the TLS_base_addr instruction.
8773       I.eraseFromParent();
8774 
8775       return Copy;
8776     }
8777 
8778     // Create a virtual register in *TLSBaseAddrReg, and populate it by
8779     // inserting a copy instruction after I. Returns the new instruction.
8780     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
8781       MachineFunction *MF = I.getParent()->getParent();
8782       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
8783       const bool is64Bit = STI.is64Bit();
8784       const X86InstrInfo *TII = STI.getInstrInfo();
8785 
8786       // Create a virtual register for the TLS base address.
8787       MachineRegisterInfo &RegInfo = MF->getRegInfo();
8788       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
8789                                                       ? &X86::GR64RegClass
8790                                                       : &X86::GR32RegClass);
8791 
8792       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
8793       MachineInstr *Next = I.getNextNode();
8794       MachineInstr *Copy =
8795           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
8796                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8797               .addReg(is64Bit ? X86::RAX : X86::EAX);
8798 
8799       return Copy;
8800     }
8801 
8802     StringRef getPassName() const override {
8803       return "Local Dynamic TLS Access Clean-up";
8804     }
8805 
8806     void getAnalysisUsage(AnalysisUsage &AU) const override {
8807       AU.setPreservesCFG();
8808       AU.addRequired<MachineDominatorTree>();
8809       MachineFunctionPass::getAnalysisUsage(AU);
8810     }
8811   };
8812 }
8813 
8814 char LDTLSCleanup::ID = 0;
8815 FunctionPass*
8816 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
8817 
8818 /// Constants defining how certain sequences should be outlined.
8819 ///
8820 /// \p MachineOutlinerDefault implies that the function is called with a call
8821 /// instruction, and a return must be emitted for the outlined function frame.
8822 ///
8823 /// That is,
8824 ///
8825 /// I1                                 OUTLINED_FUNCTION:
8826 /// I2 --> call OUTLINED_FUNCTION       I1
8827 /// I3                                  I2
8828 ///                                     I3
8829 ///                                     ret
8830 ///
8831 /// * Call construction overhead: 1 (call instruction)
8832 /// * Frame construction overhead: 1 (return instruction)
8833 ///
8834 /// \p MachineOutlinerTailCall implies that the function is being tail called.
8835 /// A jump is emitted instead of a call, and the return is already present in
8836 /// the outlined sequence. That is,
8837 ///
8838 /// I1                                 OUTLINED_FUNCTION:
8839 /// I2 --> jmp OUTLINED_FUNCTION       I1
8840 /// ret                                I2
8841 ///                                    ret
8842 ///
8843 /// * Call construction overhead: 1 (jump instruction)
8844 /// * Frame construction overhead: 0 (don't need to return)
8845 ///
8846 enum MachineOutlinerClass {
8847   MachineOutlinerDefault,
8848   MachineOutlinerTailCall
8849 };
8850 
8851 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
8852     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
8853   unsigned SequenceSize =
8854       std::accumulate(RepeatedSequenceLocs[0].front(),
8855                       std::next(RepeatedSequenceLocs[0].back()), 0,
8856                       [](unsigned Sum, const MachineInstr &MI) {
8857                         // FIXME: x86 doesn't implement getInstSizeInBytes, so
8858                         // we can't tell the cost.  Just assume each instruction
8859                         // is one byte.
8860                         if (MI.isDebugInstr() || MI.isKill())
8861                           return Sum;
8862                         return Sum + 1;
8863                       });
8864 
8865   // We check to see if CFI Instructions are present, and if they are
8866   // we find the number of CFI Instructions in the candidates.
8867   unsigned CFICount = 0;
8868   MachineBasicBlock::iterator MBBI = RepeatedSequenceLocs[0].front();
8869   for (unsigned Loc = RepeatedSequenceLocs[0].getStartIdx();
8870        Loc < RepeatedSequenceLocs[0].getEndIdx() + 1; Loc++) {
8871     const std::vector<MCCFIInstruction> &CFIInstructions =
8872         RepeatedSequenceLocs[0].getMF()->getFrameInstructions();
8873     if (MBBI->isCFIInstruction()) {
8874       unsigned CFIIndex = MBBI->getOperand(0).getCFIIndex();
8875       MCCFIInstruction CFI = CFIInstructions[CFIIndex];
8876       CFICount++;
8877     }
8878     MBBI++;
8879   }
8880 
8881   // We compare the number of found CFI Instructions to  the number of CFI
8882   // instructions in the parent function for each candidate.  We must check this
8883   // since if we outline one of the CFI instructions in a function, we have to
8884   // outline them all for correctness. If we do not, the address offsets will be
8885   // incorrect between the two sections of the program.
8886   for (outliner::Candidate &C : RepeatedSequenceLocs) {
8887     std::vector<MCCFIInstruction> CFIInstructions =
8888         C.getMF()->getFrameInstructions();
8889 
8890     if (CFICount > 0 && CFICount != CFIInstructions.size())
8891       return outliner::OutlinedFunction();
8892   }
8893 
8894   // FIXME: Use real size in bytes for call and ret instructions.
8895   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
8896     for (outliner::Candidate &C : RepeatedSequenceLocs)
8897       C.setCallInfo(MachineOutlinerTailCall, 1);
8898 
8899     return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
8900                                       0, // Number of bytes to emit frame.
8901                                       MachineOutlinerTailCall // Type of frame.
8902     );
8903   }
8904 
8905   if (CFICount > 0)
8906     return outliner::OutlinedFunction();
8907 
8908   for (outliner::Candidate &C : RepeatedSequenceLocs)
8909     C.setCallInfo(MachineOutlinerDefault, 1);
8910 
8911   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
8912                                     MachineOutlinerDefault);
8913 }
8914 
8915 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
8916                                            bool OutlineFromLinkOnceODRs) const {
8917   const Function &F = MF.getFunction();
8918 
8919   // Does the function use a red zone? If it does, then we can't risk messing
8920   // with the stack.
8921   if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) {
8922     // It could have a red zone. If it does, then we don't want to touch it.
8923     const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
8924     if (!X86FI || X86FI->getUsesRedZone())
8925       return false;
8926   }
8927 
8928   // If we *don't* want to outline from things that could potentially be deduped
8929   // then return false.
8930   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
8931       return false;
8932 
8933   // This function is viable for outlining, so return true.
8934   return true;
8935 }
8936 
8937 outliner::InstrType
8938 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  unsigned Flags) const {
8939   MachineInstr &MI = *MIT;
8940   // Don't allow debug values to impact outlining type.
8941   if (MI.isDebugInstr() || MI.isIndirectDebugValue())
8942     return outliner::InstrType::Invisible;
8943 
8944   // At this point, KILL instructions don't really tell us much so we can go
8945   // ahead and skip over them.
8946   if (MI.isKill())
8947     return outliner::InstrType::Invisible;
8948 
8949   // Is this a tail call? If yes, we can outline as a tail call.
8950   if (isTailCall(MI))
8951     return outliner::InstrType::Legal;
8952 
8953   // Is this the terminator of a basic block?
8954   if (MI.isTerminator() || MI.isReturn()) {
8955 
8956     // Does its parent have any successors in its MachineFunction?
8957     if (MI.getParent()->succ_empty())
8958       return outliner::InstrType::Legal;
8959 
8960     // It does, so we can't tail call it.
8961     return outliner::InstrType::Illegal;
8962   }
8963 
8964   // Don't outline anything that modifies or reads from the stack pointer.
8965   //
8966   // FIXME: There are instructions which are being manually built without
8967   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
8968   // able to remove the extra checks once those are fixed up. For example,
8969   // sometimes we might get something like %rax = POP64r 1. This won't be
8970   // caught by modifiesRegister or readsRegister even though the instruction
8971   // really ought to be formed so that modifiesRegister/readsRegister would
8972   // catch it.
8973   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
8974       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
8975       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
8976     return outliner::InstrType::Illegal;
8977 
8978   // Outlined calls change the instruction pointer, so don't read from it.
8979   if (MI.readsRegister(X86::RIP, &RI) ||
8980       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
8981       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
8982     return outliner::InstrType::Illegal;
8983 
8984   // Positions can't safely be outlined.
8985   if (MI.isPosition())
8986     return outliner::InstrType::Illegal;
8987 
8988   // Make sure none of the operands of this instruction do anything tricky.
8989   for (const MachineOperand &MOP : MI.operands())
8990     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
8991         MOP.isTargetIndex())
8992       return outliner::InstrType::Illegal;
8993 
8994   return outliner::InstrType::Legal;
8995 }
8996 
8997 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
8998                                           MachineFunction &MF,
8999                                           const outliner::OutlinedFunction &OF)
9000                                           const {
9001   // If we're a tail call, we already have a return, so don't do anything.
9002   if (OF.FrameConstructionID == MachineOutlinerTailCall)
9003     return;
9004 
9005   // We're a normal call, so our sequence doesn't have a return instruction.
9006   // Add it in.
9007   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
9008   MBB.insert(MBB.end(), retq);
9009 }
9010 
9011 MachineBasicBlock::iterator
9012 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
9013                                  MachineBasicBlock::iterator &It,
9014                                  MachineFunction &MF,
9015                                  const outliner::Candidate &C) const {
9016   // Is it a tail call?
9017   if (C.CallConstructionID == MachineOutlinerTailCall) {
9018     // Yes, just insert a JMP.
9019     It = MBB.insert(It,
9020                   BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
9021                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9022   } else {
9023     // No, insert a call.
9024     It = MBB.insert(It,
9025                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
9026                       .addGlobalAddress(M.getNamedValue(MF.getName())));
9027   }
9028 
9029   return It;
9030 }
9031 
9032 #define GET_INSTRINFO_HELPERS
9033 #include "X86GenInstrInfo.inc"
9034