1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86InstrInfo.h"
14 #include "X86.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrFoldTables.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Sequence.h"
22 #include "llvm/CodeGen/LivePhysRegs.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/LLVMContext.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "x86-instr-info"
46 
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "X86GenInstrInfo.inc"
49 
50 static cl::opt<bool>
51     NoFusing("disable-spill-fusing",
52              cl::desc("Disable fusing of spill code into instructions"),
53              cl::Hidden);
54 static cl::opt<bool>
55 PrintFailedFusing("print-failed-fuse-candidates",
56                   cl::desc("Print instructions that the allocator wants to"
57                            " fuse, but the X86 backend currently can't"),
58                   cl::Hidden);
59 static cl::opt<bool>
60 ReMatPICStubLoad("remat-pic-stub-load",
61                  cl::desc("Re-materialize load from stub in PIC mode"),
62                  cl::init(false), cl::Hidden);
63 static cl::opt<unsigned>
64 PartialRegUpdateClearance("partial-reg-update-clearance",
65                           cl::desc("Clearance between two register writes "
66                                    "for inserting XOR to avoid partial "
67                                    "register update"),
68                           cl::init(64), cl::Hidden);
69 static cl::opt<unsigned>
70 UndefRegClearance("undef-reg-clearance",
71                   cl::desc("How many idle instructions we would like before "
72                            "certain undef register reads"),
73                   cl::init(128), cl::Hidden);
74 
75 
76 // Pin the vtable to this file.
77 void X86InstrInfo::anchor() {}
78 
79 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
80     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81                                                : X86::ADJCALLSTACKDOWN32),
82                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83                                                : X86::ADJCALLSTACKUP32),
84                       X86::CATCHRET,
85                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
86       Subtarget(STI), RI(STI.getTargetTriple()) {
87 }
88 
89 bool
90 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
91                                     unsigned &SrcReg, unsigned &DstReg,
92                                     unsigned &SubIdx) const {
93   switch (MI.getOpcode()) {
94   default: break;
95   case X86::MOVSX16rr8:
96   case X86::MOVZX16rr8:
97   case X86::MOVSX32rr8:
98   case X86::MOVZX32rr8:
99   case X86::MOVSX64rr8:
100     if (!Subtarget.is64Bit())
101       // It's not always legal to reference the low 8-bit of the larger
102       // register in 32-bit mode.
103       return false;
104     LLVM_FALLTHROUGH;
105   case X86::MOVSX32rr16:
106   case X86::MOVZX32rr16:
107   case X86::MOVSX64rr16:
108   case X86::MOVSX64rr32: {
109     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
110       // Be conservative.
111       return false;
112     SrcReg = MI.getOperand(1).getReg();
113     DstReg = MI.getOperand(0).getReg();
114     switch (MI.getOpcode()) {
115     default: llvm_unreachable("Unreachable!");
116     case X86::MOVSX16rr8:
117     case X86::MOVZX16rr8:
118     case X86::MOVSX32rr8:
119     case X86::MOVZX32rr8:
120     case X86::MOVSX64rr8:
121       SubIdx = X86::sub_8bit;
122       break;
123     case X86::MOVSX32rr16:
124     case X86::MOVZX32rr16:
125     case X86::MOVSX64rr16:
126       SubIdx = X86::sub_16bit;
127       break;
128     case X86::MOVSX64rr32:
129       SubIdx = X86::sub_32bit;
130       break;
131     }
132     return true;
133   }
134   }
135   return false;
136 }
137 
138 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
139   const MachineFunction *MF = MI.getParent()->getParent();
140   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
141 
142   if (isFrameInstr(MI)) {
143     unsigned StackAlign = TFI->getStackAlignment();
144     int SPAdj = alignTo(getFrameSize(MI), StackAlign);
145     SPAdj -= getFrameAdjustment(MI);
146     if (!isFrameSetup(MI))
147       SPAdj = -SPAdj;
148     return SPAdj;
149   }
150 
151   // To know whether a call adjusts the stack, we need information
152   // that is bound to the following ADJCALLSTACKUP pseudo.
153   // Look for the next ADJCALLSTACKUP that follows the call.
154   if (MI.isCall()) {
155     const MachineBasicBlock *MBB = MI.getParent();
156     auto I = ++MachineBasicBlock::const_iterator(MI);
157     for (auto E = MBB->end(); I != E; ++I) {
158       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
159           I->isCall())
160         break;
161     }
162 
163     // If we could not find a frame destroy opcode, then it has already
164     // been simplified, so we don't care.
165     if (I->getOpcode() != getCallFrameDestroyOpcode())
166       return 0;
167 
168     return -(I->getOperand(1).getImm());
169   }
170 
171   // Currently handle only PUSHes we can reasonably expect to see
172   // in call sequences
173   switch (MI.getOpcode()) {
174   default:
175     return 0;
176   case X86::PUSH32i8:
177   case X86::PUSH32r:
178   case X86::PUSH32rmm:
179   case X86::PUSH32rmr:
180   case X86::PUSHi32:
181     return 4;
182   case X86::PUSH64i8:
183   case X86::PUSH64r:
184   case X86::PUSH64rmm:
185   case X86::PUSH64rmr:
186   case X86::PUSH64i32:
187     return 8;
188   }
189 }
190 
191 /// Return true and the FrameIndex if the specified
192 /// operand and follow operands form a reference to the stack frame.
193 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
194                                   int &FrameIndex) const {
195   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
196       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
197       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
198       MI.getOperand(Op + X86::AddrDisp).isImm() &&
199       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
200       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
201       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
202     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
203     return true;
204   }
205   return false;
206 }
207 
208 static bool isFrameLoadOpcode(int Opcode, unsigned &MemBytes) {
209   switch (Opcode) {
210   default:
211     return false;
212   case X86::MOV8rm:
213   case X86::KMOVBkm:
214     MemBytes = 1;
215     return true;
216   case X86::MOV16rm:
217   case X86::KMOVWkm:
218     MemBytes = 2;
219     return true;
220   case X86::MOV32rm:
221   case X86::MOVSSrm:
222   case X86::VMOVSSZrm:
223   case X86::VMOVSSrm:
224   case X86::KMOVDkm:
225     MemBytes = 4;
226     return true;
227   case X86::MOV64rm:
228   case X86::LD_Fp64m:
229   case X86::MOVSDrm:
230   case X86::VMOVSDrm:
231   case X86::VMOVSDZrm:
232   case X86::MMX_MOVD64rm:
233   case X86::MMX_MOVQ64rm:
234   case X86::KMOVQkm:
235     MemBytes = 8;
236     return true;
237   case X86::MOVAPSrm:
238   case X86::MOVUPSrm:
239   case X86::MOVAPDrm:
240   case X86::MOVUPDrm:
241   case X86::MOVDQArm:
242   case X86::MOVDQUrm:
243   case X86::VMOVAPSrm:
244   case X86::VMOVUPSrm:
245   case X86::VMOVAPDrm:
246   case X86::VMOVUPDrm:
247   case X86::VMOVDQArm:
248   case X86::VMOVDQUrm:
249   case X86::VMOVAPSZ128rm:
250   case X86::VMOVUPSZ128rm:
251   case X86::VMOVAPSZ128rm_NOVLX:
252   case X86::VMOVUPSZ128rm_NOVLX:
253   case X86::VMOVAPDZ128rm:
254   case X86::VMOVUPDZ128rm:
255   case X86::VMOVDQU8Z128rm:
256   case X86::VMOVDQU16Z128rm:
257   case X86::VMOVDQA32Z128rm:
258   case X86::VMOVDQU32Z128rm:
259   case X86::VMOVDQA64Z128rm:
260   case X86::VMOVDQU64Z128rm:
261     MemBytes = 16;
262     return true;
263   case X86::VMOVAPSYrm:
264   case X86::VMOVUPSYrm:
265   case X86::VMOVAPDYrm:
266   case X86::VMOVUPDYrm:
267   case X86::VMOVDQAYrm:
268   case X86::VMOVDQUYrm:
269   case X86::VMOVAPSZ256rm:
270   case X86::VMOVUPSZ256rm:
271   case X86::VMOVAPSZ256rm_NOVLX:
272   case X86::VMOVUPSZ256rm_NOVLX:
273   case X86::VMOVAPDZ256rm:
274   case X86::VMOVUPDZ256rm:
275   case X86::VMOVDQU8Z256rm:
276   case X86::VMOVDQU16Z256rm:
277   case X86::VMOVDQA32Z256rm:
278   case X86::VMOVDQU32Z256rm:
279   case X86::VMOVDQA64Z256rm:
280   case X86::VMOVDQU64Z256rm:
281     MemBytes = 32;
282     return true;
283   case X86::VMOVAPSZrm:
284   case X86::VMOVUPSZrm:
285   case X86::VMOVAPDZrm:
286   case X86::VMOVUPDZrm:
287   case X86::VMOVDQU8Zrm:
288   case X86::VMOVDQU16Zrm:
289   case X86::VMOVDQA32Zrm:
290   case X86::VMOVDQU32Zrm:
291   case X86::VMOVDQA64Zrm:
292   case X86::VMOVDQU64Zrm:
293     MemBytes = 64;
294     return true;
295   }
296 }
297 
298 static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) {
299   switch (Opcode) {
300   default:
301     return false;
302   case X86::MOV8mr:
303   case X86::KMOVBmk:
304     MemBytes = 1;
305     return true;
306   case X86::MOV16mr:
307   case X86::KMOVWmk:
308     MemBytes = 2;
309     return true;
310   case X86::MOV32mr:
311   case X86::MOVSSmr:
312   case X86::VMOVSSmr:
313   case X86::VMOVSSZmr:
314   case X86::KMOVDmk:
315     MemBytes = 4;
316     return true;
317   case X86::MOV64mr:
318   case X86::ST_FpP64m:
319   case X86::MOVSDmr:
320   case X86::VMOVSDmr:
321   case X86::VMOVSDZmr:
322   case X86::MMX_MOVD64mr:
323   case X86::MMX_MOVQ64mr:
324   case X86::MMX_MOVNTQmr:
325   case X86::KMOVQmk:
326     MemBytes = 8;
327     return true;
328   case X86::MOVAPSmr:
329   case X86::MOVUPSmr:
330   case X86::MOVAPDmr:
331   case X86::MOVUPDmr:
332   case X86::MOVDQAmr:
333   case X86::MOVDQUmr:
334   case X86::VMOVAPSmr:
335   case X86::VMOVUPSmr:
336   case X86::VMOVAPDmr:
337   case X86::VMOVUPDmr:
338   case X86::VMOVDQAmr:
339   case X86::VMOVDQUmr:
340   case X86::VMOVUPSZ128mr:
341   case X86::VMOVAPSZ128mr:
342   case X86::VMOVUPSZ128mr_NOVLX:
343   case X86::VMOVAPSZ128mr_NOVLX:
344   case X86::VMOVUPDZ128mr:
345   case X86::VMOVAPDZ128mr:
346   case X86::VMOVDQA32Z128mr:
347   case X86::VMOVDQU32Z128mr:
348   case X86::VMOVDQA64Z128mr:
349   case X86::VMOVDQU64Z128mr:
350   case X86::VMOVDQU8Z128mr:
351   case X86::VMOVDQU16Z128mr:
352     MemBytes = 16;
353     return true;
354   case X86::VMOVUPSYmr:
355   case X86::VMOVAPSYmr:
356   case X86::VMOVUPDYmr:
357   case X86::VMOVAPDYmr:
358   case X86::VMOVDQUYmr:
359   case X86::VMOVDQAYmr:
360   case X86::VMOVUPSZ256mr:
361   case X86::VMOVAPSZ256mr:
362   case X86::VMOVUPSZ256mr_NOVLX:
363   case X86::VMOVAPSZ256mr_NOVLX:
364   case X86::VMOVUPDZ256mr:
365   case X86::VMOVAPDZ256mr:
366   case X86::VMOVDQU8Z256mr:
367   case X86::VMOVDQU16Z256mr:
368   case X86::VMOVDQA32Z256mr:
369   case X86::VMOVDQU32Z256mr:
370   case X86::VMOVDQA64Z256mr:
371   case X86::VMOVDQU64Z256mr:
372     MemBytes = 32;
373     return true;
374   case X86::VMOVUPSZmr:
375   case X86::VMOVAPSZmr:
376   case X86::VMOVUPDZmr:
377   case X86::VMOVAPDZmr:
378   case X86::VMOVDQU8Zmr:
379   case X86::VMOVDQU16Zmr:
380   case X86::VMOVDQA32Zmr:
381   case X86::VMOVDQU32Zmr:
382   case X86::VMOVDQA64Zmr:
383   case X86::VMOVDQU64Zmr:
384     MemBytes = 64;
385     return true;
386   }
387   return false;
388 }
389 
390 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
391                                            int &FrameIndex) const {
392   unsigned Dummy;
393   return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy);
394 }
395 
396 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
397                                            int &FrameIndex,
398                                            unsigned &MemBytes) const {
399   if (isFrameLoadOpcode(MI.getOpcode(), MemBytes))
400     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
401       return MI.getOperand(0).getReg();
402   return 0;
403 }
404 
405 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
406                                                  int &FrameIndex) const {
407   unsigned Dummy;
408   if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) {
409     unsigned Reg;
410     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
411       return Reg;
412     // Check for post-frame index elimination operations
413     SmallVector<const MachineMemOperand *, 1> Accesses;
414     if (hasLoadFromStackSlot(MI, Accesses)) {
415       FrameIndex =
416           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
417               ->getFrameIndex();
418       return 1;
419     }
420   }
421   return 0;
422 }
423 
424 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
425                                           int &FrameIndex) const {
426   unsigned Dummy;
427   return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy);
428 }
429 
430 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
431                                           int &FrameIndex,
432                                           unsigned &MemBytes) const {
433   if (isFrameStoreOpcode(MI.getOpcode(), MemBytes))
434     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
435         isFrameOperand(MI, 0, FrameIndex))
436       return MI.getOperand(X86::AddrNumOperands).getReg();
437   return 0;
438 }
439 
440 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
441                                                 int &FrameIndex) const {
442   unsigned Dummy;
443   if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) {
444     unsigned Reg;
445     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
446       return Reg;
447     // Check for post-frame index elimination operations
448     SmallVector<const MachineMemOperand *, 1> Accesses;
449     if (hasStoreToStackSlot(MI, Accesses)) {
450       FrameIndex =
451           cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
452               ->getFrameIndex();
453       return 1;
454     }
455   }
456   return 0;
457 }
458 
459 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
460 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
461   // Don't waste compile time scanning use-def chains of physregs.
462   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
463     return false;
464   bool isPICBase = false;
465   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
466          E = MRI.def_instr_end(); I != E; ++I) {
467     MachineInstr *DefMI = &*I;
468     if (DefMI->getOpcode() != X86::MOVPC32r)
469       return false;
470     assert(!isPICBase && "More than one PIC base?");
471     isPICBase = true;
472   }
473   return isPICBase;
474 }
475 
476 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
477                                                      AliasAnalysis *AA) const {
478   switch (MI.getOpcode()) {
479   default: break;
480   case X86::MOV8rm:
481   case X86::MOV8rm_NOREX:
482   case X86::MOV16rm:
483   case X86::MOV32rm:
484   case X86::MOV64rm:
485   case X86::MOVSSrm:
486   case X86::MOVSDrm:
487   case X86::MOVAPSrm:
488   case X86::MOVUPSrm:
489   case X86::MOVAPDrm:
490   case X86::MOVUPDrm:
491   case X86::MOVDQArm:
492   case X86::MOVDQUrm:
493   case X86::VMOVSSrm:
494   case X86::VMOVSDrm:
495   case X86::VMOVAPSrm:
496   case X86::VMOVUPSrm:
497   case X86::VMOVAPDrm:
498   case X86::VMOVUPDrm:
499   case X86::VMOVDQArm:
500   case X86::VMOVDQUrm:
501   case X86::VMOVAPSYrm:
502   case X86::VMOVUPSYrm:
503   case X86::VMOVAPDYrm:
504   case X86::VMOVUPDYrm:
505   case X86::VMOVDQAYrm:
506   case X86::VMOVDQUYrm:
507   case X86::MMX_MOVD64rm:
508   case X86::MMX_MOVQ64rm:
509   // AVX-512
510   case X86::VMOVSSZrm:
511   case X86::VMOVSDZrm:
512   case X86::VMOVAPDZ128rm:
513   case X86::VMOVAPDZ256rm:
514   case X86::VMOVAPDZrm:
515   case X86::VMOVAPSZ128rm:
516   case X86::VMOVAPSZ256rm:
517   case X86::VMOVAPSZ128rm_NOVLX:
518   case X86::VMOVAPSZ256rm_NOVLX:
519   case X86::VMOVAPSZrm:
520   case X86::VMOVDQA32Z128rm:
521   case X86::VMOVDQA32Z256rm:
522   case X86::VMOVDQA32Zrm:
523   case X86::VMOVDQA64Z128rm:
524   case X86::VMOVDQA64Z256rm:
525   case X86::VMOVDQA64Zrm:
526   case X86::VMOVDQU16Z128rm:
527   case X86::VMOVDQU16Z256rm:
528   case X86::VMOVDQU16Zrm:
529   case X86::VMOVDQU32Z128rm:
530   case X86::VMOVDQU32Z256rm:
531   case X86::VMOVDQU32Zrm:
532   case X86::VMOVDQU64Z128rm:
533   case X86::VMOVDQU64Z256rm:
534   case X86::VMOVDQU64Zrm:
535   case X86::VMOVDQU8Z128rm:
536   case X86::VMOVDQU8Z256rm:
537   case X86::VMOVDQU8Zrm:
538   case X86::VMOVUPDZ128rm:
539   case X86::VMOVUPDZ256rm:
540   case X86::VMOVUPDZrm:
541   case X86::VMOVUPSZ128rm:
542   case X86::VMOVUPSZ256rm:
543   case X86::VMOVUPSZ128rm_NOVLX:
544   case X86::VMOVUPSZ256rm_NOVLX:
545   case X86::VMOVUPSZrm: {
546     // Loads from constant pools are trivially rematerializable.
547     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
548         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
549         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
550         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
551         MI.isDereferenceableInvariantLoad(AA)) {
552       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
553       if (BaseReg == 0 || BaseReg == X86::RIP)
554         return true;
555       // Allow re-materialization of PIC load.
556       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
557         return false;
558       const MachineFunction &MF = *MI.getParent()->getParent();
559       const MachineRegisterInfo &MRI = MF.getRegInfo();
560       return regIsPICBase(BaseReg, MRI);
561     }
562     return false;
563   }
564 
565   case X86::LEA32r:
566   case X86::LEA64r: {
567     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
568         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
569         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
570         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
571       // lea fi#, lea GV, etc. are all rematerializable.
572       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
573         return true;
574       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
575       if (BaseReg == 0)
576         return true;
577       // Allow re-materialization of lea PICBase + x.
578       const MachineFunction &MF = *MI.getParent()->getParent();
579       const MachineRegisterInfo &MRI = MF.getRegInfo();
580       return regIsPICBase(BaseReg, MRI);
581     }
582     return false;
583   }
584   }
585 
586   // All other instructions marked M_REMATERIALIZABLE are always trivially
587   // rematerializable.
588   return true;
589 }
590 
591 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
592                                  MachineBasicBlock::iterator I,
593                                  unsigned DestReg, unsigned SubIdx,
594                                  const MachineInstr &Orig,
595                                  const TargetRegisterInfo &TRI) const {
596   bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
597   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
598     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
599     // effects.
600     int Value;
601     switch (Orig.getOpcode()) {
602     case X86::MOV32r0:  Value = 0; break;
603     case X86::MOV32r1:  Value = 1; break;
604     case X86::MOV32r_1: Value = -1; break;
605     default:
606       llvm_unreachable("Unexpected instruction!");
607     }
608 
609     const DebugLoc &DL = Orig.getDebugLoc();
610     BuildMI(MBB, I, DL, get(X86::MOV32ri))
611         .add(Orig.getOperand(0))
612         .addImm(Value);
613   } else {
614     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
615     MBB.insert(I, MI);
616   }
617 
618   MachineInstr &NewMI = *std::prev(I);
619   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
620 }
621 
622 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
623 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
624   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
625     MachineOperand &MO = MI.getOperand(i);
626     if (MO.isReg() && MO.isDef() &&
627         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
628       return true;
629     }
630   }
631   return false;
632 }
633 
634 /// Check whether the shift count for a machine operand is non-zero.
635 inline static unsigned getTruncatedShiftCount(const MachineInstr &MI,
636                                               unsigned ShiftAmtOperandIdx) {
637   // The shift count is six bits with the REX.W prefix and five bits without.
638   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
639   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
640   return Imm & ShiftCountMask;
641 }
642 
643 /// Check whether the given shift count is appropriate
644 /// can be represented by a LEA instruction.
645 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
646   // Left shift instructions can be transformed into load-effective-address
647   // instructions if we can encode them appropriately.
648   // A LEA instruction utilizes a SIB byte to encode its scale factor.
649   // The SIB.scale field is two bits wide which means that we can encode any
650   // shift amount less than 4.
651   return ShAmt < 4 && ShAmt > 0;
652 }
653 
654 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
655                                   unsigned Opc, bool AllowSP, unsigned &NewSrc,
656                                   bool &isKill, MachineOperand &ImplicitOp,
657                                   LiveVariables *LV) const {
658   MachineFunction &MF = *MI.getParent()->getParent();
659   const TargetRegisterClass *RC;
660   if (AllowSP) {
661     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
662   } else {
663     RC = Opc != X86::LEA32r ?
664       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
665   }
666   unsigned SrcReg = Src.getReg();
667 
668   // For both LEA64 and LEA32 the register already has essentially the right
669   // type (32-bit or 64-bit) we may just need to forbid SP.
670   if (Opc != X86::LEA64_32r) {
671     NewSrc = SrcReg;
672     isKill = Src.isKill();
673     assert(!Src.isUndef() && "Undef op doesn't need optimization");
674 
675     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
676         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
677       return false;
678 
679     return true;
680   }
681 
682   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
683   // another we need to add 64-bit registers to the final MI.
684   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
685     ImplicitOp = Src;
686     ImplicitOp.setImplicit();
687 
688     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
689     isKill = Src.isKill();
690     assert(!Src.isUndef() && "Undef op doesn't need optimization");
691   } else {
692     // Virtual register of the wrong class, we have to create a temporary 64-bit
693     // vreg to feed into the LEA.
694     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
695     MachineInstr *Copy =
696         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
697             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
698             .add(Src);
699 
700     // Which is obviously going to be dead after we're done with it.
701     isKill = true;
702 
703     if (LV)
704       LV->replaceKillInstruction(SrcReg, MI, *Copy);
705   }
706 
707   // We've set all the parameters without issue.
708   return true;
709 }
710 
711 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
712     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
713     LiveVariables *LV, bool Is8BitOp) const {
714   // We handle 8-bit adds and various 16-bit opcodes in the switch below.
715   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
716   assert((Is8BitOp || RegInfo.getTargetRegisterInfo()->getRegSizeInBits(
717               *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
718          "Unexpected type for LEA transform");
719 
720   // TODO: For a 32-bit target, we need to adjust the LEA variables with
721   // something like this:
722   //   Opcode = X86::LEA32r;
723   //   InRegLEA = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
724   //   OutRegLEA =
725   //       Is8BitOp ? RegInfo.createVirtualRegister(&X86::GR32ABCD_RegClass)
726   //                : RegInfo.createVirtualRegister(&X86::GR32RegClass);
727   if (!Subtarget.is64Bit())
728     return nullptr;
729 
730   unsigned Opcode = X86::LEA64_32r;
731   unsigned InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
732   unsigned OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
733 
734   // Build and insert into an implicit UNDEF value. This is OK because
735   // we will be shifting and then extracting the lower 8/16-bits.
736   // This has the potential to cause partial register stall. e.g.
737   //   movw    (%rbp,%rcx,2), %dx
738   //   leal    -65(%rdx), %esi
739   // But testing has shown this *does* help performance in 64-bit mode (at
740   // least on modern x86 machines).
741   MachineBasicBlock::iterator MBBI = MI.getIterator();
742   unsigned Dest = MI.getOperand(0).getReg();
743   unsigned Src = MI.getOperand(1).getReg();
744   bool IsDead = MI.getOperand(0).isDead();
745   bool IsKill = MI.getOperand(1).isKill();
746   unsigned SubReg = Is8BitOp ? X86::sub_8bit : X86::sub_16bit;
747   assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
748   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
749   MachineInstr *InsMI =
750       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
751           .addReg(InRegLEA, RegState::Define, SubReg)
752           .addReg(Src, getKillRegState(IsKill));
753 
754   MachineInstrBuilder MIB =
755       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
756   switch (MIOpc) {
757   default: llvm_unreachable("Unreachable!");
758   case X86::SHL8ri:
759   case X86::SHL16ri: {
760     unsigned ShAmt = MI.getOperand(2).getImm();
761     MIB.addReg(0).addImm(1ULL << ShAmt)
762        .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
763     break;
764   }
765   case X86::INC8r:
766   case X86::INC16r:
767     addRegOffset(MIB, InRegLEA, true, 1);
768     break;
769   case X86::DEC8r:
770   case X86::DEC16r:
771     addRegOffset(MIB, InRegLEA, true, -1);
772     break;
773   case X86::ADD8ri:
774   case X86::ADD8ri_DB:
775   case X86::ADD16ri:
776   case X86::ADD16ri8:
777   case X86::ADD16ri_DB:
778   case X86::ADD16ri8_DB:
779     addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
780     break;
781   case X86::ADD8rr:
782   case X86::ADD8rr_DB:
783   case X86::ADD16rr:
784   case X86::ADD16rr_DB: {
785     unsigned Src2 = MI.getOperand(2).getReg();
786     bool IsKill2 = MI.getOperand(2).isKill();
787     assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
788     unsigned InRegLEA2 = 0;
789     MachineInstr *InsMI2 = nullptr;
790     if (Src == Src2) {
791       // ADD8rr/ADD16rr killed %reg1028, %reg1028
792       // just a single insert_subreg.
793       addRegReg(MIB, InRegLEA, true, InRegLEA, false);
794     } else {
795       if (Subtarget.is64Bit())
796         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
797       else
798         InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
799       // Build and insert into an implicit UNDEF value. This is OK because
800       // we will be shifting and then extracting the lower 8/16-bits.
801       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
802       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
803                    .addReg(InRegLEA2, RegState::Define, SubReg)
804                    .addReg(Src2, getKillRegState(IsKill2));
805       addRegReg(MIB, InRegLEA, true, InRegLEA2, true);
806     }
807     if (LV && IsKill2 && InsMI2)
808       LV->replaceKillInstruction(Src2, MI, *InsMI2);
809     break;
810   }
811   }
812 
813   MachineInstr *NewMI = MIB;
814   MachineInstr *ExtMI =
815       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
816           .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
817           .addReg(OutRegLEA, RegState::Kill, SubReg);
818 
819   if (LV) {
820     // Update live variables.
821     LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
822     LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
823     if (IsKill)
824       LV->replaceKillInstruction(Src, MI, *InsMI);
825     if (IsDead)
826       LV->replaceKillInstruction(Dest, MI, *ExtMI);
827   }
828 
829   return ExtMI;
830 }
831 
832 /// This method must be implemented by targets that
833 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
834 /// may be able to convert a two-address instruction into a true
835 /// three-address instruction on demand.  This allows the X86 target (for
836 /// example) to convert ADD and SHL instructions into LEA instructions if they
837 /// would require register copies due to two-addressness.
838 ///
839 /// This method returns a null pointer if the transformation cannot be
840 /// performed, otherwise it returns the new instruction.
841 ///
842 MachineInstr *
843 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
844                                     MachineInstr &MI, LiveVariables *LV) const {
845   // The following opcodes also sets the condition code register(s). Only
846   // convert them to equivalent lea if the condition code register def's
847   // are dead!
848   if (hasLiveCondCodeDef(MI))
849     return nullptr;
850 
851   MachineFunction &MF = *MI.getParent()->getParent();
852   // All instructions input are two-addr instructions.  Get the known operands.
853   const MachineOperand &Dest = MI.getOperand(0);
854   const MachineOperand &Src = MI.getOperand(1);
855 
856   // Ideally, operations with undef should be folded before we get here, but we
857   // can't guarantee it. Bail out because optimizing undefs is a waste of time.
858   // Without this, we have to forward undef state to new register operands to
859   // avoid machine verifier errors.
860   if (Src.isUndef())
861     return nullptr;
862   if (MI.getNumOperands() > 2)
863     if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
864       return nullptr;
865 
866   MachineInstr *NewMI = nullptr;
867   bool Is64Bit = Subtarget.is64Bit();
868 
869   bool Is8BitOp = false;
870   unsigned MIOpc = MI.getOpcode();
871   switch (MIOpc) {
872   default: llvm_unreachable("Unreachable!");
873   case X86::SHL64ri: {
874     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
875     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
876     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
877 
878     // LEA can't handle RSP.
879     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
880         !MF.getRegInfo().constrainRegClass(Src.getReg(),
881                                            &X86::GR64_NOSPRegClass))
882       return nullptr;
883 
884     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
885                 .add(Dest)
886                 .addReg(0)
887                 .addImm(1ULL << ShAmt)
888                 .add(Src)
889                 .addImm(0)
890                 .addReg(0);
891     break;
892   }
893   case X86::SHL32ri: {
894     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
895     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
896     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
897 
898     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
899 
900     // LEA can't handle ESP.
901     bool isKill;
902     unsigned SrcReg;
903     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
904     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
905                         SrcReg, isKill, ImplicitOp, LV))
906       return nullptr;
907 
908     MachineInstrBuilder MIB =
909         BuildMI(MF, MI.getDebugLoc(), get(Opc))
910             .add(Dest)
911             .addReg(0)
912             .addImm(1ULL << ShAmt)
913             .addReg(SrcReg, getKillRegState(isKill))
914             .addImm(0)
915             .addReg(0);
916     if (ImplicitOp.getReg() != 0)
917       MIB.add(ImplicitOp);
918     NewMI = MIB;
919 
920     break;
921   }
922   case X86::SHL8ri:
923     Is8BitOp = true;
924     LLVM_FALLTHROUGH;
925   case X86::SHL16ri: {
926     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
927     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
928     if (!isTruncatedShiftCountForLEA(ShAmt))
929       return nullptr;
930     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
931   }
932   case X86::INC64r:
933   case X86::INC32r: {
934     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
935     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r :
936         (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
937     bool isKill;
938     unsigned SrcReg;
939     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
940     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
941                         ImplicitOp, LV))
942       return nullptr;
943 
944     MachineInstrBuilder MIB =
945         BuildMI(MF, MI.getDebugLoc(), get(Opc))
946             .add(Dest)
947             .addReg(SrcReg, getKillRegState(isKill));
948     if (ImplicitOp.getReg() != 0)
949       MIB.add(ImplicitOp);
950 
951     NewMI = addOffset(MIB, 1);
952     break;
953   }
954   case X86::DEC64r:
955   case X86::DEC32r: {
956     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
957     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
958         : (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
959 
960     bool isKill;
961     unsigned SrcReg;
962     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
963     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill,
964                         ImplicitOp, LV))
965       return nullptr;
966 
967     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
968                                   .add(Dest)
969                                   .addReg(SrcReg, getKillRegState(isKill));
970     if (ImplicitOp.getReg() != 0)
971       MIB.add(ImplicitOp);
972 
973     NewMI = addOffset(MIB, -1);
974 
975     break;
976   }
977   case X86::DEC8r:
978   case X86::INC8r:
979     Is8BitOp = true;
980     LLVM_FALLTHROUGH;
981   case X86::DEC16r:
982   case X86::INC16r:
983     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
984   case X86::ADD64rr:
985   case X86::ADD64rr_DB:
986   case X86::ADD32rr:
987   case X86::ADD32rr_DB: {
988     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
989     unsigned Opc;
990     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
991       Opc = X86::LEA64r;
992     else
993       Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
994 
995     bool isKill;
996     unsigned SrcReg;
997     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
998     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
999                         SrcReg, isKill, ImplicitOp, LV))
1000       return nullptr;
1001 
1002     const MachineOperand &Src2 = MI.getOperand(2);
1003     bool isKill2;
1004     unsigned SrcReg2;
1005     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1006     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
1007                         SrcReg2, isKill2, ImplicitOp2, LV))
1008       return nullptr;
1009 
1010     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1011     if (ImplicitOp.getReg() != 0)
1012       MIB.add(ImplicitOp);
1013     if (ImplicitOp2.getReg() != 0)
1014       MIB.add(ImplicitOp2);
1015 
1016     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1017     if (LV && Src2.isKill())
1018       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
1019     break;
1020   }
1021   case X86::ADD8rr:
1022   case X86::ADD8rr_DB:
1023     Is8BitOp = true;
1024     LLVM_FALLTHROUGH;
1025   case X86::ADD16rr:
1026   case X86::ADD16rr_DB:
1027     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1028   case X86::ADD64ri32:
1029   case X86::ADD64ri8:
1030   case X86::ADD64ri32_DB:
1031   case X86::ADD64ri8_DB:
1032     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1033     NewMI = addOffset(
1034         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1035         MI.getOperand(2));
1036     break;
1037   case X86::ADD32ri:
1038   case X86::ADD32ri8:
1039   case X86::ADD32ri_DB:
1040   case X86::ADD32ri8_DB: {
1041     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
1042     unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
1043 
1044     bool isKill;
1045     unsigned SrcReg;
1046     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1047     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
1048                         SrcReg, isKill, ImplicitOp, LV))
1049       return nullptr;
1050 
1051     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1052                                   .add(Dest)
1053                                   .addReg(SrcReg, getKillRegState(isKill));
1054     if (ImplicitOp.getReg() != 0)
1055       MIB.add(ImplicitOp);
1056 
1057     NewMI = addOffset(MIB, MI.getOperand(2));
1058     break;
1059   }
1060   case X86::ADD8ri:
1061   case X86::ADD8ri_DB:
1062     Is8BitOp = true;
1063     LLVM_FALLTHROUGH;
1064   case X86::ADD16ri:
1065   case X86::ADD16ri8:
1066   case X86::ADD16ri_DB:
1067   case X86::ADD16ri8_DB:
1068     return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp);
1069   case X86::VMOVDQU8Z128rmk:
1070   case X86::VMOVDQU8Z256rmk:
1071   case X86::VMOVDQU8Zrmk:
1072   case X86::VMOVDQU16Z128rmk:
1073   case X86::VMOVDQU16Z256rmk:
1074   case X86::VMOVDQU16Zrmk:
1075   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
1076   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
1077   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
1078   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
1079   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
1080   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
1081   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
1082   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
1083   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
1084   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
1085   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
1086   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk: {
1087     unsigned Opc;
1088     switch (MIOpc) {
1089     default: llvm_unreachable("Unreachable!");
1090     case X86::VMOVDQU8Z128rmk:  Opc = X86::VPBLENDMBZ128rmk; break;
1091     case X86::VMOVDQU8Z256rmk:  Opc = X86::VPBLENDMBZ256rmk; break;
1092     case X86::VMOVDQU8Zrmk:     Opc = X86::VPBLENDMBZrmk;    break;
1093     case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
1094     case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
1095     case X86::VMOVDQU16Zrmk:    Opc = X86::VPBLENDMWZrmk;    break;
1096     case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1097     case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1098     case X86::VMOVDQU32Zrmk:    Opc = X86::VPBLENDMDZrmk;    break;
1099     case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1100     case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1101     case X86::VMOVDQU64Zrmk:    Opc = X86::VPBLENDMQZrmk;    break;
1102     case X86::VMOVUPDZ128rmk:   Opc = X86::VBLENDMPDZ128rmk; break;
1103     case X86::VMOVUPDZ256rmk:   Opc = X86::VBLENDMPDZ256rmk; break;
1104     case X86::VMOVUPDZrmk:      Opc = X86::VBLENDMPDZrmk;    break;
1105     case X86::VMOVUPSZ128rmk:   Opc = X86::VBLENDMPSZ128rmk; break;
1106     case X86::VMOVUPSZ256rmk:   Opc = X86::VBLENDMPSZ256rmk; break;
1107     case X86::VMOVUPSZrmk:      Opc = X86::VBLENDMPSZrmk;    break;
1108     case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
1109     case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
1110     case X86::VMOVDQA32Zrmk:    Opc = X86::VPBLENDMDZrmk;    break;
1111     case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
1112     case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
1113     case X86::VMOVDQA64Zrmk:    Opc = X86::VPBLENDMQZrmk;    break;
1114     case X86::VMOVAPDZ128rmk:   Opc = X86::VBLENDMPDZ128rmk; break;
1115     case X86::VMOVAPDZ256rmk:   Opc = X86::VBLENDMPDZ256rmk; break;
1116     case X86::VMOVAPDZrmk:      Opc = X86::VBLENDMPDZrmk;    break;
1117     case X86::VMOVAPSZ128rmk:   Opc = X86::VBLENDMPSZ128rmk; break;
1118     case X86::VMOVAPSZ256rmk:   Opc = X86::VBLENDMPSZ256rmk; break;
1119     case X86::VMOVAPSZrmk:      Opc = X86::VBLENDMPSZrmk;    break;
1120     }
1121 
1122     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1123               .add(Dest)
1124               .add(MI.getOperand(2))
1125               .add(Src)
1126               .add(MI.getOperand(3))
1127               .add(MI.getOperand(4))
1128               .add(MI.getOperand(5))
1129               .add(MI.getOperand(6))
1130               .add(MI.getOperand(7));
1131     break;
1132   }
1133   case X86::VMOVDQU8Z128rrk:
1134   case X86::VMOVDQU8Z256rrk:
1135   case X86::VMOVDQU8Zrrk:
1136   case X86::VMOVDQU16Z128rrk:
1137   case X86::VMOVDQU16Z256rrk:
1138   case X86::VMOVDQU16Zrrk:
1139   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
1140   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
1141   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
1142   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
1143   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
1144   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
1145   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
1146   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
1147   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
1148   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
1149   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
1150   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
1151     unsigned Opc;
1152     switch (MIOpc) {
1153     default: llvm_unreachable("Unreachable!");
1154     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
1155     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
1156     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
1157     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
1158     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
1159     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
1160     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1161     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1162     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1163     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1164     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1165     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1166     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1167     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1168     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1169     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1170     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1171     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1172     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
1173     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
1174     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
1175     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
1176     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
1177     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
1178     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
1179     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
1180     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
1181     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
1182     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
1183     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
1184     }
1185 
1186     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1187               .add(Dest)
1188               .add(MI.getOperand(2))
1189               .add(Src)
1190               .add(MI.getOperand(3));
1191     break;
1192   }
1193   }
1194 
1195   if (!NewMI) return nullptr;
1196 
1197   if (LV) {  // Update live variables
1198     if (Src.isKill())
1199       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1200     if (Dest.isDead())
1201       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1202   }
1203 
1204   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
1205   return NewMI;
1206 }
1207 
1208 /// This determines which of three possible cases of a three source commute
1209 /// the source indexes correspond to taking into account any mask operands.
1210 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
1211 /// possible.
1212 /// Case 0 - Possible to commute the first and second operands.
1213 /// Case 1 - Possible to commute the first and third operands.
1214 /// Case 2 - Possible to commute the second and third operands.
1215 static unsigned getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
1216                                        unsigned SrcOpIdx2) {
1217   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
1218   if (SrcOpIdx1 > SrcOpIdx2)
1219     std::swap(SrcOpIdx1, SrcOpIdx2);
1220 
1221   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
1222   if (X86II::isKMasked(TSFlags)) {
1223     Op2++;
1224     Op3++;
1225   }
1226 
1227   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
1228     return 0;
1229   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
1230     return 1;
1231   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
1232     return 2;
1233   llvm_unreachable("Unknown three src commute case.");
1234 }
1235 
1236 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
1237     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
1238     const X86InstrFMA3Group &FMA3Group) const {
1239 
1240   unsigned Opc = MI.getOpcode();
1241 
1242   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
1243   // analysis. The commute optimization is legal only if all users of FMA*_Int
1244   // use only the lowest element of the FMA*_Int instruction. Such analysis are
1245   // not implemented yet. So, just return 0 in that case.
1246   // When such analysis are available this place will be the right place for
1247   // calling it.
1248   assert(!(FMA3Group.isIntrinsic() && (SrcOpIdx1 == 1 || SrcOpIdx2 == 1)) &&
1249          "Intrinsic instructions can't commute operand 1");
1250 
1251   // Determine which case this commute is or if it can't be done.
1252   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1253                                          SrcOpIdx2);
1254   assert(Case < 3 && "Unexpected case number!");
1255 
1256   // Define the FMA forms mapping array that helps to map input FMA form
1257   // to output FMA form to preserve the operation semantics after
1258   // commuting the operands.
1259   const unsigned Form132Index = 0;
1260   const unsigned Form213Index = 1;
1261   const unsigned Form231Index = 2;
1262   static const unsigned FormMapping[][3] = {
1263     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
1264     // FMA132 A, C, b; ==> FMA231 C, A, b;
1265     // FMA213 B, A, c; ==> FMA213 A, B, c;
1266     // FMA231 C, A, b; ==> FMA132 A, C, b;
1267     { Form231Index, Form213Index, Form132Index },
1268     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
1269     // FMA132 A, c, B; ==> FMA132 B, c, A;
1270     // FMA213 B, a, C; ==> FMA231 C, a, B;
1271     // FMA231 C, a, B; ==> FMA213 B, a, C;
1272     { Form132Index, Form231Index, Form213Index },
1273     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
1274     // FMA132 a, C, B; ==> FMA213 a, B, C;
1275     // FMA213 b, A, C; ==> FMA132 b, C, A;
1276     // FMA231 c, A, B; ==> FMA231 c, B, A;
1277     { Form213Index, Form132Index, Form231Index }
1278   };
1279 
1280   unsigned FMAForms[3];
1281   FMAForms[0] = FMA3Group.get132Opcode();
1282   FMAForms[1] = FMA3Group.get213Opcode();
1283   FMAForms[2] = FMA3Group.get231Opcode();
1284   unsigned FormIndex;
1285   for (FormIndex = 0; FormIndex < 3; FormIndex++)
1286     if (Opc == FMAForms[FormIndex])
1287       break;
1288 
1289   // Everything is ready, just adjust the FMA opcode and return it.
1290   FormIndex = FormMapping[Case][FormIndex];
1291   return FMAForms[FormIndex];
1292 }
1293 
1294 static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
1295                              unsigned SrcOpIdx2) {
1296   // Determine which case this commute is or if it can't be done.
1297   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
1298                                          SrcOpIdx2);
1299   assert(Case < 3 && "Unexpected case value!");
1300 
1301   // For each case we need to swap two pairs of bits in the final immediate.
1302   static const uint8_t SwapMasks[3][4] = {
1303     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
1304     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
1305     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
1306   };
1307 
1308   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1309   // Clear out the bits we are swapping.
1310   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
1311                            SwapMasks[Case][2] | SwapMasks[Case][3]);
1312   // If the immediate had a bit of the pair set, then set the opposite bit.
1313   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
1314   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
1315   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
1316   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
1317   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1318 }
1319 
1320 // Returns true if this is a VPERMI2 or VPERMT2 instruction that can be
1321 // commuted.
1322 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
1323 #define VPERM_CASES(Suffix) \
1324   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
1325   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
1326   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
1327   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
1328   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
1329   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
1330   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
1331   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
1332   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
1333   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
1334   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
1335   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
1336 
1337 #define VPERM_CASES_BROADCAST(Suffix) \
1338   VPERM_CASES(Suffix) \
1339   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
1340   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
1341   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
1342   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
1343   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
1344   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
1345 
1346   switch (Opcode) {
1347   default: return false;
1348   VPERM_CASES(B)
1349   VPERM_CASES_BROADCAST(D)
1350   VPERM_CASES_BROADCAST(PD)
1351   VPERM_CASES_BROADCAST(PS)
1352   VPERM_CASES_BROADCAST(Q)
1353   VPERM_CASES(W)
1354     return true;
1355   }
1356 #undef VPERM_CASES_BROADCAST
1357 #undef VPERM_CASES
1358 }
1359 
1360 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
1361 // from the I opcode to the T opcode and vice versa.
1362 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
1363 #define VPERM_CASES(Orig, New) \
1364   case X86::Orig##128rr:    return X86::New##128rr;   \
1365   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
1366   case X86::Orig##128rm:    return X86::New##128rm;   \
1367   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
1368   case X86::Orig##256rr:    return X86::New##256rr;   \
1369   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
1370   case X86::Orig##256rm:    return X86::New##256rm;   \
1371   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
1372   case X86::Orig##rr:       return X86::New##rr;      \
1373   case X86::Orig##rrkz:     return X86::New##rrkz;    \
1374   case X86::Orig##rm:       return X86::New##rm;      \
1375   case X86::Orig##rmkz:     return X86::New##rmkz;
1376 
1377 #define VPERM_CASES_BROADCAST(Orig, New) \
1378   VPERM_CASES(Orig, New) \
1379   case X86::Orig##128rmb:   return X86::New##128rmb;   \
1380   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
1381   case X86::Orig##256rmb:   return X86::New##256rmb;   \
1382   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
1383   case X86::Orig##rmb:      return X86::New##rmb;      \
1384   case X86::Orig##rmbkz:    return X86::New##rmbkz;
1385 
1386   switch (Opcode) {
1387   VPERM_CASES(VPERMI2B, VPERMT2B)
1388   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
1389   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
1390   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
1391   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
1392   VPERM_CASES(VPERMI2W, VPERMT2W)
1393   VPERM_CASES(VPERMT2B, VPERMI2B)
1394   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
1395   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
1396   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
1397   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
1398   VPERM_CASES(VPERMT2W, VPERMI2W)
1399   }
1400 
1401   llvm_unreachable("Unreachable!");
1402 #undef VPERM_CASES_BROADCAST
1403 #undef VPERM_CASES
1404 }
1405 
1406 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1407                                                    unsigned OpIdx1,
1408                                                    unsigned OpIdx2) const {
1409   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
1410     if (NewMI)
1411       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
1412     return MI;
1413   };
1414 
1415   switch (MI.getOpcode()) {
1416   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1417   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1418   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1419   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1420   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1421   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1422     unsigned Opc;
1423     unsigned Size;
1424     switch (MI.getOpcode()) {
1425     default: llvm_unreachable("Unreachable!");
1426     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1427     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1428     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1429     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1430     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1431     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1432     }
1433     unsigned Amt = MI.getOperand(3).getImm();
1434     auto &WorkingMI = cloneIfNew(MI);
1435     WorkingMI.setDesc(get(Opc));
1436     WorkingMI.getOperand(3).setImm(Size - Amt);
1437     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1438                                                    OpIdx1, OpIdx2);
1439   }
1440   case X86::PFSUBrr:
1441   case X86::PFSUBRrr: {
1442     // PFSUB  x, y: x = x - y
1443     // PFSUBR x, y: x = y - x
1444     unsigned Opc =
1445         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
1446     auto &WorkingMI = cloneIfNew(MI);
1447     WorkingMI.setDesc(get(Opc));
1448     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1449                                                    OpIdx1, OpIdx2);
1450   }
1451   case X86::BLENDPDrri:
1452   case X86::BLENDPSrri:
1453   case X86::VBLENDPDrri:
1454   case X86::VBLENDPSrri:
1455     // If we're optimizing for size, try to use MOVSD/MOVSS.
1456     if (MI.getParent()->getParent()->getFunction().optForSize()) {
1457       unsigned Mask, Opc;
1458       switch (MI.getOpcode()) {
1459       default: llvm_unreachable("Unreachable!");
1460       case X86::BLENDPDrri:  Opc = X86::MOVSDrr;  Mask = 0x03; break;
1461       case X86::BLENDPSrri:  Opc = X86::MOVSSrr;  Mask = 0x0F; break;
1462       case X86::VBLENDPDrri: Opc = X86::VMOVSDrr; Mask = 0x03; break;
1463       case X86::VBLENDPSrri: Opc = X86::VMOVSSrr; Mask = 0x0F; break;
1464       }
1465       if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1466         auto &WorkingMI = cloneIfNew(MI);
1467         WorkingMI.setDesc(get(Opc));
1468         WorkingMI.RemoveOperand(3);
1469         return TargetInstrInfo::commuteInstructionImpl(WorkingMI,
1470                                                        /*NewMI=*/false,
1471                                                        OpIdx1, OpIdx2);
1472       }
1473     }
1474     LLVM_FALLTHROUGH;
1475   case X86::PBLENDWrri:
1476   case X86::VBLENDPDYrri:
1477   case X86::VBLENDPSYrri:
1478   case X86::VPBLENDDrri:
1479   case X86::VPBLENDWrri:
1480   case X86::VPBLENDDYrri:
1481   case X86::VPBLENDWYrri:{
1482     int8_t Mask;
1483     switch (MI.getOpcode()) {
1484     default: llvm_unreachable("Unreachable!");
1485     case X86::BLENDPDrri:    Mask = (int8_t)0x03; break;
1486     case X86::BLENDPSrri:    Mask = (int8_t)0x0F; break;
1487     case X86::PBLENDWrri:    Mask = (int8_t)0xFF; break;
1488     case X86::VBLENDPDrri:   Mask = (int8_t)0x03; break;
1489     case X86::VBLENDPSrri:   Mask = (int8_t)0x0F; break;
1490     case X86::VBLENDPDYrri:  Mask = (int8_t)0x0F; break;
1491     case X86::VBLENDPSYrri:  Mask = (int8_t)0xFF; break;
1492     case X86::VPBLENDDrri:   Mask = (int8_t)0x0F; break;
1493     case X86::VPBLENDWrri:   Mask = (int8_t)0xFF; break;
1494     case X86::VPBLENDDYrri:  Mask = (int8_t)0xFF; break;
1495     case X86::VPBLENDWYrri:  Mask = (int8_t)0xFF; break;
1496     }
1497     // Only the least significant bits of Imm are used.
1498     // Using int8_t to ensure it will be sign extended to the int64_t that
1499     // setImm takes in order to match isel behavior.
1500     int8_t Imm = MI.getOperand(3).getImm() & Mask;
1501     auto &WorkingMI = cloneIfNew(MI);
1502     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1503     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1504                                                    OpIdx1, OpIdx2);
1505   }
1506   case X86::INSERTPSrr:
1507   case X86::VINSERTPSrr:
1508   case X86::VINSERTPSZrr: {
1509     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
1510     unsigned ZMask = Imm & 15;
1511     unsigned DstIdx = (Imm >> 4) & 3;
1512     unsigned SrcIdx = (Imm >> 6) & 3;
1513 
1514     // We can commute insertps if we zero 2 of the elements, the insertion is
1515     // "inline" and we don't override the insertion with a zero.
1516     if (DstIdx == SrcIdx && (ZMask & (1 << DstIdx)) == 0 &&
1517         countPopulation(ZMask) == 2) {
1518       unsigned AltIdx = findFirstSet((ZMask | (1 << DstIdx)) ^ 15);
1519       assert(AltIdx < 4 && "Illegal insertion index");
1520       unsigned AltImm = (AltIdx << 6) | (AltIdx << 4) | ZMask;
1521       auto &WorkingMI = cloneIfNew(MI);
1522       WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
1523       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1524                                                      OpIdx1, OpIdx2);
1525     }
1526     return nullptr;
1527   }
1528   case X86::MOVSDrr:
1529   case X86::MOVSSrr:
1530   case X86::VMOVSDrr:
1531   case X86::VMOVSSrr:{
1532     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
1533     assert(Subtarget.hasSSE41() && "Commuting MOVSD/MOVSS requires SSE41!");
1534 
1535     unsigned Mask, Opc;
1536     switch (MI.getOpcode()) {
1537     default: llvm_unreachable("Unreachable!");
1538     case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
1539     case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
1540     case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
1541     case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
1542     }
1543 
1544     auto &WorkingMI = cloneIfNew(MI);
1545     WorkingMI.setDesc(get(Opc));
1546     WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1547     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1548                                                    OpIdx1, OpIdx2);
1549   }
1550   case X86::PCLMULQDQrr:
1551   case X86::VPCLMULQDQrr:
1552   case X86::VPCLMULQDQYrr:
1553   case X86::VPCLMULQDQZrr:
1554   case X86::VPCLMULQDQZ128rr:
1555   case X86::VPCLMULQDQZ256rr: {
1556     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
1557     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
1558     unsigned Imm = MI.getOperand(3).getImm();
1559     unsigned Src1Hi = Imm & 0x01;
1560     unsigned Src2Hi = Imm & 0x10;
1561     auto &WorkingMI = cloneIfNew(MI);
1562     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
1563     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1564                                                    OpIdx1, OpIdx2);
1565   }
1566   case X86::VPCMPBZ128rri:  case X86::VPCMPUBZ128rri:
1567   case X86::VPCMPBZ256rri:  case X86::VPCMPUBZ256rri:
1568   case X86::VPCMPBZrri:     case X86::VPCMPUBZrri:
1569   case X86::VPCMPDZ128rri:  case X86::VPCMPUDZ128rri:
1570   case X86::VPCMPDZ256rri:  case X86::VPCMPUDZ256rri:
1571   case X86::VPCMPDZrri:     case X86::VPCMPUDZrri:
1572   case X86::VPCMPQZ128rri:  case X86::VPCMPUQZ128rri:
1573   case X86::VPCMPQZ256rri:  case X86::VPCMPUQZ256rri:
1574   case X86::VPCMPQZrri:     case X86::VPCMPUQZrri:
1575   case X86::VPCMPWZ128rri:  case X86::VPCMPUWZ128rri:
1576   case X86::VPCMPWZ256rri:  case X86::VPCMPUWZ256rri:
1577   case X86::VPCMPWZrri:     case X86::VPCMPUWZrri:
1578   case X86::VPCMPBZ128rrik: case X86::VPCMPUBZ128rrik:
1579   case X86::VPCMPBZ256rrik: case X86::VPCMPUBZ256rrik:
1580   case X86::VPCMPBZrrik:    case X86::VPCMPUBZrrik:
1581   case X86::VPCMPDZ128rrik: case X86::VPCMPUDZ128rrik:
1582   case X86::VPCMPDZ256rrik: case X86::VPCMPUDZ256rrik:
1583   case X86::VPCMPDZrrik:    case X86::VPCMPUDZrrik:
1584   case X86::VPCMPQZ128rrik: case X86::VPCMPUQZ128rrik:
1585   case X86::VPCMPQZ256rrik: case X86::VPCMPUQZ256rrik:
1586   case X86::VPCMPQZrrik:    case X86::VPCMPUQZrrik:
1587   case X86::VPCMPWZ128rrik: case X86::VPCMPUWZ128rrik:
1588   case X86::VPCMPWZ256rrik: case X86::VPCMPUWZ256rrik:
1589   case X86::VPCMPWZrrik:    case X86::VPCMPUWZrrik: {
1590     // Flip comparison mode immediate (if necessary).
1591     unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
1592     Imm = X86::getSwappedVPCMPImm(Imm);
1593     auto &WorkingMI = cloneIfNew(MI);
1594     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1595     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1596                                                    OpIdx1, OpIdx2);
1597   }
1598   case X86::VPCOMBri: case X86::VPCOMUBri:
1599   case X86::VPCOMDri: case X86::VPCOMUDri:
1600   case X86::VPCOMQri: case X86::VPCOMUQri:
1601   case X86::VPCOMWri: case X86::VPCOMUWri: {
1602     // Flip comparison mode immediate (if necessary).
1603     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1604     Imm = X86::getSwappedVPCOMImm(Imm);
1605     auto &WorkingMI = cloneIfNew(MI);
1606     WorkingMI.getOperand(3).setImm(Imm);
1607     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1608                                                    OpIdx1, OpIdx2);
1609   }
1610   case X86::VPERM2F128rr:
1611   case X86::VPERM2I128rr: {
1612     // Flip permute source immediate.
1613     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
1614     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
1615     int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
1616     auto &WorkingMI = cloneIfNew(MI);
1617     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
1618     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1619                                                    OpIdx1, OpIdx2);
1620   }
1621   case X86::MOVHLPSrr:
1622   case X86::UNPCKHPDrr:
1623   case X86::VMOVHLPSrr:
1624   case X86::VUNPCKHPDrr:
1625   case X86::VMOVHLPSZrr:
1626   case X86::VUNPCKHPDZ128rr: {
1627     assert(Subtarget.hasSSE2() && "Commuting MOVHLP/UNPCKHPD requires SSE2!");
1628 
1629     unsigned Opc = MI.getOpcode();
1630     switch (Opc) {
1631     default: llvm_unreachable("Unreachable!");
1632     case X86::MOVHLPSrr:       Opc = X86::UNPCKHPDrr;      break;
1633     case X86::UNPCKHPDrr:      Opc = X86::MOVHLPSrr;       break;
1634     case X86::VMOVHLPSrr:      Opc = X86::VUNPCKHPDrr;     break;
1635     case X86::VUNPCKHPDrr:     Opc = X86::VMOVHLPSrr;      break;
1636     case X86::VMOVHLPSZrr:     Opc = X86::VUNPCKHPDZ128rr; break;
1637     case X86::VUNPCKHPDZ128rr: Opc = X86::VMOVHLPSZrr;     break;
1638     }
1639     auto &WorkingMI = cloneIfNew(MI);
1640     WorkingMI.setDesc(get(Opc));
1641     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1642                                                    OpIdx1, OpIdx2);
1643   }
1644   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
1645   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
1646   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
1647   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
1648   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
1649   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
1650   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
1651   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
1652   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
1653   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
1654   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
1655   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
1656   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
1657   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
1658   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
1659   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
1660     unsigned Opc;
1661     switch (MI.getOpcode()) {
1662     default: llvm_unreachable("Unreachable!");
1663     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
1664     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
1665     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
1666     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1667     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1668     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1669     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
1670     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
1671     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
1672     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1673     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1674     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1675     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1676     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1677     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1678     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
1679     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
1680     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
1681     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
1682     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
1683     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
1684     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1685     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1686     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1687     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1688     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1689     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1690     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
1691     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
1692     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
1693     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
1694     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
1695     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
1696     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1697     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1698     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1699     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
1700     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
1701     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
1702     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1703     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1704     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1705     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
1706     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
1707     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
1708     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1709     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1710     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1711     }
1712     auto &WorkingMI = cloneIfNew(MI);
1713     WorkingMI.setDesc(get(Opc));
1714     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1715                                                    OpIdx1, OpIdx2);
1716   }
1717   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
1718   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
1719   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
1720   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
1721   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
1722   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
1723   case X86::VPTERNLOGDZrrik:
1724   case X86::VPTERNLOGDZ128rrik:
1725   case X86::VPTERNLOGDZ256rrik:
1726   case X86::VPTERNLOGQZrrik:
1727   case X86::VPTERNLOGQZ128rrik:
1728   case X86::VPTERNLOGQZ256rrik:
1729   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
1730   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1731   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1732   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
1733   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1734   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1735   case X86::VPTERNLOGDZ128rmbi:
1736   case X86::VPTERNLOGDZ256rmbi:
1737   case X86::VPTERNLOGDZrmbi:
1738   case X86::VPTERNLOGQZ128rmbi:
1739   case X86::VPTERNLOGQZ256rmbi:
1740   case X86::VPTERNLOGQZrmbi:
1741   case X86::VPTERNLOGDZ128rmbikz:
1742   case X86::VPTERNLOGDZ256rmbikz:
1743   case X86::VPTERNLOGDZrmbikz:
1744   case X86::VPTERNLOGQZ128rmbikz:
1745   case X86::VPTERNLOGQZ256rmbikz:
1746   case X86::VPTERNLOGQZrmbikz: {
1747     auto &WorkingMI = cloneIfNew(MI);
1748     commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2);
1749     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1750                                                    OpIdx1, OpIdx2);
1751   }
1752   default: {
1753     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
1754       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
1755       auto &WorkingMI = cloneIfNew(MI);
1756       WorkingMI.setDesc(get(Opc));
1757       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1758                                                      OpIdx1, OpIdx2);
1759     }
1760 
1761     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
1762                                                       MI.getDesc().TSFlags);
1763     if (FMA3Group) {
1764       unsigned Opc =
1765         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
1766       auto &WorkingMI = cloneIfNew(MI);
1767       WorkingMI.setDesc(get(Opc));
1768       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
1769                                                      OpIdx1, OpIdx2);
1770     }
1771 
1772     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1773   }
1774   }
1775 }
1776 
1777 bool
1778 X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
1779                                             unsigned &SrcOpIdx1,
1780                                             unsigned &SrcOpIdx2,
1781                                             bool IsIntrinsic) const {
1782   uint64_t TSFlags = MI.getDesc().TSFlags;
1783 
1784   unsigned FirstCommutableVecOp = 1;
1785   unsigned LastCommutableVecOp = 3;
1786   unsigned KMaskOp = -1U;
1787   if (X86II::isKMasked(TSFlags)) {
1788     // For k-zero-masked operations it is Ok to commute the first vector
1789     // operand.
1790     // For regular k-masked operations a conservative choice is done as the
1791     // elements of the first vector operand, for which the corresponding bit
1792     // in the k-mask operand is set to 0, are copied to the result of the
1793     // instruction.
1794     // TODO/FIXME: The commute still may be legal if it is known that the
1795     // k-mask operand is set to either all ones or all zeroes.
1796     // It is also Ok to commute the 1st operand if all users of MI use only
1797     // the elements enabled by the k-mask operand. For example,
1798     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
1799     //                                                     : v1[i];
1800     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
1801     //                                  // Ok, to commute v1 in FMADD213PSZrk.
1802 
1803     // The k-mask operand has index = 2 for masked and zero-masked operations.
1804     KMaskOp = 2;
1805 
1806     // The operand with index = 1 is used as a source for those elements for
1807     // which the corresponding bit in the k-mask is set to 0.
1808     if (X86II::isKMergeMasked(TSFlags))
1809       FirstCommutableVecOp = 3;
1810 
1811     LastCommutableVecOp++;
1812   } else if (IsIntrinsic) {
1813     // Commuting the first operand of an intrinsic instruction isn't possible
1814     // unless we can prove that only the lowest element of the result is used.
1815     FirstCommutableVecOp = 2;
1816   }
1817 
1818   if (isMem(MI, LastCommutableVecOp))
1819     LastCommutableVecOp--;
1820 
1821   // Only the first RegOpsNum operands are commutable.
1822   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
1823   // that the operand is not specified/fixed.
1824   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
1825       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
1826        SrcOpIdx1 == KMaskOp))
1827     return false;
1828   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
1829       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
1830        SrcOpIdx2 == KMaskOp))
1831     return false;
1832 
1833   // Look for two different register operands assumed to be commutable
1834   // regardless of the FMA opcode. The FMA opcode is adjusted later.
1835   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
1836       SrcOpIdx2 == CommuteAnyOperandIndex) {
1837     unsigned CommutableOpIdx1 = SrcOpIdx1;
1838     unsigned CommutableOpIdx2 = SrcOpIdx2;
1839 
1840     // At least one of operands to be commuted is not specified and
1841     // this method is free to choose appropriate commutable operands.
1842     if (SrcOpIdx1 == SrcOpIdx2)
1843       // Both of operands are not fixed. By default set one of commutable
1844       // operands to the last register operand of the instruction.
1845       CommutableOpIdx2 = LastCommutableVecOp;
1846     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
1847       // Only one of operands is not fixed.
1848       CommutableOpIdx2 = SrcOpIdx1;
1849 
1850     // CommutableOpIdx2 is well defined now. Let's choose another commutable
1851     // operand and assign its index to CommutableOpIdx1.
1852     unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
1853     for (CommutableOpIdx1 = LastCommutableVecOp;
1854          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
1855       // Just ignore and skip the k-mask operand.
1856       if (CommutableOpIdx1 == KMaskOp)
1857         continue;
1858 
1859       // The commuted operands must have different registers.
1860       // Otherwise, the commute transformation does not change anything and
1861       // is useless then.
1862       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
1863         break;
1864     }
1865 
1866     // No appropriate commutable operands were found.
1867     if (CommutableOpIdx1 < FirstCommutableVecOp)
1868       return false;
1869 
1870     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
1871     // to return those values.
1872     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1873                               CommutableOpIdx1, CommutableOpIdx2))
1874       return false;
1875   }
1876 
1877   return true;
1878 }
1879 
1880 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
1881                                          unsigned &SrcOpIdx2) const {
1882   const MCInstrDesc &Desc = MI.getDesc();
1883   if (!Desc.isCommutable())
1884     return false;
1885 
1886   switch (MI.getOpcode()) {
1887   case X86::CMPSDrr:
1888   case X86::CMPSSrr:
1889   case X86::CMPPDrri:
1890   case X86::CMPPSrri:
1891   case X86::VCMPSDrr:
1892   case X86::VCMPSSrr:
1893   case X86::VCMPPDrri:
1894   case X86::VCMPPSrri:
1895   case X86::VCMPPDYrri:
1896   case X86::VCMPPSYrri:
1897   case X86::VCMPSDZrr:
1898   case X86::VCMPSSZrr:
1899   case X86::VCMPPDZrri:
1900   case X86::VCMPPSZrri:
1901   case X86::VCMPPDZ128rri:
1902   case X86::VCMPPSZ128rri:
1903   case X86::VCMPPDZ256rri:
1904   case X86::VCMPPSZ256rri: {
1905     // Float comparison can be safely commuted for
1906     // Ordered/Unordered/Equal/NotEqual tests
1907     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1908     switch (Imm) {
1909     case 0x00: // EQUAL
1910     case 0x03: // UNORDERED
1911     case 0x04: // NOT EQUAL
1912     case 0x07: // ORDERED
1913       // The indices of the commutable operands are 1 and 2.
1914       // Assign them to the returned operand indices here.
1915       return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
1916     }
1917     return false;
1918   }
1919   case X86::MOVSDrr:
1920   case X86::MOVSSrr:
1921   case X86::VMOVSDrr:
1922   case X86::VMOVSSrr:
1923     if (Subtarget.hasSSE41())
1924       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1925     return false;
1926   case X86::MOVHLPSrr:
1927   case X86::UNPCKHPDrr:
1928   case X86::VMOVHLPSrr:
1929   case X86::VUNPCKHPDrr:
1930   case X86::VMOVHLPSZrr:
1931   case X86::VUNPCKHPDZ128rr:
1932     if (Subtarget.hasSSE2())
1933       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1934     return false;
1935   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
1936   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
1937   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
1938   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
1939   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
1940   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
1941   case X86::VPTERNLOGDZrrik:
1942   case X86::VPTERNLOGDZ128rrik:
1943   case X86::VPTERNLOGDZ256rrik:
1944   case X86::VPTERNLOGQZrrik:
1945   case X86::VPTERNLOGQZ128rrik:
1946   case X86::VPTERNLOGQZ256rrik:
1947   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
1948   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
1949   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
1950   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
1951   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
1952   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
1953   case X86::VPTERNLOGDZ128rmbi:
1954   case X86::VPTERNLOGDZ256rmbi:
1955   case X86::VPTERNLOGDZrmbi:
1956   case X86::VPTERNLOGQZ128rmbi:
1957   case X86::VPTERNLOGQZ256rmbi:
1958   case X86::VPTERNLOGQZrmbi:
1959   case X86::VPTERNLOGDZ128rmbikz:
1960   case X86::VPTERNLOGDZ256rmbikz:
1961   case X86::VPTERNLOGDZrmbikz:
1962   case X86::VPTERNLOGQZ128rmbikz:
1963   case X86::VPTERNLOGQZ256rmbikz:
1964   case X86::VPTERNLOGQZrmbikz:
1965     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
1966   case X86::VPMADD52HUQZ128r:
1967   case X86::VPMADD52HUQZ128rk:
1968   case X86::VPMADD52HUQZ128rkz:
1969   case X86::VPMADD52HUQZ256r:
1970   case X86::VPMADD52HUQZ256rk:
1971   case X86::VPMADD52HUQZ256rkz:
1972   case X86::VPMADD52HUQZr:
1973   case X86::VPMADD52HUQZrk:
1974   case X86::VPMADD52HUQZrkz:
1975   case X86::VPMADD52LUQZ128r:
1976   case X86::VPMADD52LUQZ128rk:
1977   case X86::VPMADD52LUQZ128rkz:
1978   case X86::VPMADD52LUQZ256r:
1979   case X86::VPMADD52LUQZ256rk:
1980   case X86::VPMADD52LUQZ256rkz:
1981   case X86::VPMADD52LUQZr:
1982   case X86::VPMADD52LUQZrk:
1983   case X86::VPMADD52LUQZrkz: {
1984     unsigned CommutableOpIdx1 = 2;
1985     unsigned CommutableOpIdx2 = 3;
1986     if (X86II::isKMasked(Desc.TSFlags)) {
1987       // Skip the mask register.
1988       ++CommutableOpIdx1;
1989       ++CommutableOpIdx2;
1990     }
1991     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
1992                               CommutableOpIdx1, CommutableOpIdx2))
1993       return false;
1994     if (!MI.getOperand(SrcOpIdx1).isReg() ||
1995         !MI.getOperand(SrcOpIdx2).isReg())
1996       // No idea.
1997       return false;
1998     return true;
1999   }
2000 
2001   default:
2002     const X86InstrFMA3Group *FMA3Group = getFMA3Group(MI.getOpcode(),
2003                                                       MI.getDesc().TSFlags);
2004     if (FMA3Group)
2005       return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2,
2006                                            FMA3Group->isIntrinsic());
2007 
2008     // Handled masked instructions since we need to skip over the mask input
2009     // and the preserved input.
2010     if (X86II::isKMasked(Desc.TSFlags)) {
2011       // First assume that the first input is the mask operand and skip past it.
2012       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
2013       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
2014       // Check if the first input is tied. If there isn't one then we only
2015       // need to skip the mask operand which we did above.
2016       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
2017                                              MCOI::TIED_TO) != -1)) {
2018         // If this is zero masking instruction with a tied operand, we need to
2019         // move the first index back to the first input since this must
2020         // be a 3 input instruction and we want the first two non-mask inputs.
2021         // Otherwise this is a 2 input instruction with a preserved input and
2022         // mask, so we need to move the indices to skip one more input.
2023         if (X86II::isKMergeMasked(Desc.TSFlags)) {
2024           ++CommutableOpIdx1;
2025           ++CommutableOpIdx2;
2026         } else {
2027           --CommutableOpIdx1;
2028         }
2029       }
2030 
2031       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
2032                                 CommutableOpIdx1, CommutableOpIdx2))
2033         return false;
2034 
2035       if (!MI.getOperand(SrcOpIdx1).isReg() ||
2036           !MI.getOperand(SrcOpIdx2).isReg())
2037         // No idea.
2038         return false;
2039       return true;
2040     }
2041 
2042     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
2043   }
2044   return false;
2045 }
2046 
2047 X86::CondCode X86::getCondFromBranchOpc(unsigned BrOpc) {
2048   switch (BrOpc) {
2049   default: return X86::COND_INVALID;
2050   case X86::JE_1:  return X86::COND_E;
2051   case X86::JNE_1: return X86::COND_NE;
2052   case X86::JL_1:  return X86::COND_L;
2053   case X86::JLE_1: return X86::COND_LE;
2054   case X86::JG_1:  return X86::COND_G;
2055   case X86::JGE_1: return X86::COND_GE;
2056   case X86::JB_1:  return X86::COND_B;
2057   case X86::JBE_1: return X86::COND_BE;
2058   case X86::JA_1:  return X86::COND_A;
2059   case X86::JAE_1: return X86::COND_AE;
2060   case X86::JS_1:  return X86::COND_S;
2061   case X86::JNS_1: return X86::COND_NS;
2062   case X86::JP_1:  return X86::COND_P;
2063   case X86::JNP_1: return X86::COND_NP;
2064   case X86::JO_1:  return X86::COND_O;
2065   case X86::JNO_1: return X86::COND_NO;
2066   }
2067 }
2068 
2069 /// Return condition code of a SET opcode.
2070 X86::CondCode X86::getCondFromSETOpc(unsigned Opc) {
2071   switch (Opc) {
2072   default: return X86::COND_INVALID;
2073   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
2074   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2075   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
2076   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2077   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
2078   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
2079   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2080   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
2081   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2082   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2083   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2084   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2085   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2086   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
2087   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
2088   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
2089   }
2090 }
2091 
2092 /// Return condition code of a CMov opcode.
2093 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2094   switch (Opc) {
2095   default: return X86::COND_INVALID;
2096   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
2097   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
2098     return X86::COND_A;
2099   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2100   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2101     return X86::COND_AE;
2102   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
2103   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
2104     return X86::COND_B;
2105   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2106   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2107     return X86::COND_BE;
2108   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
2109   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
2110     return X86::COND_E;
2111   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
2112   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
2113     return X86::COND_G;
2114   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2115   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2116     return X86::COND_GE;
2117   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
2118   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
2119     return X86::COND_L;
2120   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2121   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2122     return X86::COND_LE;
2123   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2124   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2125     return X86::COND_NE;
2126   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2127   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2128     return X86::COND_NO;
2129   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2130   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2131     return X86::COND_NP;
2132   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2133   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2134     return X86::COND_NS;
2135   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
2136   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
2137     return X86::COND_O;
2138   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
2139   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
2140     return X86::COND_P;
2141   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
2142   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
2143     return X86::COND_S;
2144   }
2145 }
2146 
2147 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2148   switch (CC) {
2149   default: llvm_unreachable("Illegal condition code!");
2150   case X86::COND_E:  return X86::JE_1;
2151   case X86::COND_NE: return X86::JNE_1;
2152   case X86::COND_L:  return X86::JL_1;
2153   case X86::COND_LE: return X86::JLE_1;
2154   case X86::COND_G:  return X86::JG_1;
2155   case X86::COND_GE: return X86::JGE_1;
2156   case X86::COND_B:  return X86::JB_1;
2157   case X86::COND_BE: return X86::JBE_1;
2158   case X86::COND_A:  return X86::JA_1;
2159   case X86::COND_AE: return X86::JAE_1;
2160   case X86::COND_S:  return X86::JS_1;
2161   case X86::COND_NS: return X86::JNS_1;
2162   case X86::COND_P:  return X86::JP_1;
2163   case X86::COND_NP: return X86::JNP_1;
2164   case X86::COND_O:  return X86::JO_1;
2165   case X86::COND_NO: return X86::JNO_1;
2166   }
2167 }
2168 
2169 /// Return the inverse of the specified condition,
2170 /// e.g. turning COND_E to COND_NE.
2171 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2172   switch (CC) {
2173   default: llvm_unreachable("Illegal condition code!");
2174   case X86::COND_E:  return X86::COND_NE;
2175   case X86::COND_NE: return X86::COND_E;
2176   case X86::COND_L:  return X86::COND_GE;
2177   case X86::COND_LE: return X86::COND_G;
2178   case X86::COND_G:  return X86::COND_LE;
2179   case X86::COND_GE: return X86::COND_L;
2180   case X86::COND_B:  return X86::COND_AE;
2181   case X86::COND_BE: return X86::COND_A;
2182   case X86::COND_A:  return X86::COND_BE;
2183   case X86::COND_AE: return X86::COND_B;
2184   case X86::COND_S:  return X86::COND_NS;
2185   case X86::COND_NS: return X86::COND_S;
2186   case X86::COND_P:  return X86::COND_NP;
2187   case X86::COND_NP: return X86::COND_P;
2188   case X86::COND_O:  return X86::COND_NO;
2189   case X86::COND_NO: return X86::COND_O;
2190   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
2191   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
2192   }
2193 }
2194 
2195 /// Assuming the flags are set by MI(a,b), return the condition code if we
2196 /// modify the instructions such that flags are set by MI(b,a).
2197 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2198   switch (CC) {
2199   default: return X86::COND_INVALID;
2200   case X86::COND_E:  return X86::COND_E;
2201   case X86::COND_NE: return X86::COND_NE;
2202   case X86::COND_L:  return X86::COND_G;
2203   case X86::COND_LE: return X86::COND_GE;
2204   case X86::COND_G:  return X86::COND_L;
2205   case X86::COND_GE: return X86::COND_LE;
2206   case X86::COND_B:  return X86::COND_A;
2207   case X86::COND_BE: return X86::COND_AE;
2208   case X86::COND_A:  return X86::COND_B;
2209   case X86::COND_AE: return X86::COND_BE;
2210   }
2211 }
2212 
2213 std::pair<X86::CondCode, bool>
2214 X86::getX86ConditionCode(CmpInst::Predicate Predicate) {
2215   X86::CondCode CC = X86::COND_INVALID;
2216   bool NeedSwap = false;
2217   switch (Predicate) {
2218   default: break;
2219   // Floating-point Predicates
2220   case CmpInst::FCMP_UEQ: CC = X86::COND_E;       break;
2221   case CmpInst::FCMP_OLT: NeedSwap = true;        LLVM_FALLTHROUGH;
2222   case CmpInst::FCMP_OGT: CC = X86::COND_A;       break;
2223   case CmpInst::FCMP_OLE: NeedSwap = true;        LLVM_FALLTHROUGH;
2224   case CmpInst::FCMP_OGE: CC = X86::COND_AE;      break;
2225   case CmpInst::FCMP_UGT: NeedSwap = true;        LLVM_FALLTHROUGH;
2226   case CmpInst::FCMP_ULT: CC = X86::COND_B;       break;
2227   case CmpInst::FCMP_UGE: NeedSwap = true;        LLVM_FALLTHROUGH;
2228   case CmpInst::FCMP_ULE: CC = X86::COND_BE;      break;
2229   case CmpInst::FCMP_ONE: CC = X86::COND_NE;      break;
2230   case CmpInst::FCMP_UNO: CC = X86::COND_P;       break;
2231   case CmpInst::FCMP_ORD: CC = X86::COND_NP;      break;
2232   case CmpInst::FCMP_OEQ:                         LLVM_FALLTHROUGH;
2233   case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;
2234 
2235   // Integer Predicates
2236   case CmpInst::ICMP_EQ:  CC = X86::COND_E;       break;
2237   case CmpInst::ICMP_NE:  CC = X86::COND_NE;      break;
2238   case CmpInst::ICMP_UGT: CC = X86::COND_A;       break;
2239   case CmpInst::ICMP_UGE: CC = X86::COND_AE;      break;
2240   case CmpInst::ICMP_ULT: CC = X86::COND_B;       break;
2241   case CmpInst::ICMP_ULE: CC = X86::COND_BE;      break;
2242   case CmpInst::ICMP_SGT: CC = X86::COND_G;       break;
2243   case CmpInst::ICMP_SGE: CC = X86::COND_GE;      break;
2244   case CmpInst::ICMP_SLT: CC = X86::COND_L;       break;
2245   case CmpInst::ICMP_SLE: CC = X86::COND_LE;      break;
2246   }
2247 
2248   return std::make_pair(CC, NeedSwap);
2249 }
2250 
2251 /// Return a set opcode for the given condition and
2252 /// whether it has memory operand.
2253 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
2254   static const uint16_t Opc[16][2] = {
2255     { X86::SETAr,  X86::SETAm  },
2256     { X86::SETAEr, X86::SETAEm },
2257     { X86::SETBr,  X86::SETBm  },
2258     { X86::SETBEr, X86::SETBEm },
2259     { X86::SETEr,  X86::SETEm  },
2260     { X86::SETGr,  X86::SETGm  },
2261     { X86::SETGEr, X86::SETGEm },
2262     { X86::SETLr,  X86::SETLm  },
2263     { X86::SETLEr, X86::SETLEm },
2264     { X86::SETNEr, X86::SETNEm },
2265     { X86::SETNOr, X86::SETNOm },
2266     { X86::SETNPr, X86::SETNPm },
2267     { X86::SETNSr, X86::SETNSm },
2268     { X86::SETOr,  X86::SETOm  },
2269     { X86::SETPr,  X86::SETPm  },
2270     { X86::SETSr,  X86::SETSm  }
2271   };
2272 
2273   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
2274   return Opc[CC][HasMemoryOperand ? 1 : 0];
2275 }
2276 
2277 /// Return a cmov opcode for the given condition,
2278 /// register size in bytes, and operand type.
2279 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
2280                               bool HasMemoryOperand) {
2281   static const uint16_t Opc[32][3] = {
2282     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
2283     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2284     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
2285     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2286     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
2287     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
2288     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2289     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
2290     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2291     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2292     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2293     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2294     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2295     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
2296     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
2297     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
2298     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
2299     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2300     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
2301     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2302     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
2303     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
2304     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2305     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
2306     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2307     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2308     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2309     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2310     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2311     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
2312     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
2313     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
2314   };
2315 
2316   assert(CC < 16 && "Can only handle standard cond codes");
2317   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2318   switch(RegBytes) {
2319   default: llvm_unreachable("Illegal register size!");
2320   case 2: return Opc[Idx][0];
2321   case 4: return Opc[Idx][1];
2322   case 8: return Opc[Idx][2];
2323   }
2324 }
2325 
2326 /// Get the VPCMP immediate for the given condition.
2327 unsigned X86::getVPCMPImmForCond(ISD::CondCode CC) {
2328   switch (CC) {
2329   default: llvm_unreachable("Unexpected SETCC condition");
2330   case ISD::SETNE:  return 4;
2331   case ISD::SETEQ:  return 0;
2332   case ISD::SETULT:
2333   case ISD::SETLT: return 1;
2334   case ISD::SETUGT:
2335   case ISD::SETGT: return 6;
2336   case ISD::SETUGE:
2337   case ISD::SETGE: return 5;
2338   case ISD::SETULE:
2339   case ISD::SETLE: return 2;
2340   }
2341 }
2342 
2343 /// Get the VPCMP immediate if the opcodes are swapped.
2344 unsigned X86::getSwappedVPCMPImm(unsigned Imm) {
2345   switch (Imm) {
2346   default: llvm_unreachable("Unreachable!");
2347   case 0x01: Imm = 0x06; break; // LT  -> NLE
2348   case 0x02: Imm = 0x05; break; // LE  -> NLT
2349   case 0x05: Imm = 0x02; break; // NLT -> LE
2350   case 0x06: Imm = 0x01; break; // NLE -> LT
2351   case 0x00: // EQ
2352   case 0x03: // FALSE
2353   case 0x04: // NE
2354   case 0x07: // TRUE
2355     break;
2356   }
2357 
2358   return Imm;
2359 }
2360 
2361 /// Get the VPCOM immediate if the opcodes are swapped.
2362 unsigned X86::getSwappedVPCOMImm(unsigned Imm) {
2363   switch (Imm) {
2364   default: llvm_unreachable("Unreachable!");
2365   case 0x00: Imm = 0x02; break; // LT -> GT
2366   case 0x01: Imm = 0x03; break; // LE -> GE
2367   case 0x02: Imm = 0x00; break; // GT -> LT
2368   case 0x03: Imm = 0x01; break; // GE -> LE
2369   case 0x04: // EQ
2370   case 0x05: // NE
2371   case 0x06: // FALSE
2372   case 0x07: // TRUE
2373     break;
2374   }
2375 
2376   return Imm;
2377 }
2378 
2379 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
2380   if (!MI.isTerminator()) return false;
2381 
2382   // Conditional branch is a special case.
2383   if (MI.isBranch() && !MI.isBarrier())
2384     return true;
2385   if (!MI.isPredicable())
2386     return true;
2387   return !isPredicated(MI);
2388 }
2389 
2390 bool X86InstrInfo::isUnconditionalTailCall(const MachineInstr &MI) const {
2391   switch (MI.getOpcode()) {
2392   case X86::TCRETURNdi:
2393   case X86::TCRETURNri:
2394   case X86::TCRETURNmi:
2395   case X86::TCRETURNdi64:
2396   case X86::TCRETURNri64:
2397   case X86::TCRETURNmi64:
2398     return true;
2399   default:
2400     return false;
2401   }
2402 }
2403 
2404 bool X86InstrInfo::canMakeTailCallConditional(
2405     SmallVectorImpl<MachineOperand> &BranchCond,
2406     const MachineInstr &TailCall) const {
2407   if (TailCall.getOpcode() != X86::TCRETURNdi &&
2408       TailCall.getOpcode() != X86::TCRETURNdi64) {
2409     // Only direct calls can be done with a conditional branch.
2410     return false;
2411   }
2412 
2413   const MachineFunction *MF = TailCall.getParent()->getParent();
2414   if (Subtarget.isTargetWin64() && MF->hasWinCFI()) {
2415     // Conditional tail calls confuse the Win64 unwinder.
2416     return false;
2417   }
2418 
2419   assert(BranchCond.size() == 1);
2420   if (BranchCond[0].getImm() > X86::LAST_VALID_COND) {
2421     // Can't make a conditional tail call with this condition.
2422     return false;
2423   }
2424 
2425   const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
2426   if (X86FI->getTCReturnAddrDelta() != 0 ||
2427       TailCall.getOperand(1).getImm() != 0) {
2428     // A conditional tail call cannot do any stack adjustment.
2429     return false;
2430   }
2431 
2432   return true;
2433 }
2434 
2435 void X86InstrInfo::replaceBranchWithTailCall(
2436     MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2437     const MachineInstr &TailCall) const {
2438   assert(canMakeTailCallConditional(BranchCond, TailCall));
2439 
2440   MachineBasicBlock::iterator I = MBB.end();
2441   while (I != MBB.begin()) {
2442     --I;
2443     if (I->isDebugInstr())
2444       continue;
2445     if (!I->isBranch())
2446       assert(0 && "Can't find the branch to replace!");
2447 
2448     X86::CondCode CC = X86::getCondFromBranchOpc(I->getOpcode());
2449     assert(BranchCond.size() == 1);
2450     if (CC != BranchCond[0].getImm())
2451       continue;
2452 
2453     break;
2454   }
2455 
2456   unsigned Opc = TailCall.getOpcode() == X86::TCRETURNdi ? X86::TCRETURNdicc
2457                                                          : X86::TCRETURNdi64cc;
2458 
2459   auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2460   MIB->addOperand(TailCall.getOperand(0)); // Destination.
2461   MIB.addImm(0); // Stack offset (not used).
2462   MIB->addOperand(BranchCond[0]); // Condition.
2463   MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters.
2464 
2465   // Add implicit uses and defs of all live regs potentially clobbered by the
2466   // call. This way they still appear live across the call.
2467   LivePhysRegs LiveRegs(getRegisterInfo());
2468   LiveRegs.addLiveOuts(MBB);
2469   SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2470   LiveRegs.stepForward(*MIB, Clobbers);
2471   for (const auto &C : Clobbers) {
2472     MIB.addReg(C.first, RegState::Implicit);
2473     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2474   }
2475 
2476   I->eraseFromParent();
2477 }
2478 
2479 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
2480 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
2481 // fallthrough MBB cannot be identified.
2482 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
2483                                             MachineBasicBlock *TBB) {
2484   // Look for non-EHPad successors other than TBB. If we find exactly one, it
2485   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
2486   // and fallthrough MBB. If we find more than one, we cannot identify the
2487   // fallthrough MBB and should return nullptr.
2488   MachineBasicBlock *FallthroughBB = nullptr;
2489   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2490     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
2491       continue;
2492     // Return a nullptr if we found more than one fallthrough successor.
2493     if (FallthroughBB && FallthroughBB != TBB)
2494       return nullptr;
2495     FallthroughBB = *SI;
2496   }
2497   return FallthroughBB;
2498 }
2499 
2500 bool X86InstrInfo::AnalyzeBranchImpl(
2501     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
2502     SmallVectorImpl<MachineOperand> &Cond,
2503     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
2504 
2505   // Start from the bottom of the block and work up, examining the
2506   // terminator instructions.
2507   MachineBasicBlock::iterator I = MBB.end();
2508   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2509   while (I != MBB.begin()) {
2510     --I;
2511     if (I->isDebugInstr())
2512       continue;
2513 
2514     // Working from the bottom, when we see a non-terminator instruction, we're
2515     // done.
2516     if (!isUnpredicatedTerminator(*I))
2517       break;
2518 
2519     // A terminator that isn't a branch can't easily be handled by this
2520     // analysis.
2521     if (!I->isBranch())
2522       return true;
2523 
2524     // Handle unconditional branches.
2525     if (I->getOpcode() == X86::JMP_1) {
2526       UnCondBrIter = I;
2527 
2528       if (!AllowModify) {
2529         TBB = I->getOperand(0).getMBB();
2530         continue;
2531       }
2532 
2533       // If the block has any instructions after a JMP, delete them.
2534       while (std::next(I) != MBB.end())
2535         std::next(I)->eraseFromParent();
2536 
2537       Cond.clear();
2538       FBB = nullptr;
2539 
2540       // Delete the JMP if it's equivalent to a fall-through.
2541       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2542         TBB = nullptr;
2543         I->eraseFromParent();
2544         I = MBB.end();
2545         UnCondBrIter = MBB.end();
2546         continue;
2547       }
2548 
2549       // TBB is used to indicate the unconditional destination.
2550       TBB = I->getOperand(0).getMBB();
2551       continue;
2552     }
2553 
2554     // Handle conditional branches.
2555     X86::CondCode BranchCode = X86::getCondFromBranchOpc(I->getOpcode());
2556     if (BranchCode == X86::COND_INVALID)
2557       return true;  // Can't handle indirect branch.
2558 
2559     // In practice we should never have an undef eflags operand, if we do
2560     // abort here as we are not prepared to preserve the flag.
2561     if (I->getOperand(1).isUndef())
2562       return true;
2563 
2564     // Working from the bottom, handle the first conditional branch.
2565     if (Cond.empty()) {
2566       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2567       if (AllowModify && UnCondBrIter != MBB.end() &&
2568           MBB.isLayoutSuccessor(TargetBB)) {
2569         // If we can modify the code and it ends in something like:
2570         //
2571         //     jCC L1
2572         //     jmp L2
2573         //   L1:
2574         //     ...
2575         //   L2:
2576         //
2577         // Then we can change this to:
2578         //
2579         //     jnCC L2
2580         //   L1:
2581         //     ...
2582         //   L2:
2583         //
2584         // Which is a bit more efficient.
2585         // We conditionally jump to the fall-through block.
2586         BranchCode = GetOppositeBranchCondition(BranchCode);
2587         unsigned JNCC = GetCondBranchFromCond(BranchCode);
2588         MachineBasicBlock::iterator OldInst = I;
2589 
2590         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2591           .addMBB(UnCondBrIter->getOperand(0).getMBB());
2592         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
2593           .addMBB(TargetBB);
2594 
2595         OldInst->eraseFromParent();
2596         UnCondBrIter->eraseFromParent();
2597 
2598         // Restart the analysis.
2599         UnCondBrIter = MBB.end();
2600         I = MBB.end();
2601         continue;
2602       }
2603 
2604       FBB = TBB;
2605       TBB = I->getOperand(0).getMBB();
2606       Cond.push_back(MachineOperand::CreateImm(BranchCode));
2607       CondBranches.push_back(&*I);
2608       continue;
2609     }
2610 
2611     // Handle subsequent conditional branches. Only handle the case where all
2612     // conditional branches branch to the same destination and their condition
2613     // opcodes fit one of the special multi-branch idioms.
2614     assert(Cond.size() == 1);
2615     assert(TBB);
2616 
2617     // If the conditions are the same, we can leave them alone.
2618     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2619     auto NewTBB = I->getOperand(0).getMBB();
2620     if (OldBranchCode == BranchCode && TBB == NewTBB)
2621       continue;
2622 
2623     // If they differ, see if they fit one of the known patterns. Theoretically,
2624     // we could handle more patterns here, but we shouldn't expect to see them
2625     // if instruction selection has done a reasonable job.
2626     if (TBB == NewTBB &&
2627                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
2628                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
2629       BranchCode = X86::COND_NE_OR_P;
2630     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
2631                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
2632       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
2633         return true;
2634 
2635       // X86::COND_E_AND_NP usually has two different branch destinations.
2636       //
2637       // JP B1
2638       // JE B2
2639       // JMP B1
2640       // B1:
2641       // B2:
2642       //
2643       // Here this condition branches to B2 only if NP && E. It has another
2644       // equivalent form:
2645       //
2646       // JNE B1
2647       // JNP B2
2648       // JMP B1
2649       // B1:
2650       // B2:
2651       //
2652       // Similarly it branches to B2 only if E && NP. That is why this condition
2653       // is named with COND_E_AND_NP.
2654       BranchCode = X86::COND_E_AND_NP;
2655     } else
2656       return true;
2657 
2658     // Update the MachineOperand.
2659     Cond[0].setImm(BranchCode);
2660     CondBranches.push_back(&*I);
2661   }
2662 
2663   return false;
2664 }
2665 
2666 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
2667                                  MachineBasicBlock *&TBB,
2668                                  MachineBasicBlock *&FBB,
2669                                  SmallVectorImpl<MachineOperand> &Cond,
2670                                  bool AllowModify) const {
2671   SmallVector<MachineInstr *, 4> CondBranches;
2672   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
2673 }
2674 
2675 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
2676                                           MachineBranchPredicate &MBP,
2677                                           bool AllowModify) const {
2678   using namespace std::placeholders;
2679 
2680   SmallVector<MachineOperand, 4> Cond;
2681   SmallVector<MachineInstr *, 4> CondBranches;
2682   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
2683                         AllowModify))
2684     return true;
2685 
2686   if (Cond.size() != 1)
2687     return true;
2688 
2689   assert(MBP.TrueDest && "expected!");
2690 
2691   if (!MBP.FalseDest)
2692     MBP.FalseDest = MBB.getNextNode();
2693 
2694   const TargetRegisterInfo *TRI = &getRegisterInfo();
2695 
2696   MachineInstr *ConditionDef = nullptr;
2697   bool SingleUseCondition = true;
2698 
2699   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
2700     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
2701       ConditionDef = &*I;
2702       break;
2703     }
2704 
2705     if (I->readsRegister(X86::EFLAGS, TRI))
2706       SingleUseCondition = false;
2707   }
2708 
2709   if (!ConditionDef)
2710     return true;
2711 
2712   if (SingleUseCondition) {
2713     for (auto *Succ : MBB.successors())
2714       if (Succ->isLiveIn(X86::EFLAGS))
2715         SingleUseCondition = false;
2716   }
2717 
2718   MBP.ConditionDef = ConditionDef;
2719   MBP.SingleUseCondition = SingleUseCondition;
2720 
2721   // Currently we only recognize the simple pattern:
2722   //
2723   //   test %reg, %reg
2724   //   je %label
2725   //
2726   const unsigned TestOpcode =
2727       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
2728 
2729   if (ConditionDef->getOpcode() == TestOpcode &&
2730       ConditionDef->getNumOperands() == 3 &&
2731       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
2732       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
2733     MBP.LHS = ConditionDef->getOperand(0);
2734     MBP.RHS = MachineOperand::CreateImm(0);
2735     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
2736                         ? MachineBranchPredicate::PRED_NE
2737                         : MachineBranchPredicate::PRED_EQ;
2738     return false;
2739   }
2740 
2741   return true;
2742 }
2743 
2744 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
2745                                     int *BytesRemoved) const {
2746   assert(!BytesRemoved && "code size not handled");
2747 
2748   MachineBasicBlock::iterator I = MBB.end();
2749   unsigned Count = 0;
2750 
2751   while (I != MBB.begin()) {
2752     --I;
2753     if (I->isDebugInstr())
2754       continue;
2755     if (I->getOpcode() != X86::JMP_1 &&
2756         X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2757       break;
2758     // Remove the branch.
2759     I->eraseFromParent();
2760     I = MBB.end();
2761     ++Count;
2762   }
2763 
2764   return Count;
2765 }
2766 
2767 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
2768                                     MachineBasicBlock *TBB,
2769                                     MachineBasicBlock *FBB,
2770                                     ArrayRef<MachineOperand> Cond,
2771                                     const DebugLoc &DL,
2772                                     int *BytesAdded) const {
2773   // Shouldn't be a fall through.
2774   assert(TBB && "insertBranch must not be told to insert a fallthrough");
2775   assert((Cond.size() == 1 || Cond.size() == 0) &&
2776          "X86 branch conditions have one component!");
2777   assert(!BytesAdded && "code size not handled");
2778 
2779   if (Cond.empty()) {
2780     // Unconditional branch?
2781     assert(!FBB && "Unconditional branch with multiple successors!");
2782     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2783     return 1;
2784   }
2785 
2786   // If FBB is null, it is implied to be a fall-through block.
2787   bool FallThru = FBB == nullptr;
2788 
2789   // Conditional branch.
2790   unsigned Count = 0;
2791   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2792   switch (CC) {
2793   case X86::COND_NE_OR_P:
2794     // Synthesize NE_OR_P with two branches.
2795     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
2796     ++Count;
2797     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
2798     ++Count;
2799     break;
2800   case X86::COND_E_AND_NP:
2801     // Use the next block of MBB as FBB if it is null.
2802     if (FBB == nullptr) {
2803       FBB = getFallThroughMBB(&MBB, TBB);
2804       assert(FBB && "MBB cannot be the last block in function when the false "
2805                     "body is a fall-through.");
2806     }
2807     // Synthesize COND_E_AND_NP with two branches.
2808     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
2809     ++Count;
2810     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
2811     ++Count;
2812     break;
2813   default: {
2814     unsigned Opc = GetCondBranchFromCond(CC);
2815     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2816     ++Count;
2817   }
2818   }
2819   if (!FallThru) {
2820     // Two-way Conditional branch. Insert the second branch.
2821     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
2822     ++Count;
2823   }
2824   return Count;
2825 }
2826 
2827 bool X86InstrInfo::
2828 canInsertSelect(const MachineBasicBlock &MBB,
2829                 ArrayRef<MachineOperand> Cond,
2830                 unsigned TrueReg, unsigned FalseReg,
2831                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2832   // Not all subtargets have cmov instructions.
2833   if (!Subtarget.hasCMov())
2834     return false;
2835   if (Cond.size() != 1)
2836     return false;
2837   // We cannot do the composite conditions, at least not in SSA form.
2838   if ((X86::CondCode)Cond[0].getImm() > X86::LAST_VALID_COND)
2839     return false;
2840 
2841   // Check register classes.
2842   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2843   const TargetRegisterClass *RC =
2844     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2845   if (!RC)
2846     return false;
2847 
2848   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2849   if (X86::GR16RegClass.hasSubClassEq(RC) ||
2850       X86::GR32RegClass.hasSubClassEq(RC) ||
2851       X86::GR64RegClass.hasSubClassEq(RC)) {
2852     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2853     // Bridge. Probably Ivy Bridge as well.
2854     CondCycles = 2;
2855     TrueCycles = 2;
2856     FalseCycles = 2;
2857     return true;
2858   }
2859 
2860   // Can't do vectors.
2861   return false;
2862 }
2863 
2864 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2865                                 MachineBasicBlock::iterator I,
2866                                 const DebugLoc &DL, unsigned DstReg,
2867                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
2868                                 unsigned FalseReg) const {
2869   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2870   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
2871   const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
2872   assert(Cond.size() == 1 && "Invalid Cond array");
2873   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
2874                                  TRI.getRegSizeInBits(RC) / 8,
2875                                  false /*HasMemoryOperand*/);
2876   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
2877 }
2878 
2879 /// Test if the given register is a physical h register.
2880 static bool isHReg(unsigned Reg) {
2881   return X86::GR8_ABCD_HRegClass.contains(Reg);
2882 }
2883 
2884 // Try and copy between VR128/VR64 and GR64 registers.
2885 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2886                                         const X86Subtarget &Subtarget) {
2887   bool HasAVX = Subtarget.hasAVX();
2888   bool HasAVX512 = Subtarget.hasAVX512();
2889 
2890   // SrcReg(MaskReg) -> DestReg(GR64)
2891   // SrcReg(MaskReg) -> DestReg(GR32)
2892 
2893   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2894   if (X86::VK16RegClass.contains(SrcReg)) {
2895     if (X86::GR64RegClass.contains(DestReg)) {
2896       assert(Subtarget.hasBWI());
2897       return X86::KMOVQrk;
2898     }
2899     if (X86::GR32RegClass.contains(DestReg))
2900       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
2901   }
2902 
2903   // SrcReg(GR64) -> DestReg(MaskReg)
2904   // SrcReg(GR32) -> DestReg(MaskReg)
2905 
2906   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
2907   if (X86::VK16RegClass.contains(DestReg)) {
2908     if (X86::GR64RegClass.contains(SrcReg)) {
2909       assert(Subtarget.hasBWI());
2910       return X86::KMOVQkr;
2911     }
2912     if (X86::GR32RegClass.contains(SrcReg))
2913       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
2914   }
2915 
2916 
2917   // SrcReg(VR128) -> DestReg(GR64)
2918   // SrcReg(VR64)  -> DestReg(GR64)
2919   // SrcReg(GR64)  -> DestReg(VR128)
2920   // SrcReg(GR64)  -> DestReg(VR64)
2921 
2922   if (X86::GR64RegClass.contains(DestReg)) {
2923     if (X86::VR128XRegClass.contains(SrcReg))
2924       // Copy from a VR128 register to a GR64 register.
2925       return HasAVX512 ? X86::VMOVPQIto64Zrr :
2926              HasAVX    ? X86::VMOVPQIto64rr  :
2927                          X86::MOVPQIto64rr;
2928     if (X86::VR64RegClass.contains(SrcReg))
2929       // Copy from a VR64 register to a GR64 register.
2930       return X86::MMX_MOVD64from64rr;
2931   } else if (X86::GR64RegClass.contains(SrcReg)) {
2932     // Copy from a GR64 register to a VR128 register.
2933     if (X86::VR128XRegClass.contains(DestReg))
2934       return HasAVX512 ? X86::VMOV64toPQIZrr :
2935              HasAVX    ? X86::VMOV64toPQIrr  :
2936                          X86::MOV64toPQIrr;
2937     // Copy from a GR64 register to a VR64 register.
2938     if (X86::VR64RegClass.contains(DestReg))
2939       return X86::MMX_MOVD64to64rr;
2940   }
2941 
2942   // SrcReg(FR32) -> DestReg(GR32)
2943   // SrcReg(GR32) -> DestReg(FR32)
2944 
2945   if (X86::GR32RegClass.contains(DestReg) &&
2946       X86::FR32XRegClass.contains(SrcReg))
2947     // Copy from a FR32 register to a GR32 register.
2948     return HasAVX512 ? X86::VMOVSS2DIZrr :
2949            HasAVX    ? X86::VMOVSS2DIrr  :
2950                        X86::MOVSS2DIrr;
2951 
2952   if (X86::FR32XRegClass.contains(DestReg) &&
2953       X86::GR32RegClass.contains(SrcReg))
2954     // Copy from a GR32 register to a FR32 register.
2955     return HasAVX512 ? X86::VMOVDI2SSZrr :
2956            HasAVX    ? X86::VMOVDI2SSrr  :
2957                        X86::MOVDI2SSrr;
2958   return 0;
2959 }
2960 
2961 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2962                                MachineBasicBlock::iterator MI,
2963                                const DebugLoc &DL, unsigned DestReg,
2964                                unsigned SrcReg, bool KillSrc) const {
2965   // First deal with the normal symmetric copies.
2966   bool HasAVX = Subtarget.hasAVX();
2967   bool HasVLX = Subtarget.hasVLX();
2968   unsigned Opc = 0;
2969   if (X86::GR64RegClass.contains(DestReg, SrcReg))
2970     Opc = X86::MOV64rr;
2971   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2972     Opc = X86::MOV32rr;
2973   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2974     Opc = X86::MOV16rr;
2975   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2976     // Copying to or from a physical H register on x86-64 requires a NOREX
2977     // move.  Otherwise use a normal move.
2978     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2979         Subtarget.is64Bit()) {
2980       Opc = X86::MOV8rr_NOREX;
2981       // Both operands must be encodable without an REX prefix.
2982       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2983              "8-bit H register can not be copied outside GR8_NOREX");
2984     } else
2985       Opc = X86::MOV8rr;
2986   }
2987   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2988     Opc = X86::MMX_MOVQ64rr;
2989   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
2990     if (HasVLX)
2991       Opc = X86::VMOVAPSZ128rr;
2992     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2993       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2994     else {
2995       // If this an extended register and we don't have VLX we need to use a
2996       // 512-bit move.
2997       Opc = X86::VMOVAPSZrr;
2998       const TargetRegisterInfo *TRI = &getRegisterInfo();
2999       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
3000                                          &X86::VR512RegClass);
3001       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
3002                                         &X86::VR512RegClass);
3003     }
3004   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
3005     if (HasVLX)
3006       Opc = X86::VMOVAPSZ256rr;
3007     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3008       Opc = X86::VMOVAPSYrr;
3009     else {
3010       // If this an extended register and we don't have VLX we need to use a
3011       // 512-bit move.
3012       Opc = X86::VMOVAPSZrr;
3013       const TargetRegisterInfo *TRI = &getRegisterInfo();
3014       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
3015                                          &X86::VR512RegClass);
3016       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
3017                                         &X86::VR512RegClass);
3018     }
3019   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
3020     Opc = X86::VMOVAPSZrr;
3021   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
3022   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
3023     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
3024   if (!Opc)
3025     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3026 
3027   if (Opc) {
3028     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3029       .addReg(SrcReg, getKillRegState(KillSrc));
3030     return;
3031   }
3032 
3033   if (SrcReg == X86::EFLAGS || DestReg == X86::EFLAGS) {
3034     // FIXME: We use a fatal error here because historically LLVM has tried
3035     // lower some of these physreg copies and we want to ensure we get
3036     // reasonable bug reports if someone encounters a case no other testing
3037     // found. This path should be removed after the LLVM 7 release.
3038     report_fatal_error("Unable to copy EFLAGS physical register!");
3039   }
3040 
3041   LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
3042                     << RI.getName(DestReg) << '\n');
3043   report_fatal_error("Cannot emit physreg copy instruction");
3044 }
3045 
3046 bool X86InstrInfo::isCopyInstrImpl(const MachineInstr &MI,
3047                                    const MachineOperand *&Src,
3048                                    const MachineOperand *&Dest) const {
3049   if (MI.isMoveReg()) {
3050     Dest = &MI.getOperand(0);
3051     Src = &MI.getOperand(1);
3052     return true;
3053   }
3054   return false;
3055 }
3056 
3057 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3058                                       const TargetRegisterClass *RC,
3059                                       bool isStackAligned,
3060                                       const X86Subtarget &STI,
3061                                       bool load) {
3062   bool HasAVX = STI.hasAVX();
3063   bool HasAVX512 = STI.hasAVX512();
3064   bool HasVLX = STI.hasVLX();
3065 
3066   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
3067   default:
3068     llvm_unreachable("Unknown spill size");
3069   case 1:
3070     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3071     if (STI.is64Bit())
3072       // Copying to or from a physical H register on x86-64 requires a NOREX
3073       // move.  Otherwise use a normal move.
3074       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3075         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3076     return load ? X86::MOV8rm : X86::MOV8mr;
3077   case 2:
3078     if (X86::VK16RegClass.hasSubClassEq(RC))
3079       return load ? X86::KMOVWkm : X86::KMOVWmk;
3080     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3081     return load ? X86::MOV16rm : X86::MOV16mr;
3082   case 4:
3083     if (X86::GR32RegClass.hasSubClassEq(RC))
3084       return load ? X86::MOV32rm : X86::MOV32mr;
3085     if (X86::FR32XRegClass.hasSubClassEq(RC))
3086       return load ?
3087         (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3088         (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3089     if (X86::RFP32RegClass.hasSubClassEq(RC))
3090       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3091     if (X86::VK32RegClass.hasSubClassEq(RC)) {
3092       assert(STI.hasBWI() && "KMOVD requires BWI");
3093       return load ? X86::KMOVDkm : X86::KMOVDmk;
3094     }
3095     llvm_unreachable("Unknown 4-byte regclass");
3096   case 8:
3097     if (X86::GR64RegClass.hasSubClassEq(RC))
3098       return load ? X86::MOV64rm : X86::MOV64mr;
3099     if (X86::FR64XRegClass.hasSubClassEq(RC))
3100       return load ?
3101         (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3102         (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3103     if (X86::VR64RegClass.hasSubClassEq(RC))
3104       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3105     if (X86::RFP64RegClass.hasSubClassEq(RC))
3106       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3107     if (X86::VK64RegClass.hasSubClassEq(RC)) {
3108       assert(STI.hasBWI() && "KMOVQ requires BWI");
3109       return load ? X86::KMOVQkm : X86::KMOVQmk;
3110     }
3111     llvm_unreachable("Unknown 8-byte regclass");
3112   case 10:
3113     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3114     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3115   case 16: {
3116     if (X86::VR128XRegClass.hasSubClassEq(RC)) {
3117       // If stack is realigned we can use aligned stores.
3118       if (isStackAligned)
3119         return load ?
3120           (HasVLX    ? X86::VMOVAPSZ128rm :
3121            HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
3122            HasAVX    ? X86::VMOVAPSrm :
3123                        X86::MOVAPSrm):
3124           (HasVLX    ? X86::VMOVAPSZ128mr :
3125            HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
3126            HasAVX    ? X86::VMOVAPSmr :
3127                        X86::MOVAPSmr);
3128       else
3129         return load ?
3130           (HasVLX    ? X86::VMOVUPSZ128rm :
3131            HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
3132            HasAVX    ? X86::VMOVUPSrm :
3133                        X86::MOVUPSrm):
3134           (HasVLX    ? X86::VMOVUPSZ128mr :
3135            HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
3136            HasAVX    ? X86::VMOVUPSmr :
3137                        X86::MOVUPSmr);
3138     }
3139     if (X86::BNDRRegClass.hasSubClassEq(RC)) {
3140       if (STI.is64Bit())
3141         return load ? X86::BNDMOV64rm : X86::BNDMOV64mr;
3142       else
3143         return load ? X86::BNDMOV32rm : X86::BNDMOV32mr;
3144     }
3145     llvm_unreachable("Unknown 16-byte regclass");
3146   }
3147   case 32:
3148     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
3149     // If stack is realigned we can use aligned stores.
3150     if (isStackAligned)
3151       return load ?
3152         (HasVLX    ? X86::VMOVAPSZ256rm :
3153          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
3154                      X86::VMOVAPSYrm) :
3155         (HasVLX    ? X86::VMOVAPSZ256mr :
3156          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
3157                      X86::VMOVAPSYmr);
3158     else
3159       return load ?
3160         (HasVLX    ? X86::VMOVUPSZ256rm :
3161          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
3162                      X86::VMOVUPSYrm) :
3163         (HasVLX    ? X86::VMOVUPSZ256mr :
3164          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
3165                      X86::VMOVUPSYmr);
3166   case 64:
3167     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3168     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
3169     if (isStackAligned)
3170       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3171     else
3172       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3173   }
3174 }
3175 
3176 bool X86InstrInfo::getMemOperandWithOffset(
3177     MachineInstr &MemOp, MachineOperand *&BaseOp, int64_t &Offset,
3178     const TargetRegisterInfo *TRI) const {
3179   const MCInstrDesc &Desc = MemOp.getDesc();
3180   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
3181   if (MemRefBegin < 0)
3182     return false;
3183 
3184   MemRefBegin += X86II::getOperandBias(Desc);
3185 
3186   BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3187   if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3188     return false;
3189 
3190   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3191     return false;
3192 
3193   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3194       X86::NoRegister)
3195     return false;
3196 
3197   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3198 
3199   // Displacement can be symbolic
3200   if (!DispMO.isImm())
3201     return false;
3202 
3203   Offset = DispMO.getImm();
3204 
3205   assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
3206                             "operands of type register.");
3207   return true;
3208 }
3209 
3210 static unsigned getStoreRegOpcode(unsigned SrcReg,
3211                                   const TargetRegisterClass *RC,
3212                                   bool isStackAligned,
3213                                   const X86Subtarget &STI) {
3214   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3215 }
3216 
3217 
3218 static unsigned getLoadRegOpcode(unsigned DestReg,
3219                                  const TargetRegisterClass *RC,
3220                                  bool isStackAligned,
3221                                  const X86Subtarget &STI) {
3222   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3223 }
3224 
3225 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3226                                        MachineBasicBlock::iterator MI,
3227                                        unsigned SrcReg, bool isKill, int FrameIdx,
3228                                        const TargetRegisterClass *RC,
3229                                        const TargetRegisterInfo *TRI) const {
3230   const MachineFunction &MF = *MBB.getParent();
3231   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
3232          "Stack slot too small for store");
3233   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3234   bool isAligned =
3235       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3236       RI.canRealignStack(MF);
3237   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3238   addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3239     .addReg(SrcReg, getKillRegState(isKill));
3240 }
3241 
3242 void X86InstrInfo::storeRegToAddr(
3243     MachineFunction &MF, unsigned SrcReg, bool isKill,
3244     SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
3245     ArrayRef<MachineMemOperand *> MMOs,
3246     SmallVectorImpl<MachineInstr *> &NewMIs) const {
3247   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3248   unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3249   bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3250   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3251   DebugLoc DL;
3252   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3253   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3254     MIB.add(Addr[i]);
3255   MIB.addReg(SrcReg, getKillRegState(isKill));
3256   MIB.setMemRefs(MMOs);
3257   NewMIs.push_back(MIB);
3258 }
3259 
3260 
3261 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3262                                         MachineBasicBlock::iterator MI,
3263                                         unsigned DestReg, int FrameIdx,
3264                                         const TargetRegisterClass *RC,
3265                                         const TargetRegisterInfo *TRI) const {
3266   const MachineFunction &MF = *MBB.getParent();
3267   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
3268   bool isAligned =
3269       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3270       RI.canRealignStack(MF);
3271   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3272   addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3273 }
3274 
3275 void X86InstrInfo::loadRegFromAddr(
3276     MachineFunction &MF, unsigned DestReg,
3277     SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
3278     ArrayRef<MachineMemOperand *> MMOs,
3279     SmallVectorImpl<MachineInstr *> &NewMIs) const {
3280   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
3281   unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
3282   bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
3283   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3284   DebugLoc DL;
3285   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3286   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3287     MIB.add(Addr[i]);
3288   MIB.setMemRefs(MMOs);
3289   NewMIs.push_back(MIB);
3290 }
3291 
3292 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
3293                                   unsigned &SrcReg2, int &CmpMask,
3294                                   int &CmpValue) const {
3295   switch (MI.getOpcode()) {
3296   default: break;
3297   case X86::CMP64ri32:
3298   case X86::CMP64ri8:
3299   case X86::CMP32ri:
3300   case X86::CMP32ri8:
3301   case X86::CMP16ri:
3302   case X86::CMP16ri8:
3303   case X86::CMP8ri:
3304     SrcReg = MI.getOperand(0).getReg();
3305     SrcReg2 = 0;
3306     if (MI.getOperand(1).isImm()) {
3307       CmpMask = ~0;
3308       CmpValue = MI.getOperand(1).getImm();
3309     } else {
3310       CmpMask = CmpValue = 0;
3311     }
3312     return true;
3313   // A SUB can be used to perform comparison.
3314   case X86::SUB64rm:
3315   case X86::SUB32rm:
3316   case X86::SUB16rm:
3317   case X86::SUB8rm:
3318     SrcReg = MI.getOperand(1).getReg();
3319     SrcReg2 = 0;
3320     CmpMask = 0;
3321     CmpValue = 0;
3322     return true;
3323   case X86::SUB64rr:
3324   case X86::SUB32rr:
3325   case X86::SUB16rr:
3326   case X86::SUB8rr:
3327     SrcReg = MI.getOperand(1).getReg();
3328     SrcReg2 = MI.getOperand(2).getReg();
3329     CmpMask = 0;
3330     CmpValue = 0;
3331     return true;
3332   case X86::SUB64ri32:
3333   case X86::SUB64ri8:
3334   case X86::SUB32ri:
3335   case X86::SUB32ri8:
3336   case X86::SUB16ri:
3337   case X86::SUB16ri8:
3338   case X86::SUB8ri:
3339     SrcReg = MI.getOperand(1).getReg();
3340     SrcReg2 = 0;
3341     if (MI.getOperand(2).isImm()) {
3342       CmpMask = ~0;
3343       CmpValue = MI.getOperand(2).getImm();
3344     } else {
3345       CmpMask = CmpValue = 0;
3346     }
3347     return true;
3348   case X86::CMP64rr:
3349   case X86::CMP32rr:
3350   case X86::CMP16rr:
3351   case X86::CMP8rr:
3352     SrcReg = MI.getOperand(0).getReg();
3353     SrcReg2 = MI.getOperand(1).getReg();
3354     CmpMask = 0;
3355     CmpValue = 0;
3356     return true;
3357   case X86::TEST8rr:
3358   case X86::TEST16rr:
3359   case X86::TEST32rr:
3360   case X86::TEST64rr:
3361     SrcReg = MI.getOperand(0).getReg();
3362     if (MI.getOperand(1).getReg() != SrcReg)
3363       return false;
3364     // Compare against zero.
3365     SrcReg2 = 0;
3366     CmpMask = ~0;
3367     CmpValue = 0;
3368     return true;
3369   }
3370   return false;
3371 }
3372 
3373 /// Check whether the first instruction, whose only
3374 /// purpose is to update flags, can be made redundant.
3375 /// CMPrr can be made redundant by SUBrr if the operands are the same.
3376 /// This function can be extended later on.
3377 /// SrcReg, SrcRegs: register operands for FlagI.
3378 /// ImmValue: immediate for FlagI if it takes an immediate.
3379 inline static bool isRedundantFlagInstr(const MachineInstr &FlagI,
3380                                         unsigned SrcReg, unsigned SrcReg2,
3381                                         int ImmMask, int ImmValue,
3382                                         const MachineInstr &OI) {
3383   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
3384        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
3385        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
3386        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
3387       ((OI.getOperand(1).getReg() == SrcReg &&
3388         OI.getOperand(2).getReg() == SrcReg2) ||
3389        (OI.getOperand(1).getReg() == SrcReg2 &&
3390         OI.getOperand(2).getReg() == SrcReg)))
3391     return true;
3392 
3393   if (ImmMask != 0 &&
3394       ((FlagI.getOpcode() == X86::CMP64ri32 &&
3395         OI.getOpcode() == X86::SUB64ri32) ||
3396        (FlagI.getOpcode() == X86::CMP64ri8 &&
3397         OI.getOpcode() == X86::SUB64ri8) ||
3398        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
3399        (FlagI.getOpcode() == X86::CMP32ri8 &&
3400         OI.getOpcode() == X86::SUB32ri8) ||
3401        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
3402        (FlagI.getOpcode() == X86::CMP16ri8 &&
3403         OI.getOpcode() == X86::SUB16ri8) ||
3404        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
3405       OI.getOperand(1).getReg() == SrcReg &&
3406       OI.getOperand(2).getImm() == ImmValue)
3407     return true;
3408   return false;
3409 }
3410 
3411 /// Check whether the definition can be converted
3412 /// to remove a comparison against zero.
3413 inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag) {
3414   NoSignFlag = false;
3415 
3416   switch (MI.getOpcode()) {
3417   default: return false;
3418 
3419   // The shift instructions only modify ZF if their shift count is non-zero.
3420   // N.B.: The processor truncates the shift count depending on the encoding.
3421   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
3422   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
3423      return getTruncatedShiftCount(MI, 2) != 0;
3424 
3425   // Some left shift instructions can be turned into LEA instructions but only
3426   // if their flags aren't used. Avoid transforming such instructions.
3427   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
3428     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
3429     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
3430     return ShAmt != 0;
3431   }
3432 
3433   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
3434   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
3435      return getTruncatedShiftCount(MI, 3) != 0;
3436 
3437   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3438   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3439   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3440   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3441   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3442   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3443   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3444   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3445   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3446   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3447   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3448   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3449   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3450   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3451   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3452   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3453   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3454   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3455   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3456   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3457   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3458   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3459   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3460   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3461   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3462   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3463   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3464   case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
3465   case X86::ADC32ri8:  case X86::ADC16ri:  case X86::ADC16ri8:
3466   case X86::ADC8ri:    case X86::ADC64rr:  case X86::ADC32rr:
3467   case X86::ADC16rr:   case X86::ADC8rr:   case X86::ADC64rm:
3468   case X86::ADC32rm:   case X86::ADC16rm:  case X86::ADC8rm:
3469   case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
3470   case X86::SBB32ri8:  case X86::SBB16ri:  case X86::SBB16ri8:
3471   case X86::SBB8ri:    case X86::SBB64rr:  case X86::SBB32rr:
3472   case X86::SBB16rr:   case X86::SBB8rr:   case X86::SBB64rm:
3473   case X86::SBB32rm:   case X86::SBB16rm:  case X86::SBB8rm:
3474   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
3475   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
3476   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
3477   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
3478   case X86::ANDN32rr:  case X86::ANDN32rm:
3479   case X86::ANDN64rr:  case X86::ANDN64rm:
3480   case X86::BLSI32rr:  case X86::BLSI32rm:
3481   case X86::BLSI64rr:  case X86::BLSI64rm:
3482   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
3483   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
3484   case X86::BLSR32rr:  case X86::BLSR32rm:
3485   case X86::BLSR64rr:  case X86::BLSR64rm:
3486   case X86::BZHI32rr:  case X86::BZHI32rm:
3487   case X86::BZHI64rr:  case X86::BZHI64rm:
3488   case X86::LZCNT16rr: case X86::LZCNT16rm:
3489   case X86::LZCNT32rr: case X86::LZCNT32rm:
3490   case X86::LZCNT64rr: case X86::LZCNT64rm:
3491   case X86::POPCNT16rr:case X86::POPCNT16rm:
3492   case X86::POPCNT32rr:case X86::POPCNT32rm:
3493   case X86::POPCNT64rr:case X86::POPCNT64rm:
3494   case X86::TZCNT16rr: case X86::TZCNT16rm:
3495   case X86::TZCNT32rr: case X86::TZCNT32rm:
3496   case X86::TZCNT64rr: case X86::TZCNT64rm:
3497   case X86::BLCFILL32rr: case X86::BLCFILL32rm:
3498   case X86::BLCFILL64rr: case X86::BLCFILL64rm:
3499   case X86::BLCI32rr:    case X86::BLCI32rm:
3500   case X86::BLCI64rr:    case X86::BLCI64rm:
3501   case X86::BLCIC32rr:   case X86::BLCIC32rm:
3502   case X86::BLCIC64rr:   case X86::BLCIC64rm:
3503   case X86::BLCMSK32rr:  case X86::BLCMSK32rm:
3504   case X86::BLCMSK64rr:  case X86::BLCMSK64rm:
3505   case X86::BLCS32rr:    case X86::BLCS32rm:
3506   case X86::BLCS64rr:    case X86::BLCS64rm:
3507   case X86::BLSFILL32rr: case X86::BLSFILL32rm:
3508   case X86::BLSFILL64rr: case X86::BLSFILL64rm:
3509   case X86::BLSIC32rr:   case X86::BLSIC32rm:
3510   case X86::BLSIC64rr:   case X86::BLSIC64rm:
3511   case X86::T1MSKC32rr:  case X86::T1MSKC32rm:
3512   case X86::T1MSKC64rr:  case X86::T1MSKC64rm:
3513   case X86::TZMSK32rr:   case X86::TZMSK32rm:
3514   case X86::TZMSK64rr:   case X86::TZMSK64rm:
3515     return true;
3516   case X86::BEXTR32rr:   case X86::BEXTR64rr:
3517   case X86::BEXTR32rm:   case X86::BEXTR64rm:
3518   case X86::BEXTRI32ri:  case X86::BEXTRI32mi:
3519   case X86::BEXTRI64ri:  case X86::BEXTRI64mi:
3520     // BEXTR doesn't update the sign flag so we can't use it.
3521     NoSignFlag = true;
3522     return true;
3523   }
3524 }
3525 
3526 /// Check whether the use can be converted to remove a comparison against zero.
3527 static X86::CondCode isUseDefConvertible(const MachineInstr &MI) {
3528   switch (MI.getOpcode()) {
3529   default: return X86::COND_INVALID;
3530   case X86::LZCNT16rr: case X86::LZCNT16rm:
3531   case X86::LZCNT32rr: case X86::LZCNT32rm:
3532   case X86::LZCNT64rr: case X86::LZCNT64rm:
3533     return X86::COND_B;
3534   case X86::POPCNT16rr:case X86::POPCNT16rm:
3535   case X86::POPCNT32rr:case X86::POPCNT32rm:
3536   case X86::POPCNT64rr:case X86::POPCNT64rm:
3537     return X86::COND_E;
3538   case X86::TZCNT16rr: case X86::TZCNT16rm:
3539   case X86::TZCNT32rr: case X86::TZCNT32rm:
3540   case X86::TZCNT64rr: case X86::TZCNT64rm:
3541     return X86::COND_B;
3542   case X86::BSF16rr: case X86::BSF16rm:
3543   case X86::BSF32rr: case X86::BSF32rm:
3544   case X86::BSF64rr: case X86::BSF64rm:
3545   case X86::BSR16rr: case X86::BSR16rm:
3546   case X86::BSR32rr: case X86::BSR32rm:
3547   case X86::BSR64rr: case X86::BSR64rm:
3548     return X86::COND_E;
3549   }
3550 }
3551 
3552 /// Check if there exists an earlier instruction that
3553 /// operates on the same source operands and sets flags in the same way as
3554 /// Compare; remove Compare if possible.
3555 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
3556                                         unsigned SrcReg2, int CmpMask,
3557                                         int CmpValue,
3558                                         const MachineRegisterInfo *MRI) const {
3559   // Check whether we can replace SUB with CMP.
3560   unsigned NewOpcode = 0;
3561   switch (CmpInstr.getOpcode()) {
3562   default: break;
3563   case X86::SUB64ri32:
3564   case X86::SUB64ri8:
3565   case X86::SUB32ri:
3566   case X86::SUB32ri8:
3567   case X86::SUB16ri:
3568   case X86::SUB16ri8:
3569   case X86::SUB8ri:
3570   case X86::SUB64rm:
3571   case X86::SUB32rm:
3572   case X86::SUB16rm:
3573   case X86::SUB8rm:
3574   case X86::SUB64rr:
3575   case X86::SUB32rr:
3576   case X86::SUB16rr:
3577   case X86::SUB8rr: {
3578     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
3579       return false;
3580     // There is no use of the destination register, we can replace SUB with CMP.
3581     switch (CmpInstr.getOpcode()) {
3582     default: llvm_unreachable("Unreachable!");
3583     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
3584     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
3585     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
3586     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
3587     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
3588     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
3589     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
3590     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
3591     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3592     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
3593     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
3594     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
3595     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
3596     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
3597     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
3598     }
3599     CmpInstr.setDesc(get(NewOpcode));
3600     CmpInstr.RemoveOperand(0);
3601     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3602     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3603         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3604       return false;
3605   }
3606   }
3607 
3608   // Get the unique definition of SrcReg.
3609   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3610   if (!MI) return false;
3611 
3612   // CmpInstr is the first instruction of the BB.
3613   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3614 
3615   // If we are comparing against zero, check whether we can use MI to update
3616   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3617   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
3618   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
3619     return false;
3620 
3621   // If we have a use of the source register between the def and our compare
3622   // instruction we can eliminate the compare iff the use sets EFLAGS in the
3623   // right way.
3624   bool ShouldUpdateCC = false;
3625   bool NoSignFlag = false;
3626   X86::CondCode NewCC = X86::COND_INVALID;
3627   if (IsCmpZero && !isDefConvertible(*MI, NoSignFlag)) {
3628     // Scan forward from the use until we hit the use we're looking for or the
3629     // compare instruction.
3630     for (MachineBasicBlock::iterator J = MI;; ++J) {
3631       // Do we have a convertible instruction?
3632       NewCC = isUseDefConvertible(*J);
3633       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3634           J->getOperand(1).getReg() == SrcReg) {
3635         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
3636         ShouldUpdateCC = true; // Update CC later on.
3637         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
3638         // with the new def.
3639         Def = J;
3640         MI = &*Def;
3641         break;
3642       }
3643 
3644       if (J == I)
3645         return false;
3646     }
3647   }
3648 
3649   // We are searching for an earlier instruction that can make CmpInstr
3650   // redundant and that instruction will be saved in Sub.
3651   MachineInstr *Sub = nullptr;
3652   const TargetRegisterInfo *TRI = &getRegisterInfo();
3653 
3654   // We iterate backward, starting from the instruction before CmpInstr and
3655   // stop when reaching the definition of a source register or done with the BB.
3656   // RI points to the instruction before CmpInstr.
3657   // If the definition is in this basic block, RE points to the definition;
3658   // otherwise, RE is the rend of the basic block.
3659   MachineBasicBlock::reverse_iterator
3660       RI = ++I.getReverse(),
3661       RE = CmpInstr.getParent() == MI->getParent()
3662                ? Def.getReverse() /* points to MI */
3663                : CmpInstr.getParent()->rend();
3664   MachineInstr *Movr0Inst = nullptr;
3665   for (; RI != RE; ++RI) {
3666     MachineInstr &Instr = *RI;
3667     // Check whether CmpInstr can be made redundant by the current instruction.
3668     if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
3669                                            CmpValue, Instr)) {
3670       Sub = &Instr;
3671       break;
3672     }
3673 
3674     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
3675         Instr.readsRegister(X86::EFLAGS, TRI)) {
3676       // This instruction modifies or uses EFLAGS.
3677 
3678       // MOV32r0 etc. are implemented with xor which clobbers condition code.
3679       // They are safe to move up, if the definition to EFLAGS is dead and
3680       // earlier instructions do not read or write EFLAGS.
3681       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
3682           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
3683         Movr0Inst = &Instr;
3684         continue;
3685       }
3686 
3687       // We can't remove CmpInstr.
3688       return false;
3689     }
3690   }
3691 
3692   // Return false if no candidates exist.
3693   if (!IsCmpZero && !Sub)
3694     return false;
3695 
3696   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3697                     Sub->getOperand(2).getReg() == SrcReg);
3698 
3699   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3700   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3701   // If we are done with the basic block, we need to check whether EFLAGS is
3702   // live-out.
3703   bool IsSafe = false;
3704   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3705   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
3706   for (++I; I != E; ++I) {
3707     const MachineInstr &Instr = *I;
3708     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3709     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3710     // We should check the usage if this instruction uses and updates EFLAGS.
3711     if (!UseEFLAGS && ModifyEFLAGS) {
3712       // It is safe to remove CmpInstr if EFLAGS is updated again.
3713       IsSafe = true;
3714       break;
3715     }
3716     if (!UseEFLAGS && !ModifyEFLAGS)
3717       continue;
3718 
3719     // EFLAGS is used by this instruction.
3720     X86::CondCode OldCC = X86::COND_INVALID;
3721     bool OpcIsSET = false;
3722     if (IsCmpZero || IsSwapped) {
3723       // We decode the condition code from opcode.
3724       if (Instr.isBranch())
3725         OldCC = X86::getCondFromBranchOpc(Instr.getOpcode());
3726       else {
3727         OldCC = X86::getCondFromSETOpc(Instr.getOpcode());
3728         if (OldCC != X86::COND_INVALID)
3729           OpcIsSET = true;
3730         else
3731           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3732       }
3733       if (OldCC == X86::COND_INVALID) return false;
3734     }
3735     X86::CondCode ReplacementCC = X86::COND_INVALID;
3736     if (IsCmpZero) {
3737       switch (OldCC) {
3738       default: break;
3739       case X86::COND_A: case X86::COND_AE:
3740       case X86::COND_B: case X86::COND_BE:
3741       case X86::COND_G: case X86::COND_GE:
3742       case X86::COND_L: case X86::COND_LE:
3743       case X86::COND_O: case X86::COND_NO:
3744         // CF and OF are used, we can't perform this optimization.
3745         return false;
3746       case X86::COND_S: case X86::COND_NS:
3747         // If SF is used, but the instruction doesn't update the SF, then we
3748         // can't do the optimization.
3749         if (NoSignFlag)
3750           return false;
3751         break;
3752       }
3753 
3754       // If we're updating the condition code check if we have to reverse the
3755       // condition.
3756       if (ShouldUpdateCC)
3757         switch (OldCC) {
3758         default:
3759           return false;
3760         case X86::COND_E:
3761           ReplacementCC = NewCC;
3762           break;
3763         case X86::COND_NE:
3764           ReplacementCC = GetOppositeBranchCondition(NewCC);
3765           break;
3766         }
3767     } else if (IsSwapped) {
3768       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3769       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3770       // We swap the condition code and synthesize the new opcode.
3771       ReplacementCC = getSwappedCondition(OldCC);
3772       if (ReplacementCC == X86::COND_INVALID) return false;
3773     }
3774 
3775     if ((ShouldUpdateCC || IsSwapped) && ReplacementCC != OldCC) {
3776       // Synthesize the new opcode.
3777       bool HasMemoryOperand = Instr.hasOneMemOperand();
3778       unsigned NewOpc;
3779       if (Instr.isBranch())
3780         NewOpc = GetCondBranchFromCond(ReplacementCC);
3781       else if(OpcIsSET)
3782         NewOpc = getSETFromCond(ReplacementCC, HasMemoryOperand);
3783       else {
3784         unsigned DstReg = Instr.getOperand(0).getReg();
3785         const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
3786         NewOpc = getCMovFromCond(ReplacementCC, TRI->getRegSizeInBits(*DstRC)/8,
3787                                  HasMemoryOperand);
3788       }
3789 
3790       // Push the MachineInstr to OpsToUpdate.
3791       // If it is safe to remove CmpInstr, the condition code of these
3792       // instructions will be modified.
3793       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3794     }
3795     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3796       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3797       IsSafe = true;
3798       break;
3799     }
3800   }
3801 
3802   // If EFLAGS is not killed nor re-defined, we should check whether it is
3803   // live-out. If it is live-out, do not optimize.
3804   if ((IsCmpZero || IsSwapped) && !IsSafe) {
3805     MachineBasicBlock *MBB = CmpInstr.getParent();
3806     for (MachineBasicBlock *Successor : MBB->successors())
3807       if (Successor->isLiveIn(X86::EFLAGS))
3808         return false;
3809   }
3810 
3811   // The instruction to be updated is either Sub or MI.
3812   Sub = IsCmpZero ? MI : Sub;
3813   // Move Movr0Inst to the appropriate place before Sub.
3814   if (Movr0Inst) {
3815     // Look backwards until we find a def that doesn't use the current EFLAGS.
3816     Def = Sub;
3817     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
3818                                         InsertE = Sub->getParent()->rend();
3819     for (; InsertI != InsertE; ++InsertI) {
3820       MachineInstr *Instr = &*InsertI;
3821       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
3822           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
3823         Sub->getParent()->remove(Movr0Inst);
3824         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
3825                                    Movr0Inst);
3826         break;
3827       }
3828     }
3829     if (InsertI == InsertE)
3830       return false;
3831   }
3832 
3833   // Make sure Sub instruction defines EFLAGS and mark the def live.
3834   unsigned i = 0, e = Sub->getNumOperands();
3835   for (; i != e; ++i) {
3836     MachineOperand &MO = Sub->getOperand(i);
3837     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
3838       MO.setIsDead(false);
3839       break;
3840     }
3841   }
3842   assert(i != e && "Unable to locate a def EFLAGS operand");
3843 
3844   CmpInstr.eraseFromParent();
3845 
3846   // Modify the condition code of instructions in OpsToUpdate.
3847   for (auto &Op : OpsToUpdate)
3848     Op.first->setDesc(get(Op.second));
3849   return true;
3850 }
3851 
3852 /// Try to remove the load by folding it to a register
3853 /// operand at the use. We fold the load instructions if load defines a virtual
3854 /// register, the virtual register is used once in the same BB, and the
3855 /// instructions in-between do not load or store, and have no side effects.
3856 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
3857                                               const MachineRegisterInfo *MRI,
3858                                               unsigned &FoldAsLoadDefReg,
3859                                               MachineInstr *&DefMI) const {
3860   // Check whether we can move DefMI here.
3861   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3862   assert(DefMI);
3863   bool SawStore = false;
3864   if (!DefMI->isSafeToMove(nullptr, SawStore))
3865     return nullptr;
3866 
3867   // Collect information about virtual register operands of MI.
3868   SmallVector<unsigned, 1> SrcOperandIds;
3869   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3870     MachineOperand &MO = MI.getOperand(i);
3871     if (!MO.isReg())
3872       continue;
3873     unsigned Reg = MO.getReg();
3874     if (Reg != FoldAsLoadDefReg)
3875       continue;
3876     // Do not fold if we have a subreg use or a def.
3877     if (MO.getSubReg() || MO.isDef())
3878       return nullptr;
3879     SrcOperandIds.push_back(i);
3880   }
3881   if (SrcOperandIds.empty())
3882     return nullptr;
3883 
3884   // Check whether we can fold the def into SrcOperandId.
3885   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
3886     FoldAsLoadDefReg = 0;
3887     return FoldMI;
3888   }
3889 
3890   return nullptr;
3891 }
3892 
3893 /// Expand a single-def pseudo instruction to a two-addr
3894 /// instruction with two undef reads of the register being defined.
3895 /// This is used for mapping:
3896 ///   %xmm4 = V_SET0
3897 /// to:
3898 ///   %xmm4 = PXORrr undef %xmm4, undef %xmm4
3899 ///
3900 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3901                              const MCInstrDesc &Desc) {
3902   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3903   unsigned Reg = MIB->getOperand(0).getReg();
3904   MIB->setDesc(Desc);
3905 
3906   // MachineInstr::addOperand() will insert explicit operands before any
3907   // implicit operands.
3908   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3909   // But we don't trust that.
3910   assert(MIB->getOperand(1).getReg() == Reg &&
3911          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3912   return true;
3913 }
3914 
3915 /// Expand a single-def pseudo instruction to a two-addr
3916 /// instruction with two %k0 reads.
3917 /// This is used for mapping:
3918 ///   %k4 = K_SET1
3919 /// to:
3920 ///   %k4 = KXNORrr %k0, %k0
3921 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
3922                             const MCInstrDesc &Desc, unsigned Reg) {
3923   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3924   MIB->setDesc(Desc);
3925   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3926   return true;
3927 }
3928 
3929 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
3930                           bool MinusOne) {
3931   MachineBasicBlock &MBB = *MIB->getParent();
3932   DebugLoc DL = MIB->getDebugLoc();
3933   unsigned Reg = MIB->getOperand(0).getReg();
3934 
3935   // Insert the XOR.
3936   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
3937       .addReg(Reg, RegState::Undef)
3938       .addReg(Reg, RegState::Undef);
3939 
3940   // Turn the pseudo into an INC or DEC.
3941   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
3942   MIB.addReg(Reg);
3943 
3944   return true;
3945 }
3946 
3947 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
3948                                const TargetInstrInfo &TII,
3949                                const X86Subtarget &Subtarget) {
3950   MachineBasicBlock &MBB = *MIB->getParent();
3951   DebugLoc DL = MIB->getDebugLoc();
3952   int64_t Imm = MIB->getOperand(1).getImm();
3953   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
3954   MachineBasicBlock::iterator I = MIB.getInstr();
3955 
3956   int StackAdjustment;
3957 
3958   if (Subtarget.is64Bit()) {
3959     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
3960            MIB->getOpcode() == X86::MOV32ImmSExti8);
3961 
3962     // Can't use push/pop lowering if the function might write to the red zone.
3963     X86MachineFunctionInfo *X86FI =
3964         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
3965     if (X86FI->getUsesRedZone()) {
3966       MIB->setDesc(TII.get(MIB->getOpcode() ==
3967                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
3968       return true;
3969     }
3970 
3971     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
3972     // widen the register if necessary.
3973     StackAdjustment = 8;
3974     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
3975     MIB->setDesc(TII.get(X86::POP64r));
3976     MIB->getOperand(0)
3977         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
3978   } else {
3979     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
3980     StackAdjustment = 4;
3981     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
3982     MIB->setDesc(TII.get(X86::POP32r));
3983   }
3984 
3985   // Build CFI if necessary.
3986   MachineFunction &MF = *MBB.getParent();
3987   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
3988   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
3989   bool NeedsDwarfCFI =
3990       !IsWin64Prologue &&
3991       (MF.getMMI().hasDebugInfo() || MF.getFunction().needsUnwindTableEntry());
3992   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
3993   if (EmitCFI) {
3994     TFL->BuildCFI(MBB, I, DL,
3995         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
3996     TFL->BuildCFI(MBB, std::next(I), DL,
3997         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
3998   }
3999 
4000   return true;
4001 }
4002 
4003 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4004 // code sequence is needed for other targets.
4005 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4006                                  const TargetInstrInfo &TII) {
4007   MachineBasicBlock &MBB = *MIB->getParent();
4008   DebugLoc DL = MIB->getDebugLoc();
4009   unsigned Reg = MIB->getOperand(0).getReg();
4010   const GlobalValue *GV =
4011       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4012   auto Flags = MachineMemOperand::MOLoad |
4013                MachineMemOperand::MODereferenceable |
4014                MachineMemOperand::MOInvariant;
4015   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4016       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
4017   MachineBasicBlock::iterator I = MIB.getInstr();
4018 
4019   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4020       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4021       .addMemOperand(MMO);
4022   MIB->setDebugLoc(DL);
4023   MIB->setDesc(TII.get(X86::MOV64rm));
4024   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4025 }
4026 
4027 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4028   MachineBasicBlock &MBB = *MIB->getParent();
4029   MachineFunction &MF = *MBB.getParent();
4030   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
4031   const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
4032   unsigned XorOp =
4033       MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr;
4034   MIB->setDesc(TII.get(XorOp));
4035   MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4036   return true;
4037 }
4038 
4039 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4040 // but not VLX. If it uses an extended register we need to use an instruction
4041 // that loads the lower 128/256-bit, but is available with only AVX512F.
4042 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4043                             const TargetRegisterInfo *TRI,
4044                             const MCInstrDesc &LoadDesc,
4045                             const MCInstrDesc &BroadcastDesc,
4046                             unsigned SubIdx) {
4047   unsigned DestReg = MIB->getOperand(0).getReg();
4048   // Check if DestReg is XMM16-31 or YMM16-31.
4049   if (TRI->getEncodingValue(DestReg) < 16) {
4050     // We can use a normal VEX encoded load.
4051     MIB->setDesc(LoadDesc);
4052   } else {
4053     // Use a 128/256-bit VBROADCAST instruction.
4054     MIB->setDesc(BroadcastDesc);
4055     // Change the destination to a 512-bit register.
4056     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
4057     MIB->getOperand(0).setReg(DestReg);
4058   }
4059   return true;
4060 }
4061 
4062 // This is used to handle spills for 128/256-bit registers when we have AVX512,
4063 // but not VLX. If it uses an extended register we need to use an instruction
4064 // that stores the lower 128/256-bit, but is available with only AVX512F.
4065 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4066                              const TargetRegisterInfo *TRI,
4067                              const MCInstrDesc &StoreDesc,
4068                              const MCInstrDesc &ExtractDesc,
4069                              unsigned SubIdx) {
4070   unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
4071   // Check if DestReg is XMM16-31 or YMM16-31.
4072   if (TRI->getEncodingValue(SrcReg) < 16) {
4073     // We can use a normal VEX encoded store.
4074     MIB->setDesc(StoreDesc);
4075   } else {
4076     // Use a VEXTRACTF instruction.
4077     MIB->setDesc(ExtractDesc);
4078     // Change the destination to a 512-bit register.
4079     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
4080     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4081     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
4082   }
4083 
4084   return true;
4085 }
4086 
4087 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4088   MIB->setDesc(Desc);
4089   int64_t ShiftAmt = MIB->getOperand(2).getImm();
4090   // Temporarily remove the immediate so we can add another source register.
4091   MIB->RemoveOperand(2);
4092   // Add the register. Don't copy the kill flag if there is one.
4093   MIB.addReg(MIB->getOperand(1).getReg(),
4094              getUndefRegState(MIB->getOperand(1).isUndef()));
4095   // Add back the immediate.
4096   MIB.addImm(ShiftAmt);
4097   return true;
4098 }
4099 
4100 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
4101   bool HasAVX = Subtarget.hasAVX();
4102   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4103   switch (MI.getOpcode()) {
4104   case X86::MOV32r0:
4105     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4106   case X86::MOV32r1:
4107     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
4108   case X86::MOV32r_1:
4109     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
4110   case X86::MOV32ImmSExti8:
4111   case X86::MOV64ImmSExti8:
4112     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
4113   case X86::SETB_C8r:
4114     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4115   case X86::SETB_C16r:
4116     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4117   case X86::SETB_C32r:
4118     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4119   case X86::SETB_C64r:
4120     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4121   case X86::MMX_SET0:
4122     return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4123   case X86::V_SET0:
4124   case X86::FsFLD0SS:
4125   case X86::FsFLD0SD:
4126     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4127   case X86::AVX_SET0: {
4128     assert(HasAVX && "AVX not supported");
4129     const TargetRegisterInfo *TRI = &getRegisterInfo();
4130     unsigned SrcReg = MIB->getOperand(0).getReg();
4131     unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4132     MIB->getOperand(0).setReg(XReg);
4133     Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4134     MIB.addReg(SrcReg, RegState::ImplicitDefine);
4135     return true;
4136   }
4137   case X86::AVX512_128_SET0:
4138   case X86::AVX512_FsFLD0SS:
4139   case X86::AVX512_FsFLD0SD: {
4140     bool HasVLX = Subtarget.hasVLX();
4141     unsigned SrcReg = MIB->getOperand(0).getReg();
4142     const TargetRegisterInfo *TRI = &getRegisterInfo();
4143     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
4144       return Expand2AddrUndef(MIB,
4145                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4146     // Extended register without VLX. Use a larger XOR.
4147     SrcReg =
4148         TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
4149     MIB->getOperand(0).setReg(SrcReg);
4150     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4151   }
4152   case X86::AVX512_256_SET0:
4153   case X86::AVX512_512_SET0: {
4154     bool HasVLX = Subtarget.hasVLX();
4155     unsigned SrcReg = MIB->getOperand(0).getReg();
4156     const TargetRegisterInfo *TRI = &getRegisterInfo();
4157     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) {
4158       unsigned XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4159       MIB->getOperand(0).setReg(XReg);
4160       Expand2AddrUndef(MIB,
4161                        get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4162       MIB.addReg(SrcReg, RegState::ImplicitDefine);
4163       return true;
4164     }
4165     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4166   }
4167   case X86::V_SETALLONES:
4168     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4169   case X86::AVX2_SETALLONES:
4170     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4171   case X86::AVX1_SETALLONES: {
4172     unsigned Reg = MIB->getOperand(0).getReg();
4173     // VCMPPSYrri with an immediate 0xf should produce VCMPTRUEPS.
4174     MIB->setDesc(get(X86::VCMPPSYrri));
4175     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4176     return true;
4177   }
4178   case X86::AVX512_512_SETALLONES: {
4179     unsigned Reg = MIB->getOperand(0).getReg();
4180     MIB->setDesc(get(X86::VPTERNLOGDZrri));
4181     // VPTERNLOGD needs 3 register inputs and an immediate.
4182     // 0xff will return 1s for any input.
4183     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4184        .addReg(Reg, RegState::Undef).addImm(0xff);
4185     return true;
4186   }
4187   case X86::AVX512_512_SEXT_MASK_32:
4188   case X86::AVX512_512_SEXT_MASK_64: {
4189     unsigned Reg = MIB->getOperand(0).getReg();
4190     unsigned MaskReg = MIB->getOperand(1).getReg();
4191     unsigned MaskState = getRegState(MIB->getOperand(1));
4192     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
4193                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
4194     MI.RemoveOperand(1);
4195     MIB->setDesc(get(Opc));
4196     // VPTERNLOG needs 3 register inputs and an immediate.
4197     // 0xff will return 1s for any input.
4198     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4199        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4200     return true;
4201   }
4202   case X86::VMOVAPSZ128rm_NOVLX:
4203     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4204                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4205   case X86::VMOVUPSZ128rm_NOVLX:
4206     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4207                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4208   case X86::VMOVAPSZ256rm_NOVLX:
4209     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4210                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4211   case X86::VMOVUPSZ256rm_NOVLX:
4212     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4213                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4214   case X86::VMOVAPSZ128mr_NOVLX:
4215     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4216                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4217   case X86::VMOVUPSZ128mr_NOVLX:
4218     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4219                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4220   case X86::VMOVAPSZ256mr_NOVLX:
4221     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4222                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4223   case X86::VMOVUPSZ256mr_NOVLX:
4224     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4225                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4226   case X86::MOV32ri64: {
4227     unsigned Reg = MIB->getOperand(0).getReg();
4228     unsigned Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4229     MI.setDesc(get(X86::MOV32ri));
4230     MIB->getOperand(0).setReg(Reg32);
4231     MIB.addReg(Reg, RegState::ImplicitDefine);
4232     return true;
4233   }
4234 
4235   // KNL does not recognize dependency-breaking idioms for mask registers,
4236   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
4237   // Using %k0 as the undef input register is a performance heuristic based
4238   // on the assumption that %k0 is used less frequently than the other mask
4239   // registers, since it is not usable as a write mask.
4240   // FIXME: A more advanced approach would be to choose the best input mask
4241   // register based on context.
4242   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4243   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4244   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4245   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4246   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4247   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4248   case TargetOpcode::LOAD_STACK_GUARD:
4249     expandLoadStackGuard(MIB, *this);
4250     return true;
4251   case X86::XOR64_FP:
4252   case X86::XOR32_FP:
4253     return expandXorFP(MIB, *this);
4254   case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4255   case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4256   case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4257   case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4258   case X86::ADD8rr_DB:    MIB->setDesc(get(X86::OR8rr));    break;
4259   case X86::ADD16rr_DB:   MIB->setDesc(get(X86::OR16rr));   break;
4260   case X86::ADD32rr_DB:   MIB->setDesc(get(X86::OR32rr));   break;
4261   case X86::ADD64rr_DB:   MIB->setDesc(get(X86::OR64rr));   break;
4262   case X86::ADD8ri_DB:    MIB->setDesc(get(X86::OR8ri));    break;
4263   case X86::ADD16ri_DB:   MIB->setDesc(get(X86::OR16ri));   break;
4264   case X86::ADD32ri_DB:   MIB->setDesc(get(X86::OR32ri));   break;
4265   case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4266   case X86::ADD16ri8_DB:  MIB->setDesc(get(X86::OR16ri8));  break;
4267   case X86::ADD32ri8_DB:  MIB->setDesc(get(X86::OR32ri8));  break;
4268   case X86::ADD64ri8_DB:  MIB->setDesc(get(X86::OR64ri8));  break;
4269   }
4270   return false;
4271 }
4272 
4273 /// Return true for all instructions that only update
4274 /// the first 32 or 64-bits of the destination register and leave the rest
4275 /// unmodified. This can be used to avoid folding loads if the instructions
4276 /// only update part of the destination register, and the non-updated part is
4277 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4278 /// instructions breaks the partial register dependency and it can improve
4279 /// performance. e.g.:
4280 ///
4281 ///   movss (%rdi), %xmm0
4282 ///   cvtss2sd %xmm0, %xmm0
4283 ///
4284 /// Instead of
4285 ///   cvtss2sd (%rdi), %xmm0
4286 ///
4287 /// FIXME: This should be turned into a TSFlags.
4288 ///
4289 static bool hasPartialRegUpdate(unsigned Opcode,
4290                                 const X86Subtarget &Subtarget,
4291                                 bool ForLoadFold = false) {
4292   switch (Opcode) {
4293   case X86::CVTSI2SSrr:
4294   case X86::CVTSI2SSrm:
4295   case X86::CVTSI642SSrr:
4296   case X86::CVTSI642SSrm:
4297   case X86::CVTSI2SDrr:
4298   case X86::CVTSI2SDrm:
4299   case X86::CVTSI642SDrr:
4300   case X86::CVTSI642SDrm:
4301     // Load folding won't effect the undef register update since the input is
4302     // a GPR.
4303     return !ForLoadFold;
4304   case X86::CVTSD2SSrr:
4305   case X86::CVTSD2SSrm:
4306   case X86::CVTSS2SDrr:
4307   case X86::CVTSS2SDrm:
4308   case X86::MOVHPDrm:
4309   case X86::MOVHPSrm:
4310   case X86::MOVLPDrm:
4311   case X86::MOVLPSrm:
4312   case X86::RCPSSr:
4313   case X86::RCPSSm:
4314   case X86::RCPSSr_Int:
4315   case X86::RCPSSm_Int:
4316   case X86::ROUNDSDr:
4317   case X86::ROUNDSDm:
4318   case X86::ROUNDSSr:
4319   case X86::ROUNDSSm:
4320   case X86::RSQRTSSr:
4321   case X86::RSQRTSSm:
4322   case X86::RSQRTSSr_Int:
4323   case X86::RSQRTSSm_Int:
4324   case X86::SQRTSSr:
4325   case X86::SQRTSSm:
4326   case X86::SQRTSSr_Int:
4327   case X86::SQRTSSm_Int:
4328   case X86::SQRTSDr:
4329   case X86::SQRTSDm:
4330   case X86::SQRTSDr_Int:
4331   case X86::SQRTSDm_Int:
4332     return true;
4333   // GPR
4334   case X86::POPCNT32rm:
4335   case X86::POPCNT32rr:
4336   case X86::POPCNT64rm:
4337   case X86::POPCNT64rr:
4338     return Subtarget.hasPOPCNTFalseDeps();
4339   case X86::LZCNT32rm:
4340   case X86::LZCNT32rr:
4341   case X86::LZCNT64rm:
4342   case X86::LZCNT64rr:
4343   case X86::TZCNT32rm:
4344   case X86::TZCNT32rr:
4345   case X86::TZCNT64rm:
4346   case X86::TZCNT64rr:
4347     return Subtarget.hasLZCNTFalseDeps();
4348   }
4349 
4350   return false;
4351 }
4352 
4353 /// Inform the BreakFalseDeps pass how many idle
4354 /// instructions we would like before a partial register update.
4355 unsigned X86InstrInfo::getPartialRegUpdateClearance(
4356     const MachineInstr &MI, unsigned OpNum,
4357     const TargetRegisterInfo *TRI) const {
4358   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode(), Subtarget))
4359     return 0;
4360 
4361   // If MI is marked as reading Reg, the partial register update is wanted.
4362   const MachineOperand &MO = MI.getOperand(0);
4363   unsigned Reg = MO.getReg();
4364   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4365     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
4366       return 0;
4367   } else {
4368     if (MI.readsRegister(Reg, TRI))
4369       return 0;
4370   }
4371 
4372   // If any instructions in the clearance range are reading Reg, insert a
4373   // dependency breaking instruction, which is inexpensive and is likely to
4374   // be hidden in other instruction's cycles.
4375   return PartialRegUpdateClearance;
4376 }
4377 
4378 // Return true for any instruction the copies the high bits of the first source
4379 // operand into the unused high bits of the destination operand.
4380 static bool hasUndefRegUpdate(unsigned Opcode, bool ForLoadFold = false) {
4381   switch (Opcode) {
4382   case X86::VCVTSI2SSrr:
4383   case X86::VCVTSI2SSrm:
4384   case X86::VCVTSI2SSrr_Int:
4385   case X86::VCVTSI2SSrm_Int:
4386   case X86::VCVTSI642SSrr:
4387   case X86::VCVTSI642SSrm:
4388   case X86::VCVTSI642SSrr_Int:
4389   case X86::VCVTSI642SSrm_Int:
4390   case X86::VCVTSI2SDrr:
4391   case X86::VCVTSI2SDrm:
4392   case X86::VCVTSI2SDrr_Int:
4393   case X86::VCVTSI2SDrm_Int:
4394   case X86::VCVTSI642SDrr:
4395   case X86::VCVTSI642SDrm:
4396   case X86::VCVTSI642SDrr_Int:
4397   case X86::VCVTSI642SDrm_Int:
4398   // AVX-512
4399   case X86::VCVTSI2SSZrr:
4400   case X86::VCVTSI2SSZrm:
4401   case X86::VCVTSI2SSZrr_Int:
4402   case X86::VCVTSI2SSZrrb_Int:
4403   case X86::VCVTSI2SSZrm_Int:
4404   case X86::VCVTSI642SSZrr:
4405   case X86::VCVTSI642SSZrm:
4406   case X86::VCVTSI642SSZrr_Int:
4407   case X86::VCVTSI642SSZrrb_Int:
4408   case X86::VCVTSI642SSZrm_Int:
4409   case X86::VCVTSI2SDZrr:
4410   case X86::VCVTSI2SDZrm:
4411   case X86::VCVTSI2SDZrr_Int:
4412   case X86::VCVTSI2SDZrm_Int:
4413   case X86::VCVTSI642SDZrr:
4414   case X86::VCVTSI642SDZrm:
4415   case X86::VCVTSI642SDZrr_Int:
4416   case X86::VCVTSI642SDZrrb_Int:
4417   case X86::VCVTSI642SDZrm_Int:
4418   case X86::VCVTUSI2SSZrr:
4419   case X86::VCVTUSI2SSZrm:
4420   case X86::VCVTUSI2SSZrr_Int:
4421   case X86::VCVTUSI2SSZrrb_Int:
4422   case X86::VCVTUSI2SSZrm_Int:
4423   case X86::VCVTUSI642SSZrr:
4424   case X86::VCVTUSI642SSZrm:
4425   case X86::VCVTUSI642SSZrr_Int:
4426   case X86::VCVTUSI642SSZrrb_Int:
4427   case X86::VCVTUSI642SSZrm_Int:
4428   case X86::VCVTUSI2SDZrr:
4429   case X86::VCVTUSI2SDZrm:
4430   case X86::VCVTUSI2SDZrr_Int:
4431   case X86::VCVTUSI2SDZrm_Int:
4432   case X86::VCVTUSI642SDZrr:
4433   case X86::VCVTUSI642SDZrm:
4434   case X86::VCVTUSI642SDZrr_Int:
4435   case X86::VCVTUSI642SDZrrb_Int:
4436   case X86::VCVTUSI642SDZrm_Int:
4437     // Load folding won't effect the undef register update since the input is
4438     // a GPR.
4439     return !ForLoadFold;
4440   case X86::VCVTSD2SSrr:
4441   case X86::VCVTSD2SSrm:
4442   case X86::VCVTSD2SSrr_Int:
4443   case X86::VCVTSD2SSrm_Int:
4444   case X86::VCVTSS2SDrr:
4445   case X86::VCVTSS2SDrm:
4446   case X86::VCVTSS2SDrr_Int:
4447   case X86::VCVTSS2SDrm_Int:
4448   case X86::VRCPSSr:
4449   case X86::VRCPSSr_Int:
4450   case X86::VRCPSSm:
4451   case X86::VRCPSSm_Int:
4452   case X86::VROUNDSDr:
4453   case X86::VROUNDSDm:
4454   case X86::VROUNDSDr_Int:
4455   case X86::VROUNDSDm_Int:
4456   case X86::VROUNDSSr:
4457   case X86::VROUNDSSm:
4458   case X86::VROUNDSSr_Int:
4459   case X86::VROUNDSSm_Int:
4460   case X86::VRSQRTSSr:
4461   case X86::VRSQRTSSr_Int:
4462   case X86::VRSQRTSSm:
4463   case X86::VRSQRTSSm_Int:
4464   case X86::VSQRTSSr:
4465   case X86::VSQRTSSr_Int:
4466   case X86::VSQRTSSm:
4467   case X86::VSQRTSSm_Int:
4468   case X86::VSQRTSDr:
4469   case X86::VSQRTSDr_Int:
4470   case X86::VSQRTSDm:
4471   case X86::VSQRTSDm_Int:
4472   // AVX-512
4473   case X86::VCVTSD2SSZrr:
4474   case X86::VCVTSD2SSZrr_Int:
4475   case X86::VCVTSD2SSZrrb_Int:
4476   case X86::VCVTSD2SSZrm:
4477   case X86::VCVTSD2SSZrm_Int:
4478   case X86::VCVTSS2SDZrr:
4479   case X86::VCVTSS2SDZrr_Int:
4480   case X86::VCVTSS2SDZrrb_Int:
4481   case X86::VCVTSS2SDZrm:
4482   case X86::VCVTSS2SDZrm_Int:
4483   case X86::VGETEXPSDZr:
4484   case X86::VGETEXPSDZrb:
4485   case X86::VGETEXPSDZm:
4486   case X86::VGETEXPSSZr:
4487   case X86::VGETEXPSSZrb:
4488   case X86::VGETEXPSSZm:
4489   case X86::VGETMANTSDZrri:
4490   case X86::VGETMANTSDZrrib:
4491   case X86::VGETMANTSDZrmi:
4492   case X86::VGETMANTSSZrri:
4493   case X86::VGETMANTSSZrrib:
4494   case X86::VGETMANTSSZrmi:
4495   case X86::VRNDSCALESDZr:
4496   case X86::VRNDSCALESDZr_Int:
4497   case X86::VRNDSCALESDZrb_Int:
4498   case X86::VRNDSCALESDZm:
4499   case X86::VRNDSCALESDZm_Int:
4500   case X86::VRNDSCALESSZr:
4501   case X86::VRNDSCALESSZr_Int:
4502   case X86::VRNDSCALESSZrb_Int:
4503   case X86::VRNDSCALESSZm:
4504   case X86::VRNDSCALESSZm_Int:
4505   case X86::VRCP14SDZrr:
4506   case X86::VRCP14SDZrm:
4507   case X86::VRCP14SSZrr:
4508   case X86::VRCP14SSZrm:
4509   case X86::VRCP28SDZr:
4510   case X86::VRCP28SDZrb:
4511   case X86::VRCP28SDZm:
4512   case X86::VRCP28SSZr:
4513   case X86::VRCP28SSZrb:
4514   case X86::VRCP28SSZm:
4515   case X86::VREDUCESSZrmi:
4516   case X86::VREDUCESSZrri:
4517   case X86::VREDUCESSZrrib:
4518   case X86::VRSQRT14SDZrr:
4519   case X86::VRSQRT14SDZrm:
4520   case X86::VRSQRT14SSZrr:
4521   case X86::VRSQRT14SSZrm:
4522   case X86::VRSQRT28SDZr:
4523   case X86::VRSQRT28SDZrb:
4524   case X86::VRSQRT28SDZm:
4525   case X86::VRSQRT28SSZr:
4526   case X86::VRSQRT28SSZrb:
4527   case X86::VRSQRT28SSZm:
4528   case X86::VSQRTSSZr:
4529   case X86::VSQRTSSZr_Int:
4530   case X86::VSQRTSSZrb_Int:
4531   case X86::VSQRTSSZm:
4532   case X86::VSQRTSSZm_Int:
4533   case X86::VSQRTSDZr:
4534   case X86::VSQRTSDZr_Int:
4535   case X86::VSQRTSDZrb_Int:
4536   case X86::VSQRTSDZm:
4537   case X86::VSQRTSDZm_Int:
4538     return true;
4539   }
4540 
4541   return false;
4542 }
4543 
4544 /// Inform the BreakFalseDeps pass how many idle instructions we would like
4545 /// before certain undef register reads.
4546 ///
4547 /// This catches the VCVTSI2SD family of instructions:
4548 ///
4549 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
4550 ///
4551 /// We should to be careful *not* to catch VXOR idioms which are presumably
4552 /// handled specially in the pipeline:
4553 ///
4554 /// vxorps undef %xmm1, undef %xmm1, %xmm1
4555 ///
4556 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4557 /// high bits that are passed-through are not live.
4558 unsigned
4559 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
4560                                    const TargetRegisterInfo *TRI) const {
4561   if (!hasUndefRegUpdate(MI.getOpcode()))
4562     return 0;
4563 
4564   // Set the OpNum parameter to the first source operand.
4565   OpNum = 1;
4566 
4567   const MachineOperand &MO = MI.getOperand(OpNum);
4568   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4569     return UndefRegClearance;
4570   }
4571   return 0;
4572 }
4573 
4574 void X86InstrInfo::breakPartialRegDependency(
4575     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4576   unsigned Reg = MI.getOperand(OpNum).getReg();
4577   // If MI kills this register, the false dependence is already broken.
4578   if (MI.killsRegister(Reg, TRI))
4579     return;
4580 
4581   if (X86::VR128RegClass.contains(Reg)) {
4582     // These instructions are all floating point domain, so xorps is the best
4583     // choice.
4584     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
4585     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4586         .addReg(Reg, RegState::Undef)
4587         .addReg(Reg, RegState::Undef);
4588     MI.addRegisterKilled(Reg, TRI, true);
4589   } else if (X86::VR256RegClass.contains(Reg)) {
4590     // Use vxorps to clear the full ymm register.
4591     // It wants to read and write the xmm sub-register.
4592     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4593     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4594         .addReg(XReg, RegState::Undef)
4595         .addReg(XReg, RegState::Undef)
4596         .addReg(Reg, RegState::ImplicitDefine);
4597     MI.addRegisterKilled(Reg, TRI, true);
4598   } else if (X86::GR64RegClass.contains(Reg)) {
4599     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
4600     // as well.
4601     unsigned XReg = TRI->getSubReg(Reg, X86::sub_32bit);
4602     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4603         .addReg(XReg, RegState::Undef)
4604         .addReg(XReg, RegState::Undef)
4605         .addReg(Reg, RegState::ImplicitDefine);
4606     MI.addRegisterKilled(Reg, TRI, true);
4607   } else if (X86::GR32RegClass.contains(Reg)) {
4608     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
4609         .addReg(Reg, RegState::Undef)
4610         .addReg(Reg, RegState::Undef);
4611     MI.addRegisterKilled(Reg, TRI, true);
4612   }
4613 }
4614 
4615 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
4616                         int PtrOffset = 0) {
4617   unsigned NumAddrOps = MOs.size();
4618 
4619   if (NumAddrOps < 4) {
4620     // FrameIndex only - add an immediate offset (whether its zero or not).
4621     for (unsigned i = 0; i != NumAddrOps; ++i)
4622       MIB.add(MOs[i]);
4623     addOffset(MIB, PtrOffset);
4624   } else {
4625     // General Memory Addressing - we need to add any offset to an existing
4626     // offset.
4627     assert(MOs.size() == 5 && "Unexpected memory operand list length");
4628     for (unsigned i = 0; i != NumAddrOps; ++i) {
4629       const MachineOperand &MO = MOs[i];
4630       if (i == 3 && PtrOffset != 0) {
4631         MIB.addDisp(MO, PtrOffset);
4632       } else {
4633         MIB.add(MO);
4634       }
4635     }
4636   }
4637 }
4638 
4639 static void updateOperandRegConstraints(MachineFunction &MF,
4640                                         MachineInstr &NewMI,
4641                                         const TargetInstrInfo &TII) {
4642   MachineRegisterInfo &MRI = MF.getRegInfo();
4643   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
4644 
4645   for (int Idx : llvm::seq<int>(0, NewMI.getNumOperands())) {
4646     MachineOperand &MO = NewMI.getOperand(Idx);
4647     // We only need to update constraints on virtual register operands.
4648     if (!MO.isReg())
4649       continue;
4650     unsigned Reg = MO.getReg();
4651     if (!TRI.isVirtualRegister(Reg))
4652       continue;
4653 
4654     auto *NewRC = MRI.constrainRegClass(
4655         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
4656     if (!NewRC) {
4657       LLVM_DEBUG(
4658           dbgs() << "WARNING: Unable to update register constraint for operand "
4659                  << Idx << " of instruction:\n";
4660           NewMI.dump(); dbgs() << "\n");
4661     }
4662   }
4663 }
4664 
4665 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4666                                      ArrayRef<MachineOperand> MOs,
4667                                      MachineBasicBlock::iterator InsertPt,
4668                                      MachineInstr &MI,
4669                                      const TargetInstrInfo &TII) {
4670   // Create the base instruction with the memory operand as the first part.
4671   // Omit the implicit operands, something BuildMI can't do.
4672   MachineInstr *NewMI =
4673       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4674   MachineInstrBuilder MIB(MF, NewMI);
4675   addOperands(MIB, MOs);
4676 
4677   // Loop over the rest of the ri operands, converting them over.
4678   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
4679   for (unsigned i = 0; i != NumOps; ++i) {
4680     MachineOperand &MO = MI.getOperand(i + 2);
4681     MIB.add(MO);
4682   }
4683   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
4684     MachineOperand &MO = MI.getOperand(i);
4685     MIB.add(MO);
4686   }
4687 
4688   updateOperandRegConstraints(MF, *NewMI, TII);
4689 
4690   MachineBasicBlock *MBB = InsertPt->getParent();
4691   MBB->insert(InsertPt, NewMI);
4692 
4693   return MIB;
4694 }
4695 
4696 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4697                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
4698                               MachineBasicBlock::iterator InsertPt,
4699                               MachineInstr &MI, const TargetInstrInfo &TII,
4700                               int PtrOffset = 0) {
4701   // Omit the implicit operands, something BuildMI can't do.
4702   MachineInstr *NewMI =
4703       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4704   MachineInstrBuilder MIB(MF, NewMI);
4705 
4706   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4707     MachineOperand &MO = MI.getOperand(i);
4708     if (i == OpNo) {
4709       assert(MO.isReg() && "Expected to fold into reg operand!");
4710       addOperands(MIB, MOs, PtrOffset);
4711     } else {
4712       MIB.add(MO);
4713     }
4714   }
4715 
4716   updateOperandRegConstraints(MF, *NewMI, TII);
4717 
4718   MachineBasicBlock *MBB = InsertPt->getParent();
4719   MBB->insert(InsertPt, NewMI);
4720 
4721   return MIB;
4722 }
4723 
4724 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4725                                 ArrayRef<MachineOperand> MOs,
4726                                 MachineBasicBlock::iterator InsertPt,
4727                                 MachineInstr &MI) {
4728   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4729                                     MI.getDebugLoc(), TII.get(Opcode));
4730   addOperands(MIB, MOs);
4731   return MIB.addImm(0);
4732 }
4733 
4734 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
4735     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4736     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4737     unsigned Size, unsigned Align) const {
4738   switch (MI.getOpcode()) {
4739   case X86::INSERTPSrr:
4740   case X86::VINSERTPSrr:
4741   case X86::VINSERTPSZrr:
4742     // Attempt to convert the load of inserted vector into a fold load
4743     // of a single float.
4744     if (OpNum == 2) {
4745       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
4746       unsigned ZMask = Imm & 15;
4747       unsigned DstIdx = (Imm >> 4) & 3;
4748       unsigned SrcIdx = (Imm >> 6) & 3;
4749 
4750       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4751       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4752       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4753       if (Size <= RCSize && 4 <= Align) {
4754         int PtrOffset = SrcIdx * 4;
4755         unsigned NewImm = (DstIdx << 4) | ZMask;
4756         unsigned NewOpCode =
4757             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
4758             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
4759                                                     X86::INSERTPSrm;
4760         MachineInstr *NewMI =
4761             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
4762         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
4763         return NewMI;
4764       }
4765     }
4766     break;
4767   case X86::MOVHLPSrr:
4768   case X86::VMOVHLPSrr:
4769   case X86::VMOVHLPSZrr:
4770     // Move the upper 64-bits of the second operand to the lower 64-bits.
4771     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
4772     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
4773     if (OpNum == 2) {
4774       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4775       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4776       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4777       if (Size <= RCSize && 8 <= Align) {
4778         unsigned NewOpCode =
4779             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
4780             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
4781                                                    X86::MOVLPSrm;
4782         MachineInstr *NewMI =
4783             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
4784         return NewMI;
4785       }
4786     }
4787     break;
4788   };
4789 
4790   return nullptr;
4791 }
4792 
4793 static bool shouldPreventUndefRegUpdateMemFold(MachineFunction &MF,
4794                                                MachineInstr &MI) {
4795   if (!hasUndefRegUpdate(MI.getOpcode(), /*ForLoadFold*/true) ||
4796       !MI.getOperand(1).isReg())
4797     return false;
4798 
4799   // The are two cases we need to handle depending on where in the pipeline
4800   // the folding attempt is being made.
4801   // -Register has the undef flag set.
4802   // -Register is produced by the IMPLICIT_DEF instruction.
4803 
4804   if (MI.getOperand(1).isUndef())
4805     return true;
4806 
4807   MachineRegisterInfo &RegInfo = MF.getRegInfo();
4808   MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
4809   return VRegDef && VRegDef->isImplicitDef();
4810 }
4811 
4812 
4813 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
4814     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
4815     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4816     unsigned Size, unsigned Align, bool AllowCommute) const {
4817   bool isSlowTwoMemOps = Subtarget.slowTwoMemOps();
4818   bool isTwoAddrFold = false;
4819 
4820   // For CPUs that favor the register form of a call or push,
4821   // do not fold loads into calls or pushes, unless optimizing for size
4822   // aggressively.
4823   if (isSlowTwoMemOps && !MF.getFunction().optForMinSize() &&
4824       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
4825        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
4826        MI.getOpcode() == X86::PUSH64r))
4827     return nullptr;
4828 
4829   // Avoid partial and undef register update stalls unless optimizing for size.
4830   if (!MF.getFunction().optForSize() &&
4831       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
4832        shouldPreventUndefRegUpdateMemFold(MF, MI)))
4833     return nullptr;
4834 
4835   unsigned NumOps = MI.getDesc().getNumOperands();
4836   bool isTwoAddr =
4837       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4838 
4839   // FIXME: AsmPrinter doesn't know how to handle
4840   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4841   if (MI.getOpcode() == X86::ADD32ri &&
4842       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4843     return nullptr;
4844 
4845   // GOTTPOFF relocation loads can only be folded into add instructions.
4846   // FIXME: Need to exclude other relocations that only support specific
4847   // instructions.
4848   if (MOs.size() == X86::AddrNumOperands &&
4849       MOs[X86::AddrDisp].getTargetFlags() == X86II::MO_GOTTPOFF &&
4850       MI.getOpcode() != X86::ADD64rr)
4851     return nullptr;
4852 
4853   MachineInstr *NewMI = nullptr;
4854 
4855   // Attempt to fold any custom cases we have.
4856   if (MachineInstr *CustomMI =
4857           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
4858     return CustomMI;
4859 
4860   const X86MemoryFoldTableEntry *I = nullptr;
4861 
4862   // Folding a memory location into the two-address part of a two-address
4863   // instruction is different than folding it other places.  It requires
4864   // replacing the *two* registers with the memory location.
4865   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
4866       MI.getOperand(1).isReg() &&
4867       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4868     I = lookupTwoAddrFoldTable(MI.getOpcode());
4869     isTwoAddrFold = true;
4870   } else {
4871     if (OpNum == 0) {
4872       if (MI.getOpcode() == X86::MOV32r0) {
4873         NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
4874         if (NewMI)
4875           return NewMI;
4876       }
4877     }
4878 
4879     I = lookupFoldTable(MI.getOpcode(), OpNum);
4880   }
4881 
4882   if (I != nullptr) {
4883     unsigned Opcode = I->DstOp;
4884     unsigned MinAlign = (I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4885     if (Align < MinAlign)
4886       return nullptr;
4887     bool NarrowToMOV32rm = false;
4888     if (Size) {
4889       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4890       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
4891                                                   &RI, MF);
4892       unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
4893       if (Size < RCSize) {
4894         // Check if it's safe to fold the load. If the size of the object is
4895         // narrower than the load width, then it's not.
4896         if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4897           return nullptr;
4898         // If this is a 64-bit load, but the spill slot is 32, then we can do
4899         // a 32-bit load which is implicitly zero-extended. This likely is
4900         // due to live interval analysis remat'ing a load from stack slot.
4901         if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4902           return nullptr;
4903         Opcode = X86::MOV32rm;
4904         NarrowToMOV32rm = true;
4905       }
4906     }
4907 
4908     if (isTwoAddrFold)
4909       NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
4910     else
4911       NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
4912 
4913     if (NarrowToMOV32rm) {
4914       // If this is the special case where we use a MOV32rm to load a 32-bit
4915       // value and zero-extend the top bits. Change the destination register
4916       // to a 32-bit one.
4917       unsigned DstReg = NewMI->getOperand(0).getReg();
4918       if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4919         NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4920       else
4921         NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4922     }
4923     return NewMI;
4924   }
4925 
4926   // If the instruction and target operand are commutable, commute the
4927   // instruction and try again.
4928   if (AllowCommute) {
4929     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
4930     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4931       bool HasDef = MI.getDesc().getNumDefs();
4932       unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
4933       unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4934       unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
4935       bool Tied1 =
4936           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4937       bool Tied2 =
4938           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4939 
4940       // If either of the commutable operands are tied to the destination
4941       // then we can not commute + fold.
4942       if ((HasDef && Reg0 == Reg1 && Tied1) ||
4943           (HasDef && Reg0 == Reg2 && Tied2))
4944         return nullptr;
4945 
4946       MachineInstr *CommutedMI =
4947           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4948       if (!CommutedMI) {
4949         // Unable to commute.
4950         return nullptr;
4951       }
4952       if (CommutedMI != &MI) {
4953         // New instruction. We can't fold from this.
4954         CommutedMI->eraseFromParent();
4955         return nullptr;
4956       }
4957 
4958       // Attempt to fold with the commuted version of the instruction.
4959       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
4960                                     Size, Align, /*AllowCommute=*/false);
4961       if (NewMI)
4962         return NewMI;
4963 
4964       // Folding failed again - undo the commute before returning.
4965       MachineInstr *UncommutedMI =
4966           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
4967       if (!UncommutedMI) {
4968         // Unable to commute.
4969         return nullptr;
4970       }
4971       if (UncommutedMI != &MI) {
4972         // New instruction. It doesn't need to be kept.
4973         UncommutedMI->eraseFromParent();
4974         return nullptr;
4975       }
4976 
4977       // Return here to prevent duplicate fuse failure report.
4978       return nullptr;
4979     }
4980   }
4981 
4982   // No fusion
4983   if (PrintFailedFusing && !MI.isCopy())
4984     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
4985   return nullptr;
4986 }
4987 
4988 MachineInstr *
4989 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
4990                                     ArrayRef<unsigned> Ops,
4991                                     MachineBasicBlock::iterator InsertPt,
4992                                     int FrameIndex, LiveIntervals *LIS) const {
4993   // Check switch flag
4994   if (NoFusing)
4995     return nullptr;
4996 
4997   // Avoid partial and undef register update stalls unless optimizing for size.
4998   if (!MF.getFunction().optForSize() &&
4999       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5000        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5001     return nullptr;
5002 
5003   // Don't fold subreg spills, or reloads that use a high subreg.
5004   for (auto Op : Ops) {
5005     MachineOperand &MO = MI.getOperand(Op);
5006     auto SubReg = MO.getSubReg();
5007     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
5008       return nullptr;
5009   }
5010 
5011   const MachineFrameInfo &MFI = MF.getFrameInfo();
5012   unsigned Size = MFI.getObjectSize(FrameIndex);
5013   unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
5014   // If the function stack isn't realigned we don't want to fold instructions
5015   // that need increased alignment.
5016   if (!RI.needsStackRealignment(MF))
5017     Alignment =
5018         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
5019   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5020     unsigned NewOpc = 0;
5021     unsigned RCSize = 0;
5022     switch (MI.getOpcode()) {
5023     default: return nullptr;
5024     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5025     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5026     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5027     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5028     }
5029     // Check if it's safe to fold the load. If the size of the object is
5030     // narrower than the load width, then it's not.
5031     if (Size < RCSize)
5032       return nullptr;
5033     // Change to CMPXXri r, 0 first.
5034     MI.setDesc(get(NewOpc));
5035     MI.getOperand(1).ChangeToImmediate(0);
5036   } else if (Ops.size() != 1)
5037     return nullptr;
5038 
5039   return foldMemoryOperandImpl(MF, MI, Ops[0],
5040                                MachineOperand::CreateFI(FrameIndex), InsertPt,
5041                                Size, Alignment, /*AllowCommute=*/true);
5042 }
5043 
5044 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5045 /// because the latter uses contents that wouldn't be defined in the folded
5046 /// version.  For instance, this transformation isn't legal:
5047 ///   movss (%rdi), %xmm0
5048 ///   addps %xmm0, %xmm0
5049 /// ->
5050 ///   addps (%rdi), %xmm0
5051 ///
5052 /// But this one is:
5053 ///   movss (%rdi), %xmm0
5054 ///   addss %xmm0, %xmm0
5055 /// ->
5056 ///   addss (%rdi), %xmm0
5057 ///
5058 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5059                                              const MachineInstr &UserMI,
5060                                              const MachineFunction &MF) {
5061   unsigned Opc = LoadMI.getOpcode();
5062   unsigned UserOpc = UserMI.getOpcode();
5063   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5064   const TargetRegisterClass *RC =
5065       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5066   unsigned RegSize = TRI.getRegSizeInBits(*RC);
5067 
5068   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
5069       RegSize > 32) {
5070     // These instructions only load 32 bits, we can't fold them if the
5071     // destination register is wider than 32 bits (4 bytes), and its user
5072     // instruction isn't scalar (SS).
5073     switch (UserOpc) {
5074     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
5075     case X86::CMPSSrr_Int: case X86::VCMPSSrr_Int: case X86::VCMPSSZrr_Int:
5076     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
5077     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
5078     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
5079     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
5080     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
5081     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
5082     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
5083     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
5084     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
5085     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
5086     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
5087     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
5088     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
5089     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
5090     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
5091     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
5092     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
5093     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
5094     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
5095     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
5096     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
5097     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
5098     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
5099     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
5100     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
5101     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
5102     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
5103     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
5104     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
5105     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
5106     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
5107     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
5108     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
5109     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
5110     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
5111     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
5112     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
5113       return false;
5114     default:
5115       return true;
5116     }
5117   }
5118 
5119   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
5120       RegSize > 64) {
5121     // These instructions only load 64 bits, we can't fold them if the
5122     // destination register is wider than 64 bits (8 bytes), and its user
5123     // instruction isn't scalar (SD).
5124     switch (UserOpc) {
5125     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
5126     case X86::CMPSDrr_Int: case X86::VCMPSDrr_Int: case X86::VCMPSDZrr_Int:
5127     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
5128     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
5129     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
5130     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
5131     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
5132     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
5133     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
5134     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
5135     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
5136     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
5137     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
5138     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
5139     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
5140     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
5141     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
5142     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
5143     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
5144     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
5145     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
5146     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
5147     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
5148     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
5149     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
5150     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
5151     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
5152     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
5153     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
5154     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
5155     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
5156     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
5157     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
5158     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
5159     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
5160     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
5161     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
5162     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
5163     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
5164       return false;
5165     default:
5166       return true;
5167     }
5168   }
5169 
5170   return false;
5171 }
5172 
5173 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5174     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
5175     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
5176     LiveIntervals *LIS) const {
5177 
5178   // TODO: Support the case where LoadMI loads a wide register, but MI
5179   // only uses a subreg.
5180   for (auto Op : Ops) {
5181     if (MI.getOperand(Op).getSubReg())
5182       return nullptr;
5183   }
5184 
5185   // If loading from a FrameIndex, fold directly from the FrameIndex.
5186   unsigned NumOps = LoadMI.getDesc().getNumOperands();
5187   int FrameIndex;
5188   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5189     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5190       return nullptr;
5191     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
5192   }
5193 
5194   // Check switch flag
5195   if (NoFusing) return nullptr;
5196 
5197   // Avoid partial and undef register update stalls unless optimizing for size.
5198   if (!MF.getFunction().optForSize() &&
5199       (hasPartialRegUpdate(MI.getOpcode(), Subtarget, /*ForLoadFold*/true) ||
5200        shouldPreventUndefRegUpdateMemFold(MF, MI)))
5201     return nullptr;
5202 
5203   // Determine the alignment of the load.
5204   unsigned Alignment = 0;
5205   if (LoadMI.hasOneMemOperand())
5206     Alignment = (*LoadMI.memoperands_begin())->getAlignment();
5207   else
5208     switch (LoadMI.getOpcode()) {
5209     case X86::AVX512_512_SET0:
5210     case X86::AVX512_512_SETALLONES:
5211       Alignment = 64;
5212       break;
5213     case X86::AVX2_SETALLONES:
5214     case X86::AVX1_SETALLONES:
5215     case X86::AVX_SET0:
5216     case X86::AVX512_256_SET0:
5217       Alignment = 32;
5218       break;
5219     case X86::V_SET0:
5220     case X86::V_SETALLONES:
5221     case X86::AVX512_128_SET0:
5222       Alignment = 16;
5223       break;
5224     case X86::MMX_SET0:
5225     case X86::FsFLD0SD:
5226     case X86::AVX512_FsFLD0SD:
5227       Alignment = 8;
5228       break;
5229     case X86::FsFLD0SS:
5230     case X86::AVX512_FsFLD0SS:
5231       Alignment = 4;
5232       break;
5233     default:
5234       return nullptr;
5235     }
5236   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5237     unsigned NewOpc = 0;
5238     switch (MI.getOpcode()) {
5239     default: return nullptr;
5240     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
5241     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5242     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5243     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5244     }
5245     // Change to CMPXXri r, 0 first.
5246     MI.setDesc(get(NewOpc));
5247     MI.getOperand(1).ChangeToImmediate(0);
5248   } else if (Ops.size() != 1)
5249     return nullptr;
5250 
5251   // Make sure the subregisters match.
5252   // Otherwise we risk changing the size of the load.
5253   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5254     return nullptr;
5255 
5256   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5257   switch (LoadMI.getOpcode()) {
5258   case X86::MMX_SET0:
5259   case X86::V_SET0:
5260   case X86::V_SETALLONES:
5261   case X86::AVX2_SETALLONES:
5262   case X86::AVX1_SETALLONES:
5263   case X86::AVX_SET0:
5264   case X86::AVX512_128_SET0:
5265   case X86::AVX512_256_SET0:
5266   case X86::AVX512_512_SET0:
5267   case X86::AVX512_512_SETALLONES:
5268   case X86::FsFLD0SD:
5269   case X86::AVX512_FsFLD0SD:
5270   case X86::FsFLD0SS:
5271   case X86::AVX512_FsFLD0SS: {
5272     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5273     // Create a constant-pool entry and operands to load from it.
5274 
5275     // Medium and large mode can't fold loads this way.
5276     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5277         MF.getTarget().getCodeModel() != CodeModel::Kernel)
5278       return nullptr;
5279 
5280     // x86-32 PIC requires a PIC base register for constant pools.
5281     unsigned PICBase = 0;
5282     if (MF.getTarget().isPositionIndependent()) {
5283       if (Subtarget.is64Bit())
5284         PICBase = X86::RIP;
5285       else
5286         // FIXME: PICBase = getGlobalBaseReg(&MF);
5287         // This doesn't work for several reasons.
5288         // 1. GlobalBaseReg may have been spilled.
5289         // 2. It may not be live at MI.
5290         return nullptr;
5291     }
5292 
5293     // Create a constant-pool entry.
5294     MachineConstantPool &MCP = *MF.getConstantPool();
5295     Type *Ty;
5296     unsigned Opc = LoadMI.getOpcode();
5297     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
5298       Ty = Type::getFloatTy(MF.getFunction().getContext());
5299     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
5300       Ty = Type::getDoubleTy(MF.getFunction().getContext());
5301     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
5302       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()),16);
5303     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
5304              Opc == X86::AVX512_256_SET0 || Opc == X86::AVX1_SETALLONES)
5305       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 8);
5306     else if (Opc == X86::MMX_SET0)
5307       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 2);
5308     else
5309       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction().getContext()), 4);
5310 
5311     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
5312                       Opc == X86::AVX512_512_SETALLONES ||
5313                       Opc == X86::AVX1_SETALLONES);
5314     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5315                                     Constant::getNullValue(Ty);
5316     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5317 
5318     // Create operands to load from the constant pool entry.
5319     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5320     MOs.push_back(MachineOperand::CreateImm(1));
5321     MOs.push_back(MachineOperand::CreateReg(0, false));
5322     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5323     MOs.push_back(MachineOperand::CreateReg(0, false));
5324     break;
5325   }
5326   default: {
5327     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
5328       return nullptr;
5329 
5330     // Folding a normal load. Just copy the load's address operands.
5331     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
5332                LoadMI.operands_begin() + NumOps);
5333     break;
5334   }
5335   }
5336   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
5337                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
5338 }
5339 
5340 static SmallVector<MachineMemOperand *, 2>
5341 extractLoadMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5342   SmallVector<MachineMemOperand *, 2> LoadMMOs;
5343 
5344   for (MachineMemOperand *MMO : MMOs) {
5345     if (!MMO->isLoad())
5346       continue;
5347 
5348     if (!MMO->isStore()) {
5349       // Reuse the MMO.
5350       LoadMMOs.push_back(MMO);
5351     } else {
5352       // Clone the MMO and unset the store flag.
5353       LoadMMOs.push_back(MF.getMachineMemOperand(
5354           MMO->getPointerInfo(), MMO->getFlags() & ~MachineMemOperand::MOStore,
5355           MMO->getSize(), MMO->getBaseAlignment(), MMO->getAAInfo(), nullptr,
5356           MMO->getSyncScopeID(), MMO->getOrdering(),
5357           MMO->getFailureOrdering()));
5358     }
5359   }
5360 
5361   return LoadMMOs;
5362 }
5363 
5364 static SmallVector<MachineMemOperand *, 2>
5365 extractStoreMMOs(ArrayRef<MachineMemOperand *> MMOs, MachineFunction &MF) {
5366   SmallVector<MachineMemOperand *, 2> StoreMMOs;
5367 
5368   for (MachineMemOperand *MMO : MMOs) {
5369     if (!MMO->isStore())
5370       continue;
5371 
5372     if (!MMO->isLoad()) {
5373       // Reuse the MMO.
5374       StoreMMOs.push_back(MMO);
5375     } else {
5376       // Clone the MMO and unset the load flag.
5377       StoreMMOs.push_back(MF.getMachineMemOperand(
5378           MMO->getPointerInfo(), MMO->getFlags() & ~MachineMemOperand::MOLoad,
5379           MMO->getSize(), MMO->getBaseAlignment(), MMO->getAAInfo(), nullptr,
5380           MMO->getSyncScopeID(), MMO->getOrdering(),
5381           MMO->getFailureOrdering()));
5382     }
5383   }
5384 
5385   return StoreMMOs;
5386 }
5387 
5388 bool X86InstrInfo::unfoldMemoryOperand(
5389     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
5390     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
5391   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(MI.getOpcode());
5392   if (I == nullptr)
5393     return false;
5394   unsigned Opc = I->DstOp;
5395   unsigned Index = I->Flags & TB_INDEX_MASK;
5396   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5397   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5398   if (UnfoldLoad && !FoldedLoad)
5399     return false;
5400   UnfoldLoad &= FoldedLoad;
5401   if (UnfoldStore && !FoldedStore)
5402     return false;
5403   UnfoldStore &= FoldedStore;
5404 
5405   const MCInstrDesc &MCID = get(Opc);
5406   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5407   // TODO: Check if 32-byte or greater accesses are slow too?
5408   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
5409       Subtarget.isUnalignedMem16Slow())
5410     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5411     // conservatively assume the address is unaligned. That's bad for
5412     // performance.
5413     return false;
5414   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5415   SmallVector<MachineOperand,2> BeforeOps;
5416   SmallVector<MachineOperand,2> AfterOps;
5417   SmallVector<MachineOperand,4> ImpOps;
5418   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5419     MachineOperand &Op = MI.getOperand(i);
5420     if (i >= Index && i < Index + X86::AddrNumOperands)
5421       AddrOps.push_back(Op);
5422     else if (Op.isReg() && Op.isImplicit())
5423       ImpOps.push_back(Op);
5424     else if (i < Index)
5425       BeforeOps.push_back(Op);
5426     else if (i > Index)
5427       AfterOps.push_back(Op);
5428   }
5429 
5430   // Emit the load instruction.
5431   if (UnfoldLoad) {
5432     auto MMOs = extractLoadMMOs(MI.memoperands(), MF);
5433     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs, NewMIs);
5434     if (UnfoldStore) {
5435       // Address operands cannot be marked isKill.
5436       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5437         MachineOperand &MO = NewMIs[0]->getOperand(i);
5438         if (MO.isReg())
5439           MO.setIsKill(false);
5440       }
5441     }
5442   }
5443 
5444   // Emit the data processing instruction.
5445   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
5446   MachineInstrBuilder MIB(MF, DataMI);
5447 
5448   if (FoldedStore)
5449     MIB.addReg(Reg, RegState::Define);
5450   for (MachineOperand &BeforeOp : BeforeOps)
5451     MIB.add(BeforeOp);
5452   if (FoldedLoad)
5453     MIB.addReg(Reg);
5454   for (MachineOperand &AfterOp : AfterOps)
5455     MIB.add(AfterOp);
5456   for (MachineOperand &ImpOp : ImpOps) {
5457     MIB.addReg(ImpOp.getReg(),
5458                getDefRegState(ImpOp.isDef()) |
5459                RegState::Implicit |
5460                getKillRegState(ImpOp.isKill()) |
5461                getDeadRegState(ImpOp.isDead()) |
5462                getUndefRegState(ImpOp.isUndef()));
5463   }
5464   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5465   switch (DataMI->getOpcode()) {
5466   default: break;
5467   case X86::CMP64ri32:
5468   case X86::CMP64ri8:
5469   case X86::CMP32ri:
5470   case X86::CMP32ri8:
5471   case X86::CMP16ri:
5472   case X86::CMP16ri8:
5473   case X86::CMP8ri: {
5474     MachineOperand &MO0 = DataMI->getOperand(0);
5475     MachineOperand &MO1 = DataMI->getOperand(1);
5476     if (MO1.getImm() == 0) {
5477       unsigned NewOpc;
5478       switch (DataMI->getOpcode()) {
5479       default: llvm_unreachable("Unreachable!");
5480       case X86::CMP64ri8:
5481       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5482       case X86::CMP32ri8:
5483       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
5484       case X86::CMP16ri8:
5485       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
5486       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
5487       }
5488       DataMI->setDesc(get(NewOpc));
5489       MO1.ChangeToRegister(MO0.getReg(), false);
5490     }
5491   }
5492   }
5493   NewMIs.push_back(DataMI);
5494 
5495   // Emit the store instruction.
5496   if (UnfoldStore) {
5497     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5498     auto MMOs = extractStoreMMOs(MI.memoperands(), MF);
5499     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs, NewMIs);
5500   }
5501 
5502   return true;
5503 }
5504 
5505 bool
5506 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5507                                   SmallVectorImpl<SDNode*> &NewNodes) const {
5508   if (!N->isMachineOpcode())
5509     return false;
5510 
5511   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode());
5512   if (I == nullptr)
5513     return false;
5514   unsigned Opc = I->DstOp;
5515   unsigned Index = I->Flags & TB_INDEX_MASK;
5516   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5517   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5518   const MCInstrDesc &MCID = get(Opc);
5519   MachineFunction &MF = DAG.getMachineFunction();
5520   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5521   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5522   unsigned NumDefs = MCID.NumDefs;
5523   std::vector<SDValue> AddrOps;
5524   std::vector<SDValue> BeforeOps;
5525   std::vector<SDValue> AfterOps;
5526   SDLoc dl(N);
5527   unsigned NumOps = N->getNumOperands();
5528   for (unsigned i = 0; i != NumOps-1; ++i) {
5529     SDValue Op = N->getOperand(i);
5530     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5531       AddrOps.push_back(Op);
5532     else if (i < Index-NumDefs)
5533       BeforeOps.push_back(Op);
5534     else if (i > Index-NumDefs)
5535       AfterOps.push_back(Op);
5536   }
5537   SDValue Chain = N->getOperand(NumOps-1);
5538   AddrOps.push_back(Chain);
5539 
5540   // Emit the load instruction.
5541   SDNode *Load = nullptr;
5542   if (FoldedLoad) {
5543     EVT VT = *TRI.legalclasstypes_begin(*RC);
5544     auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5545     if (MMOs.empty() && RC == &X86::VR128RegClass &&
5546         Subtarget.isUnalignedMem16Slow())
5547       // Do not introduce a slow unaligned load.
5548       return false;
5549     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5550     // memory access is slow above.
5551     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5552     bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5553     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
5554                               VT, MVT::Other, AddrOps);
5555     NewNodes.push_back(Load);
5556 
5557     // Preserve memory reference information.
5558     DAG.setNodeMemRefs(cast<MachineSDNode>(Load), MMOs);
5559   }
5560 
5561   // Emit the data processing instruction.
5562   std::vector<EVT> VTs;
5563   const TargetRegisterClass *DstRC = nullptr;
5564   if (MCID.getNumDefs() > 0) {
5565     DstRC = getRegClass(MCID, 0, &RI, MF);
5566     VTs.push_back(*TRI.legalclasstypes_begin(*DstRC));
5567   }
5568   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5569     EVT VT = N->getValueType(i);
5570     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5571       VTs.push_back(VT);
5572   }
5573   if (Load)
5574     BeforeOps.push_back(SDValue(Load, 0));
5575   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
5576   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5577   switch (Opc) {
5578     default: break;
5579     case X86::CMP64ri32:
5580     case X86::CMP64ri8:
5581     case X86::CMP32ri:
5582     case X86::CMP32ri8:
5583     case X86::CMP16ri:
5584     case X86::CMP16ri8:
5585     case X86::CMP8ri:
5586       if (isNullConstant(BeforeOps[1])) {
5587         switch (Opc) {
5588           default: llvm_unreachable("Unreachable!");
5589           case X86::CMP64ri8:
5590           case X86::CMP64ri32: Opc = X86::TEST64rr; break;
5591           case X86::CMP32ri8:
5592           case X86::CMP32ri:   Opc = X86::TEST32rr; break;
5593           case X86::CMP16ri8:
5594           case X86::CMP16ri:   Opc = X86::TEST16rr; break;
5595           case X86::CMP8ri:    Opc = X86::TEST8rr; break;
5596         }
5597         BeforeOps[1] = BeforeOps[0];
5598       }
5599   }
5600   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5601   NewNodes.push_back(NewNode);
5602 
5603   // Emit the store instruction.
5604   if (FoldedStore) {
5605     AddrOps.pop_back();
5606     AddrOps.push_back(SDValue(NewNode, 0));
5607     AddrOps.push_back(Chain);
5608     auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF);
5609     if (MMOs.empty() && RC == &X86::VR128RegClass &&
5610         Subtarget.isUnalignedMem16Slow())
5611       // Do not introduce a slow unaligned store.
5612       return false;
5613     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5614     // memory access is slow above.
5615     unsigned Alignment = std::max<uint32_t>(TRI.getSpillSize(*RC), 16);
5616     bool isAligned = !MMOs.empty() && MMOs.front()->getAlignment() >= Alignment;
5617     SDNode *Store =
5618         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5619                            dl, MVT::Other, AddrOps);
5620     NewNodes.push_back(Store);
5621 
5622     // Preserve memory reference information.
5623     DAG.setNodeMemRefs(cast<MachineSDNode>(Store), MMOs);
5624   }
5625 
5626   return true;
5627 }
5628 
5629 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5630                                       bool UnfoldLoad, bool UnfoldStore,
5631                                       unsigned *LoadRegIndex) const {
5632   const X86MemoryFoldTableEntry *I = lookupUnfoldTable(Opc);
5633   if (I == nullptr)
5634     return 0;
5635   bool FoldedLoad = I->Flags & TB_FOLDED_LOAD;
5636   bool FoldedStore = I->Flags & TB_FOLDED_STORE;
5637   if (UnfoldLoad && !FoldedLoad)
5638     return 0;
5639   if (UnfoldStore && !FoldedStore)
5640     return 0;
5641   if (LoadRegIndex)
5642     *LoadRegIndex = I->Flags & TB_INDEX_MASK;
5643   return I->DstOp;
5644 }
5645 
5646 bool
5647 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5648                                      int64_t &Offset1, int64_t &Offset2) const {
5649   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5650     return false;
5651   unsigned Opc1 = Load1->getMachineOpcode();
5652   unsigned Opc2 = Load2->getMachineOpcode();
5653   switch (Opc1) {
5654   default: return false;
5655   case X86::MOV8rm:
5656   case X86::MOV16rm:
5657   case X86::MOV32rm:
5658   case X86::MOV64rm:
5659   case X86::LD_Fp32m:
5660   case X86::LD_Fp64m:
5661   case X86::LD_Fp80m:
5662   case X86::MOVSSrm:
5663   case X86::MOVSDrm:
5664   case X86::MMX_MOVD64rm:
5665   case X86::MMX_MOVQ64rm:
5666   case X86::MOVAPSrm:
5667   case X86::MOVUPSrm:
5668   case X86::MOVAPDrm:
5669   case X86::MOVUPDrm:
5670   case X86::MOVDQArm:
5671   case X86::MOVDQUrm:
5672   // AVX load instructions
5673   case X86::VMOVSSrm:
5674   case X86::VMOVSDrm:
5675   case X86::VMOVAPSrm:
5676   case X86::VMOVUPSrm:
5677   case X86::VMOVAPDrm:
5678   case X86::VMOVUPDrm:
5679   case X86::VMOVDQArm:
5680   case X86::VMOVDQUrm:
5681   case X86::VMOVAPSYrm:
5682   case X86::VMOVUPSYrm:
5683   case X86::VMOVAPDYrm:
5684   case X86::VMOVUPDYrm:
5685   case X86::VMOVDQAYrm:
5686   case X86::VMOVDQUYrm:
5687   // AVX512 load instructions
5688   case X86::VMOVSSZrm:
5689   case X86::VMOVSDZrm:
5690   case X86::VMOVAPSZ128rm:
5691   case X86::VMOVUPSZ128rm:
5692   case X86::VMOVAPSZ128rm_NOVLX:
5693   case X86::VMOVUPSZ128rm_NOVLX:
5694   case X86::VMOVAPDZ128rm:
5695   case X86::VMOVUPDZ128rm:
5696   case X86::VMOVDQU8Z128rm:
5697   case X86::VMOVDQU16Z128rm:
5698   case X86::VMOVDQA32Z128rm:
5699   case X86::VMOVDQU32Z128rm:
5700   case X86::VMOVDQA64Z128rm:
5701   case X86::VMOVDQU64Z128rm:
5702   case X86::VMOVAPSZ256rm:
5703   case X86::VMOVUPSZ256rm:
5704   case X86::VMOVAPSZ256rm_NOVLX:
5705   case X86::VMOVUPSZ256rm_NOVLX:
5706   case X86::VMOVAPDZ256rm:
5707   case X86::VMOVUPDZ256rm:
5708   case X86::VMOVDQU8Z256rm:
5709   case X86::VMOVDQU16Z256rm:
5710   case X86::VMOVDQA32Z256rm:
5711   case X86::VMOVDQU32Z256rm:
5712   case X86::VMOVDQA64Z256rm:
5713   case X86::VMOVDQU64Z256rm:
5714   case X86::VMOVAPSZrm:
5715   case X86::VMOVUPSZrm:
5716   case X86::VMOVAPDZrm:
5717   case X86::VMOVUPDZrm:
5718   case X86::VMOVDQU8Zrm:
5719   case X86::VMOVDQU16Zrm:
5720   case X86::VMOVDQA32Zrm:
5721   case X86::VMOVDQU32Zrm:
5722   case X86::VMOVDQA64Zrm:
5723   case X86::VMOVDQU64Zrm:
5724   case X86::KMOVBkm:
5725   case X86::KMOVWkm:
5726   case X86::KMOVDkm:
5727   case X86::KMOVQkm:
5728     break;
5729   }
5730   switch (Opc2) {
5731   default: return false;
5732   case X86::MOV8rm:
5733   case X86::MOV16rm:
5734   case X86::MOV32rm:
5735   case X86::MOV64rm:
5736   case X86::LD_Fp32m:
5737   case X86::LD_Fp64m:
5738   case X86::LD_Fp80m:
5739   case X86::MOVSSrm:
5740   case X86::MOVSDrm:
5741   case X86::MMX_MOVD64rm:
5742   case X86::MMX_MOVQ64rm:
5743   case X86::MOVAPSrm:
5744   case X86::MOVUPSrm:
5745   case X86::MOVAPDrm:
5746   case X86::MOVUPDrm:
5747   case X86::MOVDQArm:
5748   case X86::MOVDQUrm:
5749   // AVX load instructions
5750   case X86::VMOVSSrm:
5751   case X86::VMOVSDrm:
5752   case X86::VMOVAPSrm:
5753   case X86::VMOVUPSrm:
5754   case X86::VMOVAPDrm:
5755   case X86::VMOVUPDrm:
5756   case X86::VMOVDQArm:
5757   case X86::VMOVDQUrm:
5758   case X86::VMOVAPSYrm:
5759   case X86::VMOVUPSYrm:
5760   case X86::VMOVAPDYrm:
5761   case X86::VMOVUPDYrm:
5762   case X86::VMOVDQAYrm:
5763   case X86::VMOVDQUYrm:
5764   // AVX512 load instructions
5765   case X86::VMOVSSZrm:
5766   case X86::VMOVSDZrm:
5767   case X86::VMOVAPSZ128rm:
5768   case X86::VMOVUPSZ128rm:
5769   case X86::VMOVAPSZ128rm_NOVLX:
5770   case X86::VMOVUPSZ128rm_NOVLX:
5771   case X86::VMOVAPDZ128rm:
5772   case X86::VMOVUPDZ128rm:
5773   case X86::VMOVDQU8Z128rm:
5774   case X86::VMOVDQU16Z128rm:
5775   case X86::VMOVDQA32Z128rm:
5776   case X86::VMOVDQU32Z128rm:
5777   case X86::VMOVDQA64Z128rm:
5778   case X86::VMOVDQU64Z128rm:
5779   case X86::VMOVAPSZ256rm:
5780   case X86::VMOVUPSZ256rm:
5781   case X86::VMOVAPSZ256rm_NOVLX:
5782   case X86::VMOVUPSZ256rm_NOVLX:
5783   case X86::VMOVAPDZ256rm:
5784   case X86::VMOVUPDZ256rm:
5785   case X86::VMOVDQU8Z256rm:
5786   case X86::VMOVDQU16Z256rm:
5787   case X86::VMOVDQA32Z256rm:
5788   case X86::VMOVDQU32Z256rm:
5789   case X86::VMOVDQA64Z256rm:
5790   case X86::VMOVDQU64Z256rm:
5791   case X86::VMOVAPSZrm:
5792   case X86::VMOVUPSZrm:
5793   case X86::VMOVAPDZrm:
5794   case X86::VMOVUPDZrm:
5795   case X86::VMOVDQU8Zrm:
5796   case X86::VMOVDQU16Zrm:
5797   case X86::VMOVDQA32Zrm:
5798   case X86::VMOVDQU32Zrm:
5799   case X86::VMOVDQA64Zrm:
5800   case X86::VMOVDQU64Zrm:
5801   case X86::KMOVBkm:
5802   case X86::KMOVWkm:
5803   case X86::KMOVDkm:
5804   case X86::KMOVQkm:
5805     break;
5806   }
5807 
5808   // Lambda to check if both the loads have the same value for an operand index.
5809   auto HasSameOp = [&](int I) {
5810     return Load1->getOperand(I) == Load2->getOperand(I);
5811   };
5812 
5813   // All operands except the displacement should match.
5814   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||
5815       !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg))
5816     return false;
5817 
5818   // Chain Operand must be the same.
5819   if (!HasSameOp(5))
5820     return false;
5821 
5822   // Now let's examine if the displacements are constants.
5823   auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp));
5824   auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp));
5825   if (!Disp1 || !Disp2)
5826     return false;
5827 
5828   Offset1 = Disp1->getSExtValue();
5829   Offset2 = Disp2->getSExtValue();
5830   return true;
5831 }
5832 
5833 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5834                                            int64_t Offset1, int64_t Offset2,
5835                                            unsigned NumLoads) const {
5836   assert(Offset2 > Offset1);
5837   if ((Offset2 - Offset1) / 8 > 64)
5838     return false;
5839 
5840   unsigned Opc1 = Load1->getMachineOpcode();
5841   unsigned Opc2 = Load2->getMachineOpcode();
5842   if (Opc1 != Opc2)
5843     return false;  // FIXME: overly conservative?
5844 
5845   switch (Opc1) {
5846   default: break;
5847   case X86::LD_Fp32m:
5848   case X86::LD_Fp64m:
5849   case X86::LD_Fp80m:
5850   case X86::MMX_MOVD64rm:
5851   case X86::MMX_MOVQ64rm:
5852     return false;
5853   }
5854 
5855   EVT VT = Load1->getValueType(0);
5856   switch (VT.getSimpleVT().SimpleTy) {
5857   default:
5858     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5859     // have 16 of them to play with.
5860     if (Subtarget.is64Bit()) {
5861       if (NumLoads >= 3)
5862         return false;
5863     } else if (NumLoads) {
5864       return false;
5865     }
5866     break;
5867   case MVT::i8:
5868   case MVT::i16:
5869   case MVT::i32:
5870   case MVT::i64:
5871   case MVT::f32:
5872   case MVT::f64:
5873     if (NumLoads)
5874       return false;
5875     break;
5876   }
5877 
5878   return true;
5879 }
5880 
5881 bool X86InstrInfo::
5882 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5883   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5884   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5885   Cond[0].setImm(GetOppositeBranchCondition(CC));
5886   return false;
5887 }
5888 
5889 bool X86InstrInfo::
5890 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5891   // FIXME: Return false for x87 stack register classes for now. We can't
5892   // allow any loads of these registers before FpGet_ST0_80.
5893   return !(RC == &X86::CCRRegClass || RC == &X86::DFCCRRegClass ||
5894            RC == &X86::RFP32RegClass || RC == &X86::RFP64RegClass ||
5895            RC == &X86::RFP80RegClass);
5896 }
5897 
5898 /// Return a virtual register initialized with the
5899 /// the global base register value. Output instructions required to
5900 /// initialize the register in the function entry block, if necessary.
5901 ///
5902 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5903 ///
5904 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5905   assert((!Subtarget.is64Bit() ||
5906           MF->getTarget().getCodeModel() == CodeModel::Medium ||
5907           MF->getTarget().getCodeModel() == CodeModel::Large) &&
5908          "X86-64 PIC uses RIP relative addressing");
5909 
5910   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5911   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5912   if (GlobalBaseReg != 0)
5913     return GlobalBaseReg;
5914 
5915   // Create the register. The code to initialize it is inserted
5916   // later, by the CGBR pass (below).
5917   MachineRegisterInfo &RegInfo = MF->getRegInfo();
5918   GlobalBaseReg = RegInfo.createVirtualRegister(
5919       Subtarget.is64Bit() ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass);
5920   X86FI->setGlobalBaseReg(GlobalBaseReg);
5921   return GlobalBaseReg;
5922 }
5923 
5924 // These are the replaceable SSE instructions. Some of these have Int variants
5925 // that we don't include here. We don't want to replace instructions selected
5926 // by intrinsics.
5927 static const uint16_t ReplaceableInstrs[][3] = {
5928   //PackedSingle     PackedDouble    PackedInt
5929   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
5930   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
5931   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
5932   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
5933   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
5934   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
5935   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
5936   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
5937   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
5938   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
5939   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
5940   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
5941   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
5942   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
5943   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
5944   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
5945   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
5946   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
5947   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
5948   { X86::UNPCKLPDrm, X86::UNPCKLPDrm, X86::PUNPCKLQDQrm },
5949   { X86::MOVLHPSrr,  X86::UNPCKLPDrr, X86::PUNPCKLQDQrr },
5950   { X86::UNPCKHPDrm, X86::UNPCKHPDrm, X86::PUNPCKHQDQrm },
5951   { X86::UNPCKHPDrr, X86::UNPCKHPDrr, X86::PUNPCKHQDQrr },
5952   { X86::UNPCKLPSrm, X86::UNPCKLPSrm, X86::PUNPCKLDQrm },
5953   { X86::UNPCKLPSrr, X86::UNPCKLPSrr, X86::PUNPCKLDQrr },
5954   { X86::UNPCKHPSrm, X86::UNPCKHPSrm, X86::PUNPCKHDQrm },
5955   { X86::UNPCKHPSrr, X86::UNPCKHPSrr, X86::PUNPCKHDQrr },
5956   { X86::EXTRACTPSmr, X86::EXTRACTPSmr, X86::PEXTRDmr },
5957   { X86::EXTRACTPSrr, X86::EXTRACTPSrr, X86::PEXTRDrr },
5958   // AVX 128-bit support
5959   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
5960   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
5961   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
5962   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
5963   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
5964   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
5965   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
5966   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
5967   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
5968   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
5969   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5970   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
5971   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
5972   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
5973   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
5974   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
5975   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
5976   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
5977   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
5978   { X86::VUNPCKLPDrm, X86::VUNPCKLPDrm, X86::VPUNPCKLQDQrm },
5979   { X86::VMOVLHPSrr,  X86::VUNPCKLPDrr, X86::VPUNPCKLQDQrr },
5980   { X86::VUNPCKHPDrm, X86::VUNPCKHPDrm, X86::VPUNPCKHQDQrm },
5981   { X86::VUNPCKHPDrr, X86::VUNPCKHPDrr, X86::VPUNPCKHQDQrr },
5982   { X86::VUNPCKLPSrm, X86::VUNPCKLPSrm, X86::VPUNPCKLDQrm },
5983   { X86::VUNPCKLPSrr, X86::VUNPCKLPSrr, X86::VPUNPCKLDQrr },
5984   { X86::VUNPCKHPSrm, X86::VUNPCKHPSrm, X86::VPUNPCKHDQrm },
5985   { X86::VUNPCKHPSrr, X86::VUNPCKHPSrr, X86::VPUNPCKHDQrr },
5986   { X86::VEXTRACTPSmr, X86::VEXTRACTPSmr, X86::VPEXTRDmr },
5987   { X86::VEXTRACTPSrr, X86::VEXTRACTPSrr, X86::VPEXTRDrr },
5988   // AVX 256-bit support
5989   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
5990   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
5991   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
5992   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
5993   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
5994   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
5995   { X86::VPERMPSYrm,   X86::VPERMPSYrm,   X86::VPERMDYrm },
5996   { X86::VPERMPSYrr,   X86::VPERMPSYrr,   X86::VPERMDYrr },
5997   { X86::VPERMPDYmi,   X86::VPERMPDYmi,   X86::VPERMQYmi },
5998   { X86::VPERMPDYri,   X86::VPERMPDYri,   X86::VPERMQYri },
5999   // AVX512 support
6000   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
6001   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
6002   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
6003   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
6004   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
6005   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
6006   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
6007   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
6008   { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
6009   { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
6010   { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
6011   { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
6012   { X86::VBROADCASTSSZr,    X86::VBROADCASTSSZr,    X86::VPBROADCASTDZr },
6013   { X86::VBROADCASTSSZm,    X86::VBROADCASTSSZm,    X86::VPBROADCASTDZm },
6014   { X86::VMOVDDUPZ128rr,    X86::VMOVDDUPZ128rr,    X86::VPBROADCASTQZ128r },
6015   { X86::VMOVDDUPZ128rm,    X86::VMOVDDUPZ128rm,    X86::VPBROADCASTQZ128m },
6016   { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
6017   { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
6018   { X86::VBROADCASTSDZr,    X86::VBROADCASTSDZr,    X86::VPBROADCASTQZr },
6019   { X86::VBROADCASTSDZm,    X86::VBROADCASTSDZm,    X86::VPBROADCASTQZm },
6020   { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrr,   X86::VINSERTI32x4Zrr },
6021   { X86::VINSERTF32x4Zrm,   X86::VINSERTF32x4Zrm,   X86::VINSERTI32x4Zrm },
6022   { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrr,   X86::VINSERTI32x8Zrr },
6023   { X86::VINSERTF32x8Zrm,   X86::VINSERTF32x8Zrm,   X86::VINSERTI32x8Zrm },
6024   { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrr,   X86::VINSERTI64x2Zrr },
6025   { X86::VINSERTF64x2Zrm,   X86::VINSERTF64x2Zrm,   X86::VINSERTI64x2Zrm },
6026   { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrr,   X86::VINSERTI64x4Zrr },
6027   { X86::VINSERTF64x4Zrm,   X86::VINSERTF64x4Zrm,   X86::VINSERTI64x4Zrm },
6028   { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rr,X86::VINSERTI32x4Z256rr },
6029   { X86::VINSERTF32x4Z256rm,X86::VINSERTF32x4Z256rm,X86::VINSERTI32x4Z256rm },
6030   { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rr,X86::VINSERTI64x2Z256rr },
6031   { X86::VINSERTF64x2Z256rm,X86::VINSERTF64x2Z256rm,X86::VINSERTI64x2Z256rm },
6032   { X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTF32x4Zrr,   X86::VEXTRACTI32x4Zrr },
6033   { X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTF32x4Zmr,   X86::VEXTRACTI32x4Zmr },
6034   { X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTF32x8Zrr,   X86::VEXTRACTI32x8Zrr },
6035   { X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTF32x8Zmr,   X86::VEXTRACTI32x8Zmr },
6036   { X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTF64x2Zrr,   X86::VEXTRACTI64x2Zrr },
6037   { X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTF64x2Zmr,   X86::VEXTRACTI64x2Zmr },
6038   { X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTF64x4Zrr,   X86::VEXTRACTI64x4Zrr },
6039   { X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTF64x4Zmr,   X86::VEXTRACTI64x4Zmr },
6040   { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTI32x4Z256rr },
6041   { X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTF32x4Z256mr,X86::VEXTRACTI32x4Z256mr },
6042   { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTI64x2Z256rr },
6043   { X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTF64x2Z256mr,X86::VEXTRACTI64x2Z256mr },
6044   { X86::VPERMILPSmi,        X86::VPERMILPSmi,        X86::VPSHUFDmi },
6045   { X86::VPERMILPSri,        X86::VPERMILPSri,        X86::VPSHUFDri },
6046   { X86::VPERMILPSZ128mi,    X86::VPERMILPSZ128mi,    X86::VPSHUFDZ128mi },
6047   { X86::VPERMILPSZ128ri,    X86::VPERMILPSZ128ri,    X86::VPSHUFDZ128ri },
6048   { X86::VPERMILPSZ256mi,    X86::VPERMILPSZ256mi,    X86::VPSHUFDZ256mi },
6049   { X86::VPERMILPSZ256ri,    X86::VPERMILPSZ256ri,    X86::VPSHUFDZ256ri },
6050   { X86::VPERMILPSZmi,       X86::VPERMILPSZmi,       X86::VPSHUFDZmi },
6051   { X86::VPERMILPSZri,       X86::VPERMILPSZri,       X86::VPSHUFDZri },
6052   { X86::VPERMPSZ256rm,      X86::VPERMPSZ256rm,      X86::VPERMDZ256rm },
6053   { X86::VPERMPSZ256rr,      X86::VPERMPSZ256rr,      X86::VPERMDZ256rr },
6054   { X86::VPERMPDZ256mi,      X86::VPERMPDZ256mi,      X86::VPERMQZ256mi },
6055   { X86::VPERMPDZ256ri,      X86::VPERMPDZ256ri,      X86::VPERMQZ256ri },
6056   { X86::VPERMPDZ256rm,      X86::VPERMPDZ256rm,      X86::VPERMQZ256rm },
6057   { X86::VPERMPDZ256rr,      X86::VPERMPDZ256rr,      X86::VPERMQZ256rr },
6058   { X86::VPERMPSZrm,         X86::VPERMPSZrm,         X86::VPERMDZrm },
6059   { X86::VPERMPSZrr,         X86::VPERMPSZrr,         X86::VPERMDZrr },
6060   { X86::VPERMPDZmi,         X86::VPERMPDZmi,         X86::VPERMQZmi },
6061   { X86::VPERMPDZri,         X86::VPERMPDZri,         X86::VPERMQZri },
6062   { X86::VPERMPDZrm,         X86::VPERMPDZrm,         X86::VPERMQZrm },
6063   { X86::VPERMPDZrr,         X86::VPERMPDZrr,         X86::VPERMQZrr },
6064   { X86::VUNPCKLPDZ256rm,    X86::VUNPCKLPDZ256rm,    X86::VPUNPCKLQDQZ256rm },
6065   { X86::VUNPCKLPDZ256rr,    X86::VUNPCKLPDZ256rr,    X86::VPUNPCKLQDQZ256rr },
6066   { X86::VUNPCKHPDZ256rm,    X86::VUNPCKHPDZ256rm,    X86::VPUNPCKHQDQZ256rm },
6067   { X86::VUNPCKHPDZ256rr,    X86::VUNPCKHPDZ256rr,    X86::VPUNPCKHQDQZ256rr },
6068   { X86::VUNPCKLPSZ256rm,    X86::VUNPCKLPSZ256rm,    X86::VPUNPCKLDQZ256rm },
6069   { X86::VUNPCKLPSZ256rr,    X86::VUNPCKLPSZ256rr,    X86::VPUNPCKLDQZ256rr },
6070   { X86::VUNPCKHPSZ256rm,    X86::VUNPCKHPSZ256rm,    X86::VPUNPCKHDQZ256rm },
6071   { X86::VUNPCKHPSZ256rr,    X86::VUNPCKHPSZ256rr,    X86::VPUNPCKHDQZ256rr },
6072   { X86::VUNPCKLPDZ128rm,    X86::VUNPCKLPDZ128rm,    X86::VPUNPCKLQDQZ128rm },
6073   { X86::VMOVLHPSZrr,        X86::VUNPCKLPDZ128rr,    X86::VPUNPCKLQDQZ128rr },
6074   { X86::VUNPCKHPDZ128rm,    X86::VUNPCKHPDZ128rm,    X86::VPUNPCKHQDQZ128rm },
6075   { X86::VUNPCKHPDZ128rr,    X86::VUNPCKHPDZ128rr,    X86::VPUNPCKHQDQZ128rr },
6076   { X86::VUNPCKLPSZ128rm,    X86::VUNPCKLPSZ128rm,    X86::VPUNPCKLDQZ128rm },
6077   { X86::VUNPCKLPSZ128rr,    X86::VUNPCKLPSZ128rr,    X86::VPUNPCKLDQZ128rr },
6078   { X86::VUNPCKHPSZ128rm,    X86::VUNPCKHPSZ128rm,    X86::VPUNPCKHDQZ128rm },
6079   { X86::VUNPCKHPSZ128rr,    X86::VUNPCKHPSZ128rr,    X86::VPUNPCKHDQZ128rr },
6080   { X86::VUNPCKLPDZrm,       X86::VUNPCKLPDZrm,       X86::VPUNPCKLQDQZrm },
6081   { X86::VUNPCKLPDZrr,       X86::VUNPCKLPDZrr,       X86::VPUNPCKLQDQZrr },
6082   { X86::VUNPCKHPDZrm,       X86::VUNPCKHPDZrm,       X86::VPUNPCKHQDQZrm },
6083   { X86::VUNPCKHPDZrr,       X86::VUNPCKHPDZrr,       X86::VPUNPCKHQDQZrr },
6084   { X86::VUNPCKLPSZrm,       X86::VUNPCKLPSZrm,       X86::VPUNPCKLDQZrm },
6085   { X86::VUNPCKLPSZrr,       X86::VUNPCKLPSZrr,       X86::VPUNPCKLDQZrr },
6086   { X86::VUNPCKHPSZrm,       X86::VUNPCKHPSZrm,       X86::VPUNPCKHDQZrm },
6087   { X86::VUNPCKHPSZrr,       X86::VUNPCKHPSZrr,       X86::VPUNPCKHDQZrr },
6088   { X86::VEXTRACTPSZmr,      X86::VEXTRACTPSZmr,      X86::VPEXTRDZmr },
6089   { X86::VEXTRACTPSZrr,      X86::VEXTRACTPSZrr,      X86::VPEXTRDZrr },
6090 };
6091 
6092 static const uint16_t ReplaceableInstrsAVX2[][3] = {
6093   //PackedSingle       PackedDouble       PackedInt
6094   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
6095   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
6096   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
6097   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
6098   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
6099   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
6100   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
6101   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
6102   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
6103   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
6104   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6105   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6106   { X86::VMOVDDUPrm,     X86::VMOVDDUPrm,     X86::VPBROADCASTQrm},
6107   { X86::VMOVDDUPrr,     X86::VMOVDDUPrr,     X86::VPBROADCASTQrr},
6108   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6109   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6110   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6111   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
6112   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
6113   { X86::VBLENDPSYrri,    X86::VBLENDPSYrri,    X86::VPBLENDDYrri },
6114   { X86::VBLENDPSYrmi,    X86::VBLENDPSYrmi,    X86::VPBLENDDYrmi },
6115   { X86::VPERMILPSYmi,    X86::VPERMILPSYmi,    X86::VPSHUFDYmi },
6116   { X86::VPERMILPSYri,    X86::VPERMILPSYri,    X86::VPSHUFDYri },
6117   { X86::VUNPCKLPDYrm,    X86::VUNPCKLPDYrm,    X86::VPUNPCKLQDQYrm },
6118   { X86::VUNPCKLPDYrr,    X86::VUNPCKLPDYrr,    X86::VPUNPCKLQDQYrr },
6119   { X86::VUNPCKHPDYrm,    X86::VUNPCKHPDYrm,    X86::VPUNPCKHQDQYrm },
6120   { X86::VUNPCKHPDYrr,    X86::VUNPCKHPDYrr,    X86::VPUNPCKHQDQYrr },
6121   { X86::VUNPCKLPSYrm,    X86::VUNPCKLPSYrm,    X86::VPUNPCKLDQYrm },
6122   { X86::VUNPCKLPSYrr,    X86::VUNPCKLPSYrr,    X86::VPUNPCKLDQYrr },
6123   { X86::VUNPCKHPSYrm,    X86::VUNPCKHPSYrm,    X86::VPUNPCKHDQYrm },
6124   { X86::VUNPCKHPSYrr,    X86::VUNPCKHPSYrr,    X86::VPUNPCKHDQYrr },
6125 };
6126 
6127 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
6128   //PackedSingle       PackedDouble       PackedInt
6129   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6130   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6131   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
6132   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
6133 };
6134 
6135 static const uint16_t ReplaceableInstrsAVX512[][4] = {
6136   // Two integer columns for 64-bit and 32-bit elements.
6137   //PackedSingle        PackedDouble        PackedInt             PackedInt
6138   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
6139   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
6140   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
6141   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
6142   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
6143   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
6144   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
6145   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
6146   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
6147   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
6148   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
6149   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
6150   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
6151   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
6152   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
6153 };
6154 
6155 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
6156   // Two integer columns for 64-bit and 32-bit elements.
6157   //PackedSingle        PackedDouble        PackedInt           PackedInt
6158   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6159   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6160   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
6161   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
6162   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
6163   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
6164   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
6165   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
6166   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6167   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6168   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
6169   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
6170   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
6171   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
6172   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
6173   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
6174   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
6175   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
6176   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
6177   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
6178   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
6179   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
6180   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
6181   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
6182 };
6183 
6184 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
6185   // Two integer columns for 64-bit and 32-bit elements.
6186   //PackedSingle          PackedDouble
6187   //PackedInt             PackedInt
6188   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
6189     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
6190   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
6191     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
6192   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
6193     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
6194   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
6195     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
6196   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
6197     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
6198   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
6199     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
6200   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
6201     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
6202   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
6203     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
6204   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
6205     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
6206   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
6207     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
6208   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
6209     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
6210   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
6211     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
6212   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
6213     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
6214   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
6215     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
6216   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
6217     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
6218   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
6219     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
6220   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
6221     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
6222   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
6223     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
6224   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
6225     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
6226   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
6227     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
6228   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
6229     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
6230   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
6231     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
6232   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
6233     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
6234   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
6235     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
6236   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
6237     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
6238   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
6239     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
6240   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
6241     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
6242   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
6243     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
6244   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
6245     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
6246   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
6247     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
6248   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
6249     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
6250   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
6251     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
6252   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
6253     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
6254   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
6255     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
6256   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
6257     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
6258   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
6259     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
6260   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
6261     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
6262   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
6263     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
6264   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
6265     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
6266   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
6267     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
6268   { X86::VORPSZrmk,       X86::VORPDZrmk,
6269     X86::VPORQZrmk,       X86::VPORDZrmk       },
6270   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
6271     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
6272   { X86::VORPSZrrk,       X86::VORPDZrrk,
6273     X86::VPORQZrrk,       X86::VPORDZrrk       },
6274   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
6275     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
6276   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
6277     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
6278   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
6279     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
6280   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
6281     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
6282   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
6283     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
6284   // Broadcast loads can be handled the same as masked operations to avoid
6285   // changing element size.
6286   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
6287     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
6288   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
6289     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
6290   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
6291     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
6292   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
6293     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
6294   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
6295     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
6296   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
6297     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
6298   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
6299     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
6300   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
6301     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
6302   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
6303     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
6304   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
6305     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
6306   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
6307     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
6308   { X86::VORPSZrmb,       X86::VORPDZrmb,
6309     X86::VPORQZrmb,       X86::VPORDZrmb       },
6310   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
6311     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
6312   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
6313     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
6314   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
6315     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
6316   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
6317     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
6318   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
6319     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
6320   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
6321     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
6322   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
6323     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
6324   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
6325     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
6326   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
6327     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
6328   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
6329     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
6330   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
6331     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
6332   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
6333     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
6334   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
6335     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
6336   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
6337     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
6338   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
6339     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
6340   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
6341     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
6342   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
6343     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
6344   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
6345     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
6346   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
6347     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
6348   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
6349     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
6350   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
6351     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
6352   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
6353     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
6354   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
6355     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
6356   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
6357     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
6358   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
6359     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
6360   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
6361     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
6362   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
6363     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
6364 };
6365 
6366 // NOTE: These should only be used by the custom domain methods.
6367 static const uint16_t ReplaceableCustomInstrs[][3] = {
6368   //PackedSingle             PackedDouble             PackedInt
6369   { X86::BLENDPSrmi,         X86::BLENDPDrmi,         X86::PBLENDWrmi   },
6370   { X86::BLENDPSrri,         X86::BLENDPDrri,         X86::PBLENDWrri   },
6371   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDWrmi  },
6372   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDWrri  },
6373   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDWYrmi },
6374   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDWYrri },
6375 };
6376 static const uint16_t ReplaceableCustomAVX2Instrs[][3] = {
6377   //PackedSingle             PackedDouble             PackedInt
6378   { X86::VBLENDPSrmi,        X86::VBLENDPDrmi,        X86::VPBLENDDrmi  },
6379   { X86::VBLENDPSrri,        X86::VBLENDPDrri,        X86::VPBLENDDrri  },
6380   { X86::VBLENDPSYrmi,       X86::VBLENDPDYrmi,       X86::VPBLENDDYrmi },
6381   { X86::VBLENDPSYrri,       X86::VBLENDPDYrri,       X86::VPBLENDDYrri },
6382 };
6383 
6384 // Special table for changing EVEX logic instructions to VEX.
6385 // TODO: Should we run EVEX->VEX earlier?
6386 static const uint16_t ReplaceableCustomAVX512LogicInstrs[][4] = {
6387   // Two integer columns for 64-bit and 32-bit elements.
6388   //PackedSingle     PackedDouble     PackedInt           PackedInt
6389   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
6390   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
6391   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
6392   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
6393   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORQZ128rm,   X86::VPORDZ128rm   },
6394   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORQZ128rr,   X86::VPORDZ128rr   },
6395   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
6396   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
6397   { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
6398   { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
6399   { X86::VANDPSYrm,  X86::VANDPDYrm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
6400   { X86::VANDPSYrr,  X86::VANDPDYrr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
6401   { X86::VORPSYrm,   X86::VORPDYrm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
6402   { X86::VORPSYrr,   X86::VORPDYrr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
6403   { X86::VXORPSYrm,  X86::VXORPDYrm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
6404   { X86::VXORPSYrr,  X86::VXORPDYrr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
6405 };
6406 
6407 // FIXME: Some shuffle and unpack instructions have equivalents in different
6408 // domains, but they require a bit more work than just switching opcodes.
6409 
6410 static const uint16_t *lookup(unsigned opcode, unsigned domain,
6411                               ArrayRef<uint16_t[3]> Table) {
6412   for (const uint16_t (&Row)[3] : Table)
6413     if (Row[domain-1] == opcode)
6414       return Row;
6415   return nullptr;
6416 }
6417 
6418 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
6419                                     ArrayRef<uint16_t[4]> Table) {
6420   // If this is the integer domain make sure to check both integer columns.
6421   for (const uint16_t (&Row)[4] : Table)
6422     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
6423       return Row;
6424   return nullptr;
6425 }
6426 
6427 // Helper to attempt to widen/narrow blend masks.
6428 static bool AdjustBlendMask(unsigned OldMask, unsigned OldWidth,
6429                             unsigned NewWidth, unsigned *pNewMask = nullptr) {
6430   assert(((OldWidth % NewWidth) == 0 || (NewWidth % OldWidth) == 0) &&
6431          "Illegal blend mask scale");
6432   unsigned NewMask = 0;
6433 
6434   if ((OldWidth % NewWidth) == 0) {
6435     unsigned Scale = OldWidth / NewWidth;
6436     unsigned SubMask = (1u << Scale) - 1;
6437     for (unsigned i = 0; i != NewWidth; ++i) {
6438       unsigned Sub = (OldMask >> (i * Scale)) & SubMask;
6439       if (Sub == SubMask)
6440         NewMask |= (1u << i);
6441       else if (Sub != 0x0)
6442         return false;
6443     }
6444   } else {
6445     unsigned Scale = NewWidth / OldWidth;
6446     unsigned SubMask = (1u << Scale) - 1;
6447     for (unsigned i = 0; i != OldWidth; ++i) {
6448       if (OldMask & (1 << i)) {
6449         NewMask |= (SubMask << (i * Scale));
6450       }
6451     }
6452   }
6453 
6454   if (pNewMask)
6455     *pNewMask = NewMask;
6456   return true;
6457 }
6458 
6459 uint16_t X86InstrInfo::getExecutionDomainCustom(const MachineInstr &MI) const {
6460   unsigned Opcode = MI.getOpcode();
6461   unsigned NumOperands = MI.getDesc().getNumOperands();
6462 
6463   auto GetBlendDomains = [&](unsigned ImmWidth, bool Is256) {
6464     uint16_t validDomains = 0;
6465     if (MI.getOperand(NumOperands - 1).isImm()) {
6466       unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
6467       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4))
6468         validDomains |= 0x2; // PackedSingle
6469       if (AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2))
6470         validDomains |= 0x4; // PackedDouble
6471       if (!Is256 || Subtarget.hasAVX2())
6472         validDomains |= 0x8; // PackedInt
6473     }
6474     return validDomains;
6475   };
6476 
6477   switch (Opcode) {
6478   case X86::BLENDPDrmi:
6479   case X86::BLENDPDrri:
6480   case X86::VBLENDPDrmi:
6481   case X86::VBLENDPDrri:
6482     return GetBlendDomains(2, false);
6483   case X86::VBLENDPDYrmi:
6484   case X86::VBLENDPDYrri:
6485     return GetBlendDomains(4, true);
6486   case X86::BLENDPSrmi:
6487   case X86::BLENDPSrri:
6488   case X86::VBLENDPSrmi:
6489   case X86::VBLENDPSrri:
6490   case X86::VPBLENDDrmi:
6491   case X86::VPBLENDDrri:
6492     return GetBlendDomains(4, false);
6493   case X86::VBLENDPSYrmi:
6494   case X86::VBLENDPSYrri:
6495   case X86::VPBLENDDYrmi:
6496   case X86::VPBLENDDYrri:
6497     return GetBlendDomains(8, true);
6498   case X86::PBLENDWrmi:
6499   case X86::PBLENDWrri:
6500   case X86::VPBLENDWrmi:
6501   case X86::VPBLENDWrri:
6502   // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks.
6503   case X86::VPBLENDWYrmi:
6504   case X86::VPBLENDWYrri:
6505     return GetBlendDomains(8, false);
6506   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
6507   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
6508   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
6509   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
6510   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6511   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6512   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6513   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6514   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
6515   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
6516   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
6517   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
6518   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
6519   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
6520   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
6521   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm:
6522     // If we don't have DQI see if we can still switch from an EVEX integer
6523     // instruction to a VEX floating point instruction.
6524     if (Subtarget.hasDQI())
6525       return 0;
6526 
6527     if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
6528       return 0;
6529     if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
6530       return 0;
6531     // Register forms will have 3 operands. Memory form will have more.
6532     if (NumOperands == 3 &&
6533         RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
6534       return 0;
6535 
6536     // All domains are valid.
6537     return 0xe;
6538   case X86::MOVHLPSrr:
6539     // We can swap domains when both inputs are the same register.
6540     // FIXME: This doesn't catch all the cases we would like. If the input
6541     // register isn't KILLed by the instruction, the two address instruction
6542     // pass puts a COPY on one input. The other input uses the original
6543     // register. This prevents the same physical register from being used by
6544     // both inputs.
6545     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6546         MI.getOperand(0).getSubReg() == 0 &&
6547         MI.getOperand(1).getSubReg() == 0 &&
6548         MI.getOperand(2).getSubReg() == 0)
6549       return 0x6;
6550     return 0;
6551   }
6552   return 0;
6553 }
6554 
6555 bool X86InstrInfo::setExecutionDomainCustom(MachineInstr &MI,
6556                                             unsigned Domain) const {
6557   assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
6558   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6559   assert(dom && "Not an SSE instruction");
6560 
6561   unsigned Opcode = MI.getOpcode();
6562   unsigned NumOperands = MI.getDesc().getNumOperands();
6563 
6564   auto SetBlendDomain = [&](unsigned ImmWidth, bool Is256) {
6565     if (MI.getOperand(NumOperands - 1).isImm()) {
6566       unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
6567       Imm = (ImmWidth == 16 ? ((Imm << 8) | Imm) : Imm);
6568       unsigned NewImm = Imm;
6569 
6570       const uint16_t *table = lookup(Opcode, dom, ReplaceableCustomInstrs);
6571       if (!table)
6572         table = lookup(Opcode, dom, ReplaceableCustomAVX2Instrs);
6573 
6574       if (Domain == 1) { // PackedSingle
6575         AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6576       } else if (Domain == 2) { // PackedDouble
6577         AdjustBlendMask(Imm, ImmWidth, Is256 ? 4 : 2, &NewImm);
6578       } else if (Domain == 3) { // PackedInt
6579         if (Subtarget.hasAVX2()) {
6580           // If we are already VPBLENDW use that, else use VPBLENDD.
6581           if ((ImmWidth / (Is256 ? 2 : 1)) != 8) {
6582             table = lookup(Opcode, dom, ReplaceableCustomAVX2Instrs);
6583             AdjustBlendMask(Imm, ImmWidth, Is256 ? 8 : 4, &NewImm);
6584           }
6585         } else {
6586           assert(!Is256 && "128-bit vector expected");
6587           AdjustBlendMask(Imm, ImmWidth, 8, &NewImm);
6588         }
6589       }
6590 
6591       assert(table && table[Domain - 1] && "Unknown domain op");
6592       MI.setDesc(get(table[Domain - 1]));
6593       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
6594     }
6595     return true;
6596   };
6597 
6598   switch (Opcode) {
6599   case X86::BLENDPDrmi:
6600   case X86::BLENDPDrri:
6601   case X86::VBLENDPDrmi:
6602   case X86::VBLENDPDrri:
6603     return SetBlendDomain(2, false);
6604   case X86::VBLENDPDYrmi:
6605   case X86::VBLENDPDYrri:
6606     return SetBlendDomain(4, true);
6607   case X86::BLENDPSrmi:
6608   case X86::BLENDPSrri:
6609   case X86::VBLENDPSrmi:
6610   case X86::VBLENDPSrri:
6611   case X86::VPBLENDDrmi:
6612   case X86::VPBLENDDrri:
6613     return SetBlendDomain(4, false);
6614   case X86::VBLENDPSYrmi:
6615   case X86::VBLENDPSYrri:
6616   case X86::VPBLENDDYrmi:
6617   case X86::VPBLENDDYrri:
6618     return SetBlendDomain(8, true);
6619   case X86::PBLENDWrmi:
6620   case X86::PBLENDWrri:
6621   case X86::VPBLENDWrmi:
6622   case X86::VPBLENDWrri:
6623     return SetBlendDomain(8, false);
6624   case X86::VPBLENDWYrmi:
6625   case X86::VPBLENDWYrri:
6626     return SetBlendDomain(16, true);
6627   case X86::VPANDDZ128rr:  case X86::VPANDDZ128rm:
6628   case X86::VPANDDZ256rr:  case X86::VPANDDZ256rm:
6629   case X86::VPANDQZ128rr:  case X86::VPANDQZ128rm:
6630   case X86::VPANDQZ256rr:  case X86::VPANDQZ256rm:
6631   case X86::VPANDNDZ128rr: case X86::VPANDNDZ128rm:
6632   case X86::VPANDNDZ256rr: case X86::VPANDNDZ256rm:
6633   case X86::VPANDNQZ128rr: case X86::VPANDNQZ128rm:
6634   case X86::VPANDNQZ256rr: case X86::VPANDNQZ256rm:
6635   case X86::VPORDZ128rr:   case X86::VPORDZ128rm:
6636   case X86::VPORDZ256rr:   case X86::VPORDZ256rm:
6637   case X86::VPORQZ128rr:   case X86::VPORQZ128rm:
6638   case X86::VPORQZ256rr:   case X86::VPORQZ256rm:
6639   case X86::VPXORDZ128rr:  case X86::VPXORDZ128rm:
6640   case X86::VPXORDZ256rr:  case X86::VPXORDZ256rm:
6641   case X86::VPXORQZ128rr:  case X86::VPXORQZ128rm:
6642   case X86::VPXORQZ256rr:  case X86::VPXORQZ256rm: {
6643     // Without DQI, convert EVEX instructions to VEX instructions.
6644     if (Subtarget.hasDQI())
6645       return false;
6646 
6647     const uint16_t *table = lookupAVX512(MI.getOpcode(), dom,
6648                                          ReplaceableCustomAVX512LogicInstrs);
6649     assert(table && "Instruction not found in table?");
6650     // Don't change integer Q instructions to D instructions and
6651     // use D intructions if we started with a PS instruction.
6652     if (Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6653       Domain = 4;
6654     MI.setDesc(get(table[Domain - 1]));
6655     return true;
6656   }
6657   case X86::UNPCKHPDrr:
6658   case X86::MOVHLPSrr:
6659     // We just need to commute the instruction which will switch the domains.
6660     if (Domain != dom && Domain != 3 &&
6661         MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6662         MI.getOperand(0).getSubReg() == 0 &&
6663         MI.getOperand(1).getSubReg() == 0 &&
6664         MI.getOperand(2).getSubReg() == 0) {
6665       commuteInstruction(MI, false);
6666       return true;
6667     }
6668     // We must always return true for MOVHLPSrr.
6669     if (Opcode == X86::MOVHLPSrr)
6670       return true;
6671   }
6672   return false;
6673 }
6674 
6675 std::pair<uint16_t, uint16_t>
6676 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
6677   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6678   unsigned opcode = MI.getOpcode();
6679   uint16_t validDomains = 0;
6680   if (domain) {
6681     // Attempt to match for custom instructions.
6682     validDomains = getExecutionDomainCustom(MI);
6683     if (validDomains)
6684       return std::make_pair(domain, validDomains);
6685 
6686     if (lookup(opcode, domain, ReplaceableInstrs)) {
6687       validDomains = 0xe;
6688     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
6689       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
6690     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
6691       // Insert/extract instructions should only effect domain if AVX2
6692       // is enabled.
6693       if (!Subtarget.hasAVX2())
6694         return std::make_pair(0, 0);
6695       validDomains = 0xe;
6696     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
6697       validDomains = 0xe;
6698     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
6699                                                   ReplaceableInstrsAVX512DQ)) {
6700       validDomains = 0xe;
6701     } else if (Subtarget.hasDQI()) {
6702       if (const uint16_t *table = lookupAVX512(opcode, domain,
6703                                              ReplaceableInstrsAVX512DQMasked)) {
6704         if (domain == 1 || (domain == 3 && table[3] == opcode))
6705           validDomains = 0xa;
6706         else
6707           validDomains = 0xc;
6708       }
6709     }
6710   }
6711   return std::make_pair(domain, validDomains);
6712 }
6713 
6714 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
6715   assert(Domain>0 && Domain<4 && "Invalid execution domain");
6716   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6717   assert(dom && "Not an SSE instruction");
6718 
6719   // Attempt to match for custom instructions.
6720   if (setExecutionDomainCustom(MI, Domain))
6721     return;
6722 
6723   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
6724   if (!table) { // try the other table
6725     assert((Subtarget.hasAVX2() || Domain < 3) &&
6726            "256-bit vector operations only available in AVX2");
6727     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
6728   }
6729   if (!table) { // try the other table
6730     assert(Subtarget.hasAVX2() &&
6731            "256-bit insert/extract only available in AVX2");
6732     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
6733   }
6734   if (!table) { // try the AVX512 table
6735     assert(Subtarget.hasAVX512() && "Requires AVX-512");
6736     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
6737     // Don't change integer Q instructions to D instructions.
6738     if (table && Domain == 3 && table[3] == MI.getOpcode())
6739       Domain = 4;
6740   }
6741   if (!table) { // try the AVX512DQ table
6742     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
6743     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
6744     // Don't change integer Q instructions to D instructions and
6745     // use D intructions if we started with a PS instruction.
6746     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6747       Domain = 4;
6748   }
6749   if (!table) { // try the AVX512DQMasked table
6750     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
6751     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
6752     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
6753       Domain = 4;
6754   }
6755   assert(table && "Cannot change domain");
6756   MI.setDesc(get(table[Domain - 1]));
6757 }
6758 
6759 /// Return the noop instruction to use for a noop.
6760 void X86InstrInfo::getNoop(MCInst &NopInst) const {
6761   NopInst.setOpcode(X86::NOOP);
6762 }
6763 
6764 bool X86InstrInfo::isHighLatencyDef(int opc) const {
6765   switch (opc) {
6766   default: return false;
6767   case X86::DIVPDrm:
6768   case X86::DIVPDrr:
6769   case X86::DIVPSrm:
6770   case X86::DIVPSrr:
6771   case X86::DIVSDrm:
6772   case X86::DIVSDrm_Int:
6773   case X86::DIVSDrr:
6774   case X86::DIVSDrr_Int:
6775   case X86::DIVSSrm:
6776   case X86::DIVSSrm_Int:
6777   case X86::DIVSSrr:
6778   case X86::DIVSSrr_Int:
6779   case X86::SQRTPDm:
6780   case X86::SQRTPDr:
6781   case X86::SQRTPSm:
6782   case X86::SQRTPSr:
6783   case X86::SQRTSDm:
6784   case X86::SQRTSDm_Int:
6785   case X86::SQRTSDr:
6786   case X86::SQRTSDr_Int:
6787   case X86::SQRTSSm:
6788   case X86::SQRTSSm_Int:
6789   case X86::SQRTSSr:
6790   case X86::SQRTSSr_Int:
6791   // AVX instructions with high latency
6792   case X86::VDIVPDrm:
6793   case X86::VDIVPDrr:
6794   case X86::VDIVPDYrm:
6795   case X86::VDIVPDYrr:
6796   case X86::VDIVPSrm:
6797   case X86::VDIVPSrr:
6798   case X86::VDIVPSYrm:
6799   case X86::VDIVPSYrr:
6800   case X86::VDIVSDrm:
6801   case X86::VDIVSDrm_Int:
6802   case X86::VDIVSDrr:
6803   case X86::VDIVSDrr_Int:
6804   case X86::VDIVSSrm:
6805   case X86::VDIVSSrm_Int:
6806   case X86::VDIVSSrr:
6807   case X86::VDIVSSrr_Int:
6808   case X86::VSQRTPDm:
6809   case X86::VSQRTPDr:
6810   case X86::VSQRTPDYm:
6811   case X86::VSQRTPDYr:
6812   case X86::VSQRTPSm:
6813   case X86::VSQRTPSr:
6814   case X86::VSQRTPSYm:
6815   case X86::VSQRTPSYr:
6816   case X86::VSQRTSDm:
6817   case X86::VSQRTSDm_Int:
6818   case X86::VSQRTSDr:
6819   case X86::VSQRTSDr_Int:
6820   case X86::VSQRTSSm:
6821   case X86::VSQRTSSm_Int:
6822   case X86::VSQRTSSr:
6823   case X86::VSQRTSSr_Int:
6824   // AVX512 instructions with high latency
6825   case X86::VDIVPDZ128rm:
6826   case X86::VDIVPDZ128rmb:
6827   case X86::VDIVPDZ128rmbk:
6828   case X86::VDIVPDZ128rmbkz:
6829   case X86::VDIVPDZ128rmk:
6830   case X86::VDIVPDZ128rmkz:
6831   case X86::VDIVPDZ128rr:
6832   case X86::VDIVPDZ128rrk:
6833   case X86::VDIVPDZ128rrkz:
6834   case X86::VDIVPDZ256rm:
6835   case X86::VDIVPDZ256rmb:
6836   case X86::VDIVPDZ256rmbk:
6837   case X86::VDIVPDZ256rmbkz:
6838   case X86::VDIVPDZ256rmk:
6839   case X86::VDIVPDZ256rmkz:
6840   case X86::VDIVPDZ256rr:
6841   case X86::VDIVPDZ256rrk:
6842   case X86::VDIVPDZ256rrkz:
6843   case X86::VDIVPDZrrb:
6844   case X86::VDIVPDZrrbk:
6845   case X86::VDIVPDZrrbkz:
6846   case X86::VDIVPDZrm:
6847   case X86::VDIVPDZrmb:
6848   case X86::VDIVPDZrmbk:
6849   case X86::VDIVPDZrmbkz:
6850   case X86::VDIVPDZrmk:
6851   case X86::VDIVPDZrmkz:
6852   case X86::VDIVPDZrr:
6853   case X86::VDIVPDZrrk:
6854   case X86::VDIVPDZrrkz:
6855   case X86::VDIVPSZ128rm:
6856   case X86::VDIVPSZ128rmb:
6857   case X86::VDIVPSZ128rmbk:
6858   case X86::VDIVPSZ128rmbkz:
6859   case X86::VDIVPSZ128rmk:
6860   case X86::VDIVPSZ128rmkz:
6861   case X86::VDIVPSZ128rr:
6862   case X86::VDIVPSZ128rrk:
6863   case X86::VDIVPSZ128rrkz:
6864   case X86::VDIVPSZ256rm:
6865   case X86::VDIVPSZ256rmb:
6866   case X86::VDIVPSZ256rmbk:
6867   case X86::VDIVPSZ256rmbkz:
6868   case X86::VDIVPSZ256rmk:
6869   case X86::VDIVPSZ256rmkz:
6870   case X86::VDIVPSZ256rr:
6871   case X86::VDIVPSZ256rrk:
6872   case X86::VDIVPSZ256rrkz:
6873   case X86::VDIVPSZrrb:
6874   case X86::VDIVPSZrrbk:
6875   case X86::VDIVPSZrrbkz:
6876   case X86::VDIVPSZrm:
6877   case X86::VDIVPSZrmb:
6878   case X86::VDIVPSZrmbk:
6879   case X86::VDIVPSZrmbkz:
6880   case X86::VDIVPSZrmk:
6881   case X86::VDIVPSZrmkz:
6882   case X86::VDIVPSZrr:
6883   case X86::VDIVPSZrrk:
6884   case X86::VDIVPSZrrkz:
6885   case X86::VDIVSDZrm:
6886   case X86::VDIVSDZrr:
6887   case X86::VDIVSDZrm_Int:
6888   case X86::VDIVSDZrm_Intk:
6889   case X86::VDIVSDZrm_Intkz:
6890   case X86::VDIVSDZrr_Int:
6891   case X86::VDIVSDZrr_Intk:
6892   case X86::VDIVSDZrr_Intkz:
6893   case X86::VDIVSDZrrb_Int:
6894   case X86::VDIVSDZrrb_Intk:
6895   case X86::VDIVSDZrrb_Intkz:
6896   case X86::VDIVSSZrm:
6897   case X86::VDIVSSZrr:
6898   case X86::VDIVSSZrm_Int:
6899   case X86::VDIVSSZrm_Intk:
6900   case X86::VDIVSSZrm_Intkz:
6901   case X86::VDIVSSZrr_Int:
6902   case X86::VDIVSSZrr_Intk:
6903   case X86::VDIVSSZrr_Intkz:
6904   case X86::VDIVSSZrrb_Int:
6905   case X86::VDIVSSZrrb_Intk:
6906   case X86::VDIVSSZrrb_Intkz:
6907   case X86::VSQRTPDZ128m:
6908   case X86::VSQRTPDZ128mb:
6909   case X86::VSQRTPDZ128mbk:
6910   case X86::VSQRTPDZ128mbkz:
6911   case X86::VSQRTPDZ128mk:
6912   case X86::VSQRTPDZ128mkz:
6913   case X86::VSQRTPDZ128r:
6914   case X86::VSQRTPDZ128rk:
6915   case X86::VSQRTPDZ128rkz:
6916   case X86::VSQRTPDZ256m:
6917   case X86::VSQRTPDZ256mb:
6918   case X86::VSQRTPDZ256mbk:
6919   case X86::VSQRTPDZ256mbkz:
6920   case X86::VSQRTPDZ256mk:
6921   case X86::VSQRTPDZ256mkz:
6922   case X86::VSQRTPDZ256r:
6923   case X86::VSQRTPDZ256rk:
6924   case X86::VSQRTPDZ256rkz:
6925   case X86::VSQRTPDZm:
6926   case X86::VSQRTPDZmb:
6927   case X86::VSQRTPDZmbk:
6928   case X86::VSQRTPDZmbkz:
6929   case X86::VSQRTPDZmk:
6930   case X86::VSQRTPDZmkz:
6931   case X86::VSQRTPDZr:
6932   case X86::VSQRTPDZrb:
6933   case X86::VSQRTPDZrbk:
6934   case X86::VSQRTPDZrbkz:
6935   case X86::VSQRTPDZrk:
6936   case X86::VSQRTPDZrkz:
6937   case X86::VSQRTPSZ128m:
6938   case X86::VSQRTPSZ128mb:
6939   case X86::VSQRTPSZ128mbk:
6940   case X86::VSQRTPSZ128mbkz:
6941   case X86::VSQRTPSZ128mk:
6942   case X86::VSQRTPSZ128mkz:
6943   case X86::VSQRTPSZ128r:
6944   case X86::VSQRTPSZ128rk:
6945   case X86::VSQRTPSZ128rkz:
6946   case X86::VSQRTPSZ256m:
6947   case X86::VSQRTPSZ256mb:
6948   case X86::VSQRTPSZ256mbk:
6949   case X86::VSQRTPSZ256mbkz:
6950   case X86::VSQRTPSZ256mk:
6951   case X86::VSQRTPSZ256mkz:
6952   case X86::VSQRTPSZ256r:
6953   case X86::VSQRTPSZ256rk:
6954   case X86::VSQRTPSZ256rkz:
6955   case X86::VSQRTPSZm:
6956   case X86::VSQRTPSZmb:
6957   case X86::VSQRTPSZmbk:
6958   case X86::VSQRTPSZmbkz:
6959   case X86::VSQRTPSZmk:
6960   case X86::VSQRTPSZmkz:
6961   case X86::VSQRTPSZr:
6962   case X86::VSQRTPSZrb:
6963   case X86::VSQRTPSZrbk:
6964   case X86::VSQRTPSZrbkz:
6965   case X86::VSQRTPSZrk:
6966   case X86::VSQRTPSZrkz:
6967   case X86::VSQRTSDZm:
6968   case X86::VSQRTSDZm_Int:
6969   case X86::VSQRTSDZm_Intk:
6970   case X86::VSQRTSDZm_Intkz:
6971   case X86::VSQRTSDZr:
6972   case X86::VSQRTSDZr_Int:
6973   case X86::VSQRTSDZr_Intk:
6974   case X86::VSQRTSDZr_Intkz:
6975   case X86::VSQRTSDZrb_Int:
6976   case X86::VSQRTSDZrb_Intk:
6977   case X86::VSQRTSDZrb_Intkz:
6978   case X86::VSQRTSSZm:
6979   case X86::VSQRTSSZm_Int:
6980   case X86::VSQRTSSZm_Intk:
6981   case X86::VSQRTSSZm_Intkz:
6982   case X86::VSQRTSSZr:
6983   case X86::VSQRTSSZr_Int:
6984   case X86::VSQRTSSZr_Intk:
6985   case X86::VSQRTSSZr_Intkz:
6986   case X86::VSQRTSSZrb_Int:
6987   case X86::VSQRTSSZrb_Intk:
6988   case X86::VSQRTSSZrb_Intkz:
6989 
6990   case X86::VGATHERDPDYrm:
6991   case X86::VGATHERDPDZ128rm:
6992   case X86::VGATHERDPDZ256rm:
6993   case X86::VGATHERDPDZrm:
6994   case X86::VGATHERDPDrm:
6995   case X86::VGATHERDPSYrm:
6996   case X86::VGATHERDPSZ128rm:
6997   case X86::VGATHERDPSZ256rm:
6998   case X86::VGATHERDPSZrm:
6999   case X86::VGATHERDPSrm:
7000   case X86::VGATHERPF0DPDm:
7001   case X86::VGATHERPF0DPSm:
7002   case X86::VGATHERPF0QPDm:
7003   case X86::VGATHERPF0QPSm:
7004   case X86::VGATHERPF1DPDm:
7005   case X86::VGATHERPF1DPSm:
7006   case X86::VGATHERPF1QPDm:
7007   case X86::VGATHERPF1QPSm:
7008   case X86::VGATHERQPDYrm:
7009   case X86::VGATHERQPDZ128rm:
7010   case X86::VGATHERQPDZ256rm:
7011   case X86::VGATHERQPDZrm:
7012   case X86::VGATHERQPDrm:
7013   case X86::VGATHERQPSYrm:
7014   case X86::VGATHERQPSZ128rm:
7015   case X86::VGATHERQPSZ256rm:
7016   case X86::VGATHERQPSZrm:
7017   case X86::VGATHERQPSrm:
7018   case X86::VPGATHERDDYrm:
7019   case X86::VPGATHERDDZ128rm:
7020   case X86::VPGATHERDDZ256rm:
7021   case X86::VPGATHERDDZrm:
7022   case X86::VPGATHERDDrm:
7023   case X86::VPGATHERDQYrm:
7024   case X86::VPGATHERDQZ128rm:
7025   case X86::VPGATHERDQZ256rm:
7026   case X86::VPGATHERDQZrm:
7027   case X86::VPGATHERDQrm:
7028   case X86::VPGATHERQDYrm:
7029   case X86::VPGATHERQDZ128rm:
7030   case X86::VPGATHERQDZ256rm:
7031   case X86::VPGATHERQDZrm:
7032   case X86::VPGATHERQDrm:
7033   case X86::VPGATHERQQYrm:
7034   case X86::VPGATHERQQZ128rm:
7035   case X86::VPGATHERQQZ256rm:
7036   case X86::VPGATHERQQZrm:
7037   case X86::VPGATHERQQrm:
7038   case X86::VSCATTERDPDZ128mr:
7039   case X86::VSCATTERDPDZ256mr:
7040   case X86::VSCATTERDPDZmr:
7041   case X86::VSCATTERDPSZ128mr:
7042   case X86::VSCATTERDPSZ256mr:
7043   case X86::VSCATTERDPSZmr:
7044   case X86::VSCATTERPF0DPDm:
7045   case X86::VSCATTERPF0DPSm:
7046   case X86::VSCATTERPF0QPDm:
7047   case X86::VSCATTERPF0QPSm:
7048   case X86::VSCATTERPF1DPDm:
7049   case X86::VSCATTERPF1DPSm:
7050   case X86::VSCATTERPF1QPDm:
7051   case X86::VSCATTERPF1QPSm:
7052   case X86::VSCATTERQPDZ128mr:
7053   case X86::VSCATTERQPDZ256mr:
7054   case X86::VSCATTERQPDZmr:
7055   case X86::VSCATTERQPSZ128mr:
7056   case X86::VSCATTERQPSZ256mr:
7057   case X86::VSCATTERQPSZmr:
7058   case X86::VPSCATTERDDZ128mr:
7059   case X86::VPSCATTERDDZ256mr:
7060   case X86::VPSCATTERDDZmr:
7061   case X86::VPSCATTERDQZ128mr:
7062   case X86::VPSCATTERDQZ256mr:
7063   case X86::VPSCATTERDQZmr:
7064   case X86::VPSCATTERQDZ128mr:
7065   case X86::VPSCATTERQDZ256mr:
7066   case X86::VPSCATTERQDZmr:
7067   case X86::VPSCATTERQQZ128mr:
7068   case X86::VPSCATTERQQZ256mr:
7069   case X86::VPSCATTERQQZmr:
7070     return true;
7071   }
7072 }
7073 
7074 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7075                                          const MachineRegisterInfo *MRI,
7076                                          const MachineInstr &DefMI,
7077                                          unsigned DefIdx,
7078                                          const MachineInstr &UseMI,
7079                                          unsigned UseIdx) const {
7080   return isHighLatencyDef(DefMI.getOpcode());
7081 }
7082 
7083 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7084                                            const MachineBasicBlock *MBB) const {
7085   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7086          "Reassociation needs binary operators");
7087 
7088   // Integer binary math/logic instructions have a third source operand:
7089   // the EFLAGS register. That operand must be both defined here and never
7090   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7091   // not change anything because rearranging the operands could affect other
7092   // instructions that depend on the exact status flags (zero, sign, etc.)
7093   // that are set by using these particular operands with this operation.
7094   if (Inst.getNumOperands() == 4) {
7095     assert(Inst.getOperand(3).isReg() &&
7096            Inst.getOperand(3).getReg() == X86::EFLAGS &&
7097            "Unexpected operand in reassociable instruction");
7098     if (!Inst.getOperand(3).isDead())
7099       return false;
7100   }
7101 
7102   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
7103 }
7104 
7105 // TODO: There are many more machine instruction opcodes to match:
7106 //       1. Other data types (integer, vectors)
7107 //       2. Other math / logic operations (xor, or)
7108 //       3. Other forms of the same operation (intrinsics and other variants)
7109 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
7110   switch (Inst.getOpcode()) {
7111   case X86::AND8rr:
7112   case X86::AND16rr:
7113   case X86::AND32rr:
7114   case X86::AND64rr:
7115   case X86::OR8rr:
7116   case X86::OR16rr:
7117   case X86::OR32rr:
7118   case X86::OR64rr:
7119   case X86::XOR8rr:
7120   case X86::XOR16rr:
7121   case X86::XOR32rr:
7122   case X86::XOR64rr:
7123   case X86::IMUL16rr:
7124   case X86::IMUL32rr:
7125   case X86::IMUL64rr:
7126   case X86::PANDrr:
7127   case X86::PORrr:
7128   case X86::PXORrr:
7129   case X86::ANDPDrr:
7130   case X86::ANDPSrr:
7131   case X86::ORPDrr:
7132   case X86::ORPSrr:
7133   case X86::XORPDrr:
7134   case X86::XORPSrr:
7135   case X86::PADDBrr:
7136   case X86::PADDWrr:
7137   case X86::PADDDrr:
7138   case X86::PADDQrr:
7139   case X86::VPANDrr:
7140   case X86::VPANDYrr:
7141   case X86::VPANDDZ128rr:
7142   case X86::VPANDDZ256rr:
7143   case X86::VPANDDZrr:
7144   case X86::VPANDQZ128rr:
7145   case X86::VPANDQZ256rr:
7146   case X86::VPANDQZrr:
7147   case X86::VPORrr:
7148   case X86::VPORYrr:
7149   case X86::VPORDZ128rr:
7150   case X86::VPORDZ256rr:
7151   case X86::VPORDZrr:
7152   case X86::VPORQZ128rr:
7153   case X86::VPORQZ256rr:
7154   case X86::VPORQZrr:
7155   case X86::VPXORrr:
7156   case X86::VPXORYrr:
7157   case X86::VPXORDZ128rr:
7158   case X86::VPXORDZ256rr:
7159   case X86::VPXORDZrr:
7160   case X86::VPXORQZ128rr:
7161   case X86::VPXORQZ256rr:
7162   case X86::VPXORQZrr:
7163   case X86::VANDPDrr:
7164   case X86::VANDPSrr:
7165   case X86::VANDPDYrr:
7166   case X86::VANDPSYrr:
7167   case X86::VANDPDZ128rr:
7168   case X86::VANDPSZ128rr:
7169   case X86::VANDPDZ256rr:
7170   case X86::VANDPSZ256rr:
7171   case X86::VANDPDZrr:
7172   case X86::VANDPSZrr:
7173   case X86::VORPDrr:
7174   case X86::VORPSrr:
7175   case X86::VORPDYrr:
7176   case X86::VORPSYrr:
7177   case X86::VORPDZ128rr:
7178   case X86::VORPSZ128rr:
7179   case X86::VORPDZ256rr:
7180   case X86::VORPSZ256rr:
7181   case X86::VORPDZrr:
7182   case X86::VORPSZrr:
7183   case X86::VXORPDrr:
7184   case X86::VXORPSrr:
7185   case X86::VXORPDYrr:
7186   case X86::VXORPSYrr:
7187   case X86::VXORPDZ128rr:
7188   case X86::VXORPSZ128rr:
7189   case X86::VXORPDZ256rr:
7190   case X86::VXORPSZ256rr:
7191   case X86::VXORPDZrr:
7192   case X86::VXORPSZrr:
7193   case X86::KADDBrr:
7194   case X86::KADDWrr:
7195   case X86::KADDDrr:
7196   case X86::KADDQrr:
7197   case X86::KANDBrr:
7198   case X86::KANDWrr:
7199   case X86::KANDDrr:
7200   case X86::KANDQrr:
7201   case X86::KORBrr:
7202   case X86::KORWrr:
7203   case X86::KORDrr:
7204   case X86::KORQrr:
7205   case X86::KXORBrr:
7206   case X86::KXORWrr:
7207   case X86::KXORDrr:
7208   case X86::KXORQrr:
7209   case X86::VPADDBrr:
7210   case X86::VPADDWrr:
7211   case X86::VPADDDrr:
7212   case X86::VPADDQrr:
7213   case X86::VPADDBYrr:
7214   case X86::VPADDWYrr:
7215   case X86::VPADDDYrr:
7216   case X86::VPADDQYrr:
7217   case X86::VPADDBZ128rr:
7218   case X86::VPADDWZ128rr:
7219   case X86::VPADDDZ128rr:
7220   case X86::VPADDQZ128rr:
7221   case X86::VPADDBZ256rr:
7222   case X86::VPADDWZ256rr:
7223   case X86::VPADDDZ256rr:
7224   case X86::VPADDQZ256rr:
7225   case X86::VPADDBZrr:
7226   case X86::VPADDWZrr:
7227   case X86::VPADDDZrr:
7228   case X86::VPADDQZrr:
7229   case X86::VPMULLWrr:
7230   case X86::VPMULLWYrr:
7231   case X86::VPMULLWZ128rr:
7232   case X86::VPMULLWZ256rr:
7233   case X86::VPMULLWZrr:
7234   case X86::VPMULLDrr:
7235   case X86::VPMULLDYrr:
7236   case X86::VPMULLDZ128rr:
7237   case X86::VPMULLDZ256rr:
7238   case X86::VPMULLDZrr:
7239   case X86::VPMULLQZ128rr:
7240   case X86::VPMULLQZ256rr:
7241   case X86::VPMULLQZrr:
7242   // Normal min/max instructions are not commutative because of NaN and signed
7243   // zero semantics, but these are. Thus, there's no need to check for global
7244   // relaxed math; the instructions themselves have the properties we need.
7245   case X86::MAXCPDrr:
7246   case X86::MAXCPSrr:
7247   case X86::MAXCSDrr:
7248   case X86::MAXCSSrr:
7249   case X86::MINCPDrr:
7250   case X86::MINCPSrr:
7251   case X86::MINCSDrr:
7252   case X86::MINCSSrr:
7253   case X86::VMAXCPDrr:
7254   case X86::VMAXCPSrr:
7255   case X86::VMAXCPDYrr:
7256   case X86::VMAXCPSYrr:
7257   case X86::VMAXCPDZ128rr:
7258   case X86::VMAXCPSZ128rr:
7259   case X86::VMAXCPDZ256rr:
7260   case X86::VMAXCPSZ256rr:
7261   case X86::VMAXCPDZrr:
7262   case X86::VMAXCPSZrr:
7263   case X86::VMAXCSDrr:
7264   case X86::VMAXCSSrr:
7265   case X86::VMAXCSDZrr:
7266   case X86::VMAXCSSZrr:
7267   case X86::VMINCPDrr:
7268   case X86::VMINCPSrr:
7269   case X86::VMINCPDYrr:
7270   case X86::VMINCPSYrr:
7271   case X86::VMINCPDZ128rr:
7272   case X86::VMINCPSZ128rr:
7273   case X86::VMINCPDZ256rr:
7274   case X86::VMINCPSZ256rr:
7275   case X86::VMINCPDZrr:
7276   case X86::VMINCPSZrr:
7277   case X86::VMINCSDrr:
7278   case X86::VMINCSSrr:
7279   case X86::VMINCSDZrr:
7280   case X86::VMINCSSZrr:
7281     return true;
7282   case X86::ADDPDrr:
7283   case X86::ADDPSrr:
7284   case X86::ADDSDrr:
7285   case X86::ADDSSrr:
7286   case X86::MULPDrr:
7287   case X86::MULPSrr:
7288   case X86::MULSDrr:
7289   case X86::MULSSrr:
7290   case X86::VADDPDrr:
7291   case X86::VADDPSrr:
7292   case X86::VADDPDYrr:
7293   case X86::VADDPSYrr:
7294   case X86::VADDPDZ128rr:
7295   case X86::VADDPSZ128rr:
7296   case X86::VADDPDZ256rr:
7297   case X86::VADDPSZ256rr:
7298   case X86::VADDPDZrr:
7299   case X86::VADDPSZrr:
7300   case X86::VADDSDrr:
7301   case X86::VADDSSrr:
7302   case X86::VADDSDZrr:
7303   case X86::VADDSSZrr:
7304   case X86::VMULPDrr:
7305   case X86::VMULPSrr:
7306   case X86::VMULPDYrr:
7307   case X86::VMULPSYrr:
7308   case X86::VMULPDZ128rr:
7309   case X86::VMULPSZ128rr:
7310   case X86::VMULPDZ256rr:
7311   case X86::VMULPSZ256rr:
7312   case X86::VMULPDZrr:
7313   case X86::VMULPSZrr:
7314   case X86::VMULSDrr:
7315   case X86::VMULSSrr:
7316   case X86::VMULSDZrr:
7317   case X86::VMULSSZrr:
7318     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
7319   default:
7320     return false;
7321   }
7322 }
7323 
7324 /// This is an architecture-specific helper function of reassociateOps.
7325 /// Set special operand attributes for new instructions after reassociation.
7326 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7327                                          MachineInstr &OldMI2,
7328                                          MachineInstr &NewMI1,
7329                                          MachineInstr &NewMI2) const {
7330   // Integer instructions define an implicit EFLAGS source register operand as
7331   // the third source (fourth total) operand.
7332   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7333     return;
7334 
7335   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7336          "Unexpected instruction type for reassociation");
7337 
7338   MachineOperand &OldOp1 = OldMI1.getOperand(3);
7339   MachineOperand &OldOp2 = OldMI2.getOperand(3);
7340   MachineOperand &NewOp1 = NewMI1.getOperand(3);
7341   MachineOperand &NewOp2 = NewMI2.getOperand(3);
7342 
7343   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7344          "Must have dead EFLAGS operand in reassociable instruction");
7345   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7346          "Must have dead EFLAGS operand in reassociable instruction");
7347 
7348   (void)OldOp1;
7349   (void)OldOp2;
7350 
7351   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7352          "Unexpected operand in reassociable instruction");
7353   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7354          "Unexpected operand in reassociable instruction");
7355 
7356   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7357   // of this pass or other passes. The EFLAGS operands must be dead in these new
7358   // instructions because the EFLAGS operands in the original instructions must
7359   // be dead in order for reassociation to occur.
7360   NewOp1.setIsDead();
7361   NewOp2.setIsDead();
7362 }
7363 
7364 std::pair<unsigned, unsigned>
7365 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7366   return std::make_pair(TF, 0u);
7367 }
7368 
7369 ArrayRef<std::pair<unsigned, const char *>>
7370 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7371   using namespace X86II;
7372   static const std::pair<unsigned, const char *> TargetFlags[] = {
7373       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7374       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7375       {MO_GOT, "x86-got"},
7376       {MO_GOTOFF, "x86-gotoff"},
7377       {MO_GOTPCREL, "x86-gotpcrel"},
7378       {MO_PLT, "x86-plt"},
7379       {MO_TLSGD, "x86-tlsgd"},
7380       {MO_TLSLD, "x86-tlsld"},
7381       {MO_TLSLDM, "x86-tlsldm"},
7382       {MO_GOTTPOFF, "x86-gottpoff"},
7383       {MO_INDNTPOFF, "x86-indntpoff"},
7384       {MO_TPOFF, "x86-tpoff"},
7385       {MO_DTPOFF, "x86-dtpoff"},
7386       {MO_NTPOFF, "x86-ntpoff"},
7387       {MO_GOTNTPOFF, "x86-gotntpoff"},
7388       {MO_DLLIMPORT, "x86-dllimport"},
7389       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7390       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7391       {MO_TLVP, "x86-tlvp"},
7392       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7393       {MO_SECREL, "x86-secrel"},
7394       {MO_COFFSTUB, "x86-coffstub"}};
7395   return makeArrayRef(TargetFlags);
7396 }
7397 
7398 namespace {
7399   /// Create Global Base Reg pass. This initializes the PIC
7400   /// global base register for x86-32.
7401   struct CGBR : public MachineFunctionPass {
7402     static char ID;
7403     CGBR() : MachineFunctionPass(ID) {}
7404 
7405     bool runOnMachineFunction(MachineFunction &MF) override {
7406       const X86TargetMachine *TM =
7407         static_cast<const X86TargetMachine *>(&MF.getTarget());
7408       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
7409 
7410       // Don't do anything in the 64-bit small and kernel code models. They use
7411       // RIP-relative addressing for everything.
7412       if (STI.is64Bit() && (TM->getCodeModel() == CodeModel::Small ||
7413                             TM->getCodeModel() == CodeModel::Kernel))
7414         return false;
7415 
7416       // Only emit a global base reg in PIC mode.
7417       if (!TM->isPositionIndependent())
7418         return false;
7419 
7420       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7421       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7422 
7423       // If we didn't need a GlobalBaseReg, don't insert code.
7424       if (GlobalBaseReg == 0)
7425         return false;
7426 
7427       // Insert the set of GlobalBaseReg into the first MBB of the function
7428       MachineBasicBlock &FirstMBB = MF.front();
7429       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7430       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7431       MachineRegisterInfo &RegInfo = MF.getRegInfo();
7432       const X86InstrInfo *TII = STI.getInstrInfo();
7433 
7434       unsigned PC;
7435       if (STI.isPICStyleGOT())
7436         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7437       else
7438         PC = GlobalBaseReg;
7439 
7440       if (STI.is64Bit()) {
7441         if (TM->getCodeModel() == CodeModel::Medium) {
7442           // In the medium code model, use a RIP-relative LEA to materialize the
7443           // GOT.
7444           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
7445               .addReg(X86::RIP)
7446               .addImm(0)
7447               .addReg(0)
7448               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_")
7449               .addReg(0);
7450         } else if (TM->getCodeModel() == CodeModel::Large) {
7451           // In the large code model, we are aiming for this code, though the
7452           // register allocation may vary:
7453           //   leaq .LN$pb(%rip), %rax
7454           //   movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx
7455           //   addq %rcx, %rax
7456           // RAX now holds address of _GLOBAL_OFFSET_TABLE_.
7457           unsigned PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7458           unsigned GOTReg =
7459               RegInfo.createVirtualRegister(&X86::GR64RegClass);
7460           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
7461               .addReg(X86::RIP)
7462               .addImm(0)
7463               .addReg(0)
7464               .addSym(MF.getPICBaseSymbol())
7465               .addReg(0);
7466           std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
7467           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
7468               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7469                                  X86II::MO_PIC_BASE_OFFSET);
7470           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
7471               .addReg(PBReg, RegState::Kill)
7472               .addReg(GOTReg, RegState::Kill);
7473         } else {
7474           llvm_unreachable("unexpected code model");
7475         }
7476       } else {
7477         // Operand of MovePCtoStack is completely ignored by asm printer. It's
7478         // only used in JIT code emission as displacement to pc.
7479         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7480 
7481         // If we're using vanilla 'GOT' PIC style, we should use relative
7482         // addressing not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
7483         if (STI.isPICStyleGOT()) {
7484           // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel],
7485           // %some_register
7486           BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7487               .addReg(PC)
7488               .addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7489                                  X86II::MO_GOT_ABSOLUTE_ADDRESS);
7490         }
7491       }
7492 
7493       return true;
7494     }
7495 
7496     StringRef getPassName() const override {
7497       return "X86 PIC Global Base Reg Initialization";
7498     }
7499 
7500     void getAnalysisUsage(AnalysisUsage &AU) const override {
7501       AU.setPreservesCFG();
7502       MachineFunctionPass::getAnalysisUsage(AU);
7503     }
7504   };
7505 }
7506 
7507 char CGBR::ID = 0;
7508 FunctionPass*
7509 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
7510 
7511 namespace {
7512   struct LDTLSCleanup : public MachineFunctionPass {
7513     static char ID;
7514     LDTLSCleanup() : MachineFunctionPass(ID) {}
7515 
7516     bool runOnMachineFunction(MachineFunction &MF) override {
7517       if (skipFunction(MF.getFunction()))
7518         return false;
7519 
7520       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
7521       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7522         // No point folding accesses if there isn't at least two.
7523         return false;
7524       }
7525 
7526       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7527       return VisitNode(DT->getRootNode(), 0);
7528     }
7529 
7530     // Visit the dominator subtree rooted at Node in pre-order.
7531     // If TLSBaseAddrReg is non-null, then use that to replace any
7532     // TLS_base_addr instructions. Otherwise, create the register
7533     // when the first such instruction is seen, and then use it
7534     // as we encounter more instructions.
7535     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7536       MachineBasicBlock *BB = Node->getBlock();
7537       bool Changed = false;
7538 
7539       // Traverse the current block.
7540       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7541            ++I) {
7542         switch (I->getOpcode()) {
7543           case X86::TLS_base_addr32:
7544           case X86::TLS_base_addr64:
7545             if (TLSBaseAddrReg)
7546               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
7547             else
7548               I = SetRegister(*I, &TLSBaseAddrReg);
7549             Changed = true;
7550             break;
7551           default:
7552             break;
7553         }
7554       }
7555 
7556       // Visit the children of this block in the dominator tree.
7557       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7558            I != E; ++I) {
7559         Changed |= VisitNode(*I, TLSBaseAddrReg);
7560       }
7561 
7562       return Changed;
7563     }
7564 
7565     // Replace the TLS_base_addr instruction I with a copy from
7566     // TLSBaseAddrReg, returning the new instruction.
7567     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
7568                                          unsigned TLSBaseAddrReg) {
7569       MachineFunction *MF = I.getParent()->getParent();
7570       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7571       const bool is64Bit = STI.is64Bit();
7572       const X86InstrInfo *TII = STI.getInstrInfo();
7573 
7574       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7575       MachineInstr *Copy =
7576           BuildMI(*I.getParent(), I, I.getDebugLoc(),
7577                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
7578               .addReg(TLSBaseAddrReg);
7579 
7580       // Erase the TLS_base_addr instruction.
7581       I.eraseFromParent();
7582 
7583       return Copy;
7584     }
7585 
7586     // Create a virtual register in *TLSBaseAddrReg, and populate it by
7587     // inserting a copy instruction after I. Returns the new instruction.
7588     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
7589       MachineFunction *MF = I.getParent()->getParent();
7590       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7591       const bool is64Bit = STI.is64Bit();
7592       const X86InstrInfo *TII = STI.getInstrInfo();
7593 
7594       // Create a virtual register for the TLS base address.
7595       MachineRegisterInfo &RegInfo = MF->getRegInfo();
7596       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7597                                                       ? &X86::GR64RegClass
7598                                                       : &X86::GR32RegClass);
7599 
7600       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7601       MachineInstr *Next = I.getNextNode();
7602       MachineInstr *Copy =
7603           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
7604                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
7605               .addReg(is64Bit ? X86::RAX : X86::EAX);
7606 
7607       return Copy;
7608     }
7609 
7610     StringRef getPassName() const override {
7611       return "Local Dynamic TLS Access Clean-up";
7612     }
7613 
7614     void getAnalysisUsage(AnalysisUsage &AU) const override {
7615       AU.setPreservesCFG();
7616       AU.addRequired<MachineDominatorTree>();
7617       MachineFunctionPass::getAnalysisUsage(AU);
7618     }
7619   };
7620 }
7621 
7622 char LDTLSCleanup::ID = 0;
7623 FunctionPass*
7624 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
7625 
7626 /// Constants defining how certain sequences should be outlined.
7627 ///
7628 /// \p MachineOutlinerDefault implies that the function is called with a call
7629 /// instruction, and a return must be emitted for the outlined function frame.
7630 ///
7631 /// That is,
7632 ///
7633 /// I1                                 OUTLINED_FUNCTION:
7634 /// I2 --> call OUTLINED_FUNCTION       I1
7635 /// I3                                  I2
7636 ///                                     I3
7637 ///                                     ret
7638 ///
7639 /// * Call construction overhead: 1 (call instruction)
7640 /// * Frame construction overhead: 1 (return instruction)
7641 ///
7642 /// \p MachineOutlinerTailCall implies that the function is being tail called.
7643 /// A jump is emitted instead of a call, and the return is already present in
7644 /// the outlined sequence. That is,
7645 ///
7646 /// I1                                 OUTLINED_FUNCTION:
7647 /// I2 --> jmp OUTLINED_FUNCTION       I1
7648 /// ret                                I2
7649 ///                                    ret
7650 ///
7651 /// * Call construction overhead: 1 (jump instruction)
7652 /// * Frame construction overhead: 0 (don't need to return)
7653 ///
7654 enum MachineOutlinerClass {
7655   MachineOutlinerDefault,
7656   MachineOutlinerTailCall
7657 };
7658 
7659 outliner::OutlinedFunction X86InstrInfo::getOutliningCandidateInfo(
7660     std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
7661   unsigned SequenceSize =
7662       std::accumulate(RepeatedSequenceLocs[0].front(),
7663                       std::next(RepeatedSequenceLocs[0].back()), 0,
7664                       [](unsigned Sum, const MachineInstr &MI) {
7665                         // FIXME: x86 doesn't implement getInstSizeInBytes, so
7666                         // we can't tell the cost.  Just assume each instruction
7667                         // is one byte.
7668                         if (MI.isDebugInstr() || MI.isKill())
7669                           return Sum;
7670                         return Sum + 1;
7671                       });
7672 
7673   // FIXME: Use real size in bytes for call and ret instructions.
7674   if (RepeatedSequenceLocs[0].back()->isTerminator()) {
7675     for (outliner::Candidate &C : RepeatedSequenceLocs)
7676       C.setCallInfo(MachineOutlinerTailCall, 1);
7677 
7678     return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize,
7679                                       0, // Number of bytes to emit frame.
7680                                       MachineOutlinerTailCall // Type of frame.
7681     );
7682   }
7683 
7684   for (outliner::Candidate &C : RepeatedSequenceLocs)
7685     C.setCallInfo(MachineOutlinerDefault, 1);
7686 
7687   return outliner::OutlinedFunction(RepeatedSequenceLocs, SequenceSize, 1,
7688                                     MachineOutlinerDefault);
7689 }
7690 
7691 bool X86InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
7692                                            bool OutlineFromLinkOnceODRs) const {
7693   const Function &F = MF.getFunction();
7694 
7695   // Does the function use a red zone? If it does, then we can't risk messing
7696   // with the stack.
7697   if (!F.hasFnAttribute(Attribute::NoRedZone)) {
7698     // It could have a red zone. If it does, then we don't want to touch it.
7699     const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7700     if (!X86FI || X86FI->getUsesRedZone())
7701       return false;
7702   }
7703 
7704   // If we *don't* want to outline from things that could potentially be deduped
7705   // then return false.
7706   if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
7707       return false;
7708 
7709   // This function is viable for outlining, so return true.
7710   return true;
7711 }
7712 
7713 outliner::InstrType
7714 X86InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,  unsigned Flags) const {
7715   MachineInstr &MI = *MIT;
7716   // Don't allow debug values to impact outlining type.
7717   if (MI.isDebugInstr() || MI.isIndirectDebugValue())
7718     return outliner::InstrType::Invisible;
7719 
7720   // At this point, KILL instructions don't really tell us much so we can go
7721   // ahead and skip over them.
7722   if (MI.isKill())
7723     return outliner::InstrType::Invisible;
7724 
7725   // Is this a tail call? If yes, we can outline as a tail call.
7726   if (isTailCall(MI))
7727     return outliner::InstrType::Legal;
7728 
7729   // Is this the terminator of a basic block?
7730   if (MI.isTerminator() || MI.isReturn()) {
7731 
7732     // Does its parent have any successors in its MachineFunction?
7733     if (MI.getParent()->succ_empty())
7734       return outliner::InstrType::Legal;
7735 
7736     // It does, so we can't tail call it.
7737     return outliner::InstrType::Illegal;
7738   }
7739 
7740   // Don't outline anything that modifies or reads from the stack pointer.
7741   //
7742   // FIXME: There are instructions which are being manually built without
7743   // explicit uses/defs so we also have to check the MCInstrDesc. We should be
7744   // able to remove the extra checks once those are fixed up. For example,
7745   // sometimes we might get something like %rax = POP64r 1. This won't be
7746   // caught by modifiesRegister or readsRegister even though the instruction
7747   // really ought to be formed so that modifiesRegister/readsRegister would
7748   // catch it.
7749   if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
7750       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
7751       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
7752     return outliner::InstrType::Illegal;
7753 
7754   // Outlined calls change the instruction pointer, so don't read from it.
7755   if (MI.readsRegister(X86::RIP, &RI) ||
7756       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
7757       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
7758     return outliner::InstrType::Illegal;
7759 
7760   // Positions can't safely be outlined.
7761   if (MI.isPosition())
7762     return outliner::InstrType::Illegal;
7763 
7764   // Make sure none of the operands of this instruction do anything tricky.
7765   for (const MachineOperand &MOP : MI.operands())
7766     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||
7767         MOP.isTargetIndex())
7768       return outliner::InstrType::Illegal;
7769 
7770   return outliner::InstrType::Legal;
7771 }
7772 
7773 void X86InstrInfo::buildOutlinedFrame(MachineBasicBlock &MBB,
7774                                           MachineFunction &MF,
7775                                           const outliner::OutlinedFunction &OF)
7776                                           const {
7777   // If we're a tail call, we already have a return, so don't do anything.
7778   if (OF.FrameConstructionID == MachineOutlinerTailCall)
7779     return;
7780 
7781   // We're a normal call, so our sequence doesn't have a return instruction.
7782   // Add it in.
7783   MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
7784   MBB.insert(MBB.end(), retq);
7785 }
7786 
7787 MachineBasicBlock::iterator
7788 X86InstrInfo::insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
7789                                  MachineBasicBlock::iterator &It,
7790                                  MachineFunction &MF,
7791                                  const outliner::Candidate &C) const {
7792   // Is it a tail call?
7793   if (C.CallConstructionID == MachineOutlinerTailCall) {
7794     // Yes, just insert a JMP.
7795     It = MBB.insert(It,
7796                   BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
7797                       .addGlobalAddress(M.getNamedValue(MF.getName())));
7798   } else {
7799     // No, insert a call.
7800     It = MBB.insert(It,
7801                   BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
7802                       .addGlobalAddress(M.getNamedValue(MF.getName())));
7803   }
7804 
7805   return It;
7806 }
7807 
7808 #define GET_INSTRINFO_HELPERS
7809 #include "X86GenInstrInfo.inc"
7810