1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LivePhysRegs.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineDominators.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/LLVMContext.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
41 
42 using namespace llvm;
43 
44 #define DEBUG_TYPE "x86-instr-info"
45 
46 #define GET_INSTRINFO_CTOR_DTOR
47 #include "X86GenInstrInfo.inc"
48 
49 static cl::opt<bool>
50 NoFusing("disable-spill-fusing",
51          cl::desc("Disable fusing of spill code into instructions"));
52 static cl::opt<bool>
53 PrintFailedFusing("print-failed-fuse-candidates",
54                   cl::desc("Print instructions that the allocator wants to"
55                            " fuse, but the X86 backend currently can't"),
56                   cl::Hidden);
57 static cl::opt<bool>
58 ReMatPICStubLoad("remat-pic-stub-load",
59                  cl::desc("Re-materialize load from stub in PIC mode"),
60                  cl::init(false), cl::Hidden);
61 static cl::opt<unsigned>
62 PartialRegUpdateClearance("partial-reg-update-clearance",
63                           cl::desc("Clearance between two register writes "
64                                    "for inserting XOR to avoid partial "
65                                    "register update"),
66                           cl::init(64), cl::Hidden);
67 static cl::opt<unsigned>
68 UndefRegClearance("undef-reg-clearance",
69                   cl::desc("How many idle instructions we would like before "
70                            "certain undef register reads"),
71                   cl::init(128), cl::Hidden);
72 
73 enum {
74   // Select which memory operand is being unfolded.
75   // (stored in bits 0 - 3)
76   TB_INDEX_0    = 0,
77   TB_INDEX_1    = 1,
78   TB_INDEX_2    = 2,
79   TB_INDEX_3    = 3,
80   TB_INDEX_4    = 4,
81   TB_INDEX_MASK = 0xf,
82 
83   // Do not insert the reverse map (MemOp -> RegOp) into the table.
84   // This may be needed because there is a many -> one mapping.
85   TB_NO_REVERSE   = 1 << 4,
86 
87   // Do not insert the forward map (RegOp -> MemOp) into the table.
88   // This is needed for Native Client, which prohibits branch
89   // instructions from using a memory operand.
90   TB_NO_FORWARD   = 1 << 5,
91 
92   TB_FOLDED_LOAD  = 1 << 6,
93   TB_FOLDED_STORE = 1 << 7,
94 
95   // Minimum alignment required for load/store.
96   // Used for RegOp->MemOp conversion.
97   // (stored in bits 8 - 15)
98   TB_ALIGN_SHIFT = 8,
99   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
100   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
101   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
102   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
103   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
104 };
105 
106 struct X86MemoryFoldTableEntry {
107   uint16_t RegOp;
108   uint16_t MemOp;
109   uint16_t Flags;
110 };
111 
112 // Pin the vtable to this file.
113 void X86InstrInfo::anchor() {}
114 
115 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
116     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117                                                : X86::ADJCALLSTACKDOWN32),
118                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119                                                : X86::ADJCALLSTACKUP32),
120                       X86::CATCHRET,
121                       (STI.is64Bit() ? X86::RETQ : X86::RETL)),
122       Subtarget(STI), RI(STI.getTargetTriple()) {
123 
124   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
125     { X86::ADC32ri,     X86::ADC32mi,    0 },
126     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
127     { X86::ADC32rr,     X86::ADC32mr,    0 },
128     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
129     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
130     { X86::ADC64rr,     X86::ADC64mr,    0 },
131     { X86::ADD16ri,     X86::ADD16mi,    0 },
132     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
133     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
134     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
135     { X86::ADD16rr,     X86::ADD16mr,    0 },
136     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
137     { X86::ADD32ri,     X86::ADD32mi,    0 },
138     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
139     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
140     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
141     { X86::ADD32rr,     X86::ADD32mr,    0 },
142     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
143     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
144     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
145     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
146     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
147     { X86::ADD64rr,     X86::ADD64mr,    0 },
148     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
149     { X86::ADD8ri,      X86::ADD8mi,     0 },
150     { X86::ADD8rr,      X86::ADD8mr,     0 },
151     { X86::AND16ri,     X86::AND16mi,    0 },
152     { X86::AND16ri8,    X86::AND16mi8,   0 },
153     { X86::AND16rr,     X86::AND16mr,    0 },
154     { X86::AND32ri,     X86::AND32mi,    0 },
155     { X86::AND32ri8,    X86::AND32mi8,   0 },
156     { X86::AND32rr,     X86::AND32mr,    0 },
157     { X86::AND64ri32,   X86::AND64mi32,  0 },
158     { X86::AND64ri8,    X86::AND64mi8,   0 },
159     { X86::AND64rr,     X86::AND64mr,    0 },
160     { X86::AND8ri,      X86::AND8mi,     0 },
161     { X86::AND8rr,      X86::AND8mr,     0 },
162     { X86::DEC16r,      X86::DEC16m,     0 },
163     { X86::DEC32r,      X86::DEC32m,     0 },
164     { X86::DEC64r,      X86::DEC64m,     0 },
165     { X86::DEC8r,       X86::DEC8m,      0 },
166     { X86::INC16r,      X86::INC16m,     0 },
167     { X86::INC32r,      X86::INC32m,     0 },
168     { X86::INC64r,      X86::INC64m,     0 },
169     { X86::INC8r,       X86::INC8m,      0 },
170     { X86::NEG16r,      X86::NEG16m,     0 },
171     { X86::NEG32r,      X86::NEG32m,     0 },
172     { X86::NEG64r,      X86::NEG64m,     0 },
173     { X86::NEG8r,       X86::NEG8m,      0 },
174     { X86::NOT16r,      X86::NOT16m,     0 },
175     { X86::NOT32r,      X86::NOT32m,     0 },
176     { X86::NOT64r,      X86::NOT64m,     0 },
177     { X86::NOT8r,       X86::NOT8m,      0 },
178     { X86::OR16ri,      X86::OR16mi,     0 },
179     { X86::OR16ri8,     X86::OR16mi8,    0 },
180     { X86::OR16rr,      X86::OR16mr,     0 },
181     { X86::OR32ri,      X86::OR32mi,     0 },
182     { X86::OR32ri8,     X86::OR32mi8,    0 },
183     { X86::OR32rr,      X86::OR32mr,     0 },
184     { X86::OR64ri32,    X86::OR64mi32,   0 },
185     { X86::OR64ri8,     X86::OR64mi8,    0 },
186     { X86::OR64rr,      X86::OR64mr,     0 },
187     { X86::OR8ri,       X86::OR8mi,      0 },
188     { X86::OR8rr,       X86::OR8mr,      0 },
189     { X86::ROL16r1,     X86::ROL16m1,    0 },
190     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
191     { X86::ROL16ri,     X86::ROL16mi,    0 },
192     { X86::ROL32r1,     X86::ROL32m1,    0 },
193     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
194     { X86::ROL32ri,     X86::ROL32mi,    0 },
195     { X86::ROL64r1,     X86::ROL64m1,    0 },
196     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
197     { X86::ROL64ri,     X86::ROL64mi,    0 },
198     { X86::ROL8r1,      X86::ROL8m1,     0 },
199     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
200     { X86::ROL8ri,      X86::ROL8mi,     0 },
201     { X86::ROR16r1,     X86::ROR16m1,    0 },
202     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
203     { X86::ROR16ri,     X86::ROR16mi,    0 },
204     { X86::ROR32r1,     X86::ROR32m1,    0 },
205     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
206     { X86::ROR32ri,     X86::ROR32mi,    0 },
207     { X86::ROR64r1,     X86::ROR64m1,    0 },
208     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
209     { X86::ROR64ri,     X86::ROR64mi,    0 },
210     { X86::ROR8r1,      X86::ROR8m1,     0 },
211     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
212     { X86::ROR8ri,      X86::ROR8mi,     0 },
213     { X86::SAR16r1,     X86::SAR16m1,    0 },
214     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
215     { X86::SAR16ri,     X86::SAR16mi,    0 },
216     { X86::SAR32r1,     X86::SAR32m1,    0 },
217     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
218     { X86::SAR32ri,     X86::SAR32mi,    0 },
219     { X86::SAR64r1,     X86::SAR64m1,    0 },
220     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
221     { X86::SAR64ri,     X86::SAR64mi,    0 },
222     { X86::SAR8r1,      X86::SAR8m1,     0 },
223     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
224     { X86::SAR8ri,      X86::SAR8mi,     0 },
225     { X86::SBB32ri,     X86::SBB32mi,    0 },
226     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
227     { X86::SBB32rr,     X86::SBB32mr,    0 },
228     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
229     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
230     { X86::SBB64rr,     X86::SBB64mr,    0 },
231     { X86::SHL16r1,     X86::SHL16m1,    0 },
232     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
233     { X86::SHL16ri,     X86::SHL16mi,    0 },
234     { X86::SHL32r1,     X86::SHL32m1,    0 },
235     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
236     { X86::SHL32ri,     X86::SHL32mi,    0 },
237     { X86::SHL64r1,     X86::SHL64m1,    0 },
238     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
239     { X86::SHL64ri,     X86::SHL64mi,    0 },
240     { X86::SHL8r1,      X86::SHL8m1,     0 },
241     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
242     { X86::SHL8ri,      X86::SHL8mi,     0 },
243     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
244     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
245     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
246     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
247     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
248     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
249     { X86::SHR16r1,     X86::SHR16m1,    0 },
250     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
251     { X86::SHR16ri,     X86::SHR16mi,    0 },
252     { X86::SHR32r1,     X86::SHR32m1,    0 },
253     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
254     { X86::SHR32ri,     X86::SHR32mi,    0 },
255     { X86::SHR64r1,     X86::SHR64m1,    0 },
256     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
257     { X86::SHR64ri,     X86::SHR64mi,    0 },
258     { X86::SHR8r1,      X86::SHR8m1,     0 },
259     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
260     { X86::SHR8ri,      X86::SHR8mi,     0 },
261     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
262     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
263     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
264     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
265     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
266     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
267     { X86::SUB16ri,     X86::SUB16mi,    0 },
268     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
269     { X86::SUB16rr,     X86::SUB16mr,    0 },
270     { X86::SUB32ri,     X86::SUB32mi,    0 },
271     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
272     { X86::SUB32rr,     X86::SUB32mr,    0 },
273     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
274     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
275     { X86::SUB64rr,     X86::SUB64mr,    0 },
276     { X86::SUB8ri,      X86::SUB8mi,     0 },
277     { X86::SUB8rr,      X86::SUB8mr,     0 },
278     { X86::XOR16ri,     X86::XOR16mi,    0 },
279     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
280     { X86::XOR16rr,     X86::XOR16mr,    0 },
281     { X86::XOR32ri,     X86::XOR32mi,    0 },
282     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
283     { X86::XOR32rr,     X86::XOR32mr,    0 },
284     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
285     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
286     { X86::XOR64rr,     X86::XOR64mr,    0 },
287     { X86::XOR8ri,      X86::XOR8mi,     0 },
288     { X86::XOR8rr,      X86::XOR8mr,     0 }
289   };
290 
291   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
292     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
293                   Entry.RegOp, Entry.MemOp,
294                   // Index 0, folded load and store, no alignment requirement.
295                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
296   }
297 
298   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
299     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
300     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
301     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
302     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
303     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
304     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
305     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
306     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
307     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
308     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
309     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
310     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
311     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
312     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
313     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
314     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
315     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
316     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
317     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
318     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
319     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
320     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
321     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
322     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
323     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
324     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
325     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
326     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
327     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
328     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
329     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
330     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
331     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
332     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
333     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
334     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
335     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
336     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
337     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
338     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
339     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
340     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
341     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
342     { X86::MOVDQUrr,    X86::MOVDQUmr,      TB_FOLDED_STORE },
343     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
344     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
345     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
346     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
347     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
348     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
349     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
350     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
351     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
352     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
353     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
354     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
355     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
356     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
357     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
358     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
359     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
360     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
361     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
362     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
363     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
364     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
365     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
366     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
367     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
368     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
369     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
370     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
371     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
372     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
373     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
374     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
375     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
376     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
377     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
378     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
379     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
380     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
381 
382     // AVX 128-bit versions of foldable instructions
383     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
384     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
385     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
386     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
387     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
388     { X86::VMOVDQUrr,   X86::VMOVDQUmr,     TB_FOLDED_STORE },
389     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
390     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
391     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
392     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
393     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
394     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
395     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
396     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
397 
398     // AVX 256-bit foldable instructions
399     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
400     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
401     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
402     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
403     { X86::VMOVDQUYrr,  X86::VMOVDQUYmr,    TB_FOLDED_STORE },
404     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
405     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
406 
407     // AVX-512 foldable instructions
408     { X86::VEXTRACTF32x4Zrr,X86::VEXTRACTF32x4Zmr, TB_FOLDED_STORE },
409     { X86::VEXTRACTF32x8Zrr,X86::VEXTRACTF32x8Zmr, TB_FOLDED_STORE },
410     { X86::VEXTRACTF64x2Zrr,X86::VEXTRACTF64x2Zmr, TB_FOLDED_STORE },
411     { X86::VEXTRACTF64x4Zrr,X86::VEXTRACTF64x4Zmr, TB_FOLDED_STORE },
412     { X86::VEXTRACTI32x4Zrr,X86::VEXTRACTI32x4Zmr, TB_FOLDED_STORE },
413     { X86::VEXTRACTI32x8Zrr,X86::VEXTRACTI32x8Zmr, TB_FOLDED_STORE },
414     { X86::VEXTRACTI64x2Zrr,X86::VEXTRACTI64x2Zmr, TB_FOLDED_STORE },
415     { X86::VEXTRACTI64x4Zrr,X86::VEXTRACTI64x4Zmr, TB_FOLDED_STORE },
416     { X86::VEXTRACTPSZrr,   X86::VEXTRACTPSZmr,    TB_FOLDED_STORE },
417     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
418     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
419     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
420     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
421     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
422     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
423     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
424     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
425     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
426     { X86::VMOVPQIto64Zrr,  X86::VMOVPQI2QIZmr, TB_FOLDED_STORE },
427     { X86::VMOVSDto64Zrr,   X86::VMOVSDto64Zmr, TB_FOLDED_STORE },
428     { X86::VMOVSS2DIZrr,    X86::VMOVSS2DIZmr,  TB_FOLDED_STORE },
429     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
430     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
431     { X86::VPEXTRDZrr,      X86::VPEXTRDZmr,    TB_FOLDED_STORE },
432     { X86::VPEXTRQZrr,      X86::VPEXTRQZmr,    TB_FOLDED_STORE },
433     { X86::VPMOVDBZrr,      X86::VPMOVDBZmr,    TB_FOLDED_STORE },
434     { X86::VPMOVDWZrr,      X86::VPMOVDWZmr,    TB_FOLDED_STORE },
435     { X86::VPMOVQDZrr,      X86::VPMOVQDZmr,    TB_FOLDED_STORE },
436     { X86::VPMOVQWZrr,      X86::VPMOVQWZmr,    TB_FOLDED_STORE },
437     { X86::VPMOVWBZrr,      X86::VPMOVWBZmr,    TB_FOLDED_STORE },
438     { X86::VPMOVSDBZrr,     X86::VPMOVSDBZmr,   TB_FOLDED_STORE },
439     { X86::VPMOVSDWZrr,     X86::VPMOVSDWZmr,   TB_FOLDED_STORE },
440     { X86::VPMOVSQDZrr,     X86::VPMOVSQDZmr,   TB_FOLDED_STORE },
441     { X86::VPMOVSQWZrr,     X86::VPMOVSQWZmr,   TB_FOLDED_STORE },
442     { X86::VPMOVSWBZrr,     X86::VPMOVSWBZmr,   TB_FOLDED_STORE },
443     { X86::VPMOVUSDBZrr,    X86::VPMOVUSDBZmr,  TB_FOLDED_STORE },
444     { X86::VPMOVUSDWZrr,    X86::VPMOVUSDWZmr,  TB_FOLDED_STORE },
445     { X86::VPMOVUSQDZrr,    X86::VPMOVUSQDZmr,  TB_FOLDED_STORE },
446     { X86::VPMOVUSQWZrr,    X86::VPMOVUSQWZmr,  TB_FOLDED_STORE },
447     { X86::VPMOVUSWBZrr,    X86::VPMOVUSWBZmr,  TB_FOLDED_STORE },
448 
449     // AVX-512 foldable instructions (256-bit versions)
450     { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256mr, TB_FOLDED_STORE },
451     { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256mr, TB_FOLDED_STORE },
452     { X86::VEXTRACTI32x4Z256rr,X86::VEXTRACTI32x4Z256mr, TB_FOLDED_STORE },
453     { X86::VEXTRACTI64x2Z256rr,X86::VEXTRACTI64x2Z256mr, TB_FOLDED_STORE },
454     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
455     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
456     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
457     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
458     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
459     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
460     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
461     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
462     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
463     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
464     { X86::VPMOVDWZ256rr,      X86::VPMOVDWZ256mr,    TB_FOLDED_STORE },
465     { X86::VPMOVQDZ256rr,      X86::VPMOVQDZ256mr,    TB_FOLDED_STORE },
466     { X86::VPMOVWBZ256rr,      X86::VPMOVWBZ256mr,    TB_FOLDED_STORE },
467     { X86::VPMOVSDWZ256rr,     X86::VPMOVSDWZ256mr,   TB_FOLDED_STORE },
468     { X86::VPMOVSQDZ256rr,     X86::VPMOVSQDZ256mr,   TB_FOLDED_STORE },
469     { X86::VPMOVSWBZ256rr,     X86::VPMOVSWBZ256mr,   TB_FOLDED_STORE },
470     { X86::VPMOVUSDWZ256rr,    X86::VPMOVUSDWZ256mr,  TB_FOLDED_STORE },
471     { X86::VPMOVUSQDZ256rr,    X86::VPMOVUSQDZ256mr,  TB_FOLDED_STORE },
472     { X86::VPMOVUSWBZ256rr,    X86::VPMOVUSWBZ256mr,  TB_FOLDED_STORE },
473 
474     // AVX-512 foldable instructions (128-bit versions)
475     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
476     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
477     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
478     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
479     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
480     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
481     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
482     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
483     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
484     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
485 
486     // F16C foldable instructions
487     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
488     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
489   };
490 
491   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
492     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
493                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
494   }
495 
496   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
497     { X86::BSF16rr,         X86::BSF16rm,             0 },
498     { X86::BSF32rr,         X86::BSF32rm,             0 },
499     { X86::BSF64rr,         X86::BSF64rm,             0 },
500     { X86::BSR16rr,         X86::BSR16rm,             0 },
501     { X86::BSR32rr,         X86::BSR32rm,             0 },
502     { X86::BSR64rr,         X86::BSR64rm,             0 },
503     { X86::CMP16rr,         X86::CMP16rm,             0 },
504     { X86::CMP32rr,         X86::CMP32rm,             0 },
505     { X86::CMP64rr,         X86::CMP64rm,             0 },
506     { X86::CMP8rr,          X86::CMP8rm,              0 },
507     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
508     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
509     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
510     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
511     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
512     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
513     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
514     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
515     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
516     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
517     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
518     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
519     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
520     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
521     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
522     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
523     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        TB_NO_REVERSE },
524     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        TB_NO_REVERSE },
525     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        TB_NO_REVERSE },
526     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          TB_NO_REVERSE },
527     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        TB_NO_REVERSE },
528     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          TB_NO_REVERSE },
529     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_NO_REVERSE },
530     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
531     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
532     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
533     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
534     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_NO_REVERSE },
535     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
536     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
537     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  TB_NO_REVERSE },
538     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     TB_NO_REVERSE },
539     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  TB_NO_REVERSE },
540     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     TB_NO_REVERSE },
541     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       TB_NO_REVERSE },
542     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       TB_NO_REVERSE },
543     { X86::MOV16rr,         X86::MOV16rm,             0 },
544     { X86::MOV32rr,         X86::MOV32rm,             0 },
545     { X86::MOV64rr,         X86::MOV64rm,             0 },
546     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
547     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
548     { X86::MOV8rr,          X86::MOV8rm,              0 },
549     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
550     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
551     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           TB_NO_REVERSE },
552     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
553     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
554     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
555     { X86::MOVDQUrr,        X86::MOVDQUrm,            0 },
556     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
557     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
558     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
559     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
560     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
561     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
562     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
563     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
564     { X86::MOVUPDrr,        X86::MOVUPDrm,            0 },
565     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
566     { X86::MOVZPQILo2PQIrr, X86::MOVQI2PQIrm,         TB_NO_REVERSE },
567     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
568     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
569     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
570     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
571     { X86::PABSBrr,         X86::PABSBrm,             TB_ALIGN_16 },
572     { X86::PABSDrr,         X86::PABSDrm,             TB_ALIGN_16 },
573     { X86::PABSWrr,         X86::PABSWrm,             TB_ALIGN_16 },
574     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
575     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
576     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
577     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
578     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
579     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_NO_REVERSE },
580     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_NO_REVERSE },
581     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_NO_REVERSE },
582     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_NO_REVERSE },
583     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_NO_REVERSE },
584     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_NO_REVERSE },
585     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_NO_REVERSE },
586     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_NO_REVERSE },
587     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_NO_REVERSE },
588     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_NO_REVERSE },
589     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_NO_REVERSE },
590     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_NO_REVERSE },
591     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
592     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
593     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
594     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
595     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
596     { X86::RCPSSr,          X86::RCPSSm,              0 },
597     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          TB_NO_REVERSE },
598     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
599     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
600     { X86::ROUNDSDr,        X86::ROUNDSDm,            0 },
601     { X86::ROUNDSSr,        X86::ROUNDSSm,            0 },
602     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
603     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
604     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        TB_NO_REVERSE },
605     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
606     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
607     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
608     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         TB_NO_REVERSE },
609     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
610     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         TB_NO_REVERSE },
611     { X86::TEST16rr,        X86::TEST16rm,            0 },
612     { X86::TEST32rr,        X86::TEST32rm,            0 },
613     { X86::TEST64rr,        X86::TEST64rm,            0 },
614     { X86::TEST8rr,         X86::TEST8rm,             0 },
615     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
616     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
617     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
618 
619     // MMX version of foldable instructions
620     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
621     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
622     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
623     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
624     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
625     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
626     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
627     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
628     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
629     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
630 
631     // 3DNow! version of foldable instructions
632     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
633     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
634     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
635     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
636     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
637     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
638     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
639 
640     // AVX 128-bit versions of foldable instructions
641     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       TB_NO_REVERSE },
642     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       TB_NO_REVERSE },
643     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      TB_NO_REVERSE },
644     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      TB_NO_REVERSE },
645     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
646     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,TB_NO_REVERSE },
647     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
648     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    TB_NO_REVERSE },
649     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
650     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,TB_NO_REVERSE },
651     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
652     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    TB_NO_REVERSE },
653     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       TB_NO_REVERSE },
654     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         TB_NO_REVERSE },
655     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       TB_NO_REVERSE },
656     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         TB_NO_REVERSE },
657     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         TB_NO_REVERSE },
658     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
659     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQrm,         0 },
660     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSrm,         0 },
661     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
662     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         TB_NO_REVERSE },
663     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQrm,        0 },
664     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
665     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
666     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
667     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
668     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
669     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          TB_NO_REVERSE },
670     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
671     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
672     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
673     { X86::VMOVDQUrr,       X86::VMOVDQUrm,           0 },
674     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
675     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
676     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
677     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
678     { X86::VMOVZPQILo2PQIrr,X86::VMOVQI2PQIrm,        TB_NO_REVERSE },
679     { X86::VPABSBrr,        X86::VPABSBrm,            0 },
680     { X86::VPABSDrr,        X86::VPABSDrm,            0 },
681     { X86::VPABSWrr,        X86::VPABSWrm,            0 },
682     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
683     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
684     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
685     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
686     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
687     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
688     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
689     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         TB_NO_REVERSE },
690     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         TB_NO_REVERSE },
691     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         TB_NO_REVERSE },
692     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         TB_NO_REVERSE },
693     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         TB_NO_REVERSE },
694     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         TB_NO_REVERSE },
695     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         TB_NO_REVERSE },
696     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         TB_NO_REVERSE },
697     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         TB_NO_REVERSE },
698     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         TB_NO_REVERSE },
699     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         TB_NO_REVERSE },
700     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         TB_NO_REVERSE },
701     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
702     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
703     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
704     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
705     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
706     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
707     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
708     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
709     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
710     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
711     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
712     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
713     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
714     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
715 
716     // AVX 256-bit foldable instructions
717     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        TB_NO_REVERSE },
718     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
719     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
720     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
721     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
722     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        TB_NO_REVERSE },
723     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
724     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
725     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
726     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
727     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
728     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
729     { X86::VMOVDQUYrr,      X86::VMOVDQUYrm,          0 },
730     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
731     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
732     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
733     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
734     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
735     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
736     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
737     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
738     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
739     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
740     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
741     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
742     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
743     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
744     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
745 
746     // AVX2 foldable instructions
747 
748     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
749     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
750     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
751     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
752     // so they don't need an equivalent limitation.
753     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
754     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
755     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
756     { X86::VPABSBYrr,       X86::VPABSBYrm,           0 },
757     { X86::VPABSDYrr,       X86::VPABSDYrm,           0 },
758     { X86::VPABSWYrr,       X86::VPABSWYrm,           0 },
759     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      TB_NO_REVERSE },
760     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     TB_NO_REVERSE },
761     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      TB_NO_REVERSE },
762     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     TB_NO_REVERSE },
763     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      TB_NO_REVERSE },
764     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     TB_NO_REVERSE },
765     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      TB_NO_REVERSE },
766     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     TB_NO_REVERSE },
767     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
768     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
769     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        TB_NO_REVERSE },
770     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        TB_NO_REVERSE },
771     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
772     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
773     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
774     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        TB_NO_REVERSE },
775     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        TB_NO_REVERSE },
776     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        TB_NO_REVERSE },
777     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
778     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
779     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
780     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        TB_NO_REVERSE },
781     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
782     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
783     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
784 
785     // XOP foldable instructions
786     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
787     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
788     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
789     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
790     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
791     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
792     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
793     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
794     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
795     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
796     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
797     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
798     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
799     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
800     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
801     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
802     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
803     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
804     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
805     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
806     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
807     { X86::VPROTBri,           X86::VPROTBmi,         0 },
808     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
809     { X86::VPROTDri,           X86::VPROTDmi,         0 },
810     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
811     { X86::VPROTQri,           X86::VPROTQmi,         0 },
812     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
813     { X86::VPROTWri,           X86::VPROTWmi,         0 },
814     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
815     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
816     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
817     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
818     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
819     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
820     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
821     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
822     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
823 
824     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
825     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
826     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
827     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
828     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
829     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
830     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
831     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
832     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
833     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
834     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
835     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
836     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
837     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
838     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
839     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
840     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
841     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
842     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
843     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
844     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
845     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
846     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
847     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
848     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
849     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
850     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
851     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
852     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
853     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
854     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
855     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
856     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
857     { X86::RORX32ri,        X86::RORX32mi,            0 },
858     { X86::RORX64ri,        X86::RORX64mi,            0 },
859     { X86::SARX32rr,        X86::SARX32rm,            0 },
860     { X86::SARX64rr,        X86::SARX64rm,            0 },
861     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
862     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
863     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
864     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
865     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
866     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
867     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
868     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
869     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
870     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
871     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
872 
873     // AVX-512 foldable instructions
874     { X86::VBROADCASTSSZr,   X86::VBROADCASTSSZm,     TB_NO_REVERSE },
875     { X86::VBROADCASTSDZr,   X86::VBROADCASTSDZm,     TB_NO_REVERSE },
876     { X86::VMOV64toPQIZrr,   X86::VMOVQI2PQIZrm,      0 },
877     { X86::VMOV64toSDZrr,    X86::VMOV64toSDZrm,      0 },
878     { X86::VMOVDI2PDIZrr,    X86::VMOVDI2PDIZrm,      0 },
879     { X86::VMOVDI2SSZrr,     X86::VMOVDI2SSZrm,       0 },
880     { X86::VMOVAPDZrr,       X86::VMOVAPDZrm,         TB_ALIGN_64 },
881     { X86::VMOVAPSZrr,       X86::VMOVAPSZrm,         TB_ALIGN_64 },
882     { X86::VMOVDQA32Zrr,     X86::VMOVDQA32Zrm,       TB_ALIGN_64 },
883     { X86::VMOVDQA64Zrr,     X86::VMOVDQA64Zrm,       TB_ALIGN_64 },
884     { X86::VMOVDQU8Zrr,      X86::VMOVDQU8Zrm,        0 },
885     { X86::VMOVDQU16Zrr,     X86::VMOVDQU16Zrm,       0 },
886     { X86::VMOVDQU32Zrr,     X86::VMOVDQU32Zrm,       0 },
887     { X86::VMOVDQU64Zrr,     X86::VMOVDQU64Zrm,       0 },
888     { X86::VMOVUPDZrr,       X86::VMOVUPDZrm,         0 },
889     { X86::VMOVUPSZrr,       X86::VMOVUPSZrm,         0 },
890     { X86::VMOVZPQILo2PQIZrr,X86::VMOVQI2PQIZrm,      TB_NO_REVERSE },
891     { X86::VPABSBZrr,        X86::VPABSBZrm,          0 },
892     { X86::VPABSDZrr,        X86::VPABSDZrm,          0 },
893     { X86::VPABSQZrr,        X86::VPABSQZrm,          0 },
894     { X86::VPABSWZrr,        X86::VPABSWZrm,          0 },
895     { X86::VPERMILPDZri,     X86::VPERMILPDZmi,       0 },
896     { X86::VPERMILPSZri,     X86::VPERMILPSZmi,       0 },
897     { X86::VPERMPDZri,       X86::VPERMPDZmi,         0 },
898     { X86::VPERMQZri,        X86::VPERMQZmi,          0 },
899     { X86::VPMOVSXBDZrr,     X86::VPMOVSXBDZrm,       0 },
900     { X86::VPMOVSXBQZrr,     X86::VPMOVSXBQZrm,       TB_NO_REVERSE },
901     { X86::VPMOVSXBWZrr,     X86::VPMOVSXBWZrm,       0 },
902     { X86::VPMOVSXDQZrr,     X86::VPMOVSXDQZrm,       0 },
903     { X86::VPMOVSXWDZrr,     X86::VPMOVSXWDZrm,       0 },
904     { X86::VPMOVSXWQZrr,     X86::VPMOVSXWQZrm,       0 },
905     { X86::VPMOVZXBDZrr,     X86::VPMOVZXBDZrm,       0 },
906     { X86::VPMOVZXBQZrr,     X86::VPMOVZXBQZrm,       TB_NO_REVERSE },
907     { X86::VPMOVZXBWZrr,     X86::VPMOVZXBWZrm,       0 },
908     { X86::VPMOVZXDQZrr,     X86::VPMOVZXDQZrm,       0 },
909     { X86::VPMOVZXWDZrr,     X86::VPMOVZXWDZrm,       0 },
910     { X86::VPMOVZXWQZrr,     X86::VPMOVZXWQZrm,       0 },
911     { X86::VPSHUFDZri,       X86::VPSHUFDZmi,         0 },
912     { X86::VPSHUFHWZri,      X86::VPSHUFHWZmi,        0 },
913     { X86::VPSHUFLWZri,      X86::VPSHUFLWZmi,        0 },
914     { X86::VPSLLDQZ512rr,    X86::VPSLLDQZ512rm,      0 },
915     { X86::VPSLLDZri,        X86::VPSLLDZmi,          0 },
916     { X86::VPSLLQZri,        X86::VPSLLQZmi,          0 },
917     { X86::VPSLLWZri,        X86::VPSLLWZmi,          0 },
918     { X86::VPSRADZri,        X86::VPSRADZmi,          0 },
919     { X86::VPSRAQZri,        X86::VPSRAQZmi,          0 },
920     { X86::VPSRAWZri,        X86::VPSRAWZmi,          0 },
921     { X86::VPSRLDQZ512rr,    X86::VPSRLDQZ512rm,      0 },
922     { X86::VPSRLDZri,        X86::VPSRLDZmi,          0 },
923     { X86::VPSRLQZri,        X86::VPSRLQZmi,          0 },
924     { X86::VPSRLWZri,        X86::VPSRLWZmi,          0 },
925 
926     // AVX-512 foldable instructions (256-bit versions)
927     { X86::VBROADCASTSSZ256r,    X86::VBROADCASTSSZ256m,    TB_NO_REVERSE },
928     { X86::VBROADCASTSDZ256r,    X86::VBROADCASTSDZ256m,    TB_NO_REVERSE },
929     { X86::VMOVAPDZ256rr,        X86::VMOVAPDZ256rm,        TB_ALIGN_32 },
930     { X86::VMOVAPSZ256rr,        X86::VMOVAPSZ256rm,        TB_ALIGN_32 },
931     { X86::VMOVDQA32Z256rr,      X86::VMOVDQA32Z256rm,      TB_ALIGN_32 },
932     { X86::VMOVDQA64Z256rr,      X86::VMOVDQA64Z256rm,      TB_ALIGN_32 },
933     { X86::VMOVDQU8Z256rr,       X86::VMOVDQU8Z256rm,       0 },
934     { X86::VMOVDQU16Z256rr,      X86::VMOVDQU16Z256rm,      0 },
935     { X86::VMOVDQU32Z256rr,      X86::VMOVDQU32Z256rm,      0 },
936     { X86::VMOVDQU64Z256rr,      X86::VMOVDQU64Z256rm,      0 },
937     { X86::VMOVUPDZ256rr,        X86::VMOVUPDZ256rm,        0 },
938     { X86::VMOVUPSZ256rr,        X86::VMOVUPSZ256rm,        0 },
939     { X86::VPABSBZ256rr,         X86::VPABSBZ256rm,         0 },
940     { X86::VPABSDZ256rr,         X86::VPABSDZ256rm,         0 },
941     { X86::VPABSQZ256rr,         X86::VPABSQZ256rm,         0 },
942     { X86::VPABSWZ256rr,         X86::VPABSWZ256rm,         0 },
943     { X86::VPERMILPDZ256ri,      X86::VPERMILPDZ256mi,      0 },
944     { X86::VPERMILPSZ256ri,      X86::VPERMILPSZ256mi,      0 },
945     { X86::VPERMPDZ256ri,        X86::VPERMPDZ256mi,        0 },
946     { X86::VPERMQZ256ri,         X86::VPERMQZ256mi,         0 },
947     { X86::VPMOVSXBDZ256rr,      X86::VPMOVSXBDZ256rm,      TB_NO_REVERSE },
948     { X86::VPMOVSXBQZ256rr,      X86::VPMOVSXBQZ256rm,      TB_NO_REVERSE },
949     { X86::VPMOVSXBWZ256rr,      X86::VPMOVSXBWZ256rm,      0 },
950     { X86::VPMOVSXDQZ256rr,      X86::VPMOVSXDQZ256rm,      0 },
951     { X86::VPMOVSXWDZ256rr,      X86::VPMOVSXWDZ256rm,      0 },
952     { X86::VPMOVSXWQZ256rr,      X86::VPMOVSXWQZ256rm,      TB_NO_REVERSE },
953     { X86::VPMOVZXBDZ256rr,      X86::VPMOVZXBDZ256rm,      TB_NO_REVERSE },
954     { X86::VPMOVZXBQZ256rr,      X86::VPMOVZXBQZ256rm,      TB_NO_REVERSE },
955     { X86::VPMOVZXBWZ256rr,      X86::VPMOVZXBWZ256rm,      0 },
956     { X86::VPMOVZXDQZ256rr,      X86::VPMOVZXDQZ256rm,      0 },
957     { X86::VPMOVZXWDZ256rr,      X86::VPMOVZXWDZ256rm,      0 },
958     { X86::VPMOVZXWQZ256rr,      X86::VPMOVZXWQZ256rm,      TB_NO_REVERSE },
959     { X86::VPSHUFDZ256ri,        X86::VPSHUFDZ256mi,        0 },
960     { X86::VPSHUFHWZ256ri,       X86::VPSHUFHWZ256mi,       0 },
961     { X86::VPSHUFLWZ256ri,       X86::VPSHUFLWZ256mi,       0 },
962     { X86::VPSLLDQZ256rr,        X86::VPSLLDQZ256rm,        0 },
963     { X86::VPSLLDZ256ri,         X86::VPSLLDZ256mi,         0 },
964     { X86::VPSLLQZ256ri,         X86::VPSLLQZ256mi,         0 },
965     { X86::VPSLLWZ256ri,         X86::VPSLLWZ256mi,         0 },
966     { X86::VPSRADZ256ri,         X86::VPSRADZ256mi,         0 },
967     { X86::VPSRAQZ256ri,         X86::VPSRAQZ256mi,         0 },
968     { X86::VPSRAWZ256ri,         X86::VPSRAWZ256mi,         0 },
969     { X86::VPSRLDQZ256rr,        X86::VPSRLDQZ256rm,        0 },
970     { X86::VPSRLDZ256ri,         X86::VPSRLDZ256mi,         0 },
971     { X86::VPSRLQZ256ri,         X86::VPSRLQZ256mi,         0 },
972     { X86::VPSRLWZ256ri,         X86::VPSRLWZ256mi,         0 },
973 
974     // AVX-512 foldable instructions (128-bit versions)
975     { X86::VBROADCASTSSZ128r,    X86::VBROADCASTSSZ128m,    TB_NO_REVERSE },
976     { X86::VMOVAPDZ128rr,        X86::VMOVAPDZ128rm,        TB_ALIGN_16 },
977     { X86::VMOVAPSZ128rr,        X86::VMOVAPSZ128rm,        TB_ALIGN_16 },
978     { X86::VMOVDQA32Z128rr,      X86::VMOVDQA32Z128rm,      TB_ALIGN_16 },
979     { X86::VMOVDQA64Z128rr,      X86::VMOVDQA64Z128rm,      TB_ALIGN_16 },
980     { X86::VMOVDQU8Z128rr,       X86::VMOVDQU8Z128rm,       0 },
981     { X86::VMOVDQU16Z128rr,      X86::VMOVDQU16Z128rm,      0 },
982     { X86::VMOVDQU32Z128rr,      X86::VMOVDQU32Z128rm,      0 },
983     { X86::VMOVDQU64Z128rr,      X86::VMOVDQU64Z128rm,      0 },
984     { X86::VMOVUPDZ128rr,        X86::VMOVUPDZ128rm,        0 },
985     { X86::VMOVUPSZ128rr,        X86::VMOVUPSZ128rm,        0 },
986     { X86::VPABSBZ128rr,         X86::VPABSBZ128rm,         0 },
987     { X86::VPABSDZ128rr,         X86::VPABSDZ128rm,         0 },
988     { X86::VPABSQZ128rr,         X86::VPABSQZ128rm,         0 },
989     { X86::VPABSWZ128rr,         X86::VPABSWZ128rm,         0 },
990     { X86::VPERMILPDZ128ri,      X86::VPERMILPDZ128mi,      0 },
991     { X86::VPERMILPSZ128ri,      X86::VPERMILPSZ128mi,      0 },
992     { X86::VPMOVSXBDZ128rr,      X86::VPMOVSXBDZ128rm,      TB_NO_REVERSE },
993     { X86::VPMOVSXBQZ128rr,      X86::VPMOVSXBQZ128rm,      TB_NO_REVERSE },
994     { X86::VPMOVSXBWZ128rr,      X86::VPMOVSXBWZ128rm,      TB_NO_REVERSE },
995     { X86::VPMOVSXDQZ128rr,      X86::VPMOVSXDQZ128rm,      TB_NO_REVERSE },
996     { X86::VPMOVSXWDZ128rr,      X86::VPMOVSXWDZ128rm,      TB_NO_REVERSE },
997     { X86::VPMOVSXWQZ128rr,      X86::VPMOVSXWQZ128rm,      TB_NO_REVERSE },
998     { X86::VPMOVZXBDZ128rr,      X86::VPMOVZXBDZ128rm,      TB_NO_REVERSE },
999     { X86::VPMOVZXBQZ128rr,      X86::VPMOVZXBQZ128rm,      TB_NO_REVERSE },
1000     { X86::VPMOVZXBWZ128rr,      X86::VPMOVZXBWZ128rm,      TB_NO_REVERSE },
1001     { X86::VPMOVZXDQZ128rr,      X86::VPMOVZXDQZ128rm,      TB_NO_REVERSE },
1002     { X86::VPMOVZXWDZ128rr,      X86::VPMOVZXWDZ128rm,      TB_NO_REVERSE },
1003     { X86::VPMOVZXWQZ128rr,      X86::VPMOVZXWQZ128rm,      TB_NO_REVERSE },
1004     { X86::VPSHUFDZ128ri,        X86::VPSHUFDZ128mi,        0 },
1005     { X86::VPSHUFHWZ128ri,       X86::VPSHUFHWZ128mi,       0 },
1006     { X86::VPSHUFLWZ128ri,       X86::VPSHUFLWZ128mi,       0 },
1007     { X86::VPSLLDQZ128rr,        X86::VPSLLDQZ128rm,        0 },
1008     { X86::VPSLLDZ128ri,         X86::VPSLLDZ128mi,         0 },
1009     { X86::VPSLLQZ128ri,         X86::VPSLLQZ128mi,         0 },
1010     { X86::VPSLLWZ128ri,         X86::VPSLLWZ128mi,         0 },
1011     { X86::VPSRADZ128ri,         X86::VPSRADZ128mi,         0 },
1012     { X86::VPSRAQZ128ri,         X86::VPSRAQZ128mi,         0 },
1013     { X86::VPSRAWZ128ri,         X86::VPSRAWZ128mi,         0 },
1014     { X86::VPSRLDQZ128rr,        X86::VPSRLDQZ128rm,        0 },
1015     { X86::VPSRLDZ128ri,         X86::VPSRLDZ128mi,         0 },
1016     { X86::VPSRLQZ128ri,         X86::VPSRLQZ128mi,         0 },
1017     { X86::VPSRLWZ128ri,         X86::VPSRLWZ128mi,         0 },
1018 
1019     // F16C foldable instructions
1020     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
1021     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
1022 
1023     // AES foldable instructions
1024     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
1025     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
1026     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
1027     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
1028   };
1029 
1030   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
1031     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
1032                   Entry.RegOp, Entry.MemOp,
1033                   // Index 1, folded load
1034                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
1035   }
1036 
1037   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
1038     { X86::ADC32rr,         X86::ADC32rm,       0 },
1039     { X86::ADC64rr,         X86::ADC64rm,       0 },
1040     { X86::ADD16rr,         X86::ADD16rm,       0 },
1041     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
1042     { X86::ADD32rr,         X86::ADD32rm,       0 },
1043     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
1044     { X86::ADD64rr,         X86::ADD64rm,       0 },
1045     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
1046     { X86::ADD8rr,          X86::ADD8rm,        0 },
1047     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
1048     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
1049     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
1050     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   TB_NO_REVERSE },
1051     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
1052     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   TB_NO_REVERSE },
1053     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
1054     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
1055     { X86::AND16rr,         X86::AND16rm,       0 },
1056     { X86::AND32rr,         X86::AND32rm,       0 },
1057     { X86::AND64rr,         X86::AND64rm,       0 },
1058     { X86::AND8rr,          X86::AND8rm,        0 },
1059     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
1060     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
1061     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
1062     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
1063     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
1064     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
1065     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
1066     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
1067     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
1068     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
1069     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
1070     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
1071     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
1072     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
1073     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
1074     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
1075     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
1076     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
1077     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
1078     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
1079     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
1080     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
1081     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
1082     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
1083     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
1084     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
1085     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
1086     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
1087     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
1088     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
1089     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
1090     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
1091     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
1092     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
1093     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
1094     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
1095     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
1096     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
1097     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
1098     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
1099     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
1100     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
1101     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
1102     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
1103     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
1104     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
1105     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
1106     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
1107     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
1108     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
1109     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
1110     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
1111     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
1112     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
1113     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
1114     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
1115     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
1116     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
1117     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
1118     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
1119     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
1120     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
1121     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
1122     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
1123     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
1124     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   TB_NO_REVERSE },
1125     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
1126     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   TB_NO_REVERSE },
1127     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
1128     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
1129     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
1130     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
1131     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
1132     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
1133     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
1134     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
1135     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
1136     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   TB_NO_REVERSE },
1137     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   TB_NO_REVERSE },
1138     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      TB_NO_REVERSE },
1139     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
1140     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
1141     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
1142     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
1143     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      TB_NO_REVERSE },
1144     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
1145     { X86::MAXCPDrr,        X86::MAXCPDrm,      TB_ALIGN_16 },
1146     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
1147     { X86::MAXCPSrr,        X86::MAXCPSrm,      TB_ALIGN_16 },
1148     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
1149     { X86::MAXCSDrr,        X86::MAXCSDrm,      0 },
1150     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   TB_NO_REVERSE },
1151     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
1152     { X86::MAXCSSrr,        X86::MAXCSSrm,      0 },
1153     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   TB_NO_REVERSE },
1154     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
1155     { X86::MINCPDrr,        X86::MINCPDrm,      TB_ALIGN_16 },
1156     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
1157     { X86::MINCPSrr,        X86::MINCPSrm,      TB_ALIGN_16 },
1158     { X86::MINSDrr,         X86::MINSDrm,       0 },
1159     { X86::MINCSDrr,        X86::MINCSDrm,      0 },
1160     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   TB_NO_REVERSE },
1161     { X86::MINSSrr,         X86::MINSSrm,       0 },
1162     { X86::MINCSSrr,        X86::MINCSSrm,      0 },
1163     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   TB_NO_REVERSE },
1164     { X86::MOVLHPSrr,       X86::MOVHPSrm,      TB_NO_REVERSE },
1165     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
1166     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
1167     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
1168     { X86::MULSDrr,         X86::MULSDrm,       0 },
1169     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   TB_NO_REVERSE },
1170     { X86::MULSSrr,         X86::MULSSrm,       0 },
1171     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   TB_NO_REVERSE },
1172     { X86::OR16rr,          X86::OR16rm,        0 },
1173     { X86::OR32rr,          X86::OR32rm,        0 },
1174     { X86::OR64rr,          X86::OR64rm,        0 },
1175     { X86::OR8rr,           X86::OR8rm,         0 },
1176     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1177     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1178     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1179     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1180     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1181     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1182     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1183     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1184     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1185     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1186     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1187     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1188     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1189     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1190     { X86::PALIGNRrri,      X86::PALIGNRrmi,    TB_ALIGN_16 },
1191     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1192     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1193     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1194     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1195     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1196     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1197     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1198     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1199     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1200     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1201     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1202     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1203     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1204     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1205     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1206     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1207     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1208     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1209     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1210     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1211     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1212     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1213     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1214     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1215     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1216     { X86::PMADDUBSWrr,     X86::PMADDUBSWrm,   TB_ALIGN_16 },
1217     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1218     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1219     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1220     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1221     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1222     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1223     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1224     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1225     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1226     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1227     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1228     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1229     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1230     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1231     { X86::PMULHRSWrr,      X86::PMULHRSWrm,    TB_ALIGN_16 },
1232     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1233     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1234     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1235     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1236     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1237     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1238     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1239     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1240     { X86::PSIGNBrr128,     X86::PSIGNBrm128,   TB_ALIGN_16 },
1241     { X86::PSIGNWrr128,     X86::PSIGNWrm128,   TB_ALIGN_16 },
1242     { X86::PSIGNDrr128,     X86::PSIGNDrm128,   TB_ALIGN_16 },
1243     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1244     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1245     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1246     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1247     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1248     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1249     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1250     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1251     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1252     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1253     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1254     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1255     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1256     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1257     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1258     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1259     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1260     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1261     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1262     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1263     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1264     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1265     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1266     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1267     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1268     { X86::ROUNDSDr_Int,    X86::ROUNDSDm_Int,  TB_NO_REVERSE },
1269     { X86::ROUNDSSr_Int,    X86::ROUNDSSm_Int,  TB_NO_REVERSE },
1270     { X86::SBB32rr,         X86::SBB32rm,       0 },
1271     { X86::SBB64rr,         X86::SBB64rm,       0 },
1272     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1273     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1274     { X86::SUB16rr,         X86::SUB16rm,       0 },
1275     { X86::SUB32rr,         X86::SUB32rm,       0 },
1276     { X86::SUB64rr,         X86::SUB64rm,       0 },
1277     { X86::SUB8rr,          X86::SUB8rm,        0 },
1278     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1279     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1280     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1281     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   TB_NO_REVERSE },
1282     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1283     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   TB_NO_REVERSE },
1284     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1285     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1286     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1287     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1288     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1289     { X86::XOR16rr,         X86::XOR16rm,       0 },
1290     { X86::XOR32rr,         X86::XOR32rm,       0 },
1291     { X86::XOR64rr,         X86::XOR64rm,       0 },
1292     { X86::XOR8rr,          X86::XOR8rm,        0 },
1293     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1294     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1295 
1296     // MMX version of foldable instructions
1297     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
1298     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
1299     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
1300     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
1301     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
1302     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
1303     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
1304     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
1305     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
1306     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
1307     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
1308     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
1309     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
1310     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
1311     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
1312     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
1313     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
1314     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
1315     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
1316     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
1317     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
1318     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
1319     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
1320     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
1321     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
1322     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
1323     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
1324     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
1325     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
1326     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
1327     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1328     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
1329     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
1330     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
1331     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
1332     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
1333     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
1334     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
1335     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
1336     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
1337     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
1338     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
1339     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
1340     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
1341     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
1342     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
1343     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
1344     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
1345     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
1346     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
1347     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
1348     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
1349     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
1350     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
1351     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
1352     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
1353     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
1354     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
1355     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
1356     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
1357     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
1358     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
1359     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
1360     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
1361     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
1362     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
1363     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
1364     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
1365     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
1366     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
1367 
1368     // 3DNow! version of foldable instructions
1369     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
1370     { X86::PFACCrr,           X86::PFACCrm,           0 },
1371     { X86::PFADDrr,           X86::PFADDrm,           0 },
1372     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
1373     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
1374     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
1375     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
1376     { X86::PFMINrr,           X86::PFMINrm,           0 },
1377     { X86::PFMULrr,           X86::PFMULrm,           0 },
1378     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
1379     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
1380     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
1381     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
1382     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
1383     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
1384     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
1385     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
1386 
1387     // AVX 128-bit versions of foldable instructions
1388     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1389     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    TB_NO_REVERSE },
1390     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1391     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1392     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1393     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1394     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1395     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1396     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1397     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1398     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1399     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    TB_NO_REVERSE },
1400     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1401     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1402     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1403     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       TB_NO_REVERSE },
1404     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1405     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       TB_NO_REVERSE },
1406     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1407     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1408     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1409     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1410     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1411     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1412     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1413     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1414     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1415     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1416     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1417     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1418     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1419     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1420     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1421     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1422     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1423     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       TB_NO_REVERSE },
1424     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1425     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       TB_NO_REVERSE },
1426     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1427     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1428     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1429     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1430     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1431     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1432     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       TB_NO_REVERSE },
1433     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       TB_NO_REVERSE },
1434     { X86::VMAXCPDrr,         X86::VMAXCPDrm,          0 },
1435     { X86::VMAXCPSrr,         X86::VMAXCPSrm,          0 },
1436     { X86::VMAXCSDrr,         X86::VMAXCSDrm,          0 },
1437     { X86::VMAXCSSrr,         X86::VMAXCSSrm,          0 },
1438     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1439     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1440     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1441     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       TB_NO_REVERSE },
1442     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1443     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       TB_NO_REVERSE },
1444     { X86::VMINCPDrr,         X86::VMINCPDrm,          0 },
1445     { X86::VMINCPSrr,         X86::VMINCPSrm,          0 },
1446     { X86::VMINCSDrr,         X86::VMINCSDrm,          0 },
1447     { X86::VMINCSSrr,         X86::VMINCSSrm,          0 },
1448     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1449     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1450     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1451     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       TB_NO_REVERSE },
1452     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1453     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       TB_NO_REVERSE },
1454     { X86::VMOVLHPSrr,        X86::VMOVHPSrm,          TB_NO_REVERSE },
1455     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1456     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1457     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1458     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1459     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       TB_NO_REVERSE },
1460     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1461     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       TB_NO_REVERSE },
1462     { X86::VORPDrr,           X86::VORPDrm,            0 },
1463     { X86::VORPSrr,           X86::VORPSrm,            0 },
1464     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1465     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1466     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1467     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1468     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1469     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1470     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1471     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1472     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1473     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1474     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1475     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1476     { X86::VPALIGNRrri,       X86::VPALIGNRrmi,        0 },
1477     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1478     { X86::VPANDrr,           X86::VPANDrm,            0 },
1479     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1480     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1481     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1482     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1483     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1484     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1485     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1486     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1487     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1488     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1489     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1490     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1491     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1492     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1493     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1494     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1495     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1496     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1497     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1498     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1499     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1500     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1501     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1502     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1503     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1504     { X86::VPMADDUBSWrr,      X86::VPMADDUBSWrm,       0 },
1505     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1506     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1507     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1508     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1509     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1510     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1511     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1512     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1513     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1514     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1515     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1516     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1517     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1518     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1519     { X86::VPMULHRSWrr,       X86::VPMULHRSWrm,        0 },
1520     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1521     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1522     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1523     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1524     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1525     { X86::VPORrr,            X86::VPORrm,             0 },
1526     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1527     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1528     { X86::VPSIGNBrr128,      X86::VPSIGNBrm128,       0 },
1529     { X86::VPSIGNWrr128,      X86::VPSIGNWrm128,       0 },
1530     { X86::VPSIGNDrr128,      X86::VPSIGNDrm128,       0 },
1531     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1532     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1533     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1534     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1535     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1536     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1537     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1538     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1539     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1540     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1541     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1542     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1543     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1544     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1545     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1546     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1547     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1548     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1549     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1550     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1551     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1552     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1553     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1554     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1555     { X86::VPXORrr,           X86::VPXORrm,            0 },
1556     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1557     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        TB_NO_REVERSE },
1558     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1559     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      TB_NO_REVERSE },
1560     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
1561     { X86::VROUNDSDr_Int,     X86::VROUNDSDm_Int,      TB_NO_REVERSE },
1562     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
1563     { X86::VROUNDSSr_Int,     X86::VROUNDSSm_Int,      TB_NO_REVERSE },
1564     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1565     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1566     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1567     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       TB_NO_REVERSE },
1568     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1569     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       TB_NO_REVERSE },
1570     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1571     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1572     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1573     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       TB_NO_REVERSE },
1574     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1575     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       TB_NO_REVERSE },
1576     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1577     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1578     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1579     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1580     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1581     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1582 
1583     // AVX 256-bit foldable instructions
1584     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1585     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1586     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1587     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1588     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1589     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1590     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1591     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1592     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1593     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1594     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1595     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1596     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1597     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1598     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1599     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1600     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1601     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1602     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1603     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1604     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1605     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1606     { X86::VMAXCPDYrr,        X86::VMAXCPDYrm,         0 },
1607     { X86::VMAXCPSYrr,        X86::VMAXCPSYrm,         0 },
1608     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1609     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1610     { X86::VMINCPDYrr,        X86::VMINCPDYrm,         0 },
1611     { X86::VMINCPSYrr,        X86::VMINCPSYrm,         0 },
1612     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1613     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1614     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1615     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1616     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1617     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1618     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1619     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1620     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1621     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1622     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1623     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1624     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1625     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1626     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1627     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1628     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1629     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1630     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1631 
1632     // AVX2 foldable instructions
1633     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1634     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1635     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1636     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1637     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1638     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1639     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1640     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1641     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1642     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1643     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1644     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1645     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1646     { X86::VPALIGNRYrri,      X86::VPALIGNRYrmi,       0 },
1647     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1648     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1649     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1650     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1651     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1652     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1653     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1654     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1655     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1656     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1657     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1658     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1659     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1660     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1661     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1662     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1663     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1664     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1665     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1666     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1667     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1668     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1669     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1670     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1671     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1672     { X86::VPMADDUBSWYrr,     X86::VPMADDUBSWYrm,      0 },
1673     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1674     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1675     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1676     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1677     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1678     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1679     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1680     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1681     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1682     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1683     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1684     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1685     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1686     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1687     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1688     { X86::VPMULHRSWYrr,      X86::VPMULHRSWYrm,       0 },
1689     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1690     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1691     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1692     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1693     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1694     { X86::VPORYrr,           X86::VPORYrm,            0 },
1695     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1696     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1697     { X86::VPSIGNBYrr256,     X86::VPSIGNBYrm256,      0 },
1698     { X86::VPSIGNWYrr256,     X86::VPSIGNWYrm256,      0 },
1699     { X86::VPSIGNDYrr256,     X86::VPSIGNDYrm256,      0 },
1700     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1701     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1702     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1703     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1704     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1705     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1706     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1707     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1708     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1709     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1710     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1711     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1712     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1713     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1714     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1715     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1716     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1717     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1718     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1719     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1720     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1721     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1722     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1723     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1724     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1725     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1726     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1727     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1728     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1729     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1730     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1731     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1732     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1733     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1734     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1735 
1736     // FMA4 foldable patterns
1737     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
1738     { X86::VFMADDSS4rr_Int,   X86::VFMADDSS4mr_Int,    TB_NO_REVERSE },
1739     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
1740     { X86::VFMADDSD4rr_Int,   X86::VFMADDSD4mr_Int,    TB_NO_REVERSE },
1741     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
1742     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
1743     { X86::VFMADDPS4Yrr,      X86::VFMADDPS4Ymr,       TB_ALIGN_NONE },
1744     { X86::VFMADDPD4Yrr,      X86::VFMADDPD4Ymr,       TB_ALIGN_NONE },
1745     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
1746     { X86::VFNMADDSS4rr_Int,  X86::VFNMADDSS4mr_Int,   TB_NO_REVERSE },
1747     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
1748     { X86::VFNMADDSD4rr_Int,  X86::VFNMADDSD4mr_Int,   TB_NO_REVERSE },
1749     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
1750     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
1751     { X86::VFNMADDPS4Yrr,     X86::VFNMADDPS4Ymr,      TB_ALIGN_NONE },
1752     { X86::VFNMADDPD4Yrr,     X86::VFNMADDPD4Ymr,      TB_ALIGN_NONE },
1753     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
1754     { X86::VFMSUBSS4rr_Int,   X86::VFMSUBSS4mr_Int,    TB_NO_REVERSE },
1755     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
1756     { X86::VFMSUBSD4rr_Int,   X86::VFMSUBSD4mr_Int,    TB_NO_REVERSE },
1757     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
1758     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
1759     { X86::VFMSUBPS4Yrr,      X86::VFMSUBPS4Ymr,       TB_ALIGN_NONE },
1760     { X86::VFMSUBPD4Yrr,      X86::VFMSUBPD4Ymr,       TB_ALIGN_NONE },
1761     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
1762     { X86::VFNMSUBSS4rr_Int,  X86::VFNMSUBSS4mr_Int,   TB_NO_REVERSE },
1763     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
1764     { X86::VFNMSUBSD4rr_Int,  X86::VFNMSUBSD4mr_Int,   TB_NO_REVERSE },
1765     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
1766     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
1767     { X86::VFNMSUBPS4Yrr,     X86::VFNMSUBPS4Ymr,      TB_ALIGN_NONE },
1768     { X86::VFNMSUBPD4Yrr,     X86::VFNMSUBPD4Ymr,      TB_ALIGN_NONE },
1769     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
1770     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
1771     { X86::VFMADDSUBPS4Yrr,   X86::VFMADDSUBPS4Ymr,    TB_ALIGN_NONE },
1772     { X86::VFMADDSUBPD4Yrr,   X86::VFMADDSUBPD4Ymr,    TB_ALIGN_NONE },
1773     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
1774     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
1775     { X86::VFMSUBADDPS4Yrr,   X86::VFMSUBADDPS4Ymr,    TB_ALIGN_NONE },
1776     { X86::VFMSUBADDPD4Yrr,   X86::VFMSUBADDPD4Ymr,    TB_ALIGN_NONE },
1777 
1778     // XOP foldable instructions
1779     { X86::VPCMOVrrr,         X86::VPCMOVrmr,           0 },
1780     { X86::VPCMOVrrrY,        X86::VPCMOVrmrY,          0 },
1781     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1782     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1783     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1784     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1785     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1786     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1787     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1788     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1789     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1790     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1791     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1792     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1793     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1794     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1795     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1796     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1797     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1798     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1799     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1800     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1801     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1802     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1803     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1804     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1805     { X86::VPPERMrrr,         X86::VPPERMrmr,           0 },
1806     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1807     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1808     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1809     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1810     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1811     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1812     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1813     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1814     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1815     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1816     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1817     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1818 
1819     // BMI/BMI2 foldable instructions
1820     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1821     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1822     { X86::MULX32rr,          X86::MULX32rm,            0 },
1823     { X86::MULX64rr,          X86::MULX64rm,            0 },
1824     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1825     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1826     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1827     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1828 
1829     // ADX foldable instructions
1830     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
1831     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
1832     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
1833     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
1834 
1835     // AVX-512 foldable instructions
1836     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1837     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1838     { X86::VADDSDZrr,         X86::VADDSDZrm,           0 },
1839     { X86::VADDSDZrr_Int,     X86::VADDSDZrm_Int,       TB_NO_REVERSE },
1840     { X86::VADDSSZrr,         X86::VADDSSZrm,           0 },
1841     { X86::VADDSSZrr_Int,     X86::VADDSSZrm_Int,       TB_NO_REVERSE },
1842     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
1843     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
1844     { X86::VANDNPDZrr,        X86::VANDNPDZrm,          0 },
1845     { X86::VANDNPSZrr,        X86::VANDNPSZrm,          0 },
1846     { X86::VANDPDZrr,         X86::VANDPDZrm,           0 },
1847     { X86::VANDPSZrr,         X86::VANDPSZrm,           0 },
1848     { X86::VCMPPDZrri,        X86::VCMPPDZrmi,          0 },
1849     { X86::VCMPPSZrri,        X86::VCMPPSZrmi,          0 },
1850     { X86::VCMPSDZrr,         X86::VCMPSDZrm,           0 },
1851     { X86::VCMPSDZrr_Int,     X86::VCMPSDZrm_Int,       TB_NO_REVERSE },
1852     { X86::VCMPSSZrr,         X86::VCMPSSZrm,           0 },
1853     { X86::VCMPSSZrr_Int,     X86::VCMPSSZrm_Int,       TB_NO_REVERSE },
1854     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1855     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1856     { X86::VDIVSDZrr,         X86::VDIVSDZrm,           0 },
1857     { X86::VDIVSDZrr_Int,     X86::VDIVSDZrm_Int,       TB_NO_REVERSE },
1858     { X86::VDIVSSZrr,         X86::VDIVSSZrm,           0 },
1859     { X86::VDIVSSZrr_Int,     X86::VDIVSSZrm_Int,       TB_NO_REVERSE },
1860     { X86::VINSERTF32x4Zrr,   X86::VINSERTF32x4Zrm,     0 },
1861     { X86::VINSERTF32x8Zrr,   X86::VINSERTF32x8Zrm,     0 },
1862     { X86::VINSERTF64x2Zrr,   X86::VINSERTF64x2Zrm,     0 },
1863     { X86::VINSERTF64x4Zrr,   X86::VINSERTF64x4Zrm,     0 },
1864     { X86::VINSERTI32x4Zrr,   X86::VINSERTI32x4Zrm,     0 },
1865     { X86::VINSERTI32x8Zrr,   X86::VINSERTI32x8Zrm,     0 },
1866     { X86::VINSERTI64x2Zrr,   X86::VINSERTI64x2Zrm,     0 },
1867     { X86::VINSERTI64x4Zrr,   X86::VINSERTI64x4Zrm,     0 },
1868     { X86::VMAXCPDZrr,        X86::VMAXCPDZrm,          0 },
1869     { X86::VMAXCPSZrr,        X86::VMAXCPSZrm,          0 },
1870     { X86::VMAXCSDZrr,        X86::VMAXCSDZrm,          0 },
1871     { X86::VMAXCSSZrr,        X86::VMAXCSSZrm,          0 },
1872     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1873     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1874     { X86::VMAXSDZrr,         X86::VMAXSDZrm,           0 },
1875     { X86::VMAXSDZrr_Int,     X86::VMAXSDZrm_Int,       TB_NO_REVERSE },
1876     { X86::VMAXSSZrr,         X86::VMAXSSZrm,           0 },
1877     { X86::VMAXSSZrr_Int,     X86::VMAXSSZrm_Int,       TB_NO_REVERSE },
1878     { X86::VMINCPDZrr,        X86::VMINCPDZrm,          0 },
1879     { X86::VMINCPSZrr,        X86::VMINCPSZrm,          0 },
1880     { X86::VMINCSDZrr,        X86::VMINCSDZrm,          0 },
1881     { X86::VMINCSSZrr,        X86::VMINCSSZrm,          0 },
1882     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1883     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1884     { X86::VMINSDZrr,         X86::VMINSDZrm,           0 },
1885     { X86::VMINSDZrr_Int,     X86::VMINSDZrm_Int,       TB_NO_REVERSE },
1886     { X86::VMINSSZrr,         X86::VMINSSZrm,           0 },
1887     { X86::VMINSSZrr_Int,     X86::VMINSSZrm_Int,       TB_NO_REVERSE },
1888     { X86::VMOVLHPSZrr,       X86::VMOVHPSZ128rm,       TB_NO_REVERSE },
1889     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1890     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1891     { X86::VMULSDZrr,         X86::VMULSDZrm,           0 },
1892     { X86::VMULSDZrr_Int,     X86::VMULSDZrm_Int,       TB_NO_REVERSE },
1893     { X86::VMULSSZrr,         X86::VMULSSZrm,           0 },
1894     { X86::VMULSSZrr_Int,     X86::VMULSSZrm_Int,       TB_NO_REVERSE },
1895     { X86::VORPDZrr,          X86::VORPDZrm,            0 },
1896     { X86::VORPSZrr,          X86::VORPSZrm,            0 },
1897     { X86::VPACKSSDWZrr,      X86::VPACKSSDWZrm,        0 },
1898     { X86::VPACKSSWBZrr,      X86::VPACKSSWBZrm,        0 },
1899     { X86::VPACKUSDWZrr,      X86::VPACKUSDWZrm,        0 },
1900     { X86::VPACKUSWBZrr,      X86::VPACKUSWBZrm,        0 },
1901     { X86::VPADDBZrr,         X86::VPADDBZrm,           0 },
1902     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1903     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1904     { X86::VPADDSBZrr,        X86::VPADDSBZrm,          0 },
1905     { X86::VPADDSWZrr,        X86::VPADDSWZrm,          0 },
1906     { X86::VPADDUSBZrr,       X86::VPADDUSBZrm,         0 },
1907     { X86::VPADDUSWZrr,       X86::VPADDUSWZrm,         0 },
1908     { X86::VPADDWZrr,         X86::VPADDWZrm,           0 },
1909     { X86::VPALIGNRZrri,      X86::VPALIGNRZrmi,        0 },
1910     { X86::VPANDDZrr,         X86::VPANDDZrm,           0 },
1911     { X86::VPANDNDZrr,        X86::VPANDNDZrm,          0 },
1912     { X86::VPANDNQZrr,        X86::VPANDNQZrm,          0 },
1913     { X86::VPANDQZrr,         X86::VPANDQZrm,           0 },
1914     { X86::VPAVGBZrr,         X86::VPAVGBZrm,           0 },
1915     { X86::VPAVGWZrr,         X86::VPAVGWZrm,           0 },
1916     { X86::VPCMPBZrri,        X86::VPCMPBZrmi,          0 },
1917     { X86::VPCMPDZrri,        X86::VPCMPDZrmi,          0 },
1918     { X86::VPCMPEQBZrr,       X86::VPCMPEQBZrm,         0 },
1919     { X86::VPCMPEQDZrr,       X86::VPCMPEQDZrm,         0 },
1920     { X86::VPCMPEQQZrr,       X86::VPCMPEQQZrm,         0 },
1921     { X86::VPCMPEQWZrr,       X86::VPCMPEQWZrm,         0 },
1922     { X86::VPCMPGTBZrr,       X86::VPCMPGTBZrm,         0 },
1923     { X86::VPCMPGTDZrr,       X86::VPCMPGTDZrm,         0 },
1924     { X86::VPCMPGTQZrr,       X86::VPCMPGTQZrm,         0 },
1925     { X86::VPCMPGTWZrr,       X86::VPCMPGTWZrm,         0 },
1926     { X86::VPCMPQZrri,        X86::VPCMPQZrmi,          0 },
1927     { X86::VPCMPUBZrri,       X86::VPCMPUBZrmi,         0 },
1928     { X86::VPCMPUDZrri,       X86::VPCMPUDZrmi,         0 },
1929     { X86::VPCMPUQZrri,       X86::VPCMPUQZrmi,         0 },
1930     { X86::VPCMPUWZrri,       X86::VPCMPUWZrmi,         0 },
1931     { X86::VPCMPWZrri,        X86::VPCMPWZrmi,          0 },
1932     { X86::VPERMBZrr,         X86::VPERMBZrm,           0 },
1933     { X86::VPERMDZrr,         X86::VPERMDZrm,           0 },
1934     { X86::VPERMILPDZrr,      X86::VPERMILPDZrm,        0 },
1935     { X86::VPERMILPSZrr,      X86::VPERMILPSZrm,        0 },
1936     { X86::VPERMPDZrr,        X86::VPERMPDZrm,          0 },
1937     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1938     { X86::VPERMQZrr,         X86::VPERMQZrm,           0 },
1939     { X86::VPERMWZrr,         X86::VPERMWZrm,           0 },
1940     { X86::VPINSRBZrr,        X86::VPINSRBZrm,          0 },
1941     { X86::VPINSRDZrr,        X86::VPINSRDZrm,          0 },
1942     { X86::VPINSRQZrr,        X86::VPINSRQZrm,          0 },
1943     { X86::VPINSRWZrr,        X86::VPINSRWZrm,          0 },
1944     { X86::VPMADDUBSWZrr,     X86::VPMADDUBSWZrm,       0 },
1945     { X86::VPMADDWDZrr,       X86::VPMADDWDZrm,         0 },
1946     { X86::VPMAXSBZrr,        X86::VPMAXSBZrm,          0 },
1947     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1948     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1949     { X86::VPMAXSWZrr,        X86::VPMAXSWZrm,          0 },
1950     { X86::VPMAXUBZrr,        X86::VPMAXUBZrm,          0 },
1951     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1952     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1953     { X86::VPMAXUWZrr,        X86::VPMAXUWZrm,          0 },
1954     { X86::VPMINSBZrr,        X86::VPMINSBZrm,          0 },
1955     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1956     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1957     { X86::VPMINSWZrr,        X86::VPMINSWZrm,          0 },
1958     { X86::VPMINUBZrr,        X86::VPMINUBZrm,          0 },
1959     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1960     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1961     { X86::VPMINUWZrr,        X86::VPMINUWZrm,          0 },
1962     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1963     { X86::VPMULLDZrr,        X86::VPMULLDZrm,          0 },
1964     { X86::VPMULLQZrr,        X86::VPMULLQZrm,          0 },
1965     { X86::VPMULLWZrr,        X86::VPMULLWZrm,          0 },
1966     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1967     { X86::VPORDZrr,          X86::VPORDZrm,            0 },
1968     { X86::VPORQZrr,          X86::VPORQZrm,            0 },
1969     { X86::VPSADBWZ512rr,     X86::VPSADBWZ512rm,       0 },
1970     { X86::VPSHUFBZrr,        X86::VPSHUFBZrm,          0 },
1971     { X86::VPSLLDZrr,         X86::VPSLLDZrm,           0 },
1972     { X86::VPSLLQZrr,         X86::VPSLLQZrm,           0 },
1973     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1974     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1975     { X86::VPSLLVWZrr,        X86::VPSLLVWZrm,          0 },
1976     { X86::VPSLLWZrr,         X86::VPSLLWZrm,           0 },
1977     { X86::VPSRADZrr,         X86::VPSRADZrm,           0 },
1978     { X86::VPSRAQZrr,         X86::VPSRAQZrm,           0 },
1979     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1980     { X86::VPSRAVQZrr,        X86::VPSRAVQZrm,          0 },
1981     { X86::VPSRAVWZrr,        X86::VPSRAVWZrm,          0 },
1982     { X86::VPSRAWZrr,         X86::VPSRAWZrm,           0 },
1983     { X86::VPSRLDZrr,         X86::VPSRLDZrm,           0 },
1984     { X86::VPSRLQZrr,         X86::VPSRLQZrm,           0 },
1985     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1986     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1987     { X86::VPSRLVWZrr,        X86::VPSRLVWZrm,          0 },
1988     { X86::VPSRLWZrr,         X86::VPSRLWZrm,           0 },
1989     { X86::VPSUBBZrr,         X86::VPSUBBZrm,           0 },
1990     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1991     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1992     { X86::VPSUBSBZrr,        X86::VPSUBSBZrm,          0 },
1993     { X86::VPSUBSWZrr,        X86::VPSUBSWZrm,          0 },
1994     { X86::VPSUBUSBZrr,       X86::VPSUBUSBZrm,         0 },
1995     { X86::VPSUBUSWZrr,       X86::VPSUBUSWZrm,         0 },
1996     { X86::VPSUBWZrr,         X86::VPSUBWZrm,           0 },
1997     { X86::VPUNPCKHBWZrr,     X86::VPUNPCKHBWZrm,       0 },
1998     { X86::VPUNPCKHDQZrr,     X86::VPUNPCKHDQZrm,       0 },
1999     { X86::VPUNPCKHQDQZrr,    X86::VPUNPCKHQDQZrm,      0 },
2000     { X86::VPUNPCKHWDZrr,     X86::VPUNPCKHWDZrm,       0 },
2001     { X86::VPUNPCKLBWZrr,     X86::VPUNPCKLBWZrm,       0 },
2002     { X86::VPUNPCKLDQZrr,     X86::VPUNPCKLDQZrm,       0 },
2003     { X86::VPUNPCKLQDQZrr,    X86::VPUNPCKLQDQZrm,      0 },
2004     { X86::VPUNPCKLWDZrr,     X86::VPUNPCKLWDZrm,       0 },
2005     { X86::VPXORDZrr,         X86::VPXORDZrm,           0 },
2006     { X86::VPXORQZrr,         X86::VPXORQZrm,           0 },
2007     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
2008     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
2009     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
2010     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
2011     { X86::VSUBSDZrr,         X86::VSUBSDZrm,           0 },
2012     { X86::VSUBSDZrr_Int,     X86::VSUBSDZrm_Int,       TB_NO_REVERSE },
2013     { X86::VSUBSSZrr,         X86::VSUBSSZrm,           0 },
2014     { X86::VSUBSSZrr_Int,     X86::VSUBSSZrm_Int,       TB_NO_REVERSE },
2015     { X86::VUNPCKHPDZrr,      X86::VUNPCKHPDZrm,        0 },
2016     { X86::VUNPCKHPSZrr,      X86::VUNPCKHPSZrm,        0 },
2017     { X86::VUNPCKLPDZrr,      X86::VUNPCKLPDZrm,        0 },
2018     { X86::VUNPCKLPSZrr,      X86::VUNPCKLPSZrm,        0 },
2019     { X86::VXORPDZrr,         X86::VXORPDZrm,           0 },
2020     { X86::VXORPSZrr,         X86::VXORPSZrm,           0 },
2021 
2022     // AVX-512{F,VL} foldable instructions
2023     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
2024     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
2025     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
2026     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
2027     { X86::VALIGNDZ128rri,    X86::VALIGNDZ128rmi,      0 },
2028     { X86::VALIGNDZ256rri,    X86::VALIGNDZ256rmi,      0 },
2029     { X86::VALIGNQZ128rri,    X86::VALIGNQZ128rmi,      0 },
2030     { X86::VALIGNQZ256rri,    X86::VALIGNQZ256rmi,      0 },
2031     { X86::VANDNPDZ128rr,     X86::VANDNPDZ128rm,       0 },
2032     { X86::VANDNPDZ256rr,     X86::VANDNPDZ256rm,       0 },
2033     { X86::VANDNPSZ128rr,     X86::VANDNPSZ128rm,       0 },
2034     { X86::VANDNPSZ256rr,     X86::VANDNPSZ256rm,       0 },
2035     { X86::VANDPDZ128rr,      X86::VANDPDZ128rm,        0 },
2036     { X86::VANDPDZ256rr,      X86::VANDPDZ256rm,        0 },
2037     { X86::VANDPSZ128rr,      X86::VANDPSZ128rm,        0 },
2038     { X86::VANDPSZ256rr,      X86::VANDPSZ256rm,        0 },
2039     { X86::VCMPPDZ128rri,     X86::VCMPPDZ128rmi,       0 },
2040     { X86::VCMPPDZ256rri,     X86::VCMPPDZ256rmi,       0 },
2041     { X86::VCMPPSZ128rri,     X86::VCMPPSZ128rmi,       0 },
2042     { X86::VCMPPSZ256rri,     X86::VCMPPSZ256rmi,       0 },
2043     { X86::VDIVPDZ128rr,      X86::VDIVPDZ128rm,        0 },
2044     { X86::VDIVPDZ256rr,      X86::VDIVPDZ256rm,        0 },
2045     { X86::VDIVPSZ128rr,      X86::VDIVPSZ128rm,        0 },
2046     { X86::VDIVPSZ256rr,      X86::VDIVPSZ256rm,        0 },
2047     { X86::VINSERTF32x4Z256rr,X86::VINSERTF32x4Z256rm,  0 },
2048     { X86::VINSERTF64x2Z256rr,X86::VINSERTF64x2Z256rm,  0 },
2049     { X86::VINSERTI32x4Z256rr,X86::VINSERTI32x4Z256rm,  0 },
2050     { X86::VINSERTI64x2Z256rr,X86::VINSERTI64x2Z256rm,  0 },
2051     { X86::VMAXCPDZ128rr,     X86::VMAXCPDZ128rm,       0 },
2052     { X86::VMAXCPDZ256rr,     X86::VMAXCPDZ256rm,       0 },
2053     { X86::VMAXCPSZ128rr,     X86::VMAXCPSZ128rm,       0 },
2054     { X86::VMAXCPSZ256rr,     X86::VMAXCPSZ256rm,       0 },
2055     { X86::VMAXPDZ128rr,      X86::VMAXPDZ128rm,        0 },
2056     { X86::VMAXPDZ256rr,      X86::VMAXPDZ256rm,        0 },
2057     { X86::VMAXPSZ128rr,      X86::VMAXPSZ128rm,        0 },
2058     { X86::VMAXPSZ256rr,      X86::VMAXPSZ256rm,        0 },
2059     { X86::VMINCPDZ128rr,     X86::VMINCPDZ128rm,       0 },
2060     { X86::VMINCPDZ256rr,     X86::VMINCPDZ256rm,       0 },
2061     { X86::VMINCPSZ128rr,     X86::VMINCPSZ128rm,       0 },
2062     { X86::VMINCPSZ256rr,     X86::VMINCPSZ256rm,       0 },
2063     { X86::VMINPDZ128rr,      X86::VMINPDZ128rm,        0 },
2064     { X86::VMINPDZ256rr,      X86::VMINPDZ256rm,        0 },
2065     { X86::VMINPSZ128rr,      X86::VMINPSZ128rm,        0 },
2066     { X86::VMINPSZ256rr,      X86::VMINPSZ256rm,        0 },
2067     { X86::VMULPDZ128rr,      X86::VMULPDZ128rm,        0 },
2068     { X86::VMULPDZ256rr,      X86::VMULPDZ256rm,        0 },
2069     { X86::VMULPSZ128rr,      X86::VMULPSZ128rm,        0 },
2070     { X86::VMULPSZ256rr,      X86::VMULPSZ256rm,        0 },
2071     { X86::VORPDZ128rr,       X86::VORPDZ128rm,         0 },
2072     { X86::VORPDZ256rr,       X86::VORPDZ256rm,         0 },
2073     { X86::VORPSZ128rr,       X86::VORPSZ128rm,         0 },
2074     { X86::VORPSZ256rr,       X86::VORPSZ256rm,         0 },
2075     { X86::VPACKSSDWZ256rr,   X86::VPACKSSDWZ256rm,     0 },
2076     { X86::VPACKSSDWZ128rr,   X86::VPACKSSDWZ128rm,     0 },
2077     { X86::VPACKSSWBZ256rr,   X86::VPACKSSWBZ256rm,     0 },
2078     { X86::VPACKSSWBZ128rr,   X86::VPACKSSWBZ128rm,     0 },
2079     { X86::VPACKUSDWZ256rr,   X86::VPACKUSDWZ256rm,     0 },
2080     { X86::VPACKUSDWZ128rr,   X86::VPACKUSDWZ128rm,     0 },
2081     { X86::VPACKUSWBZ256rr,   X86::VPACKUSWBZ256rm,     0 },
2082     { X86::VPACKUSWBZ128rr,   X86::VPACKUSWBZ128rm,     0 },
2083     { X86::VPADDBZ128rr,      X86::VPADDBZ128rm,        0 },
2084     { X86::VPADDBZ256rr,      X86::VPADDBZ256rm,        0 },
2085     { X86::VPADDDZ128rr,      X86::VPADDDZ128rm,        0 },
2086     { X86::VPADDDZ256rr,      X86::VPADDDZ256rm,        0 },
2087     { X86::VPADDQZ128rr,      X86::VPADDQZ128rm,        0 },
2088     { X86::VPADDQZ256rr,      X86::VPADDQZ256rm,        0 },
2089     { X86::VPADDSBZ128rr,     X86::VPADDSBZ128rm,       0 },
2090     { X86::VPADDSBZ256rr,     X86::VPADDSBZ256rm,       0 },
2091     { X86::VPADDSWZ128rr,     X86::VPADDSWZ128rm,       0 },
2092     { X86::VPADDSWZ256rr,     X86::VPADDSWZ256rm,       0 },
2093     { X86::VPADDUSBZ128rr,    X86::VPADDUSBZ128rm,      0 },
2094     { X86::VPADDUSBZ256rr,    X86::VPADDUSBZ256rm,      0 },
2095     { X86::VPADDUSWZ128rr,    X86::VPADDUSWZ128rm,      0 },
2096     { X86::VPADDUSWZ256rr,    X86::VPADDUSWZ256rm,      0 },
2097     { X86::VPADDWZ128rr,      X86::VPADDWZ128rm,        0 },
2098     { X86::VPADDWZ256rr,      X86::VPADDWZ256rm,        0 },
2099     { X86::VPALIGNRZ128rri,   X86::VPALIGNRZ128rmi,     0 },
2100     { X86::VPALIGNRZ256rri,   X86::VPALIGNRZ256rmi,     0 },
2101     { X86::VPANDDZ128rr,      X86::VPANDDZ128rm,        0 },
2102     { X86::VPANDDZ256rr,      X86::VPANDDZ256rm,        0 },
2103     { X86::VPANDNDZ128rr,     X86::VPANDNDZ128rm,       0 },
2104     { X86::VPANDNDZ256rr,     X86::VPANDNDZ256rm,       0 },
2105     { X86::VPANDNQZ128rr,     X86::VPANDNQZ128rm,       0 },
2106     { X86::VPANDNQZ256rr,     X86::VPANDNQZ256rm,       0 },
2107     { X86::VPANDQZ128rr,      X86::VPANDQZ128rm,        0 },
2108     { X86::VPANDQZ256rr,      X86::VPANDQZ256rm,        0 },
2109     { X86::VPAVGBZ128rr,      X86::VPAVGBZ128rm,        0 },
2110     { X86::VPAVGBZ256rr,      X86::VPAVGBZ256rm,        0 },
2111     { X86::VPAVGWZ128rr,      X86::VPAVGWZ128rm,        0 },
2112     { X86::VPAVGWZ256rr,      X86::VPAVGWZ256rm,        0 },
2113     { X86::VPCMPBZ128rri,     X86::VPCMPBZ128rmi,       0 },
2114     { X86::VPCMPBZ256rri,     X86::VPCMPBZ256rmi,       0 },
2115     { X86::VPCMPDZ128rri,     X86::VPCMPDZ128rmi,       0 },
2116     { X86::VPCMPDZ256rri,     X86::VPCMPDZ256rmi,       0 },
2117     { X86::VPCMPEQBZ128rr,    X86::VPCMPEQBZ128rm,      0 },
2118     { X86::VPCMPEQBZ256rr,    X86::VPCMPEQBZ256rm,      0 },
2119     { X86::VPCMPEQDZ128rr,    X86::VPCMPEQDZ128rm,      0 },
2120     { X86::VPCMPEQDZ256rr,    X86::VPCMPEQDZ256rm,      0 },
2121     { X86::VPCMPEQQZ128rr,    X86::VPCMPEQQZ128rm,      0 },
2122     { X86::VPCMPEQQZ256rr,    X86::VPCMPEQQZ256rm,      0 },
2123     { X86::VPCMPEQWZ128rr,    X86::VPCMPEQWZ128rm,      0 },
2124     { X86::VPCMPEQWZ256rr,    X86::VPCMPEQWZ256rm,      0 },
2125     { X86::VPCMPGTBZ128rr,    X86::VPCMPGTBZ128rm,      0 },
2126     { X86::VPCMPGTBZ256rr,    X86::VPCMPGTBZ256rm,      0 },
2127     { X86::VPCMPGTDZ128rr,    X86::VPCMPGTDZ128rm,      0 },
2128     { X86::VPCMPGTDZ256rr,    X86::VPCMPGTDZ256rm,      0 },
2129     { X86::VPCMPGTQZ128rr,    X86::VPCMPGTQZ128rm,      0 },
2130     { X86::VPCMPGTQZ256rr,    X86::VPCMPGTQZ256rm,      0 },
2131     { X86::VPCMPGTWZ128rr,    X86::VPCMPGTWZ128rm,      0 },
2132     { X86::VPCMPGTWZ256rr,    X86::VPCMPGTWZ256rm,      0 },
2133     { X86::VPCMPQZ128rri,     X86::VPCMPQZ128rmi,       0 },
2134     { X86::VPCMPQZ256rri,     X86::VPCMPQZ256rmi,       0 },
2135     { X86::VPCMPUBZ128rri,    X86::VPCMPUBZ128rmi,      0 },
2136     { X86::VPCMPUBZ256rri,    X86::VPCMPUBZ256rmi,      0 },
2137     { X86::VPCMPUDZ128rri,    X86::VPCMPUDZ128rmi,      0 },
2138     { X86::VPCMPUDZ256rri,    X86::VPCMPUDZ256rmi,      0 },
2139     { X86::VPCMPUQZ128rri,    X86::VPCMPUQZ128rmi,      0 },
2140     { X86::VPCMPUQZ256rri,    X86::VPCMPUQZ256rmi,      0 },
2141     { X86::VPCMPUWZ128rri,    X86::VPCMPUWZ128rmi,      0 },
2142     { X86::VPCMPUWZ256rri,    X86::VPCMPUWZ256rmi,      0 },
2143     { X86::VPCMPWZ128rri,     X86::VPCMPWZ128rmi,       0 },
2144     { X86::VPCMPWZ256rri,     X86::VPCMPWZ256rmi,       0 },
2145     { X86::VPERMBZ128rr,      X86::VPERMBZ128rm,        0 },
2146     { X86::VPERMBZ256rr,      X86::VPERMBZ256rm,        0 },
2147     { X86::VPERMDZ256rr,      X86::VPERMDZ256rm,        0 },
2148     { X86::VPERMILPDZ128rr,   X86::VPERMILPDZ128rm,     0 },
2149     { X86::VPERMILPDZ256rr,   X86::VPERMILPDZ256rm,     0 },
2150     { X86::VPERMILPSZ128rr,   X86::VPERMILPSZ128rm,     0 },
2151     { X86::VPERMILPSZ256rr,   X86::VPERMILPSZ256rm,     0 },
2152     { X86::VPERMPDZ256rr,     X86::VPERMPDZ256rm,       0 },
2153     { X86::VPERMPSZ256rr,     X86::VPERMPSZ256rm,       0 },
2154     { X86::VPERMQZ256rr,      X86::VPERMQZ256rm,        0 },
2155     { X86::VPERMWZ128rr,      X86::VPERMWZ128rm,        0 },
2156     { X86::VPERMWZ256rr,      X86::VPERMWZ256rm,        0 },
2157     { X86::VPMADDUBSWZ128rr,  X86::VPMADDUBSWZ128rm,    0 },
2158     { X86::VPMADDUBSWZ256rr,  X86::VPMADDUBSWZ256rm,    0 },
2159     { X86::VPMADDWDZ128rr,    X86::VPMADDWDZ128rm,      0 },
2160     { X86::VPMADDWDZ256rr,    X86::VPMADDWDZ256rm,      0 },
2161     { X86::VPMAXSBZ128rr,     X86::VPMAXSBZ128rm,       0 },
2162     { X86::VPMAXSBZ256rr,     X86::VPMAXSBZ256rm,       0 },
2163     { X86::VPMAXSDZ128rr,     X86::VPMAXSDZ128rm,       0 },
2164     { X86::VPMAXSDZ256rr,     X86::VPMAXSDZ256rm,       0 },
2165     { X86::VPMAXSQZ128rr,     X86::VPMAXSQZ128rm,       0 },
2166     { X86::VPMAXSQZ256rr,     X86::VPMAXSQZ256rm,       0 },
2167     { X86::VPMAXSWZ128rr,     X86::VPMAXSWZ128rm,       0 },
2168     { X86::VPMAXSWZ256rr,     X86::VPMAXSWZ256rm,       0 },
2169     { X86::VPMAXUBZ128rr,     X86::VPMAXUBZ128rm,       0 },
2170     { X86::VPMAXUBZ256rr,     X86::VPMAXUBZ256rm,       0 },
2171     { X86::VPMAXUDZ128rr,     X86::VPMAXUDZ128rm,       0 },
2172     { X86::VPMAXUDZ256rr,     X86::VPMAXUDZ256rm,       0 },
2173     { X86::VPMAXUQZ128rr,     X86::VPMAXUQZ128rm,       0 },
2174     { X86::VPMAXUQZ256rr,     X86::VPMAXUQZ256rm,       0 },
2175     { X86::VPMAXUWZ128rr,     X86::VPMAXUWZ128rm,       0 },
2176     { X86::VPMAXUWZ256rr,     X86::VPMAXUWZ256rm,       0 },
2177     { X86::VPMINSBZ128rr,     X86::VPMINSBZ128rm,       0 },
2178     { X86::VPMINSBZ256rr,     X86::VPMINSBZ256rm,       0 },
2179     { X86::VPMINSDZ128rr,     X86::VPMINSDZ128rm,       0 },
2180     { X86::VPMINSDZ256rr,     X86::VPMINSDZ256rm,       0 },
2181     { X86::VPMINSQZ128rr,     X86::VPMINSQZ128rm,       0 },
2182     { X86::VPMINSQZ256rr,     X86::VPMINSQZ256rm,       0 },
2183     { X86::VPMINSWZ128rr,     X86::VPMINSWZ128rm,       0 },
2184     { X86::VPMINSWZ256rr,     X86::VPMINSWZ256rm,       0 },
2185     { X86::VPMINUBZ128rr,     X86::VPMINUBZ128rm,       0 },
2186     { X86::VPMINUBZ256rr,     X86::VPMINUBZ256rm,       0 },
2187     { X86::VPMINUDZ128rr,     X86::VPMINUDZ128rm,       0 },
2188     { X86::VPMINUDZ256rr,     X86::VPMINUDZ256rm,       0 },
2189     { X86::VPMINUQZ128rr,     X86::VPMINUQZ128rm,       0 },
2190     { X86::VPMINUQZ256rr,     X86::VPMINUQZ256rm,       0 },
2191     { X86::VPMINUWZ128rr,     X86::VPMINUWZ128rm,       0 },
2192     { X86::VPMINUWZ256rr,     X86::VPMINUWZ256rm,       0 },
2193     { X86::VPMULDQZ128rr,     X86::VPMULDQZ128rm,       0 },
2194     { X86::VPMULDQZ256rr,     X86::VPMULDQZ256rm,       0 },
2195     { X86::VPMULLDZ128rr,     X86::VPMULLDZ128rm,       0 },
2196     { X86::VPMULLDZ256rr,     X86::VPMULLDZ256rm,       0 },
2197     { X86::VPMULLQZ128rr,     X86::VPMULLQZ128rm,       0 },
2198     { X86::VPMULLQZ256rr,     X86::VPMULLQZ256rm,       0 },
2199     { X86::VPMULLWZ128rr,     X86::VPMULLWZ128rm,       0 },
2200     { X86::VPMULLWZ256rr,     X86::VPMULLWZ256rm,       0 },
2201     { X86::VPMULUDQZ128rr,    X86::VPMULUDQZ128rm,      0 },
2202     { X86::VPMULUDQZ256rr,    X86::VPMULUDQZ256rm,      0 },
2203     { X86::VPORDZ128rr,       X86::VPORDZ128rm,         0 },
2204     { X86::VPORDZ256rr,       X86::VPORDZ256rm,         0 },
2205     { X86::VPORQZ128rr,       X86::VPORQZ128rm,         0 },
2206     { X86::VPORQZ256rr,       X86::VPORQZ256rm,         0 },
2207     { X86::VPSADBWZ128rr,     X86::VPSADBWZ128rm,       0 },
2208     { X86::VPSADBWZ256rr,     X86::VPSADBWZ256rm,       0 },
2209     { X86::VPSHUFBZ128rr,     X86::VPSHUFBZ128rm,       0 },
2210     { X86::VPSHUFBZ256rr,     X86::VPSHUFBZ256rm,       0 },
2211     { X86::VPSLLDZ128rr,      X86::VPSLLDZ128rm,        0 },
2212     { X86::VPSLLDZ256rr,      X86::VPSLLDZ256rm,        0 },
2213     { X86::VPSLLQZ128rr,      X86::VPSLLQZ128rm,        0 },
2214     { X86::VPSLLQZ256rr,      X86::VPSLLQZ256rm,        0 },
2215     { X86::VPSLLVDZ128rr,     X86::VPSLLVDZ128rm,       0 },
2216     { X86::VPSLLVDZ256rr,     X86::VPSLLVDZ256rm,       0 },
2217     { X86::VPSLLVQZ128rr,     X86::VPSLLVQZ128rm,       0 },
2218     { X86::VPSLLVQZ256rr,     X86::VPSLLVQZ256rm,       0 },
2219     { X86::VPSLLVWZ128rr,     X86::VPSLLVWZ128rm,       0 },
2220     { X86::VPSLLVWZ256rr,     X86::VPSLLVWZ256rm,       0 },
2221     { X86::VPSLLWZ128rr,      X86::VPSLLWZ128rm,        0 },
2222     { X86::VPSLLWZ256rr,      X86::VPSLLWZ256rm,        0 },
2223     { X86::VPSRADZ128rr,      X86::VPSRADZ128rm,        0 },
2224     { X86::VPSRADZ256rr,      X86::VPSRADZ256rm,        0 },
2225     { X86::VPSRAQZ128rr,      X86::VPSRAQZ128rm,        0 },
2226     { X86::VPSRAQZ256rr,      X86::VPSRAQZ256rm,        0 },
2227     { X86::VPSRAVDZ128rr,     X86::VPSRAVDZ128rm,       0 },
2228     { X86::VPSRAVDZ256rr,     X86::VPSRAVDZ256rm,       0 },
2229     { X86::VPSRAVQZ128rr,     X86::VPSRAVQZ128rm,       0 },
2230     { X86::VPSRAVQZ256rr,     X86::VPSRAVQZ256rm,       0 },
2231     { X86::VPSRAVWZ128rr,     X86::VPSRAVWZ128rm,       0 },
2232     { X86::VPSRAVWZ256rr,     X86::VPSRAVWZ256rm,       0 },
2233     { X86::VPSRAWZ128rr,      X86::VPSRAWZ128rm,        0 },
2234     { X86::VPSRAWZ256rr,      X86::VPSRAWZ256rm,        0 },
2235     { X86::VPSRLDZ128rr,      X86::VPSRLDZ128rm,        0 },
2236     { X86::VPSRLDZ256rr,      X86::VPSRLDZ256rm,        0 },
2237     { X86::VPSRLQZ128rr,      X86::VPSRLQZ128rm,        0 },
2238     { X86::VPSRLQZ256rr,      X86::VPSRLQZ256rm,        0 },
2239     { X86::VPSRLVDZ128rr,     X86::VPSRLVDZ128rm,       0 },
2240     { X86::VPSRLVDZ256rr,     X86::VPSRLVDZ256rm,       0 },
2241     { X86::VPSRLVQZ128rr,     X86::VPSRLVQZ128rm,       0 },
2242     { X86::VPSRLVQZ256rr,     X86::VPSRLVQZ256rm,       0 },
2243     { X86::VPSRLVWZ128rr,     X86::VPSRLVWZ128rm,       0 },
2244     { X86::VPSRLVWZ256rr,     X86::VPSRLVWZ256rm,       0 },
2245     { X86::VPSRLWZ128rr,      X86::VPSRLWZ128rm,        0 },
2246     { X86::VPSRLWZ256rr,      X86::VPSRLWZ256rm,        0 },
2247     { X86::VPSUBBZ128rr,      X86::VPSUBBZ128rm,        0 },
2248     { X86::VPSUBBZ256rr,      X86::VPSUBBZ256rm,        0 },
2249     { X86::VPSUBDZ128rr,      X86::VPSUBDZ128rm,        0 },
2250     { X86::VPSUBDZ256rr,      X86::VPSUBDZ256rm,        0 },
2251     { X86::VPSUBQZ128rr,      X86::VPSUBQZ128rm,        0 },
2252     { X86::VPSUBQZ256rr,      X86::VPSUBQZ256rm,        0 },
2253     { X86::VPSUBSBZ128rr,     X86::VPSUBSBZ128rm,       0 },
2254     { X86::VPSUBSBZ256rr,     X86::VPSUBSBZ256rm,       0 },
2255     { X86::VPSUBSWZ128rr,     X86::VPSUBSWZ128rm,       0 },
2256     { X86::VPSUBSWZ256rr,     X86::VPSUBSWZ256rm,       0 },
2257     { X86::VPSUBUSBZ128rr,    X86::VPSUBUSBZ128rm,      0 },
2258     { X86::VPSUBUSBZ256rr,    X86::VPSUBUSBZ256rm,      0 },
2259     { X86::VPSUBUSWZ128rr,    X86::VPSUBUSWZ128rm,      0 },
2260     { X86::VPSUBUSWZ256rr,    X86::VPSUBUSWZ256rm,      0 },
2261     { X86::VPSUBWZ128rr,      X86::VPSUBWZ128rm,        0 },
2262     { X86::VPSUBWZ256rr,      X86::VPSUBWZ256rm,        0 },
2263     { X86::VPUNPCKHBWZ128rr,  X86::VPUNPCKHBWZ128rm,    0 },
2264     { X86::VPUNPCKHBWZ256rr,  X86::VPUNPCKHBWZ256rm,    0 },
2265     { X86::VPUNPCKHDQZ128rr,  X86::VPUNPCKHDQZ128rm,    0 },
2266     { X86::VPUNPCKHDQZ256rr,  X86::VPUNPCKHDQZ256rm,    0 },
2267     { X86::VPUNPCKHQDQZ128rr, X86::VPUNPCKHQDQZ128rm,   0 },
2268     { X86::VPUNPCKHQDQZ256rr, X86::VPUNPCKHQDQZ256rm,   0 },
2269     { X86::VPUNPCKHWDZ128rr,  X86::VPUNPCKHWDZ128rm,    0 },
2270     { X86::VPUNPCKHWDZ256rr,  X86::VPUNPCKHWDZ256rm,    0 },
2271     { X86::VPUNPCKLBWZ128rr,  X86::VPUNPCKLBWZ128rm,    0 },
2272     { X86::VPUNPCKLBWZ256rr,  X86::VPUNPCKLBWZ256rm,    0 },
2273     { X86::VPUNPCKLDQZ128rr,  X86::VPUNPCKLDQZ128rm,    0 },
2274     { X86::VPUNPCKLDQZ256rr,  X86::VPUNPCKLDQZ256rm,    0 },
2275     { X86::VPUNPCKLQDQZ128rr, X86::VPUNPCKLQDQZ128rm,   0 },
2276     { X86::VPUNPCKLQDQZ256rr, X86::VPUNPCKLQDQZ256rm,   0 },
2277     { X86::VPUNPCKLWDZ128rr,  X86::VPUNPCKLWDZ128rm,    0 },
2278     { X86::VPUNPCKLWDZ256rr,  X86::VPUNPCKLWDZ256rm,    0 },
2279     { X86::VPXORDZ128rr,      X86::VPXORDZ128rm,        0 },
2280     { X86::VPXORDZ256rr,      X86::VPXORDZ256rm,        0 },
2281     { X86::VPXORQZ128rr,      X86::VPXORQZ128rm,        0 },
2282     { X86::VPXORQZ256rr,      X86::VPXORQZ256rm,        0 },
2283     { X86::VSHUFPDZ128rri,    X86::VSHUFPDZ128rmi,      0 },
2284     { X86::VSHUFPDZ256rri,    X86::VSHUFPDZ256rmi,      0 },
2285     { X86::VSHUFPSZ128rri,    X86::VSHUFPSZ128rmi,      0 },
2286     { X86::VSHUFPSZ256rri,    X86::VSHUFPSZ256rmi,      0 },
2287     { X86::VSUBPDZ128rr,      X86::VSUBPDZ128rm,        0 },
2288     { X86::VSUBPDZ256rr,      X86::VSUBPDZ256rm,        0 },
2289     { X86::VSUBPSZ128rr,      X86::VSUBPSZ128rm,        0 },
2290     { X86::VSUBPSZ256rr,      X86::VSUBPSZ256rm,        0 },
2291     { X86::VUNPCKHPDZ128rr,   X86::VUNPCKHPDZ128rm,     0 },
2292     { X86::VUNPCKHPDZ256rr,   X86::VUNPCKHPDZ256rm,     0 },
2293     { X86::VUNPCKHPSZ128rr,   X86::VUNPCKHPSZ128rm,     0 },
2294     { X86::VUNPCKHPSZ256rr,   X86::VUNPCKHPSZ256rm,     0 },
2295     { X86::VUNPCKLPDZ128rr,   X86::VUNPCKLPDZ128rm,     0 },
2296     { X86::VUNPCKLPDZ256rr,   X86::VUNPCKLPDZ256rm,     0 },
2297     { X86::VUNPCKLPSZ128rr,   X86::VUNPCKLPSZ128rm,     0 },
2298     { X86::VUNPCKLPSZ256rr,   X86::VUNPCKLPSZ256rm,     0 },
2299     { X86::VXORPDZ128rr,      X86::VXORPDZ128rm,        0 },
2300     { X86::VXORPDZ256rr,      X86::VXORPDZ256rm,        0 },
2301     { X86::VXORPSZ128rr,      X86::VXORPSZ128rm,        0 },
2302     { X86::VXORPSZ256rr,      X86::VXORPSZ256rm,        0 },
2303 
2304     // AVX-512 masked foldable instructions
2305     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
2306     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
2307     { X86::VPABSBZrrkz,       X86::VPABSBZrmkz,         0 },
2308     { X86::VPABSDZrrkz,       X86::VPABSDZrmkz,         0 },
2309     { X86::VPABSQZrrkz,       X86::VPABSQZrmkz,         0 },
2310     { X86::VPABSWZrrkz,       X86::VPABSWZrmkz,         0 },
2311     { X86::VPERMILPDZrikz,    X86::VPERMILPDZmikz,      0 },
2312     { X86::VPERMILPSZrikz,    X86::VPERMILPSZmikz,      0 },
2313     { X86::VPERMPDZrikz,      X86::VPERMPDZmikz,        0 },
2314     { X86::VPERMQZrikz,       X86::VPERMQZmikz,         0 },
2315     { X86::VPMOVSXBDZrrkz,    X86::VPMOVSXBDZrmkz,      0 },
2316     { X86::VPMOVSXBQZrrkz,    X86::VPMOVSXBQZrmkz,      TB_NO_REVERSE },
2317     { X86::VPMOVSXBWZrrkz,    X86::VPMOVSXBWZrmkz,      0 },
2318     { X86::VPMOVSXDQZrrkz,    X86::VPMOVSXDQZrmkz,      0 },
2319     { X86::VPMOVSXWDZrrkz,    X86::VPMOVSXWDZrmkz,      0 },
2320     { X86::VPMOVSXWQZrrkz,    X86::VPMOVSXWQZrmkz,      0 },
2321     { X86::VPMOVZXBDZrrkz,    X86::VPMOVZXBDZrmkz,      0 },
2322     { X86::VPMOVZXBQZrrkz,    X86::VPMOVZXBQZrmkz,      TB_NO_REVERSE },
2323     { X86::VPMOVZXBWZrrkz,    X86::VPMOVZXBWZrmkz,      0 },
2324     { X86::VPMOVZXDQZrrkz,    X86::VPMOVZXDQZrmkz,      0 },
2325     { X86::VPMOVZXWDZrrkz,    X86::VPMOVZXWDZrmkz,      0 },
2326     { X86::VPMOVZXWQZrrkz,    X86::VPMOVZXWQZrmkz,      0 },
2327     { X86::VPSHUFDZrikz,      X86::VPSHUFDZmikz,        0 },
2328     { X86::VPSHUFHWZrikz,     X86::VPSHUFHWZmikz,       0 },
2329     { X86::VPSHUFLWZrikz,     X86::VPSHUFLWZmikz,       0 },
2330     { X86::VPSLLDZrikz,       X86::VPSLLDZmikz,         0 },
2331     { X86::VPSLLQZrikz,       X86::VPSLLQZmikz,         0 },
2332     { X86::VPSLLWZrikz,       X86::VPSLLWZmikz,         0 },
2333     { X86::VPSRADZrikz,       X86::VPSRADZmikz,         0 },
2334     { X86::VPSRAQZrikz,       X86::VPSRAQZmikz,         0 },
2335     { X86::VPSRAWZrikz,       X86::VPSRAWZmikz,         0 },
2336     { X86::VPSRLDZrikz,       X86::VPSRLDZmikz,         0 },
2337     { X86::VPSRLQZrikz,       X86::VPSRLQZmikz,         0 },
2338     { X86::VPSRLWZrikz,       X86::VPSRLWZmikz,         0 },
2339 
2340     // AVX-512VL 256-bit masked foldable instructions
2341     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
2342     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
2343     { X86::VPABSBZ256rrkz,    X86::VPABSBZ256rmkz,      0 },
2344     { X86::VPABSDZ256rrkz,    X86::VPABSDZ256rmkz,      0 },
2345     { X86::VPABSQZ256rrkz,    X86::VPABSQZ256rmkz,      0 },
2346     { X86::VPABSWZ256rrkz,    X86::VPABSWZ256rmkz,      0 },
2347     { X86::VPERMILPDZ256rikz, X86::VPERMILPDZ256mikz,   0 },
2348     { X86::VPERMILPSZ256rikz, X86::VPERMILPSZ256mikz,   0 },
2349     { X86::VPERMPDZ256rikz,   X86::VPERMPDZ256mikz,     0 },
2350     { X86::VPERMQZ256rikz,    X86::VPERMQZ256mikz,      0 },
2351     { X86::VPMOVSXBDZ256rrkz, X86::VPMOVSXBDZ256rmkz,   TB_NO_REVERSE },
2352     { X86::VPMOVSXBQZ256rrkz, X86::VPMOVSXBQZ256rmkz,   TB_NO_REVERSE },
2353     { X86::VPMOVSXBWZ256rrkz, X86::VPMOVSXBWZ256rmkz,   0 },
2354     { X86::VPMOVSXDQZ256rrkz, X86::VPMOVSXDQZ256rmkz,   0 },
2355     { X86::VPMOVSXWDZ256rrkz, X86::VPMOVSXWDZ256rmkz,   0 },
2356     { X86::VPMOVSXWQZ256rrkz, X86::VPMOVSXWQZ256rmkz,   TB_NO_REVERSE },
2357     { X86::VPMOVZXBDZ256rrkz, X86::VPMOVZXBDZ256rmkz,   TB_NO_REVERSE },
2358     { X86::VPMOVZXBQZ256rrkz, X86::VPMOVZXBQZ256rmkz,   TB_NO_REVERSE },
2359     { X86::VPMOVZXBWZ256rrkz, X86::VPMOVZXBWZ256rmkz,   0 },
2360     { X86::VPMOVZXDQZ256rrkz, X86::VPMOVZXDQZ256rmkz,   0 },
2361     { X86::VPMOVZXWDZ256rrkz, X86::VPMOVZXWDZ256rmkz,   0 },
2362     { X86::VPMOVZXWQZ256rrkz, X86::VPMOVZXWQZ256rmkz,   TB_NO_REVERSE },
2363     { X86::VPSHUFDZ256rikz,   X86::VPSHUFDZ256mikz,     0 },
2364     { X86::VPSHUFHWZ256rikz,  X86::VPSHUFHWZ256mikz,    0 },
2365     { X86::VPSHUFLWZ256rikz,  X86::VPSHUFLWZ256mikz,    0 },
2366     { X86::VPSLLDZ256rikz,    X86::VPSLLDZ256mikz,      0 },
2367     { X86::VPSLLQZ256rikz,    X86::VPSLLQZ256mikz,      0 },
2368     { X86::VPSLLWZ256rikz,    X86::VPSLLWZ256mikz,      0 },
2369     { X86::VPSRADZ256rikz,    X86::VPSRADZ256mikz,      0 },
2370     { X86::VPSRAQZ256rikz,    X86::VPSRAQZ256mikz,      0 },
2371     { X86::VPSRAWZ256rikz,    X86::VPSRAWZ256mikz,      0 },
2372     { X86::VPSRLDZ256rikz,    X86::VPSRLDZ256mikz,      0 },
2373     { X86::VPSRLQZ256rikz,    X86::VPSRLQZ256mikz,      0 },
2374     { X86::VPSRLWZ256rikz,    X86::VPSRLWZ256mikz,      0 },
2375 
2376     // AVX-512VL 128-bit masked foldable instructions
2377     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
2378     { X86::VPABSBZ128rrkz,    X86::VPABSBZ128rmkz,      0 },
2379     { X86::VPABSDZ128rrkz,    X86::VPABSDZ128rmkz,      0 },
2380     { X86::VPABSQZ128rrkz,    X86::VPABSQZ128rmkz,      0 },
2381     { X86::VPABSWZ128rrkz,    X86::VPABSWZ128rmkz,      0 },
2382     { X86::VPERMILPDZ128rikz, X86::VPERMILPDZ128mikz,   0 },
2383     { X86::VPERMILPSZ128rikz, X86::VPERMILPSZ128mikz,   0 },
2384     { X86::VPMOVSXBDZ128rrkz, X86::VPMOVSXBDZ128rmkz,   TB_NO_REVERSE },
2385     { X86::VPMOVSXBQZ128rrkz, X86::VPMOVSXBQZ128rmkz,   TB_NO_REVERSE },
2386     { X86::VPMOVSXBWZ128rrkz, X86::VPMOVSXBWZ128rmkz,   TB_NO_REVERSE },
2387     { X86::VPMOVSXDQZ128rrkz, X86::VPMOVSXDQZ128rmkz,   TB_NO_REVERSE },
2388     { X86::VPMOVSXWDZ128rrkz, X86::VPMOVSXWDZ128rmkz,   TB_NO_REVERSE },
2389     { X86::VPMOVSXWQZ128rrkz, X86::VPMOVSXWQZ128rmkz,   TB_NO_REVERSE },
2390     { X86::VPMOVZXBDZ128rrkz, X86::VPMOVZXBDZ128rmkz,   TB_NO_REVERSE },
2391     { X86::VPMOVZXBQZ128rrkz, X86::VPMOVZXBQZ128rmkz,   TB_NO_REVERSE },
2392     { X86::VPMOVZXBWZ128rrkz, X86::VPMOVZXBWZ128rmkz,   TB_NO_REVERSE },
2393     { X86::VPMOVZXDQZ128rrkz, X86::VPMOVZXDQZ128rmkz,   TB_NO_REVERSE },
2394     { X86::VPMOVZXWDZ128rrkz, X86::VPMOVZXWDZ128rmkz,   TB_NO_REVERSE },
2395     { X86::VPMOVZXWQZ128rrkz, X86::VPMOVZXWQZ128rmkz,   TB_NO_REVERSE },
2396     { X86::VPSHUFDZ128rikz,   X86::VPSHUFDZ128mikz,     0 },
2397     { X86::VPSHUFHWZ128rikz,  X86::VPSHUFHWZ128mikz,    0 },
2398     { X86::VPSHUFLWZ128rikz,  X86::VPSHUFLWZ128mikz,    0 },
2399     { X86::VPSLLDZ128rikz,    X86::VPSLLDZ128mikz,      0 },
2400     { X86::VPSLLQZ128rikz,    X86::VPSLLQZ128mikz,      0 },
2401     { X86::VPSLLWZ128rikz,    X86::VPSLLWZ128mikz,      0 },
2402     { X86::VPSRADZ128rikz,    X86::VPSRADZ128mikz,      0 },
2403     { X86::VPSRAQZ128rikz,    X86::VPSRAQZ128mikz,      0 },
2404     { X86::VPSRAWZ128rikz,    X86::VPSRAWZ128mikz,      0 },
2405     { X86::VPSRLDZ128rikz,    X86::VPSRLDZ128mikz,      0 },
2406     { X86::VPSRLQZ128rikz,    X86::VPSRLQZ128mikz,      0 },
2407     { X86::VPSRLWZ128rikz,    X86::VPSRLWZ128mikz,      0 },
2408 
2409     // AES foldable instructions
2410     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
2411     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
2412     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
2413     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
2414     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
2415     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
2416     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
2417     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
2418 
2419     // SHA foldable instructions
2420     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
2421     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
2422     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
2423     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
2424     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
2425     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
2426     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
2427   };
2428 
2429   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
2430     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
2431                   Entry.RegOp, Entry.MemOp,
2432                   // Index 2, folded load
2433                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
2434   }
2435 
2436   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
2437     // FMA4 foldable patterns
2438     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
2439     { X86::VFMADDSS4rr_Int,       X86::VFMADDSS4rm_Int,       TB_NO_REVERSE },
2440     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
2441     { X86::VFMADDSD4rr_Int,       X86::VFMADDSD4rm_Int,       TB_NO_REVERSE },
2442     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
2443     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
2444     { X86::VFMADDPS4Yrr,          X86::VFMADDPS4Yrm,          TB_ALIGN_NONE },
2445     { X86::VFMADDPD4Yrr,          X86::VFMADDPD4Yrm,          TB_ALIGN_NONE },
2446     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
2447     { X86::VFNMADDSS4rr_Int,      X86::VFNMADDSS4rm_Int,      TB_NO_REVERSE },
2448     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
2449     { X86::VFNMADDSD4rr_Int,      X86::VFNMADDSD4rm_Int,      TB_NO_REVERSE },
2450     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
2451     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
2452     { X86::VFNMADDPS4Yrr,         X86::VFNMADDPS4Yrm,         TB_ALIGN_NONE },
2453     { X86::VFNMADDPD4Yrr,         X86::VFNMADDPD4Yrm,         TB_ALIGN_NONE },
2454     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
2455     { X86::VFMSUBSS4rr_Int,       X86::VFMSUBSS4rm_Int,       TB_NO_REVERSE },
2456     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
2457     { X86::VFMSUBSD4rr_Int,       X86::VFMSUBSD4rm_Int,       TB_NO_REVERSE },
2458     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
2459     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
2460     { X86::VFMSUBPS4Yrr,          X86::VFMSUBPS4Yrm,          TB_ALIGN_NONE },
2461     { X86::VFMSUBPD4Yrr,          X86::VFMSUBPD4Yrm,          TB_ALIGN_NONE },
2462     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
2463     { X86::VFNMSUBSS4rr_Int,      X86::VFNMSUBSS4rm_Int,      TB_NO_REVERSE },
2464     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
2465     { X86::VFNMSUBSD4rr_Int,      X86::VFNMSUBSD4rm_Int,      TB_NO_REVERSE },
2466     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
2467     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
2468     { X86::VFNMSUBPS4Yrr,         X86::VFNMSUBPS4Yrm,         TB_ALIGN_NONE },
2469     { X86::VFNMSUBPD4Yrr,         X86::VFNMSUBPD4Yrm,         TB_ALIGN_NONE },
2470     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
2471     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
2472     { X86::VFMADDSUBPS4Yrr,       X86::VFMADDSUBPS4Yrm,       TB_ALIGN_NONE },
2473     { X86::VFMADDSUBPD4Yrr,       X86::VFMADDSUBPD4Yrm,       TB_ALIGN_NONE },
2474     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
2475     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
2476     { X86::VFMSUBADDPS4Yrr,       X86::VFMSUBADDPS4Yrm,       TB_ALIGN_NONE },
2477     { X86::VFMSUBADDPD4Yrr,       X86::VFMSUBADDPD4Yrm,       TB_ALIGN_NONE },
2478 
2479     // XOP foldable instructions
2480     { X86::VPCMOVrrr,             X86::VPCMOVrrm,             0 },
2481     { X86::VPCMOVrrrY,            X86::VPCMOVrrmY,            0 },
2482     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
2483     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
2484     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
2485     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
2486     { X86::VPPERMrrr,             X86::VPPERMrrm,             0 },
2487 
2488     // AVX-512 instructions with 3 source operands.
2489     { X86::VPERMI2Brr,            X86::VPERMI2Brm,            0 },
2490     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
2491     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
2492     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
2493     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
2494     { X86::VPERMI2Wrr,            X86::VPERMI2Wrm,            0 },
2495     { X86::VPERMT2Brr,            X86::VPERMT2Brm,            0 },
2496     { X86::VPERMT2Drr,            X86::VPERMT2Drm,            0 },
2497     { X86::VPERMT2PSrr,           X86::VPERMT2PSrm,           0 },
2498     { X86::VPERMT2PDrr,           X86::VPERMT2PDrm,           0 },
2499     { X86::VPERMT2Qrr,            X86::VPERMT2Qrm,            0 },
2500     { X86::VPERMT2Wrr,            X86::VPERMT2Wrm,            0 },
2501     { X86::VPTERNLOGDZrri,        X86::VPTERNLOGDZrmi,        0 },
2502     { X86::VPTERNLOGQZrri,        X86::VPTERNLOGQZrmi,        0 },
2503 
2504     // AVX-512VL 256-bit instructions with 3 source operands.
2505     { X86::VPERMI2B256rr,         X86::VPERMI2B256rm,         0 },
2506     { X86::VPERMI2D256rr,         X86::VPERMI2D256rm,         0 },
2507     { X86::VPERMI2PD256rr,        X86::VPERMI2PD256rm,        0 },
2508     { X86::VPERMI2PS256rr,        X86::VPERMI2PS256rm,        0 },
2509     { X86::VPERMI2Q256rr,         X86::VPERMI2Q256rm,         0 },
2510     { X86::VPERMI2W256rr,         X86::VPERMI2W256rm,         0 },
2511     { X86::VPERMT2B256rr,         X86::VPERMT2B256rm,         0 },
2512     { X86::VPERMT2D256rr,         X86::VPERMT2D256rm,         0 },
2513     { X86::VPERMT2PD256rr,        X86::VPERMT2PD256rm,        0 },
2514     { X86::VPERMT2PS256rr,        X86::VPERMT2PS256rm,        0 },
2515     { X86::VPERMT2Q256rr,         X86::VPERMT2Q256rm,         0 },
2516     { X86::VPERMT2W256rr,         X86::VPERMT2W256rm,         0 },
2517     { X86::VPTERNLOGDZ256rri,     X86::VPTERNLOGDZ256rmi,     0 },
2518     { X86::VPTERNLOGQZ256rri,     X86::VPTERNLOGQZ256rmi,     0 },
2519 
2520     // AVX-512VL 128-bit instructions with 3 source operands.
2521     { X86::VPERMI2B128rr,         X86::VPERMI2B128rm,         0 },
2522     { X86::VPERMI2D128rr,         X86::VPERMI2D128rm,         0 },
2523     { X86::VPERMI2PD128rr,        X86::VPERMI2PD128rm,        0 },
2524     { X86::VPERMI2PS128rr,        X86::VPERMI2PS128rm,        0 },
2525     { X86::VPERMI2Q128rr,         X86::VPERMI2Q128rm,         0 },
2526     { X86::VPERMI2W128rr,         X86::VPERMI2W128rm,         0 },
2527     { X86::VPERMT2B128rr,         X86::VPERMT2B128rm,         0 },
2528     { X86::VPERMT2D128rr,         X86::VPERMT2D128rm,         0 },
2529     { X86::VPERMT2PD128rr,        X86::VPERMT2PD128rm,        0 },
2530     { X86::VPERMT2PS128rr,        X86::VPERMT2PS128rm,        0 },
2531     { X86::VPERMT2Q128rr,         X86::VPERMT2Q128rm,         0 },
2532     { X86::VPERMT2W128rr,         X86::VPERMT2W128rm,         0 },
2533     { X86::VPTERNLOGDZ128rri,     X86::VPTERNLOGDZ128rmi,     0 },
2534     { X86::VPTERNLOGQZ128rri,     X86::VPTERNLOGQZ128rmi,     0 },
2535 
2536     // AVX-512 masked instructions
2537     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
2538     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
2539     { X86::VADDSDZrr_Intkz,       X86::VADDSDZrm_Intkz,       TB_NO_REVERSE },
2540     { X86::VADDSSZrr_Intkz,       X86::VADDSSZrm_Intkz,       TB_NO_REVERSE },
2541     { X86::VALIGNDZrrikz,         X86::VALIGNDZrmikz,         0 },
2542     { X86::VALIGNQZrrikz,         X86::VALIGNQZrmikz,         0 },
2543     { X86::VANDNPDZrrkz,          X86::VANDNPDZrmkz,          0 },
2544     { X86::VANDNPSZrrkz,          X86::VANDNPSZrmkz,          0 },
2545     { X86::VANDPDZrrkz,           X86::VANDPDZrmkz,           0 },
2546     { X86::VANDPSZrrkz,           X86::VANDPSZrmkz,           0 },
2547     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
2548     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
2549     { X86::VDIVSDZrr_Intkz,       X86::VDIVSDZrm_Intkz,       TB_NO_REVERSE },
2550     { X86::VDIVSSZrr_Intkz,       X86::VDIVSSZrm_Intkz,       TB_NO_REVERSE },
2551     { X86::VINSERTF32x4Zrrkz,     X86::VINSERTF32x4Zrmkz,     0 },
2552     { X86::VINSERTF32x8Zrrkz,     X86::VINSERTF32x8Zrmkz,     0 },
2553     { X86::VINSERTF64x2Zrrkz,     X86::VINSERTF64x2Zrmkz,     0 },
2554     { X86::VINSERTF64x4Zrrkz,     X86::VINSERTF64x4Zrmkz,     0 },
2555     { X86::VINSERTI32x4Zrrkz,     X86::VINSERTI32x4Zrmkz,     0 },
2556     { X86::VINSERTI32x8Zrrkz,     X86::VINSERTI32x8Zrmkz,     0 },
2557     { X86::VINSERTI64x2Zrrkz,     X86::VINSERTI64x2Zrmkz,     0 },
2558     { X86::VINSERTI64x4Zrrkz,     X86::VINSERTI64x4Zrmkz,     0 },
2559     { X86::VMAXCPDZrrkz,          X86::VMAXCPDZrmkz,          0 },
2560     { X86::VMAXCPSZrrkz,          X86::VMAXCPSZrmkz,          0 },
2561     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
2562     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
2563     { X86::VMAXSDZrr_Intkz,       X86::VMAXSDZrm_Intkz,       0 },
2564     { X86::VMAXSSZrr_Intkz,       X86::VMAXSSZrm_Intkz,       0 },
2565     { X86::VMINCPDZrrkz,          X86::VMINCPDZrmkz,          0 },
2566     { X86::VMINCPSZrrkz,          X86::VMINCPSZrmkz,          0 },
2567     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
2568     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
2569     { X86::VMINSDZrr_Intkz,       X86::VMINSDZrm_Intkz,       0 },
2570     { X86::VMINSSZrr_Intkz,       X86::VMINSSZrm_Intkz,       0 },
2571     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
2572     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
2573     { X86::VMULSDZrr_Intkz,       X86::VMULSDZrm_Intkz,       TB_NO_REVERSE },
2574     { X86::VMULSSZrr_Intkz,       X86::VMULSSZrm_Intkz,       TB_NO_REVERSE },
2575     { X86::VORPDZrrkz,            X86::VORPDZrmkz,            0 },
2576     { X86::VORPSZrrkz,            X86::VORPSZrmkz,            0 },
2577     { X86::VPACKSSDWZrrkz,        X86::VPACKSSDWZrmkz,        0 },
2578     { X86::VPACKSSWBZrrkz,        X86::VPACKSSWBZrmkz,        0 },
2579     { X86::VPACKUSDWZrrkz,        X86::VPACKUSDWZrmkz,        0 },
2580     { X86::VPACKUSWBZrrkz,        X86::VPACKUSWBZrmkz,        0 },
2581     { X86::VPADDBZrrkz,           X86::VPADDBZrmkz,           0 },
2582     { X86::VPADDDZrrkz,           X86::VPADDDZrmkz,           0 },
2583     { X86::VPADDQZrrkz,           X86::VPADDQZrmkz,           0 },
2584     { X86::VPADDSBZrrkz,          X86::VPADDSBZrmkz,          0 },
2585     { X86::VPADDSWZrrkz,          X86::VPADDSWZrmkz,          0 },
2586     { X86::VPADDUSBZrrkz,         X86::VPADDUSBZrmkz,         0 },
2587     { X86::VPADDUSWZrrkz,         X86::VPADDUSWZrmkz,         0 },
2588     { X86::VPADDWZrrkz,           X86::VPADDWZrmkz,           0 },
2589     { X86::VPALIGNRZrrikz,        X86::VPALIGNRZrmikz,        0 },
2590     { X86::VPANDDZrrkz,           X86::VPANDDZrmkz,           0 },
2591     { X86::VPANDNDZrrkz,          X86::VPANDNDZrmkz,          0 },
2592     { X86::VPANDNQZrrkz,          X86::VPANDNQZrmkz,          0 },
2593     { X86::VPANDQZrrkz,           X86::VPANDQZrmkz,           0 },
2594     { X86::VPAVGBZrrkz,           X86::VPAVGBZrmkz,           0 },
2595     { X86::VPAVGWZrrkz,           X86::VPAVGWZrmkz,           0 },
2596     { X86::VPERMBZrrkz,           X86::VPERMBZrmkz,           0 },
2597     { X86::VPERMDZrrkz,           X86::VPERMDZrmkz,           0 },
2598     { X86::VPERMILPDZrrkz,        X86::VPERMILPDZrmkz,        0 },
2599     { X86::VPERMILPSZrrkz,        X86::VPERMILPSZrmkz,        0 },
2600     { X86::VPERMPDZrrkz,          X86::VPERMPDZrmkz,          0 },
2601     { X86::VPERMPSZrrkz,          X86::VPERMPSZrmkz,          0 },
2602     { X86::VPERMQZrrkz,           X86::VPERMQZrmkz,           0 },
2603     { X86::VPERMWZrrkz,           X86::VPERMWZrmkz,           0 },
2604     { X86::VPMADDUBSWZrrkz,       X86::VPMADDUBSWZrmkz,       0 },
2605     { X86::VPMADDWDZrrkz,         X86::VPMADDWDZrmkz,         0 },
2606     { X86::VPMAXSBZrrkz,          X86::VPMAXSBZrmkz,          0 },
2607     { X86::VPMAXSDZrrkz,          X86::VPMAXSDZrmkz,          0 },
2608     { X86::VPMAXSQZrrkz,          X86::VPMAXSQZrmkz,          0 },
2609     { X86::VPMAXSWZrrkz,          X86::VPMAXSWZrmkz,          0 },
2610     { X86::VPMAXUBZrrkz,          X86::VPMAXUBZrmkz,          0 },
2611     { X86::VPMAXUDZrrkz,          X86::VPMAXUDZrmkz,          0 },
2612     { X86::VPMAXUQZrrkz,          X86::VPMAXUQZrmkz,          0 },
2613     { X86::VPMAXUWZrrkz,          X86::VPMAXUWZrmkz,          0 },
2614     { X86::VPMINSBZrrkz,          X86::VPMINSBZrmkz,          0 },
2615     { X86::VPMINSDZrrkz,          X86::VPMINSDZrmkz,          0 },
2616     { X86::VPMINSQZrrkz,          X86::VPMINSQZrmkz,          0 },
2617     { X86::VPMINSWZrrkz,          X86::VPMINSWZrmkz,          0 },
2618     { X86::VPMINUBZrrkz,          X86::VPMINUBZrmkz,          0 },
2619     { X86::VPMINUDZrrkz,          X86::VPMINUDZrmkz,          0 },
2620     { X86::VPMINUQZrrkz,          X86::VPMINUQZrmkz,          0 },
2621     { X86::VPMINUWZrrkz,          X86::VPMINUWZrmkz,          0 },
2622     { X86::VPMULLDZrrkz,          X86::VPMULLDZrmkz,          0 },
2623     { X86::VPMULLQZrrkz,          X86::VPMULLQZrmkz,          0 },
2624     { X86::VPMULLWZrrkz,          X86::VPMULLWZrmkz,          0 },
2625     { X86::VPMULDQZrrkz,          X86::VPMULDQZrmkz,          0 },
2626     { X86::VPMULUDQZrrkz,         X86::VPMULUDQZrmkz,         0 },
2627     { X86::VPORDZrrkz,            X86::VPORDZrmkz,            0 },
2628     { X86::VPORQZrrkz,            X86::VPORQZrmkz,            0 },
2629     { X86::VPSHUFBZrrkz,          X86::VPSHUFBZrmkz,          0 },
2630     { X86::VPSLLDZrrkz,           X86::VPSLLDZrmkz,           0 },
2631     { X86::VPSLLQZrrkz,           X86::VPSLLQZrmkz,           0 },
2632     { X86::VPSLLVDZrrkz,          X86::VPSLLVDZrmkz,          0 },
2633     { X86::VPSLLVQZrrkz,          X86::VPSLLVQZrmkz,          0 },
2634     { X86::VPSLLVWZrrkz,          X86::VPSLLVWZrmkz,          0 },
2635     { X86::VPSLLWZrrkz,           X86::VPSLLWZrmkz,           0 },
2636     { X86::VPSRADZrrkz,           X86::VPSRADZrmkz,           0 },
2637     { X86::VPSRAQZrrkz,           X86::VPSRAQZrmkz,           0 },
2638     { X86::VPSRAVDZrrkz,          X86::VPSRAVDZrmkz,          0 },
2639     { X86::VPSRAVQZrrkz,          X86::VPSRAVQZrmkz,          0 },
2640     { X86::VPSRAVWZrrkz,          X86::VPSRAVWZrmkz,          0 },
2641     { X86::VPSRAWZrrkz,           X86::VPSRAWZrmkz,           0 },
2642     { X86::VPSRLDZrrkz,           X86::VPSRLDZrmkz,           0 },
2643     { X86::VPSRLQZrrkz,           X86::VPSRLQZrmkz,           0 },
2644     { X86::VPSRLVDZrrkz,          X86::VPSRLVDZrmkz,          0 },
2645     { X86::VPSRLVQZrrkz,          X86::VPSRLVQZrmkz,          0 },
2646     { X86::VPSRLVWZrrkz,          X86::VPSRLVWZrmkz,          0 },
2647     { X86::VPSRLWZrrkz,           X86::VPSRLWZrmkz,           0 },
2648     { X86::VPSUBBZrrkz,           X86::VPSUBBZrmkz,           0 },
2649     { X86::VPSUBDZrrkz,           X86::VPSUBDZrmkz,           0 },
2650     { X86::VPSUBQZrrkz,           X86::VPSUBQZrmkz,           0 },
2651     { X86::VPSUBSBZrrkz,          X86::VPSUBSBZrmkz,          0 },
2652     { X86::VPSUBSWZrrkz,          X86::VPSUBSWZrmkz,          0 },
2653     { X86::VPSUBUSBZrrkz,         X86::VPSUBUSBZrmkz,         0 },
2654     { X86::VPSUBUSWZrrkz,         X86::VPSUBUSWZrmkz,         0 },
2655     { X86::VPSUBWZrrkz,           X86::VPSUBWZrmkz,           0 },
2656     { X86::VPUNPCKHBWZrrkz,       X86::VPUNPCKHBWZrmkz,       0 },
2657     { X86::VPUNPCKHDQZrrkz,       X86::VPUNPCKHDQZrmkz,       0 },
2658     { X86::VPUNPCKHQDQZrrkz,      X86::VPUNPCKHQDQZrmkz,      0 },
2659     { X86::VPUNPCKHWDZrrkz,       X86::VPUNPCKHWDZrmkz,       0 },
2660     { X86::VPUNPCKLBWZrrkz,       X86::VPUNPCKLBWZrmkz,       0 },
2661     { X86::VPUNPCKLDQZrrkz,       X86::VPUNPCKLDQZrmkz,       0 },
2662     { X86::VPUNPCKLQDQZrrkz,      X86::VPUNPCKLQDQZrmkz,      0 },
2663     { X86::VPUNPCKLWDZrrkz,       X86::VPUNPCKLWDZrmkz,       0 },
2664     { X86::VPXORDZrrkz,           X86::VPXORDZrmkz,           0 },
2665     { X86::VPXORQZrrkz,           X86::VPXORQZrmkz,           0 },
2666     { X86::VSHUFPDZrrikz,         X86::VSHUFPDZrmikz,         0 },
2667     { X86::VSHUFPSZrrikz,         X86::VSHUFPSZrmikz,         0 },
2668     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
2669     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
2670     { X86::VSUBSDZrr_Intkz,       X86::VSUBSDZrm_Intkz,       TB_NO_REVERSE },
2671     { X86::VSUBSSZrr_Intkz,       X86::VSUBSSZrm_Intkz,       TB_NO_REVERSE },
2672     { X86::VUNPCKHPDZrrkz,        X86::VUNPCKHPDZrmkz,        0 },
2673     { X86::VUNPCKHPSZrrkz,        X86::VUNPCKHPSZrmkz,        0 },
2674     { X86::VUNPCKLPDZrrkz,        X86::VUNPCKLPDZrmkz,        0 },
2675     { X86::VUNPCKLPSZrrkz,        X86::VUNPCKLPSZrmkz,        0 },
2676     { X86::VXORPDZrrkz,           X86::VXORPDZrmkz,           0 },
2677     { X86::VXORPSZrrkz,           X86::VXORPSZrmkz,           0 },
2678 
2679     // AVX-512{F,VL} masked arithmetic instructions 256-bit
2680     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
2681     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
2682     { X86::VALIGNDZ256rrikz,      X86::VALIGNDZ256rmikz,      0 },
2683     { X86::VALIGNQZ256rrikz,      X86::VALIGNQZ256rmikz,      0 },
2684     { X86::VANDNPDZ256rrkz,       X86::VANDNPDZ256rmkz,       0 },
2685     { X86::VANDNPSZ256rrkz,       X86::VANDNPSZ256rmkz,       0 },
2686     { X86::VANDPDZ256rrkz,        X86::VANDPDZ256rmkz,        0 },
2687     { X86::VANDPSZ256rrkz,        X86::VANDPSZ256rmkz,        0 },
2688     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
2689     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
2690     { X86::VINSERTF32x4Z256rrkz,  X86::VINSERTF32x4Z256rmkz,  0 },
2691     { X86::VINSERTF64x2Z256rrkz,  X86::VINSERTF64x2Z256rmkz,  0 },
2692     { X86::VINSERTI32x4Z256rrkz,  X86::VINSERTI32x4Z256rmkz,  0 },
2693     { X86::VINSERTI64x2Z256rrkz,  X86::VINSERTI64x2Z256rmkz,  0 },
2694     { X86::VMAXCPDZ256rrkz,       X86::VMAXCPDZ256rmkz,       0 },
2695     { X86::VMAXCPSZ256rrkz,       X86::VMAXCPSZ256rmkz,       0 },
2696     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
2697     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
2698     { X86::VMINCPDZ256rrkz,       X86::VMINCPDZ256rmkz,       0 },
2699     { X86::VMINCPSZ256rrkz,       X86::VMINCPSZ256rmkz,       0 },
2700     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
2701     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
2702     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
2703     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
2704     { X86::VORPDZ256rrkz,         X86::VORPDZ256rmkz,         0 },
2705     { X86::VORPSZ256rrkz,         X86::VORPSZ256rmkz,         0 },
2706     { X86::VPACKSSDWZ256rrkz,     X86::VPACKSSDWZ256rmkz,     0 },
2707     { X86::VPACKSSWBZ256rrkz,     X86::VPACKSSWBZ256rmkz,     0 },
2708     { X86::VPACKUSDWZ256rrkz,     X86::VPACKUSDWZ256rmkz,     0 },
2709     { X86::VPACKUSWBZ256rrkz,     X86::VPACKUSWBZ256rmkz,     0 },
2710     { X86::VPADDBZ256rrkz,        X86::VPADDBZ256rmkz,        0 },
2711     { X86::VPADDDZ256rrkz,        X86::VPADDDZ256rmkz,        0 },
2712     { X86::VPADDQZ256rrkz,        X86::VPADDQZ256rmkz,        0 },
2713     { X86::VPADDSBZ256rrkz,       X86::VPADDSBZ256rmkz,       0 },
2714     { X86::VPADDSWZ256rrkz,       X86::VPADDSWZ256rmkz,       0 },
2715     { X86::VPADDUSBZ256rrkz,      X86::VPADDUSBZ256rmkz,      0 },
2716     { X86::VPADDUSWZ256rrkz,      X86::VPADDUSWZ256rmkz,      0 },
2717     { X86::VPADDWZ256rrkz,        X86::VPADDWZ256rmkz,        0 },
2718     { X86::VPALIGNRZ256rrikz,     X86::VPALIGNRZ256rmikz,     0 },
2719     { X86::VPANDDZ256rrkz,        X86::VPANDDZ256rmkz,        0 },
2720     { X86::VPANDNDZ256rrkz,       X86::VPANDNDZ256rmkz,       0 },
2721     { X86::VPANDNQZ256rrkz,       X86::VPANDNQZ256rmkz,       0 },
2722     { X86::VPANDQZ256rrkz,        X86::VPANDQZ256rmkz,        0 },
2723     { X86::VPAVGBZ256rrkz,        X86::VPAVGBZ256rmkz,        0 },
2724     { X86::VPAVGWZ256rrkz,        X86::VPAVGWZ256rmkz,        0 },
2725     { X86::VPERMBZ256rrkz,        X86::VPERMBZ256rmkz,        0 },
2726     { X86::VPERMDZ256rrkz,        X86::VPERMDZ256rmkz,        0 },
2727     { X86::VPERMILPDZ256rrkz,     X86::VPERMILPDZ256rmkz,     0 },
2728     { X86::VPERMILPSZ256rrkz,     X86::VPERMILPSZ256rmkz,     0 },
2729     { X86::VPERMPDZ256rrkz,       X86::VPERMPDZ256rmkz,       0 },
2730     { X86::VPERMPSZ256rrkz,       X86::VPERMPSZ256rmkz,       0 },
2731     { X86::VPERMQZ256rrkz,        X86::VPERMQZ256rmkz,        0 },
2732     { X86::VPERMWZ256rrkz,        X86::VPERMWZ256rmkz,        0 },
2733     { X86::VPMADDUBSWZ256rrkz,    X86::VPMADDUBSWZ256rmkz,    0 },
2734     { X86::VPMADDWDZ256rrkz,      X86::VPMADDWDZ256rmkz,      0 },
2735     { X86::VPMAXSBZ256rrkz,       X86::VPMAXSBZ256rmkz,       0 },
2736     { X86::VPMAXSDZ256rrkz,       X86::VPMAXSDZ256rmkz,       0 },
2737     { X86::VPMAXSQZ256rrkz,       X86::VPMAXSQZ256rmkz,       0 },
2738     { X86::VPMAXSWZ256rrkz,       X86::VPMAXSWZ256rmkz,       0 },
2739     { X86::VPMAXUBZ256rrkz,       X86::VPMAXUBZ256rmkz,       0 },
2740     { X86::VPMAXUDZ256rrkz,       X86::VPMAXUDZ256rmkz,       0 },
2741     { X86::VPMAXUQZ256rrkz,       X86::VPMAXUQZ256rmkz,       0 },
2742     { X86::VPMAXUWZ256rrkz,       X86::VPMAXUWZ256rmkz,       0 },
2743     { X86::VPMINSBZ256rrkz,       X86::VPMINSBZ256rmkz,       0 },
2744     { X86::VPMINSDZ256rrkz,       X86::VPMINSDZ256rmkz,       0 },
2745     { X86::VPMINSQZ256rrkz,       X86::VPMINSQZ256rmkz,       0 },
2746     { X86::VPMINSWZ256rrkz,       X86::VPMINSWZ256rmkz,       0 },
2747     { X86::VPMINUBZ256rrkz,       X86::VPMINUBZ256rmkz,       0 },
2748     { X86::VPMINUDZ256rrkz,       X86::VPMINUDZ256rmkz,       0 },
2749     { X86::VPMINUQZ256rrkz,       X86::VPMINUQZ256rmkz,       0 },
2750     { X86::VPMINUWZ256rrkz,       X86::VPMINUWZ256rmkz,       0 },
2751     { X86::VPMULDQZ256rrkz,       X86::VPMULDQZ256rmkz,       0 },
2752     { X86::VPMULLDZ256rrkz,       X86::VPMULLDZ256rmkz,       0 },
2753     { X86::VPMULLQZ256rrkz,       X86::VPMULLQZ256rmkz,       0 },
2754     { X86::VPMULLWZ256rrkz,       X86::VPMULLWZ256rmkz,       0 },
2755     { X86::VPMULUDQZ256rrkz,      X86::VPMULUDQZ256rmkz,      0 },
2756     { X86::VPORDZ256rrkz,         X86::VPORDZ256rmkz,         0 },
2757     { X86::VPORQZ256rrkz,         X86::VPORQZ256rmkz,         0 },
2758     { X86::VPSHUFBZ256rrkz,       X86::VPSHUFBZ256rmkz,       0 },
2759     { X86::VPSLLDZ256rrkz,        X86::VPSLLDZ256rmkz,        0 },
2760     { X86::VPSLLQZ256rrkz,        X86::VPSLLQZ256rmkz,        0 },
2761     { X86::VPSLLVDZ256rrkz,       X86::VPSLLVDZ256rmkz,       0 },
2762     { X86::VPSLLVQZ256rrkz,       X86::VPSLLVQZ256rmkz,       0 },
2763     { X86::VPSLLVWZ256rrkz,       X86::VPSLLVWZ256rmkz,       0 },
2764     { X86::VPSLLWZ256rrkz,        X86::VPSLLWZ256rmkz,        0 },
2765     { X86::VPSRADZ256rrkz,        X86::VPSRADZ256rmkz,        0 },
2766     { X86::VPSRAQZ256rrkz,        X86::VPSRAQZ256rmkz,        0 },
2767     { X86::VPSRAVDZ256rrkz,       X86::VPSRAVDZ256rmkz,       0 },
2768     { X86::VPSRAVQZ256rrkz,       X86::VPSRAVQZ256rmkz,       0 },
2769     { X86::VPSRAVWZ256rrkz,       X86::VPSRAVWZ256rmkz,       0 },
2770     { X86::VPSRAWZ256rrkz,        X86::VPSRAWZ256rmkz,        0 },
2771     { X86::VPSRLDZ256rrkz,        X86::VPSRLDZ256rmkz,        0 },
2772     { X86::VPSRLQZ256rrkz,        X86::VPSRLQZ256rmkz,        0 },
2773     { X86::VPSRLVDZ256rrkz,       X86::VPSRLVDZ256rmkz,       0 },
2774     { X86::VPSRLVQZ256rrkz,       X86::VPSRLVQZ256rmkz,       0 },
2775     { X86::VPSRLVWZ256rrkz,       X86::VPSRLVWZ256rmkz,       0 },
2776     { X86::VPSRLWZ256rrkz,        X86::VPSRLWZ256rmkz,        0 },
2777     { X86::VPSUBBZ256rrkz,        X86::VPSUBBZ256rmkz,        0 },
2778     { X86::VPSUBDZ256rrkz,        X86::VPSUBDZ256rmkz,        0 },
2779     { X86::VPSUBQZ256rrkz,        X86::VPSUBQZ256rmkz,        0 },
2780     { X86::VPSUBSBZ256rrkz,       X86::VPSUBSBZ256rmkz,       0 },
2781     { X86::VPSUBSWZ256rrkz,       X86::VPSUBSWZ256rmkz,       0 },
2782     { X86::VPSUBUSBZ256rrkz,      X86::VPSUBUSBZ256rmkz,      0 },
2783     { X86::VPSUBUSWZ256rrkz,      X86::VPSUBUSWZ256rmkz,      0 },
2784     { X86::VPSUBWZ256rrkz,        X86::VPSUBWZ256rmkz,        0 },
2785     { X86::VPUNPCKHBWZ256rrkz,    X86::VPUNPCKHBWZ256rmkz,    0 },
2786     { X86::VPUNPCKHDQZ256rrkz,    X86::VPUNPCKHDQZ256rmkz,    0 },
2787     { X86::VPUNPCKHQDQZ256rrkz,   X86::VPUNPCKHQDQZ256rmkz,   0 },
2788     { X86::VPUNPCKHWDZ256rrkz,    X86::VPUNPCKHWDZ256rmkz,    0 },
2789     { X86::VPUNPCKLBWZ256rrkz,    X86::VPUNPCKLBWZ256rmkz,    0 },
2790     { X86::VPUNPCKLDQZ256rrkz,    X86::VPUNPCKLDQZ256rmkz,    0 },
2791     { X86::VPUNPCKLQDQZ256rrkz,   X86::VPUNPCKLQDQZ256rmkz,   0 },
2792     { X86::VPUNPCKLWDZ256rrkz,    X86::VPUNPCKLWDZ256rmkz,    0 },
2793     { X86::VPXORDZ256rrkz,        X86::VPXORDZ256rmkz,        0 },
2794     { X86::VPXORQZ256rrkz,        X86::VPXORQZ256rmkz,        0 },
2795     { X86::VSHUFPDZ256rrikz,      X86::VSHUFPDZ256rmikz,      0 },
2796     { X86::VSHUFPSZ256rrikz,      X86::VSHUFPSZ256rmikz,      0 },
2797     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
2798     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
2799     { X86::VUNPCKHPDZ256rrkz,     X86::VUNPCKHPDZ256rmkz,     0 },
2800     { X86::VUNPCKHPSZ256rrkz,     X86::VUNPCKHPSZ256rmkz,     0 },
2801     { X86::VUNPCKLPDZ256rrkz,     X86::VUNPCKLPDZ256rmkz,     0 },
2802     { X86::VUNPCKLPSZ256rrkz,     X86::VUNPCKLPSZ256rmkz,     0 },
2803     { X86::VXORPDZ256rrkz,        X86::VXORPDZ256rmkz,        0 },
2804     { X86::VXORPSZ256rrkz,        X86::VXORPSZ256rmkz,        0 },
2805 
2806     // AVX-512{F,VL} masked arithmetic instructions 128-bit
2807     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
2808     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
2809     { X86::VALIGNDZ128rrikz,      X86::VALIGNDZ128rmikz,      0 },
2810     { X86::VALIGNQZ128rrikz,      X86::VALIGNQZ128rmikz,      0 },
2811     { X86::VANDNPDZ128rrkz,       X86::VANDNPDZ128rmkz,       0 },
2812     { X86::VANDNPSZ128rrkz,       X86::VANDNPSZ128rmkz,       0 },
2813     { X86::VANDPDZ128rrkz,        X86::VANDPDZ128rmkz,        0 },
2814     { X86::VANDPSZ128rrkz,        X86::VANDPSZ128rmkz,        0 },
2815     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
2816     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
2817     { X86::VMAXCPDZ128rrkz,       X86::VMAXCPDZ128rmkz,       0 },
2818     { X86::VMAXCPSZ128rrkz,       X86::VMAXCPSZ128rmkz,       0 },
2819     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 },
2820     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
2821     { X86::VMINCPDZ128rrkz,       X86::VMINCPDZ128rmkz,       0 },
2822     { X86::VMINCPSZ128rrkz,       X86::VMINCPSZ128rmkz,       0 },
2823     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
2824     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
2825     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
2826     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
2827     { X86::VORPDZ128rrkz,         X86::VORPDZ128rmkz,         0 },
2828     { X86::VORPSZ128rrkz,         X86::VORPSZ128rmkz,         0 },
2829     { X86::VPACKSSDWZ128rrkz,     X86::VPACKSSDWZ128rmkz,     0 },
2830     { X86::VPACKSSWBZ128rrkz,     X86::VPACKSSWBZ128rmkz,     0 },
2831     { X86::VPACKUSDWZ128rrkz,     X86::VPACKUSDWZ128rmkz,     0 },
2832     { X86::VPACKUSWBZ128rrkz,     X86::VPACKUSWBZ128rmkz,     0 },
2833     { X86::VPADDBZ128rrkz,        X86::VPADDBZ128rmkz,        0 },
2834     { X86::VPADDDZ128rrkz,        X86::VPADDDZ128rmkz,        0 },
2835     { X86::VPADDQZ128rrkz,        X86::VPADDQZ128rmkz,        0 },
2836     { X86::VPADDSBZ128rrkz,       X86::VPADDSBZ128rmkz,       0 },
2837     { X86::VPADDSWZ128rrkz,       X86::VPADDSWZ128rmkz,       0 },
2838     { X86::VPADDUSBZ128rrkz,      X86::VPADDUSBZ128rmkz,      0 },
2839     { X86::VPADDUSWZ128rrkz,      X86::VPADDUSWZ128rmkz,      0 },
2840     { X86::VPADDWZ128rrkz,        X86::VPADDWZ128rmkz,        0 },
2841     { X86::VPALIGNRZ128rrikz,     X86::VPALIGNRZ128rmikz,     0 },
2842     { X86::VPANDDZ128rrkz,        X86::VPANDDZ128rmkz,        0 },
2843     { X86::VPANDNDZ128rrkz,       X86::VPANDNDZ128rmkz,       0 },
2844     { X86::VPANDNQZ128rrkz,       X86::VPANDNQZ128rmkz,       0 },
2845     { X86::VPANDQZ128rrkz,        X86::VPANDQZ128rmkz,        0 },
2846     { X86::VPAVGBZ128rrkz,        X86::VPAVGBZ128rmkz,        0 },
2847     { X86::VPAVGWZ128rrkz,        X86::VPAVGWZ128rmkz,        0 },
2848     { X86::VPERMBZ128rrkz,        X86::VPERMBZ128rmkz,        0 },
2849     { X86::VPERMILPDZ128rrkz,     X86::VPERMILPDZ128rmkz,     0 },
2850     { X86::VPERMILPSZ128rrkz,     X86::VPERMILPSZ128rmkz,     0 },
2851     { X86::VPERMWZ128rrkz,        X86::VPERMWZ128rmkz,        0 },
2852     { X86::VPMADDUBSWZ128rrkz,    X86::VPMADDUBSWZ128rmkz,    0 },
2853     { X86::VPMADDWDZ128rrkz,      X86::VPMADDWDZ128rmkz,      0 },
2854     { X86::VPMAXSBZ128rrkz,       X86::VPMAXSBZ128rmkz,       0 },
2855     { X86::VPMAXSDZ128rrkz,       X86::VPMAXSDZ128rmkz,       0 },
2856     { X86::VPMAXSQZ128rrkz,       X86::VPMAXSQZ128rmkz,       0 },
2857     { X86::VPMAXSWZ128rrkz,       X86::VPMAXSWZ128rmkz,       0 },
2858     { X86::VPMAXUBZ128rrkz,       X86::VPMAXUBZ128rmkz,       0 },
2859     { X86::VPMAXUDZ128rrkz,       X86::VPMAXUDZ128rmkz,       0 },
2860     { X86::VPMAXUQZ128rrkz,       X86::VPMAXUQZ128rmkz,       0 },
2861     { X86::VPMAXUWZ128rrkz,       X86::VPMAXUWZ128rmkz,       0 },
2862     { X86::VPMINSBZ128rrkz,       X86::VPMINSBZ128rmkz,       0 },
2863     { X86::VPMINSDZ128rrkz,       X86::VPMINSDZ128rmkz,       0 },
2864     { X86::VPMINSQZ128rrkz,       X86::VPMINSQZ128rmkz,       0 },
2865     { X86::VPMINSWZ128rrkz,       X86::VPMINSWZ128rmkz,       0 },
2866     { X86::VPMINUBZ128rrkz,       X86::VPMINUBZ128rmkz,       0 },
2867     { X86::VPMINUDZ128rrkz,       X86::VPMINUDZ128rmkz,       0 },
2868     { X86::VPMINUQZ128rrkz,       X86::VPMINUQZ128rmkz,       0 },
2869     { X86::VPMINUWZ128rrkz,       X86::VPMINUWZ128rmkz,       0 },
2870     { X86::VPMULDQZ128rrkz,       X86::VPMULDQZ128rmkz,       0 },
2871     { X86::VPMULLDZ128rrkz,       X86::VPMULLDZ128rmkz,       0 },
2872     { X86::VPMULLQZ128rrkz,       X86::VPMULLQZ128rmkz,       0 },
2873     { X86::VPMULLWZ128rrkz,       X86::VPMULLWZ128rmkz,       0 },
2874     { X86::VPMULUDQZ128rrkz,      X86::VPMULUDQZ128rmkz,      0 },
2875     { X86::VPORDZ128rrkz,         X86::VPORDZ128rmkz,         0 },
2876     { X86::VPORQZ128rrkz,         X86::VPORQZ128rmkz,         0 },
2877     { X86::VPSHUFBZ128rrkz,       X86::VPSHUFBZ128rmkz,       0 },
2878     { X86::VPSLLDZ128rrkz,        X86::VPSLLDZ128rmkz,        0 },
2879     { X86::VPSLLQZ128rrkz,        X86::VPSLLQZ128rmkz,        0 },
2880     { X86::VPSLLVDZ128rrkz,       X86::VPSLLVDZ128rmkz,       0 },
2881     { X86::VPSLLVQZ128rrkz,       X86::VPSLLVQZ128rmkz,       0 },
2882     { X86::VPSLLVWZ128rrkz,       X86::VPSLLVWZ128rmkz,       0 },
2883     { X86::VPSLLWZ128rrkz,        X86::VPSLLWZ128rmkz,        0 },
2884     { X86::VPSRADZ128rrkz,        X86::VPSRADZ128rmkz,        0 },
2885     { X86::VPSRAQZ128rrkz,        X86::VPSRAQZ128rmkz,        0 },
2886     { X86::VPSRAVDZ128rrkz,       X86::VPSRAVDZ128rmkz,       0 },
2887     { X86::VPSRAVQZ128rrkz,       X86::VPSRAVQZ128rmkz,       0 },
2888     { X86::VPSRAVWZ128rrkz,       X86::VPSRAVWZ128rmkz,       0 },
2889     { X86::VPSRAWZ128rrkz,        X86::VPSRAWZ128rmkz,        0 },
2890     { X86::VPSRLDZ128rrkz,        X86::VPSRLDZ128rmkz,        0 },
2891     { X86::VPSRLQZ128rrkz,        X86::VPSRLQZ128rmkz,        0 },
2892     { X86::VPSRLVDZ128rrkz,       X86::VPSRLVDZ128rmkz,       0 },
2893     { X86::VPSRLVQZ128rrkz,       X86::VPSRLVQZ128rmkz,       0 },
2894     { X86::VPSRLVWZ128rrkz,       X86::VPSRLVWZ128rmkz,       0 },
2895     { X86::VPSRLWZ128rrkz,        X86::VPSRLWZ128rmkz,        0 },
2896     { X86::VPSUBBZ128rrkz,        X86::VPSUBBZ128rmkz,        0 },
2897     { X86::VPSUBDZ128rrkz,        X86::VPSUBDZ128rmkz,        0 },
2898     { X86::VPSUBQZ128rrkz,        X86::VPSUBQZ128rmkz,        0 },
2899     { X86::VPSUBSBZ128rrkz,       X86::VPSUBSBZ128rmkz,       0 },
2900     { X86::VPSUBSWZ128rrkz,       X86::VPSUBSWZ128rmkz,       0 },
2901     { X86::VPSUBUSBZ128rrkz,      X86::VPSUBUSBZ128rmkz,      0 },
2902     { X86::VPSUBUSWZ128rrkz,      X86::VPSUBUSWZ128rmkz,      0 },
2903     { X86::VPSUBWZ128rrkz,        X86::VPSUBWZ128rmkz,        0 },
2904     { X86::VPUNPCKHBWZ128rrkz,    X86::VPUNPCKHBWZ128rmkz,    0 },
2905     { X86::VPUNPCKHDQZ128rrkz,    X86::VPUNPCKHDQZ128rmkz,    0 },
2906     { X86::VPUNPCKHQDQZ128rrkz,   X86::VPUNPCKHQDQZ128rmkz,   0 },
2907     { X86::VPUNPCKHWDZ128rrkz,    X86::VPUNPCKHWDZ128rmkz,    0 },
2908     { X86::VPUNPCKLBWZ128rrkz,    X86::VPUNPCKLBWZ128rmkz,    0 },
2909     { X86::VPUNPCKLDQZ128rrkz,    X86::VPUNPCKLDQZ128rmkz,    0 },
2910     { X86::VPUNPCKLQDQZ128rrkz,   X86::VPUNPCKLQDQZ128rmkz,   0 },
2911     { X86::VPUNPCKLWDZ128rrkz,    X86::VPUNPCKLWDZ128rmkz,    0 },
2912     { X86::VPXORDZ128rrkz,        X86::VPXORDZ128rmkz,        0 },
2913     { X86::VPXORQZ128rrkz,        X86::VPXORQZ128rmkz,        0 },
2914     { X86::VSHUFPDZ128rrikz,      X86::VSHUFPDZ128rmikz,      0 },
2915     { X86::VSHUFPSZ128rrikz,      X86::VSHUFPSZ128rmikz,      0 },
2916     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
2917     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
2918     { X86::VUNPCKHPDZ128rrkz,     X86::VUNPCKHPDZ128rmkz,     0 },
2919     { X86::VUNPCKHPSZ128rrkz,     X86::VUNPCKHPSZ128rmkz,     0 },
2920     { X86::VUNPCKLPDZ128rrkz,     X86::VUNPCKLPDZ128rmkz,     0 },
2921     { X86::VUNPCKLPSZ128rrkz,     X86::VUNPCKLPSZ128rmkz,     0 },
2922     { X86::VXORPDZ128rrkz,        X86::VXORPDZ128rmkz,        0 },
2923     { X86::VXORPSZ128rrkz,        X86::VXORPSZ128rmkz,        0 },
2924 
2925     // AVX-512 masked foldable instructions
2926     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
2927     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
2928     { X86::VPABSBZrrk,            X86::VPABSBZrmk,            0 },
2929     { X86::VPABSDZrrk,            X86::VPABSDZrmk,            0 },
2930     { X86::VPABSQZrrk,            X86::VPABSQZrmk,            0 },
2931     { X86::VPABSWZrrk,            X86::VPABSWZrmk,            0 },
2932     { X86::VPERMILPDZrik,         X86::VPERMILPDZmik,         0 },
2933     { X86::VPERMILPSZrik,         X86::VPERMILPSZmik,         0 },
2934     { X86::VPERMPDZrik,           X86::VPERMPDZmik,           0 },
2935     { X86::VPERMQZrik,            X86::VPERMQZmik,            0 },
2936     { X86::VPMOVSXBDZrrk,         X86::VPMOVSXBDZrmk,         0 },
2937     { X86::VPMOVSXBQZrrk,         X86::VPMOVSXBQZrmk,         TB_NO_REVERSE },
2938     { X86::VPMOVSXBWZrrk,         X86::VPMOVSXBWZrmk,         0 },
2939     { X86::VPMOVSXDQZrrk,         X86::VPMOVSXDQZrmk,         0 },
2940     { X86::VPMOVSXWDZrrk,         X86::VPMOVSXWDZrmk,         0 },
2941     { X86::VPMOVSXWQZrrk,         X86::VPMOVSXWQZrmk,         0 },
2942     { X86::VPMOVZXBDZrrk,         X86::VPMOVZXBDZrmk,         0 },
2943     { X86::VPMOVZXBQZrrk,         X86::VPMOVZXBQZrmk,         TB_NO_REVERSE },
2944     { X86::VPMOVZXBWZrrk,         X86::VPMOVZXBWZrmk,         0 },
2945     { X86::VPMOVZXDQZrrk,         X86::VPMOVZXDQZrmk,         0 },
2946     { X86::VPMOVZXWDZrrk,         X86::VPMOVZXWDZrmk,         0 },
2947     { X86::VPMOVZXWQZrrk,         X86::VPMOVZXWQZrmk,         0 },
2948     { X86::VPSHUFDZrik,           X86::VPSHUFDZmik,           0 },
2949     { X86::VPSHUFHWZrik,          X86::VPSHUFHWZmik,          0 },
2950     { X86::VPSHUFLWZrik,          X86::VPSHUFLWZmik,          0 },
2951     { X86::VPSLLDZrik,            X86::VPSLLDZmik,            0 },
2952     { X86::VPSLLQZrik,            X86::VPSLLQZmik,            0 },
2953     { X86::VPSLLWZrik,            X86::VPSLLWZmik,            0 },
2954     { X86::VPSRADZrik,            X86::VPSRADZmik,            0 },
2955     { X86::VPSRAQZrik,            X86::VPSRAQZmik,            0 },
2956     { X86::VPSRAWZrik,            X86::VPSRAWZmik,            0 },
2957     { X86::VPSRLDZrik,            X86::VPSRLDZmik,            0 },
2958     { X86::VPSRLQZrik,            X86::VPSRLQZmik,            0 },
2959     { X86::VPSRLWZrik,            X86::VPSRLWZmik,            0 },
2960 
2961     // AVX-512VL 256-bit masked foldable instructions
2962     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
2963     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
2964     { X86::VPABSBZ256rrk,         X86::VPABSBZ256rmk,         0 },
2965     { X86::VPABSDZ256rrk,         X86::VPABSDZ256rmk,         0 },
2966     { X86::VPABSQZ256rrk,         X86::VPABSQZ256rmk,         0 },
2967     { X86::VPABSWZ256rrk,         X86::VPABSWZ256rmk,         0 },
2968     { X86::VPERMILPDZ256rik,      X86::VPERMILPDZ256mik,      0 },
2969     { X86::VPERMILPSZ256rik,      X86::VPERMILPSZ256mik,      0 },
2970     { X86::VPERMPDZ256rik,        X86::VPERMPDZ256mik,        0 },
2971     { X86::VPERMQZ256rik,         X86::VPERMQZ256mik,         0 },
2972     { X86::VPMOVSXBDZ256rrk,      X86::VPMOVSXBDZ256rmk,      TB_NO_REVERSE },
2973     { X86::VPMOVSXBQZ256rrk,      X86::VPMOVSXBQZ256rmk,      TB_NO_REVERSE },
2974     { X86::VPMOVSXBWZ256rrk,      X86::VPMOVSXBWZ256rmk,      0 },
2975     { X86::VPMOVSXDQZ256rrk,      X86::VPMOVSXDQZ256rmk,      0 },
2976     { X86::VPMOVSXWDZ256rrk,      X86::VPMOVSXWDZ256rmk,      0 },
2977     { X86::VPMOVSXWQZ256rrk,      X86::VPMOVSXWQZ256rmk,      TB_NO_REVERSE },
2978     { X86::VPMOVZXBDZ256rrk,      X86::VPMOVZXBDZ256rmk,      TB_NO_REVERSE },
2979     { X86::VPMOVZXBQZ256rrk,      X86::VPMOVZXBQZ256rmk,      TB_NO_REVERSE },
2980     { X86::VPMOVZXBWZ256rrk,      X86::VPMOVZXBWZ256rmk,      0 },
2981     { X86::VPMOVZXDQZ256rrk,      X86::VPMOVZXDQZ256rmk,      0 },
2982     { X86::VPMOVZXWDZ256rrk,      X86::VPMOVZXWDZ256rmk,      0 },
2983     { X86::VPMOVZXWQZ256rrk,      X86::VPMOVZXWQZ256rmk,      TB_NO_REVERSE },
2984     { X86::VPSHUFDZ256rik,        X86::VPSHUFDZ256mik,        0 },
2985     { X86::VPSHUFHWZ256rik,       X86::VPSHUFHWZ256mik,       0 },
2986     { X86::VPSHUFLWZ256rik,       X86::VPSHUFLWZ256mik,       0 },
2987     { X86::VPSLLDZ256rik,         X86::VPSLLDZ256mik,         0 },
2988     { X86::VPSLLQZ256rik,         X86::VPSLLQZ256mik,         0 },
2989     { X86::VPSLLWZ256rik,         X86::VPSLLWZ256mik,         0 },
2990     { X86::VPSRADZ256rik,         X86::VPSRADZ256mik,         0 },
2991     { X86::VPSRAQZ256rik,         X86::VPSRAQZ256mik,         0 },
2992     { X86::VPSRAWZ256rik,         X86::VPSRAWZ256mik,         0 },
2993     { X86::VPSRLDZ256rik,         X86::VPSRLDZ256mik,         0 },
2994     { X86::VPSRLQZ256rik,         X86::VPSRLQZ256mik,         0 },
2995     { X86::VPSRLWZ256rik,         X86::VPSRLWZ256mik,         0 },
2996 
2997     // AVX-512VL 128-bit masked foldable instructions
2998     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
2999     { X86::VPABSBZ128rrk,         X86::VPABSBZ128rmk,         0 },
3000     { X86::VPABSDZ128rrk,         X86::VPABSDZ128rmk,         0 },
3001     { X86::VPABSQZ128rrk,         X86::VPABSQZ128rmk,         0 },
3002     { X86::VPABSWZ128rrk,         X86::VPABSWZ128rmk,         0 },
3003     { X86::VPERMILPDZ128rik,      X86::VPERMILPDZ128mik,      0 },
3004     { X86::VPERMILPSZ128rik,      X86::VPERMILPSZ128mik,      0 },
3005     { X86::VPMOVSXBDZ128rrk,      X86::VPMOVSXBDZ128rmk,      TB_NO_REVERSE },
3006     { X86::VPMOVSXBQZ128rrk,      X86::VPMOVSXBQZ128rmk,      TB_NO_REVERSE },
3007     { X86::VPMOVSXBWZ128rrk,      X86::VPMOVSXBWZ128rmk,      TB_NO_REVERSE },
3008     { X86::VPMOVSXDQZ128rrk,      X86::VPMOVSXDQZ128rmk,      TB_NO_REVERSE },
3009     { X86::VPMOVSXWDZ128rrk,      X86::VPMOVSXWDZ128rmk,      TB_NO_REVERSE },
3010     { X86::VPMOVSXWQZ128rrk,      X86::VPMOVSXWQZ128rmk,      TB_NO_REVERSE },
3011     { X86::VPMOVZXBDZ128rrk,      X86::VPMOVZXBDZ128rmk,      TB_NO_REVERSE },
3012     { X86::VPMOVZXBQZ128rrk,      X86::VPMOVZXBQZ128rmk,      TB_NO_REVERSE },
3013     { X86::VPMOVZXBWZ128rrk,      X86::VPMOVZXBWZ128rmk,      TB_NO_REVERSE },
3014     { X86::VPMOVZXDQZ128rrk,      X86::VPMOVZXDQZ128rmk,      TB_NO_REVERSE },
3015     { X86::VPMOVZXWDZ128rrk,      X86::VPMOVZXWDZ128rmk,      TB_NO_REVERSE },
3016     { X86::VPMOVZXWQZ128rrk,      X86::VPMOVZXWQZ128rmk,      TB_NO_REVERSE },
3017     { X86::VPSHUFDZ128rik,        X86::VPSHUFDZ128mik,        0 },
3018     { X86::VPSHUFHWZ128rik,       X86::VPSHUFHWZ128mik,       0 },
3019     { X86::VPSHUFLWZ128rik,       X86::VPSHUFLWZ128mik,       0 },
3020     { X86::VPSLLDZ128rik,         X86::VPSLLDZ128mik,         0 },
3021     { X86::VPSLLQZ128rik,         X86::VPSLLQZ128mik,         0 },
3022     { X86::VPSLLWZ128rik,         X86::VPSLLWZ128mik,         0 },
3023     { X86::VPSRADZ128rik,         X86::VPSRADZ128mik,         0 },
3024     { X86::VPSRAQZ128rik,         X86::VPSRAQZ128mik,         0 },
3025     { X86::VPSRAWZ128rik,         X86::VPSRAWZ128mik,         0 },
3026     { X86::VPSRLDZ128rik,         X86::VPSRLDZ128mik,         0 },
3027     { X86::VPSRLQZ128rik,         X86::VPSRLQZ128mik,         0 },
3028     { X86::VPSRLWZ128rik,         X86::VPSRLWZ128mik,         0 },
3029   };
3030 
3031   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
3032     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3033                   Entry.RegOp, Entry.MemOp,
3034                   // Index 3, folded load
3035                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
3036   }
3037   auto I = X86InstrFMA3Info::rm_begin();
3038   auto E = X86InstrFMA3Info::rm_end();
3039   for (; I != E; ++I) {
3040     if (!I.getGroup()->isKMasked()) {
3041       // Intrinsic forms need to pass TB_NO_REVERSE.
3042       if (I.getGroup()->isIntrinsic()) {
3043         AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3044                       I.getRegOpcode(), I.getMemOpcode(),
3045                       TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD | TB_NO_REVERSE);
3046       } else {
3047         AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
3048                       I.getRegOpcode(), I.getMemOpcode(),
3049                       TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD);
3050       }
3051     }
3052   }
3053 
3054   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
3055     // AVX-512 foldable masked instructions
3056     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
3057     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
3058     { X86::VADDSDZrr_Intk,     X86::VADDSDZrm_Intk,       TB_NO_REVERSE },
3059     { X86::VADDSSZrr_Intk,     X86::VADDSSZrm_Intk,       TB_NO_REVERSE },
3060     { X86::VALIGNDZrrik,       X86::VALIGNDZrmik,         0 },
3061     { X86::VALIGNQZrrik,       X86::VALIGNQZrmik,         0 },
3062     { X86::VANDNPDZrrk,        X86::VANDNPDZrmk,          0 },
3063     { X86::VANDNPSZrrk,        X86::VANDNPSZrmk,          0 },
3064     { X86::VANDPDZrrk,         X86::VANDPDZrmk,           0 },
3065     { X86::VANDPSZrrk,         X86::VANDPSZrmk,           0 },
3066     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
3067     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
3068     { X86::VDIVSDZrr_Intk,     X86::VDIVSDZrm_Intk,       TB_NO_REVERSE },
3069     { X86::VDIVSSZrr_Intk,     X86::VDIVSSZrm_Intk,       TB_NO_REVERSE },
3070     { X86::VINSERTF32x4Zrrk,   X86::VINSERTF32x4Zrmk,     0 },
3071     { X86::VINSERTF32x8Zrrk,   X86::VINSERTF32x8Zrmk,     0 },
3072     { X86::VINSERTF64x2Zrrk,   X86::VINSERTF64x2Zrmk,     0 },
3073     { X86::VINSERTF64x4Zrrk,   X86::VINSERTF64x4Zrmk,     0 },
3074     { X86::VINSERTI32x4Zrrk,   X86::VINSERTI32x4Zrmk,     0 },
3075     { X86::VINSERTI32x8Zrrk,   X86::VINSERTI32x8Zrmk,     0 },
3076     { X86::VINSERTI64x2Zrrk,   X86::VINSERTI64x2Zrmk,     0 },
3077     { X86::VINSERTI64x4Zrrk,   X86::VINSERTI64x4Zrmk,     0 },
3078     { X86::VMAXCPDZrrk,        X86::VMAXCPDZrmk,          0 },
3079     { X86::VMAXCPSZrrk,        X86::VMAXCPSZrmk,          0 },
3080     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
3081     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
3082     { X86::VMAXSDZrr_Intk,     X86::VMAXSDZrm_Intk,       0 },
3083     { X86::VMAXSSZrr_Intk,     X86::VMAXSSZrm_Intk,       0 },
3084     { X86::VMINCPDZrrk,        X86::VMINCPDZrmk,          0 },
3085     { X86::VMINCPSZrrk,        X86::VMINCPSZrmk,          0 },
3086     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
3087     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
3088     { X86::VMINSDZrr_Intk,     X86::VMINSDZrm_Intk,       0 },
3089     { X86::VMINSSZrr_Intk,     X86::VMINSSZrm_Intk,       0 },
3090     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
3091     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
3092     { X86::VMULSDZrr_Intk,     X86::VMULSDZrm_Intk,       TB_NO_REVERSE },
3093     { X86::VMULSSZrr_Intk,     X86::VMULSSZrm_Intk,       TB_NO_REVERSE },
3094     { X86::VORPDZrrk,          X86::VORPDZrmk,            0 },
3095     { X86::VORPSZrrk,          X86::VORPSZrmk,            0 },
3096     { X86::VPACKSSDWZrrk,      X86::VPACKSSDWZrmk,        0 },
3097     { X86::VPACKSSWBZrrk,      X86::VPACKSSWBZrmk,        0 },
3098     { X86::VPACKUSDWZrrk,      X86::VPACKUSDWZrmk,        0 },
3099     { X86::VPACKUSWBZrrk,      X86::VPACKUSWBZrmk,        0 },
3100     { X86::VPADDBZrrk,         X86::VPADDBZrmk,           0 },
3101     { X86::VPADDDZrrk,         X86::VPADDDZrmk,           0 },
3102     { X86::VPADDQZrrk,         X86::VPADDQZrmk,           0 },
3103     { X86::VPADDSBZrrk,        X86::VPADDSBZrmk,          0 },
3104     { X86::VPADDSWZrrk,        X86::VPADDSWZrmk,          0 },
3105     { X86::VPADDUSBZrrk,       X86::VPADDUSBZrmk,         0 },
3106     { X86::VPADDUSWZrrk,       X86::VPADDUSWZrmk,         0 },
3107     { X86::VPADDWZrrk,         X86::VPADDWZrmk,           0 },
3108     { X86::VPALIGNRZrrik,      X86::VPALIGNRZrmik,        0 },
3109     { X86::VPANDDZrrk,         X86::VPANDDZrmk,           0 },
3110     { X86::VPANDNDZrrk,        X86::VPANDNDZrmk,          0 },
3111     { X86::VPANDNQZrrk,        X86::VPANDNQZrmk,          0 },
3112     { X86::VPANDQZrrk,         X86::VPANDQZrmk,           0 },
3113     { X86::VPAVGBZrrk,         X86::VPAVGBZrmk,           0 },
3114     { X86::VPAVGWZrrk,         X86::VPAVGWZrmk,           0 },
3115     { X86::VPERMBZrrk,         X86::VPERMBZrmk,           0 },
3116     { X86::VPERMDZrrk,         X86::VPERMDZrmk,           0 },
3117     { X86::VPERMI2Brrk,        X86::VPERMI2Brmk,          0 },
3118     { X86::VPERMI2Drrk,        X86::VPERMI2Drmk,          0 },
3119     { X86::VPERMI2PSrrk,       X86::VPERMI2PSrmk,         0 },
3120     { X86::VPERMI2PDrrk,       X86::VPERMI2PDrmk,         0 },
3121     { X86::VPERMI2Qrrk,        X86::VPERMI2Qrmk,          0 },
3122     { X86::VPERMI2Wrrk,        X86::VPERMI2Wrmk,          0 },
3123     { X86::VPERMILPDZrrk,      X86::VPERMILPDZrmk,        0 },
3124     { X86::VPERMILPSZrrk,      X86::VPERMILPSZrmk,        0 },
3125     { X86::VPERMPDZrrk,        X86::VPERMPDZrmk,          0 },
3126     { X86::VPERMPSZrrk,        X86::VPERMPSZrmk,          0 },
3127     { X86::VPERMQZrrk,         X86::VPERMQZrmk,           0 },
3128     { X86::VPERMT2Brrk,        X86::VPERMT2Brmk,          0 },
3129     { X86::VPERMT2Drrk,        X86::VPERMT2Drmk,          0 },
3130     { X86::VPERMT2PSrrk,       X86::VPERMT2PSrmk,         0 },
3131     { X86::VPERMT2PDrrk,       X86::VPERMT2PDrmk,         0 },
3132     { X86::VPERMT2Qrrk,        X86::VPERMT2Qrmk,          0 },
3133     { X86::VPERMT2Wrrk,        X86::VPERMT2Wrmk,          0 },
3134     { X86::VPERMWZrrk,         X86::VPERMWZrmk,           0 },
3135     { X86::VPMADDUBSWZrrk,     X86::VPMADDUBSWZrmk,       0 },
3136     { X86::VPMADDWDZrrk,       X86::VPMADDWDZrmk,         0 },
3137     { X86::VPMAXSBZrrk,        X86::VPMAXSBZrmk,          0 },
3138     { X86::VPMAXSDZrrk,        X86::VPMAXSDZrmk,          0 },
3139     { X86::VPMAXSQZrrk,        X86::VPMAXSQZrmk,          0 },
3140     { X86::VPMAXSWZrrk,        X86::VPMAXSWZrmk,          0 },
3141     { X86::VPMAXUBZrrk,        X86::VPMAXUBZrmk,          0 },
3142     { X86::VPMAXUDZrrk,        X86::VPMAXUDZrmk,          0 },
3143     { X86::VPMAXUQZrrk,        X86::VPMAXUQZrmk,          0 },
3144     { X86::VPMAXUWZrrk,        X86::VPMAXUWZrmk,          0 },
3145     { X86::VPMINSBZrrk,        X86::VPMINSBZrmk,          0 },
3146     { X86::VPMINSDZrrk,        X86::VPMINSDZrmk,          0 },
3147     { X86::VPMINSQZrrk,        X86::VPMINSQZrmk,          0 },
3148     { X86::VPMINSWZrrk,        X86::VPMINSWZrmk,          0 },
3149     { X86::VPMINUBZrrk,        X86::VPMINUBZrmk,          0 },
3150     { X86::VPMINUDZrrk,        X86::VPMINUDZrmk,          0 },
3151     { X86::VPMINUQZrrk,        X86::VPMINUQZrmk,          0 },
3152     { X86::VPMINUWZrrk,        X86::VPMINUWZrmk,          0 },
3153     { X86::VPMULDQZrrk,        X86::VPMULDQZrmk,          0 },
3154     { X86::VPMULLDZrrk,        X86::VPMULLDZrmk,          0 },
3155     { X86::VPMULLQZrrk,        X86::VPMULLQZrmk,          0 },
3156     { X86::VPMULLWZrrk,        X86::VPMULLWZrmk,          0 },
3157     { X86::VPMULUDQZrrk,       X86::VPMULUDQZrmk,         0 },
3158     { X86::VPORDZrrk,          X86::VPORDZrmk,            0 },
3159     { X86::VPORQZrrk,          X86::VPORQZrmk,            0 },
3160     { X86::VPSHUFBZrrk,        X86::VPSHUFBZrmk,          0 },
3161     { X86::VPSLLDZrrk,         X86::VPSLLDZrmk,           0 },
3162     { X86::VPSLLQZrrk,         X86::VPSLLQZrmk,           0 },
3163     { X86::VPSLLVDZrrk,        X86::VPSLLVDZrmk,          0 },
3164     { X86::VPSLLVQZrrk,        X86::VPSLLVQZrmk,          0 },
3165     { X86::VPSLLVWZrrk,        X86::VPSLLVWZrmk,          0 },
3166     { X86::VPSLLWZrrk,         X86::VPSLLWZrmk,           0 },
3167     { X86::VPSRADZrrk,         X86::VPSRADZrmk,           0 },
3168     { X86::VPSRAQZrrk,         X86::VPSRAQZrmk,           0 },
3169     { X86::VPSRAVDZrrk,        X86::VPSRAVDZrmk,          0 },
3170     { X86::VPSRAVQZrrk,        X86::VPSRAVQZrmk,          0 },
3171     { X86::VPSRAVWZrrk,        X86::VPSRAVWZrmk,          0 },
3172     { X86::VPSRAWZrrk,         X86::VPSRAWZrmk,           0 },
3173     { X86::VPSRLDZrrk,         X86::VPSRLDZrmk,           0 },
3174     { X86::VPSRLQZrrk,         X86::VPSRLQZrmk,           0 },
3175     { X86::VPSRLVDZrrk,        X86::VPSRLVDZrmk,          0 },
3176     { X86::VPSRLVQZrrk,        X86::VPSRLVQZrmk,          0 },
3177     { X86::VPSRLVWZrrk,        X86::VPSRLVWZrmk,          0 },
3178     { X86::VPSRLWZrrk,         X86::VPSRLWZrmk,           0 },
3179     { X86::VPSUBBZrrk,         X86::VPSUBBZrmk,           0 },
3180     { X86::VPSUBDZrrk,         X86::VPSUBDZrmk,           0 },
3181     { X86::VPSUBQZrrk,         X86::VPSUBQZrmk,           0 },
3182     { X86::VPSUBSBZrrk,        X86::VPSUBSBZrmk,          0 },
3183     { X86::VPSUBSWZrrk,        X86::VPSUBSWZrmk,          0 },
3184     { X86::VPSUBUSBZrrk,       X86::VPSUBUSBZrmk,         0 },
3185     { X86::VPSUBUSWZrrk,       X86::VPSUBUSWZrmk,         0 },
3186     { X86::VPTERNLOGDZrrik,    X86::VPTERNLOGDZrmik,      0 },
3187     { X86::VPTERNLOGQZrrik,    X86::VPTERNLOGQZrmik,      0 },
3188     { X86::VPUNPCKHBWZrrk,     X86::VPUNPCKHBWZrmk,       0 },
3189     { X86::VPUNPCKHDQZrrk,     X86::VPUNPCKHDQZrmk,       0 },
3190     { X86::VPUNPCKHQDQZrrk,    X86::VPUNPCKHQDQZrmk,      0 },
3191     { X86::VPUNPCKHWDZrrk,     X86::VPUNPCKHWDZrmk,       0 },
3192     { X86::VPUNPCKLBWZrrk,     X86::VPUNPCKLBWZrmk,       0 },
3193     { X86::VPUNPCKLDQZrrk,     X86::VPUNPCKLDQZrmk,       0 },
3194     { X86::VPUNPCKLQDQZrrk,    X86::VPUNPCKLQDQZrmk,      0 },
3195     { X86::VPUNPCKLWDZrrk,     X86::VPUNPCKLWDZrmk,       0 },
3196     { X86::VPXORDZrrk,         X86::VPXORDZrmk,           0 },
3197     { X86::VPXORQZrrk,         X86::VPXORQZrmk,           0 },
3198     { X86::VSHUFPDZrrik,       X86::VSHUFPDZrmik,         0 },
3199     { X86::VSHUFPSZrrik,       X86::VSHUFPSZrmik,         0 },
3200     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
3201     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
3202     { X86::VSUBSDZrr_Intk,     X86::VSUBSDZrm_Intk,       TB_NO_REVERSE },
3203     { X86::VSUBSSZrr_Intk,     X86::VSUBSSZrm_Intk,       TB_NO_REVERSE },
3204     { X86::VUNPCKHPDZrrk,      X86::VUNPCKHPDZrmk,        0 },
3205     { X86::VUNPCKHPSZrrk,      X86::VUNPCKHPSZrmk,        0 },
3206     { X86::VUNPCKLPDZrrk,      X86::VUNPCKLPDZrmk,        0 },
3207     { X86::VUNPCKLPSZrrk,      X86::VUNPCKLPSZrmk,        0 },
3208     { X86::VXORPDZrrk,         X86::VXORPDZrmk,           0 },
3209     { X86::VXORPSZrrk,         X86::VXORPSZrmk,           0 },
3210 
3211     // AVX-512{F,VL} foldable masked instructions 256-bit
3212     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
3213     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
3214     { X86::VALIGNDZ256rrik,    X86::VALIGNDZ256rmik,      0 },
3215     { X86::VALIGNQZ256rrik,    X86::VALIGNQZ256rmik,      0 },
3216     { X86::VANDNPDZ256rrk,     X86::VANDNPDZ256rmk,       0 },
3217     { X86::VANDNPSZ256rrk,     X86::VANDNPSZ256rmk,       0 },
3218     { X86::VANDPDZ256rrk,      X86::VANDPDZ256rmk,        0 },
3219     { X86::VANDPSZ256rrk,      X86::VANDPSZ256rmk,        0 },
3220     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
3221     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
3222     { X86::VINSERTF32x4Z256rrk,X86::VINSERTF32x4Z256rmk,  0 },
3223     { X86::VINSERTF64x2Z256rrk,X86::VINSERTF64x2Z256rmk,  0 },
3224     { X86::VINSERTI32x4Z256rrk,X86::VINSERTI32x4Z256rmk,  0 },
3225     { X86::VINSERTI64x2Z256rrk,X86::VINSERTI64x2Z256rmk,  0 },
3226     { X86::VMAXCPDZ256rrk,     X86::VMAXCPDZ256rmk,       0 },
3227     { X86::VMAXCPSZ256rrk,     X86::VMAXCPSZ256rmk,       0 },
3228     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
3229     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
3230     { X86::VMINCPDZ256rrk,     X86::VMINCPDZ256rmk,       0 },
3231     { X86::VMINCPSZ256rrk,     X86::VMINCPSZ256rmk,       0 },
3232     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
3233     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
3234     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
3235     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
3236     { X86::VORPDZ256rrk,       X86::VORPDZ256rmk,         0 },
3237     { X86::VORPSZ256rrk,       X86::VORPSZ256rmk,         0 },
3238     { X86::VPACKSSDWZ256rrk,   X86::VPACKSSDWZ256rmk,     0 },
3239     { X86::VPACKSSWBZ256rrk,   X86::VPACKSSWBZ256rmk,     0 },
3240     { X86::VPACKUSDWZ256rrk,   X86::VPACKUSDWZ256rmk,     0 },
3241     { X86::VPACKUSWBZ256rrk,   X86::VPACKUSWBZ256rmk,     0 },
3242     { X86::VPADDBZ256rrk,      X86::VPADDBZ256rmk,        0 },
3243     { X86::VPADDDZ256rrk,      X86::VPADDDZ256rmk,        0 },
3244     { X86::VPADDQZ256rrk,      X86::VPADDQZ256rmk,        0 },
3245     { X86::VPADDSBZ256rrk,     X86::VPADDSBZ256rmk,       0 },
3246     { X86::VPADDSWZ256rrk,     X86::VPADDSWZ256rmk,       0 },
3247     { X86::VPADDUSBZ256rrk,    X86::VPADDUSBZ256rmk,      0 },
3248     { X86::VPADDUSWZ256rrk,    X86::VPADDUSWZ256rmk,      0 },
3249     { X86::VPADDWZ256rrk,      X86::VPADDWZ256rmk,        0 },
3250     { X86::VPALIGNRZ256rrik,   X86::VPALIGNRZ256rmik,     0 },
3251     { X86::VPANDDZ256rrk,      X86::VPANDDZ256rmk,        0 },
3252     { X86::VPANDNDZ256rrk,     X86::VPANDNDZ256rmk,       0 },
3253     { X86::VPANDNQZ256rrk,     X86::VPANDNQZ256rmk,       0 },
3254     { X86::VPANDQZ256rrk,      X86::VPANDQZ256rmk,        0 },
3255     { X86::VPAVGBZ256rrk,      X86::VPAVGBZ256rmk,        0 },
3256     { X86::VPAVGWZ256rrk,      X86::VPAVGWZ256rmk,        0 },
3257     { X86::VPERMBZ256rrk,      X86::VPERMBZ256rmk,        0 },
3258     { X86::VPERMDZ256rrk,      X86::VPERMDZ256rmk,        0 },
3259     { X86::VPERMI2B256rrk,     X86::VPERMI2B256rmk,       0 },
3260     { X86::VPERMI2D256rrk,     X86::VPERMI2D256rmk,       0 },
3261     { X86::VPERMI2PD256rrk,    X86::VPERMI2PD256rmk,      0 },
3262     { X86::VPERMI2PS256rrk,    X86::VPERMI2PS256rmk,      0 },
3263     { X86::VPERMI2Q256rrk,     X86::VPERMI2Q256rmk,       0 },
3264     { X86::VPERMI2W256rrk,     X86::VPERMI2W256rmk,       0 },
3265     { X86::VPERMILPDZ256rrk,   X86::VPERMILPDZ256rmk,     0 },
3266     { X86::VPERMILPSZ256rrk,   X86::VPERMILPSZ256rmk,     0 },
3267     { X86::VPERMPDZ256rrk,     X86::VPERMPDZ256rmk,       0 },
3268     { X86::VPERMPSZ256rrk,     X86::VPERMPSZ256rmk,       0 },
3269     { X86::VPERMQZ256rrk,      X86::VPERMQZ256rmk,        0 },
3270     { X86::VPERMT2B256rrk,     X86::VPERMT2B256rmk,       0 },
3271     { X86::VPERMT2D256rrk,     X86::VPERMT2D256rmk,       0 },
3272     { X86::VPERMT2PD256rrk,    X86::VPERMT2PD256rmk,      0 },
3273     { X86::VPERMT2PS256rrk,    X86::VPERMT2PS256rmk,      0 },
3274     { X86::VPERMT2Q256rrk,     X86::VPERMT2Q256rmk,       0 },
3275     { X86::VPERMT2W256rrk,     X86::VPERMT2W256rmk,       0 },
3276     { X86::VPERMWZ256rrk,      X86::VPERMWZ256rmk,        0 },
3277     { X86::VPMADDUBSWZ256rrk,  X86::VPMADDUBSWZ256rmk,    0 },
3278     { X86::VPMADDWDZ256rrk,    X86::VPMADDWDZ256rmk,      0 },
3279     { X86::VPMAXSBZ256rrk,     X86::VPMAXSBZ256rmk,       0 },
3280     { X86::VPMAXSDZ256rrk,     X86::VPMAXSDZ256rmk,       0 },
3281     { X86::VPMAXSQZ256rrk,     X86::VPMAXSQZ256rmk,       0 },
3282     { X86::VPMAXSWZ256rrk,     X86::VPMAXSWZ256rmk,       0 },
3283     { X86::VPMAXUBZ256rrk,     X86::VPMAXUBZ256rmk,       0 },
3284     { X86::VPMAXUDZ256rrk,     X86::VPMAXUDZ256rmk,       0 },
3285     { X86::VPMAXUQZ256rrk,     X86::VPMAXUQZ256rmk,       0 },
3286     { X86::VPMAXUWZ256rrk,     X86::VPMAXUWZ256rmk,       0 },
3287     { X86::VPMINSBZ256rrk,     X86::VPMINSBZ256rmk,       0 },
3288     { X86::VPMINSDZ256rrk,     X86::VPMINSDZ256rmk,       0 },
3289     { X86::VPMINSQZ256rrk,     X86::VPMINSQZ256rmk,       0 },
3290     { X86::VPMINSWZ256rrk,     X86::VPMINSWZ256rmk,       0 },
3291     { X86::VPMINUBZ256rrk,     X86::VPMINUBZ256rmk,       0 },
3292     { X86::VPMINUDZ256rrk,     X86::VPMINUDZ256rmk,       0 },
3293     { X86::VPMINUQZ256rrk,     X86::VPMINUQZ256rmk,       0 },
3294     { X86::VPMINUWZ256rrk,     X86::VPMINUWZ256rmk,       0 },
3295     { X86::VPMULDQZ256rrk,     X86::VPMULDQZ256rmk,       0 },
3296     { X86::VPMULLDZ256rrk,     X86::VPMULLDZ256rmk,       0 },
3297     { X86::VPMULLQZ256rrk,     X86::VPMULLQZ256rmk,       0 },
3298     { X86::VPMULLWZ256rrk,     X86::VPMULLWZ256rmk,       0 },
3299     { X86::VPMULUDQZ256rrk,    X86::VPMULUDQZ256rmk,      0 },
3300     { X86::VPORDZ256rrk,       X86::VPORDZ256rmk,         0 },
3301     { X86::VPORQZ256rrk,       X86::VPORQZ256rmk,         0 },
3302     { X86::VPSHUFBZ256rrk,     X86::VPSHUFBZ256rmk,       0 },
3303     { X86::VPSLLDZ256rrk,      X86::VPSLLDZ256rmk,        0 },
3304     { X86::VPSLLQZ256rrk,      X86::VPSLLQZ256rmk,        0 },
3305     { X86::VPSLLVDZ256rrk,     X86::VPSLLVDZ256rmk,       0 },
3306     { X86::VPSLLVQZ256rrk,     X86::VPSLLVQZ256rmk,       0 },
3307     { X86::VPSLLVWZ256rrk,     X86::VPSLLVWZ256rmk,       0 },
3308     { X86::VPSLLWZ256rrk,      X86::VPSLLWZ256rmk,        0 },
3309     { X86::VPSRADZ256rrk,      X86::VPSRADZ256rmk,        0 },
3310     { X86::VPSRAQZ256rrk,      X86::VPSRAQZ256rmk,        0 },
3311     { X86::VPSRAVDZ256rrk,     X86::VPSRAVDZ256rmk,       0 },
3312     { X86::VPSRAVQZ256rrk,     X86::VPSRAVQZ256rmk,       0 },
3313     { X86::VPSRAVWZ256rrk,     X86::VPSRAVWZ256rmk,       0 },
3314     { X86::VPSRAWZ256rrk,      X86::VPSRAWZ256rmk,        0 },
3315     { X86::VPSRLDZ256rrk,      X86::VPSRLDZ256rmk,        0 },
3316     { X86::VPSRLQZ256rrk,      X86::VPSRLQZ256rmk,        0 },
3317     { X86::VPSRLVDZ256rrk,     X86::VPSRLVDZ256rmk,       0 },
3318     { X86::VPSRLVQZ256rrk,     X86::VPSRLVQZ256rmk,       0 },
3319     { X86::VPSRLVWZ256rrk,     X86::VPSRLVWZ256rmk,       0 },
3320     { X86::VPSRLWZ256rrk,      X86::VPSRLWZ256rmk,        0 },
3321     { X86::VPSUBBZ256rrk,      X86::VPSUBBZ256rmk,        0 },
3322     { X86::VPSUBDZ256rrk,      X86::VPSUBDZ256rmk,        0 },
3323     { X86::VPSUBQZ256rrk,      X86::VPSUBQZ256rmk,        0 },
3324     { X86::VPSUBSBZ256rrk,     X86::VPSUBSBZ256rmk,       0 },
3325     { X86::VPSUBSWZ256rrk,     X86::VPSUBSWZ256rmk,       0 },
3326     { X86::VPSUBUSBZ256rrk,    X86::VPSUBUSBZ256rmk,      0 },
3327     { X86::VPSUBUSWZ256rrk,    X86::VPSUBUSWZ256rmk,      0 },
3328     { X86::VPSUBWZ256rrk,      X86::VPSUBWZ256rmk,        0 },
3329     { X86::VPTERNLOGDZ256rrik, X86::VPTERNLOGDZ256rmik,   0 },
3330     { X86::VPTERNLOGQZ256rrik, X86::VPTERNLOGQZ256rmik,   0 },
3331     { X86::VPUNPCKHBWZ256rrk,  X86::VPUNPCKHBWZ256rmk,    0 },
3332     { X86::VPUNPCKHDQZ256rrk,  X86::VPUNPCKHDQZ256rmk,    0 },
3333     { X86::VPUNPCKHQDQZ256rrk, X86::VPUNPCKHQDQZ256rmk,   0 },
3334     { X86::VPUNPCKHWDZ256rrk,  X86::VPUNPCKHWDZ256rmk,    0 },
3335     { X86::VPUNPCKLBWZ256rrk,  X86::VPUNPCKLBWZ256rmk,    0 },
3336     { X86::VPUNPCKLDQZ256rrk,  X86::VPUNPCKLDQZ256rmk,    0 },
3337     { X86::VPUNPCKLQDQZ256rrk, X86::VPUNPCKLQDQZ256rmk,   0 },
3338     { X86::VPUNPCKLWDZ256rrk,  X86::VPUNPCKLWDZ256rmk,    0 },
3339     { X86::VPXORDZ256rrk,      X86::VPXORDZ256rmk,        0 },
3340     { X86::VPXORQZ256rrk,      X86::VPXORQZ256rmk,        0 },
3341     { X86::VSHUFPDZ256rrik,    X86::VSHUFPDZ256rmik,      0 },
3342     { X86::VSHUFPSZ256rrik,    X86::VSHUFPSZ256rmik,      0 },
3343     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
3344     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
3345     { X86::VUNPCKHPDZ256rrk,   X86::VUNPCKHPDZ256rmk,     0 },
3346     { X86::VUNPCKHPSZ256rrk,   X86::VUNPCKHPSZ256rmk,     0 },
3347     { X86::VUNPCKLPDZ256rrk,   X86::VUNPCKLPDZ256rmk,     0 },
3348     { X86::VUNPCKLPSZ256rrk,   X86::VUNPCKLPSZ256rmk,     0 },
3349     { X86::VXORPDZ256rrk,      X86::VXORPDZ256rmk,        0 },
3350     { X86::VXORPSZ256rrk,      X86::VXORPSZ256rmk,        0 },
3351 
3352     // AVX-512{F,VL} foldable instructions 128-bit
3353     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
3354     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
3355     { X86::VALIGNDZ128rrik,    X86::VALIGNDZ128rmik,      0 },
3356     { X86::VALIGNQZ128rrik,    X86::VALIGNQZ128rmik,      0 },
3357     { X86::VANDNPDZ128rrk,     X86::VANDNPDZ128rmk,       0 },
3358     { X86::VANDNPSZ128rrk,     X86::VANDNPSZ128rmk,       0 },
3359     { X86::VANDPDZ128rrk,      X86::VANDPDZ128rmk,        0 },
3360     { X86::VANDPSZ128rrk,      X86::VANDPSZ128rmk,        0 },
3361     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
3362     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
3363     { X86::VMAXCPDZ128rrk,     X86::VMAXCPDZ128rmk,       0 },
3364     { X86::VMAXCPSZ128rrk,     X86::VMAXCPSZ128rmk,       0 },
3365     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 },
3366     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
3367     { X86::VMINCPDZ128rrk,     X86::VMINCPDZ128rmk,       0 },
3368     { X86::VMINCPSZ128rrk,     X86::VMINCPSZ128rmk,       0 },
3369     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
3370     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
3371     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
3372     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
3373     { X86::VORPDZ128rrk,       X86::VORPDZ128rmk,         0 },
3374     { X86::VORPSZ128rrk,       X86::VORPSZ128rmk,         0 },
3375     { X86::VPACKSSDWZ128rrk,   X86::VPACKSSDWZ128rmk,     0 },
3376     { X86::VPACKSSWBZ128rrk,   X86::VPACKSSWBZ128rmk,     0 },
3377     { X86::VPACKUSDWZ128rrk,   X86::VPACKUSDWZ128rmk,     0 },
3378     { X86::VPACKUSWBZ128rrk,   X86::VPACKUSWBZ128rmk,     0 },
3379     { X86::VPADDBZ128rrk,      X86::VPADDBZ128rmk,        0 },
3380     { X86::VPADDDZ128rrk,      X86::VPADDDZ128rmk,        0 },
3381     { X86::VPADDQZ128rrk,      X86::VPADDQZ128rmk,        0 },
3382     { X86::VPADDSBZ128rrk,     X86::VPADDSBZ128rmk,       0 },
3383     { X86::VPADDSWZ128rrk,     X86::VPADDSWZ128rmk,       0 },
3384     { X86::VPADDUSBZ128rrk,    X86::VPADDUSBZ128rmk,      0 },
3385     { X86::VPADDUSWZ128rrk,    X86::VPADDUSWZ128rmk,      0 },
3386     { X86::VPADDWZ128rrk,      X86::VPADDWZ128rmk,        0 },
3387     { X86::VPALIGNRZ128rrik,   X86::VPALIGNRZ128rmik,     0 },
3388     { X86::VPANDDZ128rrk,      X86::VPANDDZ128rmk,        0 },
3389     { X86::VPANDNDZ128rrk,     X86::VPANDNDZ128rmk,       0 },
3390     { X86::VPANDNQZ128rrk,     X86::VPANDNQZ128rmk,       0 },
3391     { X86::VPANDQZ128rrk,      X86::VPANDQZ128rmk,        0 },
3392     { X86::VPAVGBZ128rrk,      X86::VPAVGBZ128rmk,        0 },
3393     { X86::VPAVGWZ128rrk,      X86::VPAVGWZ128rmk,        0 },
3394     { X86::VPERMBZ128rrk,      X86::VPERMBZ128rmk,        0 },
3395     { X86::VPERMI2B128rrk,     X86::VPERMI2B128rmk,       0 },
3396     { X86::VPERMI2D128rrk,     X86::VPERMI2D128rmk,       0 },
3397     { X86::VPERMI2PD128rrk,    X86::VPERMI2PD128rmk,      0 },
3398     { X86::VPERMI2PS128rrk,    X86::VPERMI2PS128rmk,      0 },
3399     { X86::VPERMI2Q128rrk,     X86::VPERMI2Q128rmk,       0 },
3400     { X86::VPERMI2W128rrk,     X86::VPERMI2W128rmk,       0 },
3401     { X86::VPERMILPDZ128rrk,   X86::VPERMILPDZ128rmk,     0 },
3402     { X86::VPERMILPSZ128rrk,   X86::VPERMILPSZ128rmk,     0 },
3403     { X86::VPERMT2B128rrk,     X86::VPERMT2B128rmk,       0 },
3404     { X86::VPERMT2D128rrk,     X86::VPERMT2D128rmk,       0 },
3405     { X86::VPERMT2PD128rrk,    X86::VPERMT2PD128rmk,      0 },
3406     { X86::VPERMT2PS128rrk,    X86::VPERMT2PS128rmk,      0 },
3407     { X86::VPERMT2Q128rrk,     X86::VPERMT2Q128rmk,       0 },
3408     { X86::VPERMT2W128rrk,     X86::VPERMT2W128rmk,       0 },
3409     { X86::VPERMWZ128rrk,      X86::VPERMWZ128rmk,        0 },
3410     { X86::VPMADDUBSWZ128rrk,  X86::VPMADDUBSWZ128rmk,    0 },
3411     { X86::VPMADDWDZ128rrk,    X86::VPMADDWDZ128rmk,      0 },
3412     { X86::VPMAXSBZ128rrk,     X86::VPMAXSBZ128rmk,       0 },
3413     { X86::VPMAXSDZ128rrk,     X86::VPMAXSDZ128rmk,       0 },
3414     { X86::VPMAXSQZ128rrk,     X86::VPMAXSQZ128rmk,       0 },
3415     { X86::VPMAXSWZ128rrk,     X86::VPMAXSWZ128rmk,       0 },
3416     { X86::VPMAXUBZ128rrk,     X86::VPMAXUBZ128rmk,       0 },
3417     { X86::VPMAXUDZ128rrk,     X86::VPMAXUDZ128rmk,       0 },
3418     { X86::VPMAXUQZ128rrk,     X86::VPMAXUQZ128rmk,       0 },
3419     { X86::VPMAXUWZ128rrk,     X86::VPMAXUWZ128rmk,       0 },
3420     { X86::VPMINSBZ128rrk,     X86::VPMINSBZ128rmk,       0 },
3421     { X86::VPMINSDZ128rrk,     X86::VPMINSDZ128rmk,       0 },
3422     { X86::VPMINSQZ128rrk,     X86::VPMINSQZ128rmk,       0 },
3423     { X86::VPMINSWZ128rrk,     X86::VPMINSWZ128rmk,       0 },
3424     { X86::VPMINUBZ128rrk,     X86::VPMINUBZ128rmk,       0 },
3425     { X86::VPMINUDZ128rrk,     X86::VPMINUDZ128rmk,       0 },
3426     { X86::VPMINUQZ128rrk,     X86::VPMINUQZ128rmk,       0 },
3427     { X86::VPMINUWZ128rrk,     X86::VPMINUWZ128rmk,       0 },
3428     { X86::VPMULDQZ128rrk,     X86::VPMULDQZ128rmk,       0 },
3429     { X86::VPMULLDZ128rrk,     X86::VPMULLDZ128rmk,       0 },
3430     { X86::VPMULLQZ128rrk,     X86::VPMULLQZ128rmk,       0 },
3431     { X86::VPMULLWZ128rrk,     X86::VPMULLWZ128rmk,       0 },
3432     { X86::VPMULUDQZ128rrk,    X86::VPMULUDQZ128rmk,      0 },
3433     { X86::VPORDZ128rrk,       X86::VPORDZ128rmk,         0 },
3434     { X86::VPORQZ128rrk,       X86::VPORQZ128rmk,         0 },
3435     { X86::VPSHUFBZ128rrk,     X86::VPSHUFBZ128rmk,       0 },
3436     { X86::VPSLLDZ128rrk,      X86::VPSLLDZ128rmk,        0 },
3437     { X86::VPSLLQZ128rrk,      X86::VPSLLQZ128rmk,        0 },
3438     { X86::VPSLLVDZ128rrk,     X86::VPSLLVDZ128rmk,       0 },
3439     { X86::VPSLLVQZ128rrk,     X86::VPSLLVQZ128rmk,       0 },
3440     { X86::VPSLLVWZ128rrk,     X86::VPSLLVWZ128rmk,       0 },
3441     { X86::VPSLLWZ128rrk,      X86::VPSLLWZ128rmk,        0 },
3442     { X86::VPSRADZ128rrk,      X86::VPSRADZ128rmk,        0 },
3443     { X86::VPSRAQZ128rrk,      X86::VPSRAQZ128rmk,        0 },
3444     { X86::VPSRAVDZ128rrk,     X86::VPSRAVDZ128rmk,       0 },
3445     { X86::VPSRAVQZ128rrk,     X86::VPSRAVQZ128rmk,       0 },
3446     { X86::VPSRAVWZ128rrk,     X86::VPSRAVWZ128rmk,       0 },
3447     { X86::VPSRAWZ128rrk,      X86::VPSRAWZ128rmk,        0 },
3448     { X86::VPSRLDZ128rrk,      X86::VPSRLDZ128rmk,        0 },
3449     { X86::VPSRLQZ128rrk,      X86::VPSRLQZ128rmk,        0 },
3450     { X86::VPSRLVDZ128rrk,     X86::VPSRLVDZ128rmk,       0 },
3451     { X86::VPSRLVQZ128rrk,     X86::VPSRLVQZ128rmk,       0 },
3452     { X86::VPSRLVWZ128rrk,     X86::VPSRLVWZ128rmk,       0 },
3453     { X86::VPSRLWZ128rrk,      X86::VPSRLWZ128rmk,        0 },
3454     { X86::VPSUBBZ128rrk,      X86::VPSUBBZ128rmk,        0 },
3455     { X86::VPSUBDZ128rrk,      X86::VPSUBDZ128rmk,        0 },
3456     { X86::VPSUBQZ128rrk,      X86::VPSUBQZ128rmk,        0 },
3457     { X86::VPSUBSBZ128rrk,     X86::VPSUBSBZ128rmk,       0 },
3458     { X86::VPSUBSWZ128rrk,     X86::VPSUBSWZ128rmk,       0 },
3459     { X86::VPSUBUSBZ128rrk,    X86::VPSUBUSBZ128rmk,      0 },
3460     { X86::VPSUBUSWZ128rrk,    X86::VPSUBUSWZ128rmk,      0 },
3461     { X86::VPSUBWZ128rrk,      X86::VPSUBWZ128rmk,        0 },
3462     { X86::VPTERNLOGDZ128rrik, X86::VPTERNLOGDZ128rmik,   0 },
3463     { X86::VPTERNLOGQZ128rrik, X86::VPTERNLOGQZ128rmik,   0 },
3464     { X86::VPUNPCKHBWZ128rrk,  X86::VPUNPCKHBWZ128rmk,    0 },
3465     { X86::VPUNPCKHDQZ128rrk,  X86::VPUNPCKHDQZ128rmk,    0 },
3466     { X86::VPUNPCKHQDQZ128rrk, X86::VPUNPCKHQDQZ128rmk,   0 },
3467     { X86::VPUNPCKHWDZ128rrk,  X86::VPUNPCKHWDZ128rmk,    0 },
3468     { X86::VPUNPCKLBWZ128rrk,  X86::VPUNPCKLBWZ128rmk,    0 },
3469     { X86::VPUNPCKLDQZ128rrk,  X86::VPUNPCKLDQZ128rmk,    0 },
3470     { X86::VPUNPCKLQDQZ128rrk, X86::VPUNPCKLQDQZ128rmk,   0 },
3471     { X86::VPUNPCKLWDZ128rrk,  X86::VPUNPCKLWDZ128rmk,    0 },
3472     { X86::VPXORDZ128rrk,      X86::VPXORDZ128rmk,        0 },
3473     { X86::VPXORQZ128rrk,      X86::VPXORQZ128rmk,        0 },
3474     { X86::VSHUFPDZ128rrik,    X86::VSHUFPDZ128rmik,      0 },
3475     { X86::VSHUFPSZ128rrik,    X86::VSHUFPSZ128rmik,      0 },
3476     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
3477     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
3478     { X86::VUNPCKHPDZ128rrk,   X86::VUNPCKHPDZ128rmk,     0 },
3479     { X86::VUNPCKHPSZ128rrk,   X86::VUNPCKHPSZ128rmk,     0 },
3480     { X86::VUNPCKLPDZ128rrk,   X86::VUNPCKLPDZ128rmk,     0 },
3481     { X86::VUNPCKLPSZ128rrk,   X86::VUNPCKLPSZ128rmk,     0 },
3482     { X86::VXORPDZ128rrk,      X86::VXORPDZ128rmk,        0 },
3483     { X86::VXORPSZ128rrk,      X86::VXORPSZ128rmk,        0 },
3484 
3485     // 512-bit three source instructions with zero masking.
3486     { X86::VPERMI2Brrkz,       X86::VPERMI2Brmkz,         0 },
3487     { X86::VPERMI2Drrkz,       X86::VPERMI2Drmkz,         0 },
3488     { X86::VPERMI2PSrrkz,      X86::VPERMI2PSrmkz,        0 },
3489     { X86::VPERMI2PDrrkz,      X86::VPERMI2PDrmkz,        0 },
3490     { X86::VPERMI2Qrrkz,       X86::VPERMI2Qrmkz,         0 },
3491     { X86::VPERMI2Wrrkz,       X86::VPERMI2Wrmkz,         0 },
3492     { X86::VPERMT2Brrkz,       X86::VPERMT2Brmkz,         0 },
3493     { X86::VPERMT2Drrkz,       X86::VPERMT2Drmkz,         0 },
3494     { X86::VPERMT2PSrrkz,      X86::VPERMT2PSrmkz,        0 },
3495     { X86::VPERMT2PDrrkz,      X86::VPERMT2PDrmkz,        0 },
3496     { X86::VPERMT2Qrrkz,       X86::VPERMT2Qrmkz,         0 },
3497     { X86::VPERMT2Wrrkz,       X86::VPERMT2Wrmkz,         0 },
3498     { X86::VPTERNLOGDZrrikz,   X86::VPTERNLOGDZrmikz,     0 },
3499     { X86::VPTERNLOGQZrrikz,   X86::VPTERNLOGQZrmikz,     0 },
3500 
3501     // 256-bit three source instructions with zero masking.
3502     { X86::VPERMI2B256rrkz,    X86::VPERMI2B256rmkz,      0 },
3503     { X86::VPERMI2D256rrkz,    X86::VPERMI2D256rmkz,      0 },
3504     { X86::VPERMI2PD256rrkz,   X86::VPERMI2PD256rmkz,     0 },
3505     { X86::VPERMI2PS256rrkz,   X86::VPERMI2PS256rmkz,     0 },
3506     { X86::VPERMI2Q256rrkz,    X86::VPERMI2Q256rmkz,      0 },
3507     { X86::VPERMI2W256rrkz,    X86::VPERMI2W256rmkz,      0 },
3508     { X86::VPERMT2B256rrkz,    X86::VPERMT2B256rmkz,      0 },
3509     { X86::VPERMT2D256rrkz,    X86::VPERMT2D256rmkz,      0 },
3510     { X86::VPERMT2PD256rrkz,   X86::VPERMT2PD256rmkz,     0 },
3511     { X86::VPERMT2PS256rrkz,   X86::VPERMT2PS256rmkz,     0 },
3512     { X86::VPERMT2Q256rrkz,    X86::VPERMT2Q256rmkz,      0 },
3513     { X86::VPERMT2W256rrkz,    X86::VPERMT2W256rmkz,      0 },
3514     { X86::VPTERNLOGDZ256rrikz,X86::VPTERNLOGDZ256rmikz,  0 },
3515     { X86::VPTERNLOGQZ256rrikz,X86::VPTERNLOGQZ256rmikz,  0 },
3516 
3517     // 128-bit three source instructions with zero masking.
3518     { X86::VPERMI2B128rrkz,    X86::VPERMI2B128rmkz,      0 },
3519     { X86::VPERMI2D128rrkz,    X86::VPERMI2D128rmkz,      0 },
3520     { X86::VPERMI2PD128rrkz,   X86::VPERMI2PD128rmkz,     0 },
3521     { X86::VPERMI2PS128rrkz,   X86::VPERMI2PS128rmkz,     0 },
3522     { X86::VPERMI2Q128rrkz,    X86::VPERMI2Q128rmkz,      0 },
3523     { X86::VPERMI2W128rrkz,    X86::VPERMI2W128rmkz,      0 },
3524     { X86::VPERMT2B128rrkz,    X86::VPERMT2B128rmkz,      0 },
3525     { X86::VPERMT2D128rrkz,    X86::VPERMT2D128rmkz,      0 },
3526     { X86::VPERMT2PD128rrkz,   X86::VPERMT2PD128rmkz,     0 },
3527     { X86::VPERMT2PS128rrkz,   X86::VPERMT2PS128rmkz,     0 },
3528     { X86::VPERMT2Q128rrkz,    X86::VPERMT2Q128rmkz,      0 },
3529     { X86::VPERMT2W128rrkz,    X86::VPERMT2W128rmkz,      0 },
3530     { X86::VPTERNLOGDZ128rrikz,X86::VPTERNLOGDZ128rmikz,  0 },
3531     { X86::VPTERNLOGQZ128rrikz,X86::VPTERNLOGQZ128rmikz,  0 },
3532   };
3533 
3534   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
3535     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3536                   Entry.RegOp, Entry.MemOp,
3537                   // Index 4, folded load
3538                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
3539   }
3540   for (I = X86InstrFMA3Info::rm_begin(); I != E; ++I) {
3541     if (I.getGroup()->isKMasked()) {
3542       // Intrinsics need to pass TB_NO_REVERSE.
3543       if (I.getGroup()->isIntrinsic()) {
3544         AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3545                       I.getRegOpcode(), I.getMemOpcode(),
3546                       TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD | TB_NO_REVERSE);
3547       } else {
3548         AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
3549                       I.getRegOpcode(), I.getMemOpcode(),
3550                       TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD);
3551       }
3552     }
3553   }
3554 }
3555 
3556 void
3557 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
3558                             MemOp2RegOpTableType &M2RTable,
3559                             uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
3560   if ((Flags & TB_NO_FORWARD) == 0) {
3561     assert(!R2MTable.count(RegOp) && "Duplicate entry!");
3562     R2MTable[RegOp] = std::make_pair(MemOp, Flags);
3563   }
3564   if ((Flags & TB_NO_REVERSE) == 0) {
3565     assert(!M2RTable.count(MemOp) &&
3566          "Duplicated entries in unfolding maps?");
3567     M2RTable[MemOp] = std::make_pair(RegOp, Flags);
3568   }
3569 }
3570 
3571 bool
3572 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
3573                                     unsigned &SrcReg, unsigned &DstReg,
3574                                     unsigned &SubIdx) const {
3575   switch (MI.getOpcode()) {
3576   default: break;
3577   case X86::MOVSX16rr8:
3578   case X86::MOVZX16rr8:
3579   case X86::MOVSX32rr8:
3580   case X86::MOVZX32rr8:
3581   case X86::MOVSX64rr8:
3582     if (!Subtarget.is64Bit())
3583       // It's not always legal to reference the low 8-bit of the larger
3584       // register in 32-bit mode.
3585       return false;
3586   case X86::MOVSX32rr16:
3587   case X86::MOVZX32rr16:
3588   case X86::MOVSX64rr16:
3589   case X86::MOVSX64rr32: {
3590     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
3591       // Be conservative.
3592       return false;
3593     SrcReg = MI.getOperand(1).getReg();
3594     DstReg = MI.getOperand(0).getReg();
3595     switch (MI.getOpcode()) {
3596     default: llvm_unreachable("Unreachable!");
3597     case X86::MOVSX16rr8:
3598     case X86::MOVZX16rr8:
3599     case X86::MOVSX32rr8:
3600     case X86::MOVZX32rr8:
3601     case X86::MOVSX64rr8:
3602       SubIdx = X86::sub_8bit;
3603       break;
3604     case X86::MOVSX32rr16:
3605     case X86::MOVZX32rr16:
3606     case X86::MOVSX64rr16:
3607       SubIdx = X86::sub_16bit;
3608       break;
3609     case X86::MOVSX64rr32:
3610       SubIdx = X86::sub_32bit;
3611       break;
3612     }
3613     return true;
3614   }
3615   }
3616   return false;
3617 }
3618 
3619 int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
3620   const MachineFunction *MF = MI.getParent()->getParent();
3621   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
3622 
3623   if (MI.getOpcode() == getCallFrameSetupOpcode() ||
3624       MI.getOpcode() == getCallFrameDestroyOpcode()) {
3625     unsigned StackAlign = TFI->getStackAlignment();
3626     int SPAdj =
3627         (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
3628 
3629     SPAdj -= MI.getOperand(1).getImm();
3630 
3631     if (MI.getOpcode() == getCallFrameSetupOpcode())
3632       return SPAdj;
3633     else
3634       return -SPAdj;
3635   }
3636 
3637   // To know whether a call adjusts the stack, we need information
3638   // that is bound to the following ADJCALLSTACKUP pseudo.
3639   // Look for the next ADJCALLSTACKUP that follows the call.
3640   if (MI.isCall()) {
3641     const MachineBasicBlock *MBB = MI.getParent();
3642     auto I = ++MachineBasicBlock::const_iterator(MI);
3643     for (auto E = MBB->end(); I != E; ++I) {
3644       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
3645           I->isCall())
3646         break;
3647     }
3648 
3649     // If we could not find a frame destroy opcode, then it has already
3650     // been simplified, so we don't care.
3651     if (I->getOpcode() != getCallFrameDestroyOpcode())
3652       return 0;
3653 
3654     return -(I->getOperand(1).getImm());
3655   }
3656 
3657   // Currently handle only PUSHes we can reasonably expect to see
3658   // in call sequences
3659   switch (MI.getOpcode()) {
3660   default:
3661     return 0;
3662   case X86::PUSH32i8:
3663   case X86::PUSH32r:
3664   case X86::PUSH32rmm:
3665   case X86::PUSH32rmr:
3666   case X86::PUSHi32:
3667     return 4;
3668   case X86::PUSH64i8:
3669   case X86::PUSH64r:
3670   case X86::PUSH64rmm:
3671   case X86::PUSH64rmr:
3672   case X86::PUSH64i32:
3673     return 8;
3674   }
3675 }
3676 
3677 /// Return true and the FrameIndex if the specified
3678 /// operand and follow operands form a reference to the stack frame.
3679 bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
3680                                   int &FrameIndex) const {
3681   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
3682       MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
3683       MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
3684       MI.getOperand(Op + X86::AddrDisp).isImm() &&
3685       MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
3686       MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
3687       MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
3688     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
3689     return true;
3690   }
3691   return false;
3692 }
3693 
3694 static bool isFrameLoadOpcode(int Opcode) {
3695   switch (Opcode) {
3696   default:
3697     return false;
3698   case X86::MOV8rm:
3699   case X86::MOV16rm:
3700   case X86::MOV32rm:
3701   case X86::MOV64rm:
3702   case X86::LD_Fp64m:
3703   case X86::MOVSSrm:
3704   case X86::MOVSDrm:
3705   case X86::MOVAPSrm:
3706   case X86::MOVUPSrm:
3707   case X86::MOVAPDrm:
3708   case X86::MOVUPDrm:
3709   case X86::MOVDQArm:
3710   case X86::MOVDQUrm:
3711   case X86::VMOVSSrm:
3712   case X86::VMOVSDrm:
3713   case X86::VMOVAPSrm:
3714   case X86::VMOVUPSrm:
3715   case X86::VMOVAPDrm:
3716   case X86::VMOVUPDrm:
3717   case X86::VMOVDQArm:
3718   case X86::VMOVDQUrm:
3719   case X86::VMOVUPSYrm:
3720   case X86::VMOVAPSYrm:
3721   case X86::VMOVUPDYrm:
3722   case X86::VMOVAPDYrm:
3723   case X86::VMOVDQUYrm:
3724   case X86::VMOVDQAYrm:
3725   case X86::MMX_MOVD64rm:
3726   case X86::MMX_MOVQ64rm:
3727   case X86::VMOVSSZrm:
3728   case X86::VMOVSDZrm:
3729   case X86::VMOVAPSZrm:
3730   case X86::VMOVAPSZ128rm:
3731   case X86::VMOVAPSZ256rm:
3732   case X86::VMOVAPSZ128rm_NOVLX:
3733   case X86::VMOVAPSZ256rm_NOVLX:
3734   case X86::VMOVUPSZrm:
3735   case X86::VMOVUPSZ128rm:
3736   case X86::VMOVUPSZ256rm:
3737   case X86::VMOVUPSZ128rm_NOVLX:
3738   case X86::VMOVUPSZ256rm_NOVLX:
3739   case X86::VMOVAPDZrm:
3740   case X86::VMOVAPDZ128rm:
3741   case X86::VMOVAPDZ256rm:
3742   case X86::VMOVUPDZrm:
3743   case X86::VMOVUPDZ128rm:
3744   case X86::VMOVUPDZ256rm:
3745   case X86::VMOVDQA32Zrm:
3746   case X86::VMOVDQA32Z128rm:
3747   case X86::VMOVDQA32Z256rm:
3748   case X86::VMOVDQU32Zrm:
3749   case X86::VMOVDQU32Z128rm:
3750   case X86::VMOVDQU32Z256rm:
3751   case X86::VMOVDQA64Zrm:
3752   case X86::VMOVDQA64Z128rm:
3753   case X86::VMOVDQA64Z256rm:
3754   case X86::VMOVDQU64Zrm:
3755   case X86::VMOVDQU64Z128rm:
3756   case X86::VMOVDQU64Z256rm:
3757   case X86::VMOVDQU8Zrm:
3758   case X86::VMOVDQU8Z128rm:
3759   case X86::VMOVDQU8Z256rm:
3760   case X86::VMOVDQU16Zrm:
3761   case X86::VMOVDQU16Z128rm:
3762   case X86::VMOVDQU16Z256rm:
3763   case X86::KMOVBkm:
3764   case X86::KMOVWkm:
3765   case X86::KMOVDkm:
3766   case X86::KMOVQkm:
3767     return true;
3768   }
3769 }
3770 
3771 static bool isFrameStoreOpcode(int Opcode) {
3772   switch (Opcode) {
3773   default: break;
3774   case X86::MOV8mr:
3775   case X86::MOV16mr:
3776   case X86::MOV32mr:
3777   case X86::MOV64mr:
3778   case X86::ST_FpP64m:
3779   case X86::MOVSSmr:
3780   case X86::MOVSDmr:
3781   case X86::MOVAPSmr:
3782   case X86::MOVUPSmr:
3783   case X86::MOVAPDmr:
3784   case X86::MOVUPDmr:
3785   case X86::MOVDQAmr:
3786   case X86::MOVDQUmr:
3787   case X86::VMOVSSmr:
3788   case X86::VMOVSDmr:
3789   case X86::VMOVAPSmr:
3790   case X86::VMOVUPSmr:
3791   case X86::VMOVAPDmr:
3792   case X86::VMOVUPDmr:
3793   case X86::VMOVDQAmr:
3794   case X86::VMOVDQUmr:
3795   case X86::VMOVUPSYmr:
3796   case X86::VMOVAPSYmr:
3797   case X86::VMOVUPDYmr:
3798   case X86::VMOVAPDYmr:
3799   case X86::VMOVDQUYmr:
3800   case X86::VMOVDQAYmr:
3801   case X86::VMOVSSZmr:
3802   case X86::VMOVSDZmr:
3803   case X86::VMOVUPSZmr:
3804   case X86::VMOVUPSZ128mr:
3805   case X86::VMOVUPSZ256mr:
3806   case X86::VMOVUPSZ128mr_NOVLX:
3807   case X86::VMOVUPSZ256mr_NOVLX:
3808   case X86::VMOVAPSZmr:
3809   case X86::VMOVAPSZ128mr:
3810   case X86::VMOVAPSZ256mr:
3811   case X86::VMOVAPSZ128mr_NOVLX:
3812   case X86::VMOVAPSZ256mr_NOVLX:
3813   case X86::VMOVUPDZmr:
3814   case X86::VMOVUPDZ128mr:
3815   case X86::VMOVUPDZ256mr:
3816   case X86::VMOVAPDZmr:
3817   case X86::VMOVAPDZ128mr:
3818   case X86::VMOVAPDZ256mr:
3819   case X86::VMOVDQA32Zmr:
3820   case X86::VMOVDQA32Z128mr:
3821   case X86::VMOVDQA32Z256mr:
3822   case X86::VMOVDQU32Zmr:
3823   case X86::VMOVDQU32Z128mr:
3824   case X86::VMOVDQU32Z256mr:
3825   case X86::VMOVDQA64Zmr:
3826   case X86::VMOVDQA64Z128mr:
3827   case X86::VMOVDQA64Z256mr:
3828   case X86::VMOVDQU64Zmr:
3829   case X86::VMOVDQU64Z128mr:
3830   case X86::VMOVDQU64Z256mr:
3831   case X86::VMOVDQU8Zmr:
3832   case X86::VMOVDQU8Z128mr:
3833   case X86::VMOVDQU8Z256mr:
3834   case X86::VMOVDQU16Zmr:
3835   case X86::VMOVDQU16Z128mr:
3836   case X86::VMOVDQU16Z256mr:
3837   case X86::MMX_MOVD64mr:
3838   case X86::MMX_MOVQ64mr:
3839   case X86::MMX_MOVNTQmr:
3840   case X86::KMOVBmk:
3841   case X86::KMOVWmk:
3842   case X86::KMOVDmk:
3843   case X86::KMOVQmk:
3844     return true;
3845   }
3846   return false;
3847 }
3848 
3849 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
3850                                            int &FrameIndex) const {
3851   if (isFrameLoadOpcode(MI.getOpcode()))
3852     if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
3853       return MI.getOperand(0).getReg();
3854   return 0;
3855 }
3856 
3857 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
3858                                                  int &FrameIndex) const {
3859   if (isFrameLoadOpcode(MI.getOpcode())) {
3860     unsigned Reg;
3861     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
3862       return Reg;
3863     // Check for post-frame index elimination operations
3864     const MachineMemOperand *Dummy;
3865     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
3866   }
3867   return 0;
3868 }
3869 
3870 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
3871                                           int &FrameIndex) const {
3872   if (isFrameStoreOpcode(MI.getOpcode()))
3873     if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
3874         isFrameOperand(MI, 0, FrameIndex))
3875       return MI.getOperand(X86::AddrNumOperands).getReg();
3876   return 0;
3877 }
3878 
3879 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
3880                                                 int &FrameIndex) const {
3881   if (isFrameStoreOpcode(MI.getOpcode())) {
3882     unsigned Reg;
3883     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
3884       return Reg;
3885     // Check for post-frame index elimination operations
3886     const MachineMemOperand *Dummy;
3887     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
3888   }
3889   return 0;
3890 }
3891 
3892 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
3893 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
3894   // Don't waste compile time scanning use-def chains of physregs.
3895   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
3896     return false;
3897   bool isPICBase = false;
3898   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
3899          E = MRI.def_instr_end(); I != E; ++I) {
3900     MachineInstr *DefMI = &*I;
3901     if (DefMI->getOpcode() != X86::MOVPC32r)
3902       return false;
3903     assert(!isPICBase && "More than one PIC base?");
3904     isPICBase = true;
3905   }
3906   return isPICBase;
3907 }
3908 
3909 bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
3910                                                      AliasAnalysis *AA) const {
3911   switch (MI.getOpcode()) {
3912   default: break;
3913   case X86::MOV8rm:
3914   case X86::MOV8rm_NOREX:
3915   case X86::MOV16rm:
3916   case X86::MOV32rm:
3917   case X86::MOV64rm:
3918   case X86::LD_Fp64m:
3919   case X86::MOVSSrm:
3920   case X86::MOVSDrm:
3921   case X86::MOVAPSrm:
3922   case X86::MOVUPSrm:
3923   case X86::MOVAPDrm:
3924   case X86::MOVUPDrm:
3925   case X86::MOVDQArm:
3926   case X86::MOVDQUrm:
3927   case X86::VMOVSSrm:
3928   case X86::VMOVSDrm:
3929   case X86::VMOVAPSrm:
3930   case X86::VMOVUPSrm:
3931   case X86::VMOVAPDrm:
3932   case X86::VMOVUPDrm:
3933   case X86::VMOVDQArm:
3934   case X86::VMOVDQUrm:
3935   case X86::VMOVAPSYrm:
3936   case X86::VMOVUPSYrm:
3937   case X86::VMOVAPDYrm:
3938   case X86::VMOVUPDYrm:
3939   case X86::VMOVDQAYrm:
3940   case X86::VMOVDQUYrm:
3941   case X86::MMX_MOVD64rm:
3942   case X86::MMX_MOVQ64rm:
3943   // AVX-512
3944   case X86::VMOVSSZrm:
3945   case X86::VMOVSDZrm:
3946   case X86::VMOVAPDZ128rm:
3947   case X86::VMOVAPDZ256rm:
3948   case X86::VMOVAPDZrm:
3949   case X86::VMOVAPSZ128rm:
3950   case X86::VMOVAPSZ256rm:
3951   case X86::VMOVAPSZ128rm_NOVLX:
3952   case X86::VMOVAPSZ256rm_NOVLX:
3953   case X86::VMOVAPSZrm:
3954   case X86::VMOVDQA32Z128rm:
3955   case X86::VMOVDQA32Z256rm:
3956   case X86::VMOVDQA32Zrm:
3957   case X86::VMOVDQA64Z128rm:
3958   case X86::VMOVDQA64Z256rm:
3959   case X86::VMOVDQA64Zrm:
3960   case X86::VMOVDQU16Z128rm:
3961   case X86::VMOVDQU16Z256rm:
3962   case X86::VMOVDQU16Zrm:
3963   case X86::VMOVDQU32Z128rm:
3964   case X86::VMOVDQU32Z256rm:
3965   case X86::VMOVDQU32Zrm:
3966   case X86::VMOVDQU64Z128rm:
3967   case X86::VMOVDQU64Z256rm:
3968   case X86::VMOVDQU64Zrm:
3969   case X86::VMOVDQU8Z128rm:
3970   case X86::VMOVDQU8Z256rm:
3971   case X86::VMOVDQU8Zrm:
3972   case X86::VMOVUPDZ128rm:
3973   case X86::VMOVUPDZ256rm:
3974   case X86::VMOVUPDZrm:
3975   case X86::VMOVUPSZ128rm:
3976   case X86::VMOVUPSZ256rm:
3977   case X86::VMOVUPSZ128rm_NOVLX:
3978   case X86::VMOVUPSZ256rm_NOVLX:
3979   case X86::VMOVUPSZrm: {
3980     // Loads from constant pools are trivially rematerializable.
3981     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
3982         MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
3983         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
3984         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
3985         MI.isDereferenceableInvariantLoad(AA)) {
3986       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
3987       if (BaseReg == 0 || BaseReg == X86::RIP)
3988         return true;
3989       // Allow re-materialization of PIC load.
3990       if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
3991         return false;
3992       const MachineFunction &MF = *MI.getParent()->getParent();
3993       const MachineRegisterInfo &MRI = MF.getRegInfo();
3994       return regIsPICBase(BaseReg, MRI);
3995     }
3996     return false;
3997   }
3998 
3999   case X86::LEA32r:
4000   case X86::LEA64r: {
4001     if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
4002         MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
4003         MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
4004         !MI.getOperand(1 + X86::AddrDisp).isReg()) {
4005       // lea fi#, lea GV, etc. are all rematerializable.
4006       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
4007         return true;
4008       unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
4009       if (BaseReg == 0)
4010         return true;
4011       // Allow re-materialization of lea PICBase + x.
4012       const MachineFunction &MF = *MI.getParent()->getParent();
4013       const MachineRegisterInfo &MRI = MF.getRegInfo();
4014       return regIsPICBase(BaseReg, MRI);
4015     }
4016     return false;
4017   }
4018   }
4019 
4020   // All other instructions marked M_REMATERIALIZABLE are always trivially
4021   // rematerializable.
4022   return true;
4023 }
4024 
4025 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
4026                                          MachineBasicBlock::iterator I) const {
4027   MachineBasicBlock::iterator E = MBB.end();
4028 
4029   // For compile time consideration, if we are not able to determine the
4030   // safety after visiting 4 instructions in each direction, we will assume
4031   // it's not safe.
4032   MachineBasicBlock::iterator Iter = I;
4033   for (unsigned i = 0; Iter != E && i < 4; ++i) {
4034     bool SeenDef = false;
4035     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
4036       MachineOperand &MO = Iter->getOperand(j);
4037       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
4038         SeenDef = true;
4039       if (!MO.isReg())
4040         continue;
4041       if (MO.getReg() == X86::EFLAGS) {
4042         if (MO.isUse())
4043           return false;
4044         SeenDef = true;
4045       }
4046     }
4047 
4048     if (SeenDef)
4049       // This instruction defines EFLAGS, no need to look any further.
4050       return true;
4051     ++Iter;
4052     // Skip over DBG_VALUE.
4053     while (Iter != E && Iter->isDebugValue())
4054       ++Iter;
4055   }
4056 
4057   // It is safe to clobber EFLAGS at the end of a block of no successor has it
4058   // live in.
4059   if (Iter == E) {
4060     for (MachineBasicBlock *S : MBB.successors())
4061       if (S->isLiveIn(X86::EFLAGS))
4062         return false;
4063     return true;
4064   }
4065 
4066   MachineBasicBlock::iterator B = MBB.begin();
4067   Iter = I;
4068   for (unsigned i = 0; i < 4; ++i) {
4069     // If we make it to the beginning of the block, it's safe to clobber
4070     // EFLAGS iff EFLAGS is not live-in.
4071     if (Iter == B)
4072       return !MBB.isLiveIn(X86::EFLAGS);
4073 
4074     --Iter;
4075     // Skip over DBG_VALUE.
4076     while (Iter != B && Iter->isDebugValue())
4077       --Iter;
4078 
4079     bool SawKill = false;
4080     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
4081       MachineOperand &MO = Iter->getOperand(j);
4082       // A register mask may clobber EFLAGS, but we should still look for a
4083       // live EFLAGS def.
4084       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
4085         SawKill = true;
4086       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
4087         if (MO.isDef()) return MO.isDead();
4088         if (MO.isKill()) SawKill = true;
4089       }
4090     }
4091 
4092     if (SawKill)
4093       // This instruction kills EFLAGS and doesn't redefine it, so
4094       // there's no need to look further.
4095       return true;
4096   }
4097 
4098   // Conservative answer.
4099   return false;
4100 }
4101 
4102 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
4103                                  MachineBasicBlock::iterator I,
4104                                  unsigned DestReg, unsigned SubIdx,
4105                                  const MachineInstr &Orig,
4106                                  const TargetRegisterInfo &TRI) const {
4107   bool ClobbersEFLAGS = false;
4108   for (const MachineOperand &MO : Orig.operands()) {
4109     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4110       ClobbersEFLAGS = true;
4111       break;
4112     }
4113   }
4114 
4115   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
4116     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
4117     // effects.
4118     int Value;
4119     switch (Orig.getOpcode()) {
4120     case X86::MOV32r0:  Value = 0; break;
4121     case X86::MOV32r1:  Value = 1; break;
4122     case X86::MOV32r_1: Value = -1; break;
4123     default:
4124       llvm_unreachable("Unexpected instruction!");
4125     }
4126 
4127     const DebugLoc &DL = Orig.getDebugLoc();
4128     BuildMI(MBB, I, DL, get(X86::MOV32ri))
4129         .add(Orig.getOperand(0))
4130         .addImm(Value);
4131   } else {
4132     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
4133     MBB.insert(I, MI);
4134   }
4135 
4136   MachineInstr &NewMI = *std::prev(I);
4137   NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
4138 }
4139 
4140 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
4141 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
4142   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
4143     MachineOperand &MO = MI.getOperand(i);
4144     if (MO.isReg() && MO.isDef() &&
4145         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
4146       return true;
4147     }
4148   }
4149   return false;
4150 }
4151 
4152 /// Check whether the shift count for a machine operand is non-zero.
4153 inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
4154                                               unsigned ShiftAmtOperandIdx) {
4155   // The shift count is six bits with the REX.W prefix and five bits without.
4156   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
4157   unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
4158   return Imm & ShiftCountMask;
4159 }
4160 
4161 /// Check whether the given shift count is appropriate
4162 /// can be represented by a LEA instruction.
4163 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
4164   // Left shift instructions can be transformed into load-effective-address
4165   // instructions if we can encode them appropriately.
4166   // A LEA instruction utilizes a SIB byte to encode its scale factor.
4167   // The SIB.scale field is two bits wide which means that we can encode any
4168   // shift amount less than 4.
4169   return ShAmt < 4 && ShAmt > 0;
4170 }
4171 
4172 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
4173                                   unsigned Opc, bool AllowSP, unsigned &NewSrc,
4174                                   bool &isKill, bool &isUndef,
4175                                   MachineOperand &ImplicitOp,
4176                                   LiveVariables *LV) const {
4177   MachineFunction &MF = *MI.getParent()->getParent();
4178   const TargetRegisterClass *RC;
4179   if (AllowSP) {
4180     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
4181   } else {
4182     RC = Opc != X86::LEA32r ?
4183       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
4184   }
4185   unsigned SrcReg = Src.getReg();
4186 
4187   // For both LEA64 and LEA32 the register already has essentially the right
4188   // type (32-bit or 64-bit) we may just need to forbid SP.
4189   if (Opc != X86::LEA64_32r) {
4190     NewSrc = SrcReg;
4191     isKill = Src.isKill();
4192     isUndef = Src.isUndef();
4193 
4194     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
4195         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
4196       return false;
4197 
4198     return true;
4199   }
4200 
4201   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
4202   // another we need to add 64-bit registers to the final MI.
4203   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
4204     ImplicitOp = Src;
4205     ImplicitOp.setImplicit();
4206 
4207     NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
4208     isKill = Src.isKill();
4209     isUndef = Src.isUndef();
4210   } else {
4211     // Virtual register of the wrong class, we have to create a temporary 64-bit
4212     // vreg to feed into the LEA.
4213     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
4214     MachineInstr *Copy =
4215         BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4216             .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
4217             .add(Src);
4218 
4219     // Which is obviously going to be dead after we're done with it.
4220     isKill = true;
4221     isUndef = false;
4222 
4223     if (LV)
4224       LV->replaceKillInstruction(SrcReg, MI, *Copy);
4225   }
4226 
4227   // We've set all the parameters without issue.
4228   return true;
4229 }
4230 
4231 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
4232 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
4233 /// truncating back down to a 16-bit subregister.
4234 MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
4235     unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
4236     LiveVariables *LV) const {
4237   MachineBasicBlock::iterator MBBI = MI.getIterator();
4238   unsigned Dest = MI.getOperand(0).getReg();
4239   unsigned Src = MI.getOperand(1).getReg();
4240   bool isDead = MI.getOperand(0).isDead();
4241   bool isKill = MI.getOperand(1).isKill();
4242 
4243   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
4244   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
4245   unsigned Opc, leaInReg;
4246   if (Subtarget.is64Bit()) {
4247     Opc = X86::LEA64_32r;
4248     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
4249   } else {
4250     Opc = X86::LEA32r;
4251     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4252   }
4253 
4254   // Build and insert into an implicit UNDEF value. This is OK because
4255   // well be shifting and then extracting the lower 16-bits.
4256   // This has the potential to cause partial register stall. e.g.
4257   //   movw    (%rbp,%rcx,2), %dx
4258   //   leal    -65(%rdx), %esi
4259   // But testing has shown this *does* help performance in 64-bit mode (at
4260   // least on modern x86 machines).
4261   BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
4262   MachineInstr *InsMI =
4263       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4264           .addReg(leaInReg, RegState::Define, X86::sub_16bit)
4265           .addReg(Src, getKillRegState(isKill));
4266 
4267   MachineInstrBuilder MIB =
4268       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
4269   switch (MIOpc) {
4270   default: llvm_unreachable("Unreachable!");
4271   case X86::SHL16ri: {
4272     unsigned ShAmt = MI.getOperand(2).getImm();
4273     MIB.addReg(0).addImm(1ULL << ShAmt)
4274        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
4275     break;
4276   }
4277   case X86::INC16r:
4278     addRegOffset(MIB, leaInReg, true, 1);
4279     break;
4280   case X86::DEC16r:
4281     addRegOffset(MIB, leaInReg, true, -1);
4282     break;
4283   case X86::ADD16ri:
4284   case X86::ADD16ri8:
4285   case X86::ADD16ri_DB:
4286   case X86::ADD16ri8_DB:
4287     addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
4288     break;
4289   case X86::ADD16rr:
4290   case X86::ADD16rr_DB: {
4291     unsigned Src2 = MI.getOperand(2).getReg();
4292     bool isKill2 = MI.getOperand(2).isKill();
4293     unsigned leaInReg2 = 0;
4294     MachineInstr *InsMI2 = nullptr;
4295     if (Src == Src2) {
4296       // ADD16rr %reg1028<kill>, %reg1028
4297       // just a single insert_subreg.
4298       addRegReg(MIB, leaInReg, true, leaInReg, false);
4299     } else {
4300       if (Subtarget.is64Bit())
4301         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
4302       else
4303         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4304       // Build and insert into an implicit UNDEF value. This is OK because
4305       // well be shifting and then extracting the lower 16-bits.
4306       BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
4307       InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
4308                    .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
4309                    .addReg(Src2, getKillRegState(isKill2));
4310       addRegReg(MIB, leaInReg, true, leaInReg2, true);
4311     }
4312     if (LV && isKill2 && InsMI2)
4313       LV->replaceKillInstruction(Src2, MI, *InsMI2);
4314     break;
4315   }
4316   }
4317 
4318   MachineInstr *NewMI = MIB;
4319   MachineInstr *ExtMI =
4320       BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
4321           .addReg(Dest, RegState::Define | getDeadRegState(isDead))
4322           .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
4323 
4324   if (LV) {
4325     // Update live variables
4326     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
4327     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
4328     if (isKill)
4329       LV->replaceKillInstruction(Src, MI, *InsMI);
4330     if (isDead)
4331       LV->replaceKillInstruction(Dest, MI, *ExtMI);
4332   }
4333 
4334   return ExtMI;
4335 }
4336 
4337 /// This method must be implemented by targets that
4338 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
4339 /// may be able to convert a two-address instruction into a true
4340 /// three-address instruction on demand.  This allows the X86 target (for
4341 /// example) to convert ADD and SHL instructions into LEA instructions if they
4342 /// would require register copies due to two-addressness.
4343 ///
4344 /// This method returns a null pointer if the transformation cannot be
4345 /// performed, otherwise it returns the new instruction.
4346 ///
4347 MachineInstr *
4348 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
4349                                     MachineInstr &MI, LiveVariables *LV) const {
4350   // The following opcodes also sets the condition code register(s). Only
4351   // convert them to equivalent lea if the condition code register def's
4352   // are dead!
4353   if (hasLiveCondCodeDef(MI))
4354     return nullptr;
4355 
4356   MachineFunction &MF = *MI.getParent()->getParent();
4357   // All instructions input are two-addr instructions.  Get the known operands.
4358   const MachineOperand &Dest = MI.getOperand(0);
4359   const MachineOperand &Src = MI.getOperand(1);
4360 
4361   MachineInstr *NewMI = nullptr;
4362   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
4363   // we have better subtarget support, enable the 16-bit LEA generation here.
4364   // 16-bit LEA is also slow on Core2.
4365   bool DisableLEA16 = true;
4366   bool is64Bit = Subtarget.is64Bit();
4367 
4368   unsigned MIOpc = MI.getOpcode();
4369   switch (MIOpc) {
4370   default: return nullptr;
4371   case X86::SHL64ri: {
4372     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
4373     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4374     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4375 
4376     // LEA can't handle RSP.
4377     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
4378         !MF.getRegInfo().constrainRegClass(Src.getReg(),
4379                                            &X86::GR64_NOSPRegClass))
4380       return nullptr;
4381 
4382     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
4383                 .add(Dest)
4384                 .addReg(0)
4385                 .addImm(1ULL << ShAmt)
4386                 .add(Src)
4387                 .addImm(0)
4388                 .addReg(0);
4389     break;
4390   }
4391   case X86::SHL32ri: {
4392     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
4393     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4394     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4395 
4396     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4397 
4398     // LEA can't handle ESP.
4399     bool isKill, isUndef;
4400     unsigned SrcReg;
4401     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4402     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4403                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4404       return nullptr;
4405 
4406     MachineInstrBuilder MIB =
4407         BuildMI(MF, MI.getDebugLoc(), get(Opc))
4408             .add(Dest)
4409             .addReg(0)
4410             .addImm(1ULL << ShAmt)
4411             .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
4412             .addImm(0)
4413             .addReg(0);
4414     if (ImplicitOp.getReg() != 0)
4415       MIB.add(ImplicitOp);
4416     NewMI = MIB;
4417 
4418     break;
4419   }
4420   case X86::SHL16ri: {
4421     assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
4422     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4423     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
4424 
4425     if (DisableLEA16)
4426       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4427                      : nullptr;
4428     NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
4429                 .add(Dest)
4430                 .addReg(0)
4431                 .addImm(1ULL << ShAmt)
4432                 .add(Src)
4433                 .addImm(0)
4434                 .addReg(0);
4435     break;
4436   }
4437   case X86::INC64r:
4438   case X86::INC32r: {
4439     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
4440     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
4441       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
4442     bool isKill, isUndef;
4443     unsigned SrcReg;
4444     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4445     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4446                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4447       return nullptr;
4448 
4449     MachineInstrBuilder MIB =
4450         BuildMI(MF, MI.getDebugLoc(), get(Opc))
4451             .add(Dest)
4452             .addReg(SrcReg,
4453                     getKillRegState(isKill) | getUndefRegState(isUndef));
4454     if (ImplicitOp.getReg() != 0)
4455       MIB.add(ImplicitOp);
4456 
4457     NewMI = addOffset(MIB, 1);
4458     break;
4459   }
4460   case X86::INC16r:
4461     if (DisableLEA16)
4462       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4463                      : nullptr;
4464     assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
4465     NewMI = addOffset(
4466         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), 1);
4467     break;
4468   case X86::DEC64r:
4469   case X86::DEC32r: {
4470     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
4471     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
4472       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
4473 
4474     bool isKill, isUndef;
4475     unsigned SrcReg;
4476     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4477     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
4478                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4479       return nullptr;
4480 
4481     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4482                                   .add(Dest)
4483                                   .addReg(SrcReg, getUndefRegState(isUndef) |
4484                                                       getKillRegState(isKill));
4485     if (ImplicitOp.getReg() != 0)
4486       MIB.add(ImplicitOp);
4487 
4488     NewMI = addOffset(MIB, -1);
4489 
4490     break;
4491   }
4492   case X86::DEC16r:
4493     if (DisableLEA16)
4494       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4495                      : nullptr;
4496     assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
4497     NewMI = addOffset(
4498         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src), -1);
4499     break;
4500   case X86::ADD64rr:
4501   case X86::ADD64rr_DB:
4502   case X86::ADD32rr:
4503   case X86::ADD32rr_DB: {
4504     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4505     unsigned Opc;
4506     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
4507       Opc = X86::LEA64r;
4508     else
4509       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4510 
4511     bool isKill, isUndef;
4512     unsigned SrcReg;
4513     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4514     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
4515                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4516       return nullptr;
4517 
4518     const MachineOperand &Src2 = MI.getOperand(2);
4519     bool isKill2, isUndef2;
4520     unsigned SrcReg2;
4521     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
4522     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
4523                         SrcReg2, isKill2, isUndef2, ImplicitOp2, LV))
4524       return nullptr;
4525 
4526     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
4527     if (ImplicitOp.getReg() != 0)
4528       MIB.add(ImplicitOp);
4529     if (ImplicitOp2.getReg() != 0)
4530       MIB.add(ImplicitOp2);
4531 
4532     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
4533 
4534     // Preserve undefness of the operands.
4535     NewMI->getOperand(1).setIsUndef(isUndef);
4536     NewMI->getOperand(3).setIsUndef(isUndef2);
4537 
4538     if (LV && Src2.isKill())
4539       LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
4540     break;
4541   }
4542   case X86::ADD16rr:
4543   case X86::ADD16rr_DB: {
4544     if (DisableLEA16)
4545       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4546                      : nullptr;
4547     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4548     unsigned Src2 = MI.getOperand(2).getReg();
4549     bool isKill2 = MI.getOperand(2).isKill();
4550     NewMI = addRegReg(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest),
4551                       Src.getReg(), Src.isKill(), Src2, isKill2);
4552 
4553     // Preserve undefness of the operands.
4554     bool isUndef = MI.getOperand(1).isUndef();
4555     bool isUndef2 = MI.getOperand(2).isUndef();
4556     NewMI->getOperand(1).setIsUndef(isUndef);
4557     NewMI->getOperand(3).setIsUndef(isUndef2);
4558 
4559     if (LV && isKill2)
4560       LV->replaceKillInstruction(Src2, MI, *NewMI);
4561     break;
4562   }
4563   case X86::ADD64ri32:
4564   case X86::ADD64ri8:
4565   case X86::ADD64ri32_DB:
4566   case X86::ADD64ri8_DB:
4567     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4568     NewMI = addOffset(
4569         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
4570         MI.getOperand(2));
4571     break;
4572   case X86::ADD32ri:
4573   case X86::ADD32ri8:
4574   case X86::ADD32ri_DB:
4575   case X86::ADD32ri8_DB: {
4576     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4577     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
4578 
4579     bool isKill, isUndef;
4580     unsigned SrcReg;
4581     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
4582     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
4583                         SrcReg, isKill, isUndef, ImplicitOp, LV))
4584       return nullptr;
4585 
4586     MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4587                                   .add(Dest)
4588                                   .addReg(SrcReg, getUndefRegState(isUndef) |
4589                                                       getKillRegState(isKill));
4590     if (ImplicitOp.getReg() != 0)
4591       MIB.add(ImplicitOp);
4592 
4593     NewMI = addOffset(MIB, MI.getOperand(2));
4594     break;
4595   }
4596   case X86::ADD16ri:
4597   case X86::ADD16ri8:
4598   case X86::ADD16ri_DB:
4599   case X86::ADD16ri8_DB:
4600     if (DisableLEA16)
4601       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
4602                      : nullptr;
4603     assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
4604     NewMI = addOffset(
4605         BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).add(Dest).add(Src),
4606         MI.getOperand(2));
4607     break;
4608 
4609   case X86::VMOVDQU8Z128rmk:
4610   case X86::VMOVDQU8Z256rmk:
4611   case X86::VMOVDQU8Zrmk:
4612   case X86::VMOVDQU16Z128rmk:
4613   case X86::VMOVDQU16Z256rmk:
4614   case X86::VMOVDQU16Zrmk:
4615   case X86::VMOVDQU32Z128rmk: case X86::VMOVDQA32Z128rmk:
4616   case X86::VMOVDQU32Z256rmk: case X86::VMOVDQA32Z256rmk:
4617   case X86::VMOVDQU32Zrmk:    case X86::VMOVDQA32Zrmk:
4618   case X86::VMOVDQU64Z128rmk: case X86::VMOVDQA64Z128rmk:
4619   case X86::VMOVDQU64Z256rmk: case X86::VMOVDQA64Z256rmk:
4620   case X86::VMOVDQU64Zrmk:    case X86::VMOVDQA64Zrmk:
4621   case X86::VMOVUPDZ128rmk:   case X86::VMOVAPDZ128rmk:
4622   case X86::VMOVUPDZ256rmk:   case X86::VMOVAPDZ256rmk:
4623   case X86::VMOVUPDZrmk:      case X86::VMOVAPDZrmk:
4624   case X86::VMOVUPSZ128rmk:   case X86::VMOVAPSZ128rmk:
4625   case X86::VMOVUPSZ256rmk:   case X86::VMOVAPSZ256rmk:
4626   case X86::VMOVUPSZrmk:      case X86::VMOVAPSZrmk: {
4627     unsigned Opc;
4628     switch (MIOpc) {
4629     default: llvm_unreachable("Unreachable!");
4630     case X86::VMOVDQU8Z128rmk:  Opc = X86::VPBLENDMBZ128rmk; break;
4631     case X86::VMOVDQU8Z256rmk:  Opc = X86::VPBLENDMBZ256rmk; break;
4632     case X86::VMOVDQU8Zrmk:     Opc = X86::VPBLENDMBZrmk;    break;
4633     case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
4634     case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
4635     case X86::VMOVDQU16Zrmk:    Opc = X86::VPBLENDMWZrmk;    break;
4636     case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
4637     case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
4638     case X86::VMOVDQU32Zrmk:    Opc = X86::VPBLENDMDZrmk;    break;
4639     case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
4640     case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
4641     case X86::VMOVDQU64Zrmk:    Opc = X86::VPBLENDMQZrmk;    break;
4642     case X86::VMOVUPDZ128rmk:   Opc = X86::VBLENDMPDZ128rmk; break;
4643     case X86::VMOVUPDZ256rmk:   Opc = X86::VBLENDMPDZ256rmk; break;
4644     case X86::VMOVUPDZrmk:      Opc = X86::VBLENDMPDZrmk;    break;
4645     case X86::VMOVUPSZ128rmk:   Opc = X86::VBLENDMPSZ128rmk; break;
4646     case X86::VMOVUPSZ256rmk:   Opc = X86::VBLENDMPSZ256rmk; break;
4647     case X86::VMOVUPSZrmk:      Opc = X86::VBLENDMPSZrmk;    break;
4648     case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
4649     case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
4650     case X86::VMOVDQA32Zrmk:    Opc = X86::VPBLENDMDZrmk;    break;
4651     case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
4652     case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
4653     case X86::VMOVDQA64Zrmk:    Opc = X86::VPBLENDMQZrmk;    break;
4654     case X86::VMOVAPDZ128rmk:   Opc = X86::VBLENDMPDZ128rmk; break;
4655     case X86::VMOVAPDZ256rmk:   Opc = X86::VBLENDMPDZ256rmk; break;
4656     case X86::VMOVAPDZrmk:      Opc = X86::VBLENDMPDZrmk;    break;
4657     case X86::VMOVAPSZ128rmk:   Opc = X86::VBLENDMPSZ128rmk; break;
4658     case X86::VMOVAPSZ256rmk:   Opc = X86::VBLENDMPSZ256rmk; break;
4659     case X86::VMOVAPSZrmk:      Opc = X86::VBLENDMPSZrmk;    break;
4660     }
4661 
4662     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4663               .add(Dest)
4664               .add(MI.getOperand(2))
4665               .add(Src)
4666               .add(MI.getOperand(3))
4667               .add(MI.getOperand(4))
4668               .add(MI.getOperand(5))
4669               .add(MI.getOperand(6))
4670               .add(MI.getOperand(7));
4671     break;
4672   }
4673   case X86::VMOVDQU8Z128rrk:
4674   case X86::VMOVDQU8Z256rrk:
4675   case X86::VMOVDQU8Zrrk:
4676   case X86::VMOVDQU16Z128rrk:
4677   case X86::VMOVDQU16Z256rrk:
4678   case X86::VMOVDQU16Zrrk:
4679   case X86::VMOVDQU32Z128rrk: case X86::VMOVDQA32Z128rrk:
4680   case X86::VMOVDQU32Z256rrk: case X86::VMOVDQA32Z256rrk:
4681   case X86::VMOVDQU32Zrrk:    case X86::VMOVDQA32Zrrk:
4682   case X86::VMOVDQU64Z128rrk: case X86::VMOVDQA64Z128rrk:
4683   case X86::VMOVDQU64Z256rrk: case X86::VMOVDQA64Z256rrk:
4684   case X86::VMOVDQU64Zrrk:    case X86::VMOVDQA64Zrrk:
4685   case X86::VMOVUPDZ128rrk:   case X86::VMOVAPDZ128rrk:
4686   case X86::VMOVUPDZ256rrk:   case X86::VMOVAPDZ256rrk:
4687   case X86::VMOVUPDZrrk:      case X86::VMOVAPDZrrk:
4688   case X86::VMOVUPSZ128rrk:   case X86::VMOVAPSZ128rrk:
4689   case X86::VMOVUPSZ256rrk:   case X86::VMOVAPSZ256rrk:
4690   case X86::VMOVUPSZrrk:      case X86::VMOVAPSZrrk: {
4691     unsigned Opc;
4692     switch (MIOpc) {
4693     default: llvm_unreachable("Unreachable!");
4694     case X86::VMOVDQU8Z128rrk:  Opc = X86::VPBLENDMBZ128rrk; break;
4695     case X86::VMOVDQU8Z256rrk:  Opc = X86::VPBLENDMBZ256rrk; break;
4696     case X86::VMOVDQU8Zrrk:     Opc = X86::VPBLENDMBZrrk;    break;
4697     case X86::VMOVDQU16Z128rrk: Opc = X86::VPBLENDMWZ128rrk; break;
4698     case X86::VMOVDQU16Z256rrk: Opc = X86::VPBLENDMWZ256rrk; break;
4699     case X86::VMOVDQU16Zrrk:    Opc = X86::VPBLENDMWZrrk;    break;
4700     case X86::VMOVDQU32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
4701     case X86::VMOVDQU32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
4702     case X86::VMOVDQU32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
4703     case X86::VMOVDQU64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
4704     case X86::VMOVDQU64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
4705     case X86::VMOVDQU64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
4706     case X86::VMOVUPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
4707     case X86::VMOVUPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
4708     case X86::VMOVUPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
4709     case X86::VMOVUPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
4710     case X86::VMOVUPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
4711     case X86::VMOVUPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
4712     case X86::VMOVDQA32Z128rrk: Opc = X86::VPBLENDMDZ128rrk; break;
4713     case X86::VMOVDQA32Z256rrk: Opc = X86::VPBLENDMDZ256rrk; break;
4714     case X86::VMOVDQA32Zrrk:    Opc = X86::VPBLENDMDZrrk;    break;
4715     case X86::VMOVDQA64Z128rrk: Opc = X86::VPBLENDMQZ128rrk; break;
4716     case X86::VMOVDQA64Z256rrk: Opc = X86::VPBLENDMQZ256rrk; break;
4717     case X86::VMOVDQA64Zrrk:    Opc = X86::VPBLENDMQZrrk;    break;
4718     case X86::VMOVAPDZ128rrk:   Opc = X86::VBLENDMPDZ128rrk; break;
4719     case X86::VMOVAPDZ256rrk:   Opc = X86::VBLENDMPDZ256rrk; break;
4720     case X86::VMOVAPDZrrk:      Opc = X86::VBLENDMPDZrrk;    break;
4721     case X86::VMOVAPSZ128rrk:   Opc = X86::VBLENDMPSZ128rrk; break;
4722     case X86::VMOVAPSZ256rrk:   Opc = X86::VBLENDMPSZ256rrk; break;
4723     case X86::VMOVAPSZrrk:      Opc = X86::VBLENDMPSZrrk;    break;
4724     }
4725 
4726     NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
4727               .add(Dest)
4728               .add(MI.getOperand(2))
4729               .add(Src)
4730               .add(MI.getOperand(3));
4731     break;
4732   }
4733   }
4734 
4735   if (!NewMI) return nullptr;
4736 
4737   if (LV) {  // Update live variables
4738     if (Src.isKill())
4739       LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
4740     if (Dest.isDead())
4741       LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
4742   }
4743 
4744   MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
4745   return NewMI;
4746 }
4747 
4748 /// This determines which of three possible cases of a three source commute
4749 /// the source indexes correspond to taking into account any mask operands.
4750 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
4751 /// possible.
4752 /// Case 0 - Possible to commute the first and second operands.
4753 /// Case 1 - Possible to commute the first and third operands.
4754 /// Case 2 - Possible to commute the second and third operands.
4755 static int getThreeSrcCommuteCase(uint64_t TSFlags, unsigned SrcOpIdx1,
4756                                   unsigned SrcOpIdx2) {
4757   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
4758   if (SrcOpIdx1 > SrcOpIdx2)
4759     std::swap(SrcOpIdx1, SrcOpIdx2);
4760 
4761   unsigned Op1 = 1, Op2 = 2, Op3 = 3;
4762   if (X86II::isKMasked(TSFlags)) {
4763     // The k-mask operand cannot be commuted.
4764     if (SrcOpIdx1 == 2)
4765       return -1;
4766 
4767     // For k-zero-masked operations it is Ok to commute the first vector
4768     // operand.
4769     // For regular k-masked operations a conservative choice is done as the
4770     // elements of the first vector operand, for which the corresponding bit
4771     // in the k-mask operand is set to 0, are copied to the result of the
4772     // instruction.
4773     // TODO/FIXME: The commute still may be legal if it is known that the
4774     // k-mask operand is set to either all ones or all zeroes.
4775     // It is also Ok to commute the 1st operand if all users of MI use only
4776     // the elements enabled by the k-mask operand. For example,
4777     //   v4 = VFMADD213PSZrk v1, k, v2, v3; // v1[i] = k[i] ? v2[i]*v1[i]+v3[i]
4778     //                                                     : v1[i];
4779     //   VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 ->
4780     //                                  // Ok, to commute v1 in FMADD213PSZrk.
4781     if (X86II::isKMergeMasked(TSFlags) && SrcOpIdx1 == Op1)
4782       return -1;
4783     Op2++;
4784     Op3++;
4785   }
4786 
4787   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op2)
4788     return 0;
4789   if (SrcOpIdx1 == Op1 && SrcOpIdx2 == Op3)
4790     return 1;
4791   if (SrcOpIdx1 == Op2 && SrcOpIdx2 == Op3)
4792     return 2;
4793   return -1;
4794 }
4795 
4796 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
4797     const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2,
4798     const X86InstrFMA3Group &FMA3Group) const {
4799 
4800   unsigned Opc = MI.getOpcode();
4801 
4802   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
4803   if (SrcOpIdx1 > SrcOpIdx2)
4804     std::swap(SrcOpIdx1, SrcOpIdx2);
4805 
4806   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
4807   // analysis. The commute optimization is legal only if all users of FMA*_Int
4808   // use only the lowest element of the FMA*_Int instruction. Such analysis are
4809   // not implemented yet. So, just return 0 in that case.
4810   // When such analysis are available this place will be the right place for
4811   // calling it.
4812   if (FMA3Group.isIntrinsic() && SrcOpIdx1 == 1)
4813     return 0;
4814 
4815   // Determine which case this commute is or if it can't be done.
4816   int Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1, SrcOpIdx2);
4817   if (Case < 0)
4818     return 0;
4819 
4820   // Define the FMA forms mapping array that helps to map input FMA form
4821   // to output FMA form to preserve the operation semantics after
4822   // commuting the operands.
4823   const unsigned Form132Index = 0;
4824   const unsigned Form213Index = 1;
4825   const unsigned Form231Index = 2;
4826   static const unsigned FormMapping[][3] = {
4827     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
4828     // FMA132 A, C, b; ==> FMA231 C, A, b;
4829     // FMA213 B, A, c; ==> FMA213 A, B, c;
4830     // FMA231 C, A, b; ==> FMA132 A, C, b;
4831     { Form231Index, Form213Index, Form132Index },
4832     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
4833     // FMA132 A, c, B; ==> FMA132 B, c, A;
4834     // FMA213 B, a, C; ==> FMA231 C, a, B;
4835     // FMA231 C, a, B; ==> FMA213 B, a, C;
4836     { Form132Index, Form231Index, Form213Index },
4837     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
4838     // FMA132 a, C, B; ==> FMA213 a, B, C;
4839     // FMA213 b, A, C; ==> FMA132 b, C, A;
4840     // FMA231 c, A, B; ==> FMA231 c, B, A;
4841     { Form213Index, Form132Index, Form231Index }
4842   };
4843 
4844   unsigned FMAForms[3];
4845   if (FMA3Group.isRegOpcodeFromGroup(Opc)) {
4846     FMAForms[0] = FMA3Group.getReg132Opcode();
4847     FMAForms[1] = FMA3Group.getReg213Opcode();
4848     FMAForms[2] = FMA3Group.getReg231Opcode();
4849   } else {
4850     FMAForms[0] = FMA3Group.getMem132Opcode();
4851     FMAForms[1] = FMA3Group.getMem213Opcode();
4852     FMAForms[2] = FMA3Group.getMem231Opcode();
4853   }
4854   unsigned FormIndex;
4855   for (FormIndex = 0; FormIndex < 3; FormIndex++)
4856     if (Opc == FMAForms[FormIndex])
4857       break;
4858 
4859   // Everything is ready, just adjust the FMA opcode and return it.
4860   FormIndex = FormMapping[Case][FormIndex];
4861   return FMAForms[FormIndex];
4862 }
4863 
4864 static bool commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
4865                              unsigned SrcOpIdx2) {
4866   uint64_t TSFlags = MI.getDesc().TSFlags;
4867 
4868   // Determine which case this commute is or if it can't be done.
4869   int Case = getThreeSrcCommuteCase(TSFlags, SrcOpIdx1, SrcOpIdx2);
4870   if (Case < 0)
4871     return false;
4872 
4873   // For each case we need to swap two pairs of bits in the final immediate.
4874   static const uint8_t SwapMasks[3][4] = {
4875     { 0x04, 0x10, 0x08, 0x20 }, // Swap bits 2/4 and 3/5.
4876     { 0x02, 0x10, 0x08, 0x40 }, // Swap bits 1/4 and 3/6.
4877     { 0x02, 0x04, 0x20, 0x40 }, // Swap bits 1/2 and 5/6.
4878   };
4879 
4880   uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
4881   // Clear out the bits we are swapping.
4882   uint8_t NewImm = Imm & ~(SwapMasks[Case][0] | SwapMasks[Case][1] |
4883                            SwapMasks[Case][2] | SwapMasks[Case][3]);
4884   // If the immediate had a bit of the pair set, then set the opposite bit.
4885   if (Imm & SwapMasks[Case][0]) NewImm |= SwapMasks[Case][1];
4886   if (Imm & SwapMasks[Case][1]) NewImm |= SwapMasks[Case][0];
4887   if (Imm & SwapMasks[Case][2]) NewImm |= SwapMasks[Case][3];
4888   if (Imm & SwapMasks[Case][3]) NewImm |= SwapMasks[Case][2];
4889   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
4890 
4891   return true;
4892 }
4893 
4894 // Returns true if this is a VPERMI2 or VPERMT2 instrution that can be
4895 // commuted.
4896 static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
4897 #define VPERM_CASES(Suffix) \
4898   case X86::VPERMI2##Suffix##128rr:    case X86::VPERMT2##Suffix##128rr:    \
4899   case X86::VPERMI2##Suffix##256rr:    case X86::VPERMT2##Suffix##256rr:    \
4900   case X86::VPERMI2##Suffix##rr:       case X86::VPERMT2##Suffix##rr:       \
4901   case X86::VPERMI2##Suffix##128rm:    case X86::VPERMT2##Suffix##128rm:    \
4902   case X86::VPERMI2##Suffix##256rm:    case X86::VPERMT2##Suffix##256rm:    \
4903   case X86::VPERMI2##Suffix##rm:       case X86::VPERMT2##Suffix##rm:       \
4904   case X86::VPERMI2##Suffix##128rrkz:  case X86::VPERMT2##Suffix##128rrkz:  \
4905   case X86::VPERMI2##Suffix##256rrkz:  case X86::VPERMT2##Suffix##256rrkz:  \
4906   case X86::VPERMI2##Suffix##rrkz:     case X86::VPERMT2##Suffix##rrkz:     \
4907   case X86::VPERMI2##Suffix##128rmkz:  case X86::VPERMT2##Suffix##128rmkz:  \
4908   case X86::VPERMI2##Suffix##256rmkz:  case X86::VPERMT2##Suffix##256rmkz:  \
4909   case X86::VPERMI2##Suffix##rmkz:     case X86::VPERMT2##Suffix##rmkz:
4910 
4911 #define VPERM_CASES_BROADCAST(Suffix) \
4912   VPERM_CASES(Suffix) \
4913   case X86::VPERMI2##Suffix##128rmb:   case X86::VPERMT2##Suffix##128rmb:   \
4914   case X86::VPERMI2##Suffix##256rmb:   case X86::VPERMT2##Suffix##256rmb:   \
4915   case X86::VPERMI2##Suffix##rmb:      case X86::VPERMT2##Suffix##rmb:      \
4916   case X86::VPERMI2##Suffix##128rmbkz: case X86::VPERMT2##Suffix##128rmbkz: \
4917   case X86::VPERMI2##Suffix##256rmbkz: case X86::VPERMT2##Suffix##256rmbkz: \
4918   case X86::VPERMI2##Suffix##rmbkz:    case X86::VPERMT2##Suffix##rmbkz:
4919 
4920   switch (Opcode) {
4921   default: return false;
4922   VPERM_CASES(B)
4923   VPERM_CASES_BROADCAST(D)
4924   VPERM_CASES_BROADCAST(PD)
4925   VPERM_CASES_BROADCAST(PS)
4926   VPERM_CASES_BROADCAST(Q)
4927   VPERM_CASES(W)
4928     return true;
4929   }
4930 #undef VPERM_CASES_BROADCAST
4931 #undef VPERM_CASES
4932 }
4933 
4934 // Returns commuted opcode for VPERMI2 and VPERMT2 instructions by switching
4935 // from the I opcod to the T opcode and vice versa.
4936 static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
4937 #define VPERM_CASES(Orig, New) \
4938   case X86::Orig##128rr:    return X86::New##128rr;   \
4939   case X86::Orig##128rrkz:  return X86::New##128rrkz; \
4940   case X86::Orig##128rm:    return X86::New##128rm;   \
4941   case X86::Orig##128rmkz:  return X86::New##128rmkz; \
4942   case X86::Orig##256rr:    return X86::New##256rr;   \
4943   case X86::Orig##256rrkz:  return X86::New##256rrkz; \
4944   case X86::Orig##256rm:    return X86::New##256rm;   \
4945   case X86::Orig##256rmkz:  return X86::New##256rmkz; \
4946   case X86::Orig##rr:       return X86::New##rr;      \
4947   case X86::Orig##rrkz:     return X86::New##rrkz;    \
4948   case X86::Orig##rm:       return X86::New##rm;      \
4949   case X86::Orig##rmkz:     return X86::New##rmkz;
4950 
4951 #define VPERM_CASES_BROADCAST(Orig, New) \
4952   VPERM_CASES(Orig, New) \
4953   case X86::Orig##128rmb:   return X86::New##128rmb;   \
4954   case X86::Orig##128rmbkz: return X86::New##128rmbkz; \
4955   case X86::Orig##256rmb:   return X86::New##256rmb;   \
4956   case X86::Orig##256rmbkz: return X86::New##256rmbkz; \
4957   case X86::Orig##rmb:      return X86::New##rmb;      \
4958   case X86::Orig##rmbkz:    return X86::New##rmbkz;
4959 
4960   switch (Opcode) {
4961   VPERM_CASES(VPERMI2B, VPERMT2B)
4962   VPERM_CASES_BROADCAST(VPERMI2D,  VPERMT2D)
4963   VPERM_CASES_BROADCAST(VPERMI2PD, VPERMT2PD)
4964   VPERM_CASES_BROADCAST(VPERMI2PS, VPERMT2PS)
4965   VPERM_CASES_BROADCAST(VPERMI2Q,  VPERMT2Q)
4966   VPERM_CASES(VPERMI2W, VPERMT2W)
4967   VPERM_CASES(VPERMT2B, VPERMI2B)
4968   VPERM_CASES_BROADCAST(VPERMT2D,  VPERMI2D)
4969   VPERM_CASES_BROADCAST(VPERMT2PD, VPERMI2PD)
4970   VPERM_CASES_BROADCAST(VPERMT2PS, VPERMI2PS)
4971   VPERM_CASES_BROADCAST(VPERMT2Q,  VPERMI2Q)
4972   VPERM_CASES(VPERMT2W, VPERMI2W)
4973   }
4974 
4975   llvm_unreachable("Unreachable!");
4976 #undef VPERM_CASES_BROADCAST
4977 #undef VPERM_CASES
4978 }
4979 
4980 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
4981                                                    unsigned OpIdx1,
4982                                                    unsigned OpIdx2) const {
4983   auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
4984     if (NewMI)
4985       return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
4986     return MI;
4987   };
4988 
4989   switch (MI.getOpcode()) {
4990   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
4991   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
4992   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
4993   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
4994   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
4995   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
4996     unsigned Opc;
4997     unsigned Size;
4998     switch (MI.getOpcode()) {
4999     default: llvm_unreachable("Unreachable!");
5000     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
5001     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
5002     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
5003     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
5004     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
5005     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
5006     }
5007     unsigned Amt = MI.getOperand(3).getImm();
5008     auto &WorkingMI = cloneIfNew(MI);
5009     WorkingMI.setDesc(get(Opc));
5010     WorkingMI.getOperand(3).setImm(Size - Amt);
5011     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5012                                                    OpIdx1, OpIdx2);
5013   }
5014   case X86::PFSUBrr:
5015   case X86::PFSUBRrr: {
5016     // PFSUB  x, y: x = x - y
5017     // PFSUBR x, y: x = y - x
5018     unsigned Opc =
5019         (X86::PFSUBRrr == MI.getOpcode() ? X86::PFSUBrr : X86::PFSUBRrr);
5020     auto &WorkingMI = cloneIfNew(MI);
5021     WorkingMI.setDesc(get(Opc));
5022     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5023                                                    OpIdx1, OpIdx2);
5024     break;
5025   }
5026   case X86::BLENDPDrri:
5027   case X86::BLENDPSrri:
5028   case X86::PBLENDWrri:
5029   case X86::VBLENDPDrri:
5030   case X86::VBLENDPSrri:
5031   case X86::VBLENDPDYrri:
5032   case X86::VBLENDPSYrri:
5033   case X86::VPBLENDDrri:
5034   case X86::VPBLENDWrri:
5035   case X86::VPBLENDDYrri:
5036   case X86::VPBLENDWYrri:{
5037     unsigned Mask;
5038     switch (MI.getOpcode()) {
5039     default: llvm_unreachable("Unreachable!");
5040     case X86::BLENDPDrri:    Mask = 0x03; break;
5041     case X86::BLENDPSrri:    Mask = 0x0F; break;
5042     case X86::PBLENDWrri:    Mask = 0xFF; break;
5043     case X86::VBLENDPDrri:   Mask = 0x03; break;
5044     case X86::VBLENDPSrri:   Mask = 0x0F; break;
5045     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
5046     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
5047     case X86::VPBLENDDrri:   Mask = 0x0F; break;
5048     case X86::VPBLENDWrri:   Mask = 0xFF; break;
5049     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
5050     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
5051     }
5052     // Only the least significant bits of Imm are used.
5053     unsigned Imm = MI.getOperand(3).getImm() & Mask;
5054     auto &WorkingMI = cloneIfNew(MI);
5055     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
5056     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5057                                                    OpIdx1, OpIdx2);
5058   }
5059   case X86::MOVSDrr:
5060   case X86::MOVSSrr:
5061   case X86::VMOVSDrr:
5062   case X86::VMOVSSrr:{
5063     // On SSE41 or later we can commute a MOVSS/MOVSD to a BLENDPS/BLENDPD.
5064     if (!Subtarget.hasSSE41())
5065       return nullptr;
5066 
5067     unsigned Mask, Opc;
5068     switch (MI.getOpcode()) {
5069     default: llvm_unreachable("Unreachable!");
5070     case X86::MOVSDrr:  Opc = X86::BLENDPDrri;  Mask = 0x02; break;
5071     case X86::MOVSSrr:  Opc = X86::BLENDPSrri;  Mask = 0x0E; break;
5072     case X86::VMOVSDrr: Opc = X86::VBLENDPDrri; Mask = 0x02; break;
5073     case X86::VMOVSSrr: Opc = X86::VBLENDPSrri; Mask = 0x0E; break;
5074     }
5075 
5076     // MOVSD/MOVSS's 2nd operand is a FR64/FR32 reg class - we need to copy
5077     // this over to a VR128 class like the 1st operand to use a BLENDPD/BLENDPS.
5078     auto &MRI = MI.getParent()->getParent()->getRegInfo();
5079     auto VR128RC = MRI.getRegClass(MI.getOperand(1).getReg());
5080     unsigned VR128 = MRI.createVirtualRegister(VR128RC);
5081     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY),
5082             VR128)
5083         .addReg(MI.getOperand(2).getReg());
5084 
5085     auto &WorkingMI = cloneIfNew(MI);
5086     WorkingMI.setDesc(get(Opc));
5087     WorkingMI.getOperand(2).setReg(VR128);
5088     WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
5089     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5090                                                    OpIdx1, OpIdx2);
5091   }
5092   case X86::PCLMULQDQrr:
5093   case X86::VPCLMULQDQrr:{
5094     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
5095     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
5096     unsigned Imm = MI.getOperand(3).getImm();
5097     unsigned Src1Hi = Imm & 0x01;
5098     unsigned Src2Hi = Imm & 0x10;
5099     auto &WorkingMI = cloneIfNew(MI);
5100     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
5101     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5102                                                    OpIdx1, OpIdx2);
5103   }
5104   case X86::CMPSDrr:
5105   case X86::CMPSSrr:
5106   case X86::CMPPDrri:
5107   case X86::CMPPSrri:
5108   case X86::VCMPSDrr:
5109   case X86::VCMPSSrr:
5110   case X86::VCMPPDrri:
5111   case X86::VCMPPSrri:
5112   case X86::VCMPPDYrri:
5113   case X86::VCMPPSYrri:
5114   case X86::VCMPSDZrr:
5115   case X86::VCMPSSZrr:
5116   case X86::VCMPPDZrri:
5117   case X86::VCMPPSZrri:
5118   case X86::VCMPPDZ128rri:
5119   case X86::VCMPPSZ128rri:
5120   case X86::VCMPPDZ256rri:
5121   case X86::VCMPPSZ256rri: {
5122     // Float comparison can be safely commuted for
5123     // Ordered/Unordered/Equal/NotEqual tests
5124     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5125     switch (Imm) {
5126     case 0x00: // EQUAL
5127     case 0x03: // UNORDERED
5128     case 0x04: // NOT EQUAL
5129     case 0x07: // ORDERED
5130       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
5131     default:
5132       return nullptr;
5133     }
5134   }
5135   case X86::VPCMPBZ128rri: case X86::VPCMPUBZ128rri:
5136   case X86::VPCMPBZ256rri: case X86::VPCMPUBZ256rri:
5137   case X86::VPCMPBZrri:    case X86::VPCMPUBZrri:
5138   case X86::VPCMPDZ128rri: case X86::VPCMPUDZ128rri:
5139   case X86::VPCMPDZ256rri: case X86::VPCMPUDZ256rri:
5140   case X86::VPCMPDZrri:    case X86::VPCMPUDZrri:
5141   case X86::VPCMPQZ128rri: case X86::VPCMPUQZ128rri:
5142   case X86::VPCMPQZ256rri: case X86::VPCMPUQZ256rri:
5143   case X86::VPCMPQZrri:    case X86::VPCMPUQZrri:
5144   case X86::VPCMPWZ128rri: case X86::VPCMPUWZ128rri:
5145   case X86::VPCMPWZ256rri: case X86::VPCMPUWZ256rri:
5146   case X86::VPCMPWZrri:    case X86::VPCMPUWZrri: {
5147     // Flip comparison mode immediate (if necessary).
5148     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5149     switch (Imm) {
5150     default: llvm_unreachable("Unreachable!");
5151     case 0x01: Imm = 0x06; break; // LT  -> NLE
5152     case 0x02: Imm = 0x05; break; // LE  -> NLT
5153     case 0x05: Imm = 0x02; break; // NLT -> LE
5154     case 0x06: Imm = 0x01; break; // NLE -> LT
5155     case 0x00: // EQ
5156     case 0x03: // FALSE
5157     case 0x04: // NE
5158     case 0x07: // TRUE
5159       break;
5160     }
5161     auto &WorkingMI = cloneIfNew(MI);
5162     WorkingMI.getOperand(3).setImm(Imm);
5163     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5164                                                    OpIdx1, OpIdx2);
5165   }
5166   case X86::VPCOMBri: case X86::VPCOMUBri:
5167   case X86::VPCOMDri: case X86::VPCOMUDri:
5168   case X86::VPCOMQri: case X86::VPCOMUQri:
5169   case X86::VPCOMWri: case X86::VPCOMUWri: {
5170     // Flip comparison mode immediate (if necessary).
5171     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5172     switch (Imm) {
5173     default: llvm_unreachable("Unreachable!");
5174     case 0x00: Imm = 0x02; break; // LT -> GT
5175     case 0x01: Imm = 0x03; break; // LE -> GE
5176     case 0x02: Imm = 0x00; break; // GT -> LT
5177     case 0x03: Imm = 0x01; break; // GE -> LE
5178     case 0x04: // EQ
5179     case 0x05: // NE
5180     case 0x06: // FALSE
5181     case 0x07: // TRUE
5182       break;
5183     }
5184     auto &WorkingMI = cloneIfNew(MI);
5185     WorkingMI.getOperand(3).setImm(Imm);
5186     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5187                                                    OpIdx1, OpIdx2);
5188   }
5189   case X86::VPERM2F128rr:
5190   case X86::VPERM2I128rr: {
5191     // Flip permute source immediate.
5192     // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
5193     // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
5194     unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
5195     auto &WorkingMI = cloneIfNew(MI);
5196     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
5197     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5198                                                    OpIdx1, OpIdx2);
5199   }
5200   case X86::MOVHLPSrr:
5201   case X86::UNPCKHPDrr: {
5202     if (!Subtarget.hasSSE2())
5203       return nullptr;
5204 
5205     unsigned Opc = MI.getOpcode();
5206     switch (Opc) {
5207       default: llvm_unreachable("Unreachable!");
5208       case X86::MOVHLPSrr: Opc = X86::UNPCKHPDrr; break;
5209       case X86::UNPCKHPDrr: Opc = X86::MOVHLPSrr; break;
5210     }
5211     auto &WorkingMI = cloneIfNew(MI);
5212     WorkingMI.setDesc(get(Opc));
5213     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5214                                                    OpIdx1, OpIdx2);
5215   }
5216   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
5217   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
5218   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
5219   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
5220   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
5221   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
5222   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
5223   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
5224   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
5225   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
5226   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
5227   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
5228   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
5229   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
5230   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
5231   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
5232     unsigned Opc;
5233     switch (MI.getOpcode()) {
5234     default: llvm_unreachable("Unreachable!");
5235     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
5236     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
5237     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
5238     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
5239     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
5240     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
5241     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
5242     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
5243     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
5244     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
5245     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
5246     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
5247     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
5248     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
5249     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
5250     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
5251     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
5252     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
5253     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
5254     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
5255     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
5256     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
5257     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
5258     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
5259     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
5260     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
5261     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
5262     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
5263     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
5264     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
5265     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
5266     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
5267     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
5268     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
5269     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
5270     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
5271     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
5272     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
5273     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
5274     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
5275     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
5276     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
5277     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
5278     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
5279     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
5280     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
5281     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
5282     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
5283     }
5284     auto &WorkingMI = cloneIfNew(MI);
5285     WorkingMI.setDesc(get(Opc));
5286     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5287                                                    OpIdx1, OpIdx2);
5288   }
5289   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
5290   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
5291   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
5292   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
5293   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
5294   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
5295   case X86::VPTERNLOGDZrrik:     case X86::VPTERNLOGDZrmik:
5296   case X86::VPTERNLOGDZ128rrik:  case X86::VPTERNLOGDZ128rmik:
5297   case X86::VPTERNLOGDZ256rrik:  case X86::VPTERNLOGDZ256rmik:
5298   case X86::VPTERNLOGQZrrik:     case X86::VPTERNLOGQZrmik:
5299   case X86::VPTERNLOGQZ128rrik:  case X86::VPTERNLOGQZ128rmik:
5300   case X86::VPTERNLOGQZ256rrik:  case X86::VPTERNLOGQZ256rmik:
5301   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
5302   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
5303   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
5304   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
5305   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
5306   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz: {
5307     auto &WorkingMI = cloneIfNew(MI);
5308     if (!commuteVPTERNLOG(WorkingMI, OpIdx1, OpIdx2))
5309       return nullptr;
5310     return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5311                                                    OpIdx1, OpIdx2);
5312   }
5313   default: {
5314     if (isCommutableVPERMV3Instruction(MI.getOpcode())) {
5315       unsigned Opc = getCommutedVPERMV3Opcode(MI.getOpcode());
5316       auto &WorkingMI = cloneIfNew(MI);
5317       WorkingMI.setDesc(get(Opc));
5318       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5319                                                      OpIdx1, OpIdx2);
5320     }
5321 
5322     const X86InstrFMA3Group *FMA3Group =
5323         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
5324     if (FMA3Group) {
5325       unsigned Opc =
5326         getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2, *FMA3Group);
5327       if (Opc == 0)
5328         return nullptr;
5329       auto &WorkingMI = cloneIfNew(MI);
5330       WorkingMI.setDesc(get(Opc));
5331       return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
5332                                                      OpIdx1, OpIdx2);
5333     }
5334 
5335     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
5336   }
5337   }
5338 }
5339 
5340 bool X86InstrInfo::findFMA3CommutedOpIndices(
5341     const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2,
5342     const X86InstrFMA3Group &FMA3Group) const {
5343 
5344   if (!findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2))
5345     return false;
5346 
5347   // Check if we can adjust the opcode to preserve the semantics when
5348   // commute the register operands.
5349   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2, FMA3Group) != 0;
5350 }
5351 
5352 bool X86InstrInfo::findThreeSrcCommutedOpIndices(const MachineInstr &MI,
5353                                                  unsigned &SrcOpIdx1,
5354                                                  unsigned &SrcOpIdx2) const {
5355   uint64_t TSFlags = MI.getDesc().TSFlags;
5356 
5357   unsigned FirstCommutableVecOp = 1;
5358   unsigned LastCommutableVecOp = 3;
5359   unsigned KMaskOp = 0;
5360   if (X86II::isKMasked(TSFlags)) {
5361     // The k-mask operand has index = 2 for masked and zero-masked operations.
5362     KMaskOp = 2;
5363 
5364     // The operand with index = 1 is used as a source for those elements for
5365     // which the corresponding bit in the k-mask is set to 0.
5366     if (X86II::isKMergeMasked(TSFlags))
5367       FirstCommutableVecOp = 3;
5368 
5369     LastCommutableVecOp++;
5370   }
5371 
5372   if (isMem(MI, LastCommutableVecOp))
5373     LastCommutableVecOp--;
5374 
5375   // Only the first RegOpsNum operands are commutable.
5376   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
5377   // that the operand is not specified/fixed.
5378   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
5379       (SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp ||
5380        SrcOpIdx1 == KMaskOp))
5381     return false;
5382   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
5383       (SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp ||
5384        SrcOpIdx2 == KMaskOp))
5385     return false;
5386 
5387   // Look for two different register operands assumed to be commutable
5388   // regardless of the FMA opcode. The FMA opcode is adjusted later.
5389   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
5390       SrcOpIdx2 == CommuteAnyOperandIndex) {
5391     unsigned CommutableOpIdx1 = SrcOpIdx1;
5392     unsigned CommutableOpIdx2 = SrcOpIdx2;
5393 
5394     // At least one of operands to be commuted is not specified and
5395     // this method is free to choose appropriate commutable operands.
5396     if (SrcOpIdx1 == SrcOpIdx2)
5397       // Both of operands are not fixed. By default set one of commutable
5398       // operands to the last register operand of the instruction.
5399       CommutableOpIdx2 = LastCommutableVecOp;
5400     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
5401       // Only one of operands is not fixed.
5402       CommutableOpIdx2 = SrcOpIdx1;
5403 
5404     // CommutableOpIdx2 is well defined now. Let's choose another commutable
5405     // operand and assign its index to CommutableOpIdx1.
5406     unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
5407     for (CommutableOpIdx1 = LastCommutableVecOp;
5408          CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) {
5409       // Just ignore and skip the k-mask operand.
5410       if (CommutableOpIdx1 == KMaskOp)
5411         continue;
5412 
5413       // The commuted operands must have different registers.
5414       // Otherwise, the commute transformation does not change anything and
5415       // is useless then.
5416       if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
5417         break;
5418     }
5419 
5420     // No appropriate commutable operands were found.
5421     if (CommutableOpIdx1 < FirstCommutableVecOp)
5422       return false;
5423 
5424     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
5425     // to return those values.
5426     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
5427                               CommutableOpIdx1, CommutableOpIdx2))
5428       return false;
5429   }
5430 
5431   return true;
5432 }
5433 
5434 bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
5435                                          unsigned &SrcOpIdx2) const {
5436   const MCInstrDesc &Desc = MI.getDesc();
5437   if (!Desc.isCommutable())
5438     return false;
5439 
5440   switch (MI.getOpcode()) {
5441   case X86::CMPSDrr:
5442   case X86::CMPSSrr:
5443   case X86::CMPPDrri:
5444   case X86::CMPPSrri:
5445   case X86::VCMPSDrr:
5446   case X86::VCMPSSrr:
5447   case X86::VCMPPDrri:
5448   case X86::VCMPPSrri:
5449   case X86::VCMPPDYrri:
5450   case X86::VCMPPSYrri:
5451   case X86::VCMPSDZrr:
5452   case X86::VCMPSSZrr:
5453   case X86::VCMPPDZrri:
5454   case X86::VCMPPSZrri:
5455   case X86::VCMPPDZ128rri:
5456   case X86::VCMPPSZ128rri:
5457   case X86::VCMPPDZ256rri:
5458   case X86::VCMPPSZ256rri: {
5459     // Float comparison can be safely commuted for
5460     // Ordered/Unordered/Equal/NotEqual tests
5461     unsigned Imm = MI.getOperand(3).getImm() & 0x7;
5462     switch (Imm) {
5463     case 0x00: // EQUAL
5464     case 0x03: // UNORDERED
5465     case 0x04: // NOT EQUAL
5466     case 0x07: // ORDERED
5467       // The indices of the commutable operands are 1 and 2.
5468       // Assign them to the returned operand indices here.
5469       return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
5470     }
5471     return false;
5472   }
5473   case X86::MOVSDrr:
5474   case X86::MOVSSrr:
5475   case X86::VMOVSDrr:
5476   case X86::VMOVSSrr: {
5477     if (Subtarget.hasSSE41())
5478       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5479     return false;
5480   }
5481   case X86::VPTERNLOGDZrri:      case X86::VPTERNLOGDZrmi:
5482   case X86::VPTERNLOGDZ128rri:   case X86::VPTERNLOGDZ128rmi:
5483   case X86::VPTERNLOGDZ256rri:   case X86::VPTERNLOGDZ256rmi:
5484   case X86::VPTERNLOGQZrri:      case X86::VPTERNLOGQZrmi:
5485   case X86::VPTERNLOGQZ128rri:   case X86::VPTERNLOGQZ128rmi:
5486   case X86::VPTERNLOGQZ256rri:   case X86::VPTERNLOGQZ256rmi:
5487   case X86::VPTERNLOGDZrrik:     case X86::VPTERNLOGDZrmik:
5488   case X86::VPTERNLOGDZ128rrik:  case X86::VPTERNLOGDZ128rmik:
5489   case X86::VPTERNLOGDZ256rrik:  case X86::VPTERNLOGDZ256rmik:
5490   case X86::VPTERNLOGQZrrik:     case X86::VPTERNLOGQZrmik:
5491   case X86::VPTERNLOGQZ128rrik:  case X86::VPTERNLOGQZ128rmik:
5492   case X86::VPTERNLOGQZ256rrik:  case X86::VPTERNLOGQZ256rmik:
5493   case X86::VPTERNLOGDZrrikz:    case X86::VPTERNLOGDZrmikz:
5494   case X86::VPTERNLOGDZ128rrikz: case X86::VPTERNLOGDZ128rmikz:
5495   case X86::VPTERNLOGDZ256rrikz: case X86::VPTERNLOGDZ256rmikz:
5496   case X86::VPTERNLOGQZrrikz:    case X86::VPTERNLOGQZrmikz:
5497   case X86::VPTERNLOGQZ128rrikz: case X86::VPTERNLOGQZ128rmikz:
5498   case X86::VPTERNLOGQZ256rrikz: case X86::VPTERNLOGQZ256rmikz:
5499     return findThreeSrcCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5500   default:
5501     const X86InstrFMA3Group *FMA3Group =
5502         X86InstrFMA3Info::getFMA3Group(MI.getOpcode());
5503     if (FMA3Group)
5504       return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2, *FMA3Group);
5505 
5506     // Handled masked instructions since we need to skip over the mask input
5507     // and the preserved input.
5508     if (Desc.TSFlags & X86II::EVEX_K) {
5509       // First assume that the first input is the mask operand and skip past it.
5510       unsigned CommutableOpIdx1 = Desc.getNumDefs() + 1;
5511       unsigned CommutableOpIdx2 = Desc.getNumDefs() + 2;
5512       // Check if the first input is tied. If there isn't one then we only
5513       // need to skip the mask operand which we did above.
5514       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
5515                                              MCOI::TIED_TO) != -1)) {
5516         // If this is zero masking instruction with a tied operand, we need to
5517         // move the first index back to the first input since this must
5518         // be a 3 input instruction and we want the first two non-mask inputs.
5519         // Otherwise this is a 2 input instruction with a preserved input and
5520         // mask, so we need to move the indices to skip one more input.
5521         if (Desc.TSFlags & X86II::EVEX_Z)
5522           --CommutableOpIdx1;
5523         else {
5524           ++CommutableOpIdx1;
5525           ++CommutableOpIdx2;
5526         }
5527       }
5528 
5529       if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
5530                                 CommutableOpIdx1, CommutableOpIdx2))
5531         return false;
5532 
5533       if (!MI.getOperand(SrcOpIdx1).isReg() ||
5534           !MI.getOperand(SrcOpIdx2).isReg())
5535         // No idea.
5536         return false;
5537       return true;
5538     }
5539 
5540     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
5541   }
5542   return false;
5543 }
5544 
5545 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
5546   switch (BrOpc) {
5547   default: return X86::COND_INVALID;
5548   case X86::JE_1:  return X86::COND_E;
5549   case X86::JNE_1: return X86::COND_NE;
5550   case X86::JL_1:  return X86::COND_L;
5551   case X86::JLE_1: return X86::COND_LE;
5552   case X86::JG_1:  return X86::COND_G;
5553   case X86::JGE_1: return X86::COND_GE;
5554   case X86::JB_1:  return X86::COND_B;
5555   case X86::JBE_1: return X86::COND_BE;
5556   case X86::JA_1:  return X86::COND_A;
5557   case X86::JAE_1: return X86::COND_AE;
5558   case X86::JS_1:  return X86::COND_S;
5559   case X86::JNS_1: return X86::COND_NS;
5560   case X86::JP_1:  return X86::COND_P;
5561   case X86::JNP_1: return X86::COND_NP;
5562   case X86::JO_1:  return X86::COND_O;
5563   case X86::JNO_1: return X86::COND_NO;
5564   }
5565 }
5566 
5567 /// Return condition code of a SET opcode.
5568 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
5569   switch (Opc) {
5570   default: return X86::COND_INVALID;
5571   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
5572   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
5573   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
5574   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
5575   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
5576   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
5577   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
5578   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
5579   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
5580   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
5581   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
5582   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
5583   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
5584   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
5585   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
5586   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
5587   }
5588 }
5589 
5590 /// Return condition code of a CMov opcode.
5591 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
5592   switch (Opc) {
5593   default: return X86::COND_INVALID;
5594   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
5595   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
5596     return X86::COND_A;
5597   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
5598   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
5599     return X86::COND_AE;
5600   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
5601   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
5602     return X86::COND_B;
5603   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
5604   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
5605     return X86::COND_BE;
5606   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
5607   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
5608     return X86::COND_E;
5609   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
5610   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
5611     return X86::COND_G;
5612   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
5613   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
5614     return X86::COND_GE;
5615   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
5616   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
5617     return X86::COND_L;
5618   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
5619   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
5620     return X86::COND_LE;
5621   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
5622   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
5623     return X86::COND_NE;
5624   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
5625   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
5626     return X86::COND_NO;
5627   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
5628   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
5629     return X86::COND_NP;
5630   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
5631   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
5632     return X86::COND_NS;
5633   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
5634   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
5635     return X86::COND_O;
5636   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
5637   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
5638     return X86::COND_P;
5639   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
5640   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
5641     return X86::COND_S;
5642   }
5643 }
5644 
5645 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
5646   switch (CC) {
5647   default: llvm_unreachable("Illegal condition code!");
5648   case X86::COND_E:  return X86::JE_1;
5649   case X86::COND_NE: return X86::JNE_1;
5650   case X86::COND_L:  return X86::JL_1;
5651   case X86::COND_LE: return X86::JLE_1;
5652   case X86::COND_G:  return X86::JG_1;
5653   case X86::COND_GE: return X86::JGE_1;
5654   case X86::COND_B:  return X86::JB_1;
5655   case X86::COND_BE: return X86::JBE_1;
5656   case X86::COND_A:  return X86::JA_1;
5657   case X86::COND_AE: return X86::JAE_1;
5658   case X86::COND_S:  return X86::JS_1;
5659   case X86::COND_NS: return X86::JNS_1;
5660   case X86::COND_P:  return X86::JP_1;
5661   case X86::COND_NP: return X86::JNP_1;
5662   case X86::COND_O:  return X86::JO_1;
5663   case X86::COND_NO: return X86::JNO_1;
5664   }
5665 }
5666 
5667 /// Return the inverse of the specified condition,
5668 /// e.g. turning COND_E to COND_NE.
5669 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
5670   switch (CC) {
5671   default: llvm_unreachable("Illegal condition code!");
5672   case X86::COND_E:  return X86::COND_NE;
5673   case X86::COND_NE: return X86::COND_E;
5674   case X86::COND_L:  return X86::COND_GE;
5675   case X86::COND_LE: return X86::COND_G;
5676   case X86::COND_G:  return X86::COND_LE;
5677   case X86::COND_GE: return X86::COND_L;
5678   case X86::COND_B:  return X86::COND_AE;
5679   case X86::COND_BE: return X86::COND_A;
5680   case X86::COND_A:  return X86::COND_BE;
5681   case X86::COND_AE: return X86::COND_B;
5682   case X86::COND_S:  return X86::COND_NS;
5683   case X86::COND_NS: return X86::COND_S;
5684   case X86::COND_P:  return X86::COND_NP;
5685   case X86::COND_NP: return X86::COND_P;
5686   case X86::COND_O:  return X86::COND_NO;
5687   case X86::COND_NO: return X86::COND_O;
5688   case X86::COND_NE_OR_P:  return X86::COND_E_AND_NP;
5689   case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
5690   }
5691 }
5692 
5693 /// Assuming the flags are set by MI(a,b), return the condition code if we
5694 /// modify the instructions such that flags are set by MI(b,a).
5695 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
5696   switch (CC) {
5697   default: return X86::COND_INVALID;
5698   case X86::COND_E:  return X86::COND_E;
5699   case X86::COND_NE: return X86::COND_NE;
5700   case X86::COND_L:  return X86::COND_G;
5701   case X86::COND_LE: return X86::COND_GE;
5702   case X86::COND_G:  return X86::COND_L;
5703   case X86::COND_GE: return X86::COND_LE;
5704   case X86::COND_B:  return X86::COND_A;
5705   case X86::COND_BE: return X86::COND_AE;
5706   case X86::COND_A:  return X86::COND_B;
5707   case X86::COND_AE: return X86::COND_BE;
5708   }
5709 }
5710 
5711 /// Return a set opcode for the given condition and
5712 /// whether it has memory operand.
5713 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
5714   static const uint16_t Opc[16][2] = {
5715     { X86::SETAr,  X86::SETAm  },
5716     { X86::SETAEr, X86::SETAEm },
5717     { X86::SETBr,  X86::SETBm  },
5718     { X86::SETBEr, X86::SETBEm },
5719     { X86::SETEr,  X86::SETEm  },
5720     { X86::SETGr,  X86::SETGm  },
5721     { X86::SETGEr, X86::SETGEm },
5722     { X86::SETLr,  X86::SETLm  },
5723     { X86::SETLEr, X86::SETLEm },
5724     { X86::SETNEr, X86::SETNEm },
5725     { X86::SETNOr, X86::SETNOm },
5726     { X86::SETNPr, X86::SETNPm },
5727     { X86::SETNSr, X86::SETNSm },
5728     { X86::SETOr,  X86::SETOm  },
5729     { X86::SETPr,  X86::SETPm  },
5730     { X86::SETSr,  X86::SETSm  }
5731   };
5732 
5733   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
5734   return Opc[CC][HasMemoryOperand ? 1 : 0];
5735 }
5736 
5737 /// Return a cmov opcode for the given condition,
5738 /// register size in bytes, and operand type.
5739 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
5740                               bool HasMemoryOperand) {
5741   static const uint16_t Opc[32][3] = {
5742     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
5743     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
5744     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
5745     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
5746     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
5747     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
5748     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
5749     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
5750     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
5751     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
5752     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
5753     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
5754     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
5755     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
5756     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
5757     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
5758     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
5759     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
5760     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
5761     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
5762     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
5763     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
5764     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
5765     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
5766     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
5767     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
5768     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
5769     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
5770     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
5771     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
5772     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
5773     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
5774   };
5775 
5776   assert(CC < 16 && "Can only handle standard cond codes");
5777   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
5778   switch(RegBytes) {
5779   default: llvm_unreachable("Illegal register size!");
5780   case 2: return Opc[Idx][0];
5781   case 4: return Opc[Idx][1];
5782   case 8: return Opc[Idx][2];
5783   }
5784 }
5785 
5786 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
5787   if (!MI.isTerminator()) return false;
5788 
5789   // Conditional branch is a special case.
5790   if (MI.isBranch() && !MI.isBarrier())
5791     return true;
5792   if (!MI.isPredicable())
5793     return true;
5794   return !isPredicated(MI);
5795 }
5796 
5797 // Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
5798 // not be a fallthrough MBB now due to layout changes). Return nullptr if the
5799 // fallthrough MBB cannot be identified.
5800 static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
5801                                             MachineBasicBlock *TBB) {
5802   // Look for non-EHPad successors other than TBB. If we find exactly one, it
5803   // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
5804   // and fallthrough MBB. If we find more than one, we cannot identify the
5805   // fallthrough MBB and should return nullptr.
5806   MachineBasicBlock *FallthroughBB = nullptr;
5807   for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
5808     if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
5809       continue;
5810     // Return a nullptr if we found more than one fallthrough successor.
5811     if (FallthroughBB && FallthroughBB != TBB)
5812       return nullptr;
5813     FallthroughBB = *SI;
5814   }
5815   return FallthroughBB;
5816 }
5817 
5818 bool X86InstrInfo::AnalyzeBranchImpl(
5819     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
5820     SmallVectorImpl<MachineOperand> &Cond,
5821     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
5822 
5823   // Start from the bottom of the block and work up, examining the
5824   // terminator instructions.
5825   MachineBasicBlock::iterator I = MBB.end();
5826   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
5827   while (I != MBB.begin()) {
5828     --I;
5829     if (I->isDebugValue())
5830       continue;
5831 
5832     // Working from the bottom, when we see a non-terminator instruction, we're
5833     // done.
5834     if (!isUnpredicatedTerminator(*I))
5835       break;
5836 
5837     // A terminator that isn't a branch can't easily be handled by this
5838     // analysis.
5839     if (!I->isBranch())
5840       return true;
5841 
5842     // Handle unconditional branches.
5843     if (I->getOpcode() == X86::JMP_1) {
5844       UnCondBrIter = I;
5845 
5846       if (!AllowModify) {
5847         TBB = I->getOperand(0).getMBB();
5848         continue;
5849       }
5850 
5851       // If the block has any instructions after a JMP, delete them.
5852       while (std::next(I) != MBB.end())
5853         std::next(I)->eraseFromParent();
5854 
5855       Cond.clear();
5856       FBB = nullptr;
5857 
5858       // Delete the JMP if it's equivalent to a fall-through.
5859       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
5860         TBB = nullptr;
5861         I->eraseFromParent();
5862         I = MBB.end();
5863         UnCondBrIter = MBB.end();
5864         continue;
5865       }
5866 
5867       // TBB is used to indicate the unconditional destination.
5868       TBB = I->getOperand(0).getMBB();
5869       continue;
5870     }
5871 
5872     // Handle conditional branches.
5873     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
5874     if (BranchCode == X86::COND_INVALID)
5875       return true;  // Can't handle indirect branch.
5876 
5877     // Working from the bottom, handle the first conditional branch.
5878     if (Cond.empty()) {
5879       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
5880       if (AllowModify && UnCondBrIter != MBB.end() &&
5881           MBB.isLayoutSuccessor(TargetBB)) {
5882         // If we can modify the code and it ends in something like:
5883         //
5884         //     jCC L1
5885         //     jmp L2
5886         //   L1:
5887         //     ...
5888         //   L2:
5889         //
5890         // Then we can change this to:
5891         //
5892         //     jnCC L2
5893         //   L1:
5894         //     ...
5895         //   L2:
5896         //
5897         // Which is a bit more efficient.
5898         // We conditionally jump to the fall-through block.
5899         BranchCode = GetOppositeBranchCondition(BranchCode);
5900         unsigned JNCC = GetCondBranchFromCond(BranchCode);
5901         MachineBasicBlock::iterator OldInst = I;
5902 
5903         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
5904           .addMBB(UnCondBrIter->getOperand(0).getMBB());
5905         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
5906           .addMBB(TargetBB);
5907 
5908         OldInst->eraseFromParent();
5909         UnCondBrIter->eraseFromParent();
5910 
5911         // Restart the analysis.
5912         UnCondBrIter = MBB.end();
5913         I = MBB.end();
5914         continue;
5915       }
5916 
5917       FBB = TBB;
5918       TBB = I->getOperand(0).getMBB();
5919       Cond.push_back(MachineOperand::CreateImm(BranchCode));
5920       CondBranches.push_back(&*I);
5921       continue;
5922     }
5923 
5924     // Handle subsequent conditional branches. Only handle the case where all
5925     // conditional branches branch to the same destination and their condition
5926     // opcodes fit one of the special multi-branch idioms.
5927     assert(Cond.size() == 1);
5928     assert(TBB);
5929 
5930     // If the conditions are the same, we can leave them alone.
5931     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
5932     auto NewTBB = I->getOperand(0).getMBB();
5933     if (OldBranchCode == BranchCode && TBB == NewTBB)
5934       continue;
5935 
5936     // If they differ, see if they fit one of the known patterns. Theoretically,
5937     // we could handle more patterns here, but we shouldn't expect to see them
5938     // if instruction selection has done a reasonable job.
5939     if (TBB == NewTBB &&
5940                ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
5941                 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
5942       BranchCode = X86::COND_NE_OR_P;
5943     } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
5944                (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
5945       if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
5946         return true;
5947 
5948       // X86::COND_E_AND_NP usually has two different branch destinations.
5949       //
5950       // JP B1
5951       // JE B2
5952       // JMP B1
5953       // B1:
5954       // B2:
5955       //
5956       // Here this condition branches to B2 only if NP && E. It has another
5957       // equivalent form:
5958       //
5959       // JNE B1
5960       // JNP B2
5961       // JMP B1
5962       // B1:
5963       // B2:
5964       //
5965       // Similarly it branches to B2 only if E && NP. That is why this condition
5966       // is named with COND_E_AND_NP.
5967       BranchCode = X86::COND_E_AND_NP;
5968     } else
5969       return true;
5970 
5971     // Update the MachineOperand.
5972     Cond[0].setImm(BranchCode);
5973     CondBranches.push_back(&*I);
5974   }
5975 
5976   return false;
5977 }
5978 
5979 bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
5980                                  MachineBasicBlock *&TBB,
5981                                  MachineBasicBlock *&FBB,
5982                                  SmallVectorImpl<MachineOperand> &Cond,
5983                                  bool AllowModify) const {
5984   SmallVector<MachineInstr *, 4> CondBranches;
5985   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
5986 }
5987 
5988 bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB,
5989                                           MachineBranchPredicate &MBP,
5990                                           bool AllowModify) const {
5991   using namespace std::placeholders;
5992 
5993   SmallVector<MachineOperand, 4> Cond;
5994   SmallVector<MachineInstr *, 4> CondBranches;
5995   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
5996                         AllowModify))
5997     return true;
5998 
5999   if (Cond.size() != 1)
6000     return true;
6001 
6002   assert(MBP.TrueDest && "expected!");
6003 
6004   if (!MBP.FalseDest)
6005     MBP.FalseDest = MBB.getNextNode();
6006 
6007   const TargetRegisterInfo *TRI = &getRegisterInfo();
6008 
6009   MachineInstr *ConditionDef = nullptr;
6010   bool SingleUseCondition = true;
6011 
6012   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
6013     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
6014       ConditionDef = &*I;
6015       break;
6016     }
6017 
6018     if (I->readsRegister(X86::EFLAGS, TRI))
6019       SingleUseCondition = false;
6020   }
6021 
6022   if (!ConditionDef)
6023     return true;
6024 
6025   if (SingleUseCondition) {
6026     for (auto *Succ : MBB.successors())
6027       if (Succ->isLiveIn(X86::EFLAGS))
6028         SingleUseCondition = false;
6029   }
6030 
6031   MBP.ConditionDef = ConditionDef;
6032   MBP.SingleUseCondition = SingleUseCondition;
6033 
6034   // Currently we only recognize the simple pattern:
6035   //
6036   //   test %reg, %reg
6037   //   je %label
6038   //
6039   const unsigned TestOpcode =
6040       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
6041 
6042   if (ConditionDef->getOpcode() == TestOpcode &&
6043       ConditionDef->getNumOperands() == 3 &&
6044       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
6045       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
6046     MBP.LHS = ConditionDef->getOperand(0);
6047     MBP.RHS = MachineOperand::CreateImm(0);
6048     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
6049                         ? MachineBranchPredicate::PRED_NE
6050                         : MachineBranchPredicate::PRED_EQ;
6051     return false;
6052   }
6053 
6054   return true;
6055 }
6056 
6057 unsigned X86InstrInfo::removeBranch(MachineBasicBlock &MBB,
6058                                     int *BytesRemoved) const {
6059   assert(!BytesRemoved && "code size not handled");
6060 
6061   MachineBasicBlock::iterator I = MBB.end();
6062   unsigned Count = 0;
6063 
6064   while (I != MBB.begin()) {
6065     --I;
6066     if (I->isDebugValue())
6067       continue;
6068     if (I->getOpcode() != X86::JMP_1 &&
6069         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
6070       break;
6071     // Remove the branch.
6072     I->eraseFromParent();
6073     I = MBB.end();
6074     ++Count;
6075   }
6076 
6077   return Count;
6078 }
6079 
6080 unsigned X86InstrInfo::insertBranch(MachineBasicBlock &MBB,
6081                                     MachineBasicBlock *TBB,
6082                                     MachineBasicBlock *FBB,
6083                                     ArrayRef<MachineOperand> Cond,
6084                                     const DebugLoc &DL,
6085                                     int *BytesAdded) const {
6086   // Shouldn't be a fall through.
6087   assert(TBB && "insertBranch must not be told to insert a fallthrough");
6088   assert((Cond.size() == 1 || Cond.size() == 0) &&
6089          "X86 branch conditions have one component!");
6090   assert(!BytesAdded && "code size not handled");
6091 
6092   if (Cond.empty()) {
6093     // Unconditional branch?
6094     assert(!FBB && "Unconditional branch with multiple successors!");
6095     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
6096     return 1;
6097   }
6098 
6099   // If FBB is null, it is implied to be a fall-through block.
6100   bool FallThru = FBB == nullptr;
6101 
6102   // Conditional branch.
6103   unsigned Count = 0;
6104   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
6105   switch (CC) {
6106   case X86::COND_NE_OR_P:
6107     // Synthesize NE_OR_P with two branches.
6108     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
6109     ++Count;
6110     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
6111     ++Count;
6112     break;
6113   case X86::COND_E_AND_NP:
6114     // Use the next block of MBB as FBB if it is null.
6115     if (FBB == nullptr) {
6116       FBB = getFallThroughMBB(&MBB, TBB);
6117       assert(FBB && "MBB cannot be the last block in function when the false "
6118                     "body is a fall-through.");
6119     }
6120     // Synthesize COND_E_AND_NP with two branches.
6121     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
6122     ++Count;
6123     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
6124     ++Count;
6125     break;
6126   default: {
6127     unsigned Opc = GetCondBranchFromCond(CC);
6128     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
6129     ++Count;
6130   }
6131   }
6132   if (!FallThru) {
6133     // Two-way Conditional branch. Insert the second branch.
6134     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
6135     ++Count;
6136   }
6137   return Count;
6138 }
6139 
6140 bool X86InstrInfo::
6141 canInsertSelect(const MachineBasicBlock &MBB,
6142                 ArrayRef<MachineOperand> Cond,
6143                 unsigned TrueReg, unsigned FalseReg,
6144                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
6145   // Not all subtargets have cmov instructions.
6146   if (!Subtarget.hasCMov())
6147     return false;
6148   if (Cond.size() != 1)
6149     return false;
6150   // We cannot do the composite conditions, at least not in SSA form.
6151   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
6152     return false;
6153 
6154   // Check register classes.
6155   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
6156   const TargetRegisterClass *RC =
6157     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
6158   if (!RC)
6159     return false;
6160 
6161   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
6162   if (X86::GR16RegClass.hasSubClassEq(RC) ||
6163       X86::GR32RegClass.hasSubClassEq(RC) ||
6164       X86::GR64RegClass.hasSubClassEq(RC)) {
6165     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
6166     // Bridge. Probably Ivy Bridge as well.
6167     CondCycles = 2;
6168     TrueCycles = 2;
6169     FalseCycles = 2;
6170     return true;
6171   }
6172 
6173   // Can't do vectors.
6174   return false;
6175 }
6176 
6177 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
6178                                 MachineBasicBlock::iterator I,
6179                                 const DebugLoc &DL, unsigned DstReg,
6180                                 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
6181                                 unsigned FalseReg) const {
6182   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
6183   assert(Cond.size() == 1 && "Invalid Cond array");
6184   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
6185                                  MRI.getRegClass(DstReg)->getSize(),
6186                                  false /*HasMemoryOperand*/);
6187   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
6188 }
6189 
6190 /// Test if the given register is a physical h register.
6191 static bool isHReg(unsigned Reg) {
6192   return X86::GR8_ABCD_HRegClass.contains(Reg);
6193 }
6194 
6195 // Try and copy between VR128/VR64 and GR64 registers.
6196 static unsigned CopyToFromAsymmetricReg(unsigned &DestReg, unsigned &SrcReg,
6197                                         const X86Subtarget &Subtarget) {
6198   bool HasAVX = Subtarget.hasAVX();
6199   bool HasAVX512 = Subtarget.hasAVX512();
6200 
6201   // SrcReg(MaskReg) -> DestReg(GR64)
6202   // SrcReg(MaskReg) -> DestReg(GR32)
6203   // SrcReg(MaskReg) -> DestReg(GR16)
6204   // SrcReg(MaskReg) -> DestReg(GR8)
6205 
6206   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6207   if (X86::VK16RegClass.contains(SrcReg)) {
6208     if (X86::GR64RegClass.contains(DestReg)) {
6209       assert(Subtarget.hasBWI());
6210       return X86::KMOVQrk;
6211     }
6212     if (X86::GR32RegClass.contains(DestReg))
6213       return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk;
6214     if (X86::GR16RegClass.contains(DestReg)) {
6215       DestReg = getX86SubSuperRegister(DestReg, 32);
6216       return X86::KMOVWrk;
6217     }
6218     if (X86::GR8RegClass.contains(DestReg)) {
6219       DestReg = getX86SubSuperRegister(DestReg, 32);
6220       return Subtarget.hasDQI() ? X86::KMOVBrk : X86::KMOVWrk;
6221     }
6222   }
6223 
6224   // SrcReg(GR64) -> DestReg(MaskReg)
6225   // SrcReg(GR32) -> DestReg(MaskReg)
6226   // SrcReg(GR16) -> DestReg(MaskReg)
6227   // SrcReg(GR8)  -> DestReg(MaskReg)
6228 
6229   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6230   if (X86::VK16RegClass.contains(DestReg)) {
6231     if (X86::GR64RegClass.contains(SrcReg)) {
6232       assert(Subtarget.hasBWI());
6233       return X86::KMOVQkr;
6234     }
6235     if (X86::GR32RegClass.contains(SrcReg))
6236       return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr;
6237     if (X86::GR16RegClass.contains(SrcReg)) {
6238       SrcReg = getX86SubSuperRegister(SrcReg, 32);
6239       return X86::KMOVWkr;
6240     }
6241     if (X86::GR8RegClass.contains(SrcReg)) {
6242       SrcReg = getX86SubSuperRegister(SrcReg, 32);
6243       return Subtarget.hasDQI() ? X86::KMOVBkr : X86::KMOVWkr;
6244     }
6245   }
6246 
6247 
6248   // SrcReg(VR128) -> DestReg(GR64)
6249   // SrcReg(VR64)  -> DestReg(GR64)
6250   // SrcReg(GR64)  -> DestReg(VR128)
6251   // SrcReg(GR64)  -> DestReg(VR64)
6252 
6253   if (X86::GR64RegClass.contains(DestReg)) {
6254     if (X86::VR128XRegClass.contains(SrcReg))
6255       // Copy from a VR128 register to a GR64 register.
6256       return HasAVX512 ? X86::VMOVPQIto64Zrr :
6257              HasAVX    ? X86::VMOVPQIto64rr  :
6258                          X86::MOVPQIto64rr;
6259     if (X86::VR64RegClass.contains(SrcReg))
6260       // Copy from a VR64 register to a GR64 register.
6261       return X86::MMX_MOVD64from64rr;
6262   } else if (X86::GR64RegClass.contains(SrcReg)) {
6263     // Copy from a GR64 register to a VR128 register.
6264     if (X86::VR128XRegClass.contains(DestReg))
6265       return HasAVX512 ? X86::VMOV64toPQIZrr :
6266              HasAVX    ? X86::VMOV64toPQIrr  :
6267                          X86::MOV64toPQIrr;
6268     // Copy from a GR64 register to a VR64 register.
6269     if (X86::VR64RegClass.contains(DestReg))
6270       return X86::MMX_MOVD64to64rr;
6271   }
6272 
6273   // SrcReg(FR32) -> DestReg(GR32)
6274   // SrcReg(GR32) -> DestReg(FR32)
6275 
6276   if (X86::GR32RegClass.contains(DestReg) &&
6277       X86::FR32XRegClass.contains(SrcReg))
6278     // Copy from a FR32 register to a GR32 register.
6279     return HasAVX512 ? X86::VMOVSS2DIZrr :
6280            HasAVX    ? X86::VMOVSS2DIrr  :
6281                        X86::MOVSS2DIrr;
6282 
6283   if (X86::FR32XRegClass.contains(DestReg) &&
6284       X86::GR32RegClass.contains(SrcReg))
6285     // Copy from a GR32 register to a FR32 register.
6286     return HasAVX512 ? X86::VMOVDI2SSZrr :
6287            HasAVX    ? X86::VMOVDI2SSrr  :
6288                        X86::MOVDI2SSrr;
6289   return 0;
6290 }
6291 
6292 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
6293                                MachineBasicBlock::iterator MI,
6294                                const DebugLoc &DL, unsigned DestReg,
6295                                unsigned SrcReg, bool KillSrc) const {
6296   // First deal with the normal symmetric copies.
6297   bool HasAVX = Subtarget.hasAVX();
6298   bool HasVLX = Subtarget.hasVLX();
6299   unsigned Opc = 0;
6300   if (X86::GR64RegClass.contains(DestReg, SrcReg))
6301     Opc = X86::MOV64rr;
6302   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
6303     Opc = X86::MOV32rr;
6304   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
6305     Opc = X86::MOV16rr;
6306   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
6307     // Copying to or from a physical H register on x86-64 requires a NOREX
6308     // move.  Otherwise use a normal move.
6309     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
6310         Subtarget.is64Bit()) {
6311       Opc = X86::MOV8rr_NOREX;
6312       // Both operands must be encodable without an REX prefix.
6313       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
6314              "8-bit H register can not be copied outside GR8_NOREX");
6315     } else
6316       Opc = X86::MOV8rr;
6317   }
6318   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
6319     Opc = X86::MMX_MOVQ64rr;
6320   else if (X86::VR128XRegClass.contains(DestReg, SrcReg)) {
6321     if (HasVLX)
6322       Opc = X86::VMOVAPSZ128rr;
6323     else if (X86::VR128RegClass.contains(DestReg, SrcReg))
6324       Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
6325     else {
6326       // If this an extended register and we don't have VLX we need to use a
6327       // 512-bit move.
6328       Opc = X86::VMOVAPSZrr;
6329       const TargetRegisterInfo *TRI = &getRegisterInfo();
6330       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_xmm,
6331                                          &X86::VR512RegClass);
6332       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm,
6333                                         &X86::VR512RegClass);
6334     }
6335   } else if (X86::VR256XRegClass.contains(DestReg, SrcReg)) {
6336     if (HasVLX)
6337       Opc = X86::VMOVAPSZ256rr;
6338     else if (X86::VR256RegClass.contains(DestReg, SrcReg))
6339       Opc = X86::VMOVAPSYrr;
6340     else {
6341       // If this an extended register and we don't have VLX we need to use a
6342       // 512-bit move.
6343       Opc = X86::VMOVAPSZrr;
6344       const TargetRegisterInfo *TRI = &getRegisterInfo();
6345       DestReg = TRI->getMatchingSuperReg(DestReg, X86::sub_ymm,
6346                                          &X86::VR512RegClass);
6347       SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm,
6348                                         &X86::VR512RegClass);
6349     }
6350   } else if (X86::VR512RegClass.contains(DestReg, SrcReg))
6351     Opc = X86::VMOVAPSZrr;
6352   // All KMASK RegClasses hold the same k registers, can be tested against anyone.
6353   else if (X86::VK16RegClass.contains(DestReg, SrcReg))
6354     Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk;
6355   if (!Opc)
6356     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
6357 
6358   if (Opc) {
6359     BuildMI(MBB, MI, DL, get(Opc), DestReg)
6360       .addReg(SrcReg, getKillRegState(KillSrc));
6361     return;
6362   }
6363 
6364   bool FromEFLAGS = SrcReg == X86::EFLAGS;
6365   bool ToEFLAGS = DestReg == X86::EFLAGS;
6366   int Reg = FromEFLAGS ? DestReg : SrcReg;
6367   bool is32 = X86::GR32RegClass.contains(Reg);
6368   bool is64 = X86::GR64RegClass.contains(Reg);
6369 
6370   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
6371     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
6372     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
6373     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
6374     int Pop = is64 ? X86::POP64r : X86::POP32r;
6375     int PopF = is64 ? X86::POPF64 : X86::POPF32;
6376     int AX = is64 ? X86::RAX : X86::EAX;
6377 
6378     if (!Subtarget.hasLAHFSAHF()) {
6379       assert(Subtarget.is64Bit() &&
6380              "Not having LAHF/SAHF only happens on 64-bit.");
6381       // Moving EFLAGS to / from another register requires a push and a pop.
6382       // Notice that we have to adjust the stack if we don't want to clobber the
6383       // first frame index. See X86FrameLowering.cpp - usesTheStack.
6384       if (FromEFLAGS) {
6385         BuildMI(MBB, MI, DL, get(PushF));
6386         BuildMI(MBB, MI, DL, get(Pop), DestReg);
6387       }
6388       if (ToEFLAGS) {
6389         BuildMI(MBB, MI, DL, get(Push))
6390             .addReg(SrcReg, getKillRegState(KillSrc));
6391         BuildMI(MBB, MI, DL, get(PopF));
6392       }
6393       return;
6394     }
6395 
6396     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
6397     // inefficient. Instead:
6398     //   - Save the overflow flag OF into AL using SETO, and restore it using a
6399     //     signed 8-bit addition of AL and INT8_MAX.
6400     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
6401     //     using LAHF/SAHF.
6402     //   - When RAX/EAX is live and isn't the destination register, make sure it
6403     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
6404     //     the flags.
6405     // This approach is ~2.25x faster than using PUSHF/POPF.
6406     //
6407     // This is still somewhat inefficient because we don't know which flags are
6408     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
6409     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
6410     //
6411     // PUSHF/POPF is also potentially incorrect because it affects other flags
6412     // such as TF/IF/DF, which LLVM doesn't model.
6413     //
6414     // Notice that we have to adjust the stack if we don't want to clobber the
6415     // first frame index.
6416     // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
6417 
6418     const TargetRegisterInfo *TRI = &getRegisterInfo();
6419     MachineBasicBlock::LivenessQueryResult LQR =
6420         MBB.computeRegisterLiveness(TRI, AX, MI);
6421     // We do not want to save and restore AX if we do not have to.
6422     // Moreover, if we do so whereas AX is dead, we would need to set
6423     // an undef flag on the use of AX, otherwise the verifier will
6424     // complain that we read an undef value.
6425     // We do not want to change the behavior of the machine verifier
6426     // as this is usually wrong to read an undef value.
6427     if (MachineBasicBlock::LQR_Unknown == LQR) {
6428       LivePhysRegs LPR(TRI);
6429       LPR.addLiveOuts(MBB);
6430       MachineBasicBlock::iterator I = MBB.end();
6431       while (I != MI) {
6432         --I;
6433         LPR.stepBackward(*I);
6434       }
6435       // AX contains the top most register in the aliasing hierarchy.
6436       // It may not be live, but one of its aliases may be.
6437       for (MCRegAliasIterator AI(AX, TRI, true);
6438            AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
6439         LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
6440                                 : MachineBasicBlock::LQR_Dead;
6441     }
6442     bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
6443     if (!AXDead)
6444       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
6445     if (FromEFLAGS) {
6446       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
6447       BuildMI(MBB, MI, DL, get(X86::LAHF));
6448       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
6449     }
6450     if (ToEFLAGS) {
6451       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
6452       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
6453           .addReg(X86::AL)
6454           .addImm(INT8_MAX);
6455       BuildMI(MBB, MI, DL, get(X86::SAHF));
6456     }
6457     if (!AXDead)
6458       BuildMI(MBB, MI, DL, get(Pop), AX);
6459     return;
6460   }
6461 
6462   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
6463                << " to " << RI.getName(DestReg) << '\n');
6464   llvm_unreachable("Cannot emit physreg copy instruction");
6465 }
6466 
6467 static unsigned getLoadStoreRegOpcode(unsigned Reg,
6468                                       const TargetRegisterClass *RC,
6469                                       bool isStackAligned,
6470                                       const X86Subtarget &STI,
6471                                       bool load) {
6472   bool HasAVX = STI.hasAVX();
6473   bool HasAVX512 = STI.hasAVX512();
6474   bool HasVLX = STI.hasVLX();
6475 
6476   switch (RC->getSize()) {
6477   default:
6478     llvm_unreachable("Unknown spill size");
6479   case 1:
6480     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
6481     if (STI.is64Bit())
6482       // Copying to or from a physical H register on x86-64 requires a NOREX
6483       // move.  Otherwise use a normal move.
6484       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
6485         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
6486     return load ? X86::MOV8rm : X86::MOV8mr;
6487   case 2:
6488     if (X86::VK16RegClass.hasSubClassEq(RC))
6489       return load ? X86::KMOVWkm : X86::KMOVWmk;
6490     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
6491     return load ? X86::MOV16rm : X86::MOV16mr;
6492   case 4:
6493     if (X86::GR32RegClass.hasSubClassEq(RC))
6494       return load ? X86::MOV32rm : X86::MOV32mr;
6495     if (X86::FR32XRegClass.hasSubClassEq(RC))
6496       return load ?
6497         (HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
6498         (HasAVX512 ? X86::VMOVSSZmr : HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
6499     if (X86::RFP32RegClass.hasSubClassEq(RC))
6500       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
6501     if (X86::VK32RegClass.hasSubClassEq(RC))
6502       return load ? X86::KMOVDkm : X86::KMOVDmk;
6503     llvm_unreachable("Unknown 4-byte regclass");
6504   case 8:
6505     if (X86::GR64RegClass.hasSubClassEq(RC))
6506       return load ? X86::MOV64rm : X86::MOV64mr;
6507     if (X86::FR64XRegClass.hasSubClassEq(RC))
6508       return load ?
6509         (HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
6510         (HasAVX512 ? X86::VMOVSDZmr : HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
6511     if (X86::VR64RegClass.hasSubClassEq(RC))
6512       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
6513     if (X86::RFP64RegClass.hasSubClassEq(RC))
6514       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
6515     if (X86::VK64RegClass.hasSubClassEq(RC))
6516       return load ? X86::KMOVQkm : X86::KMOVQmk;
6517     llvm_unreachable("Unknown 8-byte regclass");
6518   case 10:
6519     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
6520     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
6521   case 16: {
6522     assert(X86::VR128XRegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
6523     // If stack is realigned we can use aligned stores.
6524     if (isStackAligned)
6525       return load ?
6526         (HasVLX    ? X86::VMOVAPSZ128rm :
6527          HasAVX512 ? X86::VMOVAPSZ128rm_NOVLX :
6528          HasAVX    ? X86::VMOVAPSrm :
6529                      X86::MOVAPSrm):
6530         (HasVLX    ? X86::VMOVAPSZ128mr :
6531          HasAVX512 ? X86::VMOVAPSZ128mr_NOVLX :
6532          HasAVX    ? X86::VMOVAPSmr :
6533                      X86::MOVAPSmr);
6534     else
6535       return load ?
6536         (HasVLX    ? X86::VMOVUPSZ128rm :
6537          HasAVX512 ? X86::VMOVUPSZ128rm_NOVLX :
6538          HasAVX    ? X86::VMOVUPSrm :
6539                      X86::MOVUPSrm):
6540         (HasVLX    ? X86::VMOVUPSZ128mr :
6541          HasAVX512 ? X86::VMOVUPSZ128mr_NOVLX :
6542          HasAVX    ? X86::VMOVUPSmr :
6543                      X86::MOVUPSmr);
6544   }
6545   case 32:
6546     assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
6547     // If stack is realigned we can use aligned stores.
6548     if (isStackAligned)
6549       return load ?
6550         (HasVLX    ? X86::VMOVAPSZ256rm :
6551          HasAVX512 ? X86::VMOVAPSZ256rm_NOVLX :
6552                      X86::VMOVAPSYrm) :
6553         (HasVLX    ? X86::VMOVAPSZ256mr :
6554          HasAVX512 ? X86::VMOVAPSZ256mr_NOVLX :
6555                      X86::VMOVAPSYmr);
6556     else
6557       return load ?
6558         (HasVLX    ? X86::VMOVUPSZ256rm :
6559          HasAVX512 ? X86::VMOVUPSZ256rm_NOVLX :
6560                      X86::VMOVUPSYrm) :
6561         (HasVLX    ? X86::VMOVUPSZ256mr :
6562          HasAVX512 ? X86::VMOVUPSZ256mr_NOVLX :
6563                      X86::VMOVUPSYmr);
6564   case 64:
6565     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
6566     assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
6567     if (isStackAligned)
6568       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
6569     else
6570       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
6571   }
6572 }
6573 
6574 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
6575                                          int64_t &Offset,
6576                                          const TargetRegisterInfo *TRI) const {
6577   const MCInstrDesc &Desc = MemOp.getDesc();
6578   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
6579   if (MemRefBegin < 0)
6580     return false;
6581 
6582   MemRefBegin += X86II::getOperandBias(Desc);
6583 
6584   MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
6585   if (!BaseMO.isReg()) // Can be an MO_FrameIndex
6586     return false;
6587 
6588   BaseReg = BaseMO.getReg();
6589   if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
6590     return false;
6591 
6592   if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
6593       X86::NoRegister)
6594     return false;
6595 
6596   const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
6597 
6598   // Displacement can be symbolic
6599   if (!DispMO.isImm())
6600     return false;
6601 
6602   Offset = DispMO.getImm();
6603 
6604   return true;
6605 }
6606 
6607 static unsigned getStoreRegOpcode(unsigned SrcReg,
6608                                   const TargetRegisterClass *RC,
6609                                   bool isStackAligned,
6610                                   const X86Subtarget &STI) {
6611   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
6612 }
6613 
6614 
6615 static unsigned getLoadRegOpcode(unsigned DestReg,
6616                                  const TargetRegisterClass *RC,
6617                                  bool isStackAligned,
6618                                  const X86Subtarget &STI) {
6619   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
6620 }
6621 
6622 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
6623                                        MachineBasicBlock::iterator MI,
6624                                        unsigned SrcReg, bool isKill, int FrameIdx,
6625                                        const TargetRegisterClass *RC,
6626                                        const TargetRegisterInfo *TRI) const {
6627   const MachineFunction &MF = *MBB.getParent();
6628   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= RC->getSize() &&
6629          "Stack slot too small for store");
6630   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
6631   bool isAligned =
6632       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
6633       RI.canRealignStack(MF);
6634   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
6635   DebugLoc DL = MBB.findDebugLoc(MI);
6636   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
6637     .addReg(SrcReg, getKillRegState(isKill));
6638 }
6639 
6640 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
6641                                   bool isKill,
6642                                   SmallVectorImpl<MachineOperand> &Addr,
6643                                   const TargetRegisterClass *RC,
6644                                   MachineInstr::mmo_iterator MMOBegin,
6645                                   MachineInstr::mmo_iterator MMOEnd,
6646                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
6647   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
6648   bool isAligned = MMOBegin != MMOEnd &&
6649                    (*MMOBegin)->getAlignment() >= Alignment;
6650   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
6651   DebugLoc DL;
6652   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
6653   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
6654     MIB.add(Addr[i]);
6655   MIB.addReg(SrcReg, getKillRegState(isKill));
6656   (*MIB).setMemRefs(MMOBegin, MMOEnd);
6657   NewMIs.push_back(MIB);
6658 }
6659 
6660 
6661 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
6662                                         MachineBasicBlock::iterator MI,
6663                                         unsigned DestReg, int FrameIdx,
6664                                         const TargetRegisterClass *RC,
6665                                         const TargetRegisterInfo *TRI) const {
6666   const MachineFunction &MF = *MBB.getParent();
6667   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
6668   bool isAligned =
6669       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
6670       RI.canRealignStack(MF);
6671   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
6672   DebugLoc DL = MBB.findDebugLoc(MI);
6673   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
6674 }
6675 
6676 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
6677                                  SmallVectorImpl<MachineOperand> &Addr,
6678                                  const TargetRegisterClass *RC,
6679                                  MachineInstr::mmo_iterator MMOBegin,
6680                                  MachineInstr::mmo_iterator MMOEnd,
6681                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
6682   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
6683   bool isAligned = MMOBegin != MMOEnd &&
6684                    (*MMOBegin)->getAlignment() >= Alignment;
6685   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
6686   DebugLoc DL;
6687   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
6688   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
6689     MIB.add(Addr[i]);
6690   (*MIB).setMemRefs(MMOBegin, MMOEnd);
6691   NewMIs.push_back(MIB);
6692 }
6693 
6694 bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
6695                                   unsigned &SrcReg2, int &CmpMask,
6696                                   int &CmpValue) const {
6697   switch (MI.getOpcode()) {
6698   default: break;
6699   case X86::CMP64ri32:
6700   case X86::CMP64ri8:
6701   case X86::CMP32ri:
6702   case X86::CMP32ri8:
6703   case X86::CMP16ri:
6704   case X86::CMP16ri8:
6705   case X86::CMP8ri:
6706     SrcReg = MI.getOperand(0).getReg();
6707     SrcReg2 = 0;
6708     if (MI.getOperand(1).isImm()) {
6709       CmpMask = ~0;
6710       CmpValue = MI.getOperand(1).getImm();
6711     } else {
6712       CmpMask = CmpValue = 0;
6713     }
6714     return true;
6715   // A SUB can be used to perform comparison.
6716   case X86::SUB64rm:
6717   case X86::SUB32rm:
6718   case X86::SUB16rm:
6719   case X86::SUB8rm:
6720     SrcReg = MI.getOperand(1).getReg();
6721     SrcReg2 = 0;
6722     CmpMask = 0;
6723     CmpValue = 0;
6724     return true;
6725   case X86::SUB64rr:
6726   case X86::SUB32rr:
6727   case X86::SUB16rr:
6728   case X86::SUB8rr:
6729     SrcReg = MI.getOperand(1).getReg();
6730     SrcReg2 = MI.getOperand(2).getReg();
6731     CmpMask = 0;
6732     CmpValue = 0;
6733     return true;
6734   case X86::SUB64ri32:
6735   case X86::SUB64ri8:
6736   case X86::SUB32ri:
6737   case X86::SUB32ri8:
6738   case X86::SUB16ri:
6739   case X86::SUB16ri8:
6740   case X86::SUB8ri:
6741     SrcReg = MI.getOperand(1).getReg();
6742     SrcReg2 = 0;
6743     if (MI.getOperand(2).isImm()) {
6744       CmpMask = ~0;
6745       CmpValue = MI.getOperand(2).getImm();
6746     } else {
6747       CmpMask = CmpValue = 0;
6748     }
6749     return true;
6750   case X86::CMP64rr:
6751   case X86::CMP32rr:
6752   case X86::CMP16rr:
6753   case X86::CMP8rr:
6754     SrcReg = MI.getOperand(0).getReg();
6755     SrcReg2 = MI.getOperand(1).getReg();
6756     CmpMask = 0;
6757     CmpValue = 0;
6758     return true;
6759   case X86::TEST8rr:
6760   case X86::TEST16rr:
6761   case X86::TEST32rr:
6762   case X86::TEST64rr:
6763     SrcReg = MI.getOperand(0).getReg();
6764     if (MI.getOperand(1).getReg() != SrcReg)
6765       return false;
6766     // Compare against zero.
6767     SrcReg2 = 0;
6768     CmpMask = ~0;
6769     CmpValue = 0;
6770     return true;
6771   }
6772   return false;
6773 }
6774 
6775 /// Check whether the first instruction, whose only
6776 /// purpose is to update flags, can be made redundant.
6777 /// CMPrr can be made redundant by SUBrr if the operands are the same.
6778 /// This function can be extended later on.
6779 /// SrcReg, SrcRegs: register operands for FlagI.
6780 /// ImmValue: immediate for FlagI if it takes an immediate.
6781 inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
6782                                         unsigned SrcReg2, int ImmMask,
6783                                         int ImmValue, MachineInstr &OI) {
6784   if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
6785        (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
6786        (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
6787        (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
6788       ((OI.getOperand(1).getReg() == SrcReg &&
6789         OI.getOperand(2).getReg() == SrcReg2) ||
6790        (OI.getOperand(1).getReg() == SrcReg2 &&
6791         OI.getOperand(2).getReg() == SrcReg)))
6792     return true;
6793 
6794   if (ImmMask != 0 &&
6795       ((FlagI.getOpcode() == X86::CMP64ri32 &&
6796         OI.getOpcode() == X86::SUB64ri32) ||
6797        (FlagI.getOpcode() == X86::CMP64ri8 &&
6798         OI.getOpcode() == X86::SUB64ri8) ||
6799        (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
6800        (FlagI.getOpcode() == X86::CMP32ri8 &&
6801         OI.getOpcode() == X86::SUB32ri8) ||
6802        (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
6803        (FlagI.getOpcode() == X86::CMP16ri8 &&
6804         OI.getOpcode() == X86::SUB16ri8) ||
6805        (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
6806       OI.getOperand(1).getReg() == SrcReg &&
6807       OI.getOperand(2).getImm() == ImmValue)
6808     return true;
6809   return false;
6810 }
6811 
6812 /// Check whether the definition can be converted
6813 /// to remove a comparison against zero.
6814 inline static bool isDefConvertible(MachineInstr &MI) {
6815   switch (MI.getOpcode()) {
6816   default: return false;
6817 
6818   // The shift instructions only modify ZF if their shift count is non-zero.
6819   // N.B.: The processor truncates the shift count depending on the encoding.
6820   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
6821   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
6822      return getTruncatedShiftCount(MI, 2) != 0;
6823 
6824   // Some left shift instructions can be turned into LEA instructions but only
6825   // if their flags aren't used. Avoid transforming such instructions.
6826   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
6827     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
6828     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
6829     return ShAmt != 0;
6830   }
6831 
6832   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
6833   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
6834      return getTruncatedShiftCount(MI, 3) != 0;
6835 
6836   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
6837   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
6838   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
6839   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
6840   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
6841   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
6842   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
6843   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
6844   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
6845   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
6846   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
6847   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
6848   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
6849   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
6850   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
6851   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
6852   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
6853   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
6854   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
6855   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
6856   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
6857   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
6858   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
6859   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
6860   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
6861   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
6862   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
6863   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
6864   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
6865   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
6866   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
6867   case X86::ADC32ri:   case X86::ADC32ri8:
6868   case X86::ADC32rr:   case X86::ADC64ri32:
6869   case X86::ADC64ri8:  case X86::ADC64rr:
6870   case X86::SBB32ri:   case X86::SBB32ri8:
6871   case X86::SBB32rr:   case X86::SBB64ri32:
6872   case X86::SBB64ri8:  case X86::SBB64rr:
6873   case X86::ANDN32rr:  case X86::ANDN32rm:
6874   case X86::ANDN64rr:  case X86::ANDN64rm:
6875   case X86::BEXTR32rr: case X86::BEXTR64rr:
6876   case X86::BEXTR32rm: case X86::BEXTR64rm:
6877   case X86::BLSI32rr:  case X86::BLSI32rm:
6878   case X86::BLSI64rr:  case X86::BLSI64rm:
6879   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
6880   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
6881   case X86::BLSR32rr:  case X86::BLSR32rm:
6882   case X86::BLSR64rr:  case X86::BLSR64rm:
6883   case X86::BZHI32rr:  case X86::BZHI32rm:
6884   case X86::BZHI64rr:  case X86::BZHI64rm:
6885   case X86::LZCNT16rr: case X86::LZCNT16rm:
6886   case X86::LZCNT32rr: case X86::LZCNT32rm:
6887   case X86::LZCNT64rr: case X86::LZCNT64rm:
6888   case X86::POPCNT16rr:case X86::POPCNT16rm:
6889   case X86::POPCNT32rr:case X86::POPCNT32rm:
6890   case X86::POPCNT64rr:case X86::POPCNT64rm:
6891   case X86::TZCNT16rr: case X86::TZCNT16rm:
6892   case X86::TZCNT32rr: case X86::TZCNT32rm:
6893   case X86::TZCNT64rr: case X86::TZCNT64rm:
6894     return true;
6895   }
6896 }
6897 
6898 /// Check whether the use can be converted to remove a comparison against zero.
6899 static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
6900   switch (MI.getOpcode()) {
6901   default: return X86::COND_INVALID;
6902   case X86::LZCNT16rr: case X86::LZCNT16rm:
6903   case X86::LZCNT32rr: case X86::LZCNT32rm:
6904   case X86::LZCNT64rr: case X86::LZCNT64rm:
6905     return X86::COND_B;
6906   case X86::POPCNT16rr:case X86::POPCNT16rm:
6907   case X86::POPCNT32rr:case X86::POPCNT32rm:
6908   case X86::POPCNT64rr:case X86::POPCNT64rm:
6909     return X86::COND_E;
6910   case X86::TZCNT16rr: case X86::TZCNT16rm:
6911   case X86::TZCNT32rr: case X86::TZCNT32rm:
6912   case X86::TZCNT64rr: case X86::TZCNT64rm:
6913     return X86::COND_B;
6914   }
6915 }
6916 
6917 /// Check if there exists an earlier instruction that
6918 /// operates on the same source operands and sets flags in the same way as
6919 /// Compare; remove Compare if possible.
6920 bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
6921                                         unsigned SrcReg2, int CmpMask,
6922                                         int CmpValue,
6923                                         const MachineRegisterInfo *MRI) const {
6924   // Check whether we can replace SUB with CMP.
6925   unsigned NewOpcode = 0;
6926   switch (CmpInstr.getOpcode()) {
6927   default: break;
6928   case X86::SUB64ri32:
6929   case X86::SUB64ri8:
6930   case X86::SUB32ri:
6931   case X86::SUB32ri8:
6932   case X86::SUB16ri:
6933   case X86::SUB16ri8:
6934   case X86::SUB8ri:
6935   case X86::SUB64rm:
6936   case X86::SUB32rm:
6937   case X86::SUB16rm:
6938   case X86::SUB8rm:
6939   case X86::SUB64rr:
6940   case X86::SUB32rr:
6941   case X86::SUB16rr:
6942   case X86::SUB8rr: {
6943     if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
6944       return false;
6945     // There is no use of the destination register, we can replace SUB with CMP.
6946     switch (CmpInstr.getOpcode()) {
6947     default: llvm_unreachable("Unreachable!");
6948     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
6949     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
6950     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
6951     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
6952     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
6953     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
6954     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
6955     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
6956     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
6957     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
6958     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
6959     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
6960     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
6961     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
6962     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
6963     }
6964     CmpInstr.setDesc(get(NewOpcode));
6965     CmpInstr.RemoveOperand(0);
6966     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
6967     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
6968         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
6969       return false;
6970   }
6971   }
6972 
6973   // Get the unique definition of SrcReg.
6974   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
6975   if (!MI) return false;
6976 
6977   // CmpInstr is the first instruction of the BB.
6978   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
6979 
6980   // If we are comparing against zero, check whether we can use MI to update
6981   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
6982   bool IsCmpZero = (CmpMask != 0 && CmpValue == 0);
6983   if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
6984     return false;
6985 
6986   // If we have a use of the source register between the def and our compare
6987   // instruction we can eliminate the compare iff the use sets EFLAGS in the
6988   // right way.
6989   bool ShouldUpdateCC = false;
6990   X86::CondCode NewCC = X86::COND_INVALID;
6991   if (IsCmpZero && !isDefConvertible(*MI)) {
6992     // Scan forward from the use until we hit the use we're looking for or the
6993     // compare instruction.
6994     for (MachineBasicBlock::iterator J = MI;; ++J) {
6995       // Do we have a convertible instruction?
6996       NewCC = isUseDefConvertible(*J);
6997       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
6998           J->getOperand(1).getReg() == SrcReg) {
6999         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
7000         ShouldUpdateCC = true; // Update CC later on.
7001         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
7002         // with the new def.
7003         Def = J;
7004         MI = &*Def;
7005         break;
7006       }
7007 
7008       if (J == I)
7009         return false;
7010     }
7011   }
7012 
7013   // We are searching for an earlier instruction that can make CmpInstr
7014   // redundant and that instruction will be saved in Sub.
7015   MachineInstr *Sub = nullptr;
7016   const TargetRegisterInfo *TRI = &getRegisterInfo();
7017 
7018   // We iterate backward, starting from the instruction before CmpInstr and
7019   // stop when reaching the definition of a source register or done with the BB.
7020   // RI points to the instruction before CmpInstr.
7021   // If the definition is in this basic block, RE points to the definition;
7022   // otherwise, RE is the rend of the basic block.
7023   MachineBasicBlock::reverse_iterator
7024       RI = ++I.getReverse(),
7025       RE = CmpInstr.getParent() == MI->getParent()
7026                ? Def.getReverse() /* points to MI */
7027                : CmpInstr.getParent()->rend();
7028   MachineInstr *Movr0Inst = nullptr;
7029   for (; RI != RE; ++RI) {
7030     MachineInstr &Instr = *RI;
7031     // Check whether CmpInstr can be made redundant by the current instruction.
7032     if (!IsCmpZero && isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpMask,
7033                                            CmpValue, Instr)) {
7034       Sub = &Instr;
7035       break;
7036     }
7037 
7038     if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
7039         Instr.readsRegister(X86::EFLAGS, TRI)) {
7040       // This instruction modifies or uses EFLAGS.
7041 
7042       // MOV32r0 etc. are implemented with xor which clobbers condition code.
7043       // They are safe to move up, if the definition to EFLAGS is dead and
7044       // earlier instructions do not read or write EFLAGS.
7045       if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
7046           Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
7047         Movr0Inst = &Instr;
7048         continue;
7049       }
7050 
7051       // We can't remove CmpInstr.
7052       return false;
7053     }
7054   }
7055 
7056   // Return false if no candidates exist.
7057   if (!IsCmpZero && !Sub)
7058     return false;
7059 
7060   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
7061                     Sub->getOperand(2).getReg() == SrcReg);
7062 
7063   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
7064   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
7065   // If we are done with the basic block, we need to check whether EFLAGS is
7066   // live-out.
7067   bool IsSafe = false;
7068   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
7069   MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
7070   for (++I; I != E; ++I) {
7071     const MachineInstr &Instr = *I;
7072     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
7073     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
7074     // We should check the usage if this instruction uses and updates EFLAGS.
7075     if (!UseEFLAGS && ModifyEFLAGS) {
7076       // It is safe to remove CmpInstr if EFLAGS is updated again.
7077       IsSafe = true;
7078       break;
7079     }
7080     if (!UseEFLAGS && !ModifyEFLAGS)
7081       continue;
7082 
7083     // EFLAGS is used by this instruction.
7084     X86::CondCode OldCC = X86::COND_INVALID;
7085     bool OpcIsSET = false;
7086     if (IsCmpZero || IsSwapped) {
7087       // We decode the condition code from opcode.
7088       if (Instr.isBranch())
7089         OldCC = getCondFromBranchOpc(Instr.getOpcode());
7090       else {
7091         OldCC = getCondFromSETOpc(Instr.getOpcode());
7092         if (OldCC != X86::COND_INVALID)
7093           OpcIsSET = true;
7094         else
7095           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
7096       }
7097       if (OldCC == X86::COND_INVALID) return false;
7098     }
7099     if (IsCmpZero) {
7100       switch (OldCC) {
7101       default: break;
7102       case X86::COND_A: case X86::COND_AE:
7103       case X86::COND_B: case X86::COND_BE:
7104       case X86::COND_G: case X86::COND_GE:
7105       case X86::COND_L: case X86::COND_LE:
7106       case X86::COND_O: case X86::COND_NO:
7107         // CF and OF are used, we can't perform this optimization.
7108         return false;
7109       }
7110 
7111       // If we're updating the condition code check if we have to reverse the
7112       // condition.
7113       if (ShouldUpdateCC)
7114         switch (OldCC) {
7115         default:
7116           return false;
7117         case X86::COND_E:
7118           break;
7119         case X86::COND_NE:
7120           NewCC = GetOppositeBranchCondition(NewCC);
7121           break;
7122         }
7123     } else if (IsSwapped) {
7124       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
7125       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
7126       // We swap the condition code and synthesize the new opcode.
7127       NewCC = getSwappedCondition(OldCC);
7128       if (NewCC == X86::COND_INVALID) return false;
7129     }
7130 
7131     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
7132       // Synthesize the new opcode.
7133       bool HasMemoryOperand = Instr.hasOneMemOperand();
7134       unsigned NewOpc;
7135       if (Instr.isBranch())
7136         NewOpc = GetCondBranchFromCond(NewCC);
7137       else if(OpcIsSET)
7138         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
7139       else {
7140         unsigned DstReg = Instr.getOperand(0).getReg();
7141         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
7142                                  HasMemoryOperand);
7143       }
7144 
7145       // Push the MachineInstr to OpsToUpdate.
7146       // If it is safe to remove CmpInstr, the condition code of these
7147       // instructions will be modified.
7148       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
7149     }
7150     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
7151       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
7152       IsSafe = true;
7153       break;
7154     }
7155   }
7156 
7157   // If EFLAGS is not killed nor re-defined, we should check whether it is
7158   // live-out. If it is live-out, do not optimize.
7159   if ((IsCmpZero || IsSwapped) && !IsSafe) {
7160     MachineBasicBlock *MBB = CmpInstr.getParent();
7161     for (MachineBasicBlock *Successor : MBB->successors())
7162       if (Successor->isLiveIn(X86::EFLAGS))
7163         return false;
7164   }
7165 
7166   // The instruction to be updated is either Sub or MI.
7167   Sub = IsCmpZero ? MI : Sub;
7168   // Move Movr0Inst to the appropriate place before Sub.
7169   if (Movr0Inst) {
7170     // Look backwards until we find a def that doesn't use the current EFLAGS.
7171     Def = Sub;
7172     MachineBasicBlock::reverse_iterator InsertI = Def.getReverse(),
7173                                         InsertE = Sub->getParent()->rend();
7174     for (; InsertI != InsertE; ++InsertI) {
7175       MachineInstr *Instr = &*InsertI;
7176       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
7177           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
7178         Sub->getParent()->remove(Movr0Inst);
7179         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
7180                                    Movr0Inst);
7181         break;
7182       }
7183     }
7184     if (InsertI == InsertE)
7185       return false;
7186   }
7187 
7188   // Make sure Sub instruction defines EFLAGS and mark the def live.
7189   unsigned i = 0, e = Sub->getNumOperands();
7190   for (; i != e; ++i) {
7191     MachineOperand &MO = Sub->getOperand(i);
7192     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
7193       MO.setIsDead(false);
7194       break;
7195     }
7196   }
7197   assert(i != e && "Unable to locate a def EFLAGS operand");
7198 
7199   CmpInstr.eraseFromParent();
7200 
7201   // Modify the condition code of instructions in OpsToUpdate.
7202   for (auto &Op : OpsToUpdate)
7203     Op.first->setDesc(get(Op.second));
7204   return true;
7205 }
7206 
7207 /// Try to remove the load by folding it to a register
7208 /// operand at the use. We fold the load instructions if load defines a virtual
7209 /// register, the virtual register is used once in the same BB, and the
7210 /// instructions in-between do not load or store, and have no side effects.
7211 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
7212                                               const MachineRegisterInfo *MRI,
7213                                               unsigned &FoldAsLoadDefReg,
7214                                               MachineInstr *&DefMI) const {
7215   // Check whether we can move DefMI here.
7216   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
7217   assert(DefMI);
7218   bool SawStore = false;
7219   if (!DefMI->isSafeToMove(nullptr, SawStore))
7220     return nullptr;
7221 
7222   // Collect information about virtual register operands of MI.
7223   SmallVector<unsigned, 1> SrcOperandIds;
7224   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
7225     MachineOperand &MO = MI.getOperand(i);
7226     if (!MO.isReg())
7227       continue;
7228     unsigned Reg = MO.getReg();
7229     if (Reg != FoldAsLoadDefReg)
7230       continue;
7231     // Do not fold if we have a subreg use or a def.
7232     if (MO.getSubReg() || MO.isDef())
7233       return nullptr;
7234     SrcOperandIds.push_back(i);
7235   }
7236   if (SrcOperandIds.empty())
7237     return nullptr;
7238 
7239   // Check whether we can fold the def into SrcOperandId.
7240   if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandIds, *DefMI)) {
7241     FoldAsLoadDefReg = 0;
7242     return FoldMI;
7243   }
7244 
7245   return nullptr;
7246 }
7247 
7248 /// Expand a single-def pseudo instruction to a two-addr
7249 /// instruction with two undef reads of the register being defined.
7250 /// This is used for mapping:
7251 ///   %xmm4 = V_SET0
7252 /// to:
7253 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
7254 ///
7255 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
7256                              const MCInstrDesc &Desc) {
7257   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
7258   unsigned Reg = MIB->getOperand(0).getReg();
7259   MIB->setDesc(Desc);
7260 
7261   // MachineInstr::addOperand() will insert explicit operands before any
7262   // implicit operands.
7263   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
7264   // But we don't trust that.
7265   assert(MIB->getOperand(1).getReg() == Reg &&
7266          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
7267   return true;
7268 }
7269 
7270 /// Expand a single-def pseudo instruction to a two-addr
7271 /// instruction with two %k0 reads.
7272 /// This is used for mapping:
7273 ///   %k4 = K_SET1
7274 /// to:
7275 ///   %k4 = KXNORrr %k0, %k0
7276 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
7277                             const MCInstrDesc &Desc, unsigned Reg) {
7278   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
7279   MIB->setDesc(Desc);
7280   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
7281   return true;
7282 }
7283 
7284 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
7285                           bool MinusOne) {
7286   MachineBasicBlock &MBB = *MIB->getParent();
7287   DebugLoc DL = MIB->getDebugLoc();
7288   unsigned Reg = MIB->getOperand(0).getReg();
7289 
7290   // Insert the XOR.
7291   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
7292       .addReg(Reg, RegState::Undef)
7293       .addReg(Reg, RegState::Undef);
7294 
7295   // Turn the pseudo into an INC or DEC.
7296   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
7297   MIB.addReg(Reg);
7298 
7299   return true;
7300 }
7301 
7302 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
7303                                const TargetInstrInfo &TII,
7304                                const X86Subtarget &Subtarget) {
7305   MachineBasicBlock &MBB = *MIB->getParent();
7306   DebugLoc DL = MIB->getDebugLoc();
7307   int64_t Imm = MIB->getOperand(1).getImm();
7308   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
7309   MachineBasicBlock::iterator I = MIB.getInstr();
7310 
7311   int StackAdjustment;
7312 
7313   if (Subtarget.is64Bit()) {
7314     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
7315            MIB->getOpcode() == X86::MOV32ImmSExti8);
7316 
7317     // Can't use push/pop lowering if the function might write to the red zone.
7318     X86MachineFunctionInfo *X86FI =
7319         MBB.getParent()->getInfo<X86MachineFunctionInfo>();
7320     if (X86FI->getUsesRedZone()) {
7321       MIB->setDesc(TII.get(MIB->getOpcode() ==
7322                            X86::MOV32ImmSExti8 ? X86::MOV32ri : X86::MOV64ri));
7323       return true;
7324     }
7325 
7326     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
7327     // widen the register if necessary.
7328     StackAdjustment = 8;
7329     BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
7330     MIB->setDesc(TII.get(X86::POP64r));
7331     MIB->getOperand(0)
7332         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
7333   } else {
7334     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
7335     StackAdjustment = 4;
7336     BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
7337     MIB->setDesc(TII.get(X86::POP32r));
7338   }
7339 
7340   // Build CFI if necessary.
7341   MachineFunction &MF = *MBB.getParent();
7342   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
7343   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
7344   bool NeedsDwarfCFI =
7345       !IsWin64Prologue &&
7346       (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
7347   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
7348   if (EmitCFI) {
7349     TFL->BuildCFI(MBB, I, DL,
7350         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
7351     TFL->BuildCFI(MBB, std::next(I), DL,
7352         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
7353   }
7354 
7355   return true;
7356 }
7357 
7358 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
7359 // code sequence is needed for other targets.
7360 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
7361                                  const TargetInstrInfo &TII) {
7362   MachineBasicBlock &MBB = *MIB->getParent();
7363   DebugLoc DL = MIB->getDebugLoc();
7364   unsigned Reg = MIB->getOperand(0).getReg();
7365   const GlobalValue *GV =
7366       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
7367   auto Flags = MachineMemOperand::MOLoad |
7368                MachineMemOperand::MODereferenceable |
7369                MachineMemOperand::MOInvariant;
7370   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
7371       MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 8, 8);
7372   MachineBasicBlock::iterator I = MIB.getInstr();
7373 
7374   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
7375       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
7376       .addMemOperand(MMO);
7377   MIB->setDebugLoc(DL);
7378   MIB->setDesc(TII.get(X86::MOV64rm));
7379   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
7380 }
7381 
7382 // This is used to handle spills for 128/256-bit registers when we have AVX512,
7383 // but not VLX. If it uses an extended register we need to use an instruction
7384 // that loads the lower 128/256-bit, but is available with only AVX512F.
7385 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
7386                             const TargetRegisterInfo *TRI,
7387                             const MCInstrDesc &LoadDesc,
7388                             const MCInstrDesc &BroadcastDesc,
7389                             unsigned SubIdx) {
7390   unsigned DestReg = MIB->getOperand(0).getReg();
7391   // Check if DestReg is XMM16-31 or YMM16-31.
7392   if (TRI->getEncodingValue(DestReg) < 16) {
7393     // We can use a normal VEX encoded load.
7394     MIB->setDesc(LoadDesc);
7395   } else {
7396     // Use a 128/256-bit VBROADCAST instruction.
7397     MIB->setDesc(BroadcastDesc);
7398     // Change the destination to a 512-bit register.
7399     DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass);
7400     MIB->getOperand(0).setReg(DestReg);
7401   }
7402   return true;
7403 }
7404 
7405 // This is used to handle spills for 128/256-bit registers when we have AVX512,
7406 // but not VLX. If it uses an extended register we need to use an instruction
7407 // that stores the lower 128/256-bit, but is available with only AVX512F.
7408 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
7409                              const TargetRegisterInfo *TRI,
7410                              const MCInstrDesc &StoreDesc,
7411                              const MCInstrDesc &ExtractDesc,
7412                              unsigned SubIdx) {
7413   unsigned SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
7414   // Check if DestReg is XMM16-31 or YMM16-31.
7415   if (TRI->getEncodingValue(SrcReg) < 16) {
7416     // We can use a normal VEX encoded store.
7417     MIB->setDesc(StoreDesc);
7418   } else {
7419     // Use a VEXTRACTF instruction.
7420     MIB->setDesc(ExtractDesc);
7421     // Change the destination to a 512-bit register.
7422     SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass);
7423     MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
7424     MIB.addImm(0x0); // Append immediate to extract from the lower bits.
7425   }
7426 
7427   return true;
7428 }
7429 bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
7430   bool HasAVX = Subtarget.hasAVX();
7431   MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
7432   switch (MI.getOpcode()) {
7433   case X86::MOV32r0:
7434     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
7435   case X86::MOV32r1:
7436     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
7437   case X86::MOV32r_1:
7438     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
7439   case X86::MOV32ImmSExti8:
7440   case X86::MOV64ImmSExti8:
7441     return ExpandMOVImmSExti8(MIB, *this, Subtarget);
7442   case X86::SETB_C8r:
7443     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
7444   case X86::SETB_C16r:
7445     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
7446   case X86::SETB_C32r:
7447     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
7448   case X86::SETB_C64r:
7449     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
7450   case X86::V_SET0:
7451   case X86::FsFLD0SS:
7452   case X86::FsFLD0SD:
7453     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
7454   case X86::AVX_SET0:
7455     assert(HasAVX && "AVX not supported");
7456     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
7457   case X86::AVX512_128_SET0:
7458   case X86::AVX512_FsFLD0SS:
7459   case X86::AVX512_FsFLD0SD: {
7460     bool HasVLX = Subtarget.hasVLX();
7461     unsigned SrcReg = MIB->getOperand(0).getReg();
7462     const TargetRegisterInfo *TRI = &getRegisterInfo();
7463     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
7464       return Expand2AddrUndef(MIB,
7465                               get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
7466     // Extended register without VLX. Use a larger XOR.
7467     SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass);
7468     MIB->getOperand(0).setReg(SrcReg);
7469     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7470   }
7471   case X86::AVX512_256_SET0: {
7472     bool HasVLX = Subtarget.hasVLX();
7473     unsigned SrcReg = MIB->getOperand(0).getReg();
7474     const TargetRegisterInfo *TRI = &getRegisterInfo();
7475     if (HasVLX || TRI->getEncodingValue(SrcReg) < 16)
7476       return Expand2AddrUndef(MIB,
7477                               get(HasVLX ? X86::VPXORDZ256rr : X86::VXORPSYrr));
7478     // Extended register without VLX. Use a larger XOR.
7479     SrcReg = TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass);
7480     MIB->getOperand(0).setReg(SrcReg);
7481     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7482   }
7483   case X86::AVX512_512_SET0:
7484     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
7485   case X86::V_SETALLONES:
7486     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
7487   case X86::AVX2_SETALLONES:
7488     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
7489   case X86::AVX512_512_SETALLONES: {
7490     unsigned Reg = MIB->getOperand(0).getReg();
7491     MIB->setDesc(get(X86::VPTERNLOGDZrri));
7492     // VPTERNLOGD needs 3 register inputs and an immediate.
7493     // 0xff will return 1s for any input.
7494     MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
7495        .addReg(Reg, RegState::Undef).addImm(0xff);
7496     return true;
7497   }
7498   case X86::AVX512_512_SEXT_MASK_32:
7499   case X86::AVX512_512_SEXT_MASK_64: {
7500     unsigned Reg = MIB->getOperand(0).getReg();
7501     unsigned MaskReg = MIB->getOperand(1).getReg();
7502     unsigned MaskState = getRegState(MIB->getOperand(1));
7503     unsigned Opc = (MI.getOpcode() == X86::AVX512_512_SEXT_MASK_64) ?
7504                    X86::VPTERNLOGQZrrikz : X86::VPTERNLOGDZrrikz;
7505     MI.RemoveOperand(1);
7506     MIB->setDesc(get(Opc));
7507     // VPTERNLOG needs 3 register inputs and an immediate.
7508     // 0xff will return 1s for any input.
7509     MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
7510        .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
7511     return true;
7512   }
7513   case X86::VMOVAPSZ128rm_NOVLX:
7514     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
7515                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
7516   case X86::VMOVUPSZ128rm_NOVLX:
7517     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
7518                            get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
7519   case X86::VMOVAPSZ256rm_NOVLX:
7520     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
7521                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
7522   case X86::VMOVUPSZ256rm_NOVLX:
7523     return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
7524                            get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
7525   case X86::VMOVAPSZ128mr_NOVLX:
7526     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
7527                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
7528   case X86::VMOVUPSZ128mr_NOVLX:
7529     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
7530                             get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
7531   case X86::VMOVAPSZ256mr_NOVLX:
7532     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
7533                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
7534   case X86::VMOVUPSZ256mr_NOVLX:
7535     return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
7536                             get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
7537   case X86::TEST8ri_NOREX:
7538     MI.setDesc(get(X86::TEST8ri));
7539     return true;
7540   case X86::MOV32ri64:
7541     MI.setDesc(get(X86::MOV32ri));
7542     return true;
7543 
7544   // KNL does not recognize dependency-breaking idioms for mask registers,
7545   // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
7546   // Using %k0 as the undef input register is a performance heuristic based
7547   // on the assumption that %k0 is used less frequently than the other mask
7548   // registers, since it is not usable as a write mask.
7549   // FIXME: A more advanced approach would be to choose the best input mask
7550   // register based on context.
7551   case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
7552   case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
7553   case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
7554   case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
7555   case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
7556   case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
7557   case TargetOpcode::LOAD_STACK_GUARD:
7558     expandLoadStackGuard(MIB, *this);
7559     return true;
7560   }
7561   return false;
7562 }
7563 
7564 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
7565                         int PtrOffset = 0) {
7566   unsigned NumAddrOps = MOs.size();
7567 
7568   if (NumAddrOps < 4) {
7569     // FrameIndex only - add an immediate offset (whether its zero or not).
7570     for (unsigned i = 0; i != NumAddrOps; ++i)
7571       MIB.add(MOs[i]);
7572     addOffset(MIB, PtrOffset);
7573   } else {
7574     // General Memory Addressing - we need to add any offset to an existing
7575     // offset.
7576     assert(MOs.size() == 5 && "Unexpected memory operand list length");
7577     for (unsigned i = 0; i != NumAddrOps; ++i) {
7578       const MachineOperand &MO = MOs[i];
7579       if (i == 3 && PtrOffset != 0) {
7580         MIB.addDisp(MO, PtrOffset);
7581       } else {
7582         MIB.add(MO);
7583       }
7584     }
7585   }
7586 }
7587 
7588 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
7589                                      ArrayRef<MachineOperand> MOs,
7590                                      MachineBasicBlock::iterator InsertPt,
7591                                      MachineInstr &MI,
7592                                      const TargetInstrInfo &TII) {
7593   // Create the base instruction with the memory operand as the first part.
7594   // Omit the implicit operands, something BuildMI can't do.
7595   MachineInstr *NewMI =
7596       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
7597   MachineInstrBuilder MIB(MF, NewMI);
7598   addOperands(MIB, MOs);
7599 
7600   // Loop over the rest of the ri operands, converting them over.
7601   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
7602   for (unsigned i = 0; i != NumOps; ++i) {
7603     MachineOperand &MO = MI.getOperand(i + 2);
7604     MIB.add(MO);
7605   }
7606   for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
7607     MachineOperand &MO = MI.getOperand(i);
7608     MIB.add(MO);
7609   }
7610 
7611   MachineBasicBlock *MBB = InsertPt->getParent();
7612   MBB->insert(InsertPt, NewMI);
7613 
7614   return MIB;
7615 }
7616 
7617 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
7618                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
7619                               MachineBasicBlock::iterator InsertPt,
7620                               MachineInstr &MI, const TargetInstrInfo &TII,
7621                               int PtrOffset = 0) {
7622   // Omit the implicit operands, something BuildMI can't do.
7623   MachineInstr *NewMI =
7624       MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
7625   MachineInstrBuilder MIB(MF, NewMI);
7626 
7627   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
7628     MachineOperand &MO = MI.getOperand(i);
7629     if (i == OpNo) {
7630       assert(MO.isReg() && "Expected to fold into reg operand!");
7631       addOperands(MIB, MOs, PtrOffset);
7632     } else {
7633       MIB.add(MO);
7634     }
7635   }
7636 
7637   MachineBasicBlock *MBB = InsertPt->getParent();
7638   MBB->insert(InsertPt, NewMI);
7639 
7640   return MIB;
7641 }
7642 
7643 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
7644                                 ArrayRef<MachineOperand> MOs,
7645                                 MachineBasicBlock::iterator InsertPt,
7646                                 MachineInstr &MI) {
7647   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
7648                                     MI.getDebugLoc(), TII.get(Opcode));
7649   addOperands(MIB, MOs);
7650   return MIB.addImm(0);
7651 }
7652 
7653 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
7654     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
7655     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
7656     unsigned Size, unsigned Align) const {
7657   switch (MI.getOpcode()) {
7658   case X86::INSERTPSrr:
7659   case X86::VINSERTPSrr:
7660   case X86::VINSERTPSZrr:
7661     // Attempt to convert the load of inserted vector into a fold load
7662     // of a single float.
7663     if (OpNum == 2) {
7664       unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
7665       unsigned ZMask = Imm & 15;
7666       unsigned DstIdx = (Imm >> 4) & 3;
7667       unsigned SrcIdx = (Imm >> 6) & 3;
7668 
7669       unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
7670       if (Size <= RCSize && 4 <= Align) {
7671         int PtrOffset = SrcIdx * 4;
7672         unsigned NewImm = (DstIdx << 4) | ZMask;
7673         unsigned NewOpCode =
7674             (MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm :
7675             (MI.getOpcode() == X86::VINSERTPSrr)  ? X86::VINSERTPSrm  :
7676                                                     X86::INSERTPSrm;
7677         MachineInstr *NewMI =
7678             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
7679         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
7680         return NewMI;
7681       }
7682     }
7683     break;
7684   case X86::MOVHLPSrr:
7685   case X86::VMOVHLPSrr:
7686   case X86::VMOVHLPSZrr:
7687     // Move the upper 64-bits of the second operand to the lower 64-bits.
7688     // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
7689     // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
7690     if (OpNum == 2) {
7691       unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
7692       if (Size <= RCSize && 8 <= Align) {
7693         unsigned NewOpCode =
7694             (MI.getOpcode() == X86::VMOVHLPSZrr) ? X86::VMOVLPSZ128rm :
7695             (MI.getOpcode() == X86::VMOVHLPSrr)  ? X86::VMOVLPSrm     :
7696                                                    X86::MOVLPSrm;
7697         MachineInstr *NewMI =
7698             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
7699         return NewMI;
7700       }
7701     }
7702     break;
7703   };
7704 
7705   return nullptr;
7706 }
7707 
7708 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
7709     MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
7710     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
7711     unsigned Size, unsigned Align, bool AllowCommute) const {
7712   const DenseMap<unsigned,
7713                  std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
7714   bool isCallRegIndirect = Subtarget.callRegIndirect();
7715   bool isTwoAddrFold = false;
7716 
7717   // For CPUs that favor the register form of a call or push,
7718   // do not fold loads into calls or pushes, unless optimizing for size
7719   // aggressively.
7720   if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
7721       (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
7722        MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
7723        MI.getOpcode() == X86::PUSH64r))
7724     return nullptr;
7725 
7726   unsigned NumOps = MI.getDesc().getNumOperands();
7727   bool isTwoAddr =
7728       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
7729 
7730   // FIXME: AsmPrinter doesn't know how to handle
7731   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
7732   if (MI.getOpcode() == X86::ADD32ri &&
7733       MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
7734     return nullptr;
7735 
7736   MachineInstr *NewMI = nullptr;
7737 
7738   // Attempt to fold any custom cases we have.
7739   if (MachineInstr *CustomMI =
7740           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
7741     return CustomMI;
7742 
7743   // Folding a memory location into the two-address part of a two-address
7744   // instruction is different than folding it other places.  It requires
7745   // replacing the *two* registers with the memory location.
7746   if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
7747       MI.getOperand(1).isReg() &&
7748       MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
7749     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
7750     isTwoAddrFold = true;
7751   } else if (OpNum == 0) {
7752     if (MI.getOpcode() == X86::MOV32r0) {
7753       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
7754       if (NewMI)
7755         return NewMI;
7756     }
7757 
7758     OpcodeTablePtr = &RegOp2MemOpTable0;
7759   } else if (OpNum == 1) {
7760     OpcodeTablePtr = &RegOp2MemOpTable1;
7761   } else if (OpNum == 2) {
7762     OpcodeTablePtr = &RegOp2MemOpTable2;
7763   } else if (OpNum == 3) {
7764     OpcodeTablePtr = &RegOp2MemOpTable3;
7765   } else if (OpNum == 4) {
7766     OpcodeTablePtr = &RegOp2MemOpTable4;
7767   }
7768 
7769   // If table selected...
7770   if (OpcodeTablePtr) {
7771     // Find the Opcode to fuse
7772     auto I = OpcodeTablePtr->find(MI.getOpcode());
7773     if (I != OpcodeTablePtr->end()) {
7774       unsigned Opcode = I->second.first;
7775       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
7776       if (Align < MinAlign)
7777         return nullptr;
7778       bool NarrowToMOV32rm = false;
7779       if (Size) {
7780         unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
7781         if (Size < RCSize) {
7782           // Check if it's safe to fold the load. If the size of the object is
7783           // narrower than the load width, then it's not.
7784           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
7785             return nullptr;
7786           // If this is a 64-bit load, but the spill slot is 32, then we can do
7787           // a 32-bit load which is implicitly zero-extended. This likely is
7788           // due to live interval analysis remat'ing a load from stack slot.
7789           if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
7790             return nullptr;
7791           Opcode = X86::MOV32rm;
7792           NarrowToMOV32rm = true;
7793         }
7794       }
7795 
7796       if (isTwoAddrFold)
7797         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
7798       else
7799         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
7800 
7801       if (NarrowToMOV32rm) {
7802         // If this is the special case where we use a MOV32rm to load a 32-bit
7803         // value and zero-extend the top bits. Change the destination register
7804         // to a 32-bit one.
7805         unsigned DstReg = NewMI->getOperand(0).getReg();
7806         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
7807           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
7808         else
7809           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
7810       }
7811       return NewMI;
7812     }
7813   }
7814 
7815   // If the instruction and target operand are commutable, commute the
7816   // instruction and try again.
7817   if (AllowCommute) {
7818     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
7819     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
7820       bool HasDef = MI.getDesc().getNumDefs();
7821       unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
7822       unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
7823       unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
7824       bool Tied1 =
7825           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
7826       bool Tied2 =
7827           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
7828 
7829       // If either of the commutable operands are tied to the destination
7830       // then we can not commute + fold.
7831       if ((HasDef && Reg0 == Reg1 && Tied1) ||
7832           (HasDef && Reg0 == Reg2 && Tied2))
7833         return nullptr;
7834 
7835       MachineInstr *CommutedMI =
7836           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
7837       if (!CommutedMI) {
7838         // Unable to commute.
7839         return nullptr;
7840       }
7841       if (CommutedMI != &MI) {
7842         // New instruction. We can't fold from this.
7843         CommutedMI->eraseFromParent();
7844         return nullptr;
7845       }
7846 
7847       // Attempt to fold with the commuted version of the instruction.
7848       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
7849                                     Size, Align, /*AllowCommute=*/false);
7850       if (NewMI)
7851         return NewMI;
7852 
7853       // Folding failed again - undo the commute before returning.
7854       MachineInstr *UncommutedMI =
7855           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
7856       if (!UncommutedMI) {
7857         // Unable to commute.
7858         return nullptr;
7859       }
7860       if (UncommutedMI != &MI) {
7861         // New instruction. It doesn't need to be kept.
7862         UncommutedMI->eraseFromParent();
7863         return nullptr;
7864       }
7865 
7866       // Return here to prevent duplicate fuse failure report.
7867       return nullptr;
7868     }
7869   }
7870 
7871   // No fusion
7872   if (PrintFailedFusing && !MI.isCopy())
7873     dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
7874   return nullptr;
7875 }
7876 
7877 /// Return true for all instructions that only update
7878 /// the first 32 or 64-bits of the destination register and leave the rest
7879 /// unmodified. This can be used to avoid folding loads if the instructions
7880 /// only update part of the destination register, and the non-updated part is
7881 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
7882 /// instructions breaks the partial register dependency and it can improve
7883 /// performance. e.g.:
7884 ///
7885 ///   movss (%rdi), %xmm0
7886 ///   cvtss2sd %xmm0, %xmm0
7887 ///
7888 /// Instead of
7889 ///   cvtss2sd (%rdi), %xmm0
7890 ///
7891 /// FIXME: This should be turned into a TSFlags.
7892 ///
7893 static bool hasPartialRegUpdate(unsigned Opcode) {
7894   switch (Opcode) {
7895   case X86::CVTSI2SSrr:
7896   case X86::CVTSI2SSrm:
7897   case X86::CVTSI2SS64rr:
7898   case X86::CVTSI2SS64rm:
7899   case X86::CVTSI2SDrr:
7900   case X86::CVTSI2SDrm:
7901   case X86::CVTSI2SD64rr:
7902   case X86::CVTSI2SD64rm:
7903   case X86::CVTSD2SSrr:
7904   case X86::CVTSD2SSrm:
7905   case X86::CVTSS2SDrr:
7906   case X86::CVTSS2SDrm:
7907   case X86::MOVHPDrm:
7908   case X86::MOVHPSrm:
7909   case X86::MOVLPDrm:
7910   case X86::MOVLPSrm:
7911   case X86::RCPSSr:
7912   case X86::RCPSSm:
7913   case X86::RCPSSr_Int:
7914   case X86::RCPSSm_Int:
7915   case X86::ROUNDSDr:
7916   case X86::ROUNDSDm:
7917   case X86::ROUNDSSr:
7918   case X86::ROUNDSSm:
7919   case X86::RSQRTSSr:
7920   case X86::RSQRTSSm:
7921   case X86::RSQRTSSr_Int:
7922   case X86::RSQRTSSm_Int:
7923   case X86::SQRTSSr:
7924   case X86::SQRTSSm:
7925   case X86::SQRTSSr_Int:
7926   case X86::SQRTSSm_Int:
7927   case X86::SQRTSDr:
7928   case X86::SQRTSDm:
7929   case X86::SQRTSDr_Int:
7930   case X86::SQRTSDm_Int:
7931     return true;
7932   }
7933 
7934   return false;
7935 }
7936 
7937 /// Inform the ExeDepsFix pass how many idle
7938 /// instructions we would like before a partial register update.
7939 unsigned X86InstrInfo::getPartialRegUpdateClearance(
7940     const MachineInstr &MI, unsigned OpNum,
7941     const TargetRegisterInfo *TRI) const {
7942   if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
7943     return 0;
7944 
7945   // If MI is marked as reading Reg, the partial register update is wanted.
7946   const MachineOperand &MO = MI.getOperand(0);
7947   unsigned Reg = MO.getReg();
7948   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7949     if (MO.readsReg() || MI.readsVirtualRegister(Reg))
7950       return 0;
7951   } else {
7952     if (MI.readsRegister(Reg, TRI))
7953       return 0;
7954   }
7955 
7956   // If any instructions in the clearance range are reading Reg, insert a
7957   // dependency breaking instruction, which is inexpensive and is likely to
7958   // be hidden in other instruction's cycles.
7959   return PartialRegUpdateClearance;
7960 }
7961 
7962 // Return true for any instruction the copies the high bits of the first source
7963 // operand into the unused high bits of the destination operand.
7964 static bool hasUndefRegUpdate(unsigned Opcode) {
7965   switch (Opcode) {
7966   case X86::VCVTSI2SSrr:
7967   case X86::VCVTSI2SSrm:
7968   case X86::Int_VCVTSI2SSrr:
7969   case X86::Int_VCVTSI2SSrm:
7970   case X86::VCVTSI2SS64rr:
7971   case X86::VCVTSI2SS64rm:
7972   case X86::Int_VCVTSI2SS64rr:
7973   case X86::Int_VCVTSI2SS64rm:
7974   case X86::VCVTSI2SDrr:
7975   case X86::VCVTSI2SDrm:
7976   case X86::Int_VCVTSI2SDrr:
7977   case X86::Int_VCVTSI2SDrm:
7978   case X86::VCVTSI2SD64rr:
7979   case X86::VCVTSI2SD64rm:
7980   case X86::Int_VCVTSI2SD64rr:
7981   case X86::Int_VCVTSI2SD64rm:
7982   case X86::VCVTSD2SSrr:
7983   case X86::VCVTSD2SSrm:
7984   case X86::Int_VCVTSD2SSrr:
7985   case X86::Int_VCVTSD2SSrm:
7986   case X86::VCVTSS2SDrr:
7987   case X86::VCVTSS2SDrm:
7988   case X86::Int_VCVTSS2SDrr:
7989   case X86::Int_VCVTSS2SDrm:
7990   case X86::VRCPSSr:
7991   case X86::VRCPSSr_Int:
7992   case X86::VRCPSSm:
7993   case X86::VRCPSSm_Int:
7994   case X86::VROUNDSDr:
7995   case X86::VROUNDSDm:
7996   case X86::VROUNDSDr_Int:
7997   case X86::VROUNDSDm_Int:
7998   case X86::VROUNDSSr:
7999   case X86::VROUNDSSm:
8000   case X86::VROUNDSSr_Int:
8001   case X86::VROUNDSSm_Int:
8002   case X86::VRSQRTSSr:
8003   case X86::VRSQRTSSr_Int:
8004   case X86::VRSQRTSSm:
8005   case X86::VRSQRTSSm_Int:
8006   case X86::VSQRTSSr:
8007   case X86::VSQRTSSr_Int:
8008   case X86::VSQRTSSm:
8009   case X86::VSQRTSSm_Int:
8010   case X86::VSQRTSDr:
8011   case X86::VSQRTSDr_Int:
8012   case X86::VSQRTSDm:
8013   case X86::VSQRTSDm_Int:
8014   // AVX-512
8015   case X86::VCVTSI2SSZrr:
8016   case X86::VCVTSI2SSZrm:
8017   case X86::VCVTSI2SSZrr_Int:
8018   case X86::VCVTSI2SSZrrb_Int:
8019   case X86::VCVTSI2SSZrm_Int:
8020   case X86::VCVTSI642SSZrr:
8021   case X86::VCVTSI642SSZrm:
8022   case X86::VCVTSI642SSZrr_Int:
8023   case X86::VCVTSI642SSZrrb_Int:
8024   case X86::VCVTSI642SSZrm_Int:
8025   case X86::VCVTSI2SDZrr:
8026   case X86::VCVTSI2SDZrm:
8027   case X86::VCVTSI2SDZrr_Int:
8028   case X86::VCVTSI2SDZrrb_Int:
8029   case X86::VCVTSI2SDZrm_Int:
8030   case X86::VCVTSI642SDZrr:
8031   case X86::VCVTSI642SDZrm:
8032   case X86::VCVTSI642SDZrr_Int:
8033   case X86::VCVTSI642SDZrrb_Int:
8034   case X86::VCVTSI642SDZrm_Int:
8035   case X86::VCVTUSI2SSZrr:
8036   case X86::VCVTUSI2SSZrm:
8037   case X86::VCVTUSI2SSZrr_Int:
8038   case X86::VCVTUSI2SSZrrb_Int:
8039   case X86::VCVTUSI2SSZrm_Int:
8040   case X86::VCVTUSI642SSZrr:
8041   case X86::VCVTUSI642SSZrm:
8042   case X86::VCVTUSI642SSZrr_Int:
8043   case X86::VCVTUSI642SSZrrb_Int:
8044   case X86::VCVTUSI642SSZrm_Int:
8045   case X86::VCVTUSI2SDZrr:
8046   case X86::VCVTUSI2SDZrm:
8047   case X86::VCVTUSI2SDZrr_Int:
8048   case X86::VCVTUSI2SDZrm_Int:
8049   case X86::VCVTUSI642SDZrr:
8050   case X86::VCVTUSI642SDZrm:
8051   case X86::VCVTUSI642SDZrr_Int:
8052   case X86::VCVTUSI642SDZrrb_Int:
8053   case X86::VCVTUSI642SDZrm_Int:
8054   case X86::VCVTSD2SSZrr:
8055   case X86::VCVTSD2SSZrrb:
8056   case X86::VCVTSD2SSZrm:
8057   case X86::VCVTSS2SDZrr:
8058   case X86::VCVTSS2SDZrrb:
8059   case X86::VCVTSS2SDZrm:
8060   case X86::VRNDSCALESDr:
8061   case X86::VRNDSCALESDrb:
8062   case X86::VRNDSCALESDm:
8063   case X86::VRNDSCALESSr:
8064   case X86::VRNDSCALESSrb:
8065   case X86::VRNDSCALESSm:
8066   case X86::VRCP14SSrr:
8067   case X86::VRCP14SSrm:
8068   case X86::VRSQRT14SSrr:
8069   case X86::VRSQRT14SSrm:
8070   case X86::VSQRTSSZr:
8071   case X86::VSQRTSSZr_Int:
8072   case X86::VSQRTSSZrb_Int:
8073   case X86::VSQRTSSZm:
8074   case X86::VSQRTSSZm_Int:
8075   case X86::VSQRTSDZr:
8076   case X86::VSQRTSDZr_Int:
8077   case X86::VSQRTSDZrb_Int:
8078   case X86::VSQRTSDZm:
8079   case X86::VSQRTSDZm_Int:
8080     return true;
8081   }
8082 
8083   return false;
8084 }
8085 
8086 /// Inform the ExeDepsFix pass how many idle instructions we would like before
8087 /// certain undef register reads.
8088 ///
8089 /// This catches the VCVTSI2SD family of instructions:
8090 ///
8091 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
8092 ///
8093 /// We should to be careful *not* to catch VXOR idioms which are presumably
8094 /// handled specially in the pipeline:
8095 ///
8096 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
8097 ///
8098 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
8099 /// high bits that are passed-through are not live.
8100 unsigned
8101 X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
8102                                    const TargetRegisterInfo *TRI) const {
8103   if (!hasUndefRegUpdate(MI.getOpcode()))
8104     return 0;
8105 
8106   // Set the OpNum parameter to the first source operand.
8107   OpNum = 1;
8108 
8109   const MachineOperand &MO = MI.getOperand(OpNum);
8110   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
8111     return UndefRegClearance;
8112   }
8113   return 0;
8114 }
8115 
8116 void X86InstrInfo::breakPartialRegDependency(
8117     MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
8118   unsigned Reg = MI.getOperand(OpNum).getReg();
8119   // If MI kills this register, the false dependence is already broken.
8120   if (MI.killsRegister(Reg, TRI))
8121     return;
8122 
8123   if (X86::VR128RegClass.contains(Reg)) {
8124     // These instructions are all floating point domain, so xorps is the best
8125     // choice.
8126     unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
8127     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
8128         .addReg(Reg, RegState::Undef)
8129         .addReg(Reg, RegState::Undef);
8130     MI.addRegisterKilled(Reg, TRI, true);
8131   } else if (X86::VR256RegClass.contains(Reg)) {
8132     // Use vxorps to clear the full ymm register.
8133     // It wants to read and write the xmm sub-register.
8134     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
8135     BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
8136         .addReg(XReg, RegState::Undef)
8137         .addReg(XReg, RegState::Undef)
8138         .addReg(Reg, RegState::ImplicitDefine);
8139     MI.addRegisterKilled(Reg, TRI, true);
8140   }
8141 }
8142 
8143 MachineInstr *
8144 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
8145                                     ArrayRef<unsigned> Ops,
8146                                     MachineBasicBlock::iterator InsertPt,
8147                                     int FrameIndex, LiveIntervals *LIS) const {
8148   // Check switch flag
8149   if (NoFusing)
8150     return nullptr;
8151 
8152   // Unless optimizing for size, don't fold to avoid partial
8153   // register update stalls
8154   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
8155     return nullptr;
8156 
8157   // Don't fold subreg spills, or reloads that use a high subreg.
8158   for (auto Op : Ops) {
8159     MachineOperand &MO = MI.getOperand(Op);
8160     auto SubReg = MO.getSubReg();
8161     if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
8162       return nullptr;
8163   }
8164 
8165   const MachineFrameInfo &MFI = MF.getFrameInfo();
8166   unsigned Size = MFI.getObjectSize(FrameIndex);
8167   unsigned Alignment = MFI.getObjectAlignment(FrameIndex);
8168   // If the function stack isn't realigned we don't want to fold instructions
8169   // that need increased alignment.
8170   if (!RI.needsStackRealignment(MF))
8171     Alignment =
8172         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
8173   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
8174     unsigned NewOpc = 0;
8175     unsigned RCSize = 0;
8176     switch (MI.getOpcode()) {
8177     default: return nullptr;
8178     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
8179     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
8180     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
8181     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
8182     }
8183     // Check if it's safe to fold the load. If the size of the object is
8184     // narrower than the load width, then it's not.
8185     if (Size < RCSize)
8186       return nullptr;
8187     // Change to CMPXXri r, 0 first.
8188     MI.setDesc(get(NewOpc));
8189     MI.getOperand(1).ChangeToImmediate(0);
8190   } else if (Ops.size() != 1)
8191     return nullptr;
8192 
8193   return foldMemoryOperandImpl(MF, MI, Ops[0],
8194                                MachineOperand::CreateFI(FrameIndex), InsertPt,
8195                                Size, Alignment, /*AllowCommute=*/true);
8196 }
8197 
8198 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
8199 /// because the latter uses contents that wouldn't be defined in the folded
8200 /// version.  For instance, this transformation isn't legal:
8201 ///   movss (%rdi), %xmm0
8202 ///   addps %xmm0, %xmm0
8203 /// ->
8204 ///   addps (%rdi), %xmm0
8205 ///
8206 /// But this one is:
8207 ///   movss (%rdi), %xmm0
8208 ///   addss %xmm0, %xmm0
8209 /// ->
8210 ///   addss (%rdi), %xmm0
8211 ///
8212 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
8213                                              const MachineInstr &UserMI,
8214                                              const MachineFunction &MF) {
8215   unsigned Opc = LoadMI.getOpcode();
8216   unsigned UserOpc = UserMI.getOpcode();
8217   unsigned RegSize =
8218       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
8219 
8220   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm || Opc == X86::VMOVSSZrm) &&
8221       RegSize > 4) {
8222     // These instructions only load 32 bits, we can't fold them if the
8223     // destination register is wider than 32 bits (4 bytes), and its user
8224     // instruction isn't scalar (SS).
8225     switch (UserOpc) {
8226     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int: case X86::VADDSSZrr_Int:
8227     case X86::Int_CMPSSrr: case X86::Int_VCMPSSrr: case X86::VCMPSSZrr_Int:
8228     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int: case X86::VDIVSSZrr_Int:
8229     case X86::MAXSSrr_Int: case X86::VMAXSSrr_Int: case X86::VMAXSSZrr_Int:
8230     case X86::MINSSrr_Int: case X86::VMINSSrr_Int: case X86::VMINSSZrr_Int:
8231     case X86::MULSSrr_Int: case X86::VMULSSrr_Int: case X86::VMULSSZrr_Int:
8232     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int: case X86::VSUBSSZrr_Int:
8233     case X86::VADDSSZrr_Intk: case X86::VADDSSZrr_Intkz:
8234     case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intkz:
8235     case X86::VMAXSSZrr_Intk: case X86::VMAXSSZrr_Intkz:
8236     case X86::VMINSSZrr_Intk: case X86::VMINSSZrr_Intkz:
8237     case X86::VMULSSZrr_Intk: case X86::VMULSSZrr_Intkz:
8238     case X86::VSUBSSZrr_Intk: case X86::VSUBSSZrr_Intkz:
8239     case X86::VFMADDSS4rr_Int:   case X86::VFNMADDSS4rr_Int:
8240     case X86::VFMSUBSS4rr_Int:   case X86::VFNMSUBSS4rr_Int:
8241     case X86::VFMADD132SSr_Int:  case X86::VFNMADD132SSr_Int:
8242     case X86::VFMADD213SSr_Int:  case X86::VFNMADD213SSr_Int:
8243     case X86::VFMADD231SSr_Int:  case X86::VFNMADD231SSr_Int:
8244     case X86::VFMSUB132SSr_Int:  case X86::VFNMSUB132SSr_Int:
8245     case X86::VFMSUB213SSr_Int:  case X86::VFNMSUB213SSr_Int:
8246     case X86::VFMSUB231SSr_Int:  case X86::VFNMSUB231SSr_Int:
8247     case X86::VFMADD132SSZr_Int: case X86::VFNMADD132SSZr_Int:
8248     case X86::VFMADD213SSZr_Int: case X86::VFNMADD213SSZr_Int:
8249     case X86::VFMADD231SSZr_Int: case X86::VFNMADD231SSZr_Int:
8250     case X86::VFMSUB132SSZr_Int: case X86::VFNMSUB132SSZr_Int:
8251     case X86::VFMSUB213SSZr_Int: case X86::VFNMSUB213SSZr_Int:
8252     case X86::VFMSUB231SSZr_Int: case X86::VFNMSUB231SSZr_Int:
8253     case X86::VFMADD132SSZr_Intk: case X86::VFNMADD132SSZr_Intk:
8254     case X86::VFMADD213SSZr_Intk: case X86::VFNMADD213SSZr_Intk:
8255     case X86::VFMADD231SSZr_Intk: case X86::VFNMADD231SSZr_Intk:
8256     case X86::VFMSUB132SSZr_Intk: case X86::VFNMSUB132SSZr_Intk:
8257     case X86::VFMSUB213SSZr_Intk: case X86::VFNMSUB213SSZr_Intk:
8258     case X86::VFMSUB231SSZr_Intk: case X86::VFNMSUB231SSZr_Intk:
8259     case X86::VFMADD132SSZr_Intkz: case X86::VFNMADD132SSZr_Intkz:
8260     case X86::VFMADD213SSZr_Intkz: case X86::VFNMADD213SSZr_Intkz:
8261     case X86::VFMADD231SSZr_Intkz: case X86::VFNMADD231SSZr_Intkz:
8262     case X86::VFMSUB132SSZr_Intkz: case X86::VFNMSUB132SSZr_Intkz:
8263     case X86::VFMSUB213SSZr_Intkz: case X86::VFNMSUB213SSZr_Intkz:
8264     case X86::VFMSUB231SSZr_Intkz: case X86::VFNMSUB231SSZr_Intkz:
8265       return false;
8266     default:
8267       return true;
8268     }
8269   }
8270 
8271   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm || Opc == X86::VMOVSDZrm) &&
8272       RegSize > 8) {
8273     // These instructions only load 64 bits, we can't fold them if the
8274     // destination register is wider than 64 bits (8 bytes), and its user
8275     // instruction isn't scalar (SD).
8276     switch (UserOpc) {
8277     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int: case X86::VADDSDZrr_Int:
8278     case X86::Int_CMPSDrr: case X86::Int_VCMPSDrr: case X86::VCMPSDZrr_Int:
8279     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int: case X86::VDIVSDZrr_Int:
8280     case X86::MAXSDrr_Int: case X86::VMAXSDrr_Int: case X86::VMAXSDZrr_Int:
8281     case X86::MINSDrr_Int: case X86::VMINSDrr_Int: case X86::VMINSDZrr_Int:
8282     case X86::MULSDrr_Int: case X86::VMULSDrr_Int: case X86::VMULSDZrr_Int:
8283     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int: case X86::VSUBSDZrr_Int:
8284     case X86::VADDSDZrr_Intk: case X86::VADDSDZrr_Intkz:
8285     case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intkz:
8286     case X86::VMAXSDZrr_Intk: case X86::VMAXSDZrr_Intkz:
8287     case X86::VMINSDZrr_Intk: case X86::VMINSDZrr_Intkz:
8288     case X86::VMULSDZrr_Intk: case X86::VMULSDZrr_Intkz:
8289     case X86::VSUBSDZrr_Intk: case X86::VSUBSDZrr_Intkz:
8290     case X86::VFMADDSD4rr_Int:   case X86::VFNMADDSD4rr_Int:
8291     case X86::VFMSUBSD4rr_Int:   case X86::VFNMSUBSD4rr_Int:
8292     case X86::VFMADD132SDr_Int:  case X86::VFNMADD132SDr_Int:
8293     case X86::VFMADD213SDr_Int:  case X86::VFNMADD213SDr_Int:
8294     case X86::VFMADD231SDr_Int:  case X86::VFNMADD231SDr_Int:
8295     case X86::VFMSUB132SDr_Int:  case X86::VFNMSUB132SDr_Int:
8296     case X86::VFMSUB213SDr_Int:  case X86::VFNMSUB213SDr_Int:
8297     case X86::VFMSUB231SDr_Int:  case X86::VFNMSUB231SDr_Int:
8298     case X86::VFMADD132SDZr_Int: case X86::VFNMADD132SDZr_Int:
8299     case X86::VFMADD213SDZr_Int: case X86::VFNMADD213SDZr_Int:
8300     case X86::VFMADD231SDZr_Int: case X86::VFNMADD231SDZr_Int:
8301     case X86::VFMSUB132SDZr_Int: case X86::VFNMSUB132SDZr_Int:
8302     case X86::VFMSUB213SDZr_Int: case X86::VFNMSUB213SDZr_Int:
8303     case X86::VFMSUB231SDZr_Int: case X86::VFNMSUB231SDZr_Int:
8304     case X86::VFMADD132SDZr_Intk: case X86::VFNMADD132SDZr_Intk:
8305     case X86::VFMADD213SDZr_Intk: case X86::VFNMADD213SDZr_Intk:
8306     case X86::VFMADD231SDZr_Intk: case X86::VFNMADD231SDZr_Intk:
8307     case X86::VFMSUB132SDZr_Intk: case X86::VFNMSUB132SDZr_Intk:
8308     case X86::VFMSUB213SDZr_Intk: case X86::VFNMSUB213SDZr_Intk:
8309     case X86::VFMSUB231SDZr_Intk: case X86::VFNMSUB231SDZr_Intk:
8310     case X86::VFMADD132SDZr_Intkz: case X86::VFNMADD132SDZr_Intkz:
8311     case X86::VFMADD213SDZr_Intkz: case X86::VFNMADD213SDZr_Intkz:
8312     case X86::VFMADD231SDZr_Intkz: case X86::VFNMADD231SDZr_Intkz:
8313     case X86::VFMSUB132SDZr_Intkz: case X86::VFNMSUB132SDZr_Intkz:
8314     case X86::VFMSUB213SDZr_Intkz: case X86::VFNMSUB213SDZr_Intkz:
8315     case X86::VFMSUB231SDZr_Intkz: case X86::VFNMSUB231SDZr_Intkz:
8316       return false;
8317     default:
8318       return true;
8319     }
8320   }
8321 
8322   return false;
8323 }
8324 
8325 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
8326     MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
8327     MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
8328     LiveIntervals *LIS) const {
8329 
8330   // TODO: Support the case where LoadMI loads a wide register, but MI
8331   // only uses a subreg.
8332   for (auto Op : Ops) {
8333     if (MI.getOperand(Op).getSubReg())
8334       return nullptr;
8335   }
8336 
8337   // If loading from a FrameIndex, fold directly from the FrameIndex.
8338   unsigned NumOps = LoadMI.getDesc().getNumOperands();
8339   int FrameIndex;
8340   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
8341     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
8342       return nullptr;
8343     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
8344   }
8345 
8346   // Check switch flag
8347   if (NoFusing) return nullptr;
8348 
8349   // Avoid partial register update stalls unless optimizing for size.
8350   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
8351     return nullptr;
8352 
8353   // Determine the alignment of the load.
8354   unsigned Alignment = 0;
8355   if (LoadMI.hasOneMemOperand())
8356     Alignment = (*LoadMI.memoperands_begin())->getAlignment();
8357   else
8358     switch (LoadMI.getOpcode()) {
8359     case X86::AVX512_512_SET0:
8360     case X86::AVX512_512_SETALLONES:
8361       Alignment = 64;
8362       break;
8363     case X86::AVX2_SETALLONES:
8364     case X86::AVX_SET0:
8365     case X86::AVX512_256_SET0:
8366       Alignment = 32;
8367       break;
8368     case X86::V_SET0:
8369     case X86::V_SETALLONES:
8370     case X86::AVX512_128_SET0:
8371       Alignment = 16;
8372       break;
8373     case X86::FsFLD0SD:
8374     case X86::AVX512_FsFLD0SD:
8375       Alignment = 8;
8376       break;
8377     case X86::FsFLD0SS:
8378     case X86::AVX512_FsFLD0SS:
8379       Alignment = 4;
8380       break;
8381     default:
8382       return nullptr;
8383     }
8384   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
8385     unsigned NewOpc = 0;
8386     switch (MI.getOpcode()) {
8387     default: return nullptr;
8388     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
8389     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
8390     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
8391     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
8392     }
8393     // Change to CMPXXri r, 0 first.
8394     MI.setDesc(get(NewOpc));
8395     MI.getOperand(1).ChangeToImmediate(0);
8396   } else if (Ops.size() != 1)
8397     return nullptr;
8398 
8399   // Make sure the subregisters match.
8400   // Otherwise we risk changing the size of the load.
8401   if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
8402     return nullptr;
8403 
8404   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
8405   switch (LoadMI.getOpcode()) {
8406   case X86::V_SET0:
8407   case X86::V_SETALLONES:
8408   case X86::AVX2_SETALLONES:
8409   case X86::AVX_SET0:
8410   case X86::AVX512_128_SET0:
8411   case X86::AVX512_256_SET0:
8412   case X86::AVX512_512_SET0:
8413   case X86::AVX512_512_SETALLONES:
8414   case X86::FsFLD0SD:
8415   case X86::AVX512_FsFLD0SD:
8416   case X86::FsFLD0SS:
8417   case X86::AVX512_FsFLD0SS: {
8418     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
8419     // Create a constant-pool entry and operands to load from it.
8420 
8421     // Medium and large mode can't fold loads this way.
8422     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
8423         MF.getTarget().getCodeModel() != CodeModel::Kernel)
8424       return nullptr;
8425 
8426     // x86-32 PIC requires a PIC base register for constant pools.
8427     unsigned PICBase = 0;
8428     if (MF.getTarget().isPositionIndependent()) {
8429       if (Subtarget.is64Bit())
8430         PICBase = X86::RIP;
8431       else
8432         // FIXME: PICBase = getGlobalBaseReg(&MF);
8433         // This doesn't work for several reasons.
8434         // 1. GlobalBaseReg may have been spilled.
8435         // 2. It may not be live at MI.
8436         return nullptr;
8437     }
8438 
8439     // Create a constant-pool entry.
8440     MachineConstantPool &MCP = *MF.getConstantPool();
8441     Type *Ty;
8442     unsigned Opc = LoadMI.getOpcode();
8443     if (Opc == X86::FsFLD0SS || Opc == X86::AVX512_FsFLD0SS)
8444       Ty = Type::getFloatTy(MF.getFunction()->getContext());
8445     else if (Opc == X86::FsFLD0SD || Opc == X86::AVX512_FsFLD0SD)
8446       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
8447     else if (Opc == X86::AVX512_512_SET0 || Opc == X86::AVX512_512_SETALLONES)
8448       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()),16);
8449     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0 ||
8450              Opc == X86::AVX512_256_SET0)
8451       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
8452     else
8453       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
8454 
8455     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES ||
8456                       Opc == X86::AVX512_512_SETALLONES);
8457     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
8458                                     Constant::getNullValue(Ty);
8459     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
8460 
8461     // Create operands to load from the constant pool entry.
8462     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
8463     MOs.push_back(MachineOperand::CreateImm(1));
8464     MOs.push_back(MachineOperand::CreateReg(0, false));
8465     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
8466     MOs.push_back(MachineOperand::CreateReg(0, false));
8467     break;
8468   }
8469   default: {
8470     if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
8471       return nullptr;
8472 
8473     // Folding a normal load. Just copy the load's address operands.
8474     MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
8475                LoadMI.operands_begin() + NumOps);
8476     break;
8477   }
8478   }
8479   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
8480                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
8481 }
8482 
8483 bool X86InstrInfo::unfoldMemoryOperand(
8484     MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
8485     bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
8486   auto I = MemOp2RegOpTable.find(MI.getOpcode());
8487   if (I == MemOp2RegOpTable.end())
8488     return false;
8489   unsigned Opc = I->second.first;
8490   unsigned Index = I->second.second & TB_INDEX_MASK;
8491   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
8492   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
8493   if (UnfoldLoad && !FoldedLoad)
8494     return false;
8495   UnfoldLoad &= FoldedLoad;
8496   if (UnfoldStore && !FoldedStore)
8497     return false;
8498   UnfoldStore &= FoldedStore;
8499 
8500   const MCInstrDesc &MCID = get(Opc);
8501   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
8502   // TODO: Check if 32-byte or greater accesses are slow too?
8503   if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
8504       Subtarget.isUnalignedMem16Slow())
8505     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
8506     // conservatively assume the address is unaligned. That's bad for
8507     // performance.
8508     return false;
8509   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
8510   SmallVector<MachineOperand,2> BeforeOps;
8511   SmallVector<MachineOperand,2> AfterOps;
8512   SmallVector<MachineOperand,4> ImpOps;
8513   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
8514     MachineOperand &Op = MI.getOperand(i);
8515     if (i >= Index && i < Index + X86::AddrNumOperands)
8516       AddrOps.push_back(Op);
8517     else if (Op.isReg() && Op.isImplicit())
8518       ImpOps.push_back(Op);
8519     else if (i < Index)
8520       BeforeOps.push_back(Op);
8521     else if (i > Index)
8522       AfterOps.push_back(Op);
8523   }
8524 
8525   // Emit the load instruction.
8526   if (UnfoldLoad) {
8527     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
8528         MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
8529     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
8530     if (UnfoldStore) {
8531       // Address operands cannot be marked isKill.
8532       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
8533         MachineOperand &MO = NewMIs[0]->getOperand(i);
8534         if (MO.isReg())
8535           MO.setIsKill(false);
8536       }
8537     }
8538   }
8539 
8540   // Emit the data processing instruction.
8541   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
8542   MachineInstrBuilder MIB(MF, DataMI);
8543 
8544   if (FoldedStore)
8545     MIB.addReg(Reg, RegState::Define);
8546   for (MachineOperand &BeforeOp : BeforeOps)
8547     MIB.add(BeforeOp);
8548   if (FoldedLoad)
8549     MIB.addReg(Reg);
8550   for (MachineOperand &AfterOp : AfterOps)
8551     MIB.add(AfterOp);
8552   for (MachineOperand &ImpOp : ImpOps) {
8553     MIB.addReg(ImpOp.getReg(),
8554                getDefRegState(ImpOp.isDef()) |
8555                RegState::Implicit |
8556                getKillRegState(ImpOp.isKill()) |
8557                getDeadRegState(ImpOp.isDead()) |
8558                getUndefRegState(ImpOp.isUndef()));
8559   }
8560   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
8561   switch (DataMI->getOpcode()) {
8562   default: break;
8563   case X86::CMP64ri32:
8564   case X86::CMP64ri8:
8565   case X86::CMP32ri:
8566   case X86::CMP32ri8:
8567   case X86::CMP16ri:
8568   case X86::CMP16ri8:
8569   case X86::CMP8ri: {
8570     MachineOperand &MO0 = DataMI->getOperand(0);
8571     MachineOperand &MO1 = DataMI->getOperand(1);
8572     if (MO1.getImm() == 0) {
8573       unsigned NewOpc;
8574       switch (DataMI->getOpcode()) {
8575       default: llvm_unreachable("Unreachable!");
8576       case X86::CMP64ri8:
8577       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
8578       case X86::CMP32ri8:
8579       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
8580       case X86::CMP16ri8:
8581       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
8582       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
8583       }
8584       DataMI->setDesc(get(NewOpc));
8585       MO1.ChangeToRegister(MO0.getReg(), false);
8586     }
8587   }
8588   }
8589   NewMIs.push_back(DataMI);
8590 
8591   // Emit the store instruction.
8592   if (UnfoldStore) {
8593     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
8594     std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
8595         MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
8596     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
8597   }
8598 
8599   return true;
8600 }
8601 
8602 bool
8603 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
8604                                   SmallVectorImpl<SDNode*> &NewNodes) const {
8605   if (!N->isMachineOpcode())
8606     return false;
8607 
8608   auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
8609   if (I == MemOp2RegOpTable.end())
8610     return false;
8611   unsigned Opc = I->second.first;
8612   unsigned Index = I->second.second & TB_INDEX_MASK;
8613   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
8614   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
8615   const MCInstrDesc &MCID = get(Opc);
8616   MachineFunction &MF = DAG.getMachineFunction();
8617   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
8618   unsigned NumDefs = MCID.NumDefs;
8619   std::vector<SDValue> AddrOps;
8620   std::vector<SDValue> BeforeOps;
8621   std::vector<SDValue> AfterOps;
8622   SDLoc dl(N);
8623   unsigned NumOps = N->getNumOperands();
8624   for (unsigned i = 0; i != NumOps-1; ++i) {
8625     SDValue Op = N->getOperand(i);
8626     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
8627       AddrOps.push_back(Op);
8628     else if (i < Index-NumDefs)
8629       BeforeOps.push_back(Op);
8630     else if (i > Index-NumDefs)
8631       AfterOps.push_back(Op);
8632   }
8633   SDValue Chain = N->getOperand(NumOps-1);
8634   AddrOps.push_back(Chain);
8635 
8636   // Emit the load instruction.
8637   SDNode *Load = nullptr;
8638   if (FoldedLoad) {
8639     EVT VT = *RC->vt_begin();
8640     std::pair<MachineInstr::mmo_iterator,
8641               MachineInstr::mmo_iterator> MMOs =
8642       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
8643                             cast<MachineSDNode>(N)->memoperands_end());
8644     if (!(*MMOs.first) &&
8645         RC == &X86::VR128RegClass &&
8646         Subtarget.isUnalignedMem16Slow())
8647       // Do not introduce a slow unaligned load.
8648       return false;
8649     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
8650     // memory access is slow above.
8651     unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
8652     bool isAligned = (*MMOs.first) &&
8653                      (*MMOs.first)->getAlignment() >= Alignment;
8654     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
8655                               VT, MVT::Other, AddrOps);
8656     NewNodes.push_back(Load);
8657 
8658     // Preserve memory reference information.
8659     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
8660   }
8661 
8662   // Emit the data processing instruction.
8663   std::vector<EVT> VTs;
8664   const TargetRegisterClass *DstRC = nullptr;
8665   if (MCID.getNumDefs() > 0) {
8666     DstRC = getRegClass(MCID, 0, &RI, MF);
8667     VTs.push_back(*DstRC->vt_begin());
8668   }
8669   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
8670     EVT VT = N->getValueType(i);
8671     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
8672       VTs.push_back(VT);
8673   }
8674   if (Load)
8675     BeforeOps.push_back(SDValue(Load, 0));
8676   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
8677   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
8678   NewNodes.push_back(NewNode);
8679 
8680   // Emit the store instruction.
8681   if (FoldedStore) {
8682     AddrOps.pop_back();
8683     AddrOps.push_back(SDValue(NewNode, 0));
8684     AddrOps.push_back(Chain);
8685     std::pair<MachineInstr::mmo_iterator,
8686               MachineInstr::mmo_iterator> MMOs =
8687       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
8688                              cast<MachineSDNode>(N)->memoperands_end());
8689     if (!(*MMOs.first) &&
8690         RC == &X86::VR128RegClass &&
8691         Subtarget.isUnalignedMem16Slow())
8692       // Do not introduce a slow unaligned store.
8693       return false;
8694     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
8695     // memory access is slow above.
8696     unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
8697     bool isAligned = (*MMOs.first) &&
8698                      (*MMOs.first)->getAlignment() >= Alignment;
8699     SDNode *Store =
8700         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
8701                            dl, MVT::Other, AddrOps);
8702     NewNodes.push_back(Store);
8703 
8704     // Preserve memory reference information.
8705     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
8706   }
8707 
8708   return true;
8709 }
8710 
8711 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
8712                                       bool UnfoldLoad, bool UnfoldStore,
8713                                       unsigned *LoadRegIndex) const {
8714   auto I = MemOp2RegOpTable.find(Opc);
8715   if (I == MemOp2RegOpTable.end())
8716     return 0;
8717   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
8718   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
8719   if (UnfoldLoad && !FoldedLoad)
8720     return 0;
8721   if (UnfoldStore && !FoldedStore)
8722     return 0;
8723   if (LoadRegIndex)
8724     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
8725   return I->second.first;
8726 }
8727 
8728 bool
8729 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
8730                                      int64_t &Offset1, int64_t &Offset2) const {
8731   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
8732     return false;
8733   unsigned Opc1 = Load1->getMachineOpcode();
8734   unsigned Opc2 = Load2->getMachineOpcode();
8735   switch (Opc1) {
8736   default: return false;
8737   case X86::MOV8rm:
8738   case X86::MOV16rm:
8739   case X86::MOV32rm:
8740   case X86::MOV64rm:
8741   case X86::LD_Fp32m:
8742   case X86::LD_Fp64m:
8743   case X86::LD_Fp80m:
8744   case X86::MOVSSrm:
8745   case X86::MOVSDrm:
8746   case X86::MMX_MOVD64rm:
8747   case X86::MMX_MOVQ64rm:
8748   case X86::MOVAPSrm:
8749   case X86::MOVUPSrm:
8750   case X86::MOVAPDrm:
8751   case X86::MOVUPDrm:
8752   case X86::MOVDQArm:
8753   case X86::MOVDQUrm:
8754   // AVX load instructions
8755   case X86::VMOVSSrm:
8756   case X86::VMOVSDrm:
8757   case X86::VMOVAPSrm:
8758   case X86::VMOVUPSrm:
8759   case X86::VMOVAPDrm:
8760   case X86::VMOVUPDrm:
8761   case X86::VMOVDQArm:
8762   case X86::VMOVDQUrm:
8763   case X86::VMOVAPSYrm:
8764   case X86::VMOVUPSYrm:
8765   case X86::VMOVAPDYrm:
8766   case X86::VMOVUPDYrm:
8767   case X86::VMOVDQAYrm:
8768   case X86::VMOVDQUYrm:
8769   // AVX512 load instructions
8770   case X86::VMOVSSZrm:
8771   case X86::VMOVSDZrm:
8772   case X86::VMOVAPSZ128rm:
8773   case X86::VMOVUPSZ128rm:
8774   case X86::VMOVAPSZ128rm_NOVLX:
8775   case X86::VMOVUPSZ128rm_NOVLX:
8776   case X86::VMOVAPDZ128rm:
8777   case X86::VMOVUPDZ128rm:
8778   case X86::VMOVDQU8Z128rm:
8779   case X86::VMOVDQU16Z128rm:
8780   case X86::VMOVDQA32Z128rm:
8781   case X86::VMOVDQU32Z128rm:
8782   case X86::VMOVDQA64Z128rm:
8783   case X86::VMOVDQU64Z128rm:
8784   case X86::VMOVAPSZ256rm:
8785   case X86::VMOVUPSZ256rm:
8786   case X86::VMOVAPSZ256rm_NOVLX:
8787   case X86::VMOVUPSZ256rm_NOVLX:
8788   case X86::VMOVAPDZ256rm:
8789   case X86::VMOVUPDZ256rm:
8790   case X86::VMOVDQU8Z256rm:
8791   case X86::VMOVDQU16Z256rm:
8792   case X86::VMOVDQA32Z256rm:
8793   case X86::VMOVDQU32Z256rm:
8794   case X86::VMOVDQA64Z256rm:
8795   case X86::VMOVDQU64Z256rm:
8796   case X86::VMOVAPSZrm:
8797   case X86::VMOVUPSZrm:
8798   case X86::VMOVAPDZrm:
8799   case X86::VMOVUPDZrm:
8800   case X86::VMOVDQU8Zrm:
8801   case X86::VMOVDQU16Zrm:
8802   case X86::VMOVDQA32Zrm:
8803   case X86::VMOVDQU32Zrm:
8804   case X86::VMOVDQA64Zrm:
8805   case X86::VMOVDQU64Zrm:
8806   case X86::KMOVBkm:
8807   case X86::KMOVWkm:
8808   case X86::KMOVDkm:
8809   case X86::KMOVQkm:
8810     break;
8811   }
8812   switch (Opc2) {
8813   default: return false;
8814   case X86::MOV8rm:
8815   case X86::MOV16rm:
8816   case X86::MOV32rm:
8817   case X86::MOV64rm:
8818   case X86::LD_Fp32m:
8819   case X86::LD_Fp64m:
8820   case X86::LD_Fp80m:
8821   case X86::MOVSSrm:
8822   case X86::MOVSDrm:
8823   case X86::MMX_MOVD64rm:
8824   case X86::MMX_MOVQ64rm:
8825   case X86::MOVAPSrm:
8826   case X86::MOVUPSrm:
8827   case X86::MOVAPDrm:
8828   case X86::MOVUPDrm:
8829   case X86::MOVDQArm:
8830   case X86::MOVDQUrm:
8831   // AVX load instructions
8832   case X86::VMOVSSrm:
8833   case X86::VMOVSDrm:
8834   case X86::VMOVAPSrm:
8835   case X86::VMOVUPSrm:
8836   case X86::VMOVAPDrm:
8837   case X86::VMOVUPDrm:
8838   case X86::VMOVDQArm:
8839   case X86::VMOVDQUrm:
8840   case X86::VMOVAPSYrm:
8841   case X86::VMOVUPSYrm:
8842   case X86::VMOVAPDYrm:
8843   case X86::VMOVUPDYrm:
8844   case X86::VMOVDQAYrm:
8845   case X86::VMOVDQUYrm:
8846   // AVX512 load instructions
8847   case X86::VMOVSSZrm:
8848   case X86::VMOVSDZrm:
8849   case X86::VMOVAPSZ128rm:
8850   case X86::VMOVUPSZ128rm:
8851   case X86::VMOVAPSZ128rm_NOVLX:
8852   case X86::VMOVUPSZ128rm_NOVLX:
8853   case X86::VMOVAPDZ128rm:
8854   case X86::VMOVUPDZ128rm:
8855   case X86::VMOVDQU8Z128rm:
8856   case X86::VMOVDQU16Z128rm:
8857   case X86::VMOVDQA32Z128rm:
8858   case X86::VMOVDQU32Z128rm:
8859   case X86::VMOVDQA64Z128rm:
8860   case X86::VMOVDQU64Z128rm:
8861   case X86::VMOVAPSZ256rm:
8862   case X86::VMOVUPSZ256rm:
8863   case X86::VMOVAPSZ256rm_NOVLX:
8864   case X86::VMOVUPSZ256rm_NOVLX:
8865   case X86::VMOVAPDZ256rm:
8866   case X86::VMOVUPDZ256rm:
8867   case X86::VMOVDQU8Z256rm:
8868   case X86::VMOVDQU16Z256rm:
8869   case X86::VMOVDQA32Z256rm:
8870   case X86::VMOVDQU32Z256rm:
8871   case X86::VMOVDQA64Z256rm:
8872   case X86::VMOVDQU64Z256rm:
8873   case X86::VMOVAPSZrm:
8874   case X86::VMOVUPSZrm:
8875   case X86::VMOVAPDZrm:
8876   case X86::VMOVUPDZrm:
8877   case X86::VMOVDQU8Zrm:
8878   case X86::VMOVDQU16Zrm:
8879   case X86::VMOVDQA32Zrm:
8880   case X86::VMOVDQU32Zrm:
8881   case X86::VMOVDQA64Zrm:
8882   case X86::VMOVDQU64Zrm:
8883   case X86::KMOVBkm:
8884   case X86::KMOVWkm:
8885   case X86::KMOVDkm:
8886   case X86::KMOVQkm:
8887     break;
8888   }
8889 
8890   // Check if chain operands and base addresses match.
8891   if (Load1->getOperand(0) != Load2->getOperand(0) ||
8892       Load1->getOperand(5) != Load2->getOperand(5))
8893     return false;
8894   // Segment operands should match as well.
8895   if (Load1->getOperand(4) != Load2->getOperand(4))
8896     return false;
8897   // Scale should be 1, Index should be Reg0.
8898   if (Load1->getOperand(1) == Load2->getOperand(1) &&
8899       Load1->getOperand(2) == Load2->getOperand(2)) {
8900     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
8901       return false;
8902 
8903     // Now let's examine the displacements.
8904     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
8905         isa<ConstantSDNode>(Load2->getOperand(3))) {
8906       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
8907       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
8908       return true;
8909     }
8910   }
8911   return false;
8912 }
8913 
8914 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
8915                                            int64_t Offset1, int64_t Offset2,
8916                                            unsigned NumLoads) const {
8917   assert(Offset2 > Offset1);
8918   if ((Offset2 - Offset1) / 8 > 64)
8919     return false;
8920 
8921   unsigned Opc1 = Load1->getMachineOpcode();
8922   unsigned Opc2 = Load2->getMachineOpcode();
8923   if (Opc1 != Opc2)
8924     return false;  // FIXME: overly conservative?
8925 
8926   switch (Opc1) {
8927   default: break;
8928   case X86::LD_Fp32m:
8929   case X86::LD_Fp64m:
8930   case X86::LD_Fp80m:
8931   case X86::MMX_MOVD64rm:
8932   case X86::MMX_MOVQ64rm:
8933     return false;
8934   }
8935 
8936   EVT VT = Load1->getValueType(0);
8937   switch (VT.getSimpleVT().SimpleTy) {
8938   default:
8939     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
8940     // have 16 of them to play with.
8941     if (Subtarget.is64Bit()) {
8942       if (NumLoads >= 3)
8943         return false;
8944     } else if (NumLoads) {
8945       return false;
8946     }
8947     break;
8948   case MVT::i8:
8949   case MVT::i16:
8950   case MVT::i32:
8951   case MVT::i64:
8952   case MVT::f32:
8953   case MVT::f64:
8954     if (NumLoads)
8955       return false;
8956     break;
8957   }
8958 
8959   return true;
8960 }
8961 
8962 bool X86InstrInfo::
8963 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
8964   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
8965   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
8966   Cond[0].setImm(GetOppositeBranchCondition(CC));
8967   return false;
8968 }
8969 
8970 bool X86InstrInfo::
8971 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
8972   // FIXME: Return false for x87 stack register classes for now. We can't
8973   // allow any loads of these registers before FpGet_ST0_80.
8974   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
8975            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
8976 }
8977 
8978 /// Return a virtual register initialized with the
8979 /// the global base register value. Output instructions required to
8980 /// initialize the register in the function entry block, if necessary.
8981 ///
8982 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
8983 ///
8984 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
8985   assert(!Subtarget.is64Bit() &&
8986          "X86-64 PIC uses RIP relative addressing");
8987 
8988   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
8989   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
8990   if (GlobalBaseReg != 0)
8991     return GlobalBaseReg;
8992 
8993   // Create the register. The code to initialize it is inserted
8994   // later, by the CGBR pass (below).
8995   MachineRegisterInfo &RegInfo = MF->getRegInfo();
8996   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
8997   X86FI->setGlobalBaseReg(GlobalBaseReg);
8998   return GlobalBaseReg;
8999 }
9000 
9001 // These are the replaceable SSE instructions. Some of these have Int variants
9002 // that we don't include here. We don't want to replace instructions selected
9003 // by intrinsics.
9004 static const uint16_t ReplaceableInstrs[][3] = {
9005   //PackedSingle     PackedDouble    PackedInt
9006   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
9007   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
9008   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
9009   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
9010   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
9011   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr },
9012   { X86::MOVSDmr,    X86::MOVSDmr,   X86::MOVPQI2QImr },
9013   { X86::MOVSSmr,    X86::MOVSSmr,   X86::MOVPDI2DImr },
9014   { X86::MOVSDrm,    X86::MOVSDrm,   X86::MOVQI2PQIrm },
9015   { X86::MOVSSrm,    X86::MOVSSrm,   X86::MOVDI2PDIrm },
9016   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
9017   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
9018   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
9019   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
9020   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
9021   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
9022   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
9023   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
9024   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
9025   // AVX 128-bit support
9026   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
9027   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
9028   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
9029   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
9030   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
9031   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr },
9032   { X86::VMOVSDmr,   X86::VMOVSDmr,   X86::VMOVPQI2QImr },
9033   { X86::VMOVSSmr,   X86::VMOVSSmr,   X86::VMOVPDI2DImr },
9034   { X86::VMOVSDrm,   X86::VMOVSDrm,   X86::VMOVQI2PQIrm },
9035   { X86::VMOVSSrm,   X86::VMOVSSrm,   X86::VMOVDI2PDIrm },
9036   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
9037   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
9038   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
9039   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
9040   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
9041   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
9042   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
9043   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
9044   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
9045   // AVX 256-bit support
9046   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
9047   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
9048   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
9049   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
9050   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
9051   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr },
9052   // AVX512 support
9053   { X86::VMOVLPSZ128mr,  X86::VMOVLPDZ128mr,  X86::VMOVPQI2QIZmr  },
9054   { X86::VMOVNTPSZ128mr, X86::VMOVNTPDZ128mr, X86::VMOVNTDQZ128mr },
9055   { X86::VMOVNTPSZ256mr, X86::VMOVNTPDZ256mr, X86::VMOVNTDQZ256mr },
9056   { X86::VMOVNTPSZmr,    X86::VMOVNTPDZmr,    X86::VMOVNTDQZmr    },
9057   { X86::VMOVSDZmr,      X86::VMOVSDZmr,      X86::VMOVPQI2QIZmr  },
9058   { X86::VMOVSSZmr,      X86::VMOVSSZmr,      X86::VMOVPDI2DIZmr  },
9059   { X86::VMOVSDZrm,      X86::VMOVSDZrm,      X86::VMOVQI2PQIZrm  },
9060   { X86::VMOVSSZrm,      X86::VMOVSSZrm,      X86::VMOVDI2PDIZrm  },
9061   { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128r, X86::VPBROADCASTDZ128r },
9062   { X86::VBROADCASTSSZ128m, X86::VBROADCASTSSZ128m, X86::VPBROADCASTDZ128m },
9063   { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256r, X86::VPBROADCASTDZ256r },
9064   { X86::VBROADCASTSSZ256m, X86::VBROADCASTSSZ256m, X86::VPBROADCASTDZ256m },
9065   { X86::VBROADCASTSSZr,    X86::VBROADCASTSSZr,    X86::VPBROADCASTDZr },
9066   { X86::VBROADCASTSSZm,    X86::VBROADCASTSSZm,    X86::VPBROADCASTDZm },
9067   { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256r, X86::VPBROADCASTQZ256r },
9068   { X86::VBROADCASTSDZ256m, X86::VBROADCASTSDZ256m, X86::VPBROADCASTQZ256m },
9069   { X86::VBROADCASTSDZr,    X86::VBROADCASTSDZr,    X86::VPBROADCASTQZr },
9070   { X86::VBROADCASTSDZm,    X86::VBROADCASTSDZm,    X86::VPBROADCASTQZm },
9071 };
9072 
9073 static const uint16_t ReplaceableInstrsAVX2[][3] = {
9074   //PackedSingle       PackedDouble       PackedInt
9075   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
9076   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
9077   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
9078   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
9079   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
9080   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
9081   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
9082   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
9083   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
9084   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
9085   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
9086   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
9087   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
9088   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
9089   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
9090   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm},
9091   { X86::VBROADCASTF128,  X86::VBROADCASTF128,  X86::VBROADCASTI128 },
9092 };
9093 
9094 static const uint16_t ReplaceableInstrsAVX2InsertExtract[][3] = {
9095   //PackedSingle       PackedDouble       PackedInt
9096   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
9097   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
9098   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
9099   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
9100 };
9101 
9102 static const uint16_t ReplaceableInstrsAVX512[][4] = {
9103   // Two integer columns for 64-bit and 32-bit elements.
9104   //PackedSingle        PackedDouble        PackedInt             PackedInt
9105   { X86::VMOVAPSZ128mr, X86::VMOVAPDZ128mr, X86::VMOVDQA64Z128mr, X86::VMOVDQA32Z128mr  },
9106   { X86::VMOVAPSZ128rm, X86::VMOVAPDZ128rm, X86::VMOVDQA64Z128rm, X86::VMOVDQA32Z128rm  },
9107   { X86::VMOVAPSZ128rr, X86::VMOVAPDZ128rr, X86::VMOVDQA64Z128rr, X86::VMOVDQA32Z128rr  },
9108   { X86::VMOVUPSZ128mr, X86::VMOVUPDZ128mr, X86::VMOVDQU64Z128mr, X86::VMOVDQU32Z128mr  },
9109   { X86::VMOVUPSZ128rm, X86::VMOVUPDZ128rm, X86::VMOVDQU64Z128rm, X86::VMOVDQU32Z128rm  },
9110   { X86::VMOVAPSZ256mr, X86::VMOVAPDZ256mr, X86::VMOVDQA64Z256mr, X86::VMOVDQA32Z256mr  },
9111   { X86::VMOVAPSZ256rm, X86::VMOVAPDZ256rm, X86::VMOVDQA64Z256rm, X86::VMOVDQA32Z256rm  },
9112   { X86::VMOVAPSZ256rr, X86::VMOVAPDZ256rr, X86::VMOVDQA64Z256rr, X86::VMOVDQA32Z256rr  },
9113   { X86::VMOVUPSZ256mr, X86::VMOVUPDZ256mr, X86::VMOVDQU64Z256mr, X86::VMOVDQU32Z256mr  },
9114   { X86::VMOVUPSZ256rm, X86::VMOVUPDZ256rm, X86::VMOVDQU64Z256rm, X86::VMOVDQU32Z256rm  },
9115   { X86::VMOVAPSZmr,    X86::VMOVAPDZmr,    X86::VMOVDQA64Zmr,    X86::VMOVDQA32Zmr     },
9116   { X86::VMOVAPSZrm,    X86::VMOVAPDZrm,    X86::VMOVDQA64Zrm,    X86::VMOVDQA32Zrm     },
9117   { X86::VMOVAPSZrr,    X86::VMOVAPDZrr,    X86::VMOVDQA64Zrr,    X86::VMOVDQA32Zrr     },
9118   { X86::VMOVUPSZmr,    X86::VMOVUPDZmr,    X86::VMOVDQU64Zmr,    X86::VMOVDQU32Zmr     },
9119   { X86::VMOVUPSZrm,    X86::VMOVUPDZrm,    X86::VMOVDQU64Zrm,    X86::VMOVDQU32Zrm     },
9120 };
9121 
9122 static const uint16_t ReplaceableInstrsAVX512DQ[][4] = {
9123   // Two integer columns for 64-bit and 32-bit elements.
9124   //PackedSingle        PackedDouble        PackedInt           PackedInt
9125   { X86::VANDNPSZ128rm, X86::VANDNPDZ128rm, X86::VPANDNQZ128rm, X86::VPANDNDZ128rm },
9126   { X86::VANDNPSZ128rr, X86::VANDNPDZ128rr, X86::VPANDNQZ128rr, X86::VPANDNDZ128rr },
9127   { X86::VANDPSZ128rm,  X86::VANDPDZ128rm,  X86::VPANDQZ128rm,  X86::VPANDDZ128rm  },
9128   { X86::VANDPSZ128rr,  X86::VANDPDZ128rr,  X86::VPANDQZ128rr,  X86::VPANDDZ128rr  },
9129   { X86::VORPSZ128rm,   X86::VORPDZ128rm,   X86::VPORQZ128rm,   X86::VPORDZ128rm   },
9130   { X86::VORPSZ128rr,   X86::VORPDZ128rr,   X86::VPORQZ128rr,   X86::VPORDZ128rr   },
9131   { X86::VXORPSZ128rm,  X86::VXORPDZ128rm,  X86::VPXORQZ128rm,  X86::VPXORDZ128rm  },
9132   { X86::VXORPSZ128rr,  X86::VXORPDZ128rr,  X86::VPXORQZ128rr,  X86::VPXORDZ128rr  },
9133   { X86::VANDNPSZ256rm, X86::VANDNPDZ256rm, X86::VPANDNQZ256rm, X86::VPANDNDZ256rm },
9134   { X86::VANDNPSZ256rr, X86::VANDNPDZ256rr, X86::VPANDNQZ256rr, X86::VPANDNDZ256rr },
9135   { X86::VANDPSZ256rm,  X86::VANDPDZ256rm,  X86::VPANDQZ256rm,  X86::VPANDDZ256rm  },
9136   { X86::VANDPSZ256rr,  X86::VANDPDZ256rr,  X86::VPANDQZ256rr,  X86::VPANDDZ256rr  },
9137   { X86::VORPSZ256rm,   X86::VORPDZ256rm,   X86::VPORQZ256rm,   X86::VPORDZ256rm   },
9138   { X86::VORPSZ256rr,   X86::VORPDZ256rr,   X86::VPORQZ256rr,   X86::VPORDZ256rr   },
9139   { X86::VXORPSZ256rm,  X86::VXORPDZ256rm,  X86::VPXORQZ256rm,  X86::VPXORDZ256rm  },
9140   { X86::VXORPSZ256rr,  X86::VXORPDZ256rr,  X86::VPXORQZ256rr,  X86::VPXORDZ256rr  },
9141   { X86::VANDNPSZrm,    X86::VANDNPDZrm,    X86::VPANDNQZrm,    X86::VPANDNDZrm    },
9142   { X86::VANDNPSZrr,    X86::VANDNPDZrr,    X86::VPANDNQZrr,    X86::VPANDNDZrr    },
9143   { X86::VANDPSZrm,     X86::VANDPDZrm,     X86::VPANDQZrm,     X86::VPANDDZrm     },
9144   { X86::VANDPSZrr,     X86::VANDPDZrr,     X86::VPANDQZrr,     X86::VPANDDZrr     },
9145   { X86::VORPSZrm,      X86::VORPDZrm,      X86::VPORQZrm,      X86::VPORDZrm      },
9146   { X86::VORPSZrr,      X86::VORPDZrr,      X86::VPORQZrr,      X86::VPORDZrr      },
9147   { X86::VXORPSZrm,     X86::VXORPDZrm,     X86::VPXORQZrm,     X86::VPXORDZrm     },
9148   { X86::VXORPSZrr,     X86::VXORPDZrr,     X86::VPXORQZrr,     X86::VPXORDZrr     },
9149 };
9150 
9151 static const uint16_t ReplaceableInstrsAVX512DQMasked[][4] = {
9152   // Two integer columns for 64-bit and 32-bit elements.
9153   //PackedSingle          PackedDouble
9154   //PackedInt             PackedInt
9155   { X86::VANDNPSZ128rmk,  X86::VANDNPDZ128rmk,
9156     X86::VPANDNQZ128rmk,  X86::VPANDNDZ128rmk  },
9157   { X86::VANDNPSZ128rmkz, X86::VANDNPDZ128rmkz,
9158     X86::VPANDNQZ128rmkz, X86::VPANDNDZ128rmkz },
9159   { X86::VANDNPSZ128rrk,  X86::VANDNPDZ128rrk,
9160     X86::VPANDNQZ128rrk,  X86::VPANDNDZ128rrk  },
9161   { X86::VANDNPSZ128rrkz, X86::VANDNPDZ128rrkz,
9162     X86::VPANDNQZ128rrkz, X86::VPANDNDZ128rrkz },
9163   { X86::VANDPSZ128rmk,   X86::VANDPDZ128rmk,
9164     X86::VPANDQZ128rmk,   X86::VPANDDZ128rmk   },
9165   { X86::VANDPSZ128rmkz,  X86::VANDPDZ128rmkz,
9166     X86::VPANDQZ128rmkz,  X86::VPANDDZ128rmkz  },
9167   { X86::VANDPSZ128rrk,   X86::VANDPDZ128rrk,
9168     X86::VPANDQZ128rrk,   X86::VPANDDZ128rrk   },
9169   { X86::VANDPSZ128rrkz,  X86::VANDPDZ128rrkz,
9170     X86::VPANDQZ128rrkz,  X86::VPANDDZ128rrkz  },
9171   { X86::VORPSZ128rmk,    X86::VORPDZ128rmk,
9172     X86::VPORQZ128rmk,    X86::VPORDZ128rmk    },
9173   { X86::VORPSZ128rmkz,   X86::VORPDZ128rmkz,
9174     X86::VPORQZ128rmkz,   X86::VPORDZ128rmkz   },
9175   { X86::VORPSZ128rrk,    X86::VORPDZ128rrk,
9176     X86::VPORQZ128rrk,    X86::VPORDZ128rrk    },
9177   { X86::VORPSZ128rrkz,   X86::VORPDZ128rrkz,
9178     X86::VPORQZ128rrkz,   X86::VPORDZ128rrkz   },
9179   { X86::VXORPSZ128rmk,   X86::VXORPDZ128rmk,
9180     X86::VPXORQZ128rmk,   X86::VPXORDZ128rmk   },
9181   { X86::VXORPSZ128rmkz,  X86::VXORPDZ128rmkz,
9182     X86::VPXORQZ128rmkz,  X86::VPXORDZ128rmkz  },
9183   { X86::VXORPSZ128rrk,   X86::VXORPDZ128rrk,
9184     X86::VPXORQZ128rrk,   X86::VPXORDZ128rrk   },
9185   { X86::VXORPSZ128rrkz,  X86::VXORPDZ128rrkz,
9186     X86::VPXORQZ128rrkz,  X86::VPXORDZ128rrkz  },
9187   { X86::VANDNPSZ256rmk,  X86::VANDNPDZ256rmk,
9188     X86::VPANDNQZ256rmk,  X86::VPANDNDZ256rmk  },
9189   { X86::VANDNPSZ256rmkz, X86::VANDNPDZ256rmkz,
9190     X86::VPANDNQZ256rmkz, X86::VPANDNDZ256rmkz },
9191   { X86::VANDNPSZ256rrk,  X86::VANDNPDZ256rrk,
9192     X86::VPANDNQZ256rrk,  X86::VPANDNDZ256rrk  },
9193   { X86::VANDNPSZ256rrkz, X86::VANDNPDZ256rrkz,
9194     X86::VPANDNQZ256rrkz, X86::VPANDNDZ256rrkz },
9195   { X86::VANDPSZ256rmk,   X86::VANDPDZ256rmk,
9196     X86::VPANDQZ256rmk,   X86::VPANDDZ256rmk   },
9197   { X86::VANDPSZ256rmkz,  X86::VANDPDZ256rmkz,
9198     X86::VPANDQZ256rmkz,  X86::VPANDDZ256rmkz  },
9199   { X86::VANDPSZ256rrk,   X86::VANDPDZ256rrk,
9200     X86::VPANDQZ256rrk,   X86::VPANDDZ256rrk   },
9201   { X86::VANDPSZ256rrkz,  X86::VANDPDZ256rrkz,
9202     X86::VPANDQZ256rrkz,  X86::VPANDDZ256rrkz  },
9203   { X86::VORPSZ256rmk,    X86::VORPDZ256rmk,
9204     X86::VPORQZ256rmk,    X86::VPORDZ256rmk    },
9205   { X86::VORPSZ256rmkz,   X86::VORPDZ256rmkz,
9206     X86::VPORQZ256rmkz,   X86::VPORDZ256rmkz   },
9207   { X86::VORPSZ256rrk,    X86::VORPDZ256rrk,
9208     X86::VPORQZ256rrk,    X86::VPORDZ256rrk    },
9209   { X86::VORPSZ256rrkz,   X86::VORPDZ256rrkz,
9210     X86::VPORQZ256rrkz,   X86::VPORDZ256rrkz   },
9211   { X86::VXORPSZ256rmk,   X86::VXORPDZ256rmk,
9212     X86::VPXORQZ256rmk,   X86::VPXORDZ256rmk   },
9213   { X86::VXORPSZ256rmkz,  X86::VXORPDZ256rmkz,
9214     X86::VPXORQZ256rmkz,  X86::VPXORDZ256rmkz  },
9215   { X86::VXORPSZ256rrk,   X86::VXORPDZ256rrk,
9216     X86::VPXORQZ256rrk,   X86::VPXORDZ256rrk   },
9217   { X86::VXORPSZ256rrkz,  X86::VXORPDZ256rrkz,
9218     X86::VPXORQZ256rrkz,  X86::VPXORDZ256rrkz  },
9219   { X86::VANDNPSZrmk,     X86::VANDNPDZrmk,
9220     X86::VPANDNQZrmk,     X86::VPANDNDZrmk     },
9221   { X86::VANDNPSZrmkz,    X86::VANDNPDZrmkz,
9222     X86::VPANDNQZrmkz,    X86::VPANDNDZrmkz    },
9223   { X86::VANDNPSZrrk,     X86::VANDNPDZrrk,
9224     X86::VPANDNQZrrk,     X86::VPANDNDZrrk     },
9225   { X86::VANDNPSZrrkz,    X86::VANDNPDZrrkz,
9226     X86::VPANDNQZrrkz,    X86::VPANDNDZrrkz    },
9227   { X86::VANDPSZrmk,      X86::VANDPDZrmk,
9228     X86::VPANDQZrmk,      X86::VPANDDZrmk      },
9229   { X86::VANDPSZrmkz,     X86::VANDPDZrmkz,
9230     X86::VPANDQZrmkz,     X86::VPANDDZrmkz     },
9231   { X86::VANDPSZrrk,      X86::VANDPDZrrk,
9232     X86::VPANDQZrrk,      X86::VPANDDZrrk      },
9233   { X86::VANDPSZrrkz,     X86::VANDPDZrrkz,
9234     X86::VPANDQZrrkz,     X86::VPANDDZrrkz     },
9235   { X86::VORPSZrmk,       X86::VORPDZrmk,
9236     X86::VPORQZrmk,       X86::VPORDZrmk       },
9237   { X86::VORPSZrmkz,      X86::VORPDZrmkz,
9238     X86::VPORQZrmkz,      X86::VPORDZrmkz      },
9239   { X86::VORPSZrrk,       X86::VORPDZrrk,
9240     X86::VPORQZrrk,       X86::VPORDZrrk       },
9241   { X86::VORPSZrrkz,      X86::VORPDZrrkz,
9242     X86::VPORQZrrkz,      X86::VPORDZrrkz      },
9243   { X86::VXORPSZrmk,      X86::VXORPDZrmk,
9244     X86::VPXORQZrmk,      X86::VPXORDZrmk      },
9245   { X86::VXORPSZrmkz,     X86::VXORPDZrmkz,
9246     X86::VPXORQZrmkz,     X86::VPXORDZrmkz     },
9247   { X86::VXORPSZrrk,      X86::VXORPDZrrk,
9248     X86::VPXORQZrrk,      X86::VPXORDZrrk      },
9249   { X86::VXORPSZrrkz,     X86::VXORPDZrrkz,
9250     X86::VPXORQZrrkz,     X86::VPXORDZrrkz     },
9251   // Broadcast loads can be handled the same as masked operations to avoid
9252   // changing element size.
9253   { X86::VANDNPSZ128rmb,  X86::VANDNPDZ128rmb,
9254     X86::VPANDNQZ128rmb,  X86::VPANDNDZ128rmb  },
9255   { X86::VANDPSZ128rmb,   X86::VANDPDZ128rmb,
9256     X86::VPANDQZ128rmb,   X86::VPANDDZ128rmb   },
9257   { X86::VORPSZ128rmb,    X86::VORPDZ128rmb,
9258     X86::VPORQZ128rmb,    X86::VPORDZ128rmb    },
9259   { X86::VXORPSZ128rmb,   X86::VXORPDZ128rmb,
9260     X86::VPXORQZ128rmb,   X86::VPXORDZ128rmb   },
9261   { X86::VANDNPSZ256rmb,  X86::VANDNPDZ256rmb,
9262     X86::VPANDNQZ256rmb,  X86::VPANDNDZ256rmb  },
9263   { X86::VANDPSZ256rmb,   X86::VANDPDZ256rmb,
9264     X86::VPANDQZ256rmb,   X86::VPANDDZ256rmb   },
9265   { X86::VORPSZ256rmb,    X86::VORPDZ256rmb,
9266     X86::VPORQZ256rmb,    X86::VPORDZ256rmb    },
9267   { X86::VXORPSZ256rmb,   X86::VXORPDZ256rmb,
9268     X86::VPXORQZ256rmb,   X86::VPXORDZ256rmb   },
9269   { X86::VANDNPSZrmb,     X86::VANDNPDZrmb,
9270     X86::VPANDNQZrmb,     X86::VPANDNDZrmb     },
9271   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
9272     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
9273   { X86::VANDPSZrmb,      X86::VANDPDZrmb,
9274     X86::VPANDQZrmb,      X86::VPANDDZrmb      },
9275   { X86::VORPSZrmb,       X86::VORPDZrmb,
9276     X86::VPORQZrmb,       X86::VPORDZrmb       },
9277   { X86::VXORPSZrmb,      X86::VXORPDZrmb,
9278     X86::VPXORQZrmb,      X86::VPXORDZrmb      },
9279   { X86::VANDNPSZ128rmbk, X86::VANDNPDZ128rmbk,
9280     X86::VPANDNQZ128rmbk, X86::VPANDNDZ128rmbk },
9281   { X86::VANDPSZ128rmbk,  X86::VANDPDZ128rmbk,
9282     X86::VPANDQZ128rmbk,  X86::VPANDDZ128rmbk  },
9283   { X86::VORPSZ128rmbk,   X86::VORPDZ128rmbk,
9284     X86::VPORQZ128rmbk,   X86::VPORDZ128rmbk   },
9285   { X86::VXORPSZ128rmbk,  X86::VXORPDZ128rmbk,
9286     X86::VPXORQZ128rmbk,  X86::VPXORDZ128rmbk  },
9287   { X86::VANDNPSZ256rmbk, X86::VANDNPDZ256rmbk,
9288     X86::VPANDNQZ256rmbk, X86::VPANDNDZ256rmbk },
9289   { X86::VANDPSZ256rmbk,  X86::VANDPDZ256rmbk,
9290     X86::VPANDQZ256rmbk,  X86::VPANDDZ256rmbk  },
9291   { X86::VORPSZ256rmbk,   X86::VORPDZ256rmbk,
9292     X86::VPORQZ256rmbk,   X86::VPORDZ256rmbk   },
9293   { X86::VXORPSZ256rmbk,  X86::VXORPDZ256rmbk,
9294     X86::VPXORQZ256rmbk,  X86::VPXORDZ256rmbk  },
9295   { X86::VANDNPSZrmbk,    X86::VANDNPDZrmbk,
9296     X86::VPANDNQZrmbk,    X86::VPANDNDZrmbk    },
9297   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
9298     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
9299   { X86::VANDPSZrmbk,     X86::VANDPDZrmbk,
9300     X86::VPANDQZrmbk,     X86::VPANDDZrmbk     },
9301   { X86::VORPSZrmbk,      X86::VORPDZrmbk,
9302     X86::VPORQZrmbk,      X86::VPORDZrmbk      },
9303   { X86::VXORPSZrmbk,     X86::VXORPDZrmbk,
9304     X86::VPXORQZrmbk,     X86::VPXORDZrmbk     },
9305   { X86::VANDNPSZ128rmbkz,X86::VANDNPDZ128rmbkz,
9306     X86::VPANDNQZ128rmbkz,X86::VPANDNDZ128rmbkz},
9307   { X86::VANDPSZ128rmbkz, X86::VANDPDZ128rmbkz,
9308     X86::VPANDQZ128rmbkz, X86::VPANDDZ128rmbkz },
9309   { X86::VORPSZ128rmbkz,  X86::VORPDZ128rmbkz,
9310     X86::VPORQZ128rmbkz,  X86::VPORDZ128rmbkz  },
9311   { X86::VXORPSZ128rmbkz, X86::VXORPDZ128rmbkz,
9312     X86::VPXORQZ128rmbkz, X86::VPXORDZ128rmbkz },
9313   { X86::VANDNPSZ256rmbkz,X86::VANDNPDZ256rmbkz,
9314     X86::VPANDNQZ256rmbkz,X86::VPANDNDZ256rmbkz},
9315   { X86::VANDPSZ256rmbkz, X86::VANDPDZ256rmbkz,
9316     X86::VPANDQZ256rmbkz, X86::VPANDDZ256rmbkz },
9317   { X86::VORPSZ256rmbkz,  X86::VORPDZ256rmbkz,
9318     X86::VPORQZ256rmbkz,  X86::VPORDZ256rmbkz  },
9319   { X86::VXORPSZ256rmbkz, X86::VXORPDZ256rmbkz,
9320     X86::VPXORQZ256rmbkz, X86::VPXORDZ256rmbkz },
9321   { X86::VANDNPSZrmbkz,   X86::VANDNPDZrmbkz,
9322     X86::VPANDNQZrmbkz,   X86::VPANDNDZrmbkz   },
9323   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
9324     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
9325   { X86::VANDPSZrmbkz,    X86::VANDPDZrmbkz,
9326     X86::VPANDQZrmbkz,    X86::VPANDDZrmbkz    },
9327   { X86::VORPSZrmbkz,     X86::VORPDZrmbkz,
9328     X86::VPORQZrmbkz,     X86::VPORDZrmbkz     },
9329   { X86::VXORPSZrmbkz,    X86::VXORPDZrmbkz,
9330     X86::VPXORQZrmbkz,    X86::VPXORDZrmbkz    },
9331 };
9332 
9333 // FIXME: Some shuffle and unpack instructions have equivalents in different
9334 // domains, but they require a bit more work than just switching opcodes.
9335 
9336 static const uint16_t *lookup(unsigned opcode, unsigned domain,
9337                               ArrayRef<uint16_t[3]> Table) {
9338   for (const uint16_t (&Row)[3] : Table)
9339     if (Row[domain-1] == opcode)
9340       return Row;
9341   return nullptr;
9342 }
9343 
9344 static const uint16_t *lookupAVX512(unsigned opcode, unsigned domain,
9345                                     ArrayRef<uint16_t[4]> Table) {
9346   // If this is the integer domain make sure to check both integer columns.
9347   for (const uint16_t (&Row)[4] : Table)
9348     if (Row[domain-1] == opcode || (domain == 3 && Row[3] == opcode))
9349       return Row;
9350   return nullptr;
9351 }
9352 
9353 std::pair<uint16_t, uint16_t>
9354 X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
9355   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9356   unsigned opcode = MI.getOpcode();
9357   uint16_t validDomains = 0;
9358   if (domain) {
9359     if (lookup(MI.getOpcode(), domain, ReplaceableInstrs)) {
9360       validDomains = 0xe;
9361     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2)) {
9362       validDomains = Subtarget.hasAVX2() ? 0xe : 0x6;
9363     } else if (lookup(opcode, domain, ReplaceableInstrsAVX2InsertExtract)) {
9364       // Insert/extract instructions should only effect domain if AVX2
9365       // is enabled.
9366       if (!Subtarget.hasAVX2())
9367         return std::make_pair(0, 0);
9368       validDomains = 0xe;
9369     } else if (lookupAVX512(opcode, domain, ReplaceableInstrsAVX512)) {
9370       validDomains = 0xe;
9371     } else if (Subtarget.hasDQI() && lookupAVX512(opcode, domain,
9372                                                   ReplaceableInstrsAVX512DQ)) {
9373       validDomains = 0xe;
9374     } else if (Subtarget.hasDQI()) {
9375       if (const uint16_t *table = lookupAVX512(opcode, domain,
9376                                              ReplaceableInstrsAVX512DQMasked)) {
9377         if (domain == 1 || (domain == 3 && table[3] == opcode))
9378           validDomains = 0xa;
9379         else
9380           validDomains = 0xc;
9381       }
9382     }
9383   }
9384   return std::make_pair(domain, validDomains);
9385 }
9386 
9387 void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
9388   assert(Domain>0 && Domain<4 && "Invalid execution domain");
9389   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
9390   assert(dom && "Not an SSE instruction");
9391   const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
9392   if (!table) { // try the other table
9393     assert((Subtarget.hasAVX2() || Domain < 3) &&
9394            "256-bit vector operations only available in AVX2");
9395     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
9396   }
9397   if (!table) { // try the other table
9398     assert(Subtarget.hasAVX2() &&
9399            "256-bit insert/extract only available in AVX2");
9400     table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2InsertExtract);
9401   }
9402   if (!table) { // try the AVX512 table
9403     assert(Subtarget.hasAVX512() && "Requires AVX-512");
9404     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512);
9405     // Don't change integer Q instructions to D instructions.
9406     if (table && Domain == 3 && table[3] == MI.getOpcode())
9407       Domain = 4;
9408   }
9409   if (!table) { // try the AVX512DQ table
9410     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
9411     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQ);
9412     // Don't change integer Q instructions to D instructions and
9413     // use D intructions if we started with a PS instruction.
9414     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9415       Domain = 4;
9416   }
9417   if (!table) { // try the AVX512DQMasked table
9418     assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ");
9419     table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
9420     if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
9421       Domain = 4;
9422   }
9423   assert(table && "Cannot change domain");
9424   MI.setDesc(get(table[Domain - 1]));
9425 }
9426 
9427 /// Return the noop instruction to use for a noop.
9428 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
9429   NopInst.setOpcode(X86::NOOP);
9430 }
9431 
9432 bool X86InstrInfo::isHighLatencyDef(int opc) const {
9433   switch (opc) {
9434   default: return false;
9435   case X86::DIVPDrm:
9436   case X86::DIVPDrr:
9437   case X86::DIVPSrm:
9438   case X86::DIVPSrr:
9439   case X86::DIVSDrm:
9440   case X86::DIVSDrm_Int:
9441   case X86::DIVSDrr:
9442   case X86::DIVSDrr_Int:
9443   case X86::DIVSSrm:
9444   case X86::DIVSSrm_Int:
9445   case X86::DIVSSrr:
9446   case X86::DIVSSrr_Int:
9447   case X86::SQRTPDm:
9448   case X86::SQRTPDr:
9449   case X86::SQRTPSm:
9450   case X86::SQRTPSr:
9451   case X86::SQRTSDm:
9452   case X86::SQRTSDm_Int:
9453   case X86::SQRTSDr:
9454   case X86::SQRTSDr_Int:
9455   case X86::SQRTSSm:
9456   case X86::SQRTSSm_Int:
9457   case X86::SQRTSSr:
9458   case X86::SQRTSSr_Int:
9459   // AVX instructions with high latency
9460   case X86::VDIVPDrm:
9461   case X86::VDIVPDrr:
9462   case X86::VDIVPDYrm:
9463   case X86::VDIVPDYrr:
9464   case X86::VDIVPSrm:
9465   case X86::VDIVPSrr:
9466   case X86::VDIVPSYrm:
9467   case X86::VDIVPSYrr:
9468   case X86::VDIVSDrm:
9469   case X86::VDIVSDrm_Int:
9470   case X86::VDIVSDrr:
9471   case X86::VDIVSDrr_Int:
9472   case X86::VDIVSSrm:
9473   case X86::VDIVSSrm_Int:
9474   case X86::VDIVSSrr:
9475   case X86::VDIVSSrr_Int:
9476   case X86::VSQRTPDm:
9477   case X86::VSQRTPDr:
9478   case X86::VSQRTPDYm:
9479   case X86::VSQRTPDYr:
9480   case X86::VSQRTPSm:
9481   case X86::VSQRTPSr:
9482   case X86::VSQRTPSYm:
9483   case X86::VSQRTPSYr:
9484   case X86::VSQRTSDm:
9485   case X86::VSQRTSDm_Int:
9486   case X86::VSQRTSDr:
9487   case X86::VSQRTSDr_Int:
9488   case X86::VSQRTSSm:
9489   case X86::VSQRTSSm_Int:
9490   case X86::VSQRTSSr:
9491   case X86::VSQRTSSr_Int:
9492   // AVX512 instructions with high latency
9493   case X86::VDIVPDZ128rm:
9494   case X86::VDIVPDZ128rmb:
9495   case X86::VDIVPDZ128rmbk:
9496   case X86::VDIVPDZ128rmbkz:
9497   case X86::VDIVPDZ128rmk:
9498   case X86::VDIVPDZ128rmkz:
9499   case X86::VDIVPDZ128rr:
9500   case X86::VDIVPDZ128rrk:
9501   case X86::VDIVPDZ128rrkz:
9502   case X86::VDIVPDZ256rm:
9503   case X86::VDIVPDZ256rmb:
9504   case X86::VDIVPDZ256rmbk:
9505   case X86::VDIVPDZ256rmbkz:
9506   case X86::VDIVPDZ256rmk:
9507   case X86::VDIVPDZ256rmkz:
9508   case X86::VDIVPDZ256rr:
9509   case X86::VDIVPDZ256rrk:
9510   case X86::VDIVPDZ256rrkz:
9511   case X86::VDIVPDZrb:
9512   case X86::VDIVPDZrbk:
9513   case X86::VDIVPDZrbkz:
9514   case X86::VDIVPDZrm:
9515   case X86::VDIVPDZrmb:
9516   case X86::VDIVPDZrmbk:
9517   case X86::VDIVPDZrmbkz:
9518   case X86::VDIVPDZrmk:
9519   case X86::VDIVPDZrmkz:
9520   case X86::VDIVPDZrr:
9521   case X86::VDIVPDZrrk:
9522   case X86::VDIVPDZrrkz:
9523   case X86::VDIVPSZ128rm:
9524   case X86::VDIVPSZ128rmb:
9525   case X86::VDIVPSZ128rmbk:
9526   case X86::VDIVPSZ128rmbkz:
9527   case X86::VDIVPSZ128rmk:
9528   case X86::VDIVPSZ128rmkz:
9529   case X86::VDIVPSZ128rr:
9530   case X86::VDIVPSZ128rrk:
9531   case X86::VDIVPSZ128rrkz:
9532   case X86::VDIVPSZ256rm:
9533   case X86::VDIVPSZ256rmb:
9534   case X86::VDIVPSZ256rmbk:
9535   case X86::VDIVPSZ256rmbkz:
9536   case X86::VDIVPSZ256rmk:
9537   case X86::VDIVPSZ256rmkz:
9538   case X86::VDIVPSZ256rr:
9539   case X86::VDIVPSZ256rrk:
9540   case X86::VDIVPSZ256rrkz:
9541   case X86::VDIVPSZrb:
9542   case X86::VDIVPSZrbk:
9543   case X86::VDIVPSZrbkz:
9544   case X86::VDIVPSZrm:
9545   case X86::VDIVPSZrmb:
9546   case X86::VDIVPSZrmbk:
9547   case X86::VDIVPSZrmbkz:
9548   case X86::VDIVPSZrmk:
9549   case X86::VDIVPSZrmkz:
9550   case X86::VDIVPSZrr:
9551   case X86::VDIVPSZrrk:
9552   case X86::VDIVPSZrrkz:
9553   case X86::VDIVSDZrm:
9554   case X86::VDIVSDZrr:
9555   case X86::VDIVSDZrm_Int:
9556   case X86::VDIVSDZrm_Intk:
9557   case X86::VDIVSDZrm_Intkz:
9558   case X86::VDIVSDZrr_Int:
9559   case X86::VDIVSDZrr_Intk:
9560   case X86::VDIVSDZrr_Intkz:
9561   case X86::VDIVSDZrrb:
9562   case X86::VDIVSDZrrbk:
9563   case X86::VDIVSDZrrbkz:
9564   case X86::VDIVSSZrm:
9565   case X86::VDIVSSZrr:
9566   case X86::VDIVSSZrm_Int:
9567   case X86::VDIVSSZrm_Intk:
9568   case X86::VDIVSSZrm_Intkz:
9569   case X86::VDIVSSZrr_Int:
9570   case X86::VDIVSSZrr_Intk:
9571   case X86::VDIVSSZrr_Intkz:
9572   case X86::VDIVSSZrrb:
9573   case X86::VDIVSSZrrbk:
9574   case X86::VDIVSSZrrbkz:
9575   case X86::VSQRTPDZ128m:
9576   case X86::VSQRTPDZ128mb:
9577   case X86::VSQRTPDZ128mbk:
9578   case X86::VSQRTPDZ128mbkz:
9579   case X86::VSQRTPDZ128mk:
9580   case X86::VSQRTPDZ128mkz:
9581   case X86::VSQRTPDZ128r:
9582   case X86::VSQRTPDZ128rk:
9583   case X86::VSQRTPDZ128rkz:
9584   case X86::VSQRTPDZ256m:
9585   case X86::VSQRTPDZ256mb:
9586   case X86::VSQRTPDZ256mbk:
9587   case X86::VSQRTPDZ256mbkz:
9588   case X86::VSQRTPDZ256mk:
9589   case X86::VSQRTPDZ256mkz:
9590   case X86::VSQRTPDZ256r:
9591   case X86::VSQRTPDZ256rk:
9592   case X86::VSQRTPDZ256rkz:
9593   case X86::VSQRTPDZm:
9594   case X86::VSQRTPDZmb:
9595   case X86::VSQRTPDZmbk:
9596   case X86::VSQRTPDZmbkz:
9597   case X86::VSQRTPDZmk:
9598   case X86::VSQRTPDZmkz:
9599   case X86::VSQRTPDZr:
9600   case X86::VSQRTPDZrb:
9601   case X86::VSQRTPDZrbk:
9602   case X86::VSQRTPDZrbkz:
9603   case X86::VSQRTPDZrk:
9604   case X86::VSQRTPDZrkz:
9605   case X86::VSQRTPSZ128m:
9606   case X86::VSQRTPSZ128mb:
9607   case X86::VSQRTPSZ128mbk:
9608   case X86::VSQRTPSZ128mbkz:
9609   case X86::VSQRTPSZ128mk:
9610   case X86::VSQRTPSZ128mkz:
9611   case X86::VSQRTPSZ128r:
9612   case X86::VSQRTPSZ128rk:
9613   case X86::VSQRTPSZ128rkz:
9614   case X86::VSQRTPSZ256m:
9615   case X86::VSQRTPSZ256mb:
9616   case X86::VSQRTPSZ256mbk:
9617   case X86::VSQRTPSZ256mbkz:
9618   case X86::VSQRTPSZ256mk:
9619   case X86::VSQRTPSZ256mkz:
9620   case X86::VSQRTPSZ256r:
9621   case X86::VSQRTPSZ256rk:
9622   case X86::VSQRTPSZ256rkz:
9623   case X86::VSQRTPSZm:
9624   case X86::VSQRTPSZmb:
9625   case X86::VSQRTPSZmbk:
9626   case X86::VSQRTPSZmbkz:
9627   case X86::VSQRTPSZmk:
9628   case X86::VSQRTPSZmkz:
9629   case X86::VSQRTPSZr:
9630   case X86::VSQRTPSZrb:
9631   case X86::VSQRTPSZrbk:
9632   case X86::VSQRTPSZrbkz:
9633   case X86::VSQRTPSZrk:
9634   case X86::VSQRTPSZrkz:
9635   case X86::VSQRTSDZm:
9636   case X86::VSQRTSDZm_Int:
9637   case X86::VSQRTSDZm_Intk:
9638   case X86::VSQRTSDZm_Intkz:
9639   case X86::VSQRTSDZr:
9640   case X86::VSQRTSDZr_Int:
9641   case X86::VSQRTSDZr_Intk:
9642   case X86::VSQRTSDZr_Intkz:
9643   case X86::VSQRTSDZrb_Int:
9644   case X86::VSQRTSDZrb_Intk:
9645   case X86::VSQRTSDZrb_Intkz:
9646   case X86::VSQRTSSZm:
9647   case X86::VSQRTSSZm_Int:
9648   case X86::VSQRTSSZm_Intk:
9649   case X86::VSQRTSSZm_Intkz:
9650   case X86::VSQRTSSZr:
9651   case X86::VSQRTSSZr_Int:
9652   case X86::VSQRTSSZr_Intk:
9653   case X86::VSQRTSSZr_Intkz:
9654   case X86::VSQRTSSZrb_Int:
9655   case X86::VSQRTSSZrb_Intk:
9656   case X86::VSQRTSSZrb_Intkz:
9657 
9658   case X86::VGATHERDPDYrm:
9659   case X86::VGATHERDPDZ128rm:
9660   case X86::VGATHERDPDZ256rm:
9661   case X86::VGATHERDPDZrm:
9662   case X86::VGATHERDPDrm:
9663   case X86::VGATHERDPSYrm:
9664   case X86::VGATHERDPSZ128rm:
9665   case X86::VGATHERDPSZ256rm:
9666   case X86::VGATHERDPSZrm:
9667   case X86::VGATHERDPSrm:
9668   case X86::VGATHERPF0DPDm:
9669   case X86::VGATHERPF0DPSm:
9670   case X86::VGATHERPF0QPDm:
9671   case X86::VGATHERPF0QPSm:
9672   case X86::VGATHERPF1DPDm:
9673   case X86::VGATHERPF1DPSm:
9674   case X86::VGATHERPF1QPDm:
9675   case X86::VGATHERPF1QPSm:
9676   case X86::VGATHERQPDYrm:
9677   case X86::VGATHERQPDZ128rm:
9678   case X86::VGATHERQPDZ256rm:
9679   case X86::VGATHERQPDZrm:
9680   case X86::VGATHERQPDrm:
9681   case X86::VGATHERQPSYrm:
9682   case X86::VGATHERQPSZ128rm:
9683   case X86::VGATHERQPSZ256rm:
9684   case X86::VGATHERQPSZrm:
9685   case X86::VGATHERQPSrm:
9686   case X86::VPGATHERDDYrm:
9687   case X86::VPGATHERDDZ128rm:
9688   case X86::VPGATHERDDZ256rm:
9689   case X86::VPGATHERDDZrm:
9690   case X86::VPGATHERDDrm:
9691   case X86::VPGATHERDQYrm:
9692   case X86::VPGATHERDQZ128rm:
9693   case X86::VPGATHERDQZ256rm:
9694   case X86::VPGATHERDQZrm:
9695   case X86::VPGATHERDQrm:
9696   case X86::VPGATHERQDYrm:
9697   case X86::VPGATHERQDZ128rm:
9698   case X86::VPGATHERQDZ256rm:
9699   case X86::VPGATHERQDZrm:
9700   case X86::VPGATHERQDrm:
9701   case X86::VPGATHERQQYrm:
9702   case X86::VPGATHERQQZ128rm:
9703   case X86::VPGATHERQQZ256rm:
9704   case X86::VPGATHERQQZrm:
9705   case X86::VPGATHERQQrm:
9706   case X86::VSCATTERDPDZ128mr:
9707   case X86::VSCATTERDPDZ256mr:
9708   case X86::VSCATTERDPDZmr:
9709   case X86::VSCATTERDPSZ128mr:
9710   case X86::VSCATTERDPSZ256mr:
9711   case X86::VSCATTERDPSZmr:
9712   case X86::VSCATTERPF0DPDm:
9713   case X86::VSCATTERPF0DPSm:
9714   case X86::VSCATTERPF0QPDm:
9715   case X86::VSCATTERPF0QPSm:
9716   case X86::VSCATTERPF1DPDm:
9717   case X86::VSCATTERPF1DPSm:
9718   case X86::VSCATTERPF1QPDm:
9719   case X86::VSCATTERPF1QPSm:
9720   case X86::VSCATTERQPDZ128mr:
9721   case X86::VSCATTERQPDZ256mr:
9722   case X86::VSCATTERQPDZmr:
9723   case X86::VSCATTERQPSZ128mr:
9724   case X86::VSCATTERQPSZ256mr:
9725   case X86::VSCATTERQPSZmr:
9726   case X86::VPSCATTERDDZ128mr:
9727   case X86::VPSCATTERDDZ256mr:
9728   case X86::VPSCATTERDDZmr:
9729   case X86::VPSCATTERDQZ128mr:
9730   case X86::VPSCATTERDQZ256mr:
9731   case X86::VPSCATTERDQZmr:
9732   case X86::VPSCATTERQDZ128mr:
9733   case X86::VPSCATTERQDZ256mr:
9734   case X86::VPSCATTERQDZmr:
9735   case X86::VPSCATTERQQZ128mr:
9736   case X86::VPSCATTERQQZ256mr:
9737   case X86::VPSCATTERQQZmr:
9738     return true;
9739   }
9740 }
9741 
9742 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
9743                                          const MachineRegisterInfo *MRI,
9744                                          const MachineInstr &DefMI,
9745                                          unsigned DefIdx,
9746                                          const MachineInstr &UseMI,
9747                                          unsigned UseIdx) const {
9748   return isHighLatencyDef(DefMI.getOpcode());
9749 }
9750 
9751 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
9752                                            const MachineBasicBlock *MBB) const {
9753   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
9754          "Reassociation needs binary operators");
9755 
9756   // Integer binary math/logic instructions have a third source operand:
9757   // the EFLAGS register. That operand must be both defined here and never
9758   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
9759   // not change anything because rearranging the operands could affect other
9760   // instructions that depend on the exact status flags (zero, sign, etc.)
9761   // that are set by using these particular operands with this operation.
9762   if (Inst.getNumOperands() == 4) {
9763     assert(Inst.getOperand(3).isReg() &&
9764            Inst.getOperand(3).getReg() == X86::EFLAGS &&
9765            "Unexpected operand in reassociable instruction");
9766     if (!Inst.getOperand(3).isDead())
9767       return false;
9768   }
9769 
9770   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
9771 }
9772 
9773 // TODO: There are many more machine instruction opcodes to match:
9774 //       1. Other data types (integer, vectors)
9775 //       2. Other math / logic operations (xor, or)
9776 //       3. Other forms of the same operation (intrinsics and other variants)
9777 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
9778   switch (Inst.getOpcode()) {
9779   case X86::AND8rr:
9780   case X86::AND16rr:
9781   case X86::AND32rr:
9782   case X86::AND64rr:
9783   case X86::OR8rr:
9784   case X86::OR16rr:
9785   case X86::OR32rr:
9786   case X86::OR64rr:
9787   case X86::XOR8rr:
9788   case X86::XOR16rr:
9789   case X86::XOR32rr:
9790   case X86::XOR64rr:
9791   case X86::IMUL16rr:
9792   case X86::IMUL32rr:
9793   case X86::IMUL64rr:
9794   case X86::PANDrr:
9795   case X86::PORrr:
9796   case X86::PXORrr:
9797   case X86::ANDPDrr:
9798   case X86::ANDPSrr:
9799   case X86::ORPDrr:
9800   case X86::ORPSrr:
9801   case X86::XORPDrr:
9802   case X86::XORPSrr:
9803   case X86::PADDBrr:
9804   case X86::PADDWrr:
9805   case X86::PADDDrr:
9806   case X86::PADDQrr:
9807   case X86::VPANDrr:
9808   case X86::VPANDYrr:
9809   case X86::VPANDDZ128rr:
9810   case X86::VPANDDZ256rr:
9811   case X86::VPANDDZrr:
9812   case X86::VPANDQZ128rr:
9813   case X86::VPANDQZ256rr:
9814   case X86::VPANDQZrr:
9815   case X86::VPORrr:
9816   case X86::VPORYrr:
9817   case X86::VPORDZ128rr:
9818   case X86::VPORDZ256rr:
9819   case X86::VPORDZrr:
9820   case X86::VPORQZ128rr:
9821   case X86::VPORQZ256rr:
9822   case X86::VPORQZrr:
9823   case X86::VPXORrr:
9824   case X86::VPXORYrr:
9825   case X86::VPXORDZ128rr:
9826   case X86::VPXORDZ256rr:
9827   case X86::VPXORDZrr:
9828   case X86::VPXORQZ128rr:
9829   case X86::VPXORQZ256rr:
9830   case X86::VPXORQZrr:
9831   case X86::VANDPDrr:
9832   case X86::VANDPSrr:
9833   case X86::VANDPDYrr:
9834   case X86::VANDPSYrr:
9835   case X86::VANDPDZ128rr:
9836   case X86::VANDPSZ128rr:
9837   case X86::VANDPDZ256rr:
9838   case X86::VANDPSZ256rr:
9839   case X86::VANDPDZrr:
9840   case X86::VANDPSZrr:
9841   case X86::VORPDrr:
9842   case X86::VORPSrr:
9843   case X86::VORPDYrr:
9844   case X86::VORPSYrr:
9845   case X86::VORPDZ128rr:
9846   case X86::VORPSZ128rr:
9847   case X86::VORPDZ256rr:
9848   case X86::VORPSZ256rr:
9849   case X86::VORPDZrr:
9850   case X86::VORPSZrr:
9851   case X86::VXORPDrr:
9852   case X86::VXORPSrr:
9853   case X86::VXORPDYrr:
9854   case X86::VXORPSYrr:
9855   case X86::VXORPDZ128rr:
9856   case X86::VXORPSZ128rr:
9857   case X86::VXORPDZ256rr:
9858   case X86::VXORPSZ256rr:
9859   case X86::VXORPDZrr:
9860   case X86::VXORPSZrr:
9861   case X86::KADDBrr:
9862   case X86::KADDWrr:
9863   case X86::KADDDrr:
9864   case X86::KADDQrr:
9865   case X86::KANDBrr:
9866   case X86::KANDWrr:
9867   case X86::KANDDrr:
9868   case X86::KANDQrr:
9869   case X86::KORBrr:
9870   case X86::KORWrr:
9871   case X86::KORDrr:
9872   case X86::KORQrr:
9873   case X86::KXORBrr:
9874   case X86::KXORWrr:
9875   case X86::KXORDrr:
9876   case X86::KXORQrr:
9877   case X86::VPADDBrr:
9878   case X86::VPADDWrr:
9879   case X86::VPADDDrr:
9880   case X86::VPADDQrr:
9881   case X86::VPADDBYrr:
9882   case X86::VPADDWYrr:
9883   case X86::VPADDDYrr:
9884   case X86::VPADDQYrr:
9885   case X86::VPADDBZ128rr:
9886   case X86::VPADDWZ128rr:
9887   case X86::VPADDDZ128rr:
9888   case X86::VPADDQZ128rr:
9889   case X86::VPADDBZ256rr:
9890   case X86::VPADDWZ256rr:
9891   case X86::VPADDDZ256rr:
9892   case X86::VPADDQZ256rr:
9893   case X86::VPADDBZrr:
9894   case X86::VPADDWZrr:
9895   case X86::VPADDDZrr:
9896   case X86::VPADDQZrr:
9897   case X86::VPMULLWrr:
9898   case X86::VPMULLWYrr:
9899   case X86::VPMULLWZ128rr:
9900   case X86::VPMULLWZ256rr:
9901   case X86::VPMULLWZrr:
9902   case X86::VPMULLDrr:
9903   case X86::VPMULLDYrr:
9904   case X86::VPMULLDZ128rr:
9905   case X86::VPMULLDZ256rr:
9906   case X86::VPMULLDZrr:
9907   case X86::VPMULLQZ128rr:
9908   case X86::VPMULLQZ256rr:
9909   case X86::VPMULLQZrr:
9910   // Normal min/max instructions are not commutative because of NaN and signed
9911   // zero semantics, but these are. Thus, there's no need to check for global
9912   // relaxed math; the instructions themselves have the properties we need.
9913   case X86::MAXCPDrr:
9914   case X86::MAXCPSrr:
9915   case X86::MAXCSDrr:
9916   case X86::MAXCSSrr:
9917   case X86::MINCPDrr:
9918   case X86::MINCPSrr:
9919   case X86::MINCSDrr:
9920   case X86::MINCSSrr:
9921   case X86::VMAXCPDrr:
9922   case X86::VMAXCPSrr:
9923   case X86::VMAXCPDYrr:
9924   case X86::VMAXCPSYrr:
9925   case X86::VMAXCPDZ128rr:
9926   case X86::VMAXCPSZ128rr:
9927   case X86::VMAXCPDZ256rr:
9928   case X86::VMAXCPSZ256rr:
9929   case X86::VMAXCPDZrr:
9930   case X86::VMAXCPSZrr:
9931   case X86::VMAXCSDrr:
9932   case X86::VMAXCSSrr:
9933   case X86::VMAXCSDZrr:
9934   case X86::VMAXCSSZrr:
9935   case X86::VMINCPDrr:
9936   case X86::VMINCPSrr:
9937   case X86::VMINCPDYrr:
9938   case X86::VMINCPSYrr:
9939   case X86::VMINCPDZ128rr:
9940   case X86::VMINCPSZ128rr:
9941   case X86::VMINCPDZ256rr:
9942   case X86::VMINCPSZ256rr:
9943   case X86::VMINCPDZrr:
9944   case X86::VMINCPSZrr:
9945   case X86::VMINCSDrr:
9946   case X86::VMINCSSrr:
9947   case X86::VMINCSDZrr:
9948   case X86::VMINCSSZrr:
9949     return true;
9950   case X86::ADDPDrr:
9951   case X86::ADDPSrr:
9952   case X86::ADDSDrr:
9953   case X86::ADDSSrr:
9954   case X86::MULPDrr:
9955   case X86::MULPSrr:
9956   case X86::MULSDrr:
9957   case X86::MULSSrr:
9958   case X86::VADDPDrr:
9959   case X86::VADDPSrr:
9960   case X86::VADDPDYrr:
9961   case X86::VADDPSYrr:
9962   case X86::VADDPDZ128rr:
9963   case X86::VADDPSZ128rr:
9964   case X86::VADDPDZ256rr:
9965   case X86::VADDPSZ256rr:
9966   case X86::VADDPDZrr:
9967   case X86::VADDPSZrr:
9968   case X86::VADDSDrr:
9969   case X86::VADDSSrr:
9970   case X86::VADDSDZrr:
9971   case X86::VADDSSZrr:
9972   case X86::VMULPDrr:
9973   case X86::VMULPSrr:
9974   case X86::VMULPDYrr:
9975   case X86::VMULPSYrr:
9976   case X86::VMULPDZ128rr:
9977   case X86::VMULPSZ128rr:
9978   case X86::VMULPDZ256rr:
9979   case X86::VMULPSZ256rr:
9980   case X86::VMULPDZrr:
9981   case X86::VMULPSZrr:
9982   case X86::VMULSDrr:
9983   case X86::VMULSSrr:
9984   case X86::VMULSDZrr:
9985   case X86::VMULSSZrr:
9986     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
9987   default:
9988     return false;
9989   }
9990 }
9991 
9992 /// This is an architecture-specific helper function of reassociateOps.
9993 /// Set special operand attributes for new instructions after reassociation.
9994 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
9995                                          MachineInstr &OldMI2,
9996                                          MachineInstr &NewMI1,
9997                                          MachineInstr &NewMI2) const {
9998   // Integer instructions define an implicit EFLAGS source register operand as
9999   // the third source (fourth total) operand.
10000   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
10001     return;
10002 
10003   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
10004          "Unexpected instruction type for reassociation");
10005 
10006   MachineOperand &OldOp1 = OldMI1.getOperand(3);
10007   MachineOperand &OldOp2 = OldMI2.getOperand(3);
10008   MachineOperand &NewOp1 = NewMI1.getOperand(3);
10009   MachineOperand &NewOp2 = NewMI2.getOperand(3);
10010 
10011   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
10012          "Must have dead EFLAGS operand in reassociable instruction");
10013   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
10014          "Must have dead EFLAGS operand in reassociable instruction");
10015 
10016   (void)OldOp1;
10017   (void)OldOp2;
10018 
10019   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
10020          "Unexpected operand in reassociable instruction");
10021   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
10022          "Unexpected operand in reassociable instruction");
10023 
10024   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
10025   // of this pass or other passes. The EFLAGS operands must be dead in these new
10026   // instructions because the EFLAGS operands in the original instructions must
10027   // be dead in order for reassociation to occur.
10028   NewOp1.setIsDead();
10029   NewOp2.setIsDead();
10030 }
10031 
10032 std::pair<unsigned, unsigned>
10033 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
10034   return std::make_pair(TF, 0u);
10035 }
10036 
10037 ArrayRef<std::pair<unsigned, const char *>>
10038 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
10039   using namespace X86II;
10040   static const std::pair<unsigned, const char *> TargetFlags[] = {
10041       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
10042       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
10043       {MO_GOT, "x86-got"},
10044       {MO_GOTOFF, "x86-gotoff"},
10045       {MO_GOTPCREL, "x86-gotpcrel"},
10046       {MO_PLT, "x86-plt"},
10047       {MO_TLSGD, "x86-tlsgd"},
10048       {MO_TLSLD, "x86-tlsld"},
10049       {MO_TLSLDM, "x86-tlsldm"},
10050       {MO_GOTTPOFF, "x86-gottpoff"},
10051       {MO_INDNTPOFF, "x86-indntpoff"},
10052       {MO_TPOFF, "x86-tpoff"},
10053       {MO_DTPOFF, "x86-dtpoff"},
10054       {MO_NTPOFF, "x86-ntpoff"},
10055       {MO_GOTNTPOFF, "x86-gotntpoff"},
10056       {MO_DLLIMPORT, "x86-dllimport"},
10057       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
10058       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
10059       {MO_TLVP, "x86-tlvp"},
10060       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
10061       {MO_SECREL, "x86-secrel"}};
10062   return makeArrayRef(TargetFlags);
10063 }
10064 
10065 bool X86InstrInfo::isTailCall(const MachineInstr &Inst) const {
10066   switch (Inst.getOpcode()) {
10067     case X86::TCRETURNdi:
10068     case X86::TCRETURNmi:
10069     case X86::TCRETURNri:
10070     case X86::TCRETURNdi64:
10071     case X86::TCRETURNmi64:
10072     case X86::TCRETURNri64:
10073     case X86::TAILJMPd:
10074     case X86::TAILJMPm:
10075     case X86::TAILJMPr:
10076     case X86::TAILJMPd64:
10077     case X86::TAILJMPm64:
10078     case X86::TAILJMPr64:
10079     case X86::TAILJMPm64_REX:
10080     case X86::TAILJMPr64_REX:
10081       return true;
10082     default:
10083       return false;
10084   }
10085 }
10086 
10087 namespace {
10088   /// Create Global Base Reg pass. This initializes the PIC
10089   /// global base register for x86-32.
10090   struct CGBR : public MachineFunctionPass {
10091     static char ID;
10092     CGBR() : MachineFunctionPass(ID) {}
10093 
10094     bool runOnMachineFunction(MachineFunction &MF) override {
10095       const X86TargetMachine *TM =
10096         static_cast<const X86TargetMachine *>(&MF.getTarget());
10097       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
10098 
10099       // Don't do anything if this is 64-bit as 64-bit PIC
10100       // uses RIP relative addressing.
10101       if (STI.is64Bit())
10102         return false;
10103 
10104       // Only emit a global base reg in PIC mode.
10105       if (!TM->isPositionIndependent())
10106         return false;
10107 
10108       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
10109       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
10110 
10111       // If we didn't need a GlobalBaseReg, don't insert code.
10112       if (GlobalBaseReg == 0)
10113         return false;
10114 
10115       // Insert the set of GlobalBaseReg into the first MBB of the function
10116       MachineBasicBlock &FirstMBB = MF.front();
10117       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
10118       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
10119       MachineRegisterInfo &RegInfo = MF.getRegInfo();
10120       const X86InstrInfo *TII = STI.getInstrInfo();
10121 
10122       unsigned PC;
10123       if (STI.isPICStyleGOT())
10124         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
10125       else
10126         PC = GlobalBaseReg;
10127 
10128       // Operand of MovePCtoStack is completely ignored by asm printer. It's
10129       // only used in JIT code emission as displacement to pc.
10130       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
10131 
10132       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
10133       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
10134       if (STI.isPICStyleGOT()) {
10135         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
10136         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
10137           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
10138                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
10139       }
10140 
10141       return true;
10142     }
10143 
10144     StringRef getPassName() const override {
10145       return "X86 PIC Global Base Reg Initialization";
10146     }
10147 
10148     void getAnalysisUsage(AnalysisUsage &AU) const override {
10149       AU.setPreservesCFG();
10150       MachineFunctionPass::getAnalysisUsage(AU);
10151     }
10152   };
10153 }
10154 
10155 char CGBR::ID = 0;
10156 FunctionPass*
10157 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
10158 
10159 namespace {
10160   struct LDTLSCleanup : public MachineFunctionPass {
10161     static char ID;
10162     LDTLSCleanup() : MachineFunctionPass(ID) {}
10163 
10164     bool runOnMachineFunction(MachineFunction &MF) override {
10165       if (skipFunction(*MF.getFunction()))
10166         return false;
10167 
10168       X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
10169       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
10170         // No point folding accesses if there isn't at least two.
10171         return false;
10172       }
10173 
10174       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
10175       return VisitNode(DT->getRootNode(), 0);
10176     }
10177 
10178     // Visit the dominator subtree rooted at Node in pre-order.
10179     // If TLSBaseAddrReg is non-null, then use that to replace any
10180     // TLS_base_addr instructions. Otherwise, create the register
10181     // when the first such instruction is seen, and then use it
10182     // as we encounter more instructions.
10183     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
10184       MachineBasicBlock *BB = Node->getBlock();
10185       bool Changed = false;
10186 
10187       // Traverse the current block.
10188       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
10189            ++I) {
10190         switch (I->getOpcode()) {
10191           case X86::TLS_base_addr32:
10192           case X86::TLS_base_addr64:
10193             if (TLSBaseAddrReg)
10194               I = ReplaceTLSBaseAddrCall(*I, TLSBaseAddrReg);
10195             else
10196               I = SetRegister(*I, &TLSBaseAddrReg);
10197             Changed = true;
10198             break;
10199           default:
10200             break;
10201         }
10202       }
10203 
10204       // Visit the children of this block in the dominator tree.
10205       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
10206            I != E; ++I) {
10207         Changed |= VisitNode(*I, TLSBaseAddrReg);
10208       }
10209 
10210       return Changed;
10211     }
10212 
10213     // Replace the TLS_base_addr instruction I with a copy from
10214     // TLSBaseAddrReg, returning the new instruction.
10215     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr &I,
10216                                          unsigned TLSBaseAddrReg) {
10217       MachineFunction *MF = I.getParent()->getParent();
10218       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
10219       const bool is64Bit = STI.is64Bit();
10220       const X86InstrInfo *TII = STI.getInstrInfo();
10221 
10222       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
10223       MachineInstr *Copy =
10224           BuildMI(*I.getParent(), I, I.getDebugLoc(),
10225                   TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
10226               .addReg(TLSBaseAddrReg);
10227 
10228       // Erase the TLS_base_addr instruction.
10229       I.eraseFromParent();
10230 
10231       return Copy;
10232     }
10233 
10234     // Create a virtal register in *TLSBaseAddrReg, and populate it by
10235     // inserting a copy instruction after I. Returns the new instruction.
10236     MachineInstr *SetRegister(MachineInstr &I, unsigned *TLSBaseAddrReg) {
10237       MachineFunction *MF = I.getParent()->getParent();
10238       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
10239       const bool is64Bit = STI.is64Bit();
10240       const X86InstrInfo *TII = STI.getInstrInfo();
10241 
10242       // Create a virtual register for the TLS base address.
10243       MachineRegisterInfo &RegInfo = MF->getRegInfo();
10244       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
10245                                                       ? &X86::GR64RegClass
10246                                                       : &X86::GR32RegClass);
10247 
10248       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
10249       MachineInstr *Next = I.getNextNode();
10250       MachineInstr *Copy =
10251           BuildMI(*I.getParent(), Next, I.getDebugLoc(),
10252                   TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
10253               .addReg(is64Bit ? X86::RAX : X86::EAX);
10254 
10255       return Copy;
10256     }
10257 
10258     StringRef getPassName() const override {
10259       return "Local Dynamic TLS Access Clean-up";
10260     }
10261 
10262     void getAnalysisUsage(AnalysisUsage &AU) const override {
10263       AU.setPreservesCFG();
10264       AU.addRequired<MachineDominatorTree>();
10265       MachineFunctionPass::getAnalysisUsage(AU);
10266     }
10267   };
10268 }
10269 
10270 char LDTLSCleanup::ID = 0;
10271 FunctionPass*
10272 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
10273