1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/StackMaps.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include <limits>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "x86-instr-info"
44 
45 #define GET_INSTRINFO_CTOR_DTOR
46 #include "X86GenInstrInfo.inc"
47 
48 static cl::opt<bool>
49 NoFusing("disable-spill-fusing",
50          cl::desc("Disable fusing of spill code into instructions"));
51 static cl::opt<bool>
52 PrintFailedFusing("print-failed-fuse-candidates",
53                   cl::desc("Print instructions that the allocator wants to"
54                            " fuse, but the X86 backend currently can't"),
55                   cl::Hidden);
56 static cl::opt<bool>
57 ReMatPICStubLoad("remat-pic-stub-load",
58                  cl::desc("Re-materialize load from stub in PIC mode"),
59                  cl::init(false), cl::Hidden);
60 
61 enum {
62   // Select which memory operand is being unfolded.
63   // (stored in bits 0 - 3)
64   TB_INDEX_0    = 0,
65   TB_INDEX_1    = 1,
66   TB_INDEX_2    = 2,
67   TB_INDEX_3    = 3,
68   TB_INDEX_4    = 4,
69   TB_INDEX_MASK = 0xf,
70 
71   // Do not insert the reverse map (MemOp -> RegOp) into the table.
72   // This may be needed because there is a many -> one mapping.
73   TB_NO_REVERSE   = 1 << 4,
74 
75   // Do not insert the forward map (RegOp -> MemOp) into the table.
76   // This is needed for Native Client, which prohibits branch
77   // instructions from using a memory operand.
78   TB_NO_FORWARD   = 1 << 5,
79 
80   TB_FOLDED_LOAD  = 1 << 6,
81   TB_FOLDED_STORE = 1 << 7,
82 
83   // Minimum alignment required for load/store.
84   // Used for RegOp->MemOp conversion.
85   // (stored in bits 8 - 15)
86   TB_ALIGN_SHIFT = 8,
87   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
88   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
89   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
90   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
91   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
92 };
93 
94 struct X86MemoryFoldTableEntry {
95   uint16_t RegOp;
96   uint16_t MemOp;
97   uint16_t Flags;
98 };
99 
100 // Pin the vtable to this file.
101 void X86InstrInfo::anchor() {}
102 
103 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104     : X86GenInstrInfo(
105           (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106           (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
107       Subtarget(STI), RI(STI) {
108 
109   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
110     { X86::ADC32ri,     X86::ADC32mi,    0 },
111     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
112     { X86::ADC32rr,     X86::ADC32mr,    0 },
113     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
114     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
115     { X86::ADC64rr,     X86::ADC64mr,    0 },
116     { X86::ADD16ri,     X86::ADD16mi,    0 },
117     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
118     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
119     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
120     { X86::ADD16rr,     X86::ADD16mr,    0 },
121     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
122     { X86::ADD32ri,     X86::ADD32mi,    0 },
123     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
124     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
125     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
126     { X86::ADD32rr,     X86::ADD32mr,    0 },
127     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
128     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
129     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
130     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
131     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
132     { X86::ADD64rr,     X86::ADD64mr,    0 },
133     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
134     { X86::ADD8ri,      X86::ADD8mi,     0 },
135     { X86::ADD8rr,      X86::ADD8mr,     0 },
136     { X86::AND16ri,     X86::AND16mi,    0 },
137     { X86::AND16ri8,    X86::AND16mi8,   0 },
138     { X86::AND16rr,     X86::AND16mr,    0 },
139     { X86::AND32ri,     X86::AND32mi,    0 },
140     { X86::AND32ri8,    X86::AND32mi8,   0 },
141     { X86::AND32rr,     X86::AND32mr,    0 },
142     { X86::AND64ri32,   X86::AND64mi32,  0 },
143     { X86::AND64ri8,    X86::AND64mi8,   0 },
144     { X86::AND64rr,     X86::AND64mr,    0 },
145     { X86::AND8ri,      X86::AND8mi,     0 },
146     { X86::AND8rr,      X86::AND8mr,     0 },
147     { X86::DEC16r,      X86::DEC16m,     0 },
148     { X86::DEC32r,      X86::DEC32m,     0 },
149     { X86::DEC64r,      X86::DEC64m,     0 },
150     { X86::DEC8r,       X86::DEC8m,      0 },
151     { X86::INC16r,      X86::INC16m,     0 },
152     { X86::INC32r,      X86::INC32m,     0 },
153     { X86::INC64r,      X86::INC64m,     0 },
154     { X86::INC8r,       X86::INC8m,      0 },
155     { X86::NEG16r,      X86::NEG16m,     0 },
156     { X86::NEG32r,      X86::NEG32m,     0 },
157     { X86::NEG64r,      X86::NEG64m,     0 },
158     { X86::NEG8r,       X86::NEG8m,      0 },
159     { X86::NOT16r,      X86::NOT16m,     0 },
160     { X86::NOT32r,      X86::NOT32m,     0 },
161     { X86::NOT64r,      X86::NOT64m,     0 },
162     { X86::NOT8r,       X86::NOT8m,      0 },
163     { X86::OR16ri,      X86::OR16mi,     0 },
164     { X86::OR16ri8,     X86::OR16mi8,    0 },
165     { X86::OR16rr,      X86::OR16mr,     0 },
166     { X86::OR32ri,      X86::OR32mi,     0 },
167     { X86::OR32ri8,     X86::OR32mi8,    0 },
168     { X86::OR32rr,      X86::OR32mr,     0 },
169     { X86::OR64ri32,    X86::OR64mi32,   0 },
170     { X86::OR64ri8,     X86::OR64mi8,    0 },
171     { X86::OR64rr,      X86::OR64mr,     0 },
172     { X86::OR8ri,       X86::OR8mi,      0 },
173     { X86::OR8rr,       X86::OR8mr,      0 },
174     { X86::ROL16r1,     X86::ROL16m1,    0 },
175     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
176     { X86::ROL16ri,     X86::ROL16mi,    0 },
177     { X86::ROL32r1,     X86::ROL32m1,    0 },
178     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
179     { X86::ROL32ri,     X86::ROL32mi,    0 },
180     { X86::ROL64r1,     X86::ROL64m1,    0 },
181     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
182     { X86::ROL64ri,     X86::ROL64mi,    0 },
183     { X86::ROL8r1,      X86::ROL8m1,     0 },
184     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
185     { X86::ROL8ri,      X86::ROL8mi,     0 },
186     { X86::ROR16r1,     X86::ROR16m1,    0 },
187     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
188     { X86::ROR16ri,     X86::ROR16mi,    0 },
189     { X86::ROR32r1,     X86::ROR32m1,    0 },
190     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
191     { X86::ROR32ri,     X86::ROR32mi,    0 },
192     { X86::ROR64r1,     X86::ROR64m1,    0 },
193     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
194     { X86::ROR64ri,     X86::ROR64mi,    0 },
195     { X86::ROR8r1,      X86::ROR8m1,     0 },
196     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
197     { X86::ROR8ri,      X86::ROR8mi,     0 },
198     { X86::SAR16r1,     X86::SAR16m1,    0 },
199     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
200     { X86::SAR16ri,     X86::SAR16mi,    0 },
201     { X86::SAR32r1,     X86::SAR32m1,    0 },
202     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
203     { X86::SAR32ri,     X86::SAR32mi,    0 },
204     { X86::SAR64r1,     X86::SAR64m1,    0 },
205     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
206     { X86::SAR64ri,     X86::SAR64mi,    0 },
207     { X86::SAR8r1,      X86::SAR8m1,     0 },
208     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
209     { X86::SAR8ri,      X86::SAR8mi,     0 },
210     { X86::SBB32ri,     X86::SBB32mi,    0 },
211     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
212     { X86::SBB32rr,     X86::SBB32mr,    0 },
213     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
214     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
215     { X86::SBB64rr,     X86::SBB64mr,    0 },
216     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
217     { X86::SHL16ri,     X86::SHL16mi,    0 },
218     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
219     { X86::SHL32ri,     X86::SHL32mi,    0 },
220     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
221     { X86::SHL64ri,     X86::SHL64mi,    0 },
222     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
223     { X86::SHL8ri,      X86::SHL8mi,     0 },
224     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
225     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
226     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
227     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
228     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
229     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
230     { X86::SHR16r1,     X86::SHR16m1,    0 },
231     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
232     { X86::SHR16ri,     X86::SHR16mi,    0 },
233     { X86::SHR32r1,     X86::SHR32m1,    0 },
234     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
235     { X86::SHR32ri,     X86::SHR32mi,    0 },
236     { X86::SHR64r1,     X86::SHR64m1,    0 },
237     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
238     { X86::SHR64ri,     X86::SHR64mi,    0 },
239     { X86::SHR8r1,      X86::SHR8m1,     0 },
240     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
241     { X86::SHR8ri,      X86::SHR8mi,     0 },
242     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
243     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
244     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
245     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
246     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
247     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
248     { X86::SUB16ri,     X86::SUB16mi,    0 },
249     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
250     { X86::SUB16rr,     X86::SUB16mr,    0 },
251     { X86::SUB32ri,     X86::SUB32mi,    0 },
252     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
253     { X86::SUB32rr,     X86::SUB32mr,    0 },
254     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
255     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
256     { X86::SUB64rr,     X86::SUB64mr,    0 },
257     { X86::SUB8ri,      X86::SUB8mi,     0 },
258     { X86::SUB8rr,      X86::SUB8mr,     0 },
259     { X86::XOR16ri,     X86::XOR16mi,    0 },
260     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
261     { X86::XOR16rr,     X86::XOR16mr,    0 },
262     { X86::XOR32ri,     X86::XOR32mi,    0 },
263     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
264     { X86::XOR32rr,     X86::XOR32mr,    0 },
265     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
266     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
267     { X86::XOR64rr,     X86::XOR64mr,    0 },
268     { X86::XOR8ri,      X86::XOR8mi,     0 },
269     { X86::XOR8rr,      X86::XOR8mr,     0 }
270   };
271 
272   for (unsigned i = 0, e = array_lengthof(MemoryFoldTable2Addr); i != e; ++i) {
273     unsigned RegOp = MemoryFoldTable2Addr[i].RegOp;
274     unsigned MemOp = MemoryFoldTable2Addr[i].MemOp;
275     unsigned Flags = MemoryFoldTable2Addr[i].Flags;
276     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
277                   RegOp, MemOp,
278                   // Index 0, folded load and store, no alignment requirement.
279                   Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
280   }
281 
282   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
283     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
284     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
285     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
286     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
287     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
288     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
289     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
290     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
291     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
292     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
293     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
294     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
295     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
296     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
297     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
298     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
299     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
300     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
301     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
302     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
303     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
304     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
305     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
306     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
307     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
308     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
309     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
310     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
311     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
312     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
313     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
314     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
315     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
316     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
317     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
318     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
319     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
320     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
321     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
322     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
326     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
327     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
328     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
329     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
330     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
331     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
332     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
333     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
334     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
335     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
336     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
337     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
338     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
339     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
340     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
341     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
342     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
343     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
344     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
345     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
346     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
347     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
348     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
349     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
350     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
351     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
352     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
353     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
354     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
355     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
356     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
357     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
358     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
359     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
360     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
361 
362     // AVX 128-bit versions of foldable instructions
363     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
364     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
365     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
366     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
367     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
368     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
369     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
370     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
371     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
372     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
373     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
374     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
375     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
376 
377     // AVX 256-bit foldable instructions
378     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
379     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
380     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
381     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
382     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
383     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
384 
385     // AVX-512 foldable instructions
386     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
387     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
388     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
389     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
390     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
391     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
392     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
393     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
394     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
395     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
396     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
397 
398     // AVX-512 foldable instructions (256-bit versions)
399     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
400     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
401     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
402     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
403     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
404     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
405     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
406     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
407     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
408     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
409 
410     // AVX-512 foldable instructions (128-bit versions)
411     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
412     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
413     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
414     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
415     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
416     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
417     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
418     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
419     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
420     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
421 
422     // F16C foldable instructions
423     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
424     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
425   };
426 
427   for (unsigned i = 0, e = array_lengthof(MemoryFoldTable0); i != e; ++i) {
428     unsigned RegOp      = MemoryFoldTable0[i].RegOp;
429     unsigned MemOp      = MemoryFoldTable0[i].MemOp;
430     unsigned Flags      = MemoryFoldTable0[i].Flags;
431     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
432                   RegOp, MemOp, TB_INDEX_0 | Flags);
433   }
434 
435   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
436     { X86::CMP16rr,         X86::CMP16rm,             0 },
437     { X86::CMP32rr,         X86::CMP32rm,             0 },
438     { X86::CMP64rr,         X86::CMP64rm,             0 },
439     { X86::CMP8rr,          X86::CMP8rm,              0 },
440     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
441     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
442     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
443     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
444     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
445     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
446     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
447     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
448     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
449     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
450     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
451     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
452     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
453     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
454     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
455     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
456     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
457     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
458     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
459     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
460     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
461     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
462     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
463     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
464     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
465     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
466     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
467     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
468     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
469     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
470     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
471     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
472     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
473     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
474     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
475     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
476     { X86::MOV16rr,         X86::MOV16rm,             0 },
477     { X86::MOV32rr,         X86::MOV32rm,             0 },
478     { X86::MOV64rr,         X86::MOV64rm,             0 },
479     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
480     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
481     { X86::MOV8rr,          X86::MOV8rm,              0 },
482     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
483     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
484     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
485     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
486     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
487     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
488     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
489     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
490     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
491     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
492     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
493     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
494     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
495     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
496     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
497     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
498     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
499     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
500     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
501     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
502     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
503     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
504     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
505     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
506     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
507     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
508     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
509     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
510     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
511     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
512     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
513     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
514     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
515     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
516     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
517     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
518     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
519     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
520     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
521     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
522     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
523     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
524     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
525     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
526     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
527     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
528     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
529     { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
530     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
531     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
532     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
533     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
534     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
535     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
536     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
537     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
538     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
539     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
540     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
541     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
542     { X86::TEST16rr,        X86::TEST16rm,            0 },
543     { X86::TEST32rr,        X86::TEST32rm,            0 },
544     { X86::TEST64rr,        X86::TEST64rm,            0 },
545     { X86::TEST8rr,         X86::TEST8rm,             0 },
546     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
547     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
548     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
549 
550     // AVX 128-bit versions of foldable instructions
551     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
552     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
553     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
554     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
555     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
556     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
557     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
558     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
559     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
560     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
561     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
562     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
563     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
564     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
565     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
566     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
567     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
568     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
569     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
570     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
571     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
572     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
573     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
574     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
575     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
576     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
577     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
578     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
579     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
580     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
581     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
582     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
583     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
584     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
585     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
586     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
587     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
588     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
589     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
590     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
591     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
592     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
593     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
594     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
595     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
596     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
597     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
598     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
599     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
600     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
601     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
602     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
603     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
604     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
605     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
606     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
607     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
608     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
609     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
610     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
611     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
612     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
613     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
614     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
615     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
616     { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
617     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
618     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
619     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
620     { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
621     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
622     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
623     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
624     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
625     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
626     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
627 
628     // AVX 256-bit foldable instructions
629     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
630     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
631     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
632     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
633     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
634     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
635     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
636     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
637     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
638     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
639     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
640     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
641     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
642     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
643     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
644     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
645     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
646     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
647     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
648     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
649     { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
650     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
651     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
652     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
653     { X86::VRSQRTPSYr_Int,  X86::VRSQRTPSYm_Int,      0 },
654     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
655     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
656     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
657     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
658 
659     // AVX2 foldable instructions
660 
661     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
662     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
663     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
664     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
665     // so they don't need an equivalent limitation.
666     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
667     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
668     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
669     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
670     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
671     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
672     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      0 },
673     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     0 },
674     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      0 },
675     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     0 },
676     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      0 },
677     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     0 },
678     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      0 },
679     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     0 },
680     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
681     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
682     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        0 },
683     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        0 },
684     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
685     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
686     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
687     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        0 },
688     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        0 },
689     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        0 },
690     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
691     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
692     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
693     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        0 },
694     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
695     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
696     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
697 
698     // XOP foldable instructions
699     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
700     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
701     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
702     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
703     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
704     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
705     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
706     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
707     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
708     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
709     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
710     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
711     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
712     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
713     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
714     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
715     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
716     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
717     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
718     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
719     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
720     { X86::VPROTBri,           X86::VPROTBmi,         0 },
721     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
722     { X86::VPROTDri,           X86::VPROTDmi,         0 },
723     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
724     { X86::VPROTQri,           X86::VPROTQmi,         0 },
725     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
726     { X86::VPROTWri,           X86::VPROTWmi,         0 },
727     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
728     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
729     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
730     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
731     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
732     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
733     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
734     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
735     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
736 
737     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
738     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
739     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
740     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
741     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
742     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
743     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
744     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
745     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
746     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
747     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
748     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
749     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
750     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
751     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
752     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
753     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
754     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
755     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
756     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
757     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
758     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
759     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
760     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
761     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
762     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
763     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
764     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
765     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
766     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
767     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
768     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
769     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
770     { X86::RORX32ri,        X86::RORX32mi,            0 },
771     { X86::RORX64ri,        X86::RORX64mi,            0 },
772     { X86::SARX32rr,        X86::SARX32rm,            0 },
773     { X86::SARX64rr,        X86::SARX64rm,            0 },
774     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
775     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
776     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
777     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
778     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
779     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
780     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
781     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
782     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
783     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
784     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
785 
786     // AVX-512 foldable instructions
787     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
788     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
789     { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
790     { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
791     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
792     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
793     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zrm,         0 },
794     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zrm,        0 },
795     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
796     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
797     { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
798     { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
799     { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
800     { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
801     { X86::VBROADCASTSSZr,  X86::VBROADCASTSSZm,      TB_NO_REVERSE },
802     { X86::VBROADCASTSDZr,  X86::VBROADCASTSDZm,      TB_NO_REVERSE },
803 
804     // AVX-512 foldable instructions (256-bit versions)
805     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256rm,          TB_ALIGN_32 },
806     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256rm,          TB_ALIGN_32 },
807     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256rm,        TB_ALIGN_32 },
808     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256rm,        TB_ALIGN_32 },
809     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256rm,         0 },
810     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256rm,        0 },
811     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256rm,        0 },
812     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256rm,        0 },
813     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256rm,          0 },
814     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256rm,          0 },
815     { X86::VBROADCASTSSZ256r,  X86::VBROADCASTSSZ256m,      TB_NO_REVERSE },
816     { X86::VBROADCASTSDZ256r,  X86::VBROADCASTSDZ256m,      TB_NO_REVERSE },
817 
818     // AVX-512 foldable instructions (256-bit versions)
819     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128rm,          TB_ALIGN_16 },
820     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128rm,          TB_ALIGN_16 },
821     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128rm,        TB_ALIGN_16 },
822     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128rm,        TB_ALIGN_16 },
823     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128rm,         0 },
824     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128rm,        0 },
825     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128rm,        0 },
826     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128rm,        0 },
827     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128rm,          0 },
828     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128rm,          0 },
829     { X86::VBROADCASTSSZ128r,  X86::VBROADCASTSSZ128m,      TB_NO_REVERSE },
830 
831     // F16C foldable instructions
832     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
833     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
834 
835     // AES foldable instructions
836     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
837     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
838     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
839     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
840   };
841 
842   for (unsigned i = 0, e = array_lengthof(MemoryFoldTable1); i != e; ++i) {
843     unsigned RegOp = MemoryFoldTable1[i].RegOp;
844     unsigned MemOp = MemoryFoldTable1[i].MemOp;
845     unsigned Flags = MemoryFoldTable1[i].Flags;
846     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
847                   RegOp, MemOp,
848                   // Index 1, folded load
849                   Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
850   }
851 
852   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
853     { X86::ADC32rr,         X86::ADC32rm,       0 },
854     { X86::ADC64rr,         X86::ADC64rm,       0 },
855     { X86::ADD16rr,         X86::ADD16rm,       0 },
856     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
857     { X86::ADD32rr,         X86::ADD32rm,       0 },
858     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
859     { X86::ADD64rr,         X86::ADD64rm,       0 },
860     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
861     { X86::ADD8rr,          X86::ADD8rm,        0 },
862     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
863     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
864     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
865     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
866     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
867     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
868     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
869     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
870     { X86::AND16rr,         X86::AND16rm,       0 },
871     { X86::AND32rr,         X86::AND32rm,       0 },
872     { X86::AND64rr,         X86::AND64rm,       0 },
873     { X86::AND8rr,          X86::AND8rm,        0 },
874     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
875     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
876     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
877     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
878     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
879     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
880     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
881     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
882     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
883     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
884     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
885     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
886     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
887     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
888     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
889     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
890     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
891     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
892     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
893     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
894     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
895     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
896     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
897     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
898     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
899     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
900     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
901     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
902     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
903     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
904     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
905     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
906     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
907     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
908     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
909     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
910     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
911     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
912     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
913     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
914     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
915     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
916     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
917     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
918     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
919     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
920     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
921     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
922     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
923     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
924     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
925     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
926     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
927     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
928     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
929     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
930     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
931     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
932     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
933     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
934     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
935     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
936     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
937     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
938     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
939     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
940     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
941     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
942 
943     // FIXME: We should not be folding Fs* scalar loads into vector
944     // instructions because the vector instructions require vector-sized
945     // loads. Lowering should create vector-sized instructions (the Fv*
946     // variants below) to allow load folding.
947     { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
948     { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
949     { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
950     { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
951     { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
952     { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
953     { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
954     { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
955 
956     { X86::FvANDNPDrr,      X86::FvANDNPDrm,    TB_ALIGN_16 },
957     { X86::FvANDNPSrr,      X86::FvANDNPSrm,    TB_ALIGN_16 },
958     { X86::FvANDPDrr,       X86::FvANDPDrm,     TB_ALIGN_16 },
959     { X86::FvANDPSrr,       X86::FvANDPSrm,     TB_ALIGN_16 },
960     { X86::FvORPDrr,        X86::FvORPDrm,      TB_ALIGN_16 },
961     { X86::FvORPSrr,        X86::FvORPSrm,      TB_ALIGN_16 },
962     { X86::FvXORPDrr,       X86::FvXORPDrm,     TB_ALIGN_16 },
963     { X86::FvXORPSrr,       X86::FvXORPSrm,     TB_ALIGN_16 },
964     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
965     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
966     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
967     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
968     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
969     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
970     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
971     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
972     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
973     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
974     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
975     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
976     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
977     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
978     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
979     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
980     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
981     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
982     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
983     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
984     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
985     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
986     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
987     { X86::MINSDrr,         X86::MINSDrm,       0 },
988     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
989     { X86::MINSSrr,         X86::MINSSrm,       0 },
990     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
991     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
992     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
993     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
994     { X86::MULSDrr,         X86::MULSDrm,       0 },
995     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
996     { X86::MULSSrr,         X86::MULSSrm,       0 },
997     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
998     { X86::OR16rr,          X86::OR16rm,        0 },
999     { X86::OR32rr,          X86::OR32rm,        0 },
1000     { X86::OR64rr,          X86::OR64rm,        0 },
1001     { X86::OR8rr,           X86::OR8rm,         0 },
1002     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
1003     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
1004     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
1005     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
1006     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
1007     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
1008     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
1009     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
1010     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
1011     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
1012     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
1013     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
1014     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
1015     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
1016     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
1017     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
1018     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
1019     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
1020     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
1021     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
1022     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
1023     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
1024     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
1025     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
1026     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
1027     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
1028     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
1029     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
1030     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
1031     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
1032     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
1033     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
1034     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
1035     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
1036     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
1037     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
1038     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
1039     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
1040     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
1041     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
1042     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
1043     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
1044     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
1045     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
1046     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
1047     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
1048     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
1049     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
1050     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
1051     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
1052     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
1053     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
1054     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
1055     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
1056     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
1057     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
1058     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
1059     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
1060     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
1061     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
1062     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
1063     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
1064     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
1065     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
1066     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
1067     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
1068     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
1069     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
1070     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
1071     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
1072     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
1073     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
1074     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
1075     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
1076     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
1077     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
1078     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
1079     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
1080     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
1081     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
1082     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
1083     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
1084     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
1085     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
1086     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
1087     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
1088     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
1089     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
1090     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
1091     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
1092     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
1093     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
1094     { X86::SBB32rr,         X86::SBB32rm,       0 },
1095     { X86::SBB64rr,         X86::SBB64rm,       0 },
1096     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
1097     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
1098     { X86::SUB16rr,         X86::SUB16rm,       0 },
1099     { X86::SUB32rr,         X86::SUB32rm,       0 },
1100     { X86::SUB64rr,         X86::SUB64rm,       0 },
1101     { X86::SUB8rr,          X86::SUB8rm,        0 },
1102     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
1103     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
1104     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
1105     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
1106     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
1107     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
1108     // FIXME: TEST*rr -> swapped operand of TEST*mr.
1109     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
1110     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
1111     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
1112     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
1113     { X86::XOR16rr,         X86::XOR16rm,       0 },
1114     { X86::XOR32rr,         X86::XOR32rm,       0 },
1115     { X86::XOR64rr,         X86::XOR64rm,       0 },
1116     { X86::XOR8rr,          X86::XOR8rm,        0 },
1117     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
1118     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
1119 
1120     // AVX 128-bit versions of foldable instructions
1121     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
1122     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
1123     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
1124     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
1125     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
1126     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
1127     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
1128     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
1129     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
1130     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
1131     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
1132     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
1133     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
1134     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
1135     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
1136     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
1137     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
1138     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
1139     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
1140     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
1141     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
1142     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
1143     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
1144     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
1145     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
1146     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
1147     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
1148     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
1149     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
1150     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
1151     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
1152     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
1153     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
1154     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
1155     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
1156     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
1157     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
1158     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
1159     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
1160     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
1161     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
1162     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
1163     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
1164     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
1165     // Do not fold VFs* loads because there are no scalar load variants for
1166     // these instructions. When folded, the load is required to be 128-bits, so
1167     // the load size would not match.
1168     { X86::VFvANDNPDrr,       X86::VFvANDNPDrm,        0 },
1169     { X86::VFvANDNPSrr,       X86::VFvANDNPSrm,        0 },
1170     { X86::VFvANDPDrr,        X86::VFvANDPDrm,         0 },
1171     { X86::VFvANDPSrr,        X86::VFvANDPSrm,         0 },
1172     { X86::VFvORPDrr,         X86::VFvORPDrm,          0 },
1173     { X86::VFvORPSrr,         X86::VFvORPSrm,          0 },
1174     { X86::VFvXORPDrr,        X86::VFvXORPDrm,         0 },
1175     { X86::VFvXORPSrr,        X86::VFvXORPSrm,         0 },
1176     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
1177     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
1178     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
1179     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
1180     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
1181     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
1182     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
1183     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
1184     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
1185     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
1186     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
1187     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
1188     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
1189     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
1190     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
1191     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
1192     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
1193     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
1194     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
1195     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
1196     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
1197     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
1198     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
1199     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
1200     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
1201     { X86::VORPDrr,           X86::VORPDrm,            0 },
1202     { X86::VORPSrr,           X86::VORPSrm,            0 },
1203     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
1204     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
1205     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
1206     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
1207     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
1208     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
1209     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
1210     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
1211     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
1212     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
1213     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
1214     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
1215     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
1216     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
1217     { X86::VPANDrr,           X86::VPANDrm,            0 },
1218     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
1219     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
1220     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
1221     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
1222     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
1223     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
1224     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
1225     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
1226     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
1227     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
1228     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
1229     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
1230     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
1231     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
1232     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
1233     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
1234     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
1235     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
1236     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
1237     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
1238     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
1239     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
1240     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
1241     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
1242     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
1243     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
1244     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
1245     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
1246     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
1247     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
1248     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
1249     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
1250     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
1251     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
1252     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
1253     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
1254     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
1255     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
1256     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
1257     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
1258     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
1259     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
1260     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
1261     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
1262     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
1263     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
1264     { X86::VPORrr,            X86::VPORrm,             0 },
1265     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
1266     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
1267     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
1268     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
1269     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
1270     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
1271     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
1272     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
1273     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
1274     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
1275     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
1276     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
1277     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
1278     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
1279     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
1280     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
1281     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
1282     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
1283     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
1284     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
1285     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
1286     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
1287     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
1288     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
1289     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
1290     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
1291     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
1292     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
1293     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
1294     { X86::VPXORrr,           X86::VPXORrm,            0 },
1295     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
1296     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
1297     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
1298     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
1299     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1300     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
1301     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1302     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
1303     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
1304     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
1305     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
1306     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
1307     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
1308     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
1309 
1310     // AVX 256-bit foldable instructions
1311     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
1312     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
1313     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
1314     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
1315     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1316     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1317     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1318     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1319     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1320     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1321     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1322     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1323     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1324     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1325     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1326     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1327     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
1328     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1329     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1330     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1331     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1332     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1333     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1334     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1335     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1336     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1337     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1338     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1339     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1340     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1341     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1342     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1343     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1344     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1345     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1346     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1347     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1348     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1349     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1350     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1351     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1352     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1353     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1354 
1355     // AVX2 foldable instructions
1356     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1357     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1358     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1359     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1360     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1361     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1362     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1363     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1364     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1365     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1366     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1367     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1368     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1369     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1370     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1371     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1372     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1373     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1374     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1375     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1376     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
1377     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1378     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1379     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1380     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1381     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1382     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1383     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1384     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1385     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1386     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1387     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1388     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1389     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1390     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1391     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1392     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1393     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1394     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1395     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1396     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1397     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1398     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1399     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1400     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1401     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1402     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1403     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1404     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1405     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1406     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1407     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1408     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1409     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1410     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1411     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1412     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1413     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1414     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1415     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1416     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1417     { X86::VPORYrr,           X86::VPORYrm,            0 },
1418     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1419     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1420     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1421     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1422     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1423     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1424     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1425     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1426     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1427     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1428     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1429     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1430     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1431     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1432     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1433     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1434     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1435     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1436     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1437     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1438     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1439     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1440     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1441     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1442     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1443     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
1444     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1445     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1446     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
1447     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
1448     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1449     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1450     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1451     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1452     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1453     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1454     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1455     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1456     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1457     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1458 
1459     // FMA4 foldable patterns
1460     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0 },
1461     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0 },
1462     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        0 },
1463     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        0 },
1464     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       0 },
1465     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       0 },
1466     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0 },
1467     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0 },
1468     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       0 },
1469     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       0 },
1470     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      0 },
1471     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      0 },
1472     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0 },
1473     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0 },
1474     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        0 },
1475     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        0 },
1476     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       0 },
1477     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       0 },
1478     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0 },
1479     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0 },
1480     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       0 },
1481     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       0 },
1482     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      0 },
1483     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      0 },
1484     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     0 },
1485     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     0 },
1486     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    0 },
1487     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    0 },
1488     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     0 },
1489     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     0 },
1490     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    0 },
1491     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    0 },
1492 
1493     // XOP foldable instructions
1494     { X86::VPCMOVrr,          X86::VPCMOVmr,            0 },
1495     { X86::VPCMOVrrY,         X86::VPCMOVmrY,           0 },
1496     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
1497     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
1498     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
1499     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
1500     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
1501     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
1502     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
1503     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
1504     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
1505     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
1506     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
1507     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
1508     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
1509     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
1510     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
1511     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
1512     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
1513     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
1514     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
1515     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
1516     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
1517     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
1518     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
1519     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
1520     { X86::VPPERMrr,          X86::VPPERMmr,            0 },
1521     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
1522     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
1523     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
1524     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
1525     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
1526     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
1527     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
1528     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
1529     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
1530     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
1531     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
1532     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
1533 
1534     // BMI/BMI2 foldable instructions
1535     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1536     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1537     { X86::MULX32rr,          X86::MULX32rm,            0 },
1538     { X86::MULX64rr,          X86::MULX64rm,            0 },
1539     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1540     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1541     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1542     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1543 
1544     // AVX-512 foldable instructions
1545     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
1546     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
1547     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
1548     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
1549     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
1550     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
1551     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
1552     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
1553     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
1554     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
1555     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
1556     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
1557     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
1558     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
1559     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
1560     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
1561     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
1562     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
1563     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
1564     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
1565     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
1566     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
1567     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
1568     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
1569     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
1570     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
1571     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
1572     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
1573     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
1574     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
1575     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
1576     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
1577     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
1578     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
1579     { X86::VALIGNQrri,        X86::VALIGNQrmi,          0 },
1580     { X86::VALIGNDrri,        X86::VALIGNDrmi,          0 },
1581     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
1582     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
1583     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
1584 
1585     // AVX-512{F,VL} foldable instructions
1586     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
1587     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
1588     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
1589 
1590     // AVX-512{F,VL} foldable instructions
1591     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
1592     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
1593     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
1594     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
1595 
1596     // AES foldable instructions
1597     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
1598     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
1599     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
1600     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
1601     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
1602     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
1603     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
1604     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
1605 
1606     // SHA foldable instructions
1607     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
1608     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
1609     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
1610     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
1611     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
1612     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
1613     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
1614   };
1615 
1616   for (unsigned i = 0, e = array_lengthof(MemoryFoldTable2); i != e; ++i) {
1617     unsigned RegOp = MemoryFoldTable2[i].RegOp;
1618     unsigned MemOp = MemoryFoldTable2[i].MemOp;
1619     unsigned Flags = MemoryFoldTable2[i].Flags;
1620     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1621                   RegOp, MemOp,
1622                   // Index 2, folded load
1623                   Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1624   }
1625 
1626   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
1627     // FMA foldable instructions
1628     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
1629     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
1630     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
1631     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
1632     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
1633     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
1634 
1635     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
1636     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
1637     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
1638     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
1639     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
1640     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
1641     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
1642     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
1643     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
1644     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
1645     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
1646     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
1647 
1648     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
1649     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
1650     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
1651     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
1652     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
1653     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
1654 
1655     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
1656     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
1657     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
1658     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
1659     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
1660     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
1661     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
1662     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
1663     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
1664     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
1665     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
1666     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
1667 
1668     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
1669     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
1670     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
1671     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
1672     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
1673     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
1674 
1675     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
1676     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
1677     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
1678     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
1679     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
1680     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
1681     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
1682     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
1683     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
1684     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
1685     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
1686     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
1687 
1688     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
1689     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
1690     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
1691     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
1692     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
1693     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
1694 
1695     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
1696     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
1697     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
1698     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
1699     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
1700     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
1701     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
1702     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
1703     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
1704     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
1705     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
1706     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
1707 
1708     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
1709     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
1710     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
1711     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
1712     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
1713     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
1714     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
1715     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
1716     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
1717     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
1718     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
1719     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
1720 
1721     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
1722     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
1723     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
1724     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
1725     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
1726     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
1727     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
1728     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
1729     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
1730     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
1731     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
1732     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
1733 
1734     // FMA4 foldable patterns
1735     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1736     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1737     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1738     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1739     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1740     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1741     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1742     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1743     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1744     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1745     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1746     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1747     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1748     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1749     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1750     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1751     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1752     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1753     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1754     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1755     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1756     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1757     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1758     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1759     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1760     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1761     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1762     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1763     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1764     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1765     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1766     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1767 
1768     // XOP foldable instructions
1769     { X86::VPCMOVrr,              X86::VPCMOVrm,              0 },
1770     { X86::VPCMOVrrY,             X86::VPCMOVrmY,             0 },
1771     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
1772     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
1773     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
1774     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
1775     { X86::VPPERMrr,              X86::VPPERMrm,              0 },
1776 
1777     // AVX-512 VPERMI instructions with 3 source operands.
1778     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
1779     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
1780     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
1781     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
1782     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
1783     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
1784     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
1785     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
1786     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
1787     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
1788     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
1789     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
1790     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
1791      // AVX-512 arithmetic instructions
1792     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
1793     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
1794     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
1795     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
1796     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
1797     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
1798     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
1799     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
1800     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
1801     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
1802     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
1803     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
1804     // AVX-512{F,VL} arithmetic instructions 256-bit
1805     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
1806     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
1807     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
1808     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
1809     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
1810     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
1811     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
1812     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
1813     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
1814     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
1815     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
1816     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
1817     // AVX-512{F,VL} arithmetic instructions 128-bit
1818     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
1819     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
1820     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
1821     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
1822     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
1823     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
1824     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
1825     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
1826     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
1827     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
1828     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
1829     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
1830   };
1831 
1832   for (unsigned i = 0, e = array_lengthof(MemoryFoldTable3); i != e; ++i) {
1833     unsigned RegOp = MemoryFoldTable3[i].RegOp;
1834     unsigned MemOp = MemoryFoldTable3[i].MemOp;
1835     unsigned Flags = MemoryFoldTable3[i].Flags;
1836     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1837                   RegOp, MemOp,
1838                   // Index 3, folded load
1839                   Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1840   }
1841 
1842   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
1843      // AVX-512 foldable instructions
1844     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
1845     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
1846     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
1847     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
1848     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
1849     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
1850     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
1851     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
1852     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
1853     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
1854     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
1855     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
1856     // AVX-512{F,VL} foldable instructions 256-bit
1857     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
1858     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
1859     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
1860     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
1861     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
1862     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
1863     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
1864     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
1865     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
1866     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
1867     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
1868     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
1869     // AVX-512{F,VL} foldable instructions 128-bit
1870     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
1871     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
1872     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
1873     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
1874     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
1875     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
1876     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
1877     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
1878     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
1879     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
1880     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
1881     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
1882   };
1883 
1884   for (unsigned i = 0, e = array_lengthof(MemoryFoldTable4); i != e; ++i) {
1885     unsigned RegOp = MemoryFoldTable4[i].RegOp;
1886     unsigned MemOp = MemoryFoldTable4[i].MemOp;
1887     unsigned Flags = MemoryFoldTable4[i].Flags;
1888     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
1889                   RegOp, MemOp,
1890                   // Index 4, folded load
1891                   Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
1892   }
1893 }
1894 
1895 void
1896 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1897                             MemOp2RegOpTableType &M2RTable,
1898                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
1899     if ((Flags & TB_NO_FORWARD) == 0) {
1900       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1901       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1902     }
1903     if ((Flags & TB_NO_REVERSE) == 0) {
1904       assert(!M2RTable.count(MemOp) &&
1905            "Duplicated entries in unfolding maps?");
1906       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1907     }
1908 }
1909 
1910 bool
1911 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1912                                     unsigned &SrcReg, unsigned &DstReg,
1913                                     unsigned &SubIdx) const {
1914   switch (MI.getOpcode()) {
1915   default: break;
1916   case X86::MOVSX16rr8:
1917   case X86::MOVZX16rr8:
1918   case X86::MOVSX32rr8:
1919   case X86::MOVZX32rr8:
1920   case X86::MOVSX64rr8:
1921     if (!Subtarget.is64Bit())
1922       // It's not always legal to reference the low 8-bit of the larger
1923       // register in 32-bit mode.
1924       return false;
1925   case X86::MOVSX32rr16:
1926   case X86::MOVZX32rr16:
1927   case X86::MOVSX64rr16:
1928   case X86::MOVSX64rr32: {
1929     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1930       // Be conservative.
1931       return false;
1932     SrcReg = MI.getOperand(1).getReg();
1933     DstReg = MI.getOperand(0).getReg();
1934     switch (MI.getOpcode()) {
1935     default: llvm_unreachable("Unreachable!");
1936     case X86::MOVSX16rr8:
1937     case X86::MOVZX16rr8:
1938     case X86::MOVSX32rr8:
1939     case X86::MOVZX32rr8:
1940     case X86::MOVSX64rr8:
1941       SubIdx = X86::sub_8bit;
1942       break;
1943     case X86::MOVSX32rr16:
1944     case X86::MOVZX32rr16:
1945     case X86::MOVSX64rr16:
1946       SubIdx = X86::sub_16bit;
1947       break;
1948     case X86::MOVSX64rr32:
1949       SubIdx = X86::sub_32bit;
1950       break;
1951     }
1952     return true;
1953   }
1954   }
1955   return false;
1956 }
1957 
1958 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
1959   const MachineFunction *MF = MI->getParent()->getParent();
1960   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
1961 
1962   if (MI->getOpcode() == getCallFrameSetupOpcode() ||
1963       MI->getOpcode() == getCallFrameDestroyOpcode()) {
1964     unsigned StackAlign = TFI->getStackAlignment();
1965     int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
1966                  StackAlign;
1967 
1968     SPAdj -= MI->getOperand(1).getImm();
1969 
1970     if (MI->getOpcode() == getCallFrameSetupOpcode())
1971       return SPAdj;
1972     else
1973       return -SPAdj;
1974   }
1975 
1976   // To know whether a call adjusts the stack, we need information
1977   // that is bound to the following ADJCALLSTACKUP pseudo.
1978   // Look for the next ADJCALLSTACKUP that follows the call.
1979   if (MI->isCall()) {
1980     const MachineBasicBlock* MBB = MI->getParent();
1981     auto I = ++MachineBasicBlock::const_iterator(MI);
1982     for (auto E = MBB->end(); I != E; ++I) {
1983       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
1984           I->isCall())
1985         break;
1986     }
1987 
1988     // If we could not find a frame destroy opcode, then it has already
1989     // been simplified, so we don't care.
1990     if (I->getOpcode() != getCallFrameDestroyOpcode())
1991       return 0;
1992 
1993     return -(I->getOperand(1).getImm());
1994   }
1995 
1996   // Currently handle only PUSHes we can reasonably expect to see
1997   // in call sequences
1998   switch (MI->getOpcode()) {
1999   default:
2000     return 0;
2001   case X86::PUSH32i8:
2002   case X86::PUSH32r:
2003   case X86::PUSH32rmm:
2004   case X86::PUSH32rmr:
2005   case X86::PUSHi32:
2006     return 4;
2007   }
2008 }
2009 
2010 /// Return true and the FrameIndex if the specified
2011 /// operand and follow operands form a reference to the stack frame.
2012 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2013                                   int &FrameIndex) const {
2014   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2015       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2016       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2017       MI->getOperand(Op+X86::AddrDisp).isImm() &&
2018       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2019       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2020       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2021     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
2022     return true;
2023   }
2024   return false;
2025 }
2026 
2027 static bool isFrameLoadOpcode(int Opcode) {
2028   switch (Opcode) {
2029   default:
2030     return false;
2031   case X86::MOV8rm:
2032   case X86::MOV16rm:
2033   case X86::MOV32rm:
2034   case X86::MOV64rm:
2035   case X86::LD_Fp64m:
2036   case X86::MOVSSrm:
2037   case X86::MOVSDrm:
2038   case X86::MOVAPSrm:
2039   case X86::MOVAPDrm:
2040   case X86::MOVDQArm:
2041   case X86::VMOVSSrm:
2042   case X86::VMOVSDrm:
2043   case X86::VMOVAPSrm:
2044   case X86::VMOVAPDrm:
2045   case X86::VMOVDQArm:
2046   case X86::VMOVUPSYrm:
2047   case X86::VMOVAPSYrm:
2048   case X86::VMOVUPDYrm:
2049   case X86::VMOVAPDYrm:
2050   case X86::VMOVDQUYrm:
2051   case X86::VMOVDQAYrm:
2052   case X86::MMX_MOVD64rm:
2053   case X86::MMX_MOVQ64rm:
2054   case X86::VMOVAPSZrm:
2055   case X86::VMOVUPSZrm:
2056     return true;
2057   }
2058 }
2059 
2060 static bool isFrameStoreOpcode(int Opcode) {
2061   switch (Opcode) {
2062   default: break;
2063   case X86::MOV8mr:
2064   case X86::MOV16mr:
2065   case X86::MOV32mr:
2066   case X86::MOV64mr:
2067   case X86::ST_FpP64m:
2068   case X86::MOVSSmr:
2069   case X86::MOVSDmr:
2070   case X86::MOVAPSmr:
2071   case X86::MOVAPDmr:
2072   case X86::MOVDQAmr:
2073   case X86::VMOVSSmr:
2074   case X86::VMOVSDmr:
2075   case X86::VMOVAPSmr:
2076   case X86::VMOVAPDmr:
2077   case X86::VMOVDQAmr:
2078   case X86::VMOVUPSYmr:
2079   case X86::VMOVAPSYmr:
2080   case X86::VMOVUPDYmr:
2081   case X86::VMOVAPDYmr:
2082   case X86::VMOVDQUYmr:
2083   case X86::VMOVDQAYmr:
2084   case X86::VMOVUPSZmr:
2085   case X86::VMOVAPSZmr:
2086   case X86::MMX_MOVD64mr:
2087   case X86::MMX_MOVQ64mr:
2088   case X86::MMX_MOVNTQmr:
2089     return true;
2090   }
2091   return false;
2092 }
2093 
2094 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
2095                                            int &FrameIndex) const {
2096   if (isFrameLoadOpcode(MI->getOpcode()))
2097     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2098       return MI->getOperand(0).getReg();
2099   return 0;
2100 }
2101 
2102 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
2103                                                  int &FrameIndex) const {
2104   if (isFrameLoadOpcode(MI->getOpcode())) {
2105     unsigned Reg;
2106     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2107       return Reg;
2108     // Check for post-frame index elimination operations
2109     const MachineMemOperand *Dummy;
2110     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
2111   }
2112   return 0;
2113 }
2114 
2115 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
2116                                           int &FrameIndex) const {
2117   if (isFrameStoreOpcode(MI->getOpcode()))
2118     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2119         isFrameOperand(MI, 0, FrameIndex))
2120       return MI->getOperand(X86::AddrNumOperands).getReg();
2121   return 0;
2122 }
2123 
2124 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2125                                                 int &FrameIndex) const {
2126   if (isFrameStoreOpcode(MI->getOpcode())) {
2127     unsigned Reg;
2128     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2129       return Reg;
2130     // Check for post-frame index elimination operations
2131     const MachineMemOperand *Dummy;
2132     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
2133   }
2134   return 0;
2135 }
2136 
2137 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
2138 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
2139   // Don't waste compile time scanning use-def chains of physregs.
2140   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2141     return false;
2142   bool isPICBase = false;
2143   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2144          E = MRI.def_instr_end(); I != E; ++I) {
2145     MachineInstr *DefMI = &*I;
2146     if (DefMI->getOpcode() != X86::MOVPC32r)
2147       return false;
2148     assert(!isPICBase && "More than one PIC base?");
2149     isPICBase = true;
2150   }
2151   return isPICBase;
2152 }
2153 
2154 bool
2155 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2156                                                 AliasAnalysis *AA) const {
2157   switch (MI->getOpcode()) {
2158   default: break;
2159   case X86::MOV8rm:
2160   case X86::MOV16rm:
2161   case X86::MOV32rm:
2162   case X86::MOV64rm:
2163   case X86::LD_Fp64m:
2164   case X86::MOVSSrm:
2165   case X86::MOVSDrm:
2166   case X86::MOVAPSrm:
2167   case X86::MOVUPSrm:
2168   case X86::MOVAPDrm:
2169   case X86::MOVDQArm:
2170   case X86::MOVDQUrm:
2171   case X86::VMOVSSrm:
2172   case X86::VMOVSDrm:
2173   case X86::VMOVAPSrm:
2174   case X86::VMOVUPSrm:
2175   case X86::VMOVAPDrm:
2176   case X86::VMOVDQArm:
2177   case X86::VMOVDQUrm:
2178   case X86::VMOVAPSYrm:
2179   case X86::VMOVUPSYrm:
2180   case X86::VMOVAPDYrm:
2181   case X86::VMOVDQAYrm:
2182   case X86::VMOVDQUYrm:
2183   case X86::MMX_MOVD64rm:
2184   case X86::MMX_MOVQ64rm:
2185   case X86::FsVMOVAPSrm:
2186   case X86::FsVMOVAPDrm:
2187   case X86::FsMOVAPSrm:
2188   case X86::FsMOVAPDrm: {
2189     // Loads from constant pools are trivially rematerializable.
2190     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2191         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2192         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2193         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2194         MI->isInvariantLoad(AA)) {
2195       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2196       if (BaseReg == 0 || BaseReg == X86::RIP)
2197         return true;
2198       // Allow re-materialization of PIC load.
2199       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
2200         return false;
2201       const MachineFunction &MF = *MI->getParent()->getParent();
2202       const MachineRegisterInfo &MRI = MF.getRegInfo();
2203       return regIsPICBase(BaseReg, MRI);
2204     }
2205     return false;
2206   }
2207 
2208   case X86::LEA32r:
2209   case X86::LEA64r: {
2210     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2211         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2212         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2213         !MI->getOperand(1+X86::AddrDisp).isReg()) {
2214       // lea fi#, lea GV, etc. are all rematerializable.
2215       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
2216         return true;
2217       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
2218       if (BaseReg == 0)
2219         return true;
2220       // Allow re-materialization of lea PICBase + x.
2221       const MachineFunction &MF = *MI->getParent()->getParent();
2222       const MachineRegisterInfo &MRI = MF.getRegInfo();
2223       return regIsPICBase(BaseReg, MRI);
2224     }
2225     return false;
2226   }
2227   }
2228 
2229   // All other instructions marked M_REMATERIALIZABLE are always trivially
2230   // rematerializable.
2231   return true;
2232 }
2233 
2234 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2235                                          MachineBasicBlock::iterator I) const {
2236   MachineBasicBlock::iterator E = MBB.end();
2237 
2238   // For compile time consideration, if we are not able to determine the
2239   // safety after visiting 4 instructions in each direction, we will assume
2240   // it's not safe.
2241   MachineBasicBlock::iterator Iter = I;
2242   for (unsigned i = 0; Iter != E && i < 4; ++i) {
2243     bool SeenDef = false;
2244     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2245       MachineOperand &MO = Iter->getOperand(j);
2246       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2247         SeenDef = true;
2248       if (!MO.isReg())
2249         continue;
2250       if (MO.getReg() == X86::EFLAGS) {
2251         if (MO.isUse())
2252           return false;
2253         SeenDef = true;
2254       }
2255     }
2256 
2257     if (SeenDef)
2258       // This instruction defines EFLAGS, no need to look any further.
2259       return true;
2260     ++Iter;
2261     // Skip over DBG_VALUE.
2262     while (Iter != E && Iter->isDebugValue())
2263       ++Iter;
2264   }
2265 
2266   // It is safe to clobber EFLAGS at the end of a block of no successor has it
2267   // live in.
2268   if (Iter == E) {
2269     for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2270            SE = MBB.succ_end(); SI != SE; ++SI)
2271       if ((*SI)->isLiveIn(X86::EFLAGS))
2272         return false;
2273     return true;
2274   }
2275 
2276   MachineBasicBlock::iterator B = MBB.begin();
2277   Iter = I;
2278   for (unsigned i = 0; i < 4; ++i) {
2279     // If we make it to the beginning of the block, it's safe to clobber
2280     // EFLAGS iff EFLAGS is not live-in.
2281     if (Iter == B)
2282       return !MBB.isLiveIn(X86::EFLAGS);
2283 
2284     --Iter;
2285     // Skip over DBG_VALUE.
2286     while (Iter != B && Iter->isDebugValue())
2287       --Iter;
2288 
2289     bool SawKill = false;
2290     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2291       MachineOperand &MO = Iter->getOperand(j);
2292       // A register mask may clobber EFLAGS, but we should still look for a
2293       // live EFLAGS def.
2294       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2295         SawKill = true;
2296       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2297         if (MO.isDef()) return MO.isDead();
2298         if (MO.isKill()) SawKill = true;
2299       }
2300     }
2301 
2302     if (SawKill)
2303       // This instruction kills EFLAGS and doesn't redefine it, so
2304       // there's no need to look further.
2305       return true;
2306   }
2307 
2308   // Conservative answer.
2309   return false;
2310 }
2311 
2312 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2313                                  MachineBasicBlock::iterator I,
2314                                  unsigned DestReg, unsigned SubIdx,
2315                                  const MachineInstr *Orig,
2316                                  const TargetRegisterInfo &TRI) const {
2317   // MOV32r0 is implemented with a xor which clobbers condition code.
2318   // Re-materialize it as movri instructions to avoid side effects.
2319   unsigned Opc = Orig->getOpcode();
2320   if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2321     DebugLoc DL = Orig->getDebugLoc();
2322     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2323       .addImm(0);
2324   } else {
2325     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
2326     MBB.insert(I, MI);
2327   }
2328 
2329   MachineInstr *NewMI = std::prev(I);
2330   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
2331 }
2332 
2333 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
2334 static bool hasLiveCondCodeDef(MachineInstr *MI) {
2335   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2336     MachineOperand &MO = MI->getOperand(i);
2337     if (MO.isReg() && MO.isDef() &&
2338         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2339       return true;
2340     }
2341   }
2342   return false;
2343 }
2344 
2345 /// Check whether the shift count for a machine operand is non-zero.
2346 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2347                                               unsigned ShiftAmtOperandIdx) {
2348   // The shift count is six bits with the REX.W prefix and five bits without.
2349   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2350   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2351   return Imm & ShiftCountMask;
2352 }
2353 
2354 /// Check whether the given shift count is appropriate
2355 /// can be represented by a LEA instruction.
2356 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2357   // Left shift instructions can be transformed into load-effective-address
2358   // instructions if we can encode them appropriately.
2359   // A LEA instruction utilizes a SIB byte to encode it's scale factor.
2360   // The SIB.scale field is two bits wide which means that we can encode any
2361   // shift amount less than 4.
2362   return ShAmt < 4 && ShAmt > 0;
2363 }
2364 
2365 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2366                                   unsigned Opc, bool AllowSP,
2367                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
2368                                   MachineOperand &ImplicitOp) const {
2369   MachineFunction &MF = *MI->getParent()->getParent();
2370   const TargetRegisterClass *RC;
2371   if (AllowSP) {
2372     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2373   } else {
2374     RC = Opc != X86::LEA32r ?
2375       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2376   }
2377   unsigned SrcReg = Src.getReg();
2378 
2379   // For both LEA64 and LEA32 the register already has essentially the right
2380   // type (32-bit or 64-bit) we may just need to forbid SP.
2381   if (Opc != X86::LEA64_32r) {
2382     NewSrc = SrcReg;
2383     isKill = Src.isKill();
2384     isUndef = Src.isUndef();
2385 
2386     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2387         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2388       return false;
2389 
2390     return true;
2391   }
2392 
2393   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2394   // another we need to add 64-bit registers to the final MI.
2395   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2396     ImplicitOp = Src;
2397     ImplicitOp.setImplicit();
2398 
2399     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2400     MachineBasicBlock::LivenessQueryResult LQR =
2401       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2402 
2403     switch (LQR) {
2404     case MachineBasicBlock::LQR_Unknown:
2405       // We can't give sane liveness flags to the instruction, abandon LEA
2406       // formation.
2407       return false;
2408     case MachineBasicBlock::LQR_Live:
2409       isKill = MI->killsRegister(SrcReg);
2410       isUndef = false;
2411       break;
2412     default:
2413       // The physreg itself is dead, so we have to use it as an <undef>.
2414       isKill = false;
2415       isUndef = true;
2416       break;
2417     }
2418   } else {
2419     // Virtual register of the wrong class, we have to create a temporary 64-bit
2420     // vreg to feed into the LEA.
2421     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2422     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2423             get(TargetOpcode::COPY))
2424       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2425         .addOperand(Src);
2426 
2427     // Which is obviously going to be dead after we're done with it.
2428     isKill = true;
2429     isUndef = false;
2430   }
2431 
2432   // We've set all the parameters without issue.
2433   return true;
2434 }
2435 
2436 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2437 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
2438 /// truncating back down to a 16-bit subregister.
2439 MachineInstr *
2440 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2441                                            MachineFunction::iterator &MFI,
2442                                            MachineBasicBlock::iterator &MBBI,
2443                                            LiveVariables *LV) const {
2444   MachineInstr *MI = MBBI;
2445   unsigned Dest = MI->getOperand(0).getReg();
2446   unsigned Src = MI->getOperand(1).getReg();
2447   bool isDead = MI->getOperand(0).isDead();
2448   bool isKill = MI->getOperand(1).isKill();
2449 
2450   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2451   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
2452   unsigned Opc, leaInReg;
2453   if (Subtarget.is64Bit()) {
2454     Opc = X86::LEA64_32r;
2455     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2456   } else {
2457     Opc = X86::LEA32r;
2458     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2459   }
2460 
2461   // Build and insert into an implicit UNDEF value. This is OK because
2462   // well be shifting and then extracting the lower 16-bits.
2463   // This has the potential to cause partial register stall. e.g.
2464   //   movw    (%rbp,%rcx,2), %dx
2465   //   leal    -65(%rdx), %esi
2466   // But testing has shown this *does* help performance in 64-bit mode (at
2467   // least on modern x86 machines).
2468   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2469   MachineInstr *InsMI =
2470     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2471     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2472     .addReg(Src, getKillRegState(isKill));
2473 
2474   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2475                                     get(Opc), leaOutReg);
2476   switch (MIOpc) {
2477   default: llvm_unreachable("Unreachable!");
2478   case X86::SHL16ri: {
2479     unsigned ShAmt = MI->getOperand(2).getImm();
2480     MIB.addReg(0).addImm(1 << ShAmt)
2481        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
2482     break;
2483   }
2484   case X86::INC16r:
2485     addRegOffset(MIB, leaInReg, true, 1);
2486     break;
2487   case X86::DEC16r:
2488     addRegOffset(MIB, leaInReg, true, -1);
2489     break;
2490   case X86::ADD16ri:
2491   case X86::ADD16ri8:
2492   case X86::ADD16ri_DB:
2493   case X86::ADD16ri8_DB:
2494     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
2495     break;
2496   case X86::ADD16rr:
2497   case X86::ADD16rr_DB: {
2498     unsigned Src2 = MI->getOperand(2).getReg();
2499     bool isKill2 = MI->getOperand(2).isKill();
2500     unsigned leaInReg2 = 0;
2501     MachineInstr *InsMI2 = nullptr;
2502     if (Src == Src2) {
2503       // ADD16rr %reg1028<kill>, %reg1028
2504       // just a single insert_subreg.
2505       addRegReg(MIB, leaInReg, true, leaInReg, false);
2506     } else {
2507       if (Subtarget.is64Bit())
2508         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2509       else
2510         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2511       // Build and insert into an implicit UNDEF value. This is OK because
2512       // well be shifting and then extracting the lower 16-bits.
2513       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
2514       InsMI2 =
2515         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
2516         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2517         .addReg(Src2, getKillRegState(isKill2));
2518       addRegReg(MIB, leaInReg, true, leaInReg2, true);
2519     }
2520     if (LV && isKill2 && InsMI2)
2521       LV->replaceKillInstruction(Src2, MI, InsMI2);
2522     break;
2523   }
2524   }
2525 
2526   MachineInstr *NewMI = MIB;
2527   MachineInstr *ExtMI =
2528     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2529     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2530     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
2531 
2532   if (LV) {
2533     // Update live variables
2534     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2535     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2536     if (isKill)
2537       LV->replaceKillInstruction(Src, MI, InsMI);
2538     if (isDead)
2539       LV->replaceKillInstruction(Dest, MI, ExtMI);
2540   }
2541 
2542   return ExtMI;
2543 }
2544 
2545 /// This method must be implemented by targets that
2546 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
2547 /// may be able to convert a two-address instruction into a true
2548 /// three-address instruction on demand.  This allows the X86 target (for
2549 /// example) to convert ADD and SHL instructions into LEA instructions if they
2550 /// would require register copies due to two-addressness.
2551 ///
2552 /// This method returns a null pointer if the transformation cannot be
2553 /// performed, otherwise it returns the new instruction.
2554 ///
2555 MachineInstr *
2556 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2557                                     MachineBasicBlock::iterator &MBBI,
2558                                     LiveVariables *LV) const {
2559   MachineInstr *MI = MBBI;
2560 
2561   // The following opcodes also sets the condition code register(s). Only
2562   // convert them to equivalent lea if the condition code register def's
2563   // are dead!
2564   if (hasLiveCondCodeDef(MI))
2565     return nullptr;
2566 
2567   MachineFunction &MF = *MI->getParent()->getParent();
2568   // All instructions input are two-addr instructions.  Get the known operands.
2569   const MachineOperand &Dest = MI->getOperand(0);
2570   const MachineOperand &Src = MI->getOperand(1);
2571 
2572   MachineInstr *NewMI = nullptr;
2573   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
2574   // we have better subtarget support, enable the 16-bit LEA generation here.
2575   // 16-bit LEA is also slow on Core2.
2576   bool DisableLEA16 = true;
2577   bool is64Bit = Subtarget.is64Bit();
2578 
2579   unsigned MIOpc = MI->getOpcode();
2580   switch (MIOpc) {
2581   default: return nullptr;
2582   case X86::SHL64ri: {
2583     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2584     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2585     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2586 
2587     // LEA can't handle RSP.
2588     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2589         !MF.getRegInfo().constrainRegClass(Src.getReg(),
2590                                            &X86::GR64_NOSPRegClass))
2591       return nullptr;
2592 
2593     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2594       .addOperand(Dest)
2595       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2596     break;
2597   }
2598   case X86::SHL32ri: {
2599     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2600     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2601     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2602 
2603     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2604 
2605     // LEA can't handle ESP.
2606     bool isKill, isUndef;
2607     unsigned SrcReg;
2608     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2609     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2610                         SrcReg, isKill, isUndef, ImplicitOp))
2611       return nullptr;
2612 
2613     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2614       .addOperand(Dest)
2615       .addReg(0).addImm(1 << ShAmt)
2616       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2617       .addImm(0).addReg(0);
2618     if (ImplicitOp.getReg() != 0)
2619       MIB.addOperand(ImplicitOp);
2620     NewMI = MIB;
2621 
2622     break;
2623   }
2624   case X86::SHL16ri: {
2625     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2626     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
2627     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
2628 
2629     if (DisableLEA16)
2630       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
2631     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2632       .addOperand(Dest)
2633       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2634     break;
2635   }
2636   case X86::INC64r:
2637   case X86::INC32r: {
2638     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2639     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2640       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2641     bool isKill, isUndef;
2642     unsigned SrcReg;
2643     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2644     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2645                         SrcReg, isKill, isUndef, ImplicitOp))
2646       return nullptr;
2647 
2648     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2649         .addOperand(Dest)
2650         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2651     if (ImplicitOp.getReg() != 0)
2652       MIB.addOperand(ImplicitOp);
2653 
2654     NewMI = addOffset(MIB, 1);
2655     break;
2656   }
2657   case X86::INC16r:
2658     if (DisableLEA16)
2659       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2660                      : nullptr;
2661     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2662     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2663                       .addOperand(Dest).addOperand(Src), 1);
2664     break;
2665   case X86::DEC64r:
2666   case X86::DEC32r: {
2667     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2668     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2669       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2670 
2671     bool isKill, isUndef;
2672     unsigned SrcReg;
2673     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2674     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2675                         SrcReg, isKill, isUndef, ImplicitOp))
2676       return nullptr;
2677 
2678     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2679         .addOperand(Dest)
2680         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2681     if (ImplicitOp.getReg() != 0)
2682       MIB.addOperand(ImplicitOp);
2683 
2684     NewMI = addOffset(MIB, -1);
2685 
2686     break;
2687   }
2688   case X86::DEC16r:
2689     if (DisableLEA16)
2690       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2691                      : nullptr;
2692     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2693     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2694                       .addOperand(Dest).addOperand(Src), -1);
2695     break;
2696   case X86::ADD64rr:
2697   case X86::ADD64rr_DB:
2698   case X86::ADD32rr:
2699   case X86::ADD32rr_DB: {
2700     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2701     unsigned Opc;
2702     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2703       Opc = X86::LEA64r;
2704     else
2705       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2706 
2707     bool isKill, isUndef;
2708     unsigned SrcReg;
2709     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2710     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2711                         SrcReg, isKill, isUndef, ImplicitOp))
2712       return nullptr;
2713 
2714     const MachineOperand &Src2 = MI->getOperand(2);
2715     bool isKill2, isUndef2;
2716     unsigned SrcReg2;
2717     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2718     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2719                         SrcReg2, isKill2, isUndef2, ImplicitOp2))
2720       return nullptr;
2721 
2722     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2723       .addOperand(Dest);
2724     if (ImplicitOp.getReg() != 0)
2725       MIB.addOperand(ImplicitOp);
2726     if (ImplicitOp2.getReg() != 0)
2727       MIB.addOperand(ImplicitOp2);
2728 
2729     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2730 
2731     // Preserve undefness of the operands.
2732     NewMI->getOperand(1).setIsUndef(isUndef);
2733     NewMI->getOperand(3).setIsUndef(isUndef2);
2734 
2735     if (LV && Src2.isKill())
2736       LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2737     break;
2738   }
2739   case X86::ADD16rr:
2740   case X86::ADD16rr_DB: {
2741     if (DisableLEA16)
2742       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2743                      : nullptr;
2744     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2745     unsigned Src2 = MI->getOperand(2).getReg();
2746     bool isKill2 = MI->getOperand(2).isKill();
2747     NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2748                       .addOperand(Dest),
2749                       Src.getReg(), Src.isKill(), Src2, isKill2);
2750 
2751     // Preserve undefness of the operands.
2752     bool isUndef = MI->getOperand(1).isUndef();
2753     bool isUndef2 = MI->getOperand(2).isUndef();
2754     NewMI->getOperand(1).setIsUndef(isUndef);
2755     NewMI->getOperand(3).setIsUndef(isUndef2);
2756 
2757     if (LV && isKill2)
2758       LV->replaceKillInstruction(Src2, MI, NewMI);
2759     break;
2760   }
2761   case X86::ADD64ri32:
2762   case X86::ADD64ri8:
2763   case X86::ADD64ri32_DB:
2764   case X86::ADD64ri8_DB:
2765     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2766     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2767                       .addOperand(Dest).addOperand(Src),
2768                       MI->getOperand(2).getImm());
2769     break;
2770   case X86::ADD32ri:
2771   case X86::ADD32ri8:
2772   case X86::ADD32ri_DB:
2773   case X86::ADD32ri8_DB: {
2774     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2775     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2776 
2777     bool isKill, isUndef;
2778     unsigned SrcReg;
2779     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2780     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2781                         SrcReg, isKill, isUndef, ImplicitOp))
2782       return nullptr;
2783 
2784     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2785         .addOperand(Dest)
2786         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2787     if (ImplicitOp.getReg() != 0)
2788       MIB.addOperand(ImplicitOp);
2789 
2790     NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2791     break;
2792   }
2793   case X86::ADD16ri:
2794   case X86::ADD16ri8:
2795   case X86::ADD16ri_DB:
2796   case X86::ADD16ri8_DB:
2797     if (DisableLEA16)
2798       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2799                      : nullptr;
2800     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2801     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2802                       .addOperand(Dest).addOperand(Src),
2803                       MI->getOperand(2).getImm());
2804     break;
2805   }
2806 
2807   if (!NewMI) return nullptr;
2808 
2809   if (LV) {  // Update live variables
2810     if (Src.isKill())
2811       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2812     if (Dest.isDead())
2813       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2814   }
2815 
2816   MFI->insert(MBBI, NewMI);          // Insert the new inst
2817   return NewMI;
2818 }
2819 
2820 /// We have a few instructions that must be hacked on to commute them.
2821 ///
2822 MachineInstr *
2823 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2824   switch (MI->getOpcode()) {
2825   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2826   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2827   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2828   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2829   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2830   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2831     unsigned Opc;
2832     unsigned Size;
2833     switch (MI->getOpcode()) {
2834     default: llvm_unreachable("Unreachable!");
2835     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2836     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2837     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2838     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2839     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2840     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2841     }
2842     unsigned Amt = MI->getOperand(3).getImm();
2843     if (NewMI) {
2844       MachineFunction &MF = *MI->getParent()->getParent();
2845       MI = MF.CloneMachineInstr(MI);
2846       NewMI = false;
2847     }
2848     MI->setDesc(get(Opc));
2849     MI->getOperand(3).setImm(Size-Amt);
2850     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2851   }
2852   case X86::BLENDPDrri:
2853   case X86::BLENDPSrri:
2854   case X86::PBLENDWrri:
2855   case X86::VBLENDPDrri:
2856   case X86::VBLENDPSrri:
2857   case X86::VBLENDPDYrri:
2858   case X86::VBLENDPSYrri:
2859   case X86::VPBLENDDrri:
2860   case X86::VPBLENDWrri:
2861   case X86::VPBLENDDYrri:
2862   case X86::VPBLENDWYrri:{
2863     unsigned Mask;
2864     switch (MI->getOpcode()) {
2865     default: llvm_unreachable("Unreachable!");
2866     case X86::BLENDPDrri:    Mask = 0x03; break;
2867     case X86::BLENDPSrri:    Mask = 0x0F; break;
2868     case X86::PBLENDWrri:    Mask = 0xFF; break;
2869     case X86::VBLENDPDrri:   Mask = 0x03; break;
2870     case X86::VBLENDPSrri:   Mask = 0x0F; break;
2871     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
2872     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
2873     case X86::VPBLENDDrri:   Mask = 0x0F; break;
2874     case X86::VPBLENDWrri:   Mask = 0xFF; break;
2875     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
2876     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
2877     }
2878     // Only the least significant bits of Imm are used.
2879     unsigned Imm = MI->getOperand(3).getImm() & Mask;
2880     if (NewMI) {
2881       MachineFunction &MF = *MI->getParent()->getParent();
2882       MI = MF.CloneMachineInstr(MI);
2883       NewMI = false;
2884     }
2885     MI->getOperand(3).setImm(Mask ^ Imm);
2886     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2887   }
2888   case X86::PCLMULQDQrr:
2889   case X86::VPCLMULQDQrr:{
2890     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2891     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2892     unsigned Imm = MI->getOperand(3).getImm();
2893     unsigned Src1Hi = Imm & 0x01;
2894     unsigned Src2Hi = Imm & 0x10;
2895     if (NewMI) {
2896       MachineFunction &MF = *MI->getParent()->getParent();
2897       MI = MF.CloneMachineInstr(MI);
2898       NewMI = false;
2899     }
2900     MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
2901     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2902   }
2903   case X86::CMPPDrri:
2904   case X86::CMPPSrri:
2905   case X86::VCMPPDrri:
2906   case X86::VCMPPSrri:
2907   case X86::VCMPPDYrri:
2908   case X86::VCMPPSYrri: {
2909     // Float comparison can be safely commuted for
2910     // Ordered/Unordered/Equal/NotEqual tests
2911     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
2912     switch (Imm) {
2913     case 0x00: // EQUAL
2914     case 0x03: // UNORDERED
2915     case 0x04: // NOT EQUAL
2916     case 0x07: // ORDERED
2917       if (NewMI) {
2918         MachineFunction &MF = *MI->getParent()->getParent();
2919         MI = MF.CloneMachineInstr(MI);
2920         NewMI = false;
2921       }
2922       return TargetInstrInfo::commuteInstruction(MI, NewMI);
2923     default:
2924       return nullptr;
2925     }
2926   }
2927   case X86::VPCOMBri: case X86::VPCOMUBri:
2928   case X86::VPCOMDri: case X86::VPCOMUDri:
2929   case X86::VPCOMQri: case X86::VPCOMUQri:
2930   case X86::VPCOMWri: case X86::VPCOMUWri: {
2931     // Flip comparison mode immediate (if necessary).
2932     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
2933     switch (Imm) {
2934     case 0x00: Imm = 0x02; break; // LT -> GT
2935     case 0x01: Imm = 0x03; break; // LE -> GE
2936     case 0x02: Imm = 0x00; break; // GT -> LT
2937     case 0x03: Imm = 0x01; break; // GE -> LE
2938     case 0x04: // EQ
2939     case 0x05: // NE
2940     case 0x06: // FALSE
2941     case 0x07: // TRUE
2942     default:
2943       break;
2944     }
2945     if (NewMI) {
2946       MachineFunction &MF = *MI->getParent()->getParent();
2947       MI = MF.CloneMachineInstr(MI);
2948       NewMI = false;
2949     }
2950     MI->getOperand(3).setImm(Imm);
2951     return TargetInstrInfo::commuteInstruction(MI, NewMI);
2952   }
2953   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
2954   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2955   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
2956   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2957   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2958   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
2959   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
2960   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2961   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2962   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
2963   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
2964   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2965   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
2966   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2967   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
2968   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2969     unsigned Opc;
2970     switch (MI->getOpcode()) {
2971     default: llvm_unreachable("Unreachable!");
2972     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2973     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2974     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2975     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2976     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2977     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2978     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2979     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2980     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2981     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2982     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2983     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2984     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2985     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2986     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2987     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2988     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2989     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2990     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2991     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2992     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2993     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2994     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2995     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2996     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2997     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2998     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2999     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
3000     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
3001     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
3002     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
3003     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
3004     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
3005     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3006     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3007     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3008     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
3009     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
3010     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
3011     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3012     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3013     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
3014     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
3015     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
3016     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
3017     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3018     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3019     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
3020     }
3021     if (NewMI) {
3022       MachineFunction &MF = *MI->getParent()->getParent();
3023       MI = MF.CloneMachineInstr(MI);
3024       NewMI = false;
3025     }
3026     MI->setDesc(get(Opc));
3027     // Fallthrough intended.
3028   }
3029   default:
3030     return TargetInstrInfo::commuteInstruction(MI, NewMI);
3031   }
3032 }
3033 
3034 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
3035                                          unsigned &SrcOpIdx2) const {
3036   switch (MI->getOpcode()) {
3037     case X86::CMPPDrri:
3038     case X86::CMPPSrri:
3039     case X86::VCMPPDrri:
3040     case X86::VCMPPSrri:
3041     case X86::VCMPPDYrri:
3042     case X86::VCMPPSYrri: {
3043       // Float comparison can be safely commuted for
3044       // Ordered/Unordered/Equal/NotEqual tests
3045       unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3046       switch (Imm) {
3047       case 0x00: // EQUAL
3048       case 0x03: // UNORDERED
3049       case 0x04: // NOT EQUAL
3050       case 0x07: // ORDERED
3051         SrcOpIdx1 = 1;
3052         SrcOpIdx2 = 2;
3053         return true;
3054       }
3055       return false;
3056     }
3057     case X86::VFMADDPDr231r:
3058     case X86::VFMADDPSr231r:
3059     case X86::VFMADDSDr231r:
3060     case X86::VFMADDSSr231r:
3061     case X86::VFMSUBPDr231r:
3062     case X86::VFMSUBPSr231r:
3063     case X86::VFMSUBSDr231r:
3064     case X86::VFMSUBSSr231r:
3065     case X86::VFNMADDPDr231r:
3066     case X86::VFNMADDPSr231r:
3067     case X86::VFNMADDSDr231r:
3068     case X86::VFNMADDSSr231r:
3069     case X86::VFNMSUBPDr231r:
3070     case X86::VFNMSUBPSr231r:
3071     case X86::VFNMSUBSDr231r:
3072     case X86::VFNMSUBSSr231r:
3073     case X86::VFMADDPDr231rY:
3074     case X86::VFMADDPSr231rY:
3075     case X86::VFMSUBPDr231rY:
3076     case X86::VFMSUBPSr231rY:
3077     case X86::VFNMADDPDr231rY:
3078     case X86::VFNMADDPSr231rY:
3079     case X86::VFNMSUBPDr231rY:
3080     case X86::VFNMSUBPSr231rY:
3081       SrcOpIdx1 = 2;
3082       SrcOpIdx2 = 3;
3083       return true;
3084     default:
3085       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3086   }
3087 }
3088 
3089 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
3090   switch (BrOpc) {
3091   default: return X86::COND_INVALID;
3092   case X86::JE_1:  return X86::COND_E;
3093   case X86::JNE_1: return X86::COND_NE;
3094   case X86::JL_1:  return X86::COND_L;
3095   case X86::JLE_1: return X86::COND_LE;
3096   case X86::JG_1:  return X86::COND_G;
3097   case X86::JGE_1: return X86::COND_GE;
3098   case X86::JB_1:  return X86::COND_B;
3099   case X86::JBE_1: return X86::COND_BE;
3100   case X86::JA_1:  return X86::COND_A;
3101   case X86::JAE_1: return X86::COND_AE;
3102   case X86::JS_1:  return X86::COND_S;
3103   case X86::JNS_1: return X86::COND_NS;
3104   case X86::JP_1:  return X86::COND_P;
3105   case X86::JNP_1: return X86::COND_NP;
3106   case X86::JO_1:  return X86::COND_O;
3107   case X86::JNO_1: return X86::COND_NO;
3108   }
3109 }
3110 
3111 /// Return condition code of a SET opcode.
3112 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3113   switch (Opc) {
3114   default: return X86::COND_INVALID;
3115   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
3116   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3117   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
3118   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3119   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
3120   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
3121   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3122   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
3123   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3124   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3125   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3126   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3127   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3128   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
3129   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
3130   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
3131   }
3132 }
3133 
3134 /// Return condition code of a CMov opcode.
3135 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
3136   switch (Opc) {
3137   default: return X86::COND_INVALID;
3138   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
3139   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
3140     return X86::COND_A;
3141   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3142   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3143     return X86::COND_AE;
3144   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
3145   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
3146     return X86::COND_B;
3147   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3148   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3149     return X86::COND_BE;
3150   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
3151   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
3152     return X86::COND_E;
3153   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
3154   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
3155     return X86::COND_G;
3156   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3157   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3158     return X86::COND_GE;
3159   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
3160   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
3161     return X86::COND_L;
3162   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3163   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3164     return X86::COND_LE;
3165   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3166   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3167     return X86::COND_NE;
3168   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3169   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3170     return X86::COND_NO;
3171   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3172   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3173     return X86::COND_NP;
3174   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3175   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3176     return X86::COND_NS;
3177   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
3178   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
3179     return X86::COND_O;
3180   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
3181   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
3182     return X86::COND_P;
3183   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
3184   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
3185     return X86::COND_S;
3186   }
3187 }
3188 
3189 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3190   switch (CC) {
3191   default: llvm_unreachable("Illegal condition code!");
3192   case X86::COND_E:  return X86::JE_1;
3193   case X86::COND_NE: return X86::JNE_1;
3194   case X86::COND_L:  return X86::JL_1;
3195   case X86::COND_LE: return X86::JLE_1;
3196   case X86::COND_G:  return X86::JG_1;
3197   case X86::COND_GE: return X86::JGE_1;
3198   case X86::COND_B:  return X86::JB_1;
3199   case X86::COND_BE: return X86::JBE_1;
3200   case X86::COND_A:  return X86::JA_1;
3201   case X86::COND_AE: return X86::JAE_1;
3202   case X86::COND_S:  return X86::JS_1;
3203   case X86::COND_NS: return X86::JNS_1;
3204   case X86::COND_P:  return X86::JP_1;
3205   case X86::COND_NP: return X86::JNP_1;
3206   case X86::COND_O:  return X86::JO_1;
3207   case X86::COND_NO: return X86::JNO_1;
3208   }
3209 }
3210 
3211 /// Return the inverse of the specified condition,
3212 /// e.g. turning COND_E to COND_NE.
3213 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3214   switch (CC) {
3215   default: llvm_unreachable("Illegal condition code!");
3216   case X86::COND_E:  return X86::COND_NE;
3217   case X86::COND_NE: return X86::COND_E;
3218   case X86::COND_L:  return X86::COND_GE;
3219   case X86::COND_LE: return X86::COND_G;
3220   case X86::COND_G:  return X86::COND_LE;
3221   case X86::COND_GE: return X86::COND_L;
3222   case X86::COND_B:  return X86::COND_AE;
3223   case X86::COND_BE: return X86::COND_A;
3224   case X86::COND_A:  return X86::COND_BE;
3225   case X86::COND_AE: return X86::COND_B;
3226   case X86::COND_S:  return X86::COND_NS;
3227   case X86::COND_NS: return X86::COND_S;
3228   case X86::COND_P:  return X86::COND_NP;
3229   case X86::COND_NP: return X86::COND_P;
3230   case X86::COND_O:  return X86::COND_NO;
3231   case X86::COND_NO: return X86::COND_O;
3232   }
3233 }
3234 
3235 /// Assuming the flags are set by MI(a,b), return the condition code if we
3236 /// modify the instructions such that flags are set by MI(b,a).
3237 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
3238   switch (CC) {
3239   default: return X86::COND_INVALID;
3240   case X86::COND_E:  return X86::COND_E;
3241   case X86::COND_NE: return X86::COND_NE;
3242   case X86::COND_L:  return X86::COND_G;
3243   case X86::COND_LE: return X86::COND_GE;
3244   case X86::COND_G:  return X86::COND_L;
3245   case X86::COND_GE: return X86::COND_LE;
3246   case X86::COND_B:  return X86::COND_A;
3247   case X86::COND_BE: return X86::COND_AE;
3248   case X86::COND_A:  return X86::COND_B;
3249   case X86::COND_AE: return X86::COND_BE;
3250   }
3251 }
3252 
3253 /// Return a set opcode for the given condition and
3254 /// whether it has memory operand.
3255 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
3256   static const uint16_t Opc[16][2] = {
3257     { X86::SETAr,  X86::SETAm  },
3258     { X86::SETAEr, X86::SETAEm },
3259     { X86::SETBr,  X86::SETBm  },
3260     { X86::SETBEr, X86::SETBEm },
3261     { X86::SETEr,  X86::SETEm  },
3262     { X86::SETGr,  X86::SETGm  },
3263     { X86::SETGEr, X86::SETGEm },
3264     { X86::SETLr,  X86::SETLm  },
3265     { X86::SETLEr, X86::SETLEm },
3266     { X86::SETNEr, X86::SETNEm },
3267     { X86::SETNOr, X86::SETNOm },
3268     { X86::SETNPr, X86::SETNPm },
3269     { X86::SETNSr, X86::SETNSm },
3270     { X86::SETOr,  X86::SETOm  },
3271     { X86::SETPr,  X86::SETPm  },
3272     { X86::SETSr,  X86::SETSm  }
3273   };
3274 
3275   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
3276   return Opc[CC][HasMemoryOperand ? 1 : 0];
3277 }
3278 
3279 /// Return a cmov opcode for the given condition,
3280 /// register size in bytes, and operand type.
3281 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3282                               bool HasMemoryOperand) {
3283   static const uint16_t Opc[32][3] = {
3284     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
3285     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3286     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
3287     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3288     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
3289     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
3290     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3291     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
3292     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3293     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3294     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3295     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3296     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3297     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
3298     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
3299     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
3300     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
3301     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3302     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
3303     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3304     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
3305     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
3306     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3307     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
3308     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3309     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3310     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3311     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3312     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3313     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
3314     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
3315     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
3316   };
3317 
3318   assert(CC < 16 && "Can only handle standard cond codes");
3319   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
3320   switch(RegBytes) {
3321   default: llvm_unreachable("Illegal register size!");
3322   case 2: return Opc[Idx][0];
3323   case 4: return Opc[Idx][1];
3324   case 8: return Opc[Idx][2];
3325   }
3326 }
3327 
3328 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
3329   if (!MI->isTerminator()) return false;
3330 
3331   // Conditional branch is a special case.
3332   if (MI->isBranch() && !MI->isBarrier())
3333     return true;
3334   if (!MI->isPredicable())
3335     return true;
3336   return !isPredicated(MI);
3337 }
3338 
3339 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
3340                                  MachineBasicBlock *&TBB,
3341                                  MachineBasicBlock *&FBB,
3342                                  SmallVectorImpl<MachineOperand> &Cond,
3343                                  bool AllowModify) const {
3344   // Start from the bottom of the block and work up, examining the
3345   // terminator instructions.
3346   MachineBasicBlock::iterator I = MBB.end();
3347   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
3348   while (I != MBB.begin()) {
3349     --I;
3350     if (I->isDebugValue())
3351       continue;
3352 
3353     // Working from the bottom, when we see a non-terminator instruction, we're
3354     // done.
3355     if (!isUnpredicatedTerminator(I))
3356       break;
3357 
3358     // A terminator that isn't a branch can't easily be handled by this
3359     // analysis.
3360     if (!I->isBranch())
3361       return true;
3362 
3363     // Handle unconditional branches.
3364     if (I->getOpcode() == X86::JMP_1) {
3365       UnCondBrIter = I;
3366 
3367       if (!AllowModify) {
3368         TBB = I->getOperand(0).getMBB();
3369         continue;
3370       }
3371 
3372       // If the block has any instructions after a JMP, delete them.
3373       while (std::next(I) != MBB.end())
3374         std::next(I)->eraseFromParent();
3375 
3376       Cond.clear();
3377       FBB = nullptr;
3378 
3379       // Delete the JMP if it's equivalent to a fall-through.
3380       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
3381         TBB = nullptr;
3382         I->eraseFromParent();
3383         I = MBB.end();
3384         UnCondBrIter = MBB.end();
3385         continue;
3386       }
3387 
3388       // TBB is used to indicate the unconditional destination.
3389       TBB = I->getOperand(0).getMBB();
3390       continue;
3391     }
3392 
3393     // Handle conditional branches.
3394     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
3395     if (BranchCode == X86::COND_INVALID)
3396       return true;  // Can't handle indirect branch.
3397 
3398     // Working from the bottom, handle the first conditional branch.
3399     if (Cond.empty()) {
3400       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3401       if (AllowModify && UnCondBrIter != MBB.end() &&
3402           MBB.isLayoutSuccessor(TargetBB)) {
3403         // If we can modify the code and it ends in something like:
3404         //
3405         //     jCC L1
3406         //     jmp L2
3407         //   L1:
3408         //     ...
3409         //   L2:
3410         //
3411         // Then we can change this to:
3412         //
3413         //     jnCC L2
3414         //   L1:
3415         //     ...
3416         //   L2:
3417         //
3418         // Which is a bit more efficient.
3419         // We conditionally jump to the fall-through block.
3420         BranchCode = GetOppositeBranchCondition(BranchCode);
3421         unsigned JNCC = GetCondBranchFromCond(BranchCode);
3422         MachineBasicBlock::iterator OldInst = I;
3423 
3424         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3425           .addMBB(UnCondBrIter->getOperand(0).getMBB());
3426         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
3427           .addMBB(TargetBB);
3428 
3429         OldInst->eraseFromParent();
3430         UnCondBrIter->eraseFromParent();
3431 
3432         // Restart the analysis.
3433         UnCondBrIter = MBB.end();
3434         I = MBB.end();
3435         continue;
3436       }
3437 
3438       FBB = TBB;
3439       TBB = I->getOperand(0).getMBB();
3440       Cond.push_back(MachineOperand::CreateImm(BranchCode));
3441       continue;
3442     }
3443 
3444     // Handle subsequent conditional branches. Only handle the case where all
3445     // conditional branches branch to the same destination and their condition
3446     // opcodes fit one of the special multi-branch idioms.
3447     assert(Cond.size() == 1);
3448     assert(TBB);
3449 
3450     // Only handle the case where all conditional branches branch to the same
3451     // destination.
3452     if (TBB != I->getOperand(0).getMBB())
3453       return true;
3454 
3455     // If the conditions are the same, we can leave them alone.
3456     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
3457     if (OldBranchCode == BranchCode)
3458       continue;
3459 
3460     // If they differ, see if they fit one of the known patterns. Theoretically,
3461     // we could handle more patterns here, but we shouldn't expect to see them
3462     // if instruction selection has done a reasonable job.
3463     if ((OldBranchCode == X86::COND_NP &&
3464          BranchCode == X86::COND_E) ||
3465         (OldBranchCode == X86::COND_E &&
3466          BranchCode == X86::COND_NP))
3467       BranchCode = X86::COND_NP_OR_E;
3468     else if ((OldBranchCode == X86::COND_P &&
3469               BranchCode == X86::COND_NE) ||
3470              (OldBranchCode == X86::COND_NE &&
3471               BranchCode == X86::COND_P))
3472       BranchCode = X86::COND_NE_OR_P;
3473     else
3474       return true;
3475 
3476     // Update the MachineOperand.
3477     Cond[0].setImm(BranchCode);
3478   }
3479 
3480   return false;
3481 }
3482 
3483 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
3484   MachineBasicBlock::iterator I = MBB.end();
3485   unsigned Count = 0;
3486 
3487   while (I != MBB.begin()) {
3488     --I;
3489     if (I->isDebugValue())
3490       continue;
3491     if (I->getOpcode() != X86::JMP_1 &&
3492         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
3493       break;
3494     // Remove the branch.
3495     I->eraseFromParent();
3496     I = MBB.end();
3497     ++Count;
3498   }
3499 
3500   return Count;
3501 }
3502 
3503 unsigned
3504 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
3505                            MachineBasicBlock *FBB,
3506                            const SmallVectorImpl<MachineOperand> &Cond,
3507                            DebugLoc DL) const {
3508   // Shouldn't be a fall through.
3509   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
3510   assert((Cond.size() == 1 || Cond.size() == 0) &&
3511          "X86 branch conditions have one component!");
3512 
3513   if (Cond.empty()) {
3514     // Unconditional branch?
3515     assert(!FBB && "Unconditional branch with multiple successors!");
3516     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
3517     return 1;
3518   }
3519 
3520   // Conditional branch.
3521   unsigned Count = 0;
3522   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3523   switch (CC) {
3524   case X86::COND_NP_OR_E:
3525     // Synthesize NP_OR_E with two branches.
3526     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
3527     ++Count;
3528     BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
3529     ++Count;
3530     break;
3531   case X86::COND_NE_OR_P:
3532     // Synthesize NE_OR_P with two branches.
3533     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
3534     ++Count;
3535     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
3536     ++Count;
3537     break;
3538   default: {
3539     unsigned Opc = GetCondBranchFromCond(CC);
3540     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
3541     ++Count;
3542   }
3543   }
3544   if (FBB) {
3545     // Two-way Conditional branch. Insert the second branch.
3546     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
3547     ++Count;
3548   }
3549   return Count;
3550 }
3551 
3552 bool X86InstrInfo::
3553 canInsertSelect(const MachineBasicBlock &MBB,
3554                 const SmallVectorImpl<MachineOperand> &Cond,
3555                 unsigned TrueReg, unsigned FalseReg,
3556                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3557   // Not all subtargets have cmov instructions.
3558   if (!Subtarget.hasCMov())
3559     return false;
3560   if (Cond.size() != 1)
3561     return false;
3562   // We cannot do the composite conditions, at least not in SSA form.
3563   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3564     return false;
3565 
3566   // Check register classes.
3567   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3568   const TargetRegisterClass *RC =
3569     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3570   if (!RC)
3571     return false;
3572 
3573   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3574   if (X86::GR16RegClass.hasSubClassEq(RC) ||
3575       X86::GR32RegClass.hasSubClassEq(RC) ||
3576       X86::GR64RegClass.hasSubClassEq(RC)) {
3577     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3578     // Bridge. Probably Ivy Bridge as well.
3579     CondCycles = 2;
3580     TrueCycles = 2;
3581     FalseCycles = 2;
3582     return true;
3583   }
3584 
3585   // Can't do vectors.
3586   return false;
3587 }
3588 
3589 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3590                                 MachineBasicBlock::iterator I, DebugLoc DL,
3591                                 unsigned DstReg,
3592                                 const SmallVectorImpl<MachineOperand> &Cond,
3593                                 unsigned TrueReg, unsigned FalseReg) const {
3594    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3595    assert(Cond.size() == 1 && "Invalid Cond array");
3596    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
3597                                   MRI.getRegClass(DstReg)->getSize(),
3598                                   false/*HasMemoryOperand*/);
3599    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3600 }
3601 
3602 /// Test if the given register is a physical h register.
3603 static bool isHReg(unsigned Reg) {
3604   return X86::GR8_ABCD_HRegClass.contains(Reg);
3605 }
3606 
3607 // Try and copy between VR128/VR64 and GR64 registers.
3608 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
3609                                         const X86Subtarget &Subtarget) {
3610 
3611   // SrcReg(VR128) -> DestReg(GR64)
3612   // SrcReg(VR64)  -> DestReg(GR64)
3613   // SrcReg(GR64)  -> DestReg(VR128)
3614   // SrcReg(GR64)  -> DestReg(VR64)
3615 
3616   bool HasAVX = Subtarget.hasAVX();
3617   bool HasAVX512 = Subtarget.hasAVX512();
3618   if (X86::GR64RegClass.contains(DestReg)) {
3619     if (X86::VR128XRegClass.contains(SrcReg))
3620       // Copy from a VR128 register to a GR64 register.
3621       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3622                                                X86::MOVPQIto64rr);
3623     if (X86::VR64RegClass.contains(SrcReg))
3624       // Copy from a VR64 register to a GR64 register.
3625       return X86::MOVSDto64rr;
3626   } else if (X86::GR64RegClass.contains(SrcReg)) {
3627     // Copy from a GR64 register to a VR128 register.
3628     if (X86::VR128XRegClass.contains(DestReg))
3629       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3630                                                X86::MOV64toPQIrr);
3631     // Copy from a GR64 register to a VR64 register.
3632     if (X86::VR64RegClass.contains(DestReg))
3633       return X86::MOV64toSDrr;
3634   }
3635 
3636   // SrcReg(FR32) -> DestReg(GR32)
3637   // SrcReg(GR32) -> DestReg(FR32)
3638 
3639   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
3640     // Copy from a FR32 register to a GR32 register.
3641     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
3642 
3643   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
3644     // Copy from a GR32 register to a FR32 register.
3645     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
3646   return 0;
3647 }
3648 
3649 inline static bool MaskRegClassContains(unsigned Reg) {
3650   return X86::VK8RegClass.contains(Reg) ||
3651          X86::VK16RegClass.contains(Reg) ||
3652          X86::VK32RegClass.contains(Reg) ||
3653          X86::VK64RegClass.contains(Reg) ||
3654          X86::VK1RegClass.contains(Reg);
3655 }
3656 static
3657 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3658   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3659       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3660       X86::VR512RegClass.contains(DestReg, SrcReg)) {
3661      DestReg = get512BitSuperRegister(DestReg);
3662      SrcReg = get512BitSuperRegister(SrcReg);
3663      return X86::VMOVAPSZrr;
3664   }
3665   if (MaskRegClassContains(DestReg) &&
3666       MaskRegClassContains(SrcReg))
3667     return X86::KMOVWkk;
3668   if (MaskRegClassContains(DestReg) &&
3669       (X86::GR32RegClass.contains(SrcReg) ||
3670        X86::GR16RegClass.contains(SrcReg) ||
3671        X86::GR8RegClass.contains(SrcReg))) {
3672     SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3673     return X86::KMOVWkr;
3674   }
3675   if ((X86::GR32RegClass.contains(DestReg) ||
3676        X86::GR16RegClass.contains(DestReg) ||
3677        X86::GR8RegClass.contains(DestReg)) &&
3678        MaskRegClassContains(SrcReg)) {
3679     DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3680     return X86::KMOVWrk;
3681   }
3682   return 0;
3683 }
3684 
3685 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3686                                MachineBasicBlock::iterator MI, DebugLoc DL,
3687                                unsigned DestReg, unsigned SrcReg,
3688                                bool KillSrc) const {
3689   // First deal with the normal symmetric copies.
3690   bool HasAVX = Subtarget.hasAVX();
3691   bool HasAVX512 = Subtarget.hasAVX512();
3692   unsigned Opc = 0;
3693   if (X86::GR64RegClass.contains(DestReg, SrcReg))
3694     Opc = X86::MOV64rr;
3695   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3696     Opc = X86::MOV32rr;
3697   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3698     Opc = X86::MOV16rr;
3699   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3700     // Copying to or from a physical H register on x86-64 requires a NOREX
3701     // move.  Otherwise use a normal move.
3702     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
3703         Subtarget.is64Bit()) {
3704       Opc = X86::MOV8rr_NOREX;
3705       // Both operands must be encodable without an REX prefix.
3706       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3707              "8-bit H register can not be copied outside GR8_NOREX");
3708     } else
3709       Opc = X86::MOV8rr;
3710   }
3711   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3712     Opc = X86::MMX_MOVQ64rr;
3713   else if (HasAVX512)
3714     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3715   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
3716     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
3717   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3718     Opc = X86::VMOVAPSYrr;
3719   if (!Opc)
3720     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
3721 
3722   if (Opc) {
3723     BuildMI(MBB, MI, DL, get(Opc), DestReg)
3724       .addReg(SrcReg, getKillRegState(KillSrc));
3725     return;
3726   }
3727 
3728   // Moving EFLAGS to / from another register requires a push and a pop.
3729   // Notice that we have to adjust the stack if we don't want to clobber the
3730   // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
3731   if (SrcReg == X86::EFLAGS) {
3732     if (X86::GR64RegClass.contains(DestReg)) {
3733       BuildMI(MBB, MI, DL, get(X86::PUSHF64));
3734       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
3735       return;
3736     }
3737     if (X86::GR32RegClass.contains(DestReg)) {
3738       BuildMI(MBB, MI, DL, get(X86::PUSHF32));
3739       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
3740       return;
3741     }
3742   }
3743   if (DestReg == X86::EFLAGS) {
3744     if (X86::GR64RegClass.contains(SrcReg)) {
3745       BuildMI(MBB, MI, DL, get(X86::PUSH64r))
3746         .addReg(SrcReg, getKillRegState(KillSrc));
3747       BuildMI(MBB, MI, DL, get(X86::POPF64));
3748       return;
3749     }
3750     if (X86::GR32RegClass.contains(SrcReg)) {
3751       BuildMI(MBB, MI, DL, get(X86::PUSH32r))
3752         .addReg(SrcReg, getKillRegState(KillSrc));
3753       BuildMI(MBB, MI, DL, get(X86::POPF32));
3754       return;
3755     }
3756   }
3757 
3758   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3759                << " to " << RI.getName(DestReg) << '\n');
3760   llvm_unreachable("Cannot emit physreg copy instruction");
3761 }
3762 
3763 static unsigned getLoadStoreRegOpcode(unsigned Reg,
3764                                       const TargetRegisterClass *RC,
3765                                       bool isStackAligned,
3766                                       const X86Subtarget &STI,
3767                                       bool load) {
3768   if (STI.hasAVX512()) {
3769     if (X86::VK8RegClass.hasSubClassEq(RC)  ||
3770       X86::VK16RegClass.hasSubClassEq(RC))
3771       return load ? X86::KMOVWkm : X86::KMOVWmk;
3772     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
3773       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
3774     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
3775       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
3776     if (X86::VR512RegClass.hasSubClassEq(RC))
3777       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3778   }
3779 
3780   bool HasAVX = STI.hasAVX();
3781   switch (RC->getSize()) {
3782   default:
3783     llvm_unreachable("Unknown spill size");
3784   case 1:
3785     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
3786     if (STI.is64Bit())
3787       // Copying to or from a physical H register on x86-64 requires a NOREX
3788       // move.  Otherwise use a normal move.
3789       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3790         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3791     return load ? X86::MOV8rm : X86::MOV8mr;
3792   case 2:
3793     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3794     return load ? X86::MOV16rm : X86::MOV16mr;
3795   case 4:
3796     if (X86::GR32RegClass.hasSubClassEq(RC))
3797       return load ? X86::MOV32rm : X86::MOV32mr;
3798     if (X86::FR32RegClass.hasSubClassEq(RC))
3799       return load ?
3800         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
3801         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
3802     if (X86::RFP32RegClass.hasSubClassEq(RC))
3803       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
3804     llvm_unreachable("Unknown 4-byte regclass");
3805   case 8:
3806     if (X86::GR64RegClass.hasSubClassEq(RC))
3807       return load ? X86::MOV64rm : X86::MOV64mr;
3808     if (X86::FR64RegClass.hasSubClassEq(RC))
3809       return load ?
3810         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
3811         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
3812     if (X86::VR64RegClass.hasSubClassEq(RC))
3813       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
3814     if (X86::RFP64RegClass.hasSubClassEq(RC))
3815       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
3816     llvm_unreachable("Unknown 8-byte regclass");
3817   case 10:
3818     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
3819     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
3820   case 16: {
3821     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
3822             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
3823     // If stack is realigned we can use aligned stores.
3824     if (isStackAligned)
3825       return load ?
3826         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
3827         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
3828     else
3829       return load ?
3830         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
3831         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
3832   }
3833   case 32:
3834     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
3835             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
3836     // If stack is realigned we can use aligned stores.
3837     if (isStackAligned)
3838       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
3839     else
3840       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3841   case 64:
3842     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
3843     if (isStackAligned)
3844       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
3845     else
3846       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3847   }
3848 }
3849 
3850 static unsigned getStoreRegOpcode(unsigned SrcReg,
3851                                   const TargetRegisterClass *RC,
3852                                   bool isStackAligned,
3853                                   const X86Subtarget &STI) {
3854   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
3855 }
3856 
3857 
3858 static unsigned getLoadRegOpcode(unsigned DestReg,
3859                                  const TargetRegisterClass *RC,
3860                                  bool isStackAligned,
3861                                  const X86Subtarget &STI) {
3862   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
3863 }
3864 
3865 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3866                                        MachineBasicBlock::iterator MI,
3867                                        unsigned SrcReg, bool isKill, int FrameIdx,
3868                                        const TargetRegisterClass *RC,
3869                                        const TargetRegisterInfo *TRI) const {
3870   const MachineFunction &MF = *MBB.getParent();
3871   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3872          "Stack slot too small for store");
3873   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3874   bool isAligned =
3875       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3876       RI.canRealignStack(MF);
3877   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3878   DebugLoc DL = MBB.findDebugLoc(MI);
3879   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3880     .addReg(SrcReg, getKillRegState(isKill));
3881 }
3882 
3883 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3884                                   bool isKill,
3885                                   SmallVectorImpl<MachineOperand> &Addr,
3886                                   const TargetRegisterClass *RC,
3887                                   MachineInstr::mmo_iterator MMOBegin,
3888                                   MachineInstr::mmo_iterator MMOEnd,
3889                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
3890   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3891   bool isAligned = MMOBegin != MMOEnd &&
3892                    (*MMOBegin)->getAlignment() >= Alignment;
3893   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
3894   DebugLoc DL;
3895   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3896   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3897     MIB.addOperand(Addr[i]);
3898   MIB.addReg(SrcReg, getKillRegState(isKill));
3899   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3900   NewMIs.push_back(MIB);
3901 }
3902 
3903 
3904 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3905                                         MachineBasicBlock::iterator MI,
3906                                         unsigned DestReg, int FrameIdx,
3907                                         const TargetRegisterClass *RC,
3908                                         const TargetRegisterInfo *TRI) const {
3909   const MachineFunction &MF = *MBB.getParent();
3910   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3911   bool isAligned =
3912       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
3913       RI.canRealignStack(MF);
3914   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3915   DebugLoc DL = MBB.findDebugLoc(MI);
3916   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
3917 }
3918 
3919 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
3920                                  SmallVectorImpl<MachineOperand> &Addr,
3921                                  const TargetRegisterClass *RC,
3922                                  MachineInstr::mmo_iterator MMOBegin,
3923                                  MachineInstr::mmo_iterator MMOEnd,
3924                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
3925   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
3926   bool isAligned = MMOBegin != MMOEnd &&
3927                    (*MMOBegin)->getAlignment() >= Alignment;
3928   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
3929   DebugLoc DL;
3930   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3931   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3932     MIB.addOperand(Addr[i]);
3933   (*MIB).setMemRefs(MMOBegin, MMOEnd);
3934   NewMIs.push_back(MIB);
3935 }
3936 
3937 bool X86InstrInfo::
3938 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3939                int &CmpMask, int &CmpValue) const {
3940   switch (MI->getOpcode()) {
3941   default: break;
3942   case X86::CMP64ri32:
3943   case X86::CMP64ri8:
3944   case X86::CMP32ri:
3945   case X86::CMP32ri8:
3946   case X86::CMP16ri:
3947   case X86::CMP16ri8:
3948   case X86::CMP8ri:
3949     SrcReg = MI->getOperand(0).getReg();
3950     SrcReg2 = 0;
3951     CmpMask = ~0;
3952     CmpValue = MI->getOperand(1).getImm();
3953     return true;
3954   // A SUB can be used to perform comparison.
3955   case X86::SUB64rm:
3956   case X86::SUB32rm:
3957   case X86::SUB16rm:
3958   case X86::SUB8rm:
3959     SrcReg = MI->getOperand(1).getReg();
3960     SrcReg2 = 0;
3961     CmpMask = ~0;
3962     CmpValue = 0;
3963     return true;
3964   case X86::SUB64rr:
3965   case X86::SUB32rr:
3966   case X86::SUB16rr:
3967   case X86::SUB8rr:
3968     SrcReg = MI->getOperand(1).getReg();
3969     SrcReg2 = MI->getOperand(2).getReg();
3970     CmpMask = ~0;
3971     CmpValue = 0;
3972     return true;
3973   case X86::SUB64ri32:
3974   case X86::SUB64ri8:
3975   case X86::SUB32ri:
3976   case X86::SUB32ri8:
3977   case X86::SUB16ri:
3978   case X86::SUB16ri8:
3979   case X86::SUB8ri:
3980     SrcReg = MI->getOperand(1).getReg();
3981     SrcReg2 = 0;
3982     CmpMask = ~0;
3983     CmpValue = MI->getOperand(2).getImm();
3984     return true;
3985   case X86::CMP64rr:
3986   case X86::CMP32rr:
3987   case X86::CMP16rr:
3988   case X86::CMP8rr:
3989     SrcReg = MI->getOperand(0).getReg();
3990     SrcReg2 = MI->getOperand(1).getReg();
3991     CmpMask = ~0;
3992     CmpValue = 0;
3993     return true;
3994   case X86::TEST8rr:
3995   case X86::TEST16rr:
3996   case X86::TEST32rr:
3997   case X86::TEST64rr:
3998     SrcReg = MI->getOperand(0).getReg();
3999     if (MI->getOperand(1).getReg() != SrcReg) return false;
4000     // Compare against zero.
4001     SrcReg2 = 0;
4002     CmpMask = ~0;
4003     CmpValue = 0;
4004     return true;
4005   }
4006   return false;
4007 }
4008 
4009 /// Check whether the first instruction, whose only
4010 /// purpose is to update flags, can be made redundant.
4011 /// CMPrr can be made redundant by SUBrr if the operands are the same.
4012 /// This function can be extended later on.
4013 /// SrcReg, SrcRegs: register operands for FlagI.
4014 /// ImmValue: immediate for FlagI if it takes an immediate.
4015 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4016                                         unsigned SrcReg2, int ImmValue,
4017                                         MachineInstr *OI) {
4018   if (((FlagI->getOpcode() == X86::CMP64rr &&
4019         OI->getOpcode() == X86::SUB64rr) ||
4020        (FlagI->getOpcode() == X86::CMP32rr &&
4021         OI->getOpcode() == X86::SUB32rr)||
4022        (FlagI->getOpcode() == X86::CMP16rr &&
4023         OI->getOpcode() == X86::SUB16rr)||
4024        (FlagI->getOpcode() == X86::CMP8rr &&
4025         OI->getOpcode() == X86::SUB8rr)) &&
4026       ((OI->getOperand(1).getReg() == SrcReg &&
4027         OI->getOperand(2).getReg() == SrcReg2) ||
4028        (OI->getOperand(1).getReg() == SrcReg2 &&
4029         OI->getOperand(2).getReg() == SrcReg)))
4030     return true;
4031 
4032   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4033         OI->getOpcode() == X86::SUB64ri32) ||
4034        (FlagI->getOpcode() == X86::CMP64ri8 &&
4035         OI->getOpcode() == X86::SUB64ri8) ||
4036        (FlagI->getOpcode() == X86::CMP32ri &&
4037         OI->getOpcode() == X86::SUB32ri) ||
4038        (FlagI->getOpcode() == X86::CMP32ri8 &&
4039         OI->getOpcode() == X86::SUB32ri8) ||
4040        (FlagI->getOpcode() == X86::CMP16ri &&
4041         OI->getOpcode() == X86::SUB16ri) ||
4042        (FlagI->getOpcode() == X86::CMP16ri8 &&
4043         OI->getOpcode() == X86::SUB16ri8) ||
4044        (FlagI->getOpcode() == X86::CMP8ri &&
4045         OI->getOpcode() == X86::SUB8ri)) &&
4046       OI->getOperand(1).getReg() == SrcReg &&
4047       OI->getOperand(2).getImm() == ImmValue)
4048     return true;
4049   return false;
4050 }
4051 
4052 /// Check whether the definition can be converted
4053 /// to remove a comparison against zero.
4054 inline static bool isDefConvertible(MachineInstr *MI) {
4055   switch (MI->getOpcode()) {
4056   default: return false;
4057 
4058   // The shift instructions only modify ZF if their shift count is non-zero.
4059   // N.B.: The processor truncates the shift count depending on the encoding.
4060   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
4061   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
4062      return getTruncatedShiftCount(MI, 2) != 0;
4063 
4064   // Some left shift instructions can be turned into LEA instructions but only
4065   // if their flags aren't used. Avoid transforming such instructions.
4066   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
4067     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4068     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4069     return ShAmt != 0;
4070   }
4071 
4072   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4073   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4074      return getTruncatedShiftCount(MI, 3) != 0;
4075 
4076   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4077   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
4078   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
4079   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
4080   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
4081   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
4082   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4083   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
4084   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
4085   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
4086   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
4087   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
4088   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4089   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
4090   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
4091   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
4092   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
4093   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4094   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
4095   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
4096   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
4097   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
4098   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
4099   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
4100   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
4101   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
4102   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
4103   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
4104   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
4105   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
4106   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
4107   case X86::ADC32ri:   case X86::ADC32ri8:
4108   case X86::ADC32rr:   case X86::ADC64ri32:
4109   case X86::ADC64ri8:  case X86::ADC64rr:
4110   case X86::SBB32ri:   case X86::SBB32ri8:
4111   case X86::SBB32rr:   case X86::SBB64ri32:
4112   case X86::SBB64ri8:  case X86::SBB64rr:
4113   case X86::ANDN32rr:  case X86::ANDN32rm:
4114   case X86::ANDN64rr:  case X86::ANDN64rm:
4115   case X86::BEXTR32rr: case X86::BEXTR64rr:
4116   case X86::BEXTR32rm: case X86::BEXTR64rm:
4117   case X86::BLSI32rr:  case X86::BLSI32rm:
4118   case X86::BLSI64rr:  case X86::BLSI64rm:
4119   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4120   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4121   case X86::BLSR32rr:  case X86::BLSR32rm:
4122   case X86::BLSR64rr:  case X86::BLSR64rm:
4123   case X86::BZHI32rr:  case X86::BZHI32rm:
4124   case X86::BZHI64rr:  case X86::BZHI64rm:
4125   case X86::LZCNT16rr: case X86::LZCNT16rm:
4126   case X86::LZCNT32rr: case X86::LZCNT32rm:
4127   case X86::LZCNT64rr: case X86::LZCNT64rm:
4128   case X86::POPCNT16rr:case X86::POPCNT16rm:
4129   case X86::POPCNT32rr:case X86::POPCNT32rm:
4130   case X86::POPCNT64rr:case X86::POPCNT64rm:
4131   case X86::TZCNT16rr: case X86::TZCNT16rm:
4132   case X86::TZCNT32rr: case X86::TZCNT32rm:
4133   case X86::TZCNT64rr: case X86::TZCNT64rm:
4134     return true;
4135   }
4136 }
4137 
4138 /// Check whether the use can be converted to remove a comparison against zero.
4139 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
4140   switch (MI->getOpcode()) {
4141   default: return X86::COND_INVALID;
4142   case X86::LZCNT16rr: case X86::LZCNT16rm:
4143   case X86::LZCNT32rr: case X86::LZCNT32rm:
4144   case X86::LZCNT64rr: case X86::LZCNT64rm:
4145     return X86::COND_B;
4146   case X86::POPCNT16rr:case X86::POPCNT16rm:
4147   case X86::POPCNT32rr:case X86::POPCNT32rm:
4148   case X86::POPCNT64rr:case X86::POPCNT64rm:
4149     return X86::COND_E;
4150   case X86::TZCNT16rr: case X86::TZCNT16rm:
4151   case X86::TZCNT32rr: case X86::TZCNT32rm:
4152   case X86::TZCNT64rr: case X86::TZCNT64rm:
4153     return X86::COND_B;
4154   }
4155 }
4156 
4157 /// Check if there exists an earlier instruction that
4158 /// operates on the same source operands and sets flags in the same way as
4159 /// Compare; remove Compare if possible.
4160 bool X86InstrInfo::
4161 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
4162                      int CmpMask, int CmpValue,
4163                      const MachineRegisterInfo *MRI) const {
4164   // Check whether we can replace SUB with CMP.
4165   unsigned NewOpcode = 0;
4166   switch (CmpInstr->getOpcode()) {
4167   default: break;
4168   case X86::SUB64ri32:
4169   case X86::SUB64ri8:
4170   case X86::SUB32ri:
4171   case X86::SUB32ri8:
4172   case X86::SUB16ri:
4173   case X86::SUB16ri8:
4174   case X86::SUB8ri:
4175   case X86::SUB64rm:
4176   case X86::SUB32rm:
4177   case X86::SUB16rm:
4178   case X86::SUB8rm:
4179   case X86::SUB64rr:
4180   case X86::SUB32rr:
4181   case X86::SUB16rr:
4182   case X86::SUB8rr: {
4183     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
4184       return false;
4185     // There is no use of the destination register, we can replace SUB with CMP.
4186     switch (CmpInstr->getOpcode()) {
4187     default: llvm_unreachable("Unreachable!");
4188     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
4189     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
4190     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
4191     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
4192     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
4193     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
4194     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
4195     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
4196     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4197     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
4198     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
4199     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
4200     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
4201     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
4202     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
4203     }
4204     CmpInstr->setDesc(get(NewOpcode));
4205     CmpInstr->RemoveOperand(0);
4206     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4207     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4208         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4209       return false;
4210   }
4211   }
4212 
4213   // Get the unique definition of SrcReg.
4214   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4215   if (!MI) return false;
4216 
4217   // CmpInstr is the first instruction of the BB.
4218   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4219 
4220   // If we are comparing against zero, check whether we can use MI to update
4221   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4222   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
4223   if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
4224     return false;
4225 
4226   // If we have a use of the source register between the def and our compare
4227   // instruction we can eliminate the compare iff the use sets EFLAGS in the
4228   // right way.
4229   bool ShouldUpdateCC = false;
4230   X86::CondCode NewCC = X86::COND_INVALID;
4231   if (IsCmpZero && !isDefConvertible(MI)) {
4232     // Scan forward from the use until we hit the use we're looking for or the
4233     // compare instruction.
4234     for (MachineBasicBlock::iterator J = MI;; ++J) {
4235       // Do we have a convertible instruction?
4236       NewCC = isUseDefConvertible(J);
4237       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4238           J->getOperand(1).getReg() == SrcReg) {
4239         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4240         ShouldUpdateCC = true; // Update CC later on.
4241         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4242         // with the new def.
4243         MI = Def = J;
4244         break;
4245       }
4246 
4247       if (J == I)
4248         return false;
4249     }
4250   }
4251 
4252   // We are searching for an earlier instruction that can make CmpInstr
4253   // redundant and that instruction will be saved in Sub.
4254   MachineInstr *Sub = nullptr;
4255   const TargetRegisterInfo *TRI = &getRegisterInfo();
4256 
4257   // We iterate backward, starting from the instruction before CmpInstr and
4258   // stop when reaching the definition of a source register or done with the BB.
4259   // RI points to the instruction before CmpInstr.
4260   // If the definition is in this basic block, RE points to the definition;
4261   // otherwise, RE is the rend of the basic block.
4262   MachineBasicBlock::reverse_iterator
4263       RI = MachineBasicBlock::reverse_iterator(I),
4264       RE = CmpInstr->getParent() == MI->getParent() ?
4265            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
4266            CmpInstr->getParent()->rend();
4267   MachineInstr *Movr0Inst = nullptr;
4268   for (; RI != RE; ++RI) {
4269     MachineInstr *Instr = &*RI;
4270     // Check whether CmpInstr can be made redundant by the current instruction.
4271     if (!IsCmpZero &&
4272         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
4273       Sub = Instr;
4274       break;
4275     }
4276 
4277     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
4278         Instr->readsRegister(X86::EFLAGS, TRI)) {
4279       // This instruction modifies or uses EFLAGS.
4280 
4281       // MOV32r0 etc. are implemented with xor which clobbers condition code.
4282       // They are safe to move up, if the definition to EFLAGS is dead and
4283       // earlier instructions do not read or write EFLAGS.
4284       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
4285           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
4286         Movr0Inst = Instr;
4287         continue;
4288       }
4289 
4290       // We can't remove CmpInstr.
4291       return false;
4292     }
4293   }
4294 
4295   // Return false if no candidates exist.
4296   if (!IsCmpZero && !Sub)
4297     return false;
4298 
4299   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
4300                     Sub->getOperand(2).getReg() == SrcReg);
4301 
4302   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
4303   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4304   // If we are done with the basic block, we need to check whether EFLAGS is
4305   // live-out.
4306   bool IsSafe = false;
4307   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
4308   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
4309   for (++I; I != E; ++I) {
4310     const MachineInstr &Instr = *I;
4311     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4312     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4313     // We should check the usage if this instruction uses and updates EFLAGS.
4314     if (!UseEFLAGS && ModifyEFLAGS) {
4315       // It is safe to remove CmpInstr if EFLAGS is updated again.
4316       IsSafe = true;
4317       break;
4318     }
4319     if (!UseEFLAGS && !ModifyEFLAGS)
4320       continue;
4321 
4322     // EFLAGS is used by this instruction.
4323     X86::CondCode OldCC = X86::COND_INVALID;
4324     bool OpcIsSET = false;
4325     if (IsCmpZero || IsSwapped) {
4326       // We decode the condition code from opcode.
4327       if (Instr.isBranch())
4328         OldCC = getCondFromBranchOpc(Instr.getOpcode());
4329       else {
4330         OldCC = getCondFromSETOpc(Instr.getOpcode());
4331         if (OldCC != X86::COND_INVALID)
4332           OpcIsSET = true;
4333         else
4334           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
4335       }
4336       if (OldCC == X86::COND_INVALID) return false;
4337     }
4338     if (IsCmpZero) {
4339       switch (OldCC) {
4340       default: break;
4341       case X86::COND_A: case X86::COND_AE:
4342       case X86::COND_B: case X86::COND_BE:
4343       case X86::COND_G: case X86::COND_GE:
4344       case X86::COND_L: case X86::COND_LE:
4345       case X86::COND_O: case X86::COND_NO:
4346         // CF and OF are used, we can't perform this optimization.
4347         return false;
4348       }
4349 
4350       // If we're updating the condition code check if we have to reverse the
4351       // condition.
4352       if (ShouldUpdateCC)
4353         switch (OldCC) {
4354         default:
4355           return false;
4356         case X86::COND_E:
4357           break;
4358         case X86::COND_NE:
4359           NewCC = GetOppositeBranchCondition(NewCC);
4360           break;
4361         }
4362     } else if (IsSwapped) {
4363       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4364       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4365       // We swap the condition code and synthesize the new opcode.
4366       NewCC = getSwappedCondition(OldCC);
4367       if (NewCC == X86::COND_INVALID) return false;
4368     }
4369 
4370     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
4371       // Synthesize the new opcode.
4372       bool HasMemoryOperand = Instr.hasOneMemOperand();
4373       unsigned NewOpc;
4374       if (Instr.isBranch())
4375         NewOpc = GetCondBranchFromCond(NewCC);
4376       else if(OpcIsSET)
4377         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
4378       else {
4379         unsigned DstReg = Instr.getOperand(0).getReg();
4380         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
4381                                  HasMemoryOperand);
4382       }
4383 
4384       // Push the MachineInstr to OpsToUpdate.
4385       // If it is safe to remove CmpInstr, the condition code of these
4386       // instructions will be modified.
4387       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4388     }
4389     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4390       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
4391       IsSafe = true;
4392       break;
4393     }
4394   }
4395 
4396   // If EFLAGS is not killed nor re-defined, we should check whether it is
4397   // live-out. If it is live-out, do not optimize.
4398   if ((IsCmpZero || IsSwapped) && !IsSafe) {
4399     MachineBasicBlock *MBB = CmpInstr->getParent();
4400     for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
4401              SE = MBB->succ_end(); SI != SE; ++SI)
4402       if ((*SI)->isLiveIn(X86::EFLAGS))
4403         return false;
4404   }
4405 
4406   // The instruction to be updated is either Sub or MI.
4407   Sub = IsCmpZero ? MI : Sub;
4408   // Move Movr0Inst to the appropriate place before Sub.
4409   if (Movr0Inst) {
4410     // Look backwards until we find a def that doesn't use the current EFLAGS.
4411     Def = Sub;
4412     MachineBasicBlock::reverse_iterator
4413       InsertI = MachineBasicBlock::reverse_iterator(++Def),
4414                 InsertE = Sub->getParent()->rend();
4415     for (; InsertI != InsertE; ++InsertI) {
4416       MachineInstr *Instr = &*InsertI;
4417       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4418           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4419         Sub->getParent()->remove(Movr0Inst);
4420         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4421                                    Movr0Inst);
4422         break;
4423       }
4424     }
4425     if (InsertI == InsertE)
4426       return false;
4427   }
4428 
4429   // Make sure Sub instruction defines EFLAGS and mark the def live.
4430   unsigned i = 0, e = Sub->getNumOperands();
4431   for (; i != e; ++i) {
4432     MachineOperand &MO = Sub->getOperand(i);
4433     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4434       MO.setIsDead(false);
4435       break;
4436     }
4437   }
4438   assert(i != e && "Unable to locate a def EFLAGS operand");
4439 
4440   CmpInstr->eraseFromParent();
4441 
4442   // Modify the condition code of instructions in OpsToUpdate.
4443   for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
4444     OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
4445   return true;
4446 }
4447 
4448 /// Try to remove the load by folding it to a register
4449 /// operand at the use. We fold the load instructions if load defines a virtual
4450 /// register, the virtual register is used once in the same BB, and the
4451 /// instructions in-between do not load or store, and have no side effects.
4452 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
4453                                               const MachineRegisterInfo *MRI,
4454                                               unsigned &FoldAsLoadDefReg,
4455                                               MachineInstr *&DefMI) const {
4456   if (FoldAsLoadDefReg == 0)
4457     return nullptr;
4458   // To be conservative, if there exists another load, clear the load candidate.
4459   if (MI->mayLoad()) {
4460     FoldAsLoadDefReg = 0;
4461     return nullptr;
4462   }
4463 
4464   // Check whether we can move DefMI here.
4465   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4466   assert(DefMI);
4467   bool SawStore = false;
4468   if (!DefMI->isSafeToMove(this, nullptr, SawStore))
4469     return nullptr;
4470 
4471   // Collect information about virtual register operands of MI.
4472   unsigned SrcOperandId = 0;
4473   bool FoundSrcOperand = false;
4474   for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
4475     MachineOperand &MO = MI->getOperand(i);
4476     if (!MO.isReg())
4477       continue;
4478     unsigned Reg = MO.getReg();
4479     if (Reg != FoldAsLoadDefReg)
4480       continue;
4481     // Do not fold if we have a subreg use or a def or multiple uses.
4482     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
4483       return nullptr;
4484 
4485     SrcOperandId = i;
4486     FoundSrcOperand = true;
4487   }
4488   if (!FoundSrcOperand)
4489     return nullptr;
4490 
4491   // Check whether we can fold the def into SrcOperandId.
4492   SmallVector<unsigned, 8> Ops;
4493   Ops.push_back(SrcOperandId);
4494   MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
4495   if (FoldMI) {
4496     FoldAsLoadDefReg = 0;
4497     return FoldMI;
4498   }
4499 
4500   return nullptr;
4501 }
4502 
4503 /// Expand a single-def pseudo instruction to a two-addr
4504 /// instruction with two undef reads of the register being defined.
4505 /// This is used for mapping:
4506 ///   %xmm4 = V_SET0
4507 /// to:
4508 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
4509 ///
4510 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4511                              const MCInstrDesc &Desc) {
4512   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
4513   unsigned Reg = MIB->getOperand(0).getReg();
4514   MIB->setDesc(Desc);
4515 
4516   // MachineInstr::addOperand() will insert explicit operands before any
4517   // implicit operands.
4518   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4519   // But we don't trust that.
4520   assert(MIB->getOperand(1).getReg() == Reg &&
4521          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
4522   return true;
4523 }
4524 
4525 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4526 // code sequence is needed for other targets.
4527 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4528                                  const TargetInstrInfo &TII) {
4529   MachineBasicBlock &MBB = *MIB->getParent();
4530   DebugLoc DL = MIB->getDebugLoc();
4531   unsigned Reg = MIB->getOperand(0).getReg();
4532   const GlobalValue *GV =
4533       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4534   unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4535   MachineMemOperand *MMO = MBB.getParent()->
4536       getMachineMemOperand(MachinePointerInfo::getGOT(), Flag, 8, 8);
4537   MachineBasicBlock::iterator I = MIB.getInstr();
4538 
4539   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4540       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4541       .addMemOperand(MMO);
4542   MIB->setDebugLoc(DL);
4543   MIB->setDesc(TII.get(X86::MOV64rm));
4544   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4545 }
4546 
4547 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
4548   bool HasAVX = Subtarget.hasAVX();
4549   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4550   switch (MI->getOpcode()) {
4551   case X86::MOV32r0:
4552     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4553   case X86::SETB_C8r:
4554     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4555   case X86::SETB_C16r:
4556     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4557   case X86::SETB_C32r:
4558     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4559   case X86::SETB_C64r:
4560     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4561   case X86::V_SET0:
4562   case X86::FsFLD0SS:
4563   case X86::FsFLD0SD:
4564     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4565   case X86::AVX_SET0:
4566     assert(HasAVX && "AVX not supported");
4567     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
4568   case X86::AVX512_512_SET0:
4569     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4570   case X86::V_SETALLONES:
4571     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4572   case X86::AVX2_SETALLONES:
4573     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4574   case X86::TEST8ri_NOREX:
4575     MI->setDesc(get(X86::TEST8ri));
4576     return true;
4577   case X86::KSET0B:
4578   case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
4579   case X86::KSET1B:
4580   case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
4581   case TargetOpcode::LOAD_STACK_GUARD:
4582     expandLoadStackGuard(MIB, *this);
4583     return true;
4584   }
4585   return false;
4586 }
4587 
4588 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
4589                                      const SmallVectorImpl<MachineOperand> &MOs,
4590                                      MachineInstr *MI,
4591                                      const TargetInstrInfo &TII) {
4592   // Create the base instruction with the memory operand as the first part.
4593   // Omit the implicit operands, something BuildMI can't do.
4594   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4595                                               MI->getDebugLoc(), true);
4596   MachineInstrBuilder MIB(MF, NewMI);
4597   unsigned NumAddrOps = MOs.size();
4598   for (unsigned i = 0; i != NumAddrOps; ++i)
4599     MIB.addOperand(MOs[i]);
4600   if (NumAddrOps < 4)  // FrameIndex only
4601     addOffset(MIB, 0);
4602 
4603   // Loop over the rest of the ri operands, converting them over.
4604   unsigned NumOps = MI->getDesc().getNumOperands()-2;
4605   for (unsigned i = 0; i != NumOps; ++i) {
4606     MachineOperand &MO = MI->getOperand(i+2);
4607     MIB.addOperand(MO);
4608   }
4609   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4610     MachineOperand &MO = MI->getOperand(i);
4611     MIB.addOperand(MO);
4612   }
4613   return MIB;
4614 }
4615 
4616 static MachineInstr *FuseInst(MachineFunction &MF,
4617                               unsigned Opcode, unsigned OpNo,
4618                               const SmallVectorImpl<MachineOperand> &MOs,
4619                               MachineInstr *MI, const TargetInstrInfo &TII) {
4620   // Omit the implicit operands, something BuildMI can't do.
4621   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4622                                               MI->getDebugLoc(), true);
4623   MachineInstrBuilder MIB(MF, NewMI);
4624 
4625   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4626     MachineOperand &MO = MI->getOperand(i);
4627     if (i == OpNo) {
4628       assert(MO.isReg() && "Expected to fold into reg operand!");
4629       unsigned NumAddrOps = MOs.size();
4630       for (unsigned i = 0; i != NumAddrOps; ++i)
4631         MIB.addOperand(MOs[i]);
4632       if (NumAddrOps < 4)  // FrameIndex only
4633         addOffset(MIB, 0);
4634     } else {
4635       MIB.addOperand(MO);
4636     }
4637   }
4638   return MIB;
4639 }
4640 
4641 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
4642                                 const SmallVectorImpl<MachineOperand> &MOs,
4643                                 MachineInstr *MI) {
4644   MachineFunction &MF = *MI->getParent()->getParent();
4645   MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
4646 
4647   unsigned NumAddrOps = MOs.size();
4648   for (unsigned i = 0; i != NumAddrOps; ++i)
4649     MIB.addOperand(MOs[i]);
4650   if (NumAddrOps < 4)  // FrameIndex only
4651     addOffset(MIB, 0);
4652   return MIB.addImm(0);
4653 }
4654 
4655 MachineInstr*
4656 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
4657                                     MachineInstr *MI, unsigned OpNum,
4658                                     const SmallVectorImpl<MachineOperand> &MOs,
4659                                     unsigned Size, unsigned Align,
4660                                     bool AllowCommute) const {
4661   const DenseMap<unsigned,
4662                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
4663   bool isCallRegIndirect = Subtarget.callRegIndirect();
4664   bool isTwoAddrFold = false;
4665 
4666   // For CPUs that favor the register form of a call,
4667   // do not fold loads into calls.
4668   if (isCallRegIndirect &&
4669     (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r))
4670     return nullptr;
4671 
4672   unsigned NumOps = MI->getDesc().getNumOperands();
4673   bool isTwoAddr = NumOps > 1 &&
4674     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4675 
4676   // FIXME: AsmPrinter doesn't know how to handle
4677   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4678   if (MI->getOpcode() == X86::ADD32ri &&
4679       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4680     return nullptr;
4681 
4682   MachineInstr *NewMI = nullptr;
4683   // Folding a memory location into the two-address part of a two-address
4684   // instruction is different than folding it other places.  It requires
4685   // replacing the *two* registers with the memory location.
4686   if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
4687       MI->getOperand(0).isReg() &&
4688       MI->getOperand(1).isReg() &&
4689       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
4690     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4691     isTwoAddrFold = true;
4692   } else if (OpNum == 0) {
4693     if (MI->getOpcode() == X86::MOV32r0) {
4694       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
4695       if (NewMI)
4696         return NewMI;
4697     }
4698 
4699     OpcodeTablePtr = &RegOp2MemOpTable0;
4700   } else if (OpNum == 1) {
4701     OpcodeTablePtr = &RegOp2MemOpTable1;
4702   } else if (OpNum == 2) {
4703     OpcodeTablePtr = &RegOp2MemOpTable2;
4704   } else if (OpNum == 3) {
4705     OpcodeTablePtr = &RegOp2MemOpTable3;
4706   } else if (OpNum == 4) {
4707     OpcodeTablePtr = &RegOp2MemOpTable4;
4708   }
4709 
4710   // If table selected...
4711   if (OpcodeTablePtr) {
4712     // Find the Opcode to fuse
4713     DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4714       OpcodeTablePtr->find(MI->getOpcode());
4715     if (I != OpcodeTablePtr->end()) {
4716       unsigned Opcode = I->second.first;
4717       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
4718       if (Align < MinAlign)
4719         return nullptr;
4720       bool NarrowToMOV32rm = false;
4721       if (Size) {
4722         unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
4723         if (Size < RCSize) {
4724           // Check if it's safe to fold the load. If the size of the object is
4725           // narrower than the load width, then it's not.
4726           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
4727             return nullptr;
4728           // If this is a 64-bit load, but the spill slot is 32, then we can do
4729           // a 32-bit load which is implicitly zero-extended. This likely is
4730           // due to live interval analysis remat'ing a load from stack slot.
4731           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
4732             return nullptr;
4733           Opcode = X86::MOV32rm;
4734           NarrowToMOV32rm = true;
4735         }
4736       }
4737 
4738       if (isTwoAddrFold)
4739         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
4740       else
4741         NewMI = FuseInst(MF, Opcode, OpNum, MOs, MI, *this);
4742 
4743       if (NarrowToMOV32rm) {
4744         // If this is the special case where we use a MOV32rm to load a 32-bit
4745         // value and zero-extend the top bits. Change the destination register
4746         // to a 32-bit one.
4747         unsigned DstReg = NewMI->getOperand(0).getReg();
4748         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
4749           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4750         else
4751           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4752       }
4753       return NewMI;
4754     }
4755   }
4756 
4757   // If the instruction and target operand are commutable, commute the
4758   // instruction and try again.
4759   if (AllowCommute) {
4760     unsigned OriginalOpIdx = OpNum, CommuteOpIdx1, CommuteOpIdx2;
4761     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
4762       bool HasDef = MI->getDesc().getNumDefs();
4763       unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
4764       unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
4765       unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
4766       bool Tied0 =
4767           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
4768       bool Tied1 =
4769           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
4770 
4771       // If either of the commutable operands are tied to the destination
4772       // then we can not commute + fold.
4773       if ((HasDef && Reg0 == Reg1 && Tied0) ||
4774           (HasDef && Reg0 == Reg2 && Tied1))
4775         return nullptr;
4776 
4777       if ((CommuteOpIdx1 == OriginalOpIdx) ||
4778           (CommuteOpIdx2 == OriginalOpIdx)) {
4779         MachineInstr *CommutedMI = commuteInstruction(MI, false);
4780         if (!CommutedMI) {
4781           // Unable to commute.
4782           return nullptr;
4783         }
4784         if (CommutedMI != MI) {
4785           // New instruction. We can't fold from this.
4786           CommutedMI->eraseFromParent();
4787           return nullptr;
4788         }
4789 
4790         // Attempt to fold with the commuted version of the instruction.
4791         unsigned CommuteOp =
4792             (CommuteOpIdx1 == OriginalOpIdx ? CommuteOpIdx2 : CommuteOpIdx1);
4793         NewMI = foldMemoryOperandImpl(MF, MI, CommuteOp, MOs, Size, Align,
4794                                       /*AllowCommute=*/false);
4795         if (NewMI)
4796           return NewMI;
4797 
4798         // Folding failed again - undo the commute before returning.
4799         MachineInstr *UncommutedMI = commuteInstruction(MI, false);
4800         if (!UncommutedMI) {
4801           // Unable to commute.
4802           return nullptr;
4803         }
4804         if (UncommutedMI != MI) {
4805           // New instruction. It doesn't need to be kept.
4806           UncommutedMI->eraseFromParent();
4807           return nullptr;
4808         }
4809 
4810         // Return here to prevent duplicate fuse failure report.
4811         return nullptr;
4812       }
4813     }
4814   }
4815 
4816   // No fusion
4817   if (PrintFailedFusing && !MI->isCopy())
4818     dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
4819   return nullptr;
4820 }
4821 
4822 /// Return true for all instructions that only update
4823 /// the first 32 or 64-bits of the destination register and leave the rest
4824 /// unmodified. This can be used to avoid folding loads if the instructions
4825 /// only update part of the destination register, and the non-updated part is
4826 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
4827 /// instructions breaks the partial register dependency and it can improve
4828 /// performance. e.g.:
4829 ///
4830 ///   movss (%rdi), %xmm0
4831 ///   cvtss2sd %xmm0, %xmm0
4832 ///
4833 /// Instead of
4834 ///   cvtss2sd (%rdi), %xmm0
4835 ///
4836 /// FIXME: This should be turned into a TSFlags.
4837 ///
4838 static bool hasPartialRegUpdate(unsigned Opcode) {
4839   switch (Opcode) {
4840   case X86::CVTSI2SSrr:
4841   case X86::CVTSI2SSrm:
4842   case X86::CVTSI2SS64rr:
4843   case X86::CVTSI2SS64rm:
4844   case X86::CVTSI2SDrr:
4845   case X86::CVTSI2SDrm:
4846   case X86::CVTSI2SD64rr:
4847   case X86::CVTSI2SD64rm:
4848   case X86::CVTSD2SSrr:
4849   case X86::CVTSD2SSrm:
4850   case X86::Int_CVTSD2SSrr:
4851   case X86::Int_CVTSD2SSrm:
4852   case X86::CVTSS2SDrr:
4853   case X86::CVTSS2SDrm:
4854   case X86::Int_CVTSS2SDrr:
4855   case X86::Int_CVTSS2SDrm:
4856   case X86::RCPSSr:
4857   case X86::RCPSSm:
4858   case X86::RCPSSr_Int:
4859   case X86::RCPSSm_Int:
4860   case X86::ROUNDSDr:
4861   case X86::ROUNDSDm:
4862   case X86::ROUNDSDr_Int:
4863   case X86::ROUNDSSr:
4864   case X86::ROUNDSSm:
4865   case X86::ROUNDSSr_Int:
4866   case X86::RSQRTSSr:
4867   case X86::RSQRTSSm:
4868   case X86::RSQRTSSr_Int:
4869   case X86::RSQRTSSm_Int:
4870   case X86::SQRTSSr:
4871   case X86::SQRTSSm:
4872   case X86::SQRTSSr_Int:
4873   case X86::SQRTSSm_Int:
4874   case X86::SQRTSDr:
4875   case X86::SQRTSDm:
4876   case X86::SQRTSDr_Int:
4877   case X86::SQRTSDm_Int:
4878     return true;
4879   }
4880 
4881   return false;
4882 }
4883 
4884 /// Inform the ExeDepsFix pass how many idle
4885 /// instructions we would like before a partial register update.
4886 unsigned X86InstrInfo::
4887 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
4888                              const TargetRegisterInfo *TRI) const {
4889   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
4890     return 0;
4891 
4892   // If MI is marked as reading Reg, the partial register update is wanted.
4893   const MachineOperand &MO = MI->getOperand(0);
4894   unsigned Reg = MO.getReg();
4895   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4896     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
4897       return 0;
4898   } else {
4899     if (MI->readsRegister(Reg, TRI))
4900       return 0;
4901   }
4902 
4903   // If any of the preceding 16 instructions are reading Reg, insert a
4904   // dependency breaking instruction.  The magic number is based on a few
4905   // Nehalem experiments.
4906   return 16;
4907 }
4908 
4909 // Return true for any instruction the copies the high bits of the first source
4910 // operand into the unused high bits of the destination operand.
4911 static bool hasUndefRegUpdate(unsigned Opcode) {
4912   switch (Opcode) {
4913   case X86::VCVTSI2SSrr:
4914   case X86::VCVTSI2SSrm:
4915   case X86::Int_VCVTSI2SSrr:
4916   case X86::Int_VCVTSI2SSrm:
4917   case X86::VCVTSI2SS64rr:
4918   case X86::VCVTSI2SS64rm:
4919   case X86::Int_VCVTSI2SS64rr:
4920   case X86::Int_VCVTSI2SS64rm:
4921   case X86::VCVTSI2SDrr:
4922   case X86::VCVTSI2SDrm:
4923   case X86::Int_VCVTSI2SDrr:
4924   case X86::Int_VCVTSI2SDrm:
4925   case X86::VCVTSI2SD64rr:
4926   case X86::VCVTSI2SD64rm:
4927   case X86::Int_VCVTSI2SD64rr:
4928   case X86::Int_VCVTSI2SD64rm:
4929   case X86::VCVTSD2SSrr:
4930   case X86::VCVTSD2SSrm:
4931   case X86::Int_VCVTSD2SSrr:
4932   case X86::Int_VCVTSD2SSrm:
4933   case X86::VCVTSS2SDrr:
4934   case X86::VCVTSS2SDrm:
4935   case X86::Int_VCVTSS2SDrr:
4936   case X86::Int_VCVTSS2SDrm:
4937   case X86::VRCPSSr:
4938   case X86::VRCPSSm:
4939   case X86::VRCPSSm_Int:
4940   case X86::VROUNDSDr:
4941   case X86::VROUNDSDm:
4942   case X86::VROUNDSDr_Int:
4943   case X86::VROUNDSSr:
4944   case X86::VROUNDSSm:
4945   case X86::VROUNDSSr_Int:
4946   case X86::VRSQRTSSr:
4947   case X86::VRSQRTSSm:
4948   case X86::VRSQRTSSm_Int:
4949   case X86::VSQRTSSr:
4950   case X86::VSQRTSSm:
4951   case X86::VSQRTSSm_Int:
4952   case X86::VSQRTSDr:
4953   case X86::VSQRTSDm:
4954   case X86::VSQRTSDm_Int:
4955     // AVX-512
4956   case X86::VCVTSD2SSZrr:
4957   case X86::VCVTSD2SSZrm:
4958   case X86::VCVTSS2SDZrr:
4959   case X86::VCVTSS2SDZrm:
4960     return true;
4961   }
4962 
4963   return false;
4964 }
4965 
4966 /// Inform the ExeDepsFix pass how many idle instructions we would like before
4967 /// certain undef register reads.
4968 ///
4969 /// This catches the VCVTSI2SD family of instructions:
4970 ///
4971 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
4972 ///
4973 /// We should to be careful *not* to catch VXOR idioms which are presumably
4974 /// handled specially in the pipeline:
4975 ///
4976 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
4977 ///
4978 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
4979 /// high bits that are passed-through are not live.
4980 unsigned X86InstrInfo::
4981 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
4982                      const TargetRegisterInfo *TRI) const {
4983   if (!hasUndefRegUpdate(MI->getOpcode()))
4984     return 0;
4985 
4986   // Set the OpNum parameter to the first source operand.
4987   OpNum = 1;
4988 
4989   const MachineOperand &MO = MI->getOperand(OpNum);
4990   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
4991     // Use the same magic number as getPartialRegUpdateClearance.
4992     return 16;
4993   }
4994   return 0;
4995 }
4996 
4997 void X86InstrInfo::
4998 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
4999                           const TargetRegisterInfo *TRI) const {
5000   unsigned Reg = MI->getOperand(OpNum).getReg();
5001   // If MI kills this register, the false dependence is already broken.
5002   if (MI->killsRegister(Reg, TRI))
5003     return;
5004   if (X86::VR128RegClass.contains(Reg)) {
5005     // These instructions are all floating point domain, so xorps is the best
5006     // choice.
5007     bool HasAVX = Subtarget.hasAVX();
5008     unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
5009     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
5010       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5011   } else if (X86::VR256RegClass.contains(Reg)) {
5012     // Use vxorps to clear the full ymm register.
5013     // It wants to read and write the xmm sub-register.
5014     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5015     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
5016       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
5017       .addReg(Reg, RegState::ImplicitDefine);
5018   } else
5019     return;
5020   MI->addRegisterKilled(Reg, TRI, true);
5021 }
5022 
5023 MachineInstr*
5024 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
5025                                     const SmallVectorImpl<unsigned> &Ops,
5026                                     int FrameIndex) const {
5027   // Check switch flag
5028   if (NoFusing) return nullptr;
5029 
5030   // Unless optimizing for size, don't fold to avoid partial
5031   // register update stalls
5032   if (!MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize) &&
5033       hasPartialRegUpdate(MI->getOpcode()))
5034     return nullptr;
5035 
5036   const MachineFrameInfo *MFI = MF.getFrameInfo();
5037   unsigned Size = MFI->getObjectSize(FrameIndex);
5038   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
5039   // If the function stack isn't realigned we don't want to fold instructions
5040   // that need increased alignment.
5041   if (!RI.needsStackRealignment(MF))
5042     Alignment =
5043         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
5044   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5045     unsigned NewOpc = 0;
5046     unsigned RCSize = 0;
5047     switch (MI->getOpcode()) {
5048     default: return nullptr;
5049     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
5050     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5051     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5052     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
5053     }
5054     // Check if it's safe to fold the load. If the size of the object is
5055     // narrower than the load width, then it's not.
5056     if (Size < RCSize)
5057       return nullptr;
5058     // Change to CMPXXri r, 0 first.
5059     MI->setDesc(get(NewOpc));
5060     MI->getOperand(1).ChangeToImmediate(0);
5061   } else if (Ops.size() != 1)
5062     return nullptr;
5063 
5064   SmallVector<MachineOperand,4> MOs;
5065   MOs.push_back(MachineOperand::CreateFI(FrameIndex));
5066   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
5067                                Size, Alignment, /*AllowCommute=*/true);
5068 }
5069 
5070 static bool isPartialRegisterLoad(const MachineInstr &LoadMI,
5071                                   const MachineFunction &MF) {
5072   unsigned Opc = LoadMI.getOpcode();
5073   unsigned RegSize =
5074       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
5075 
5076   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
5077     // These instructions only load 32 bits, we can't fold them if the
5078     // destination register is wider than 32 bits (4 bytes).
5079     return true;
5080 
5081   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
5082     // These instructions only load 64 bits, we can't fold them if the
5083     // destination register is wider than 64 bits (8 bytes).
5084     return true;
5085 
5086   return false;
5087 }
5088 
5089 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
5090                                                   MachineInstr *MI,
5091                                            const SmallVectorImpl<unsigned> &Ops,
5092                                                   MachineInstr *LoadMI) const {
5093   // If loading from a FrameIndex, fold directly from the FrameIndex.
5094   unsigned NumOps = LoadMI->getDesc().getNumOperands();
5095   int FrameIndex;
5096   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
5097     if (isPartialRegisterLoad(*LoadMI, MF))
5098       return nullptr;
5099     return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
5100   }
5101 
5102   // Check switch flag
5103   if (NoFusing) return nullptr;
5104 
5105   // Unless optimizing for size, don't fold to avoid partial
5106   // register update stalls
5107   if (!MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize) &&
5108       hasPartialRegUpdate(MI->getOpcode()))
5109     return nullptr;
5110 
5111   // Determine the alignment of the load.
5112   unsigned Alignment = 0;
5113   if (LoadMI->hasOneMemOperand())
5114     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
5115   else
5116     switch (LoadMI->getOpcode()) {
5117     case X86::AVX2_SETALLONES:
5118     case X86::AVX_SET0:
5119       Alignment = 32;
5120       break;
5121     case X86::V_SET0:
5122     case X86::V_SETALLONES:
5123       Alignment = 16;
5124       break;
5125     case X86::FsFLD0SD:
5126       Alignment = 8;
5127       break;
5128     case X86::FsFLD0SS:
5129       Alignment = 4;
5130       break;
5131     default:
5132       return nullptr;
5133     }
5134   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5135     unsigned NewOpc = 0;
5136     switch (MI->getOpcode()) {
5137     default: return nullptr;
5138     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
5139     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5140     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5141     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
5142     }
5143     // Change to CMPXXri r, 0 first.
5144     MI->setDesc(get(NewOpc));
5145     MI->getOperand(1).ChangeToImmediate(0);
5146   } else if (Ops.size() != 1)
5147     return nullptr;
5148 
5149   // Make sure the subregisters match.
5150   // Otherwise we risk changing the size of the load.
5151   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
5152     return nullptr;
5153 
5154   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5155   switch (LoadMI->getOpcode()) {
5156   case X86::V_SET0:
5157   case X86::V_SETALLONES:
5158   case X86::AVX2_SETALLONES:
5159   case X86::AVX_SET0:
5160   case X86::FsFLD0SD:
5161   case X86::FsFLD0SS: {
5162     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
5163     // Create a constant-pool entry and operands to load from it.
5164 
5165     // Medium and large mode can't fold loads this way.
5166     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5167         MF.getTarget().getCodeModel() != CodeModel::Kernel)
5168       return nullptr;
5169 
5170     // x86-32 PIC requires a PIC base register for constant pools.
5171     unsigned PICBase = 0;
5172     if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
5173       if (Subtarget.is64Bit())
5174         PICBase = X86::RIP;
5175       else
5176         // FIXME: PICBase = getGlobalBaseReg(&MF);
5177         // This doesn't work for several reasons.
5178         // 1. GlobalBaseReg may have been spilled.
5179         // 2. It may not be live at MI.
5180         return nullptr;
5181     }
5182 
5183     // Create a constant-pool entry.
5184     MachineConstantPool &MCP = *MF.getConstantPool();
5185     Type *Ty;
5186     unsigned Opc = LoadMI->getOpcode();
5187     if (Opc == X86::FsFLD0SS)
5188       Ty = Type::getFloatTy(MF.getFunction()->getContext());
5189     else if (Opc == X86::FsFLD0SD)
5190       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
5191     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
5192       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
5193     else
5194       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
5195 
5196     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
5197     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5198                                     Constant::getNullValue(Ty);
5199     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
5200 
5201     // Create operands to load from the constant pool entry.
5202     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5203     MOs.push_back(MachineOperand::CreateImm(1));
5204     MOs.push_back(MachineOperand::CreateReg(0, false));
5205     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5206     MOs.push_back(MachineOperand::CreateReg(0, false));
5207     break;
5208   }
5209   default: {
5210     if (isPartialRegisterLoad(*LoadMI, MF))
5211       return nullptr;
5212 
5213     // Folding a normal load. Just copy the load's address operands.
5214     for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
5215       MOs.push_back(LoadMI->getOperand(i));
5216     break;
5217   }
5218   }
5219   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs,
5220                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
5221 }
5222 
5223 
5224 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
5225                                   const SmallVectorImpl<unsigned> &Ops) const {
5226   // Check switch flag
5227   if (NoFusing) return 0;
5228 
5229   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5230     switch (MI->getOpcode()) {
5231     default: return false;
5232     case X86::TEST8rr:
5233     case X86::TEST16rr:
5234     case X86::TEST32rr:
5235     case X86::TEST64rr:
5236       return true;
5237     case X86::ADD32ri:
5238       // FIXME: AsmPrinter doesn't know how to handle
5239       // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5240       if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
5241         return false;
5242       break;
5243     }
5244   }
5245 
5246   if (Ops.size() != 1)
5247     return false;
5248 
5249   unsigned OpNum = Ops[0];
5250   unsigned Opc = MI->getOpcode();
5251   unsigned NumOps = MI->getDesc().getNumOperands();
5252   bool isTwoAddr = NumOps > 1 &&
5253     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
5254 
5255   // Folding a memory location into the two-address part of a two-address
5256   // instruction is different than folding it other places.  It requires
5257   // replacing the *two* registers with the memory location.
5258   const DenseMap<unsigned,
5259                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
5260   if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
5261     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5262   } else if (OpNum == 0) {
5263     if (Opc == X86::MOV32r0)
5264       return true;
5265 
5266     OpcodeTablePtr = &RegOp2MemOpTable0;
5267   } else if (OpNum == 1) {
5268     OpcodeTablePtr = &RegOp2MemOpTable1;
5269   } else if (OpNum == 2) {
5270     OpcodeTablePtr = &RegOp2MemOpTable2;
5271   } else if (OpNum == 3) {
5272     OpcodeTablePtr = &RegOp2MemOpTable3;
5273   }
5274 
5275   if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
5276     return true;
5277   return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
5278 }
5279 
5280 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
5281                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
5282                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
5283   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5284     MemOp2RegOpTable.find(MI->getOpcode());
5285   if (I == MemOp2RegOpTable.end())
5286     return false;
5287   unsigned Opc = I->second.first;
5288   unsigned Index = I->second.second & TB_INDEX_MASK;
5289   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5290   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5291   if (UnfoldLoad && !FoldedLoad)
5292     return false;
5293   UnfoldLoad &= FoldedLoad;
5294   if (UnfoldStore && !FoldedStore)
5295     return false;
5296   UnfoldStore &= FoldedStore;
5297 
5298   const MCInstrDesc &MCID = get(Opc);
5299   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5300   if (!MI->hasOneMemOperand() &&
5301       RC == &X86::VR128RegClass &&
5302       !Subtarget.isUnalignedMemAccessFast())
5303     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5304     // conservatively assume the address is unaligned. That's bad for
5305     // performance.
5306     return false;
5307   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5308   SmallVector<MachineOperand,2> BeforeOps;
5309   SmallVector<MachineOperand,2> AfterOps;
5310   SmallVector<MachineOperand,4> ImpOps;
5311   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5312     MachineOperand &Op = MI->getOperand(i);
5313     if (i >= Index && i < Index + X86::AddrNumOperands)
5314       AddrOps.push_back(Op);
5315     else if (Op.isReg() && Op.isImplicit())
5316       ImpOps.push_back(Op);
5317     else if (i < Index)
5318       BeforeOps.push_back(Op);
5319     else if (i > Index)
5320       AfterOps.push_back(Op);
5321   }
5322 
5323   // Emit the load instruction.
5324   if (UnfoldLoad) {
5325     std::pair<MachineInstr::mmo_iterator,
5326               MachineInstr::mmo_iterator> MMOs =
5327       MF.extractLoadMemRefs(MI->memoperands_begin(),
5328                             MI->memoperands_end());
5329     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
5330     if (UnfoldStore) {
5331       // Address operands cannot be marked isKill.
5332       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
5333         MachineOperand &MO = NewMIs[0]->getOperand(i);
5334         if (MO.isReg())
5335           MO.setIsKill(false);
5336       }
5337     }
5338   }
5339 
5340   // Emit the data processing instruction.
5341   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
5342   MachineInstrBuilder MIB(MF, DataMI);
5343 
5344   if (FoldedStore)
5345     MIB.addReg(Reg, RegState::Define);
5346   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
5347     MIB.addOperand(BeforeOps[i]);
5348   if (FoldedLoad)
5349     MIB.addReg(Reg);
5350   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
5351     MIB.addOperand(AfterOps[i]);
5352   for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
5353     MachineOperand &MO = ImpOps[i];
5354     MIB.addReg(MO.getReg(),
5355                getDefRegState(MO.isDef()) |
5356                RegState::Implicit |
5357                getKillRegState(MO.isKill()) |
5358                getDeadRegState(MO.isDead()) |
5359                getUndefRegState(MO.isUndef()));
5360   }
5361   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
5362   switch (DataMI->getOpcode()) {
5363   default: break;
5364   case X86::CMP64ri32:
5365   case X86::CMP64ri8:
5366   case X86::CMP32ri:
5367   case X86::CMP32ri8:
5368   case X86::CMP16ri:
5369   case X86::CMP16ri8:
5370   case X86::CMP8ri: {
5371     MachineOperand &MO0 = DataMI->getOperand(0);
5372     MachineOperand &MO1 = DataMI->getOperand(1);
5373     if (MO1.getImm() == 0) {
5374       unsigned NewOpc;
5375       switch (DataMI->getOpcode()) {
5376       default: llvm_unreachable("Unreachable!");
5377       case X86::CMP64ri8:
5378       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
5379       case X86::CMP32ri8:
5380       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
5381       case X86::CMP16ri8:
5382       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
5383       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
5384       }
5385       DataMI->setDesc(get(NewOpc));
5386       MO1.ChangeToRegister(MO0.getReg(), false);
5387     }
5388   }
5389   }
5390   NewMIs.push_back(DataMI);
5391 
5392   // Emit the store instruction.
5393   if (UnfoldStore) {
5394     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5395     std::pair<MachineInstr::mmo_iterator,
5396               MachineInstr::mmo_iterator> MMOs =
5397       MF.extractStoreMemRefs(MI->memoperands_begin(),
5398                              MI->memoperands_end());
5399     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
5400   }
5401 
5402   return true;
5403 }
5404 
5405 bool
5406 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
5407                                   SmallVectorImpl<SDNode*> &NewNodes) const {
5408   if (!N->isMachineOpcode())
5409     return false;
5410 
5411   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5412     MemOp2RegOpTable.find(N->getMachineOpcode());
5413   if (I == MemOp2RegOpTable.end())
5414     return false;
5415   unsigned Opc = I->second.first;
5416   unsigned Index = I->second.second & TB_INDEX_MASK;
5417   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5418   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5419   const MCInstrDesc &MCID = get(Opc);
5420   MachineFunction &MF = DAG.getMachineFunction();
5421   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5422   unsigned NumDefs = MCID.NumDefs;
5423   std::vector<SDValue> AddrOps;
5424   std::vector<SDValue> BeforeOps;
5425   std::vector<SDValue> AfterOps;
5426   SDLoc dl(N);
5427   unsigned NumOps = N->getNumOperands();
5428   for (unsigned i = 0; i != NumOps-1; ++i) {
5429     SDValue Op = N->getOperand(i);
5430     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
5431       AddrOps.push_back(Op);
5432     else if (i < Index-NumDefs)
5433       BeforeOps.push_back(Op);
5434     else if (i > Index-NumDefs)
5435       AfterOps.push_back(Op);
5436   }
5437   SDValue Chain = N->getOperand(NumOps-1);
5438   AddrOps.push_back(Chain);
5439 
5440   // Emit the load instruction.
5441   SDNode *Load = nullptr;
5442   if (FoldedLoad) {
5443     EVT VT = *RC->vt_begin();
5444     std::pair<MachineInstr::mmo_iterator,
5445               MachineInstr::mmo_iterator> MMOs =
5446       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5447                             cast<MachineSDNode>(N)->memoperands_end());
5448     if (!(*MMOs.first) &&
5449         RC == &X86::VR128RegClass &&
5450         !Subtarget.isUnalignedMemAccessFast())
5451       // Do not introduce a slow unaligned load.
5452       return false;
5453     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5454     bool isAligned = (*MMOs.first) &&
5455                      (*MMOs.first)->getAlignment() >= Alignment;
5456     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
5457                               VT, MVT::Other, AddrOps);
5458     NewNodes.push_back(Load);
5459 
5460     // Preserve memory reference information.
5461     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
5462   }
5463 
5464   // Emit the data processing instruction.
5465   std::vector<EVT> VTs;
5466   const TargetRegisterClass *DstRC = nullptr;
5467   if (MCID.getNumDefs() > 0) {
5468     DstRC = getRegClass(MCID, 0, &RI, MF);
5469     VTs.push_back(*DstRC->vt_begin());
5470   }
5471   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
5472     EVT VT = N->getValueType(i);
5473     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
5474       VTs.push_back(VT);
5475   }
5476   if (Load)
5477     BeforeOps.push_back(SDValue(Load, 0));
5478   std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
5479   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
5480   NewNodes.push_back(NewNode);
5481 
5482   // Emit the store instruction.
5483   if (FoldedStore) {
5484     AddrOps.pop_back();
5485     AddrOps.push_back(SDValue(NewNode, 0));
5486     AddrOps.push_back(Chain);
5487     std::pair<MachineInstr::mmo_iterator,
5488               MachineInstr::mmo_iterator> MMOs =
5489       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5490                              cast<MachineSDNode>(N)->memoperands_end());
5491     if (!(*MMOs.first) &&
5492         RC == &X86::VR128RegClass &&
5493         !Subtarget.isUnalignedMemAccessFast())
5494       // Do not introduce a slow unaligned store.
5495       return false;
5496     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5497     bool isAligned = (*MMOs.first) &&
5498                      (*MMOs.first)->getAlignment() >= Alignment;
5499     SDNode *Store =
5500         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5501                            dl, MVT::Other, AddrOps);
5502     NewNodes.push_back(Store);
5503 
5504     // Preserve memory reference information.
5505     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
5506   }
5507 
5508   return true;
5509 }
5510 
5511 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
5512                                       bool UnfoldLoad, bool UnfoldStore,
5513                                       unsigned *LoadRegIndex) const {
5514   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5515     MemOp2RegOpTable.find(Opc);
5516   if (I == MemOp2RegOpTable.end())
5517     return 0;
5518   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5519   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
5520   if (UnfoldLoad && !FoldedLoad)
5521     return 0;
5522   if (UnfoldStore && !FoldedStore)
5523     return 0;
5524   if (LoadRegIndex)
5525     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
5526   return I->second.first;
5527 }
5528 
5529 bool
5530 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5531                                      int64_t &Offset1, int64_t &Offset2) const {
5532   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5533     return false;
5534   unsigned Opc1 = Load1->getMachineOpcode();
5535   unsigned Opc2 = Load2->getMachineOpcode();
5536   switch (Opc1) {
5537   default: return false;
5538   case X86::MOV8rm:
5539   case X86::MOV16rm:
5540   case X86::MOV32rm:
5541   case X86::MOV64rm:
5542   case X86::LD_Fp32m:
5543   case X86::LD_Fp64m:
5544   case X86::LD_Fp80m:
5545   case X86::MOVSSrm:
5546   case X86::MOVSDrm:
5547   case X86::MMX_MOVD64rm:
5548   case X86::MMX_MOVQ64rm:
5549   case X86::FsMOVAPSrm:
5550   case X86::FsMOVAPDrm:
5551   case X86::MOVAPSrm:
5552   case X86::MOVUPSrm:
5553   case X86::MOVAPDrm:
5554   case X86::MOVDQArm:
5555   case X86::MOVDQUrm:
5556   // AVX load instructions
5557   case X86::VMOVSSrm:
5558   case X86::VMOVSDrm:
5559   case X86::FsVMOVAPSrm:
5560   case X86::FsVMOVAPDrm:
5561   case X86::VMOVAPSrm:
5562   case X86::VMOVUPSrm:
5563   case X86::VMOVAPDrm:
5564   case X86::VMOVDQArm:
5565   case X86::VMOVDQUrm:
5566   case X86::VMOVAPSYrm:
5567   case X86::VMOVUPSYrm:
5568   case X86::VMOVAPDYrm:
5569   case X86::VMOVDQAYrm:
5570   case X86::VMOVDQUYrm:
5571     break;
5572   }
5573   switch (Opc2) {
5574   default: return false;
5575   case X86::MOV8rm:
5576   case X86::MOV16rm:
5577   case X86::MOV32rm:
5578   case X86::MOV64rm:
5579   case X86::LD_Fp32m:
5580   case X86::LD_Fp64m:
5581   case X86::LD_Fp80m:
5582   case X86::MOVSSrm:
5583   case X86::MOVSDrm:
5584   case X86::MMX_MOVD64rm:
5585   case X86::MMX_MOVQ64rm:
5586   case X86::FsMOVAPSrm:
5587   case X86::FsMOVAPDrm:
5588   case X86::MOVAPSrm:
5589   case X86::MOVUPSrm:
5590   case X86::MOVAPDrm:
5591   case X86::MOVDQArm:
5592   case X86::MOVDQUrm:
5593   // AVX load instructions
5594   case X86::VMOVSSrm:
5595   case X86::VMOVSDrm:
5596   case X86::FsVMOVAPSrm:
5597   case X86::FsVMOVAPDrm:
5598   case X86::VMOVAPSrm:
5599   case X86::VMOVUPSrm:
5600   case X86::VMOVAPDrm:
5601   case X86::VMOVDQArm:
5602   case X86::VMOVDQUrm:
5603   case X86::VMOVAPSYrm:
5604   case X86::VMOVUPSYrm:
5605   case X86::VMOVAPDYrm:
5606   case X86::VMOVDQAYrm:
5607   case X86::VMOVDQUYrm:
5608     break;
5609   }
5610 
5611   // Check if chain operands and base addresses match.
5612   if (Load1->getOperand(0) != Load2->getOperand(0) ||
5613       Load1->getOperand(5) != Load2->getOperand(5))
5614     return false;
5615   // Segment operands should match as well.
5616   if (Load1->getOperand(4) != Load2->getOperand(4))
5617     return false;
5618   // Scale should be 1, Index should be Reg0.
5619   if (Load1->getOperand(1) == Load2->getOperand(1) &&
5620       Load1->getOperand(2) == Load2->getOperand(2)) {
5621     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5622       return false;
5623 
5624     // Now let's examine the displacements.
5625     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5626         isa<ConstantSDNode>(Load2->getOperand(3))) {
5627       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5628       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5629       return true;
5630     }
5631   }
5632   return false;
5633 }
5634 
5635 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5636                                            int64_t Offset1, int64_t Offset2,
5637                                            unsigned NumLoads) const {
5638   assert(Offset2 > Offset1);
5639   if ((Offset2 - Offset1) / 8 > 64)
5640     return false;
5641 
5642   unsigned Opc1 = Load1->getMachineOpcode();
5643   unsigned Opc2 = Load2->getMachineOpcode();
5644   if (Opc1 != Opc2)
5645     return false;  // FIXME: overly conservative?
5646 
5647   switch (Opc1) {
5648   default: break;
5649   case X86::LD_Fp32m:
5650   case X86::LD_Fp64m:
5651   case X86::LD_Fp80m:
5652   case X86::MMX_MOVD64rm:
5653   case X86::MMX_MOVQ64rm:
5654     return false;
5655   }
5656 
5657   EVT VT = Load1->getValueType(0);
5658   switch (VT.getSimpleVT().SimpleTy) {
5659   default:
5660     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5661     // have 16 of them to play with.
5662     if (Subtarget.is64Bit()) {
5663       if (NumLoads >= 3)
5664         return false;
5665     } else if (NumLoads) {
5666       return false;
5667     }
5668     break;
5669   case MVT::i8:
5670   case MVT::i16:
5671   case MVT::i32:
5672   case MVT::i64:
5673   case MVT::f32:
5674   case MVT::f64:
5675     if (NumLoads)
5676       return false;
5677     break;
5678   }
5679 
5680   return true;
5681 }
5682 
5683 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5684                                           MachineInstr *Second) const {
5685   // Check if this processor supports macro-fusion. Since this is a minor
5686   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5687   // proxy for SandyBridge+.
5688   if (!Subtarget.hasAVX())
5689     return false;
5690 
5691   enum {
5692     FuseTest,
5693     FuseCmp,
5694     FuseInc
5695   } FuseKind;
5696 
5697   switch(Second->getOpcode()) {
5698   default:
5699     return false;
5700   case X86::JE_1:
5701   case X86::JNE_1:
5702   case X86::JL_1:
5703   case X86::JLE_1:
5704   case X86::JG_1:
5705   case X86::JGE_1:
5706     FuseKind = FuseInc;
5707     break;
5708   case X86::JB_1:
5709   case X86::JBE_1:
5710   case X86::JA_1:
5711   case X86::JAE_1:
5712     FuseKind = FuseCmp;
5713     break;
5714   case X86::JS_1:
5715   case X86::JNS_1:
5716   case X86::JP_1:
5717   case X86::JNP_1:
5718   case X86::JO_1:
5719   case X86::JNO_1:
5720     FuseKind = FuseTest;
5721     break;
5722   }
5723   switch (First->getOpcode()) {
5724   default:
5725     return false;
5726   case X86::TEST8rr:
5727   case X86::TEST16rr:
5728   case X86::TEST32rr:
5729   case X86::TEST64rr:
5730   case X86::TEST8ri:
5731   case X86::TEST16ri:
5732   case X86::TEST32ri:
5733   case X86::TEST32i32:
5734   case X86::TEST64i32:
5735   case X86::TEST64ri32:
5736   case X86::TEST8rm:
5737   case X86::TEST16rm:
5738   case X86::TEST32rm:
5739   case X86::TEST64rm:
5740   case X86::TEST8ri_NOREX:
5741   case X86::AND16i16:
5742   case X86::AND16ri:
5743   case X86::AND16ri8:
5744   case X86::AND16rm:
5745   case X86::AND16rr:
5746   case X86::AND32i32:
5747   case X86::AND32ri:
5748   case X86::AND32ri8:
5749   case X86::AND32rm:
5750   case X86::AND32rr:
5751   case X86::AND64i32:
5752   case X86::AND64ri32:
5753   case X86::AND64ri8:
5754   case X86::AND64rm:
5755   case X86::AND64rr:
5756   case X86::AND8i8:
5757   case X86::AND8ri:
5758   case X86::AND8rm:
5759   case X86::AND8rr:
5760     return true;
5761   case X86::CMP16i16:
5762   case X86::CMP16ri:
5763   case X86::CMP16ri8:
5764   case X86::CMP16rm:
5765   case X86::CMP16rr:
5766   case X86::CMP32i32:
5767   case X86::CMP32ri:
5768   case X86::CMP32ri8:
5769   case X86::CMP32rm:
5770   case X86::CMP32rr:
5771   case X86::CMP64i32:
5772   case X86::CMP64ri32:
5773   case X86::CMP64ri8:
5774   case X86::CMP64rm:
5775   case X86::CMP64rr:
5776   case X86::CMP8i8:
5777   case X86::CMP8ri:
5778   case X86::CMP8rm:
5779   case X86::CMP8rr:
5780   case X86::ADD16i16:
5781   case X86::ADD16ri:
5782   case X86::ADD16ri8:
5783   case X86::ADD16ri8_DB:
5784   case X86::ADD16ri_DB:
5785   case X86::ADD16rm:
5786   case X86::ADD16rr:
5787   case X86::ADD16rr_DB:
5788   case X86::ADD32i32:
5789   case X86::ADD32ri:
5790   case X86::ADD32ri8:
5791   case X86::ADD32ri8_DB:
5792   case X86::ADD32ri_DB:
5793   case X86::ADD32rm:
5794   case X86::ADD32rr:
5795   case X86::ADD32rr_DB:
5796   case X86::ADD64i32:
5797   case X86::ADD64ri32:
5798   case X86::ADD64ri32_DB:
5799   case X86::ADD64ri8:
5800   case X86::ADD64ri8_DB:
5801   case X86::ADD64rm:
5802   case X86::ADD64rr:
5803   case X86::ADD64rr_DB:
5804   case X86::ADD8i8:
5805   case X86::ADD8mi:
5806   case X86::ADD8mr:
5807   case X86::ADD8ri:
5808   case X86::ADD8rm:
5809   case X86::ADD8rr:
5810   case X86::SUB16i16:
5811   case X86::SUB16ri:
5812   case X86::SUB16ri8:
5813   case X86::SUB16rm:
5814   case X86::SUB16rr:
5815   case X86::SUB32i32:
5816   case X86::SUB32ri:
5817   case X86::SUB32ri8:
5818   case X86::SUB32rm:
5819   case X86::SUB32rr:
5820   case X86::SUB64i32:
5821   case X86::SUB64ri32:
5822   case X86::SUB64ri8:
5823   case X86::SUB64rm:
5824   case X86::SUB64rr:
5825   case X86::SUB8i8:
5826   case X86::SUB8ri:
5827   case X86::SUB8rm:
5828   case X86::SUB8rr:
5829     return FuseKind == FuseCmp || FuseKind == FuseInc;
5830   case X86::INC16r:
5831   case X86::INC32r:
5832   case X86::INC64r:
5833   case X86::INC8r:
5834   case X86::DEC16r:
5835   case X86::DEC32r:
5836   case X86::DEC64r:
5837   case X86::DEC8r:
5838     return FuseKind == FuseInc;
5839   }
5840 }
5841 
5842 bool X86InstrInfo::
5843 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
5844   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
5845   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
5846   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
5847     return true;
5848   Cond[0].setImm(GetOppositeBranchCondition(CC));
5849   return false;
5850 }
5851 
5852 bool X86InstrInfo::
5853 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
5854   // FIXME: Return false for x87 stack register classes for now. We can't
5855   // allow any loads of these registers before FpGet_ST0_80.
5856   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
5857            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
5858 }
5859 
5860 /// Return a virtual register initialized with the
5861 /// the global base register value. Output instructions required to
5862 /// initialize the register in the function entry block, if necessary.
5863 ///
5864 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
5865 ///
5866 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
5867   assert(!Subtarget.is64Bit() &&
5868          "X86-64 PIC uses RIP relative addressing");
5869 
5870   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
5871   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
5872   if (GlobalBaseReg != 0)
5873     return GlobalBaseReg;
5874 
5875   // Create the register. The code to initialize it is inserted
5876   // later, by the CGBR pass (below).
5877   MachineRegisterInfo &RegInfo = MF->getRegInfo();
5878   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
5879   X86FI->setGlobalBaseReg(GlobalBaseReg);
5880   return GlobalBaseReg;
5881 }
5882 
5883 // These are the replaceable SSE instructions. Some of these have Int variants
5884 // that we don't include here. We don't want to replace instructions selected
5885 // by intrinsics.
5886 static const uint16_t ReplaceableInstrs[][3] = {
5887   //PackedSingle     PackedDouble    PackedInt
5888   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
5889   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
5890   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
5891   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
5892   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
5893   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
5894   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
5895   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
5896   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
5897   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
5898   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
5899   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
5900   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
5901   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
5902   // AVX 128-bit support
5903   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
5904   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
5905   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
5906   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
5907   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
5908   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
5909   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
5910   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
5911   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
5912   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
5913   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
5914   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
5915   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
5916   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
5917   // AVX 256-bit support
5918   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
5919   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
5920   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
5921   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
5922   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
5923   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
5924 };
5925 
5926 static const uint16_t ReplaceableInstrsAVX2[][3] = {
5927   //PackedSingle       PackedDouble       PackedInt
5928   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
5929   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
5930   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
5931   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
5932   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
5933   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
5934   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
5935   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
5936   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
5937   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
5938   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
5939   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
5940   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
5941   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
5942   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
5943   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
5944   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
5945   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
5946   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
5947   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
5948 };
5949 
5950 // FIXME: Some shuffle and unpack instructions have equivalents in different
5951 // domains, but they require a bit more work than just switching opcodes.
5952 
5953 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
5954   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
5955     if (ReplaceableInstrs[i][domain-1] == opcode)
5956       return ReplaceableInstrs[i];
5957   return nullptr;
5958 }
5959 
5960 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
5961   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
5962     if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
5963       return ReplaceableInstrsAVX2[i];
5964   return nullptr;
5965 }
5966 
5967 std::pair<uint16_t, uint16_t>
5968 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
5969   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5970   bool hasAVX2 = Subtarget.hasAVX2();
5971   uint16_t validDomains = 0;
5972   if (domain && lookup(MI->getOpcode(), domain))
5973     validDomains = 0xe;
5974   else if (domain && lookupAVX2(MI->getOpcode(), domain))
5975     validDomains = hasAVX2 ? 0xe : 0x6;
5976   return std::make_pair(domain, validDomains);
5977 }
5978 
5979 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
5980   assert(Domain>0 && Domain<4 && "Invalid execution domain");
5981   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
5982   assert(dom && "Not an SSE instruction");
5983   const uint16_t *table = lookup(MI->getOpcode(), dom);
5984   if (!table) { // try the other table
5985     assert((Subtarget.hasAVX2() || Domain < 3) &&
5986            "256-bit vector operations only available in AVX2");
5987     table = lookupAVX2(MI->getOpcode(), dom);
5988   }
5989   assert(table && "Cannot change domain");
5990   MI->setDesc(get(table[Domain-1]));
5991 }
5992 
5993 /// Return the noop instruction to use for a noop.
5994 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
5995   NopInst.setOpcode(X86::NOOP);
5996 }
5997 
5998 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
5999 // In particular, getJumpInstrTableEntryBound must always return an upper bound
6000 // on the encoding lengths of the instructions generated by
6001 // getUnconditionalBranch and getTrap.
6002 void X86InstrInfo::getUnconditionalBranch(
6003     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
6004   Branch.setOpcode(X86::JMP_1);
6005   Branch.addOperand(MCOperand::CreateExpr(BranchTarget));
6006 }
6007 
6008 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
6009 // In particular, getJumpInstrTableEntryBound must always return an upper bound
6010 // on the encoding lengths of the instructions generated by
6011 // getUnconditionalBranch and getTrap.
6012 void X86InstrInfo::getTrap(MCInst &MI) const {
6013   MI.setOpcode(X86::TRAP);
6014 }
6015 
6016 // See getTrap and getUnconditionalBranch for conditions on the value returned
6017 // by this function.
6018 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
6019   // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
6020   // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
6021   return 5;
6022 }
6023 
6024 bool X86InstrInfo::isHighLatencyDef(int opc) const {
6025   switch (opc) {
6026   default: return false;
6027   case X86::DIVSDrm:
6028   case X86::DIVSDrm_Int:
6029   case X86::DIVSDrr:
6030   case X86::DIVSDrr_Int:
6031   case X86::DIVSSrm:
6032   case X86::DIVSSrm_Int:
6033   case X86::DIVSSrr:
6034   case X86::DIVSSrr_Int:
6035   case X86::SQRTPDm:
6036   case X86::SQRTPDr:
6037   case X86::SQRTPSm:
6038   case X86::SQRTPSr:
6039   case X86::SQRTSDm:
6040   case X86::SQRTSDm_Int:
6041   case X86::SQRTSDr:
6042   case X86::SQRTSDr_Int:
6043   case X86::SQRTSSm:
6044   case X86::SQRTSSm_Int:
6045   case X86::SQRTSSr:
6046   case X86::SQRTSSr_Int:
6047   // AVX instructions with high latency
6048   case X86::VDIVSDrm:
6049   case X86::VDIVSDrm_Int:
6050   case X86::VDIVSDrr:
6051   case X86::VDIVSDrr_Int:
6052   case X86::VDIVSSrm:
6053   case X86::VDIVSSrm_Int:
6054   case X86::VDIVSSrr:
6055   case X86::VDIVSSrr_Int:
6056   case X86::VSQRTPDm:
6057   case X86::VSQRTPDr:
6058   case X86::VSQRTPSm:
6059   case X86::VSQRTPSr:
6060   case X86::VSQRTSDm:
6061   case X86::VSQRTSDm_Int:
6062   case X86::VSQRTSDr:
6063   case X86::VSQRTSSm:
6064   case X86::VSQRTSSm_Int:
6065   case X86::VSQRTSSr:
6066   case X86::VSQRTPDZm:
6067   case X86::VSQRTPDZr:
6068   case X86::VSQRTPSZm:
6069   case X86::VSQRTPSZr:
6070   case X86::VSQRTSDZm:
6071   case X86::VSQRTSDZm_Int:
6072   case X86::VSQRTSDZr:
6073   case X86::VSQRTSSZm_Int:
6074   case X86::VSQRTSSZr:
6075   case X86::VSQRTSSZm:
6076   case X86::VDIVSDZrm:
6077   case X86::VDIVSDZrr:
6078   case X86::VDIVSSZrm:
6079   case X86::VDIVSSZrr:
6080 
6081   case X86::VGATHERQPSZrm:
6082   case X86::VGATHERQPDZrm:
6083   case X86::VGATHERDPDZrm:
6084   case X86::VGATHERDPSZrm:
6085   case X86::VPGATHERQDZrm:
6086   case X86::VPGATHERQQZrm:
6087   case X86::VPGATHERDDZrm:
6088   case X86::VPGATHERDQZrm:
6089   case X86::VSCATTERQPDZmr:
6090   case X86::VSCATTERQPSZmr:
6091   case X86::VSCATTERDPDZmr:
6092   case X86::VSCATTERDPSZmr:
6093   case X86::VPSCATTERQDZmr:
6094   case X86::VPSCATTERQQZmr:
6095   case X86::VPSCATTERDDZmr:
6096   case X86::VPSCATTERDQZmr:
6097     return true;
6098   }
6099 }
6100 
6101 bool X86InstrInfo::
6102 hasHighOperandLatency(const InstrItineraryData *ItinData,
6103                       const MachineRegisterInfo *MRI,
6104                       const MachineInstr *DefMI, unsigned DefIdx,
6105                       const MachineInstr *UseMI, unsigned UseIdx) const {
6106   return isHighLatencyDef(DefMI->getOpcode());
6107 }
6108 
6109 namespace {
6110   /// Create Global Base Reg pass. This initializes the PIC
6111   /// global base register for x86-32.
6112   struct CGBR : public MachineFunctionPass {
6113     static char ID;
6114     CGBR() : MachineFunctionPass(ID) {}
6115 
6116     bool runOnMachineFunction(MachineFunction &MF) override {
6117       const X86TargetMachine *TM =
6118         static_cast<const X86TargetMachine *>(&MF.getTarget());
6119       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
6120 
6121       // Don't do anything if this is 64-bit as 64-bit PIC
6122       // uses RIP relative addressing.
6123       if (STI.is64Bit())
6124         return false;
6125 
6126       // Only emit a global base reg in PIC mode.
6127       if (TM->getRelocationModel() != Reloc::PIC_)
6128         return false;
6129 
6130       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
6131       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6132 
6133       // If we didn't need a GlobalBaseReg, don't insert code.
6134       if (GlobalBaseReg == 0)
6135         return false;
6136 
6137       // Insert the set of GlobalBaseReg into the first MBB of the function
6138       MachineBasicBlock &FirstMBB = MF.front();
6139       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
6140       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
6141       MachineRegisterInfo &RegInfo = MF.getRegInfo();
6142       const X86InstrInfo *TII = STI.getInstrInfo();
6143 
6144       unsigned PC;
6145       if (STI.isPICStyleGOT())
6146         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
6147       else
6148         PC = GlobalBaseReg;
6149 
6150       // Operand of MovePCtoStack is completely ignored by asm printer. It's
6151       // only used in JIT code emission as displacement to pc.
6152       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
6153 
6154       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
6155       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
6156       if (STI.isPICStyleGOT()) {
6157         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
6158         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
6159           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
6160                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
6161       }
6162 
6163       return true;
6164     }
6165 
6166     const char *getPassName() const override {
6167       return "X86 PIC Global Base Reg Initialization";
6168     }
6169 
6170     void getAnalysisUsage(AnalysisUsage &AU) const override {
6171       AU.setPreservesCFG();
6172       MachineFunctionPass::getAnalysisUsage(AU);
6173     }
6174   };
6175 }
6176 
6177 char CGBR::ID = 0;
6178 FunctionPass*
6179 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
6180 
6181 namespace {
6182   struct LDTLSCleanup : public MachineFunctionPass {
6183     static char ID;
6184     LDTLSCleanup() : MachineFunctionPass(ID) {}
6185 
6186     bool runOnMachineFunction(MachineFunction &MF) override {
6187       X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
6188       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
6189         // No point folding accesses if there isn't at least two.
6190         return false;
6191       }
6192 
6193       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
6194       return VisitNode(DT->getRootNode(), 0);
6195     }
6196 
6197     // Visit the dominator subtree rooted at Node in pre-order.
6198     // If TLSBaseAddrReg is non-null, then use that to replace any
6199     // TLS_base_addr instructions. Otherwise, create the register
6200     // when the first such instruction is seen, and then use it
6201     // as we encounter more instructions.
6202     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
6203       MachineBasicBlock *BB = Node->getBlock();
6204       bool Changed = false;
6205 
6206       // Traverse the current block.
6207       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
6208            ++I) {
6209         switch (I->getOpcode()) {
6210           case X86::TLS_base_addr32:
6211           case X86::TLS_base_addr64:
6212             if (TLSBaseAddrReg)
6213               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
6214             else
6215               I = SetRegister(I, &TLSBaseAddrReg);
6216             Changed = true;
6217             break;
6218           default:
6219             break;
6220         }
6221       }
6222 
6223       // Visit the children of this block in the dominator tree.
6224       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
6225            I != E; ++I) {
6226         Changed |= VisitNode(*I, TLSBaseAddrReg);
6227       }
6228 
6229       return Changed;
6230     }
6231 
6232     // Replace the TLS_base_addr instruction I with a copy from
6233     // TLSBaseAddrReg, returning the new instruction.
6234     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
6235                                          unsigned TLSBaseAddrReg) {
6236       MachineFunction *MF = I->getParent()->getParent();
6237       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6238       const bool is64Bit = STI.is64Bit();
6239       const X86InstrInfo *TII = STI.getInstrInfo();
6240 
6241       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
6242       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
6243                                    TII->get(TargetOpcode::COPY),
6244                                    is64Bit ? X86::RAX : X86::EAX)
6245                                    .addReg(TLSBaseAddrReg);
6246 
6247       // Erase the TLS_base_addr instruction.
6248       I->eraseFromParent();
6249 
6250       return Copy;
6251     }
6252 
6253     // Create a virtal register in *TLSBaseAddrReg, and populate it by
6254     // inserting a copy instruction after I. Returns the new instruction.
6255     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
6256       MachineFunction *MF = I->getParent()->getParent();
6257       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6258       const bool is64Bit = STI.is64Bit();
6259       const X86InstrInfo *TII = STI.getInstrInfo();
6260 
6261       // Create a virtual register for the TLS base address.
6262       MachineRegisterInfo &RegInfo = MF->getRegInfo();
6263       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
6264                                                       ? &X86::GR64RegClass
6265                                                       : &X86::GR32RegClass);
6266 
6267       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
6268       MachineInstr *Next = I->getNextNode();
6269       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
6270                                    TII->get(TargetOpcode::COPY),
6271                                    *TLSBaseAddrReg)
6272                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
6273 
6274       return Copy;
6275     }
6276 
6277     const char *getPassName() const override {
6278       return "Local Dynamic TLS Access Clean-up";
6279     }
6280 
6281     void getAnalysisUsage(AnalysisUsage &AU) const override {
6282       AU.setPreservesCFG();
6283       AU.addRequired<MachineDominatorTree>();
6284       MachineFunctionPass::getAnalysisUsage(AU);
6285     }
6286   };
6287 }
6288 
6289 char LDTLSCleanup::ID = 0;
6290 FunctionPass*
6291 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
6292